Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
1 23:17:40.101454 lava-dispatcher, installed at version: 2024.01
2 23:17:40.101751 start: 0 validate
3 23:17:40.101916 Start time: 2024-04-03 23:17:40.101908+00:00 (UTC)
4 23:17:40.102086 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:17:40.102270 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:17:40.362561 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:17:40.362733 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:18:17.867966 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:18:17.868480 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:18:18.121451 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:18:18.122047 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:18:20.870362 validate duration: 40.77
14 23:18:20.870622 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:18:20.870719 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:18:20.870806 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:18:20.870929 Not decompressing ramdisk as can be used compressed.
18 23:18:20.871015 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 23:18:20.871077 saving as /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/ramdisk/rootfs.cpio.gz
20 23:18:20.871140 total size: 47897469 (45 MB)
21 23:18:21.120261 progress 0 % (0 MB)
22 23:18:21.133047 progress 5 % (2 MB)
23 23:18:21.146090 progress 10 % (4 MB)
24 23:18:21.158787 progress 15 % (6 MB)
25 23:18:21.171409 progress 20 % (9 MB)
26 23:18:21.184279 progress 25 % (11 MB)
27 23:18:21.197195 progress 30 % (13 MB)
28 23:18:21.210516 progress 35 % (16 MB)
29 23:18:21.223307 progress 40 % (18 MB)
30 23:18:21.236076 progress 45 % (20 MB)
31 23:18:21.248596 progress 50 % (22 MB)
32 23:18:21.261054 progress 55 % (25 MB)
33 23:18:21.273828 progress 60 % (27 MB)
34 23:18:21.286467 progress 65 % (29 MB)
35 23:18:21.299115 progress 70 % (32 MB)
36 23:18:21.311729 progress 75 % (34 MB)
37 23:18:21.324360 progress 80 % (36 MB)
38 23:18:21.336938 progress 85 % (38 MB)
39 23:18:21.349330 progress 90 % (41 MB)
40 23:18:21.361666 progress 95 % (43 MB)
41 23:18:21.374111 progress 100 % (45 MB)
42 23:18:21.374450 45 MB downloaded in 0.50 s (90.76 MB/s)
43 23:18:21.374645 end: 1.1.1 http-download (duration 00:00:01) [common]
45 23:18:21.374938 end: 1.1 download-retry (duration 00:00:01) [common]
46 23:18:21.375039 start: 1.2 download-retry (timeout 00:09:59) [common]
47 23:18:21.375182 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 23:18:21.375345 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:18:21.375427 saving as /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/kernel/Image
50 23:18:21.375503 total size: 54286848 (51 MB)
51 23:18:21.375578 No compression specified
52 23:18:21.376821 progress 0 % (0 MB)
53 23:18:21.394355 progress 5 % (2 MB)
54 23:18:21.410866 progress 10 % (5 MB)
55 23:18:21.426909 progress 15 % (7 MB)
56 23:18:21.442972 progress 20 % (10 MB)
57 23:18:21.458780 progress 25 % (12 MB)
58 23:18:21.474523 progress 30 % (15 MB)
59 23:18:21.489843 progress 35 % (18 MB)
60 23:18:21.504889 progress 40 % (20 MB)
61 23:18:21.519903 progress 45 % (23 MB)
62 23:18:21.535097 progress 50 % (25 MB)
63 23:18:21.550063 progress 55 % (28 MB)
64 23:18:21.564917 progress 60 % (31 MB)
65 23:18:21.579623 progress 65 % (33 MB)
66 23:18:21.594596 progress 70 % (36 MB)
67 23:18:21.609733 progress 75 % (38 MB)
68 23:18:21.624718 progress 80 % (41 MB)
69 23:18:21.639528 progress 85 % (44 MB)
70 23:18:21.654251 progress 90 % (46 MB)
71 23:18:21.668535 progress 95 % (49 MB)
72 23:18:21.682905 progress 100 % (51 MB)
73 23:18:21.683169 51 MB downloaded in 0.31 s (168.27 MB/s)
74 23:18:21.683325 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:18:21.683556 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:18:21.683646 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:18:21.683733 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:18:21.683880 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:18:21.683949 saving as /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/dtb/mt8192-asurada-spherion-r0.dtb
81 23:18:21.684012 total size: 47230 (0 MB)
82 23:18:21.684075 No compression specified
83 23:18:21.685123 progress 69 % (0 MB)
84 23:18:21.685408 progress 100 % (0 MB)
85 23:18:21.685579 0 MB downloaded in 0.00 s (28.79 MB/s)
86 23:18:21.685706 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:18:21.685927 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:18:21.686013 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:18:21.686097 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:18:21.686212 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:18:21.686279 saving as /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/modules/modules.tar
93 23:18:21.686339 total size: 8629908 (8 MB)
94 23:18:21.686400 Using unxz to decompress xz
95 23:18:21.690912 progress 0 % (0 MB)
96 23:18:21.712030 progress 5 % (0 MB)
97 23:18:21.740306 progress 10 % (0 MB)
98 23:18:21.767954 progress 15 % (1 MB)
99 23:18:21.794146 progress 20 % (1 MB)
100 23:18:21.822354 progress 25 % (2 MB)
101 23:18:21.852098 progress 30 % (2 MB)
102 23:18:21.880056 progress 35 % (2 MB)
103 23:18:21.909298 progress 40 % (3 MB)
104 23:18:21.936619 progress 45 % (3 MB)
105 23:18:21.964885 progress 50 % (4 MB)
106 23:18:21.993360 progress 55 % (4 MB)
107 23:18:22.025941 progress 60 % (4 MB)
108 23:18:22.054615 progress 65 % (5 MB)
109 23:18:22.083132 progress 70 % (5 MB)
110 23:18:22.111374 progress 75 % (6 MB)
111 23:18:22.140419 progress 80 % (6 MB)
112 23:18:22.170030 progress 85 % (7 MB)
113 23:18:22.202302 progress 90 % (7 MB)
114 23:18:22.236291 progress 95 % (7 MB)
115 23:18:22.266461 progress 100 % (8 MB)
116 23:18:22.272616 8 MB downloaded in 0.59 s (14.04 MB/s)
117 23:18:22.272982 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:18:22.273387 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:18:22.273534 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:18:22.273679 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:18:22.273802 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:18:22.273937 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:18:22.274249 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2
125 23:18:22.274453 makedir: /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin
126 23:18:22.274604 makedir: /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/tests
127 23:18:22.274756 makedir: /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/results
128 23:18:22.274920 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-add-keys
129 23:18:22.275128 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-add-sources
130 23:18:22.275325 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-background-process-start
131 23:18:22.275516 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-background-process-stop
132 23:18:22.275706 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-common-functions
133 23:18:22.275890 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-echo-ipv4
134 23:18:22.276084 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-install-packages
135 23:18:22.276270 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-installed-packages
136 23:18:22.276453 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-os-build
137 23:18:22.276643 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-probe-channel
138 23:18:22.276831 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-probe-ip
139 23:18:22.277020 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-target-ip
140 23:18:22.277208 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-target-mac
141 23:18:22.277393 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-target-storage
142 23:18:22.277605 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-test-case
143 23:18:22.277795 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-test-event
144 23:18:22.277984 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-test-feedback
145 23:18:22.278170 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-test-raise
146 23:18:22.278359 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-test-reference
147 23:18:22.278552 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-test-runner
148 23:18:22.278740 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-test-set
149 23:18:22.278927 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-test-shell
150 23:18:22.279120 Updating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-install-packages (oe)
151 23:18:22.279343 Updating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/bin/lava-installed-packages (oe)
152 23:18:22.279528 Creating /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/environment
153 23:18:22.279681 LAVA metadata
154 23:18:22.279804 - LAVA_JOB_ID=13248404
155 23:18:22.279908 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:18:22.280068 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:18:22.280174 skipped lava-vland-overlay
158 23:18:22.280293 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:18:22.280417 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:18:22.280516 skipped lava-multinode-overlay
161 23:18:22.280653 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:18:22.280794 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:18:22.280917 Loading test definitions
164 23:18:22.281059 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:18:22.281181 Using /lava-13248404 at stage 0
166 23:18:22.281653 uuid=13248404_1.5.2.3.1 testdef=None
167 23:18:22.281786 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:18:22.281914 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:18:22.282716 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:18:22.283068 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:18:22.284004 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:18:22.284370 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:18:22.285275 runner path: /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/0/tests/0_igt-gpu-panfrost test_uuid 13248404_1.5.2.3.1
176 23:18:22.285503 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:18:22.285843 Creating lava-test-runner.conf files
179 23:18:22.285942 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248404/lava-overlay-cqla7ar2/lava-13248404/0 for stage 0
180 23:18:22.286074 - 0_igt-gpu-panfrost
181 23:18:22.286219 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:18:22.286345 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:18:22.294387 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:18:22.294542 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:18:22.294648 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:18:22.294738 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:18:22.294844 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:18:24.247676 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 23:18:24.248144 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 23:18:24.248305 extracting modules file /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248404/extract-overlay-ramdisk-4mb7_mqd/ramdisk
191 23:18:24.505591 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:18:24.505776 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
193 23:18:24.505877 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248404/compress-overlay-t6kzu9g1/overlay-1.5.2.4.tar.gz to ramdisk
194 23:18:24.505950 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248404/compress-overlay-t6kzu9g1/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248404/extract-overlay-ramdisk-4mb7_mqd/ramdisk
195 23:18:24.513369 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:18:24.513537 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
197 23:18:24.513634 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:18:24.513733 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
199 23:18:24.513851 Building ramdisk /var/lib/lava/dispatcher/tmp/13248404/extract-overlay-ramdisk-4mb7_mqd/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248404/extract-overlay-ramdisk-4mb7_mqd/ramdisk
200 23:18:25.852065 >> 466176 blocks
201 23:18:32.462076 rename /var/lib/lava/dispatcher/tmp/13248404/extract-overlay-ramdisk-4mb7_mqd/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/ramdisk/ramdisk.cpio.gz
202 23:18:32.462536 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 23:18:32.462660 start: 1.5.8 prepare-kernel (timeout 00:09:48) [common]
204 23:18:32.462783 start: 1.5.8.1 prepare-fit (timeout 00:09:48) [common]
205 23:18:32.462906 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/kernel/Image'
206 23:18:47.367705 Returned 0 in 14 seconds
207 23:18:47.468351 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/kernel/image.itb
208 23:18:48.408522 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:18:48.408931 output: Created: Thu Apr 4 00:18:48 2024
210 23:18:48.409013 output: Image 0 (kernel-1)
211 23:18:48.409082 output: Description:
212 23:18:48.409146 output: Created: Thu Apr 4 00:18:48 2024
213 23:18:48.409209 output: Type: Kernel Image
214 23:18:48.409269 output: Compression: lzma compressed
215 23:18:48.409327 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
216 23:18:48.409385 output: Architecture: AArch64
217 23:18:48.409444 output: OS: Linux
218 23:18:48.409512 output: Load Address: 0x00000000
219 23:18:48.409569 output: Entry Point: 0x00000000
220 23:18:48.409627 output: Hash algo: crc32
221 23:18:48.409687 output: Hash value: d7c9dcc1
222 23:18:48.409747 output: Image 1 (fdt-1)
223 23:18:48.409806 output: Description: mt8192-asurada-spherion-r0
224 23:18:48.409863 output: Created: Thu Apr 4 00:18:48 2024
225 23:18:48.409919 output: Type: Flat Device Tree
226 23:18:48.409973 output: Compression: uncompressed
227 23:18:48.410028 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 23:18:48.410083 output: Architecture: AArch64
229 23:18:48.410138 output: Hash algo: crc32
230 23:18:48.410192 output: Hash value: 4bf0d1ac
231 23:18:48.410247 output: Image 2 (ramdisk-1)
232 23:18:48.410301 output: Description: unavailable
233 23:18:48.410355 output: Created: Thu Apr 4 00:18:48 2024
234 23:18:48.410409 output: Type: RAMDisk Image
235 23:18:48.410464 output: Compression: Unknown Compression
236 23:18:48.410518 output: Data Size: 61040160 Bytes = 59609.53 KiB = 58.21 MiB
237 23:18:48.410573 output: Architecture: AArch64
238 23:18:48.410627 output: OS: Linux
239 23:18:48.410681 output: Load Address: unavailable
240 23:18:48.410735 output: Entry Point: unavailable
241 23:18:48.410788 output: Hash algo: crc32
242 23:18:48.410842 output: Hash value: 6c9c6f09
243 23:18:48.410896 output: Default Configuration: 'conf-1'
244 23:18:48.410949 output: Configuration 0 (conf-1)
245 23:18:48.411004 output: Description: mt8192-asurada-spherion-r0
246 23:18:48.411058 output: Kernel: kernel-1
247 23:18:48.411111 output: Init Ramdisk: ramdisk-1
248 23:18:48.411165 output: FDT: fdt-1
249 23:18:48.411219 output: Loadables: kernel-1
250 23:18:48.411273 output:
251 23:18:48.411483 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 23:18:48.411586 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 23:18:48.411693 end: 1.5 prepare-tftp-overlay (duration 00:00:26) [common]
254 23:18:48.411786 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:32) [common]
255 23:18:48.411875 No LXC device requested
256 23:18:48.411958 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:18:48.412044 start: 1.7 deploy-device-env (timeout 00:09:32) [common]
258 23:18:48.412128 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:18:48.412201 Checking files for TFTP limit of 4294967296 bytes.
260 23:18:48.412730 end: 1 tftp-deploy (duration 00:00:28) [common]
261 23:18:48.412858 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:18:48.412954 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:18:48.413085 substitutions:
264 23:18:48.413155 - {DTB}: 13248404/tftp-deploy-19eirvby/dtb/mt8192-asurada-spherion-r0.dtb
265 23:18:48.413223 - {INITRD}: 13248404/tftp-deploy-19eirvby/ramdisk/ramdisk.cpio.gz
266 23:18:48.413284 - {KERNEL}: 13248404/tftp-deploy-19eirvby/kernel/Image
267 23:18:48.413343 - {LAVA_MAC}: None
268 23:18:48.413400 - {PRESEED_CONFIG}: None
269 23:18:48.413457 - {PRESEED_LOCAL}: None
270 23:18:48.413519 - {RAMDISK}: 13248404/tftp-deploy-19eirvby/ramdisk/ramdisk.cpio.gz
271 23:18:48.413575 - {ROOT_PART}: None
272 23:18:48.413631 - {ROOT}: None
273 23:18:48.413687 - {SERVER_IP}: 192.168.201.1
274 23:18:48.413741 - {TEE}: None
275 23:18:48.413796 Parsed boot commands:
276 23:18:48.413854 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:18:48.414047 Parsed boot commands: tftpboot 192.168.201.1 13248404/tftp-deploy-19eirvby/kernel/image.itb 13248404/tftp-deploy-19eirvby/kernel/cmdline
278 23:18:48.414138 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:18:48.414227 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:18:48.414325 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:18:48.414415 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:18:48.414490 Not connected, no need to disconnect.
283 23:18:48.414565 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:18:48.414645 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:18:48.414716 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 23:18:48.419209 Setting prompt string to ['lava-test: # ']
287 23:18:48.419643 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:18:48.419760 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:18:48.419865 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:18:48.419964 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:18:48.420186 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 23:18:53.556960 >> Command sent successfully.
293 23:18:53.559528 Returned 0 in 5 seconds
294 23:18:53.659932 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:18:53.660379 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:18:53.660508 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:18:53.660614 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:18:53.660683 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:18:53.660753 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:18:53.661027 [Enter `^Ec?' for help]
302 23:18:53.834457
303 23:18:53.834625
304 23:18:53.834726 F0: 102B 0000
305 23:18:53.834821
306 23:18:53.834961 F3: 1001 0000 [0200]
307 23:18:53.835064
308 23:18:53.837948 F3: 1001 0000
309 23:18:53.838044
310 23:18:53.838115 F7: 102D 0000
311 23:18:53.838176
312 23:18:53.838235 F1: 0000 0000
313 23:18:53.838296
314 23:18:53.841830 V0: 0000 0000 [0001]
315 23:18:53.841936
316 23:18:53.842000 00: 0007 8000
317 23:18:53.842064
318 23:18:53.845320 01: 0000 0000
319 23:18:53.845450
320 23:18:53.845592 BP: 0C00 0209 [0000]
321 23:18:53.845658
322 23:18:53.845720 G0: 1182 0000
323 23:18:53.848915
324 23:18:53.849028 EC: 0000 0021 [4000]
325 23:18:53.849122
326 23:18:53.852930 S7: 0000 0000 [0000]
327 23:18:53.853106
328 23:18:53.853207 CC: 0000 0000 [0001]
329 23:18:53.853298
330 23:18:53.853412 T0: 0000 0040 [010F]
331 23:18:53.856196
332 23:18:53.856373 Jump to BL
333 23:18:53.856456
334 23:18:53.880771
335 23:18:53.880921
336 23:18:53.880996
337 23:18:53.887791 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:18:53.891082 ARM64: Exception handlers installed.
339 23:18:53.894860 ARM64: Testing exception
340 23:18:53.898445 ARM64: Done test exception
341 23:18:53.905834 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:18:53.916537 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:18:53.923146 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:18:53.933156 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:18:53.939967 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:18:53.946893 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:18:53.957613 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:18:53.964165 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:18:53.983720 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:18:53.986934 WDT: Last reset was cold boot
351 23:18:53.990077 SPI1(PAD0) initialized at 2873684 Hz
352 23:18:53.993694 SPI5(PAD0) initialized at 992727 Hz
353 23:18:53.996580 VBOOT: Loading verstage.
354 23:18:54.003374 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:18:54.006826 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:18:54.010314 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:18:54.013384 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:18:54.021209 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:18:54.027570 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:18:54.038487 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 23:18:54.038682
362 23:18:54.038796
363 23:18:54.048474 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:18:54.051944 ARM64: Exception handlers installed.
365 23:18:54.054968 ARM64: Testing exception
366 23:18:54.055127 ARM64: Done test exception
367 23:18:54.062319 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:18:54.065915 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:18:54.079383 Probing TPM: . done!
370 23:18:54.079563 TPM ready after 0 ms
371 23:18:54.086350 Connected to device vid:did:rid of 1ae0:0028:00
372 23:18:54.136469 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 23:18:54.136675 Initialized TPM device CR50 revision 0
374 23:18:54.148311 tlcl_send_startup: Startup return code is 0
375 23:18:54.148471 TPM: setup succeeded
376 23:18:54.159708 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:18:54.168565 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:18:54.180157 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:18:54.190571 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:18:54.193955 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:18:54.197390 in-header: 03 07 00 00 08 00 00 00
382 23:18:54.201359 in-data: aa e4 47 04 13 02 00 00
383 23:18:54.201522 Chrome EC: UHEPI supported
384 23:18:54.208353 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:18:54.212138 in-header: 03 9d 00 00 08 00 00 00
386 23:18:54.216063 in-data: 10 20 20 08 00 00 00 00
387 23:18:54.216217 Phase 1
388 23:18:54.219678 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:18:54.227443 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:18:54.234489 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:18:54.234659 Recovery requested (1009000e)
392 23:18:54.243197 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:18:54.248719 tlcl_extend: response is 0
394 23:18:54.256929 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:18:54.262106 tlcl_extend: response is 0
396 23:18:54.268759 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:18:54.289893 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 23:18:54.297169 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:18:54.297316
400 23:18:54.297384
401 23:18:54.304801 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:18:54.308175 ARM64: Exception handlers installed.
403 23:18:54.312038 ARM64: Testing exception
404 23:18:54.315562 ARM64: Done test exception
405 23:18:54.334825 pmic_efuse_setting: Set efuses in 11 msecs
406 23:18:54.338037 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:18:54.344680 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:18:54.348055 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:18:54.354631 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:18:54.358165 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:18:54.364748 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:18:54.368326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:18:54.371529 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:18:54.378271 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:18:54.381360 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:18:54.388179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:18:54.391269 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:18:54.394707 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:18:54.401459 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:18:54.408044 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:18:54.411246 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:18:54.417864 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:18:54.424521 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:18:54.431373 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:18:54.434843 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:18:54.442470 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:18:54.446058 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:18:54.453239 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:18:54.456456 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:18:54.463599 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:18:54.467182 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:18:54.473986 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:18:54.477772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:18:54.484587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:18:54.488039 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:18:54.494576 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:18:54.498056 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:18:54.505216 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:18:54.508668 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:18:54.512675 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:18:54.520296 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:18:54.523734 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:18:54.530667 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:18:54.533991 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:18:54.537130 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:18:54.543790 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:18:54.547348 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:18:54.550788 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:18:54.557075 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:18:54.560576 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:18:54.563947 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:18:54.570427 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:18:54.573586 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:18:54.577060 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:18:54.580468 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:18:54.587051 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:18:54.590457 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:18:54.597059 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:18:54.606606 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:18:54.610178 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:18:54.620036 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:18:54.626539 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:18:54.633301 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:18:54.636822 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:18:54.639977 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:18:54.647537 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x15
467 23:18:54.654012 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:18:54.657250 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 23:18:54.663885 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:18:54.672045 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 23:18:54.675310 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 23:18:54.681822 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 23:18:54.685328 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 23:18:54.688445 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 23:18:54.692102 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 23:18:54.695214 ADC[4]: Raw value=897780 ID=7
477 23:18:54.698468 ADC[3]: Raw value=213440 ID=1
478 23:18:54.702089 RAM Code: 0x71
479 23:18:54.705519 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 23:18:54.708596 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 23:18:54.718896 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 23:18:54.725957 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 23:18:54.729201 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 23:18:54.732479 in-header: 03 07 00 00 08 00 00 00
485 23:18:54.735798 in-data: aa e4 47 04 13 02 00 00
486 23:18:54.739138 Chrome EC: UHEPI supported
487 23:18:54.742838 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 23:18:54.746684 in-header: 03 d5 00 00 08 00 00 00
489 23:18:54.750619 in-data: 98 20 60 08 00 00 00 00
490 23:18:54.754226 MRC: failed to locate region type 0.
491 23:18:54.761697 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 23:18:54.764980 DRAM-K: Running full calibration
493 23:18:54.771593 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 23:18:54.771750 header.status = 0x0
495 23:18:54.774910 header.version = 0x6 (expected: 0x6)
496 23:18:54.778691 header.size = 0xd00 (expected: 0xd00)
497 23:18:54.782484 header.flags = 0x0
498 23:18:54.785555 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 23:18:54.804795 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
500 23:18:54.812575 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 23:18:54.812733 dram_init: ddr_geometry: 2
502 23:18:54.816474 [EMI] MDL number = 2
503 23:18:54.816630 [EMI] Get MDL freq = 0
504 23:18:54.820086 dram_init: ddr_type: 0
505 23:18:54.823631 is_discrete_lpddr4: 1
506 23:18:54.823774 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 23:18:54.827383
508 23:18:54.827511
509 23:18:54.827580 [Bian_co] ETT version 0.0.0.1
510 23:18:54.834098 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 23:18:54.834246
512 23:18:54.837671 dramc_set_vcore_voltage set vcore to 650000
513 23:18:54.837789 Read voltage for 800, 4
514 23:18:54.841606 Vio18 = 0
515 23:18:54.841797 Vcore = 650000
516 23:18:54.841929 Vdram = 0
517 23:18:54.842045 Vddq = 0
518 23:18:54.844897 Vmddr = 0
519 23:18:54.845054 dram_init: config_dvfs: 1
520 23:18:54.852116 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 23:18:54.856049 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 23:18:54.859644 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 23:18:54.863103 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 23:18:54.867111 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 23:18:54.870880 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 23:18:54.874456 MEM_TYPE=3, freq_sel=18
527 23:18:54.878158 sv_algorithm_assistance_LP4_1600
528 23:18:54.881256 ============ PULL DRAM RESETB DOWN ============
529 23:18:54.884604 ========== PULL DRAM RESETB DOWN end =========
530 23:18:54.891572 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 23:18:54.894698 ===================================
532 23:18:54.894848 LPDDR4 DRAM CONFIGURATION
533 23:18:54.897991 ===================================
534 23:18:54.901258 EX_ROW_EN[0] = 0x0
535 23:18:54.904739 EX_ROW_EN[1] = 0x0
536 23:18:54.904889 LP4Y_EN = 0x0
537 23:18:54.907908 WORK_FSP = 0x0
538 23:18:54.908075 WL = 0x2
539 23:18:54.911224 RL = 0x2
540 23:18:54.911379 BL = 0x2
541 23:18:54.914855 RPST = 0x0
542 23:18:54.915008 RD_PRE = 0x0
543 23:18:54.918076 WR_PRE = 0x1
544 23:18:54.918216 WR_PST = 0x0
545 23:18:54.921444 DBI_WR = 0x0
546 23:18:54.921601 DBI_RD = 0x0
547 23:18:54.924565 OTF = 0x1
548 23:18:54.927973 ===================================
549 23:18:54.931202 ===================================
550 23:18:54.931364 ANA top config
551 23:18:54.934763 ===================================
552 23:18:54.938003 DLL_ASYNC_EN = 0
553 23:18:54.941507 ALL_SLAVE_EN = 1
554 23:18:54.941671 NEW_RANK_MODE = 1
555 23:18:54.944663 DLL_IDLE_MODE = 1
556 23:18:54.947958 LP45_APHY_COMB_EN = 1
557 23:18:54.951265 TX_ODT_DIS = 1
558 23:18:54.951422 NEW_8X_MODE = 1
559 23:18:54.954780 ===================================
560 23:18:54.957984 ===================================
561 23:18:54.961645 data_rate = 1600
562 23:18:54.964866 CKR = 1
563 23:18:54.968173 DQ_P2S_RATIO = 8
564 23:18:54.971456 ===================================
565 23:18:54.974604 CA_P2S_RATIO = 8
566 23:18:54.977946 DQ_CA_OPEN = 0
567 23:18:54.978098 DQ_SEMI_OPEN = 0
568 23:18:54.981417 CA_SEMI_OPEN = 0
569 23:18:54.984843 CA_FULL_RATE = 0
570 23:18:54.988098 DQ_CKDIV4_EN = 1
571 23:18:54.991445 CA_CKDIV4_EN = 1
572 23:18:54.994568 CA_PREDIV_EN = 0
573 23:18:54.994712 PH8_DLY = 0
574 23:18:54.998101 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 23:18:55.001385 DQ_AAMCK_DIV = 4
576 23:18:55.004799 CA_AAMCK_DIV = 4
577 23:18:55.008110 CA_ADMCK_DIV = 4
578 23:18:55.011590 DQ_TRACK_CA_EN = 0
579 23:18:55.011753 CA_PICK = 800
580 23:18:55.014877 CA_MCKIO = 800
581 23:18:55.018225 MCKIO_SEMI = 0
582 23:18:55.021487 PLL_FREQ = 3068
583 23:18:55.024748 DQ_UI_PI_RATIO = 32
584 23:18:55.027952 CA_UI_PI_RATIO = 0
585 23:18:55.031502 ===================================
586 23:18:55.034660 ===================================
587 23:18:55.034816 memory_type:LPDDR4
588 23:18:55.038192 GP_NUM : 10
589 23:18:55.041303 SRAM_EN : 1
590 23:18:55.041449 MD32_EN : 0
591 23:18:55.044808 ===================================
592 23:18:55.048217 [ANA_INIT] >>>>>>>>>>>>>>
593 23:18:55.051328 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 23:18:55.054738 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 23:18:55.058076 ===================================
596 23:18:55.061484 data_rate = 1600,PCW = 0X7600
597 23:18:55.064477 ===================================
598 23:18:55.068017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 23:18:55.071170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 23:18:55.077768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 23:18:55.081246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 23:18:55.084624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 23:18:55.087766 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 23:18:55.091635 [ANA_INIT] flow start
605 23:18:55.095373 [ANA_INIT] PLL >>>>>>>>
606 23:18:55.095532 [ANA_INIT] PLL <<<<<<<<
607 23:18:55.098981 [ANA_INIT] MIDPI >>>>>>>>
608 23:18:55.102807 [ANA_INIT] MIDPI <<<<<<<<
609 23:18:55.102934 [ANA_INIT] DLL >>>>>>>>
610 23:18:55.106314 [ANA_INIT] flow end
611 23:18:55.109655 ============ LP4 DIFF to SE enter ============
612 23:18:55.113522 ============ LP4 DIFF to SE exit ============
613 23:18:55.117437 [ANA_INIT] <<<<<<<<<<<<<
614 23:18:55.117593 [Flow] Enable top DCM control >>>>>
615 23:18:55.121024 [Flow] Enable top DCM control <<<<<
616 23:18:55.124704 Enable DLL master slave shuffle
617 23:18:55.132801 ==============================================================
618 23:18:55.132976 Gating Mode config
619 23:18:55.139350 ==============================================================
620 23:18:55.139480 Config description:
621 23:18:55.149095 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 23:18:55.155971 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 23:18:55.159455 SELPH_MODE 0: By rank 1: By Phase
624 23:18:55.166074 ==============================================================
625 23:18:55.169288 GAT_TRACK_EN = 1
626 23:18:55.172601 RX_GATING_MODE = 2
627 23:18:55.176059 RX_GATING_TRACK_MODE = 2
628 23:18:55.179655 SELPH_MODE = 1
629 23:18:55.182683 PICG_EARLY_EN = 1
630 23:18:55.186087 VALID_LAT_VALUE = 1
631 23:18:55.189550 ==============================================================
632 23:18:55.192685 Enter into Gating configuration >>>>
633 23:18:55.195820 Exit from Gating configuration <<<<
634 23:18:55.199315 Enter into DVFS_PRE_config >>>>>
635 23:18:55.209352 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 23:18:55.212614 Exit from DVFS_PRE_config <<<<<
637 23:18:55.216094 Enter into PICG configuration >>>>
638 23:18:55.219192 Exit from PICG configuration <<<<
639 23:18:55.222588 [RX_INPUT] configuration >>>>>
640 23:18:55.225789 [RX_INPUT] configuration <<<<<
641 23:18:55.232491 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 23:18:55.235638 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 23:18:55.242689 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 23:18:55.249081 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 23:18:55.255672 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 23:18:55.262404 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 23:18:55.265763 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 23:18:55.269055 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 23:18:55.272422 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 23:18:55.278985 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 23:18:55.282488 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 23:18:55.285571 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 23:18:55.289121 ===================================
654 23:18:55.292198 LPDDR4 DRAM CONFIGURATION
655 23:18:55.295691 ===================================
656 23:18:55.295831 EX_ROW_EN[0] = 0x0
657 23:18:55.299152 EX_ROW_EN[1] = 0x0
658 23:18:55.299294 LP4Y_EN = 0x0
659 23:18:55.302636 WORK_FSP = 0x0
660 23:18:55.305659 WL = 0x2
661 23:18:55.305805 RL = 0x2
662 23:18:55.309099 BL = 0x2
663 23:18:55.309214 RPST = 0x0
664 23:18:55.312512 RD_PRE = 0x0
665 23:18:55.312622 WR_PRE = 0x1
666 23:18:55.315694 WR_PST = 0x0
667 23:18:55.315833 DBI_WR = 0x0
668 23:18:55.319254 DBI_RD = 0x0
669 23:18:55.319390 OTF = 0x1
670 23:18:55.322488 ===================================
671 23:18:55.325909 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 23:18:55.332377 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 23:18:55.335733 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 23:18:55.338996 ===================================
675 23:18:55.342362 LPDDR4 DRAM CONFIGURATION
676 23:18:55.345487 ===================================
677 23:18:55.345615 EX_ROW_EN[0] = 0x10
678 23:18:55.349173 EX_ROW_EN[1] = 0x0
679 23:18:55.349318 LP4Y_EN = 0x0
680 23:18:55.352752 WORK_FSP = 0x0
681 23:18:55.352883 WL = 0x2
682 23:18:55.356719 RL = 0x2
683 23:18:55.356841 BL = 0x2
684 23:18:55.360435 RPST = 0x0
685 23:18:55.360577 RD_PRE = 0x0
686 23:18:55.363968 WR_PRE = 0x1
687 23:18:55.364099 WR_PST = 0x0
688 23:18:55.367506 DBI_WR = 0x0
689 23:18:55.367641 DBI_RD = 0x0
690 23:18:55.367736 OTF = 0x1
691 23:18:55.371073 ===================================
692 23:18:55.378072 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 23:18:55.382681 nWR fixed to 40
694 23:18:55.386155 [ModeRegInit_LP4] CH0 RK0
695 23:18:55.386283 [ModeRegInit_LP4] CH0 RK1
696 23:18:55.389796 [ModeRegInit_LP4] CH1 RK0
697 23:18:55.392941 [ModeRegInit_LP4] CH1 RK1
698 23:18:55.393103 match AC timing 13
699 23:18:55.396677 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 23:18:55.400207 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 23:18:55.407277 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 23:18:55.411084 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 23:18:55.414553 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 23:18:55.417982 [EMI DOE] emi_dcm 0
705 23:18:55.421823 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 23:18:55.421982 ==
707 23:18:55.425365 Dram Type= 6, Freq= 0, CH_0, rank 0
708 23:18:55.429358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 23:18:55.429522 ==
710 23:18:55.436471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 23:18:55.440105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 23:18:55.450251 [CA 0] Center 38 (7~69) winsize 63
713 23:18:55.453876 [CA 1] Center 37 (7~68) winsize 62
714 23:18:55.457777 [CA 2] Center 35 (5~66) winsize 62
715 23:18:55.461626 [CA 3] Center 35 (5~66) winsize 62
716 23:18:55.465268 [CA 4] Center 34 (4~65) winsize 62
717 23:18:55.465430 [CA 5] Center 34 (4~65) winsize 62
718 23:18:55.468876
719 23:18:55.472622 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 23:18:55.472804
721 23:18:55.476282 [CATrainingPosCal] consider 1 rank data
722 23:18:55.476440 u2DelayCellTimex100 = 270/100 ps
723 23:18:55.480323 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 23:18:55.483913 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 23:18:55.487778 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 23:18:55.491359 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 23:18:55.495203 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 23:18:55.498626 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 23:18:55.498788
730 23:18:55.502549 CA PerBit enable=1, Macro0, CA PI delay=34
731 23:18:55.502668
732 23:18:55.506500 [CBTSetCACLKResult] CA Dly = 34
733 23:18:55.506644 CS Dly: 6 (0~37)
734 23:18:55.510018 ==
735 23:18:55.510163 Dram Type= 6, Freq= 0, CH_0, rank 1
736 23:18:55.517216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 23:18:55.517377 ==
738 23:18:55.520898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 23:18:55.527912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 23:18:55.536613 [CA 0] Center 38 (7~69) winsize 63
741 23:18:55.540479 [CA 1] Center 38 (7~69) winsize 63
742 23:18:55.543977 [CA 2] Center 35 (5~66) winsize 62
743 23:18:55.547931 [CA 3] Center 35 (5~66) winsize 62
744 23:18:55.551672 [CA 4] Center 34 (4~65) winsize 62
745 23:18:55.551834 [CA 5] Center 34 (4~65) winsize 62
746 23:18:55.555336
747 23:18:55.558923 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 23:18:55.559064
749 23:18:55.562314 [CATrainingPosCal] consider 2 rank data
750 23:18:55.562426 u2DelayCellTimex100 = 270/100 ps
751 23:18:55.566196 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 23:18:55.569527 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 23:18:55.573414 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 23:18:55.576603 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 23:18:55.580357 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 23:18:55.583989 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 23:18:55.584122
758 23:18:55.591569 CA PerBit enable=1, Macro0, CA PI delay=34
759 23:18:55.591752
760 23:18:55.591853 [CBTSetCACLKResult] CA Dly = 34
761 23:18:55.594894 CS Dly: 6 (0~37)
762 23:18:55.594998
763 23:18:55.598682 ----->DramcWriteLeveling(PI) begin...
764 23:18:55.598810 ==
765 23:18:55.602280 Dram Type= 6, Freq= 0, CH_0, rank 0
766 23:18:55.605987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 23:18:55.606116 ==
768 23:18:55.609634 Write leveling (Byte 0): 33 => 33
769 23:18:55.613185 Write leveling (Byte 1): 32 => 32
770 23:18:55.613323 DramcWriteLeveling(PI) end<-----
771 23:18:55.613398
772 23:18:55.617092 ==
773 23:18:55.617230 Dram Type= 6, Freq= 0, CH_0, rank 0
774 23:18:55.620962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 23:18:55.624875 ==
776 23:18:55.625038 [Gating] SW mode calibration
777 23:18:55.632207 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 23:18:55.639315 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 23:18:55.642919 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 23:18:55.646921 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 23:18:55.650021 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 23:18:55.656629 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 23:18:55.660059 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 23:18:55.663584 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 23:18:55.669892 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 23:18:55.673929 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 23:18:55.677602 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 23:18:55.681193 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:18:55.684991 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:18:55.688907 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:18:55.695616 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:18:55.698814 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:18:55.702698 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:18:55.709305 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:18:55.712893 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:18:55.716021 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:18:55.722786 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
798 23:18:55.726247 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:18:55.729559 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:18:55.732762 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:18:55.739347 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:18:55.742808 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:18:55.745994 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 23:18:55.752585 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 23:18:55.756050 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:18:55.759210 0 9 12 | B1->B0 | 2e2e 3232 | 0 1 | (0 0) (1 1)
807 23:18:55.766143 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 23:18:55.769239 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 23:18:55.772641 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 23:18:55.779447 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 23:18:55.782833 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 23:18:55.786121 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 23:18:55.792849 0 10 8 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
814 23:18:55.796105 0 10 12 | B1->B0 | 2f2f 2727 | 0 0 | (1 0) (0 0)
815 23:18:55.799295 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 23:18:55.805836 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 23:18:55.809593 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 23:18:55.812902 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 23:18:55.815953 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 23:18:55.822698 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 23:18:55.826168 0 11 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
822 23:18:55.829437 0 11 12 | B1->B0 | 3434 4343 | 1 0 | (1 1) (1 1)
823 23:18:55.836050 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 23:18:55.839602 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 23:18:55.842712 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 23:18:55.849626 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 23:18:55.852683 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 23:18:55.856116 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 23:18:55.862861 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 23:18:55.866281 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 23:18:55.869629 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 23:18:55.876188 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 23:18:55.879489 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 23:18:55.883027 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 23:18:55.889578 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 23:18:55.892895 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 23:18:55.896288 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:18:55.899555 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:18:55.906189 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:18:55.909561 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:18:55.912971 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:18:55.919746 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:18:55.923122 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:18:55.926266 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:18:55.933010 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
846 23:18:55.936460 Total UI for P1: 0, mck2ui 16
847 23:18:55.939705 best dqsien dly found for B0: ( 0, 14, 6)
848 23:18:55.942851 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
849 23:18:55.946391 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 23:18:55.949714 Total UI for P1: 0, mck2ui 16
851 23:18:55.952850 best dqsien dly found for B1: ( 0, 14, 12)
852 23:18:55.956324 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
853 23:18:55.959598 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 23:18:55.959750
855 23:18:55.966341 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
856 23:18:55.969580 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 23:18:55.969693 [Gating] SW calibration Done
858 23:18:55.973159 ==
859 23:18:55.976235 Dram Type= 6, Freq= 0, CH_0, rank 0
860 23:18:55.979474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 23:18:55.979588 ==
862 23:18:55.979655 RX Vref Scan: 0
863 23:18:55.979717
864 23:18:55.983100 RX Vref 0 -> 0, step: 1
865 23:18:55.983209
866 23:18:55.986232 RX Delay -130 -> 252, step: 16
867 23:18:55.989436 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
868 23:18:55.992995 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 23:18:55.996140 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
870 23:18:56.002931 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
871 23:18:56.006276 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 23:18:56.009465 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 23:18:56.013255 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 23:18:56.016368 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 23:18:56.022968 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
876 23:18:56.026388 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 23:18:56.029645 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 23:18:56.032796 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 23:18:56.036210 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 23:18:56.042982 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 23:18:56.046045 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 23:18:56.049469 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 23:18:56.049599 ==
884 23:18:56.052973 Dram Type= 6, Freq= 0, CH_0, rank 0
885 23:18:56.056171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 23:18:56.059442 ==
887 23:18:56.059571 DQS Delay:
888 23:18:56.059641 DQS0 = 0, DQS1 = 0
889 23:18:56.063081 DQM Delay:
890 23:18:56.063187 DQM0 = 84, DQM1 = 70
891 23:18:56.066154 DQ Delay:
892 23:18:56.066252 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
893 23:18:56.069364 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 23:18:56.073015 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =61
895 23:18:56.076294 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 23:18:56.076436
897 23:18:56.079490
898 23:18:56.079594 ==
899 23:18:56.082859 Dram Type= 6, Freq= 0, CH_0, rank 0
900 23:18:56.086761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 23:18:56.086881 ==
902 23:18:56.086978
903 23:18:56.087061
904 23:18:56.087141 TX Vref Scan disable
905 23:18:56.090272 == TX Byte 0 ==
906 23:18:56.093451 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
907 23:18:56.100130 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
908 23:18:56.100285 == TX Byte 1 ==
909 23:18:56.103652 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
910 23:18:56.110266 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
911 23:18:56.110409 ==
912 23:18:56.113514 Dram Type= 6, Freq= 0, CH_0, rank 0
913 23:18:56.116931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 23:18:56.117072 ==
915 23:18:56.129454 TX Vref=22, minBit 3, minWin=26, winSum=428
916 23:18:56.132570 TX Vref=24, minBit 14, minWin=26, winSum=435
917 23:18:56.136087 TX Vref=26, minBit 2, minWin=27, winSum=442
918 23:18:56.139571 TX Vref=28, minBit 9, minWin=27, winSum=444
919 23:18:56.142773 TX Vref=30, minBit 9, minWin=27, winSum=444
920 23:18:56.149287 TX Vref=32, minBit 10, minWin=26, winSum=437
921 23:18:56.152530 [TxChooseVref] Worse bit 9, Min win 27, Win sum 444, Final Vref 28
922 23:18:56.152676
923 23:18:56.156171 Final TX Range 1 Vref 28
924 23:18:56.156304
925 23:18:56.156411 ==
926 23:18:56.159275 Dram Type= 6, Freq= 0, CH_0, rank 0
927 23:18:56.162581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 23:18:56.162716 ==
929 23:18:56.162825
930 23:18:56.166127
931 23:18:56.166245 TX Vref Scan disable
932 23:18:56.169619 == TX Byte 0 ==
933 23:18:56.172919 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
934 23:18:56.176028 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
935 23:18:56.179442 == TX Byte 1 ==
936 23:18:56.182589 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
937 23:18:56.186113 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
938 23:18:56.189234
939 23:18:56.189351 [DATLAT]
940 23:18:56.189454 Freq=800, CH0 RK0
941 23:18:56.189568
942 23:18:56.192669 DATLAT Default: 0xa
943 23:18:56.192779 0, 0xFFFF, sum = 0
944 23:18:56.195862 1, 0xFFFF, sum = 0
945 23:18:56.195952 2, 0xFFFF, sum = 0
946 23:18:56.199084 3, 0xFFFF, sum = 0
947 23:18:56.202684 4, 0xFFFF, sum = 0
948 23:18:56.202805 5, 0xFFFF, sum = 0
949 23:18:56.205957 6, 0xFFFF, sum = 0
950 23:18:56.206071 7, 0xFFFF, sum = 0
951 23:18:56.209278 8, 0xFFFF, sum = 0
952 23:18:56.209392 9, 0x0, sum = 1
953 23:18:56.209508 10, 0x0, sum = 2
954 23:18:56.212732 11, 0x0, sum = 3
955 23:18:56.212813 12, 0x0, sum = 4
956 23:18:56.215916 best_step = 10
957 23:18:56.215999
958 23:18:56.216083 ==
959 23:18:56.219286 Dram Type= 6, Freq= 0, CH_0, rank 0
960 23:18:56.222597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 23:18:56.222693 ==
962 23:18:56.225987 RX Vref Scan: 1
963 23:18:56.226095
964 23:18:56.226196 Set Vref Range= 32 -> 127
965 23:18:56.229391
966 23:18:56.229510 RX Vref 32 -> 127, step: 1
967 23:18:56.229598
968 23:18:56.232663 RX Delay -111 -> 252, step: 8
969 23:18:56.232773
970 23:18:56.236069 Set Vref, RX VrefLevel [Byte0]: 32
971 23:18:56.239226 [Byte1]: 32
972 23:18:56.239318
973 23:18:56.242669 Set Vref, RX VrefLevel [Byte0]: 33
974 23:18:56.245830 [Byte1]: 33
975 23:18:56.249832
976 23:18:56.249928 Set Vref, RX VrefLevel [Byte0]: 34
977 23:18:56.253220 [Byte1]: 34
978 23:18:56.257496
979 23:18:56.257621 Set Vref, RX VrefLevel [Byte0]: 35
980 23:18:56.260988 [Byte1]: 35
981 23:18:56.265127
982 23:18:56.265254 Set Vref, RX VrefLevel [Byte0]: 36
983 23:18:56.268449 [Byte1]: 36
984 23:18:56.272985
985 23:18:56.273091 Set Vref, RX VrefLevel [Byte0]: 37
986 23:18:56.276311 [Byte1]: 37
987 23:18:56.280420
988 23:18:56.280526 Set Vref, RX VrefLevel [Byte0]: 38
989 23:18:56.283695 [Byte1]: 38
990 23:18:56.288188
991 23:18:56.288305 Set Vref, RX VrefLevel [Byte0]: 39
992 23:18:56.291606 [Byte1]: 39
993 23:18:56.296019
994 23:18:56.296130 Set Vref, RX VrefLevel [Byte0]: 40
995 23:18:56.299036 [Byte1]: 40
996 23:18:56.303456
997 23:18:56.303561 Set Vref, RX VrefLevel [Byte0]: 41
998 23:18:56.306645 [Byte1]: 41
999 23:18:56.310911
1000 23:18:56.311011 Set Vref, RX VrefLevel [Byte0]: 42
1001 23:18:56.314338 [Byte1]: 42
1002 23:18:56.318683
1003 23:18:56.318781 Set Vref, RX VrefLevel [Byte0]: 43
1004 23:18:56.322190 [Byte1]: 43
1005 23:18:56.326478
1006 23:18:56.326587 Set Vref, RX VrefLevel [Byte0]: 44
1007 23:18:56.329696 [Byte1]: 44
1008 23:18:56.333802
1009 23:18:56.333906 Set Vref, RX VrefLevel [Byte0]: 45
1010 23:18:56.337538 [Byte1]: 45
1011 23:18:56.341828
1012 23:18:56.341941 Set Vref, RX VrefLevel [Byte0]: 46
1013 23:18:56.344953 [Byte1]: 46
1014 23:18:56.349602
1015 23:18:56.349715 Set Vref, RX VrefLevel [Byte0]: 47
1016 23:18:56.353103 [Byte1]: 47
1017 23:18:56.357050
1018 23:18:56.357158 Set Vref, RX VrefLevel [Byte0]: 48
1019 23:18:56.360294 [Byte1]: 48
1020 23:18:56.364911
1021 23:18:56.365021 Set Vref, RX VrefLevel [Byte0]: 49
1022 23:18:56.368254 [Byte1]: 49
1023 23:18:56.372355
1024 23:18:56.372464 Set Vref, RX VrefLevel [Byte0]: 50
1025 23:18:56.375744 [Byte1]: 50
1026 23:18:56.379739
1027 23:18:56.379841 Set Vref, RX VrefLevel [Byte0]: 51
1028 23:18:56.383263 [Byte1]: 51
1029 23:18:56.387611
1030 23:18:56.387716 Set Vref, RX VrefLevel [Byte0]: 52
1031 23:18:56.390698 [Byte1]: 52
1032 23:18:56.394987
1033 23:18:56.395096 Set Vref, RX VrefLevel [Byte0]: 53
1034 23:18:56.398544 [Byte1]: 53
1035 23:18:56.402983
1036 23:18:56.403085 Set Vref, RX VrefLevel [Byte0]: 54
1037 23:18:56.406036 [Byte1]: 54
1038 23:18:56.410375
1039 23:18:56.410482 Set Vref, RX VrefLevel [Byte0]: 55
1040 23:18:56.413571 [Byte1]: 55
1041 23:18:56.418256
1042 23:18:56.418358 Set Vref, RX VrefLevel [Byte0]: 56
1043 23:18:56.421351 [Byte1]: 56
1044 23:18:56.425621
1045 23:18:56.425724 Set Vref, RX VrefLevel [Byte0]: 57
1046 23:18:56.429029 [Byte1]: 57
1047 23:18:56.433275
1048 23:18:56.433373 Set Vref, RX VrefLevel [Byte0]: 58
1049 23:18:56.436758 [Byte1]: 58
1050 23:18:56.441143
1051 23:18:56.441230 Set Vref, RX VrefLevel [Byte0]: 59
1052 23:18:56.444440 [Byte1]: 59
1053 23:18:56.448689
1054 23:18:56.448798 Set Vref, RX VrefLevel [Byte0]: 60
1055 23:18:56.452065 [Byte1]: 60
1056 23:18:56.456469
1057 23:18:56.456557 Set Vref, RX VrefLevel [Byte0]: 61
1058 23:18:56.459639 [Byte1]: 61
1059 23:18:56.463898
1060 23:18:56.463988 Set Vref, RX VrefLevel [Byte0]: 62
1061 23:18:56.467073 [Byte1]: 62
1062 23:18:56.471750
1063 23:18:56.471838 Set Vref, RX VrefLevel [Byte0]: 63
1064 23:18:56.474799 [Byte1]: 63
1065 23:18:56.479331
1066 23:18:56.479427 Set Vref, RX VrefLevel [Byte0]: 64
1067 23:18:56.482555 [Byte1]: 64
1068 23:18:56.486829
1069 23:18:56.486953 Set Vref, RX VrefLevel [Byte0]: 65
1070 23:18:56.490044 [Byte1]: 65
1071 23:18:56.494550
1072 23:18:56.494639 Set Vref, RX VrefLevel [Byte0]: 66
1073 23:18:56.497951 [Byte1]: 66
1074 23:18:56.502052
1075 23:18:56.502140 Set Vref, RX VrefLevel [Byte0]: 67
1076 23:18:56.505526 [Byte1]: 67
1077 23:18:56.509953
1078 23:18:56.510038 Set Vref, RX VrefLevel [Byte0]: 68
1079 23:18:56.512970 [Byte1]: 68
1080 23:18:56.517600
1081 23:18:56.517682 Set Vref, RX VrefLevel [Byte0]: 69
1082 23:18:56.520639 [Byte1]: 69
1083 23:18:56.525218
1084 23:18:56.525301 Set Vref, RX VrefLevel [Byte0]: 70
1085 23:18:56.528404 [Byte1]: 70
1086 23:18:56.532686
1087 23:18:56.532769 Set Vref, RX VrefLevel [Byte0]: 71
1088 23:18:56.535923 [Byte1]: 71
1089 23:18:56.540570
1090 23:18:56.540687 Set Vref, RX VrefLevel [Byte0]: 72
1091 23:18:56.543671 [Byte1]: 72
1092 23:18:56.548128
1093 23:18:56.548210 Set Vref, RX VrefLevel [Byte0]: 73
1094 23:18:56.551419 [Byte1]: 73
1095 23:18:56.555554
1096 23:18:56.555640 Set Vref, RX VrefLevel [Byte0]: 74
1097 23:18:56.559032 [Byte1]: 74
1098 23:18:56.563374
1099 23:18:56.563457 Set Vref, RX VrefLevel [Byte0]: 75
1100 23:18:56.566786 [Byte1]: 75
1101 23:18:56.571118
1102 23:18:56.571200 Set Vref, RX VrefLevel [Byte0]: 76
1103 23:18:56.574251 [Byte1]: 76
1104 23:18:56.578583
1105 23:18:56.578664 Set Vref, RX VrefLevel [Byte0]: 77
1106 23:18:56.582085 [Byte1]: 77
1107 23:18:56.586245
1108 23:18:56.586328 Set Vref, RX VrefLevel [Byte0]: 78
1109 23:18:56.589572 [Byte1]: 78
1110 23:18:56.593845
1111 23:18:56.593928 Set Vref, RX VrefLevel [Byte0]: 79
1112 23:18:56.597212 [Byte1]: 79
1113 23:18:56.601425
1114 23:18:56.601514 Final RX Vref Byte 0 = 63 to rank0
1115 23:18:56.605084 Final RX Vref Byte 1 = 59 to rank0
1116 23:18:56.608166 Final RX Vref Byte 0 = 63 to rank1
1117 23:18:56.611649 Final RX Vref Byte 1 = 59 to rank1==
1118 23:18:56.615087 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 23:18:56.621380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 23:18:56.621499 ==
1121 23:18:56.621569 DQS Delay:
1122 23:18:56.621631 DQS0 = 0, DQS1 = 0
1123 23:18:56.624966 DQM Delay:
1124 23:18:56.625049 DQM0 = 81, DQM1 = 67
1125 23:18:56.628292 DQ Delay:
1126 23:18:56.631536 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1127 23:18:56.635026 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1128 23:18:56.635110 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1129 23:18:56.641677 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1130 23:18:56.641762
1131 23:18:56.641827
1132 23:18:56.648157 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1133 23:18:56.651482 CH0 RK0: MR19=606, MR18=2B2A
1134 23:18:56.658015 CH0_RK0: MR19=0x606, MR18=0x2B2A, DQSOSC=398, MR23=63, INC=93, DEC=62
1135 23:18:56.658133
1136 23:18:56.661352 ----->DramcWriteLeveling(PI) begin...
1137 23:18:56.661464 ==
1138 23:18:56.664769 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 23:18:56.667915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 23:18:56.668001 ==
1141 23:18:56.671307 Write leveling (Byte 0): 30 => 30
1142 23:18:56.674745 Write leveling (Byte 1): 31 => 31
1143 23:18:56.677768 DramcWriteLeveling(PI) end<-----
1144 23:18:56.677853
1145 23:18:56.677920 ==
1146 23:18:56.681359 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 23:18:56.684691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 23:18:56.684776 ==
1149 23:18:56.687829 [Gating] SW mode calibration
1150 23:18:56.694605 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 23:18:56.701292 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 23:18:56.704841 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 23:18:56.707972 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 23:18:56.714767 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1155 23:18:56.717975 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:18:56.721272 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:18:56.728070 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:18:56.731222 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:18:56.734770 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:18:56.741383 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:18:56.744818 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:18:56.748156 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:18:56.754535 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:18:56.757916 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:18:56.802021 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:18:56.802394 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:18:56.802503 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:18:56.802605 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:18:56.802695 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1170 23:18:56.802784 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1171 23:18:56.802885 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:18:56.802985 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:18:56.803072 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:18:56.803158 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:18:56.846199 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:18:56.846548 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:18:56.846635 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:18:56.846719 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1179 23:18:56.846783 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1180 23:18:56.846876 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:18:56.847291 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 23:18:56.847381 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 23:18:56.847632 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 23:18:56.847697 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 23:18:56.890471 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
1186 23:18:56.890899 0 10 8 | B1->B0 | 3131 2626 | 0 0 | (0 1) (1 0)
1187 23:18:56.890983 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1188 23:18:56.891051 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:18:56.891131 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:18:56.891193 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:18:56.891250 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 23:18:56.891306 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:18:56.891375 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 23:18:56.891441 0 11 8 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
1195 23:18:56.934513 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:18:56.934867 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:18:56.934940 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:18:56.935012 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 23:18:56.935091 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 23:18:56.935171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 23:18:56.935293 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 23:18:56.935375 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 23:18:56.935432 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:18:56.935499 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:18:56.949150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:18:56.949490 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:18:56.949580 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:18:56.952479 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:18:56.955540 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:18:56.959057 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:18:56.965842 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:18:56.969132 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:18:56.972301 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:18:56.975825 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:18:56.982235 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:18:56.985883 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:18:56.988899 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1218 23:18:56.995570 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 23:18:56.999063 Total UI for P1: 0, mck2ui 16
1220 23:18:57.002513 best dqsien dly found for B0: ( 0, 14, 4)
1221 23:18:57.005935 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1222 23:18:57.009064 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 23:18:57.012519 Total UI for P1: 0, mck2ui 16
1224 23:18:57.015696 best dqsien dly found for B1: ( 0, 14, 8)
1225 23:18:57.019138 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1226 23:18:57.022297 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1227 23:18:57.022428
1228 23:18:57.029108 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1229 23:18:57.032257 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1230 23:18:57.032347 [Gating] SW calibration Done
1231 23:18:57.035593 ==
1232 23:18:57.039018 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 23:18:57.042333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 23:18:57.042435 ==
1235 23:18:57.042500 RX Vref Scan: 0
1236 23:18:57.042576
1237 23:18:57.045743 RX Vref 0 -> 0, step: 1
1238 23:18:57.045826
1239 23:18:57.048875 RX Delay -130 -> 252, step: 16
1240 23:18:57.052312 iDelay=222, Bit 0, Center 77 (-34 ~ 189) 224
1241 23:18:57.055363 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1242 23:18:57.062123 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1243 23:18:57.065520 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1244 23:18:57.068664 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1245 23:18:57.072153 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1246 23:18:57.075338 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1247 23:18:57.078980 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1248 23:18:57.085671 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1249 23:18:57.088861 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1250 23:18:57.092205 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1251 23:18:57.095668 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1252 23:18:57.102151 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1253 23:18:57.105215 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1254 23:18:57.108627 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1255 23:18:57.112060 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1256 23:18:57.112167 ==
1257 23:18:57.115645 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 23:18:57.118613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 23:18:57.122057 ==
1260 23:18:57.122164 DQS Delay:
1261 23:18:57.122234 DQS0 = 0, DQS1 = 0
1262 23:18:57.125592 DQM Delay:
1263 23:18:57.125691 DQM0 = 79, DQM1 = 69
1264 23:18:57.128715 DQ Delay:
1265 23:18:57.131872 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1266 23:18:57.131977 DQ4 =85, DQ5 =61, DQ6 =93, DQ7 =93
1267 23:18:57.135364 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1268 23:18:57.138773 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1269 23:18:57.141961
1270 23:18:57.142068
1271 23:18:57.142135 ==
1272 23:18:57.145305 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 23:18:57.148752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 23:18:57.148868 ==
1275 23:18:57.148937
1276 23:18:57.148998
1277 23:18:57.152116 TX Vref Scan disable
1278 23:18:57.152214 == TX Byte 0 ==
1279 23:18:57.158758 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1280 23:18:57.162110 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1281 23:18:57.162240 == TX Byte 1 ==
1282 23:18:57.168718 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1283 23:18:57.171950 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1284 23:18:57.172075 ==
1285 23:18:57.175422 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 23:18:57.178945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 23:18:57.179058 ==
1288 23:18:57.191813 TX Vref=22, minBit 1, minWin=26, winSum=432
1289 23:18:57.195366 TX Vref=24, minBit 3, minWin=27, winSum=440
1290 23:18:57.198554 TX Vref=26, minBit 0, minWin=27, winSum=437
1291 23:18:57.201975 TX Vref=28, minBit 1, minWin=27, winSum=441
1292 23:18:57.205210 TX Vref=30, minBit 8, minWin=27, winSum=445
1293 23:18:57.211908 TX Vref=32, minBit 11, minWin=26, winSum=437
1294 23:18:57.215042 [TxChooseVref] Worse bit 8, Min win 27, Win sum 445, Final Vref 30
1295 23:18:57.215139
1296 23:18:57.218342 Final TX Range 1 Vref 30
1297 23:18:57.218427
1298 23:18:57.218492 ==
1299 23:18:57.221957 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 23:18:57.224988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 23:18:57.225076 ==
1302 23:18:57.228482
1303 23:18:57.228580
1304 23:18:57.228647 TX Vref Scan disable
1305 23:18:57.231651 == TX Byte 0 ==
1306 23:18:57.235292 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1307 23:18:57.238365 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1308 23:18:57.241871 == TX Byte 1 ==
1309 23:18:57.245495 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1310 23:18:57.248523 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1311 23:18:57.252044
1312 23:18:57.252133 [DATLAT]
1313 23:18:57.252198 Freq=800, CH0 RK1
1314 23:18:57.252260
1315 23:18:57.255268 DATLAT Default: 0xa
1316 23:18:57.255353 0, 0xFFFF, sum = 0
1317 23:18:57.258627 1, 0xFFFF, sum = 0
1318 23:18:57.258715 2, 0xFFFF, sum = 0
1319 23:18:57.262321 3, 0xFFFF, sum = 0
1320 23:18:57.262428 4, 0xFFFF, sum = 0
1321 23:18:57.265075 5, 0xFFFF, sum = 0
1322 23:18:57.265163 6, 0xFFFF, sum = 0
1323 23:18:57.268686 7, 0xFFFF, sum = 0
1324 23:18:57.271753 8, 0xFFFF, sum = 0
1325 23:18:57.271846 9, 0x0, sum = 1
1326 23:18:57.271914 10, 0x0, sum = 2
1327 23:18:57.275457 11, 0x0, sum = 3
1328 23:18:57.275568 12, 0x0, sum = 4
1329 23:18:57.278683 best_step = 10
1330 23:18:57.278769
1331 23:18:57.278833 ==
1332 23:18:57.281931 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 23:18:57.285177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 23:18:57.285267 ==
1335 23:18:57.288377 RX Vref Scan: 0
1336 23:18:57.288461
1337 23:18:57.288527 RX Vref 0 -> 0, step: 1
1338 23:18:57.288586
1339 23:18:57.291627 RX Delay -111 -> 252, step: 8
1340 23:18:57.298606 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1341 23:18:57.301996 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1342 23:18:57.305295 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1343 23:18:57.308593 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1344 23:18:57.312204 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1345 23:18:57.318623 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1346 23:18:57.322241 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1347 23:18:57.325326 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1348 23:18:57.328857 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1349 23:18:57.332014 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1350 23:18:57.338505 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1351 23:18:57.341915 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1352 23:18:57.345375 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1353 23:18:57.348572 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1354 23:18:57.351966 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1355 23:18:57.358705 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1356 23:18:57.358822 ==
1357 23:18:57.361783 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 23:18:57.365149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 23:18:57.365259 ==
1360 23:18:57.365360 DQS Delay:
1361 23:18:57.368642 DQS0 = 0, DQS1 = 0
1362 23:18:57.368728 DQM Delay:
1363 23:18:57.371847 DQM0 = 79, DQM1 = 70
1364 23:18:57.371976 DQ Delay:
1365 23:18:57.375384 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1366 23:18:57.378910 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1367 23:18:57.381921 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1368 23:18:57.385311 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1369 23:18:57.385426
1370 23:18:57.385519
1371 23:18:57.391977 [DQSOSCAuto] RK1, (LSB)MR18= 0x4620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1372 23:18:57.395545 CH0 RK1: MR19=606, MR18=4620
1373 23:18:57.402077 CH0_RK1: MR19=0x606, MR18=0x4620, DQSOSC=392, MR23=63, INC=96, DEC=64
1374 23:18:57.405647 [RxdqsGatingPostProcess] freq 800
1375 23:18:57.412027 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 23:18:57.412165 Pre-setting of DQS Precalculation
1377 23:18:57.418929 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 23:18:57.419065 ==
1379 23:18:57.421900 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 23:18:57.425446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 23:18:57.425581 ==
1382 23:18:57.432052 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 23:18:57.438722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 23:18:57.447105 [CA 0] Center 36 (6~66) winsize 61
1385 23:18:57.450209 [CA 1] Center 37 (7~67) winsize 61
1386 23:18:57.453783 [CA 2] Center 34 (4~64) winsize 61
1387 23:18:57.457041 [CA 3] Center 34 (4~64) winsize 61
1388 23:18:57.460223 [CA 4] Center 34 (4~64) winsize 61
1389 23:18:57.463798 [CA 5] Center 33 (3~64) winsize 62
1390 23:18:57.463944
1391 23:18:57.466869 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1392 23:18:57.466982
1393 23:18:57.470384 [CATrainingPosCal] consider 1 rank data
1394 23:18:57.473500 u2DelayCellTimex100 = 270/100 ps
1395 23:18:57.476822 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1396 23:18:57.480164 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
1397 23:18:57.487040 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1398 23:18:57.490424 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1399 23:18:57.493469 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1400 23:18:57.497055 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1401 23:18:57.497163
1402 23:18:57.500591 CA PerBit enable=1, Macro0, CA PI delay=33
1403 23:18:57.500695
1404 23:18:57.503532 [CBTSetCACLKResult] CA Dly = 33
1405 23:18:57.503612 CS Dly: 5 (0~36)
1406 23:18:57.503698 ==
1407 23:18:57.506956 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 23:18:57.513631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 23:18:57.513740 ==
1410 23:18:57.516931 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 23:18:57.523700 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 23:18:57.532963 [CA 0] Center 36 (6~67) winsize 62
1413 23:18:57.536532 [CA 1] Center 36 (6~67) winsize 62
1414 23:18:57.539588 [CA 2] Center 35 (5~65) winsize 61
1415 23:18:57.543174 [CA 3] Center 33 (3~64) winsize 62
1416 23:18:57.546306 [CA 4] Center 34 (4~65) winsize 62
1417 23:18:57.549495 [CA 5] Center 33 (3~64) winsize 62
1418 23:18:57.549595
1419 23:18:57.552947 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1420 23:18:57.553056
1421 23:18:57.556299 [CATrainingPosCal] consider 2 rank data
1422 23:18:57.559730 u2DelayCellTimex100 = 270/100 ps
1423 23:18:57.563123 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1424 23:18:57.566347 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
1425 23:18:57.572985 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1426 23:18:57.576897 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1427 23:18:57.580294 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1428 23:18:57.583909 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1429 23:18:57.584033
1430 23:18:57.587710 CA PerBit enable=1, Macro0, CA PI delay=33
1431 23:18:57.587821
1432 23:18:57.587914 [CBTSetCACLKResult] CA Dly = 33
1433 23:18:57.591433 CS Dly: 6 (0~38)
1434 23:18:57.591540
1435 23:18:57.595123 ----->DramcWriteLeveling(PI) begin...
1436 23:18:57.595230 ==
1437 23:18:57.598617 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 23:18:57.602427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 23:18:57.602540 ==
1440 23:18:57.605931 Write leveling (Byte 0): 29 => 29
1441 23:18:57.609515 Write leveling (Byte 1): 31 => 31
1442 23:18:57.612839 DramcWriteLeveling(PI) end<-----
1443 23:18:57.612915
1444 23:18:57.612980 ==
1445 23:18:57.615973 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 23:18:57.619601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 23:18:57.619691 ==
1448 23:18:57.622572 [Gating] SW mode calibration
1449 23:18:57.629154 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 23:18:57.635773 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 23:18:57.639248 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 23:18:57.642680 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 23:18:57.645722 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1454 23:18:57.652640 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:18:57.655769 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:18:57.659298 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:18:57.665746 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:18:57.669151 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:18:57.672518 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:18:57.679229 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:18:57.682730 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:18:57.685897 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:18:57.692575 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:18:57.695983 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:18:57.699019 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:18:57.705988 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:18:57.709054 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:18:57.712434 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:18:57.719227 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1470 23:18:57.722645 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:18:57.725832 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:18:57.732300 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:18:57.735668 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:18:57.739052 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:18:57.745706 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 23:18:57.749266 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 23:18:57.752469 0 9 8 | B1->B0 | 2424 2727 | 0 0 | (0 0) (1 1)
1478 23:18:57.759130 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 23:18:57.762224 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 23:18:57.765780 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 23:18:57.768990 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 23:18:57.775873 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 23:18:57.779025 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 23:18:57.782473 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1485 23:18:57.789067 0 10 8 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (0 0)
1486 23:18:57.792277 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1487 23:18:57.795872 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:18:57.802228 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:18:57.805814 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 23:18:57.809247 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:18:57.815806 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 23:18:57.818901 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 23:18:57.822599 0 11 8 | B1->B0 | 3434 3737 | 1 0 | (0 0) (0 0)
1494 23:18:57.829084 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:18:57.832551 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:18:57.835730 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 23:18:57.842202 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 23:18:57.845826 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 23:18:57.849075 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 23:18:57.855721 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 23:18:57.858822 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1502 23:18:57.862299 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:18:57.865450 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:18:57.872475 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:18:57.875783 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:18:57.878866 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:18:57.885793 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:18:57.888971 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:18:57.892087 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:18:57.898784 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:18:57.902080 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:18:57.905553 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:18:57.912447 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:18:57.915526 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 23:18:57.918929 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 23:18:57.925674 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 23:18:57.928850 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 23:18:57.932227 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 23:18:57.935513 Total UI for P1: 0, mck2ui 16
1520 23:18:57.938872 best dqsien dly found for B0: ( 0, 14, 8)
1521 23:18:57.942021 Total UI for P1: 0, mck2ui 16
1522 23:18:57.945373 best dqsien dly found for B1: ( 0, 14, 8)
1523 23:18:57.948722 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1524 23:18:57.952006 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1525 23:18:57.952119
1526 23:18:57.955544 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1527 23:18:57.962409 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1528 23:18:57.962527 [Gating] SW calibration Done
1529 23:18:57.962596 ==
1530 23:18:57.965653 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 23:18:57.971933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 23:18:57.972059 ==
1533 23:18:57.972156 RX Vref Scan: 0
1534 23:18:57.972247
1535 23:18:57.975364 RX Vref 0 -> 0, step: 1
1536 23:18:57.975465
1537 23:18:57.978843 RX Delay -130 -> 252, step: 16
1538 23:18:57.982245 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1539 23:18:57.985327 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1540 23:18:57.988759 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1541 23:18:57.995436 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1542 23:18:57.998970 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1543 23:18:58.002107 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1544 23:18:58.005658 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1545 23:18:58.009036 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1546 23:18:58.012207 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1547 23:18:58.018905 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1548 23:18:58.022257 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1549 23:18:58.025681 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1550 23:18:58.028704 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1551 23:18:58.035753 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1552 23:18:58.038900 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1553 23:18:58.042080 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1554 23:18:58.042174 ==
1555 23:18:58.045485 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 23:18:58.048730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 23:18:58.048810 ==
1558 23:18:58.052171 DQS Delay:
1559 23:18:58.052276 DQS0 = 0, DQS1 = 0
1560 23:18:58.055660 DQM Delay:
1561 23:18:58.055746 DQM0 = 81, DQM1 = 70
1562 23:18:58.055811 DQ Delay:
1563 23:18:58.058765 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1564 23:18:58.062134 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1565 23:18:58.065723 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1566 23:18:58.068893 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1567 23:18:58.069002
1568 23:18:58.069097
1569 23:18:58.069186 ==
1570 23:18:58.072255 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 23:18:58.078847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 23:18:58.078992 ==
1573 23:18:58.079090
1574 23:18:58.079183
1575 23:18:58.079272 TX Vref Scan disable
1576 23:18:58.082587 == TX Byte 0 ==
1577 23:18:58.086035 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1578 23:18:58.089599 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1579 23:18:58.092686 == TX Byte 1 ==
1580 23:18:58.096077 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1581 23:18:58.099175 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1582 23:18:58.102697 ==
1583 23:18:58.105853 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 23:18:58.109214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 23:18:58.109293 ==
1586 23:18:58.121674 TX Vref=22, minBit 1, minWin=26, winSum=438
1587 23:18:58.124864 TX Vref=24, minBit 1, minWin=27, winSum=440
1588 23:18:58.128300 TX Vref=26, minBit 0, minWin=27, winSum=443
1589 23:18:58.131529 TX Vref=28, minBit 5, minWin=27, winSum=446
1590 23:18:58.134862 TX Vref=30, minBit 0, minWin=27, winSum=447
1591 23:18:58.141437 TX Vref=32, minBit 0, minWin=27, winSum=446
1592 23:18:58.144852 [TxChooseVref] Worse bit 0, Min win 27, Win sum 447, Final Vref 30
1593 23:18:58.144959
1594 23:18:58.148273 Final TX Range 1 Vref 30
1595 23:18:58.148349
1596 23:18:58.148416 ==
1597 23:18:58.151774 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 23:18:58.155382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 23:18:58.155464 ==
1600 23:18:58.155531
1601 23:18:58.155591
1602 23:18:58.158446 TX Vref Scan disable
1603 23:18:58.162021 == TX Byte 0 ==
1604 23:18:58.165366 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1605 23:18:58.168701 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1606 23:18:58.171909 == TX Byte 1 ==
1607 23:18:58.175347 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1608 23:18:58.178472 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1609 23:18:58.178556
1610 23:18:58.181970 [DATLAT]
1611 23:18:58.182058 Freq=800, CH1 RK0
1612 23:18:58.182125
1613 23:18:58.185183 DATLAT Default: 0xa
1614 23:18:58.185287 0, 0xFFFF, sum = 0
1615 23:18:58.188641 1, 0xFFFF, sum = 0
1616 23:18:58.188719 2, 0xFFFF, sum = 0
1617 23:18:58.191907 3, 0xFFFF, sum = 0
1618 23:18:58.192012 4, 0xFFFF, sum = 0
1619 23:18:58.195333 5, 0xFFFF, sum = 0
1620 23:18:58.195418 6, 0xFFFF, sum = 0
1621 23:18:58.198504 7, 0xFFFF, sum = 0
1622 23:18:58.198582 8, 0xFFFF, sum = 0
1623 23:18:58.201888 9, 0x0, sum = 1
1624 23:18:58.201994 10, 0x0, sum = 2
1625 23:18:58.205218 11, 0x0, sum = 3
1626 23:18:58.205295 12, 0x0, sum = 4
1627 23:18:58.208332 best_step = 10
1628 23:18:58.208414
1629 23:18:58.208479 ==
1630 23:18:58.211851 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 23:18:58.215036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 23:18:58.215110 ==
1633 23:18:58.218543 RX Vref Scan: 1
1634 23:18:58.218614
1635 23:18:58.218674 Set Vref Range= 32 -> 127
1636 23:18:58.218732
1637 23:18:58.221672 RX Vref 32 -> 127, step: 1
1638 23:18:58.221742
1639 23:18:58.225126 RX Delay -111 -> 252, step: 8
1640 23:18:58.225194
1641 23:18:58.228359 Set Vref, RX VrefLevel [Byte0]: 32
1642 23:18:58.231801 [Byte1]: 32
1643 23:18:58.231873
1644 23:18:58.235329 Set Vref, RX VrefLevel [Byte0]: 33
1645 23:18:58.238294 [Byte1]: 33
1646 23:18:58.241939
1647 23:18:58.242010 Set Vref, RX VrefLevel [Byte0]: 34
1648 23:18:58.245273 [Byte1]: 34
1649 23:18:58.249673
1650 23:18:58.249756 Set Vref, RX VrefLevel [Byte0]: 35
1651 23:18:58.252877 [Byte1]: 35
1652 23:18:58.257268
1653 23:18:58.257348 Set Vref, RX VrefLevel [Byte0]: 36
1654 23:18:58.260668 [Byte1]: 36
1655 23:18:58.264801
1656 23:18:58.264920 Set Vref, RX VrefLevel [Byte0]: 37
1657 23:18:58.268204 [Byte1]: 37
1658 23:18:58.272402
1659 23:18:58.272486 Set Vref, RX VrefLevel [Byte0]: 38
1660 23:18:58.275749 [Byte1]: 38
1661 23:18:58.280101
1662 23:18:58.280211 Set Vref, RX VrefLevel [Byte0]: 39
1663 23:18:58.283602 [Byte1]: 39
1664 23:18:58.287850
1665 23:18:58.287944 Set Vref, RX VrefLevel [Byte0]: 40
1666 23:18:58.291035 [Byte1]: 40
1667 23:18:58.295631
1668 23:18:58.295710 Set Vref, RX VrefLevel [Byte0]: 41
1669 23:18:58.298967 [Byte1]: 41
1670 23:18:58.303136
1671 23:18:58.303216 Set Vref, RX VrefLevel [Byte0]: 42
1672 23:18:58.306380 [Byte1]: 42
1673 23:18:58.310606
1674 23:18:58.310680 Set Vref, RX VrefLevel [Byte0]: 43
1675 23:18:58.314175 [Byte1]: 43
1676 23:18:58.318318
1677 23:18:58.318396 Set Vref, RX VrefLevel [Byte0]: 44
1678 23:18:58.321722 [Byte1]: 44
1679 23:18:58.326064
1680 23:18:58.326135 Set Vref, RX VrefLevel [Byte0]: 45
1681 23:18:58.329599 [Byte1]: 45
1682 23:18:58.333588
1683 23:18:58.333669 Set Vref, RX VrefLevel [Byte0]: 46
1684 23:18:58.337042 [Byte1]: 46
1685 23:18:58.341295
1686 23:18:58.341409 Set Vref, RX VrefLevel [Byte0]: 47
1687 23:18:58.344490 [Byte1]: 47
1688 23:18:58.348949
1689 23:18:58.349029 Set Vref, RX VrefLevel [Byte0]: 48
1690 23:18:58.352180 [Byte1]: 48
1691 23:18:58.356721
1692 23:18:58.356794 Set Vref, RX VrefLevel [Byte0]: 49
1693 23:18:58.359970 [Byte1]: 49
1694 23:18:58.364237
1695 23:18:58.364346 Set Vref, RX VrefLevel [Byte0]: 50
1696 23:18:58.367644 [Byte1]: 50
1697 23:18:58.371754
1698 23:18:58.371859 Set Vref, RX VrefLevel [Byte0]: 51
1699 23:18:58.375459 [Byte1]: 51
1700 23:18:58.379676
1701 23:18:58.379777 Set Vref, RX VrefLevel [Byte0]: 52
1702 23:18:58.382769 [Byte1]: 52
1703 23:18:58.387355
1704 23:18:58.387432 Set Vref, RX VrefLevel [Byte0]: 53
1705 23:18:58.390599 [Byte1]: 53
1706 23:18:58.394784
1707 23:18:58.394865 Set Vref, RX VrefLevel [Byte0]: 54
1708 23:18:58.398239 [Byte1]: 54
1709 23:18:58.402666
1710 23:18:58.402766 Set Vref, RX VrefLevel [Byte0]: 55
1711 23:18:58.405798 [Byte1]: 55
1712 23:18:58.410300
1713 23:18:58.410374 Set Vref, RX VrefLevel [Byte0]: 56
1714 23:18:58.413360 [Byte1]: 56
1715 23:18:58.417800
1716 23:18:58.417882 Set Vref, RX VrefLevel [Byte0]: 57
1717 23:18:58.421129 [Byte1]: 57
1718 23:18:58.425358
1719 23:18:58.425444 Set Vref, RX VrefLevel [Byte0]: 58
1720 23:18:58.428922 [Byte1]: 58
1721 23:18:58.433067
1722 23:18:58.433172 Set Vref, RX VrefLevel [Byte0]: 59
1723 23:18:58.436480 [Byte1]: 59
1724 23:18:58.440703
1725 23:18:58.440777 Set Vref, RX VrefLevel [Byte0]: 60
1726 23:18:58.443934 [Byte1]: 60
1727 23:18:58.450718
1728 23:18:58.450805 Set Vref, RX VrefLevel [Byte0]: 61
1729 23:18:58.451660 [Byte1]: 61
1730 23:18:58.455926
1731 23:18:58.456035 Set Vref, RX VrefLevel [Byte0]: 62
1732 23:18:58.459365 [Byte1]: 62
1733 23:18:58.463730
1734 23:18:58.463841 Set Vref, RX VrefLevel [Byte0]: 63
1735 23:18:58.467204 [Byte1]: 63
1736 23:18:58.471373
1737 23:18:58.471528 Set Vref, RX VrefLevel [Byte0]: 64
1738 23:18:58.474567 [Byte1]: 64
1739 23:18:58.478972
1740 23:18:58.479081 Set Vref, RX VrefLevel [Byte0]: 65
1741 23:18:58.482303 [Byte1]: 65
1742 23:18:58.486543
1743 23:18:58.486625 Set Vref, RX VrefLevel [Byte0]: 66
1744 23:18:58.489962 [Byte1]: 66
1745 23:18:58.494172
1746 23:18:58.494251 Set Vref, RX VrefLevel [Byte0]: 67
1747 23:18:58.497605 [Byte1]: 67
1748 23:18:58.501899
1749 23:18:58.501977 Set Vref, RX VrefLevel [Byte0]: 68
1750 23:18:58.505154 [Byte1]: 68
1751 23:18:58.509613
1752 23:18:58.509698 Set Vref, RX VrefLevel [Byte0]: 69
1753 23:18:58.512708 [Byte1]: 69
1754 23:18:58.517225
1755 23:18:58.517307 Set Vref, RX VrefLevel [Byte0]: 70
1756 23:18:58.520387 [Byte1]: 70
1757 23:18:58.525078
1758 23:18:58.525180 Set Vref, RX VrefLevel [Byte0]: 71
1759 23:18:58.528145 [Byte1]: 71
1760 23:18:58.532424
1761 23:18:58.532503 Set Vref, RX VrefLevel [Byte0]: 72
1762 23:18:58.536050 [Byte1]: 72
1763 23:18:58.540311
1764 23:18:58.540395 Set Vref, RX VrefLevel [Byte0]: 73
1765 23:18:58.543548 [Byte1]: 73
1766 23:18:58.547731
1767 23:18:58.547833 Set Vref, RX VrefLevel [Byte0]: 74
1768 23:18:58.551249 [Byte1]: 74
1769 23:18:58.555550
1770 23:18:58.555641 Set Vref, RX VrefLevel [Byte0]: 75
1771 23:18:58.558663 [Byte1]: 75
1772 23:18:58.563248
1773 23:18:58.563376 Set Vref, RX VrefLevel [Byte0]: 76
1774 23:18:58.566524 [Byte1]: 76
1775 23:18:58.570745
1776 23:18:58.570862 Final RX Vref Byte 0 = 55 to rank0
1777 23:18:58.574233 Final RX Vref Byte 1 = 56 to rank0
1778 23:18:58.577361 Final RX Vref Byte 0 = 55 to rank1
1779 23:18:58.580852 Final RX Vref Byte 1 = 56 to rank1==
1780 23:18:58.584189 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 23:18:58.590706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 23:18:58.590827 ==
1783 23:18:58.590924 DQS Delay:
1784 23:18:58.591012 DQS0 = 0, DQS1 = 0
1785 23:18:58.593933 DQM Delay:
1786 23:18:58.594031 DQM0 = 81, DQM1 = 71
1787 23:18:58.597574 DQ Delay:
1788 23:18:58.600503 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1789 23:18:58.603772 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1790 23:18:58.603903 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1791 23:18:58.610749 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1792 23:18:58.610836
1793 23:18:58.610904
1794 23:18:58.617240 [DQSOSCAuto] RK0, (LSB)MR18= 0x141e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1795 23:18:58.620797 CH1 RK0: MR19=606, MR18=141E
1796 23:18:58.627420 CH1_RK0: MR19=0x606, MR18=0x141E, DQSOSC=402, MR23=63, INC=91, DEC=60
1797 23:18:58.627538
1798 23:18:58.630554 ----->DramcWriteLeveling(PI) begin...
1799 23:18:58.630654 ==
1800 23:18:58.634051 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 23:18:58.637579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 23:18:58.637692 ==
1803 23:18:58.640565 Write leveling (Byte 0): 28 => 28
1804 23:18:58.644089 Write leveling (Byte 1): 27 => 27
1805 23:18:58.647282 DramcWriteLeveling(PI) end<-----
1806 23:18:58.647364
1807 23:18:58.647428 ==
1808 23:18:58.650870 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 23:18:58.654089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 23:18:58.654175 ==
1811 23:18:58.657336 [Gating] SW mode calibration
1812 23:18:58.664168 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 23:18:58.670457 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 23:18:58.673968 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1815 23:18:58.677233 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1816 23:18:58.684050 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1817 23:18:58.687417 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:18:58.690499 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:18:58.697332 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:18:58.700931 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:18:58.704058 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:18:58.710431 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:18:58.713786 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:18:58.717183 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:18:58.724022 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:18:58.727065 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:18:58.730622 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:18:58.737367 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:18:58.740516 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:18:58.743717 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1831 23:18:58.747161 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1832 23:18:58.753925 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:18:58.757282 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:18:58.760640 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:18:58.767331 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:18:58.770822 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:18:58.773917 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:18:58.780488 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:18:58.783867 0 9 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1840 23:18:58.787304 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
1841 23:18:58.793830 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 23:18:58.797181 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 23:18:58.800622 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 23:18:58.807140 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 23:18:58.810607 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 23:18:58.813785 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 23:18:58.820664 0 10 4 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
1848 23:18:58.823833 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1849 23:18:58.827360 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:18:58.830682 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:18:58.837611 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:18:58.840702 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:18:58.844202 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:18:58.850826 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1855 23:18:58.854003 0 11 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (0 0)
1856 23:18:58.857401 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1857 23:18:58.863992 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 23:18:58.867414 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 23:18:58.870474 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 23:18:58.877321 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 23:18:58.880534 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 23:18:58.884000 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 23:18:58.890525 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1864 23:18:58.893984 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1865 23:18:58.897364 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 23:18:58.903798 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 23:18:58.907258 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 23:18:58.910766 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 23:18:58.917289 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 23:18:58.920511 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 23:18:58.924034 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 23:18:58.930762 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 23:18:58.934112 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 23:18:58.937376 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:18:58.940620 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:18:58.947565 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:18:58.950552 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 23:18:58.954039 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 23:18:58.960800 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1880 23:18:58.964138 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 23:18:58.967349 Total UI for P1: 0, mck2ui 16
1882 23:18:58.970621 best dqsien dly found for B0: ( 0, 14, 4)
1883 23:18:58.973946 Total UI for P1: 0, mck2ui 16
1884 23:18:58.977293 best dqsien dly found for B1: ( 0, 14, 6)
1885 23:18:58.980688 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1886 23:18:58.984021 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1887 23:18:58.984142
1888 23:18:58.987291 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1889 23:18:58.990745 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1890 23:18:58.993879 [Gating] SW calibration Done
1891 23:18:58.994004 ==
1892 23:18:58.997454 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 23:18:59.000601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 23:18:59.000711 ==
1895 23:18:59.003939 RX Vref Scan: 0
1896 23:18:59.004068
1897 23:18:59.007670 RX Vref 0 -> 0, step: 1
1898 23:18:59.007777
1899 23:18:59.007878 RX Delay -130 -> 252, step: 16
1900 23:18:59.014038 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1901 23:18:59.017452 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1902 23:18:59.020847 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1903 23:18:59.023834 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1904 23:18:59.027329 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1905 23:18:59.033991 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1906 23:18:59.037190 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1907 23:18:59.040712 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1908 23:18:59.044028 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1909 23:18:59.047303 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1910 23:18:59.054095 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1911 23:18:59.057462 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1912 23:18:59.060600 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1913 23:18:59.063967 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1914 23:18:59.067236 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1915 23:18:59.073956 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1916 23:18:59.074134 ==
1917 23:18:59.077538 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 23:18:59.080776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 23:18:59.080863 ==
1920 23:18:59.080928 DQS Delay:
1921 23:18:59.083989 DQS0 = 0, DQS1 = 0
1922 23:18:59.084089 DQM Delay:
1923 23:18:59.087248 DQM0 = 78, DQM1 = 72
1924 23:18:59.087347 DQ Delay:
1925 23:18:59.090800 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =77
1926 23:18:59.094250 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1927 23:18:59.097365 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1928 23:18:59.100832 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1929 23:18:59.100928
1930 23:18:59.100994
1931 23:18:59.101053 ==
1932 23:18:59.104244 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 23:18:59.107356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 23:18:59.107478 ==
1935 23:18:59.110773
1936 23:18:59.110889
1937 23:18:59.110983 TX Vref Scan disable
1938 23:18:59.113997 == TX Byte 0 ==
1939 23:18:59.117336 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1940 23:18:59.120812 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1941 23:18:59.123947 == TX Byte 1 ==
1942 23:18:59.127221 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1943 23:18:59.130804 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1944 23:18:59.130927 ==
1945 23:18:59.134007 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 23:18:59.140545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 23:18:59.140773 ==
1948 23:18:59.152348 TX Vref=22, minBit 0, minWin=27, winSum=449
1949 23:18:59.155808 TX Vref=24, minBit 3, minWin=27, winSum=451
1950 23:18:59.159128 TX Vref=26, minBit 0, minWin=28, winSum=456
1951 23:18:59.162628 TX Vref=28, minBit 1, minWin=27, winSum=456
1952 23:18:59.165692 TX Vref=30, minBit 1, minWin=27, winSum=456
1953 23:18:59.169079 TX Vref=32, minBit 1, minWin=27, winSum=456
1954 23:18:59.175793 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 26
1955 23:18:59.175930
1956 23:18:59.179185 Final TX Range 1 Vref 26
1957 23:18:59.179274
1958 23:18:59.179340 ==
1959 23:18:59.182473 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 23:18:59.186089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 23:18:59.186185 ==
1962 23:18:59.186252
1963 23:18:59.189081
1964 23:18:59.189156 TX Vref Scan disable
1965 23:18:59.192628 == TX Byte 0 ==
1966 23:18:59.195928 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1967 23:18:59.199279 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1968 23:18:59.202573 == TX Byte 1 ==
1969 23:18:59.205938 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1970 23:18:59.209085 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1971 23:18:59.212736
1972 23:18:59.212815 [DATLAT]
1973 23:18:59.212880 Freq=800, CH1 RK1
1974 23:18:59.212945
1975 23:18:59.215878 DATLAT Default: 0xa
1976 23:18:59.215952 0, 0xFFFF, sum = 0
1977 23:18:59.219270 1, 0xFFFF, sum = 0
1978 23:18:59.219347 2, 0xFFFF, sum = 0
1979 23:18:59.222619 3, 0xFFFF, sum = 0
1980 23:18:59.222727 4, 0xFFFF, sum = 0
1981 23:18:59.225853 5, 0xFFFF, sum = 0
1982 23:18:59.225936 6, 0xFFFF, sum = 0
1983 23:18:59.229183 7, 0xFFFF, sum = 0
1984 23:18:59.229297 8, 0xFFFF, sum = 0
1985 23:18:59.232741 9, 0x0, sum = 1
1986 23:18:59.232823 10, 0x0, sum = 2
1987 23:18:59.235874 11, 0x0, sum = 3
1988 23:18:59.235953 12, 0x0, sum = 4
1989 23:18:59.239251 best_step = 10
1990 23:18:59.239337
1991 23:18:59.239428 ==
1992 23:18:59.242769 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 23:18:59.245902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 23:18:59.246017 ==
1995 23:18:59.249190 RX Vref Scan: 0
1996 23:18:59.249270
1997 23:18:59.249335 RX Vref 0 -> 0, step: 1
1998 23:18:59.249394
1999 23:18:59.252322 RX Delay -111 -> 252, step: 8
2000 23:18:59.259226 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2001 23:18:59.262558 iDelay=209, Bit 1, Center 68 (-55 ~ 192) 248
2002 23:18:59.265691 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2003 23:18:59.269167 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2004 23:18:59.272630 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2005 23:18:59.279101 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2006 23:18:59.282695 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2007 23:18:59.286073 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2008 23:18:59.289335 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2009 23:18:59.292754 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2010 23:18:59.299326 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2011 23:18:59.302628 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2012 23:18:59.305840 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2013 23:18:59.309158 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2014 23:18:59.312433 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2015 23:18:59.319239 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2016 23:18:59.319382 ==
2017 23:18:59.322739 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 23:18:59.325772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 23:18:59.325883 ==
2020 23:18:59.325978 DQS Delay:
2021 23:18:59.329585 DQS0 = 0, DQS1 = 0
2022 23:18:59.329693 DQM Delay:
2023 23:18:59.332644 DQM0 = 76, DQM1 = 74
2024 23:18:59.332751 DQ Delay:
2025 23:18:59.336016 DQ0 =80, DQ1 =68, DQ2 =64, DQ3 =72
2026 23:18:59.339521 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2027 23:18:59.342620 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
2028 23:18:59.346196 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2029 23:18:59.346305
2030 23:18:59.346398
2031 23:18:59.352711 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2032 23:18:59.356199 CH1 RK1: MR19=606, MR18=1E36
2033 23:18:59.362470 CH1_RK1: MR19=0x606, MR18=0x1E36, DQSOSC=396, MR23=63, INC=94, DEC=62
2034 23:18:59.365876 [RxdqsGatingPostProcess] freq 800
2035 23:18:59.372620 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2036 23:18:59.375922 Pre-setting of DQS Precalculation
2037 23:18:59.379037 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2038 23:18:59.385855 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2039 23:18:59.392333 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2040 23:18:59.392450
2041 23:18:59.392525
2042 23:18:59.395731 [Calibration Summary] 1600 Mbps
2043 23:18:59.399324 CH 0, Rank 0
2044 23:18:59.399436 SW Impedance : PASS
2045 23:18:59.402343 DUTY Scan : NO K
2046 23:18:59.405697 ZQ Calibration : PASS
2047 23:18:59.405787 Jitter Meter : NO K
2048 23:18:59.409316 CBT Training : PASS
2049 23:18:59.412522 Write leveling : PASS
2050 23:18:59.412614 RX DQS gating : PASS
2051 23:18:59.415597 RX DQ/DQS(RDDQC) : PASS
2052 23:18:59.419219 TX DQ/DQS : PASS
2053 23:18:59.419306 RX DATLAT : PASS
2054 23:18:59.422340 RX DQ/DQS(Engine): PASS
2055 23:18:59.422423 TX OE : NO K
2056 23:18:59.425598 All Pass.
2057 23:18:59.425676
2058 23:18:59.425739 CH 0, Rank 1
2059 23:18:59.429170 SW Impedance : PASS
2060 23:18:59.429285 DUTY Scan : NO K
2061 23:18:59.432453 ZQ Calibration : PASS
2062 23:18:59.435935 Jitter Meter : NO K
2063 23:18:59.436056 CBT Training : PASS
2064 23:18:59.439005 Write leveling : PASS
2065 23:18:59.442586 RX DQS gating : PASS
2066 23:18:59.442684 RX DQ/DQS(RDDQC) : PASS
2067 23:18:59.445634 TX DQ/DQS : PASS
2068 23:18:59.449108 RX DATLAT : PASS
2069 23:18:59.449196 RX DQ/DQS(Engine): PASS
2070 23:18:59.452312 TX OE : NO K
2071 23:18:59.452414 All Pass.
2072 23:18:59.452505
2073 23:18:59.455836 CH 1, Rank 0
2074 23:18:59.455936 SW Impedance : PASS
2075 23:18:59.458977 DUTY Scan : NO K
2076 23:18:59.462545 ZQ Calibration : PASS
2077 23:18:59.462653 Jitter Meter : NO K
2078 23:18:59.465583 CBT Training : PASS
2079 23:18:59.469184 Write leveling : PASS
2080 23:18:59.469299 RX DQS gating : PASS
2081 23:18:59.472243 RX DQ/DQS(RDDQC) : PASS
2082 23:18:59.472348 TX DQ/DQS : PASS
2083 23:18:59.475538 RX DATLAT : PASS
2084 23:18:59.479066 RX DQ/DQS(Engine): PASS
2085 23:18:59.479179 TX OE : NO K
2086 23:18:59.482616 All Pass.
2087 23:18:59.482700
2088 23:18:59.482764 CH 1, Rank 1
2089 23:18:59.485657 SW Impedance : PASS
2090 23:18:59.485762 DUTY Scan : NO K
2091 23:18:59.489195 ZQ Calibration : PASS
2092 23:18:59.492323 Jitter Meter : NO K
2093 23:18:59.492435 CBT Training : PASS
2094 23:18:59.495873 Write leveling : PASS
2095 23:18:59.499053 RX DQS gating : PASS
2096 23:18:59.499137 RX DQ/DQS(RDDQC) : PASS
2097 23:18:59.502569 TX DQ/DQS : PASS
2098 23:18:59.505582 RX DATLAT : PASS
2099 23:18:59.505677 RX DQ/DQS(Engine): PASS
2100 23:18:59.508872 TX OE : NO K
2101 23:18:59.508983 All Pass.
2102 23:18:59.509074
2103 23:18:59.512554 DramC Write-DBI off
2104 23:18:59.515600 PER_BANK_REFRESH: Hybrid Mode
2105 23:18:59.515711 TX_TRACKING: ON
2106 23:18:59.518972 [GetDramInforAfterCalByMRR] Vendor 6.
2107 23:18:59.522467 [GetDramInforAfterCalByMRR] Revision 606.
2108 23:18:59.525921 [GetDramInforAfterCalByMRR] Revision 2 0.
2109 23:18:59.526041 MR0 0x3b3b
2110 23:18:59.529376 MR8 0x5151
2111 23:18:59.532625 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 23:18:59.532738
2113 23:18:59.532832 MR0 0x3b3b
2114 23:18:59.535689 MR8 0x5151
2115 23:18:59.539052 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 23:18:59.539161
2117 23:18:59.545764 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2118 23:18:59.549304 [FAST_K] Save calibration result to emmc
2119 23:18:59.555698 [FAST_K] Save calibration result to emmc
2120 23:18:59.555848 dram_init: config_dvfs: 1
2121 23:18:59.559253 dramc_set_vcore_voltage set vcore to 662500
2122 23:18:59.562651 Read voltage for 1200, 2
2123 23:18:59.562748 Vio18 = 0
2124 23:18:59.566049 Vcore = 662500
2125 23:18:59.566150 Vdram = 0
2126 23:18:59.566217 Vddq = 0
2127 23:18:59.569169 Vmddr = 0
2128 23:18:59.572631 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2129 23:18:59.579085 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2130 23:18:59.579222 MEM_TYPE=3, freq_sel=15
2131 23:18:59.582634 sv_algorithm_assistance_LP4_1600
2132 23:18:59.589142 ============ PULL DRAM RESETB DOWN ============
2133 23:18:59.592380 ========== PULL DRAM RESETB DOWN end =========
2134 23:18:59.595834 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 23:18:59.599213 ===================================
2136 23:18:59.602623 LPDDR4 DRAM CONFIGURATION
2137 23:18:59.605703 ===================================
2138 23:18:59.605827 EX_ROW_EN[0] = 0x0
2139 23:18:59.609032 EX_ROW_EN[1] = 0x0
2140 23:18:59.612580 LP4Y_EN = 0x0
2141 23:18:59.612696 WORK_FSP = 0x0
2142 23:18:59.615695 WL = 0x4
2143 23:18:59.615800 RL = 0x4
2144 23:18:59.619169 BL = 0x2
2145 23:18:59.619262 RPST = 0x0
2146 23:18:59.622332 RD_PRE = 0x0
2147 23:18:59.622412 WR_PRE = 0x1
2148 23:18:59.625558 WR_PST = 0x0
2149 23:18:59.625660 DBI_WR = 0x0
2150 23:18:59.629132 DBI_RD = 0x0
2151 23:18:59.629253 OTF = 0x1
2152 23:18:59.632597 ===================================
2153 23:18:59.635796 ===================================
2154 23:18:59.638957 ANA top config
2155 23:18:59.642411 ===================================
2156 23:18:59.642532 DLL_ASYNC_EN = 0
2157 23:18:59.645625 ALL_SLAVE_EN = 0
2158 23:18:59.649042 NEW_RANK_MODE = 1
2159 23:18:59.652516 DLL_IDLE_MODE = 1
2160 23:18:59.655793 LP45_APHY_COMB_EN = 1
2161 23:18:59.655909 TX_ODT_DIS = 1
2162 23:18:59.659106 NEW_8X_MODE = 1
2163 23:18:59.662394 ===================================
2164 23:18:59.665841 ===================================
2165 23:18:59.668875 data_rate = 2400
2166 23:18:59.672331 CKR = 1
2167 23:18:59.675468 DQ_P2S_RATIO = 8
2168 23:18:59.678870 ===================================
2169 23:18:59.678995 CA_P2S_RATIO = 8
2170 23:18:59.682170 DQ_CA_OPEN = 0
2171 23:18:59.685501 DQ_SEMI_OPEN = 0
2172 23:18:59.689022 CA_SEMI_OPEN = 0
2173 23:18:59.692087 CA_FULL_RATE = 0
2174 23:18:59.695476 DQ_CKDIV4_EN = 0
2175 23:18:59.695607 CA_CKDIV4_EN = 0
2176 23:18:59.699075 CA_PREDIV_EN = 0
2177 23:18:59.702434 PH8_DLY = 17
2178 23:18:59.705456 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2179 23:18:59.709010 DQ_AAMCK_DIV = 4
2180 23:18:59.712358 CA_AAMCK_DIV = 4
2181 23:18:59.712454 CA_ADMCK_DIV = 4
2182 23:18:59.715516 DQ_TRACK_CA_EN = 0
2183 23:18:59.718972 CA_PICK = 1200
2184 23:18:59.722181 CA_MCKIO = 1200
2185 23:18:59.725591 MCKIO_SEMI = 0
2186 23:18:59.728944 PLL_FREQ = 2366
2187 23:18:59.732341 DQ_UI_PI_RATIO = 32
2188 23:18:59.732461 CA_UI_PI_RATIO = 0
2189 23:18:59.735634 ===================================
2190 23:18:59.738934 ===================================
2191 23:18:59.742072 memory_type:LPDDR4
2192 23:18:59.745649 GP_NUM : 10
2193 23:18:59.745773 SRAM_EN : 1
2194 23:18:59.748880 MD32_EN : 0
2195 23:18:59.752336 ===================================
2196 23:18:59.755357 [ANA_INIT] >>>>>>>>>>>>>>
2197 23:18:59.758962 <<<<<< [CONFIGURE PHASE]: ANA_TX
2198 23:18:59.762012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2199 23:18:59.765576 ===================================
2200 23:18:59.765716 data_rate = 2400,PCW = 0X5b00
2201 23:18:59.768916 ===================================
2202 23:18:59.772014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2203 23:18:59.778834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 23:18:59.785611 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 23:18:59.788793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2206 23:18:59.792265 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2207 23:18:59.795351 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2208 23:18:59.798718 [ANA_INIT] flow start
2209 23:18:59.798854 [ANA_INIT] PLL >>>>>>>>
2210 23:18:59.802032 [ANA_INIT] PLL <<<<<<<<
2211 23:18:59.805341 [ANA_INIT] MIDPI >>>>>>>>
2212 23:18:59.808739 [ANA_INIT] MIDPI <<<<<<<<
2213 23:18:59.808866 [ANA_INIT] DLL >>>>>>>>
2214 23:18:59.812158 [ANA_INIT] DLL <<<<<<<<
2215 23:18:59.815331 [ANA_INIT] flow end
2216 23:18:59.818861 ============ LP4 DIFF to SE enter ============
2217 23:18:59.821877 ============ LP4 DIFF to SE exit ============
2218 23:18:59.825414 [ANA_INIT] <<<<<<<<<<<<<
2219 23:18:59.828623 [Flow] Enable top DCM control >>>>>
2220 23:18:59.831910 [Flow] Enable top DCM control <<<<<
2221 23:18:59.835354 Enable DLL master slave shuffle
2222 23:18:59.838868 ==============================================================
2223 23:18:59.842153 Gating Mode config
2224 23:18:59.845349 ==============================================================
2225 23:18:59.848913 Config description:
2226 23:18:59.858657 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2227 23:18:59.865451 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2228 23:18:59.868666 SELPH_MODE 0: By rank 1: By Phase
2229 23:18:59.875511 ==============================================================
2230 23:18:59.878606 GAT_TRACK_EN = 1
2231 23:18:59.881877 RX_GATING_MODE = 2
2232 23:18:59.885237 RX_GATING_TRACK_MODE = 2
2233 23:18:59.888455 SELPH_MODE = 1
2234 23:18:59.888578 PICG_EARLY_EN = 1
2235 23:18:59.891875 VALID_LAT_VALUE = 1
2236 23:18:59.898420 ==============================================================
2237 23:18:59.901998 Enter into Gating configuration >>>>
2238 23:18:59.905167 Exit from Gating configuration <<<<
2239 23:18:59.908654 Enter into DVFS_PRE_config >>>>>
2240 23:18:59.918419 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2241 23:18:59.921823 Exit from DVFS_PRE_config <<<<<
2242 23:18:59.925125 Enter into PICG configuration >>>>
2243 23:18:59.928686 Exit from PICG configuration <<<<
2244 23:18:59.931837 [RX_INPUT] configuration >>>>>
2245 23:18:59.934970 [RX_INPUT] configuration <<<<<
2246 23:18:59.938232 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2247 23:18:59.945216 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2248 23:18:59.951744 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 23:18:59.958267 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 23:18:59.964986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 23:18:59.971817 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 23:18:59.974956 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2253 23:18:59.978291 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2254 23:18:59.981489 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2255 23:18:59.984862 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2256 23:18:59.991501 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2257 23:18:59.994712 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 23:18:59.998079 ===================================
2259 23:19:00.001398 LPDDR4 DRAM CONFIGURATION
2260 23:19:00.004956 ===================================
2261 23:19:00.005074 EX_ROW_EN[0] = 0x0
2262 23:19:00.008105 EX_ROW_EN[1] = 0x0
2263 23:19:00.008217 LP4Y_EN = 0x0
2264 23:19:00.011680 WORK_FSP = 0x0
2265 23:19:00.011792 WL = 0x4
2266 23:19:00.014732 RL = 0x4
2267 23:19:00.014841 BL = 0x2
2268 23:19:00.018089 RPST = 0x0
2269 23:19:00.018197 RD_PRE = 0x0
2270 23:19:00.021612 WR_PRE = 0x1
2271 23:19:00.024731 WR_PST = 0x0
2272 23:19:00.024842 DBI_WR = 0x0
2273 23:19:00.028069 DBI_RD = 0x0
2274 23:19:00.028177 OTF = 0x1
2275 23:19:00.031392 ===================================
2276 23:19:00.034737 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2277 23:19:00.038202 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2278 23:19:00.044806 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 23:19:00.047922 ===================================
2280 23:19:00.051522 LPDDR4 DRAM CONFIGURATION
2281 23:19:00.054574 ===================================
2282 23:19:00.054689 EX_ROW_EN[0] = 0x10
2283 23:19:00.057962 EX_ROW_EN[1] = 0x0
2284 23:19:00.058071 LP4Y_EN = 0x0
2285 23:19:00.061265 WORK_FSP = 0x0
2286 23:19:00.061376 WL = 0x4
2287 23:19:00.064609 RL = 0x4
2288 23:19:00.064717 BL = 0x2
2289 23:19:00.068005 RPST = 0x0
2290 23:19:00.068120 RD_PRE = 0x0
2291 23:19:00.071329 WR_PRE = 0x1
2292 23:19:00.071437 WR_PST = 0x0
2293 23:19:00.074463 DBI_WR = 0x0
2294 23:19:00.074574 DBI_RD = 0x0
2295 23:19:00.077822 OTF = 0x1
2296 23:19:00.081159 ===================================
2297 23:19:00.087864 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2298 23:19:00.087992 ==
2299 23:19:00.091261 Dram Type= 6, Freq= 0, CH_0, rank 0
2300 23:19:00.094783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2301 23:19:00.094895 ==
2302 23:19:00.097780 [Duty_Offset_Calibration]
2303 23:19:00.097891 B0:2 B1:0 CA:3
2304 23:19:00.097986
2305 23:19:00.101270 [DutyScan_Calibration_Flow] k_type=0
2306 23:19:00.111983
2307 23:19:00.112114 ==CLK 0==
2308 23:19:00.115406 Final CLK duty delay cell = 0
2309 23:19:00.118334 [0] MAX Duty = 5031%(X100), DQS PI = 12
2310 23:19:00.121902 [0] MIN Duty = 4875%(X100), DQS PI = 58
2311 23:19:00.125226 [0] AVG Duty = 4953%(X100)
2312 23:19:00.125335
2313 23:19:00.128523 CH0 CLK Duty spec in!! Max-Min= 156%
2314 23:19:00.131950 [DutyScan_Calibration_Flow] ====Done====
2315 23:19:00.132064
2316 23:19:00.134914 [DutyScan_Calibration_Flow] k_type=1
2317 23:19:00.150402
2318 23:19:00.150562 ==DQS 0 ==
2319 23:19:00.153522 Final DQS duty delay cell = 0
2320 23:19:00.157089 [0] MAX Duty = 5062%(X100), DQS PI = 12
2321 23:19:00.160451 [0] MIN Duty = 4907%(X100), DQS PI = 46
2322 23:19:00.160573 [0] AVG Duty = 4984%(X100)
2323 23:19:00.163624
2324 23:19:00.163731 ==DQS 1 ==
2325 23:19:00.167191 Final DQS duty delay cell = -4
2326 23:19:00.170404 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2327 23:19:00.173515 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2328 23:19:00.177066 [-4] AVG Duty = 4937%(X100)
2329 23:19:00.177173
2330 23:19:00.180630 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2331 23:19:00.180729
2332 23:19:00.183721 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2333 23:19:00.187135 [DutyScan_Calibration_Flow] ====Done====
2334 23:19:00.187238
2335 23:19:00.190315 [DutyScan_Calibration_Flow] k_type=3
2336 23:19:00.208108
2337 23:19:00.208267 ==DQM 0 ==
2338 23:19:00.211409 Final DQM duty delay cell = 0
2339 23:19:00.214866 [0] MAX Duty = 5124%(X100), DQS PI = 30
2340 23:19:00.217891 [0] MIN Duty = 4876%(X100), DQS PI = 0
2341 23:19:00.217986 [0] AVG Duty = 5000%(X100)
2342 23:19:00.221345
2343 23:19:00.221453 ==DQM 1 ==
2344 23:19:00.224587 Final DQM duty delay cell = 4
2345 23:19:00.228018 [4] MAX Duty = 5124%(X100), DQS PI = 50
2346 23:19:00.231203 [4] MIN Duty = 5000%(X100), DQS PI = 14
2347 23:19:00.234565 [4] AVG Duty = 5062%(X100)
2348 23:19:00.234675
2349 23:19:00.238261 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2350 23:19:00.238344
2351 23:19:00.241329 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2352 23:19:00.244786 [DutyScan_Calibration_Flow] ====Done====
2353 23:19:00.244894
2354 23:19:00.247918 [DutyScan_Calibration_Flow] k_type=2
2355 23:19:00.262874
2356 23:19:00.263037 ==DQ 0 ==
2357 23:19:00.266271 Final DQ duty delay cell = -4
2358 23:19:00.269270 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2359 23:19:00.272663 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2360 23:19:00.275946 [-4] AVG Duty = 4969%(X100)
2361 23:19:00.276056
2362 23:19:00.276149 ==DQ 1 ==
2363 23:19:00.279576 Final DQ duty delay cell = -4
2364 23:19:00.282699 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2365 23:19:00.286243 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2366 23:19:00.289593 [-4] AVG Duty = 4938%(X100)
2367 23:19:00.289702
2368 23:19:00.292734 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2369 23:19:00.292840
2370 23:19:00.296220 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2371 23:19:00.299248 [DutyScan_Calibration_Flow] ====Done====
2372 23:19:00.299355 ==
2373 23:19:00.302627 Dram Type= 6, Freq= 0, CH_1, rank 0
2374 23:19:00.306260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 23:19:00.306381 ==
2376 23:19:00.309728 [Duty_Offset_Calibration]
2377 23:19:00.309833 B0:1 B1:-2 CA:0
2378 23:19:00.309925
2379 23:19:00.312773 [DutyScan_Calibration_Flow] k_type=0
2380 23:19:00.324247
2381 23:19:00.324395 ==CLK 0==
2382 23:19:00.327648 Final CLK duty delay cell = 4
2383 23:19:00.330911 [4] MAX Duty = 5156%(X100), DQS PI = 0
2384 23:19:00.333983 [4] MIN Duty = 5031%(X100), DQS PI = 26
2385 23:19:00.334090 [4] AVG Duty = 5093%(X100)
2386 23:19:00.337641
2387 23:19:00.340718 CH1 CLK Duty spec in!! Max-Min= 125%
2388 23:19:00.344022 [DutyScan_Calibration_Flow] ====Done====
2389 23:19:00.344131
2390 23:19:00.347204 [DutyScan_Calibration_Flow] k_type=1
2391 23:19:00.362706
2392 23:19:00.362843 ==DQS 0 ==
2393 23:19:00.366035 Final DQS duty delay cell = -4
2394 23:19:00.369158 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2395 23:19:00.372470 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2396 23:19:00.375972 [-4] AVG Duty = 4953%(X100)
2397 23:19:00.376063
2398 23:19:00.376126 ==DQS 1 ==
2399 23:19:00.379143 Final DQS duty delay cell = 0
2400 23:19:00.382491 [0] MAX Duty = 5093%(X100), DQS PI = 32
2401 23:19:00.385884 [0] MIN Duty = 4875%(X100), DQS PI = 10
2402 23:19:00.389043 [0] AVG Duty = 4984%(X100)
2403 23:19:00.389145
2404 23:19:00.392316 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2405 23:19:00.392429
2406 23:19:00.395637 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2407 23:19:00.399133 [DutyScan_Calibration_Flow] ====Done====
2408 23:19:00.399239
2409 23:19:00.402310 [DutyScan_Calibration_Flow] k_type=3
2410 23:19:00.419383
2411 23:19:00.419507 ==DQM 0 ==
2412 23:19:00.422525 Final DQM duty delay cell = 0
2413 23:19:00.425847 [0] MAX Duty = 5000%(X100), DQS PI = 54
2414 23:19:00.429353 [0] MIN Duty = 4876%(X100), DQS PI = 20
2415 23:19:00.432492 [0] AVG Duty = 4938%(X100)
2416 23:19:00.432614
2417 23:19:00.432711 ==DQM 1 ==
2418 23:19:00.435963 Final DQM duty delay cell = 0
2419 23:19:00.439300 [0] MAX Duty = 5031%(X100), DQS PI = 4
2420 23:19:00.442665 [0] MIN Duty = 4907%(X100), DQS PI = 10
2421 23:19:00.445717 [0] AVG Duty = 4969%(X100)
2422 23:19:00.445794
2423 23:19:00.449293 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2424 23:19:00.449393
2425 23:19:00.452507 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2426 23:19:00.455569 [DutyScan_Calibration_Flow] ====Done====
2427 23:19:00.455739
2428 23:19:00.458966 [DutyScan_Calibration_Flow] k_type=2
2429 23:19:00.475701
2430 23:19:00.475857 ==DQ 0 ==
2431 23:19:00.479036 Final DQ duty delay cell = 0
2432 23:19:00.482388 [0] MAX Duty = 5062%(X100), DQS PI = 0
2433 23:19:00.485860 [0] MIN Duty = 4938%(X100), DQS PI = 26
2434 23:19:00.485954 [0] AVG Duty = 5000%(X100)
2435 23:19:00.486017
2436 23:19:00.488891 ==DQ 1 ==
2437 23:19:00.492248 Final DQ duty delay cell = 0
2438 23:19:00.495658 [0] MAX Duty = 5125%(X100), DQS PI = 14
2439 23:19:00.498829 [0] MIN Duty = 4938%(X100), DQS PI = 58
2440 23:19:00.498910 [0] AVG Duty = 5031%(X100)
2441 23:19:00.498995
2442 23:19:00.502345 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2443 23:19:00.502435
2444 23:19:00.509006 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2445 23:19:00.512013 [DutyScan_Calibration_Flow] ====Done====
2446 23:19:00.515684 nWR fixed to 30
2447 23:19:00.515816 [ModeRegInit_LP4] CH0 RK0
2448 23:19:00.519002 [ModeRegInit_LP4] CH0 RK1
2449 23:19:00.522068 [ModeRegInit_LP4] CH1 RK0
2450 23:19:00.522149 [ModeRegInit_LP4] CH1 RK1
2451 23:19:00.525580 match AC timing 7
2452 23:19:00.528675 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2453 23:19:00.532210 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2454 23:19:00.538799 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2455 23:19:00.542523 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2456 23:19:00.548836 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2457 23:19:00.548952 ==
2458 23:19:00.552230 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 23:19:00.555793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 23:19:00.555894 ==
2461 23:19:00.562324 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2462 23:19:00.565785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2463 23:19:00.575723 [CA 0] Center 40 (10~71) winsize 62
2464 23:19:00.579135 [CA 1] Center 39 (9~70) winsize 62
2465 23:19:00.582331 [CA 2] Center 36 (6~66) winsize 61
2466 23:19:00.585874 [CA 3] Center 35 (5~66) winsize 62
2467 23:19:00.588917 [CA 4] Center 34 (4~65) winsize 62
2468 23:19:00.592324 [CA 5] Center 33 (3~64) winsize 62
2469 23:19:00.592425
2470 23:19:00.595386 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2471 23:19:00.595454
2472 23:19:00.598915 [CATrainingPosCal] consider 1 rank data
2473 23:19:00.602354 u2DelayCellTimex100 = 270/100 ps
2474 23:19:00.605407 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2475 23:19:00.612399 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2476 23:19:00.615671 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2477 23:19:00.618999 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2478 23:19:00.622300 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2479 23:19:00.625457 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2480 23:19:00.625588
2481 23:19:00.628877 CA PerBit enable=1, Macro0, CA PI delay=33
2482 23:19:00.628986
2483 23:19:00.632430 [CBTSetCACLKResult] CA Dly = 33
2484 23:19:00.632538 CS Dly: 7 (0~38)
2485 23:19:00.635480 ==
2486 23:19:00.635604 Dram Type= 6, Freq= 0, CH_0, rank 1
2487 23:19:00.642285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2488 23:19:00.642378 ==
2489 23:19:00.645465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2490 23:19:00.652188 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2491 23:19:00.661723 [CA 0] Center 40 (10~70) winsize 61
2492 23:19:00.665044 [CA 1] Center 39 (9~70) winsize 62
2493 23:19:00.668375 [CA 2] Center 35 (5~66) winsize 62
2494 23:19:00.671743 [CA 3] Center 35 (5~66) winsize 62
2495 23:19:00.674794 [CA 4] Center 34 (4~65) winsize 62
2496 23:19:00.678329 [CA 5] Center 33 (3~64) winsize 62
2497 23:19:00.678408
2498 23:19:00.681493 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2499 23:19:00.681568
2500 23:19:00.684923 [CATrainingPosCal] consider 2 rank data
2501 23:19:00.688019 u2DelayCellTimex100 = 270/100 ps
2502 23:19:00.691528 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2503 23:19:00.698269 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2504 23:19:00.701658 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2505 23:19:00.704719 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 23:19:00.708200 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2507 23:19:00.711638 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2508 23:19:00.711709
2509 23:19:00.714750 CA PerBit enable=1, Macro0, CA PI delay=33
2510 23:19:00.714819
2511 23:19:00.718180 [CBTSetCACLKResult] CA Dly = 33
2512 23:19:00.718255 CS Dly: 8 (0~40)
2513 23:19:00.721513
2514 23:19:00.725001 ----->DramcWriteLeveling(PI) begin...
2515 23:19:00.725081 ==
2516 23:19:00.728212 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 23:19:00.731312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 23:19:00.731382 ==
2519 23:19:00.734868 Write leveling (Byte 0): 35 => 35
2520 23:19:00.738140 Write leveling (Byte 1): 31 => 31
2521 23:19:00.741323 DramcWriteLeveling(PI) end<-----
2522 23:19:00.741397
2523 23:19:00.741459 ==
2524 23:19:00.744873 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 23:19:00.748149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 23:19:00.748221 ==
2527 23:19:00.751446 [Gating] SW mode calibration
2528 23:19:00.758168 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2529 23:19:00.764747 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2530 23:19:00.768139 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 23:19:00.771741 0 15 4 | B1->B0 | 2a2a 3434 | 1 0 | (1 1) (0 0)
2532 23:19:00.774854 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 23:19:00.781518 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 23:19:00.784935 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 23:19:00.787963 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 23:19:00.795041 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 23:19:00.798169 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 23:19:00.801303 1 0 0 | B1->B0 | 3333 2d2d | 1 1 | (1 1) (1 0)
2539 23:19:00.808135 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 23:19:00.811643 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 23:19:00.814993 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 23:19:00.821460 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 23:19:00.824634 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 23:19:00.827938 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 23:19:00.834600 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2546 23:19:00.838111 1 1 0 | B1->B0 | 2626 3232 | 1 0 | (0 0) (0 0)
2547 23:19:00.841187 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2548 23:19:00.847794 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 23:19:00.851240 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 23:19:00.854442 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 23:19:00.861295 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 23:19:00.864365 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 23:19:00.867830 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2554 23:19:00.874596 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2555 23:19:00.877713 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2556 23:19:00.881216 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 23:19:00.887692 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 23:19:00.891241 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 23:19:00.894640 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 23:19:00.901321 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 23:19:00.904476 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 23:19:00.907810 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 23:19:00.914677 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 23:19:00.917740 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 23:19:00.921201 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:19:00.924258 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:19:00.931220 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 23:19:00.934407 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 23:19:00.937910 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 23:19:00.944395 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2571 23:19:00.947490 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2572 23:19:00.950932 Total UI for P1: 0, mck2ui 16
2573 23:19:00.954359 best dqsien dly found for B0: ( 1, 4, 0)
2574 23:19:00.957782 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 23:19:00.961186 Total UI for P1: 0, mck2ui 16
2576 23:19:00.964274 best dqsien dly found for B1: ( 1, 4, 2)
2577 23:19:00.967625 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2578 23:19:00.970691 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2579 23:19:00.970833
2580 23:19:00.977319 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2581 23:19:00.980726 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2582 23:19:00.980869 [Gating] SW calibration Done
2583 23:19:00.984262 ==
2584 23:19:00.984370 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 23:19:00.990845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 23:19:00.990956 ==
2587 23:19:00.991050 RX Vref Scan: 0
2588 23:19:00.991137
2589 23:19:00.994255 RX Vref 0 -> 0, step: 1
2590 23:19:00.994356
2591 23:19:00.997516 RX Delay -40 -> 252, step: 8
2592 23:19:01.000913 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2593 23:19:01.004105 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2594 23:19:01.007614 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2595 23:19:01.014365 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2596 23:19:01.017621 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2597 23:19:01.020586 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2598 23:19:01.023981 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2599 23:19:01.027527 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2600 23:19:01.034195 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2601 23:19:01.037247 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2602 23:19:01.040527 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2603 23:19:01.044017 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2604 23:19:01.047154 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2605 23:19:01.053904 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2606 23:19:01.057444 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2607 23:19:01.060447 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2608 23:19:01.060557 ==
2609 23:19:01.063884 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 23:19:01.067411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 23:19:01.067526 ==
2612 23:19:01.070356 DQS Delay:
2613 23:19:01.070444 DQS0 = 0, DQS1 = 0
2614 23:19:01.073896 DQM Delay:
2615 23:19:01.073972 DQM0 = 112, DQM1 = 103
2616 23:19:01.074042 DQ Delay:
2617 23:19:01.076965 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2618 23:19:01.080496 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2619 23:19:01.087098 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2620 23:19:01.090680 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2621 23:19:01.090818
2622 23:19:01.090915
2623 23:19:01.091021 ==
2624 23:19:01.093734 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 23:19:01.097292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 23:19:01.097426 ==
2627 23:19:01.097527
2628 23:19:01.097590
2629 23:19:01.100609 TX Vref Scan disable
2630 23:19:01.100730 == TX Byte 0 ==
2631 23:19:01.107150 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2632 23:19:01.110586 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2633 23:19:01.110784 == TX Byte 1 ==
2634 23:19:01.116979 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2635 23:19:01.120506 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2636 23:19:01.120681 ==
2637 23:19:01.123763 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 23:19:01.127104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 23:19:01.127226 ==
2640 23:19:01.140420 TX Vref=22, minBit 0, minWin=25, winSum=414
2641 23:19:01.143801 TX Vref=24, minBit 1, minWin=25, winSum=422
2642 23:19:01.147116 TX Vref=26, minBit 7, minWin=25, winSum=424
2643 23:19:01.150261 TX Vref=28, minBit 2, minWin=26, winSum=429
2644 23:19:01.153566 TX Vref=30, minBit 5, minWin=26, winSum=429
2645 23:19:01.157003 TX Vref=32, minBit 1, minWin=26, winSum=428
2646 23:19:01.163434 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 28
2647 23:19:01.163569
2648 23:19:01.166891 Final TX Range 1 Vref 28
2649 23:19:01.166976
2650 23:19:01.167047 ==
2651 23:19:01.170309 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 23:19:01.173493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 23:19:01.173610 ==
2654 23:19:01.173705
2655 23:19:01.176905
2656 23:19:01.177009 TX Vref Scan disable
2657 23:19:01.180075 == TX Byte 0 ==
2658 23:19:01.183421 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2659 23:19:01.186900 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2660 23:19:01.206636 == TX Byte 1 ==
2661 23:19:01.206763 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2662 23:19:01.206833 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2663 23:19:01.206895
2664 23:19:01.206961 [DATLAT]
2665 23:19:01.207018 Freq=1200, CH0 RK0
2666 23:19:01.207075
2667 23:19:01.207129 DATLAT Default: 0xd
2668 23:19:01.207190 0, 0xFFFF, sum = 0
2669 23:19:01.207443 1, 0xFFFF, sum = 0
2670 23:19:01.207511 2, 0xFFFF, sum = 0
2671 23:19:01.210579 3, 0xFFFF, sum = 0
2672 23:19:01.210726 4, 0xFFFF, sum = 0
2673 23:19:01.214021 5, 0xFFFF, sum = 0
2674 23:19:01.214195 6, 0xFFFF, sum = 0
2675 23:19:01.217030 7, 0xFFFF, sum = 0
2676 23:19:01.217179 8, 0xFFFF, sum = 0
2677 23:19:01.220557 9, 0xFFFF, sum = 0
2678 23:19:01.220684 10, 0xFFFF, sum = 0
2679 23:19:01.223857 11, 0xFFFF, sum = 0
2680 23:19:01.223977 12, 0x0, sum = 1
2681 23:19:01.227169 13, 0x0, sum = 2
2682 23:19:01.227332 14, 0x0, sum = 3
2683 23:19:01.230436 15, 0x0, sum = 4
2684 23:19:01.230593 best_step = 13
2685 23:19:01.230716
2686 23:19:01.230845 ==
2687 23:19:01.233725 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 23:19:01.240316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 23:19:01.240489 ==
2690 23:19:01.240615 RX Vref Scan: 1
2691 23:19:01.240743
2692 23:19:01.243841 Set Vref Range= 32 -> 127
2693 23:19:01.243969
2694 23:19:01.247162 RX Vref 32 -> 127, step: 1
2695 23:19:01.247287
2696 23:19:01.250471 RX Delay -37 -> 252, step: 4
2697 23:19:01.250581
2698 23:19:01.253757 Set Vref, RX VrefLevel [Byte0]: 32
2699 23:19:01.256783 [Byte1]: 32
2700 23:19:01.256892
2701 23:19:01.260513 Set Vref, RX VrefLevel [Byte0]: 33
2702 23:19:01.263642 [Byte1]: 33
2703 23:19:01.263763
2704 23:19:01.267141 Set Vref, RX VrefLevel [Byte0]: 34
2705 23:19:01.270214 [Byte1]: 34
2706 23:19:01.274510
2707 23:19:01.274653 Set Vref, RX VrefLevel [Byte0]: 35
2708 23:19:01.277822 [Byte1]: 35
2709 23:19:01.282919
2710 23:19:01.283063 Set Vref, RX VrefLevel [Byte0]: 36
2711 23:19:01.286043 [Byte1]: 36
2712 23:19:01.290650
2713 23:19:01.290771 Set Vref, RX VrefLevel [Byte0]: 37
2714 23:19:01.293847 [Byte1]: 37
2715 23:19:01.298838
2716 23:19:01.299048 Set Vref, RX VrefLevel [Byte0]: 38
2717 23:19:01.301797 [Byte1]: 38
2718 23:19:01.306465
2719 23:19:01.309956 Set Vref, RX VrefLevel [Byte0]: 39
2720 23:19:01.310140 [Byte1]: 39
2721 23:19:01.314543
2722 23:19:01.314720 Set Vref, RX VrefLevel [Byte0]: 40
2723 23:19:01.318015 [Byte1]: 40
2724 23:19:01.322565
2725 23:19:01.322702 Set Vref, RX VrefLevel [Byte0]: 41
2726 23:19:01.326120 [Byte1]: 41
2727 23:19:01.330628
2728 23:19:01.330757 Set Vref, RX VrefLevel [Byte0]: 42
2729 23:19:01.334025 [Byte1]: 42
2730 23:19:01.338616
2731 23:19:01.338768 Set Vref, RX VrefLevel [Byte0]: 43
2732 23:19:01.341993 [Byte1]: 43
2733 23:19:01.346809
2734 23:19:01.346938 Set Vref, RX VrefLevel [Byte0]: 44
2735 23:19:01.350085 [Byte1]: 44
2736 23:19:01.354602
2737 23:19:01.354700 Set Vref, RX VrefLevel [Byte0]: 45
2738 23:19:01.357956 [Byte1]: 45
2739 23:19:01.362504
2740 23:19:01.362618 Set Vref, RX VrefLevel [Byte0]: 46
2741 23:19:01.365769 [Byte1]: 46
2742 23:19:01.370588
2743 23:19:01.370706 Set Vref, RX VrefLevel [Byte0]: 47
2744 23:19:01.373938 [Byte1]: 47
2745 23:19:01.378590
2746 23:19:01.378738 Set Vref, RX VrefLevel [Byte0]: 48
2747 23:19:01.381932 [Byte1]: 48
2748 23:19:01.386824
2749 23:19:01.386963 Set Vref, RX VrefLevel [Byte0]: 49
2750 23:19:01.389955 [Byte1]: 49
2751 23:19:01.394826
2752 23:19:01.394918 Set Vref, RX VrefLevel [Byte0]: 50
2753 23:19:01.397938 [Byte1]: 50
2754 23:19:01.402594
2755 23:19:01.402687 Set Vref, RX VrefLevel [Byte0]: 51
2756 23:19:01.405969 [Byte1]: 51
2757 23:19:01.410594
2758 23:19:01.410749 Set Vref, RX VrefLevel [Byte0]: 52
2759 23:19:01.414144 [Byte1]: 52
2760 23:19:01.418816
2761 23:19:01.419000 Set Vref, RX VrefLevel [Byte0]: 53
2762 23:19:01.422122 [Byte1]: 53
2763 23:19:01.426467
2764 23:19:01.426580 Set Vref, RX VrefLevel [Byte0]: 54
2765 23:19:01.429985 [Byte1]: 54
2766 23:19:01.434808
2767 23:19:01.434995 Set Vref, RX VrefLevel [Byte0]: 55
2768 23:19:01.437804 [Byte1]: 55
2769 23:19:01.442576
2770 23:19:01.442745 Set Vref, RX VrefLevel [Byte0]: 56
2771 23:19:01.445929 [Byte1]: 56
2772 23:19:01.450465
2773 23:19:01.450589 Set Vref, RX VrefLevel [Byte0]: 57
2774 23:19:01.454069 [Byte1]: 57
2775 23:19:01.458586
2776 23:19:01.458718 Set Vref, RX VrefLevel [Byte0]: 58
2777 23:19:01.462014 [Byte1]: 58
2778 23:19:01.466531
2779 23:19:01.466697 Set Vref, RX VrefLevel [Byte0]: 59
2780 23:19:01.469760 [Byte1]: 59
2781 23:19:01.474623
2782 23:19:01.474771 Set Vref, RX VrefLevel [Byte0]: 60
2783 23:19:01.477951 [Byte1]: 60
2784 23:19:01.482675
2785 23:19:01.482774 Set Vref, RX VrefLevel [Byte0]: 61
2786 23:19:01.486056 [Byte1]: 61
2787 23:19:01.490606
2788 23:19:01.490696 Set Vref, RX VrefLevel [Byte0]: 62
2789 23:19:01.493857 [Byte1]: 62
2790 23:19:01.498519
2791 23:19:01.498611 Set Vref, RX VrefLevel [Byte0]: 63
2792 23:19:01.502130 [Byte1]: 63
2793 23:19:01.506846
2794 23:19:01.506929 Set Vref, RX VrefLevel [Byte0]: 64
2795 23:19:01.509895 [Byte1]: 64
2796 23:19:01.514679
2797 23:19:01.514794 Set Vref, RX VrefLevel [Byte0]: 65
2798 23:19:01.517857 [Byte1]: 65
2799 23:19:01.522788
2800 23:19:01.522893 Set Vref, RX VrefLevel [Byte0]: 66
2801 23:19:01.526109 [Byte1]: 66
2802 23:19:01.530771
2803 23:19:01.530855 Set Vref, RX VrefLevel [Byte0]: 67
2804 23:19:01.534068 [Byte1]: 67
2805 23:19:01.538695
2806 23:19:01.538804 Set Vref, RX VrefLevel [Byte0]: 68
2807 23:19:01.541775 [Byte1]: 68
2808 23:19:01.546662
2809 23:19:01.546769 Set Vref, RX VrefLevel [Byte0]: 69
2810 23:19:01.550012 [Byte1]: 69
2811 23:19:01.554655
2812 23:19:01.554739 Set Vref, RX VrefLevel [Byte0]: 70
2813 23:19:01.557974 [Byte1]: 70
2814 23:19:01.562692
2815 23:19:01.562795 Set Vref, RX VrefLevel [Byte0]: 71
2816 23:19:01.565825 [Byte1]: 71
2817 23:19:01.570470
2818 23:19:01.573905 Set Vref, RX VrefLevel [Byte0]: 72
2819 23:19:01.576968 [Byte1]: 72
2820 23:19:01.577054
2821 23:19:01.580590 Set Vref, RX VrefLevel [Byte0]: 73
2822 23:19:01.583716 [Byte1]: 73
2823 23:19:01.583805
2824 23:19:01.587073 Final RX Vref Byte 0 = 60 to rank0
2825 23:19:01.590606 Final RX Vref Byte 1 = 50 to rank0
2826 23:19:01.593657 Final RX Vref Byte 0 = 60 to rank1
2827 23:19:01.596922 Final RX Vref Byte 1 = 50 to rank1==
2828 23:19:01.600459 Dram Type= 6, Freq= 0, CH_0, rank 0
2829 23:19:01.604056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 23:19:01.604148 ==
2831 23:19:01.607157 DQS Delay:
2832 23:19:01.607243 DQS0 = 0, DQS1 = 0
2833 23:19:01.610282 DQM Delay:
2834 23:19:01.610366 DQM0 = 112, DQM1 = 101
2835 23:19:01.614032 DQ Delay:
2836 23:19:01.617303 DQ0 =112, DQ1 =112, DQ2 =110, DQ3 =108
2837 23:19:01.620473 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2838 23:19:01.624050 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2839 23:19:01.627046 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2840 23:19:01.627131
2841 23:19:01.627195
2842 23:19:01.633725 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2843 23:19:01.637147 CH0 RK0: MR19=303, MR18=FBFA
2844 23:19:01.643639 CH0_RK0: MR19=0x303, MR18=0xFBFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2845 23:19:01.643731
2846 23:19:01.647132 ----->DramcWriteLeveling(PI) begin...
2847 23:19:01.647217 ==
2848 23:19:01.650239 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 23:19:01.653691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 23:19:01.653776 ==
2851 23:19:01.656882 Write leveling (Byte 0): 30 => 30
2852 23:19:01.660244 Write leveling (Byte 1): 29 => 29
2853 23:19:01.663886 DramcWriteLeveling(PI) end<-----
2854 23:19:01.663976
2855 23:19:01.664041 ==
2856 23:19:01.666880 Dram Type= 6, Freq= 0, CH_0, rank 1
2857 23:19:01.670207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2858 23:19:01.673618 ==
2859 23:19:01.673712 [Gating] SW mode calibration
2860 23:19:01.680459 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2861 23:19:01.686852 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2862 23:19:01.690535 0 15 0 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
2863 23:19:01.696978 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 23:19:01.700556 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 23:19:01.703917 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 23:19:01.710291 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 23:19:01.714167 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 23:19:01.717245 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2869 23:19:01.724074 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2870 23:19:01.727047 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
2871 23:19:01.730328 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 23:19:01.733759 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 23:19:01.740645 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 23:19:01.743795 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 23:19:01.746991 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 23:19:01.754021 1 0 24 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
2877 23:19:01.757167 1 0 28 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0)
2878 23:19:01.760319 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2879 23:19:01.767309 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 23:19:01.770748 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 23:19:01.773847 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 23:19:01.780703 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 23:19:01.783911 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 23:19:01.787327 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 23:19:01.794034 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2886 23:19:01.797311 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2887 23:19:01.800614 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 23:19:01.804040 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 23:19:01.810867 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 23:19:01.813905 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 23:19:01.817560 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 23:19:01.824235 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 23:19:01.827440 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 23:19:01.830697 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 23:19:01.837781 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 23:19:01.840781 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 23:19:01.844289 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 23:19:01.850808 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 23:19:01.853949 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 23:19:01.857529 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 23:19:01.864173 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2902 23:19:01.867263 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2903 23:19:01.870614 Total UI for P1: 0, mck2ui 16
2904 23:19:01.873859 best dqsien dly found for B0: ( 1, 3, 28)
2905 23:19:01.877090 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 23:19:01.880547 Total UI for P1: 0, mck2ui 16
2907 23:19:01.883885 best dqsien dly found for B1: ( 1, 4, 0)
2908 23:19:01.887349 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2909 23:19:01.890570 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2910 23:19:01.890661
2911 23:19:01.894005 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2912 23:19:01.900572 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2913 23:19:01.900668 [Gating] SW calibration Done
2914 23:19:01.900756 ==
2915 23:19:01.903632 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 23:19:01.910365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 23:19:01.910473 ==
2918 23:19:01.910561 RX Vref Scan: 0
2919 23:19:01.910646
2920 23:19:01.913548 RX Vref 0 -> 0, step: 1
2921 23:19:01.913630
2922 23:19:01.916918 RX Delay -40 -> 252, step: 8
2923 23:19:01.920303 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2924 23:19:01.923547 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2925 23:19:01.927063 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2926 23:19:01.933378 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2927 23:19:01.936883 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2928 23:19:01.939915 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2929 23:19:01.943440 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2930 23:19:01.946861 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2931 23:19:01.953419 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2932 23:19:01.956875 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2933 23:19:01.960219 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2934 23:19:01.963365 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2935 23:19:01.966659 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2936 23:19:01.973300 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2937 23:19:01.976811 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2938 23:19:01.980284 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2939 23:19:01.980370 ==
2940 23:19:01.983548 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 23:19:01.986895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 23:19:01.986990 ==
2943 23:19:01.990282 DQS Delay:
2944 23:19:01.990368 DQS0 = 0, DQS1 = 0
2945 23:19:01.990453 DQM Delay:
2946 23:19:01.993518 DQM0 = 112, DQM1 = 101
2947 23:19:01.993627 DQ Delay:
2948 23:19:01.996845 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2949 23:19:02.000230 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2950 23:19:02.003370 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2951 23:19:02.010287 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
2952 23:19:02.010409
2953 23:19:02.010515
2954 23:19:02.010600 ==
2955 23:19:02.013378 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 23:19:02.016646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 23:19:02.016751 ==
2958 23:19:02.016838
2959 23:19:02.016919
2960 23:19:02.020126 TX Vref Scan disable
2961 23:19:02.020207 == TX Byte 0 ==
2962 23:19:02.026803 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2963 23:19:02.030257 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2964 23:19:02.030347 == TX Byte 1 ==
2965 23:19:02.036811 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2966 23:19:02.040305 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2967 23:19:02.040397 ==
2968 23:19:02.043444 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 23:19:02.046586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 23:19:02.046667 ==
2971 23:19:02.059673 TX Vref=22, minBit 0, minWin=26, winSum=427
2972 23:19:02.062944 TX Vref=24, minBit 0, minWin=26, winSum=430
2973 23:19:02.066252 TX Vref=26, minBit 10, minWin=26, winSum=438
2974 23:19:02.069577 TX Vref=28, minBit 1, minWin=26, winSum=440
2975 23:19:02.073079 TX Vref=30, minBit 10, minWin=26, winSum=441
2976 23:19:02.079753 TX Vref=32, minBit 8, minWin=26, winSum=440
2977 23:19:02.082858 [TxChooseVref] Worse bit 10, Min win 26, Win sum 441, Final Vref 30
2978 23:19:02.082950
2979 23:19:02.086316 Final TX Range 1 Vref 30
2980 23:19:02.086405
2981 23:19:02.086470 ==
2982 23:19:02.089671 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 23:19:02.093138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 23:19:02.093226 ==
2985 23:19:02.093292
2986 23:19:02.096259
2987 23:19:02.096368 TX Vref Scan disable
2988 23:19:02.099574 == TX Byte 0 ==
2989 23:19:02.102991 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2990 23:19:02.106206 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2991 23:19:02.109575 == TX Byte 1 ==
2992 23:19:02.113064 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2993 23:19:02.116227 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2994 23:19:02.116316
2995 23:19:02.119696 [DATLAT]
2996 23:19:02.119807 Freq=1200, CH0 RK1
2997 23:19:02.119902
2998 23:19:02.123119 DATLAT Default: 0xd
2999 23:19:02.123196 0, 0xFFFF, sum = 0
3000 23:19:02.126528 1, 0xFFFF, sum = 0
3001 23:19:02.126614 2, 0xFFFF, sum = 0
3002 23:19:02.129637 3, 0xFFFF, sum = 0
3003 23:19:02.129750 4, 0xFFFF, sum = 0
3004 23:19:02.132964 5, 0xFFFF, sum = 0
3005 23:19:02.133077 6, 0xFFFF, sum = 0
3006 23:19:02.136470 7, 0xFFFF, sum = 0
3007 23:19:02.139664 8, 0xFFFF, sum = 0
3008 23:19:02.139752 9, 0xFFFF, sum = 0
3009 23:19:02.142859 10, 0xFFFF, sum = 0
3010 23:19:02.142944 11, 0xFFFF, sum = 0
3011 23:19:02.146497 12, 0x0, sum = 1
3012 23:19:02.146582 13, 0x0, sum = 2
3013 23:19:02.149459 14, 0x0, sum = 3
3014 23:19:02.149558 15, 0x0, sum = 4
3015 23:19:02.149625 best_step = 13
3016 23:19:02.149686
3017 23:19:02.153064 ==
3018 23:19:02.156370 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 23:19:02.159658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 23:19:02.159747 ==
3021 23:19:02.159814 RX Vref Scan: 0
3022 23:19:02.159873
3023 23:19:02.163169 RX Vref 0 -> 0, step: 1
3024 23:19:02.163251
3025 23:19:02.166362 RX Delay -37 -> 252, step: 4
3026 23:19:02.169915 iDelay=195, Bit 0, Center 106 (35 ~ 178) 144
3027 23:19:02.176300 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3028 23:19:02.179729 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3029 23:19:02.183096 iDelay=195, Bit 3, Center 110 (39 ~ 182) 144
3030 23:19:02.186646 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3031 23:19:02.189881 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3032 23:19:02.193202 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3033 23:19:02.199961 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3034 23:19:02.203055 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3035 23:19:02.206281 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3036 23:19:02.209720 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3037 23:19:02.213004 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3038 23:19:02.220070 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3039 23:19:02.222963 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3040 23:19:02.226449 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3041 23:19:02.229619 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3042 23:19:02.229704 ==
3043 23:19:02.233042 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 23:19:02.239774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 23:19:02.239903 ==
3046 23:19:02.240000 DQS Delay:
3047 23:19:02.240089 DQS0 = 0, DQS1 = 0
3048 23:19:02.242914 DQM Delay:
3049 23:19:02.242998 DQM0 = 110, DQM1 = 101
3050 23:19:02.246293 DQ Delay:
3051 23:19:02.249907 DQ0 =106, DQ1 =110, DQ2 =108, DQ3 =110
3052 23:19:02.252996 DQ4 =110, DQ5 =102, DQ6 =120, DQ7 =120
3053 23:19:02.256510 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =94
3054 23:19:02.259576 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =108
3055 23:19:02.259663
3056 23:19:02.259729
3057 23:19:02.266323 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3058 23:19:02.269578 CH0 RK1: MR19=403, MR18=13FA
3059 23:19:02.276248 CH0_RK1: MR19=0x403, MR18=0x13FA, DQSOSC=402, MR23=63, INC=40, DEC=27
3060 23:19:02.279845 [RxdqsGatingPostProcess] freq 1200
3061 23:19:02.286266 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3062 23:19:02.289754 best DQS0 dly(2T, 0.5T) = (0, 12)
3063 23:19:02.289850 best DQS1 dly(2T, 0.5T) = (0, 12)
3064 23:19:02.293088 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3065 23:19:02.296243 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3066 23:19:02.299830 best DQS0 dly(2T, 0.5T) = (0, 11)
3067 23:19:02.302769 best DQS1 dly(2T, 0.5T) = (0, 12)
3068 23:19:02.306416 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3069 23:19:02.309411 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3070 23:19:02.313054 Pre-setting of DQS Precalculation
3071 23:19:02.319577 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3072 23:19:02.319681 ==
3073 23:19:02.322876 Dram Type= 6, Freq= 0, CH_1, rank 0
3074 23:19:02.326331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 23:19:02.326420 ==
3076 23:19:02.333184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3077 23:19:02.336351 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3078 23:19:02.345663 [CA 0] Center 38 (8~68) winsize 61
3079 23:19:02.348982 [CA 1] Center 38 (8~69) winsize 62
3080 23:19:02.352317 [CA 2] Center 35 (5~65) winsize 61
3081 23:19:02.355610 [CA 3] Center 34 (4~65) winsize 62
3082 23:19:02.359056 [CA 4] Center 35 (5~65) winsize 61
3083 23:19:02.362164 [CA 5] Center 34 (4~64) winsize 61
3084 23:19:02.362247
3085 23:19:02.365681 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3086 23:19:02.365766
3087 23:19:02.368831 [CATrainingPosCal] consider 1 rank data
3088 23:19:02.372288 u2DelayCellTimex100 = 270/100 ps
3089 23:19:02.375480 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3090 23:19:02.378822 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
3091 23:19:02.385574 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3092 23:19:02.389080 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3093 23:19:02.392156 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3094 23:19:02.395613 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3095 23:19:02.395697
3096 23:19:02.398958 CA PerBit enable=1, Macro0, CA PI delay=34
3097 23:19:02.399055
3098 23:19:02.402159 [CBTSetCACLKResult] CA Dly = 34
3099 23:19:02.402246 CS Dly: 7 (0~38)
3100 23:19:02.405598 ==
3101 23:19:02.408549 Dram Type= 6, Freq= 0, CH_1, rank 1
3102 23:19:02.412139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 23:19:02.412256 ==
3104 23:19:02.415234 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3105 23:19:02.422155 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3106 23:19:02.431450 [CA 0] Center 38 (8~68) winsize 61
3107 23:19:02.434727 [CA 1] Center 38 (8~69) winsize 62
3108 23:19:02.437940 [CA 2] Center 35 (5~66) winsize 62
3109 23:19:02.441534 [CA 3] Center 34 (4~65) winsize 62
3110 23:19:02.444680 [CA 4] Center 35 (5~65) winsize 61
3111 23:19:02.447841 [CA 5] Center 33 (3~64) winsize 62
3112 23:19:02.447932
3113 23:19:02.451179 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3114 23:19:02.451256
3115 23:19:02.454466 [CATrainingPosCal] consider 2 rank data
3116 23:19:02.457904 u2DelayCellTimex100 = 270/100 ps
3117 23:19:02.461326 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3118 23:19:02.464625 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
3119 23:19:02.471292 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3120 23:19:02.474551 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3121 23:19:02.477722 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3122 23:19:02.481118 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3123 23:19:02.481198
3124 23:19:02.484476 CA PerBit enable=1, Macro0, CA PI delay=34
3125 23:19:02.484560
3126 23:19:02.487950 [CBTSetCACLKResult] CA Dly = 34
3127 23:19:02.488043 CS Dly: 8 (0~40)
3128 23:19:02.488107
3129 23:19:02.491020 ----->DramcWriteLeveling(PI) begin...
3130 23:19:02.494570 ==
3131 23:19:02.497621 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 23:19:02.501011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 23:19:02.501086 ==
3134 23:19:02.504289 Write leveling (Byte 0): 27 => 27
3135 23:19:02.507866 Write leveling (Byte 1): 29 => 29
3136 23:19:02.511134 DramcWriteLeveling(PI) end<-----
3137 23:19:02.511209
3138 23:19:02.511272 ==
3139 23:19:02.514451 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 23:19:02.517787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 23:19:02.517865 ==
3142 23:19:02.520859 [Gating] SW mode calibration
3143 23:19:02.527650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3144 23:19:02.534105 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3145 23:19:02.537644 0 15 0 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
3146 23:19:02.540949 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 23:19:02.547486 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 23:19:02.550915 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 23:19:02.554440 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 23:19:02.557441 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 23:19:02.564050 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3152 23:19:02.567705 0 15 28 | B1->B0 | 3030 3333 | 0 0 | (0 1) (0 1)
3153 23:19:02.570867 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3154 23:19:02.577519 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 23:19:02.581068 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 23:19:02.584221 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 23:19:02.590676 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 23:19:02.593902 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 23:19:02.597471 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 23:19:02.603986 1 0 28 | B1->B0 | 3939 3131 | 0 0 | (0 0) (0 0)
3161 23:19:02.607075 1 1 0 | B1->B0 | 4040 3e3e | 0 1 | (0 0) (1 1)
3162 23:19:02.610565 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 23:19:02.617207 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 23:19:02.620435 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 23:19:02.623820 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 23:19:02.630574 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 23:19:02.633705 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 23:19:02.637210 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3169 23:19:02.643826 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3170 23:19:02.647298 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 23:19:02.650463 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 23:19:02.657296 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 23:19:02.660461 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 23:19:02.663846 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 23:19:02.670632 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 23:19:02.673896 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 23:19:02.677152 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 23:19:02.683687 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 23:19:02.687114 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 23:19:02.690537 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 23:19:02.693985 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 23:19:02.700535 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 23:19:02.703742 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 23:19:02.707195 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3185 23:19:02.713786 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 23:19:02.717041 Total UI for P1: 0, mck2ui 16
3187 23:19:02.720469 best dqsien dly found for B0: ( 1, 3, 28)
3188 23:19:02.720557 Total UI for P1: 0, mck2ui 16
3189 23:19:02.727266 best dqsien dly found for B1: ( 1, 3, 28)
3190 23:19:02.730595 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3191 23:19:02.733927 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3192 23:19:02.734011
3193 23:19:02.737219 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3194 23:19:02.740280 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3195 23:19:02.743636 [Gating] SW calibration Done
3196 23:19:02.743717 ==
3197 23:19:02.747189 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 23:19:02.750186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 23:19:02.750272 ==
3200 23:19:02.753719 RX Vref Scan: 0
3201 23:19:02.753802
3202 23:19:02.753885 RX Vref 0 -> 0, step: 1
3203 23:19:02.753965
3204 23:19:02.756864 RX Delay -40 -> 252, step: 8
3205 23:19:02.760479 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3206 23:19:02.767091 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3207 23:19:02.770453 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3208 23:19:02.773516 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3209 23:19:02.776969 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3210 23:19:02.780166 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3211 23:19:02.787056 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3212 23:19:02.790446 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3213 23:19:02.793512 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3214 23:19:02.797239 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3215 23:19:02.800382 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3216 23:19:02.807177 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3217 23:19:02.810168 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3218 23:19:02.813624 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3219 23:19:02.816833 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3220 23:19:02.820381 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3221 23:19:02.823685 ==
3222 23:19:02.823791 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 23:19:02.830188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 23:19:02.830299 ==
3225 23:19:02.830392 DQS Delay:
3226 23:19:02.833711 DQS0 = 0, DQS1 = 0
3227 23:19:02.833783 DQM Delay:
3228 23:19:02.836879 DQM0 = 118, DQM1 = 108
3229 23:19:02.836949 DQ Delay:
3230 23:19:02.840335 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =119
3231 23:19:02.843527 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3232 23:19:02.847105 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3233 23:19:02.850275 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =111
3234 23:19:02.850359
3235 23:19:02.850425
3236 23:19:02.850485 ==
3237 23:19:02.853641 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 23:19:02.860337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 23:19:02.860446 ==
3240 23:19:02.860537
3241 23:19:02.860634
3242 23:19:02.860721 TX Vref Scan disable
3243 23:19:02.863457 == TX Byte 0 ==
3244 23:19:02.866641 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3245 23:19:02.873518 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3246 23:19:02.873611 == TX Byte 1 ==
3247 23:19:02.876841 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3248 23:19:02.883546 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3249 23:19:02.883659 ==
3250 23:19:02.886693 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 23:19:02.890148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 23:19:02.890235 ==
3253 23:19:02.901235 TX Vref=22, minBit 11, minWin=24, winSum=409
3254 23:19:02.904742 TX Vref=24, minBit 2, minWin=25, winSum=413
3255 23:19:02.908025 TX Vref=26, minBit 1, minWin=25, winSum=417
3256 23:19:02.911501 TX Vref=28, minBit 1, minWin=25, winSum=418
3257 23:19:02.914871 TX Vref=30, minBit 1, minWin=25, winSum=421
3258 23:19:02.921587 TX Vref=32, minBit 2, minWin=25, winSum=421
3259 23:19:02.924766 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 30
3260 23:19:02.924848
3261 23:19:02.927897 Final TX Range 1 Vref 30
3262 23:19:02.928055
3263 23:19:02.928168 ==
3264 23:19:02.931210 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 23:19:02.934640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 23:19:02.934713 ==
3267 23:19:02.934775
3268 23:19:02.937905
3269 23:19:02.938005 TX Vref Scan disable
3270 23:19:02.941401 == TX Byte 0 ==
3271 23:19:02.944826 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3272 23:19:02.947957 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3273 23:19:02.951287 == TX Byte 1 ==
3274 23:19:02.954507 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3275 23:19:02.957786 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3276 23:19:02.961322
3277 23:19:02.961422 [DATLAT]
3278 23:19:02.961542 Freq=1200, CH1 RK0
3279 23:19:02.961620
3280 23:19:02.964794 DATLAT Default: 0xd
3281 23:19:02.964890 0, 0xFFFF, sum = 0
3282 23:19:02.967970 1, 0xFFFF, sum = 0
3283 23:19:02.968048 2, 0xFFFF, sum = 0
3284 23:19:02.971241 3, 0xFFFF, sum = 0
3285 23:19:02.971363 4, 0xFFFF, sum = 0
3286 23:19:02.974532 5, 0xFFFF, sum = 0
3287 23:19:02.977857 6, 0xFFFF, sum = 0
3288 23:19:02.977936 7, 0xFFFF, sum = 0
3289 23:19:02.981419 8, 0xFFFF, sum = 0
3290 23:19:02.981530 9, 0xFFFF, sum = 0
3291 23:19:02.984549 10, 0xFFFF, sum = 0
3292 23:19:02.984654 11, 0xFFFF, sum = 0
3293 23:19:02.987825 12, 0x0, sum = 1
3294 23:19:02.987932 13, 0x0, sum = 2
3295 23:19:02.991160 14, 0x0, sum = 3
3296 23:19:02.991261 15, 0x0, sum = 4
3297 23:19:02.991361 best_step = 13
3298 23:19:02.991450
3299 23:19:02.994585 ==
3300 23:19:02.997650 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 23:19:03.001053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3302 23:19:03.001161 ==
3303 23:19:03.001253 RX Vref Scan: 1
3304 23:19:03.001350
3305 23:19:03.004653 Set Vref Range= 32 -> 127
3306 23:19:03.004857
3307 23:19:03.007743 RX Vref 32 -> 127, step: 1
3308 23:19:03.007923
3309 23:19:03.011230 RX Delay -21 -> 252, step: 4
3310 23:19:03.011393
3311 23:19:03.014566 Set Vref, RX VrefLevel [Byte0]: 32
3312 23:19:03.017882 [Byte1]: 32
3313 23:19:03.017981
3314 23:19:03.021111 Set Vref, RX VrefLevel [Byte0]: 33
3315 23:19:03.024495 [Byte1]: 33
3316 23:19:03.027742
3317 23:19:03.027870 Set Vref, RX VrefLevel [Byte0]: 34
3318 23:19:03.031121 [Byte1]: 34
3319 23:19:03.035697
3320 23:19:03.035799 Set Vref, RX VrefLevel [Byte0]: 35
3321 23:19:03.038760 [Byte1]: 35
3322 23:19:03.043456
3323 23:19:03.043540 Set Vref, RX VrefLevel [Byte0]: 36
3324 23:19:03.046890 [Byte1]: 36
3325 23:19:03.051579
3326 23:19:03.051724 Set Vref, RX VrefLevel [Byte0]: 37
3327 23:19:03.054697 [Byte1]: 37
3328 23:19:03.059269
3329 23:19:03.059402 Set Vref, RX VrefLevel [Byte0]: 38
3330 23:19:03.062739 [Byte1]: 38
3331 23:19:03.067471
3332 23:19:03.067579 Set Vref, RX VrefLevel [Byte0]: 39
3333 23:19:03.070640 [Byte1]: 39
3334 23:19:03.075320
3335 23:19:03.075429 Set Vref, RX VrefLevel [Byte0]: 40
3336 23:19:03.078436 [Byte1]: 40
3337 23:19:03.082921
3338 23:19:03.083026 Set Vref, RX VrefLevel [Byte0]: 41
3339 23:19:03.086618 [Byte1]: 41
3340 23:19:03.090914
3341 23:19:03.091012 Set Vref, RX VrefLevel [Byte0]: 42
3342 23:19:03.094455 [Byte1]: 42
3343 23:19:03.098973
3344 23:19:03.099071 Set Vref, RX VrefLevel [Byte0]: 43
3345 23:19:03.102166 [Byte1]: 43
3346 23:19:03.106894
3347 23:19:03.106998 Set Vref, RX VrefLevel [Byte0]: 44
3348 23:19:03.109974 [Byte1]: 44
3349 23:19:03.114675
3350 23:19:03.114774 Set Vref, RX VrefLevel [Byte0]: 45
3351 23:19:03.118187 [Byte1]: 45
3352 23:19:03.122904
3353 23:19:03.122980 Set Vref, RX VrefLevel [Byte0]: 46
3354 23:19:03.125941 [Byte1]: 46
3355 23:19:03.130410
3356 23:19:03.130493 Set Vref, RX VrefLevel [Byte0]: 47
3357 23:19:03.133871 [Byte1]: 47
3358 23:19:03.138519
3359 23:19:03.138613 Set Vref, RX VrefLevel [Byte0]: 48
3360 23:19:03.141935 [Byte1]: 48
3361 23:19:03.146552
3362 23:19:03.146641 Set Vref, RX VrefLevel [Byte0]: 49
3363 23:19:03.149676 [Byte1]: 49
3364 23:19:03.154551
3365 23:19:03.154640 Set Vref, RX VrefLevel [Byte0]: 50
3366 23:19:03.157894 [Byte1]: 50
3367 23:19:03.162560
3368 23:19:03.162666 Set Vref, RX VrefLevel [Byte0]: 51
3369 23:19:03.165702 [Byte1]: 51
3370 23:19:03.170111
3371 23:19:03.170197 Set Vref, RX VrefLevel [Byte0]: 52
3372 23:19:03.173455 [Byte1]: 52
3373 23:19:03.178089
3374 23:19:03.178174 Set Vref, RX VrefLevel [Byte0]: 53
3375 23:19:03.181585 [Byte1]: 53
3376 23:19:03.186146
3377 23:19:03.186230 Set Vref, RX VrefLevel [Byte0]: 54
3378 23:19:03.189468 [Byte1]: 54
3379 23:19:03.194132
3380 23:19:03.194215 Set Vref, RX VrefLevel [Byte0]: 55
3381 23:19:03.197249 [Byte1]: 55
3382 23:19:03.202079
3383 23:19:03.202162 Set Vref, RX VrefLevel [Byte0]: 56
3384 23:19:03.205101 [Byte1]: 56
3385 23:19:03.209892
3386 23:19:03.209975 Set Vref, RX VrefLevel [Byte0]: 57
3387 23:19:03.213063 [Byte1]: 57
3388 23:19:03.217780
3389 23:19:03.217863 Set Vref, RX VrefLevel [Byte0]: 58
3390 23:19:03.220915 [Byte1]: 58
3391 23:19:03.225616
3392 23:19:03.225699 Set Vref, RX VrefLevel [Byte0]: 59
3393 23:19:03.228993 [Byte1]: 59
3394 23:19:03.233405
3395 23:19:03.233496 Set Vref, RX VrefLevel [Byte0]: 60
3396 23:19:03.236878 [Byte1]: 60
3397 23:19:03.241435
3398 23:19:03.241527 Set Vref, RX VrefLevel [Byte0]: 61
3399 23:19:03.244739 [Byte1]: 61
3400 23:19:03.249614
3401 23:19:03.249696 Set Vref, RX VrefLevel [Byte0]: 62
3402 23:19:03.252654 [Byte1]: 62
3403 23:19:03.257287
3404 23:19:03.257371 Set Vref, RX VrefLevel [Byte0]: 63
3405 23:19:03.260640 [Byte1]: 63
3406 23:19:03.265232
3407 23:19:03.265534 Set Vref, RX VrefLevel [Byte0]: 64
3408 23:19:03.268547 [Byte1]: 64
3409 23:19:03.273000
3410 23:19:03.273210 Set Vref, RX VrefLevel [Byte0]: 65
3411 23:19:03.276439 [Byte1]: 65
3412 23:19:03.281119
3413 23:19:03.281314 Set Vref, RX VrefLevel [Byte0]: 66
3414 23:19:03.284260 [Byte1]: 66
3415 23:19:03.288863
3416 23:19:03.289059 Set Vref, RX VrefLevel [Byte0]: 67
3417 23:19:03.292304 [Byte1]: 67
3418 23:19:03.296962
3419 23:19:03.297101 Set Vref, RX VrefLevel [Byte0]: 68
3420 23:19:03.300417 [Byte1]: 68
3421 23:19:03.304783
3422 23:19:03.304946 Final RX Vref Byte 0 = 57 to rank0
3423 23:19:03.308404 Final RX Vref Byte 1 = 51 to rank0
3424 23:19:03.311598 Final RX Vref Byte 0 = 57 to rank1
3425 23:19:03.314678 Final RX Vref Byte 1 = 51 to rank1==
3426 23:19:03.318058 Dram Type= 6, Freq= 0, CH_1, rank 0
3427 23:19:03.324782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 23:19:03.324917 ==
3429 23:19:03.325016 DQS Delay:
3430 23:19:03.325117 DQS0 = 0, DQS1 = 0
3431 23:19:03.328382 DQM Delay:
3432 23:19:03.328482 DQM0 = 117, DQM1 = 110
3433 23:19:03.331766 DQ Delay:
3434 23:19:03.334734 DQ0 =120, DQ1 =114, DQ2 =108, DQ3 =116
3435 23:19:03.338247 DQ4 =114, DQ5 =124, DQ6 =130, DQ7 =116
3436 23:19:03.341831 DQ8 =100, DQ9 =102, DQ10 =106, DQ11 =104
3437 23:19:03.344814 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3438 23:19:03.344971
3439 23:19:03.345115
3440 23:19:03.351660 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3441 23:19:03.355011 CH1 RK0: MR19=303, MR18=ECF3
3442 23:19:03.361760 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3443 23:19:03.361928
3444 23:19:03.364765 ----->DramcWriteLeveling(PI) begin...
3445 23:19:03.364924 ==
3446 23:19:03.368574 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 23:19:03.371635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 23:19:03.374921 ==
3449 23:19:03.375087 Write leveling (Byte 0): 25 => 25
3450 23:19:03.378315 Write leveling (Byte 1): 26 => 26
3451 23:19:03.381489 DramcWriteLeveling(PI) end<-----
3452 23:19:03.381644
3453 23:19:03.381788 ==
3454 23:19:03.384952 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 23:19:03.391659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 23:19:03.391763 ==
3457 23:19:03.391850 [Gating] SW mode calibration
3458 23:19:03.401550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3459 23:19:03.404698 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3460 23:19:03.411366 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3461 23:19:03.414957 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 23:19:03.418079 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 23:19:03.421339 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 23:19:03.428269 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 23:19:03.431579 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 23:19:03.434987 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3467 23:19:03.441693 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3468 23:19:03.444888 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 23:19:03.448013 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 23:19:03.454779 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 23:19:03.458373 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 23:19:03.461612 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 23:19:03.468044 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
3474 23:19:03.471311 1 0 24 | B1->B0 | 2929 4343 | 0 1 | (0 0) (0 0)
3475 23:19:03.474937 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3476 23:19:03.481457 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 23:19:03.484646 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 23:19:03.487826 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 23:19:03.494505 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 23:19:03.497830 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 23:19:03.501242 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 23:19:03.508054 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3483 23:19:03.511094 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3484 23:19:03.514297 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 23:19:03.521171 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 23:19:03.524541 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 23:19:03.527933 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 23:19:03.534540 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 23:19:03.537525 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:19:03.541051 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 23:19:03.547687 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 23:19:03.551032 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 23:19:03.554210 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 23:19:03.560969 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 23:19:03.564242 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 23:19:03.567541 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 23:19:03.570680 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3498 23:19:03.577626 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3499 23:19:03.580744 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 23:19:03.584141 Total UI for P1: 0, mck2ui 16
3501 23:19:03.587488 best dqsien dly found for B0: ( 1, 3, 22)
3502 23:19:03.590695 Total UI for P1: 0, mck2ui 16
3503 23:19:03.593895 best dqsien dly found for B1: ( 1, 3, 24)
3504 23:19:03.597454 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3505 23:19:03.600699 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3506 23:19:03.600840
3507 23:19:03.604161 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3508 23:19:03.607554 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3509 23:19:03.610551 [Gating] SW calibration Done
3510 23:19:03.610645 ==
3511 23:19:03.614044 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 23:19:03.620349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 23:19:03.620445 ==
3514 23:19:03.620527 RX Vref Scan: 0
3515 23:19:03.620605
3516 23:19:03.623898 RX Vref 0 -> 0, step: 1
3517 23:19:03.623987
3518 23:19:03.627219 RX Delay -40 -> 252, step: 8
3519 23:19:03.630490 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3520 23:19:03.633753 iDelay=200, Bit 1, Center 107 (40 ~ 175) 136
3521 23:19:03.636993 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3522 23:19:03.643784 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3523 23:19:03.646887 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3524 23:19:03.650259 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3525 23:19:03.653636 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3526 23:19:03.656883 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3527 23:19:03.660142 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3528 23:19:03.667035 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3529 23:19:03.670135 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3530 23:19:03.673345 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3531 23:19:03.677031 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3532 23:19:03.683505 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3533 23:19:03.686851 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3534 23:19:03.690255 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3535 23:19:03.690345 ==
3536 23:19:03.693290 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 23:19:03.696961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 23:19:03.697045 ==
3539 23:19:03.700158 DQS Delay:
3540 23:19:03.700233 DQS0 = 0, DQS1 = 0
3541 23:19:03.703484 DQM Delay:
3542 23:19:03.703581 DQM0 = 113, DQM1 = 113
3543 23:19:03.703653 DQ Delay:
3544 23:19:03.706771 DQ0 =115, DQ1 =107, DQ2 =103, DQ3 =111
3545 23:19:03.713209 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3546 23:19:03.716560 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3547 23:19:03.720083 DQ12 =123, DQ13 =123, DQ14 =115, DQ15 =119
3548 23:19:03.720157
3549 23:19:03.720218
3550 23:19:03.720277 ==
3551 23:19:03.723361 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 23:19:03.726668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 23:19:03.726740 ==
3554 23:19:03.726801
3555 23:19:03.726862
3556 23:19:03.729818 TX Vref Scan disable
3557 23:19:03.733152 == TX Byte 0 ==
3558 23:19:03.736476 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3559 23:19:03.739702 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3560 23:19:03.743350 == TX Byte 1 ==
3561 23:19:03.746586 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3562 23:19:03.749819 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3563 23:19:03.749890 ==
3564 23:19:03.753115 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 23:19:03.756519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 23:19:03.759656 ==
3567 23:19:03.769768 TX Vref=22, minBit 0, minWin=25, winSum=416
3568 23:19:03.772948 TX Vref=24, minBit 0, minWin=25, winSum=423
3569 23:19:03.776527 TX Vref=26, minBit 0, minWin=25, winSum=425
3570 23:19:03.779817 TX Vref=28, minBit 0, minWin=25, winSum=424
3571 23:19:03.783173 TX Vref=30, minBit 1, minWin=25, winSum=428
3572 23:19:03.789792 TX Vref=32, minBit 1, minWin=25, winSum=425
3573 23:19:03.792811 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 30
3574 23:19:03.792881
3575 23:19:03.796095 Final TX Range 1 Vref 30
3576 23:19:03.796164
3577 23:19:03.796226 ==
3578 23:19:03.799463 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 23:19:03.802730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 23:19:03.805932 ==
3581 23:19:03.806010
3582 23:19:03.806069
3583 23:19:03.806125 TX Vref Scan disable
3584 23:19:03.809335 == TX Byte 0 ==
3585 23:19:03.812676 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3586 23:19:03.816038 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3587 23:19:03.819484 == TX Byte 1 ==
3588 23:19:03.822887 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3589 23:19:03.829217 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3590 23:19:03.829288
3591 23:19:03.829348 [DATLAT]
3592 23:19:03.829405 Freq=1200, CH1 RK1
3593 23:19:03.829541
3594 23:19:03.832815 DATLAT Default: 0xd
3595 23:19:03.832889 0, 0xFFFF, sum = 0
3596 23:19:03.835773 1, 0xFFFF, sum = 0
3597 23:19:03.839436 2, 0xFFFF, sum = 0
3598 23:19:03.839536 3, 0xFFFF, sum = 0
3599 23:19:03.842522 4, 0xFFFF, sum = 0
3600 23:19:03.842590 5, 0xFFFF, sum = 0
3601 23:19:03.845770 6, 0xFFFF, sum = 0
3602 23:19:03.845836 7, 0xFFFF, sum = 0
3603 23:19:03.849117 8, 0xFFFF, sum = 0
3604 23:19:03.849182 9, 0xFFFF, sum = 0
3605 23:19:03.852545 10, 0xFFFF, sum = 0
3606 23:19:03.852612 11, 0xFFFF, sum = 0
3607 23:19:03.855769 12, 0x0, sum = 1
3608 23:19:03.855841 13, 0x0, sum = 2
3609 23:19:03.859183 14, 0x0, sum = 3
3610 23:19:03.859250 15, 0x0, sum = 4
3611 23:19:03.862306 best_step = 13
3612 23:19:03.862373
3613 23:19:03.862431 ==
3614 23:19:03.865893 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 23:19:03.868881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 23:19:03.868945 ==
3617 23:19:03.869002 RX Vref Scan: 0
3618 23:19:03.872211
3619 23:19:03.872279 RX Vref 0 -> 0, step: 1
3620 23:19:03.872340
3621 23:19:03.875835 RX Delay -13 -> 252, step: 4
3622 23:19:03.878898 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3623 23:19:03.885624 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3624 23:19:03.888829 iDelay=195, Bit 2, Center 104 (39 ~ 170) 132
3625 23:19:03.892351 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3626 23:19:03.895631 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3627 23:19:03.898661 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3628 23:19:03.905442 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3629 23:19:03.908761 iDelay=195, Bit 7, Center 114 (51 ~ 178) 128
3630 23:19:03.912153 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3631 23:19:03.915595 iDelay=195, Bit 9, Center 104 (39 ~ 170) 132
3632 23:19:03.918810 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3633 23:19:03.925200 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3634 23:19:03.928647 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3635 23:19:03.932117 iDelay=195, Bit 13, Center 120 (59 ~ 182) 124
3636 23:19:03.935180 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3637 23:19:03.941763 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3638 23:19:03.941867 ==
3639 23:19:03.945126 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 23:19:03.948500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 23:19:03.948579 ==
3642 23:19:03.948642 DQS Delay:
3643 23:19:03.951777 DQS0 = 0, DQS1 = 0
3644 23:19:03.951856 DQM Delay:
3645 23:19:03.955267 DQM0 = 114, DQM1 = 113
3646 23:19:03.955346 DQ Delay:
3647 23:19:03.958627 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =112
3648 23:19:03.961494 DQ4 =110, DQ5 =124, DQ6 =124, DQ7 =114
3649 23:19:03.965137 DQ8 =100, DQ9 =104, DQ10 =116, DQ11 =106
3650 23:19:03.968321 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =122
3651 23:19:03.968400
3652 23:19:03.971703
3653 23:19:03.978048 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3654 23:19:03.981465 CH1 RK1: MR19=304, MR18=FA0A
3655 23:19:03.988099 CH1_RK1: MR19=0x304, MR18=0xFA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3656 23:19:03.991345 [RxdqsGatingPostProcess] freq 1200
3657 23:19:03.994634 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3658 23:19:03.997845 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 23:19:04.001307 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 23:19:04.004620 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 23:19:04.007915 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 23:19:04.011265 best DQS0 dly(2T, 0.5T) = (0, 11)
3663 23:19:04.014536 best DQS1 dly(2T, 0.5T) = (0, 11)
3664 23:19:04.018062 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3665 23:19:04.020983 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3666 23:19:04.024552 Pre-setting of DQS Precalculation
3667 23:19:04.027779 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3668 23:19:04.037635 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3669 23:19:04.044379 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3670 23:19:04.044457
3671 23:19:04.044520
3672 23:19:04.047705 [Calibration Summary] 2400 Mbps
3673 23:19:04.047773 CH 0, Rank 0
3674 23:19:04.050957 SW Impedance : PASS
3675 23:19:04.051044 DUTY Scan : NO K
3676 23:19:04.054527 ZQ Calibration : PASS
3677 23:19:04.057515 Jitter Meter : NO K
3678 23:19:04.057588 CBT Training : PASS
3679 23:19:04.060896 Write leveling : PASS
3680 23:19:04.064207 RX DQS gating : PASS
3681 23:19:04.064277 RX DQ/DQS(RDDQC) : PASS
3682 23:19:04.067744 TX DQ/DQS : PASS
3683 23:19:04.067817 RX DATLAT : PASS
3684 23:19:04.070992 RX DQ/DQS(Engine): PASS
3685 23:19:04.074176 TX OE : NO K
3686 23:19:04.074253 All Pass.
3687 23:19:04.074315
3688 23:19:04.074378 CH 0, Rank 1
3689 23:19:04.077599 SW Impedance : PASS
3690 23:19:04.080885 DUTY Scan : NO K
3691 23:19:04.080960 ZQ Calibration : PASS
3692 23:19:04.083858 Jitter Meter : NO K
3693 23:19:04.087537 CBT Training : PASS
3694 23:19:04.087611 Write leveling : PASS
3695 23:19:04.090527 RX DQS gating : PASS
3696 23:19:04.093908 RX DQ/DQS(RDDQC) : PASS
3697 23:19:04.093978 TX DQ/DQS : PASS
3698 23:19:04.097102 RX DATLAT : PASS
3699 23:19:04.100338 RX DQ/DQS(Engine): PASS
3700 23:19:04.100411 TX OE : NO K
3701 23:19:04.103760 All Pass.
3702 23:19:04.103827
3703 23:19:04.103893 CH 1, Rank 0
3704 23:19:04.107078 SW Impedance : PASS
3705 23:19:04.107153 DUTY Scan : NO K
3706 23:19:04.110461 ZQ Calibration : PASS
3707 23:19:04.113769 Jitter Meter : NO K
3708 23:19:04.113836 CBT Training : PASS
3709 23:19:04.116934 Write leveling : PASS
3710 23:19:04.120509 RX DQS gating : PASS
3711 23:19:04.120583 RX DQ/DQS(RDDQC) : PASS
3712 23:19:04.123517 TX DQ/DQS : PASS
3713 23:19:04.126828 RX DATLAT : PASS
3714 23:19:04.126905 RX DQ/DQS(Engine): PASS
3715 23:19:04.129940 TX OE : NO K
3716 23:19:04.130032 All Pass.
3717 23:19:04.130179
3718 23:19:04.133620 CH 1, Rank 1
3719 23:19:04.133698 SW Impedance : PASS
3720 23:19:04.136706 DUTY Scan : NO K
3721 23:19:04.139997 ZQ Calibration : PASS
3722 23:19:04.140065 Jitter Meter : NO K
3723 23:19:04.143432 CBT Training : PASS
3724 23:19:04.143501 Write leveling : PASS
3725 23:19:04.146841 RX DQS gating : PASS
3726 23:19:04.150009 RX DQ/DQS(RDDQC) : PASS
3727 23:19:04.150085 TX DQ/DQS : PASS
3728 23:19:04.153458 RX DATLAT : PASS
3729 23:19:04.156791 RX DQ/DQS(Engine): PASS
3730 23:19:04.156859 TX OE : NO K
3731 23:19:04.160111 All Pass.
3732 23:19:04.160181
3733 23:19:04.160240 DramC Write-DBI off
3734 23:19:04.163362 PER_BANK_REFRESH: Hybrid Mode
3735 23:19:04.166525 TX_TRACKING: ON
3736 23:19:04.173453 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3737 23:19:04.176520 [FAST_K] Save calibration result to emmc
3738 23:19:04.179856 dramc_set_vcore_voltage set vcore to 650000
3739 23:19:04.183212 Read voltage for 600, 5
3740 23:19:04.183291 Vio18 = 0
3741 23:19:04.186592 Vcore = 650000
3742 23:19:04.186687 Vdram = 0
3743 23:19:04.186750 Vddq = 0
3744 23:19:04.189882 Vmddr = 0
3745 23:19:04.193185 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3746 23:19:04.199561 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3747 23:19:04.199634 MEM_TYPE=3, freq_sel=19
3748 23:19:04.203193 sv_algorithm_assistance_LP4_1600
3749 23:19:04.209463 ============ PULL DRAM RESETB DOWN ============
3750 23:19:04.212895 ========== PULL DRAM RESETB DOWN end =========
3751 23:19:04.216192 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3752 23:19:04.219552 ===================================
3753 23:19:04.222761 LPDDR4 DRAM CONFIGURATION
3754 23:19:04.226354 ===================================
3755 23:19:04.229688 EX_ROW_EN[0] = 0x0
3756 23:19:04.229757 EX_ROW_EN[1] = 0x0
3757 23:19:04.233117 LP4Y_EN = 0x0
3758 23:19:04.233193 WORK_FSP = 0x0
3759 23:19:04.236070 WL = 0x2
3760 23:19:04.236137 RL = 0x2
3761 23:19:04.239489 BL = 0x2
3762 23:19:04.239561 RPST = 0x0
3763 23:19:04.243049 RD_PRE = 0x0
3764 23:19:04.243120 WR_PRE = 0x1
3765 23:19:04.245969 WR_PST = 0x0
3766 23:19:04.246044 DBI_WR = 0x0
3767 23:19:04.249699 DBI_RD = 0x0
3768 23:19:04.249769 OTF = 0x1
3769 23:19:04.252680 ===================================
3770 23:19:04.256107 ===================================
3771 23:19:04.259311 ANA top config
3772 23:19:04.262706 ===================================
3773 23:19:04.266031 DLL_ASYNC_EN = 0
3774 23:19:04.266099 ALL_SLAVE_EN = 1
3775 23:19:04.269524 NEW_RANK_MODE = 1
3776 23:19:04.272581 DLL_IDLE_MODE = 1
3777 23:19:04.275880 LP45_APHY_COMB_EN = 1
3778 23:19:04.275962 TX_ODT_DIS = 1
3779 23:19:04.279319 NEW_8X_MODE = 1
3780 23:19:04.282594 ===================================
3781 23:19:04.285754 ===================================
3782 23:19:04.289254 data_rate = 1200
3783 23:19:04.292282 CKR = 1
3784 23:19:04.295703 DQ_P2S_RATIO = 8
3785 23:19:04.298951 ===================================
3786 23:19:04.302069 CA_P2S_RATIO = 8
3787 23:19:04.302142 DQ_CA_OPEN = 0
3788 23:19:04.305427 DQ_SEMI_OPEN = 0
3789 23:19:04.308765 CA_SEMI_OPEN = 0
3790 23:19:04.312045 CA_FULL_RATE = 0
3791 23:19:04.315520 DQ_CKDIV4_EN = 1
3792 23:19:04.318773 CA_CKDIV4_EN = 1
3793 23:19:04.322183 CA_PREDIV_EN = 0
3794 23:19:04.322251 PH8_DLY = 0
3795 23:19:04.325115 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3796 23:19:04.328606 DQ_AAMCK_DIV = 4
3797 23:19:04.331980 CA_AAMCK_DIV = 4
3798 23:19:04.335425 CA_ADMCK_DIV = 4
3799 23:19:04.338746 DQ_TRACK_CA_EN = 0
3800 23:19:04.338838 CA_PICK = 600
3801 23:19:04.342058 CA_MCKIO = 600
3802 23:19:04.345006 MCKIO_SEMI = 0
3803 23:19:04.348482 PLL_FREQ = 2288
3804 23:19:04.351979 DQ_UI_PI_RATIO = 32
3805 23:19:04.355215 CA_UI_PI_RATIO = 0
3806 23:19:04.358263 ===================================
3807 23:19:04.361781 ===================================
3808 23:19:04.361861 memory_type:LPDDR4
3809 23:19:04.364905 GP_NUM : 10
3810 23:19:04.368467 SRAM_EN : 1
3811 23:19:04.368555 MD32_EN : 0
3812 23:19:04.371515 ===================================
3813 23:19:04.374842 [ANA_INIT] >>>>>>>>>>>>>>
3814 23:19:04.378457 <<<<<< [CONFIGURE PHASE]: ANA_TX
3815 23:19:04.381651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3816 23:19:04.385053 ===================================
3817 23:19:04.388427 data_rate = 1200,PCW = 0X5800
3818 23:19:04.391673 ===================================
3819 23:19:04.394863 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3820 23:19:04.398042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 23:19:04.404911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 23:19:04.408054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3823 23:19:04.411437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3824 23:19:04.417985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3825 23:19:04.418065 [ANA_INIT] flow start
3826 23:19:04.421290 [ANA_INIT] PLL >>>>>>>>
3827 23:19:04.424536 [ANA_INIT] PLL <<<<<<<<
3828 23:19:04.424616 [ANA_INIT] MIDPI >>>>>>>>
3829 23:19:04.427868 [ANA_INIT] MIDPI <<<<<<<<
3830 23:19:04.431419 [ANA_INIT] DLL >>>>>>>>
3831 23:19:04.431499 [ANA_INIT] flow end
3832 23:19:04.434609 ============ LP4 DIFF to SE enter ============
3833 23:19:04.441212 ============ LP4 DIFF to SE exit ============
3834 23:19:04.441293 [ANA_INIT] <<<<<<<<<<<<<
3835 23:19:04.444571 [Flow] Enable top DCM control >>>>>
3836 23:19:04.447835 [Flow] Enable top DCM control <<<<<
3837 23:19:04.451061 Enable DLL master slave shuffle
3838 23:19:04.457595 ==============================================================
3839 23:19:04.457676 Gating Mode config
3840 23:19:04.464455 ==============================================================
3841 23:19:04.467712 Config description:
3842 23:19:04.477638 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3843 23:19:04.484427 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3844 23:19:04.487538 SELPH_MODE 0: By rank 1: By Phase
3845 23:19:04.494437 ==============================================================
3846 23:19:04.497765 GAT_TRACK_EN = 1
3847 23:19:04.500932 RX_GATING_MODE = 2
3848 23:19:04.501028 RX_GATING_TRACK_MODE = 2
3849 23:19:04.504114 SELPH_MODE = 1
3850 23:19:04.507579 PICG_EARLY_EN = 1
3851 23:19:04.511108 VALID_LAT_VALUE = 1
3852 23:19:04.517453 ==============================================================
3853 23:19:04.520820 Enter into Gating configuration >>>>
3854 23:19:04.524178 Exit from Gating configuration <<<<
3855 23:19:04.527564 Enter into DVFS_PRE_config >>>>>
3856 23:19:04.537289 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3857 23:19:04.540581 Exit from DVFS_PRE_config <<<<<
3858 23:19:04.543817 Enter into PICG configuration >>>>
3859 23:19:04.547302 Exit from PICG configuration <<<<
3860 23:19:04.550616 [RX_INPUT] configuration >>>>>
3861 23:19:04.553976 [RX_INPUT] configuration <<<<<
3862 23:19:04.557216 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3863 23:19:04.563776 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3864 23:19:04.570547 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3865 23:19:04.576824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3866 23:19:04.583767 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3867 23:19:04.586986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3868 23:19:04.593576 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3869 23:19:04.596934 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3870 23:19:04.600187 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3871 23:19:04.603342 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3872 23:19:04.607059 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3873 23:19:04.613398 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 23:19:04.617018 ===================================
3875 23:19:04.620063 LPDDR4 DRAM CONFIGURATION
3876 23:19:04.623265 ===================================
3877 23:19:04.623346 EX_ROW_EN[0] = 0x0
3878 23:19:04.626812 EX_ROW_EN[1] = 0x0
3879 23:19:04.626893 LP4Y_EN = 0x0
3880 23:19:04.629979 WORK_FSP = 0x0
3881 23:19:04.630058 WL = 0x2
3882 23:19:04.633208 RL = 0x2
3883 23:19:04.633288 BL = 0x2
3884 23:19:04.636506 RPST = 0x0
3885 23:19:04.636600 RD_PRE = 0x0
3886 23:19:04.639773 WR_PRE = 0x1
3887 23:19:04.639853 WR_PST = 0x0
3888 23:19:04.643367 DBI_WR = 0x0
3889 23:19:04.643448 DBI_RD = 0x0
3890 23:19:04.646725 OTF = 0x1
3891 23:19:04.650094 ===================================
3892 23:19:04.653435 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3893 23:19:04.656854 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3894 23:19:04.663324 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3895 23:19:04.666520 ===================================
3896 23:19:04.666655 LPDDR4 DRAM CONFIGURATION
3897 23:19:04.669772 ===================================
3898 23:19:04.673037 EX_ROW_EN[0] = 0x10
3899 23:19:04.676729 EX_ROW_EN[1] = 0x0
3900 23:19:04.676874 LP4Y_EN = 0x0
3901 23:19:04.679867 WORK_FSP = 0x0
3902 23:19:04.679947 WL = 0x2
3903 23:19:04.683050 RL = 0x2
3904 23:19:04.683180 BL = 0x2
3905 23:19:04.686784 RPST = 0x0
3906 23:19:04.686864 RD_PRE = 0x0
3907 23:19:04.689904 WR_PRE = 0x1
3908 23:19:04.690016 WR_PST = 0x0
3909 23:19:04.692868 DBI_WR = 0x0
3910 23:19:04.692948 DBI_RD = 0x0
3911 23:19:04.696539 OTF = 0x1
3912 23:19:04.699573 ===================================
3913 23:19:04.706340 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3914 23:19:04.709764 nWR fixed to 30
3915 23:19:04.712742 [ModeRegInit_LP4] CH0 RK0
3916 23:19:04.712852 [ModeRegInit_LP4] CH0 RK1
3917 23:19:04.716179 [ModeRegInit_LP4] CH1 RK0
3918 23:19:04.719502 [ModeRegInit_LP4] CH1 RK1
3919 23:19:04.719582 match AC timing 17
3920 23:19:04.725910 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3921 23:19:04.729634 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3922 23:19:04.732476 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3923 23:19:04.739326 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3924 23:19:04.742644 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3925 23:19:04.742728 ==
3926 23:19:04.745945 Dram Type= 6, Freq= 0, CH_0, rank 0
3927 23:19:04.749068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3928 23:19:04.749149 ==
3929 23:19:04.755713 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3930 23:19:04.762588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3931 23:19:04.765595 [CA 0] Center 37 (7~67) winsize 61
3932 23:19:04.769069 [CA 1] Center 37 (7~67) winsize 61
3933 23:19:04.772046 [CA 2] Center 35 (5~65) winsize 61
3934 23:19:04.775768 [CA 3] Center 35 (5~65) winsize 61
3935 23:19:04.778850 [CA 4] Center 34 (4~65) winsize 62
3936 23:19:04.782535 [CA 5] Center 34 (4~64) winsize 61
3937 23:19:04.782610
3938 23:19:04.785425 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3939 23:19:04.785534
3940 23:19:04.788661 [CATrainingPosCal] consider 1 rank data
3941 23:19:04.792317 u2DelayCellTimex100 = 270/100 ps
3942 23:19:04.795518 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3943 23:19:04.798792 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3944 23:19:04.802091 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3945 23:19:04.805348 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3946 23:19:04.812046 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3947 23:19:04.815236 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3948 23:19:04.815315
3949 23:19:04.818323 CA PerBit enable=1, Macro0, CA PI delay=34
3950 23:19:04.818403
3951 23:19:04.821702 [CBTSetCACLKResult] CA Dly = 34
3952 23:19:04.821781 CS Dly: 4 (0~35)
3953 23:19:04.821845 ==
3954 23:19:04.825254 Dram Type= 6, Freq= 0, CH_0, rank 1
3955 23:19:04.831886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3956 23:19:04.831967 ==
3957 23:19:04.834879 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3958 23:19:04.841550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3959 23:19:04.844739 [CA 0] Center 37 (7~67) winsize 61
3960 23:19:04.848045 [CA 1] Center 37 (7~67) winsize 61
3961 23:19:04.851544 [CA 2] Center 35 (5~65) winsize 61
3962 23:19:04.854894 [CA 3] Center 34 (4~65) winsize 62
3963 23:19:04.858077 [CA 4] Center 34 (4~65) winsize 62
3964 23:19:04.861209 [CA 5] Center 34 (4~64) winsize 61
3965 23:19:04.861289
3966 23:19:04.864672 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3967 23:19:04.864752
3968 23:19:04.868141 [CATrainingPosCal] consider 2 rank data
3969 23:19:04.871407 u2DelayCellTimex100 = 270/100 ps
3970 23:19:04.874787 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3971 23:19:04.881049 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3972 23:19:04.884788 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3973 23:19:04.887784 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3974 23:19:04.891204 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3975 23:19:04.894535 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3976 23:19:04.894612
3977 23:19:04.897903 CA PerBit enable=1, Macro0, CA PI delay=34
3978 23:19:04.897975
3979 23:19:04.901288 [CBTSetCACLKResult] CA Dly = 34
3980 23:19:04.901360 CS Dly: 4 (0~36)
3981 23:19:04.904648
3982 23:19:04.907571 ----->DramcWriteLeveling(PI) begin...
3983 23:19:04.907678 ==
3984 23:19:04.910914 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 23:19:04.914261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 23:19:04.914342 ==
3987 23:19:04.917596 Write leveling (Byte 0): 35 => 35
3988 23:19:04.920814 Write leveling (Byte 1): 30 => 30
3989 23:19:04.924371 DramcWriteLeveling(PI) end<-----
3990 23:19:04.924451
3991 23:19:04.924514 ==
3992 23:19:04.927537 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 23:19:04.930848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 23:19:04.930933 ==
3995 23:19:04.934105 [Gating] SW mode calibration
3996 23:19:04.940837 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3997 23:19:04.947315 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3998 23:19:04.950560 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 23:19:04.954207 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 23:19:04.960648 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 23:19:04.963960 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4002 23:19:04.967233 0 9 16 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (1 1)
4003 23:19:04.973757 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4004 23:19:04.977236 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 23:19:04.980600 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 23:19:04.987207 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 23:19:04.990526 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 23:19:04.993626 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 23:19:05.000463 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4010 23:19:05.003720 0 10 16 | B1->B0 | 3333 3b3b | 0 0 | (1 1) (0 0)
4011 23:19:05.007226 0 10 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4012 23:19:05.013682 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 23:19:05.016875 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 23:19:05.020598 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 23:19:05.026995 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 23:19:05.030301 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 23:19:05.033639 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4018 23:19:05.036771 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4019 23:19:05.043597 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 23:19:05.046954 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 23:19:05.050241 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 23:19:05.056691 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 23:19:05.060006 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 23:19:05.063269 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 23:19:05.069857 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:19:05.073071 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 23:19:05.076705 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 23:19:05.083227 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 23:19:05.086599 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 23:19:05.089938 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 23:19:05.096602 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 23:19:05.099702 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 23:19:05.103059 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4034 23:19:05.106657 Total UI for P1: 0, mck2ui 16
4035 23:19:05.109657 best dqsien dly found for B0: ( 0, 13, 10)
4036 23:19:05.116700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4037 23:19:05.119697 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 23:19:05.123135 Total UI for P1: 0, mck2ui 16
4039 23:19:05.126135 best dqsien dly found for B1: ( 0, 13, 18)
4040 23:19:05.129559 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4041 23:19:05.133007 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4042 23:19:05.133081
4043 23:19:05.136217 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4044 23:19:05.139670 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4045 23:19:05.142872 [Gating] SW calibration Done
4046 23:19:05.142942 ==
4047 23:19:05.145949 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 23:19:05.152906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 23:19:05.152985 ==
4050 23:19:05.153049 RX Vref Scan: 0
4051 23:19:05.153108
4052 23:19:05.156187 RX Vref 0 -> 0, step: 1
4053 23:19:05.156260
4054 23:19:05.159515 RX Delay -230 -> 252, step: 16
4055 23:19:05.162674 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4056 23:19:05.165974 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4057 23:19:05.169344 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4058 23:19:05.176042 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4059 23:19:05.179414 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4060 23:19:05.182551 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4061 23:19:05.185929 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4062 23:19:05.189486 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4063 23:19:05.196134 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4064 23:19:05.199507 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4065 23:19:05.202587 iDelay=218, Bit 10, Center 25 (-150 ~ 201) 352
4066 23:19:05.205794 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4067 23:19:05.212556 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4068 23:19:05.215839 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4069 23:19:05.219357 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4070 23:19:05.222615 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4071 23:19:05.225843 ==
4072 23:19:05.225954 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 23:19:05.232400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 23:19:05.232484 ==
4075 23:19:05.232549 DQS Delay:
4076 23:19:05.235802 DQS0 = 0, DQS1 = 0
4077 23:19:05.235884 DQM Delay:
4078 23:19:05.238964 DQM0 = 38, DQM1 = 29
4079 23:19:05.239071 DQ Delay:
4080 23:19:05.242191 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4081 23:19:05.245731 DQ4 =41, DQ5 =17, DQ6 =57, DQ7 =49
4082 23:19:05.248843 DQ8 =17, DQ9 =17, DQ10 =25, DQ11 =25
4083 23:19:05.252385 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4084 23:19:05.252467
4085 23:19:05.252532
4086 23:19:05.252593 ==
4087 23:19:05.255755 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 23:19:05.259041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 23:19:05.259125 ==
4090 23:19:05.259191
4091 23:19:05.259252
4092 23:19:05.262015 TX Vref Scan disable
4093 23:19:05.265367 == TX Byte 0 ==
4094 23:19:05.269007 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4095 23:19:05.272195 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4096 23:19:05.275338 == TX Byte 1 ==
4097 23:19:05.278770 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4098 23:19:05.282196 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4099 23:19:05.282294 ==
4100 23:19:05.285395 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 23:19:05.292039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 23:19:05.292169 ==
4103 23:19:05.292299
4104 23:19:05.292422
4105 23:19:05.292515 TX Vref Scan disable
4106 23:19:05.296146 == TX Byte 0 ==
4107 23:19:05.299650 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4108 23:19:05.306168 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4109 23:19:05.306254 == TX Byte 1 ==
4110 23:19:05.309680 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4111 23:19:05.316348 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4112 23:19:05.316482
4113 23:19:05.316614 [DATLAT]
4114 23:19:05.316740 Freq=600, CH0 RK0
4115 23:19:05.316825
4116 23:19:05.319643 DATLAT Default: 0x9
4117 23:19:05.319740 0, 0xFFFF, sum = 0
4118 23:19:05.322839 1, 0xFFFF, sum = 0
4119 23:19:05.325993 2, 0xFFFF, sum = 0
4120 23:19:05.326090 3, 0xFFFF, sum = 0
4121 23:19:05.329759 4, 0xFFFF, sum = 0
4122 23:19:05.329858 5, 0xFFFF, sum = 0
4123 23:19:05.332896 6, 0xFFFF, sum = 0
4124 23:19:05.333037 7, 0xFFFF, sum = 0
4125 23:19:05.333120 8, 0x0, sum = 1
4126 23:19:05.336378 9, 0x0, sum = 2
4127 23:19:05.336478 10, 0x0, sum = 3
4128 23:19:05.339734 11, 0x0, sum = 4
4129 23:19:05.339832 best_step = 9
4130 23:19:05.339929
4131 23:19:05.340004 ==
4132 23:19:05.342941 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 23:19:05.349288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 23:19:05.349386 ==
4135 23:19:05.349452 RX Vref Scan: 1
4136 23:19:05.349552
4137 23:19:05.352659 RX Vref 0 -> 0, step: 1
4138 23:19:05.352787
4139 23:19:05.356217 RX Delay -195 -> 252, step: 8
4140 23:19:05.356315
4141 23:19:05.359536 Set Vref, RX VrefLevel [Byte0]: 60
4142 23:19:05.362685 [Byte1]: 50
4143 23:19:05.362783
4144 23:19:05.365819 Final RX Vref Byte 0 = 60 to rank0
4145 23:19:05.369218 Final RX Vref Byte 1 = 50 to rank0
4146 23:19:05.372261 Final RX Vref Byte 0 = 60 to rank1
4147 23:19:05.375660 Final RX Vref Byte 1 = 50 to rank1==
4148 23:19:05.379150 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 23:19:05.382489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 23:19:05.382597 ==
4151 23:19:05.385804 DQS Delay:
4152 23:19:05.385903 DQS0 = 0, DQS1 = 0
4153 23:19:05.389096 DQM Delay:
4154 23:19:05.389196 DQM0 = 34, DQM1 = 29
4155 23:19:05.389302 DQ Delay:
4156 23:19:05.392358 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4157 23:19:05.395631 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =48
4158 23:19:05.398977 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4159 23:19:05.402211 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4160 23:19:05.402285
4161 23:19:05.402348
4162 23:19:05.412201 [DQSOSCAuto] RK0, (LSB)MR18= 0x4241, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4163 23:19:05.415617 CH0 RK0: MR19=808, MR18=4241
4164 23:19:05.422269 CH0_RK0: MR19=0x808, MR18=0x4241, DQSOSC=397, MR23=63, INC=166, DEC=110
4165 23:19:05.422347
4166 23:19:05.425493 ----->DramcWriteLeveling(PI) begin...
4167 23:19:05.425585 ==
4168 23:19:05.428775 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 23:19:05.431920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 23:19:05.431994 ==
4171 23:19:05.435451 Write leveling (Byte 0): 32 => 32
4172 23:19:05.438798 Write leveling (Byte 1): 30 => 30
4173 23:19:05.442089 DramcWriteLeveling(PI) end<-----
4174 23:19:05.442175
4175 23:19:05.442266 ==
4176 23:19:05.445281 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 23:19:05.448510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 23:19:05.448610 ==
4179 23:19:05.451784 [Gating] SW mode calibration
4180 23:19:05.458435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4181 23:19:05.465059 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4182 23:19:05.468348 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 23:19:05.471753 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 23:19:05.478183 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 23:19:05.481484 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4186 23:19:05.484935 0 9 16 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
4187 23:19:05.491490 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 23:19:05.494594 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 23:19:05.497901 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 23:19:05.504654 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 23:19:05.508042 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 23:19:05.511475 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 23:19:05.517736 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4194 23:19:05.521146 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
4195 23:19:05.524563 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 23:19:05.531162 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 23:19:05.534396 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 23:19:05.537628 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 23:19:05.544344 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 23:19:05.547557 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 23:19:05.551084 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4202 23:19:05.557675 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4203 23:19:05.560981 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 23:19:05.564077 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 23:19:05.570814 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 23:19:05.574206 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 23:19:05.577614 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 23:19:05.584335 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:19:05.587250 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:19:05.590566 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 23:19:05.597383 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 23:19:05.600723 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 23:19:05.603795 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 23:19:05.610388 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 23:19:05.613938 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 23:19:05.617161 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 23:19:05.623931 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4218 23:19:05.627126 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4219 23:19:05.630385 Total UI for P1: 0, mck2ui 16
4220 23:19:05.633770 best dqsien dly found for B0: ( 0, 13, 12)
4221 23:19:05.636943 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 23:19:05.640336 Total UI for P1: 0, mck2ui 16
4223 23:19:05.643666 best dqsien dly found for B1: ( 0, 13, 18)
4224 23:19:05.646910 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4225 23:19:05.650548 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4226 23:19:05.650629
4227 23:19:05.656896 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4228 23:19:05.660520 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4229 23:19:05.660601 [Gating] SW calibration Done
4230 23:19:05.663763 ==
4231 23:19:05.667024 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 23:19:05.670233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 23:19:05.670315 ==
4234 23:19:05.670379 RX Vref Scan: 0
4235 23:19:05.670439
4236 23:19:05.673594 RX Vref 0 -> 0, step: 1
4237 23:19:05.673674
4238 23:19:05.676859 RX Delay -230 -> 252, step: 16
4239 23:19:05.679796 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4240 23:19:05.684052 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4241 23:19:05.689734 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4242 23:19:05.693008 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4243 23:19:05.696370 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4244 23:19:05.699717 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4245 23:19:05.706359 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4246 23:19:05.709662 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4247 23:19:05.712813 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4248 23:19:05.716397 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4249 23:19:05.723041 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4250 23:19:05.725988 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4251 23:19:05.729146 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4252 23:19:05.732572 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4253 23:19:05.739277 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4254 23:19:05.742665 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4255 23:19:05.742741 ==
4256 23:19:05.745894 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 23:19:05.749250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 23:19:05.749348 ==
4259 23:19:05.752525 DQS Delay:
4260 23:19:05.752625 DQS0 = 0, DQS1 = 0
4261 23:19:05.752718 DQM Delay:
4262 23:19:05.755838 DQM0 = 36, DQM1 = 28
4263 23:19:05.755962 DQ Delay:
4264 23:19:05.759415 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4265 23:19:05.762490 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4266 23:19:05.765792 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4267 23:19:05.769190 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4268 23:19:05.769353
4269 23:19:05.769449
4270 23:19:05.769542 ==
4271 23:19:05.772641 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 23:19:05.779013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 23:19:05.779133 ==
4274 23:19:05.779224
4275 23:19:05.779314
4276 23:19:05.779403 TX Vref Scan disable
4277 23:19:05.782757 == TX Byte 0 ==
4278 23:19:05.785730 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4279 23:19:05.792337 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4280 23:19:05.792451 == TX Byte 1 ==
4281 23:19:05.795592 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4282 23:19:05.802415 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4283 23:19:05.802524 ==
4284 23:19:05.805815 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 23:19:05.808929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 23:19:05.809010 ==
4287 23:19:05.809075
4288 23:19:05.809135
4289 23:19:05.812313 TX Vref Scan disable
4290 23:19:05.815672 == TX Byte 0 ==
4291 23:19:05.819127 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4292 23:19:05.822496 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4293 23:19:05.825635 == TX Byte 1 ==
4294 23:19:05.828952 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4295 23:19:05.832157 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4296 23:19:05.832250
4297 23:19:05.832331 [DATLAT]
4298 23:19:05.835585 Freq=600, CH0 RK1
4299 23:19:05.835666
4300 23:19:05.838975 DATLAT Default: 0x9
4301 23:19:05.839055 0, 0xFFFF, sum = 0
4302 23:19:05.842004 1, 0xFFFF, sum = 0
4303 23:19:05.842086 2, 0xFFFF, sum = 0
4304 23:19:05.845370 3, 0xFFFF, sum = 0
4305 23:19:05.845451 4, 0xFFFF, sum = 0
4306 23:19:05.848765 5, 0xFFFF, sum = 0
4307 23:19:05.848847 6, 0xFFFF, sum = 0
4308 23:19:05.852005 7, 0xFFFF, sum = 0
4309 23:19:05.852086 8, 0x0, sum = 1
4310 23:19:05.855598 9, 0x0, sum = 2
4311 23:19:05.855680 10, 0x0, sum = 3
4312 23:19:05.855744 11, 0x0, sum = 4
4313 23:19:05.858815 best_step = 9
4314 23:19:05.858926
4315 23:19:05.859024 ==
4316 23:19:05.861920 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 23:19:05.865204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 23:19:05.865303 ==
4319 23:19:05.868673 RX Vref Scan: 0
4320 23:19:05.868770
4321 23:19:05.868861 RX Vref 0 -> 0, step: 1
4322 23:19:05.872077
4323 23:19:05.872158 RX Delay -195 -> 252, step: 8
4324 23:19:05.879751 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4325 23:19:05.883175 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4326 23:19:05.886480 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4327 23:19:05.889583 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4328 23:19:05.896307 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4329 23:19:05.899752 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4330 23:19:05.902710 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4331 23:19:05.906054 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4332 23:19:05.912729 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4333 23:19:05.916085 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4334 23:19:05.919430 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4335 23:19:05.922722 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4336 23:19:05.926140 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4337 23:19:05.932484 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4338 23:19:05.936060 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4339 23:19:05.939478 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4340 23:19:05.939547 ==
4341 23:19:05.942603 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 23:19:05.949030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 23:19:05.949140 ==
4344 23:19:05.949242 DQS Delay:
4345 23:19:05.949332 DQS0 = 0, DQS1 = 0
4346 23:19:05.952481 DQM Delay:
4347 23:19:05.952578 DQM0 = 33, DQM1 = 28
4348 23:19:05.955809 DQ Delay:
4349 23:19:05.959092 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4350 23:19:05.962552 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4351 23:19:05.965914 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4352 23:19:05.969198 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4353 23:19:05.969279
4354 23:19:05.969343
4355 23:19:05.975820 [DQSOSCAuto] RK1, (LSB)MR18= 0x6737, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4356 23:19:05.979052 CH0 RK1: MR19=808, MR18=6737
4357 23:19:05.985699 CH0_RK1: MR19=0x808, MR18=0x6737, DQSOSC=390, MR23=63, INC=172, DEC=114
4358 23:19:05.989012 [RxdqsGatingPostProcess] freq 600
4359 23:19:05.992620 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4360 23:19:05.996012 Pre-setting of DQS Precalculation
4361 23:19:06.002346 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4362 23:19:06.002449 ==
4363 23:19:06.005820 Dram Type= 6, Freq= 0, CH_1, rank 0
4364 23:19:06.008929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 23:19:06.009029 ==
4366 23:19:06.015884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4367 23:19:06.018808 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4368 23:19:06.023346 [CA 0] Center 36 (6~66) winsize 61
4369 23:19:06.026761 [CA 1] Center 36 (6~67) winsize 62
4370 23:19:06.030083 [CA 2] Center 34 (4~65) winsize 62
4371 23:19:06.033460 [CA 3] Center 34 (4~65) winsize 62
4372 23:19:06.036456 [CA 4] Center 35 (5~65) winsize 61
4373 23:19:06.039638 [CA 5] Center 34 (4~65) winsize 62
4374 23:19:06.039738
4375 23:19:06.043283 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4376 23:19:06.043384
4377 23:19:06.046619 [CATrainingPosCal] consider 1 rank data
4378 23:19:06.049835 u2DelayCellTimex100 = 270/100 ps
4379 23:19:06.053049 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4380 23:19:06.059582 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4381 23:19:06.062868 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4382 23:19:06.066261 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4383 23:19:06.069524 CA4 delay=35 (5~65),Diff = 1 PI (9 cell)
4384 23:19:06.072826 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4385 23:19:06.072931
4386 23:19:06.076245 CA PerBit enable=1, Macro0, CA PI delay=34
4387 23:19:06.076350
4388 23:19:06.079501 [CBTSetCACLKResult] CA Dly = 34
4389 23:19:06.082782 CS Dly: 6 (0~37)
4390 23:19:06.082882 ==
4391 23:19:06.085996 Dram Type= 6, Freq= 0, CH_1, rank 1
4392 23:19:06.089502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 23:19:06.089602 ==
4394 23:19:06.092811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4395 23:19:06.099547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4396 23:19:06.103620 [CA 0] Center 36 (6~67) winsize 62
4397 23:19:06.106727 [CA 1] Center 36 (6~67) winsize 62
4398 23:19:06.109894 [CA 2] Center 34 (4~65) winsize 62
4399 23:19:06.113227 [CA 3] Center 34 (4~65) winsize 62
4400 23:19:06.116782 [CA 4] Center 34 (4~65) winsize 62
4401 23:19:06.120199 [CA 5] Center 34 (4~65) winsize 62
4402 23:19:06.120280
4403 23:19:06.123485 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4404 23:19:06.123567
4405 23:19:06.126519 [CATrainingPosCal] consider 2 rank data
4406 23:19:06.129953 u2DelayCellTimex100 = 270/100 ps
4407 23:19:06.133023 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4408 23:19:06.139878 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4409 23:19:06.143147 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4410 23:19:06.146408 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4411 23:19:06.149881 CA4 delay=35 (5~65),Diff = 1 PI (9 cell)
4412 23:19:06.152960 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4413 23:19:06.153043
4414 23:19:06.156258 CA PerBit enable=1, Macro0, CA PI delay=34
4415 23:19:06.156340
4416 23:19:06.159788 [CBTSetCACLKResult] CA Dly = 34
4417 23:19:06.163105 CS Dly: 6 (0~37)
4418 23:19:06.163186
4419 23:19:06.166268 ----->DramcWriteLeveling(PI) begin...
4420 23:19:06.166350 ==
4421 23:19:06.169700 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 23:19:06.172633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 23:19:06.172716 ==
4424 23:19:06.176018 Write leveling (Byte 0): 28 => 28
4425 23:19:06.179319 Write leveling (Byte 1): 31 => 31
4426 23:19:06.182615 DramcWriteLeveling(PI) end<-----
4427 23:19:06.182695
4428 23:19:06.182758 ==
4429 23:19:06.186034 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 23:19:06.189306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 23:19:06.189386 ==
4432 23:19:06.194773 [Gating] SW mode calibration
4433 23:19:06.199337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4434 23:19:06.206223 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4435 23:19:06.209345 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 23:19:06.212568 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 23:19:06.219077 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 23:19:06.222531 0 9 12 | B1->B0 | 3030 3131 | 1 1 | (1 0) (1 1)
4439 23:19:06.225768 0 9 16 | B1->B0 | 2626 2424 | 0 1 | (1 0) (1 0)
4440 23:19:06.232486 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 23:19:06.235821 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 23:19:06.239261 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 23:19:06.245670 0 10 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4444 23:19:06.248927 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 23:19:06.252183 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 23:19:06.259041 0 10 12 | B1->B0 | 2f2f 2d2d | 0 1 | (0 0) (0 0)
4447 23:19:06.262537 0 10 16 | B1->B0 | 3e3e 4141 | 1 0 | (0 0) (0 0)
4448 23:19:06.265446 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 23:19:06.272370 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 23:19:06.275760 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 23:19:06.279141 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 23:19:06.285801 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 23:19:06.288888 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 23:19:06.292186 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 23:19:06.295483 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 23:19:06.301965 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 23:19:06.305558 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 23:19:06.308576 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 23:19:06.315144 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 23:19:06.318868 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 23:19:06.321938 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 23:19:06.328483 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 23:19:06.331741 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 23:19:06.335480 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 23:19:06.341882 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 23:19:06.345245 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 23:19:06.348595 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 23:19:06.355152 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 23:19:06.358502 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 23:19:06.361773 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4471 23:19:06.364951 Total UI for P1: 0, mck2ui 16
4472 23:19:06.368502 best dqsien dly found for B0: ( 0, 13, 10)
4473 23:19:06.374899 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 23:19:06.374978 Total UI for P1: 0, mck2ui 16
4475 23:19:06.381561 best dqsien dly found for B1: ( 0, 13, 12)
4476 23:19:06.384930 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4477 23:19:06.388101 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4478 23:19:06.388177
4479 23:19:06.391348 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4480 23:19:06.394860 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4481 23:19:06.398183 [Gating] SW calibration Done
4482 23:19:06.398254 ==
4483 23:19:06.401579 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 23:19:06.404811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 23:19:06.404885 ==
4486 23:19:06.408005 RX Vref Scan: 0
4487 23:19:06.408073
4488 23:19:06.408137 RX Vref 0 -> 0, step: 1
4489 23:19:06.411237
4490 23:19:06.411310 RX Delay -230 -> 252, step: 16
4491 23:19:06.418247 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4492 23:19:06.421488 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4493 23:19:06.424837 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4494 23:19:06.428094 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4495 23:19:06.434600 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4496 23:19:06.438007 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4497 23:19:06.441339 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4498 23:19:06.444568 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4499 23:19:06.447962 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4500 23:19:06.454519 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4501 23:19:06.457825 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4502 23:19:06.461037 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4503 23:19:06.464636 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4504 23:19:06.471129 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4505 23:19:06.474514 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4506 23:19:06.477747 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4507 23:19:06.477827 ==
4508 23:19:06.481243 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 23:19:06.484332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 23:19:06.487734 ==
4511 23:19:06.487808 DQS Delay:
4512 23:19:06.487875 DQS0 = 0, DQS1 = 0
4513 23:19:06.490844 DQM Delay:
4514 23:19:06.490916 DQM0 = 39, DQM1 = 28
4515 23:19:06.494097 DQ Delay:
4516 23:19:06.497661 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4517 23:19:06.497734 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4518 23:19:06.501042 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4519 23:19:06.504135 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4520 23:19:06.507490
4521 23:19:06.507558
4522 23:19:06.507616 ==
4523 23:19:06.510728 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 23:19:06.513942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 23:19:06.514017 ==
4526 23:19:06.514077
4527 23:19:06.514133
4528 23:19:06.517363 TX Vref Scan disable
4529 23:19:06.517431 == TX Byte 0 ==
4530 23:19:06.523897 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4531 23:19:06.527213 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4532 23:19:06.527279 == TX Byte 1 ==
4533 23:19:06.533859 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4534 23:19:06.537132 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4535 23:19:06.537208 ==
4536 23:19:06.540406 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 23:19:06.543553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 23:19:06.543663 ==
4539 23:19:06.543729
4540 23:19:06.546923
4541 23:19:06.547048 TX Vref Scan disable
4542 23:19:06.550439 == TX Byte 0 ==
4543 23:19:06.553690 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4544 23:19:06.560019 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4545 23:19:06.560202 == TX Byte 1 ==
4546 23:19:06.563497 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4547 23:19:06.569993 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4548 23:19:06.570078
4549 23:19:06.570157 [DATLAT]
4550 23:19:06.570262 Freq=600, CH1 RK0
4551 23:19:06.570367
4552 23:19:06.573393 DATLAT Default: 0x9
4553 23:19:06.576947 0, 0xFFFF, sum = 0
4554 23:19:06.577037 1, 0xFFFF, sum = 0
4555 23:19:06.579904 2, 0xFFFF, sum = 0
4556 23:19:06.579989 3, 0xFFFF, sum = 0
4557 23:19:06.583357 4, 0xFFFF, sum = 0
4558 23:19:06.583444 5, 0xFFFF, sum = 0
4559 23:19:06.586476 6, 0xFFFF, sum = 0
4560 23:19:06.586557 7, 0xFFFF, sum = 0
4561 23:19:06.589768 8, 0x0, sum = 1
4562 23:19:06.589850 9, 0x0, sum = 2
4563 23:19:06.593074 10, 0x0, sum = 3
4564 23:19:06.593190 11, 0x0, sum = 4
4565 23:19:06.593284 best_step = 9
4566 23:19:06.593378
4567 23:19:06.596465 ==
4568 23:19:06.599886 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 23:19:06.603007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 23:19:06.603081 ==
4571 23:19:06.603156 RX Vref Scan: 1
4572 23:19:06.603216
4573 23:19:06.606474 RX Vref 0 -> 0, step: 1
4574 23:19:06.606551
4575 23:19:06.609656 RX Delay -195 -> 252, step: 8
4576 23:19:06.609732
4577 23:19:06.612967 Set Vref, RX VrefLevel [Byte0]: 57
4578 23:19:06.616485 [Byte1]: 51
4579 23:19:06.616608
4580 23:19:06.619775 Final RX Vref Byte 0 = 57 to rank0
4581 23:19:06.623064 Final RX Vref Byte 1 = 51 to rank0
4582 23:19:06.626042 Final RX Vref Byte 0 = 57 to rank1
4583 23:19:06.629399 Final RX Vref Byte 1 = 51 to rank1==
4584 23:19:06.632765 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 23:19:06.636039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 23:19:06.639367 ==
4587 23:19:06.639485 DQS Delay:
4588 23:19:06.639577 DQS0 = 0, DQS1 = 0
4589 23:19:06.642684 DQM Delay:
4590 23:19:06.642822 DQM0 = 41, DQM1 = 32
4591 23:19:06.646269 DQ Delay:
4592 23:19:06.646352 DQ0 =48, DQ1 =36, DQ2 =28, DQ3 =36
4593 23:19:06.649451 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =36
4594 23:19:06.652535 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4595 23:19:06.655956 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4596 23:19:06.656072
4597 23:19:06.659284
4598 23:19:06.665909 [DQSOSCAuto] RK0, (LSB)MR18= 0x202d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4599 23:19:06.669415 CH1 RK0: MR19=808, MR18=202D
4600 23:19:06.676034 CH1_RK0: MR19=0x808, MR18=0x202D, DQSOSC=401, MR23=63, INC=163, DEC=108
4601 23:19:06.676147
4602 23:19:06.679465 ----->DramcWriteLeveling(PI) begin...
4603 23:19:06.679562 ==
4604 23:19:06.682780 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 23:19:06.685854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 23:19:06.685971 ==
4607 23:19:06.689003 Write leveling (Byte 0): 30 => 30
4608 23:19:06.692405 Write leveling (Byte 1): 30 => 30
4609 23:19:06.695612 DramcWriteLeveling(PI) end<-----
4610 23:19:06.695708
4611 23:19:06.695780 ==
4612 23:19:06.698906 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 23:19:06.702346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 23:19:06.702433 ==
4615 23:19:06.705436 [Gating] SW mode calibration
4616 23:19:06.712228 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4617 23:19:06.718765 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4618 23:19:06.722065 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 23:19:06.728564 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4620 23:19:06.732222 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4621 23:19:06.735222 0 9 12 | B1->B0 | 3333 2929 | 0 0 | (0 0) (0 0)
4622 23:19:06.741867 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4623 23:19:06.745250 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 23:19:06.748549 0 9 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4625 23:19:06.755101 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 23:19:06.758514 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 23:19:06.761595 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 23:19:06.768276 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4629 23:19:06.771555 0 10 12 | B1->B0 | 2b2b 3939 | 0 0 | (0 0) (0 0)
4630 23:19:06.774885 0 10 16 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
4631 23:19:06.781502 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 23:19:06.784830 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 23:19:06.788253 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 23:19:06.794750 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 23:19:06.798008 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 23:19:06.801323 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 23:19:06.807723 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 23:19:06.810979 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 23:19:06.814525 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 23:19:06.820926 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 23:19:06.824283 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 23:19:06.827615 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 23:19:06.834353 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 23:19:06.837514 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 23:19:06.840815 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 23:19:06.844050 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 23:19:06.850734 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 23:19:06.854077 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 23:19:06.857413 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 23:19:06.863780 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 23:19:06.867252 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 23:19:06.870514 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4653 23:19:06.877393 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4654 23:19:06.880500 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 23:19:06.883922 Total UI for P1: 0, mck2ui 16
4656 23:19:06.887461 best dqsien dly found for B0: ( 0, 13, 12)
4657 23:19:06.890746 Total UI for P1: 0, mck2ui 16
4658 23:19:06.893971 best dqsien dly found for B1: ( 0, 13, 10)
4659 23:19:06.897388 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4660 23:19:06.900584 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4661 23:19:06.900691
4662 23:19:06.904042 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4663 23:19:06.907473 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4664 23:19:06.910348 [Gating] SW calibration Done
4665 23:19:06.910424 ==
4666 23:19:06.913762 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 23:19:06.920529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 23:19:06.920639 ==
4669 23:19:06.920734 RX Vref Scan: 0
4670 23:19:06.920827
4671 23:19:06.923451 RX Vref 0 -> 0, step: 1
4672 23:19:06.923552
4673 23:19:06.926949 RX Delay -230 -> 252, step: 16
4674 23:19:06.930153 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4675 23:19:06.933769 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4676 23:19:06.937078 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4677 23:19:06.943532 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4678 23:19:06.946897 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4679 23:19:06.949969 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4680 23:19:06.953617 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4681 23:19:06.960148 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4682 23:19:06.963315 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4683 23:19:06.966627 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4684 23:19:06.970113 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4685 23:19:06.976924 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4686 23:19:06.979838 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4687 23:19:06.983003 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4688 23:19:06.986695 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4689 23:19:06.992943 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4690 23:19:06.993033 ==
4691 23:19:06.996235 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 23:19:06.999587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 23:19:06.999671 ==
4694 23:19:06.999737 DQS Delay:
4695 23:19:07.002950 DQS0 = 0, DQS1 = 0
4696 23:19:07.003032 DQM Delay:
4697 23:19:07.006368 DQM0 = 38, DQM1 = 30
4698 23:19:07.006450 DQ Delay:
4699 23:19:07.009499 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4700 23:19:07.012914 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4701 23:19:07.016219 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4702 23:19:07.019554 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4703 23:19:07.019643
4704 23:19:07.019709
4705 23:19:07.019770 ==
4706 23:19:07.022830 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 23:19:07.026066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 23:19:07.026153 ==
4709 23:19:07.029270
4710 23:19:07.029392
4711 23:19:07.029509 TX Vref Scan disable
4712 23:19:07.032645 == TX Byte 0 ==
4713 23:19:07.035874 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4714 23:19:07.039374 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4715 23:19:07.042479 == TX Byte 1 ==
4716 23:19:07.045834 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4717 23:19:07.049228 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4718 23:19:07.049343 ==
4719 23:19:07.052488 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 23:19:07.059030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 23:19:07.059164 ==
4722 23:19:07.059236
4723 23:19:07.059298
4724 23:19:07.062258 TX Vref Scan disable
4725 23:19:07.062328 == TX Byte 0 ==
4726 23:19:07.068836 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4727 23:19:07.072361 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4728 23:19:07.072441 == TX Byte 1 ==
4729 23:19:07.079135 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4730 23:19:07.082179 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4731 23:19:07.082287
4732 23:19:07.082378 [DATLAT]
4733 23:19:07.085488 Freq=600, CH1 RK1
4734 23:19:07.085590
4735 23:19:07.085682 DATLAT Default: 0x9
4736 23:19:07.088784 0, 0xFFFF, sum = 0
4737 23:19:07.088859 1, 0xFFFF, sum = 0
4738 23:19:07.092204 2, 0xFFFF, sum = 0
4739 23:19:07.092304 3, 0xFFFF, sum = 0
4740 23:19:07.095514 4, 0xFFFF, sum = 0
4741 23:19:07.095585 5, 0xFFFF, sum = 0
4742 23:19:07.098643 6, 0xFFFF, sum = 0
4743 23:19:07.102013 7, 0xFFFF, sum = 0
4744 23:19:07.102117 8, 0x0, sum = 1
4745 23:19:07.102212 9, 0x0, sum = 2
4746 23:19:07.105353 10, 0x0, sum = 3
4747 23:19:07.105455 11, 0x0, sum = 4
4748 23:19:07.108636 best_step = 9
4749 23:19:07.108733
4750 23:19:07.108821 ==
4751 23:19:07.111984 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 23:19:07.115119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 23:19:07.115222 ==
4754 23:19:07.118538 RX Vref Scan: 0
4755 23:19:07.118632
4756 23:19:07.118723 RX Vref 0 -> 0, step: 1
4757 23:19:07.118809
4758 23:19:07.121882 RX Delay -195 -> 252, step: 8
4759 23:19:07.129256 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4760 23:19:07.132390 iDelay=205, Bit 1, Center 36 (-115 ~ 188) 304
4761 23:19:07.135653 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4762 23:19:07.139060 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4763 23:19:07.145941 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4764 23:19:07.149345 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4765 23:19:07.152390 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4766 23:19:07.155837 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4767 23:19:07.158924 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4768 23:19:07.165740 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4769 23:19:07.169139 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4770 23:19:07.172170 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4771 23:19:07.175495 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4772 23:19:07.182200 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4773 23:19:07.185688 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4774 23:19:07.188946 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4775 23:19:07.189027 ==
4776 23:19:07.192170 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 23:19:07.198926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 23:19:07.199023 ==
4779 23:19:07.199090 DQS Delay:
4780 23:19:07.199151 DQS0 = 0, DQS1 = 0
4781 23:19:07.202144 DQM Delay:
4782 23:19:07.202227 DQM0 = 37, DQM1 = 32
4783 23:19:07.205328 DQ Delay:
4784 23:19:07.208651 DQ0 =44, DQ1 =36, DQ2 =24, DQ3 =32
4785 23:19:07.208743 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4786 23:19:07.212188 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4787 23:19:07.218783 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4788 23:19:07.218895
4789 23:19:07.218963
4790 23:19:07.225415 [DQSOSCAuto] RK1, (LSB)MR18= 0x3656, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4791 23:19:07.228716 CH1 RK1: MR19=808, MR18=3656
4792 23:19:07.235249 CH1_RK1: MR19=0x808, MR18=0x3656, DQSOSC=393, MR23=63, INC=169, DEC=113
4793 23:19:07.238844 [RxdqsGatingPostProcess] freq 600
4794 23:19:07.242170 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4795 23:19:07.245515 Pre-setting of DQS Precalculation
4796 23:19:07.252091 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4797 23:19:07.258640 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4798 23:19:07.265420 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4799 23:19:07.265528
4800 23:19:07.265597
4801 23:19:07.268352 [Calibration Summary] 1200 Mbps
4802 23:19:07.268438 CH 0, Rank 0
4803 23:19:07.271687 SW Impedance : PASS
4804 23:19:07.274874 DUTY Scan : NO K
4805 23:19:07.274957 ZQ Calibration : PASS
4806 23:19:07.278612 Jitter Meter : NO K
4807 23:19:07.281654 CBT Training : PASS
4808 23:19:07.281754 Write leveling : PASS
4809 23:19:07.284933 RX DQS gating : PASS
4810 23:19:07.288382 RX DQ/DQS(RDDQC) : PASS
4811 23:19:07.288464 TX DQ/DQS : PASS
4812 23:19:07.291574 RX DATLAT : PASS
4813 23:19:07.291657 RX DQ/DQS(Engine): PASS
4814 23:19:07.295070 TX OE : NO K
4815 23:19:07.295151 All Pass.
4816 23:19:07.295215
4817 23:19:07.298206 CH 0, Rank 1
4818 23:19:07.298287 SW Impedance : PASS
4819 23:19:07.301592 DUTY Scan : NO K
4820 23:19:07.304800 ZQ Calibration : PASS
4821 23:19:07.304882 Jitter Meter : NO K
4822 23:19:07.308372 CBT Training : PASS
4823 23:19:07.311559 Write leveling : PASS
4824 23:19:07.311640 RX DQS gating : PASS
4825 23:19:07.314716 RX DQ/DQS(RDDQC) : PASS
4826 23:19:07.318179 TX DQ/DQS : PASS
4827 23:19:07.318260 RX DATLAT : PASS
4828 23:19:07.321540 RX DQ/DQS(Engine): PASS
4829 23:19:07.324654 TX OE : NO K
4830 23:19:07.324763 All Pass.
4831 23:19:07.324857
4832 23:19:07.324947 CH 1, Rank 0
4833 23:19:07.327769 SW Impedance : PASS
4834 23:19:07.331523 DUTY Scan : NO K
4835 23:19:07.331605 ZQ Calibration : PASS
4836 23:19:07.334526 Jitter Meter : NO K
4837 23:19:07.337912 CBT Training : PASS
4838 23:19:07.338009 Write leveling : PASS
4839 23:19:07.340997 RX DQS gating : PASS
4840 23:19:07.344305 RX DQ/DQS(RDDQC) : PASS
4841 23:19:07.344388 TX DQ/DQS : PASS
4842 23:19:07.347707 RX DATLAT : PASS
4843 23:19:07.351037 RX DQ/DQS(Engine): PASS
4844 23:19:07.351119 TX OE : NO K
4845 23:19:07.351185 All Pass.
4846 23:19:07.354476
4847 23:19:07.354558 CH 1, Rank 1
4848 23:19:07.357930 SW Impedance : PASS
4849 23:19:07.358013 DUTY Scan : NO K
4850 23:19:07.360867 ZQ Calibration : PASS
4851 23:19:07.360979 Jitter Meter : NO K
4852 23:19:07.364556 CBT Training : PASS
4853 23:19:07.367536 Write leveling : PASS
4854 23:19:07.367634 RX DQS gating : PASS
4855 23:19:07.371151 RX DQ/DQS(RDDQC) : PASS
4856 23:19:07.374225 TX DQ/DQS : PASS
4857 23:19:07.374306 RX DATLAT : PASS
4858 23:19:07.377692 RX DQ/DQS(Engine): PASS
4859 23:19:07.381060 TX OE : NO K
4860 23:19:07.381141 All Pass.
4861 23:19:07.381205
4862 23:19:07.384192 DramC Write-DBI off
4863 23:19:07.384273 PER_BANK_REFRESH: Hybrid Mode
4864 23:19:07.387521 TX_TRACKING: ON
4865 23:19:07.394571 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4866 23:19:07.397785 [FAST_K] Save calibration result to emmc
4867 23:19:07.404381 dramc_set_vcore_voltage set vcore to 662500
4868 23:19:07.404463 Read voltage for 933, 3
4869 23:19:07.407618 Vio18 = 0
4870 23:19:07.407703 Vcore = 662500
4871 23:19:07.407769 Vdram = 0
4872 23:19:07.411081 Vddq = 0
4873 23:19:07.411163 Vmddr = 0
4874 23:19:07.414234 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4875 23:19:07.420897 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4876 23:19:07.424299 MEM_TYPE=3, freq_sel=17
4877 23:19:07.427322 sv_algorithm_assistance_LP4_1600
4878 23:19:07.430661 ============ PULL DRAM RESETB DOWN ============
4879 23:19:07.433843 ========== PULL DRAM RESETB DOWN end =========
4880 23:19:07.440675 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4881 23:19:07.443886 ===================================
4882 23:19:07.443992 LPDDR4 DRAM CONFIGURATION
4883 23:19:07.447076 ===================================
4884 23:19:07.450444 EX_ROW_EN[0] = 0x0
4885 23:19:07.450526 EX_ROW_EN[1] = 0x0
4886 23:19:07.453747 LP4Y_EN = 0x0
4887 23:19:07.453852 WORK_FSP = 0x0
4888 23:19:07.457341 WL = 0x3
4889 23:19:07.460718 RL = 0x3
4890 23:19:07.460820 BL = 0x2
4891 23:19:07.463662 RPST = 0x0
4892 23:19:07.463738 RD_PRE = 0x0
4893 23:19:07.466983 WR_PRE = 0x1
4894 23:19:07.467056 WR_PST = 0x0
4895 23:19:07.470276 DBI_WR = 0x0
4896 23:19:07.470358 DBI_RD = 0x0
4897 23:19:07.473776 OTF = 0x1
4898 23:19:07.476918 ===================================
4899 23:19:07.480723 ===================================
4900 23:19:07.480811 ANA top config
4901 23:19:07.483643 ===================================
4902 23:19:07.487179 DLL_ASYNC_EN = 0
4903 23:19:07.490602 ALL_SLAVE_EN = 1
4904 23:19:07.490678 NEW_RANK_MODE = 1
4905 23:19:07.493857 DLL_IDLE_MODE = 1
4906 23:19:07.496800 LP45_APHY_COMB_EN = 1
4907 23:19:07.500079 TX_ODT_DIS = 1
4908 23:19:07.500153 NEW_8X_MODE = 1
4909 23:19:07.503718 ===================================
4910 23:19:07.506712 ===================================
4911 23:19:07.510389 data_rate = 1866
4912 23:19:07.513674 CKR = 1
4913 23:19:07.516839 DQ_P2S_RATIO = 8
4914 23:19:07.520405 ===================================
4915 23:19:07.523655 CA_P2S_RATIO = 8
4916 23:19:07.526694 DQ_CA_OPEN = 0
4917 23:19:07.529846 DQ_SEMI_OPEN = 0
4918 23:19:07.529921 CA_SEMI_OPEN = 0
4919 23:19:07.533448 CA_FULL_RATE = 0
4920 23:19:07.536478 DQ_CKDIV4_EN = 1
4921 23:19:07.539987 CA_CKDIV4_EN = 1
4922 23:19:07.543398 CA_PREDIV_EN = 0
4923 23:19:07.546460 PH8_DLY = 0
4924 23:19:07.546536 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4925 23:19:07.549787 DQ_AAMCK_DIV = 4
4926 23:19:07.553198 CA_AAMCK_DIV = 4
4927 23:19:07.556443 CA_ADMCK_DIV = 4
4928 23:19:07.559822 DQ_TRACK_CA_EN = 0
4929 23:19:07.563051 CA_PICK = 933
4930 23:19:07.563131 CA_MCKIO = 933
4931 23:19:07.566447 MCKIO_SEMI = 0
4932 23:19:07.569740 PLL_FREQ = 3732
4933 23:19:07.573159 DQ_UI_PI_RATIO = 32
4934 23:19:07.576584 CA_UI_PI_RATIO = 0
4935 23:19:07.579741 ===================================
4936 23:19:07.583025 ===================================
4937 23:19:07.586490 memory_type:LPDDR4
4938 23:19:07.586568 GP_NUM : 10
4939 23:19:07.589870 SRAM_EN : 1
4940 23:19:07.589945 MD32_EN : 0
4941 23:19:07.593104 ===================================
4942 23:19:07.596554 [ANA_INIT] >>>>>>>>>>>>>>
4943 23:19:07.599765 <<<<<< [CONFIGURE PHASE]: ANA_TX
4944 23:19:07.603089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4945 23:19:07.606469 ===================================
4946 23:19:07.609727 data_rate = 1866,PCW = 0X8f00
4947 23:19:07.612905 ===================================
4948 23:19:07.616190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4949 23:19:07.622861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 23:19:07.626169 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4951 23:19:07.632854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4952 23:19:07.635931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4953 23:19:07.639252 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4954 23:19:07.639334 [ANA_INIT] flow start
4955 23:19:07.642522 [ANA_INIT] PLL >>>>>>>>
4956 23:19:07.646156 [ANA_INIT] PLL <<<<<<<<
4957 23:19:07.646234 [ANA_INIT] MIDPI >>>>>>>>
4958 23:19:07.649395 [ANA_INIT] MIDPI <<<<<<<<
4959 23:19:07.652626 [ANA_INIT] DLL >>>>>>>>
4960 23:19:07.652705 [ANA_INIT] flow end
4961 23:19:07.659073 ============ LP4 DIFF to SE enter ============
4962 23:19:07.662719 ============ LP4 DIFF to SE exit ============
4963 23:19:07.665865 [ANA_INIT] <<<<<<<<<<<<<
4964 23:19:07.668936 [Flow] Enable top DCM control >>>>>
4965 23:19:07.672424 [Flow] Enable top DCM control <<<<<
4966 23:19:07.672514 Enable DLL master slave shuffle
4967 23:19:07.679173 ==============================================================
4968 23:19:07.682480 Gating Mode config
4969 23:19:07.685603 ==============================================================
4970 23:19:07.688847 Config description:
4971 23:19:07.699004 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4972 23:19:07.705686 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4973 23:19:07.708866 SELPH_MODE 0: By rank 1: By Phase
4974 23:19:07.715638 ==============================================================
4975 23:19:07.718934 GAT_TRACK_EN = 1
4976 23:19:07.722224 RX_GATING_MODE = 2
4977 23:19:07.725655 RX_GATING_TRACK_MODE = 2
4978 23:19:07.728971 SELPH_MODE = 1
4979 23:19:07.729046 PICG_EARLY_EN = 1
4980 23:19:07.731925 VALID_LAT_VALUE = 1
4981 23:19:07.738541 ==============================================================
4982 23:19:07.741805 Enter into Gating configuration >>>>
4983 23:19:07.745296 Exit from Gating configuration <<<<
4984 23:19:07.748582 Enter into DVFS_PRE_config >>>>>
4985 23:19:07.758582 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4986 23:19:07.761925 Exit from DVFS_PRE_config <<<<<
4987 23:19:07.765358 Enter into PICG configuration >>>>
4988 23:19:07.768636 Exit from PICG configuration <<<<
4989 23:19:07.771570 [RX_INPUT] configuration >>>>>
4990 23:19:07.775207 [RX_INPUT] configuration <<<<<
4991 23:19:07.781769 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4992 23:19:07.785203 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4993 23:19:07.791509 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4994 23:19:07.798450 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4995 23:19:07.805106 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4996 23:19:07.811446 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4997 23:19:07.814677 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4998 23:19:07.818111 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4999 23:19:07.821287 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5000 23:19:07.827861 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5001 23:19:07.831291 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5002 23:19:07.834560 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 23:19:07.838003 ===================================
5004 23:19:07.840903 LPDDR4 DRAM CONFIGURATION
5005 23:19:07.844323 ===================================
5006 23:19:07.844425 EX_ROW_EN[0] = 0x0
5007 23:19:07.847609 EX_ROW_EN[1] = 0x0
5008 23:19:07.850919 LP4Y_EN = 0x0
5009 23:19:07.851020 WORK_FSP = 0x0
5010 23:19:07.854207 WL = 0x3
5011 23:19:07.854320 RL = 0x3
5012 23:19:07.857470 BL = 0x2
5013 23:19:07.857578 RPST = 0x0
5014 23:19:07.860956 RD_PRE = 0x0
5015 23:19:07.861035 WR_PRE = 0x1
5016 23:19:07.863997 WR_PST = 0x0
5017 23:19:07.864109 DBI_WR = 0x0
5018 23:19:07.867394 DBI_RD = 0x0
5019 23:19:07.867469 OTF = 0x1
5020 23:19:07.870590 ===================================
5021 23:19:07.874292 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5022 23:19:07.880731 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5023 23:19:07.884165 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 23:19:07.887141 ===================================
5025 23:19:07.890639 LPDDR4 DRAM CONFIGURATION
5026 23:19:07.893974 ===================================
5027 23:19:07.894072 EX_ROW_EN[0] = 0x10
5028 23:19:07.897168 EX_ROW_EN[1] = 0x0
5029 23:19:07.900463 LP4Y_EN = 0x0
5030 23:19:07.900532 WORK_FSP = 0x0
5031 23:19:07.904049 WL = 0x3
5032 23:19:07.904124 RL = 0x3
5033 23:19:07.906979 BL = 0x2
5034 23:19:07.907061 RPST = 0x0
5035 23:19:07.910592 RD_PRE = 0x0
5036 23:19:07.910661 WR_PRE = 0x1
5037 23:19:07.913717 WR_PST = 0x0
5038 23:19:07.913791 DBI_WR = 0x0
5039 23:19:07.917194 DBI_RD = 0x0
5040 23:19:07.917287 OTF = 0x1
5041 23:19:07.920240 ===================================
5042 23:19:07.927012 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5043 23:19:07.931541 nWR fixed to 30
5044 23:19:07.934839 [ModeRegInit_LP4] CH0 RK0
5045 23:19:07.934913 [ModeRegInit_LP4] CH0 RK1
5046 23:19:07.938105 [ModeRegInit_LP4] CH1 RK0
5047 23:19:07.941481 [ModeRegInit_LP4] CH1 RK1
5048 23:19:07.941568 match AC timing 9
5049 23:19:07.947747 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5050 23:19:07.951024 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5051 23:19:07.954364 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5052 23:19:07.961051 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5053 23:19:07.964474 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5054 23:19:07.964574 ==
5055 23:19:07.967814 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 23:19:07.970948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 23:19:07.971022 ==
5058 23:19:07.977871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 23:19:07.984268 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5060 23:19:07.987549 [CA 0] Center 38 (8~69) winsize 62
5061 23:19:07.990979 [CA 1] Center 38 (8~69) winsize 62
5062 23:19:07.994308 [CA 2] Center 35 (5~66) winsize 62
5063 23:19:07.997714 [CA 3] Center 35 (5~66) winsize 62
5064 23:19:08.000928 [CA 4] Center 34 (4~65) winsize 62
5065 23:19:08.004355 [CA 5] Center 34 (4~64) winsize 61
5066 23:19:08.004454
5067 23:19:08.007556 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5068 23:19:08.007652
5069 23:19:08.010860 [CATrainingPosCal] consider 1 rank data
5070 23:19:08.014044 u2DelayCellTimex100 = 270/100 ps
5071 23:19:08.017295 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5072 23:19:08.020872 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5073 23:19:08.023974 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5074 23:19:08.027555 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5075 23:19:08.030648 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5076 23:19:08.037338 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5077 23:19:08.037442
5078 23:19:08.040643 CA PerBit enable=1, Macro0, CA PI delay=34
5079 23:19:08.040745
5080 23:19:08.043758 [CBTSetCACLKResult] CA Dly = 34
5081 23:19:08.043856 CS Dly: 7 (0~38)
5082 23:19:08.043944 ==
5083 23:19:08.047205 Dram Type= 6, Freq= 0, CH_0, rank 1
5084 23:19:08.050503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 23:19:08.053736 ==
5086 23:19:08.057064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5087 23:19:08.063895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5088 23:19:08.066882 [CA 0] Center 38 (8~69) winsize 62
5089 23:19:08.070525 [CA 1] Center 38 (8~69) winsize 62
5090 23:19:08.073676 [CA 2] Center 35 (5~66) winsize 62
5091 23:19:08.076928 [CA 3] Center 35 (5~66) winsize 62
5092 23:19:08.080225 [CA 4] Center 34 (4~65) winsize 62
5093 23:19:08.083767 [CA 5] Center 33 (3~64) winsize 62
5094 23:19:08.083896
5095 23:19:08.086660 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5096 23:19:08.086756
5097 23:19:08.090263 [CATrainingPosCal] consider 2 rank data
5098 23:19:08.093208 u2DelayCellTimex100 = 270/100 ps
5099 23:19:08.096895 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5100 23:19:08.099864 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5101 23:19:08.103200 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5102 23:19:08.110071 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5103 23:19:08.113453 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5104 23:19:08.116803 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5105 23:19:08.116917
5106 23:19:08.119983 CA PerBit enable=1, Macro0, CA PI delay=34
5107 23:19:08.120068
5108 23:19:08.123305 [CBTSetCACLKResult] CA Dly = 34
5109 23:19:08.123403 CS Dly: 7 (0~39)
5110 23:19:08.123492
5111 23:19:08.126576 ----->DramcWriteLeveling(PI) begin...
5112 23:19:08.126644 ==
5113 23:19:08.129864 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 23:19:08.136569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 23:19:08.136668 ==
5116 23:19:08.139812 Write leveling (Byte 0): 30 => 30
5117 23:19:08.143175 Write leveling (Byte 1): 28 => 28
5118 23:19:08.143269 DramcWriteLeveling(PI) end<-----
5119 23:19:08.146356
5120 23:19:08.146429 ==
5121 23:19:08.149625 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 23:19:08.152964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 23:19:08.153059 ==
5124 23:19:08.156633 [Gating] SW mode calibration
5125 23:19:08.162994 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5126 23:19:08.166429 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5127 23:19:08.173035 0 14 0 | B1->B0 | 2323 2f2f | 1 1 | (0 0) (1 1)
5128 23:19:08.176371 0 14 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5129 23:19:08.179295 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 23:19:08.186179 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 23:19:08.189177 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 23:19:08.192470 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 23:19:08.199261 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 23:19:08.202638 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5135 23:19:08.205848 0 15 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
5136 23:19:08.212608 0 15 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
5137 23:19:08.215754 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 23:19:08.219100 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 23:19:08.225624 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 23:19:08.229141 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 23:19:08.232559 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 23:19:08.238874 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 23:19:08.242231 1 0 0 | B1->B0 | 2e2e 403f | 0 1 | (1 1) (0 0)
5144 23:19:08.245689 1 0 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5145 23:19:08.252134 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 23:19:08.255811 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 23:19:08.258994 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 23:19:08.265909 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 23:19:08.268959 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 23:19:08.272186 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5151 23:19:08.278732 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5152 23:19:08.282080 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5153 23:19:08.285583 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5154 23:19:08.292230 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 23:19:08.295502 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 23:19:08.298841 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 23:19:08.305503 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 23:19:08.308867 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 23:19:08.311750 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 23:19:08.318414 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 23:19:08.321757 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 23:19:08.325218 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 23:19:08.331793 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 23:19:08.335123 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 23:19:08.338421 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 23:19:08.345155 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5167 23:19:08.348435 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5168 23:19:08.351724 Total UI for P1: 0, mck2ui 16
5169 23:19:08.354813 best dqsien dly found for B0: ( 1, 2, 28)
5170 23:19:08.358498 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5171 23:19:08.361442 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 23:19:08.365020 Total UI for P1: 0, mck2ui 16
5173 23:19:08.368241 best dqsien dly found for B1: ( 1, 3, 2)
5174 23:19:08.374870 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5175 23:19:08.377970 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5176 23:19:08.378071
5177 23:19:08.381197 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5178 23:19:08.384498 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5179 23:19:08.387912 [Gating] SW calibration Done
5180 23:19:08.388011 ==
5181 23:19:08.391513 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 23:19:08.394556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 23:19:08.394632 ==
5184 23:19:08.397915 RX Vref Scan: 0
5185 23:19:08.397982
5186 23:19:08.398042 RX Vref 0 -> 0, step: 1
5187 23:19:08.398104
5188 23:19:08.401262 RX Delay -80 -> 252, step: 8
5189 23:19:08.404643 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5190 23:19:08.407953 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5191 23:19:08.414595 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5192 23:19:08.417925 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5193 23:19:08.421245 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5194 23:19:08.424614 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5195 23:19:08.427750 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5196 23:19:08.430943 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5197 23:19:08.437617 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5198 23:19:08.440777 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5199 23:19:08.444170 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5200 23:19:08.447664 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5201 23:19:08.454097 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5202 23:19:08.457567 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5203 23:19:08.461025 iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208
5204 23:19:08.464045 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5205 23:19:08.464160 ==
5206 23:19:08.467251 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 23:19:08.470725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 23:19:08.473921 ==
5209 23:19:08.474031 DQS Delay:
5210 23:19:08.474161 DQS0 = 0, DQS1 = 0
5211 23:19:08.477411 DQM Delay:
5212 23:19:08.477545 DQM0 = 95, DQM1 = 84
5213 23:19:08.480702 DQ Delay:
5214 23:19:08.480819 DQ0 =99, DQ1 =95, DQ2 =91, DQ3 =91
5215 23:19:08.484041 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5216 23:19:08.487256 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5217 23:19:08.493837 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5218 23:19:08.493916
5219 23:19:08.493981
5220 23:19:08.494049 ==
5221 23:19:08.497197 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 23:19:08.500390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 23:19:08.500503 ==
5224 23:19:08.500595
5225 23:19:08.500692
5226 23:19:08.503603 TX Vref Scan disable
5227 23:19:08.503716 == TX Byte 0 ==
5228 23:19:08.510539 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5229 23:19:08.513440 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5230 23:19:08.513534 == TX Byte 1 ==
5231 23:19:08.520183 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5232 23:19:08.523559 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5233 23:19:08.523669 ==
5234 23:19:08.527064 Dram Type= 6, Freq= 0, CH_0, rank 0
5235 23:19:08.530252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5236 23:19:08.530365 ==
5237 23:19:08.530458
5238 23:19:08.530555
5239 23:19:08.533822 TX Vref Scan disable
5240 23:19:08.537108 == TX Byte 0 ==
5241 23:19:08.540395 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5242 23:19:08.543633 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5243 23:19:08.547004 == TX Byte 1 ==
5244 23:19:08.549969 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5245 23:19:08.553285 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5246 23:19:08.553395
5247 23:19:08.556709 [DATLAT]
5248 23:19:08.556814 Freq=933, CH0 RK0
5249 23:19:08.556911
5250 23:19:08.559895 DATLAT Default: 0xd
5251 23:19:08.559967 0, 0xFFFF, sum = 0
5252 23:19:08.563279 1, 0xFFFF, sum = 0
5253 23:19:08.563381 2, 0xFFFF, sum = 0
5254 23:19:08.566575 3, 0xFFFF, sum = 0
5255 23:19:08.566684 4, 0xFFFF, sum = 0
5256 23:19:08.569873 5, 0xFFFF, sum = 0
5257 23:19:08.569953 6, 0xFFFF, sum = 0
5258 23:19:08.573165 7, 0xFFFF, sum = 0
5259 23:19:08.576579 8, 0xFFFF, sum = 0
5260 23:19:08.576656 9, 0xFFFF, sum = 0
5261 23:19:08.579945 10, 0x0, sum = 1
5262 23:19:08.580030 11, 0x0, sum = 2
5263 23:19:08.580098 12, 0x0, sum = 3
5264 23:19:08.583059 13, 0x0, sum = 4
5265 23:19:08.583145 best_step = 11
5266 23:19:08.583211
5267 23:19:08.583294 ==
5268 23:19:08.586507 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 23:19:08.593177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 23:19:08.593275 ==
5271 23:19:08.593343 RX Vref Scan: 1
5272 23:19:08.593405
5273 23:19:08.596446 RX Vref 0 -> 0, step: 1
5274 23:19:08.596530
5275 23:19:08.599720 RX Delay -69 -> 252, step: 4
5276 23:19:08.599799
5277 23:19:08.602966 Set Vref, RX VrefLevel [Byte0]: 60
5278 23:19:08.606545 [Byte1]: 50
5279 23:19:08.606636
5280 23:19:08.609653 Final RX Vref Byte 0 = 60 to rank0
5281 23:19:08.612957 Final RX Vref Byte 1 = 50 to rank0
5282 23:19:08.616463 Final RX Vref Byte 0 = 60 to rank1
5283 23:19:08.619771 Final RX Vref Byte 1 = 50 to rank1==
5284 23:19:08.623064 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 23:19:08.626503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 23:19:08.626605 ==
5287 23:19:08.629703 DQS Delay:
5288 23:19:08.629802 DQS0 = 0, DQS1 = 0
5289 23:19:08.632528 DQM Delay:
5290 23:19:08.632635 DQM0 = 96, DQM1 = 83
5291 23:19:08.636210 DQ Delay:
5292 23:19:08.636324 DQ0 =96, DQ1 =96, DQ2 =94, DQ3 =94
5293 23:19:08.639410 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5294 23:19:08.642668 DQ8 =76, DQ9 =70, DQ10 =82, DQ11 =78
5295 23:19:08.646114 DQ12 =88, DQ13 =88, DQ14 =98, DQ15 =90
5296 23:19:08.649451
5297 23:19:08.649529
5298 23:19:08.655781 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5299 23:19:08.659478 CH0 RK0: MR19=505, MR18=1313
5300 23:19:08.665643 CH0_RK0: MR19=0x505, MR18=0x1313, DQSOSC=415, MR23=63, INC=62, DEC=41
5301 23:19:08.665718
5302 23:19:08.668895 ----->DramcWriteLeveling(PI) begin...
5303 23:19:08.668964 ==
5304 23:19:08.672496 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 23:19:08.675771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 23:19:08.675845 ==
5307 23:19:08.678934 Write leveling (Byte 0): 33 => 33
5308 23:19:08.682342 Write leveling (Byte 1): 29 => 29
5309 23:19:08.685501 DramcWriteLeveling(PI) end<-----
5310 23:19:08.685573
5311 23:19:08.685635 ==
5312 23:19:08.688838 Dram Type= 6, Freq= 0, CH_0, rank 1
5313 23:19:08.692044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 23:19:08.692126 ==
5315 23:19:08.695600 [Gating] SW mode calibration
5316 23:19:08.701932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5317 23:19:08.708559 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5318 23:19:08.711886 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
5319 23:19:08.718675 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 23:19:08.721673 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 23:19:08.724985 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 23:19:08.731768 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 23:19:08.735045 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 23:19:08.738288 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 23:19:08.745143 0 14 28 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 0)
5326 23:19:08.748530 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5327 23:19:08.751802 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 23:19:08.758576 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 23:19:08.761829 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 23:19:08.764979 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 23:19:08.768230 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 23:19:08.774802 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5333 23:19:08.778059 0 15 28 | B1->B0 | 2828 3636 | 0 0 | (0 0) (0 0)
5334 23:19:08.782362 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5335 23:19:08.788135 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 23:19:08.791546 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 23:19:08.794950 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 23:19:08.801373 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 23:19:08.804777 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 23:19:08.807878 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 23:19:08.814464 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5342 23:19:08.817916 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 23:19:08.821162 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 23:19:08.827837 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 23:19:08.830954 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 23:19:08.834491 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 23:19:08.840797 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 23:19:08.844421 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 23:19:08.847626 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 23:19:08.854366 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 23:19:08.857679 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 23:19:08.860653 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 23:19:08.867659 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 23:19:08.870544 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 23:19:08.874244 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 23:19:08.880719 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 23:19:08.884043 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5358 23:19:08.887316 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5359 23:19:08.890628 Total UI for P1: 0, mck2ui 16
5360 23:19:08.894006 best dqsien dly found for B0: ( 1, 2, 28)
5361 23:19:08.900699 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 23:19:08.900781 Total UI for P1: 0, mck2ui 16
5363 23:19:08.907511 best dqsien dly found for B1: ( 1, 3, 0)
5364 23:19:08.910492 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5365 23:19:08.913968 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5366 23:19:08.914050
5367 23:19:08.917144 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5368 23:19:08.920766 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5369 23:19:08.923986 [Gating] SW calibration Done
5370 23:19:08.924068 ==
5371 23:19:08.927214 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 23:19:08.930556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 23:19:08.930638 ==
5374 23:19:08.934010 RX Vref Scan: 0
5375 23:19:08.934092
5376 23:19:08.934157 RX Vref 0 -> 0, step: 1
5377 23:19:08.934218
5378 23:19:08.937236 RX Delay -80 -> 252, step: 8
5379 23:19:08.940505 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5380 23:19:08.946998 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5381 23:19:08.950502 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5382 23:19:08.953667 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5383 23:19:08.957225 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5384 23:19:08.960206 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5385 23:19:08.963779 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5386 23:19:08.970455 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5387 23:19:08.973849 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5388 23:19:08.977286 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5389 23:19:08.980238 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5390 23:19:08.983601 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5391 23:19:08.990129 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5392 23:19:08.993413 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5393 23:19:08.996888 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5394 23:19:09.000264 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5395 23:19:09.000345 ==
5396 23:19:09.003613 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 23:19:09.010253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 23:19:09.010361 ==
5399 23:19:09.010454 DQS Delay:
5400 23:19:09.010542 DQS0 = 0, DQS1 = 0
5401 23:19:09.013423 DQM Delay:
5402 23:19:09.013541 DQM0 = 91, DQM1 = 82
5403 23:19:09.016579 DQ Delay:
5404 23:19:09.020069 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5405 23:19:09.023235 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5406 23:19:09.026655 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5407 23:19:09.029809 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5408 23:19:09.029923
5409 23:19:09.030017
5410 23:19:09.030118 ==
5411 23:19:09.033162 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 23:19:09.036406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 23:19:09.036516 ==
5414 23:19:09.036611
5415 23:19:09.036703
5416 23:19:09.039654 TX Vref Scan disable
5417 23:19:09.039755 == TX Byte 0 ==
5418 23:19:09.046379 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5419 23:19:09.049724 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5420 23:19:09.053130 == TX Byte 1 ==
5421 23:19:09.056366 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5422 23:19:09.059536 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5423 23:19:09.059615 ==
5424 23:19:09.062864 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 23:19:09.066284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 23:19:09.066359 ==
5427 23:19:09.069367
5428 23:19:09.069466
5429 23:19:09.069577 TX Vref Scan disable
5430 23:19:09.073074 == TX Byte 0 ==
5431 23:19:09.076476 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5432 23:19:09.079653 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5433 23:19:09.082821 == TX Byte 1 ==
5434 23:19:09.086070 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5435 23:19:09.092751 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5436 23:19:09.092840
5437 23:19:09.092942 [DATLAT]
5438 23:19:09.093042 Freq=933, CH0 RK1
5439 23:19:09.093134
5440 23:19:09.096041 DATLAT Default: 0xb
5441 23:19:09.096115 0, 0xFFFF, sum = 0
5442 23:19:09.099433 1, 0xFFFF, sum = 0
5443 23:19:09.099537 2, 0xFFFF, sum = 0
5444 23:19:09.102691 3, 0xFFFF, sum = 0
5445 23:19:09.106022 4, 0xFFFF, sum = 0
5446 23:19:09.106097 5, 0xFFFF, sum = 0
5447 23:19:09.109431 6, 0xFFFF, sum = 0
5448 23:19:09.109529 7, 0xFFFF, sum = 0
5449 23:19:09.112359 8, 0xFFFF, sum = 0
5450 23:19:09.112432 9, 0xFFFF, sum = 0
5451 23:19:09.115771 10, 0x0, sum = 1
5452 23:19:09.115844 11, 0x0, sum = 2
5453 23:19:09.119247 12, 0x0, sum = 3
5454 23:19:09.119350 13, 0x0, sum = 4
5455 23:19:09.119442 best_step = 11
5456 23:19:09.119531
5457 23:19:09.122722 ==
5458 23:19:09.125646 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 23:19:09.129144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 23:19:09.129245 ==
5461 23:19:09.129340 RX Vref Scan: 0
5462 23:19:09.129428
5463 23:19:09.132218 RX Vref 0 -> 0, step: 1
5464 23:19:09.132324
5465 23:19:09.135792 RX Delay -77 -> 252, step: 4
5466 23:19:09.142495 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5467 23:19:09.145594 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5468 23:19:09.149112 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5469 23:19:09.152275 iDelay=199, Bit 3, Center 86 (-9 ~ 182) 192
5470 23:19:09.155517 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5471 23:19:09.158898 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5472 23:19:09.165745 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5473 23:19:09.168769 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5474 23:19:09.172113 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5475 23:19:09.175486 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5476 23:19:09.178988 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5477 23:19:09.185632 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5478 23:19:09.188684 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5479 23:19:09.191970 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5480 23:19:09.195298 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5481 23:19:09.198445 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5482 23:19:09.201754 ==
5483 23:19:09.201838 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 23:19:09.208407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 23:19:09.208515 ==
5486 23:19:09.208608 DQS Delay:
5487 23:19:09.212056 DQS0 = 0, DQS1 = 0
5488 23:19:09.212166 DQM Delay:
5489 23:19:09.215492 DQM0 = 92, DQM1 = 84
5490 23:19:09.215625 DQ Delay:
5491 23:19:09.218836 DQ0 =92, DQ1 =92, DQ2 =90, DQ3 =86
5492 23:19:09.221862 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
5493 23:19:09.225227 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =76
5494 23:19:09.228631 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =90
5495 23:19:09.228710
5496 23:19:09.228773
5497 23:19:09.235294 [DQSOSCAuto] RK1, (LSB)MR18= 0x3113, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5498 23:19:09.238502 CH0 RK1: MR19=505, MR18=3113
5499 23:19:09.245006 CH0_RK1: MR19=0x505, MR18=0x3113, DQSOSC=406, MR23=63, INC=65, DEC=43
5500 23:19:09.248484 [RxdqsGatingPostProcess] freq 933
5501 23:19:09.255261 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5502 23:19:09.255386 best DQS0 dly(2T, 0.5T) = (0, 10)
5503 23:19:09.258512 best DQS1 dly(2T, 0.5T) = (0, 11)
5504 23:19:09.261782 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5505 23:19:09.264991 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5506 23:19:09.268406 best DQS0 dly(2T, 0.5T) = (0, 10)
5507 23:19:09.271711 best DQS1 dly(2T, 0.5T) = (0, 11)
5508 23:19:09.274843 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5509 23:19:09.278245 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5510 23:19:09.281496 Pre-setting of DQS Precalculation
5511 23:19:09.288139 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5512 23:19:09.288247 ==
5513 23:19:09.291553 Dram Type= 6, Freq= 0, CH_1, rank 0
5514 23:19:09.294938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 23:19:09.295019 ==
5516 23:19:09.301286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 23:19:09.304676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5518 23:19:09.308748 [CA 0] Center 38 (8~68) winsize 61
5519 23:19:09.311990 [CA 1] Center 38 (8~69) winsize 62
5520 23:19:09.315268 [CA 2] Center 35 (6~65) winsize 60
5521 23:19:09.318610 [CA 3] Center 35 (5~65) winsize 61
5522 23:19:09.321949 [CA 4] Center 35 (6~65) winsize 60
5523 23:19:09.325224 [CA 5] Center 34 (5~64) winsize 60
5524 23:19:09.325305
5525 23:19:09.328506 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5526 23:19:09.328588
5527 23:19:09.331759 [CATrainingPosCal] consider 1 rank data
5528 23:19:09.335113 u2DelayCellTimex100 = 270/100 ps
5529 23:19:09.338328 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5530 23:19:09.345259 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5531 23:19:09.348198 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5532 23:19:09.351803 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5533 23:19:09.354886 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5534 23:19:09.358313 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5535 23:19:09.358420
5536 23:19:09.361570 CA PerBit enable=1, Macro0, CA PI delay=34
5537 23:19:09.361678
5538 23:19:09.364719 [CBTSetCACLKResult] CA Dly = 34
5539 23:19:09.364828 CS Dly: 6 (0~37)
5540 23:19:09.368127 ==
5541 23:19:09.371292 Dram Type= 6, Freq= 0, CH_1, rank 1
5542 23:19:09.374753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 23:19:09.374841 ==
5544 23:19:09.378228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5545 23:19:09.384701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5546 23:19:09.388583 [CA 0] Center 38 (8~68) winsize 61
5547 23:19:09.392070 [CA 1] Center 38 (8~69) winsize 62
5548 23:19:09.395487 [CA 2] Center 36 (6~66) winsize 61
5549 23:19:09.398447 [CA 3] Center 35 (5~65) winsize 61
5550 23:19:09.401703 [CA 4] Center 35 (5~66) winsize 62
5551 23:19:09.405035 [CA 5] Center 34 (4~65) winsize 62
5552 23:19:09.405144
5553 23:19:09.408467 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5554 23:19:09.408570
5555 23:19:09.411854 [CATrainingPosCal] consider 2 rank data
5556 23:19:09.414930 u2DelayCellTimex100 = 270/100 ps
5557 23:19:09.418324 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5558 23:19:09.424837 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5559 23:19:09.427982 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5560 23:19:09.431461 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5561 23:19:09.434877 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5562 23:19:09.438197 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5563 23:19:09.438304
5564 23:19:09.441657 CA PerBit enable=1, Macro0, CA PI delay=34
5565 23:19:09.441765
5566 23:19:09.444888 [CBTSetCACLKResult] CA Dly = 34
5567 23:19:09.447848 CS Dly: 7 (0~39)
5568 23:19:09.447954
5569 23:19:09.451449 ----->DramcWriteLeveling(PI) begin...
5570 23:19:09.451553 ==
5571 23:19:09.454598 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 23:19:09.457955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 23:19:09.458037 ==
5574 23:19:09.461173 Write leveling (Byte 0): 25 => 25
5575 23:19:09.464547 Write leveling (Byte 1): 31 => 31
5576 23:19:09.467965 DramcWriteLeveling(PI) end<-----
5577 23:19:09.468046
5578 23:19:09.468110 ==
5579 23:19:09.470942 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 23:19:09.474627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 23:19:09.474710 ==
5582 23:19:09.477706 [Gating] SW mode calibration
5583 23:19:09.484424 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5584 23:19:09.490734 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5585 23:19:09.494065 0 14 0 | B1->B0 | 2f2f 3131 | 1 0 | (1 1) (0 0)
5586 23:19:09.497593 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 23:19:09.504097 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 23:19:09.507265 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 23:19:09.510723 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 23:19:09.517460 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 23:19:09.520769 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 23:19:09.524014 0 14 28 | B1->B0 | 3232 3030 | 0 1 | (0 0) (1 0)
5593 23:19:09.530492 0 15 0 | B1->B0 | 2a2a 2b2b | 0 1 | (0 0) (1 0)
5594 23:19:09.533991 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 23:19:09.537060 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 23:19:09.543878 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 23:19:09.547251 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 23:19:09.550582 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 23:19:09.556791 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 23:19:09.560125 0 15 28 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (0 0)
5601 23:19:09.563256 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 23:19:09.569822 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 23:19:09.573130 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 23:19:09.576527 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 23:19:09.583412 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 23:19:09.586697 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 23:19:09.590033 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5608 23:19:09.596295 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5609 23:19:09.599685 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5610 23:19:09.602877 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 23:19:09.609617 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 23:19:09.613015 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 23:19:09.616269 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 23:19:09.622987 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 23:19:09.626179 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:19:09.629638 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:19:09.635785 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:19:09.639512 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 23:19:09.642712 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 23:19:09.649094 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 23:19:09.652517 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 23:19:09.655820 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 23:19:09.662390 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 23:19:09.665926 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5625 23:19:09.669251 Total UI for P1: 0, mck2ui 16
5626 23:19:09.672501 best dqsien dly found for B1: ( 1, 2, 26)
5627 23:19:09.675956 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5628 23:19:09.682565 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 23:19:09.682699 Total UI for P1: 0, mck2ui 16
5630 23:19:09.689087 best dqsien dly found for B0: ( 1, 2, 30)
5631 23:19:09.692337 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5632 23:19:09.695636 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5633 23:19:09.695741
5634 23:19:09.698892 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5635 23:19:09.702381 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5636 23:19:09.705615 [Gating] SW calibration Done
5637 23:19:09.705722 ==
5638 23:19:09.708643 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 23:19:09.712215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 23:19:09.712336 ==
5641 23:19:09.715629 RX Vref Scan: 0
5642 23:19:09.715755
5643 23:19:09.715866 RX Vref 0 -> 0, step: 1
5644 23:19:09.715958
5645 23:19:09.718712 RX Delay -80 -> 252, step: 8
5646 23:19:09.725210 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5647 23:19:09.728413 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5648 23:19:09.731685 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5649 23:19:09.735131 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5650 23:19:09.738387 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5651 23:19:09.741789 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5652 23:19:09.744855 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5653 23:19:09.751633 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5654 23:19:09.754797 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5655 23:19:09.758279 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5656 23:19:09.761588 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5657 23:19:09.764780 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5658 23:19:09.771725 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5659 23:19:09.774886 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5660 23:19:09.778279 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5661 23:19:09.781473 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5662 23:19:09.781581 ==
5663 23:19:09.784546 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 23:19:09.788148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 23:19:09.791464 ==
5666 23:19:09.791547 DQS Delay:
5667 23:19:09.791612 DQS0 = 0, DQS1 = 0
5668 23:19:09.794700 DQM Delay:
5669 23:19:09.794781 DQM0 = 98, DQM1 = 90
5670 23:19:09.797862 DQ Delay:
5671 23:19:09.801093 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5672 23:19:09.804221 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5673 23:19:09.807765 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5674 23:19:09.811035 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5675 23:19:09.811146
5676 23:19:09.811239
5677 23:19:09.811328 ==
5678 23:19:09.814247 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 23:19:09.817382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 23:19:09.817496 ==
5681 23:19:09.817564
5682 23:19:09.817624
5683 23:19:09.820992 TX Vref Scan disable
5684 23:19:09.821099 == TX Byte 0 ==
5685 23:19:09.827374 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5686 23:19:09.830649 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5687 23:19:09.833945 == TX Byte 1 ==
5688 23:19:09.837278 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5689 23:19:09.840695 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5690 23:19:09.840775 ==
5691 23:19:09.843988 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 23:19:09.847290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 23:19:09.847366 ==
5694 23:19:09.850726
5695 23:19:09.850799
5696 23:19:09.850861 TX Vref Scan disable
5697 23:19:09.854069 == TX Byte 0 ==
5698 23:19:09.857405 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5699 23:19:09.863656 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5700 23:19:09.863734 == TX Byte 1 ==
5701 23:19:09.867279 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5702 23:19:09.873954 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5703 23:19:09.874033
5704 23:19:09.874097 [DATLAT]
5705 23:19:09.874158 Freq=933, CH1 RK0
5706 23:19:09.874217
5707 23:19:09.877204 DATLAT Default: 0xd
5708 23:19:09.877314 0, 0xFFFF, sum = 0
5709 23:19:09.880575 1, 0xFFFF, sum = 0
5710 23:19:09.883473 2, 0xFFFF, sum = 0
5711 23:19:09.883594 3, 0xFFFF, sum = 0
5712 23:19:09.886737 4, 0xFFFF, sum = 0
5713 23:19:09.886845 5, 0xFFFF, sum = 0
5714 23:19:09.890224 6, 0xFFFF, sum = 0
5715 23:19:09.890345 7, 0xFFFF, sum = 0
5716 23:19:09.893244 8, 0xFFFF, sum = 0
5717 23:19:09.893356 9, 0xFFFF, sum = 0
5718 23:19:09.896851 10, 0x0, sum = 1
5719 23:19:09.896957 11, 0x0, sum = 2
5720 23:19:09.900252 12, 0x0, sum = 3
5721 23:19:09.900356 13, 0x0, sum = 4
5722 23:19:09.903558 best_step = 11
5723 23:19:09.903659
5724 23:19:09.903749 ==
5725 23:19:09.906817 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 23:19:09.910090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 23:19:09.910193 ==
5728 23:19:09.910263 RX Vref Scan: 1
5729 23:19:09.913271
5730 23:19:09.913374 RX Vref 0 -> 0, step: 1
5731 23:19:09.913467
5732 23:19:09.916783 RX Delay -61 -> 252, step: 4
5733 23:19:09.916887
5734 23:19:09.919673 Set Vref, RX VrefLevel [Byte0]: 57
5735 23:19:09.923244 [Byte1]: 51
5736 23:19:09.926765
5737 23:19:09.926870 Final RX Vref Byte 0 = 57 to rank0
5738 23:19:09.929782 Final RX Vref Byte 1 = 51 to rank0
5739 23:19:09.933007 Final RX Vref Byte 0 = 57 to rank1
5740 23:19:09.936505 Final RX Vref Byte 1 = 51 to rank1==
5741 23:19:09.939703 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 23:19:09.946400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 23:19:09.946506 ==
5744 23:19:09.946602 DQS Delay:
5745 23:19:09.949740 DQS0 = 0, DQS1 = 0
5746 23:19:09.949840 DQM Delay:
5747 23:19:09.949932 DQM0 = 99, DQM1 = 92
5748 23:19:09.953000 DQ Delay:
5749 23:19:09.956388 DQ0 =106, DQ1 =94, DQ2 =88, DQ3 =94
5750 23:19:09.959718 DQ4 =96, DQ5 =110, DQ6 =112, DQ7 =98
5751 23:19:09.962783 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5752 23:19:09.965986 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =100
5753 23:19:09.966092
5754 23:19:09.966184
5755 23:19:09.972672 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5756 23:19:09.975890 CH1 RK0: MR19=405, MR18=FE07
5757 23:19:09.982728 CH1_RK0: MR19=0x405, MR18=0xFE07, DQSOSC=419, MR23=63, INC=61, DEC=41
5758 23:19:09.982816
5759 23:19:09.986046 ----->DramcWriteLeveling(PI) begin...
5760 23:19:09.986134 ==
5761 23:19:09.989111 Dram Type= 6, Freq= 0, CH_1, rank 1
5762 23:19:09.992516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 23:19:09.992595 ==
5764 23:19:09.995876 Write leveling (Byte 0): 25 => 25
5765 23:19:09.999164 Write leveling (Byte 1): 27 => 27
5766 23:19:10.002357 DramcWriteLeveling(PI) end<-----
5767 23:19:10.002457
5768 23:19:10.002548 ==
5769 23:19:10.005685 Dram Type= 6, Freq= 0, CH_1, rank 1
5770 23:19:10.012533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 23:19:10.012610 ==
5772 23:19:10.012673 [Gating] SW mode calibration
5773 23:19:10.022564 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5774 23:19:10.025548 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5775 23:19:10.028817 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5776 23:19:10.035525 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 23:19:10.038699 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 23:19:10.042287 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 23:19:10.048587 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 23:19:10.051906 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 23:19:10.055250 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 0)
5782 23:19:10.062011 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)
5783 23:19:10.065406 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 23:19:10.068397 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 23:19:10.075168 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 23:19:10.078476 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 23:19:10.081964 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 23:19:10.088572 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 23:19:10.091838 0 15 24 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
5790 23:19:10.094892 0 15 28 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5791 23:19:10.101423 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5792 23:19:10.104874 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 23:19:10.108239 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 23:19:10.114784 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 23:19:10.117925 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 23:19:10.121298 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5797 23:19:10.127907 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5798 23:19:10.131208 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5799 23:19:10.134610 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 23:19:10.140922 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 23:19:10.144427 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 23:19:10.147818 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 23:19:10.154467 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 23:19:10.157601 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 23:19:10.161082 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 23:19:10.167322 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 23:19:10.170657 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 23:19:10.173995 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 23:19:10.180729 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 23:19:10.184057 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 23:19:10.187355 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 23:19:10.194001 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 23:19:10.197368 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5814 23:19:10.200746 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 23:19:10.204033 Total UI for P1: 0, mck2ui 16
5816 23:19:10.207182 best dqsien dly found for B0: ( 1, 2, 24)
5817 23:19:10.210516 Total UI for P1: 0, mck2ui 16
5818 23:19:10.214102 best dqsien dly found for B1: ( 1, 2, 26)
5819 23:19:10.217355 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5820 23:19:10.220690 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5821 23:19:10.220789
5822 23:19:10.227005 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5823 23:19:10.230633 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5824 23:19:10.233789 [Gating] SW calibration Done
5825 23:19:10.233861 ==
5826 23:19:10.237041 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 23:19:10.240449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 23:19:10.240553 ==
5829 23:19:10.240643 RX Vref Scan: 0
5830 23:19:10.240740
5831 23:19:10.243506 RX Vref 0 -> 0, step: 1
5832 23:19:10.243583
5833 23:19:10.246881 RX Delay -80 -> 252, step: 8
5834 23:19:10.250122 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5835 23:19:10.253420 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5836 23:19:10.259878 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5837 23:19:10.263233 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5838 23:19:10.266598 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5839 23:19:10.270098 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5840 23:19:10.273113 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5841 23:19:10.276677 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5842 23:19:10.283300 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5843 23:19:10.286539 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5844 23:19:10.289955 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5845 23:19:10.292791 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5846 23:19:10.296495 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5847 23:19:10.302952 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5848 23:19:10.306299 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5849 23:19:10.309671 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5850 23:19:10.309806 ==
5851 23:19:10.312676 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 23:19:10.316416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 23:19:10.316518 ==
5854 23:19:10.319649 DQS Delay:
5855 23:19:10.319748 DQS0 = 0, DQS1 = 0
5856 23:19:10.319836 DQM Delay:
5857 23:19:10.322731 DQM0 = 95, DQM1 = 91
5858 23:19:10.322874 DQ Delay:
5859 23:19:10.326116 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =91
5860 23:19:10.329655 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5861 23:19:10.332619 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =83
5862 23:19:10.336268 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5863 23:19:10.336390
5864 23:19:10.336506
5865 23:19:10.336625 ==
5866 23:19:10.339491 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 23:19:10.346018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 23:19:10.346124 ==
5869 23:19:10.346218
5870 23:19:10.346308
5871 23:19:10.348955 TX Vref Scan disable
5872 23:19:10.349054 == TX Byte 0 ==
5873 23:19:10.352421 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5874 23:19:10.359074 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5875 23:19:10.359184 == TX Byte 1 ==
5876 23:19:10.362216 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5877 23:19:10.368918 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5878 23:19:10.368999 ==
5879 23:19:10.372255 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 23:19:10.375537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 23:19:10.375646 ==
5882 23:19:10.375766
5883 23:19:10.375857
5884 23:19:10.378811 TX Vref Scan disable
5885 23:19:10.382093 == TX Byte 0 ==
5886 23:19:10.385366 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5887 23:19:10.388734 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5888 23:19:10.392061 == TX Byte 1 ==
5889 23:19:10.395146 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5890 23:19:10.398824 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5891 23:19:10.398935
5892 23:19:10.401815 [DATLAT]
5893 23:19:10.401926 Freq=933, CH1 RK1
5894 23:19:10.402018
5895 23:19:10.405226 DATLAT Default: 0xb
5896 23:19:10.405327 0, 0xFFFF, sum = 0
5897 23:19:10.408642 1, 0xFFFF, sum = 0
5898 23:19:10.408763 2, 0xFFFF, sum = 0
5899 23:19:10.411972 3, 0xFFFF, sum = 0
5900 23:19:10.412076 4, 0xFFFF, sum = 0
5901 23:19:10.415316 5, 0xFFFF, sum = 0
5902 23:19:10.415418 6, 0xFFFF, sum = 0
5903 23:19:10.418259 7, 0xFFFF, sum = 0
5904 23:19:10.418378 8, 0xFFFF, sum = 0
5905 23:19:10.421655 9, 0xFFFF, sum = 0
5906 23:19:10.421755 10, 0x0, sum = 1
5907 23:19:10.424995 11, 0x0, sum = 2
5908 23:19:10.425071 12, 0x0, sum = 3
5909 23:19:10.428213 13, 0x0, sum = 4
5910 23:19:10.428326 best_step = 11
5911 23:19:10.428419
5912 23:19:10.428506 ==
5913 23:19:10.431406 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 23:19:10.438452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 23:19:10.438557 ==
5916 23:19:10.438665 RX Vref Scan: 0
5917 23:19:10.438777
5918 23:19:10.441419 RX Vref 0 -> 0, step: 1
5919 23:19:10.441517
5920 23:19:10.444708 RX Delay -61 -> 252, step: 4
5921 23:19:10.447932 iDelay=203, Bit 0, Center 98 (3 ~ 194) 192
5922 23:19:10.451215 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5923 23:19:10.457964 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5924 23:19:10.461313 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5925 23:19:10.464799 iDelay=203, Bit 4, Center 92 (-1 ~ 186) 188
5926 23:19:10.467846 iDelay=203, Bit 5, Center 104 (11 ~ 198) 188
5927 23:19:10.471186 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5928 23:19:10.477832 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5929 23:19:10.481119 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5930 23:19:10.484407 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5931 23:19:10.487587 iDelay=203, Bit 10, Center 96 (7 ~ 186) 180
5932 23:19:10.491091 iDelay=203, Bit 11, Center 88 (-1 ~ 178) 180
5933 23:19:10.494121 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5934 23:19:10.500744 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5935 23:19:10.504182 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5936 23:19:10.507718 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5937 23:19:10.507822 ==
5938 23:19:10.510785 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 23:19:10.513920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 23:19:10.517209 ==
5941 23:19:10.517318 DQS Delay:
5942 23:19:10.517418 DQS0 = 0, DQS1 = 0
5943 23:19:10.520835 DQM Delay:
5944 23:19:10.520934 DQM0 = 94, DQM1 = 94
5945 23:19:10.524091 DQ Delay:
5946 23:19:10.524194 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =92
5947 23:19:10.527480 DQ4 =92, DQ5 =104, DQ6 =106, DQ7 =92
5948 23:19:10.530840 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =88
5949 23:19:10.537163 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =98
5950 23:19:10.537273
5951 23:19:10.537366
5952 23:19:10.543906 [DQSOSCAuto] RK1, (LSB)MR18= 0xf23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5953 23:19:10.547241 CH1 RK1: MR19=505, MR18=F23
5954 23:19:10.553911 CH1_RK1: MR19=0x505, MR18=0xF23, DQSOSC=410, MR23=63, INC=64, DEC=42
5955 23:19:10.557096 [RxdqsGatingPostProcess] freq 933
5956 23:19:10.560508 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5957 23:19:10.563831 best DQS0 dly(2T, 0.5T) = (0, 10)
5958 23:19:10.566841 best DQS1 dly(2T, 0.5T) = (0, 10)
5959 23:19:10.570135 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5960 23:19:10.573514 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5961 23:19:10.576969 best DQS0 dly(2T, 0.5T) = (0, 10)
5962 23:19:10.579997 best DQS1 dly(2T, 0.5T) = (0, 10)
5963 23:19:10.583567 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5964 23:19:10.586794 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5965 23:19:10.590377 Pre-setting of DQS Precalculation
5966 23:19:10.593417 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5967 23:19:10.600279 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5968 23:19:10.610211 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5969 23:19:10.610319
5970 23:19:10.610416
5971 23:19:10.613450 [Calibration Summary] 1866 Mbps
5972 23:19:10.613560 CH 0, Rank 0
5973 23:19:10.616691 SW Impedance : PASS
5974 23:19:10.616803 DUTY Scan : NO K
5975 23:19:10.620047 ZQ Calibration : PASS
5976 23:19:10.623246 Jitter Meter : NO K
5977 23:19:10.623349 CBT Training : PASS
5978 23:19:10.626516 Write leveling : PASS
5979 23:19:10.626595 RX DQS gating : PASS
5980 23:19:10.629901 RX DQ/DQS(RDDQC) : PASS
5981 23:19:10.633236 TX DQ/DQS : PASS
5982 23:19:10.633349 RX DATLAT : PASS
5983 23:19:10.636737 RX DQ/DQS(Engine): PASS
5984 23:19:10.640018 TX OE : NO K
5985 23:19:10.640128 All Pass.
5986 23:19:10.640231
5987 23:19:10.640324 CH 0, Rank 1
5988 23:19:10.643435 SW Impedance : PASS
5989 23:19:10.646662 DUTY Scan : NO K
5990 23:19:10.646739 ZQ Calibration : PASS
5991 23:19:10.649947 Jitter Meter : NO K
5992 23:19:10.653117 CBT Training : PASS
5993 23:19:10.653217 Write leveling : PASS
5994 23:19:10.656555 RX DQS gating : PASS
5995 23:19:10.659810 RX DQ/DQS(RDDQC) : PASS
5996 23:19:10.659890 TX DQ/DQS : PASS
5997 23:19:10.663116 RX DATLAT : PASS
5998 23:19:10.666433 RX DQ/DQS(Engine): PASS
5999 23:19:10.666544 TX OE : NO K
6000 23:19:10.666639 All Pass.
6001 23:19:10.669714
6002 23:19:10.669813 CH 1, Rank 0
6003 23:19:10.673047 SW Impedance : PASS
6004 23:19:10.673158 DUTY Scan : NO K
6005 23:19:10.676292 ZQ Calibration : PASS
6006 23:19:10.679563 Jitter Meter : NO K
6007 23:19:10.679664 CBT Training : PASS
6008 23:19:10.682792 Write leveling : PASS
6009 23:19:10.682875 RX DQS gating : PASS
6010 23:19:10.686121 RX DQ/DQS(RDDQC) : PASS
6011 23:19:10.689531 TX DQ/DQS : PASS
6012 23:19:10.689640 RX DATLAT : PASS
6013 23:19:10.692913 RX DQ/DQS(Engine): PASS
6014 23:19:10.696071 TX OE : NO K
6015 23:19:10.696157 All Pass.
6016 23:19:10.696221
6017 23:19:10.696281 CH 1, Rank 1
6018 23:19:10.699405 SW Impedance : PASS
6019 23:19:10.702893 DUTY Scan : NO K
6020 23:19:10.702992 ZQ Calibration : PASS
6021 23:19:10.706160 Jitter Meter : NO K
6022 23:19:10.709428 CBT Training : PASS
6023 23:19:10.709522 Write leveling : PASS
6024 23:19:10.712454 RX DQS gating : PASS
6025 23:19:10.715800 RX DQ/DQS(RDDQC) : PASS
6026 23:19:10.715874 TX DQ/DQS : PASS
6027 23:19:10.719468 RX DATLAT : PASS
6028 23:19:10.722573 RX DQ/DQS(Engine): PASS
6029 23:19:10.722647 TX OE : NO K
6030 23:19:10.725889 All Pass.
6031 23:19:10.725987
6032 23:19:10.726052 DramC Write-DBI off
6033 23:19:10.728989 PER_BANK_REFRESH: Hybrid Mode
6034 23:19:10.729072 TX_TRACKING: ON
6035 23:19:10.739183 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6036 23:19:10.742472 [FAST_K] Save calibration result to emmc
6037 23:19:10.745602 dramc_set_vcore_voltage set vcore to 650000
6038 23:19:10.748976 Read voltage for 400, 6
6039 23:19:10.749076 Vio18 = 0
6040 23:19:10.752274 Vcore = 650000
6041 23:19:10.752351 Vdram = 0
6042 23:19:10.752420 Vddq = 0
6043 23:19:10.755747 Vmddr = 0
6044 23:19:10.759068 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6045 23:19:10.765633 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6046 23:19:10.765745 MEM_TYPE=3, freq_sel=20
6047 23:19:10.769156 sv_algorithm_assistance_LP4_800
6048 23:19:10.772499 ============ PULL DRAM RESETB DOWN ============
6049 23:19:10.779295 ========== PULL DRAM RESETB DOWN end =========
6050 23:19:10.782537 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6051 23:19:10.785492 ===================================
6052 23:19:10.788817 LPDDR4 DRAM CONFIGURATION
6053 23:19:10.792231 ===================================
6054 23:19:10.792336 EX_ROW_EN[0] = 0x0
6055 23:19:10.795539 EX_ROW_EN[1] = 0x0
6056 23:19:10.798850 LP4Y_EN = 0x0
6057 23:19:10.798952 WORK_FSP = 0x0
6058 23:19:10.802097 WL = 0x2
6059 23:19:10.802215 RL = 0x2
6060 23:19:10.805621 BL = 0x2
6061 23:19:10.805730 RPST = 0x0
6062 23:19:10.808815 RD_PRE = 0x0
6063 23:19:10.808918 WR_PRE = 0x1
6064 23:19:10.811924 WR_PST = 0x0
6065 23:19:10.812026 DBI_WR = 0x0
6066 23:19:10.815592 DBI_RD = 0x0
6067 23:19:10.815699 OTF = 0x1
6068 23:19:10.818858 ===================================
6069 23:19:10.822175 ===================================
6070 23:19:10.825417 ANA top config
6071 23:19:10.828733 ===================================
6072 23:19:10.828837 DLL_ASYNC_EN = 0
6073 23:19:10.832237 ALL_SLAVE_EN = 1
6074 23:19:10.835595 NEW_RANK_MODE = 1
6075 23:19:10.838554 DLL_IDLE_MODE = 1
6076 23:19:10.838638 LP45_APHY_COMB_EN = 1
6077 23:19:10.841908 TX_ODT_DIS = 1
6078 23:19:10.845246 NEW_8X_MODE = 1
6079 23:19:10.848549 ===================================
6080 23:19:10.851841 ===================================
6081 23:19:10.855397 data_rate = 800
6082 23:19:10.858372 CKR = 1
6083 23:19:10.861953 DQ_P2S_RATIO = 4
6084 23:19:10.865287 ===================================
6085 23:19:10.865392 CA_P2S_RATIO = 4
6086 23:19:10.868451 DQ_CA_OPEN = 0
6087 23:19:10.871627 DQ_SEMI_OPEN = 1
6088 23:19:10.874955 CA_SEMI_OPEN = 1
6089 23:19:10.878514 CA_FULL_RATE = 0
6090 23:19:10.881894 DQ_CKDIV4_EN = 0
6091 23:19:10.881996 CA_CKDIV4_EN = 1
6092 23:19:10.885162 CA_PREDIV_EN = 0
6093 23:19:10.888182 PH8_DLY = 0
6094 23:19:10.891590 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6095 23:19:10.894962 DQ_AAMCK_DIV = 0
6096 23:19:10.898386 CA_AAMCK_DIV = 0
6097 23:19:10.898488 CA_ADMCK_DIV = 4
6098 23:19:10.901693 DQ_TRACK_CA_EN = 0
6099 23:19:10.905007 CA_PICK = 800
6100 23:19:10.908277 CA_MCKIO = 400
6101 23:19:10.911507 MCKIO_SEMI = 400
6102 23:19:10.914959 PLL_FREQ = 3016
6103 23:19:10.918525 DQ_UI_PI_RATIO = 32
6104 23:19:10.921537 CA_UI_PI_RATIO = 32
6105 23:19:10.921608 ===================================
6106 23:19:10.924730 ===================================
6107 23:19:10.928373 memory_type:LPDDR4
6108 23:19:10.931626 GP_NUM : 10
6109 23:19:10.931727 SRAM_EN : 1
6110 23:19:10.934737 MD32_EN : 0
6111 23:19:10.937974 ===================================
6112 23:19:10.941450 [ANA_INIT] >>>>>>>>>>>>>>
6113 23:19:10.944898 <<<<<< [CONFIGURE PHASE]: ANA_TX
6114 23:19:10.947912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6115 23:19:10.951302 ===================================
6116 23:19:10.951404 data_rate = 800,PCW = 0X7400
6117 23:19:10.954704 ===================================
6118 23:19:10.958041 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6119 23:19:10.964695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6120 23:19:10.977869 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6121 23:19:10.981118 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6122 23:19:10.984386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6123 23:19:10.987764 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6124 23:19:10.991044 [ANA_INIT] flow start
6125 23:19:10.991146 [ANA_INIT] PLL >>>>>>>>
6126 23:19:10.994131 [ANA_INIT] PLL <<<<<<<<
6127 23:19:10.997714 [ANA_INIT] MIDPI >>>>>>>>
6128 23:19:11.000966 [ANA_INIT] MIDPI <<<<<<<<
6129 23:19:11.001066 [ANA_INIT] DLL >>>>>>>>
6130 23:19:11.004478 [ANA_INIT] flow end
6131 23:19:11.007778 ============ LP4 DIFF to SE enter ============
6132 23:19:11.011097 ============ LP4 DIFF to SE exit ============
6133 23:19:11.014509 [ANA_INIT] <<<<<<<<<<<<<
6134 23:19:11.017469 [Flow] Enable top DCM control >>>>>
6135 23:19:11.021041 [Flow] Enable top DCM control <<<<<
6136 23:19:11.024091 Enable DLL master slave shuffle
6137 23:19:11.030835 ==============================================================
6138 23:19:11.030925 Gating Mode config
6139 23:19:11.037425 ==============================================================
6140 23:19:11.037512 Config description:
6141 23:19:11.047399 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6142 23:19:11.054110 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6143 23:19:11.060422 SELPH_MODE 0: By rank 1: By Phase
6144 23:19:11.063840 ==============================================================
6145 23:19:11.067216 GAT_TRACK_EN = 0
6146 23:19:11.070683 RX_GATING_MODE = 2
6147 23:19:11.073986 RX_GATING_TRACK_MODE = 2
6148 23:19:11.077260 SELPH_MODE = 1
6149 23:19:11.080513 PICG_EARLY_EN = 1
6150 23:19:11.083798 VALID_LAT_VALUE = 1
6151 23:19:11.086959 ==============================================================
6152 23:19:11.093618 Enter into Gating configuration >>>>
6153 23:19:11.093696 Exit from Gating configuration <<<<
6154 23:19:11.097005 Enter into DVFS_PRE_config >>>>>
6155 23:19:11.110599 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6156 23:19:11.113570 Exit from DVFS_PRE_config <<<<<
6157 23:19:11.116827 Enter into PICG configuration >>>>
6158 23:19:11.120268 Exit from PICG configuration <<<<
6159 23:19:11.120369 [RX_INPUT] configuration >>>>>
6160 23:19:11.123590 [RX_INPUT] configuration <<<<<
6161 23:19:11.130167 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6162 23:19:11.133641 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6163 23:19:11.139957 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 23:19:11.146574 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 23:19:11.153161 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6166 23:19:11.159973 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6167 23:19:11.163433 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6168 23:19:11.166674 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6169 23:19:11.173297 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6170 23:19:11.176807 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6171 23:19:11.179912 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6172 23:19:11.183374 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6173 23:19:11.186293 ===================================
6174 23:19:11.189808 LPDDR4 DRAM CONFIGURATION
6175 23:19:11.193727 ===================================
6176 23:19:11.196437 EX_ROW_EN[0] = 0x0
6177 23:19:11.196535 EX_ROW_EN[1] = 0x0
6178 23:19:11.199630 LP4Y_EN = 0x0
6179 23:19:11.199725 WORK_FSP = 0x0
6180 23:19:11.203165 WL = 0x2
6181 23:19:11.203261 RL = 0x2
6182 23:19:11.206426 BL = 0x2
6183 23:19:11.206521 RPST = 0x0
6184 23:19:11.209767 RD_PRE = 0x0
6185 23:19:11.209861 WR_PRE = 0x1
6186 23:19:11.212906 WR_PST = 0x0
6187 23:19:11.216489 DBI_WR = 0x0
6188 23:19:11.216585 DBI_RD = 0x0
6189 23:19:11.219538 OTF = 0x1
6190 23:19:11.222932 ===================================
6191 23:19:11.226442 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6192 23:19:11.229427 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6193 23:19:11.232712 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 23:19:11.236261 ===================================
6195 23:19:11.239516 LPDDR4 DRAM CONFIGURATION
6196 23:19:11.242870 ===================================
6197 23:19:11.246164 EX_ROW_EN[0] = 0x10
6198 23:19:11.246236 EX_ROW_EN[1] = 0x0
6199 23:19:11.249323 LP4Y_EN = 0x0
6200 23:19:11.249420 WORK_FSP = 0x0
6201 23:19:11.252938 WL = 0x2
6202 23:19:11.253030 RL = 0x2
6203 23:19:11.256111 BL = 0x2
6204 23:19:11.256248 RPST = 0x0
6205 23:19:11.259511 RD_PRE = 0x0
6206 23:19:11.259603 WR_PRE = 0x1
6207 23:19:11.262736 WR_PST = 0x0
6208 23:19:11.262833 DBI_WR = 0x0
6209 23:19:11.266013 DBI_RD = 0x0
6210 23:19:11.269387 OTF = 0x1
6211 23:19:11.272713 ===================================
6212 23:19:11.275912 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6213 23:19:11.280838 nWR fixed to 30
6214 23:19:11.284468 [ModeRegInit_LP4] CH0 RK0
6215 23:19:11.284574 [ModeRegInit_LP4] CH0 RK1
6216 23:19:11.287825 [ModeRegInit_LP4] CH1 RK0
6217 23:19:11.290855 [ModeRegInit_LP4] CH1 RK1
6218 23:19:11.290951 match AC timing 19
6219 23:19:11.297541 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6220 23:19:11.300950 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6221 23:19:11.304414 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6222 23:19:11.310656 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6223 23:19:11.314213 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6224 23:19:11.314285 ==
6225 23:19:11.317319 Dram Type= 6, Freq= 0, CH_0, rank 0
6226 23:19:11.320855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6227 23:19:11.320944 ==
6228 23:19:11.327514 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6229 23:19:11.333927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6230 23:19:11.337135 [CA 0] Center 36 (8~64) winsize 57
6231 23:19:11.340615 [CA 1] Center 36 (8~64) winsize 57
6232 23:19:11.343766 [CA 2] Center 36 (8~64) winsize 57
6233 23:19:11.347062 [CA 3] Center 36 (8~64) winsize 57
6234 23:19:11.347135 [CA 4] Center 36 (8~64) winsize 57
6235 23:19:11.350377 [CA 5] Center 36 (8~64) winsize 57
6236 23:19:11.350490
6237 23:19:11.357380 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6238 23:19:11.357503
6239 23:19:11.360450 [CATrainingPosCal] consider 1 rank data
6240 23:19:11.363945 u2DelayCellTimex100 = 270/100 ps
6241 23:19:11.366983 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 23:19:11.370267 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 23:19:11.373804 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 23:19:11.376874 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 23:19:11.380188 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 23:19:11.383557 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 23:19:11.383657
6248 23:19:11.386890 CA PerBit enable=1, Macro0, CA PI delay=36
6249 23:19:11.387012
6250 23:19:11.390622 [CBTSetCACLKResult] CA Dly = 36
6251 23:19:11.393534 CS Dly: 1 (0~32)
6252 23:19:11.393634 ==
6253 23:19:11.396883 Dram Type= 6, Freq= 0, CH_0, rank 1
6254 23:19:11.400225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 23:19:11.400324 ==
6256 23:19:11.406915 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6257 23:19:11.413329 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6258 23:19:11.416696 [CA 0] Center 36 (8~64) winsize 57
6259 23:19:11.416794 [CA 1] Center 36 (8~64) winsize 57
6260 23:19:11.419969 [CA 2] Center 36 (8~64) winsize 57
6261 23:19:11.423153 [CA 3] Center 36 (8~64) winsize 57
6262 23:19:11.426463 [CA 4] Center 36 (8~64) winsize 57
6263 23:19:11.429890 [CA 5] Center 36 (8~64) winsize 57
6264 23:19:11.429979
6265 23:19:11.433229 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6266 23:19:11.433305
6267 23:19:11.439997 [CATrainingPosCal] consider 2 rank data
6268 23:19:11.440106 u2DelayCellTimex100 = 270/100 ps
6269 23:19:11.443431 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 23:19:11.449880 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 23:19:11.453181 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 23:19:11.456408 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 23:19:11.460020 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 23:19:11.463278 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 23:19:11.463376
6276 23:19:11.466309 CA PerBit enable=1, Macro0, CA PI delay=36
6277 23:19:11.466397
6278 23:19:11.469645 [CBTSetCACLKResult] CA Dly = 36
6279 23:19:11.473032 CS Dly: 1 (0~32)
6280 23:19:11.473128
6281 23:19:11.476503 ----->DramcWriteLeveling(PI) begin...
6282 23:19:11.476593 ==
6283 23:19:11.479583 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 23:19:11.482968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 23:19:11.483068 ==
6286 23:19:11.486126 Write leveling (Byte 0): 40 => 8
6287 23:19:11.489541 Write leveling (Byte 1): 40 => 8
6288 23:19:11.492763 DramcWriteLeveling(PI) end<-----
6289 23:19:11.492838
6290 23:19:11.492901 ==
6291 23:19:11.496031 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 23:19:11.499297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 23:19:11.499401 ==
6294 23:19:11.502622 [Gating] SW mode calibration
6295 23:19:11.509183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6296 23:19:11.515805 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6297 23:19:11.519156 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6298 23:19:11.522574 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6299 23:19:11.529206 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 23:19:11.532510 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 23:19:11.535578 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 23:19:11.542474 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 23:19:11.545737 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 23:19:11.548819 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 23:19:11.555473 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 23:19:11.555577 Total UI for P1: 0, mck2ui 16
6307 23:19:11.562234 best dqsien dly found for B0: ( 0, 14, 24)
6308 23:19:11.562341 Total UI for P1: 0, mck2ui 16
6309 23:19:11.569016 best dqsien dly found for B1: ( 0, 14, 24)
6310 23:19:11.572223 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6311 23:19:11.575297 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6312 23:19:11.575397
6313 23:19:11.578844 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6314 23:19:11.581966 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6315 23:19:11.585397 [Gating] SW calibration Done
6316 23:19:11.585521 ==
6317 23:19:11.588610 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 23:19:11.591962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 23:19:11.592060 ==
6320 23:19:11.595367 RX Vref Scan: 0
6321 23:19:11.595462
6322 23:19:11.595552 RX Vref 0 -> 0, step: 1
6323 23:19:11.595647
6324 23:19:11.598609 RX Delay -410 -> 252, step: 16
6325 23:19:11.605426 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6326 23:19:11.608306 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6327 23:19:11.611708 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6328 23:19:11.615091 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6329 23:19:11.621892 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6330 23:19:11.625227 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6331 23:19:11.628167 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6332 23:19:11.631532 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6333 23:19:11.638086 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6334 23:19:11.641375 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6335 23:19:11.644735 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6336 23:19:11.651156 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6337 23:19:11.654618 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6338 23:19:11.657929 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6339 23:19:11.661078 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6340 23:19:11.667924 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6341 23:19:11.668026 ==
6342 23:19:11.671405 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 23:19:11.674743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 23:19:11.674850 ==
6345 23:19:11.674939 DQS Delay:
6346 23:19:11.677918 DQS0 = 59, DQS1 = 59
6347 23:19:11.677987 DQM Delay:
6348 23:19:11.681172 DQM0 = 17, DQM1 = 10
6349 23:19:11.681265 DQ Delay:
6350 23:19:11.684607 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6351 23:19:11.687879 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6352 23:19:11.691018 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6353 23:19:11.694374 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6354 23:19:11.694452
6355 23:19:11.694525
6356 23:19:11.694584 ==
6357 23:19:11.697721 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 23:19:11.701256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 23:19:11.701376 ==
6360 23:19:11.701467
6361 23:19:11.701553
6362 23:19:11.704468 TX Vref Scan disable
6363 23:19:11.707895 == TX Byte 0 ==
6364 23:19:11.710879 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 23:19:11.714060 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 23:19:11.717483 == TX Byte 1 ==
6367 23:19:11.720822 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 23:19:11.724114 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 23:19:11.724184 ==
6370 23:19:11.727439 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 23:19:11.730779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 23:19:11.730848 ==
6373 23:19:11.734177
6374 23:19:11.734246
6375 23:19:11.734323 TX Vref Scan disable
6376 23:19:11.737593 == TX Byte 0 ==
6377 23:19:11.740775 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 23:19:11.744022 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 23:19:11.747369 == TX Byte 1 ==
6380 23:19:11.750543 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6381 23:19:11.754213 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6382 23:19:11.754303
6383 23:19:11.754378 [DATLAT]
6384 23:19:11.757139 Freq=400, CH0 RK0
6385 23:19:11.757230
6386 23:19:11.760573 DATLAT Default: 0xf
6387 23:19:11.760665 0, 0xFFFF, sum = 0
6388 23:19:11.763955 1, 0xFFFF, sum = 0
6389 23:19:11.764028 2, 0xFFFF, sum = 0
6390 23:19:11.767059 3, 0xFFFF, sum = 0
6391 23:19:11.767129 4, 0xFFFF, sum = 0
6392 23:19:11.770441 5, 0xFFFF, sum = 0
6393 23:19:11.770510 6, 0xFFFF, sum = 0
6394 23:19:11.773792 7, 0xFFFF, sum = 0
6395 23:19:11.773859 8, 0xFFFF, sum = 0
6396 23:19:11.777110 9, 0xFFFF, sum = 0
6397 23:19:11.777216 10, 0xFFFF, sum = 0
6398 23:19:11.780441 11, 0xFFFF, sum = 0
6399 23:19:11.780540 12, 0xFFFF, sum = 0
6400 23:19:11.783760 13, 0x0, sum = 1
6401 23:19:11.783879 14, 0x0, sum = 2
6402 23:19:11.787193 15, 0x0, sum = 3
6403 23:19:11.787307 16, 0x0, sum = 4
6404 23:19:11.790488 best_step = 14
6405 23:19:11.790576
6406 23:19:11.790668 ==
6407 23:19:11.794020 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 23:19:11.797129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 23:19:11.797231 ==
6410 23:19:11.800461 RX Vref Scan: 1
6411 23:19:11.800559
6412 23:19:11.800664 RX Vref 0 -> 0, step: 1
6413 23:19:11.800760
6414 23:19:11.803944 RX Delay -359 -> 252, step: 8
6415 23:19:11.804034
6416 23:19:11.806944 Set Vref, RX VrefLevel [Byte0]: 60
6417 23:19:11.810243 [Byte1]: 50
6418 23:19:11.814733
6419 23:19:11.814802 Final RX Vref Byte 0 = 60 to rank0
6420 23:19:11.818140 Final RX Vref Byte 1 = 50 to rank0
6421 23:19:11.821621 Final RX Vref Byte 0 = 60 to rank1
6422 23:19:11.824667 Final RX Vref Byte 1 = 50 to rank1==
6423 23:19:11.828056 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 23:19:11.834463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 23:19:11.834535 ==
6426 23:19:11.834597 DQS Delay:
6427 23:19:11.837824 DQS0 = 60, DQS1 = 68
6428 23:19:11.837894 DQM Delay:
6429 23:19:11.837953 DQM0 = 14, DQM1 = 13
6430 23:19:11.841201 DQ Delay:
6431 23:19:11.844507 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6432 23:19:11.848104 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6433 23:19:11.848173 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6434 23:19:11.854636 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6435 23:19:11.854706
6436 23:19:11.854808
6437 23:19:11.861275 [DQSOSCAuto] RK0, (LSB)MR18= 0x8583, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6438 23:19:11.864314 CH0 RK0: MR19=C0C, MR18=8583
6439 23:19:11.871023 CH0_RK0: MR19=0xC0C, MR18=0x8583, DQSOSC=393, MR23=63, INC=382, DEC=254
6440 23:19:11.871094 ==
6441 23:19:11.874245 Dram Type= 6, Freq= 0, CH_0, rank 1
6442 23:19:11.877571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 23:19:11.877653 ==
6444 23:19:11.880851 [Gating] SW mode calibration
6445 23:19:11.887477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6446 23:19:11.894276 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6447 23:19:11.897374 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6448 23:19:11.900714 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6449 23:19:11.907449 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 23:19:11.910535 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 23:19:11.913985 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 23:19:11.920622 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 23:19:11.923947 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 23:19:11.927371 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 23:19:11.933875 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 23:19:11.933955 Total UI for P1: 0, mck2ui 16
6457 23:19:11.940260 best dqsien dly found for B0: ( 0, 14, 24)
6458 23:19:11.940341 Total UI for P1: 0, mck2ui 16
6459 23:19:11.946935 best dqsien dly found for B1: ( 0, 14, 24)
6460 23:19:11.950129 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6461 23:19:11.953449 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6462 23:19:11.953548
6463 23:19:11.956744 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6464 23:19:11.960297 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6465 23:19:11.963596 [Gating] SW calibration Done
6466 23:19:11.963693 ==
6467 23:19:11.967040 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 23:19:11.970343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 23:19:11.970413 ==
6470 23:19:11.973634 RX Vref Scan: 0
6471 23:19:11.973701
6472 23:19:11.973759 RX Vref 0 -> 0, step: 1
6473 23:19:11.976560
6474 23:19:11.976625 RX Delay -410 -> 252, step: 16
6475 23:19:11.983174 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6476 23:19:11.986499 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6477 23:19:11.989890 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6478 23:19:11.993091 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6479 23:19:11.999878 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6480 23:19:12.002977 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6481 23:19:12.006288 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6482 23:19:12.009679 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6483 23:19:12.016253 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6484 23:19:12.019737 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6485 23:19:12.022799 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6486 23:19:12.029561 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6487 23:19:12.032873 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6488 23:19:12.036105 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6489 23:19:12.039286 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6490 23:19:12.045980 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6491 23:19:12.046054 ==
6492 23:19:12.049379 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 23:19:12.052626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 23:19:12.052715 ==
6495 23:19:12.052806 DQS Delay:
6496 23:19:12.055837 DQS0 = 59, DQS1 = 59
6497 23:19:12.055930 DQM Delay:
6498 23:19:12.059047 DQM0 = 16, DQM1 = 10
6499 23:19:12.059138 DQ Delay:
6500 23:19:12.062323 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6501 23:19:12.065870 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6502 23:19:12.069187 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6503 23:19:12.072521 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6504 23:19:12.072653
6505 23:19:12.072715
6506 23:19:12.072772 ==
6507 23:19:12.075922 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 23:19:12.079208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 23:19:12.079289 ==
6510 23:19:12.082505
6511 23:19:12.082597
6512 23:19:12.082694 TX Vref Scan disable
6513 23:19:12.085551 == TX Byte 0 ==
6514 23:19:12.088903 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6515 23:19:12.092204 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6516 23:19:12.095549 == TX Byte 1 ==
6517 23:19:12.098952 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6518 23:19:12.102292 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6519 23:19:12.102366 ==
6520 23:19:12.105535 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 23:19:12.108654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 23:19:12.112076 ==
6523 23:19:12.112175
6524 23:19:12.112265
6525 23:19:12.112354 TX Vref Scan disable
6526 23:19:12.115277 == TX Byte 0 ==
6527 23:19:12.118911 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6528 23:19:12.121886 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6529 23:19:12.125222 == TX Byte 1 ==
6530 23:19:12.128846 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6531 23:19:12.131960 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6532 23:19:12.132030
6533 23:19:12.135374 [DATLAT]
6534 23:19:12.135443 Freq=400, CH0 RK1
6535 23:19:12.135508
6536 23:19:12.138468 DATLAT Default: 0xe
6537 23:19:12.138545 0, 0xFFFF, sum = 0
6538 23:19:12.141817 1, 0xFFFF, sum = 0
6539 23:19:12.141888 2, 0xFFFF, sum = 0
6540 23:19:12.145074 3, 0xFFFF, sum = 0
6541 23:19:12.145142 4, 0xFFFF, sum = 0
6542 23:19:12.148650 5, 0xFFFF, sum = 0
6543 23:19:12.148735 6, 0xFFFF, sum = 0
6544 23:19:12.151902 7, 0xFFFF, sum = 0
6545 23:19:12.152022 8, 0xFFFF, sum = 0
6546 23:19:12.155203 9, 0xFFFF, sum = 0
6547 23:19:12.155286 10, 0xFFFF, sum = 0
6548 23:19:12.158737 11, 0xFFFF, sum = 0
6549 23:19:12.158820 12, 0xFFFF, sum = 0
6550 23:19:12.161690 13, 0x0, sum = 1
6551 23:19:12.161765 14, 0x0, sum = 2
6552 23:19:12.165157 15, 0x0, sum = 3
6553 23:19:12.165241 16, 0x0, sum = 4
6554 23:19:12.168226 best_step = 14
6555 23:19:12.168307
6556 23:19:12.168372 ==
6557 23:19:12.171549 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 23:19:12.174989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 23:19:12.175071 ==
6560 23:19:12.178277 RX Vref Scan: 0
6561 23:19:12.178358
6562 23:19:12.178422 RX Vref 0 -> 0, step: 1
6563 23:19:12.178483
6564 23:19:12.181534 RX Delay -359 -> 252, step: 8
6565 23:19:12.189914 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6566 23:19:12.193241 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6567 23:19:12.196189 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6568 23:19:12.199540 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6569 23:19:12.206469 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6570 23:19:12.209788 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6571 23:19:12.212826 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6572 23:19:12.216266 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6573 23:19:12.222808 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6574 23:19:12.226499 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6575 23:19:12.229444 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6576 23:19:12.233227 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6577 23:19:12.239782 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6578 23:19:12.242952 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6579 23:19:12.246446 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6580 23:19:12.252940 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6581 23:19:12.253021 ==
6582 23:19:12.256169 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 23:19:12.259569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 23:19:12.259666 ==
6585 23:19:12.259779 DQS Delay:
6586 23:19:12.262874 DQS0 = 60, DQS1 = 72
6587 23:19:12.262943 DQM Delay:
6588 23:19:12.266180 DQM0 = 11, DQM1 = 17
6589 23:19:12.266251 DQ Delay:
6590 23:19:12.269443 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6591 23:19:12.272735 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6592 23:19:12.276196 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6593 23:19:12.279300 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6594 23:19:12.279369
6595 23:19:12.279428
6596 23:19:12.285887 [DQSOSCAuto] RK1, (LSB)MR18= 0xcb81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6597 23:19:12.289413 CH0 RK1: MR19=C0C, MR18=CB81
6598 23:19:12.296092 CH0_RK1: MR19=0xC0C, MR18=0xCB81, DQSOSC=384, MR23=63, INC=400, DEC=267
6599 23:19:12.299489 [RxdqsGatingPostProcess] freq 400
6600 23:19:12.302843 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6601 23:19:12.306150 best DQS0 dly(2T, 0.5T) = (0, 10)
6602 23:19:12.309182 best DQS1 dly(2T, 0.5T) = (0, 10)
6603 23:19:12.312513 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6604 23:19:12.316091 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6605 23:19:12.319369 best DQS0 dly(2T, 0.5T) = (0, 10)
6606 23:19:12.322571 best DQS1 dly(2T, 0.5T) = (0, 10)
6607 23:19:12.325815 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6608 23:19:12.328955 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6609 23:19:12.332590 Pre-setting of DQS Precalculation
6610 23:19:12.335942 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6611 23:19:12.339335 ==
6612 23:19:12.342339 Dram Type= 6, Freq= 0, CH_1, rank 0
6613 23:19:12.345731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 23:19:12.345813 ==
6615 23:19:12.349143 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6616 23:19:12.355479 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6617 23:19:12.358850 [CA 0] Center 36 (8~64) winsize 57
6618 23:19:12.362334 [CA 1] Center 36 (8~64) winsize 57
6619 23:19:12.365442 [CA 2] Center 36 (8~64) winsize 57
6620 23:19:12.368769 [CA 3] Center 36 (8~64) winsize 57
6621 23:19:12.372010 [CA 4] Center 36 (8~64) winsize 57
6622 23:19:12.375428 [CA 5] Center 36 (8~64) winsize 57
6623 23:19:12.375556
6624 23:19:12.378639 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6625 23:19:12.378738
6626 23:19:12.381978 [CATrainingPosCal] consider 1 rank data
6627 23:19:12.385591 u2DelayCellTimex100 = 270/100 ps
6628 23:19:12.388619 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 23:19:12.392097 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 23:19:12.395287 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 23:19:12.402067 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 23:19:12.405458 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 23:19:12.408513 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 23:19:12.408609
6635 23:19:12.411905 CA PerBit enable=1, Macro0, CA PI delay=36
6636 23:19:12.412002
6637 23:19:12.415243 [CBTSetCACLKResult] CA Dly = 36
6638 23:19:12.415315 CS Dly: 1 (0~32)
6639 23:19:12.415377 ==
6640 23:19:12.418567 Dram Type= 6, Freq= 0, CH_1, rank 1
6641 23:19:12.425199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 23:19:12.425299 ==
6643 23:19:12.428442 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6644 23:19:12.435185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6645 23:19:12.438485 [CA 0] Center 36 (8~64) winsize 57
6646 23:19:12.441776 [CA 1] Center 36 (8~64) winsize 57
6647 23:19:12.445075 [CA 2] Center 36 (8~64) winsize 57
6648 23:19:12.448428 [CA 3] Center 36 (8~64) winsize 57
6649 23:19:12.451764 [CA 4] Center 36 (8~64) winsize 57
6650 23:19:12.455146 [CA 5] Center 36 (8~64) winsize 57
6651 23:19:12.455243
6652 23:19:12.458561 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6653 23:19:12.458632
6654 23:19:12.461463 [CATrainingPosCal] consider 2 rank data
6655 23:19:12.464769 u2DelayCellTimex100 = 270/100 ps
6656 23:19:12.468319 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 23:19:12.471515 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 23:19:12.474795 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 23:19:12.478088 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 23:19:12.481255 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 23:19:12.487991 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 23:19:12.488095
6663 23:19:12.491309 CA PerBit enable=1, Macro0, CA PI delay=36
6664 23:19:12.491408
6665 23:19:12.494655 [CBTSetCACLKResult] CA Dly = 36
6666 23:19:12.494737 CS Dly: 1 (0~32)
6667 23:19:12.494797
6668 23:19:12.498043 ----->DramcWriteLeveling(PI) begin...
6669 23:19:12.498141 ==
6670 23:19:12.501133 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 23:19:12.504485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 23:19:12.507672 ==
6673 23:19:12.507778 Write leveling (Byte 0): 40 => 8
6674 23:19:12.510958 Write leveling (Byte 1): 40 => 8
6675 23:19:12.514315 DramcWriteLeveling(PI) end<-----
6676 23:19:12.514389
6677 23:19:12.514455 ==
6678 23:19:12.517896 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 23:19:12.524266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 23:19:12.524369 ==
6681 23:19:12.527539 [Gating] SW mode calibration
6682 23:19:12.534438 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6683 23:19:12.537550 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6684 23:19:12.544409 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6685 23:19:12.547702 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6686 23:19:12.551083 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 23:19:12.557425 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 23:19:12.560699 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 23:19:12.564048 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 23:19:12.570515 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 23:19:12.574139 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 23:19:12.577037 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 23:19:12.580527 Total UI for P1: 0, mck2ui 16
6694 23:19:12.583725 best dqsien dly found for B0: ( 0, 14, 24)
6695 23:19:12.586898 Total UI for P1: 0, mck2ui 16
6696 23:19:12.590505 best dqsien dly found for B1: ( 0, 14, 24)
6697 23:19:12.593594 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6698 23:19:12.596857 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6699 23:19:12.596950
6700 23:19:12.603714 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6701 23:19:12.606984 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6702 23:19:12.607056 [Gating] SW calibration Done
6703 23:19:12.610288 ==
6704 23:19:12.610386 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 23:19:12.616969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 23:19:12.617047 ==
6707 23:19:12.617110 RX Vref Scan: 0
6708 23:19:12.617169
6709 23:19:12.620342 RX Vref 0 -> 0, step: 1
6710 23:19:12.620442
6711 23:19:12.623603 RX Delay -410 -> 252, step: 16
6712 23:19:12.626977 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6713 23:19:12.630326 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6714 23:19:12.637086 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6715 23:19:12.640114 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6716 23:19:12.643565 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6717 23:19:12.646848 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6718 23:19:12.653312 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6719 23:19:12.656605 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6720 23:19:12.659980 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6721 23:19:12.663319 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6722 23:19:12.670025 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6723 23:19:12.673390 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6724 23:19:12.676716 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6725 23:19:12.683262 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6726 23:19:12.686581 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6727 23:19:12.689692 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6728 23:19:12.689800 ==
6729 23:19:12.693039 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 23:19:12.696486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 23:19:12.696590 ==
6732 23:19:12.699638 DQS Delay:
6733 23:19:12.699740 DQS0 = 43, DQS1 = 67
6734 23:19:12.703156 DQM Delay:
6735 23:19:12.703256 DQM0 = 6, DQM1 = 19
6736 23:19:12.706547 DQ Delay:
6737 23:19:12.706653 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6738 23:19:12.709590 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6739 23:19:12.713175 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6740 23:19:12.716312 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6741 23:19:12.716417
6742 23:19:12.716512
6743 23:19:12.716603 ==
6744 23:19:12.719726 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 23:19:12.726248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 23:19:12.726329 ==
6747 23:19:12.726393
6748 23:19:12.726458
6749 23:19:12.726521 TX Vref Scan disable
6750 23:19:12.729482 == TX Byte 0 ==
6751 23:19:12.733033 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 23:19:12.736092 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 23:19:12.739265 == TX Byte 1 ==
6754 23:19:12.742727 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 23:19:12.745909 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 23:19:12.749127 ==
6757 23:19:12.752560 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 23:19:12.755777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 23:19:12.755883 ==
6760 23:19:12.755977
6761 23:19:12.756067
6762 23:19:12.759371 TX Vref Scan disable
6763 23:19:12.759475 == TX Byte 0 ==
6764 23:19:12.762498 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 23:19:12.769193 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 23:19:12.769295 == TX Byte 1 ==
6767 23:19:12.772496 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 23:19:12.778832 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 23:19:12.778934
6770 23:19:12.779025 [DATLAT]
6771 23:19:12.779118 Freq=400, CH1 RK0
6772 23:19:12.779207
6773 23:19:12.782195 DATLAT Default: 0xf
6774 23:19:12.782291 0, 0xFFFF, sum = 0
6775 23:19:12.785486 1, 0xFFFF, sum = 0
6776 23:19:12.789052 2, 0xFFFF, sum = 0
6777 23:19:12.789177 3, 0xFFFF, sum = 0
6778 23:19:12.792382 4, 0xFFFF, sum = 0
6779 23:19:12.792507 5, 0xFFFF, sum = 0
6780 23:19:12.795406 6, 0xFFFF, sum = 0
6781 23:19:12.795526 7, 0xFFFF, sum = 0
6782 23:19:12.798584 8, 0xFFFF, sum = 0
6783 23:19:12.798703 9, 0xFFFF, sum = 0
6784 23:19:12.801945 10, 0xFFFF, sum = 0
6785 23:19:12.802029 11, 0xFFFF, sum = 0
6786 23:19:12.805287 12, 0xFFFF, sum = 0
6787 23:19:12.805397 13, 0x0, sum = 1
6788 23:19:12.808436 14, 0x0, sum = 2
6789 23:19:12.808565 15, 0x0, sum = 3
6790 23:19:12.811845 16, 0x0, sum = 4
6791 23:19:12.811945 best_step = 14
6792 23:19:12.812046
6793 23:19:12.812135 ==
6794 23:19:12.815075 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 23:19:12.821836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 23:19:12.821939 ==
6797 23:19:12.822041 RX Vref Scan: 1
6798 23:19:12.822128
6799 23:19:12.825201 RX Vref 0 -> 0, step: 1
6800 23:19:12.825318
6801 23:19:12.828466 RX Delay -375 -> 252, step: 8
6802 23:19:12.828564
6803 23:19:12.832115 Set Vref, RX VrefLevel [Byte0]: 57
6804 23:19:12.834931 [Byte1]: 51
6805 23:19:12.835039
6806 23:19:12.838287 Final RX Vref Byte 0 = 57 to rank0
6807 23:19:12.841625 Final RX Vref Byte 1 = 51 to rank0
6808 23:19:12.844829 Final RX Vref Byte 0 = 57 to rank1
6809 23:19:12.848400 Final RX Vref Byte 1 = 51 to rank1==
6810 23:19:12.851812 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 23:19:12.854901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 23:19:12.858141 ==
6813 23:19:12.858245 DQS Delay:
6814 23:19:12.858339 DQS0 = 52, DQS1 = 64
6815 23:19:12.861676 DQM Delay:
6816 23:19:12.861778 DQM0 = 9, DQM1 = 11
6817 23:19:12.864808 DQ Delay:
6818 23:19:12.864905 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6819 23:19:12.867896 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6820 23:19:12.871339 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6821 23:19:12.874678 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6822 23:19:12.874778
6823 23:19:12.874845
6824 23:19:12.884552 [DQSOSCAuto] RK0, (LSB)MR18= 0x5569, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6825 23:19:12.887813 CH1 RK0: MR19=C0C, MR18=5569
6826 23:19:12.894557 CH1_RK0: MR19=0xC0C, MR18=0x5569, DQSOSC=396, MR23=63, INC=376, DEC=251
6827 23:19:12.894662 ==
6828 23:19:12.897917 Dram Type= 6, Freq= 0, CH_1, rank 1
6829 23:19:12.901186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 23:19:12.901293 ==
6831 23:19:12.904505 [Gating] SW mode calibration
6832 23:19:12.911089 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6833 23:19:12.914450 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6834 23:19:12.921089 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6835 23:19:12.924327 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6836 23:19:12.930902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 23:19:12.934400 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 23:19:12.937603 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 23:19:12.940819 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 23:19:12.947293 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 23:19:12.950617 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 23:19:12.953854 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 23:19:12.957128 Total UI for P1: 0, mck2ui 16
6844 23:19:12.960465 best dqsien dly found for B0: ( 0, 14, 24)
6845 23:19:12.964012 Total UI for P1: 0, mck2ui 16
6846 23:19:12.967013 best dqsien dly found for B1: ( 0, 14, 24)
6847 23:19:12.970396 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6848 23:19:12.976997 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6849 23:19:12.977131
6850 23:19:12.980493 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6851 23:19:12.983854 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6852 23:19:12.986871 [Gating] SW calibration Done
6853 23:19:12.986975 ==
6854 23:19:12.990119 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 23:19:12.993518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 23:19:12.993629 ==
6857 23:19:12.997029 RX Vref Scan: 0
6858 23:19:12.997132
6859 23:19:12.997225 RX Vref 0 -> 0, step: 1
6860 23:19:12.997316
6861 23:19:13.000053 RX Delay -410 -> 252, step: 16
6862 23:19:13.003369 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6863 23:19:13.009945 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6864 23:19:13.013601 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6865 23:19:13.016700 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6866 23:19:13.020119 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6867 23:19:13.026825 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6868 23:19:13.029963 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6869 23:19:13.033106 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6870 23:19:13.039852 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6871 23:19:13.043091 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6872 23:19:13.046397 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6873 23:19:13.049930 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6874 23:19:13.056396 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6875 23:19:13.059664 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6876 23:19:13.062897 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6877 23:19:13.066496 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6878 23:19:13.069728 ==
6879 23:19:13.069833 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 23:19:13.076279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 23:19:13.076364 ==
6882 23:19:13.076431 DQS Delay:
6883 23:19:13.079372 DQS0 = 59, DQS1 = 59
6884 23:19:13.079451 DQM Delay:
6885 23:19:13.082920 DQM0 = 19, DQM1 = 14
6886 23:19:13.082998 DQ Delay:
6887 23:19:13.086053 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6888 23:19:13.089430 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6889 23:19:13.092638 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6890 23:19:13.096180 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6891 23:19:13.096261
6892 23:19:13.096326
6893 23:19:13.096387 ==
6894 23:19:13.099463 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 23:19:13.102848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 23:19:13.102925 ==
6897 23:19:13.102990
6898 23:19:13.103050
6899 23:19:13.105952 TX Vref Scan disable
6900 23:19:13.106029 == TX Byte 0 ==
6901 23:19:13.112581 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6902 23:19:13.116105 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6903 23:19:13.116182 == TX Byte 1 ==
6904 23:19:13.122419 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6905 23:19:13.125830 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6906 23:19:13.125906 ==
6907 23:19:13.129157 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 23:19:13.132424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 23:19:13.132499 ==
6910 23:19:13.132563
6911 23:19:13.132626
6912 23:19:13.135694 TX Vref Scan disable
6913 23:19:13.135768 == TX Byte 0 ==
6914 23:19:13.142509 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6915 23:19:13.145824 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6916 23:19:13.145898 == TX Byte 1 ==
6917 23:19:13.152552 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6918 23:19:13.155821 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6919 23:19:13.155897
6920 23:19:13.155964 [DATLAT]
6921 23:19:13.159005 Freq=400, CH1 RK1
6922 23:19:13.159080
6923 23:19:13.159143 DATLAT Default: 0xe
6924 23:19:13.162367 0, 0xFFFF, sum = 0
6925 23:19:13.162445 1, 0xFFFF, sum = 0
6926 23:19:13.165653 2, 0xFFFF, sum = 0
6927 23:19:13.165733 3, 0xFFFF, sum = 0
6928 23:19:13.169213 4, 0xFFFF, sum = 0
6929 23:19:13.169288 5, 0xFFFF, sum = 0
6930 23:19:13.172244 6, 0xFFFF, sum = 0
6931 23:19:13.172320 7, 0xFFFF, sum = 0
6932 23:19:13.175568 8, 0xFFFF, sum = 0
6933 23:19:13.175643 9, 0xFFFF, sum = 0
6934 23:19:13.179164 10, 0xFFFF, sum = 0
6935 23:19:13.182247 11, 0xFFFF, sum = 0
6936 23:19:13.182329 12, 0xFFFF, sum = 0
6937 23:19:13.185581 13, 0x0, sum = 1
6938 23:19:13.185657 14, 0x0, sum = 2
6939 23:19:13.188926 15, 0x0, sum = 3
6940 23:19:13.189011 16, 0x0, sum = 4
6941 23:19:13.189101 best_step = 14
6942 23:19:13.189166
6943 23:19:13.192434 ==
6944 23:19:13.192513 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 23:19:13.199232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 23:19:13.199314 ==
6947 23:19:13.199379 RX Vref Scan: 0
6948 23:19:13.199441
6949 23:19:13.202230 RX Vref 0 -> 0, step: 1
6950 23:19:13.202311
6951 23:19:13.205808 RX Delay -359 -> 252, step: 8
6952 23:19:13.212516 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6953 23:19:13.215703 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6954 23:19:13.219377 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6955 23:19:13.222273 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6956 23:19:13.229053 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6957 23:19:13.232399 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6958 23:19:13.235657 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6959 23:19:13.239046 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6960 23:19:13.245624 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6961 23:19:13.249010 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6962 23:19:13.251987 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6963 23:19:13.259096 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6964 23:19:13.262265 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6965 23:19:13.265615 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6966 23:19:13.268923 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6967 23:19:13.275646 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6968 23:19:13.275727 ==
6969 23:19:13.278955 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 23:19:13.282290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 23:19:13.282368 ==
6972 23:19:13.282437 DQS Delay:
6973 23:19:13.285653 DQS0 = 60, DQS1 = 64
6974 23:19:13.285730 DQM Delay:
6975 23:19:13.288846 DQM0 = 12, DQM1 = 10
6976 23:19:13.288924 DQ Delay:
6977 23:19:13.292024 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6978 23:19:13.295502 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6979 23:19:13.298603 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6980 23:19:13.301964 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6981 23:19:13.302040
6982 23:19:13.302103
6983 23:19:13.308669 [DQSOSCAuto] RK1, (LSB)MR18= 0x7aab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6984 23:19:13.311758 CH1 RK1: MR19=C0C, MR18=7AAB
6985 23:19:13.318488 CH1_RK1: MR19=0xC0C, MR18=0x7AAB, DQSOSC=388, MR23=63, INC=392, DEC=261
6986 23:19:13.321683 [RxdqsGatingPostProcess] freq 400
6987 23:19:13.328273 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6988 23:19:13.331619 best DQS0 dly(2T, 0.5T) = (0, 10)
6989 23:19:13.331703 best DQS1 dly(2T, 0.5T) = (0, 10)
6990 23:19:13.334953 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6991 23:19:13.338522 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6992 23:19:13.341904 best DQS0 dly(2T, 0.5T) = (0, 10)
6993 23:19:13.345215 best DQS1 dly(2T, 0.5T) = (0, 10)
6994 23:19:13.348509 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6995 23:19:13.351763 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6996 23:19:13.354946 Pre-setting of DQS Precalculation
6997 23:19:13.361691 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6998 23:19:13.368225 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6999 23:19:13.374924 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7000 23:19:13.375009
7001 23:19:13.375073
7002 23:19:13.378192 [Calibration Summary] 800 Mbps
7003 23:19:13.378287 CH 0, Rank 0
7004 23:19:13.381520 SW Impedance : PASS
7005 23:19:13.384799 DUTY Scan : NO K
7006 23:19:13.384914 ZQ Calibration : PASS
7007 23:19:13.388173 Jitter Meter : NO K
7008 23:19:13.391517 CBT Training : PASS
7009 23:19:13.391672 Write leveling : PASS
7010 23:19:13.394748 RX DQS gating : PASS
7011 23:19:13.398066 RX DQ/DQS(RDDQC) : PASS
7012 23:19:13.398164 TX DQ/DQS : PASS
7013 23:19:13.401201 RX DATLAT : PASS
7014 23:19:13.401286 RX DQ/DQS(Engine): PASS
7015 23:19:13.404716 TX OE : NO K
7016 23:19:13.404812 All Pass.
7017 23:19:13.404874
7018 23:19:13.407994 CH 0, Rank 1
7019 23:19:13.408082 SW Impedance : PASS
7020 23:19:13.411365 DUTY Scan : NO K
7021 23:19:13.414535 ZQ Calibration : PASS
7022 23:19:13.414661 Jitter Meter : NO K
7023 23:19:13.417994 CBT Training : PASS
7024 23:19:13.421159 Write leveling : NO K
7025 23:19:13.421253 RX DQS gating : PASS
7026 23:19:13.424645 RX DQ/DQS(RDDQC) : PASS
7027 23:19:13.427674 TX DQ/DQS : PASS
7028 23:19:13.427762 RX DATLAT : PASS
7029 23:19:13.431087 RX DQ/DQS(Engine): PASS
7030 23:19:13.434525 TX OE : NO K
7031 23:19:13.434693 All Pass.
7032 23:19:13.434805
7033 23:19:13.434907 CH 1, Rank 0
7034 23:19:13.437840 SW Impedance : PASS
7035 23:19:13.441267 DUTY Scan : NO K
7036 23:19:13.441347 ZQ Calibration : PASS
7037 23:19:13.444442 Jitter Meter : NO K
7038 23:19:13.447701 CBT Training : PASS
7039 23:19:13.447786 Write leveling : PASS
7040 23:19:13.451031 RX DQS gating : PASS
7041 23:19:13.454246 RX DQ/DQS(RDDQC) : PASS
7042 23:19:13.454338 TX DQ/DQS : PASS
7043 23:19:13.457633 RX DATLAT : PASS
7044 23:19:13.457722 RX DQ/DQS(Engine): PASS
7045 23:19:13.460773 TX OE : NO K
7046 23:19:13.460923 All Pass.
7047 23:19:13.461058
7048 23:19:13.464165 CH 1, Rank 1
7049 23:19:13.464240 SW Impedance : PASS
7050 23:19:13.467489 DUTY Scan : NO K
7051 23:19:13.470843 ZQ Calibration : PASS
7052 23:19:13.470920 Jitter Meter : NO K
7053 23:19:13.474067 CBT Training : PASS
7054 23:19:13.477411 Write leveling : NO K
7055 23:19:13.477509 RX DQS gating : PASS
7056 23:19:13.480768 RX DQ/DQS(RDDQC) : PASS
7057 23:19:13.484019 TX DQ/DQS : PASS
7058 23:19:13.484093 RX DATLAT : PASS
7059 23:19:13.487396 RX DQ/DQS(Engine): PASS
7060 23:19:13.490661 TX OE : NO K
7061 23:19:13.490739 All Pass.
7062 23:19:13.490809
7063 23:19:13.494009 DramC Write-DBI off
7064 23:19:13.494084 PER_BANK_REFRESH: Hybrid Mode
7065 23:19:13.497395 TX_TRACKING: ON
7066 23:19:13.504189 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7067 23:19:13.510416 [FAST_K] Save calibration result to emmc
7068 23:19:13.514032 dramc_set_vcore_voltage set vcore to 725000
7069 23:19:13.514119 Read voltage for 1600, 0
7070 23:19:13.517410 Vio18 = 0
7071 23:19:13.517520 Vcore = 725000
7072 23:19:13.517613 Vdram = 0
7073 23:19:13.520593 Vddq = 0
7074 23:19:13.520663 Vmddr = 0
7075 23:19:13.523960 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7076 23:19:13.530621 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7077 23:19:13.533990 MEM_TYPE=3, freq_sel=13
7078 23:19:13.537276 sv_algorithm_assistance_LP4_3733
7079 23:19:13.540446 ============ PULL DRAM RESETB DOWN ============
7080 23:19:13.543890 ========== PULL DRAM RESETB DOWN end =========
7081 23:19:13.550491 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7082 23:19:13.553761 ===================================
7083 23:19:13.553836 LPDDR4 DRAM CONFIGURATION
7084 23:19:13.557052 ===================================
7085 23:19:13.560168 EX_ROW_EN[0] = 0x0
7086 23:19:13.560242 EX_ROW_EN[1] = 0x0
7087 23:19:13.563580 LP4Y_EN = 0x0
7088 23:19:13.563675 WORK_FSP = 0x1
7089 23:19:13.567192 WL = 0x5
7090 23:19:13.567286 RL = 0x5
7091 23:19:13.570395 BL = 0x2
7092 23:19:13.573766 RPST = 0x0
7093 23:19:13.573842 RD_PRE = 0x0
7094 23:19:13.576936 WR_PRE = 0x1
7095 23:19:13.577008 WR_PST = 0x1
7096 23:19:13.580204 DBI_WR = 0x0
7097 23:19:13.580289 DBI_RD = 0x0
7098 23:19:13.583508 OTF = 0x1
7099 23:19:13.586785 ===================================
7100 23:19:13.590361 ===================================
7101 23:19:13.590473 ANA top config
7102 23:19:13.593648 ===================================
7103 23:19:13.596963 DLL_ASYNC_EN = 0
7104 23:19:13.600327 ALL_SLAVE_EN = 0
7105 23:19:13.600424 NEW_RANK_MODE = 1
7106 23:19:13.603572 DLL_IDLE_MODE = 1
7107 23:19:13.606817 LP45_APHY_COMB_EN = 1
7108 23:19:13.610193 TX_ODT_DIS = 0
7109 23:19:13.613426 NEW_8X_MODE = 1
7110 23:19:13.616497 ===================================
7111 23:19:13.616605 ===================================
7112 23:19:13.619762 data_rate = 3200
7113 23:19:13.623175 CKR = 1
7114 23:19:13.626442 DQ_P2S_RATIO = 8
7115 23:19:13.629689 ===================================
7116 23:19:13.633004 CA_P2S_RATIO = 8
7117 23:19:13.636409 DQ_CA_OPEN = 0
7118 23:19:13.639892 DQ_SEMI_OPEN = 0
7119 23:19:13.639992 CA_SEMI_OPEN = 0
7120 23:19:13.643015 CA_FULL_RATE = 0
7121 23:19:13.646396 DQ_CKDIV4_EN = 0
7122 23:19:13.650027 CA_CKDIV4_EN = 0
7123 23:19:13.653017 CA_PREDIV_EN = 0
7124 23:19:13.656756 PH8_DLY = 12
7125 23:19:13.656864 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7126 23:19:13.660004 DQ_AAMCK_DIV = 4
7127 23:19:13.663406 CA_AAMCK_DIV = 4
7128 23:19:13.666320 CA_ADMCK_DIV = 4
7129 23:19:13.669719 DQ_TRACK_CA_EN = 0
7130 23:19:13.673013 CA_PICK = 1600
7131 23:19:13.673128 CA_MCKIO = 1600
7132 23:19:13.676841 MCKIO_SEMI = 0
7133 23:19:13.679998 PLL_FREQ = 3068
7134 23:19:13.682925 DQ_UI_PI_RATIO = 32
7135 23:19:13.686482 CA_UI_PI_RATIO = 0
7136 23:19:13.689683 ===================================
7137 23:19:13.693135 ===================================
7138 23:19:13.696059 memory_type:LPDDR4
7139 23:19:13.696141 GP_NUM : 10
7140 23:19:13.699520 SRAM_EN : 1
7141 23:19:13.699628 MD32_EN : 0
7142 23:19:13.703044 ===================================
7143 23:19:13.706241 [ANA_INIT] >>>>>>>>>>>>>>
7144 23:19:13.709617 <<<<<< [CONFIGURE PHASE]: ANA_TX
7145 23:19:13.712771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7146 23:19:13.716092 ===================================
7147 23:19:13.719153 data_rate = 3200,PCW = 0X7600
7148 23:19:13.722604 ===================================
7149 23:19:13.725848 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7150 23:19:13.732822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7151 23:19:13.736120 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7152 23:19:13.742683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7153 23:19:13.745996 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7154 23:19:13.748904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7155 23:19:13.748986 [ANA_INIT] flow start
7156 23:19:13.752636 [ANA_INIT] PLL >>>>>>>>
7157 23:19:13.755526 [ANA_INIT] PLL <<<<<<<<
7158 23:19:13.758913 [ANA_INIT] MIDPI >>>>>>>>
7159 23:19:13.758999 [ANA_INIT] MIDPI <<<<<<<<
7160 23:19:13.762305 [ANA_INIT] DLL >>>>>>>>
7161 23:19:13.765754 [ANA_INIT] DLL <<<<<<<<
7162 23:19:13.765836 [ANA_INIT] flow end
7163 23:19:13.768971 ============ LP4 DIFF to SE enter ============
7164 23:19:13.775728 ============ LP4 DIFF to SE exit ============
7165 23:19:13.775810 [ANA_INIT] <<<<<<<<<<<<<
7166 23:19:13.779053 [Flow] Enable top DCM control >>>>>
7167 23:19:13.782278 [Flow] Enable top DCM control <<<<<
7168 23:19:13.785836 Enable DLL master slave shuffle
7169 23:19:13.792556 ==============================================================
7170 23:19:13.792641 Gating Mode config
7171 23:19:13.798795 ==============================================================
7172 23:19:13.802455 Config description:
7173 23:19:13.812098 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7174 23:19:13.818578 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7175 23:19:13.821923 SELPH_MODE 0: By rank 1: By Phase
7176 23:19:13.828503 ==============================================================
7177 23:19:13.831962 GAT_TRACK_EN = 1
7178 23:19:13.835122 RX_GATING_MODE = 2
7179 23:19:13.835230 RX_GATING_TRACK_MODE = 2
7180 23:19:13.838442 SELPH_MODE = 1
7181 23:19:13.841847 PICG_EARLY_EN = 1
7182 23:19:13.845162 VALID_LAT_VALUE = 1
7183 23:19:13.851867 ==============================================================
7184 23:19:13.854941 Enter into Gating configuration >>>>
7185 23:19:13.858187 Exit from Gating configuration <<<<
7186 23:19:13.861557 Enter into DVFS_PRE_config >>>>>
7187 23:19:13.871685 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7188 23:19:13.874737 Exit from DVFS_PRE_config <<<<<
7189 23:19:13.878385 Enter into PICG configuration >>>>
7190 23:19:13.881689 Exit from PICG configuration <<<<
7191 23:19:13.885014 [RX_INPUT] configuration >>>>>
7192 23:19:13.887973 [RX_INPUT] configuration <<<<<
7193 23:19:13.891640 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7194 23:19:13.898263 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7195 23:19:13.904823 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 23:19:13.911405 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 23:19:13.914660 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7198 23:19:13.921583 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7199 23:19:13.924488 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7200 23:19:13.931318 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7201 23:19:13.934837 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7202 23:19:13.937930 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7203 23:19:13.941360 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7204 23:19:13.947675 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7205 23:19:13.950968 ===================================
7206 23:19:13.954475 LPDDR4 DRAM CONFIGURATION
7207 23:19:13.957854 ===================================
7208 23:19:13.957936 EX_ROW_EN[0] = 0x0
7209 23:19:13.961026 EX_ROW_EN[1] = 0x0
7210 23:19:13.961108 LP4Y_EN = 0x0
7211 23:19:13.964524 WORK_FSP = 0x1
7212 23:19:13.964605 WL = 0x5
7213 23:19:13.967956 RL = 0x5
7214 23:19:13.968037 BL = 0x2
7215 23:19:13.970943 RPST = 0x0
7216 23:19:13.971029 RD_PRE = 0x0
7217 23:19:13.974218 WR_PRE = 0x1
7218 23:19:13.974300 WR_PST = 0x1
7219 23:19:13.977763 DBI_WR = 0x0
7220 23:19:13.977845 DBI_RD = 0x0
7221 23:19:13.981005 OTF = 0x1
7222 23:19:13.984102 ===================================
7223 23:19:13.987592 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7224 23:19:13.990991 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7225 23:19:13.997293 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 23:19:14.000528 ===================================
7227 23:19:14.000611 LPDDR4 DRAM CONFIGURATION
7228 23:19:14.003839 ===================================
7229 23:19:14.007472 EX_ROW_EN[0] = 0x10
7230 23:19:14.010762 EX_ROW_EN[1] = 0x0
7231 23:19:14.010839 LP4Y_EN = 0x0
7232 23:19:14.013843 WORK_FSP = 0x1
7233 23:19:14.013925 WL = 0x5
7234 23:19:14.017116 RL = 0x5
7235 23:19:14.017203 BL = 0x2
7236 23:19:14.020771 RPST = 0x0
7237 23:19:14.020853 RD_PRE = 0x0
7238 23:19:14.024000 WR_PRE = 0x1
7239 23:19:14.024081 WR_PST = 0x1
7240 23:19:14.027450 DBI_WR = 0x0
7241 23:19:14.027531 DBI_RD = 0x0
7242 23:19:14.030746 OTF = 0x1
7243 23:19:14.033801 ===================================
7244 23:19:14.040678 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7245 23:19:14.040760 ==
7246 23:19:14.044005 Dram Type= 6, Freq= 0, CH_0, rank 0
7247 23:19:14.047233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7248 23:19:14.047315 ==
7249 23:19:14.050591 [Duty_Offset_Calibration]
7250 23:19:14.050672 B0:2 B1:0 CA:3
7251 23:19:14.050737
7252 23:19:14.053846 [DutyScan_Calibration_Flow] k_type=0
7253 23:19:14.064706
7254 23:19:14.064787 ==CLK 0==
7255 23:19:14.068041 Final CLK duty delay cell = 0
7256 23:19:14.071260 [0] MAX Duty = 5031%(X100), DQS PI = 12
7257 23:19:14.074731 [0] MIN Duty = 4907%(X100), DQS PI = 6
7258 23:19:14.074812 [0] AVG Duty = 4969%(X100)
7259 23:19:14.077938
7260 23:19:14.081582 CH0 CLK Duty spec in!! Max-Min= 124%
7261 23:19:14.084509 [DutyScan_Calibration_Flow] ====Done====
7262 23:19:14.084588
7263 23:19:14.087743 [DutyScan_Calibration_Flow] k_type=1
7264 23:19:14.104576
7265 23:19:14.104660 ==DQS 0 ==
7266 23:19:14.108016 Final DQS duty delay cell = 0
7267 23:19:14.111470 [0] MAX Duty = 5094%(X100), DQS PI = 12
7268 23:19:14.114778 [0] MIN Duty = 4875%(X100), DQS PI = 48
7269 23:19:14.118139 [0] AVG Duty = 4984%(X100)
7270 23:19:14.118218
7271 23:19:14.118281 ==DQS 1 ==
7272 23:19:14.121414 Final DQS duty delay cell = 0
7273 23:19:14.124624 [0] MAX Duty = 5156%(X100), DQS PI = 32
7274 23:19:14.127885 [0] MIN Duty = 5031%(X100), DQS PI = 14
7275 23:19:14.131095 [0] AVG Duty = 5093%(X100)
7276 23:19:14.131174
7277 23:19:14.134746 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7278 23:19:14.134826
7279 23:19:14.137966 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7280 23:19:14.141300 [DutyScan_Calibration_Flow] ====Done====
7281 23:19:14.141418
7282 23:19:14.144482 [DutyScan_Calibration_Flow] k_type=3
7283 23:19:14.162842
7284 23:19:14.162921 ==DQM 0 ==
7285 23:19:14.166033 Final DQM duty delay cell = 0
7286 23:19:14.169309 [0] MAX Duty = 5156%(X100), DQS PI = 14
7287 23:19:14.172600 [0] MIN Duty = 4875%(X100), DQS PI = 0
7288 23:19:14.175871 [0] AVG Duty = 5015%(X100)
7289 23:19:14.175953
7290 23:19:14.176018 ==DQM 1 ==
7291 23:19:14.179518 Final DQM duty delay cell = 4
7292 23:19:14.182466 [4] MAX Duty = 5156%(X100), DQS PI = 52
7293 23:19:14.185738 [4] MIN Duty = 5000%(X100), DQS PI = 12
7294 23:19:14.189003 [4] AVG Duty = 5078%(X100)
7295 23:19:14.189113
7296 23:19:14.192480 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7297 23:19:14.192565
7298 23:19:14.195736 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7299 23:19:14.198812 [DutyScan_Calibration_Flow] ====Done====
7300 23:19:14.198932
7301 23:19:14.202124 [DutyScan_Calibration_Flow] k_type=2
7302 23:19:14.218904
7303 23:19:14.219010 ==DQ 0 ==
7304 23:19:14.222455 Final DQ duty delay cell = -4
7305 23:19:14.225487 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7306 23:19:14.228968 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7307 23:19:14.232198 [-4] AVG Duty = 4938%(X100)
7308 23:19:14.232272
7309 23:19:14.232375 ==DQ 1 ==
7310 23:19:14.235480 Final DQ duty delay cell = 0
7311 23:19:14.238981 [0] MAX Duty = 5156%(X100), DQS PI = 60
7312 23:19:14.242345 [0] MIN Duty = 5000%(X100), DQS PI = 16
7313 23:19:14.245678 [0] AVG Duty = 5078%(X100)
7314 23:19:14.245760
7315 23:19:14.249008 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7316 23:19:14.249117
7317 23:19:14.252459 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7318 23:19:14.255274 [DutyScan_Calibration_Flow] ====Done====
7319 23:19:14.255376 ==
7320 23:19:14.258946 Dram Type= 6, Freq= 0, CH_1, rank 0
7321 23:19:14.262233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7322 23:19:14.262326 ==
7323 23:19:14.265378 [Duty_Offset_Calibration]
7324 23:19:14.265453 B0:1 B1:-2 CA:1
7325 23:19:14.265535
7326 23:19:14.268736 [DutyScan_Calibration_Flow] k_type=0
7327 23:19:14.279469
7328 23:19:14.279559 ==CLK 0==
7329 23:19:14.282718 Final CLK duty delay cell = 0
7330 23:19:14.286390 [0] MAX Duty = 5094%(X100), DQS PI = 22
7331 23:19:14.289411 [0] MIN Duty = 4844%(X100), DQS PI = 4
7332 23:19:14.289528 [0] AVG Duty = 4969%(X100)
7333 23:19:14.292768
7334 23:19:14.296098 CH1 CLK Duty spec in!! Max-Min= 250%
7335 23:19:14.299394 [DutyScan_Calibration_Flow] ====Done====
7336 23:19:14.299506
7337 23:19:14.302663 [DutyScan_Calibration_Flow] k_type=1
7338 23:19:14.319266
7339 23:19:14.319360 ==DQS 0 ==
7340 23:19:14.322614 Final DQS duty delay cell = 0
7341 23:19:14.325980 [0] MAX Duty = 5187%(X100), DQS PI = 24
7342 23:19:14.329294 [0] MIN Duty = 5062%(X100), DQS PI = 48
7343 23:19:14.332729 [0] AVG Duty = 5124%(X100)
7344 23:19:14.332808
7345 23:19:14.332871 ==DQS 1 ==
7346 23:19:14.335701 Final DQS duty delay cell = 0
7347 23:19:14.339171 [0] MAX Duty = 5093%(X100), DQS PI = 60
7348 23:19:14.342478 [0] MIN Duty = 4844%(X100), DQS PI = 24
7349 23:19:14.345597 [0] AVG Duty = 4968%(X100)
7350 23:19:14.345715
7351 23:19:14.348886 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7352 23:19:14.348981
7353 23:19:14.352511 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7354 23:19:14.355664 [DutyScan_Calibration_Flow] ====Done====
7355 23:19:14.355743
7356 23:19:14.358936 [DutyScan_Calibration_Flow] k_type=3
7357 23:19:14.376213
7358 23:19:14.376293 ==DQM 0 ==
7359 23:19:14.379802 Final DQM duty delay cell = 0
7360 23:19:14.383052 [0] MAX Duty = 5031%(X100), DQS PI = 26
7361 23:19:14.386119 [0] MIN Duty = 4813%(X100), DQS PI = 54
7362 23:19:14.389572 [0] AVG Duty = 4922%(X100)
7363 23:19:14.389681
7364 23:19:14.389774 ==DQM 1 ==
7365 23:19:14.393002 Final DQM duty delay cell = 0
7366 23:19:14.395983 [0] MAX Duty = 5093%(X100), DQS PI = 36
7367 23:19:14.399736 [0] MIN Duty = 4875%(X100), DQS PI = 24
7368 23:19:14.402746 [0] AVG Duty = 4984%(X100)
7369 23:19:14.402827
7370 23:19:14.406035 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7371 23:19:14.406116
7372 23:19:14.409276 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7373 23:19:14.412721 [DutyScan_Calibration_Flow] ====Done====
7374 23:19:14.412803
7375 23:19:14.415930 [DutyScan_Calibration_Flow] k_type=2
7376 23:19:14.433341
7377 23:19:14.433421 ==DQ 0 ==
7378 23:19:14.436716 Final DQ duty delay cell = 0
7379 23:19:14.440024 [0] MAX Duty = 5093%(X100), DQS PI = 20
7380 23:19:14.442965 [0] MIN Duty = 4938%(X100), DQS PI = 0
7381 23:19:14.443046 [0] AVG Duty = 5015%(X100)
7382 23:19:14.443110
7383 23:19:14.446617 ==DQ 1 ==
7384 23:19:14.449629 Final DQ duty delay cell = 0
7385 23:19:14.452890 [0] MAX Duty = 5125%(X100), DQS PI = 34
7386 23:19:14.456308 [0] MIN Duty = 4969%(X100), DQS PI = 24
7387 23:19:14.456390 [0] AVG Duty = 5047%(X100)
7388 23:19:14.456455
7389 23:19:14.459587 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7390 23:19:14.463012
7391 23:19:14.466298 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7392 23:19:14.469472 [DutyScan_Calibration_Flow] ====Done====
7393 23:19:14.473140 nWR fixed to 30
7394 23:19:14.473227 [ModeRegInit_LP4] CH0 RK0
7395 23:19:14.476373 [ModeRegInit_LP4] CH0 RK1
7396 23:19:14.479747 [ModeRegInit_LP4] CH1 RK0
7397 23:19:14.479854 [ModeRegInit_LP4] CH1 RK1
7398 23:19:14.482933 match AC timing 5
7399 23:19:14.486253 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7400 23:19:14.492919 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7401 23:19:14.496259 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7402 23:19:14.503050 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7403 23:19:14.506075 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7404 23:19:14.506201 [MiockJmeterHQA]
7405 23:19:14.506291
7406 23:19:14.509451 [DramcMiockJmeter] u1RxGatingPI = 0
7407 23:19:14.512890 0 : 4365, 4140
7408 23:19:14.512985 4 : 4257, 4029
7409 23:19:14.513082 8 : 4363, 4138
7410 23:19:14.516100 12 : 4363, 4137
7411 23:19:14.516233 16 : 4363, 4137
7412 23:19:14.519237 20 : 4252, 4027
7413 23:19:14.519313 24 : 4253, 4026
7414 23:19:14.522843 28 : 4252, 4027
7415 23:19:14.522990 32 : 4252, 4027
7416 23:19:14.525754 36 : 4255, 4029
7417 23:19:14.525871 40 : 4363, 4137
7418 23:19:14.525965 44 : 4252, 4027
7419 23:19:14.529482 48 : 4252, 4027
7420 23:19:14.529572 52 : 4253, 4026
7421 23:19:14.532485 56 : 4255, 4030
7422 23:19:14.532630 60 : 4253, 4027
7423 23:19:14.535769 64 : 4361, 4137
7424 23:19:14.535852 68 : 4361, 4137
7425 23:19:14.539158 72 : 4252, 4027
7426 23:19:14.539283 76 : 4250, 4026
7427 23:19:14.539376 80 : 4250, 4027
7428 23:19:14.542560 84 : 4250, 4027
7429 23:19:14.542697 88 : 4253, 4029
7430 23:19:14.545955 92 : 4360, 4138
7431 23:19:14.546064 96 : 4250, 4026
7432 23:19:14.549303 100 : 4250, 4027
7433 23:19:14.549384 104 : 4360, 3466
7434 23:19:14.552457 108 : 4250, 0
7435 23:19:14.552602 112 : 4250, 0
7436 23:19:14.552682 116 : 4250, 0
7437 23:19:14.555730 120 : 4360, 0
7438 23:19:14.555815 124 : 4361, 0
7439 23:19:14.559021 128 : 4363, 0
7440 23:19:14.559102 132 : 4250, 0
7441 23:19:14.559166 136 : 4360, 0
7442 23:19:14.562471 140 : 4250, 0
7443 23:19:14.562556 144 : 4250, 0
7444 23:19:14.562651 148 : 4250, 0
7445 23:19:14.565760 152 : 4249, 0
7446 23:19:14.565841 156 : 4250, 0
7447 23:19:14.568955 160 : 4250, 0
7448 23:19:14.569036 164 : 4249, 0
7449 23:19:14.569099 168 : 4253, 0
7450 23:19:14.572300 172 : 4254, 0
7451 23:19:14.572380 176 : 4250, 0
7452 23:19:14.575791 180 : 4363, 0
7453 23:19:14.575928 184 : 4361, 0
7454 23:19:14.576035 188 : 4360, 0
7455 23:19:14.579042 192 : 4363, 0
7456 23:19:14.579127 196 : 4250, 0
7457 23:19:14.582498 200 : 4250, 0
7458 23:19:14.582577 204 : 4250, 0
7459 23:19:14.582659 208 : 4253, 0
7460 23:19:14.585774 212 : 4250, 0
7461 23:19:14.585872 216 : 4250, 0
7462 23:19:14.585957 220 : 4253, 0
7463 23:19:14.588946 224 : 4250, 0
7464 23:19:14.589027 228 : 4361, 0
7465 23:19:14.592229 232 : 4250, 0
7466 23:19:14.592311 236 : 4250, 883
7467 23:19:14.595535 240 : 4250, 4027
7468 23:19:14.595616 244 : 4360, 4138
7469 23:19:14.595680 248 : 4249, 4027
7470 23:19:14.598899 252 : 4250, 4026
7471 23:19:14.599003 256 : 4363, 4140
7472 23:19:14.602334 260 : 4250, 4027
7473 23:19:14.602415 264 : 4252, 4027
7474 23:19:14.605765 268 : 4250, 4026
7475 23:19:14.605912 272 : 4253, 4029
7476 23:19:14.609181 276 : 4250, 4027
7477 23:19:14.609265 280 : 4250, 4027
7478 23:19:14.612086 284 : 4360, 4137
7479 23:19:14.612170 288 : 4250, 4026
7480 23:19:14.615474 292 : 4250, 4027
7481 23:19:14.615560 296 : 4361, 4138
7482 23:19:14.618747 300 : 4250, 4027
7483 23:19:14.618835 304 : 4250, 4026
7484 23:19:14.618923 308 : 4363, 4140
7485 23:19:14.622187 312 : 4250, 4027
7486 23:19:14.622321 316 : 4250, 4027
7487 23:19:14.625591 320 : 4250, 4026
7488 23:19:14.625675 324 : 4253, 4029
7489 23:19:14.628664 328 : 4250, 4027
7490 23:19:14.628749 332 : 4250, 4027
7491 23:19:14.631960 336 : 4360, 4137
7492 23:19:14.632041 340 : 4250, 4026
7493 23:19:14.635235 344 : 4250, 4027
7494 23:19:14.635329 348 : 4361, 4138
7495 23:19:14.638864 352 : 4250, 4012
7496 23:19:14.638972 356 : 4250, 2755
7497 23:19:14.639098 360 : 4363, 1
7498 23:19:14.641977
7499 23:19:14.642070 MIOCK jitter meter ch=0
7500 23:19:14.642162
7501 23:19:14.645349 1T = (360-108) = 252 dly cells
7502 23:19:14.652016 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7503 23:19:14.652099 ==
7504 23:19:14.655280 Dram Type= 6, Freq= 0, CH_0, rank 0
7505 23:19:14.658493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7506 23:19:14.658575 ==
7507 23:19:14.665090 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7508 23:19:14.668450 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7509 23:19:14.671768 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7510 23:19:14.678302 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7511 23:19:14.687877 [CA 0] Center 44 (14~75) winsize 62
7512 23:19:14.691145 [CA 1] Center 43 (13~74) winsize 62
7513 23:19:14.694667 [CA 2] Center 40 (11~69) winsize 59
7514 23:19:14.697881 [CA 3] Center 39 (10~68) winsize 59
7515 23:19:14.701144 [CA 4] Center 37 (8~67) winsize 60
7516 23:19:14.704491 [CA 5] Center 37 (7~67) winsize 61
7517 23:19:14.704574
7518 23:19:14.707710 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7519 23:19:14.707793
7520 23:19:14.711111 [CATrainingPosCal] consider 1 rank data
7521 23:19:14.714372 u2DelayCellTimex100 = 258/100 ps
7522 23:19:14.720920 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7523 23:19:14.724348 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7524 23:19:14.727548 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7525 23:19:14.730909 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7526 23:19:14.734087 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7527 23:19:14.737576 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7528 23:19:14.737669
7529 23:19:14.741016 CA PerBit enable=1, Macro0, CA PI delay=37
7530 23:19:14.741135
7531 23:19:14.744162 [CBTSetCACLKResult] CA Dly = 37
7532 23:19:14.747516 CS Dly: 11 (0~42)
7533 23:19:14.750977 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7534 23:19:14.754365 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7535 23:19:14.754451 ==
7536 23:19:14.757662 Dram Type= 6, Freq= 0, CH_0, rank 1
7537 23:19:14.764028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 23:19:14.764115 ==
7539 23:19:14.767362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 23:19:14.773997 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 23:19:14.777373 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 23:19:14.783888 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 23:19:14.792054 [CA 0] Center 44 (14~75) winsize 62
7544 23:19:14.795016 [CA 1] Center 43 (13~74) winsize 62
7545 23:19:14.798384 [CA 2] Center 39 (10~69) winsize 60
7546 23:19:14.801687 [CA 3] Center 39 (10~69) winsize 60
7547 23:19:14.804919 [CA 4] Center 37 (8~67) winsize 60
7548 23:19:14.808231 [CA 5] Center 37 (7~67) winsize 61
7549 23:19:14.808313
7550 23:19:14.811537 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 23:19:14.811620
7552 23:19:14.818018 [CATrainingPosCal] consider 2 rank data
7553 23:19:14.818112 u2DelayCellTimex100 = 258/100 ps
7554 23:19:14.825089 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7555 23:19:14.828390 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7556 23:19:14.831488 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7557 23:19:14.834820 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7558 23:19:14.838111 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7559 23:19:14.841384 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7560 23:19:14.841467
7561 23:19:14.844897 CA PerBit enable=1, Macro0, CA PI delay=37
7562 23:19:14.845005
7563 23:19:14.847982 [CBTSetCACLKResult] CA Dly = 37
7564 23:19:14.851174 CS Dly: 11 (0~43)
7565 23:19:14.854884 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 23:19:14.858115 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 23:19:14.858202
7568 23:19:14.861189 ----->DramcWriteLeveling(PI) begin...
7569 23:19:14.861275 ==
7570 23:19:14.864636 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 23:19:14.871291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 23:19:14.871378 ==
7573 23:19:14.874696 Write leveling (Byte 0): 34 => 34
7574 23:19:14.877619 Write leveling (Byte 1): 28 => 28
7575 23:19:14.881093 DramcWriteLeveling(PI) end<-----
7576 23:19:14.881178
7577 23:19:14.881264 ==
7578 23:19:14.884446 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 23:19:14.887674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 23:19:14.887787 ==
7581 23:19:14.890870 [Gating] SW mode calibration
7582 23:19:14.897510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7583 23:19:14.900912 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7584 23:19:14.907661 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 23:19:14.911019 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 23:19:14.914429 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 23:19:14.920808 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 23:19:14.924068 1 4 16 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
7589 23:19:14.927277 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7590 23:19:14.934115 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
7591 23:19:14.937211 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 23:19:14.943901 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 23:19:14.946883 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 23:19:14.950178 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 23:19:14.957020 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7596 23:19:14.960063 1 5 16 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
7597 23:19:14.963350 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
7598 23:19:14.969894 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7599 23:19:14.973127 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7600 23:19:14.976508 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 23:19:14.983258 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 23:19:14.986746 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 23:19:14.990029 1 6 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7604 23:19:14.993176 1 6 16 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7605 23:19:14.999886 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7606 23:19:15.002891 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7607 23:19:15.009539 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 23:19:15.012825 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 23:19:15.016502 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 23:19:15.019688 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 23:19:15.026195 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 23:19:15.029447 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7613 23:19:15.033131 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7614 23:19:15.039472 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 23:19:15.042834 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 23:19:15.046162 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 23:19:15.052500 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 23:19:15.055826 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 23:19:15.059144 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 23:19:15.065734 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 23:19:15.069152 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 23:19:15.072313 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 23:19:15.079060 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 23:19:15.082400 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 23:19:15.085868 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 23:19:15.092290 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 23:19:15.095838 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7628 23:19:15.099111 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7629 23:19:15.105407 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7630 23:19:15.108931 Total UI for P1: 0, mck2ui 16
7631 23:19:15.112206 best dqsien dly found for B0: ( 1, 9, 14)
7632 23:19:15.115423 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7633 23:19:15.118682 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 23:19:15.122101 Total UI for P1: 0, mck2ui 16
7635 23:19:15.125565 best dqsien dly found for B1: ( 1, 9, 24)
7636 23:19:15.128788 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7637 23:19:15.132061 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7638 23:19:15.132141
7639 23:19:15.138797 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7640 23:19:15.142108 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7641 23:19:15.145234 [Gating] SW calibration Done
7642 23:19:15.145314 ==
7643 23:19:15.148558 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 23:19:15.151855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 23:19:15.151936 ==
7646 23:19:15.152022 RX Vref Scan: 0
7647 23:19:15.155207
7648 23:19:15.155292 RX Vref 0 -> 0, step: 1
7649 23:19:15.155379
7650 23:19:15.158498 RX Delay 0 -> 252, step: 8
7651 23:19:15.161827 iDelay=192, Bit 0, Center 131 (72 ~ 191) 120
7652 23:19:15.165102 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7653 23:19:15.171627 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7654 23:19:15.175069 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7655 23:19:15.178528 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7656 23:19:15.181525 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7657 23:19:15.184910 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7658 23:19:15.191605 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7659 23:19:15.194951 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7660 23:19:15.198257 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7661 23:19:15.201688 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7662 23:19:15.204766 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7663 23:19:15.211446 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7664 23:19:15.214706 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7665 23:19:15.217987 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7666 23:19:15.221360 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7667 23:19:15.221445 ==
7668 23:19:15.224841 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 23:19:15.231530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 23:19:15.231643 ==
7671 23:19:15.231742 DQS Delay:
7672 23:19:15.234561 DQS0 = 0, DQS1 = 0
7673 23:19:15.234643 DQM Delay:
7674 23:19:15.237858 DQM0 = 127, DQM1 = 123
7675 23:19:15.237940 DQ Delay:
7676 23:19:15.241319 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =119
7677 23:19:15.244671 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7678 23:19:15.247865 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7679 23:19:15.251532 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =135
7680 23:19:15.251614
7681 23:19:15.251679
7682 23:19:15.251738 ==
7683 23:19:15.254637 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 23:19:15.257940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 23:19:15.261439 ==
7686 23:19:15.261531
7687 23:19:15.261597
7688 23:19:15.261657 TX Vref Scan disable
7689 23:19:15.264685 == TX Byte 0 ==
7690 23:19:15.267947 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7691 23:19:15.271318 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7692 23:19:15.274659 == TX Byte 1 ==
7693 23:19:15.278047 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7694 23:19:15.281353 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7695 23:19:15.284535 ==
7696 23:19:15.287957 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 23:19:15.290866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 23:19:15.290973 ==
7699 23:19:15.304075
7700 23:19:15.307159 TX Vref early break, caculate TX vref
7701 23:19:15.310569 TX Vref=16, minBit 8, minWin=21, winSum=354
7702 23:19:15.313963 TX Vref=18, minBit 7, minWin=22, winSum=366
7703 23:19:15.316885 TX Vref=20, minBit 11, minWin=22, winSum=375
7704 23:19:15.320227 TX Vref=22, minBit 0, minWin=23, winSum=386
7705 23:19:15.323827 TX Vref=24, minBit 7, minWin=23, winSum=397
7706 23:19:15.330403 TX Vref=26, minBit 1, minWin=24, winSum=401
7707 23:19:15.333617 TX Vref=28, minBit 8, minWin=23, winSum=400
7708 23:19:15.336621 TX Vref=30, minBit 3, minWin=24, winSum=398
7709 23:19:15.340207 TX Vref=32, minBit 1, minWin=23, winSum=384
7710 23:19:15.343494 TX Vref=34, minBit 9, minWin=22, winSum=379
7711 23:19:15.349957 [TxChooseVref] Worse bit 1, Min win 24, Win sum 401, Final Vref 26
7712 23:19:15.350040
7713 23:19:15.353317 Final TX Range 0 Vref 26
7714 23:19:15.353399
7715 23:19:15.353463 ==
7716 23:19:15.356686 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 23:19:15.360011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 23:19:15.360089 ==
7719 23:19:15.360153
7720 23:19:15.360213
7721 23:19:15.363331 TX Vref Scan disable
7722 23:19:15.370114 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7723 23:19:15.370195 == TX Byte 0 ==
7724 23:19:15.373067 u2DelayCellOfst[0]=15 cells (4 PI)
7725 23:19:15.376390 u2DelayCellOfst[1]=18 cells (5 PI)
7726 23:19:15.379714 u2DelayCellOfst[2]=15 cells (4 PI)
7727 23:19:15.382993 u2DelayCellOfst[3]=15 cells (4 PI)
7728 23:19:15.386393 u2DelayCellOfst[4]=7 cells (2 PI)
7729 23:19:15.389724 u2DelayCellOfst[5]=0 cells (0 PI)
7730 23:19:15.393077 u2DelayCellOfst[6]=22 cells (6 PI)
7731 23:19:15.396285 u2DelayCellOfst[7]=18 cells (5 PI)
7732 23:19:15.399429 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7733 23:19:15.402723 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7734 23:19:15.406367 == TX Byte 1 ==
7735 23:19:15.409384 u2DelayCellOfst[8]=0 cells (0 PI)
7736 23:19:15.412945 u2DelayCellOfst[9]=3 cells (1 PI)
7737 23:19:15.416313 u2DelayCellOfst[10]=7 cells (2 PI)
7738 23:19:15.416394 u2DelayCellOfst[11]=3 cells (1 PI)
7739 23:19:15.419662 u2DelayCellOfst[12]=11 cells (3 PI)
7740 23:19:15.422614 u2DelayCellOfst[13]=11 cells (3 PI)
7741 23:19:15.426029 u2DelayCellOfst[14]=15 cells (4 PI)
7742 23:19:15.429394 u2DelayCellOfst[15]=11 cells (3 PI)
7743 23:19:15.436068 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7744 23:19:15.439576 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7745 23:19:15.439658 DramC Write-DBI on
7746 23:19:15.439722 ==
7747 23:19:15.442701 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 23:19:15.449875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 23:19:15.449974 ==
7750 23:19:15.450041
7751 23:19:15.450101
7752 23:19:15.450158 TX Vref Scan disable
7753 23:19:15.453552 == TX Byte 0 ==
7754 23:19:15.456860 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7755 23:19:15.460089 == TX Byte 1 ==
7756 23:19:15.463147 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7757 23:19:15.466739 DramC Write-DBI off
7758 23:19:15.466845
7759 23:19:15.466938 [DATLAT]
7760 23:19:15.467028 Freq=1600, CH0 RK0
7761 23:19:15.467115
7762 23:19:15.469971 DATLAT Default: 0xf
7763 23:19:15.470057 0, 0xFFFF, sum = 0
7764 23:19:15.473174 1, 0xFFFF, sum = 0
7765 23:19:15.476632 2, 0xFFFF, sum = 0
7766 23:19:15.476772 3, 0xFFFF, sum = 0
7767 23:19:15.479849 4, 0xFFFF, sum = 0
7768 23:19:15.479932 5, 0xFFFF, sum = 0
7769 23:19:15.483228 6, 0xFFFF, sum = 0
7770 23:19:15.483312 7, 0xFFFF, sum = 0
7771 23:19:15.486686 8, 0xFFFF, sum = 0
7772 23:19:15.486770 9, 0xFFFF, sum = 0
7773 23:19:15.489646 10, 0xFFFF, sum = 0
7774 23:19:15.489760 11, 0xFFFF, sum = 0
7775 23:19:15.492999 12, 0xFFFF, sum = 0
7776 23:19:15.493078 13, 0xCFFF, sum = 0
7777 23:19:15.496366 14, 0x0, sum = 1
7778 23:19:15.496476 15, 0x0, sum = 2
7779 23:19:15.499615 16, 0x0, sum = 3
7780 23:19:15.499691 17, 0x0, sum = 4
7781 23:19:15.503012 best_step = 15
7782 23:19:15.503115
7783 23:19:15.503220 ==
7784 23:19:15.506667 Dram Type= 6, Freq= 0, CH_0, rank 0
7785 23:19:15.509793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7786 23:19:15.509873 ==
7787 23:19:15.513160 RX Vref Scan: 1
7788 23:19:15.513241
7789 23:19:15.513331 Set Vref Range= 24 -> 127
7790 23:19:15.513430
7791 23:19:15.516441 RX Vref 24 -> 127, step: 1
7792 23:19:15.516528
7793 23:19:15.519800 RX Delay 11 -> 252, step: 4
7794 23:19:15.519884
7795 23:19:15.523177 Set Vref, RX VrefLevel [Byte0]: 24
7796 23:19:15.526116 [Byte1]: 24
7797 23:19:15.526190
7798 23:19:15.529527 Set Vref, RX VrefLevel [Byte0]: 25
7799 23:19:15.532947 [Byte1]: 25
7800 23:19:15.536533
7801 23:19:15.536614 Set Vref, RX VrefLevel [Byte0]: 26
7802 23:19:15.539418 [Byte1]: 26
7803 23:19:15.543921
7804 23:19:15.544002 Set Vref, RX VrefLevel [Byte0]: 27
7805 23:19:15.547176 [Byte1]: 27
7806 23:19:15.551304
7807 23:19:15.551410 Set Vref, RX VrefLevel [Byte0]: 28
7808 23:19:15.554920 [Byte1]: 28
7809 23:19:15.559053
7810 23:19:15.559133 Set Vref, RX VrefLevel [Byte0]: 29
7811 23:19:15.562226 [Byte1]: 29
7812 23:19:15.566752
7813 23:19:15.566854 Set Vref, RX VrefLevel [Byte0]: 30
7814 23:19:15.570113 [Byte1]: 30
7815 23:19:15.574356
7816 23:19:15.574444 Set Vref, RX VrefLevel [Byte0]: 31
7817 23:19:15.577461 [Byte1]: 31
7818 23:19:15.582028
7819 23:19:15.582119 Set Vref, RX VrefLevel [Byte0]: 32
7820 23:19:15.585120 [Byte1]: 32
7821 23:19:15.589726
7822 23:19:15.589809 Set Vref, RX VrefLevel [Byte0]: 33
7823 23:19:15.592780 [Byte1]: 33
7824 23:19:15.597303
7825 23:19:15.597389 Set Vref, RX VrefLevel [Byte0]: 34
7826 23:19:15.600573 [Byte1]: 34
7827 23:19:15.604887
7828 23:19:15.604971 Set Vref, RX VrefLevel [Byte0]: 35
7829 23:19:15.608117 [Byte1]: 35
7830 23:19:15.612308
7831 23:19:15.612380 Set Vref, RX VrefLevel [Byte0]: 36
7832 23:19:15.615642 [Byte1]: 36
7833 23:19:15.620125
7834 23:19:15.620202 Set Vref, RX VrefLevel [Byte0]: 37
7835 23:19:15.623288 [Byte1]: 37
7836 23:19:15.627635
7837 23:19:15.627717 Set Vref, RX VrefLevel [Byte0]: 38
7838 23:19:15.631070 [Byte1]: 38
7839 23:19:15.635336
7840 23:19:15.635416 Set Vref, RX VrefLevel [Byte0]: 39
7841 23:19:15.638696 [Byte1]: 39
7842 23:19:15.642866
7843 23:19:15.642937 Set Vref, RX VrefLevel [Byte0]: 40
7844 23:19:15.646101 [Byte1]: 40
7845 23:19:15.650592
7846 23:19:15.650674 Set Vref, RX VrefLevel [Byte0]: 41
7847 23:19:15.653795 [Byte1]: 41
7848 23:19:15.658199
7849 23:19:15.658281 Set Vref, RX VrefLevel [Byte0]: 42
7850 23:19:15.661287 [Byte1]: 42
7851 23:19:15.665528
7852 23:19:15.665610 Set Vref, RX VrefLevel [Byte0]: 43
7853 23:19:15.668785 [Byte1]: 43
7854 23:19:15.673402
7855 23:19:15.673492 Set Vref, RX VrefLevel [Byte0]: 44
7856 23:19:15.676697 [Byte1]: 44
7857 23:19:15.680935
7858 23:19:15.681047 Set Vref, RX VrefLevel [Byte0]: 45
7859 23:19:15.684017 [Byte1]: 45
7860 23:19:15.688436
7861 23:19:15.688520 Set Vref, RX VrefLevel [Byte0]: 46
7862 23:19:15.691563 [Byte1]: 46
7863 23:19:15.696023
7864 23:19:15.696105 Set Vref, RX VrefLevel [Byte0]: 47
7865 23:19:15.699263 [Byte1]: 47
7866 23:19:15.703759
7867 23:19:15.703839 Set Vref, RX VrefLevel [Byte0]: 48
7868 23:19:15.706879 [Byte1]: 48
7869 23:19:15.711445
7870 23:19:15.711522 Set Vref, RX VrefLevel [Byte0]: 49
7871 23:19:15.714755 [Byte1]: 49
7872 23:19:15.719047
7873 23:19:15.719119 Set Vref, RX VrefLevel [Byte0]: 50
7874 23:19:15.722308 [Byte1]: 50
7875 23:19:15.726657
7876 23:19:15.726754 Set Vref, RX VrefLevel [Byte0]: 51
7877 23:19:15.729970 [Byte1]: 51
7878 23:19:15.734199
7879 23:19:15.734284 Set Vref, RX VrefLevel [Byte0]: 52
7880 23:19:15.737366 [Byte1]: 52
7881 23:19:15.741590
7882 23:19:15.741687 Set Vref, RX VrefLevel [Byte0]: 53
7883 23:19:15.744883 [Byte1]: 53
7884 23:19:15.749242
7885 23:19:15.749338 Set Vref, RX VrefLevel [Byte0]: 54
7886 23:19:15.752487 [Byte1]: 54
7887 23:19:15.756898
7888 23:19:15.756989 Set Vref, RX VrefLevel [Byte0]: 55
7889 23:19:15.760392 [Byte1]: 55
7890 23:19:15.764471
7891 23:19:15.764545 Set Vref, RX VrefLevel [Byte0]: 56
7892 23:19:15.767934 [Byte1]: 56
7893 23:19:15.772089
7894 23:19:15.772165 Set Vref, RX VrefLevel [Byte0]: 57
7895 23:19:15.775412 [Byte1]: 57
7896 23:19:15.779600
7897 23:19:15.779676 Set Vref, RX VrefLevel [Byte0]: 58
7898 23:19:15.782987 [Byte1]: 58
7899 23:19:15.787596
7900 23:19:15.787706 Set Vref, RX VrefLevel [Byte0]: 59
7901 23:19:15.790856 [Byte1]: 59
7902 23:19:15.794890
7903 23:19:15.794981 Set Vref, RX VrefLevel [Byte0]: 60
7904 23:19:15.798285 [Byte1]: 60
7905 23:19:15.802603
7906 23:19:15.802685 Set Vref, RX VrefLevel [Byte0]: 61
7907 23:19:15.806007 [Byte1]: 61
7908 23:19:15.810170
7909 23:19:15.810252 Set Vref, RX VrefLevel [Byte0]: 62
7910 23:19:15.813521 [Byte1]: 62
7911 23:19:15.817961
7912 23:19:15.818047 Set Vref, RX VrefLevel [Byte0]: 63
7913 23:19:15.821385 [Byte1]: 63
7914 23:19:15.825618
7915 23:19:15.825711 Set Vref, RX VrefLevel [Byte0]: 64
7916 23:19:15.828825 [Byte1]: 64
7917 23:19:15.833343
7918 23:19:15.833447 Set Vref, RX VrefLevel [Byte0]: 65
7919 23:19:15.836695 [Byte1]: 65
7920 23:19:15.840566
7921 23:19:15.840647 Set Vref, RX VrefLevel [Byte0]: 66
7922 23:19:15.844049 [Byte1]: 66
7923 23:19:15.848391
7924 23:19:15.848507 Set Vref, RX VrefLevel [Byte0]: 67
7925 23:19:15.851754 [Byte1]: 67
7926 23:19:15.855929
7927 23:19:15.856026 Set Vref, RX VrefLevel [Byte0]: 68
7928 23:19:15.859278 [Byte1]: 68
7929 23:19:15.863365
7930 23:19:15.863470 Set Vref, RX VrefLevel [Byte0]: 69
7931 23:19:15.866859 [Byte1]: 69
7932 23:19:15.871350
7933 23:19:15.871460 Set Vref, RX VrefLevel [Byte0]: 70
7934 23:19:15.874342 [Byte1]: 70
7935 23:19:15.878853
7936 23:19:15.878949 Set Vref, RX VrefLevel [Byte0]: 71
7937 23:19:15.882306 [Byte1]: 71
7938 23:19:15.886408
7939 23:19:15.886494 Set Vref, RX VrefLevel [Byte0]: 72
7940 23:19:15.889814 [Byte1]: 72
7941 23:19:15.894026
7942 23:19:15.894110 Set Vref, RX VrefLevel [Byte0]: 73
7943 23:19:15.897190 [Byte1]: 73
7944 23:19:15.901523
7945 23:19:15.901598 Set Vref, RX VrefLevel [Byte0]: 74
7946 23:19:15.905016 [Byte1]: 74
7947 23:19:15.909033
7948 23:19:15.909131 Final RX Vref Byte 0 = 63 to rank0
7949 23:19:15.912403 Final RX Vref Byte 1 = 57 to rank0
7950 23:19:15.915641 Final RX Vref Byte 0 = 63 to rank1
7951 23:19:15.919059 Final RX Vref Byte 1 = 57 to rank1==
7952 23:19:15.922496 Dram Type= 6, Freq= 0, CH_0, rank 0
7953 23:19:15.928946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 23:19:15.929025 ==
7955 23:19:15.929088 DQS Delay:
7956 23:19:15.929149 DQS0 = 0, DQS1 = 0
7957 23:19:15.932487 DQM Delay:
7958 23:19:15.932555 DQM0 = 126, DQM1 = 119
7959 23:19:15.935684 DQ Delay:
7960 23:19:15.939011 DQ0 =126, DQ1 =126, DQ2 =124, DQ3 =122
7961 23:19:15.942405 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7962 23:19:15.945551 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7963 23:19:15.948841 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7964 23:19:15.948923
7965 23:19:15.948987
7966 23:19:15.949047
7967 23:19:15.952386 [DramC_TX_OE_Calibration] TA2
7968 23:19:15.955595 Original DQ_B0 (3 6) =30, OEN = 27
7969 23:19:15.958832 Original DQ_B1 (3 6) =30, OEN = 27
7970 23:19:15.961984 24, 0x0, End_B0=24 End_B1=24
7971 23:19:15.962094 25, 0x0, End_B0=25 End_B1=25
7972 23:19:15.965457 26, 0x0, End_B0=26 End_B1=26
7973 23:19:15.968924 27, 0x0, End_B0=27 End_B1=27
7974 23:19:15.972138 28, 0x0, End_B0=28 End_B1=28
7975 23:19:15.975348 29, 0x0, End_B0=29 End_B1=29
7976 23:19:15.975425 30, 0x0, End_B0=30 End_B1=30
7977 23:19:15.978621 31, 0x4141, End_B0=30 End_B1=30
7978 23:19:15.982120 Byte0 end_step=30 best_step=27
7979 23:19:15.985361 Byte1 end_step=30 best_step=27
7980 23:19:15.988458 Byte0 TX OE(2T, 0.5T) = (3, 3)
7981 23:19:15.991955 Byte1 TX OE(2T, 0.5T) = (3, 3)
7982 23:19:15.992072
7983 23:19:15.992172
7984 23:19:15.998677 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
7985 23:19:16.001927 CH0 RK0: MR19=303, MR18=1212
7986 23:19:16.008505 CH0_RK0: MR19=0x303, MR18=0x1212, DQSOSC=400, MR23=63, INC=23, DEC=15
7987 23:19:16.008589
7988 23:19:16.011722 ----->DramcWriteLeveling(PI) begin...
7989 23:19:16.011810 ==
7990 23:19:16.014990 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 23:19:16.018720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 23:19:16.018800 ==
7993 23:19:16.021681 Write leveling (Byte 0): 34 => 34
7994 23:19:16.025002 Write leveling (Byte 1): 27 => 27
7995 23:19:16.028446 DramcWriteLeveling(PI) end<-----
7996 23:19:16.028521
7997 23:19:16.028587 ==
7998 23:19:16.031862 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 23:19:16.035109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 23:19:16.035187 ==
8001 23:19:16.038154 [Gating] SW mode calibration
8002 23:19:16.044845 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8003 23:19:16.051539 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8004 23:19:16.055039 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 23:19:16.061486 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 23:19:16.064778 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 23:19:16.068061 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8008 23:19:16.074668 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8009 23:19:16.077900 1 4 20 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8010 23:19:16.081282 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 23:19:16.087875 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 23:19:16.091355 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 23:19:16.094658 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8014 23:19:16.101158 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8015 23:19:16.104493 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
8016 23:19:16.107661 1 5 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8017 23:19:16.114456 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8018 23:19:16.117673 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 23:19:16.120915 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 23:19:16.127739 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 23:19:16.130980 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 23:19:16.134393 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8023 23:19:16.137718 1 6 12 | B1->B0 | 2424 4242 | 0 0 | (0 0) (0 0)
8024 23:19:16.144254 1 6 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8025 23:19:16.147614 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 23:19:16.150901 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 23:19:16.157161 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 23:19:16.160457 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 23:19:16.164132 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 23:19:16.170718 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8031 23:19:16.173973 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8032 23:19:16.177400 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8033 23:19:16.183774 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8034 23:19:16.187074 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 23:19:16.190262 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 23:19:16.196990 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 23:19:16.200459 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 23:19:16.203753 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 23:19:16.210415 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 23:19:16.213593 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 23:19:16.216889 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 23:19:16.223656 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 23:19:16.226835 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 23:19:16.230159 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 23:19:16.236792 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 23:19:16.240078 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8047 23:19:16.243572 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8048 23:19:16.246945 Total UI for P1: 0, mck2ui 16
8049 23:19:16.250053 best dqsien dly found for B0: ( 1, 9, 6)
8050 23:19:16.256518 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8051 23:19:16.259772 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8052 23:19:16.263114 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 23:19:16.266453 Total UI for P1: 0, mck2ui 16
8054 23:19:16.270180 best dqsien dly found for B1: ( 1, 9, 18)
8055 23:19:16.273309 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8056 23:19:16.276545 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8057 23:19:16.276630
8058 23:19:16.283123 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8059 23:19:16.286503 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8060 23:19:16.289888 [Gating] SW calibration Done
8061 23:19:16.289986 ==
8062 23:19:16.293093 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 23:19:16.296420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 23:19:16.296524 ==
8065 23:19:16.296614 RX Vref Scan: 0
8066 23:19:16.296719
8067 23:19:16.299675 RX Vref 0 -> 0, step: 1
8068 23:19:16.299790
8069 23:19:16.303259 RX Delay 0 -> 252, step: 8
8070 23:19:16.306661 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8071 23:19:16.309642 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8072 23:19:16.312945 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8073 23:19:16.319460 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8074 23:19:16.322822 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8075 23:19:16.326079 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8076 23:19:16.329512 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8077 23:19:16.332889 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8078 23:19:16.339422 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8079 23:19:16.342559 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8080 23:19:16.345999 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8081 23:19:16.349407 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8082 23:19:16.355727 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8083 23:19:16.359127 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8084 23:19:16.362523 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8085 23:19:16.365668 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8086 23:19:16.365776 ==
8087 23:19:16.369248 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 23:19:16.375766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 23:19:16.375875 ==
8090 23:19:16.375972 DQS Delay:
8091 23:19:16.376064 DQS0 = 0, DQS1 = 0
8092 23:19:16.379187 DQM Delay:
8093 23:19:16.379262 DQM0 = 127, DQM1 = 121
8094 23:19:16.382474 DQ Delay:
8095 23:19:16.385946 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8096 23:19:16.389224 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8097 23:19:16.392224 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8098 23:19:16.395541 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8099 23:19:16.395641
8100 23:19:16.395730
8101 23:19:16.395804 ==
8102 23:19:16.398947 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 23:19:16.402574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 23:19:16.405889 ==
8105 23:19:16.406001
8106 23:19:16.406081
8107 23:19:16.406177 TX Vref Scan disable
8108 23:19:16.409018 == TX Byte 0 ==
8109 23:19:16.412414 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8110 23:19:16.415687 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8111 23:19:16.418988 == TX Byte 1 ==
8112 23:19:16.422169 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8113 23:19:16.425850 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8114 23:19:16.425926 ==
8115 23:19:16.428836 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 23:19:16.435457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 23:19:16.435573 ==
8118 23:19:16.448186
8119 23:19:16.451599 TX Vref early break, caculate TX vref
8120 23:19:16.454577 TX Vref=16, minBit 0, minWin=22, winSum=363
8121 23:19:16.458165 TX Vref=18, minBit 8, minWin=22, winSum=371
8122 23:19:16.461396 TX Vref=20, minBit 8, minWin=22, winSum=384
8123 23:19:16.464846 TX Vref=22, minBit 8, minWin=23, winSum=390
8124 23:19:16.467952 TX Vref=24, minBit 0, minWin=24, winSum=396
8125 23:19:16.474834 TX Vref=26, minBit 8, minWin=24, winSum=408
8126 23:19:16.478151 TX Vref=28, minBit 8, minWin=24, winSum=414
8127 23:19:16.481256 TX Vref=30, minBit 8, minWin=24, winSum=404
8128 23:19:16.484660 TX Vref=32, minBit 8, minWin=22, winSum=394
8129 23:19:16.487670 TX Vref=34, minBit 8, minWin=23, winSum=388
8130 23:19:16.494551 [TxChooseVref] Worse bit 8, Min win 24, Win sum 414, Final Vref 28
8131 23:19:16.494638
8132 23:19:16.497526 Final TX Range 0 Vref 28
8133 23:19:16.497636
8134 23:19:16.497731 ==
8135 23:19:16.500917 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 23:19:16.504452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 23:19:16.504560 ==
8138 23:19:16.504653
8139 23:19:16.504740
8140 23:19:16.507464 TX Vref Scan disable
8141 23:19:16.514092 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8142 23:19:16.514175 == TX Byte 0 ==
8143 23:19:16.517748 u2DelayCellOfst[0]=11 cells (3 PI)
8144 23:19:16.520655 u2DelayCellOfst[1]=18 cells (5 PI)
8145 23:19:16.524408 u2DelayCellOfst[2]=11 cells (3 PI)
8146 23:19:16.527559 u2DelayCellOfst[3]=11 cells (3 PI)
8147 23:19:16.530878 u2DelayCellOfst[4]=3 cells (1 PI)
8148 23:19:16.534235 u2DelayCellOfst[5]=0 cells (0 PI)
8149 23:19:16.537484 u2DelayCellOfst[6]=18 cells (5 PI)
8150 23:19:16.540712 u2DelayCellOfst[7]=18 cells (5 PI)
8151 23:19:16.544054 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8152 23:19:16.547436 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8153 23:19:16.550854 == TX Byte 1 ==
8154 23:19:16.554117 u2DelayCellOfst[8]=0 cells (0 PI)
8155 23:19:16.554198 u2DelayCellOfst[9]=0 cells (0 PI)
8156 23:19:16.557453 u2DelayCellOfst[10]=7 cells (2 PI)
8157 23:19:16.560436 u2DelayCellOfst[11]=7 cells (2 PI)
8158 23:19:16.563748 u2DelayCellOfst[12]=11 cells (3 PI)
8159 23:19:16.567146 u2DelayCellOfst[13]=15 cells (4 PI)
8160 23:19:16.570469 u2DelayCellOfst[14]=15 cells (4 PI)
8161 23:19:16.574046 u2DelayCellOfst[15]=11 cells (3 PI)
8162 23:19:16.577176 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8163 23:19:16.583794 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8164 23:19:16.583883 DramC Write-DBI on
8165 23:19:16.583948 ==
8166 23:19:16.586808 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 23:19:16.593403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 23:19:16.593518 ==
8169 23:19:16.593612
8170 23:19:16.593700
8171 23:19:16.593790 TX Vref Scan disable
8172 23:19:16.597539 == TX Byte 0 ==
8173 23:19:16.601222 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8174 23:19:16.604219 == TX Byte 1 ==
8175 23:19:16.607657 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8176 23:19:16.610963 DramC Write-DBI off
8177 23:19:16.611075
8178 23:19:16.611188 [DATLAT]
8179 23:19:16.611287 Freq=1600, CH0 RK1
8180 23:19:16.611391
8181 23:19:16.614460 DATLAT Default: 0xf
8182 23:19:16.614550 0, 0xFFFF, sum = 0
8183 23:19:16.617577 1, 0xFFFF, sum = 0
8184 23:19:16.620820 2, 0xFFFF, sum = 0
8185 23:19:16.620900 3, 0xFFFF, sum = 0
8186 23:19:16.624423 4, 0xFFFF, sum = 0
8187 23:19:16.624505 5, 0xFFFF, sum = 0
8188 23:19:16.627716 6, 0xFFFF, sum = 0
8189 23:19:16.627800 7, 0xFFFF, sum = 0
8190 23:19:16.630761 8, 0xFFFF, sum = 0
8191 23:19:16.630840 9, 0xFFFF, sum = 0
8192 23:19:16.634473 10, 0xFFFF, sum = 0
8193 23:19:16.634550 11, 0xFFFF, sum = 0
8194 23:19:16.637391 12, 0xFFFF, sum = 0
8195 23:19:16.637495 13, 0xCFFF, sum = 0
8196 23:19:16.640829 14, 0x0, sum = 1
8197 23:19:16.640933 15, 0x0, sum = 2
8198 23:19:16.644215 16, 0x0, sum = 3
8199 23:19:16.644298 17, 0x0, sum = 4
8200 23:19:16.647544 best_step = 15
8201 23:19:16.647624
8202 23:19:16.647688 ==
8203 23:19:16.650765 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 23:19:16.654425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 23:19:16.654507 ==
8206 23:19:16.654571 RX Vref Scan: 0
8207 23:19:16.657412
8208 23:19:16.657528 RX Vref 0 -> 0, step: 1
8209 23:19:16.657628
8210 23:19:16.660737 RX Delay 3 -> 252, step: 4
8211 23:19:16.664421 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8212 23:19:16.670949 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8213 23:19:16.674311 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8214 23:19:16.677613 iDelay=191, Bit 3, Center 120 (63 ~ 178) 116
8215 23:19:16.680671 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8216 23:19:16.684062 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8217 23:19:16.690774 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8218 23:19:16.693994 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8219 23:19:16.697214 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8220 23:19:16.700536 iDelay=191, Bit 9, Center 106 (51 ~ 162) 112
8221 23:19:16.704114 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8222 23:19:16.710704 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8223 23:19:16.713877 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8224 23:19:16.717261 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8225 23:19:16.720433 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8226 23:19:16.724067 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8227 23:19:16.727175 ==
8228 23:19:16.730529 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 23:19:16.733714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 23:19:16.733792 ==
8231 23:19:16.733877 DQS Delay:
8232 23:19:16.737175 DQS0 = 0, DQS1 = 0
8233 23:19:16.737258 DQM Delay:
8234 23:19:16.740279 DQM0 = 124, DQM1 = 118
8235 23:19:16.740388 DQ Delay:
8236 23:19:16.743599 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =120
8237 23:19:16.747081 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8238 23:19:16.750544 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =112
8239 23:19:16.753811 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8240 23:19:16.753892
8241 23:19:16.753957
8242 23:19:16.754015
8243 23:19:16.757008 [DramC_TX_OE_Calibration] TA2
8244 23:19:16.760445 Original DQ_B0 (3 6) =30, OEN = 27
8245 23:19:16.763732 Original DQ_B1 (3 6) =30, OEN = 27
8246 23:19:16.766994 24, 0x0, End_B0=24 End_B1=24
8247 23:19:16.770235 25, 0x0, End_B0=25 End_B1=25
8248 23:19:16.770324 26, 0x0, End_B0=26 End_B1=26
8249 23:19:16.773494 27, 0x0, End_B0=27 End_B1=27
8250 23:19:16.776777 28, 0x0, End_B0=28 End_B1=28
8251 23:19:16.780179 29, 0x0, End_B0=29 End_B1=29
8252 23:19:16.783375 30, 0x0, End_B0=30 End_B1=30
8253 23:19:16.783464 31, 0x5151, End_B0=30 End_B1=30
8254 23:19:16.786570 Byte0 end_step=30 best_step=27
8255 23:19:16.789911 Byte1 end_step=30 best_step=27
8256 23:19:16.793224 Byte0 TX OE(2T, 0.5T) = (3, 3)
8257 23:19:16.796497 Byte1 TX OE(2T, 0.5T) = (3, 3)
8258 23:19:16.796576
8259 23:19:16.796640
8260 23:19:16.803162 [DQSOSCAuto] RK1, (LSB)MR18= 0x2613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
8261 23:19:16.806400 CH0 RK1: MR19=303, MR18=2613
8262 23:19:16.813383 CH0_RK1: MR19=0x303, MR18=0x2613, DQSOSC=390, MR23=63, INC=24, DEC=16
8263 23:19:16.816404 [RxdqsGatingPostProcess] freq 1600
8264 23:19:16.823414 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8265 23:19:16.826705 best DQS0 dly(2T, 0.5T) = (1, 1)
8266 23:19:16.826822 best DQS1 dly(2T, 0.5T) = (1, 1)
8267 23:19:16.829683 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8268 23:19:16.832968 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8269 23:19:16.836626 best DQS0 dly(2T, 0.5T) = (1, 1)
8270 23:19:16.839663 best DQS1 dly(2T, 0.5T) = (1, 1)
8271 23:19:16.843216 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8272 23:19:16.846346 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8273 23:19:16.849685 Pre-setting of DQS Precalculation
8274 23:19:16.852857 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8275 23:19:16.856227 ==
8276 23:19:16.856328 Dram Type= 6, Freq= 0, CH_1, rank 0
8277 23:19:16.862741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 23:19:16.862826 ==
8279 23:19:16.866369 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8280 23:19:16.872559 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8281 23:19:16.875942 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8282 23:19:16.882549 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8283 23:19:16.890855 [CA 0] Center 42 (13~71) winsize 59
8284 23:19:16.894212 [CA 1] Center 42 (13~72) winsize 60
8285 23:19:16.897209 [CA 2] Center 37 (9~66) winsize 58
8286 23:19:16.900535 [CA 3] Center 36 (7~66) winsize 60
8287 23:19:16.903883 [CA 4] Center 37 (8~67) winsize 60
8288 23:19:16.907197 [CA 5] Center 37 (8~66) winsize 59
8289 23:19:16.907279
8290 23:19:16.910575 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8291 23:19:16.910657
8292 23:19:16.913851 [CATrainingPosCal] consider 1 rank data
8293 23:19:16.916905 u2DelayCellTimex100 = 258/100 ps
8294 23:19:16.923588 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8295 23:19:16.926892 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8296 23:19:16.930181 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8297 23:19:16.933522 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8298 23:19:16.936802 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8299 23:19:16.940125 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8300 23:19:16.940199
8301 23:19:16.943507 CA PerBit enable=1, Macro0, CA PI delay=36
8302 23:19:16.943580
8303 23:19:16.946847 [CBTSetCACLKResult] CA Dly = 36
8304 23:19:16.950104 CS Dly: 9 (0~40)
8305 23:19:16.953492 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8306 23:19:16.956746 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8307 23:19:16.956818 ==
8308 23:19:16.959934 Dram Type= 6, Freq= 0, CH_1, rank 1
8309 23:19:16.966618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 23:19:16.966700 ==
8311 23:19:16.970270 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8312 23:19:16.973327 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8313 23:19:16.980139 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8314 23:19:16.986325 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8315 23:19:16.993843 [CA 0] Center 42 (13~71) winsize 59
8316 23:19:16.997310 [CA 1] Center 42 (12~72) winsize 61
8317 23:19:17.000455 [CA 2] Center 38 (9~67) winsize 59
8318 23:19:17.003796 [CA 3] Center 36 (7~66) winsize 60
8319 23:19:17.007080 [CA 4] Center 38 (8~68) winsize 61
8320 23:19:17.010447 [CA 5] Center 36 (6~67) winsize 62
8321 23:19:17.010554
8322 23:19:17.013772 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8323 23:19:17.013854
8324 23:19:17.016964 [CATrainingPosCal] consider 2 rank data
8325 23:19:17.020296 u2DelayCellTimex100 = 258/100 ps
8326 23:19:17.023871 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8327 23:19:17.030584 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8328 23:19:17.033495 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8329 23:19:17.036854 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8330 23:19:17.040076 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8331 23:19:17.043476 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8332 23:19:17.043557
8333 23:19:17.047048 CA PerBit enable=1, Macro0, CA PI delay=36
8334 23:19:17.047129
8335 23:19:17.050141 [CBTSetCACLKResult] CA Dly = 36
8336 23:19:17.053543 CS Dly: 10 (0~43)
8337 23:19:17.056971 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8338 23:19:17.060362 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8339 23:19:17.060443
8340 23:19:17.063760 ----->DramcWriteLeveling(PI) begin...
8341 23:19:17.063841 ==
8342 23:19:17.066702 Dram Type= 6, Freq= 0, CH_1, rank 0
8343 23:19:17.073265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8344 23:19:17.073372 ==
8345 23:19:17.076621 Write leveling (Byte 0): 24 => 24
8346 23:19:17.076702 Write leveling (Byte 1): 27 => 27
8347 23:19:17.079907 DramcWriteLeveling(PI) end<-----
8348 23:19:17.080014
8349 23:19:17.080097 ==
8350 23:19:17.083225 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 23:19:17.089978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 23:19:17.090061 ==
8353 23:19:17.093255 [Gating] SW mode calibration
8354 23:19:17.099776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8355 23:19:17.103535 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8356 23:19:17.110189 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 23:19:17.113239 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 23:19:17.116663 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 23:19:17.123051 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 23:19:17.126305 1 4 16 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
8361 23:19:17.129741 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 23:19:17.136537 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 23:19:17.139881 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 23:19:17.143213 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 23:19:17.149622 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 23:19:17.153029 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 23:19:17.156422 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8368 23:19:17.163192 1 5 16 | B1->B0 | 2424 2525 | 0 0 | (1 0) (1 0)
8369 23:19:17.166115 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 23:19:17.169460 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 23:19:17.176285 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 23:19:17.179311 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 23:19:17.182969 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 23:19:17.189236 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 23:19:17.192609 1 6 12 | B1->B0 | 2929 2626 | 0 1 | (0 0) (0 0)
8376 23:19:17.196109 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8377 23:19:17.199580 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 23:19:17.206042 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 23:19:17.209264 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 23:19:17.212574 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 23:19:17.219177 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 23:19:17.222450 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 23:19:17.225892 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8384 23:19:17.232590 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8385 23:19:17.235943 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 23:19:17.239143 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 23:19:17.245550 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 23:19:17.248985 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 23:19:17.252412 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 23:19:17.259134 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 23:19:17.262241 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 23:19:17.265501 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 23:19:17.272410 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 23:19:17.275416 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 23:19:17.278755 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 23:19:17.285453 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 23:19:17.288744 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 23:19:17.292115 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 23:19:17.298779 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8400 23:19:17.301865 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8401 23:19:17.305321 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 23:19:17.308731 Total UI for P1: 0, mck2ui 16
8403 23:19:17.311893 best dqsien dly found for B0: ( 1, 9, 14)
8404 23:19:17.315260 Total UI for P1: 0, mck2ui 16
8405 23:19:17.318829 best dqsien dly found for B1: ( 1, 9, 16)
8406 23:19:17.322048 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8407 23:19:17.325492 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8408 23:19:17.325570
8409 23:19:17.331974 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8410 23:19:17.335260 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8411 23:19:17.338637 [Gating] SW calibration Done
8412 23:19:17.338719 ==
8413 23:19:17.341539 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 23:19:17.345142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 23:19:17.345229 ==
8416 23:19:17.345295 RX Vref Scan: 0
8417 23:19:17.345358
8418 23:19:17.348339 RX Vref 0 -> 0, step: 1
8419 23:19:17.348424
8420 23:19:17.351713 RX Delay 0 -> 252, step: 8
8421 23:19:17.354933 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8422 23:19:17.358510 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8423 23:19:17.361621 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8424 23:19:17.368591 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8425 23:19:17.371648 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8426 23:19:17.374889 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8427 23:19:17.377952 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8428 23:19:17.384741 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8429 23:19:17.387917 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8430 23:19:17.391571 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8431 23:19:17.394845 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8432 23:19:17.397833 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8433 23:19:17.404596 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8434 23:19:17.407783 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8435 23:19:17.411334 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8436 23:19:17.414405 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8437 23:19:17.414486 ==
8438 23:19:17.418007 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 23:19:17.424383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 23:19:17.424505 ==
8441 23:19:17.424611 DQS Delay:
8442 23:19:17.424697 DQS0 = 0, DQS1 = 0
8443 23:19:17.428069 DQM Delay:
8444 23:19:17.428154 DQM0 = 132, DQM1 = 126
8445 23:19:17.430912 DQ Delay:
8446 23:19:17.434646 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8447 23:19:17.437954 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8448 23:19:17.441136 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8449 23:19:17.444523 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8450 23:19:17.444604
8451 23:19:17.444670
8452 23:19:17.444732 ==
8453 23:19:17.447767 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 23:19:17.451114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 23:19:17.454234 ==
8456 23:19:17.454328
8457 23:19:17.454388
8458 23:19:17.454445 TX Vref Scan disable
8459 23:19:17.457544 == TX Byte 0 ==
8460 23:19:17.461184 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8461 23:19:17.464538 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8462 23:19:17.467669 == TX Byte 1 ==
8463 23:19:17.471053 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8464 23:19:17.474383 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8465 23:19:17.474464 ==
8466 23:19:17.477796 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 23:19:17.484228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 23:19:17.484304 ==
8469 23:19:17.497041
8470 23:19:17.500304 TX Vref early break, caculate TX vref
8471 23:19:17.503990 TX Vref=16, minBit 8, minWin=22, winSum=369
8472 23:19:17.507306 TX Vref=18, minBit 11, minWin=22, winSum=375
8473 23:19:17.510533 TX Vref=20, minBit 11, minWin=23, winSum=390
8474 23:19:17.513826 TX Vref=22, minBit 11, minWin=23, winSum=397
8475 23:19:17.517086 TX Vref=24, minBit 0, minWin=24, winSum=408
8476 23:19:17.523706 TX Vref=26, minBit 5, minWin=25, winSum=416
8477 23:19:17.527254 TX Vref=28, minBit 1, minWin=25, winSum=420
8478 23:19:17.530591 TX Vref=30, minBit 0, minWin=25, winSum=415
8479 23:19:17.533788 TX Vref=32, minBit 0, minWin=24, winSum=406
8480 23:19:17.537275 TX Vref=34, minBit 1, minWin=23, winSum=399
8481 23:19:17.540201 TX Vref=36, minBit 0, minWin=22, winSum=383
8482 23:19:17.546853 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 28
8483 23:19:17.546950
8484 23:19:17.550297 Final TX Range 0 Vref 28
8485 23:19:17.550392
8486 23:19:17.550486 ==
8487 23:19:17.553562 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 23:19:17.556931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 23:19:17.557028 ==
8490 23:19:17.557122
8491 23:19:17.560181
8492 23:19:17.560300 TX Vref Scan disable
8493 23:19:17.566761 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8494 23:19:17.566895 == TX Byte 0 ==
8495 23:19:17.570088 u2DelayCellOfst[0]=18 cells (5 PI)
8496 23:19:17.573344 u2DelayCellOfst[1]=11 cells (3 PI)
8497 23:19:17.576740 u2DelayCellOfst[2]=0 cells (0 PI)
8498 23:19:17.579779 u2DelayCellOfst[3]=7 cells (2 PI)
8499 23:19:17.583186 u2DelayCellOfst[4]=7 cells (2 PI)
8500 23:19:17.586533 u2DelayCellOfst[5]=22 cells (6 PI)
8501 23:19:17.589877 u2DelayCellOfst[6]=22 cells (6 PI)
8502 23:19:17.593168 u2DelayCellOfst[7]=7 cells (2 PI)
8503 23:19:17.596450 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8504 23:19:17.599855 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8505 23:19:17.603167 == TX Byte 1 ==
8506 23:19:17.606237 u2DelayCellOfst[8]=0 cells (0 PI)
8507 23:19:17.609597 u2DelayCellOfst[9]=7 cells (2 PI)
8508 23:19:17.612977 u2DelayCellOfst[10]=15 cells (4 PI)
8509 23:19:17.616504 u2DelayCellOfst[11]=11 cells (3 PI)
8510 23:19:17.616579 u2DelayCellOfst[12]=18 cells (5 PI)
8511 23:19:17.619566 u2DelayCellOfst[13]=22 cells (6 PI)
8512 23:19:17.623132 u2DelayCellOfst[14]=22 cells (6 PI)
8513 23:19:17.626511 u2DelayCellOfst[15]=22 cells (6 PI)
8514 23:19:17.633059 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8515 23:19:17.636192 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8516 23:19:17.636268 DramC Write-DBI on
8517 23:19:17.639373 ==
8518 23:19:17.643082 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 23:19:17.646069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 23:19:17.646174 ==
8521 23:19:17.646265
8522 23:19:17.646330
8523 23:19:17.649367 TX Vref Scan disable
8524 23:19:17.649447 == TX Byte 0 ==
8525 23:19:17.656210 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8526 23:19:17.656325 == TX Byte 1 ==
8527 23:19:17.659582 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8528 23:19:17.662666 DramC Write-DBI off
8529 23:19:17.662751
8530 23:19:17.662816 [DATLAT]
8531 23:19:17.665797 Freq=1600, CH1 RK0
8532 23:19:17.665912
8533 23:19:17.666006 DATLAT Default: 0xf
8534 23:19:17.669137 0, 0xFFFF, sum = 0
8535 23:19:17.669209 1, 0xFFFF, sum = 0
8536 23:19:17.672577 2, 0xFFFF, sum = 0
8537 23:19:17.672656 3, 0xFFFF, sum = 0
8538 23:19:17.675877 4, 0xFFFF, sum = 0
8539 23:19:17.675954 5, 0xFFFF, sum = 0
8540 23:19:17.679227 6, 0xFFFF, sum = 0
8541 23:19:17.679304 7, 0xFFFF, sum = 0
8542 23:19:17.682533 8, 0xFFFF, sum = 0
8543 23:19:17.682608 9, 0xFFFF, sum = 0
8544 23:19:17.685880 10, 0xFFFF, sum = 0
8545 23:19:17.689153 11, 0xFFFF, sum = 0
8546 23:19:17.689233 12, 0xFFFF, sum = 0
8547 23:19:17.692442 13, 0x8FFF, sum = 0
8548 23:19:17.692521 14, 0x0, sum = 1
8549 23:19:17.696028 15, 0x0, sum = 2
8550 23:19:17.696117 16, 0x0, sum = 3
8551 23:19:17.699359 17, 0x0, sum = 4
8552 23:19:17.699448 best_step = 15
8553 23:19:17.699513
8554 23:19:17.699576 ==
8555 23:19:17.702562 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 23:19:17.705651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 23:19:17.705727 ==
8558 23:19:17.708851 RX Vref Scan: 1
8559 23:19:17.708926
8560 23:19:17.712190 Set Vref Range= 24 -> 127
8561 23:19:17.712266
8562 23:19:17.712327 RX Vref 24 -> 127, step: 1
8563 23:19:17.712393
8564 23:19:17.715521 RX Delay 11 -> 252, step: 4
8565 23:19:17.715593
8566 23:19:17.718900 Set Vref, RX VrefLevel [Byte0]: 24
8567 23:19:17.722102 [Byte1]: 24
8568 23:19:17.725909
8569 23:19:17.725992 Set Vref, RX VrefLevel [Byte0]: 25
8570 23:19:17.729266 [Byte1]: 25
8571 23:19:17.733493
8572 23:19:17.733574 Set Vref, RX VrefLevel [Byte0]: 26
8573 23:19:17.736503 [Byte1]: 26
8574 23:19:17.741096
8575 23:19:17.741189 Set Vref, RX VrefLevel [Byte0]: 27
8576 23:19:17.744429 [Byte1]: 27
8577 23:19:17.748657
8578 23:19:17.748738 Set Vref, RX VrefLevel [Byte0]: 28
8579 23:19:17.752131 [Byte1]: 28
8580 23:19:17.756432
8581 23:19:17.756513 Set Vref, RX VrefLevel [Byte0]: 29
8582 23:19:17.759649 [Byte1]: 29
8583 23:19:17.763842
8584 23:19:17.763944 Set Vref, RX VrefLevel [Byte0]: 30
8585 23:19:17.767072 [Byte1]: 30
8586 23:19:17.771347
8587 23:19:17.771428 Set Vref, RX VrefLevel [Byte0]: 31
8588 23:19:17.774753 [Byte1]: 31
8589 23:19:17.779292
8590 23:19:17.779372 Set Vref, RX VrefLevel [Byte0]: 32
8591 23:19:17.782213 [Byte1]: 32
8592 23:19:17.786795
8593 23:19:17.786876 Set Vref, RX VrefLevel [Byte0]: 33
8594 23:19:17.790070 [Byte1]: 33
8595 23:19:17.794209
8596 23:19:17.794317 Set Vref, RX VrefLevel [Byte0]: 34
8597 23:19:17.797412 [Byte1]: 34
8598 23:19:17.801869
8599 23:19:17.801953 Set Vref, RX VrefLevel [Byte0]: 35
8600 23:19:17.805270 [Byte1]: 35
8601 23:19:17.809550
8602 23:19:17.809667 Set Vref, RX VrefLevel [Byte0]: 36
8603 23:19:17.812599 [Byte1]: 36
8604 23:19:17.817358
8605 23:19:17.817480 Set Vref, RX VrefLevel [Byte0]: 37
8606 23:19:17.820642 [Byte1]: 37
8607 23:19:17.824832
8608 23:19:17.824913 Set Vref, RX VrefLevel [Byte0]: 38
8609 23:19:17.828103 [Byte1]: 38
8610 23:19:17.832418
8611 23:19:17.832554 Set Vref, RX VrefLevel [Byte0]: 39
8612 23:19:17.835604 [Byte1]: 39
8613 23:19:17.840017
8614 23:19:17.840127 Set Vref, RX VrefLevel [Byte0]: 40
8615 23:19:17.843375 [Byte1]: 40
8616 23:19:17.847330
8617 23:19:17.847466 Set Vref, RX VrefLevel [Byte0]: 41
8618 23:19:17.850850 [Byte1]: 41
8619 23:19:17.855192
8620 23:19:17.855299 Set Vref, RX VrefLevel [Byte0]: 42
8621 23:19:17.858622 [Byte1]: 42
8622 23:19:17.862793
8623 23:19:17.862904 Set Vref, RX VrefLevel [Byte0]: 43
8624 23:19:17.866083 [Byte1]: 43
8625 23:19:17.870312
8626 23:19:17.870432 Set Vref, RX VrefLevel [Byte0]: 44
8627 23:19:17.873623 [Byte1]: 44
8628 23:19:17.877764
8629 23:19:17.877871 Set Vref, RX VrefLevel [Byte0]: 45
8630 23:19:17.881448 [Byte1]: 45
8631 23:19:17.885661
8632 23:19:17.885771 Set Vref, RX VrefLevel [Byte0]: 46
8633 23:19:17.888972 [Byte1]: 46
8634 23:19:17.893250
8635 23:19:17.893362 Set Vref, RX VrefLevel [Byte0]: 47
8636 23:19:17.896514 [Byte1]: 47
8637 23:19:17.900851
8638 23:19:17.900935 Set Vref, RX VrefLevel [Byte0]: 48
8639 23:19:17.904172 [Byte1]: 48
8640 23:19:17.908522
8641 23:19:17.908613 Set Vref, RX VrefLevel [Byte0]: 49
8642 23:19:17.911556 [Byte1]: 49
8643 23:19:17.916093
8644 23:19:17.916177 Set Vref, RX VrefLevel [Byte0]: 50
8645 23:19:17.919415 [Byte1]: 50
8646 23:19:17.923520
8647 23:19:17.923604 Set Vref, RX VrefLevel [Byte0]: 51
8648 23:19:17.926870 [Byte1]: 51
8649 23:19:17.931450
8650 23:19:17.931533 Set Vref, RX VrefLevel [Byte0]: 52
8651 23:19:17.934419 [Byte1]: 52
8652 23:19:17.938847
8653 23:19:17.938930 Set Vref, RX VrefLevel [Byte0]: 53
8654 23:19:17.942299 [Byte1]: 53
8655 23:19:17.946424
8656 23:19:17.946510 Set Vref, RX VrefLevel [Byte0]: 54
8657 23:19:17.949674 [Byte1]: 54
8658 23:19:17.954296
8659 23:19:17.954380 Set Vref, RX VrefLevel [Byte0]: 55
8660 23:19:17.957666 [Byte1]: 55
8661 23:19:17.961827
8662 23:19:17.961906 Set Vref, RX VrefLevel [Byte0]: 56
8663 23:19:17.965026 [Byte1]: 56
8664 23:19:17.969401
8665 23:19:17.969508 Set Vref, RX VrefLevel [Byte0]: 57
8666 23:19:17.972858 [Byte1]: 57
8667 23:19:17.976974
8668 23:19:17.977054 Set Vref, RX VrefLevel [Byte0]: 58
8669 23:19:17.980249 [Byte1]: 58
8670 23:19:17.984538
8671 23:19:17.984617 Set Vref, RX VrefLevel [Byte0]: 59
8672 23:19:17.987830 [Byte1]: 59
8673 23:19:17.992140
8674 23:19:17.992222 Set Vref, RX VrefLevel [Byte0]: 60
8675 23:19:17.995371 [Byte1]: 60
8676 23:19:17.999906
8677 23:19:18.000033 Set Vref, RX VrefLevel [Byte0]: 61
8678 23:19:18.002872 [Byte1]: 61
8679 23:19:18.007474
8680 23:19:18.007595 Set Vref, RX VrefLevel [Byte0]: 62
8681 23:19:18.010763 [Byte1]: 62
8682 23:19:18.014847
8683 23:19:18.014958 Set Vref, RX VrefLevel [Byte0]: 63
8684 23:19:18.018160 [Byte1]: 63
8685 23:19:18.022506
8686 23:19:18.022594 Set Vref, RX VrefLevel [Byte0]: 64
8687 23:19:18.025889 [Byte1]: 64
8688 23:19:18.030107
8689 23:19:18.030207 Set Vref, RX VrefLevel [Byte0]: 65
8690 23:19:18.033460 [Byte1]: 65
8691 23:19:18.038018
8692 23:19:18.038146 Set Vref, RX VrefLevel [Byte0]: 66
8693 23:19:18.040998 [Byte1]: 66
8694 23:19:18.045262
8695 23:19:18.045370 Set Vref, RX VrefLevel [Byte0]: 67
8696 23:19:18.048597 [Byte1]: 67
8697 23:19:18.052902
8698 23:19:18.053049 Set Vref, RX VrefLevel [Byte0]: 68
8699 23:19:18.056232 [Byte1]: 68
8700 23:19:18.060846
8701 23:19:18.060953 Set Vref, RX VrefLevel [Byte0]: 69
8702 23:19:18.063917 [Byte1]: 69
8703 23:19:18.068253
8704 23:19:18.068386 Set Vref, RX VrefLevel [Byte0]: 70
8705 23:19:18.071694 [Byte1]: 70
8706 23:19:18.075861
8707 23:19:18.075969 Set Vref, RX VrefLevel [Byte0]: 71
8708 23:19:18.079183 [Byte1]: 71
8709 23:19:18.083579
8710 23:19:18.083661 Set Vref, RX VrefLevel [Byte0]: 72
8711 23:19:18.086991 [Byte1]: 72
8712 23:19:18.091285
8713 23:19:18.091378 Final RX Vref Byte 0 = 56 to rank0
8714 23:19:18.094406 Final RX Vref Byte 1 = 54 to rank0
8715 23:19:18.097707 Final RX Vref Byte 0 = 56 to rank1
8716 23:19:18.101058 Final RX Vref Byte 1 = 54 to rank1==
8717 23:19:18.104411 Dram Type= 6, Freq= 0, CH_1, rank 0
8718 23:19:18.111082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8719 23:19:18.111174 ==
8720 23:19:18.111242 DQS Delay:
8721 23:19:18.114237 DQS0 = 0, DQS1 = 0
8722 23:19:18.114315 DQM Delay:
8723 23:19:18.114379 DQM0 = 131, DQM1 = 124
8724 23:19:18.117713 DQ Delay:
8725 23:19:18.120683 DQ0 =136, DQ1 =126, DQ2 =122, DQ3 =128
8726 23:19:18.124246 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8727 23:19:18.127430 DQ8 =110, DQ9 =114, DQ10 =122, DQ11 =118
8728 23:19:18.130906 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8729 23:19:18.130986
8730 23:19:18.131050
8731 23:19:18.131109
8732 23:19:18.134098 [DramC_TX_OE_Calibration] TA2
8733 23:19:18.137417 Original DQ_B0 (3 6) =30, OEN = 27
8734 23:19:18.140781 Original DQ_B1 (3 6) =30, OEN = 27
8735 23:19:18.144039 24, 0x0, End_B0=24 End_B1=24
8736 23:19:18.144112 25, 0x0, End_B0=25 End_B1=25
8737 23:19:18.147722 26, 0x0, End_B0=26 End_B1=26
8738 23:19:18.150882 27, 0x0, End_B0=27 End_B1=27
8739 23:19:18.154301 28, 0x0, End_B0=28 End_B1=28
8740 23:19:18.157550 29, 0x0, End_B0=29 End_B1=29
8741 23:19:18.157632 30, 0x0, End_B0=30 End_B1=30
8742 23:19:18.160628 31, 0x4141, End_B0=30 End_B1=30
8743 23:19:18.163886 Byte0 end_step=30 best_step=27
8744 23:19:18.167251 Byte1 end_step=30 best_step=27
8745 23:19:18.170564 Byte0 TX OE(2T, 0.5T) = (3, 3)
8746 23:19:18.174100 Byte1 TX OE(2T, 0.5T) = (3, 3)
8747 23:19:18.174181
8748 23:19:18.174244
8749 23:19:18.180777 [DQSOSCAuto] RK0, (LSB)MR18= 0x70b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
8750 23:19:18.183990 CH1 RK0: MR19=303, MR18=70B
8751 23:19:18.190648 CH1_RK0: MR19=0x303, MR18=0x70B, DQSOSC=404, MR23=63, INC=22, DEC=15
8752 23:19:18.190728
8753 23:19:18.193901 ----->DramcWriteLeveling(PI) begin...
8754 23:19:18.193982 ==
8755 23:19:18.197547 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 23:19:18.200891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 23:19:18.200972 ==
8758 23:19:18.203824 Write leveling (Byte 0): 24 => 24
8759 23:19:18.207077 Write leveling (Byte 1): 28 => 28
8760 23:19:18.210801 DramcWriteLeveling(PI) end<-----
8761 23:19:18.210880
8762 23:19:18.210942 ==
8763 23:19:18.213932 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 23:19:18.217388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 23:19:18.217482 ==
8766 23:19:18.220671 [Gating] SW mode calibration
8767 23:19:18.227054 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8768 23:19:18.233710 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8769 23:19:18.236986 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 23:19:18.240201 1 4 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
8771 23:19:18.246831 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8772 23:19:18.250162 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8773 23:19:18.253383 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 23:19:18.260199 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 23:19:18.263470 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 23:19:18.266895 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 23:19:18.273139 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 23:19:18.276752 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 23:19:18.279942 1 5 8 | B1->B0 | 3434 2929 | 0 0 | (1 0) (1 0)
8780 23:19:18.286597 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8781 23:19:18.289840 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 23:19:18.293485 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 23:19:18.299742 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 23:19:18.303394 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 23:19:18.306334 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 23:19:18.312946 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 23:19:18.316282 1 6 8 | B1->B0 | 2625 4444 | 1 1 | (0 0) (0 0)
8788 23:19:18.319540 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8789 23:19:18.326212 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 23:19:18.329703 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 23:19:18.332830 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 23:19:18.339771 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 23:19:18.342807 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 23:19:18.346048 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8795 23:19:18.352806 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8796 23:19:18.356077 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8797 23:19:18.359589 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 23:19:18.366079 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 23:19:18.369307 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 23:19:18.372758 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 23:19:18.379334 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 23:19:18.382744 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 23:19:18.385869 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 23:19:18.392747 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 23:19:18.395985 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 23:19:18.399280 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 23:19:18.405945 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 23:19:18.409192 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 23:19:18.412667 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 23:19:18.419216 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 23:19:18.422144 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8812 23:19:18.425428 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8813 23:19:18.432504 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 23:19:18.432618 Total UI for P1: 0, mck2ui 16
8815 23:19:18.435595 best dqsien dly found for B0: ( 1, 9, 10)
8816 23:19:18.438809 Total UI for P1: 0, mck2ui 16
8817 23:19:18.442393 best dqsien dly found for B1: ( 1, 9, 12)
8818 23:19:18.448880 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8819 23:19:18.452209 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8820 23:19:18.452297
8821 23:19:18.455358 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8822 23:19:18.458855 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8823 23:19:18.461926 [Gating] SW calibration Done
8824 23:19:18.461999 ==
8825 23:19:18.465450 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 23:19:18.468524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 23:19:18.468638 ==
8828 23:19:18.472103 RX Vref Scan: 0
8829 23:19:18.472192
8830 23:19:18.472252 RX Vref 0 -> 0, step: 1
8831 23:19:18.472328
8832 23:19:18.475427 RX Delay 0 -> 252, step: 8
8833 23:19:18.478593 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8834 23:19:18.485240 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8835 23:19:18.488435 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8836 23:19:18.491821 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8837 23:19:18.495189 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8838 23:19:18.498477 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8839 23:19:18.504898 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8840 23:19:18.508402 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8841 23:19:18.511698 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8842 23:19:18.514984 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8843 23:19:18.518262 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8844 23:19:18.525004 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8845 23:19:18.528381 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8846 23:19:18.531388 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8847 23:19:18.534761 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8848 23:19:18.538045 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8849 23:19:18.541581 ==
8850 23:19:18.544946 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 23:19:18.548352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 23:19:18.548450 ==
8853 23:19:18.548543 DQS Delay:
8854 23:19:18.551678 DQS0 = 0, DQS1 = 0
8855 23:19:18.551774 DQM Delay:
8856 23:19:18.554597 DQM0 = 130, DQM1 = 127
8857 23:19:18.554698 DQ Delay:
8858 23:19:18.558236 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =127
8859 23:19:18.561213 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =127
8860 23:19:18.564787 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8861 23:19:18.568030 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8862 23:19:18.568133
8863 23:19:18.568224
8864 23:19:18.568312 ==
8865 23:19:18.571202 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 23:19:18.578039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 23:19:18.578119 ==
8868 23:19:18.578183
8869 23:19:18.578243
8870 23:19:18.578300 TX Vref Scan disable
8871 23:19:18.581346 == TX Byte 0 ==
8872 23:19:18.585119 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8873 23:19:18.591563 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8874 23:19:18.591668 == TX Byte 1 ==
8875 23:19:18.594893 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8876 23:19:18.601313 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8877 23:19:18.601421 ==
8878 23:19:18.604672 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 23:19:18.607877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 23:19:18.607992 ==
8881 23:19:18.621940
8882 23:19:18.625080 TX Vref early break, caculate TX vref
8883 23:19:18.628406 TX Vref=16, minBit 0, minWin=23, winSum=380
8884 23:19:18.631706 TX Vref=18, minBit 0, minWin=23, winSum=384
8885 23:19:18.634975 TX Vref=20, minBit 0, minWin=24, winSum=402
8886 23:19:18.638293 TX Vref=22, minBit 0, minWin=25, winSum=407
8887 23:19:18.641708 TX Vref=24, minBit 0, minWin=25, winSum=413
8888 23:19:18.648296 TX Vref=26, minBit 0, minWin=25, winSum=420
8889 23:19:18.651401 TX Vref=28, minBit 5, minWin=25, winSum=426
8890 23:19:18.654901 TX Vref=30, minBit 1, minWin=25, winSum=421
8891 23:19:18.658216 TX Vref=32, minBit 5, minWin=24, winSum=415
8892 23:19:18.661603 TX Vref=34, minBit 1, minWin=23, winSum=404
8893 23:19:18.664837 TX Vref=36, minBit 1, minWin=23, winSum=396
8894 23:19:18.671484 [TxChooseVref] Worse bit 5, Min win 25, Win sum 426, Final Vref 28
8895 23:19:18.671566
8896 23:19:18.674824 Final TX Range 0 Vref 28
8897 23:19:18.674905
8898 23:19:18.674969 ==
8899 23:19:18.677867 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 23:19:18.681248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 23:19:18.681330 ==
8902 23:19:18.681393
8903 23:19:18.684605
8904 23:19:18.684685 TX Vref Scan disable
8905 23:19:18.691518 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8906 23:19:18.691600 == TX Byte 0 ==
8907 23:19:18.694726 u2DelayCellOfst[0]=18 cells (5 PI)
8908 23:19:18.698127 u2DelayCellOfst[1]=11 cells (3 PI)
8909 23:19:18.701375 u2DelayCellOfst[2]=0 cells (0 PI)
8910 23:19:18.704664 u2DelayCellOfst[3]=3 cells (1 PI)
8911 23:19:18.707949 u2DelayCellOfst[4]=7 cells (2 PI)
8912 23:19:18.711317 u2DelayCellOfst[5]=22 cells (6 PI)
8913 23:19:18.714547 u2DelayCellOfst[6]=18 cells (5 PI)
8914 23:19:18.717920 u2DelayCellOfst[7]=7 cells (2 PI)
8915 23:19:18.721467 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8916 23:19:18.724484 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8917 23:19:18.727909 == TX Byte 1 ==
8918 23:19:18.731199 u2DelayCellOfst[8]=0 cells (0 PI)
8919 23:19:18.731281 u2DelayCellOfst[9]=7 cells (2 PI)
8920 23:19:18.734342 u2DelayCellOfst[10]=15 cells (4 PI)
8921 23:19:18.737908 u2DelayCellOfst[11]=7 cells (2 PI)
8922 23:19:18.741276 u2DelayCellOfst[12]=18 cells (5 PI)
8923 23:19:18.744700 u2DelayCellOfst[13]=18 cells (5 PI)
8924 23:19:18.748023 u2DelayCellOfst[14]=22 cells (6 PI)
8925 23:19:18.751248 u2DelayCellOfst[15]=18 cells (5 PI)
8926 23:19:18.754501 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8927 23:19:18.761090 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8928 23:19:18.761173 DramC Write-DBI on
8929 23:19:18.761237 ==
8930 23:19:18.764403 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 23:19:18.770817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 23:19:18.770921 ==
8933 23:19:18.771013
8934 23:19:18.771110
8935 23:19:18.771196 TX Vref Scan disable
8936 23:19:18.774876 == TX Byte 0 ==
8937 23:19:18.778268 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8938 23:19:18.781339 == TX Byte 1 ==
8939 23:19:18.784580 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8940 23:19:18.788024 DramC Write-DBI off
8941 23:19:18.788104
8942 23:19:18.788223 [DATLAT]
8943 23:19:18.788322 Freq=1600, CH1 RK1
8944 23:19:18.788436
8945 23:19:18.791361 DATLAT Default: 0xf
8946 23:19:18.794512 0, 0xFFFF, sum = 0
8947 23:19:18.794587 1, 0xFFFF, sum = 0
8948 23:19:18.798074 2, 0xFFFF, sum = 0
8949 23:19:18.798179 3, 0xFFFF, sum = 0
8950 23:19:18.801401 4, 0xFFFF, sum = 0
8951 23:19:18.801507 5, 0xFFFF, sum = 0
8952 23:19:18.804710 6, 0xFFFF, sum = 0
8953 23:19:18.804810 7, 0xFFFF, sum = 0
8954 23:19:18.807922 8, 0xFFFF, sum = 0
8955 23:19:18.808021 9, 0xFFFF, sum = 0
8956 23:19:18.811366 10, 0xFFFF, sum = 0
8957 23:19:18.811469 11, 0xFFFF, sum = 0
8958 23:19:18.814721 12, 0xFFFF, sum = 0
8959 23:19:18.814827 13, 0x8FFF, sum = 0
8960 23:19:18.817960 14, 0x0, sum = 1
8961 23:19:18.818034 15, 0x0, sum = 2
8962 23:19:18.820974 16, 0x0, sum = 3
8963 23:19:18.821076 17, 0x0, sum = 4
8964 23:19:18.824327 best_step = 15
8965 23:19:18.824428
8966 23:19:18.824527 ==
8967 23:19:18.827862 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 23:19:18.831169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 23:19:18.831275 ==
8970 23:19:18.834465 RX Vref Scan: 0
8971 23:19:18.834545
8972 23:19:18.834610 RX Vref 0 -> 0, step: 1
8973 23:19:18.834669
8974 23:19:18.837550 RX Delay 3 -> 252, step: 4
8975 23:19:18.844151 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8976 23:19:18.847643 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8977 23:19:18.851012 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8978 23:19:18.854102 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8979 23:19:18.857501 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8980 23:19:18.864042 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8981 23:19:18.867493 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8982 23:19:18.870859 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
8983 23:19:18.874245 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8984 23:19:18.877660 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8985 23:19:18.883948 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8986 23:19:18.887267 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8987 23:19:18.890538 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8988 23:19:18.894021 iDelay=195, Bit 13, Center 132 (75 ~ 190) 116
8989 23:19:18.897255 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8990 23:19:18.903936 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8991 23:19:18.904018 ==
8992 23:19:18.907093 Dram Type= 6, Freq= 0, CH_1, rank 1
8993 23:19:18.910415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8994 23:19:18.910492 ==
8995 23:19:18.910555 DQS Delay:
8996 23:19:18.913730 DQS0 = 0, DQS1 = 0
8997 23:19:18.913801 DQM Delay:
8998 23:19:18.917050 DQM0 = 127, DQM1 = 125
8999 23:19:18.917118 DQ Delay:
9000 23:19:18.920502 DQ0 =134, DQ1 =126, DQ2 =114, DQ3 =124
9001 23:19:18.923695 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =122
9002 23:19:18.927263 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9003 23:19:18.930273 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9004 23:19:18.930355
9005 23:19:18.933642
9006 23:19:18.933722
9007 23:19:18.933786 [DramC_TX_OE_Calibration] TA2
9008 23:19:18.936940 Original DQ_B0 (3 6) =30, OEN = 27
9009 23:19:18.940452 Original DQ_B1 (3 6) =30, OEN = 27
9010 23:19:18.943651 24, 0x0, End_B0=24 End_B1=24
9011 23:19:18.947027 25, 0x0, End_B0=25 End_B1=25
9012 23:19:18.950177 26, 0x0, End_B0=26 End_B1=26
9013 23:19:18.950260 27, 0x0, End_B0=27 End_B1=27
9014 23:19:18.953846 28, 0x0, End_B0=28 End_B1=28
9015 23:19:18.957079 29, 0x0, End_B0=29 End_B1=29
9016 23:19:18.960083 30, 0x0, End_B0=30 End_B1=30
9017 23:19:18.963765 31, 0x4141, End_B0=30 End_B1=30
9018 23:19:18.963848 Byte0 end_step=30 best_step=27
9019 23:19:18.967002 Byte1 end_step=30 best_step=27
9020 23:19:18.970207 Byte0 TX OE(2T, 0.5T) = (3, 3)
9021 23:19:18.973577 Byte1 TX OE(2T, 0.5T) = (3, 3)
9022 23:19:18.973658
9023 23:19:18.973723
9024 23:19:18.980232 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9025 23:19:18.983509 CH1 RK1: MR19=303, MR18=F1B
9026 23:19:18.990126 CH1_RK1: MR19=0x303, MR18=0xF1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9027 23:19:18.993462 [RxdqsGatingPostProcess] freq 1600
9028 23:19:19.000122 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9029 23:19:19.003501 best DQS0 dly(2T, 0.5T) = (1, 1)
9030 23:19:19.003612 best DQS1 dly(2T, 0.5T) = (1, 1)
9031 23:19:19.006649 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9032 23:19:19.009927 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9033 23:19:19.013130 best DQS0 dly(2T, 0.5T) = (1, 1)
9034 23:19:19.016407 best DQS1 dly(2T, 0.5T) = (1, 1)
9035 23:19:19.020127 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9036 23:19:19.023101 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9037 23:19:19.026466 Pre-setting of DQS Precalculation
9038 23:19:19.029757 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9039 23:19:19.039818 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9040 23:19:19.046404 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9041 23:19:19.046486
9042 23:19:19.046549
9043 23:19:19.049769 [Calibration Summary] 3200 Mbps
9044 23:19:19.049851 CH 0, Rank 0
9045 23:19:19.053064 SW Impedance : PASS
9046 23:19:19.053145 DUTY Scan : NO K
9047 23:19:19.056419 ZQ Calibration : PASS
9048 23:19:19.059732 Jitter Meter : NO K
9049 23:19:19.059827 CBT Training : PASS
9050 23:19:19.063010 Write leveling : PASS
9051 23:19:19.066275 RX DQS gating : PASS
9052 23:19:19.066363 RX DQ/DQS(RDDQC) : PASS
9053 23:19:19.069598 TX DQ/DQS : PASS
9054 23:19:19.072963 RX DATLAT : PASS
9055 23:19:19.073044 RX DQ/DQS(Engine): PASS
9056 23:19:19.076389 TX OE : PASS
9057 23:19:19.076471 All Pass.
9058 23:19:19.076535
9059 23:19:19.079647 CH 0, Rank 1
9060 23:19:19.079728 SW Impedance : PASS
9061 23:19:19.082913 DUTY Scan : NO K
9062 23:19:19.086507 ZQ Calibration : PASS
9063 23:19:19.086607 Jitter Meter : NO K
9064 23:19:19.089540 CBT Training : PASS
9065 23:19:19.092935 Write leveling : PASS
9066 23:19:19.093005 RX DQS gating : PASS
9067 23:19:19.096450 RX DQ/DQS(RDDQC) : PASS
9068 23:19:19.096549 TX DQ/DQS : PASS
9069 23:19:19.099748 RX DATLAT : PASS
9070 23:19:19.103067 RX DQ/DQS(Engine): PASS
9071 23:19:19.103145 TX OE : PASS
9072 23:19:19.106254 All Pass.
9073 23:19:19.106334
9074 23:19:19.106427 CH 1, Rank 0
9075 23:19:19.109388 SW Impedance : PASS
9076 23:19:19.109514 DUTY Scan : NO K
9077 23:19:19.112730 ZQ Calibration : PASS
9078 23:19:19.116306 Jitter Meter : NO K
9079 23:19:19.116415 CBT Training : PASS
9080 23:19:19.119411 Write leveling : PASS
9081 23:19:19.122733 RX DQS gating : PASS
9082 23:19:19.122827 RX DQ/DQS(RDDQC) : PASS
9083 23:19:19.125856 TX DQ/DQS : PASS
9084 23:19:19.129299 RX DATLAT : PASS
9085 23:19:19.129403 RX DQ/DQS(Engine): PASS
9086 23:19:19.132644 TX OE : PASS
9087 23:19:19.132723 All Pass.
9088 23:19:19.132786
9089 23:19:19.135952 CH 1, Rank 1
9090 23:19:19.136031 SW Impedance : PASS
9091 23:19:19.139236 DUTY Scan : NO K
9092 23:19:19.142553 ZQ Calibration : PASS
9093 23:19:19.142632 Jitter Meter : NO K
9094 23:19:19.146129 CBT Training : PASS
9095 23:19:19.149038 Write leveling : PASS
9096 23:19:19.149117 RX DQS gating : PASS
9097 23:19:19.152556 RX DQ/DQS(RDDQC) : PASS
9098 23:19:19.152649 TX DQ/DQS : PASS
9099 23:19:19.155868 RX DATLAT : PASS
9100 23:19:19.159203 RX DQ/DQS(Engine): PASS
9101 23:19:19.159282 TX OE : PASS
9102 23:19:19.162368 All Pass.
9103 23:19:19.162449
9104 23:19:19.162546 DramC Write-DBI on
9105 23:19:19.165804 PER_BANK_REFRESH: Hybrid Mode
9106 23:19:19.169058 TX_TRACKING: ON
9107 23:19:19.175719 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9108 23:19:19.185934 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9109 23:19:19.192302 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9110 23:19:19.195540 [FAST_K] Save calibration result to emmc
9111 23:19:19.198972 sync common calibartion params.
9112 23:19:19.199055 sync cbt_mode0:1, 1:1
9113 23:19:19.202429 dram_init: ddr_geometry: 2
9114 23:19:19.205440 dram_init: ddr_geometry: 2
9115 23:19:19.209037 dram_init: ddr_geometry: 2
9116 23:19:19.209151 0:dram_rank_size:100000000
9117 23:19:19.212232 1:dram_rank_size:100000000
9118 23:19:19.218769 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9119 23:19:19.218882 DFS_SHUFFLE_HW_MODE: ON
9120 23:19:19.225452 dramc_set_vcore_voltage set vcore to 725000
9121 23:19:19.225546 Read voltage for 1600, 0
9122 23:19:19.225611 Vio18 = 0
9123 23:19:19.229145 Vcore = 725000
9124 23:19:19.229252 Vdram = 0
9125 23:19:19.229343 Vddq = 0
9126 23:19:19.232212 Vmddr = 0
9127 23:19:19.232319 switch to 3200 Mbps bootup
9128 23:19:19.235507 [DramcRunTimeConfig]
9129 23:19:19.235613 PHYPLL
9130 23:19:19.238993 DPM_CONTROL_AFTERK: ON
9131 23:19:19.239074 PER_BANK_REFRESH: ON
9132 23:19:19.242290 REFRESH_OVERHEAD_REDUCTION: ON
9133 23:19:19.245638 CMD_PICG_NEW_MODE: OFF
9134 23:19:19.245746 XRTWTW_NEW_MODE: ON
9135 23:19:19.249048 XRTRTR_NEW_MODE: ON
9136 23:19:19.249128 TX_TRACKING: ON
9137 23:19:19.252234 RDSEL_TRACKING: OFF
9138 23:19:19.255670 DQS Precalculation for DVFS: ON
9139 23:19:19.255778 RX_TRACKING: OFF
9140 23:19:19.259095 HW_GATING DBG: ON
9141 23:19:19.259175 ZQCS_ENABLE_LP4: ON
9142 23:19:19.262399 RX_PICG_NEW_MODE: ON
9143 23:19:19.262480 TX_PICG_NEW_MODE: ON
9144 23:19:19.265696 ENABLE_RX_DCM_DPHY: ON
9145 23:19:19.268915 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9146 23:19:19.272293 DUMMY_READ_FOR_TRACKING: OFF
9147 23:19:19.272374 !!! SPM_CONTROL_AFTERK: OFF
9148 23:19:19.275558 !!! SPM could not control APHY
9149 23:19:19.278768 IMPEDANCE_TRACKING: ON
9150 23:19:19.278848 TEMP_SENSOR: ON
9151 23:19:19.282057 HW_SAVE_FOR_SR: OFF
9152 23:19:19.285413 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9153 23:19:19.288758 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9154 23:19:19.292273 Read ODT Tracking: ON
9155 23:19:19.292354 Refresh Rate DeBounce: ON
9156 23:19:19.295366 DFS_NO_QUEUE_FLUSH: ON
9157 23:19:19.298893 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9158 23:19:19.302237 ENABLE_DFS_RUNTIME_MRW: OFF
9159 23:19:19.302320 DDR_RESERVE_NEW_MODE: ON
9160 23:19:19.305425 MR_CBT_SWITCH_FREQ: ON
9161 23:19:19.308394 =========================
9162 23:19:19.325988 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9163 23:19:19.329280 dram_init: ddr_geometry: 2
9164 23:19:19.347531 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9165 23:19:19.350803 dram_init: dram init end (result: 0)
9166 23:19:19.357568 DRAM-K: Full calibration passed in 24581 msecs
9167 23:19:19.360875 MRC: failed to locate region type 0.
9168 23:19:19.360955 DRAM rank0 size:0x100000000,
9169 23:19:19.364053 DRAM rank1 size=0x100000000
9170 23:19:19.374297 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9171 23:19:19.380808 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9172 23:19:19.387549 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9173 23:19:19.393931 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9174 23:19:19.397377 DRAM rank0 size:0x100000000,
9175 23:19:19.400635 DRAM rank1 size=0x100000000
9176 23:19:19.400717 CBMEM:
9177 23:19:19.403882 IMD: root @ 0xfffff000 254 entries.
9178 23:19:19.407742 IMD: root @ 0xffffec00 62 entries.
9179 23:19:19.410930 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9180 23:19:19.413901 WARNING: RO_VPD is uninitialized or empty.
9181 23:19:19.420465 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9182 23:19:19.431004 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9183 23:19:19.440406 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9184 23:19:19.451790 BS: romstage times (exec / console): total (unknown) / 24044 ms
9185 23:19:19.451898
9186 23:19:19.451999
9187 23:19:19.461617 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9188 23:19:19.465237 ARM64: Exception handlers installed.
9189 23:19:19.468632 ARM64: Testing exception
9190 23:19:19.471769 ARM64: Done test exception
9191 23:19:19.471844 Enumerating buses...
9192 23:19:19.475005 Show all devs... Before device enumeration.
9193 23:19:19.478407 Root Device: enabled 1
9194 23:19:19.481689 CPU_CLUSTER: 0: enabled 1
9195 23:19:19.481793 CPU: 00: enabled 1
9196 23:19:19.484893 Compare with tree...
9197 23:19:19.484973 Root Device: enabled 1
9198 23:19:19.488003 CPU_CLUSTER: 0: enabled 1
9199 23:19:19.491555 CPU: 00: enabled 1
9200 23:19:19.491636 Root Device scanning...
9201 23:19:19.494869 scan_static_bus for Root Device
9202 23:19:19.498218 CPU_CLUSTER: 0 enabled
9203 23:19:19.501461 scan_static_bus for Root Device done
9204 23:19:19.504843 scan_bus: bus Root Device finished in 8 msecs
9205 23:19:19.504915 done
9206 23:19:19.513460 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9207 23:19:19.514569 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9208 23:19:19.521413 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9209 23:19:19.524446 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9210 23:19:19.527819 Allocating resources...
9211 23:19:19.531027 Reading resources...
9212 23:19:19.534444 Root Device read_resources bus 0 link: 0
9213 23:19:19.537699 DRAM rank0 size:0x100000000,
9214 23:19:19.537779 DRAM rank1 size=0x100000000
9215 23:19:19.541357 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9216 23:19:19.544515 CPU: 00 missing read_resources
9217 23:19:19.551017 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9218 23:19:19.554416 Root Device read_resources bus 0 link: 0 done
9219 23:19:19.554505 Done reading resources.
9220 23:19:19.561098 Show resources in subtree (Root Device)...After reading.
9221 23:19:19.564428 Root Device child on link 0 CPU_CLUSTER: 0
9222 23:19:19.567746 CPU_CLUSTER: 0 child on link 0 CPU: 00
9223 23:19:19.577625 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9224 23:19:19.577719 CPU: 00
9225 23:19:19.580591 Root Device assign_resources, bus 0 link: 0
9226 23:19:19.583867 CPU_CLUSTER: 0 missing set_resources
9227 23:19:19.590838 Root Device assign_resources, bus 0 link: 0 done
9228 23:19:19.590918 Done setting resources.
9229 23:19:19.597250 Show resources in subtree (Root Device)...After assigning values.
9230 23:19:19.600846 Root Device child on link 0 CPU_CLUSTER: 0
9231 23:19:19.604124 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 23:19:19.614236 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 23:19:19.614330 CPU: 00
9234 23:19:19.617610 Done allocating resources.
9235 23:19:19.623875 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9236 23:19:19.623956 Enabling resources...
9237 23:19:19.624019 done.
9238 23:19:19.630860 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9239 23:19:19.630948 Initializing devices...
9240 23:19:19.633995 Root Device init
9241 23:19:19.634073 init hardware done!
9242 23:19:19.637091 0x00000018: ctrlr->caps
9243 23:19:19.640560 52.000 MHz: ctrlr->f_max
9244 23:19:19.640642 0.400 MHz: ctrlr->f_min
9245 23:19:19.643890 0x40ff8080: ctrlr->voltages
9246 23:19:19.647068 sclk: 390625
9247 23:19:19.647179 Bus Width = 1
9248 23:19:19.647242 sclk: 390625
9249 23:19:19.650619 Bus Width = 1
9250 23:19:19.650723 Early init status = 3
9251 23:19:19.657223 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9252 23:19:19.660603 in-header: 03 fc 00 00 01 00 00 00
9253 23:19:19.664268 in-data: 00
9254 23:19:19.667044 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9255 23:19:19.671342 in-header: 03 fd 00 00 00 00 00 00
9256 23:19:19.674747 in-data:
9257 23:19:19.678110 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9258 23:19:19.682639 in-header: 03 fc 00 00 01 00 00 00
9259 23:19:19.685831 in-data: 00
9260 23:19:19.688918 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9261 23:19:19.694539 in-header: 03 fd 00 00 00 00 00 00
9262 23:19:19.697940 in-data:
9263 23:19:19.701092 [SSUSB] Setting up USB HOST controller...
9264 23:19:19.704562 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9265 23:19:19.707741 [SSUSB] phy power-on done.
9266 23:19:19.711089 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9267 23:19:19.717787 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9268 23:19:19.721096 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9269 23:19:19.727623 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9270 23:19:19.734168 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9271 23:19:19.740867 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9272 23:19:19.747524 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9273 23:19:19.754210 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9274 23:19:19.757435 SPM: binary array size = 0x9dc
9275 23:19:19.760641 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9276 23:19:19.767103 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9277 23:19:19.773728 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9278 23:19:19.780415 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9279 23:19:19.783886 configure_display: Starting display init
9280 23:19:19.817788 anx7625_power_on_init: Init interface.
9281 23:19:19.821153 anx7625_disable_pd_protocol: Disabled PD feature.
9282 23:19:19.824429 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9283 23:19:19.852274 anx7625_start_dp_work: Secure OCM version=00
9284 23:19:19.855443 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9285 23:19:19.870249 sp_tx_get_edid_block: EDID Block = 1
9286 23:19:19.972973 Extracted contents:
9287 23:19:19.976314 header: 00 ff ff ff ff ff ff 00
9288 23:19:19.979632 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9289 23:19:19.982979 version: 01 04
9290 23:19:19.986087 basic params: 95 1f 11 78 0a
9291 23:19:19.989495 chroma info: 76 90 94 55 54 90 27 21 50 54
9292 23:19:19.992912 established: 00 00 00
9293 23:19:19.999561 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9294 23:19:20.002820 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9295 23:19:20.009231 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9296 23:19:20.015968 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9297 23:19:20.022476 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9298 23:19:20.025858 extensions: 00
9299 23:19:20.025945 checksum: fb
9300 23:19:20.026013
9301 23:19:20.029277 Manufacturer: IVO Model 57d Serial Number 0
9302 23:19:20.032421 Made week 0 of 2020
9303 23:19:20.032502 EDID version: 1.4
9304 23:19:20.035599 Digital display
9305 23:19:20.039116 6 bits per primary color channel
9306 23:19:20.039198 DisplayPort interface
9307 23:19:20.042366 Maximum image size: 31 cm x 17 cm
9308 23:19:20.045716 Gamma: 220%
9309 23:19:20.045797 Check DPMS levels
9310 23:19:20.048959 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9311 23:19:20.055612 First detailed timing is preferred timing
9312 23:19:20.055695 Established timings supported:
9313 23:19:20.058839 Standard timings supported:
9314 23:19:20.062220 Detailed timings
9315 23:19:20.065589 Hex of detail: 383680a07038204018303c0035ae10000019
9316 23:19:20.068856 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9317 23:19:20.075419 0780 0798 07c8 0820 hborder 0
9318 23:19:20.078729 0438 043b 0447 0458 vborder 0
9319 23:19:20.082261 -hsync -vsync
9320 23:19:20.082341 Did detailed timing
9321 23:19:20.088915 Hex of detail: 000000000000000000000000000000000000
9322 23:19:20.092075 Manufacturer-specified data, tag 0
9323 23:19:20.095460 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9324 23:19:20.098866 ASCII string: InfoVision
9325 23:19:20.102016 Hex of detail: 000000fe00523134304e574635205248200a
9326 23:19:20.105448 ASCII string: R140NWF5 RH
9327 23:19:20.105568 Checksum
9328 23:19:20.108762 Checksum: 0xfb (valid)
9329 23:19:20.112083 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9330 23:19:20.115163 DSI data_rate: 832800000 bps
9331 23:19:20.122041 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9332 23:19:20.125409 anx7625_parse_edid: pixelclock(138800).
9333 23:19:20.128569 hactive(1920), hsync(48), hfp(24), hbp(88)
9334 23:19:20.131768 vactive(1080), vsync(12), vfp(3), vbp(17)
9335 23:19:20.135065 anx7625_dsi_config: config dsi.
9336 23:19:20.141797 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9337 23:19:20.154760 anx7625_dsi_config: success to config DSI
9338 23:19:20.158203 anx7625_dp_start: MIPI phy setup OK.
9339 23:19:20.161589 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9340 23:19:20.164845 mtk_ddp_mode_set invalid vrefresh 60
9341 23:19:20.168195 main_disp_path_setup
9342 23:19:20.168272 ovl_layer_smi_id_en
9343 23:19:20.171500 ovl_layer_smi_id_en
9344 23:19:20.171587 ccorr_config
9345 23:19:20.171653 aal_config
9346 23:19:20.174876 gamma_config
9347 23:19:20.174970 postmask_config
9348 23:19:20.178300 dither_config
9349 23:19:20.181639 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9350 23:19:20.187915 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9351 23:19:20.191270 Root Device init finished in 554 msecs
9352 23:19:20.194768 CPU_CLUSTER: 0 init
9353 23:19:20.201363 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9354 23:19:20.207841 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9355 23:19:20.207922 APU_MBOX 0x190000b0 = 0x10001
9356 23:19:20.210967 APU_MBOX 0x190001b0 = 0x10001
9357 23:19:20.214492 APU_MBOX 0x190005b0 = 0x10001
9358 23:19:20.217929 APU_MBOX 0x190006b0 = 0x10001
9359 23:19:20.224334 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9360 23:19:20.234040 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9361 23:19:20.246272 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9362 23:19:20.252727 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9363 23:19:20.264514 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9364 23:19:20.273723 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9365 23:19:20.276965 CPU_CLUSTER: 0 init finished in 81 msecs
9366 23:19:20.280405 Devices initialized
9367 23:19:20.283736 Show all devs... After init.
9368 23:19:20.283822 Root Device: enabled 1
9369 23:19:20.286941 CPU_CLUSTER: 0: enabled 1
9370 23:19:20.290211 CPU: 00: enabled 1
9371 23:19:20.293643 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9372 23:19:20.296958 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9373 23:19:20.300312 ELOG: NV offset 0x57f000 size 0x1000
9374 23:19:20.307121 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9375 23:19:20.313646 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9376 23:19:20.316845 ELOG: Event(17) added with size 13 at 2024-04-03 23:19:21 UTC
9377 23:19:20.320017 out: cmd=0x121: 03 db 21 01 00 00 00 00
9378 23:19:20.324096 in-header: 03 52 00 00 2c 00 00 00
9379 23:19:20.337286 in-data: 0c 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9380 23:19:20.344269 ELOG: Event(A1) added with size 10 at 2024-04-03 23:19:21 UTC
9381 23:19:20.350798 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9382 23:19:20.354088 ELOG: Event(A0) added with size 9 at 2024-04-03 23:19:21 UTC
9383 23:19:20.360877 elog_add_boot_reason: Logged dev mode boot
9384 23:19:20.364357 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9385 23:19:20.367725 Finalize devices...
9386 23:19:20.367855 Devices finalized
9387 23:19:20.374242 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9388 23:19:20.377504 Writing coreboot table at 0xffe64000
9389 23:19:20.380830 0. 000000000010a000-0000000000113fff: RAMSTAGE
9390 23:19:20.383827 1. 0000000040000000-00000000400fffff: RAM
9391 23:19:20.387280 2. 0000000040100000-000000004032afff: RAMSTAGE
9392 23:19:20.393969 3. 000000004032b000-00000000545fffff: RAM
9393 23:19:20.397211 4. 0000000054600000-000000005465ffff: BL31
9394 23:19:20.400592 5. 0000000054660000-00000000ffe63fff: RAM
9395 23:19:20.403885 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9396 23:19:20.410398 7. 0000000100000000-000000023fffffff: RAM
9397 23:19:20.410513 Passing 5 GPIOs to payload:
9398 23:19:20.417107 NAME | PORT | POLARITY | VALUE
9399 23:19:20.420281 EC in RW | 0x000000aa | low | undefined
9400 23:19:20.426902 EC interrupt | 0x00000005 | low | undefined
9401 23:19:20.430063 TPM interrupt | 0x000000ab | high | undefined
9402 23:19:20.433708 SD card detect | 0x00000011 | high | undefined
9403 23:19:20.440167 speaker enable | 0x00000093 | high | undefined
9404 23:19:20.443615 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9405 23:19:20.446847 in-header: 03 f9 00 00 02 00 00 00
9406 23:19:20.446938 in-data: 02 00
9407 23:19:20.450101 ADC[4]: Raw value=894821 ID=7
9408 23:19:20.453510 ADC[3]: Raw value=213440 ID=1
9409 23:19:20.453593 RAM Code: 0x71
9410 23:19:20.456762 ADC[6]: Raw value=74722 ID=0
9411 23:19:20.460078 ADC[5]: Raw value=212700 ID=1
9412 23:19:20.460158 SKU Code: 0x1
9413 23:19:20.466569 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 84da
9414 23:19:20.470055 coreboot table: 964 bytes.
9415 23:19:20.473191 IMD ROOT 0. 0xfffff000 0x00001000
9416 23:19:20.476628 IMD SMALL 1. 0xffffe000 0x00001000
9417 23:19:20.479846 RO MCACHE 2. 0xffffc000 0x00001104
9418 23:19:20.483075 CONSOLE 3. 0xfff7c000 0x00080000
9419 23:19:20.486503 FMAP 4. 0xfff7b000 0x00000452
9420 23:19:20.489671 TIME STAMP 5. 0xfff7a000 0x00000910
9421 23:19:20.492958 VBOOT WORK 6. 0xfff66000 0x00014000
9422 23:19:20.496268 RAMOOPS 7. 0xffe66000 0x00100000
9423 23:19:20.499504 COREBOOT 8. 0xffe64000 0x00002000
9424 23:19:20.499631 IMD small region:
9425 23:19:20.503194 IMD ROOT 0. 0xffffec00 0x00000400
9426 23:19:20.506507 VPD 1. 0xffffeb80 0x0000006c
9427 23:19:20.509852 MMC STATUS 2. 0xffffeb60 0x00000004
9428 23:19:20.516143 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9429 23:19:20.519534 Probing TPM: done!
9430 23:19:20.522824 Connected to device vid:did:rid of 1ae0:0028:00
9431 23:19:20.533057 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9432 23:19:20.536523 Initialized TPM device CR50 revision 0
9433 23:19:20.539919 Checking cr50 for pending updates
9434 23:19:20.543370 Reading cr50 TPM mode
9435 23:19:20.552069 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9436 23:19:20.559014 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9437 23:19:20.598787 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9438 23:19:20.602264 Checking segment from ROM address 0x40100000
9439 23:19:20.605701 Checking segment from ROM address 0x4010001c
9440 23:19:20.611912 Loading segment from ROM address 0x40100000
9441 23:19:20.612000 code (compression=0)
9442 23:19:20.621875 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9443 23:19:20.628570 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9444 23:19:20.628648 it's not compressed!
9445 23:19:20.635359 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9446 23:19:20.641861 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9447 23:19:20.659434 Loading segment from ROM address 0x4010001c
9448 23:19:20.659515 Entry Point 0x80000000
9449 23:19:20.662517 Loaded segments
9450 23:19:20.665912 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9451 23:19:20.672528 Jumping to boot code at 0x80000000(0xffe64000)
9452 23:19:20.679241 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9453 23:19:20.685632 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9454 23:19:20.693605 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9455 23:19:20.696836 Checking segment from ROM address 0x40100000
9456 23:19:20.700208 Checking segment from ROM address 0x4010001c
9457 23:19:20.706877 Loading segment from ROM address 0x40100000
9458 23:19:20.707009 code (compression=1)
9459 23:19:20.713694 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9460 23:19:20.723634 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9461 23:19:20.723726 using LZMA
9462 23:19:20.732014 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9463 23:19:20.738700 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9464 23:19:20.742011 Loading segment from ROM address 0x4010001c
9465 23:19:20.742094 Entry Point 0x54601000
9466 23:19:20.745506 Loaded segments
9467 23:19:20.748473 NOTICE: MT8192 bl31_setup
9468 23:19:20.755447 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9469 23:19:20.759028 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9470 23:19:20.762466 WARNING: region 0:
9471 23:19:20.765700 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 23:19:20.765824 WARNING: region 1:
9473 23:19:20.772467 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9474 23:19:20.775634 WARNING: region 2:
9475 23:19:20.778726 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9476 23:19:20.782356 WARNING: region 3:
9477 23:19:20.785553 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9478 23:19:20.789042 WARNING: region 4:
9479 23:19:20.795541 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 23:19:20.795628 WARNING: region 5:
9481 23:19:20.798987 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 23:19:20.802184 WARNING: region 6:
9483 23:19:20.805533 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 23:19:20.808971 WARNING: region 7:
9485 23:19:20.811909 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 23:19:20.818892 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9487 23:19:20.822373 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9488 23:19:20.825452 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9489 23:19:20.832003 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9490 23:19:20.835386 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9491 23:19:20.838851 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9492 23:19:20.845631 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9493 23:19:20.848647 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9494 23:19:20.855261 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9495 23:19:20.858724 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9496 23:19:20.862031 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9497 23:19:20.868715 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9498 23:19:20.872180 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9499 23:19:20.875158 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9500 23:19:20.881881 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9501 23:19:20.885182 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9502 23:19:20.891872 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9503 23:19:20.895437 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9504 23:19:20.898612 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9505 23:19:20.905152 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9506 23:19:20.908766 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9507 23:19:20.912386 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9508 23:19:20.918914 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9509 23:19:20.922336 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9510 23:19:20.928866 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9511 23:19:20.932459 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9512 23:19:20.935670 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9513 23:19:20.942547 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9514 23:19:20.945481 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9515 23:19:20.949093 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9516 23:19:20.955790 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9517 23:19:20.958750 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9518 23:19:20.965508 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9519 23:19:20.968886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9520 23:19:20.972133 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9521 23:19:20.975464 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9522 23:19:20.981894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9523 23:19:20.985357 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9524 23:19:20.988759 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9525 23:19:20.992138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9526 23:19:20.998758 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9527 23:19:21.001977 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9528 23:19:21.005224 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9529 23:19:21.008756 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9530 23:19:21.015394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9531 23:19:21.018761 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9532 23:19:21.022072 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9533 23:19:21.025515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9534 23:19:21.032183 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9535 23:19:21.035501 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9536 23:19:21.042098 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9537 23:19:21.045496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9538 23:19:21.048605 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9539 23:19:21.055515 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9540 23:19:21.058946 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9541 23:19:21.065553 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9542 23:19:21.068568 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9543 23:19:21.075392 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9544 23:19:21.078572 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9545 23:19:21.082253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9546 23:19:21.088638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9547 23:19:21.091898 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9548 23:19:21.098706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9549 23:19:21.102003 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9550 23:19:21.108648 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9551 23:19:21.111844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9552 23:19:21.118799 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9553 23:19:21.122009 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9554 23:19:21.125349 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9555 23:19:21.131863 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9556 23:19:21.135409 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9557 23:19:21.141742 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9558 23:19:21.145198 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9559 23:19:21.148549 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9560 23:19:21.155349 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9561 23:19:21.158644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9562 23:19:21.165555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9563 23:19:21.168449 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9564 23:19:21.175445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9565 23:19:21.178803 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9566 23:19:21.185498 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9567 23:19:21.188926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9568 23:19:21.191891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9569 23:19:21.198533 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9570 23:19:21.201929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9571 23:19:21.208506 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9572 23:19:21.212062 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9573 23:19:21.218887 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9574 23:19:21.222020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9575 23:19:21.225349 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9576 23:19:21.231964 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9577 23:19:21.235204 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9578 23:19:21.242234 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9579 23:19:21.245400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9580 23:19:21.252152 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9581 23:19:21.255311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9582 23:19:21.258754 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9583 23:19:21.265270 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9584 23:19:21.268687 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9585 23:19:21.272151 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9586 23:19:21.275536 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9587 23:19:21.282146 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9588 23:19:21.285313 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9589 23:19:21.292125 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9590 23:19:21.295791 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9591 23:19:21.299133 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9592 23:19:21.305728 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9593 23:19:21.309106 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9594 23:19:21.312293 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9595 23:19:21.318999 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9596 23:19:21.321994 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9597 23:19:21.328925 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9598 23:19:21.332000 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9599 23:19:21.335455 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9600 23:19:21.342017 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9601 23:19:21.345624 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9602 23:19:21.348922 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9603 23:19:21.355554 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9604 23:19:21.358843 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9605 23:19:21.361948 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9606 23:19:21.368873 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9607 23:19:21.372049 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9608 23:19:21.375489 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9609 23:19:21.379034 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9610 23:19:21.385459 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9611 23:19:21.388666 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9612 23:19:21.392047 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9613 23:19:21.398502 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9614 23:19:21.401900 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9615 23:19:21.408731 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9616 23:19:21.412104 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9617 23:19:21.415530 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9618 23:19:21.422249 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9619 23:19:21.425234 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9620 23:19:21.432171 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9621 23:19:21.435328 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9622 23:19:21.438856 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9623 23:19:21.445526 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9624 23:19:21.448688 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9625 23:19:21.455259 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9626 23:19:21.458735 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9627 23:19:21.461869 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9628 23:19:21.468539 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9629 23:19:21.472001 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9630 23:19:21.475262 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9631 23:19:21.482113 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9632 23:19:21.485660 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9633 23:19:21.492013 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9634 23:19:21.495490 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9635 23:19:21.498477 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9636 23:19:21.505238 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9637 23:19:21.508591 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9638 23:19:21.515380 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9639 23:19:21.518751 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9640 23:19:21.522158 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9641 23:19:21.528922 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9642 23:19:21.531918 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9643 23:19:21.535635 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9644 23:19:21.542334 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9645 23:19:21.545526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9646 23:19:21.551974 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9647 23:19:21.555654 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9648 23:19:21.558887 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9649 23:19:21.565254 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9650 23:19:21.568533 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9651 23:19:21.575487 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9652 23:19:21.578389 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9653 23:19:21.581929 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9654 23:19:21.588530 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9655 23:19:21.592020 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9656 23:19:21.598652 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9657 23:19:21.601788 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9658 23:19:21.605158 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9659 23:19:21.611713 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9660 23:19:21.615181 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9661 23:19:21.618458 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9662 23:19:21.624882 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9663 23:19:21.628204 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9664 23:19:21.634872 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9665 23:19:21.638214 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9666 23:19:21.641628 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9667 23:19:21.648419 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9668 23:19:21.651332 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9669 23:19:21.658097 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9670 23:19:21.661509 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9671 23:19:21.665052 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9672 23:19:21.671454 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9673 23:19:21.674892 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9674 23:19:21.681459 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9675 23:19:21.684580 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9676 23:19:21.687937 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9677 23:19:21.694451 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9678 23:19:21.698103 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9679 23:19:21.704668 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9680 23:19:21.707945 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9681 23:19:21.714727 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9682 23:19:21.717838 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9683 23:19:21.721104 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9684 23:19:21.727742 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9685 23:19:21.731057 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9686 23:19:21.737655 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9687 23:19:21.741032 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9688 23:19:21.744238 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9689 23:19:21.751004 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9690 23:19:21.754342 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9691 23:19:21.761054 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9692 23:19:21.764389 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9693 23:19:21.770633 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9694 23:19:21.774330 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9695 23:19:21.777576 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9696 23:19:21.784009 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9697 23:19:21.787332 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9698 23:19:21.793867 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9699 23:19:21.797322 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9700 23:19:21.800584 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9701 23:19:21.807365 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9702 23:19:21.810566 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9703 23:19:21.817014 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9704 23:19:21.820577 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9705 23:19:21.827228 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9706 23:19:21.830234 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9707 23:19:21.833799 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9708 23:19:21.840454 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9709 23:19:21.843488 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9710 23:19:21.850391 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9711 23:19:21.853671 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9712 23:19:21.860352 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9713 23:19:21.863638 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9714 23:19:21.866963 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9715 23:19:21.873624 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9716 23:19:21.876959 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9717 23:19:21.880334 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9718 23:19:21.883526 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9719 23:19:21.886736 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9720 23:19:21.893306 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9721 23:19:21.896575 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9722 23:19:21.902975 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9723 23:19:21.906326 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9724 23:19:21.909532 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9725 23:19:21.916254 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9726 23:19:21.919548 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9727 23:19:21.926178 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9728 23:19:21.929439 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9729 23:19:21.932594 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9730 23:19:21.939305 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9731 23:19:21.942612 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9732 23:19:21.949168 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9733 23:19:21.952585 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9734 23:19:21.955840 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9735 23:19:21.962577 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9736 23:19:21.965536 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9737 23:19:21.968923 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9738 23:19:21.975678 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9739 23:19:21.979042 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9740 23:19:21.982329 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9741 23:19:21.988859 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9742 23:19:21.992122 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9743 23:19:21.998661 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9744 23:19:22.002103 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9745 23:19:22.005414 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9746 23:19:22.011722 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9747 23:19:22.015074 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9748 23:19:22.021744 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9749 23:19:22.025321 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9750 23:19:22.028656 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9751 23:19:22.034812 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9752 23:19:22.038481 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9753 23:19:22.041408 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9754 23:19:22.048438 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9755 23:19:22.051520 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9756 23:19:22.054919 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9757 23:19:22.058134 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9758 23:19:22.061537 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9759 23:19:22.068033 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9760 23:19:22.071200 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9761 23:19:22.074495 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9762 23:19:22.077838 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9763 23:19:22.084686 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9764 23:19:22.087974 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9765 23:19:22.091213 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9766 23:19:22.097762 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9767 23:19:22.100993 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9768 23:19:22.104589 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9769 23:19:22.110861 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9770 23:19:22.114237 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9771 23:19:22.120785 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9772 23:19:22.124098 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9773 23:19:22.130673 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9774 23:19:22.134300 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9775 23:19:22.137255 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9776 23:19:22.143888 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9777 23:19:22.147135 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9778 23:19:22.153848 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9779 23:19:22.157351 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9780 23:19:22.160778 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9781 23:19:22.167113 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9782 23:19:22.170313 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9783 23:19:22.176842 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9784 23:19:22.180404 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9785 23:19:22.183537 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9786 23:19:22.190126 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9787 23:19:22.193456 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9788 23:19:22.200286 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9789 23:19:22.203578 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9790 23:19:22.210039 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9791 23:19:22.213354 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9792 23:19:22.216717 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9793 23:19:22.223564 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9794 23:19:22.226420 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9795 23:19:22.233065 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9796 23:19:22.236558 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9797 23:19:22.239882 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9798 23:19:22.246275 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9799 23:19:22.249626 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9800 23:19:22.256220 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9801 23:19:22.259667 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9802 23:19:22.266111 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9803 23:19:22.269510 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9804 23:19:22.272523 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9805 23:19:22.279424 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9806 23:19:22.282673 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9807 23:19:22.289353 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9808 23:19:22.292629 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9809 23:19:22.295665 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9810 23:19:22.302241 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9811 23:19:22.305850 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9812 23:19:22.312463 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9813 23:19:22.315624 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9814 23:19:22.322285 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9815 23:19:22.325711 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9816 23:19:22.329074 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9817 23:19:22.335434 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9818 23:19:22.338776 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9819 23:19:22.345631 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9820 23:19:22.348653 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9821 23:19:22.352265 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9822 23:19:22.358961 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9823 23:19:22.362242 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9824 23:19:22.368509 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9825 23:19:22.372085 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9826 23:19:22.375158 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9827 23:19:22.381820 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9828 23:19:22.385180 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9829 23:19:22.391829 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9830 23:19:22.395152 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9831 23:19:22.398329 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9832 23:19:22.405052 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9833 23:19:22.408499 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9834 23:19:22.415011 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9835 23:19:22.418401 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9836 23:19:22.425110 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9837 23:19:22.428356 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9838 23:19:22.431501 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9839 23:19:22.438364 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9840 23:19:22.441356 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9841 23:19:22.448173 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9842 23:19:22.451665 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9843 23:19:22.458239 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9844 23:19:22.461429 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9845 23:19:22.464765 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9846 23:19:22.471194 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9847 23:19:22.474901 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9848 23:19:22.481310 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9849 23:19:22.484608 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9850 23:19:22.491322 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9851 23:19:22.494161 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9852 23:19:22.500728 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9853 23:19:22.504122 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9854 23:19:22.507423 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9855 23:19:22.514052 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9856 23:19:22.517643 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9857 23:19:22.524227 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9858 23:19:22.527361 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9859 23:19:22.534113 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9860 23:19:22.537483 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9861 23:19:22.543822 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9862 23:19:22.547213 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9863 23:19:22.550594 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9864 23:19:22.557306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9865 23:19:22.560474 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9866 23:19:22.567067 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9867 23:19:22.570433 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9868 23:19:22.576845 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9869 23:19:22.580126 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9870 23:19:22.586771 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9871 23:19:22.590093 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9872 23:19:22.593419 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9873 23:19:22.599994 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9874 23:19:22.603161 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9875 23:19:22.609990 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9876 23:19:22.613240 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9877 23:19:22.619855 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9878 23:19:22.623170 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9879 23:19:22.626578 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9880 23:19:22.633336 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9881 23:19:22.636473 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9882 23:19:22.642997 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9883 23:19:22.646656 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9884 23:19:22.653106 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9885 23:19:22.656473 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9886 23:19:22.662824 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9887 23:19:22.666120 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9888 23:19:22.669464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9889 23:19:22.676237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9890 23:19:22.679480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9891 23:19:22.685876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9892 23:19:22.689183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9893 23:19:22.695997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9894 23:19:22.699162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9895 23:19:22.705878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9896 23:19:22.709345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9897 23:19:22.715839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9898 23:19:22.719018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9899 23:19:22.722424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9900 23:19:22.729040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9901 23:19:22.732356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9902 23:19:22.738883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9903 23:19:22.742360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9904 23:19:22.748765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9905 23:19:22.752122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9906 23:19:22.758976 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9907 23:19:22.762108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9908 23:19:22.768926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9909 23:19:22.772390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9910 23:19:22.778802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9911 23:19:22.782202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9912 23:19:22.788729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9913 23:19:22.792112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9914 23:19:22.798742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9915 23:19:22.801879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9916 23:19:22.808812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9917 23:19:22.812169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9918 23:19:22.818775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9919 23:19:22.821831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9920 23:19:22.828679 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9921 23:19:22.828762 INFO: [APUAPC] vio 0
9922 23:19:22.835778 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9923 23:19:22.839016 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9924 23:19:22.842016 INFO: [APUAPC] D0_APC_0: 0x400510
9925 23:19:22.845418 INFO: [APUAPC] D0_APC_1: 0x0
9926 23:19:22.848663 INFO: [APUAPC] D0_APC_2: 0x1540
9927 23:19:22.852202 INFO: [APUAPC] D0_APC_3: 0x0
9928 23:19:22.855457 INFO: [APUAPC] D1_APC_0: 0xffffffff
9929 23:19:22.858704 INFO: [APUAPC] D1_APC_1: 0xffffffff
9930 23:19:22.862144 INFO: [APUAPC] D1_APC_2: 0x3fffff
9931 23:19:22.865416 INFO: [APUAPC] D1_APC_3: 0x0
9932 23:19:22.868682 INFO: [APUAPC] D2_APC_0: 0xffffffff
9933 23:19:22.871917 INFO: [APUAPC] D2_APC_1: 0xffffffff
9934 23:19:22.875287 INFO: [APUAPC] D2_APC_2: 0x3fffff
9935 23:19:22.878447 INFO: [APUAPC] D2_APC_3: 0x0
9936 23:19:22.881722 INFO: [APUAPC] D3_APC_0: 0xffffffff
9937 23:19:22.885076 INFO: [APUAPC] D3_APC_1: 0xffffffff
9938 23:19:22.888519 INFO: [APUAPC] D3_APC_2: 0x3fffff
9939 23:19:22.891821 INFO: [APUAPC] D3_APC_3: 0x0
9940 23:19:22.895125 INFO: [APUAPC] D4_APC_0: 0xffffffff
9941 23:19:22.898511 INFO: [APUAPC] D4_APC_1: 0xffffffff
9942 23:19:22.901684 INFO: [APUAPC] D4_APC_2: 0x3fffff
9943 23:19:22.904938 INFO: [APUAPC] D4_APC_3: 0x0
9944 23:19:22.908324 INFO: [APUAPC] D5_APC_0: 0xffffffff
9945 23:19:22.911849 INFO: [APUAPC] D5_APC_1: 0xffffffff
9946 23:19:22.914853 INFO: [APUAPC] D5_APC_2: 0x3fffff
9947 23:19:22.914957 INFO: [APUAPC] D5_APC_3: 0x0
9948 23:19:22.918246 INFO: [APUAPC] D6_APC_0: 0xffffffff
9949 23:19:22.924818 INFO: [APUAPC] D6_APC_1: 0xffffffff
9950 23:19:22.924914 INFO: [APUAPC] D6_APC_2: 0x3fffff
9951 23:19:22.928336 INFO: [APUAPC] D6_APC_3: 0x0
9952 23:19:22.931582 INFO: [APUAPC] D7_APC_0: 0xffffffff
9953 23:19:22.934694 INFO: [APUAPC] D7_APC_1: 0xffffffff
9954 23:19:22.938103 INFO: [APUAPC] D7_APC_2: 0x3fffff
9955 23:19:22.941441 INFO: [APUAPC] D7_APC_3: 0x0
9956 23:19:22.944810 INFO: [APUAPC] D8_APC_0: 0xffffffff
9957 23:19:22.948135 INFO: [APUAPC] D8_APC_1: 0xffffffff
9958 23:19:22.951455 INFO: [APUAPC] D8_APC_2: 0x3fffff
9959 23:19:22.954850 INFO: [APUAPC] D8_APC_3: 0x0
9960 23:19:22.958086 INFO: [APUAPC] D9_APC_0: 0xffffffff
9961 23:19:22.961154 INFO: [APUAPC] D9_APC_1: 0xffffffff
9962 23:19:22.964542 INFO: [APUAPC] D9_APC_2: 0x3fffff
9963 23:19:22.967879 INFO: [APUAPC] D9_APC_3: 0x0
9964 23:19:22.971216 INFO: [APUAPC] D10_APC_0: 0xffffffff
9965 23:19:22.974555 INFO: [APUAPC] D10_APC_1: 0xffffffff
9966 23:19:22.978283 INFO: [APUAPC] D10_APC_2: 0x3fffff
9967 23:19:22.981446 INFO: [APUAPC] D10_APC_3: 0x0
9968 23:19:22.984877 INFO: [APUAPC] D11_APC_0: 0xffffffff
9969 23:19:22.987925 INFO: [APUAPC] D11_APC_1: 0xffffffff
9970 23:19:22.991250 INFO: [APUAPC] D11_APC_2: 0x3fffff
9971 23:19:22.994701 INFO: [APUAPC] D11_APC_3: 0x0
9972 23:19:22.997970 INFO: [APUAPC] D12_APC_0: 0xffffffff
9973 23:19:23.001284 INFO: [APUAPC] D12_APC_1: 0xffffffff
9974 23:19:23.004638 INFO: [APUAPC] D12_APC_2: 0x3fffff
9975 23:19:23.008020 INFO: [APUAPC] D12_APC_3: 0x0
9976 23:19:23.011322 INFO: [APUAPC] D13_APC_0: 0xffffffff
9977 23:19:23.014560 INFO: [APUAPC] D13_APC_1: 0xffffffff
9978 23:19:23.017630 INFO: [APUAPC] D13_APC_2: 0x3fffff
9979 23:19:23.020968 INFO: [APUAPC] D13_APC_3: 0x0
9980 23:19:23.024194 INFO: [APUAPC] D14_APC_0: 0xffffffff
9981 23:19:23.027475 INFO: [APUAPC] D14_APC_1: 0xffffffff
9982 23:19:23.030974 INFO: [APUAPC] D14_APC_2: 0x3fffff
9983 23:19:23.034106 INFO: [APUAPC] D14_APC_3: 0x0
9984 23:19:23.037604 INFO: [APUAPC] D15_APC_0: 0xffffffff
9985 23:19:23.040776 INFO: [APUAPC] D15_APC_1: 0xffffffff
9986 23:19:23.044248 INFO: [APUAPC] D15_APC_2: 0x3fffff
9987 23:19:23.047698 INFO: [APUAPC] D15_APC_3: 0x0
9988 23:19:23.050694 INFO: [APUAPC] APC_CON: 0x4
9989 23:19:23.053925 INFO: [NOCDAPC] D0_APC_0: 0x0
9990 23:19:23.057271 INFO: [NOCDAPC] D0_APC_1: 0x0
9991 23:19:23.060570 INFO: [NOCDAPC] D1_APC_0: 0x0
9992 23:19:23.063850 INFO: [NOCDAPC] D1_APC_1: 0xfff
9993 23:19:23.067388 INFO: [NOCDAPC] D2_APC_0: 0x0
9994 23:19:23.070749 INFO: [NOCDAPC] D2_APC_1: 0xfff
9995 23:19:23.070834 INFO: [NOCDAPC] D3_APC_0: 0x0
9996 23:19:23.074114 INFO: [NOCDAPC] D3_APC_1: 0xfff
9997 23:19:23.077473 INFO: [NOCDAPC] D4_APC_0: 0x0
9998 23:19:23.080846 INFO: [NOCDAPC] D4_APC_1: 0xfff
9999 23:19:23.084131 INFO: [NOCDAPC] D5_APC_0: 0x0
10000 23:19:23.087079 INFO: [NOCDAPC] D5_APC_1: 0xfff
10001 23:19:23.090421 INFO: [NOCDAPC] D6_APC_0: 0x0
10002 23:19:23.094052 INFO: [NOCDAPC] D6_APC_1: 0xfff
10003 23:19:23.097208 INFO: [NOCDAPC] D7_APC_0: 0x0
10004 23:19:23.100440 INFO: [NOCDAPC] D7_APC_1: 0xfff
10005 23:19:23.103719 INFO: [NOCDAPC] D8_APC_0: 0x0
10006 23:19:23.103832 INFO: [NOCDAPC] D8_APC_1: 0xfff
10007 23:19:23.107130 INFO: [NOCDAPC] D9_APC_0: 0x0
10008 23:19:23.110475 INFO: [NOCDAPC] D9_APC_1: 0xfff
10009 23:19:23.113730 INFO: [NOCDAPC] D10_APC_0: 0x0
10010 23:19:23.116979 INFO: [NOCDAPC] D10_APC_1: 0xfff
10011 23:19:23.120381 INFO: [NOCDAPC] D11_APC_0: 0x0
10012 23:19:23.123662 INFO: [NOCDAPC] D11_APC_1: 0xfff
10013 23:19:23.127233 INFO: [NOCDAPC] D12_APC_0: 0x0
10014 23:19:23.130330 INFO: [NOCDAPC] D12_APC_1: 0xfff
10015 23:19:23.133448 INFO: [NOCDAPC] D13_APC_0: 0x0
10016 23:19:23.137116 INFO: [NOCDAPC] D13_APC_1: 0xfff
10017 23:19:23.140327 INFO: [NOCDAPC] D14_APC_0: 0x0
10018 23:19:23.143369 INFO: [NOCDAPC] D14_APC_1: 0xfff
10019 23:19:23.146915 INFO: [NOCDAPC] D15_APC_0: 0x0
10020 23:19:23.150388 INFO: [NOCDAPC] D15_APC_1: 0xfff
10021 23:19:23.150488 INFO: [NOCDAPC] APC_CON: 0x4
10022 23:19:23.153576 INFO: [APUAPC] set_apusys_apc done
10023 23:19:23.156780 INFO: [DEVAPC] devapc_init done
10024 23:19:23.163571 INFO: GICv3 without legacy support detected.
10025 23:19:23.166745 INFO: ARM GICv3 driver initialized in EL3
10026 23:19:23.170022 INFO: Maximum SPI INTID supported: 639
10027 23:19:23.173329 INFO: BL31: Initializing runtime services
10028 23:19:23.180019 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10029 23:19:23.183334 INFO: SPM: enable CPC mode
10030 23:19:23.186618 INFO: mcdi ready for mcusys-off-idle and system suspend
10031 23:19:23.193352 INFO: BL31: Preparing for EL3 exit to normal world
10032 23:19:23.196650 INFO: Entry point address = 0x80000000
10033 23:19:23.196733 INFO: SPSR = 0x8
10034 23:19:23.203424
10035 23:19:23.203502
10036 23:19:23.203567
10037 23:19:23.206752 Starting depthcharge on Spherion...
10038 23:19:23.206859
10039 23:19:23.206974 Wipe memory regions:
10040 23:19:23.207073
10041 23:19:23.208013 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10042 23:19:23.208153 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10043 23:19:23.208266 Setting prompt string to ['asurada:']
10044 23:19:23.208377 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10045 23:19:23.210213 [0x00000040000000, 0x00000054600000)
10046 23:19:23.332384
10047 23:19:23.332521 [0x00000054660000, 0x00000080000000)
10048 23:19:23.593205
10049 23:19:23.593352 [0x000000821a7280, 0x000000ffe64000)
10050 23:19:24.338412
10051 23:19:24.338552 [0x00000100000000, 0x00000240000000)
10052 23:19:26.228459
10053 23:19:26.231720 Initializing XHCI USB controller at 0x11200000.
10054 23:19:27.269571
10055 23:19:27.272882 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10056 23:19:27.272995
10057 23:19:27.273086
10058 23:19:27.273180
10059 23:19:27.273515 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 23:19:27.373898 asurada: tftpboot 192.168.201.1 13248404/tftp-deploy-19eirvby/kernel/image.itb 13248404/tftp-deploy-19eirvby/kernel/cmdline
10062 23:19:27.374030 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 23:19:27.374108 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10064 23:19:27.378010 tftpboot 192.168.201.1 13248404/tftp-deploy-19eirvby/kernel/image.ittp-deploy-19eirvby/kernel/cmdline
10065 23:19:27.378094
10066 23:19:27.378158 Waiting for link
10067 23:19:27.538608
10068 23:19:27.538742 R8152: Initializing
10069 23:19:27.538810
10070 23:19:27.542019 Version 6 (ocp_data = 5c30)
10071 23:19:27.542099
10072 23:19:27.545080 R8152: Done initializing
10073 23:19:27.545160
10074 23:19:27.545223 Adding net device
10075 23:19:29.449218
10076 23:19:29.449779 done.
10077 23:19:29.450115
10078 23:19:29.450442 MAC: 00:24:32:30:78:ff
10079 23:19:29.450818
10080 23:19:29.452709 Sending DHCP discover... done.
10081 23:19:29.453271
10082 23:19:29.455901 Waiting for reply... done.
10083 23:19:29.456310
10084 23:19:29.460321 Sending DHCP request... done.
10085 23:19:29.460731
10086 23:19:29.465647 Waiting for reply... done.
10087 23:19:29.466058
10088 23:19:29.466391 My ip is 192.168.201.21
10089 23:19:29.466702
10090 23:19:29.469060 The DHCP server ip is 192.168.201.1
10091 23:19:29.469759
10092 23:19:29.475803 TFTP server IP predefined by user: 192.168.201.1
10093 23:19:29.476215
10094 23:19:29.482212 Bootfile predefined by user: 13248404/tftp-deploy-19eirvby/kernel/image.itb
10095 23:19:29.482632
10096 23:19:29.485314 Sending tftp read request... done.
10097 23:19:29.485754
10098 23:19:29.489067 Waiting for the transfer...
10099 23:19:29.489770
10100 23:19:30.117096 00000000 ################################################################
10101 23:19:30.117231
10102 23:19:30.762047 00080000 ################################################################
10103 23:19:30.762601
10104 23:19:31.312231 00100000 ################################################################
10105 23:19:31.312376
10106 23:19:31.849694 00180000 ################################################################
10107 23:19:31.849827
10108 23:19:32.410747 00200000 ################################################################
10109 23:19:32.410886
10110 23:19:32.965799 00280000 ################################################################
10111 23:19:32.965927
10112 23:19:33.537874 00300000 ################################################################
10113 23:19:33.538052
10114 23:19:34.085971 00380000 ################################################################
10115 23:19:34.086105
10116 23:19:34.633646 00400000 ################################################################
10117 23:19:34.633790
10118 23:19:35.308973 00480000 ################################################################
10119 23:19:35.309609
10120 23:19:36.016526 00500000 ################################################################
10121 23:19:36.017093
10122 23:19:36.696901 00580000 ################################################################
10123 23:19:36.697448
10124 23:19:37.320704 00600000 ################################################################
10125 23:19:37.320835
10126 23:19:37.909465 00680000 ################################################################
10127 23:19:37.910204
10128 23:19:38.470799 00700000 ################################################################
10129 23:19:38.470933
10130 23:19:39.038562 00780000 ################################################################
10131 23:19:39.038714
10132 23:19:39.593639 00800000 ################################################################
10133 23:19:39.593859
10134 23:19:40.192659 00880000 ################################################################
10135 23:19:40.192800
10136 23:19:40.746967 00900000 ################################################################
10137 23:19:40.747108
10138 23:19:41.290308 00980000 ################################################################
10139 23:19:41.290456
10140 23:19:41.871093 00a00000 ################################################################
10141 23:19:41.871643
10142 23:19:42.458260 00a80000 ################################################################
10143 23:19:42.458396
10144 23:19:43.023773 00b00000 ################################################################
10145 23:19:43.023909
10146 23:19:43.587988 00b80000 ################################################################
10147 23:19:43.588118
10148 23:19:44.180279 00c00000 ################################################################
10149 23:19:44.180420
10150 23:19:44.767100 00c80000 ################################################################
10151 23:19:44.767238
10152 23:19:45.326627 00d00000 ################################################################
10153 23:19:45.326757
10154 23:19:45.861636 00d80000 ################################################################
10155 23:19:45.861772
10156 23:19:46.557261 00e00000 ################################################################
10157 23:19:46.557402
10158 23:19:47.206939 00e80000 ################################################################
10159 23:19:47.207108
10160 23:19:47.768702 00f00000 ################################################################
10161 23:19:47.768843
10162 23:19:48.311911 00f80000 ################################################################
10163 23:19:48.312043
10164 23:19:48.866727 01000000 ################################################################
10165 23:19:48.866898
10166 23:19:49.443291 01080000 ################################################################
10167 23:19:49.443428
10168 23:19:49.989964 01100000 ################################################################
10169 23:19:49.990099
10170 23:19:50.571852 01180000 ################################################################
10171 23:19:50.571987
10172 23:19:51.144144 01200000 ################################################################
10173 23:19:51.144274
10174 23:19:51.749804 01280000 ################################################################
10175 23:19:51.749949
10176 23:19:52.396284 01300000 ################################################################
10177 23:19:52.396850
10178 23:19:52.970645 01380000 ################################################################
10179 23:19:52.970788
10180 23:19:53.557757 01400000 ################################################################
10181 23:19:53.557890
10182 23:19:54.134268 01480000 ################################################################
10183 23:19:54.134405
10184 23:19:54.663093 01500000 ################################################################
10185 23:19:54.663251
10186 23:19:55.235261 01580000 ################################################################
10187 23:19:55.235395
10188 23:19:55.849744 01600000 ################################################################
10189 23:19:55.850285
10190 23:19:56.537376 01680000 ################################################################
10191 23:19:56.537942
10192 23:19:57.235741 01700000 ################################################################
10193 23:19:57.236369
10194 23:19:57.944731 01780000 ################################################################
10195 23:19:57.945239
10196 23:19:58.664544 01800000 ################################################################
10197 23:19:58.665051
10198 23:19:59.371187 01880000 ################################################################
10199 23:19:59.371827
10200 23:20:00.015416 01900000 ################################################################
10201 23:20:00.015936
10202 23:20:00.641680 01980000 ################################################################
10203 23:20:00.641816
10204 23:20:01.189049 01a00000 ################################################################
10205 23:20:01.189209
10206 23:20:01.715706 01a80000 ################################################################
10207 23:20:01.715837
10208 23:20:02.267755 01b00000 ################################################################
10209 23:20:02.267886
10210 23:20:02.822751 01b80000 ################################################################
10211 23:20:02.822885
10212 23:20:03.384847 01c00000 ################################################################
10213 23:20:03.384984
10214 23:20:03.930487 01c80000 ################################################################
10215 23:20:03.930622
10216 23:20:04.500389 01d00000 ################################################################
10217 23:20:04.500543
10218 23:20:05.048350 01d80000 ################################################################
10219 23:20:05.048491
10220 23:20:05.591684 01e00000 ################################################################
10221 23:20:05.591828
10222 23:20:06.147342 01e80000 ################################################################
10223 23:20:06.147477
10224 23:20:06.720366 01f00000 ################################################################
10225 23:20:06.720510
10226 23:20:07.277795 01f80000 ################################################################
10227 23:20:07.277955
10228 23:20:07.840806 02000000 ################################################################
10229 23:20:07.840951
10230 23:20:08.404998 02080000 ################################################################
10231 23:20:08.405129
10232 23:20:08.979435 02100000 ################################################################
10233 23:20:08.979571
10234 23:20:09.582879 02180000 ################################################################
10235 23:20:09.583027
10236 23:20:10.155407 02200000 ################################################################
10237 23:20:10.155535
10238 23:20:10.757183 02280000 ################################################################
10239 23:20:10.757323
10240 23:20:11.332309 02300000 ################################################################
10241 23:20:11.332453
10242 23:20:11.923078 02380000 ################################################################
10243 23:20:11.923221
10244 23:20:12.526476 02400000 ################################################################
10245 23:20:12.526613
10246 23:20:13.103023 02480000 ################################################################
10247 23:20:13.103189
10248 23:20:13.640610 02500000 ################################################################
10249 23:20:13.640758
10250 23:20:14.198524 02580000 ################################################################
10251 23:20:14.198658
10252 23:20:14.756038 02600000 ################################################################
10253 23:20:14.756209
10254 23:20:15.324147 02680000 ################################################################
10255 23:20:15.324332
10256 23:20:15.895389 02700000 ################################################################
10257 23:20:15.895524
10258 23:20:16.447054 02780000 ################################################################
10259 23:20:16.447190
10260 23:20:16.991329 02800000 ################################################################
10261 23:20:16.991486
10262 23:20:17.551554 02880000 ################################################################
10263 23:20:17.551711
10264 23:20:18.066210 02900000 ################################################################
10265 23:20:18.066403
10266 23:20:18.590527 02980000 ################################################################
10267 23:20:18.590698
10268 23:20:19.137226 02a00000 ################################################################
10269 23:20:19.137397
10270 23:20:19.667531 02a80000 ################################################################
10271 23:20:19.667691
10272 23:20:20.207660 02b00000 ################################################################
10273 23:20:20.207826
10274 23:20:20.761742 02b80000 ################################################################
10275 23:20:20.761911
10276 23:20:21.289635 02c00000 ################################################################
10277 23:20:21.289812
10278 23:20:21.807528 02c80000 ################################################################
10279 23:20:21.807691
10280 23:20:22.343025 02d00000 ################################################################
10281 23:20:22.343185
10282 23:20:22.892713 02d80000 ################################################################
10283 23:20:22.892845
10284 23:20:23.447288 02e00000 ################################################################
10285 23:20:23.447462
10286 23:20:23.995685 02e80000 ################################################################
10287 23:20:23.995835
10288 23:20:24.524301 02f00000 ################################################################
10289 23:20:24.524455
10290 23:20:25.073663 02f80000 ################################################################
10291 23:20:25.073922
10292 23:20:25.617758 03000000 ################################################################
10293 23:20:25.617897
10294 23:20:26.167041 03080000 ################################################################
10295 23:20:26.167180
10296 23:20:26.736924 03100000 ################################################################
10297 23:20:26.737070
10298 23:20:27.314018 03180000 ################################################################
10299 23:20:27.314163
10300 23:20:27.850828 03200000 ################################################################
10301 23:20:27.850978
10302 23:20:28.400915 03280000 ################################################################
10303 23:20:28.401055
10304 23:20:28.934897 03300000 ################################################################
10305 23:20:28.935046
10306 23:20:29.455621 03380000 ################################################################
10307 23:20:29.455768
10308 23:20:29.990551 03400000 ################################################################
10309 23:20:29.990697
10310 23:20:30.514914 03480000 ################################################################
10311 23:20:30.515049
10312 23:20:31.047564 03500000 ################################################################
10313 23:20:31.047697
10314 23:20:31.594864 03580000 ################################################################
10315 23:20:31.594999
10316 23:20:32.118816 03600000 ################################################################
10317 23:20:32.119006
10318 23:20:32.657212 03680000 ################################################################
10319 23:20:32.657410
10320 23:20:33.215324 03700000 ################################################################
10321 23:20:33.215521
10322 23:20:33.775705 03780000 ################################################################
10323 23:20:33.775911
10324 23:20:34.334605 03800000 ################################################################
10325 23:20:34.334761
10326 23:20:34.895858 03880000 ################################################################
10327 23:20:34.896020
10328 23:20:35.472013 03900000 ################################################################
10329 23:20:35.472185
10330 23:20:36.052898 03980000 ################################################################
10331 23:20:36.053054
10332 23:20:36.597531 03a00000 ################################################################
10333 23:20:36.597688
10334 23:20:37.138530 03a80000 ################################################################
10335 23:20:37.138686
10336 23:20:37.700401 03b00000 ################################################################
10337 23:20:37.700549
10338 23:20:38.262553 03b80000 ################################################################
10339 23:20:38.262749
10340 23:20:38.813227 03c00000 ################################################################
10341 23:20:38.813380
10342 23:20:39.348798 03c80000 ################################################################
10343 23:20:39.348948
10344 23:20:39.904833 03d00000 ################################################################
10345 23:20:39.904984
10346 23:20:40.462379 03d80000 ################################################################
10347 23:20:40.462529
10348 23:20:41.019679 03e00000 ################################################################
10349 23:20:41.019823
10350 23:20:41.598465 03e80000 ################################################################
10351 23:20:41.598615
10352 23:20:42.154710 03f00000 ################################################################
10353 23:20:42.154859
10354 23:20:42.698446 03f80000 ################################################################
10355 23:20:42.698600
10356 23:20:43.274823 04000000 ################################################################
10357 23:20:43.274975
10358 23:20:43.853790 04080000 ################################################################
10359 23:20:43.853939
10360 23:20:44.428191 04100000 ################################################################
10361 23:20:44.428349
10362 23:20:45.007348 04180000 ################################################################
10363 23:20:45.007495
10364 23:20:45.598347 04200000 ################################################################
10365 23:20:45.598506
10366 23:20:46.137591 04280000 ################################################################
10367 23:20:46.137743
10368 23:20:46.671529 04300000 ################################################################
10369 23:20:46.671676
10370 23:20:47.248551 04380000 ################################################################
10371 23:20:47.248694
10372 23:20:47.846352 04400000 ################################################################
10373 23:20:47.846860
10374 23:20:48.524256 04480000 ################################################################
10375 23:20:48.524772
10376 23:20:49.213983 04500000 ################################################################
10377 23:20:49.214536
10378 23:20:49.905340 04580000 ################################################################
10379 23:20:49.905921
10380 23:20:50.577371 04600000 ################################################################
10381 23:20:50.577920
10382 23:20:50.672370 04680000 ######### done.
10383 23:20:50.672822
10384 23:20:50.675892 The bootfile was 73996694 bytes long.
10385 23:20:50.676320
10386 23:20:50.678957 Sending tftp read request... done.
10387 23:20:50.679365
10388 23:20:50.682828 Waiting for the transfer...
10389 23:20:50.683236
10390 23:20:50.683558 00000000 # done.
10391 23:20:50.683871
10392 23:20:50.689682 Command line loaded dynamically from TFTP file: 13248404/tftp-deploy-19eirvby/kernel/cmdline
10393 23:20:50.690211
10394 23:20:50.706029 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10395 23:20:50.706619
10396 23:20:50.706959 Loading FIT.
10397 23:20:50.707266
10398 23:20:50.709306 Image ramdisk-1 has 61040160 bytes.
10399 23:20:50.709842
10400 23:20:50.712757 Image fdt-1 has 47230 bytes.
10401 23:20:50.713266
10402 23:20:50.716068 Image kernel-1 has 12907270 bytes.
10403 23:20:50.716480
10404 23:20:50.722804 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10405 23:20:50.723216
10406 23:20:50.742888 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10407 23:20:50.743419
10408 23:20:50.746169 Choosing best match conf-1 for compat google,spherion-rev2.
10409 23:20:50.750733
10410 23:20:50.755190 Connected to device vid:did:rid of 1ae0:0028:00
10411 23:20:50.762120
10412 23:20:50.765828 tpm_get_response: command 0x17b, return code 0x0
10413 23:20:50.766255
10414 23:20:50.768671 ec_init: CrosEC protocol v3 supported (256, 248)
10415 23:20:50.773275
10416 23:20:50.777236 tpm_cleanup: add release locality here.
10417 23:20:50.777884
10418 23:20:50.778243 Shutting down all USB controllers.
10419 23:20:50.780246
10420 23:20:50.780655 Removing current net device
10421 23:20:50.780981
10422 23:20:50.786792 Exiting depthcharge with code 4 at timestamp: 116901850
10423 23:20:50.787290
10424 23:20:50.790163 LZMA decompressing kernel-1 to 0x821a6718
10425 23:20:50.790576
10426 23:20:50.793520 LZMA decompressing kernel-1 to 0x40000000
10427 23:20:52.387047
10428 23:20:52.387556 jumping to kernel
10429 23:20:52.389665 end: 2.2.4 bootloader-commands (duration 00:01:29) [common]
10430 23:20:52.390179 start: 2.2.5 auto-login-action (timeout 00:02:56) [common]
10431 23:20:52.390584 Setting prompt string to ['Linux version [0-9]']
10432 23:20:52.390957 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10433 23:20:52.391319 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10434 23:20:52.469376
10435 23:20:52.472402 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10436 23:20:52.476273 start: 2.2.5.1 login-action (timeout 00:02:56) [common]
10437 23:20:52.476825 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10438 23:20:52.477407 Setting prompt string to []
10439 23:20:52.477874 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10440 23:20:52.478267 Using line separator: #'\n'#
10441 23:20:52.478579 No login prompt set.
10442 23:20:52.478892 Parsing kernel messages
10443 23:20:52.479172 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10444 23:20:52.479666 [login-action] Waiting for messages, (timeout 00:02:56)
10445 23:20:52.479989 Waiting using forced prompt support (timeout 00:01:28)
10446 23:20:52.495729 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10447 23:20:52.499056 [ 0.000000] random: crng init done
10448 23:20:52.505329 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10449 23:20:52.508569 [ 0.000000] efi: UEFI not found.
10450 23:20:52.515418 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10451 23:20:52.522040 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10452 23:20:52.532359 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10453 23:20:52.541610 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10454 23:20:52.548877 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10455 23:20:52.554785 [ 0.000000] printk: bootconsole [mtk8250] enabled
10456 23:20:52.561642 [ 0.000000] NUMA: No NUMA configuration found
10457 23:20:52.568140 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10458 23:20:52.571275 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10459 23:20:52.574658 [ 0.000000] Zone ranges:
10460 23:20:52.581349 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10461 23:20:52.584517 [ 0.000000] DMA32 empty
10462 23:20:52.590914 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10463 23:20:52.594165 [ 0.000000] Movable zone start for each node
10464 23:20:52.597588 [ 0.000000] Early memory node ranges
10465 23:20:52.604222 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10466 23:20:52.610597 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10467 23:20:52.617570 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10468 23:20:52.623853 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10469 23:20:52.630346 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10470 23:20:52.637135 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10471 23:20:52.693547 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10472 23:20:52.699771 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10473 23:20:52.706652 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10474 23:20:52.710102 [ 0.000000] psci: probing for conduit method from DT.
10475 23:20:52.716673 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10476 23:20:52.720037 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10477 23:20:52.726505 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10478 23:20:52.729860 [ 0.000000] psci: SMC Calling Convention v1.2
10479 23:20:52.736204 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10480 23:20:52.739281 [ 0.000000] Detected VIPT I-cache on CPU0
10481 23:20:52.746315 [ 0.000000] CPU features: detected: GIC system register CPU interface
10482 23:20:52.752757 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10483 23:20:52.759024 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10484 23:20:52.765849 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10485 23:20:52.772347 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10486 23:20:52.782457 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10487 23:20:52.785614 [ 0.000000] alternatives: applying boot alternatives
10488 23:20:52.792437 [ 0.000000] Fallback order for Node 0: 0
10489 23:20:52.799117 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10490 23:20:52.802035 [ 0.000000] Policy zone: Normal
10491 23:20:52.815534 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10492 23:20:52.825263 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10493 23:20:52.837445 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10494 23:20:52.847398 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10495 23:20:52.853983 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10496 23:20:52.857423 <6>[ 0.000000] software IO TLB: area num 8.
10497 23:20:52.914307 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10498 23:20:53.064067 <6>[ 0.000000] Memory: 7904960K/8385536K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 447808K reserved, 32768K cma-reserved)
10499 23:20:53.070611 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10500 23:20:53.077222 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10501 23:20:53.080799 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10502 23:20:53.087424 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10503 23:20:53.093769 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10504 23:20:53.096947 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10505 23:20:53.107001 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10506 23:20:53.113512 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10507 23:20:53.119790 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10508 23:20:53.126538 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10509 23:20:53.129815 <6>[ 0.000000] GICv3: 608 SPIs implemented
10510 23:20:53.132859 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10511 23:20:53.139875 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10512 23:20:53.142939 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10513 23:20:53.149442 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10514 23:20:53.162894 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10515 23:20:53.175774 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10516 23:20:53.182630 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10517 23:20:53.190187 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10518 23:20:53.203480 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10519 23:20:53.209974 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10520 23:20:53.216563 <6>[ 0.009178] Console: colour dummy device 80x25
10521 23:20:53.226371 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10522 23:20:53.233299 <6>[ 0.024342] pid_max: default: 32768 minimum: 301
10523 23:20:53.236580 <6>[ 0.029213] LSM: Security Framework initializing
10524 23:20:53.243237 <6>[ 0.034181] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10525 23:20:53.253147 <6>[ 0.042043] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10526 23:20:53.259712 <6>[ 0.051461] cblist_init_generic: Setting adjustable number of callback queues.
10527 23:20:53.266361 <6>[ 0.058904] cblist_init_generic: Setting shift to 3 and lim to 1.
10528 23:20:53.276303 <6>[ 0.065282] cblist_init_generic: Setting adjustable number of callback queues.
10529 23:20:53.282961 <6>[ 0.072709] cblist_init_generic: Setting shift to 3 and lim to 1.
10530 23:20:53.286483 <6>[ 0.079112] rcu: Hierarchical SRCU implementation.
10531 23:20:53.293089 <6>[ 0.084153] rcu: Max phase no-delay instances is 1000.
10532 23:20:53.299339 <6>[ 0.091203] EFI services will not be available.
10533 23:20:53.302648 <6>[ 0.096165] smp: Bringing up secondary CPUs ...
10534 23:20:53.311084 <6>[ 0.101216] Detected VIPT I-cache on CPU1
10535 23:20:53.317465 <6>[ 0.101288] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10536 23:20:53.324283 <6>[ 0.101320] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10537 23:20:53.327748 <6>[ 0.101657] Detected VIPT I-cache on CPU2
10538 23:20:53.334018 <6>[ 0.101707] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10539 23:20:53.341067 <6>[ 0.101726] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10540 23:20:53.347387 <6>[ 0.101987] Detected VIPT I-cache on CPU3
10541 23:20:53.354044 <6>[ 0.102035] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10542 23:20:53.360736 <6>[ 0.102050] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10543 23:20:53.364167 <6>[ 0.102356] CPU features: detected: Spectre-v4
10544 23:20:53.370775 <6>[ 0.102363] CPU features: detected: Spectre-BHB
10545 23:20:53.374007 <6>[ 0.102367] Detected PIPT I-cache on CPU4
10546 23:20:53.380665 <6>[ 0.102426] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10547 23:20:53.387125 <6>[ 0.102443] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10548 23:20:53.393833 <6>[ 0.102737] Detected PIPT I-cache on CPU5
10549 23:20:53.400494 <6>[ 0.102802] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10550 23:20:53.407173 <6>[ 0.102818] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10551 23:20:53.410471 <6>[ 0.103099] Detected PIPT I-cache on CPU6
10552 23:20:53.417009 <6>[ 0.103164] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10553 23:20:53.423551 <6>[ 0.103181] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10554 23:20:53.430116 <6>[ 0.103475] Detected PIPT I-cache on CPU7
10555 23:20:53.436898 <6>[ 0.103541] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10556 23:20:53.443144 <6>[ 0.103557] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10557 23:20:53.446564 <6>[ 0.103604] smp: Brought up 1 node, 8 CPUs
10558 23:20:53.453093 <6>[ 0.244896] SMP: Total of 8 processors activated.
10559 23:20:53.456492 <6>[ 0.249818] CPU features: detected: 32-bit EL0 Support
10560 23:20:53.466297 <6>[ 0.255181] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10561 23:20:53.473591 <6>[ 0.263981] CPU features: detected: Common not Private translations
10562 23:20:53.480227 <6>[ 0.270497] CPU features: detected: CRC32 instructions
10563 23:20:53.483417 <6>[ 0.275882] CPU features: detected: RCpc load-acquire (LDAPR)
10564 23:20:53.490148 <6>[ 0.281842] CPU features: detected: LSE atomic instructions
10565 23:20:53.496792 <6>[ 0.287624] CPU features: detected: Privileged Access Never
10566 23:20:53.503266 <6>[ 0.293403] CPU features: detected: RAS Extension Support
10567 23:20:53.509347 <6>[ 0.299047] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10568 23:20:53.512984 <6>[ 0.306266] CPU: All CPU(s) started at EL2
10569 23:20:53.519188 <6>[ 0.310610] alternatives: applying system-wide alternatives
10570 23:20:53.528520 <6>[ 0.321415] devtmpfs: initialized
10571 23:20:53.544323 <6>[ 0.330406] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10572 23:20:53.550973 <6>[ 0.340362] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10573 23:20:53.557914 <6>[ 0.348578] pinctrl core: initialized pinctrl subsystem
10574 23:20:53.560906 <6>[ 0.355257] DMI not present or invalid.
10575 23:20:53.567692 <6>[ 0.359669] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10576 23:20:53.577682 <6>[ 0.366454] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10577 23:20:53.584323 <6>[ 0.374046] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10578 23:20:53.594155 <6>[ 0.382277] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10579 23:20:53.597352 <6>[ 0.390517] audit: initializing netlink subsys (disabled)
10580 23:20:53.607500 <5>[ 0.396210] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10581 23:20:53.614091 <6>[ 0.396915] thermal_sys: Registered thermal governor 'step_wise'
10582 23:20:53.620584 <6>[ 0.404180] thermal_sys: Registered thermal governor 'power_allocator'
10583 23:20:53.623923 <6>[ 0.410436] cpuidle: using governor menu
10584 23:20:53.630706 <6>[ 0.421397] NET: Registered PF_QIPCRTR protocol family
10585 23:20:53.637291 <6>[ 0.426881] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10586 23:20:53.643970 <6>[ 0.433986] ASID allocator initialised with 32768 entries
10587 23:20:53.647116 <6>[ 0.440564] Serial: AMBA PL011 UART driver
10588 23:20:53.656837 <4>[ 0.449381] Trying to register duplicate clock ID: 134
10589 23:20:53.711311 <6>[ 0.507131] KASLR enabled
10590 23:20:53.725882 <6>[ 0.514945] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10591 23:20:53.732518 <6>[ 0.521960] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10592 23:20:53.739178 <6>[ 0.528449] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10593 23:20:53.745822 <6>[ 0.535457] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10594 23:20:53.752139 <6>[ 0.541944] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10595 23:20:53.759037 <6>[ 0.548951] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10596 23:20:53.765611 <6>[ 0.555439] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10597 23:20:53.771922 <6>[ 0.562443] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10598 23:20:53.775257 <6>[ 0.569981] ACPI: Interpreter disabled.
10599 23:20:53.784200 <6>[ 0.576501] iommu: Default domain type: Translated
10600 23:20:53.790854 <6>[ 0.581613] iommu: DMA domain TLB invalidation policy: strict mode
10601 23:20:53.793952 <5>[ 0.588276] SCSI subsystem initialized
10602 23:20:53.800674 <6>[ 0.592448] usbcore: registered new interface driver usbfs
10603 23:20:53.807225 <6>[ 0.598182] usbcore: registered new interface driver hub
10604 23:20:53.810455 <6>[ 0.603734] usbcore: registered new device driver usb
10605 23:20:53.817385 <6>[ 0.609841] pps_core: LinuxPPS API ver. 1 registered
10606 23:20:53.827319 <6>[ 0.615036] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10607 23:20:53.831119 <6>[ 0.624379] PTP clock support registered
10608 23:20:53.834180 <6>[ 0.628621] EDAC MC: Ver: 3.0.0
10609 23:20:53.841317 <6>[ 0.633803] FPGA manager framework
10610 23:20:53.847950 <6>[ 0.637481] Advanced Linux Sound Architecture Driver Initialized.
10611 23:20:53.851618 <6>[ 0.644265] vgaarb: loaded
10612 23:20:53.858173 <6>[ 0.647432] clocksource: Switched to clocksource arch_sys_counter
10613 23:20:53.861631 <5>[ 0.653877] VFS: Disk quotas dquot_6.6.0
10614 23:20:53.868283 <6>[ 0.658065] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10615 23:20:53.871664 <6>[ 0.665257] pnp: PnP ACPI: disabled
10616 23:20:53.879819 <6>[ 0.671951] NET: Registered PF_INET protocol family
10617 23:20:53.889437 <6>[ 0.677559] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10618 23:20:53.900838 <6>[ 0.689885] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10619 23:20:53.910589 <6>[ 0.698698] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10620 23:20:53.917336 <6>[ 0.706668] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10621 23:20:53.927341 <6>[ 0.715364] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10622 23:20:53.933841 <6>[ 0.725114] TCP: Hash tables configured (established 65536 bind 65536)
10623 23:20:53.940753 <6>[ 0.731980] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10624 23:20:53.950302 <6>[ 0.739177] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10625 23:20:53.957141 <6>[ 0.746886] NET: Registered PF_UNIX/PF_LOCAL protocol family
10626 23:20:53.963567 <6>[ 0.753030] RPC: Registered named UNIX socket transport module.
10627 23:20:53.967056 <6>[ 0.759185] RPC: Registered udp transport module.
10628 23:20:53.973634 <6>[ 0.764117] RPC: Registered tcp transport module.
10629 23:20:53.979769 <6>[ 0.769050] RPC: Registered tcp NFSv4.1 backchannel transport module.
10630 23:20:53.983591 <6>[ 0.775716] PCI: CLS 0 bytes, default 64
10631 23:20:53.986958 <6>[ 0.780034] Unpacking initramfs...
10632 23:20:54.003444 <6>[ 0.791984] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10633 23:20:54.012853 <6>[ 0.800634] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10634 23:20:54.016032 <6>[ 0.809489] kvm [1]: IPA Size Limit: 40 bits
10635 23:20:54.022965 <6>[ 0.814016] kvm [1]: GICv3: no GICV resource entry
10636 23:20:54.026023 <6>[ 0.819037] kvm [1]: disabling GICv2 emulation
10637 23:20:54.032755 <6>[ 0.823726] kvm [1]: GIC system register CPU interface enabled
10638 23:20:54.039395 <6>[ 0.831476] kvm [1]: vgic interrupt IRQ18
10639 23:20:54.042869 <6>[ 0.835866] kvm [1]: VHE mode initialized successfully
10640 23:20:54.050232 <5>[ 0.842242] Initialise system trusted keyrings
10641 23:20:54.056832 <6>[ 0.847022] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10642 23:20:54.064865 <6>[ 0.857060] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10643 23:20:54.071591 <5>[ 0.863471] NFS: Registering the id_resolver key type
10644 23:20:54.074986 <5>[ 0.868760] Key type id_resolver registered
10645 23:20:54.081663 <5>[ 0.873173] Key type id_legacy registered
10646 23:20:54.088350 <6>[ 0.877461] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10647 23:20:54.094579 <6>[ 0.884380] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10648 23:20:54.101592 <6>[ 0.892108] 9p: Installing v9fs 9p2000 file system support
10649 23:20:54.138595 <5>[ 0.930635] Key type asymmetric registered
10650 23:20:54.141740 <5>[ 0.934966] Asymmetric key parser 'x509' registered
10651 23:20:54.152115 <6>[ 0.940105] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10652 23:20:54.155228 <6>[ 0.947735] io scheduler mq-deadline registered
10653 23:20:54.158493 <6>[ 0.952498] io scheduler kyber registered
10654 23:20:54.177670 <6>[ 0.969944] EINJ: ACPI disabled.
10655 23:20:54.210452 <4>[ 0.996139] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10656 23:20:54.220246 <4>[ 1.006777] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10657 23:20:54.235736 <6>[ 1.027709] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10658 23:20:54.243392 <6>[ 1.035720] printk: console [ttyS0] disabled
10659 23:20:54.271792 <6>[ 1.060347] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10660 23:20:54.278088 <6>[ 1.069812] printk: console [ttyS0] enabled
10661 23:20:54.281921 <6>[ 1.069812] printk: console [ttyS0] enabled
10662 23:20:54.287908 <6>[ 1.078705] printk: bootconsole [mtk8250] disabled
10663 23:20:54.291243 <6>[ 1.078705] printk: bootconsole [mtk8250] disabled
10664 23:20:54.297950 <6>[ 1.089765] SuperH (H)SCI(F) driver initialized
10665 23:20:54.301251 <6>[ 1.095028] msm_serial: driver initialized
10666 23:20:54.315550 <6>[ 1.104053] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10667 23:20:54.324961 <6>[ 1.112603] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10668 23:20:54.332010 <6>[ 1.121145] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10669 23:20:54.342003 <6>[ 1.129774] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10670 23:20:54.351842 <6>[ 1.138479] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10671 23:20:54.358504 <6>[ 1.147199] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10672 23:20:54.368539 <6>[ 1.155740] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10673 23:20:54.374932 <6>[ 1.164543] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10674 23:20:54.385032 <6>[ 1.173084] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10675 23:20:54.397024 <6>[ 1.188881] loop: module loaded
10676 23:20:54.403619 <6>[ 1.194887] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10677 23:20:54.425963 <4>[ 1.218291] mtk-pmic-keys: Failed to locate of_node [id: -1]
10678 23:20:54.433347 <6>[ 1.225145] megasas: 07.719.03.00-rc1
10679 23:20:54.443003 <6>[ 1.234836] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10680 23:20:54.450955 <6>[ 1.242815] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10681 23:20:54.467337 <6>[ 1.259261] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10682 23:20:54.523294 <6>[ 1.308884] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10683 23:20:56.689217 <6>[ 3.482095] Freeing initrd memory: 59608K
10684 23:20:56.701274 <6>[ 3.493704] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10685 23:20:56.712226 <6>[ 3.504859] tun: Universal TUN/TAP device driver, 1.6
10686 23:20:56.715608 <6>[ 3.510927] thunder_xcv, ver 1.0
10687 23:20:56.718793 <6>[ 3.514435] thunder_bgx, ver 1.0
10688 23:20:56.721905 <6>[ 3.517930] nicpf, ver 1.0
10689 23:20:56.732663 <6>[ 3.521972] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10690 23:20:56.736177 <6>[ 3.529448] hns3: Copyright (c) 2017 Huawei Corporation.
10691 23:20:56.742628 <6>[ 3.535036] hclge is initializing
10692 23:20:56.745887 <6>[ 3.538617] e1000: Intel(R) PRO/1000 Network Driver
10693 23:20:56.752698 <6>[ 3.543746] e1000: Copyright (c) 1999-2006 Intel Corporation.
10694 23:20:56.755693 <6>[ 3.549759] e1000e: Intel(R) PRO/1000 Network Driver
10695 23:20:56.762525 <6>[ 3.554974] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10696 23:20:56.769149 <6>[ 3.561160] igb: Intel(R) Gigabit Ethernet Network Driver
10697 23:20:56.775709 <6>[ 3.566811] igb: Copyright (c) 2007-2014 Intel Corporation.
10698 23:20:56.782063 <6>[ 3.572650] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10699 23:20:56.789003 <6>[ 3.579168] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10700 23:20:56.792030 <6>[ 3.585633] sky2: driver version 1.30
10701 23:20:56.798924 <6>[ 3.590637] VFIO - User Level meta-driver version: 0.3
10702 23:20:56.806310 <6>[ 3.598913] usbcore: registered new interface driver usb-storage
10703 23:20:56.812926 <6>[ 3.605368] usbcore: registered new device driver onboard-usb-hub
10704 23:20:56.822118 <6>[ 3.614556] mt6397-rtc mt6359-rtc: registered as rtc0
10705 23:20:56.832062 <6>[ 3.620033] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:20:57 UTC (1712186457)
10706 23:20:56.835050 <6>[ 3.629650] i2c_dev: i2c /dev entries driver
10707 23:20:56.852327 <6>[ 3.641599] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10708 23:20:56.858937 <4>[ 3.650340] cpu cpu0: supply cpu not found, using dummy regulator
10709 23:20:56.865311 <4>[ 3.656768] cpu cpu1: supply cpu not found, using dummy regulator
10710 23:20:56.872109 <4>[ 3.663189] cpu cpu2: supply cpu not found, using dummy regulator
10711 23:20:56.878850 <4>[ 3.669592] cpu cpu3: supply cpu not found, using dummy regulator
10712 23:20:56.885316 <4>[ 3.675989] cpu cpu4: supply cpu not found, using dummy regulator
10713 23:20:56.892045 <4>[ 3.682385] cpu cpu5: supply cpu not found, using dummy regulator
10714 23:20:56.898627 <4>[ 3.688782] cpu cpu6: supply cpu not found, using dummy regulator
10715 23:20:56.905201 <4>[ 3.695182] cpu cpu7: supply cpu not found, using dummy regulator
10716 23:20:56.923215 <6>[ 3.715864] cpu cpu0: EM: created perf domain
10717 23:20:56.926645 <6>[ 3.720814] cpu cpu4: EM: created perf domain
10718 23:20:56.933750 <6>[ 3.726422] sdhci: Secure Digital Host Controller Interface driver
10719 23:20:56.940637 <6>[ 3.732855] sdhci: Copyright(c) Pierre Ossman
10720 23:20:56.947132 <6>[ 3.737818] Synopsys Designware Multimedia Card Interface Driver
10721 23:20:56.953695 <6>[ 3.744454] sdhci-pltfm: SDHCI platform and OF driver helper
10722 23:20:56.957099 <6>[ 3.744483] mmc0: CQHCI version 5.10
10723 23:20:56.963791 <6>[ 3.754704] ledtrig-cpu: registered to indicate activity on CPUs
10724 23:20:56.970169 <6>[ 3.761808] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10725 23:20:56.976897 <6>[ 3.768867] usbcore: registered new interface driver usbhid
10726 23:20:56.980114 <6>[ 3.774691] usbhid: USB HID core driver
10727 23:20:56.986688 <6>[ 3.778900] spi_master spi0: will run message pump with realtime priority
10728 23:20:57.031639 <6>[ 3.817712] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10729 23:20:57.050038 <6>[ 3.832746] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10730 23:20:57.053409 <6>[ 3.847496] mmc0: Command Queue Engine enabled
10731 23:20:57.059900 <6>[ 3.852253] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10732 23:20:57.066442 <6>[ 3.859020] cros-ec-spi spi0.0: Chrome EC device registered
10733 23:20:57.073322 <6>[ 3.859482] mmcblk0: mmc0:0001 DA4128 116 GiB
10734 23:20:57.081933 <6>[ 3.875117] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10735 23:20:57.089404 <6>[ 3.882464] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10736 23:20:57.096349 <6>[ 3.888625] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10737 23:20:57.106133 <6>[ 3.893196] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10738 23:20:57.112514 <6>[ 3.894547] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10739 23:20:57.115845 <6>[ 3.904500] NET: Registered PF_PACKET protocol family
10740 23:20:57.122435 <6>[ 3.915068] 9pnet: Installing 9P2000 support
10741 23:20:57.125677 <5>[ 3.919640] Key type dns_resolver registered
10742 23:20:57.132485 <6>[ 3.924614] registered taskstats version 1
10743 23:20:57.135891 <5>[ 3.929003] Loading compiled-in X.509 certificates
10744 23:20:57.165986 <4>[ 3.952448] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10745 23:20:57.176154 <4>[ 3.963223] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10746 23:20:57.182611 <3>[ 3.973813] debugfs: File 'uA_load' in directory '/' already present!
10747 23:20:57.189076 <3>[ 3.980522] debugfs: File 'min_uV' in directory '/' already present!
10748 23:20:57.195610 <3>[ 3.987134] debugfs: File 'max_uV' in directory '/' already present!
10749 23:20:57.202503 <3>[ 3.993745] debugfs: File 'constraint_flags' in directory '/' already present!
10750 23:20:57.214739 <3>[ 4.004429] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10751 23:20:57.225115 <6>[ 4.018021] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10752 23:20:57.231813 <6>[ 4.024790] xhci-mtk 11200000.usb: xHCI Host Controller
10753 23:20:57.238635 <6>[ 4.030296] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10754 23:20:57.248659 <6>[ 4.038155] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10755 23:20:57.254933 <6>[ 4.047597] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10756 23:20:57.261694 <6>[ 4.053663] xhci-mtk 11200000.usb: xHCI Host Controller
10757 23:20:57.268139 <6>[ 4.059137] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10758 23:20:57.274731 <6>[ 4.066786] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10759 23:20:57.281461 <6>[ 4.074524] hub 1-0:1.0: USB hub found
10760 23:20:57.284775 <6>[ 4.078534] hub 1-0:1.0: 1 port detected
10761 23:20:57.294957 <6>[ 4.082804] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10762 23:20:57.298048 <6>[ 4.091367] hub 2-0:1.0: USB hub found
10763 23:20:57.301346 <6>[ 4.095373] hub 2-0:1.0: 1 port detected
10764 23:20:57.310120 <6>[ 4.103322] mtk-msdc 11f70000.mmc: Got CD GPIO
10765 23:20:57.322089 <6>[ 4.111811] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10766 23:20:57.328861 <6>[ 4.119819] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10767 23:20:57.338725 <4>[ 4.127715] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10768 23:20:57.348673 <6>[ 4.137235] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10769 23:20:57.355485 <6>[ 4.145311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10770 23:20:57.361773 <6>[ 4.153301] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10771 23:20:57.371908 <6>[ 4.161225] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10772 23:20:57.378364 <6>[ 4.169042] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10773 23:20:57.388288 <6>[ 4.176858] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10774 23:20:57.398056 <6>[ 4.186988] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10775 23:20:57.404687 <6>[ 4.195343] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10776 23:20:57.414743 <6>[ 4.203685] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10777 23:20:57.421281 <6>[ 4.212023] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10778 23:20:57.431264 <6>[ 4.220360] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10779 23:20:57.437719 <6>[ 4.228700] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10780 23:20:57.447516 <6>[ 4.237045] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10781 23:20:57.454403 <6>[ 4.245383] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10782 23:20:57.464123 <6>[ 4.253720] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10783 23:20:57.470817 <6>[ 4.262058] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10784 23:20:57.480789 <6>[ 4.270395] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10785 23:20:57.487327 <6>[ 4.278733] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10786 23:20:57.497226 <6>[ 4.287082] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10787 23:20:57.507318 <6>[ 4.295422] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10788 23:20:57.513852 <6>[ 4.303762] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10789 23:20:57.520364 <6>[ 4.312514] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10790 23:20:57.527223 <6>[ 4.319747] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10791 23:20:57.533637 <6>[ 4.326634] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10792 23:20:57.543980 <6>[ 4.333510] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10793 23:20:57.550338 <6>[ 4.340545] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10794 23:20:57.556856 <6>[ 4.347403] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10795 23:20:57.566739 <6>[ 4.356533] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10796 23:20:57.576961 <6>[ 4.365652] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10797 23:20:57.586603 <6>[ 4.374946] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10798 23:20:57.596477 <6>[ 4.384413] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10799 23:20:57.606698 <6>[ 4.393880] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10800 23:20:57.613291 <6>[ 4.402999] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10801 23:20:57.623333 <6>[ 4.412468] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10802 23:20:57.633406 <6>[ 4.421587] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10803 23:20:57.643546 <6>[ 4.430881] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10804 23:20:57.652960 <6>[ 4.441042] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10805 23:20:57.663279 <6>[ 4.452701] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10806 23:20:57.714283 <6>[ 4.503700] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10807 23:20:57.868826 <6>[ 4.661539] hub 1-1:1.0: USB hub found
10808 23:20:57.872141 <6>[ 4.666072] hub 1-1:1.0: 4 ports detected
10809 23:20:57.882180 <6>[ 4.674862] hub 1-1:1.0: USB hub found
10810 23:20:57.885343 <6>[ 4.679236] hub 1-1:1.0: 4 ports detected
10811 23:20:57.994858 <6>[ 4.784092] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10812 23:20:58.021032 <6>[ 4.813851] hub 2-1:1.0: USB hub found
10813 23:20:58.024561 <6>[ 4.818363] hub 2-1:1.0: 3 ports detected
10814 23:20:58.033790 <6>[ 4.826536] hub 2-1:1.0: USB hub found
10815 23:20:58.037207 <6>[ 4.830942] hub 2-1:1.0: 3 ports detected
10816 23:20:58.210253 <6>[ 4.999799] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10817 23:20:58.342424 <6>[ 5.135270] hub 1-1.4:1.0: USB hub found
10818 23:20:58.345865 <6>[ 5.139901] hub 1-1.4:1.0: 2 ports detected
10819 23:20:58.355676 <6>[ 5.148302] hub 1-1.4:1.0: USB hub found
10820 23:20:58.358987 <6>[ 5.152958] hub 1-1.4:1.0: 2 ports detected
10821 23:20:58.426436 <6>[ 5.215837] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10822 23:20:58.654005 <6>[ 5.443750] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10823 23:20:58.846168 <6>[ 5.635739] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10824 23:21:09.955234 <6>[ 16.752839] ALSA device list:
10825 23:21:09.961364 <6>[ 16.756136] No soundcards found.
10826 23:21:09.969752 <6>[ 16.764323] Freeing unused kernel memory: 8448K
10827 23:21:09.973356 <6>[ 16.769981] Run /init as init process
10828 23:21:10.006686 <6>[ 16.801067] NET: Registered PF_INET6 protocol family
10829 23:21:10.013088 <6>[ 16.807231] Segment Routing with IPv6
10830 23:21:10.016438 <6>[ 16.811171] In-situ OAM (IOAM) with IPv6
10831 23:21:10.059564 <30>[ 16.827572] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10832 23:21:10.066071 <30>[ 16.860627] systemd[1]: Detected architecture arm64.
10833 23:21:10.066158
10834 23:21:10.072755 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10835 23:21:10.072835
10836 23:21:10.072918
10837 23:21:10.085202 <30>[ 16.879758] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10838 23:21:10.241404 <30>[ 17.032627] systemd[1]: Queued start job for default target graphical.target.
10839 23:21:10.293767 <30>[ 17.085008] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10840 23:21:10.300543 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10841 23:21:10.300636
10842 23:21:10.321296 <30>[ 17.112383] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10843 23:21:10.330982 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10844 23:21:10.331070
10845 23:21:10.349131 <30>[ 17.140466] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10846 23:21:10.359243 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10847 23:21:10.359355
10848 23:21:10.377753 <30>[ 17.169188] systemd[1]: Created slice user.slice - User and Session Slice.
10849 23:21:10.384486 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10850 23:21:10.384570
10851 23:21:10.408583 <30>[ 17.196416] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10852 23:21:10.415334 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10853 23:21:10.418276
10854 23:21:10.435840 <30>[ 17.223915] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10855 23:21:10.442510 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10856 23:21:10.442593
10857 23:21:10.470860 <30>[ 17.252332] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10858 23:21:10.481237 <30>[ 17.272302] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10859 23:21:10.487876 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10860 23:21:10.487958
10861 23:21:10.504536 <30>[ 17.295786] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10862 23:21:10.511118 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10863 23:21:10.511205
10864 23:21:10.528591 <30>[ 17.319798] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10865 23:21:10.538451 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10866 23:21:10.538537
10867 23:21:10.553584 <30>[ 17.348300] systemd[1]: Reached target paths.target - Path Units.
10868 23:21:10.560622 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10869 23:21:10.563566
10870 23:21:10.580994 <30>[ 17.372208] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10871 23:21:10.587385 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10872 23:21:10.587463
10873 23:21:10.601198 <30>[ 17.395729] systemd[1]: Reached target slices.target - Slice Units.
10874 23:21:10.611206 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10875 23:21:10.611331
10876 23:21:10.625578 <30>[ 17.420256] systemd[1]: Reached target swap.target - Swaps.
10877 23:21:10.632194 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10878 23:21:10.632312
10879 23:21:10.653176 <30>[ 17.444269] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10880 23:21:10.662951 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10881 23:21:10.663163
10882 23:21:10.681770 <30>[ 17.472730] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10883 23:21:10.691542 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10884 23:21:10.691739
10885 23:21:10.710778 <30>[ 17.501938] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10886 23:21:10.720650 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10887 23:21:10.720800
10888 23:21:10.737281 <30>[ 17.528487] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10889 23:21:10.747096 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10890 23:21:10.747251
10891 23:21:10.766110 <30>[ 17.557113] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10892 23:21:10.772637 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10893 23:21:10.772784
10894 23:21:10.793931 <30>[ 17.585244] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10895 23:21:10.803835 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10896 23:21:10.803976
10897 23:21:10.821555 <30>[ 17.612973] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10898 23:21:10.831664 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10899 23:21:10.831807
10900 23:21:10.872806 <30>[ 17.663808] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10901 23:21:10.878985 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10902 23:21:10.879135
10903 23:21:10.901146 <30>[ 17.692455] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10904 23:21:10.908013 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10905 23:21:10.908155
10906 23:21:10.933385 <30>[ 17.724575] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10907 23:21:10.940079 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10908 23:21:10.940168
10909 23:21:10.967333 <30>[ 17.752235] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10910 23:21:11.017097 <30>[ 17.808251] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10911 23:21:11.026634 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10912 23:21:11.026742
10913 23:21:11.049846 <30>[ 17.841218] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10914 23:21:11.056656 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10915 23:21:11.056747
10916 23:21:11.082048 <30>[ 17.873326] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10917 23:21:11.095410 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 17.887222] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10918 23:21:11.098332 Module dm_mod...
10919 23:21:11.098416
10920 23:21:11.140860 <30>[ 17.932257] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10921 23:21:11.147490 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10922 23:21:11.147590
10923 23:21:11.174088 <30>[ 17.965326] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10924 23:21:11.180703 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10925 23:21:11.180796
10926 23:21:11.206099 <30>[ 17.997356] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10927 23:21:11.212487 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10928 23:21:11.212579
10929 23:21:11.277127 <30>[ 18.068307] systemd[1]: Starting systemd-journald.service - Journal Service...
10930 23:21:11.283602 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10931 23:21:11.283750
10932 23:21:11.303691 <30>[ 18.095035] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10933 23:21:11.310174 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10934 23:21:11.310281
10935 23:21:11.335137 <30>[ 18.123092] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10936 23:21:11.341721 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10937 23:21:11.341811
10938 23:21:11.365246 <30>[ 18.156468] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10939 23:21:11.374896 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10940 23:21:11.374993
10941 23:21:11.396238 <30>[ 18.187609] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10942 23:21:11.406213 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10943 23:21:11.406302
10944 23:21:11.428088 <30>[ 18.219661] systemd[1]: Started systemd-journald.service - Journal Service.
10945 23:21:11.434720 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10946 23:21:11.434805
10947 23:21:11.455500 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10948 23:21:11.455605
10949 23:21:11.473766 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10950 23:21:11.473873
10951 23:21:11.493360 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10952 23:21:11.493466
10953 23:21:11.514260 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10954 23:21:11.514359
10955 23:21:11.534591 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10956 23:21:11.534689
10957 23:21:11.558828 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10958 23:21:11.558939
10959 23:21:11.579669 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10960 23:21:11.579776
10961 23:21:11.603338 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10962 23:21:11.603446
10963 23:21:11.623818 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10964 23:21:11.623948
10965 23:21:11.645443 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10966 23:21:11.645620
10967 23:21:11.666844 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10968 23:21:11.666988
10969 23:21:11.687451 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10970 23:21:11.687592
10971 23:21:11.701442 See 'systemctl status systemd-remount-fs.service' for details.
10972 23:21:11.701609
10973 23:21:11.722294 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10974 23:21:11.722438
10975 23:21:11.743215 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10976 23:21:11.743358
10977 23:21:11.793251 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10978 23:21:11.793399
10979 23:21:11.815750 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10980 23:21:11.815879
10981 23:21:11.838109 <46>[ 18.629367] systemd-journald[181]: Received client request to flush runtime journal.
10982 23:21:11.844591 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10983 23:21:11.844688
10984 23:21:11.870127 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10985 23:21:11.870267
10986 23:21:11.894352 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10987 23:21:11.894501
10988 23:21:11.918425 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10989 23:21:11.918557
10990 23:21:11.938330 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10991 23:21:11.938457
10992 23:21:11.958156 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10993 23:21:11.958294
10994 23:21:11.978003 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10995 23:21:11.978146
10996 23:21:11.996951 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10997 23:21:11.997081
10998 23:21:12.036709 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10999 23:21:12.036853
11000 23:21:12.059704 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11001 23:21:12.059866
11002 23:21:12.080710 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11003 23:21:12.080860
11004 23:21:12.096429 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11005 23:21:12.096574
11006 23:21:12.136843 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11007 23:21:12.137018
11008 23:21:12.161447 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11009 23:21:12.161632
11010 23:21:12.183726 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11011 23:21:12.183897
11012 23:21:12.201750 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11013 23:21:12.201898
11014 23:21:12.258199 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11015 23:21:12.258351
11016 23:21:12.285420 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11017 23:21:12.285566
11018 23:21:12.342860 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11019 23:21:12.343005
11020 23:21:12.363238 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11021 23:21:12.363378
11022 23:21:12.381857 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11023 23:21:12.381958
11024 23:21:12.496694 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11025 23:21:12.496844
11026 23:21:12.513879 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11027 23:21:12.514016
11028 23:21:12.533204 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11029 23:21:12.533314
11030 23:21:12.557868 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11031 23:21:12.557955
11032 23:21:12.577065 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11033 23:21:12.577184
11034 23:21:12.583291 <6>[ 19.376913] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11035 23:21:12.593402 <3>[ 19.379793] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11036 23:21:12.599991 <6>[ 19.384669] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11037 23:21:12.610033 <3>[ 19.392669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11038 23:21:12.619744 <6>[ 19.401446] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11039 23:21:12.626454 <3>[ 19.409512] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11040 23:21:12.633040 <4>[ 19.421209] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11041 23:21:12.643013 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11042 23:21:12.643107
11043 23:21:12.653644 <3>[ 19.444995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11044 23:21:12.660409 <4>[ 19.445036] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11045 23:21:12.666850 <6>[ 19.446868] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11046 23:21:12.676736 <6>[ 19.446883] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11047 23:21:12.683484 <3>[ 19.453612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11048 23:21:12.690201 <6>[ 19.466209] usbcore: registered new device driver r8152-cfgselector
11049 23:21:12.700186 <3>[ 19.467829] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11050 23:21:12.707092 <3>[ 19.467841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11051 23:21:12.714163 <3>[ 19.467846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11052 23:21:12.723891 <4>[ 19.468464] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11053 23:21:12.727387 <4>[ 19.468464] Fallback method does not support PEC.
11054 23:21:12.733814 <6>[ 19.469213] mc: Linux media interface: v0.10
11055 23:21:12.737276 <6>[ 19.481178] remoteproc remoteproc0: scp is available
11056 23:21:12.747281 <3>[ 19.493954] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11057 23:21:12.750795 <6>[ 19.498545] remoteproc remoteproc0: powering up scp
11058 23:21:12.761096 <3>[ 19.510114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11059 23:21:12.767751 <3>[ 19.511995] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11060 23:21:12.777790 <6>[ 19.514635] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11061 23:21:12.784361 <3>[ 19.528271] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11062 23:21:12.790868 <6>[ 19.532804] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11063 23:21:12.797797 <3>[ 19.537991] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11064 23:21:12.804214 <6>[ 19.549609] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11065 23:21:12.810782 <6>[ 19.556106] videodev: Linux video capture interface: v2.00
11066 23:21:12.821175 <3>[ 19.557597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11067 23:21:12.827298 <3>[ 19.557643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11068 23:21:12.837161 <3>[ 19.557654] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11069 23:21:12.843792 <3>[ 19.557667] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11070 23:21:12.850383 <3>[ 19.557675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11071 23:21:12.856786 <6>[ 19.559654] pci_bus 0000:00: root bus resource [bus 00-ff]
11072 23:21:12.867222 <6>[ 19.564773] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11073 23:21:12.873512 <3>[ 19.564956] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11074 23:21:12.886792 <6>[ 19.666928] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11075 23:21:12.893447 <6>[ 19.674987] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11076 23:21:12.900001 <6>[ 19.674991] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11077 23:21:12.909799 <6>[ 19.675001] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11078 23:21:12.916705 <6>[ 19.675045] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11079 23:21:12.923164 <6>[ 19.675067] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11080 23:21:12.932951 <3>[ 19.675078] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11081 23:21:12.936316 <6>[ 19.675185] pci 0000:00:00.0: supports D1 D2
11082 23:21:12.942694 <6>[ 19.675189] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11083 23:21:12.953957 <6>[ 19.676841] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11084 23:21:12.957021 <6>[ 19.676954] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11085 23:21:12.967260 <6>[ 19.676984] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11086 23:21:12.974092 <6>[ 19.677003] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11087 23:21:12.980477 <6>[ 19.677020] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11088 23:21:12.984031 <6>[ 19.677131] pci 0000:01:00.0: supports D1 D2
11089 23:21:12.990427 <6>[ 19.677133] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11090 23:21:13.000541 <6>[ 19.685004] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11091 23:21:13.007227 <6>[ 19.685010] remoteproc remoteproc0: remote processor scp is now up
11092 23:21:13.013958 <6>[ 19.687631] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11093 23:21:13.023646 <6>[ 19.687655] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11094 23:21:13.030252 <6>[ 19.687658] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11095 23:21:13.037154 <6>[ 19.687665] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11096 23:21:13.046859 <6>[ 19.687678] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11097 23:21:13.053603 <6>[ 19.687691] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11098 23:21:13.060199 <6>[ 19.687703] pci 0000:00:00.0: PCI bridge to [bus 01]
11099 23:21:13.066718 <6>[ 19.687708] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11100 23:21:13.073368 <6>[ 19.687842] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11101 23:21:13.079849 <6>[ 19.688342] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11102 23:21:13.086552 <6>[ 19.688793] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11103 23:21:13.093184 <3>[ 19.693456] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
11104 23:21:13.103420 <6>[ 19.700272] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11105 23:21:13.113154 <6>[ 19.723882] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11106 23:21:13.119914 <3>[ 19.753051] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11107 23:21:13.122940 <6>[ 19.766246] Bluetooth: Core ver 2.22
11108 23:21:13.129790 <6>[ 19.781805] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11109 23:21:13.136358 <6>[ 19.785200] NET: Registered PF_BLUETOOTH protocol family
11110 23:21:13.149424 <6>[ 19.795045] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11111 23:21:13.159533 <4>[ 19.797100] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11112 23:21:13.166768 <4>[ 19.797111] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11113 23:21:13.174015 <6>[ 19.800283] Bluetooth: HCI device and connection manager initialized
11114 23:21:13.177625 <6>[ 19.800305] Bluetooth: HCI socket layer initialized
11115 23:21:13.183879 <6>[ 19.800313] Bluetooth: L2CAP socket layer initialized
11116 23:21:13.187124 <6>[ 19.800341] Bluetooth: SCO socket layer initialized
11117 23:21:13.197011 <6>[ 19.801207] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11118 23:21:13.203946 <5>[ 19.802527] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11119 23:21:13.211361 <6>[ 19.807704] usbcore: registered new interface driver uvcvideo
11120 23:21:13.218072 <6>[ 19.813136] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11121 23:21:13.224641 <5>[ 19.815851] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11122 23:21:13.231153 <6>[ 19.824643] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11123 23:21:13.241144 <5>[ 19.830899] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11124 23:21:13.247723 <6>[ 19.859815] usbcore: registered new interface driver btusb
11125 23:21:13.254281 <4>[ 19.867546] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11126 23:21:13.264435 <4>[ 19.867682] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11127 23:21:13.271066 <3>[ 19.867706] Bluetooth: hci0: Failed to load firmware file (-2)
11128 23:21:13.277352 <3>[ 19.867712] Bluetooth: hci0: Failed to set up firmware (-2)
11129 23:21:13.287290 <4>[ 19.867721] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11130 23:21:13.290572 <6>[ 19.887633] r8152 2-1.3:1.0 eth0: v1.12.13
11131 23:21:13.297461 <6>[ 19.893625] cfg80211: failed to load regulatory.db
11132 23:21:13.304060 <6>[ 19.957448] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11133 23:21:13.310586 <6>[ 19.957958] usbcore: registered new interface driver r8152
11134 23:21:13.317281 <6>[ 19.965896] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11135 23:21:13.324114 <3>[ 19.966491] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11136 23:21:13.334501 <3>[ 19.967296] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
11137 23:21:13.344245 <3>[ 19.973313] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11138 23:21:13.350822 <6>[ 19.983147] usbcore: registered new interface driver cdc_ether
11139 23:21:13.354382 <6>[ 19.995564] mt7921e 0000:01:00.0: ASIC revision: 79610010
11140 23:21:13.360970 <6>[ 20.004516] usbcore: registered new interface driver r8153_ecm
11141 23:21:13.370741 <3>[ 20.010914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11142 23:21:13.377317 <6>[ 20.059151] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
11143 23:21:13.384151 <6>[ 20.104822] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11144 23:21:13.387110 <6>[ 20.104822]
11145 23:21:13.393864 <3>[ 20.129470] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11146 23:21:13.403825 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11147 23:21:13.403910
11148 23:21:13.424076 <3>[ 20.215800] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11149 23:21:13.430711 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11150 23:21:13.430795
11151 23:21:13.470467 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11152 23:21:13.470578
11153 23:21:13.499519 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11154 23:21:13.499624
11155 23:21:13.522965 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11156 23:21:13.523055
11157 23:21:13.541948 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11158 23:21:13.542036
11159 23:21:13.589991 [[0;32m OK [<46>[ 20.368239] systemd-journald[181]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.1 (1537 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
11160 23:21:13.606326 0m] Finished [0<46>[ 20.390893] systemd-journald[181]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11161 23:21:13.616249 <6>[ 20.392401] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11162 23:21:13.622769 ;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11163 23:21:13.622853
11164 23:21:13.694499 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11165 23:21:13.694629
11166 23:21:13.716971 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11167 23:21:13.717082
11168 23:21:13.737260 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11169 23:21:13.737414
11170 23:21:13.757269 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11171 23:21:13.757376
11172 23:21:13.810081 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11173 23:21:13.810342
11174 23:21:13.858230 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11175 23:21:13.858330
11176 23:21:13.877619 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11177 23:21:13.877717
11178 23:21:13.893178 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11179 23:21:13.893292
11180 23:21:13.913262 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11181 23:21:13.913463
11182 23:21:13.966591 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11183 23:21:13.966916
11184 23:21:13.992235 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11185 23:21:13.992595
11186 23:21:14.017313 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11187 23:21:14.017675
11188 23:21:14.087302 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11189 23:21:14.087756
11190 23:21:14.107052 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11191 23:21:14.107284
11192 23:21:14.132615 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11193 23:21:14.132706
11194 23:21:14.183779
11195 23:21:14.183919
11196 23:21:14.186943 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11197 23:21:14.187068
11198 23:21:14.190206 debian-bookworm-arm64 login: root (automatic login)
11199 23:21:14.190348
11200 23:21:14.190485
11201 23:21:14.207740 Linux debian-bookworm-arm64 6.1.83-cip18 #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024 aarch64
11202 23:21:14.208055
11203 23:21:14.214523 The programs included with the Debian GNU/Linux system are free software;
11204 23:21:14.220828 the exact distribution terms for each program are described in the
11205 23:21:14.224070 individual files in /usr/share/doc/*/copyright.
11206 23:21:14.224168
11207 23:21:14.230625 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11208 23:21:14.233949 permitted by applicable law.
11209 23:21:14.234454 Matched prompt #10: / #
11211 23:21:14.234794 Setting prompt string to ['/ #']
11212 23:21:14.234957 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11214 23:21:14.235328 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11215 23:21:14.235483 start: 2.2.6 expect-shell-connection (timeout 00:02:34) [common]
11216 23:21:14.235647 Setting prompt string to ['/ #']
11217 23:21:14.235792 Forcing a shell prompt, looking for ['/ #']
11219 23:21:14.286171 / #
11220 23:21:14.286418 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11221 23:21:14.286604 Waiting using forced prompt support (timeout 00:02:30)
11222 23:21:14.291120
11223 23:21:14.291522 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11224 23:21:14.291739 start: 2.2.7 export-device-env (timeout 00:02:34) [common]
11225 23:21:14.291963 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11226 23:21:14.292169 end: 2.2 depthcharge-retry (duration 00:02:26) [common]
11227 23:21:14.292378 end: 2 depthcharge-action (duration 00:02:26) [common]
11228 23:21:14.292601 start: 3 lava-test-retry (timeout 00:07:07) [common]
11229 23:21:14.292867 start: 3.1 lava-test-shell (timeout 00:07:07) [common]
11230 23:21:14.293105 Using namespace: common
11232 23:21:14.393791 / # #
11233 23:21:14.394417 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11234 23:21:14.399682 #
11235 23:21:14.400444 Using /lava-13248404
11237 23:21:14.501312 / # export SHELL=/bin/sh
11238 23:21:14.501571 export SHELL=/bin/sh<6>[ 21.275828] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11239 23:21:14.506510
11241 23:21:14.607030 / # . /lava-13248404/environment
11242 23:21:14.612478 . /lava-13248404/environment
11244 23:21:14.713010 / # /lava-13248404/bin/lava-test-runner /lava-13248404/0
11245 23:21:14.713152 Test shell timeout: 10s (minimum of the action and connection timeout)
11246 23:21:14.718297 /lava-13248404/bin/lava-test-runner /lava-13248404/0
11247 23:21:14.744062 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 21.537441] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 13248404_1.5.2.3.1>
11248 23:21:14.744324 Received signal: <STARTRUN> 0_igt-gpu-panfrost 13248404_1.5.2.3.1
11249 23:21:14.744396 Starting test lava.0_igt-gpu-panfrost (13248404_1.5.2.3.1)
11250 23:21:14.744480 Skipping test definition patterns.
11251 23:21:14.747392 nfrost
11252 23:21:14.750882 + cd /lava-13248404/0/tests/0_igt-gpu-panfrost
11253 23:21:14.750980 + cat uuid
11254 23:21:14.754319 + UUID=13248404_1.5.2.3.1
11255 23:21:14.754399 + set +x
11256 23:21:14.764109 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11257 23:21:14.779848 <8>[ 21.574975] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11258 23:21:14.780111 Received signal: <TESTSET> START panfrost_gem_new
11259 23:21:14.780184 Starting test_set panfrost_gem_new
11260 23:21:14.799569 <14>[ 21.594594] [IGT] panfrost_gem_new: executing
11261 23:21:14.806061 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 21.601901] [IGT] panfrost_gem_new: exiting, ret=77
11262 23:21:14.809568 h64) (Linux: 6.1.83-cip18 aarch64)
11263 23:21:14.822687 Using IGT_SRANDOM=1712186475 for randomisati<8>[ 21.613428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11264 23:21:14.822768 on
11265 23:21:14.823003 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11267 23:21:14.829242 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11268 23:21:14.832628 Test requirement: !(fd<0)
11269 23:21:14.839355 No known gpu found for chipset flags 0x32 (panf<14>[ 21.634970] [IGT] panfrost_gem_new: executing
11270 23:21:14.839437 rost)
11271 23:21:14.849195 Last errno: 2, No such fi<14>[ 21.642220] [IGT] panfrost_gem_new: exiting, ret=77
11272 23:21:14.849300 le or directory
11273 23:21:14.852560 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11274 23:21:14.859057 IG<8>[ 21.652540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11275 23:21:14.859308 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11277 23:21:14.865909 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11278 23:21:14.869196 Using IGT_SRANDOM=1712186475 for randomisation
11279 23:21:14.879049 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11280 23:21:14.879131 Test requirement: !(fd<0)
11281 23:21:14.885639 No known gpu found for chipset flags 0x32 (panfrost)
11282 23:21:14.888634 Last errno:<14>[ 21.685263] [IGT] panfrost_gem_new: executing
11283 23:21:14.892204 2, No such file or directory
11284 23:21:14.898572 [1mSubtest gem-n<14>[ 21.693470] [IGT] panfrost_gem_new: exiting, ret=77
11285 23:21:14.902022 ew-0: SKIP (0.000s)[0m
11286 23:21:14.908684 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11287 23:21:14.918746 Using IGT_SRANDOM=1<8>[ 21.707897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11288 23:21:14.918831 712186475 for randomisation
11289 23:21:14.919071 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11291 23:21:14.921824 Tes<8>[ 21.718276] <LAVA_SIGNAL_TESTSET STOP>
11292 23:21:14.922076 Received signal: <TESTSET> STOP
11293 23:21:14.922149 Closing test_set panfrost_gem_new
11294 23:21:14.928523 t requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11295 23:21:14.931920 Test requirement: !(fd<0)
11296 23:21:14.938570 No known gpu found for chipset flags 0x32 (panfrost)
11297 23:21:14.941613 Last errno: 2, No such file or directory
11298 23:21:14.944830 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11299 23:21:14.955759 <8>[ 21.750873] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11300 23:21:14.956012 Received signal: <TESTSET> START panfrost_get_param
11301 23:21:14.956101 Starting test_set panfrost_get_param
11302 23:21:14.975262 <14>[ 21.770388] [IGT] panfrost_get_param: executing
11303 23:21:14.982107 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 21.777722] [IGT] panfrost_get_param: exiting, ret=77
11304 23:21:14.985133 h64) (Linux: 6.1.83-cip18 aarch64)
11305 23:21:14.998631 Using IGT_SRANDOM=1712186475 for randomisati<8>[ 21.789097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11306 23:21:14.998813 on
11307 23:21:14.999151 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11309 23:21:15.005270 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11310 23:21:15.008560 Test requirement: !(fd<0)
11311 23:21:15.011734 No known gpu found for chipset flags 0x32 (panfrost)
11312 23:21:15.018694 Last errno: 2, No such fi<14>[ 21.812773] [IGT] panfrost_get_param: executing
11313 23:21:15.021928 le or directory
11314 23:21:15.028406 [1mSubtest bas<14>[ 21.821386] [IGT] panfrost_get_param: exiting, ret=77
11315 23:21:15.031799 e-params: SKIP (0.000s)[0m
11316 23:21:15.041695 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83<8>[ 21.833859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11317 23:21:15.042122 -cip18 aarch64)
11318 23:21:15.042893 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11320 23:21:15.048253 Using IGT_SRANDOM=1712186475 for randomisation
11321 23:21:15.054805 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11322 23:21:15.058132 Test requirement: !(fd<0)
11323 23:21:15.061356 No<14>[ 21.855554] [IGT] panfrost_get_param: executing
11324 23:21:15.071365 known gpu found for chipset fla<14>[ 21.863947] [IGT] panfrost_get_param: exiting, ret=77
11325 23:21:15.071927 gs 0x32 (panfrost)
11326 23:21:15.074800 Last errno: 2, No such file or directory
11327 23:21:15.084833 [1mSubtest get-ba<8>[ 21.875961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11328 23:21:15.085582 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11330 23:21:15.087994 d-param: SKIP (0<8>[ 21.885319] <LAVA_SIGNAL_TESTSET STOP>
11331 23:21:15.088823 Received signal: <TESTSET> STOP
11332 23:21:15.089258 Closing test_set panfrost_get_param
11333 23:21:15.091549 .000s)[0m
11334 23:21:15.098051 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11335 23:21:15.101522 Using IGT_SRANDOM=1712186475 for randomisation
11336 23:21:15.107871 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11337 23:21:15.111400 Test requirement: !(fd<0)
11338 23:21:15.114432 No known gpu found for chipset flags 0x32 (panfrost)
11339 23:21:15.121384 Received signal: <TESTSET> START panfrost_prime
11340 23:21:15.121852 Starting test_set panfrost_prime
11341 23:21:15.124470 Last errno: 2, No such file o<8>[ 21.916418] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11342 23:21:15.124971 r directory
11343 23:21:15.127647 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11344 23:21:15.150034 <14>[ 21.944652] [IGT] panfrost_prime: executing
11345 23:21:15.160006 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 21.952710] [IGT] panfrost_prime: exiting, ret=77
11346 23:21:15.160536 .83-cip18 aarch64)
11347 23:21:15.166551 Using IGT_SRANDOM=1712186475 for randomisation
11348 23:21:15.176269 Test requirement not met in function drm_open_driver, file .<8>[ 21.968979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11349 23:21:15.176555 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11351 23:21:15.179503 ./lib/drmtest.c:694:
11352 23:21:15.182630 Test requi<8>[ 21.979202] <LAVA_SIGNAL_TESTSET STOP>
11353 23:21:15.182904 Received signal: <TESTSET> STOP
11354 23:21:15.183001 Closing test_set panfrost_prime
11355 23:21:15.186343 rement: !(fd<0)
11356 23:21:15.189301 No known gpu found for chipset flags 0x32 (panfrost)
11357 23:21:15.192666 Last errno: 2, No such file or directory
11358 23:21:15.199120 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11359 23:21:15.215712 <8>[ 22.010866] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11360 23:21:15.215962 Received signal: <TESTSET> START panfrost_submit
11361 23:21:15.216033 Starting test_set panfrost_submit
11362 23:21:15.242523 <14>[ 22.037690] [IGT] panfrost_submit: executing
11363 23:21:15.252417 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 22.045742] [IGT] panfrost_submit: exiting, ret=77
11364 23:21:15.252508 .83-cip18 aarch64)
11365 23:21:15.259057 Using IGT_SRANDOM=1712186475 for randomisation
11366 23:21:15.269053 Test requirement not met in function drm_open_driver, file .<8>[ 22.062013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11367 23:21:15.269335 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11369 23:21:15.272593 ./lib/drmtest.c:694:
11370 23:21:15.272690 Test requirement: !(fd<0)
11371 23:21:15.279063 No known gpu found for chipset flags 0x32 (panfrost)
11372 23:21:15.282412 Last errno: 2, No such file or directory
11373 23:21:15.285603 [1mSubtest pan-submit: SKIP (0.000s)[0m
11374 23:21:15.298359 <14>[ 22.093585] [IGT] panfrost_submit: executing
11375 23:21:15.308322 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 22.101795] [IGT] panfrost_submit: exiting, ret=77
11376 23:21:15.308407 .83-cip18 aarch64)
11377 23:21:15.315082 Using IGT_SRANDOM=1712186475 for randomisation
11378 23:21:15.324782 Test requirement not met in <8>[ 22.114927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11379 23:21:15.325035 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11381 23:21:15.328359 function drm_open_driver, file ../lib/drmtest.c:694:
11382 23:21:15.331508 Test requirement: !(fd<0)
11383 23:21:15.334817 No known gpu found for chipset flags 0x32 (panfrost)
11384 23:21:15.338224 Last errno: 2, No such file or directory
11385 23:21:15.344925 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11386 23:21:15.353411 <14>[ 22.148369] [IGT] panfrost_submit: executing
11387 23:21:15.363162 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 22.156530] [IGT] panfrost_submit: exiting, ret=77
11388 23:21:15.363243 .83-cip18 aarch64)
11389 23:21:15.369732 Using IGT_SRANDOM=1712186476 for randomisation
11390 23:21:15.379645 Test requirement not met in function drm_ope<8>[ 22.171139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11391 23:21:15.379929 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11393 23:21:15.383303 n_driver, file ../lib/drmtest.c:694:
11394 23:21:15.386254 Test requirement: !(fd<0)
11395 23:21:15.389691 No known gpu found for chipset flags 0x32 (panfrost)
11396 23:21:15.396108 Last errno: 2, No such file or directory
11397 23:21:15.399660 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11398 23:21:15.408916 <14>[ 22.204010] [IGT] panfrost_submit: executing
11399 23:21:15.419080 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 22.212088] [IGT] panfrost_submit: exiting, ret=77
11400 23:21:15.419168 .83-cip18 aarch64)
11401 23:21:15.425423 Using IGT_SRANDOM=1712186476 for randomisation
11402 23:21:15.438559 Test requirement not met in function drm_open_driver, file .<8>[ 22.228472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11403 23:21:15.438642 ./lib/drmtest.c:694:
11404 23:21:15.438905 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11406 23:21:15.442041 Test requirement: !(fd<0)
11407 23:21:15.445454 No known gpu found for chipset flags 0x32 (panfrost)
11408 23:21:15.452150 Last errno: 2, No such file or directory
11409 23:21:15.455309 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11410 23:21:15.465927 <14>[ 22.261272] [IGT] panfrost_submit: executing
11411 23:21:15.475881 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 22.269380] [IGT] panfrost_submit: exiting, ret=77
11412 23:21:15.475993 .83-cip18 aarch64)
11413 23:21:15.482814 Using IGT_SRANDOM=1712186476 for randomisation
11414 23:21:15.496052 Test requirement not met in function drm_open_driver, file .<8>[ 22.286233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11415 23:21:15.496187 ./lib/drmtest.c:694:
11416 23:21:15.496429 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11418 23:21:15.499379 Test requirement: !(fd<0)
11419 23:21:15.505940 No known gpu found for chipset flags 0x32 (panfrost)
11420 23:21:15.509071 Last errno: 2, No such file or directory
11421 23:21:15.515582 [1mSubtest pan-submit-error-bad-requirements: <14>[ 22.312138] [IGT] panfrost_submit: executing
11422 23:21:15.519067 SKIP (0.000s)[0m
11423 23:21:15.525449 IGT-Version: <14>[ 22.319204] [IGT] panfrost_submit: exiting, ret=77
11424 23:21:15.528978 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11425 23:21:15.538869 Using IGT_SRANDOM=1712186<8>[ 22.331662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11426 23:21:15.539124 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11428 23:21:15.542349 476 for randomisation
11429 23:21:15.548792 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11430 23:21:15.552091 Test requirement: !(fd<0)
11431 23:21:15.555177 No known gpu found for chipset flags 0x32 (panfrost)
11432 23:21:15.558587 Last errno: 2, No such file or directory
11433 23:21:15.568338 [1mSubtest pan-submit-error-bad-out-sync: S<14>[ 22.363231] [IGT] panfrost_submit: executing
11434 23:21:15.568515 KIP (0.000s)[0m
11435 23:21:15.578509 IGT-Version: 1.28-ga44ebfe (aa<14>[ 22.372011] [IGT] panfrost_submit: exiting, ret=77
11436 23:21:15.581750 rch64) (Linux: 6.1.83-cip18 aarch64)
11437 23:21:15.585081 Using IGT_SRANDOM=1712186476 for randomisation
11438 23:21:15.595011 Test requirement not met in function drm_o<8>[ 22.387793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11439 23:21:15.595268 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11441 23:21:15.598429 pen_driver, file ../lib/drmtest.c:694:
11442 23:21:15.601806 Test requirement: !(fd<0)
11443 23:21:15.605037 No known gpu found for chipset flags 0x32 (panfrost)
11444 23:21:15.608274 Last errno: 2, No such file or directory
11445 23:21:15.618085 [1mSubtest pan-reset: SKIP (<14>[ 22.411068] [IGT] panfrost_submit: executing
11446 23:21:15.618166 0.000s)[0m
11447 23:21:15.624814 IGT-Version: 1.2<14>[ 22.419224] [IGT] panfrost_submit: exiting, ret=77
11448 23:21:15.628187 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11449 23:21:15.637965 Using IGT_SRANDOM=1712186476<8>[ 22.431112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11450 23:21:15.638220 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11452 23:21:15.641215 for randomisation
11453 23:21:15.647828 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11454 23:21:15.651362 Test requirement: !(fd<0)
11455 23:21:15.654433 No known gpu found for chipset flags 0x32 (panfrost)
11456 23:21:15.657719 Last errno: 2, No such file or directory
11457 23:21:15.667611 [1mSubtest pan-submit-and-close: SKIP (0.000s)<14>[ 22.462654] [IGT] panfrost_submit: executing
11458 23:21:15.667692 [0m
11459 23:21:15.677665 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 22.471028] [IGT] panfrost_submit: exiting, ret=77
11460 23:21:15.677749 .83-cip18 aarch64)
11461 23:21:15.684305 Using IGT_SRANDOM=1712186476 for randomisation
11462 23:21:15.694296 Test requirement not met in <8>[ 22.484693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11463 23:21:15.694552 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11465 23:21:15.700756 function drm_open_driver, file .<8>[ 22.496215] <LAVA_SIGNAL_TESTSET STOP>
11466 23:21:15.701042 Received signal: <TESTSET> STOP
11467 23:21:15.701144 Closing test_set panfrost_submit
11468 23:21:15.707575 ./lib/drmtest.c:<8>[ 22.501384] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 13248404_1.5.2.3.1>
11469 23:21:15.707656 694:
11470 23:21:15.707890 Received signal: <ENDRUN> 0_igt-gpu-panfrost 13248404_1.5.2.3.1
11471 23:21:15.707968 Ending use of test pattern.
11472 23:21:15.708027 Ending test lava.0_igt-gpu-panfrost (13248404_1.5.2.3.1), duration 0.96
11474 23:21:15.711166 Test requirement: !(fd<0)
11475 23:21:15.717565 No known gpu found for chipset flags 0x32 (panfrost)
11476 23:21:15.720691 Last errno: 2, No such file or directory
11477 23:21:15.723971 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11478 23:21:15.724050 + set +x
11479 23:21:15.727575 <LAVA_TEST_RUNNER EXIT>
11480 23:21:15.727825 ok: lava_test_shell seems to have completed
11481 23:21:15.728152 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11482 23:21:15.728274 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11483 23:21:15.728411 end: 3 lava-test-retry (duration 00:00:01) [common]
11484 23:21:15.728542 start: 4 finalize (timeout 00:07:05) [common]
11485 23:21:15.728676 start: 4.1 power-off (timeout 00:00:30) [common]
11486 23:21:15.728968 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11487 23:21:15.805374 >> Command sent successfully.
11488 23:21:15.807844 Returned 0 in 0 seconds
11489 23:21:15.908227 end: 4.1 power-off (duration 00:00:00) [common]
11491 23:21:15.908556 start: 4.2 read-feedback (timeout 00:07:05) [common]
11492 23:21:15.908821 Listened to connection for namespace 'common' for up to 1s
11493 23:21:16.909582 Finalising connection for namespace 'common'
11494 23:21:16.909753 Disconnecting from shell: Finalise
11495 23:21:16.909830 / #
11496 23:21:17.010150 end: 4.2 read-feedback (duration 00:00:01) [common]
11497 23:21:17.010432 end: 4 finalize (duration 00:00:01) [common]
11498 23:21:17.010551 Cleaning after the job
11499 23:21:17.010650 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/ramdisk
11500 23:21:17.019799 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/kernel
11501 23:21:17.029297 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/dtb
11502 23:21:17.029471 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248404/tftp-deploy-19eirvby/modules
11503 23:21:17.037239 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248404
11504 23:21:17.172275 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248404
11505 23:21:17.172479 Job finished correctly