Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 23
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
1 23:24:24.791589 lava-dispatcher, installed at version: 2024.01
2 23:24:24.791814 start: 0 validate
3 23:24:24.791954 Start time: 2024-04-03 23:24:24.791946+00:00 (UTC)
4 23:24:24.792085 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:24:24.792275 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:24:25.050535 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:24:25.050746 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:24:25.307709 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:24:25.307950 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:24:25.556569 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:24:25.556821 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:24:25.815827 validate duration: 1.02
14 23:24:25.816196 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:24:25.816358 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:24:25.816493 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:24:25.816667 Not decompressing ramdisk as can be used compressed.
18 23:24:25.816792 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 23:24:25.816874 saving as /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/ramdisk/rootfs.cpio.gz
20 23:24:25.816980 total size: 47897469 (45 MB)
21 23:24:25.818417 progress 0 % (0 MB)
22 23:24:25.832534 progress 5 % (2 MB)
23 23:24:25.848931 progress 10 % (4 MB)
24 23:24:25.867461 progress 15 % (6 MB)
25 23:24:25.885269 progress 20 % (9 MB)
26 23:24:25.899203 progress 25 % (11 MB)
27 23:24:25.911882 progress 30 % (13 MB)
28 23:24:25.924547 progress 35 % (16 MB)
29 23:24:25.937222 progress 40 % (18 MB)
30 23:24:25.950270 progress 45 % (20 MB)
31 23:24:25.963411 progress 50 % (22 MB)
32 23:24:25.976884 progress 55 % (25 MB)
33 23:24:25.990556 progress 60 % (27 MB)
34 23:24:26.003965 progress 65 % (29 MB)
35 23:24:26.017498 progress 70 % (32 MB)
36 23:24:26.030816 progress 75 % (34 MB)
37 23:24:26.044057 progress 80 % (36 MB)
38 23:24:26.057288 progress 85 % (38 MB)
39 23:24:26.070794 progress 90 % (41 MB)
40 23:24:26.084405 progress 95 % (43 MB)
41 23:24:26.097752 progress 100 % (45 MB)
42 23:24:26.098022 45 MB downloaded in 0.28 s (162.53 MB/s)
43 23:24:26.098201 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:24:26.098455 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:24:26.098550 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:24:26.098645 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:24:26.098786 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:24:26.098857 saving as /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/kernel/Image
50 23:24:26.098922 total size: 54286848 (51 MB)
51 23:24:26.098986 No compression specified
52 23:24:26.100341 progress 0 % (0 MB)
53 23:24:26.116036 progress 5 % (2 MB)
54 23:24:26.130713 progress 10 % (5 MB)
55 23:24:26.145156 progress 15 % (7 MB)
56 23:24:26.159861 progress 20 % (10 MB)
57 23:24:26.174406 progress 25 % (12 MB)
58 23:24:26.188920 progress 30 % (15 MB)
59 23:24:26.203322 progress 35 % (18 MB)
60 23:24:26.218315 progress 40 % (20 MB)
61 23:24:26.233607 progress 45 % (23 MB)
62 23:24:26.248255 progress 50 % (25 MB)
63 23:24:26.263985 progress 55 % (28 MB)
64 23:24:26.279411 progress 60 % (31 MB)
65 23:24:26.297950 progress 65 % (33 MB)
66 23:24:26.318332 progress 70 % (36 MB)
67 23:24:26.333863 progress 75 % (38 MB)
68 23:24:26.352680 progress 80 % (41 MB)
69 23:24:26.367602 progress 85 % (44 MB)
70 23:24:26.382288 progress 90 % (46 MB)
71 23:24:26.396765 progress 95 % (49 MB)
72 23:24:26.414689 progress 100 % (51 MB)
73 23:24:26.415047 51 MB downloaded in 0.32 s (163.77 MB/s)
74 23:24:26.415291 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:24:26.415719 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:24:26.415869 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:24:26.416028 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:24:26.416236 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:24:26.416359 saving as /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/dtb/mt8192-asurada-spherion-r0.dtb
81 23:24:26.416465 total size: 47230 (0 MB)
82 23:24:26.416579 No compression specified
83 23:24:26.418359 progress 69 % (0 MB)
84 23:24:26.418760 progress 100 % (0 MB)
85 23:24:26.419002 0 MB downloaded in 0.00 s (17.78 MB/s)
86 23:24:26.419209 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:24:26.419624 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:24:26.419773 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:24:26.419912 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:24:26.420096 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:24:26.420214 saving as /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/modules/modules.tar
93 23:24:26.420330 total size: 8629908 (8 MB)
94 23:24:26.420441 Using unxz to decompress xz
95 23:24:26.426077 progress 0 % (0 MB)
96 23:24:26.445530 progress 5 % (0 MB)
97 23:24:26.471845 progress 10 % (0 MB)
98 23:24:26.506068 progress 15 % (1 MB)
99 23:24:26.530678 progress 20 % (1 MB)
100 23:24:26.556008 progress 25 % (2 MB)
101 23:24:26.582435 progress 30 % (2 MB)
102 23:24:26.607151 progress 35 % (2 MB)
103 23:24:26.634650 progress 40 % (3 MB)
104 23:24:26.665198 progress 45 % (3 MB)
105 23:24:26.694842 progress 50 % (4 MB)
106 23:24:26.722759 progress 55 % (4 MB)
107 23:24:26.761915 progress 60 % (4 MB)
108 23:24:26.792644 progress 65 % (5 MB)
109 23:24:26.823404 progress 70 % (5 MB)
110 23:24:26.851436 progress 75 % (6 MB)
111 23:24:26.878578 progress 80 % (6 MB)
112 23:24:26.907792 progress 85 % (7 MB)
113 23:24:26.937403 progress 90 % (7 MB)
114 23:24:26.967484 progress 95 % (7 MB)
115 23:24:26.994688 progress 100 % (8 MB)
116 23:24:27.000819 8 MB downloaded in 0.58 s (14.18 MB/s)
117 23:24:27.001204 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:24:27.001636 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:24:27.001780 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:24:27.001933 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:24:27.002064 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:24:27.002204 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:24:27.002526 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7
125 23:24:27.002742 makedir: /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin
126 23:24:27.002900 makedir: /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/tests
127 23:24:27.003056 makedir: /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/results
128 23:24:27.003232 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-add-keys
129 23:24:27.003449 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-add-sources
130 23:24:27.003651 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-background-process-start
131 23:24:27.003850 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-background-process-stop
132 23:24:27.004045 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-common-functions
133 23:24:27.004247 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-echo-ipv4
134 23:24:27.004454 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-install-packages
135 23:24:27.004650 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-installed-packages
136 23:24:27.004844 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-os-build
137 23:24:27.005043 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-probe-channel
138 23:24:27.005239 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-probe-ip
139 23:24:27.005434 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-target-ip
140 23:24:27.005628 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-target-mac
141 23:24:27.005819 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-target-storage
142 23:24:27.006041 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-test-case
143 23:24:27.006238 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-test-event
144 23:24:27.006442 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-test-feedback
145 23:24:27.006628 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-test-raise
146 23:24:27.006859 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-test-reference
147 23:24:27.007050 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-test-runner
148 23:24:27.007242 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-test-set
149 23:24:27.007434 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-test-shell
150 23:24:27.007633 Updating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-install-packages (oe)
151 23:24:27.007859 Updating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/bin/lava-installed-packages (oe)
152 23:24:27.008046 Creating /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/environment
153 23:24:27.008199 LAVA metadata
154 23:24:27.008349 - LAVA_JOB_ID=13248445
155 23:24:27.008486 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:24:27.008688 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:24:27.008817 skipped lava-vland-overlay
158 23:24:27.008964 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:24:27.009092 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:24:27.009199 skipped lava-multinode-overlay
161 23:24:27.009320 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:24:27.009452 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:24:27.009572 Loading test definitions
164 23:24:27.009717 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:24:27.009850 Using /lava-13248445 at stage 0
166 23:24:27.010415 uuid=13248445_1.5.2.3.1 testdef=None
167 23:24:27.010557 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:24:27.010689 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:24:27.011561 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:24:27.011927 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:24:27.013010 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:24:27.013487 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:24:27.014596 runner path: /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/0/tests/0_igt-kms-mediatek test_uuid 13248445_1.5.2.3.1
176 23:24:27.014821 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:24:27.015159 Creating lava-test-runner.conf files
179 23:24:27.015257 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248445/lava-overlay-ig14vem7/lava-13248445/0 for stage 0
180 23:24:27.015399 - 0_igt-kms-mediatek
181 23:24:27.015552 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:24:27.015688 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:24:27.027177 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:24:27.027361 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:24:27.027555 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:24:27.027711 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:24:27.027895 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:24:29.055435 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 23:24:29.055906 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 23:24:29.056087 extracting modules file /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248445/extract-overlay-ramdisk-252doayp/ramdisk
191 23:24:29.356436 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:24:29.356631 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
193 23:24:29.356732 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248445/compress-overlay-r9uflt6y/overlay-1.5.2.4.tar.gz to ramdisk
194 23:24:29.356809 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248445/compress-overlay-r9uflt6y/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248445/extract-overlay-ramdisk-252doayp/ramdisk
195 23:24:29.363474 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:24:29.363589 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
197 23:24:29.363682 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:24:29.363771 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
199 23:24:29.363849 Building ramdisk /var/lib/lava/dispatcher/tmp/13248445/extract-overlay-ramdisk-252doayp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248445/extract-overlay-ramdisk-252doayp/ramdisk
200 23:24:30.763232 >> 466177 blocks
201 23:24:37.478202 rename /var/lib/lava/dispatcher/tmp/13248445/extract-overlay-ramdisk-252doayp/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/ramdisk/ramdisk.cpio.gz
202 23:24:37.478672 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 23:24:37.478796 start: 1.5.8 prepare-kernel (timeout 00:09:48) [common]
204 23:24:37.478902 start: 1.5.8.1 prepare-fit (timeout 00:09:48) [common]
205 23:24:37.479015 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/kernel/Image'
206 23:24:52.600072 Returned 0 in 15 seconds
207 23:24:52.700736 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/kernel/image.itb
208 23:24:53.690055 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:24:53.690452 output: Created: Thu Apr 4 00:24:53 2024
210 23:24:53.690567 output: Image 0 (kernel-1)
211 23:24:53.690639 output: Description:
212 23:24:53.690706 output: Created: Thu Apr 4 00:24:53 2024
213 23:24:53.690807 output: Type: Kernel Image
214 23:24:53.690906 output: Compression: lzma compressed
215 23:24:53.690997 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
216 23:24:53.691084 output: Architecture: AArch64
217 23:24:53.691177 output: OS: Linux
218 23:24:53.691269 output: Load Address: 0x00000000
219 23:24:53.691349 output: Entry Point: 0x00000000
220 23:24:53.691450 output: Hash algo: crc32
221 23:24:53.691547 output: Hash value: d7c9dcc1
222 23:24:53.691636 output: Image 1 (fdt-1)
223 23:24:53.691732 output: Description: mt8192-asurada-spherion-r0
224 23:24:53.691826 output: Created: Thu Apr 4 00:24:53 2024
225 23:24:53.691918 output: Type: Flat Device Tree
226 23:24:53.691999 output: Compression: uncompressed
227 23:24:53.692094 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 23:24:53.692184 output: Architecture: AArch64
229 23:24:53.692269 output: Hash algo: crc32
230 23:24:53.692365 output: Hash value: 4bf0d1ac
231 23:24:53.692456 output: Image 2 (ramdisk-1)
232 23:24:53.692550 output: Description: unavailable
233 23:24:53.692631 output: Created: Thu Apr 4 00:24:53 2024
234 23:24:53.692723 output: Type: RAMDisk Image
235 23:24:53.692811 output: Compression: Unknown Compression
236 23:24:53.692898 output: Data Size: 61050210 Bytes = 59619.35 KiB = 58.22 MiB
237 23:24:53.692979 output: Architecture: AArch64
238 23:24:53.693075 output: OS: Linux
239 23:24:53.693164 output: Load Address: unavailable
240 23:24:53.693249 output: Entry Point: unavailable
241 23:24:53.693333 output: Hash algo: crc32
242 23:24:53.693424 output: Hash value: 49e76a41
243 23:24:53.693516 output: Default Configuration: 'conf-1'
244 23:24:53.693597 output: Configuration 0 (conf-1)
245 23:24:53.693680 output: Description: mt8192-asurada-spherion-r0
246 23:24:53.693741 output: Kernel: kernel-1
247 23:24:53.693818 output: Init Ramdisk: ramdisk-1
248 23:24:53.693905 output: FDT: fdt-1
249 23:24:53.693993 output: Loadables: kernel-1
250 23:24:53.694072 output:
251 23:24:53.694336 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 23:24:53.694481 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 23:24:53.694638 end: 1.5 prepare-tftp-overlay (duration 00:00:27) [common]
254 23:24:53.694773 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:32) [common]
255 23:24:53.694895 No LXC device requested
256 23:24:53.695020 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:24:53.695147 start: 1.7 deploy-device-env (timeout 00:09:32) [common]
258 23:24:53.695265 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:24:53.695371 Checking files for TFTP limit of 4294967296 bytes.
260 23:24:53.696054 end: 1 tftp-deploy (duration 00:00:28) [common]
261 23:24:53.696197 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:24:53.696339 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:24:53.696514 substitutions:
264 23:24:53.696619 - {DTB}: 13248445/tftp-deploy-wwg_t9yx/dtb/mt8192-asurada-spherion-r0.dtb
265 23:24:53.696715 - {INITRD}: 13248445/tftp-deploy-wwg_t9yx/ramdisk/ramdisk.cpio.gz
266 23:24:53.696811 - {KERNEL}: 13248445/tftp-deploy-wwg_t9yx/kernel/Image
267 23:24:53.696904 - {LAVA_MAC}: None
268 23:24:53.696995 - {PRESEED_CONFIG}: None
269 23:24:53.697079 - {PRESEED_LOCAL}: None
270 23:24:53.697180 - {RAMDISK}: 13248445/tftp-deploy-wwg_t9yx/ramdisk/ramdisk.cpio.gz
271 23:24:53.697276 - {ROOT_PART}: None
272 23:24:53.697359 - {ROOT}: None
273 23:24:53.697450 - {SERVER_IP}: 192.168.201.1
274 23:24:53.697522 - {TEE}: None
275 23:24:53.697622 Parsed boot commands:
276 23:24:53.697715 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:24:53.697959 Parsed boot commands: tftpboot 192.168.201.1 13248445/tftp-deploy-wwg_t9yx/kernel/image.itb 13248445/tftp-deploy-wwg_t9yx/kernel/cmdline
278 23:24:53.698101 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:24:53.698239 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:24:53.698377 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:24:53.698497 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:24:53.698592 Not connected, no need to disconnect.
283 23:24:53.698704 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:24:53.698822 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:24:53.698921 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 23:24:53.703204 Setting prompt string to ['lava-test: # ']
287 23:24:53.703590 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:24:53.703704 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:24:53.703811 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:24:53.703917 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:24:53.704143 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 23:24:58.834747 >> Command sent successfully.
293 23:24:58.837617 Returned 0 in 5 seconds
294 23:24:58.938088 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:24:58.938634 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:24:58.938828 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:24:58.939011 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:24:58.939158 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:24:58.939309 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:24:58.939736 [Enter `^Ec?' for help]
302 23:24:59.111029
303 23:24:59.111168
304 23:24:59.111240 F0: 102B 0000
305 23:24:59.111306
306 23:24:59.111391 F3: 1001 0000 [0200]
307 23:24:59.114277
308 23:24:59.114377 F3: 1001 0000
309 23:24:59.114475
310 23:24:59.114539 F7: 102D 0000
311 23:24:59.114629
312 23:24:59.117688 F1: 0000 0000
313 23:24:59.117788
314 23:24:59.117886 V0: 0000 0000 [0001]
315 23:24:59.117980
316 23:24:59.120777 00: 0007 8000
317 23:24:59.120864
318 23:24:59.120947 01: 0000 0000
319 23:24:59.121023
320 23:24:59.124263 BP: 0C00 0209 [0000]
321 23:24:59.124372
322 23:24:59.124475 G0: 1182 0000
323 23:24:59.124538
324 23:24:59.124597 EC: 0000 0021 [4000]
325 23:24:59.128192
326 23:24:59.128274 S7: 0000 0000 [0000]
327 23:24:59.128390
328 23:24:59.131482 CC: 0000 0000 [0001]
329 23:24:59.131565
330 23:24:59.131658 T0: 0000 0040 [010F]
331 23:24:59.131720
332 23:24:59.131779 Jump to BL
333 23:24:59.131837
334 23:24:59.158226
335 23:24:59.158369
336 23:24:59.158480
337 23:24:59.165575 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:24:59.169054 ARM64: Exception handlers installed.
339 23:24:59.172472 ARM64: Testing exception
340 23:24:59.175523 ARM64: Done test exception
341 23:24:59.182315 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:24:59.192831 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:24:59.199707 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:24:59.209599 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:24:59.216159 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:24:59.222679 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:24:59.235096 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:24:59.241473 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:24:59.260550 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:24:59.263916 WDT: Last reset was cold boot
351 23:24:59.267245 SPI1(PAD0) initialized at 2873684 Hz
352 23:24:59.270713 SPI5(PAD0) initialized at 992727 Hz
353 23:24:59.273813 VBOOT: Loading verstage.
354 23:24:59.280584 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:24:59.284095 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:24:59.287034 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:24:59.290392 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:24:59.298221 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:24:59.304516 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:24:59.315920 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 23:24:59.316008
362 23:24:59.316096
363 23:24:59.326503 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:24:59.329658 ARM64: Exception handlers installed.
365 23:24:59.329746 ARM64: Testing exception
366 23:24:59.332784 ARM64: Done test exception
367 23:24:59.336237 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:24:59.343149 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:24:59.356496 Probing TPM: . done!
370 23:24:59.356584 TPM ready after 0 ms
371 23:24:59.363536 Connected to device vid:did:rid of 1ae0:0028:00
372 23:24:59.370514 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 23:24:59.429550 Initialized TPM device CR50 revision 0
374 23:24:59.441337 tlcl_send_startup: Startup return code is 0
375 23:24:59.441508 TPM: setup succeeded
376 23:24:59.452907 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:24:59.461569 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:24:59.475524 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:24:59.482320 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:24:59.486248 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:24:59.489292 in-header: 03 07 00 00 08 00 00 00
382 23:24:59.493108 in-data: aa e4 47 04 13 02 00 00
383 23:24:59.496570 Chrome EC: UHEPI supported
384 23:24:59.500707 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:24:59.505002 in-header: 03 95 00 00 08 00 00 00
386 23:24:59.508456 in-data: 18 20 20 08 00 00 00 00
387 23:24:59.508583 Phase 1
388 23:24:59.511943 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:24:59.519035 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:24:59.526451 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:24:59.530206 Recovery requested (1009000e)
392 23:24:59.539793 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:24:59.543778 tlcl_extend: response is 0
394 23:24:59.554256 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:24:59.558128 tlcl_extend: response is 0
396 23:24:59.565041 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:24:59.584592 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 23:24:59.591471 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:24:59.591600
400 23:24:59.591720
401 23:24:59.601283 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:24:59.604587 ARM64: Exception handlers installed.
403 23:24:59.608006 ARM64: Testing exception
404 23:24:59.608113 ARM64: Done test exception
405 23:24:59.630371 pmic_efuse_setting: Set efuses in 11 msecs
406 23:24:59.633496 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:24:59.640322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:24:59.643317 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:24:59.650893 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:24:59.654428 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:24:59.658255 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:24:59.662097 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:24:59.669259 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:24:59.672988 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:24:59.676708 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:24:59.684250 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:24:59.688045 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:24:59.691818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:24:59.695510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:24:59.703085 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:24:59.710510 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:24:59.713863 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:24:59.721344 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:24:59.725134 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:24:59.732670 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:24:59.736313 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:24:59.743585 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:24:59.747482 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:24:59.755097 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:24:59.758601 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:24:59.762683 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:24:59.770185 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:24:59.773577 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:24:59.781215 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:24:59.784768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:24:59.788149 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:24:59.795588 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:24:59.799323 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:24:59.803396 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:24:59.810645 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:24:59.814088 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:24:59.818003 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:24:59.825563 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:24:59.829534 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:24:59.833040 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:24:59.836954 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:24:59.844110 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:24:59.848022 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:24:59.851427 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:24:59.855305 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:24:59.858796 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:24:59.862647 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:24:59.870176 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:24:59.873748 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:24:59.877670 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:24:59.880992 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:24:59.885162 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:24:59.892277 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:24:59.899780 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:24:59.907333 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:24:59.914529 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:24:59.922010 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:24:59.928878 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:24:59.932538 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:24:59.936033 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:24:59.943422 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x23
467 23:24:59.950502 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:24:59.954647 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 23:24:59.957669 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:24:59.967882 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 23:25:00.035154 [RTC]rtc_get_frequency_meter,154: input=23, output=940
472 23:25:00.036478 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 23:25:00.036611 [RTC]rtc_get_frequency_meter,154: input=17, output=802
474 23:25:00.036718 [RTC]rtc_get_frequency_meter,154: input=16, output=781
475 23:25:00.036818 [RTC]rtc_get_frequency_meter,154: input=16, output=781
476 23:25:00.036919 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 23:25:00.037035 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 23:25:00.037130 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 23:25:00.039760 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:25:00.043990 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 23:25:00.047448 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:25:00.051174 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 23:25:00.054976 ADC[4]: Raw value=905465 ID=7
484 23:25:00.055091 ADC[3]: Raw value=213441 ID=1
485 23:25:00.058924 RAM Code: 0x71
486 23:25:00.062460 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:25:00.066207 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:25:00.077238 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 23:25:00.081222 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 23:25:00.084429 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:25:00.089207 in-header: 03 07 00 00 08 00 00 00
492 23:25:00.092708 in-data: aa e4 47 04 13 02 00 00
493 23:25:00.096472 Chrome EC: UHEPI supported
494 23:25:00.103814 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:25:00.107147 in-header: 03 95 00 00 08 00 00 00
496 23:25:00.110856 in-data: 18 20 20 08 00 00 00 00
497 23:25:00.110981 MRC: failed to locate region type 0.
498 23:25:00.118086 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:25:00.122234 DRAM-K: Running full calibration
500 23:25:00.129437 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 23:25:00.129625 header.status = 0x0
502 23:25:00.133367 header.version = 0x6 (expected: 0x6)
503 23:25:00.136693 header.size = 0xd00 (expected: 0xd00)
504 23:25:00.136845 header.flags = 0x0
505 23:25:00.143551 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:25:00.163108 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 23:25:00.170371 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:25:00.170482 dram_init: ddr_geometry: 2
509 23:25:00.174023 [EMI] MDL number = 2
510 23:25:00.178027 [EMI] Get MDL freq = 0
511 23:25:00.178110 dram_init: ddr_type: 0
512 23:25:00.181623 is_discrete_lpddr4: 1
513 23:25:00.181707 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:25:00.185491
515 23:25:00.185588
516 23:25:00.185656 [Bian_co] ETT version 0.0.0.1
517 23:25:00.189353 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 23:25:00.189441
519 23:25:00.196689 dramc_set_vcore_voltage set vcore to 650000
520 23:25:00.196778 Read voltage for 800, 4
521 23:25:00.196846 Vio18 = 0
522 23:25:00.200701 Vcore = 650000
523 23:25:00.200807 Vdram = 0
524 23:25:00.200909 Vddq = 0
525 23:25:00.201004 Vmddr = 0
526 23:25:00.204203 dram_init: config_dvfs: 1
527 23:25:00.208167 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:25:00.215577 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:25:00.219564 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 23:25:00.223180 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 23:25:00.227256 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 23:25:00.230737 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 23:25:00.230843 MEM_TYPE=3, freq_sel=18
534 23:25:00.234183 sv_algorithm_assistance_LP4_1600
535 23:25:00.240946 ============ PULL DRAM RESETB DOWN ============
536 23:25:00.244079 ========== PULL DRAM RESETB DOWN end =========
537 23:25:00.247445 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:25:00.250756 ===================================
539 23:25:00.254457 LPDDR4 DRAM CONFIGURATION
540 23:25:00.258170 ===================================
541 23:25:00.258296 EX_ROW_EN[0] = 0x0
542 23:25:00.262055 EX_ROW_EN[1] = 0x0
543 23:25:00.262192 LP4Y_EN = 0x0
544 23:25:00.265600 WORK_FSP = 0x0
545 23:25:00.265725 WL = 0x2
546 23:25:00.269430 RL = 0x2
547 23:25:00.269542 BL = 0x2
548 23:25:00.273250 RPST = 0x0
549 23:25:00.273368 RD_PRE = 0x0
550 23:25:00.276374 WR_PRE = 0x1
551 23:25:00.276493 WR_PST = 0x0
552 23:25:00.279694 DBI_WR = 0x0
553 23:25:00.279838 DBI_RD = 0x0
554 23:25:00.283354 OTF = 0x1
555 23:25:00.286479 ===================================
556 23:25:00.289634 ===================================
557 23:25:00.289797 ANA top config
558 23:25:00.292940 ===================================
559 23:25:00.296386 DLL_ASYNC_EN = 0
560 23:25:00.299877 ALL_SLAVE_EN = 1
561 23:25:00.300038 NEW_RANK_MODE = 1
562 23:25:00.302954 DLL_IDLE_MODE = 1
563 23:25:00.306396 LP45_APHY_COMB_EN = 1
564 23:25:00.309835 TX_ODT_DIS = 1
565 23:25:00.309954 NEW_8X_MODE = 1
566 23:25:00.313230 ===================================
567 23:25:00.317031 ===================================
568 23:25:00.320112 data_rate = 1600
569 23:25:00.323543 CKR = 1
570 23:25:00.326941 DQ_P2S_RATIO = 8
571 23:25:00.330320 ===================================
572 23:25:00.333418 CA_P2S_RATIO = 8
573 23:25:00.333528 DQ_CA_OPEN = 0
574 23:25:00.336735 DQ_SEMI_OPEN = 0
575 23:25:00.339938 CA_SEMI_OPEN = 0
576 23:25:00.343505 CA_FULL_RATE = 0
577 23:25:00.346874 DQ_CKDIV4_EN = 1
578 23:25:00.350331 CA_CKDIV4_EN = 1
579 23:25:00.350421 CA_PREDIV_EN = 0
580 23:25:00.353448 PH8_DLY = 0
581 23:25:00.356960 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:25:00.360187 DQ_AAMCK_DIV = 4
583 23:25:00.363630 CA_AAMCK_DIV = 4
584 23:25:00.366743 CA_ADMCK_DIV = 4
585 23:25:00.366832 DQ_TRACK_CA_EN = 0
586 23:25:00.370401 CA_PICK = 800
587 23:25:00.373527 CA_MCKIO = 800
588 23:25:00.377254 MCKIO_SEMI = 0
589 23:25:00.381107 PLL_FREQ = 3068
590 23:25:00.381189 DQ_UI_PI_RATIO = 32
591 23:25:00.384551 CA_UI_PI_RATIO = 0
592 23:25:00.388535 ===================================
593 23:25:00.392272 ===================================
594 23:25:00.395919 memory_type:LPDDR4
595 23:25:00.396053 GP_NUM : 10
596 23:25:00.400080 SRAM_EN : 1
597 23:25:00.400209 MD32_EN : 0
598 23:25:00.404082 ===================================
599 23:25:00.407514 [ANA_INIT] >>>>>>>>>>>>>>
600 23:25:00.407606 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:25:00.411489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:25:00.414953 ===================================
603 23:25:00.417920 data_rate = 1600,PCW = 0X7600
604 23:25:00.421449 ===================================
605 23:25:00.424959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:25:00.431764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:25:00.434856 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:25:00.441352 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:25:00.444865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:25:00.448272 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:25:00.448414 [ANA_INIT] flow start
612 23:25:00.451718 [ANA_INIT] PLL >>>>>>>>
613 23:25:00.455066 [ANA_INIT] PLL <<<<<<<<
614 23:25:00.457899 [ANA_INIT] MIDPI >>>>>>>>
615 23:25:00.458022 [ANA_INIT] MIDPI <<<<<<<<
616 23:25:00.461578 [ANA_INIT] DLL >>>>>>>>
617 23:25:00.464892 [ANA_INIT] flow end
618 23:25:00.468127 ============ LP4 DIFF to SE enter ============
619 23:25:00.471513 ============ LP4 DIFF to SE exit ============
620 23:25:00.474795 [ANA_INIT] <<<<<<<<<<<<<
621 23:25:00.477968 [Flow] Enable top DCM control >>>>>
622 23:25:00.481269 [Flow] Enable top DCM control <<<<<
623 23:25:00.484775 Enable DLL master slave shuffle
624 23:25:00.488079 ==============================================================
625 23:25:00.491386 Gating Mode config
626 23:25:00.494733 ==============================================================
627 23:25:00.498179 Config description:
628 23:25:00.507950 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:25:00.514748 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:25:00.517898 SELPH_MODE 0: By rank 1: By Phase
631 23:25:00.524707 ==============================================================
632 23:25:00.528121 GAT_TRACK_EN = 1
633 23:25:00.531560 RX_GATING_MODE = 2
634 23:25:00.534949 RX_GATING_TRACK_MODE = 2
635 23:25:00.538362 SELPH_MODE = 1
636 23:25:00.538450 PICG_EARLY_EN = 1
637 23:25:00.541583 VALID_LAT_VALUE = 1
638 23:25:00.548331 ==============================================================
639 23:25:00.551446 Enter into Gating configuration >>>>
640 23:25:00.554894 Exit from Gating configuration <<<<
641 23:25:00.557988 Enter into DVFS_PRE_config >>>>>
642 23:25:00.568238 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:25:00.571726 Exit from DVFS_PRE_config <<<<<
644 23:25:00.575136 Enter into PICG configuration >>>>
645 23:25:00.578246 Exit from PICG configuration <<<<
646 23:25:00.581572 [RX_INPUT] configuration >>>>>
647 23:25:00.584975 [RX_INPUT] configuration <<<<<
648 23:25:00.588426 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:25:00.594911 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:25:00.601474 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:25:00.608028 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:25:00.611444 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:25:00.618277 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:25:00.621551 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:25:00.628094 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:25:00.631514 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:25:00.634999 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:25:00.638114 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:25:00.644973 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:25:00.648245 ===================================
661 23:25:00.648348 LPDDR4 DRAM CONFIGURATION
662 23:25:00.651827 ===================================
663 23:25:00.655276 EX_ROW_EN[0] = 0x0
664 23:25:00.658655 EX_ROW_EN[1] = 0x0
665 23:25:00.658740 LP4Y_EN = 0x0
666 23:25:00.661651 WORK_FSP = 0x0
667 23:25:00.661736 WL = 0x2
668 23:25:00.665165 RL = 0x2
669 23:25:00.665250 BL = 0x2
670 23:25:00.668492 RPST = 0x0
671 23:25:00.668577 RD_PRE = 0x0
672 23:25:00.671750 WR_PRE = 0x1
673 23:25:00.671835 WR_PST = 0x0
674 23:25:00.674988 DBI_WR = 0x0
675 23:25:00.675073 DBI_RD = 0x0
676 23:25:00.678440 OTF = 0x1
677 23:25:00.681678 ===================================
678 23:25:00.685140 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:25:00.688540 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:25:00.695400 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:25:00.698894 ===================================
682 23:25:00.699002 LPDDR4 DRAM CONFIGURATION
683 23:25:00.701966 ===================================
684 23:25:00.705344 EX_ROW_EN[0] = 0x10
685 23:25:00.705453 EX_ROW_EN[1] = 0x0
686 23:25:00.708773 LP4Y_EN = 0x0
687 23:25:00.708879 WORK_FSP = 0x0
688 23:25:00.711776 WL = 0x2
689 23:25:00.711884 RL = 0x2
690 23:25:00.715329 BL = 0x2
691 23:25:00.718658 RPST = 0x0
692 23:25:00.718766 RD_PRE = 0x0
693 23:25:00.721936 WR_PRE = 0x1
694 23:25:00.722066 WR_PST = 0x0
695 23:25:00.725128 DBI_WR = 0x0
696 23:25:00.725256 DBI_RD = 0x0
697 23:25:00.728494 OTF = 0x1
698 23:25:00.731740 ===================================
699 23:25:00.735179 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:25:00.740666 nWR fixed to 40
701 23:25:00.743758 [ModeRegInit_LP4] CH0 RK0
702 23:25:00.743886 [ModeRegInit_LP4] CH0 RK1
703 23:25:00.747301 [ModeRegInit_LP4] CH1 RK0
704 23:25:00.750506 [ModeRegInit_LP4] CH1 RK1
705 23:25:00.750640 match AC timing 13
706 23:25:00.757380 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 23:25:00.760858 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:25:00.763775 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:25:00.770694 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:25:00.773749 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:25:00.773837 [EMI DOE] emi_dcm 0
712 23:25:00.780551 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:25:00.780662 ==
714 23:25:00.784026 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:25:00.787434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 23:25:00.787524 ==
717 23:25:00.793841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:25:00.800322 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:25:00.808044 [CA 0] Center 36 (6~67) winsize 62
720 23:25:00.811502 [CA 1] Center 36 (6~67) winsize 62
721 23:25:00.814873 [CA 2] Center 34 (4~65) winsize 62
722 23:25:00.817883 [CA 3] Center 33 (3~64) winsize 62
723 23:25:00.821323 [CA 4] Center 33 (3~64) winsize 62
724 23:25:00.824476 [CA 5] Center 32 (2~62) winsize 61
725 23:25:00.824556
726 23:25:00.828173 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 23:25:00.828275
728 23:25:00.831518 [CATrainingPosCal] consider 1 rank data
729 23:25:00.834541 u2DelayCellTimex100 = 270/100 ps
730 23:25:00.837847 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 23:25:00.841546 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 23:25:00.847897 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 23:25:00.851473 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 23:25:00.854628 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 23:25:00.858043 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 23:25:00.858130
737 23:25:00.861675 CA PerBit enable=1, Macro0, CA PI delay=32
738 23:25:00.861760
739 23:25:00.864850 [CBTSetCACLKResult] CA Dly = 32
740 23:25:00.864935 CS Dly: 5 (0~36)
741 23:25:00.865002 ==
742 23:25:00.868175 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:25:00.875134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 23:25:00.875246 ==
745 23:25:00.878257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:25:00.884790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:25:00.894101 [CA 0] Center 36 (6~67) winsize 62
748 23:25:00.897443 [CA 1] Center 36 (6~67) winsize 62
749 23:25:00.900995 [CA 2] Center 34 (4~65) winsize 62
750 23:25:00.904464 [CA 3] Center 33 (3~64) winsize 62
751 23:25:00.907452 [CA 4] Center 32 (2~63) winsize 62
752 23:25:00.910840 [CA 5] Center 32 (2~63) winsize 62
753 23:25:00.910953
754 23:25:00.914332 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 23:25:00.914412
756 23:25:00.917756 [CATrainingPosCal] consider 2 rank data
757 23:25:00.920814 u2DelayCellTimex100 = 270/100 ps
758 23:25:00.924194 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 23:25:00.927641 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 23:25:00.934100 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 23:25:00.937567 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 23:25:00.940914 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 23:25:00.944044 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 23:25:00.944131
765 23:25:00.947364 CA PerBit enable=1, Macro0, CA PI delay=32
766 23:25:00.947470
767 23:25:00.950807 [CBTSetCACLKResult] CA Dly = 32
768 23:25:00.950887 CS Dly: 5 (0~36)
769 23:25:00.950960
770 23:25:00.954189 ----->DramcWriteLeveling(PI) begin...
771 23:25:00.954298 ==
772 23:25:00.958117 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:25:00.961948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 23:25:00.965458 ==
775 23:25:00.965545 Write leveling (Byte 0): 33 => 33
776 23:25:00.969364 Write leveling (Byte 1): 33 => 33
777 23:25:00.972890 DramcWriteLeveling(PI) end<-----
778 23:25:00.972972
779 23:25:00.973047 ==
780 23:25:00.976159 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:25:00.979635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:25:00.979716 ==
783 23:25:00.982839 [Gating] SW mode calibration
784 23:25:00.990220 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:25:00.997194 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:25:01.000388 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:25:01.003954 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 23:25:01.010501 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 23:25:01.013837 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:25:01.017302 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:25:01.020458 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:25:01.027339 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:25:01.030334 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:25:01.033748 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:25:01.040491 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:25:01.043952 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:25:01.047088 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:25:01.053905 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:25:01.057100 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:25:01.060520 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:25:01.067027 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:25:01.070452 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:25:01.073972 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 23:25:01.080463 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 23:25:01.083732 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:25:01.087588 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:25:01.090675 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:25:01.097404 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:25:01.100501 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:25:01.103851 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:25:01.110731 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:25:01.113914 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
813 23:25:01.117354 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 23:25:01.123752 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:25:01.127051 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:25:01.130574 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:25:01.137202 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:25:01.140476 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:25:01.143964 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
820 23:25:01.150443 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
821 23:25:01.153914 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
822 23:25:01.157366 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:25:01.163881 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:25:01.167171 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:25:01.170616 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:25:01.177362 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:25:01.180446 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:25:01.183953 0 11 8 | B1->B0 | 2b2b 4343 | 0 1 | (0 0) (0 0)
829 23:25:01.187371 0 11 12 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
830 23:25:01.193872 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:25:01.197506 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:25:01.200834 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:25:01.207154 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:25:01.210647 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:25:01.213939 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 23:25:01.220514 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 23:25:01.223983 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 23:25:01.227446 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:25:01.233979 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:25:01.237468 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:25:01.240530 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:25:01.247275 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:25:01.250639 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:25:01.253931 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:25:01.260643 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:25:01.264175 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:25:01.267461 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:25:01.270745 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:25:01.277472 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:25:01.280840 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:25:01.284014 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 23:25:01.290664 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 23:25:01.294226 Total UI for P1: 0, mck2ui 16
854 23:25:01.297252 best dqsien dly found for B0: ( 0, 14, 4)
855 23:25:01.300559 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 23:25:01.304049 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 23:25:01.307535 Total UI for P1: 0, mck2ui 16
858 23:25:01.311270 best dqsien dly found for B1: ( 0, 14, 10)
859 23:25:01.314417 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
860 23:25:01.317605 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 23:25:01.317720
862 23:25:01.324307 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
863 23:25:01.327742 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 23:25:01.327820 [Gating] SW calibration Done
865 23:25:01.331148 ==
866 23:25:01.331260 Dram Type= 6, Freq= 0, CH_0, rank 0
867 23:25:01.337685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 23:25:01.337803 ==
869 23:25:01.337906 RX Vref Scan: 0
870 23:25:01.338005
871 23:25:01.341109 RX Vref 0 -> 0, step: 1
872 23:25:01.341199
873 23:25:01.344532 RX Delay -130 -> 252, step: 16
874 23:25:01.347995 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
875 23:25:01.350983 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
876 23:25:01.354419 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
877 23:25:01.361249 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
878 23:25:01.364538 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
879 23:25:01.367913 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
880 23:25:01.370898 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
881 23:25:01.374411 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
882 23:25:01.381082 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
883 23:25:01.384478 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
884 23:25:01.387845 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
885 23:25:01.390876 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
886 23:25:01.394520 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
887 23:25:01.401214 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
888 23:25:01.404518 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
889 23:25:01.407872 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
890 23:25:01.407980 ==
891 23:25:01.411181 Dram Type= 6, Freq= 0, CH_0, rank 0
892 23:25:01.414851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 23:25:01.414965 ==
894 23:25:01.417785 DQS Delay:
895 23:25:01.417863 DQS0 = 0, DQS1 = 0
896 23:25:01.421218 DQM Delay:
897 23:25:01.421329 DQM0 = 89, DQM1 = 83
898 23:25:01.421423 DQ Delay:
899 23:25:01.424780 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
900 23:25:01.427906 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
901 23:25:01.431467 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
902 23:25:01.434711 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
903 23:25:01.434788
904 23:25:01.434852
905 23:25:01.434916 ==
906 23:25:01.438091 Dram Type= 6, Freq= 0, CH_0, rank 0
907 23:25:01.444870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 23:25:01.444950 ==
909 23:25:01.445018
910 23:25:01.445083
911 23:25:01.445149 TX Vref Scan disable
912 23:25:01.448359 == TX Byte 0 ==
913 23:25:01.451744 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 23:25:01.455194 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 23:25:01.458157 == TX Byte 1 ==
916 23:25:01.461662 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
917 23:25:01.465096 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
918 23:25:01.468222 ==
919 23:25:01.471782 Dram Type= 6, Freq= 0, CH_0, rank 0
920 23:25:01.475161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 23:25:01.475276 ==
922 23:25:01.487229 TX Vref=22, minBit 8, minWin=27, winSum=446
923 23:25:01.490645 TX Vref=24, minBit 4, minWin=27, winSum=448
924 23:25:01.493764 TX Vref=26, minBit 13, minWin=27, winSum=454
925 23:25:01.497196 TX Vref=28, minBit 13, minWin=27, winSum=455
926 23:25:01.500816 TX Vref=30, minBit 15, minWin=27, winSum=455
927 23:25:01.507398 TX Vref=32, minBit 11, minWin=27, winSum=454
928 23:25:01.510645 [TxChooseVref] Worse bit 13, Min win 27, Win sum 455, Final Vref 28
929 23:25:01.510763
930 23:25:01.513914 Final TX Range 1 Vref 28
931 23:25:01.514003
932 23:25:01.514082 ==
933 23:25:01.517225 Dram Type= 6, Freq= 0, CH_0, rank 0
934 23:25:01.520568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 23:25:01.524080 ==
936 23:25:01.524168
937 23:25:01.524246
938 23:25:01.524341 TX Vref Scan disable
939 23:25:01.527525 == TX Byte 0 ==
940 23:25:01.530758 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
941 23:25:01.537561 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
942 23:25:01.537650 == TX Byte 1 ==
943 23:25:01.540704 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
944 23:25:01.544181 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
945 23:25:01.547396
946 23:25:01.547526 [DATLAT]
947 23:25:01.547644 Freq=800, CH0 RK0
948 23:25:01.547758
949 23:25:01.550812 DATLAT Default: 0xa
950 23:25:01.550940 0, 0xFFFF, sum = 0
951 23:25:01.554403 1, 0xFFFF, sum = 0
952 23:25:01.554492 2, 0xFFFF, sum = 0
953 23:25:01.557297 3, 0xFFFF, sum = 0
954 23:25:01.557377 4, 0xFFFF, sum = 0
955 23:25:01.560717 5, 0xFFFF, sum = 0
956 23:25:01.564234 6, 0xFFFF, sum = 0
957 23:25:01.564344 7, 0xFFFF, sum = 0
958 23:25:01.567668 8, 0xFFFF, sum = 0
959 23:25:01.567751 9, 0x0, sum = 1
960 23:25:01.567818 10, 0x0, sum = 2
961 23:25:01.570707 11, 0x0, sum = 3
962 23:25:01.570787 12, 0x0, sum = 4
963 23:25:01.574220 best_step = 10
964 23:25:01.574296
965 23:25:01.574358 ==
966 23:25:01.577580 Dram Type= 6, Freq= 0, CH_0, rank 0
967 23:25:01.581132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 23:25:01.581210 ==
969 23:25:01.584177 RX Vref Scan: 1
970 23:25:01.584279
971 23:25:01.584364 Set Vref Range= 32 -> 127
972 23:25:01.584427
973 23:25:01.587636 RX Vref 32 -> 127, step: 1
974 23:25:01.587723
975 23:25:01.590833 RX Delay -79 -> 252, step: 8
976 23:25:01.590965
977 23:25:01.593997 Set Vref, RX VrefLevel [Byte0]: 32
978 23:25:01.597420 [Byte1]: 32
979 23:25:01.597501
980 23:25:01.600976 Set Vref, RX VrefLevel [Byte0]: 33
981 23:25:01.603988 [Byte1]: 33
982 23:25:01.607993
983 23:25:01.608119 Set Vref, RX VrefLevel [Byte0]: 34
984 23:25:01.611313 [Byte1]: 34
985 23:25:01.615497
986 23:25:01.615616 Set Vref, RX VrefLevel [Byte0]: 35
987 23:25:01.618511 [Byte1]: 35
988 23:25:01.623201
989 23:25:01.623297 Set Vref, RX VrefLevel [Byte0]: 36
990 23:25:01.626468 [Byte1]: 36
991 23:25:01.630878
992 23:25:01.630986 Set Vref, RX VrefLevel [Byte0]: 37
993 23:25:01.633871 [Byte1]: 37
994 23:25:01.637997
995 23:25:01.638102 Set Vref, RX VrefLevel [Byte0]: 38
996 23:25:01.641311 [Byte1]: 38
997 23:25:01.645579
998 23:25:01.645678 Set Vref, RX VrefLevel [Byte0]: 39
999 23:25:01.648892 [Byte1]: 39
1000 23:25:01.653121
1001 23:25:01.656194 Set Vref, RX VrefLevel [Byte0]: 40
1002 23:25:01.656299 [Byte1]: 40
1003 23:25:01.660469
1004 23:25:01.660637 Set Vref, RX VrefLevel [Byte0]: 41
1005 23:25:01.663880 [Byte1]: 41
1006 23:25:01.668086
1007 23:25:01.668208 Set Vref, RX VrefLevel [Byte0]: 42
1008 23:25:01.671579 [Byte1]: 42
1009 23:25:01.675997
1010 23:25:01.676104 Set Vref, RX VrefLevel [Byte0]: 43
1011 23:25:01.678983 [Byte1]: 43
1012 23:25:01.683258
1013 23:25:01.683344 Set Vref, RX VrefLevel [Byte0]: 44
1014 23:25:01.686626 [Byte1]: 44
1015 23:25:01.690723
1016 23:25:01.690809 Set Vref, RX VrefLevel [Byte0]: 45
1017 23:25:01.694177 [Byte1]: 45
1018 23:25:01.698281
1019 23:25:01.698366 Set Vref, RX VrefLevel [Byte0]: 46
1020 23:25:01.701521 [Byte1]: 46
1021 23:25:01.705775
1022 23:25:01.705860 Set Vref, RX VrefLevel [Byte0]: 47
1023 23:25:01.709240 [Byte1]: 47
1024 23:25:01.713525
1025 23:25:01.713626 Set Vref, RX VrefLevel [Byte0]: 48
1026 23:25:01.716716 [Byte1]: 48
1027 23:25:01.721343
1028 23:25:01.721429 Set Vref, RX VrefLevel [Byte0]: 49
1029 23:25:01.724532 [Byte1]: 49
1030 23:25:01.728766
1031 23:25:01.728849 Set Vref, RX VrefLevel [Byte0]: 50
1032 23:25:01.732154 [Byte1]: 50
1033 23:25:01.736067
1034 23:25:01.736182 Set Vref, RX VrefLevel [Byte0]: 51
1035 23:25:01.739427 [Byte1]: 51
1036 23:25:01.743431
1037 23:25:01.746818 Set Vref, RX VrefLevel [Byte0]: 52
1038 23:25:01.746924 [Byte1]: 52
1039 23:25:01.751103
1040 23:25:01.751206 Set Vref, RX VrefLevel [Byte0]: 53
1041 23:25:01.754543 [Byte1]: 53
1042 23:25:01.758976
1043 23:25:01.759082 Set Vref, RX VrefLevel [Byte0]: 54
1044 23:25:01.762263 [Byte1]: 54
1045 23:25:01.766324
1046 23:25:01.766441 Set Vref, RX VrefLevel [Byte0]: 55
1047 23:25:01.769792 [Byte1]: 55
1048 23:25:01.773880
1049 23:25:01.773987 Set Vref, RX VrefLevel [Byte0]: 56
1050 23:25:01.777048 [Byte1]: 56
1051 23:25:01.781244
1052 23:25:01.781346 Set Vref, RX VrefLevel [Byte0]: 57
1053 23:25:01.784618 [Byte1]: 57
1054 23:25:01.789070
1055 23:25:01.789200 Set Vref, RX VrefLevel [Byte0]: 58
1056 23:25:01.792119 [Byte1]: 58
1057 23:25:01.796418
1058 23:25:01.796504 Set Vref, RX VrefLevel [Byte0]: 59
1059 23:25:01.799858 [Byte1]: 59
1060 23:25:01.803981
1061 23:25:01.804065 Set Vref, RX VrefLevel [Byte0]: 60
1062 23:25:01.807224 [Byte1]: 60
1063 23:25:01.811447
1064 23:25:01.811531 Set Vref, RX VrefLevel [Byte0]: 61
1065 23:25:01.814957 [Byte1]: 61
1066 23:25:01.819040
1067 23:25:01.819122 Set Vref, RX VrefLevel [Byte0]: 62
1068 23:25:01.822268 [Byte1]: 62
1069 23:25:01.826485
1070 23:25:01.826628 Set Vref, RX VrefLevel [Byte0]: 63
1071 23:25:01.830066 [Byte1]: 63
1072 23:25:01.834232
1073 23:25:01.834350 Set Vref, RX VrefLevel [Byte0]: 64
1074 23:25:01.837524 [Byte1]: 64
1075 23:25:01.842099
1076 23:25:01.842209 Set Vref, RX VrefLevel [Byte0]: 65
1077 23:25:01.845106 [Byte1]: 65
1078 23:25:01.849470
1079 23:25:01.849556 Set Vref, RX VrefLevel [Byte0]: 66
1080 23:25:01.852403 [Byte1]: 66
1081 23:25:01.856760
1082 23:25:01.856851 Set Vref, RX VrefLevel [Byte0]: 67
1083 23:25:01.860159 [Byte1]: 67
1084 23:25:01.864485
1085 23:25:01.864567 Set Vref, RX VrefLevel [Byte0]: 68
1086 23:25:01.867924 [Byte1]: 68
1087 23:25:01.871925
1088 23:25:01.872005 Set Vref, RX VrefLevel [Byte0]: 69
1089 23:25:01.875282 [Byte1]: 69
1090 23:25:01.879643
1091 23:25:01.879721 Set Vref, RX VrefLevel [Byte0]: 70
1092 23:25:01.883042 [Byte1]: 70
1093 23:25:01.887094
1094 23:25:01.887206 Set Vref, RX VrefLevel [Byte0]: 71
1095 23:25:01.890359 [Byte1]: 71
1096 23:25:01.894487
1097 23:25:01.894567 Set Vref, RX VrefLevel [Byte0]: 72
1098 23:25:01.897739 [Byte1]: 72
1099 23:25:01.902270
1100 23:25:01.902383 Set Vref, RX VrefLevel [Byte0]: 73
1101 23:25:01.905528 [Byte1]: 73
1102 23:25:01.909886
1103 23:25:01.909965 Set Vref, RX VrefLevel [Byte0]: 74
1104 23:25:01.913018 [Byte1]: 74
1105 23:25:01.917363
1106 23:25:01.917439 Set Vref, RX VrefLevel [Byte0]: 75
1107 23:25:01.920388 [Byte1]: 75
1108 23:25:01.924914
1109 23:25:01.925001 Set Vref, RX VrefLevel [Byte0]: 76
1110 23:25:01.928407 [Byte1]: 76
1111 23:25:01.932532
1112 23:25:01.932616 Set Vref, RX VrefLevel [Byte0]: 77
1113 23:25:01.935803 [Byte1]: 77
1114 23:25:01.940058
1115 23:25:01.940145 Final RX Vref Byte 0 = 59 to rank0
1116 23:25:01.943219 Final RX Vref Byte 1 = 60 to rank0
1117 23:25:01.946806 Final RX Vref Byte 0 = 59 to rank1
1118 23:25:01.950115 Final RX Vref Byte 1 = 60 to rank1==
1119 23:25:01.953129 Dram Type= 6, Freq= 0, CH_0, rank 0
1120 23:25:01.959949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1121 23:25:01.960047 ==
1122 23:25:01.960119 DQS Delay:
1123 23:25:01.960182 DQS0 = 0, DQS1 = 0
1124 23:25:01.963367 DQM Delay:
1125 23:25:01.963452 DQM0 = 92, DQM1 = 85
1126 23:25:01.966312 DQ Delay:
1127 23:25:01.969760 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1128 23:25:01.973237 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1129 23:25:01.973329 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
1130 23:25:01.976839 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1131 23:25:01.980244
1132 23:25:01.980342
1133 23:25:01.986601 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1134 23:25:01.990077 CH0 RK0: MR19=606, MR18=4B41
1135 23:25:01.997034 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1136 23:25:01.997119
1137 23:25:02.000269 ----->DramcWriteLeveling(PI) begin...
1138 23:25:02.000360 ==
1139 23:25:02.003861 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 23:25:02.006849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 23:25:02.006926 ==
1142 23:25:02.010097 Write leveling (Byte 0): 35 => 35
1143 23:25:02.013562 Write leveling (Byte 1): 31 => 31
1144 23:25:02.016858 DramcWriteLeveling(PI) end<-----
1145 23:25:02.016963
1146 23:25:02.017051 ==
1147 23:25:02.020328 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 23:25:02.023598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 23:25:02.023705 ==
1150 23:25:02.026966 [Gating] SW mode calibration
1151 23:25:02.070914 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1152 23:25:02.071296 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1153 23:25:02.071412 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 23:25:02.071511 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 23:25:02.071616 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1156 23:25:02.071707 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:25:02.071799 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:25:02.071907 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:25:02.071996 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:25:02.101741 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:25:02.102026 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:25:02.102133 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:25:02.102247 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:25:02.102353 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:25:02.102448 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:25:02.105677 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:25:02.105754 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:25:02.109108 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:25:02.112548 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:25:02.119027 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1171 23:25:02.122209 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1172 23:25:02.126009 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:25:02.132311 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:25:02.135900 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:25:02.139185 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:25:02.145870 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:25:02.149004 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:25:02.152176 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 23:25:02.159019 0 9 8 | B1->B0 | 2727 2828 | 1 1 | (0 0) (0 0)
1180 23:25:02.162336 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:25:02.165619 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 23:25:02.172505 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 23:25:02.175520 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 23:25:02.178887 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 23:25:02.185581 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 23:25:02.188979 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 23:25:02.192478 0 10 8 | B1->B0 | 2c2c 2d2d | 0 0 | (0 0) (0 0)
1188 23:25:02.195596 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:25:02.203030 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:25:02.206468 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:25:02.210407 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 23:25:02.214010 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:25:02.220561 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 23:25:02.224001 0 11 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1195 23:25:02.227172 0 11 8 | B1->B0 | 3c3c 3b3b | 0 1 | (0 0) (0 0)
1196 23:25:02.231271 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:25:02.237843 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:25:02.241361 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 23:25:02.244629 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 23:25:02.251346 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 23:25:02.254364 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 23:25:02.257748 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 23:25:02.264507 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1204 23:25:02.267933 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:25:02.270889 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:25:02.277774 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:25:02.281202 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:25:02.284806 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:25:02.287772 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:25:02.294620 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:25:02.297772 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:25:02.301215 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:25:02.307718 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:25:02.311139 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:25:02.314587 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:25:02.321403 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:25:02.324618 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 23:25:02.328143 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 23:25:02.334715 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1220 23:25:02.338069 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 23:25:02.341445 Total UI for P1: 0, mck2ui 16
1222 23:25:02.344673 best dqsien dly found for B0: ( 0, 14, 8)
1223 23:25:02.348040 Total UI for P1: 0, mck2ui 16
1224 23:25:02.351358 best dqsien dly found for B1: ( 0, 14, 8)
1225 23:25:02.354749 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1226 23:25:02.357897 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1227 23:25:02.358022
1228 23:25:02.361378 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 23:25:02.364554 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1230 23:25:02.367844 [Gating] SW calibration Done
1231 23:25:02.367968 ==
1232 23:25:02.371183 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 23:25:02.374619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 23:25:02.374755 ==
1235 23:25:02.378180 RX Vref Scan: 0
1236 23:25:02.378313
1237 23:25:02.381568 RX Vref 0 -> 0, step: 1
1238 23:25:02.381694
1239 23:25:02.381818 RX Delay -130 -> 252, step: 16
1240 23:25:02.387919 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1241 23:25:02.391325 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1242 23:25:02.394755 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1243 23:25:02.398255 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1244 23:25:02.401236 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1245 23:25:02.408157 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1246 23:25:02.411434 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1247 23:25:02.414931 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1248 23:25:02.417906 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1249 23:25:02.421307 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1250 23:25:02.428125 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1251 23:25:02.431132 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1252 23:25:02.434393 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1253 23:25:02.438245 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1254 23:25:02.441136 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1255 23:25:02.448134 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1256 23:25:02.448262 ==
1257 23:25:02.451055 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 23:25:02.454613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 23:25:02.454741 ==
1260 23:25:02.454866 DQS Delay:
1261 23:25:02.458292 DQS0 = 0, DQS1 = 0
1262 23:25:02.458428 DQM Delay:
1263 23:25:02.461181 DQM0 = 93, DQM1 = 85
1264 23:25:02.461315 DQ Delay:
1265 23:25:02.464639 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1266 23:25:02.468069 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1267 23:25:02.471376 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1268 23:25:02.474650 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1269 23:25:02.474756
1270 23:25:02.474874
1271 23:25:02.474965 ==
1272 23:25:02.478077 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 23:25:02.481515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 23:25:02.481627 ==
1275 23:25:02.484635
1276 23:25:02.484759
1277 23:25:02.484887 TX Vref Scan disable
1278 23:25:02.488074 == TX Byte 0 ==
1279 23:25:02.491098 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1280 23:25:02.494549 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1281 23:25:02.498118 == TX Byte 1 ==
1282 23:25:02.501480 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1283 23:25:02.504644 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1284 23:25:02.504734 ==
1285 23:25:02.507991 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 23:25:02.514432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 23:25:02.514539 ==
1288 23:25:02.527040 TX Vref=22, minBit 8, minWin=27, winSum=446
1289 23:25:02.530356 TX Vref=24, minBit 1, minWin=28, winSum=451
1290 23:25:02.533528 TX Vref=26, minBit 2, minWin=28, winSum=456
1291 23:25:02.536638 TX Vref=28, minBit 8, minWin=28, winSum=461
1292 23:25:02.540290 TX Vref=30, minBit 2, minWin=28, winSum=457
1293 23:25:02.546886 TX Vref=32, minBit 0, minWin=28, winSum=454
1294 23:25:02.550019 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 28
1295 23:25:02.550108
1296 23:25:02.553258 Final TX Range 1 Vref 28
1297 23:25:02.553342
1298 23:25:02.553407 ==
1299 23:25:02.556777 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 23:25:02.559936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 23:25:02.560014 ==
1302 23:25:02.563151
1303 23:25:02.563230
1304 23:25:02.563295 TX Vref Scan disable
1305 23:25:02.566963 == TX Byte 0 ==
1306 23:25:02.570330 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1307 23:25:02.573326 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1308 23:25:02.577161 == TX Byte 1 ==
1309 23:25:02.580432 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1310 23:25:02.583493 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1311 23:25:02.586918
1312 23:25:02.587040 [DATLAT]
1313 23:25:02.587156 Freq=800, CH0 RK1
1314 23:25:02.587270
1315 23:25:02.590427 DATLAT Default: 0xa
1316 23:25:02.590544 0, 0xFFFF, sum = 0
1317 23:25:02.593833 1, 0xFFFF, sum = 0
1318 23:25:02.593955 2, 0xFFFF, sum = 0
1319 23:25:02.596915 3, 0xFFFF, sum = 0
1320 23:25:02.597042 4, 0xFFFF, sum = 0
1321 23:25:02.600317 5, 0xFFFF, sum = 0
1322 23:25:02.600439 6, 0xFFFF, sum = 0
1323 23:25:02.603458 7, 0xFFFF, sum = 0
1324 23:25:02.603584 8, 0xFFFF, sum = 0
1325 23:25:02.606943 9, 0x0, sum = 1
1326 23:25:02.607070 10, 0x0, sum = 2
1327 23:25:02.610390 11, 0x0, sum = 3
1328 23:25:02.610515 12, 0x0, sum = 4
1329 23:25:02.613589 best_step = 10
1330 23:25:02.613707
1331 23:25:02.613816 ==
1332 23:25:02.616945 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 23:25:02.620389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 23:25:02.620510 ==
1335 23:25:02.623475 RX Vref Scan: 0
1336 23:25:02.623595
1337 23:25:02.623708 RX Vref 0 -> 0, step: 1
1338 23:25:02.623819
1339 23:25:02.626757 RX Delay -79 -> 252, step: 8
1340 23:25:02.633433 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1341 23:25:02.636882 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1342 23:25:02.640072 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1343 23:25:02.643401 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1344 23:25:02.646733 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1345 23:25:02.653576 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1346 23:25:02.656803 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1347 23:25:02.660122 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1348 23:25:02.663549 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1349 23:25:02.666749 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1350 23:25:02.670322 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1351 23:25:02.677029 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1352 23:25:02.680251 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1353 23:25:02.683521 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1354 23:25:02.686952 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1355 23:25:02.693949 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1356 23:25:02.694057 ==
1357 23:25:02.696938 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 23:25:02.700452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 23:25:02.700564 ==
1360 23:25:02.700657 DQS Delay:
1361 23:25:02.703845 DQS0 = 0, DQS1 = 0
1362 23:25:02.703929 DQM Delay:
1363 23:25:02.706885 DQM0 = 93, DQM1 = 83
1364 23:25:02.706966 DQ Delay:
1365 23:25:02.710362 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1366 23:25:02.713935 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1367 23:25:02.716902 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1368 23:25:02.720299 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1369 23:25:02.720381
1370 23:25:02.720445
1371 23:25:02.727166 [DQSOSCAuto] RK1, (LSB)MR18= 0x4415, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1372 23:25:02.730239 CH0 RK1: MR19=606, MR18=4415
1373 23:25:02.737025 CH0_RK1: MR19=0x606, MR18=0x4415, DQSOSC=392, MR23=63, INC=96, DEC=64
1374 23:25:02.740458 [RxdqsGatingPostProcess] freq 800
1375 23:25:02.746861 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 23:25:02.750130 Pre-setting of DQS Precalculation
1377 23:25:02.753982 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 23:25:02.754065 ==
1379 23:25:02.757122 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 23:25:02.760442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 23:25:02.760527 ==
1382 23:25:02.766987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 23:25:02.773375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 23:25:02.781935 [CA 0] Center 36 (6~67) winsize 62
1385 23:25:02.785275 [CA 1] Center 36 (6~67) winsize 62
1386 23:25:02.788448 [CA 2] Center 35 (5~66) winsize 62
1387 23:25:02.792014 [CA 3] Center 34 (4~65) winsize 62
1388 23:25:02.795130 [CA 4] Center 35 (5~65) winsize 61
1389 23:25:02.798346 [CA 5] Center 34 (4~65) winsize 62
1390 23:25:02.798430
1391 23:25:02.801963 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1392 23:25:02.802046
1393 23:25:02.805424 [CATrainingPosCal] consider 1 rank data
1394 23:25:02.808590 u2DelayCellTimex100 = 270/100 ps
1395 23:25:02.811978 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 23:25:02.815057 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 23:25:02.821869 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1398 23:25:02.825169 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 23:25:02.828301 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1400 23:25:02.832026 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 23:25:02.832142
1402 23:25:02.835336 CA PerBit enable=1, Macro0, CA PI delay=34
1403 23:25:02.835441
1404 23:25:02.838519 [CBTSetCACLKResult] CA Dly = 34
1405 23:25:02.838621 CS Dly: 6 (0~37)
1406 23:25:02.838686 ==
1407 23:25:02.842055 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 23:25:02.848603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 23:25:02.848690 ==
1410 23:25:02.852023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 23:25:02.858504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 23:25:02.868410 [CA 0] Center 36 (6~67) winsize 62
1413 23:25:02.871803 [CA 1] Center 37 (6~68) winsize 63
1414 23:25:02.875627 [CA 2] Center 35 (4~66) winsize 63
1415 23:25:02.879239 [CA 3] Center 34 (4~65) winsize 62
1416 23:25:02.883053 [CA 4] Center 35 (4~66) winsize 63
1417 23:25:02.886608 [CA 5] Center 34 (4~65) winsize 62
1418 23:25:02.886692
1419 23:25:02.890522 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1420 23:25:02.890606
1421 23:25:02.894222 [CATrainingPosCal] consider 2 rank data
1422 23:25:02.894341 u2DelayCellTimex100 = 270/100 ps
1423 23:25:02.898106 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 23:25:02.901090 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 23:25:02.907941 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1426 23:25:02.911045 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 23:25:02.914408 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1428 23:25:02.917803 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 23:25:02.917930
1430 23:25:02.921345 CA PerBit enable=1, Macro0, CA PI delay=34
1431 23:25:02.921458
1432 23:25:02.924769 [CBTSetCACLKResult] CA Dly = 34
1433 23:25:02.924889 CS Dly: 6 (0~38)
1434 23:25:02.924999
1435 23:25:02.927826 ----->DramcWriteLeveling(PI) begin...
1436 23:25:02.931295 ==
1437 23:25:02.934717 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 23:25:02.938130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 23:25:02.938255 ==
1440 23:25:02.941103 Write leveling (Byte 0): 28 => 28
1441 23:25:02.944485 Write leveling (Byte 1): 28 => 28
1442 23:25:02.947958 DramcWriteLeveling(PI) end<-----
1443 23:25:02.948065
1444 23:25:02.948159 ==
1445 23:25:02.951140 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 23:25:02.954682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 23:25:02.954766 ==
1448 23:25:02.958009 [Gating] SW mode calibration
1449 23:25:02.965050 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 23:25:02.968136 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 23:25:02.974715 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1452 23:25:02.977948 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 23:25:02.981450 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:25:02.988089 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:25:02.991365 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:25:02.994728 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:25:03.001406 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:25:03.004594 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:25:03.007971 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:25:03.014637 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:25:03.017877 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:25:03.021523 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:25:03.024946 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:25:03.031456 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:25:03.034865 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:25:03.037982 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:25:03.044904 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 23:25:03.047966 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1469 23:25:03.051493 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1470 23:25:03.057944 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:25:03.061411 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:25:03.064554 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:25:03.071568 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:25:03.074916 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:25:03.077855 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 23:25:03.084608 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1477 23:25:03.088047 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
1478 23:25:03.091497 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 23:25:03.098012 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 23:25:03.101349 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 23:25:03.104826 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 23:25:03.111629 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 23:25:03.114619 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 23:25:03.117968 0 10 4 | B1->B0 | 3232 2e2e | 1 1 | (1 0) (0 0)
1485 23:25:03.124712 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1486 23:25:03.128137 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:25:03.131590 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:25:03.134713 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:25:03.141291 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 23:25:03.144650 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:25:03.148064 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1492 23:25:03.154628 0 11 4 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
1493 23:25:03.158117 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
1494 23:25:03.161232 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:25:03.168217 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:25:03.171209 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 23:25:03.174680 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 23:25:03.181583 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 23:25:03.184463 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 23:25:03.188059 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 23:25:03.194600 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:25:03.198219 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:25:03.201217 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:25:03.207841 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:25:03.211306 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:25:03.214736 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:25:03.221498 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:25:03.224565 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:25:03.228048 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:25:03.231407 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:25:03.238256 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:25:03.241586 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:25:03.244978 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:25:03.251326 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 23:25:03.254617 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 23:25:03.258127 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 23:25:03.264668 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 23:25:03.264758 Total UI for P1: 0, mck2ui 16
1519 23:25:03.271377 best dqsien dly found for B0: ( 0, 14, 4)
1520 23:25:03.271458 Total UI for P1: 0, mck2ui 16
1521 23:25:03.278126 best dqsien dly found for B1: ( 0, 14, 4)
1522 23:25:03.281711 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1523 23:25:03.284620 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1524 23:25:03.284707
1525 23:25:03.288061 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 23:25:03.291167 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1527 23:25:03.294674 [Gating] SW calibration Done
1528 23:25:03.294785 ==
1529 23:25:03.298010 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 23:25:03.301227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 23:25:03.301309 ==
1532 23:25:03.304489 RX Vref Scan: 0
1533 23:25:03.304566
1534 23:25:03.304642 RX Vref 0 -> 0, step: 1
1535 23:25:03.304718
1536 23:25:03.308010 RX Delay -130 -> 252, step: 16
1537 23:25:03.311450 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1538 23:25:03.318246 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1539 23:25:03.321217 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1540 23:25:03.324687 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1541 23:25:03.327674 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1542 23:25:03.331311 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1543 23:25:03.337915 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1544 23:25:03.340955 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1545 23:25:03.344509 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1546 23:25:03.348050 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1547 23:25:03.351107 iDelay=222, Bit 10, Center 93 (-2 ~ 189) 192
1548 23:25:03.357585 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1549 23:25:03.361010 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1550 23:25:03.364427 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1551 23:25:03.368044 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1552 23:25:03.370941 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1553 23:25:03.374707 ==
1554 23:25:03.374834 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 23:25:03.381317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 23:25:03.381443 ==
1557 23:25:03.381560 DQS Delay:
1558 23:25:03.384322 DQS0 = 0, DQS1 = 0
1559 23:25:03.384449 DQM Delay:
1560 23:25:03.387843 DQM0 = 94, DQM1 = 92
1561 23:25:03.387968 DQ Delay:
1562 23:25:03.390967 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1563 23:25:03.394313 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1564 23:25:03.397675 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1565 23:25:03.401169 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1566 23:25:03.401270
1567 23:25:03.401387
1568 23:25:03.401483 ==
1569 23:25:03.404318 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 23:25:03.407789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 23:25:03.407872 ==
1572 23:25:03.407938
1573 23:25:03.407999
1574 23:25:03.411009 TX Vref Scan disable
1575 23:25:03.414410 == TX Byte 0 ==
1576 23:25:03.417594 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1577 23:25:03.421236 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1578 23:25:03.424503 == TX Byte 1 ==
1579 23:25:03.427798 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1580 23:25:03.431310 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1581 23:25:03.431386 ==
1582 23:25:03.434409 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 23:25:03.441068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 23:25:03.441150 ==
1585 23:25:03.452879 TX Vref=22, minBit 3, minWin=26, winSum=435
1586 23:25:03.456249 TX Vref=24, minBit 0, minWin=27, winSum=440
1587 23:25:03.459665 TX Vref=26, minBit 7, minWin=26, winSum=441
1588 23:25:03.463204 TX Vref=28, minBit 1, minWin=27, winSum=447
1589 23:25:03.466584 TX Vref=30, minBit 2, minWin=27, winSum=449
1590 23:25:03.469609 TX Vref=32, minBit 2, minWin=27, winSum=449
1591 23:25:03.476587 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 30
1592 23:25:03.476672
1593 23:25:03.479686 Final TX Range 1 Vref 30
1594 23:25:03.479791
1595 23:25:03.479887 ==
1596 23:25:03.483122 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 23:25:03.486428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 23:25:03.486532 ==
1599 23:25:03.486628
1600 23:25:03.486722
1601 23:25:03.489681 TX Vref Scan disable
1602 23:25:03.493146 == TX Byte 0 ==
1603 23:25:03.496278 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1604 23:25:03.499512 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1605 23:25:03.503172 == TX Byte 1 ==
1606 23:25:03.506169 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1607 23:25:03.509917 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1608 23:25:03.510022
1609 23:25:03.512970 [DATLAT]
1610 23:25:03.513046 Freq=800, CH1 RK0
1611 23:25:03.513125
1612 23:25:03.516268 DATLAT Default: 0xa
1613 23:25:03.516385 0, 0xFFFF, sum = 0
1614 23:25:03.519888 1, 0xFFFF, sum = 0
1615 23:25:03.519992 2, 0xFFFF, sum = 0
1616 23:25:03.523154 3, 0xFFFF, sum = 0
1617 23:25:03.523257 4, 0xFFFF, sum = 0
1618 23:25:03.526197 5, 0xFFFF, sum = 0
1619 23:25:03.526302 6, 0xFFFF, sum = 0
1620 23:25:03.529655 7, 0xFFFF, sum = 0
1621 23:25:03.529760 8, 0xFFFF, sum = 0
1622 23:25:03.533037 9, 0x0, sum = 1
1623 23:25:03.533129 10, 0x0, sum = 2
1624 23:25:03.536405 11, 0x0, sum = 3
1625 23:25:03.536481 12, 0x0, sum = 4
1626 23:25:03.539676 best_step = 10
1627 23:25:03.539786
1628 23:25:03.539885 ==
1629 23:25:03.543044 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 23:25:03.546235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 23:25:03.546340 ==
1632 23:25:03.546437 RX Vref Scan: 1
1633 23:25:03.550039
1634 23:25:03.550146 Set Vref Range= 32 -> 127
1635 23:25:03.550248
1636 23:25:03.552952 RX Vref 32 -> 127, step: 1
1637 23:25:03.553053
1638 23:25:03.556257 RX Delay -79 -> 252, step: 8
1639 23:25:03.556351
1640 23:25:03.559702 Set Vref, RX VrefLevel [Byte0]: 32
1641 23:25:03.563110 [Byte1]: 32
1642 23:25:03.563214
1643 23:25:03.566199 Set Vref, RX VrefLevel [Byte0]: 33
1644 23:25:03.569584 [Byte1]: 33
1645 23:25:03.569685
1646 23:25:03.573283 Set Vref, RX VrefLevel [Byte0]: 34
1647 23:25:03.576277 [Byte1]: 34
1648 23:25:03.580129
1649 23:25:03.580232 Set Vref, RX VrefLevel [Byte0]: 35
1650 23:25:03.583422 [Byte1]: 35
1651 23:25:03.587925
1652 23:25:03.588002 Set Vref, RX VrefLevel [Byte0]: 36
1653 23:25:03.590932 [Byte1]: 36
1654 23:25:03.595175
1655 23:25:03.595280 Set Vref, RX VrefLevel [Byte0]: 37
1656 23:25:03.598509 [Byte1]: 37
1657 23:25:03.602867
1658 23:25:03.602945 Set Vref, RX VrefLevel [Byte0]: 38
1659 23:25:03.606173 [Byte1]: 38
1660 23:25:03.610399
1661 23:25:03.610475 Set Vref, RX VrefLevel [Byte0]: 39
1662 23:25:03.613517 [Byte1]: 39
1663 23:25:03.617898
1664 23:25:03.618003 Set Vref, RX VrefLevel [Byte0]: 40
1665 23:25:03.621370 [Byte1]: 40
1666 23:25:03.625706
1667 23:25:03.625785 Set Vref, RX VrefLevel [Byte0]: 41
1668 23:25:03.628672 [Byte1]: 41
1669 23:25:03.633039
1670 23:25:03.633145 Set Vref, RX VrefLevel [Byte0]: 42
1671 23:25:03.636512 [Byte1]: 42
1672 23:25:03.640814
1673 23:25:03.640896 Set Vref, RX VrefLevel [Byte0]: 43
1674 23:25:03.643991 [Byte1]: 43
1675 23:25:03.648132
1676 23:25:03.648239 Set Vref, RX VrefLevel [Byte0]: 44
1677 23:25:03.651599 [Byte1]: 44
1678 23:25:03.655951
1679 23:25:03.656029 Set Vref, RX VrefLevel [Byte0]: 45
1680 23:25:03.659050 [Byte1]: 45
1681 23:25:03.663612
1682 23:25:03.663723 Set Vref, RX VrefLevel [Byte0]: 46
1683 23:25:03.666619 [Byte1]: 46
1684 23:25:03.671018
1685 23:25:03.671131 Set Vref, RX VrefLevel [Byte0]: 47
1686 23:25:03.674120 [Byte1]: 47
1687 23:25:03.678240
1688 23:25:03.678350 Set Vref, RX VrefLevel [Byte0]: 48
1689 23:25:03.681714 [Byte1]: 48
1690 23:25:03.685822
1691 23:25:03.685937 Set Vref, RX VrefLevel [Byte0]: 49
1692 23:25:03.689376 [Byte1]: 49
1693 23:25:03.693590
1694 23:25:03.693720 Set Vref, RX VrefLevel [Byte0]: 50
1695 23:25:03.696783 [Byte1]: 50
1696 23:25:03.701084
1697 23:25:03.701211 Set Vref, RX VrefLevel [Byte0]: 51
1698 23:25:03.704440 [Byte1]: 51
1699 23:25:03.708725
1700 23:25:03.708852 Set Vref, RX VrefLevel [Byte0]: 52
1701 23:25:03.711842 [Byte1]: 52
1702 23:25:03.715873
1703 23:25:03.716002 Set Vref, RX VrefLevel [Byte0]: 53
1704 23:25:03.719314 [Byte1]: 53
1705 23:25:03.723663
1706 23:25:03.723785 Set Vref, RX VrefLevel [Byte0]: 54
1707 23:25:03.727153 [Byte1]: 54
1708 23:25:03.731018
1709 23:25:03.731101 Set Vref, RX VrefLevel [Byte0]: 55
1710 23:25:03.734471 [Byte1]: 55
1711 23:25:03.738787
1712 23:25:03.738895 Set Vref, RX VrefLevel [Byte0]: 56
1713 23:25:03.742042 [Byte1]: 56
1714 23:25:03.746365
1715 23:25:03.746453 Set Vref, RX VrefLevel [Byte0]: 57
1716 23:25:03.749673 [Byte1]: 57
1717 23:25:03.753720
1718 23:25:03.753824 Set Vref, RX VrefLevel [Byte0]: 58
1719 23:25:03.757158 [Byte1]: 58
1720 23:25:03.761525
1721 23:25:03.761656 Set Vref, RX VrefLevel [Byte0]: 59
1722 23:25:03.764427 [Byte1]: 59
1723 23:25:03.768990
1724 23:25:03.769075 Set Vref, RX VrefLevel [Byte0]: 60
1725 23:25:03.772376 [Byte1]: 60
1726 23:25:03.776619
1727 23:25:03.776707 Set Vref, RX VrefLevel [Byte0]: 61
1728 23:25:03.779926 [Byte1]: 61
1729 23:25:03.784188
1730 23:25:03.784323 Set Vref, RX VrefLevel [Byte0]: 62
1731 23:25:03.787432 [Byte1]: 62
1732 23:25:03.791495
1733 23:25:03.791626 Set Vref, RX VrefLevel [Byte0]: 63
1734 23:25:03.794939 [Byte1]: 63
1735 23:25:03.799294
1736 23:25:03.799404 Set Vref, RX VrefLevel [Byte0]: 64
1737 23:25:03.802451 [Byte1]: 64
1738 23:25:03.806601
1739 23:25:03.806711 Set Vref, RX VrefLevel [Byte0]: 65
1740 23:25:03.809902 [Byte1]: 65
1741 23:25:03.814168
1742 23:25:03.814274 Set Vref, RX VrefLevel [Byte0]: 66
1743 23:25:03.817649 [Byte1]: 66
1744 23:25:03.821938
1745 23:25:03.822040 Set Vref, RX VrefLevel [Byte0]: 67
1746 23:25:03.824949 [Byte1]: 67
1747 23:25:03.829265
1748 23:25:03.829353 Set Vref, RX VrefLevel [Byte0]: 68
1749 23:25:03.832735 [Byte1]: 68
1750 23:25:03.837061
1751 23:25:03.837146 Set Vref, RX VrefLevel [Byte0]: 69
1752 23:25:03.839877 [Byte1]: 69
1753 23:25:03.844306
1754 23:25:03.844392 Set Vref, RX VrefLevel [Byte0]: 70
1755 23:25:03.847759 [Byte1]: 70
1756 23:25:03.852119
1757 23:25:03.852231 Final RX Vref Byte 0 = 61 to rank0
1758 23:25:03.855119 Final RX Vref Byte 1 = 58 to rank0
1759 23:25:03.858550 Final RX Vref Byte 0 = 61 to rank1
1760 23:25:03.862102 Final RX Vref Byte 1 = 58 to rank1==
1761 23:25:03.865150 Dram Type= 6, Freq= 0, CH_1, rank 0
1762 23:25:03.871940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1763 23:25:03.872065 ==
1764 23:25:03.872182 DQS Delay:
1765 23:25:03.872298 DQS0 = 0, DQS1 = 0
1766 23:25:03.875140 DQM Delay:
1767 23:25:03.875265 DQM0 = 95, DQM1 = 89
1768 23:25:03.878616 DQ Delay:
1769 23:25:03.882052 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1770 23:25:03.885439 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
1771 23:25:03.888681 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1772 23:25:03.892173 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1773 23:25:03.892291
1774 23:25:03.892381
1775 23:25:03.898512 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1776 23:25:03.901909 CH1 RK0: MR19=606, MR18=2B48
1777 23:25:03.908637 CH1_RK0: MR19=0x606, MR18=0x2B48, DQSOSC=391, MR23=63, INC=96, DEC=64
1778 23:25:03.908724
1779 23:25:03.912164 ----->DramcWriteLeveling(PI) begin...
1780 23:25:03.912251 ==
1781 23:25:03.915331 Dram Type= 6, Freq= 0, CH_1, rank 1
1782 23:25:03.918632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 23:25:03.918718 ==
1784 23:25:03.922174 Write leveling (Byte 0): 28 => 28
1785 23:25:03.925349 Write leveling (Byte 1): 28 => 28
1786 23:25:03.928736 DramcWriteLeveling(PI) end<-----
1787 23:25:03.928843
1788 23:25:03.928942 ==
1789 23:25:03.931836 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 23:25:03.935203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 23:25:03.935310 ==
1792 23:25:03.938816 [Gating] SW mode calibration
1793 23:25:03.945410 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1794 23:25:03.952005 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1795 23:25:03.955348 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1796 23:25:03.958820 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1797 23:25:03.965216 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 23:25:03.968575 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 23:25:03.971892 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 23:25:03.978662 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 23:25:03.982268 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 23:25:03.985161 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 23:25:03.992021 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 23:25:03.995327 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 23:25:03.998868 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 23:25:04.005359 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 23:25:04.008786 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 23:25:04.012164 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 23:25:04.018804 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 23:25:04.021935 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 23:25:04.025365 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1812 23:25:04.028769 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1813 23:25:04.035080 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 23:25:04.038617 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 23:25:04.041862 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 23:25:04.048481 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 23:25:04.052170 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:25:04.055545 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:25:04.062217 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:25:04.065231 0 9 4 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
1821 23:25:04.068761 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
1822 23:25:04.075286 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 23:25:04.078868 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 23:25:04.082103 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 23:25:04.088945 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 23:25:04.091908 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 23:25:04.095346 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1828 23:25:04.102183 0 10 4 | B1->B0 | 2929 3333 | 0 1 | (0 0) (1 0)
1829 23:25:04.105387 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:25:04.108881 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 23:25:04.112232 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 23:25:04.118744 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:25:04.122089 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:25:04.125502 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:25:04.132525 0 11 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1836 23:25:04.135467 0 11 4 | B1->B0 | 3535 2d2d | 0 0 | (0 0) (0 0)
1837 23:25:04.138915 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1838 23:25:04.145359 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 23:25:04.148892 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 23:25:04.152349 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 23:25:04.158742 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 23:25:04.162348 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 23:25:04.165517 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1844 23:25:04.171971 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1845 23:25:04.175644 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1846 23:25:04.179106 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 23:25:04.185728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 23:25:04.188731 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 23:25:04.192114 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 23:25:04.198672 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 23:25:04.202296 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 23:25:04.205619 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 23:25:04.208963 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 23:25:04.215696 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 23:25:04.218789 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 23:25:04.222189 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 23:25:04.228738 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 23:25:04.232215 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 23:25:04.235542 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1860 23:25:04.242145 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1861 23:25:04.245647 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 23:25:04.249117 Total UI for P1: 0, mck2ui 16
1863 23:25:04.252124 best dqsien dly found for B0: ( 0, 14, 2)
1864 23:25:04.255656 Total UI for P1: 0, mck2ui 16
1865 23:25:04.259045 best dqsien dly found for B1: ( 0, 14, 2)
1866 23:25:04.262239 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1867 23:25:04.265539 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1868 23:25:04.265637
1869 23:25:04.269060 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1870 23:25:04.272330 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1871 23:25:04.275450 [Gating] SW calibration Done
1872 23:25:04.275534 ==
1873 23:25:04.279061 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 23:25:04.282144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 23:25:04.282251 ==
1876 23:25:04.285544 RX Vref Scan: 0
1877 23:25:04.285657
1878 23:25:04.288926 RX Vref 0 -> 0, step: 1
1879 23:25:04.289007
1880 23:25:04.289071 RX Delay -130 -> 252, step: 16
1881 23:25:04.295381 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1882 23:25:04.299062 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1883 23:25:04.302219 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1884 23:25:04.305671 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1885 23:25:04.308752 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1886 23:25:04.315989 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1887 23:25:04.318982 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1888 23:25:04.322200 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1889 23:25:04.325734 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1890 23:25:04.329138 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1891 23:25:04.335723 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1892 23:25:04.339271 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1893 23:25:04.342222 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1894 23:25:04.345697 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1895 23:25:04.349225 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1896 23:25:04.355674 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1897 23:25:04.355765 ==
1898 23:25:04.359107 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 23:25:04.362551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1900 23:25:04.362635 ==
1901 23:25:04.362707 DQS Delay:
1902 23:25:04.365966 DQS0 = 0, DQS1 = 0
1903 23:25:04.366042 DQM Delay:
1904 23:25:04.369304 DQM0 = 93, DQM1 = 88
1905 23:25:04.369388 DQ Delay:
1906 23:25:04.372427 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1907 23:25:04.375998 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1908 23:25:04.379163 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1909 23:25:04.382419 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1910 23:25:04.382496
1911 23:25:04.382575
1912 23:25:04.382684 ==
1913 23:25:04.385794 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 23:25:04.389010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 23:25:04.389089 ==
1916 23:25:04.392492
1917 23:25:04.392574
1918 23:25:04.392641 TX Vref Scan disable
1919 23:25:04.395838 == TX Byte 0 ==
1920 23:25:04.399642 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1921 23:25:04.402674 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1922 23:25:04.406042 == TX Byte 1 ==
1923 23:25:04.409369 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1924 23:25:04.412593 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1925 23:25:04.412717 ==
1926 23:25:04.416080 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 23:25:04.422538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 23:25:04.422635 ==
1929 23:25:04.434529 TX Vref=22, minBit 3, minWin=26, winSum=440
1930 23:25:04.437694 TX Vref=24, minBit 1, minWin=27, winSum=447
1931 23:25:04.441046 TX Vref=26, minBit 1, minWin=27, winSum=456
1932 23:25:04.444328 TX Vref=28, minBit 1, minWin=27, winSum=454
1933 23:25:04.447407 TX Vref=30, minBit 4, minWin=27, winSum=455
1934 23:25:04.454275 TX Vref=32, minBit 1, minWin=27, winSum=453
1935 23:25:04.457903 [TxChooseVref] Worse bit 1, Min win 27, Win sum 456, Final Vref 26
1936 23:25:04.457993
1937 23:25:04.460891 Final TX Range 1 Vref 26
1938 23:25:04.460978
1939 23:25:04.461065 ==
1940 23:25:04.464300 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 23:25:04.467658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 23:25:04.467744 ==
1943 23:25:04.467832
1944 23:25:04.471020
1945 23:25:04.471106 TX Vref Scan disable
1946 23:25:04.474523 == TX Byte 0 ==
1947 23:25:04.477542 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1948 23:25:04.480912 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1949 23:25:04.484252 == TX Byte 1 ==
1950 23:25:04.487867 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1951 23:25:04.491249 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1952 23:25:04.494226
1953 23:25:04.494313 [DATLAT]
1954 23:25:04.494400 Freq=800, CH1 RK1
1955 23:25:04.494482
1956 23:25:04.497593 DATLAT Default: 0xa
1957 23:25:04.497678 0, 0xFFFF, sum = 0
1958 23:25:04.501038 1, 0xFFFF, sum = 0
1959 23:25:04.501125 2, 0xFFFF, sum = 0
1960 23:25:04.504196 3, 0xFFFF, sum = 0
1961 23:25:04.504282 4, 0xFFFF, sum = 0
1962 23:25:04.507664 5, 0xFFFF, sum = 0
1963 23:25:04.507754 6, 0xFFFF, sum = 0
1964 23:25:04.511043 7, 0xFFFF, sum = 0
1965 23:25:04.514499 8, 0xFFFF, sum = 0
1966 23:25:04.514585 9, 0x0, sum = 1
1967 23:25:04.514674 10, 0x0, sum = 2
1968 23:25:04.517957 11, 0x0, sum = 3
1969 23:25:04.518043 12, 0x0, sum = 4
1970 23:25:04.521077 best_step = 10
1971 23:25:04.521155
1972 23:25:04.521219 ==
1973 23:25:04.524415 Dram Type= 6, Freq= 0, CH_1, rank 1
1974 23:25:04.527574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1975 23:25:04.527660 ==
1976 23:25:04.531035 RX Vref Scan: 0
1977 23:25:04.531113
1978 23:25:04.531184 RX Vref 0 -> 0, step: 1
1979 23:25:04.531251
1980 23:25:04.534366 RX Delay -79 -> 252, step: 8
1981 23:25:04.540904 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1982 23:25:04.544298 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1983 23:25:04.547642 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1984 23:25:04.551294 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1985 23:25:04.554357 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1986 23:25:04.557754 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1987 23:25:04.564610 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1988 23:25:04.567675 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1989 23:25:04.571146 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1990 23:25:04.574469 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1991 23:25:04.577923 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
1992 23:25:04.584496 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
1993 23:25:04.587965 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1994 23:25:04.590904 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1995 23:25:04.594302 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1996 23:25:04.597937 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1997 23:25:04.598023 ==
1998 23:25:04.601171 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 23:25:04.607984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 23:25:04.608071 ==
2001 23:25:04.608174 DQS Delay:
2002 23:25:04.611389 DQS0 = 0, DQS1 = 0
2003 23:25:04.611475 DQM Delay:
2004 23:25:04.611562 DQM0 = 97, DQM1 = 91
2005 23:25:04.614349 DQ Delay:
2006 23:25:04.617767 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2007 23:25:04.621130 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2008 23:25:04.624464 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2009 23:25:04.627687 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2010 23:25:04.627765
2011 23:25:04.627837
2012 23:25:04.634385 [DQSOSCAuto] RK1, (LSB)MR18= 0x430d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
2013 23:25:04.637597 CH1 RK1: MR19=606, MR18=430D
2014 23:25:04.644421 CH1_RK1: MR19=0x606, MR18=0x430D, DQSOSC=393, MR23=63, INC=95, DEC=63
2015 23:25:04.647832 [RxdqsGatingPostProcess] freq 800
2016 23:25:04.650992 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2017 23:25:04.654359 Pre-setting of DQS Precalculation
2018 23:25:04.661369 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2019 23:25:04.667858 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2020 23:25:04.674533 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2021 23:25:04.674643
2022 23:25:04.674742
2023 23:25:04.677713 [Calibration Summary] 1600 Mbps
2024 23:25:04.677791 CH 0, Rank 0
2025 23:25:04.681177 SW Impedance : PASS
2026 23:25:04.684606 DUTY Scan : NO K
2027 23:25:04.684678 ZQ Calibration : PASS
2028 23:25:04.687734 Jitter Meter : NO K
2029 23:25:04.691261 CBT Training : PASS
2030 23:25:04.691344 Write leveling : PASS
2031 23:25:04.694756 RX DQS gating : PASS
2032 23:25:04.697848 RX DQ/DQS(RDDQC) : PASS
2033 23:25:04.697924 TX DQ/DQS : PASS
2034 23:25:04.701231 RX DATLAT : PASS
2035 23:25:04.704437 RX DQ/DQS(Engine): PASS
2036 23:25:04.704509 TX OE : NO K
2037 23:25:04.704570 All Pass.
2038 23:25:04.707950
2039 23:25:04.708022 CH 0, Rank 1
2040 23:25:04.711401 SW Impedance : PASS
2041 23:25:04.711484 DUTY Scan : NO K
2042 23:25:04.714749 ZQ Calibration : PASS
2043 23:25:04.714832 Jitter Meter : NO K
2044 23:25:04.717905 CBT Training : PASS
2045 23:25:04.721481 Write leveling : PASS
2046 23:25:04.721566 RX DQS gating : PASS
2047 23:25:04.724517 RX DQ/DQS(RDDQC) : PASS
2048 23:25:04.727977 TX DQ/DQS : PASS
2049 23:25:04.728070 RX DATLAT : PASS
2050 23:25:04.731231 RX DQ/DQS(Engine): PASS
2051 23:25:04.734618 TX OE : NO K
2052 23:25:04.734726 All Pass.
2053 23:25:04.734820
2054 23:25:04.734908 CH 1, Rank 0
2055 23:25:04.737927 SW Impedance : PASS
2056 23:25:04.741444 DUTY Scan : NO K
2057 23:25:04.741545 ZQ Calibration : PASS
2058 23:25:04.744694 Jitter Meter : NO K
2059 23:25:04.744795 CBT Training : PASS
2060 23:25:04.748264 Write leveling : PASS
2061 23:25:04.751343 RX DQS gating : PASS
2062 23:25:04.751432 RX DQ/DQS(RDDQC) : PASS
2063 23:25:04.754917 TX DQ/DQS : PASS
2064 23:25:04.758307 RX DATLAT : PASS
2065 23:25:04.758397 RX DQ/DQS(Engine): PASS
2066 23:25:04.761667 TX OE : NO K
2067 23:25:04.761761 All Pass.
2068 23:25:04.761826
2069 23:25:04.765127 CH 1, Rank 1
2070 23:25:04.765205 SW Impedance : PASS
2071 23:25:04.768391 DUTY Scan : NO K
2072 23:25:04.771790 ZQ Calibration : PASS
2073 23:25:04.771894 Jitter Meter : NO K
2074 23:25:04.774884 CBT Training : PASS
2075 23:25:04.778692 Write leveling : PASS
2076 23:25:04.778796 RX DQS gating : PASS
2077 23:25:04.782084 RX DQ/DQS(RDDQC) : PASS
2078 23:25:04.782168 TX DQ/DQS : PASS
2079 23:25:04.785148 RX DATLAT : PASS
2080 23:25:04.788569 RX DQ/DQS(Engine): PASS
2081 23:25:04.788661 TX OE : NO K
2082 23:25:04.791696 All Pass.
2083 23:25:04.791800
2084 23:25:04.791894 DramC Write-DBI off
2085 23:25:04.795077 PER_BANK_REFRESH: Hybrid Mode
2086 23:25:04.798594 TX_TRACKING: ON
2087 23:25:04.802004 [GetDramInforAfterCalByMRR] Vendor 6.
2088 23:25:04.805089 [GetDramInforAfterCalByMRR] Revision 606.
2089 23:25:04.808322 [GetDramInforAfterCalByMRR] Revision 2 0.
2090 23:25:04.808435 MR0 0x3b3b
2091 23:25:04.808533 MR8 0x5151
2092 23:25:04.812074 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2093 23:25:04.815256
2094 23:25:04.815361 MR0 0x3b3b
2095 23:25:04.815457 MR8 0x5151
2096 23:25:04.818425 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2097 23:25:04.818535
2098 23:25:04.828573 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2099 23:25:04.832003 [FAST_K] Save calibration result to emmc
2100 23:25:04.835074 [FAST_K] Save calibration result to emmc
2101 23:25:04.838551 dram_init: config_dvfs: 1
2102 23:25:04.841613 dramc_set_vcore_voltage set vcore to 662500
2103 23:25:04.845133 Read voltage for 1200, 2
2104 23:25:04.845239 Vio18 = 0
2105 23:25:04.845349 Vcore = 662500
2106 23:25:04.848568 Vdram = 0
2107 23:25:04.848671 Vddq = 0
2108 23:25:04.848768 Vmddr = 0
2109 23:25:04.854973 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2110 23:25:04.858592 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2111 23:25:04.861735 MEM_TYPE=3, freq_sel=15
2112 23:25:04.865126 sv_algorithm_assistance_LP4_1600
2113 23:25:04.868360 ============ PULL DRAM RESETB DOWN ============
2114 23:25:04.871989 ========== PULL DRAM RESETB DOWN end =========
2115 23:25:04.878451 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2116 23:25:04.882004 ===================================
2117 23:25:04.882116 LPDDR4 DRAM CONFIGURATION
2118 23:25:04.885177 ===================================
2119 23:25:04.888480 EX_ROW_EN[0] = 0x0
2120 23:25:04.892092 EX_ROW_EN[1] = 0x0
2121 23:25:04.892193 LP4Y_EN = 0x0
2122 23:25:04.895237 WORK_FSP = 0x0
2123 23:25:04.895341 WL = 0x4
2124 23:25:04.898864 RL = 0x4
2125 23:25:04.898975 BL = 0x2
2126 23:25:04.901922 RPST = 0x0
2127 23:25:04.902025 RD_PRE = 0x0
2128 23:25:04.905475 WR_PRE = 0x1
2129 23:25:04.905583 WR_PST = 0x0
2130 23:25:04.908852 DBI_WR = 0x0
2131 23:25:04.908954 DBI_RD = 0x0
2132 23:25:04.911908 OTF = 0x1
2133 23:25:04.915390 ===================================
2134 23:25:04.918778 ===================================
2135 23:25:04.918882 ANA top config
2136 23:25:04.922055 ===================================
2137 23:25:04.925456 DLL_ASYNC_EN = 0
2138 23:25:04.928762 ALL_SLAVE_EN = 0
2139 23:25:04.928876 NEW_RANK_MODE = 1
2140 23:25:04.932161 DLL_IDLE_MODE = 1
2141 23:25:04.935460 LP45_APHY_COMB_EN = 1
2142 23:25:04.938487 TX_ODT_DIS = 1
2143 23:25:04.941920 NEW_8X_MODE = 1
2144 23:25:04.945291 ===================================
2145 23:25:04.948760 ===================================
2146 23:25:04.948863 data_rate = 2400
2147 23:25:04.951859 CKR = 1
2148 23:25:04.955253 DQ_P2S_RATIO = 8
2149 23:25:04.958768 ===================================
2150 23:25:04.961790 CA_P2S_RATIO = 8
2151 23:25:04.965377 DQ_CA_OPEN = 0
2152 23:25:04.968282 DQ_SEMI_OPEN = 0
2153 23:25:04.968399 CA_SEMI_OPEN = 0
2154 23:25:04.972082 CA_FULL_RATE = 0
2155 23:25:04.975334 DQ_CKDIV4_EN = 0
2156 23:25:04.978555 CA_CKDIV4_EN = 0
2157 23:25:04.982058 CA_PREDIV_EN = 0
2158 23:25:04.985248 PH8_DLY = 17
2159 23:25:04.985354 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2160 23:25:04.988566 DQ_AAMCK_DIV = 4
2161 23:25:04.991867 CA_AAMCK_DIV = 4
2162 23:25:04.995514 CA_ADMCK_DIV = 4
2163 23:25:04.998557 DQ_TRACK_CA_EN = 0
2164 23:25:05.002045 CA_PICK = 1200
2165 23:25:05.002152 CA_MCKIO = 1200
2166 23:25:05.005299 MCKIO_SEMI = 0
2167 23:25:05.008810 PLL_FREQ = 2366
2168 23:25:05.011864 DQ_UI_PI_RATIO = 32
2169 23:25:05.015170 CA_UI_PI_RATIO = 0
2170 23:25:05.018742 ===================================
2171 23:25:05.022058 ===================================
2172 23:25:05.025466 memory_type:LPDDR4
2173 23:25:05.025574 GP_NUM : 10
2174 23:25:05.028964 SRAM_EN : 1
2175 23:25:05.029042 MD32_EN : 0
2176 23:25:05.031961 ===================================
2177 23:25:05.035608 [ANA_INIT] >>>>>>>>>>>>>>
2178 23:25:05.038792 <<<<<< [CONFIGURE PHASE]: ANA_TX
2179 23:25:05.042064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2180 23:25:05.045585 ===================================
2181 23:25:05.049026 data_rate = 2400,PCW = 0X5b00
2182 23:25:05.052036 ===================================
2183 23:25:05.055298 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2184 23:25:05.058724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2185 23:25:05.065715 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 23:25:05.069154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2187 23:25:05.072249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2188 23:25:05.075812 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2189 23:25:05.078809 [ANA_INIT] flow start
2190 23:25:05.082440 [ANA_INIT] PLL >>>>>>>>
2191 23:25:05.082544 [ANA_INIT] PLL <<<<<<<<
2192 23:25:05.085815 [ANA_INIT] MIDPI >>>>>>>>
2193 23:25:05.089279 [ANA_INIT] MIDPI <<<<<<<<
2194 23:25:05.092713 [ANA_INIT] DLL >>>>>>>>
2195 23:25:05.092790 [ANA_INIT] DLL <<<<<<<<
2196 23:25:05.095641 [ANA_INIT] flow end
2197 23:25:05.098912 ============ LP4 DIFF to SE enter ============
2198 23:25:05.102247 ============ LP4 DIFF to SE exit ============
2199 23:25:05.105618 [ANA_INIT] <<<<<<<<<<<<<
2200 23:25:05.109019 [Flow] Enable top DCM control >>>>>
2201 23:25:05.112688 [Flow] Enable top DCM control <<<<<
2202 23:25:05.115704 Enable DLL master slave shuffle
2203 23:25:05.119143 ==============================================================
2204 23:25:05.122535 Gating Mode config
2205 23:25:05.129405 ==============================================================
2206 23:25:05.129490 Config description:
2207 23:25:05.139498 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2208 23:25:05.146145 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2209 23:25:05.149416 SELPH_MODE 0: By rank 1: By Phase
2210 23:25:05.155934 ==============================================================
2211 23:25:05.159510 GAT_TRACK_EN = 1
2212 23:25:05.162840 RX_GATING_MODE = 2
2213 23:25:05.165903 RX_GATING_TRACK_MODE = 2
2214 23:25:05.169292 SELPH_MODE = 1
2215 23:25:05.172727 PICG_EARLY_EN = 1
2216 23:25:05.176141 VALID_LAT_VALUE = 1
2217 23:25:05.179557 ==============================================================
2218 23:25:05.182955 Enter into Gating configuration >>>>
2219 23:25:05.186028 Exit from Gating configuration <<<<
2220 23:25:05.189591 Enter into DVFS_PRE_config >>>>>
2221 23:25:05.199409 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2222 23:25:05.202890 Exit from DVFS_PRE_config <<<<<
2223 23:25:05.206277 Enter into PICG configuration >>>>
2224 23:25:05.209608 Exit from PICG configuration <<<<
2225 23:25:05.212954 [RX_INPUT] configuration >>>>>
2226 23:25:05.216408 [RX_INPUT] configuration <<<<<
2227 23:25:05.219456 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2228 23:25:05.226107 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2229 23:25:05.233073 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2230 23:25:05.239518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2231 23:25:05.246390 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2232 23:25:05.249592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2233 23:25:05.256422 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2234 23:25:05.260060 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2235 23:25:05.263221 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2236 23:25:05.266423 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2237 23:25:05.269752 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2238 23:25:05.276247 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2239 23:25:05.279555 ===================================
2240 23:25:05.283112 LPDDR4 DRAM CONFIGURATION
2241 23:25:05.286457 ===================================
2242 23:25:05.286562 EX_ROW_EN[0] = 0x0
2243 23:25:05.289932 EX_ROW_EN[1] = 0x0
2244 23:25:05.290009 LP4Y_EN = 0x0
2245 23:25:05.292871 WORK_FSP = 0x0
2246 23:25:05.292962 WL = 0x4
2247 23:25:05.296321 RL = 0x4
2248 23:25:05.296396 BL = 0x2
2249 23:25:05.299936 RPST = 0x0
2250 23:25:05.300017 RD_PRE = 0x0
2251 23:25:05.303107 WR_PRE = 0x1
2252 23:25:05.303184 WR_PST = 0x0
2253 23:25:05.306281 DBI_WR = 0x0
2254 23:25:05.306361 DBI_RD = 0x0
2255 23:25:05.309817 OTF = 0x1
2256 23:25:05.313091 ===================================
2257 23:25:05.316494 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2258 23:25:05.320004 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2259 23:25:05.326372 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 23:25:05.329661 ===================================
2261 23:25:05.329741 LPDDR4 DRAM CONFIGURATION
2262 23:25:05.332904 ===================================
2263 23:25:05.336559 EX_ROW_EN[0] = 0x10
2264 23:25:05.339906 EX_ROW_EN[1] = 0x0
2265 23:25:05.340012 LP4Y_EN = 0x0
2266 23:25:05.343013 WORK_FSP = 0x0
2267 23:25:05.343121 WL = 0x4
2268 23:25:05.346394 RL = 0x4
2269 23:25:05.346470 BL = 0x2
2270 23:25:05.349931 RPST = 0x0
2271 23:25:05.350007 RD_PRE = 0x0
2272 23:25:05.352976 WR_PRE = 0x1
2273 23:25:05.353051 WR_PST = 0x0
2274 23:25:05.356411 DBI_WR = 0x0
2275 23:25:05.356496 DBI_RD = 0x0
2276 23:25:05.359763 OTF = 0x1
2277 23:25:05.363276 ===================================
2278 23:25:05.370051 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2279 23:25:05.370158 ==
2280 23:25:05.373348 Dram Type= 6, Freq= 0, CH_0, rank 0
2281 23:25:05.376489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2282 23:25:05.376570 ==
2283 23:25:05.380075 [Duty_Offset_Calibration]
2284 23:25:05.380176 B0:2 B1:1 CA:1
2285 23:25:05.380267
2286 23:25:05.383038 [DutyScan_Calibration_Flow] k_type=0
2287 23:25:05.393045
2288 23:25:05.393161 ==CLK 0==
2289 23:25:05.396390 Final CLK duty delay cell = 0
2290 23:25:05.399675 [0] MAX Duty = 5187%(X100), DQS PI = 24
2291 23:25:05.403011 [0] MIN Duty = 4875%(X100), DQS PI = 0
2292 23:25:05.403114 [0] AVG Duty = 5031%(X100)
2293 23:25:05.406345
2294 23:25:05.406430 CH0 CLK Duty spec in!! Max-Min= 312%
2295 23:25:05.412942 [DutyScan_Calibration_Flow] ====Done====
2296 23:25:05.413033
2297 23:25:05.416205 [DutyScan_Calibration_Flow] k_type=1
2298 23:25:05.430692
2299 23:25:05.430808 ==DQS 0 ==
2300 23:25:05.434132 Final DQS duty delay cell = -4
2301 23:25:05.437664 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2302 23:25:05.440939 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2303 23:25:05.444151 [-4] AVG Duty = 4937%(X100)
2304 23:25:05.444255
2305 23:25:05.444357 ==DQS 1 ==
2306 23:25:05.447582 Final DQS duty delay cell = -4
2307 23:25:05.450978 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2308 23:25:05.454354 [-4] MIN Duty = 4844%(X100), DQS PI = 30
2309 23:25:05.457460 [-4] AVG Duty = 4906%(X100)
2310 23:25:05.457544
2311 23:25:05.460776 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2312 23:25:05.460869
2313 23:25:05.464197 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2314 23:25:05.467695 [DutyScan_Calibration_Flow] ====Done====
2315 23:25:05.467774
2316 23:25:05.470683 [DutyScan_Calibration_Flow] k_type=3
2317 23:25:05.487872
2318 23:25:05.487955 ==DQM 0 ==
2319 23:25:05.491261 Final DQM duty delay cell = 0
2320 23:25:05.494817 [0] MAX Duty = 5156%(X100), DQS PI = 28
2321 23:25:05.498005 [0] MIN Duty = 4907%(X100), DQS PI = 60
2322 23:25:05.498084 [0] AVG Duty = 5031%(X100)
2323 23:25:05.501115
2324 23:25:05.501223 ==DQM 1 ==
2325 23:25:05.504836 Final DQM duty delay cell = 0
2326 23:25:05.508021 [0] MAX Duty = 5093%(X100), DQS PI = 0
2327 23:25:05.511119 [0] MIN Duty = 5031%(X100), DQS PI = 14
2328 23:25:05.511196 [0] AVG Duty = 5062%(X100)
2329 23:25:05.514584
2330 23:25:05.518018 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2331 23:25:05.518102
2332 23:25:05.521282 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2333 23:25:05.524687 [DutyScan_Calibration_Flow] ====Done====
2334 23:25:05.524804
2335 23:25:05.527696 [DutyScan_Calibration_Flow] k_type=2
2336 23:25:05.544403
2337 23:25:05.544515 ==DQ 0 ==
2338 23:25:05.547827 Final DQ duty delay cell = 0
2339 23:25:05.550749 [0] MAX Duty = 5062%(X100), DQS PI = 32
2340 23:25:05.554134 [0] MIN Duty = 4875%(X100), DQS PI = 62
2341 23:25:05.554243 [0] AVG Duty = 4968%(X100)
2342 23:25:05.557612
2343 23:25:05.557717 ==DQ 1 ==
2344 23:25:05.560877 Final DQ duty delay cell = 0
2345 23:25:05.564183 [0] MAX Duty = 5093%(X100), DQS PI = 24
2346 23:25:05.567473 [0] MIN Duty = 4938%(X100), DQS PI = 36
2347 23:25:05.567552 [0] AVG Duty = 5015%(X100)
2348 23:25:05.567617
2349 23:25:05.571069 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2350 23:25:05.574416
2351 23:25:05.577455 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2352 23:25:05.581008 [DutyScan_Calibration_Flow] ====Done====
2353 23:25:05.581086 ==
2354 23:25:05.584219 Dram Type= 6, Freq= 0, CH_1, rank 0
2355 23:25:05.587689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2356 23:25:05.587800 ==
2357 23:25:05.591158 [Duty_Offset_Calibration]
2358 23:25:05.591264 B0:1 B1:0 CA:0
2359 23:25:05.591357
2360 23:25:05.594200 [DutyScan_Calibration_Flow] k_type=0
2361 23:25:05.603631
2362 23:25:05.603718 ==CLK 0==
2363 23:25:05.607004 Final CLK duty delay cell = -4
2364 23:25:05.610050 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2365 23:25:05.613573 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2366 23:25:05.616941 [-4] AVG Duty = 4953%(X100)
2367 23:25:05.617020
2368 23:25:05.620302 CH1 CLK Duty spec in!! Max-Min= 93%
2369 23:25:05.623496 [DutyScan_Calibration_Flow] ====Done====
2370 23:25:05.623598
2371 23:25:05.626614 [DutyScan_Calibration_Flow] k_type=1
2372 23:25:05.643079
2373 23:25:05.643168 ==DQS 0 ==
2374 23:25:05.646517 Final DQS duty delay cell = 0
2375 23:25:05.650153 [0] MAX Duty = 5094%(X100), DQS PI = 26
2376 23:25:05.653297 [0] MIN Duty = 4875%(X100), DQS PI = 0
2377 23:25:05.653373 [0] AVG Duty = 4984%(X100)
2378 23:25:05.656455
2379 23:25:05.656538 ==DQS 1 ==
2380 23:25:05.659580 Final DQS duty delay cell = 0
2381 23:25:05.662913 [0] MAX Duty = 5187%(X100), DQS PI = 18
2382 23:25:05.666220 [0] MIN Duty = 4969%(X100), DQS PI = 8
2383 23:25:05.669572 [0] AVG Duty = 5078%(X100)
2384 23:25:05.669682
2385 23:25:05.672878 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2386 23:25:05.672962
2387 23:25:05.676103 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2388 23:25:05.679637 [DutyScan_Calibration_Flow] ====Done====
2389 23:25:05.679726
2390 23:25:05.683181 [DutyScan_Calibration_Flow] k_type=3
2391 23:25:05.699591
2392 23:25:05.699742 ==DQM 0 ==
2393 23:25:05.702993 Final DQM duty delay cell = 0
2394 23:25:05.706376 [0] MAX Duty = 5156%(X100), DQS PI = 6
2395 23:25:05.709678 [0] MIN Duty = 5031%(X100), DQS PI = 0
2396 23:25:05.709786 [0] AVG Duty = 5093%(X100)
2397 23:25:05.709886
2398 23:25:05.713145 ==DQM 1 ==
2399 23:25:05.716618 Final DQM duty delay cell = 0
2400 23:25:05.719666 [0] MAX Duty = 5031%(X100), DQS PI = 26
2401 23:25:05.723221 [0] MIN Duty = 4875%(X100), DQS PI = 38
2402 23:25:05.723327 [0] AVG Duty = 4953%(X100)
2403 23:25:05.723424
2404 23:25:05.729728 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2405 23:25:05.729818
2406 23:25:05.732961 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2407 23:25:05.736491 [DutyScan_Calibration_Flow] ====Done====
2408 23:25:05.736580
2409 23:25:05.739672 [DutyScan_Calibration_Flow] k_type=2
2410 23:25:05.755500
2411 23:25:05.755608 ==DQ 0 ==
2412 23:25:05.759081 Final DQ duty delay cell = -4
2413 23:25:05.762387 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2414 23:25:05.765766 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2415 23:25:05.768722 [-4] AVG Duty = 4984%(X100)
2416 23:25:05.768827
2417 23:25:05.768924 ==DQ 1 ==
2418 23:25:05.772394 Final DQ duty delay cell = 0
2419 23:25:05.775474 [0] MAX Duty = 5125%(X100), DQS PI = 20
2420 23:25:05.778960 [0] MIN Duty = 4969%(X100), DQS PI = 10
2421 23:25:05.779069 [0] AVG Duty = 5047%(X100)
2422 23:25:05.782276
2423 23:25:05.785498 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2424 23:25:05.785607
2425 23:25:05.788921 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2426 23:25:05.792119 [DutyScan_Calibration_Flow] ====Done====
2427 23:25:05.795437 nWR fixed to 30
2428 23:25:05.795552 [ModeRegInit_LP4] CH0 RK0
2429 23:25:05.798874 [ModeRegInit_LP4] CH0 RK1
2430 23:25:05.802112 [ModeRegInit_LP4] CH1 RK0
2431 23:25:05.802221 [ModeRegInit_LP4] CH1 RK1
2432 23:25:05.805762 match AC timing 7
2433 23:25:05.809111 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2434 23:25:05.812351 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2435 23:25:05.819191 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2436 23:25:05.822273 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2437 23:25:05.829022 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2438 23:25:05.829148 ==
2439 23:25:05.832479 Dram Type= 6, Freq= 0, CH_0, rank 0
2440 23:25:05.835877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2441 23:25:05.836004 ==
2442 23:25:05.842343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2443 23:25:05.845616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2444 23:25:05.855564 [CA 0] Center 39 (8~70) winsize 63
2445 23:25:05.858971 [CA 1] Center 39 (8~70) winsize 63
2446 23:25:05.862395 [CA 2] Center 35 (5~66) winsize 62
2447 23:25:05.865850 [CA 3] Center 34 (4~65) winsize 62
2448 23:25:05.868873 [CA 4] Center 33 (3~64) winsize 62
2449 23:25:05.872400 [CA 5] Center 32 (3~62) winsize 60
2450 23:25:05.872482
2451 23:25:05.875784 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2452 23:25:05.875867
2453 23:25:05.879239 [CATrainingPosCal] consider 1 rank data
2454 23:25:05.882381 u2DelayCellTimex100 = 270/100 ps
2455 23:25:05.885520 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2456 23:25:05.888932 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2457 23:25:05.895473 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2458 23:25:05.898895 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2459 23:25:05.902214 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2460 23:25:05.905667 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2461 23:25:05.905748
2462 23:25:05.908985 CA PerBit enable=1, Macro0, CA PI delay=32
2463 23:25:05.909059
2464 23:25:05.912175 [CBTSetCACLKResult] CA Dly = 32
2465 23:25:05.912254 CS Dly: 6 (0~37)
2466 23:25:05.915585 ==
2467 23:25:05.915661 Dram Type= 6, Freq= 0, CH_0, rank 1
2468 23:25:05.922496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2469 23:25:05.922577 ==
2470 23:25:05.925680 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2471 23:25:05.932378 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2472 23:25:05.941425 [CA 0] Center 38 (8~69) winsize 62
2473 23:25:05.944791 [CA 1] Center 38 (8~69) winsize 62
2474 23:25:05.948203 [CA 2] Center 35 (5~66) winsize 62
2475 23:25:05.951514 [CA 3] Center 34 (4~65) winsize 62
2476 23:25:05.954881 [CA 4] Center 33 (3~64) winsize 62
2477 23:25:05.958228 [CA 5] Center 32 (3~62) winsize 60
2478 23:25:05.958331
2479 23:25:05.961630 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2480 23:25:05.961748
2481 23:25:05.965078 [CATrainingPosCal] consider 2 rank data
2482 23:25:05.968590 u2DelayCellTimex100 = 270/100 ps
2483 23:25:05.971644 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2484 23:25:05.975083 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2485 23:25:05.978383 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2486 23:25:05.985034 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2487 23:25:05.988339 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2488 23:25:05.991816 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2489 23:25:05.991892
2490 23:25:05.995367 CA PerBit enable=1, Macro0, CA PI delay=32
2491 23:25:05.995470
2492 23:25:05.998516 [CBTSetCACLKResult] CA Dly = 32
2493 23:25:05.998628 CS Dly: 6 (0~38)
2494 23:25:05.998722
2495 23:25:06.002008 ----->DramcWriteLeveling(PI) begin...
2496 23:25:06.002112 ==
2497 23:25:06.005253 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 23:25:06.011641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 23:25:06.011722 ==
2500 23:25:06.015141 Write leveling (Byte 0): 33 => 33
2501 23:25:06.018615 Write leveling (Byte 1): 27 => 27
2502 23:25:06.018730 DramcWriteLeveling(PI) end<-----
2503 23:25:06.018841
2504 23:25:06.021591 ==
2505 23:25:06.024980 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 23:25:06.028354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 23:25:06.028469 ==
2508 23:25:06.031797 [Gating] SW mode calibration
2509 23:25:06.038183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2510 23:25:06.041586 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2511 23:25:06.048383 0 15 0 | B1->B0 | 2323 3232 | 1 0 | (1 1) (0 0)
2512 23:25:06.051680 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2513 23:25:06.054887 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 23:25:06.061545 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 23:25:06.065166 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 23:25:06.068224 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 23:25:06.074829 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2518 23:25:06.078294 0 15 28 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
2519 23:25:06.081531 1 0 0 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
2520 23:25:06.088210 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 23:25:06.091277 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 23:25:06.094731 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 23:25:06.101406 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 23:25:06.104654 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 23:25:06.108108 1 0 24 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
2526 23:25:06.114706 1 0 28 | B1->B0 | 2828 4444 | 0 0 | (0 0) (0 0)
2527 23:25:06.118107 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2528 23:25:06.121520 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 23:25:06.128333 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 23:25:06.131455 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 23:25:06.135030 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 23:25:06.138070 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 23:25:06.144600 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 23:25:06.148124 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2535 23:25:06.151231 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2536 23:25:06.158009 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2537 23:25:06.161483 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 23:25:06.164680 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 23:25:06.171506 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 23:25:06.174588 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 23:25:06.178013 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 23:25:06.184789 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 23:25:06.188094 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 23:25:06.191478 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 23:25:06.198193 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 23:25:06.201507 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 23:25:06.204859 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 23:25:06.211421 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 23:25:06.214953 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 23:25:06.218247 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2551 23:25:06.221502 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2552 23:25:06.224846 Total UI for P1: 0, mck2ui 16
2553 23:25:06.228130 best dqsien dly found for B0: ( 1, 3, 28)
2554 23:25:06.235087 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 23:25:06.238187 Total UI for P1: 0, mck2ui 16
2556 23:25:06.241649 best dqsien dly found for B1: ( 1, 4, 0)
2557 23:25:06.244841 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2558 23:25:06.248378 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2559 23:25:06.248483
2560 23:25:06.251785 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2561 23:25:06.255191 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2562 23:25:06.258247 [Gating] SW calibration Done
2563 23:25:06.258349 ==
2564 23:25:06.261720 Dram Type= 6, Freq= 0, CH_0, rank 0
2565 23:25:06.264745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2566 23:25:06.264881 ==
2567 23:25:06.268206 RX Vref Scan: 0
2568 23:25:06.268335
2569 23:25:06.268448 RX Vref 0 -> 0, step: 1
2570 23:25:06.268564
2571 23:25:06.271508 RX Delay -40 -> 252, step: 8
2572 23:25:06.274850 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2573 23:25:06.281748 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2574 23:25:06.284938 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2575 23:25:06.288344 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2576 23:25:06.291762 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2577 23:25:06.294841 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2578 23:25:06.301632 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2579 23:25:06.304920 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2580 23:25:06.308300 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2581 23:25:06.311569 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2582 23:25:06.315130 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2583 23:25:06.321631 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2584 23:25:06.324941 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2585 23:25:06.328425 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2586 23:25:06.331699 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2587 23:25:06.335114 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2588 23:25:06.335242 ==
2589 23:25:06.338495 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 23:25:06.344973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 23:25:06.345098 ==
2592 23:25:06.345212 DQS Delay:
2593 23:25:06.348359 DQS0 = 0, DQS1 = 0
2594 23:25:06.348484 DQM Delay:
2595 23:25:06.351689 DQM0 = 121, DQM1 = 113
2596 23:25:06.351816 DQ Delay:
2597 23:25:06.354884 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2598 23:25:06.358186 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2599 23:25:06.361703 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2600 23:25:06.364866 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2601 23:25:06.364976
2602 23:25:06.365073
2603 23:25:06.365167 ==
2604 23:25:06.368275 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 23:25:06.375132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 23:25:06.375242 ==
2607 23:25:06.375339
2608 23:25:06.375433
2609 23:25:06.375524 TX Vref Scan disable
2610 23:25:06.378330 == TX Byte 0 ==
2611 23:25:06.381749 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2612 23:25:06.384788 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2613 23:25:06.388252 == TX Byte 1 ==
2614 23:25:06.391699 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2615 23:25:06.394771 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2616 23:25:06.398065 ==
2617 23:25:06.401687 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 23:25:06.405035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 23:25:06.405143 ==
2620 23:25:06.416645 TX Vref=22, minBit 0, minWin=25, winSum=413
2621 23:25:06.419682 TX Vref=24, minBit 0, minWin=25, winSum=415
2622 23:25:06.423131 TX Vref=26, minBit 12, minWin=25, winSum=424
2623 23:25:06.426351 TX Vref=28, minBit 4, minWin=26, winSum=428
2624 23:25:06.429531 TX Vref=30, minBit 0, minWin=26, winSum=425
2625 23:25:06.436188 TX Vref=32, minBit 1, minWin=26, winSum=428
2626 23:25:06.439687 [TxChooseVref] Worse bit 4, Min win 26, Win sum 428, Final Vref 28
2627 23:25:06.439801
2628 23:25:06.443113 Final TX Range 1 Vref 28
2629 23:25:06.443226
2630 23:25:06.443325 ==
2631 23:25:06.446224 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 23:25:06.449607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 23:25:06.449717 ==
2634 23:25:06.453060
2635 23:25:06.453191
2636 23:25:06.453307 TX Vref Scan disable
2637 23:25:06.456332 == TX Byte 0 ==
2638 23:25:06.459606 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2639 23:25:06.466194 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2640 23:25:06.466280 == TX Byte 1 ==
2641 23:25:06.469682 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2642 23:25:06.476085 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2643 23:25:06.476219
2644 23:25:06.476347 [DATLAT]
2645 23:25:06.476461 Freq=1200, CH0 RK0
2646 23:25:06.476573
2647 23:25:06.479629 DATLAT Default: 0xd
2648 23:25:06.479751 0, 0xFFFF, sum = 0
2649 23:25:06.482991 1, 0xFFFF, sum = 0
2650 23:25:06.483120 2, 0xFFFF, sum = 0
2651 23:25:06.486258 3, 0xFFFF, sum = 0
2652 23:25:06.486390 4, 0xFFFF, sum = 0
2653 23:25:06.489590 5, 0xFFFF, sum = 0
2654 23:25:06.492975 6, 0xFFFF, sum = 0
2655 23:25:06.493108 7, 0xFFFF, sum = 0
2656 23:25:06.496528 8, 0xFFFF, sum = 0
2657 23:25:06.496656 9, 0xFFFF, sum = 0
2658 23:25:06.499552 10, 0xFFFF, sum = 0
2659 23:25:06.499642 11, 0xFFFF, sum = 0
2660 23:25:06.502842 12, 0x0, sum = 1
2661 23:25:06.502948 13, 0x0, sum = 2
2662 23:25:06.506464 14, 0x0, sum = 3
2663 23:25:06.506561 15, 0x0, sum = 4
2664 23:25:06.506640 best_step = 13
2665 23:25:06.506748
2666 23:25:06.509885 ==
2667 23:25:06.513242 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 23:25:06.516122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 23:25:06.516247 ==
2670 23:25:06.516369 RX Vref Scan: 1
2671 23:25:06.516482
2672 23:25:06.519530 Set Vref Range= 32 -> 127
2673 23:25:06.519654
2674 23:25:06.523094 RX Vref 32 -> 127, step: 1
2675 23:25:06.523217
2676 23:25:06.526547 RX Delay -13 -> 252, step: 4
2677 23:25:06.526667
2678 23:25:06.529525 Set Vref, RX VrefLevel [Byte0]: 32
2679 23:25:06.532927 [Byte1]: 32
2680 23:25:06.533049
2681 23:25:06.536337 Set Vref, RX VrefLevel [Byte0]: 33
2682 23:25:06.539796 [Byte1]: 33
2683 23:25:06.539917
2684 23:25:06.542949 Set Vref, RX VrefLevel [Byte0]: 34
2685 23:25:06.546423 [Byte1]: 34
2686 23:25:06.550808
2687 23:25:06.550928 Set Vref, RX VrefLevel [Byte0]: 35
2688 23:25:06.553769 [Byte1]: 35
2689 23:25:06.558388
2690 23:25:06.558522 Set Vref, RX VrefLevel [Byte0]: 36
2691 23:25:06.561623 [Byte1]: 36
2692 23:25:06.566183
2693 23:25:06.566293 Set Vref, RX VrefLevel [Byte0]: 37
2694 23:25:06.569703 [Byte1]: 37
2695 23:25:06.574380
2696 23:25:06.574463 Set Vref, RX VrefLevel [Byte0]: 38
2697 23:25:06.577838 [Byte1]: 38
2698 23:25:06.582133
2699 23:25:06.582239 Set Vref, RX VrefLevel [Byte0]: 39
2700 23:25:06.585551 [Byte1]: 39
2701 23:25:06.590143
2702 23:25:06.590251 Set Vref, RX VrefLevel [Byte0]: 40
2703 23:25:06.593231 [Byte1]: 40
2704 23:25:06.598039
2705 23:25:06.598129 Set Vref, RX VrefLevel [Byte0]: 41
2706 23:25:06.601267 [Byte1]: 41
2707 23:25:06.605888
2708 23:25:06.606011 Set Vref, RX VrefLevel [Byte0]: 42
2709 23:25:06.609018 [Byte1]: 42
2710 23:25:06.613599
2711 23:25:06.613726 Set Vref, RX VrefLevel [Byte0]: 43
2712 23:25:06.616985 [Byte1]: 43
2713 23:25:06.621608
2714 23:25:06.621735 Set Vref, RX VrefLevel [Byte0]: 44
2715 23:25:06.624983 [Byte1]: 44
2716 23:25:06.629373
2717 23:25:06.629456 Set Vref, RX VrefLevel [Byte0]: 45
2718 23:25:06.632868 [Byte1]: 45
2719 23:25:06.637542
2720 23:25:06.637643 Set Vref, RX VrefLevel [Byte0]: 46
2721 23:25:06.640726 [Byte1]: 46
2722 23:25:06.645463
2723 23:25:06.645543 Set Vref, RX VrefLevel [Byte0]: 47
2724 23:25:06.648709 [Byte1]: 47
2725 23:25:06.653164
2726 23:25:06.653241 Set Vref, RX VrefLevel [Byte0]: 48
2727 23:25:06.656654 [Byte1]: 48
2728 23:25:06.660988
2729 23:25:06.661067 Set Vref, RX VrefLevel [Byte0]: 49
2730 23:25:06.664301 [Byte1]: 49
2731 23:25:06.669007
2732 23:25:06.669083 Set Vref, RX VrefLevel [Byte0]: 50
2733 23:25:06.672342 [Byte1]: 50
2734 23:25:06.676679
2735 23:25:06.676764 Set Vref, RX VrefLevel [Byte0]: 51
2736 23:25:06.680045 [Byte1]: 51
2737 23:25:06.684716
2738 23:25:06.684800 Set Vref, RX VrefLevel [Byte0]: 52
2739 23:25:06.688158 [Byte1]: 52
2740 23:25:06.692390
2741 23:25:06.692475 Set Vref, RX VrefLevel [Byte0]: 53
2742 23:25:06.696044 [Byte1]: 53
2743 23:25:06.700684
2744 23:25:06.700767 Set Vref, RX VrefLevel [Byte0]: 54
2745 23:25:06.703690 [Byte1]: 54
2746 23:25:06.708308
2747 23:25:06.708393 Set Vref, RX VrefLevel [Byte0]: 55
2748 23:25:06.711894 [Byte1]: 55
2749 23:25:06.716485
2750 23:25:06.716568 Set Vref, RX VrefLevel [Byte0]: 56
2751 23:25:06.719658 [Byte1]: 56
2752 23:25:06.724451
2753 23:25:06.724535 Set Vref, RX VrefLevel [Byte0]: 57
2754 23:25:06.727378 [Byte1]: 57
2755 23:25:06.732071
2756 23:25:06.732159 Set Vref, RX VrefLevel [Byte0]: 58
2757 23:25:06.735412 [Byte1]: 58
2758 23:25:06.740021
2759 23:25:06.740114 Set Vref, RX VrefLevel [Byte0]: 59
2760 23:25:06.743291 [Byte1]: 59
2761 23:25:06.748018
2762 23:25:06.748103 Set Vref, RX VrefLevel [Byte0]: 60
2763 23:25:06.751207 [Byte1]: 60
2764 23:25:06.755794
2765 23:25:06.755904 Set Vref, RX VrefLevel [Byte0]: 61
2766 23:25:06.758873 [Byte1]: 61
2767 23:25:06.763482
2768 23:25:06.763566 Set Vref, RX VrefLevel [Byte0]: 62
2769 23:25:06.766924 [Byte1]: 62
2770 23:25:06.771378
2771 23:25:06.771464 Set Vref, RX VrefLevel [Byte0]: 63
2772 23:25:06.774985 [Byte1]: 63
2773 23:25:06.779409
2774 23:25:06.782749 Set Vref, RX VrefLevel [Byte0]: 64
2775 23:25:06.785757 [Byte1]: 64
2776 23:25:06.785841
2777 23:25:06.789215 Set Vref, RX VrefLevel [Byte0]: 65
2778 23:25:06.792306 [Byte1]: 65
2779 23:25:06.792391
2780 23:25:06.795807 Set Vref, RX VrefLevel [Byte0]: 66
2781 23:25:06.799357 [Byte1]: 66
2782 23:25:06.803219
2783 23:25:06.803302 Set Vref, RX VrefLevel [Byte0]: 67
2784 23:25:06.806220 [Byte1]: 67
2785 23:25:06.810922
2786 23:25:06.811006 Set Vref, RX VrefLevel [Byte0]: 68
2787 23:25:06.814107 [Byte1]: 68
2788 23:25:06.818936
2789 23:25:06.819053 Set Vref, RX VrefLevel [Byte0]: 69
2790 23:25:06.822419 [Byte1]: 69
2791 23:25:06.826675
2792 23:25:06.826788 Final RX Vref Byte 0 = 55 to rank0
2793 23:25:06.830271 Final RX Vref Byte 1 = 48 to rank0
2794 23:25:06.833413 Final RX Vref Byte 0 = 55 to rank1
2795 23:25:06.836785 Final RX Vref Byte 1 = 48 to rank1==
2796 23:25:06.840246 Dram Type= 6, Freq= 0, CH_0, rank 0
2797 23:25:06.846611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2798 23:25:06.846697 ==
2799 23:25:06.846765 DQS Delay:
2800 23:25:06.846827 DQS0 = 0, DQS1 = 0
2801 23:25:06.850181 DQM Delay:
2802 23:25:06.850265 DQM0 = 120, DQM1 = 111
2803 23:25:06.853387 DQ Delay:
2804 23:25:06.856717 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2805 23:25:06.859873 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2806 23:25:06.863332 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2807 23:25:06.866779 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2808 23:25:06.866891
2809 23:25:06.866984
2810 23:25:06.873694 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2811 23:25:06.876769 CH0 RK0: MR19=404, MR18=140D
2812 23:25:06.883327 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2813 23:25:06.883441
2814 23:25:06.887002 ----->DramcWriteLeveling(PI) begin...
2815 23:25:06.887107 ==
2816 23:25:06.890214 Dram Type= 6, Freq= 0, CH_0, rank 1
2817 23:25:06.893428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2818 23:25:06.896808 ==
2819 23:25:06.896888 Write leveling (Byte 0): 32 => 32
2820 23:25:06.900258 Write leveling (Byte 1): 30 => 30
2821 23:25:06.903440 DramcWriteLeveling(PI) end<-----
2822 23:25:06.903543
2823 23:25:06.903635 ==
2824 23:25:06.906854 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 23:25:06.913269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 23:25:06.913381 ==
2827 23:25:06.913474 [Gating] SW mode calibration
2828 23:25:06.923306 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2829 23:25:06.926816 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2830 23:25:06.933405 0 15 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2831 23:25:06.936817 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 23:25:06.940263 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 23:25:06.943295 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 23:25:06.950322 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 23:25:06.953370 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 23:25:06.956880 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2837 23:25:06.963218 0 15 28 | B1->B0 | 2d2d 2e2e | 1 0 | (1 0) (0 0)
2838 23:25:06.966968 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2839 23:25:06.970289 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 23:25:06.976847 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 23:25:06.980349 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 23:25:06.983478 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 23:25:06.989935 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 23:25:06.993504 1 0 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
2845 23:25:06.996844 1 0 28 | B1->B0 | 3c3c 3b3a | 0 1 | (0 0) (0 0)
2846 23:25:07.003634 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2847 23:25:07.006656 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 23:25:07.009900 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 23:25:07.016852 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 23:25:07.020235 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 23:25:07.023750 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 23:25:07.026606 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2853 23:25:07.033524 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2854 23:25:07.037014 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2855 23:25:07.039878 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 23:25:07.046764 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 23:25:07.049837 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 23:25:07.053220 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 23:25:07.060216 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 23:25:07.063233 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 23:25:07.066791 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 23:25:07.073137 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 23:25:07.076801 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 23:25:07.079981 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 23:25:07.086685 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 23:25:07.090028 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 23:25:07.093244 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 23:25:07.099794 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 23:25:07.103239 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2870 23:25:07.106633 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2871 23:25:07.113446 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 23:25:07.113567 Total UI for P1: 0, mck2ui 16
2873 23:25:07.116994 best dqsien dly found for B0: ( 1, 3, 30)
2874 23:25:07.120217 Total UI for P1: 0, mck2ui 16
2875 23:25:07.123326 best dqsien dly found for B1: ( 1, 3, 30)
2876 23:25:07.126969 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2877 23:25:07.133609 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2878 23:25:07.133719
2879 23:25:07.137005 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2880 23:25:07.140598 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2881 23:25:07.143559 [Gating] SW calibration Done
2882 23:25:07.143670 ==
2883 23:25:07.146767 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 23:25:07.150153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 23:25:07.150283 ==
2886 23:25:07.150399 RX Vref Scan: 0
2887 23:25:07.150509
2888 23:25:07.153521 RX Vref 0 -> 0, step: 1
2889 23:25:07.153639
2890 23:25:07.157111 RX Delay -40 -> 252, step: 8
2891 23:25:07.160101 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2892 23:25:07.163565 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2893 23:25:07.170110 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2894 23:25:07.173466 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2895 23:25:07.176844 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2896 23:25:07.180281 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2897 23:25:07.183661 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2898 23:25:07.190364 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2899 23:25:07.193720 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2900 23:25:07.197161 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2901 23:25:07.200205 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2902 23:25:07.203497 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2903 23:25:07.210315 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2904 23:25:07.213351 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2905 23:25:07.216961 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2906 23:25:07.220277 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2907 23:25:07.220396 ==
2908 23:25:07.223612 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 23:25:07.226915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 23:25:07.230356 ==
2911 23:25:07.230469 DQS Delay:
2912 23:25:07.230562 DQS0 = 0, DQS1 = 0
2913 23:25:07.233447 DQM Delay:
2914 23:25:07.233520 DQM0 = 122, DQM1 = 112
2915 23:25:07.236894 DQ Delay:
2916 23:25:07.240508 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2917 23:25:07.243663 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2918 23:25:07.247089 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2919 23:25:07.250414 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2920 23:25:07.250531
2921 23:25:07.250630
2922 23:25:07.250725 ==
2923 23:25:07.253773 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 23:25:07.256995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 23:25:07.257101 ==
2926 23:25:07.257197
2927 23:25:07.257290
2928 23:25:07.260359 TX Vref Scan disable
2929 23:25:07.263731 == TX Byte 0 ==
2930 23:25:07.266867 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2931 23:25:07.270277 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2932 23:25:07.273761 == TX Byte 1 ==
2933 23:25:07.277229 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2934 23:25:07.280633 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2935 23:25:07.280739 ==
2936 23:25:07.283665 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 23:25:07.287076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 23:25:07.290509 ==
2939 23:25:07.300797 TX Vref=22, minBit 2, minWin=25, winSum=413
2940 23:25:07.304175 TX Vref=24, minBit 3, minWin=25, winSum=418
2941 23:25:07.307546 TX Vref=26, minBit 3, minWin=25, winSum=422
2942 23:25:07.310575 TX Vref=28, minBit 0, minWin=26, winSum=424
2943 23:25:07.313922 TX Vref=30, minBit 12, minWin=25, winSum=426
2944 23:25:07.320562 TX Vref=32, minBit 0, minWin=26, winSum=428
2945 23:25:07.323942 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 32
2946 23:25:07.324048
2947 23:25:07.327216 Final TX Range 1 Vref 32
2948 23:25:07.327319
2949 23:25:07.327416 ==
2950 23:25:07.330597 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 23:25:07.334006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 23:25:07.334110 ==
2953 23:25:07.337063
2954 23:25:07.337168
2955 23:25:07.337264 TX Vref Scan disable
2956 23:25:07.340537 == TX Byte 0 ==
2957 23:25:07.344066 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2958 23:25:07.347094 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2959 23:25:07.350503 == TX Byte 1 ==
2960 23:25:07.353699 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2961 23:25:07.356970 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2962 23:25:07.360484
2963 23:25:07.360590 [DATLAT]
2964 23:25:07.360688 Freq=1200, CH0 RK1
2965 23:25:07.360783
2966 23:25:07.363656 DATLAT Default: 0xd
2967 23:25:07.363782 0, 0xFFFF, sum = 0
2968 23:25:07.367099 1, 0xFFFF, sum = 0
2969 23:25:07.367226 2, 0xFFFF, sum = 0
2970 23:25:07.370328 3, 0xFFFF, sum = 0
2971 23:25:07.370436 4, 0xFFFF, sum = 0
2972 23:25:07.373649 5, 0xFFFF, sum = 0
2973 23:25:07.377092 6, 0xFFFF, sum = 0
2974 23:25:07.377177 7, 0xFFFF, sum = 0
2975 23:25:07.380488 8, 0xFFFF, sum = 0
2976 23:25:07.380572 9, 0xFFFF, sum = 0
2977 23:25:07.383883 10, 0xFFFF, sum = 0
2978 23:25:07.383967 11, 0xFFFF, sum = 0
2979 23:25:07.387262 12, 0x0, sum = 1
2980 23:25:07.387346 13, 0x0, sum = 2
2981 23:25:07.390425 14, 0x0, sum = 3
2982 23:25:07.390508 15, 0x0, sum = 4
2983 23:25:07.390576 best_step = 13
2984 23:25:07.390637
2985 23:25:07.393788 ==
2986 23:25:07.397234 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 23:25:07.400637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 23:25:07.400720 ==
2989 23:25:07.400786 RX Vref Scan: 0
2990 23:25:07.400874
2991 23:25:07.403930 RX Vref 0 -> 0, step: 1
2992 23:25:07.404053
2993 23:25:07.407154 RX Delay -13 -> 252, step: 4
2994 23:25:07.410474 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
2995 23:25:07.417336 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2996 23:25:07.420365 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2997 23:25:07.423766 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
2998 23:25:07.427253 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
2999 23:25:07.430643 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3000 23:25:07.433623 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3001 23:25:07.440576 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3002 23:25:07.443664 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3003 23:25:07.447170 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3004 23:25:07.450371 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3005 23:25:07.453966 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3006 23:25:07.460405 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3007 23:25:07.463762 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3008 23:25:07.467238 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3009 23:25:07.470341 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3010 23:25:07.470424 ==
3011 23:25:07.473726 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 23:25:07.480520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 23:25:07.480609 ==
3014 23:25:07.480688 DQS Delay:
3015 23:25:07.483768 DQS0 = 0, DQS1 = 0
3016 23:25:07.483870 DQM Delay:
3017 23:25:07.483976 DQM0 = 121, DQM1 = 109
3018 23:25:07.487106 DQ Delay:
3019 23:25:07.490327 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3020 23:25:07.493675 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3021 23:25:07.497063 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =100
3022 23:25:07.500154 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3023 23:25:07.500261
3024 23:25:07.500380
3025 23:25:07.510188 [DQSOSCAuto] RK1, (LSB)MR18= 0xff0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3026 23:25:07.510287 CH0 RK1: MR19=403, MR18=FF0
3027 23:25:07.517140 CH0_RK1: MR19=0x403, MR18=0xFF0, DQSOSC=404, MR23=63, INC=40, DEC=26
3028 23:25:07.520180 [RxdqsGatingPostProcess] freq 1200
3029 23:25:07.527089 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3030 23:25:07.530150 best DQS0 dly(2T, 0.5T) = (0, 11)
3031 23:25:07.533573 best DQS1 dly(2T, 0.5T) = (0, 12)
3032 23:25:07.537294 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3033 23:25:07.537400 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3034 23:25:07.540408 best DQS0 dly(2T, 0.5T) = (0, 11)
3035 23:25:07.543644 best DQS1 dly(2T, 0.5T) = (0, 11)
3036 23:25:07.547222 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3037 23:25:07.550711 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3038 23:25:07.554181 Pre-setting of DQS Precalculation
3039 23:25:07.560588 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3040 23:25:07.560694 ==
3041 23:25:07.563947 Dram Type= 6, Freq= 0, CH_1, rank 0
3042 23:25:07.567306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 23:25:07.567429 ==
3044 23:25:07.573900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3045 23:25:07.577246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3046 23:25:07.586830 [CA 0] Center 37 (7~68) winsize 62
3047 23:25:07.589942 [CA 1] Center 37 (7~68) winsize 62
3048 23:25:07.593344 [CA 2] Center 35 (5~65) winsize 61
3049 23:25:07.596926 [CA 3] Center 34 (5~64) winsize 60
3050 23:25:07.599835 [CA 4] Center 34 (4~64) winsize 61
3051 23:25:07.603487 [CA 5] Center 33 (3~63) winsize 61
3052 23:25:07.603572
3053 23:25:07.606696 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3054 23:25:07.606810
3055 23:25:07.610118 [CATrainingPosCal] consider 1 rank data
3056 23:25:07.613333 u2DelayCellTimex100 = 270/100 ps
3057 23:25:07.616606 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3058 23:25:07.619827 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3059 23:25:07.626644 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3060 23:25:07.629849 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3061 23:25:07.633188 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3062 23:25:07.636803 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3063 23:25:07.636896
3064 23:25:07.639962 CA PerBit enable=1, Macro0, CA PI delay=33
3065 23:25:07.640061
3066 23:25:07.643426 [CBTSetCACLKResult] CA Dly = 33
3067 23:25:07.643532 CS Dly: 7 (0~38)
3068 23:25:07.643625 ==
3069 23:25:07.646961 Dram Type= 6, Freq= 0, CH_1, rank 1
3070 23:25:07.653332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 23:25:07.653423 ==
3072 23:25:07.656859 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 23:25:07.663666 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3074 23:25:07.672381 [CA 0] Center 37 (7~68) winsize 62
3075 23:25:07.675636 [CA 1] Center 38 (7~69) winsize 63
3076 23:25:07.678957 [CA 2] Center 35 (5~65) winsize 61
3077 23:25:07.682528 [CA 3] Center 34 (4~65) winsize 62
3078 23:25:07.685483 [CA 4] Center 34 (4~65) winsize 62
3079 23:25:07.688910 [CA 5] Center 34 (4~64) winsize 61
3080 23:25:07.689046
3081 23:25:07.692261 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3082 23:25:07.692402
3083 23:25:07.695850 [CATrainingPosCal] consider 2 rank data
3084 23:25:07.699168 u2DelayCellTimex100 = 270/100 ps
3085 23:25:07.702540 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 23:25:07.705571 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 23:25:07.712441 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3088 23:25:07.715596 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3089 23:25:07.718960 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 23:25:07.722336 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3091 23:25:07.722418
3092 23:25:07.725778 CA PerBit enable=1, Macro0, CA PI delay=33
3093 23:25:07.725882
3094 23:25:07.729145 [CBTSetCACLKResult] CA Dly = 33
3095 23:25:07.729230 CS Dly: 8 (0~41)
3096 23:25:07.729296
3097 23:25:07.732518 ----->DramcWriteLeveling(PI) begin...
3098 23:25:07.735700 ==
3099 23:25:07.735816 Dram Type= 6, Freq= 0, CH_1, rank 0
3100 23:25:07.742460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 23:25:07.742591 ==
3102 23:25:07.745606 Write leveling (Byte 0): 26 => 26
3103 23:25:07.749174 Write leveling (Byte 1): 28 => 28
3104 23:25:07.752416 DramcWriteLeveling(PI) end<-----
3105 23:25:07.752543
3106 23:25:07.752664 ==
3107 23:25:07.755627 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 23:25:07.759055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 23:25:07.759165 ==
3110 23:25:07.762298 [Gating] SW mode calibration
3111 23:25:07.768933 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3112 23:25:07.772376 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3113 23:25:07.779248 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 23:25:07.782556 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 23:25:07.785959 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 23:25:07.792409 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 23:25:07.795834 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 23:25:07.799257 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 23:25:07.806079 0 15 24 | B1->B0 | 3434 2b2b | 0 0 | (0 1) (0 0)
3120 23:25:07.809219 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3121 23:25:07.812660 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 23:25:07.819151 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 23:25:07.822450 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 23:25:07.825767 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 23:25:07.832704 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 23:25:07.835769 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 23:25:07.839242 1 0 24 | B1->B0 | 3333 4040 | 1 0 | (0 0) (0 0)
3128 23:25:07.842658 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 23:25:07.849409 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 23:25:07.852784 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 23:25:07.855957 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 23:25:07.862728 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 23:25:07.866218 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 23:25:07.869461 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 23:25:07.876157 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3136 23:25:07.879581 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3137 23:25:07.882956 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 23:25:07.889592 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 23:25:07.892639 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 23:25:07.896344 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 23:25:07.902862 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 23:25:07.906400 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 23:25:07.909727 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 23:25:07.913114 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 23:25:07.919622 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 23:25:07.923199 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 23:25:07.926485 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 23:25:07.933002 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 23:25:07.936449 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 23:25:07.939607 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 23:25:07.946499 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3152 23:25:07.949628 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3153 23:25:07.952957 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 23:25:07.956315 Total UI for P1: 0, mck2ui 16
3155 23:25:07.959845 best dqsien dly found for B0: ( 1, 3, 26)
3156 23:25:07.962851 Total UI for P1: 0, mck2ui 16
3157 23:25:07.966364 best dqsien dly found for B1: ( 1, 3, 26)
3158 23:25:07.969766 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3159 23:25:07.973263 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3160 23:25:07.973350
3161 23:25:07.976207 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3162 23:25:07.982891 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3163 23:25:07.982998 [Gating] SW calibration Done
3164 23:25:07.983092 ==
3165 23:25:07.986417 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 23:25:07.992841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 23:25:07.992940 ==
3168 23:25:07.993036 RX Vref Scan: 0
3169 23:25:07.993126
3170 23:25:07.996184 RX Vref 0 -> 0, step: 1
3171 23:25:07.996298
3172 23:25:08.000040 RX Delay -40 -> 252, step: 8
3173 23:25:08.003092 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3174 23:25:08.006393 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3175 23:25:08.009736 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3176 23:25:08.016351 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3177 23:25:08.019691 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3178 23:25:08.023227 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3179 23:25:08.026618 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3180 23:25:08.029690 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3181 23:25:08.033192 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3182 23:25:08.039935 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3183 23:25:08.043334 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3184 23:25:08.046418 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3185 23:25:08.050043 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3186 23:25:08.056550 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3187 23:25:08.059812 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3188 23:25:08.063124 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3189 23:25:08.063260 ==
3190 23:25:08.066707 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 23:25:08.069786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 23:25:08.069885 ==
3193 23:25:08.073303 DQS Delay:
3194 23:25:08.073406 DQS0 = 0, DQS1 = 0
3195 23:25:08.073471 DQM Delay:
3196 23:25:08.076662 DQM0 = 119, DQM1 = 116
3197 23:25:08.076760 DQ Delay:
3198 23:25:08.079735 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3199 23:25:08.083362 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3200 23:25:08.090060 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3201 23:25:08.093122 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3202 23:25:08.093247
3203 23:25:08.093309
3204 23:25:08.093367 ==
3205 23:25:08.096745 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 23:25:08.099708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 23:25:08.099828 ==
3208 23:25:08.099938
3209 23:25:08.100025
3210 23:25:08.103317 TX Vref Scan disable
3211 23:25:08.103433 == TX Byte 0 ==
3212 23:25:08.109820 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3213 23:25:08.113328 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3214 23:25:08.113432 == TX Byte 1 ==
3215 23:25:08.119949 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3216 23:25:08.123204 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3217 23:25:08.123303 ==
3218 23:25:08.126701 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 23:25:08.129567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 23:25:08.129653 ==
3221 23:25:08.142595 TX Vref=22, minBit 9, minWin=24, winSum=412
3222 23:25:08.145813 TX Vref=24, minBit 1, minWin=25, winSum=414
3223 23:25:08.149388 TX Vref=26, minBit 12, minWin=25, winSum=423
3224 23:25:08.152758 TX Vref=28, minBit 1, minWin=26, winSum=431
3225 23:25:08.155959 TX Vref=30, minBit 1, minWin=26, winSum=433
3226 23:25:08.162621 TX Vref=32, minBit 10, minWin=26, winSum=432
3227 23:25:08.166175 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 30
3228 23:25:08.166285
3229 23:25:08.169175 Final TX Range 1 Vref 30
3230 23:25:08.169283
3231 23:25:08.169383 ==
3232 23:25:08.172586 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 23:25:08.176102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 23:25:08.176209 ==
3235 23:25:08.179349
3236 23:25:08.179430
3237 23:25:08.179493 TX Vref Scan disable
3238 23:25:08.182443 == TX Byte 0 ==
3239 23:25:08.185865 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3240 23:25:08.189180 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3241 23:25:08.192602 == TX Byte 1 ==
3242 23:25:08.196076 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3243 23:25:08.202418 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3244 23:25:08.202543
3245 23:25:08.202657 [DATLAT]
3246 23:25:08.202771 Freq=1200, CH1 RK0
3247 23:25:08.202883
3248 23:25:08.205921 DATLAT Default: 0xd
3249 23:25:08.206048 0, 0xFFFF, sum = 0
3250 23:25:08.209271 1, 0xFFFF, sum = 0
3251 23:25:08.209401 2, 0xFFFF, sum = 0
3252 23:25:08.212631 3, 0xFFFF, sum = 0
3253 23:25:08.212762 4, 0xFFFF, sum = 0
3254 23:25:08.216044 5, 0xFFFF, sum = 0
3255 23:25:08.219332 6, 0xFFFF, sum = 0
3256 23:25:08.219462 7, 0xFFFF, sum = 0
3257 23:25:08.222462 8, 0xFFFF, sum = 0
3258 23:25:08.222575 9, 0xFFFF, sum = 0
3259 23:25:08.225863 10, 0xFFFF, sum = 0
3260 23:25:08.225966 11, 0xFFFF, sum = 0
3261 23:25:08.228818 12, 0x0, sum = 1
3262 23:25:08.228895 13, 0x0, sum = 2
3263 23:25:08.232448 14, 0x0, sum = 3
3264 23:25:08.232529 15, 0x0, sum = 4
3265 23:25:08.232595 best_step = 13
3266 23:25:08.235478
3267 23:25:08.235581 ==
3268 23:25:08.238944 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 23:25:08.242446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 23:25:08.242553 ==
3271 23:25:08.242663 RX Vref Scan: 1
3272 23:25:08.242759
3273 23:25:08.245498 Set Vref Range= 32 -> 127
3274 23:25:08.245598
3275 23:25:08.249077 RX Vref 32 -> 127, step: 1
3276 23:25:08.249163
3277 23:25:08.252541 RX Delay -5 -> 252, step: 4
3278 23:25:08.252649
3279 23:25:08.255510 Set Vref, RX VrefLevel [Byte0]: 32
3280 23:25:08.259170 [Byte1]: 32
3281 23:25:08.259256
3282 23:25:08.262290 Set Vref, RX VrefLevel [Byte0]: 33
3283 23:25:08.265596 [Byte1]: 33
3284 23:25:08.265680
3285 23:25:08.269057 Set Vref, RX VrefLevel [Byte0]: 34
3286 23:25:08.272479 [Byte1]: 34
3287 23:25:08.276829
3288 23:25:08.276938 Set Vref, RX VrefLevel [Byte0]: 35
3289 23:25:08.279812 [Byte1]: 35
3290 23:25:08.284541
3291 23:25:08.284642 Set Vref, RX VrefLevel [Byte0]: 36
3292 23:25:08.287866 [Byte1]: 36
3293 23:25:08.292244
3294 23:25:08.292336 Set Vref, RX VrefLevel [Byte0]: 37
3295 23:25:08.295723 [Byte1]: 37
3296 23:25:08.300066
3297 23:25:08.300151 Set Vref, RX VrefLevel [Byte0]: 38
3298 23:25:08.303569 [Byte1]: 38
3299 23:25:08.308189
3300 23:25:08.308273 Set Vref, RX VrefLevel [Byte0]: 39
3301 23:25:08.311116 [Byte1]: 39
3302 23:25:08.316001
3303 23:25:08.316108 Set Vref, RX VrefLevel [Byte0]: 40
3304 23:25:08.319113 [Byte1]: 40
3305 23:25:08.323543
3306 23:25:08.323625 Set Vref, RX VrefLevel [Byte0]: 41
3307 23:25:08.326943 [Byte1]: 41
3308 23:25:08.331769
3309 23:25:08.331846 Set Vref, RX VrefLevel [Byte0]: 42
3310 23:25:08.334809 [Byte1]: 42
3311 23:25:08.339503
3312 23:25:08.339634 Set Vref, RX VrefLevel [Byte0]: 43
3313 23:25:08.342667 [Byte1]: 43
3314 23:25:08.347292
3315 23:25:08.347420 Set Vref, RX VrefLevel [Byte0]: 44
3316 23:25:08.350757 [Byte1]: 44
3317 23:25:08.354962
3318 23:25:08.355085 Set Vref, RX VrefLevel [Byte0]: 45
3319 23:25:08.358207 [Byte1]: 45
3320 23:25:08.363133
3321 23:25:08.363240 Set Vref, RX VrefLevel [Byte0]: 46
3322 23:25:08.366040 [Byte1]: 46
3323 23:25:08.370673
3324 23:25:08.370778 Set Vref, RX VrefLevel [Byte0]: 47
3325 23:25:08.374015 [Byte1]: 47
3326 23:25:08.378718
3327 23:25:08.378823 Set Vref, RX VrefLevel [Byte0]: 48
3328 23:25:08.381898 [Byte1]: 48
3329 23:25:08.386661
3330 23:25:08.386766 Set Vref, RX VrefLevel [Byte0]: 49
3331 23:25:08.389737 [Byte1]: 49
3332 23:25:08.394334
3333 23:25:08.394464 Set Vref, RX VrefLevel [Byte0]: 50
3334 23:25:08.397753 [Byte1]: 50
3335 23:25:08.401994
3336 23:25:08.402124 Set Vref, RX VrefLevel [Byte0]: 51
3337 23:25:08.405366 [Byte1]: 51
3338 23:25:08.409971
3339 23:25:08.410097 Set Vref, RX VrefLevel [Byte0]: 52
3340 23:25:08.413508 [Byte1]: 52
3341 23:25:08.417672
3342 23:25:08.417798 Set Vref, RX VrefLevel [Byte0]: 53
3343 23:25:08.421189 [Byte1]: 53
3344 23:25:08.425892
3345 23:25:08.426016 Set Vref, RX VrefLevel [Byte0]: 54
3346 23:25:08.429245 [Byte1]: 54
3347 23:25:08.433418
3348 23:25:08.433545 Set Vref, RX VrefLevel [Byte0]: 55
3349 23:25:08.436763 [Byte1]: 55
3350 23:25:08.441589
3351 23:25:08.441712 Set Vref, RX VrefLevel [Byte0]: 56
3352 23:25:08.444675 [Byte1]: 56
3353 23:25:08.449210
3354 23:25:08.449336 Set Vref, RX VrefLevel [Byte0]: 57
3355 23:25:08.452743 [Byte1]: 57
3356 23:25:08.456963
3357 23:25:08.457070 Set Vref, RX VrefLevel [Byte0]: 58
3358 23:25:08.460512 [Byte1]: 58
3359 23:25:08.464742
3360 23:25:08.464852 Set Vref, RX VrefLevel [Byte0]: 59
3361 23:25:08.468552 [Byte1]: 59
3362 23:25:08.473080
3363 23:25:08.473164 Set Vref, RX VrefLevel [Byte0]: 60
3364 23:25:08.475966 [Byte1]: 60
3365 23:25:08.480675
3366 23:25:08.480758 Set Vref, RX VrefLevel [Byte0]: 61
3367 23:25:08.483939 [Byte1]: 61
3368 23:25:08.488663
3369 23:25:08.488769 Set Vref, RX VrefLevel [Byte0]: 62
3370 23:25:08.491636 [Byte1]: 62
3371 23:25:08.496452
3372 23:25:08.496532 Set Vref, RX VrefLevel [Byte0]: 63
3373 23:25:08.499667 [Byte1]: 63
3374 23:25:08.503981
3375 23:25:08.504088 Set Vref, RX VrefLevel [Byte0]: 64
3376 23:25:08.507371 [Byte1]: 64
3377 23:25:08.512115
3378 23:25:08.512195 Set Vref, RX VrefLevel [Byte0]: 65
3379 23:25:08.515182 [Byte1]: 65
3380 23:25:08.519957
3381 23:25:08.520033 Set Vref, RX VrefLevel [Byte0]: 66
3382 23:25:08.523265 [Byte1]: 66
3383 23:25:08.528027
3384 23:25:08.528101 Set Vref, RX VrefLevel [Byte0]: 67
3385 23:25:08.531138 [Byte1]: 67
3386 23:25:08.535790
3387 23:25:08.535874 Set Vref, RX VrefLevel [Byte0]: 68
3388 23:25:08.539062 [Byte1]: 68
3389 23:25:08.543389
3390 23:25:08.543473 Set Vref, RX VrefLevel [Byte0]: 69
3391 23:25:08.546834 [Byte1]: 69
3392 23:25:08.551451
3393 23:25:08.551534 Set Vref, RX VrefLevel [Byte0]: 70
3394 23:25:08.554437 [Byte1]: 70
3395 23:25:08.559219
3396 23:25:08.559304 Final RX Vref Byte 0 = 54 to rank0
3397 23:25:08.562378 Final RX Vref Byte 1 = 53 to rank0
3398 23:25:08.565935 Final RX Vref Byte 0 = 54 to rank1
3399 23:25:08.569306 Final RX Vref Byte 1 = 53 to rank1==
3400 23:25:08.572773 Dram Type= 6, Freq= 0, CH_1, rank 0
3401 23:25:08.579253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 23:25:08.579338 ==
3403 23:25:08.579405 DQS Delay:
3404 23:25:08.579467 DQS0 = 0, DQS1 = 0
3405 23:25:08.582643 DQM Delay:
3406 23:25:08.582726 DQM0 = 120, DQM1 = 117
3407 23:25:08.585682 DQ Delay:
3408 23:25:08.589066 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3409 23:25:08.592449 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120
3410 23:25:08.595720 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3411 23:25:08.599237 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3412 23:25:08.599348
3413 23:25:08.599442
3414 23:25:08.605897 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3415 23:25:08.609376 CH1 RK0: MR19=404, MR18=114
3416 23:25:08.615995 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3417 23:25:08.616103
3418 23:25:08.619407 ----->DramcWriteLeveling(PI) begin...
3419 23:25:08.619486 ==
3420 23:25:08.622604 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 23:25:08.625864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 23:25:08.625970 ==
3423 23:25:08.629309 Write leveling (Byte 0): 27 => 27
3424 23:25:08.632747 Write leveling (Byte 1): 28 => 28
3425 23:25:08.636111 DramcWriteLeveling(PI) end<-----
3426 23:25:08.636217
3427 23:25:08.636316 ==
3428 23:25:08.639097 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 23:25:08.642785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 23:25:08.646128 ==
3431 23:25:08.646209 [Gating] SW mode calibration
3432 23:25:08.656232 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3433 23:25:08.659246 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3434 23:25:08.662581 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 23:25:08.669329 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 23:25:08.672768 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 23:25:08.676240 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 23:25:08.682706 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 23:25:08.686291 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3440 23:25:08.689640 0 15 24 | B1->B0 | 2525 3333 | 0 0 | (0 1) (0 1)
3441 23:25:08.696486 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3442 23:25:08.699527 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 23:25:08.702802 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 23:25:08.706608 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 23:25:08.712887 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 23:25:08.715995 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 23:25:08.719652 1 0 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
3448 23:25:08.726089 1 0 24 | B1->B0 | 4141 2626 | 1 1 | (0 0) (0 0)
3449 23:25:08.729293 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 23:25:08.732664 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 23:25:08.739377 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 23:25:08.742626 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 23:25:08.745987 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 23:25:08.752414 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 23:25:08.755743 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 23:25:08.759249 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3457 23:25:08.766094 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3458 23:25:08.769098 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 23:25:08.772390 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 23:25:08.779027 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 23:25:08.782477 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 23:25:08.785595 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 23:25:08.792524 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 23:25:08.795561 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 23:25:08.798978 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 23:25:08.805403 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 23:25:08.809045 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 23:25:08.812045 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 23:25:08.818511 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 23:25:08.821904 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 23:25:08.825186 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3472 23:25:08.832052 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3473 23:25:08.835140 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3474 23:25:08.838570 Total UI for P1: 0, mck2ui 16
3475 23:25:08.841916 best dqsien dly found for B1: ( 1, 3, 22)
3476 23:25:08.845176 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 23:25:08.848762 Total UI for P1: 0, mck2ui 16
3478 23:25:08.852061 best dqsien dly found for B0: ( 1, 3, 28)
3479 23:25:08.855199 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3480 23:25:08.858651 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3481 23:25:08.858736
3482 23:25:08.865106 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3483 23:25:08.868308 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3484 23:25:08.868393 [Gating] SW calibration Done
3485 23:25:08.871864 ==
3486 23:25:08.874984 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 23:25:08.878415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 23:25:08.878501 ==
3489 23:25:08.878567 RX Vref Scan: 0
3490 23:25:08.878629
3491 23:25:08.881968 RX Vref 0 -> 0, step: 1
3492 23:25:08.882057
3493 23:25:08.885159 RX Delay -40 -> 252, step: 8
3494 23:25:08.888362 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3495 23:25:08.891722 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3496 23:25:08.895200 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3497 23:25:08.901656 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3498 23:25:08.905088 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3499 23:25:08.908492 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3500 23:25:08.911893 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3501 23:25:08.915216 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3502 23:25:08.921727 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3503 23:25:08.924896 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3504 23:25:08.928204 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3505 23:25:08.931522 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3506 23:25:08.934972 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3507 23:25:08.941600 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3508 23:25:08.944883 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3509 23:25:08.948417 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3510 23:25:08.948501 ==
3511 23:25:08.951572 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 23:25:08.954940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 23:25:08.958009 ==
3514 23:25:08.958093 DQS Delay:
3515 23:25:08.958159 DQS0 = 0, DQS1 = 0
3516 23:25:08.961452 DQM Delay:
3517 23:25:08.961536 DQM0 = 121, DQM1 = 117
3518 23:25:08.964601 DQ Delay:
3519 23:25:08.967867 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3520 23:25:08.971457 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3521 23:25:08.974571 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3522 23:25:08.977977 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3523 23:25:08.978100
3524 23:25:08.978213
3525 23:25:08.978325 ==
3526 23:25:08.981312 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 23:25:08.984621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 23:25:08.984749 ==
3529 23:25:08.984861
3530 23:25:08.988115
3531 23:25:08.988225 TX Vref Scan disable
3532 23:25:08.991322 == TX Byte 0 ==
3533 23:25:08.994948 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3534 23:25:08.997965 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3535 23:25:09.001272 == TX Byte 1 ==
3536 23:25:09.004713 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3537 23:25:09.008209 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3538 23:25:09.008318 ==
3539 23:25:09.011297 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 23:25:09.018138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 23:25:09.018243 ==
3542 23:25:09.028105 TX Vref=22, minBit 0, minWin=26, winSum=419
3543 23:25:09.031536 TX Vref=24, minBit 2, minWin=26, winSum=426
3544 23:25:09.034927 TX Vref=26, minBit 0, minWin=26, winSum=428
3545 23:25:09.038307 TX Vref=28, minBit 10, minWin=25, winSum=433
3546 23:25:09.041798 TX Vref=30, minBit 9, minWin=26, winSum=437
3547 23:25:09.048214 TX Vref=32, minBit 9, minWin=26, winSum=434
3548 23:25:09.051465 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3549 23:25:09.051600
3550 23:25:09.054917 Final TX Range 1 Vref 30
3551 23:25:09.055043
3552 23:25:09.055161 ==
3553 23:25:09.058237 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 23:25:09.061372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 23:25:09.061502 ==
3556 23:25:09.064687
3557 23:25:09.064809
3558 23:25:09.064923 TX Vref Scan disable
3559 23:25:09.068103 == TX Byte 0 ==
3560 23:25:09.071542 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3561 23:25:09.077848 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3562 23:25:09.077973 == TX Byte 1 ==
3563 23:25:09.081277 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3564 23:25:09.087757 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3565 23:25:09.087884
3566 23:25:09.087994 [DATLAT]
3567 23:25:09.088107 Freq=1200, CH1 RK1
3568 23:25:09.088219
3569 23:25:09.091399 DATLAT Default: 0xd
3570 23:25:09.091519 0, 0xFFFF, sum = 0
3571 23:25:09.094708 1, 0xFFFF, sum = 0
3572 23:25:09.097636 2, 0xFFFF, sum = 0
3573 23:25:09.097748 3, 0xFFFF, sum = 0
3574 23:25:09.101303 4, 0xFFFF, sum = 0
3575 23:25:09.101412 5, 0xFFFF, sum = 0
3576 23:25:09.104651 6, 0xFFFF, sum = 0
3577 23:25:09.104763 7, 0xFFFF, sum = 0
3578 23:25:09.107917 8, 0xFFFF, sum = 0
3579 23:25:09.107994 9, 0xFFFF, sum = 0
3580 23:25:09.111086 10, 0xFFFF, sum = 0
3581 23:25:09.111192 11, 0xFFFF, sum = 0
3582 23:25:09.114443 12, 0x0, sum = 1
3583 23:25:09.114552 13, 0x0, sum = 2
3584 23:25:09.117589 14, 0x0, sum = 3
3585 23:25:09.117695 15, 0x0, sum = 4
3586 23:25:09.121121 best_step = 13
3587 23:25:09.121227
3588 23:25:09.121321 ==
3589 23:25:09.124124 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 23:25:09.127571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 23:25:09.127678 ==
3592 23:25:09.127771 RX Vref Scan: 0
3593 23:25:09.131184
3594 23:25:09.131261 RX Vref 0 -> 0, step: 1
3595 23:25:09.131324
3596 23:25:09.134178 RX Delay -5 -> 252, step: 4
3597 23:25:09.137544 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3598 23:25:09.144280 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3599 23:25:09.147647 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3600 23:25:09.150697 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3601 23:25:09.154147 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3602 23:25:09.157422 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3603 23:25:09.163875 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3604 23:25:09.167407 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3605 23:25:09.170706 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3606 23:25:09.173872 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3607 23:25:09.177400 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3608 23:25:09.183962 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3609 23:25:09.187444 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3610 23:25:09.190788 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3611 23:25:09.193957 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3612 23:25:09.200596 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3613 23:25:09.200702 ==
3614 23:25:09.203994 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 23:25:09.207363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 23:25:09.207468 ==
3617 23:25:09.207564 DQS Delay:
3618 23:25:09.210344 DQS0 = 0, DQS1 = 0
3619 23:25:09.210418 DQM Delay:
3620 23:25:09.214105 DQM0 = 120, DQM1 = 118
3621 23:25:09.214183 DQ Delay:
3622 23:25:09.217389 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3623 23:25:09.220542 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3624 23:25:09.223974 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3625 23:25:09.226997 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3626 23:25:09.227104
3627 23:25:09.227196
3628 23:25:09.237122 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3629 23:25:09.240495 CH1 RK1: MR19=403, MR18=10ED
3630 23:25:09.243771 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3631 23:25:09.247154 [RxdqsGatingPostProcess] freq 1200
3632 23:25:09.253886 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3633 23:25:09.256941 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 23:25:09.260445 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 23:25:09.263907 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 23:25:09.267046 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 23:25:09.270434 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 23:25:09.273962 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 23:25:09.276883 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 23:25:09.280243 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 23:25:09.283589 Pre-setting of DQS Precalculation
3642 23:25:09.286976 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3643 23:25:09.293589 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3644 23:25:09.300125 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3645 23:25:09.300232
3646 23:25:09.303564
3647 23:25:09.303672 [Calibration Summary] 2400 Mbps
3648 23:25:09.307075 CH 0, Rank 0
3649 23:25:09.307182 SW Impedance : PASS
3650 23:25:09.310275 DUTY Scan : NO K
3651 23:25:09.313455 ZQ Calibration : PASS
3652 23:25:09.313559 Jitter Meter : NO K
3653 23:25:09.316812 CBT Training : PASS
3654 23:25:09.320219 Write leveling : PASS
3655 23:25:09.320328 RX DQS gating : PASS
3656 23:25:09.323695 RX DQ/DQS(RDDQC) : PASS
3657 23:25:09.327070 TX DQ/DQS : PASS
3658 23:25:09.327180 RX DATLAT : PASS
3659 23:25:09.330377 RX DQ/DQS(Engine): PASS
3660 23:25:09.330484 TX OE : NO K
3661 23:25:09.333707 All Pass.
3662 23:25:09.333808
3663 23:25:09.333911 CH 0, Rank 1
3664 23:25:09.337082 SW Impedance : PASS
3665 23:25:09.337184 DUTY Scan : NO K
3666 23:25:09.340488 ZQ Calibration : PASS
3667 23:25:09.343607 Jitter Meter : NO K
3668 23:25:09.343682 CBT Training : PASS
3669 23:25:09.347089 Write leveling : PASS
3670 23:25:09.350305 RX DQS gating : PASS
3671 23:25:09.350403 RX DQ/DQS(RDDQC) : PASS
3672 23:25:09.353513 TX DQ/DQS : PASS
3673 23:25:09.356903 RX DATLAT : PASS
3674 23:25:09.356984 RX DQ/DQS(Engine): PASS
3675 23:25:09.360322 TX OE : NO K
3676 23:25:09.360423 All Pass.
3677 23:25:09.360516
3678 23:25:09.363496 CH 1, Rank 0
3679 23:25:09.363593 SW Impedance : PASS
3680 23:25:09.366586 DUTY Scan : NO K
3681 23:25:09.370005 ZQ Calibration : PASS
3682 23:25:09.370131 Jitter Meter : NO K
3683 23:25:09.373418 CBT Training : PASS
3684 23:25:09.376528 Write leveling : PASS
3685 23:25:09.376607 RX DQS gating : PASS
3686 23:25:09.379971 RX DQ/DQS(RDDQC) : PASS
3687 23:25:09.383505 TX DQ/DQS : PASS
3688 23:25:09.383616 RX DATLAT : PASS
3689 23:25:09.386420 RX DQ/DQS(Engine): PASS
3690 23:25:09.386527 TX OE : NO K
3691 23:25:09.389771 All Pass.
3692 23:25:09.389893
3693 23:25:09.390015 CH 1, Rank 1
3694 23:25:09.393234 SW Impedance : PASS
3695 23:25:09.396439 DUTY Scan : NO K
3696 23:25:09.396525 ZQ Calibration : PASS
3697 23:25:09.399779 Jitter Meter : NO K
3698 23:25:09.399890 CBT Training : PASS
3699 23:25:09.403060 Write leveling : PASS
3700 23:25:09.406581 RX DQS gating : PASS
3701 23:25:09.406694 RX DQ/DQS(RDDQC) : PASS
3702 23:25:09.409981 TX DQ/DQS : PASS
3703 23:25:09.413071 RX DATLAT : PASS
3704 23:25:09.413162 RX DQ/DQS(Engine): PASS
3705 23:25:09.416433 TX OE : NO K
3706 23:25:09.416526 All Pass.
3707 23:25:09.416592
3708 23:25:09.420089 DramC Write-DBI off
3709 23:25:09.423187 PER_BANK_REFRESH: Hybrid Mode
3710 23:25:09.423318 TX_TRACKING: ON
3711 23:25:09.433168 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3712 23:25:09.436462 [FAST_K] Save calibration result to emmc
3713 23:25:09.439854 dramc_set_vcore_voltage set vcore to 650000
3714 23:25:09.443173 Read voltage for 600, 5
3715 23:25:09.443291 Vio18 = 0
3716 23:25:09.443411 Vcore = 650000
3717 23:25:09.446247 Vdram = 0
3718 23:25:09.446370 Vddq = 0
3719 23:25:09.446486 Vmddr = 0
3720 23:25:09.453253 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3721 23:25:09.456253 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3722 23:25:09.459673 MEM_TYPE=3, freq_sel=19
3723 23:25:09.463137 sv_algorithm_assistance_LP4_1600
3724 23:25:09.466301 ============ PULL DRAM RESETB DOWN ============
3725 23:25:09.469621 ========== PULL DRAM RESETB DOWN end =========
3726 23:25:09.476241 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 23:25:09.479768 ===================================
3728 23:25:09.479850 LPDDR4 DRAM CONFIGURATION
3729 23:25:09.483167 ===================================
3730 23:25:09.486366 EX_ROW_EN[0] = 0x0
3731 23:25:09.489464 EX_ROW_EN[1] = 0x0
3732 23:25:09.489574 LP4Y_EN = 0x0
3733 23:25:09.493032 WORK_FSP = 0x0
3734 23:25:09.493112 WL = 0x2
3735 23:25:09.496004 RL = 0x2
3736 23:25:09.496111 BL = 0x2
3737 23:25:09.499607 RPST = 0x0
3738 23:25:09.499684 RD_PRE = 0x0
3739 23:25:09.503023 WR_PRE = 0x1
3740 23:25:09.503100 WR_PST = 0x0
3741 23:25:09.505980 DBI_WR = 0x0
3742 23:25:09.506056 DBI_RD = 0x0
3743 23:25:09.509400 OTF = 0x1
3744 23:25:09.512779 ===================================
3745 23:25:09.516112 ===================================
3746 23:25:09.516193 ANA top config
3747 23:25:09.519176 ===================================
3748 23:25:09.522682 DLL_ASYNC_EN = 0
3749 23:25:09.526211 ALL_SLAVE_EN = 1
3750 23:25:09.529493 NEW_RANK_MODE = 1
3751 23:25:09.529599 DLL_IDLE_MODE = 1
3752 23:25:09.532695 LP45_APHY_COMB_EN = 1
3753 23:25:09.536165 TX_ODT_DIS = 1
3754 23:25:09.539253 NEW_8X_MODE = 1
3755 23:25:09.542592 ===================================
3756 23:25:09.545987 ===================================
3757 23:25:09.549437 data_rate = 1200
3758 23:25:09.549522 CKR = 1
3759 23:25:09.552527 DQ_P2S_RATIO = 8
3760 23:25:09.555904 ===================================
3761 23:25:09.558999 CA_P2S_RATIO = 8
3762 23:25:09.562391 DQ_CA_OPEN = 0
3763 23:25:09.565929 DQ_SEMI_OPEN = 0
3764 23:25:09.569358 CA_SEMI_OPEN = 0
3765 23:25:09.569435 CA_FULL_RATE = 0
3766 23:25:09.572856 DQ_CKDIV4_EN = 1
3767 23:25:09.575872 CA_CKDIV4_EN = 1
3768 23:25:09.579173 CA_PREDIV_EN = 0
3769 23:25:09.582666 PH8_DLY = 0
3770 23:25:09.585716 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3771 23:25:09.585803 DQ_AAMCK_DIV = 4
3772 23:25:09.588910 CA_AAMCK_DIV = 4
3773 23:25:09.592356 CA_ADMCK_DIV = 4
3774 23:25:09.595815 DQ_TRACK_CA_EN = 0
3775 23:25:09.598854 CA_PICK = 600
3776 23:25:09.602548 CA_MCKIO = 600
3777 23:25:09.602630 MCKIO_SEMI = 0
3778 23:25:09.605853 PLL_FREQ = 2288
3779 23:25:09.609072 DQ_UI_PI_RATIO = 32
3780 23:25:09.612649 CA_UI_PI_RATIO = 0
3781 23:25:09.615607 ===================================
3782 23:25:09.619092 ===================================
3783 23:25:09.622328 memory_type:LPDDR4
3784 23:25:09.622437 GP_NUM : 10
3785 23:25:09.626019 SRAM_EN : 1
3786 23:25:09.629056 MD32_EN : 0
3787 23:25:09.632469 ===================================
3788 23:25:09.632583 [ANA_INIT] >>>>>>>>>>>>>>
3789 23:25:09.635846 <<<<<< [CONFIGURE PHASE]: ANA_TX
3790 23:25:09.639166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3791 23:25:09.642369 ===================================
3792 23:25:09.645502 data_rate = 1200,PCW = 0X5800
3793 23:25:09.648778 ===================================
3794 23:25:09.652113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3795 23:25:09.658898 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 23:25:09.661946 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 23:25:09.668795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3798 23:25:09.672257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3799 23:25:09.675329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3800 23:25:09.675436 [ANA_INIT] flow start
3801 23:25:09.678886 [ANA_INIT] PLL >>>>>>>>
3802 23:25:09.681946 [ANA_INIT] PLL <<<<<<<<
3803 23:25:09.685388 [ANA_INIT] MIDPI >>>>>>>>
3804 23:25:09.685491 [ANA_INIT] MIDPI <<<<<<<<
3805 23:25:09.688713 [ANA_INIT] DLL >>>>>>>>
3806 23:25:09.691770 [ANA_INIT] flow end
3807 23:25:09.695339 ============ LP4 DIFF to SE enter ============
3808 23:25:09.698666 ============ LP4 DIFF to SE exit ============
3809 23:25:09.701849 [ANA_INIT] <<<<<<<<<<<<<
3810 23:25:09.705256 [Flow] Enable top DCM control >>>>>
3811 23:25:09.708599 [Flow] Enable top DCM control <<<<<
3812 23:25:09.711757 Enable DLL master slave shuffle
3813 23:25:09.715042 ==============================================================
3814 23:25:09.718321 Gating Mode config
3815 23:25:09.725073 ==============================================================
3816 23:25:09.725167 Config description:
3817 23:25:09.735420 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3818 23:25:09.741806 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3819 23:25:09.745232 SELPH_MODE 0: By rank 1: By Phase
3820 23:25:09.751876 ==============================================================
3821 23:25:09.755080 GAT_TRACK_EN = 1
3822 23:25:09.758598 RX_GATING_MODE = 2
3823 23:25:09.761771 RX_GATING_TRACK_MODE = 2
3824 23:25:09.765111 SELPH_MODE = 1
3825 23:25:09.768173 PICG_EARLY_EN = 1
3826 23:25:09.768282 VALID_LAT_VALUE = 1
3827 23:25:09.774815 ==============================================================
3828 23:25:09.778339 Enter into Gating configuration >>>>
3829 23:25:09.781687 Exit from Gating configuration <<<<
3830 23:25:09.785119 Enter into DVFS_PRE_config >>>>>
3831 23:25:09.794662 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3832 23:25:09.798108 Exit from DVFS_PRE_config <<<<<
3833 23:25:09.801475 Enter into PICG configuration >>>>
3834 23:25:09.804709 Exit from PICG configuration <<<<
3835 23:25:09.808175 [RX_INPUT] configuration >>>>>
3836 23:25:09.811371 [RX_INPUT] configuration <<<<<
3837 23:25:09.817928 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3838 23:25:09.821197 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3839 23:25:09.828073 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3840 23:25:09.834659 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3841 23:25:09.841309 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 23:25:09.847768 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 23:25:09.851247 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3844 23:25:09.854580 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3845 23:25:09.857583 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3846 23:25:09.864497 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3847 23:25:09.867647 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3848 23:25:09.871079 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3849 23:25:09.874441 ===================================
3850 23:25:09.877851 LPDDR4 DRAM CONFIGURATION
3851 23:25:09.881005 ===================================
3852 23:25:09.881114 EX_ROW_EN[0] = 0x0
3853 23:25:09.884413 EX_ROW_EN[1] = 0x0
3854 23:25:09.887870 LP4Y_EN = 0x0
3855 23:25:09.887973 WORK_FSP = 0x0
3856 23:25:09.891293 WL = 0x2
3857 23:25:09.891397 RL = 0x2
3858 23:25:09.894689 BL = 0x2
3859 23:25:09.894817 RPST = 0x0
3860 23:25:09.897756 RD_PRE = 0x0
3861 23:25:09.897886 WR_PRE = 0x1
3862 23:25:09.901174 WR_PST = 0x0
3863 23:25:09.901300 DBI_WR = 0x0
3864 23:25:09.904210 DBI_RD = 0x0
3865 23:25:09.904331 OTF = 0x1
3866 23:25:09.907759 ===================================
3867 23:25:09.910705 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3868 23:25:09.917752 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3869 23:25:09.920851 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 23:25:09.924192 ===================================
3871 23:25:09.927382 LPDDR4 DRAM CONFIGURATION
3872 23:25:09.930740 ===================================
3873 23:25:09.930870 EX_ROW_EN[0] = 0x10
3874 23:25:09.934241 EX_ROW_EN[1] = 0x0
3875 23:25:09.934326 LP4Y_EN = 0x0
3876 23:25:09.937572 WORK_FSP = 0x0
3877 23:25:09.937684 WL = 0x2
3878 23:25:09.941059 RL = 0x2
3879 23:25:09.944221 BL = 0x2
3880 23:25:09.944336 RPST = 0x0
3881 23:25:09.947465 RD_PRE = 0x0
3882 23:25:09.947548 WR_PRE = 0x1
3883 23:25:09.950673 WR_PST = 0x0
3884 23:25:09.950756 DBI_WR = 0x0
3885 23:25:09.953958 DBI_RD = 0x0
3886 23:25:09.954041 OTF = 0x1
3887 23:25:09.957448 ===================================
3888 23:25:09.964045 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3889 23:25:09.967908 nWR fixed to 30
3890 23:25:09.971267 [ModeRegInit_LP4] CH0 RK0
3891 23:25:09.971374 [ModeRegInit_LP4] CH0 RK1
3892 23:25:09.974486 [ModeRegInit_LP4] CH1 RK0
3893 23:25:09.978028 [ModeRegInit_LP4] CH1 RK1
3894 23:25:09.978133 match AC timing 17
3895 23:25:09.984321 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3896 23:25:09.987712 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3897 23:25:09.991068 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3898 23:25:09.998069 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3899 23:25:10.001133 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3900 23:25:10.001242 ==
3901 23:25:10.004592 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 23:25:10.007942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3903 23:25:10.008046 ==
3904 23:25:10.014477 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3905 23:25:10.020953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3906 23:25:10.024251 [CA 0] Center 36 (5~67) winsize 63
3907 23:25:10.027594 [CA 1] Center 36 (5~67) winsize 63
3908 23:25:10.030739 [CA 2] Center 34 (3~65) winsize 63
3909 23:25:10.034184 [CA 3] Center 33 (3~64) winsize 62
3910 23:25:10.037476 [CA 4] Center 33 (2~64) winsize 63
3911 23:25:10.041186 [CA 5] Center 32 (2~63) winsize 62
3912 23:25:10.041291
3913 23:25:10.044291 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3914 23:25:10.044407
3915 23:25:10.047772 [CATrainingPosCal] consider 1 rank data
3916 23:25:10.050618 u2DelayCellTimex100 = 270/100 ps
3917 23:25:10.054149 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3918 23:25:10.057486 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3919 23:25:10.060835 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3920 23:25:10.063929 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3921 23:25:10.067261 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3922 23:25:10.074045 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3923 23:25:10.074154
3924 23:25:10.077208 CA PerBit enable=1, Macro0, CA PI delay=32
3925 23:25:10.077324
3926 23:25:10.080366 [CBTSetCACLKResult] CA Dly = 32
3927 23:25:10.080445 CS Dly: 4 (0~35)
3928 23:25:10.080527 ==
3929 23:25:10.084097 Dram Type= 6, Freq= 0, CH_0, rank 1
3930 23:25:10.087286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 23:25:10.090578 ==
3932 23:25:10.093895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 23:25:10.100688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3934 23:25:10.104103 [CA 0] Center 36 (5~67) winsize 63
3935 23:25:10.107158 [CA 1] Center 36 (5~67) winsize 63
3936 23:25:10.110790 [CA 2] Center 34 (3~65) winsize 63
3937 23:25:10.113835 [CA 3] Center 34 (3~65) winsize 63
3938 23:25:10.116965 [CA 4] Center 33 (2~64) winsize 63
3939 23:25:10.120469 [CA 5] Center 32 (2~63) winsize 62
3940 23:25:10.120576
3941 23:25:10.123882 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3942 23:25:10.123998
3943 23:25:10.127157 [CATrainingPosCal] consider 2 rank data
3944 23:25:10.130533 u2DelayCellTimex100 = 270/100 ps
3945 23:25:10.134071 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3946 23:25:10.137065 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3947 23:25:10.140215 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3948 23:25:10.147070 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3949 23:25:10.150385 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3950 23:25:10.153841 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3951 23:25:10.153983
3952 23:25:10.157276 CA PerBit enable=1, Macro0, CA PI delay=32
3953 23:25:10.157385
3954 23:25:10.160454 [CBTSetCACLKResult] CA Dly = 32
3955 23:25:10.160573 CS Dly: 4 (0~35)
3956 23:25:10.160671
3957 23:25:10.163768 ----->DramcWriteLeveling(PI) begin...
3958 23:25:10.163882 ==
3959 23:25:10.166923 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 23:25:10.173583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 23:25:10.173694 ==
3962 23:25:10.176745 Write leveling (Byte 0): 33 => 33
3963 23:25:10.180239 Write leveling (Byte 1): 31 => 31
3964 23:25:10.180344 DramcWriteLeveling(PI) end<-----
3965 23:25:10.183456
3966 23:25:10.183541 ==
3967 23:25:10.186969 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 23:25:10.190224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 23:25:10.190345 ==
3970 23:25:10.193355 [Gating] SW mode calibration
3971 23:25:10.200336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3972 23:25:10.203595 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3973 23:25:10.210013 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 23:25:10.213535 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 23:25:10.216513 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 23:25:10.223476 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
3977 23:25:10.226514 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3978 23:25:10.229736 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 23:25:10.236691 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 23:25:10.239630 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 23:25:10.243030 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 23:25:10.249625 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 23:25:10.253247 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 23:25:10.256586 0 10 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
3985 23:25:10.263020 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
3986 23:25:10.266304 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 23:25:10.269809 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 23:25:10.276216 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 23:25:10.279868 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 23:25:10.283232 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 23:25:10.289618 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 23:25:10.292934 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3993 23:25:10.296414 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3994 23:25:10.302933 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 23:25:10.306275 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 23:25:10.309886 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 23:25:10.316159 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 23:25:10.319573 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 23:25:10.322876 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 23:25:10.326417 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 23:25:10.332997 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 23:25:10.336197 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 23:25:10.339288 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 23:25:10.346102 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 23:25:10.349223 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 23:25:10.352922 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 23:25:10.359345 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 23:25:10.362720 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4009 23:25:10.365945 Total UI for P1: 0, mck2ui 16
4010 23:25:10.369151 best dqsien dly found for B0: ( 0, 13, 10)
4011 23:25:10.372555 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4012 23:25:10.379333 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 23:25:10.382661 Total UI for P1: 0, mck2ui 16
4014 23:25:10.386513 best dqsien dly found for B1: ( 0, 13, 16)
4015 23:25:10.389006 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4016 23:25:10.392408 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4017 23:25:10.392517
4018 23:25:10.396003 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4019 23:25:10.399163 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4020 23:25:10.402819 [Gating] SW calibration Done
4021 23:25:10.402959 ==
4022 23:25:10.405938 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 23:25:10.409298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 23:25:10.409434 ==
4025 23:25:10.412734 RX Vref Scan: 0
4026 23:25:10.412870
4027 23:25:10.412992 RX Vref 0 -> 0, step: 1
4028 23:25:10.415947
4029 23:25:10.416092 RX Delay -230 -> 252, step: 16
4030 23:25:10.422454 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4031 23:25:10.426038 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4032 23:25:10.428998 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4033 23:25:10.432368 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4034 23:25:10.439257 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4035 23:25:10.442308 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4036 23:25:10.445858 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4037 23:25:10.449316 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4038 23:25:10.452663 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4039 23:25:10.458988 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4040 23:25:10.462394 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4041 23:25:10.465862 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4042 23:25:10.468855 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4043 23:25:10.475833 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4044 23:25:10.478912 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4045 23:25:10.482493 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4046 23:25:10.482571 ==
4047 23:25:10.485685 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 23:25:10.488822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 23:25:10.488907 ==
4050 23:25:10.492165 DQS Delay:
4051 23:25:10.492268 DQS0 = 0, DQS1 = 0
4052 23:25:10.495719 DQM Delay:
4053 23:25:10.495828 DQM0 = 50, DQM1 = 46
4054 23:25:10.495930 DQ Delay:
4055 23:25:10.498772 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4056 23:25:10.502353 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4057 23:25:10.505416 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4058 23:25:10.508737 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =57
4059 23:25:10.508815
4060 23:25:10.508879
4061 23:25:10.512144 ==
4062 23:25:10.512262 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 23:25:10.518667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 23:25:10.518787 ==
4065 23:25:10.518881
4066 23:25:10.518984
4067 23:25:10.521959 TX Vref Scan disable
4068 23:25:10.522041 == TX Byte 0 ==
4069 23:25:10.525207 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4070 23:25:10.532064 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4071 23:25:10.532183 == TX Byte 1 ==
4072 23:25:10.535273 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4073 23:25:10.542001 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4074 23:25:10.542091 ==
4075 23:25:10.545214 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 23:25:10.548563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 23:25:10.548657 ==
4078 23:25:10.548727
4079 23:25:10.548789
4080 23:25:10.551778 TX Vref Scan disable
4081 23:25:10.555202 == TX Byte 0 ==
4082 23:25:10.558613 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4083 23:25:10.561907 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4084 23:25:10.565294 == TX Byte 1 ==
4085 23:25:10.568641 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4086 23:25:10.571686 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4087 23:25:10.571802
4088 23:25:10.575026 [DATLAT]
4089 23:25:10.575106 Freq=600, CH0 RK0
4090 23:25:10.575178
4091 23:25:10.578514 DATLAT Default: 0x9
4092 23:25:10.578591 0, 0xFFFF, sum = 0
4093 23:25:10.581583 1, 0xFFFF, sum = 0
4094 23:25:10.581665 2, 0xFFFF, sum = 0
4095 23:25:10.584936 3, 0xFFFF, sum = 0
4096 23:25:10.585018 4, 0xFFFF, sum = 0
4097 23:25:10.588219 5, 0xFFFF, sum = 0
4098 23:25:10.588308 6, 0xFFFF, sum = 0
4099 23:25:10.591730 7, 0xFFFF, sum = 0
4100 23:25:10.591862 8, 0x0, sum = 1
4101 23:25:10.595046 9, 0x0, sum = 2
4102 23:25:10.595173 10, 0x0, sum = 3
4103 23:25:10.598240 11, 0x0, sum = 4
4104 23:25:10.598365 best_step = 9
4105 23:25:10.598479
4106 23:25:10.598592 ==
4107 23:25:10.601639 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 23:25:10.604953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 23:25:10.608452 ==
4110 23:25:10.608536 RX Vref Scan: 1
4111 23:25:10.608609
4112 23:25:10.611462 RX Vref 0 -> 0, step: 1
4113 23:25:10.611546
4114 23:25:10.614780 RX Delay -163 -> 252, step: 8
4115 23:25:10.614864
4116 23:25:10.618387 Set Vref, RX VrefLevel [Byte0]: 55
4117 23:25:10.618470 [Byte1]: 48
4118 23:25:10.623142
4119 23:25:10.623264 Final RX Vref Byte 0 = 55 to rank0
4120 23:25:10.626273 Final RX Vref Byte 1 = 48 to rank0
4121 23:25:10.629731 Final RX Vref Byte 0 = 55 to rank1
4122 23:25:10.633112 Final RX Vref Byte 1 = 48 to rank1==
4123 23:25:10.636532 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 23:25:10.643011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 23:25:10.643142 ==
4126 23:25:10.643258 DQS Delay:
4127 23:25:10.646236 DQS0 = 0, DQS1 = 0
4128 23:25:10.646364 DQM Delay:
4129 23:25:10.646480 DQM0 = 52, DQM1 = 46
4130 23:25:10.649661 DQ Delay:
4131 23:25:10.652916 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4132 23:25:10.656190 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4133 23:25:10.659604 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4134 23:25:10.662999 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4135 23:25:10.663115
4136 23:25:10.663228
4137 23:25:10.669362 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f63, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4138 23:25:10.672800 CH0 RK0: MR19=808, MR18=6F63
4139 23:25:10.679159 CH0_RK0: MR19=0x808, MR18=0x6F63, DQSOSC=389, MR23=63, INC=173, DEC=115
4140 23:25:10.679268
4141 23:25:10.682675 ----->DramcWriteLeveling(PI) begin...
4142 23:25:10.682765 ==
4143 23:25:10.686143 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 23:25:10.689237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 23:25:10.689329 ==
4146 23:25:10.692572 Write leveling (Byte 0): 35 => 35
4147 23:25:10.695952 Write leveling (Byte 1): 32 => 32
4148 23:25:10.699102 DramcWriteLeveling(PI) end<-----
4149 23:25:10.699183
4150 23:25:10.699248 ==
4151 23:25:10.702470 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 23:25:10.705765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 23:25:10.705850 ==
4154 23:25:10.709359 [Gating] SW mode calibration
4155 23:25:10.715876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4156 23:25:10.722597 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4157 23:25:10.725547 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 23:25:10.732549 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 23:25:10.735512 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 23:25:10.738967 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
4161 23:25:10.745718 0 9 16 | B1->B0 | 2e2e 2626 | 0 0 | (1 1) (0 0)
4162 23:25:10.748901 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 23:25:10.752283 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 23:25:10.758787 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 23:25:10.762338 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 23:25:10.765555 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 23:25:10.772290 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 23:25:10.775628 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4169 23:25:10.778687 0 10 16 | B1->B0 | 3b3b 3d3d | 0 0 | (1 1) (0 0)
4170 23:25:10.785559 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 23:25:10.788649 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 23:25:10.792055 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 23:25:10.798757 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 23:25:10.802133 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 23:25:10.805324 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 23:25:10.808821 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4177 23:25:10.815220 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 23:25:10.818486 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 23:25:10.821983 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 23:25:10.828775 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 23:25:10.831777 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 23:25:10.835147 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 23:25:10.842199 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 23:25:10.845327 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 23:25:10.848744 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 23:25:10.855494 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 23:25:10.858340 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 23:25:10.861678 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 23:25:10.868461 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 23:25:10.871836 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 23:25:10.875328 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 23:25:10.882013 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4193 23:25:10.882098 Total UI for P1: 0, mck2ui 16
4194 23:25:10.888551 best dqsien dly found for B1: ( 0, 13, 10)
4195 23:25:10.891934 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 23:25:10.895032 Total UI for P1: 0, mck2ui 16
4197 23:25:10.898473 best dqsien dly found for B0: ( 0, 13, 12)
4198 23:25:10.901621 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4199 23:25:10.905114 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4200 23:25:10.905198
4201 23:25:10.908234 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4202 23:25:10.911591 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4203 23:25:10.914825 [Gating] SW calibration Done
4204 23:25:10.914934 ==
4205 23:25:10.918238 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 23:25:10.921647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 23:25:10.924850 ==
4208 23:25:10.924932 RX Vref Scan: 0
4209 23:25:10.924998
4210 23:25:10.928407 RX Vref 0 -> 0, step: 1
4211 23:25:10.928490
4212 23:25:10.931535 RX Delay -230 -> 252, step: 16
4213 23:25:10.935028 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4214 23:25:10.938339 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4215 23:25:10.941449 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4216 23:25:10.948178 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4217 23:25:10.951348 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4218 23:25:10.954788 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4219 23:25:10.958237 iDelay=218, Bit 6, Center 73 (-70 ~ 217) 288
4220 23:25:10.961598 iDelay=218, Bit 7, Center 73 (-70 ~ 217) 288
4221 23:25:10.968204 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4222 23:25:10.971488 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4223 23:25:10.974749 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4224 23:25:10.978083 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4225 23:25:10.981431 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4226 23:25:10.988064 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4227 23:25:10.991499 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4228 23:25:10.994495 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4229 23:25:10.994580 ==
4230 23:25:10.998163 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 23:25:11.004622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 23:25:11.004708 ==
4233 23:25:11.004775 DQS Delay:
4234 23:25:11.008054 DQS0 = 0, DQS1 = 0
4235 23:25:11.008164 DQM Delay:
4236 23:25:11.008259 DQM0 = 55, DQM1 = 43
4237 23:25:11.011228 DQ Delay:
4238 23:25:11.014630 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4239 23:25:11.017701 DQ4 =57, DQ5 =41, DQ6 =73, DQ7 =73
4240 23:25:11.020983 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4241 23:25:11.024393 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4242 23:25:11.024477
4243 23:25:11.024543
4244 23:25:11.024603 ==
4245 23:25:11.027906 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 23:25:11.030891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 23:25:11.030975 ==
4248 23:25:11.031042
4249 23:25:11.031103
4250 23:25:11.034248 TX Vref Scan disable
4251 23:25:11.034357 == TX Byte 0 ==
4252 23:25:11.041113 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4253 23:25:11.044079 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4254 23:25:11.044185 == TX Byte 1 ==
4255 23:25:11.050807 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4256 23:25:11.054289 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4257 23:25:11.054396 ==
4258 23:25:11.057667 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 23:25:11.060656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 23:25:11.060766 ==
4261 23:25:11.064167
4262 23:25:11.064270
4263 23:25:11.064356 TX Vref Scan disable
4264 23:25:11.067709 == TX Byte 0 ==
4265 23:25:11.070852 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4266 23:25:11.077492 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4267 23:25:11.077622 == TX Byte 1 ==
4268 23:25:11.080883 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4269 23:25:11.087888 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4270 23:25:11.087998
4271 23:25:11.088095 [DATLAT]
4272 23:25:11.088189 Freq=600, CH0 RK1
4273 23:25:11.088282
4274 23:25:11.090876 DATLAT Default: 0x9
4275 23:25:11.090978 0, 0xFFFF, sum = 0
4276 23:25:11.094228 1, 0xFFFF, sum = 0
4277 23:25:11.094360 2, 0xFFFF, sum = 0
4278 23:25:11.097636 3, 0xFFFF, sum = 0
4279 23:25:11.101057 4, 0xFFFF, sum = 0
4280 23:25:11.101185 5, 0xFFFF, sum = 0
4281 23:25:11.104219 6, 0xFFFF, sum = 0
4282 23:25:11.104348 7, 0xFFFF, sum = 0
4283 23:25:11.107744 8, 0x0, sum = 1
4284 23:25:11.107855 9, 0x0, sum = 2
4285 23:25:11.107951 10, 0x0, sum = 3
4286 23:25:11.111189 11, 0x0, sum = 4
4287 23:25:11.111305 best_step = 9
4288 23:25:11.111400
4289 23:25:11.111498 ==
4290 23:25:11.114210 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 23:25:11.121050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 23:25:11.121162 ==
4293 23:25:11.121256 RX Vref Scan: 0
4294 23:25:11.121358
4295 23:25:11.124045 RX Vref 0 -> 0, step: 1
4296 23:25:11.124145
4297 23:25:11.127474 RX Delay -163 -> 252, step: 8
4298 23:25:11.130792 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4299 23:25:11.137465 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4300 23:25:11.140803 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4301 23:25:11.144124 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4302 23:25:11.147531 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4303 23:25:11.150981 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4304 23:25:11.154043 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4305 23:25:11.160976 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4306 23:25:11.164381 iDelay=197, Bit 8, Center 40 (-99 ~ 180) 280
4307 23:25:11.167528 iDelay=197, Bit 9, Center 32 (-107 ~ 172) 280
4308 23:25:11.170562 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4309 23:25:11.177377 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4310 23:25:11.180861 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4311 23:25:11.184088 iDelay=197, Bit 13, Center 56 (-83 ~ 196) 280
4312 23:25:11.187419 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4313 23:25:11.190579 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4314 23:25:11.190685 ==
4315 23:25:11.194065 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 23:25:11.200785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 23:25:11.200870 ==
4318 23:25:11.200935 DQS Delay:
4319 23:25:11.204020 DQS0 = 0, DQS1 = 0
4320 23:25:11.204123 DQM Delay:
4321 23:25:11.207132 DQM0 = 52, DQM1 = 47
4322 23:25:11.207243 DQ Delay:
4323 23:25:11.210787 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4324 23:25:11.214124 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4325 23:25:11.217119 DQ8 =40, DQ9 =32, DQ10 =48, DQ11 =40
4326 23:25:11.220669 DQ12 =52, DQ13 =56, DQ14 =56, DQ15 =52
4327 23:25:11.220752
4328 23:25:11.220817
4329 23:25:11.227170 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4330 23:25:11.230566 CH0 RK1: MR19=808, MR18=5F21
4331 23:25:11.237367 CH0_RK1: MR19=0x808, MR18=0x5F21, DQSOSC=391, MR23=63, INC=171, DEC=114
4332 23:25:11.240734 [RxdqsGatingPostProcess] freq 600
4333 23:25:11.244190 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4334 23:25:11.247306 Pre-setting of DQS Precalculation
4335 23:25:11.253938 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4336 23:25:11.254024 ==
4337 23:25:11.257151 Dram Type= 6, Freq= 0, CH_1, rank 0
4338 23:25:11.260719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 23:25:11.260802 ==
4340 23:25:11.267153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4341 23:25:11.273671 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4342 23:25:11.277121 [CA 0] Center 36 (5~67) winsize 63
4343 23:25:11.280526 [CA 1] Center 36 (5~67) winsize 63
4344 23:25:11.283783 [CA 2] Center 34 (4~65) winsize 62
4345 23:25:11.287041 [CA 3] Center 34 (4~65) winsize 62
4346 23:25:11.290893 [CA 4] Center 34 (4~65) winsize 62
4347 23:25:11.291018 [CA 5] Center 33 (3~64) winsize 62
4348 23:25:11.294133
4349 23:25:11.297319 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4350 23:25:11.297430
4351 23:25:11.300798 [CATrainingPosCal] consider 1 rank data
4352 23:25:11.304013 u2DelayCellTimex100 = 270/100 ps
4353 23:25:11.307199 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4354 23:25:11.310544 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4355 23:25:11.313963 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4356 23:25:11.317393 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4357 23:25:11.320341 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4358 23:25:11.323745 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4359 23:25:11.323874
4360 23:25:11.327155 CA PerBit enable=1, Macro0, CA PI delay=33
4361 23:25:11.330605
4362 23:25:11.330717 [CBTSetCACLKResult] CA Dly = 33
4363 23:25:11.333532 CS Dly: 6 (0~37)
4364 23:25:11.333622 ==
4365 23:25:11.337115 Dram Type= 6, Freq= 0, CH_1, rank 1
4366 23:25:11.340239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 23:25:11.340352 ==
4368 23:25:11.347055 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 23:25:11.353472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4370 23:25:11.356783 [CA 0] Center 36 (6~67) winsize 62
4371 23:25:11.360123 [CA 1] Center 36 (6~67) winsize 62
4372 23:25:11.363193 [CA 2] Center 35 (5~66) winsize 62
4373 23:25:11.366627 [CA 3] Center 35 (4~66) winsize 63
4374 23:25:11.369587 [CA 4] Center 35 (4~66) winsize 63
4375 23:25:11.373109 [CA 5] Center 34 (4~65) winsize 62
4376 23:25:11.373194
4377 23:25:11.376533 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4378 23:25:11.376639
4379 23:25:11.379646 [CATrainingPosCal] consider 2 rank data
4380 23:25:11.383017 u2DelayCellTimex100 = 270/100 ps
4381 23:25:11.386493 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4382 23:25:11.389508 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4383 23:25:11.392948 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4384 23:25:11.396367 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4385 23:25:11.399640 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4386 23:25:11.406079 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4387 23:25:11.406199
4388 23:25:11.409415 CA PerBit enable=1, Macro0, CA PI delay=34
4389 23:25:11.409496
4390 23:25:11.412982 [CBTSetCACLKResult] CA Dly = 34
4391 23:25:11.413059 CS Dly: 6 (0~38)
4392 23:25:11.413134
4393 23:25:11.416050 ----->DramcWriteLeveling(PI) begin...
4394 23:25:11.416140 ==
4395 23:25:11.419549 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 23:25:11.426064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 23:25:11.426151 ==
4398 23:25:11.429309 Write leveling (Byte 0): 30 => 30
4399 23:25:11.432386 Write leveling (Byte 1): 30 => 30
4400 23:25:11.432474 DramcWriteLeveling(PI) end<-----
4401 23:25:11.432542
4402 23:25:11.435893 ==
4403 23:25:11.439165 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 23:25:11.442281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 23:25:11.442373 ==
4406 23:25:11.445794 [Gating] SW mode calibration
4407 23:25:11.452410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 23:25:11.455412 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4409 23:25:11.462286 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 23:25:11.465662 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 23:25:11.468929 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4412 23:25:11.475569 0 9 12 | B1->B0 | 3030 3030 | 1 0 | (1 1) (0 1)
4413 23:25:11.478991 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 23:25:11.482077 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 23:25:11.488864 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 23:25:11.491973 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 23:25:11.495418 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 23:25:11.502250 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 23:25:11.505251 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 23:25:11.508810 0 10 12 | B1->B0 | 3838 3e3e | 0 0 | (0 0) (0 0)
4421 23:25:11.515287 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 23:25:11.518717 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 23:25:11.522109 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 23:25:11.528559 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 23:25:11.532079 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 23:25:11.535459 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 23:25:11.542017 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 23:25:11.545056 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4429 23:25:11.548569 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 23:25:11.552027 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 23:25:11.558371 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 23:25:11.561839 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 23:25:11.565014 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 23:25:11.571735 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 23:25:11.575094 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 23:25:11.578233 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 23:25:11.585075 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 23:25:11.588184 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 23:25:11.591682 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 23:25:11.598181 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 23:25:11.601610 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 23:25:11.605070 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 23:25:11.611698 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4444 23:25:11.614683 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4445 23:25:11.618157 Total UI for P1: 0, mck2ui 16
4446 23:25:11.621433 best dqsien dly found for B0: ( 0, 13, 8)
4447 23:25:11.624796 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 23:25:11.627996 Total UI for P1: 0, mck2ui 16
4449 23:25:11.631409 best dqsien dly found for B1: ( 0, 13, 12)
4450 23:25:11.634377 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4451 23:25:11.637947 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4452 23:25:11.641423
4453 23:25:11.644953 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4454 23:25:11.647916 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4455 23:25:11.651532 [Gating] SW calibration Done
4456 23:25:11.651648 ==
4457 23:25:11.654554 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 23:25:11.657841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 23:25:11.657946 ==
4460 23:25:11.658056 RX Vref Scan: 0
4461 23:25:11.658153
4462 23:25:11.661313 RX Vref 0 -> 0, step: 1
4463 23:25:11.661417
4464 23:25:11.664650 RX Delay -230 -> 252, step: 16
4465 23:25:11.668017 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4466 23:25:11.671291 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4467 23:25:11.678014 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4468 23:25:11.681237 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4469 23:25:11.684542 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4470 23:25:11.687869 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4471 23:25:11.694598 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4472 23:25:11.698100 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4473 23:25:11.701198 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4474 23:25:11.704723 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4475 23:25:11.708142 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4476 23:25:11.714455 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4477 23:25:11.718105 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4478 23:25:11.721496 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4479 23:25:11.724597 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4480 23:25:11.731044 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4481 23:25:11.731126 ==
4482 23:25:11.734470 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 23:25:11.738040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 23:25:11.738123 ==
4485 23:25:11.738188 DQS Delay:
4486 23:25:11.741063 DQS0 = 0, DQS1 = 0
4487 23:25:11.741145 DQM Delay:
4488 23:25:11.744571 DQM0 = 52, DQM1 = 49
4489 23:25:11.744653 DQ Delay:
4490 23:25:11.747894 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4491 23:25:11.750899 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4492 23:25:11.754568 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4493 23:25:11.757745 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4494 23:25:11.757827
4495 23:25:11.757893
4496 23:25:11.757953 ==
4497 23:25:11.761052 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 23:25:11.764574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 23:25:11.764657 ==
4500 23:25:11.764723
4501 23:25:11.767690
4502 23:25:11.767771 TX Vref Scan disable
4503 23:25:11.771186 == TX Byte 0 ==
4504 23:25:11.774417 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4505 23:25:11.777609 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4506 23:25:11.780979 == TX Byte 1 ==
4507 23:25:11.784738 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4508 23:25:11.787868 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4509 23:25:11.787980 ==
4510 23:25:11.791097 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 23:25:11.797851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 23:25:11.797959 ==
4513 23:25:11.798073
4514 23:25:11.798179
4515 23:25:11.798284 TX Vref Scan disable
4516 23:25:11.801922 == TX Byte 0 ==
4517 23:25:11.805549 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4518 23:25:11.812048 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4519 23:25:11.812167 == TX Byte 1 ==
4520 23:25:11.815234 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 23:25:11.821855 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 23:25:11.821941
4523 23:25:11.822007 [DATLAT]
4524 23:25:11.822069 Freq=600, CH1 RK0
4525 23:25:11.822128
4526 23:25:11.825337 DATLAT Default: 0x9
4527 23:25:11.825419 0, 0xFFFF, sum = 0
4528 23:25:11.828808 1, 0xFFFF, sum = 0
4529 23:25:11.831785 2, 0xFFFF, sum = 0
4530 23:25:11.831868 3, 0xFFFF, sum = 0
4531 23:25:11.835219 4, 0xFFFF, sum = 0
4532 23:25:11.835303 5, 0xFFFF, sum = 0
4533 23:25:11.838642 6, 0xFFFF, sum = 0
4534 23:25:11.838725 7, 0xFFFF, sum = 0
4535 23:25:11.842070 8, 0x0, sum = 1
4536 23:25:11.842154 9, 0x0, sum = 2
4537 23:25:11.842220 10, 0x0, sum = 3
4538 23:25:11.845069 11, 0x0, sum = 4
4539 23:25:11.845153 best_step = 9
4540 23:25:11.845218
4541 23:25:11.845278 ==
4542 23:25:11.848577 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 23:25:11.854906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 23:25:11.854990 ==
4545 23:25:11.855055 RX Vref Scan: 1
4546 23:25:11.855117
4547 23:25:11.858355 RX Vref 0 -> 0, step: 1
4548 23:25:11.858465
4549 23:25:11.861793 RX Delay -147 -> 252, step: 8
4550 23:25:11.861876
4551 23:25:11.864736 Set Vref, RX VrefLevel [Byte0]: 54
4552 23:25:11.868404 [Byte1]: 53
4553 23:25:11.868492
4554 23:25:11.871872 Final RX Vref Byte 0 = 54 to rank0
4555 23:25:11.874802 Final RX Vref Byte 1 = 53 to rank0
4556 23:25:11.878351 Final RX Vref Byte 0 = 54 to rank1
4557 23:25:11.881674 Final RX Vref Byte 1 = 53 to rank1==
4558 23:25:11.885031 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 23:25:11.888350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 23:25:11.888455 ==
4561 23:25:11.891731 DQS Delay:
4562 23:25:11.891832 DQS0 = 0, DQS1 = 0
4563 23:25:11.894819 DQM Delay:
4564 23:25:11.894900 DQM0 = 48, DQM1 = 45
4565 23:25:11.894989 DQ Delay:
4566 23:25:11.898144 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4567 23:25:11.901561 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4568 23:25:11.905129 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4569 23:25:11.908118 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4570 23:25:11.908226
4571 23:25:11.908335
4572 23:25:11.917940 [DQSOSCAuto] RK0, (LSB)MR18= 0x466b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4573 23:25:11.921362 CH1 RK0: MR19=808, MR18=466B
4574 23:25:11.927858 CH1_RK0: MR19=0x808, MR18=0x466B, DQSOSC=389, MR23=63, INC=173, DEC=115
4575 23:25:11.927974
4576 23:25:11.931360 ----->DramcWriteLeveling(PI) begin...
4577 23:25:11.931475 ==
4578 23:25:11.934837 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 23:25:11.938316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 23:25:11.938419 ==
4581 23:25:11.941343 Write leveling (Byte 0): 31 => 31
4582 23:25:11.944641 Write leveling (Byte 1): 31 => 31
4583 23:25:11.948228 DramcWriteLeveling(PI) end<-----
4584 23:25:11.948342
4585 23:25:11.948437 ==
4586 23:25:11.951317 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 23:25:11.954988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 23:25:11.955077 ==
4589 23:25:11.958041 [Gating] SW mode calibration
4590 23:25:11.964769 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4591 23:25:11.971126 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4592 23:25:11.974495 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 23:25:11.978038 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 23:25:11.984380 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 23:25:11.987886 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (1 1) (1 1)
4596 23:25:11.991326 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 23:25:11.997974 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 23:25:12.000990 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 23:25:12.004478 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 23:25:12.007894 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 23:25:12.014741 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 23:25:12.017677 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 23:25:12.021226 0 10 12 | B1->B0 | 3a3a 3232 | 0 1 | (0 0) (0 0)
4604 23:25:12.027921 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 23:25:12.031138 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 23:25:12.034385 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 23:25:12.041312 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 23:25:12.044593 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 23:25:12.047899 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 23:25:12.054346 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4611 23:25:12.057756 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4612 23:25:12.060731 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 23:25:12.067662 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 23:25:12.071188 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 23:25:12.074273 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 23:25:12.081242 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 23:25:12.084487 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 23:25:12.087625 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 23:25:12.094321 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 23:25:12.097781 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 23:25:12.101147 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 23:25:12.107442 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 23:25:12.110743 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 23:25:12.114286 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 23:25:12.120937 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 23:25:12.123970 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4627 23:25:12.127404 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4628 23:25:12.133921 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 23:25:12.134008 Total UI for P1: 0, mck2ui 16
4630 23:25:12.137189 best dqsien dly found for B0: ( 0, 13, 14)
4631 23:25:12.140650 Total UI for P1: 0, mck2ui 16
4632 23:25:12.144059 best dqsien dly found for B1: ( 0, 13, 10)
4633 23:25:12.150511 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4634 23:25:12.153734 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4635 23:25:12.153836
4636 23:25:12.157230 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4637 23:25:12.160647 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4638 23:25:12.164145 [Gating] SW calibration Done
4639 23:25:12.164253 ==
4640 23:25:12.167052 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 23:25:12.170308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 23:25:12.170414 ==
4643 23:25:12.173752 RX Vref Scan: 0
4644 23:25:12.173867
4645 23:25:12.173961 RX Vref 0 -> 0, step: 1
4646 23:25:12.174052
4647 23:25:12.177200 RX Delay -230 -> 252, step: 16
4648 23:25:12.180165 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4649 23:25:12.187087 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4650 23:25:12.190495 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4651 23:25:12.193624 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4652 23:25:12.197037 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4653 23:25:12.203462 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4654 23:25:12.206904 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4655 23:25:12.210232 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4656 23:25:12.213217 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4657 23:25:12.216604 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4658 23:25:12.223242 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4659 23:25:12.226582 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4660 23:25:12.230130 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4661 23:25:12.233172 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4662 23:25:12.239968 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4663 23:25:12.243194 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4664 23:25:12.243315 ==
4665 23:25:12.246447 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 23:25:12.249784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 23:25:12.249888 ==
4668 23:25:12.252943 DQS Delay:
4669 23:25:12.253031 DQS0 = 0, DQS1 = 0
4670 23:25:12.256365 DQM Delay:
4671 23:25:12.256498 DQM0 = 50, DQM1 = 48
4672 23:25:12.256614 DQ Delay:
4673 23:25:12.259850 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4674 23:25:12.262906 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4675 23:25:12.266219 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4676 23:25:12.269750 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4677 23:25:12.269872
4678 23:25:12.269989
4679 23:25:12.270100 ==
4680 23:25:12.273128 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 23:25:12.279585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 23:25:12.279671 ==
4683 23:25:12.279738
4684 23:25:12.279800
4685 23:25:12.279859 TX Vref Scan disable
4686 23:25:12.283495 == TX Byte 0 ==
4687 23:25:12.286888 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4688 23:25:12.293642 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4689 23:25:12.293726 == TX Byte 1 ==
4690 23:25:12.296876 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4691 23:25:12.303371 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4692 23:25:12.303455 ==
4693 23:25:12.306768 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 23:25:12.310237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 23:25:12.310322 ==
4696 23:25:12.310388
4697 23:25:12.310450
4698 23:25:12.313518 TX Vref Scan disable
4699 23:25:12.316563 == TX Byte 0 ==
4700 23:25:12.320113 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4701 23:25:12.323496 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4702 23:25:12.326567 == TX Byte 1 ==
4703 23:25:12.330114 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4704 23:25:12.333446 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4705 23:25:12.333532
4706 23:25:12.333598 [DATLAT]
4707 23:25:12.336605 Freq=600, CH1 RK1
4708 23:25:12.336714
4709 23:25:12.336818 DATLAT Default: 0x9
4710 23:25:12.339802 0, 0xFFFF, sum = 0
4711 23:25:12.343011 1, 0xFFFF, sum = 0
4712 23:25:12.343102 2, 0xFFFF, sum = 0
4713 23:25:12.346583 3, 0xFFFF, sum = 0
4714 23:25:12.346694 4, 0xFFFF, sum = 0
4715 23:25:12.349948 5, 0xFFFF, sum = 0
4716 23:25:12.350022 6, 0xFFFF, sum = 0
4717 23:25:12.353367 7, 0xFFFF, sum = 0
4718 23:25:12.353441 8, 0x0, sum = 1
4719 23:25:12.356400 9, 0x0, sum = 2
4720 23:25:12.356507 10, 0x0, sum = 3
4721 23:25:12.356601 11, 0x0, sum = 4
4722 23:25:12.359734 best_step = 9
4723 23:25:12.359826
4724 23:25:12.359892 ==
4725 23:25:12.363074 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 23:25:12.366281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 23:25:12.366362 ==
4728 23:25:12.369880 RX Vref Scan: 0
4729 23:25:12.369956
4730 23:25:12.370021 RX Vref 0 -> 0, step: 1
4731 23:25:12.373061
4732 23:25:12.373147 RX Delay -163 -> 252, step: 8
4733 23:25:12.380959 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4734 23:25:12.384052 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4735 23:25:12.387229 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4736 23:25:12.390575 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4737 23:25:12.394032 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4738 23:25:12.400704 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4739 23:25:12.403677 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4740 23:25:12.407264 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4741 23:25:12.410618 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4742 23:25:12.416909 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4743 23:25:12.420283 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4744 23:25:12.423696 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4745 23:25:12.427047 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4746 23:25:12.430572 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4747 23:25:12.436931 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4748 23:25:12.440218 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4749 23:25:12.440331 ==
4750 23:25:12.443621 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 23:25:12.447015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 23:25:12.447100 ==
4753 23:25:12.450047 DQS Delay:
4754 23:25:12.450130 DQS0 = 0, DQS1 = 0
4755 23:25:12.450196 DQM Delay:
4756 23:25:12.453401 DQM0 = 49, DQM1 = 46
4757 23:25:12.453485 DQ Delay:
4758 23:25:12.456865 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4759 23:25:12.460260 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4760 23:25:12.463519 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4761 23:25:12.466754 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4762 23:25:12.466839
4763 23:25:12.466905
4764 23:25:12.476554 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4765 23:25:12.480045 CH1 RK1: MR19=808, MR18=6B23
4766 23:25:12.483105 CH1_RK1: MR19=0x808, MR18=0x6B23, DQSOSC=389, MR23=63, INC=173, DEC=115
4767 23:25:12.486808 [RxdqsGatingPostProcess] freq 600
4768 23:25:12.493119 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4769 23:25:12.496573 Pre-setting of DQS Precalculation
4770 23:25:12.499944 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4771 23:25:12.510060 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4772 23:25:12.516397 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4773 23:25:12.516493
4774 23:25:12.516560
4775 23:25:12.519900 [Calibration Summary] 1200 Mbps
4776 23:25:12.520007 CH 0, Rank 0
4777 23:25:12.523193 SW Impedance : PASS
4778 23:25:12.523294 DUTY Scan : NO K
4779 23:25:12.526613 ZQ Calibration : PASS
4780 23:25:12.529529 Jitter Meter : NO K
4781 23:25:12.529605 CBT Training : PASS
4782 23:25:12.533022 Write leveling : PASS
4783 23:25:12.536493 RX DQS gating : PASS
4784 23:25:12.536569 RX DQ/DQS(RDDQC) : PASS
4785 23:25:12.539547 TX DQ/DQS : PASS
4786 23:25:12.539618 RX DATLAT : PASS
4787 23:25:12.542991 RX DQ/DQS(Engine): PASS
4788 23:25:12.546122 TX OE : NO K
4789 23:25:12.546206 All Pass.
4790 23:25:12.546271
4791 23:25:12.546336 CH 0, Rank 1
4792 23:25:12.549534 SW Impedance : PASS
4793 23:25:12.552986 DUTY Scan : NO K
4794 23:25:12.553095 ZQ Calibration : PASS
4795 23:25:12.556067 Jitter Meter : NO K
4796 23:25:12.559520 CBT Training : PASS
4797 23:25:12.559602 Write leveling : PASS
4798 23:25:12.562962 RX DQS gating : PASS
4799 23:25:12.566417 RX DQ/DQS(RDDQC) : PASS
4800 23:25:12.566533 TX DQ/DQS : PASS
4801 23:25:12.569447 RX DATLAT : PASS
4802 23:25:12.572964 RX DQ/DQS(Engine): PASS
4803 23:25:12.573041 TX OE : NO K
4804 23:25:12.576076 All Pass.
4805 23:25:12.576180
4806 23:25:12.576276 CH 1, Rank 0
4807 23:25:12.579321 SW Impedance : PASS
4808 23:25:12.579425 DUTY Scan : NO K
4809 23:25:12.582757 ZQ Calibration : PASS
4810 23:25:12.586140 Jitter Meter : NO K
4811 23:25:12.586217 CBT Training : PASS
4812 23:25:12.589549 Write leveling : PASS
4813 23:25:12.593048 RX DQS gating : PASS
4814 23:25:12.593130 RX DQ/DQS(RDDQC) : PASS
4815 23:25:12.595966 TX DQ/DQS : PASS
4816 23:25:12.596049 RX DATLAT : PASS
4817 23:25:12.599557 RX DQ/DQS(Engine): PASS
4818 23:25:12.602831 TX OE : NO K
4819 23:25:12.602916 All Pass.
4820 23:25:12.602982
4821 23:25:12.603042 CH 1, Rank 1
4822 23:25:12.606117 SW Impedance : PASS
4823 23:25:12.609332 DUTY Scan : NO K
4824 23:25:12.609416 ZQ Calibration : PASS
4825 23:25:12.612655 Jitter Meter : NO K
4826 23:25:12.615908 CBT Training : PASS
4827 23:25:12.615986 Write leveling : PASS
4828 23:25:12.619460 RX DQS gating : PASS
4829 23:25:12.622745 RX DQ/DQS(RDDQC) : PASS
4830 23:25:12.622821 TX DQ/DQS : PASS
4831 23:25:12.626065 RX DATLAT : PASS
4832 23:25:12.629269 RX DQ/DQS(Engine): PASS
4833 23:25:12.629352 TX OE : NO K
4834 23:25:12.632653 All Pass.
4835 23:25:12.632735
4836 23:25:12.632800 DramC Write-DBI off
4837 23:25:12.635925 PER_BANK_REFRESH: Hybrid Mode
4838 23:25:12.636015 TX_TRACKING: ON
4839 23:25:12.645940 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4840 23:25:12.649383 [FAST_K] Save calibration result to emmc
4841 23:25:12.652687 dramc_set_vcore_voltage set vcore to 662500
4842 23:25:12.655755 Read voltage for 933, 3
4843 23:25:12.655837 Vio18 = 0
4844 23:25:12.659170 Vcore = 662500
4845 23:25:12.659253 Vdram = 0
4846 23:25:12.659318 Vddq = 0
4847 23:25:12.659379 Vmddr = 0
4848 23:25:12.665591 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4849 23:25:12.672479 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4850 23:25:12.672563 MEM_TYPE=3, freq_sel=17
4851 23:25:12.675439 sv_algorithm_assistance_LP4_1600
4852 23:25:12.678896 ============ PULL DRAM RESETB DOWN ============
4853 23:25:12.685542 ========== PULL DRAM RESETB DOWN end =========
4854 23:25:12.688946 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4855 23:25:12.692145 ===================================
4856 23:25:12.695600 LPDDR4 DRAM CONFIGURATION
4857 23:25:12.699119 ===================================
4858 23:25:12.699213 EX_ROW_EN[0] = 0x0
4859 23:25:12.702198 EX_ROW_EN[1] = 0x0
4860 23:25:12.702283 LP4Y_EN = 0x0
4861 23:25:12.705560 WORK_FSP = 0x0
4862 23:25:12.708850 WL = 0x3
4863 23:25:12.708937 RL = 0x3
4864 23:25:12.712283 BL = 0x2
4865 23:25:12.712371 RPST = 0x0
4866 23:25:12.715299 RD_PRE = 0x0
4867 23:25:12.715382 WR_PRE = 0x1
4868 23:25:12.718722 WR_PST = 0x0
4869 23:25:12.718799 DBI_WR = 0x0
4870 23:25:12.722043 DBI_RD = 0x0
4871 23:25:12.722126 OTF = 0x1
4872 23:25:12.725597 ===================================
4873 23:25:12.728984 ===================================
4874 23:25:12.732220 ANA top config
4875 23:25:12.735437 ===================================
4876 23:25:12.735523 DLL_ASYNC_EN = 0
4877 23:25:12.738820 ALL_SLAVE_EN = 1
4878 23:25:12.742191 NEW_RANK_MODE = 1
4879 23:25:12.745483 DLL_IDLE_MODE = 1
4880 23:25:12.745589 LP45_APHY_COMB_EN = 1
4881 23:25:12.748616 TX_ODT_DIS = 1
4882 23:25:12.752097 NEW_8X_MODE = 1
4883 23:25:12.755317 ===================================
4884 23:25:12.758651 ===================================
4885 23:25:12.761744 data_rate = 1866
4886 23:25:12.765071 CKR = 1
4887 23:25:12.768398 DQ_P2S_RATIO = 8
4888 23:25:12.771739 ===================================
4889 23:25:12.771845 CA_P2S_RATIO = 8
4890 23:25:12.775207 DQ_CA_OPEN = 0
4891 23:25:12.778229 DQ_SEMI_OPEN = 0
4892 23:25:12.781820 CA_SEMI_OPEN = 0
4893 23:25:12.784875 CA_FULL_RATE = 0
4894 23:25:12.788101 DQ_CKDIV4_EN = 1
4895 23:25:12.788209 CA_CKDIV4_EN = 1
4896 23:25:12.791690 CA_PREDIV_EN = 0
4897 23:25:12.795146 PH8_DLY = 0
4898 23:25:12.798252 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4899 23:25:12.801630 DQ_AAMCK_DIV = 4
4900 23:25:12.804746 CA_AAMCK_DIV = 4
4901 23:25:12.804828 CA_ADMCK_DIV = 4
4902 23:25:12.808117 DQ_TRACK_CA_EN = 0
4903 23:25:12.811561 CA_PICK = 933
4904 23:25:12.814659 CA_MCKIO = 933
4905 23:25:12.818276 MCKIO_SEMI = 0
4906 23:25:12.821660 PLL_FREQ = 3732
4907 23:25:12.824703 DQ_UI_PI_RATIO = 32
4908 23:25:12.824781 CA_UI_PI_RATIO = 0
4909 23:25:12.828026 ===================================
4910 23:25:12.831507 ===================================
4911 23:25:12.834793 memory_type:LPDDR4
4912 23:25:12.838033 GP_NUM : 10
4913 23:25:12.838115 SRAM_EN : 1
4914 23:25:12.841294 MD32_EN : 0
4915 23:25:12.844752 ===================================
4916 23:25:12.847985 [ANA_INIT] >>>>>>>>>>>>>>
4917 23:25:12.851244 <<<<<< [CONFIGURE PHASE]: ANA_TX
4918 23:25:12.854564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4919 23:25:12.858107 ===================================
4920 23:25:12.858187 data_rate = 1866,PCW = 0X8f00
4921 23:25:12.861412 ===================================
4922 23:25:12.864784 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4923 23:25:12.871403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 23:25:12.877667 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 23:25:12.881105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4926 23:25:12.884677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4927 23:25:12.887888 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4928 23:25:12.891035 [ANA_INIT] flow start
4929 23:25:12.894578 [ANA_INIT] PLL >>>>>>>>
4930 23:25:12.894697 [ANA_INIT] PLL <<<<<<<<
4931 23:25:12.897942 [ANA_INIT] MIDPI >>>>>>>>
4932 23:25:12.901146 [ANA_INIT] MIDPI <<<<<<<<
4933 23:25:12.901270 [ANA_INIT] DLL >>>>>>>>
4934 23:25:12.904219 [ANA_INIT] flow end
4935 23:25:12.907681 ============ LP4 DIFF to SE enter ============
4936 23:25:12.911088 ============ LP4 DIFF to SE exit ============
4937 23:25:12.914110 [ANA_INIT] <<<<<<<<<<<<<
4938 23:25:12.917679 [Flow] Enable top DCM control >>>>>
4939 23:25:12.921145 [Flow] Enable top DCM control <<<<<
4940 23:25:12.924191 Enable DLL master slave shuffle
4941 23:25:12.930737 ==============================================================
4942 23:25:12.930825 Gating Mode config
4943 23:25:12.937613 ==============================================================
4944 23:25:12.937697 Config description:
4945 23:25:12.947138 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4946 23:25:12.954145 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4947 23:25:12.960717 SELPH_MODE 0: By rank 1: By Phase
4948 23:25:12.963741 ==============================================================
4949 23:25:12.967093 GAT_TRACK_EN = 1
4950 23:25:12.970502 RX_GATING_MODE = 2
4951 23:25:12.974003 RX_GATING_TRACK_MODE = 2
4952 23:25:12.977104 SELPH_MODE = 1
4953 23:25:12.980554 PICG_EARLY_EN = 1
4954 23:25:12.983650 VALID_LAT_VALUE = 1
4955 23:25:12.990312 ==============================================================
4956 23:25:12.993811 Enter into Gating configuration >>>>
4957 23:25:12.996760 Exit from Gating configuration <<<<
4958 23:25:13.000530 Enter into DVFS_PRE_config >>>>>
4959 23:25:13.010177 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4960 23:25:13.013593 Exit from DVFS_PRE_config <<<<<
4961 23:25:13.016890 Enter into PICG configuration >>>>
4962 23:25:13.020120 Exit from PICG configuration <<<<
4963 23:25:13.023251 [RX_INPUT] configuration >>>>>
4964 23:25:13.023361 [RX_INPUT] configuration <<<<<
4965 23:25:13.030251 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4966 23:25:13.036766 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4967 23:25:13.040126 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 23:25:13.046768 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 23:25:13.053521 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 23:25:13.060032 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 23:25:13.063319 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4972 23:25:13.066767 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4973 23:25:13.073262 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4974 23:25:13.076689 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4975 23:25:13.079933 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4976 23:25:13.086490 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4977 23:25:13.089954 ===================================
4978 23:25:13.090032 LPDDR4 DRAM CONFIGURATION
4979 23:25:13.092948 ===================================
4980 23:25:13.096276 EX_ROW_EN[0] = 0x0
4981 23:25:13.096398 EX_ROW_EN[1] = 0x0
4982 23:25:13.099669 LP4Y_EN = 0x0
4983 23:25:13.102853 WORK_FSP = 0x0
4984 23:25:13.102936 WL = 0x3
4985 23:25:13.106228 RL = 0x3
4986 23:25:13.106305 BL = 0x2
4987 23:25:13.109658 RPST = 0x0
4988 23:25:13.109736 RD_PRE = 0x0
4989 23:25:13.113069 WR_PRE = 0x1
4990 23:25:13.113156 WR_PST = 0x0
4991 23:25:13.116385 DBI_WR = 0x0
4992 23:25:13.116463 DBI_RD = 0x0
4993 23:25:13.119546 OTF = 0x1
4994 23:25:13.122748 ===================================
4995 23:25:13.126287 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4996 23:25:13.129381 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4997 23:25:13.136177 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 23:25:13.139453 ===================================
4999 23:25:13.139540 LPDDR4 DRAM CONFIGURATION
5000 23:25:13.142932 ===================================
5001 23:25:13.146250 EX_ROW_EN[0] = 0x10
5002 23:25:13.146379 EX_ROW_EN[1] = 0x0
5003 23:25:13.149361 LP4Y_EN = 0x0
5004 23:25:13.149483 WORK_FSP = 0x0
5005 23:25:13.152714 WL = 0x3
5006 23:25:13.156200 RL = 0x3
5007 23:25:13.156341 BL = 0x2
5008 23:25:13.159248 RPST = 0x0
5009 23:25:13.159358 RD_PRE = 0x0
5010 23:25:13.162872 WR_PRE = 0x1
5011 23:25:13.162987 WR_PST = 0x0
5012 23:25:13.165996 DBI_WR = 0x0
5013 23:25:13.166094 DBI_RD = 0x0
5014 23:25:13.169233 OTF = 0x1
5015 23:25:13.172582 ===================================
5016 23:25:13.179024 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5017 23:25:13.182435 nWR fixed to 30
5018 23:25:13.182523 [ModeRegInit_LP4] CH0 RK0
5019 23:25:13.185710 [ModeRegInit_LP4] CH0 RK1
5020 23:25:13.189128 [ModeRegInit_LP4] CH1 RK0
5021 23:25:13.189210 [ModeRegInit_LP4] CH1 RK1
5022 23:25:13.192594 match AC timing 9
5023 23:25:13.195732 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5024 23:25:13.199433 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5025 23:25:13.205896 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5026 23:25:13.209359 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5027 23:25:13.215682 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5028 23:25:13.215799 ==
5029 23:25:13.219106 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 23:25:13.222630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5031 23:25:13.222748 ==
5032 23:25:13.229113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5033 23:25:13.232581 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5034 23:25:13.236487 [CA 0] Center 37 (6~68) winsize 63
5035 23:25:13.239916 [CA 1] Center 37 (7~68) winsize 62
5036 23:25:13.243240 [CA 2] Center 34 (4~65) winsize 62
5037 23:25:13.246556 [CA 3] Center 34 (3~65) winsize 63
5038 23:25:13.249958 [CA 4] Center 33 (3~63) winsize 61
5039 23:25:13.253396 [CA 5] Center 32 (2~62) winsize 61
5040 23:25:13.253479
5041 23:25:13.256453 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5042 23:25:13.256533
5043 23:25:13.259877 [CATrainingPosCal] consider 1 rank data
5044 23:25:13.263155 u2DelayCellTimex100 = 270/100 ps
5045 23:25:13.266766 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5046 23:25:13.269997 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5047 23:25:13.276787 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5048 23:25:13.280142 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5049 23:25:13.283588 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5050 23:25:13.287045 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5051 23:25:13.287121
5052 23:25:13.290126 CA PerBit enable=1, Macro0, CA PI delay=32
5053 23:25:13.290221
5054 23:25:13.293403 [CBTSetCACLKResult] CA Dly = 32
5055 23:25:13.293522 CS Dly: 5 (0~36)
5056 23:25:13.296658 ==
5057 23:25:13.296770 Dram Type= 6, Freq= 0, CH_0, rank 1
5058 23:25:13.303560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 23:25:13.303642 ==
5060 23:25:13.306619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 23:25:13.313338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5062 23:25:13.316895 [CA 0] Center 37 (6~68) winsize 63
5063 23:25:13.319866 [CA 1] Center 37 (6~68) winsize 63
5064 23:25:13.323460 [CA 2] Center 34 (4~65) winsize 62
5065 23:25:13.326963 [CA 3] Center 34 (3~65) winsize 63
5066 23:25:13.330037 [CA 4] Center 33 (3~63) winsize 61
5067 23:25:13.333295 [CA 5] Center 32 (2~62) winsize 61
5068 23:25:13.333396
5069 23:25:13.336581 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5070 23:25:13.336658
5071 23:25:13.339932 [CATrainingPosCal] consider 2 rank data
5072 23:25:13.343313 u2DelayCellTimex100 = 270/100 ps
5073 23:25:13.346802 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5074 23:25:13.353362 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5075 23:25:13.356675 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5076 23:25:13.359987 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5077 23:25:13.363092 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5078 23:25:13.366590 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5079 23:25:13.366673
5080 23:25:13.369857 CA PerBit enable=1, Macro0, CA PI delay=32
5081 23:25:13.369941
5082 23:25:13.373086 [CBTSetCACLKResult] CA Dly = 32
5083 23:25:13.376537 CS Dly: 5 (0~37)
5084 23:25:13.376622
5085 23:25:13.379874 ----->DramcWriteLeveling(PI) begin...
5086 23:25:13.380005 ==
5087 23:25:13.382925 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 23:25:13.386157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 23:25:13.386239 ==
5090 23:25:13.389651 Write leveling (Byte 0): 31 => 31
5091 23:25:13.392908 Write leveling (Byte 1): 28 => 28
5092 23:25:13.396181 DramcWriteLeveling(PI) end<-----
5093 23:25:13.396298
5094 23:25:13.396370 ==
5095 23:25:13.399587 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 23:25:13.403124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 23:25:13.403208 ==
5098 23:25:13.406333 [Gating] SW mode calibration
5099 23:25:13.413225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5100 23:25:13.419468 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5101 23:25:13.422954 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5102 23:25:13.426374 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 23:25:13.432733 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 23:25:13.436048 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 23:25:13.439395 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 23:25:13.446115 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 23:25:13.449420 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
5108 23:25:13.452752 0 14 28 | B1->B0 | 3232 2525 | 1 0 | (1 0) (1 0)
5109 23:25:13.459564 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5110 23:25:13.463009 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 23:25:13.466112 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 23:25:13.469475 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 23:25:13.476084 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 23:25:13.479618 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 23:25:13.482615 0 15 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
5116 23:25:13.489488 0 15 28 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (1 1)
5117 23:25:13.492953 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5118 23:25:13.496018 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 23:25:13.502611 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 23:25:13.505976 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 23:25:13.509663 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 23:25:13.515925 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 23:25:13.519437 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5124 23:25:13.522784 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5125 23:25:13.529266 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5126 23:25:13.532694 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 23:25:13.536029 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 23:25:13.542453 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 23:25:13.546057 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 23:25:13.549416 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 23:25:13.555778 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 23:25:13.559364 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 23:25:13.562389 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 23:25:13.569185 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 23:25:13.572252 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 23:25:13.575690 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 23:25:13.582209 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 23:25:13.585670 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 23:25:13.589185 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5140 23:25:13.595589 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5141 23:25:13.599017 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5142 23:25:13.602477 Total UI for P1: 0, mck2ui 16
5143 23:25:13.605540 best dqsien dly found for B0: ( 1, 2, 26)
5144 23:25:13.609078 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 23:25:13.612029 Total UI for P1: 0, mck2ui 16
5146 23:25:13.615520 best dqsien dly found for B1: ( 1, 2, 30)
5147 23:25:13.618993 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5148 23:25:13.622047 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5149 23:25:13.622156
5150 23:25:13.625578 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5151 23:25:13.629181 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5152 23:25:13.632134 [Gating] SW calibration Done
5153 23:25:13.632236 ==
5154 23:25:13.635499 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 23:25:13.642277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 23:25:13.642388 ==
5157 23:25:13.642459 RX Vref Scan: 0
5158 23:25:13.642527
5159 23:25:13.645681 RX Vref 0 -> 0, step: 1
5160 23:25:13.645777
5161 23:25:13.649046 RX Delay -80 -> 252, step: 8
5162 23:25:13.652534 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5163 23:25:13.655679 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5164 23:25:13.658900 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5165 23:25:13.662111 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5166 23:25:13.668993 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5167 23:25:13.672133 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5168 23:25:13.675465 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5169 23:25:13.679009 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5170 23:25:13.682035 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5171 23:25:13.685347 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5172 23:25:13.691883 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5173 23:25:13.695338 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5174 23:25:13.698631 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5175 23:25:13.702123 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5176 23:25:13.705229 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5177 23:25:13.712033 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5178 23:25:13.712137 ==
5179 23:25:13.715038 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 23:25:13.718506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 23:25:13.718605 ==
5182 23:25:13.718707 DQS Delay:
5183 23:25:13.722044 DQS0 = 0, DQS1 = 0
5184 23:25:13.722149 DQM Delay:
5185 23:25:13.725504 DQM0 = 103, DQM1 = 95
5186 23:25:13.725615 DQ Delay:
5187 23:25:13.728496 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5188 23:25:13.731975 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5189 23:25:13.735344 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5190 23:25:13.738417 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5191 23:25:13.738524
5192 23:25:13.738616
5193 23:25:13.738715 ==
5194 23:25:13.742077 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 23:25:13.745094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 23:25:13.745188 ==
5197 23:25:13.748624
5198 23:25:13.748713
5199 23:25:13.748798 TX Vref Scan disable
5200 23:25:13.751869 == TX Byte 0 ==
5201 23:25:13.755092 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5202 23:25:13.758522 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5203 23:25:13.761895 == TX Byte 1 ==
5204 23:25:13.765185 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5205 23:25:13.768578 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5206 23:25:13.768685 ==
5207 23:25:13.771635 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 23:25:13.778377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 23:25:13.778486 ==
5210 23:25:13.778590
5211 23:25:13.778683
5212 23:25:13.781544 TX Vref Scan disable
5213 23:25:13.781647 == TX Byte 0 ==
5214 23:25:13.788322 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5215 23:25:13.791357 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5216 23:25:13.791443 == TX Byte 1 ==
5217 23:25:13.798102 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5218 23:25:13.801476 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5219 23:25:13.801587
5220 23:25:13.801681 [DATLAT]
5221 23:25:13.804822 Freq=933, CH0 RK0
5222 23:25:13.804901
5223 23:25:13.804966 DATLAT Default: 0xd
5224 23:25:13.808223 0, 0xFFFF, sum = 0
5225 23:25:13.808350 1, 0xFFFF, sum = 0
5226 23:25:13.811593 2, 0xFFFF, sum = 0
5227 23:25:13.811671 3, 0xFFFF, sum = 0
5228 23:25:13.814736 4, 0xFFFF, sum = 0
5229 23:25:13.814816 5, 0xFFFF, sum = 0
5230 23:25:13.818226 6, 0xFFFF, sum = 0
5231 23:25:13.818305 7, 0xFFFF, sum = 0
5232 23:25:13.821237 8, 0xFFFF, sum = 0
5233 23:25:13.821313 9, 0xFFFF, sum = 0
5234 23:25:13.824820 10, 0x0, sum = 1
5235 23:25:13.824897 11, 0x0, sum = 2
5236 23:25:13.828211 12, 0x0, sum = 3
5237 23:25:13.828329 13, 0x0, sum = 4
5238 23:25:13.831596 best_step = 11
5239 23:25:13.831669
5240 23:25:13.831739 ==
5241 23:25:13.834669 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 23:25:13.838141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 23:25:13.838222 ==
5244 23:25:13.841193 RX Vref Scan: 1
5245 23:25:13.841266
5246 23:25:13.841330 RX Vref 0 -> 0, step: 1
5247 23:25:13.841389
5248 23:25:13.844681 RX Delay -45 -> 252, step: 4
5249 23:25:13.844760
5250 23:25:13.847996 Set Vref, RX VrefLevel [Byte0]: 55
5251 23:25:13.851152 [Byte1]: 48
5252 23:25:13.855156
5253 23:25:13.855256 Final RX Vref Byte 0 = 55 to rank0
5254 23:25:13.858481 Final RX Vref Byte 1 = 48 to rank0
5255 23:25:13.861934 Final RX Vref Byte 0 = 55 to rank1
5256 23:25:13.865402 Final RX Vref Byte 1 = 48 to rank1==
5257 23:25:13.868474 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 23:25:13.875419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 23:25:13.875504 ==
5260 23:25:13.875574 DQS Delay:
5261 23:25:13.875638 DQS0 = 0, DQS1 = 0
5262 23:25:13.878436 DQM Delay:
5263 23:25:13.878549 DQM0 = 104, DQM1 = 94
5264 23:25:13.881990 DQ Delay:
5265 23:25:13.885238 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5266 23:25:13.888346 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5267 23:25:13.891742 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =88
5268 23:25:13.895178 DQ12 =98, DQ13 =98, DQ14 =106, DQ15 =102
5269 23:25:13.895288
5270 23:25:13.895359
5271 23:25:13.901846 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5272 23:25:13.905099 CH0 RK0: MR19=505, MR18=3129
5273 23:25:13.911591 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5274 23:25:13.911681
5275 23:25:13.915169 ----->DramcWriteLeveling(PI) begin...
5276 23:25:13.915289 ==
5277 23:25:13.918303 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 23:25:13.921808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 23:25:13.921916 ==
5280 23:25:13.925374 Write leveling (Byte 0): 33 => 33
5281 23:25:13.928425 Write leveling (Byte 1): 28 => 28
5282 23:25:13.931947 DramcWriteLeveling(PI) end<-----
5283 23:25:13.932023
5284 23:25:13.932093 ==
5285 23:25:13.935321 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 23:25:13.938763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 23:25:13.938881 ==
5288 23:25:13.941788 [Gating] SW mode calibration
5289 23:25:13.948603 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 23:25:13.955386 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 23:25:13.958321 0 14 0 | B1->B0 | 3131 3131 | 0 0 | (0 0) (0 0)
5292 23:25:13.965033 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 23:25:13.968390 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 23:25:13.971511 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 23:25:13.978350 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 23:25:13.981844 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 23:25:13.984776 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
5298 23:25:13.991147 0 14 28 | B1->B0 | 2929 2e2e | 0 0 | (1 0) (1 0)
5299 23:25:13.994731 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5300 23:25:13.998141 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 23:25:14.004777 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 23:25:14.007903 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 23:25:14.011269 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 23:25:14.018056 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 23:25:14.021055 0 15 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5306 23:25:14.024467 0 15 28 | B1->B0 | 3d3d 3838 | 0 1 | (0 0) (0 0)
5307 23:25:14.030986 1 0 0 | B1->B0 | 4545 4242 | 0 1 | (0 0) (0 0)
5308 23:25:14.034388 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 23:25:14.037920 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 23:25:14.044308 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 23:25:14.047888 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 23:25:14.051385 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 23:25:14.057792 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 23:25:14.061116 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5315 23:25:14.064533 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 23:25:14.067677 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 23:25:14.074547 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 23:25:14.077598 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 23:25:14.081114 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 23:25:14.088036 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 23:25:14.091352 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 23:25:14.094407 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 23:25:14.101370 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 23:25:14.104424 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 23:25:14.107760 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 23:25:14.114246 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 23:25:14.117667 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 23:25:14.120948 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 23:25:14.127858 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5330 23:25:14.130812 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5331 23:25:14.134228 Total UI for P1: 0, mck2ui 16
5332 23:25:14.137626 best dqsien dly found for B0: ( 1, 2, 24)
5333 23:25:14.141068 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 23:25:14.144066 Total UI for P1: 0, mck2ui 16
5335 23:25:14.147523 best dqsien dly found for B1: ( 1, 2, 28)
5336 23:25:14.150690 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5337 23:25:14.154216 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5338 23:25:14.154330
5339 23:25:14.160698 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5340 23:25:14.164090 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5341 23:25:14.164224 [Gating] SW calibration Done
5342 23:25:14.167522 ==
5343 23:25:14.170856 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 23:25:14.174116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 23:25:14.174246 ==
5346 23:25:14.174363 RX Vref Scan: 0
5347 23:25:14.174473
5348 23:25:14.177370 RX Vref 0 -> 0, step: 1
5349 23:25:14.177494
5350 23:25:14.180571 RX Delay -80 -> 252, step: 8
5351 23:25:14.183932 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5352 23:25:14.187512 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5353 23:25:14.190523 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5354 23:25:14.197400 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5355 23:25:14.200788 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5356 23:25:14.203782 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5357 23:25:14.207153 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5358 23:25:14.210260 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5359 23:25:14.217110 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5360 23:25:14.220192 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5361 23:25:14.223589 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5362 23:25:14.227092 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5363 23:25:14.230467 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5364 23:25:14.233482 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5365 23:25:14.240277 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5366 23:25:14.243630 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5367 23:25:14.243749 ==
5368 23:25:14.247060 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 23:25:14.250480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 23:25:14.250604 ==
5371 23:25:14.250719 DQS Delay:
5372 23:25:14.253488 DQS0 = 0, DQS1 = 0
5373 23:25:14.253613 DQM Delay:
5374 23:25:14.256875 DQM0 = 105, DQM1 = 94
5375 23:25:14.256999 DQ Delay:
5376 23:25:14.260023 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5377 23:25:14.263498 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5378 23:25:14.267025 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5379 23:25:14.270030 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5380 23:25:14.270149
5381 23:25:14.270262
5382 23:25:14.270369 ==
5383 23:25:14.273551 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 23:25:14.279978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 23:25:14.280102 ==
5386 23:25:14.280216
5387 23:25:14.280344
5388 23:25:14.280454 TX Vref Scan disable
5389 23:25:14.283851 == TX Byte 0 ==
5390 23:25:14.287216 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5391 23:25:14.293773 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5392 23:25:14.293898 == TX Byte 1 ==
5393 23:25:14.297179 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5394 23:25:14.303573 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5395 23:25:14.303682 ==
5396 23:25:14.307030 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 23:25:14.310437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 23:25:14.310536 ==
5399 23:25:14.310625
5400 23:25:14.310711
5401 23:25:14.313417 TX Vref Scan disable
5402 23:25:14.313500 == TX Byte 0 ==
5403 23:25:14.320350 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5404 23:25:14.323670 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5405 23:25:14.323748 == TX Byte 1 ==
5406 23:25:14.330157 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5407 23:25:14.333478 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5408 23:25:14.333556
5409 23:25:14.333633 [DATLAT]
5410 23:25:14.337006 Freq=933, CH0 RK1
5411 23:25:14.337115
5412 23:25:14.337247 DATLAT Default: 0xb
5413 23:25:14.340341 0, 0xFFFF, sum = 0
5414 23:25:14.340422 1, 0xFFFF, sum = 0
5415 23:25:14.343860 2, 0xFFFF, sum = 0
5416 23:25:14.343941 3, 0xFFFF, sum = 0
5417 23:25:14.346788 4, 0xFFFF, sum = 0
5418 23:25:14.349992 5, 0xFFFF, sum = 0
5419 23:25:14.350112 6, 0xFFFF, sum = 0
5420 23:25:14.353384 7, 0xFFFF, sum = 0
5421 23:25:14.353488 8, 0xFFFF, sum = 0
5422 23:25:14.356728 9, 0xFFFF, sum = 0
5423 23:25:14.356816 10, 0x0, sum = 1
5424 23:25:14.360183 11, 0x0, sum = 2
5425 23:25:14.360270 12, 0x0, sum = 3
5426 23:25:14.363176 13, 0x0, sum = 4
5427 23:25:14.363263 best_step = 11
5428 23:25:14.363350
5429 23:25:14.363432 ==
5430 23:25:14.366611 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 23:25:14.370065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 23:25:14.370155 ==
5433 23:25:14.373554 RX Vref Scan: 0
5434 23:25:14.373639
5435 23:25:14.376628 RX Vref 0 -> 0, step: 1
5436 23:25:14.376714
5437 23:25:14.376820 RX Delay -45 -> 252, step: 4
5438 23:25:14.384479 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5439 23:25:14.387583 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5440 23:25:14.391055 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5441 23:25:14.394145 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5442 23:25:14.397344 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5443 23:25:14.404060 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5444 23:25:14.407671 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5445 23:25:14.410689 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5446 23:25:14.414398 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5447 23:25:14.417494 iDelay=199, Bit 9, Center 84 (3 ~ 166) 164
5448 23:25:14.420860 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5449 23:25:14.427474 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5450 23:25:14.430853 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5451 23:25:14.434130 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5452 23:25:14.437666 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5453 23:25:14.443895 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5454 23:25:14.444007 ==
5455 23:25:14.447280 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 23:25:14.450675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 23:25:14.450787 ==
5458 23:25:14.450891 DQS Delay:
5459 23:25:14.454072 DQS0 = 0, DQS1 = 0
5460 23:25:14.454157 DQM Delay:
5461 23:25:14.457447 DQM0 = 104, DQM1 = 95
5462 23:25:14.457533 DQ Delay:
5463 23:25:14.460886 DQ0 =100, DQ1 =106, DQ2 =102, DQ3 =102
5464 23:25:14.464214 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =112
5465 23:25:14.467349 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =90
5466 23:25:14.470759 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =104
5467 23:25:14.470845
5468 23:25:14.470932
5469 23:25:14.480758 [DQSOSCAuto] RK1, (LSB)MR18= 0x2902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5470 23:25:14.480848 CH0 RK1: MR19=505, MR18=2902
5471 23:25:14.487260 CH0_RK1: MR19=0x505, MR18=0x2902, DQSOSC=408, MR23=63, INC=65, DEC=43
5472 23:25:14.490616 [RxdqsGatingPostProcess] freq 933
5473 23:25:14.497118 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5474 23:25:14.500560 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 23:25:14.503969 best DQS1 dly(2T, 0.5T) = (0, 10)
5476 23:25:14.507051 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 23:25:14.510587 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5478 23:25:14.513770 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 23:25:14.513849 best DQS1 dly(2T, 0.5T) = (0, 10)
5480 23:25:14.517396 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 23:25:14.520620 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5482 23:25:14.524108 Pre-setting of DQS Precalculation
5483 23:25:14.530620 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5484 23:25:14.530752 ==
5485 23:25:14.534019 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 23:25:14.536947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 23:25:14.537071 ==
5488 23:25:14.543916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5489 23:25:14.550453 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5490 23:25:14.553832 [CA 0] Center 36 (6~67) winsize 62
5491 23:25:14.557136 [CA 1] Center 37 (6~68) winsize 63
5492 23:25:14.560381 [CA 2] Center 35 (5~65) winsize 61
5493 23:25:14.563780 [CA 3] Center 34 (4~65) winsize 62
5494 23:25:14.566963 [CA 4] Center 34 (4~65) winsize 62
5495 23:25:14.570244 [CA 5] Center 33 (3~64) winsize 62
5496 23:25:14.570352
5497 23:25:14.573690 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5498 23:25:14.573809
5499 23:25:14.576797 [CATrainingPosCal] consider 1 rank data
5500 23:25:14.580462 u2DelayCellTimex100 = 270/100 ps
5501 23:25:14.583500 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 23:25:14.586914 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5503 23:25:14.590474 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5504 23:25:14.593633 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5505 23:25:14.597166 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5506 23:25:14.600320 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5507 23:25:14.600401
5508 23:25:14.606894 CA PerBit enable=1, Macro0, CA PI delay=33
5509 23:25:14.606988
5510 23:25:14.607058 [CBTSetCACLKResult] CA Dly = 33
5511 23:25:14.610225 CS Dly: 7 (0~38)
5512 23:25:14.610341 ==
5513 23:25:14.613672 Dram Type= 6, Freq= 0, CH_1, rank 1
5514 23:25:14.617088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 23:25:14.617180 ==
5516 23:25:14.623487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 23:25:14.630295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5518 23:25:14.633481 [CA 0] Center 36 (6~67) winsize 62
5519 23:25:14.636952 [CA 1] Center 37 (7~68) winsize 62
5520 23:25:14.640063 [CA 2] Center 34 (4~65) winsize 62
5521 23:25:14.643507 [CA 3] Center 34 (4~65) winsize 62
5522 23:25:14.646857 [CA 4] Center 34 (4~65) winsize 62
5523 23:25:14.650329 [CA 5] Center 33 (3~64) winsize 62
5524 23:25:14.650459
5525 23:25:14.653667 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5526 23:25:14.653800
5527 23:25:14.657094 [CATrainingPosCal] consider 2 rank data
5528 23:25:14.660496 u2DelayCellTimex100 = 270/100 ps
5529 23:25:14.663412 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 23:25:14.667011 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5531 23:25:14.670451 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5532 23:25:14.673396 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5533 23:25:14.676558 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5534 23:25:14.680047 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5535 23:25:14.680156
5536 23:25:14.686874 CA PerBit enable=1, Macro0, CA PI delay=33
5537 23:25:14.686979
5538 23:25:14.690151 [CBTSetCACLKResult] CA Dly = 33
5539 23:25:14.690260 CS Dly: 8 (0~40)
5540 23:25:14.690357
5541 23:25:14.693433 ----->DramcWriteLeveling(PI) begin...
5542 23:25:14.693563 ==
5543 23:25:14.696603 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 23:25:14.700127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 23:25:14.700252 ==
5546 23:25:14.703285 Write leveling (Byte 0): 28 => 28
5547 23:25:14.706568 Write leveling (Byte 1): 29 => 29
5548 23:25:14.709860 DramcWriteLeveling(PI) end<-----
5549 23:25:14.709984
5550 23:25:14.710099 ==
5551 23:25:14.713230 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 23:25:14.719663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 23:25:14.719777 ==
5554 23:25:14.719876 [Gating] SW mode calibration
5555 23:25:14.729605 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5556 23:25:14.732961 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5557 23:25:14.736337 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 23:25:14.743128 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 23:25:14.746613 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 23:25:14.749609 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 23:25:14.756418 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 23:25:14.759799 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 23:25:14.763138 0 14 24 | B1->B0 | 3333 2d2d | 1 1 | (1 0) (0 1)
5564 23:25:14.769634 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
5565 23:25:14.773044 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 23:25:14.776502 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 23:25:14.782942 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 23:25:14.786365 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 23:25:14.789675 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 23:25:14.796281 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 23:25:14.799575 0 15 24 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
5572 23:25:14.802656 0 15 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5573 23:25:14.809312 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 23:25:14.812827 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 23:25:14.816019 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 23:25:14.822587 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 23:25:14.825939 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 23:25:14.829479 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 23:25:14.835868 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5580 23:25:14.839377 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 23:25:14.842563 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 23:25:14.849191 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 23:25:14.852528 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 23:25:14.855923 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 23:25:14.862269 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 23:25:14.865768 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 23:25:14.869232 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 23:25:14.875495 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 23:25:14.879080 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 23:25:14.882069 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 23:25:14.889021 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 23:25:14.891999 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 23:25:14.895384 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 23:25:14.902283 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 23:25:14.905315 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5596 23:25:14.908725 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 23:25:14.912055 Total UI for P1: 0, mck2ui 16
5598 23:25:14.915129 best dqsien dly found for B0: ( 1, 2, 24)
5599 23:25:14.918648 Total UI for P1: 0, mck2ui 16
5600 23:25:14.921990 best dqsien dly found for B1: ( 1, 2, 24)
5601 23:25:14.925058 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5602 23:25:14.928537 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5603 23:25:14.928672
5604 23:25:14.932054 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5605 23:25:14.938373 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5606 23:25:14.938508 [Gating] SW calibration Done
5607 23:25:14.938628 ==
5608 23:25:14.941975 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 23:25:14.948353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 23:25:14.948487 ==
5611 23:25:14.948615 RX Vref Scan: 0
5612 23:25:14.948729
5613 23:25:14.951975 RX Vref 0 -> 0, step: 1
5614 23:25:14.952113
5615 23:25:14.955076 RX Delay -80 -> 252, step: 8
5616 23:25:14.958442 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5617 23:25:14.961600 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5618 23:25:14.965024 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5619 23:25:14.968271 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5620 23:25:14.975084 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5621 23:25:14.978454 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5622 23:25:14.981560 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5623 23:25:14.985126 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5624 23:25:14.988435 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5625 23:25:14.991568 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5626 23:25:14.998405 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5627 23:25:15.001347 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5628 23:25:15.004818 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5629 23:25:15.008204 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5630 23:25:15.011653 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5631 23:25:15.018059 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5632 23:25:15.018187 ==
5633 23:25:15.021562 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 23:25:15.024625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 23:25:15.024708 ==
5636 23:25:15.024801 DQS Delay:
5637 23:25:15.027909 DQS0 = 0, DQS1 = 0
5638 23:25:15.028023 DQM Delay:
5639 23:25:15.031382 DQM0 = 103, DQM1 = 98
5640 23:25:15.031455 DQ Delay:
5641 23:25:15.034433 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5642 23:25:15.038083 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5643 23:25:15.041476 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5644 23:25:15.044954 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =103
5645 23:25:15.045029
5646 23:25:15.045092
5647 23:25:15.045159 ==
5648 23:25:15.047971 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 23:25:15.054838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 23:25:15.054951 ==
5651 23:25:15.055052
5652 23:25:15.055132
5653 23:25:15.055198 TX Vref Scan disable
5654 23:25:15.058165 == TX Byte 0 ==
5655 23:25:15.061650 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5656 23:25:15.064697 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5657 23:25:15.068048 == TX Byte 1 ==
5658 23:25:15.071244 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5659 23:25:15.077880 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5660 23:25:15.077968 ==
5661 23:25:15.081410 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 23:25:15.084781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 23:25:15.084864 ==
5664 23:25:15.084934
5665 23:25:15.085004
5666 23:25:15.088514 TX Vref Scan disable
5667 23:25:15.088589 == TX Byte 0 ==
5668 23:25:15.094584 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5669 23:25:15.097994 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5670 23:25:15.098101 == TX Byte 1 ==
5671 23:25:15.104746 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5672 23:25:15.108101 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5673 23:25:15.108177
5674 23:25:15.108240 [DATLAT]
5675 23:25:15.111514 Freq=933, CH1 RK0
5676 23:25:15.111637
5677 23:25:15.111721 DATLAT Default: 0xd
5678 23:25:15.114628 0, 0xFFFF, sum = 0
5679 23:25:15.114703 1, 0xFFFF, sum = 0
5680 23:25:15.118039 2, 0xFFFF, sum = 0
5681 23:25:15.118147 3, 0xFFFF, sum = 0
5682 23:25:15.121456 4, 0xFFFF, sum = 0
5683 23:25:15.121541 5, 0xFFFF, sum = 0
5684 23:25:15.124610 6, 0xFFFF, sum = 0
5685 23:25:15.124681 7, 0xFFFF, sum = 0
5686 23:25:15.128186 8, 0xFFFF, sum = 0
5687 23:25:15.131196 9, 0xFFFF, sum = 0
5688 23:25:15.131272 10, 0x0, sum = 1
5689 23:25:15.131342 11, 0x0, sum = 2
5690 23:25:15.134730 12, 0x0, sum = 3
5691 23:25:15.134805 13, 0x0, sum = 4
5692 23:25:15.137697 best_step = 11
5693 23:25:15.137768
5694 23:25:15.137833 ==
5695 23:25:15.141005 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 23:25:15.144587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 23:25:15.144663 ==
5698 23:25:15.147856 RX Vref Scan: 1
5699 23:25:15.147955
5700 23:25:15.148048 RX Vref 0 -> 0, step: 1
5701 23:25:15.148142
5702 23:25:15.151150 RX Delay -45 -> 252, step: 4
5703 23:25:15.151223
5704 23:25:15.154408 Set Vref, RX VrefLevel [Byte0]: 54
5705 23:25:15.157860 [Byte1]: 53
5706 23:25:15.161907
5707 23:25:15.161985 Final RX Vref Byte 0 = 54 to rank0
5708 23:25:15.165211 Final RX Vref Byte 1 = 53 to rank0
5709 23:25:15.168689 Final RX Vref Byte 0 = 54 to rank1
5710 23:25:15.171754 Final RX Vref Byte 1 = 53 to rank1==
5711 23:25:15.175142 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 23:25:15.181629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 23:25:15.181721 ==
5714 23:25:15.181787 DQS Delay:
5715 23:25:15.181849 DQS0 = 0, DQS1 = 0
5716 23:25:15.185076 DQM Delay:
5717 23:25:15.185155 DQM0 = 103, DQM1 = 100
5718 23:25:15.188435 DQ Delay:
5719 23:25:15.191818 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5720 23:25:15.194925 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5721 23:25:15.198353 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5722 23:25:15.201572 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =108
5723 23:25:15.201693
5724 23:25:15.201784
5725 23:25:15.208302 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5726 23:25:15.211601 CH1 RK0: MR19=505, MR18=1A32
5727 23:25:15.218249 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5728 23:25:15.218359
5729 23:25:15.221372 ----->DramcWriteLeveling(PI) begin...
5730 23:25:15.221451 ==
5731 23:25:15.224831 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 23:25:15.228004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 23:25:15.231416 ==
5734 23:25:15.231542 Write leveling (Byte 0): 28 => 28
5735 23:25:15.234824 Write leveling (Byte 1): 30 => 30
5736 23:25:15.238012 DramcWriteLeveling(PI) end<-----
5737 23:25:15.238136
5738 23:25:15.238256 ==
5739 23:25:15.241562 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 23:25:15.248175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 23:25:15.248314 ==
5742 23:25:15.251182 [Gating] SW mode calibration
5743 23:25:15.257907 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5744 23:25:15.261479 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5745 23:25:15.267779 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 23:25:15.271236 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 23:25:15.274557 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 23:25:15.281231 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 23:25:15.284731 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 23:25:15.287777 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 23:25:15.291154 0 14 24 | B1->B0 | 2f2f 3030 | 0 1 | (0 0) (1 0)
5752 23:25:15.297601 0 14 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5753 23:25:15.300946 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 23:25:15.304355 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 23:25:15.311408 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 23:25:15.314410 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 23:25:15.317986 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 23:25:15.324632 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 23:25:15.327625 0 15 24 | B1->B0 | 3535 2525 | 0 0 | (0 0) (0 0)
5760 23:25:15.330912 0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5761 23:25:15.337982 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 23:25:15.341028 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 23:25:15.344630 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 23:25:15.350979 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 23:25:15.354398 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 23:25:15.357689 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 23:25:15.364142 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5768 23:25:15.367709 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5769 23:25:15.370985 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 23:25:15.377360 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 23:25:15.380861 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 23:25:15.384334 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 23:25:15.390720 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 23:25:15.394245 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 23:25:15.397293 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 23:25:15.404006 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 23:25:15.407333 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 23:25:15.410379 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 23:25:15.417323 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 23:25:15.420322 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 23:25:15.423880 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 23:25:15.430177 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 23:25:15.433577 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5784 23:25:15.437002 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 23:25:15.440565 Total UI for P1: 0, mck2ui 16
5786 23:25:15.443558 best dqsien dly found for B0: ( 1, 2, 24)
5787 23:25:15.446962 Total UI for P1: 0, mck2ui 16
5788 23:25:15.450355 best dqsien dly found for B1: ( 1, 2, 24)
5789 23:25:15.453344 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5790 23:25:15.456980 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5791 23:25:15.457089
5792 23:25:15.459975 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5793 23:25:15.466679 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5794 23:25:15.466787 [Gating] SW calibration Done
5795 23:25:15.469938 ==
5796 23:25:15.470069 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 23:25:15.476669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 23:25:15.476802 ==
5799 23:25:15.476920 RX Vref Scan: 0
5800 23:25:15.477035
5801 23:25:15.479968 RX Vref 0 -> 0, step: 1
5802 23:25:15.480078
5803 23:25:15.483209 RX Delay -80 -> 252, step: 8
5804 23:25:15.486559 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5805 23:25:15.489940 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5806 23:25:15.493115 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5807 23:25:15.499643 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5808 23:25:15.503013 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5809 23:25:15.506384 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5810 23:25:15.509434 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5811 23:25:15.512939 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5812 23:25:15.516153 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5813 23:25:15.522942 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5814 23:25:15.526397 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5815 23:25:15.529501 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5816 23:25:15.532856 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5817 23:25:15.536322 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5818 23:25:15.542834 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5819 23:25:15.545943 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5820 23:25:15.546025 ==
5821 23:25:15.549425 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 23:25:15.552858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 23:25:15.552960 ==
5824 23:25:15.553055 DQS Delay:
5825 23:25:15.555863 DQS0 = 0, DQS1 = 0
5826 23:25:15.555939 DQM Delay:
5827 23:25:15.559273 DQM0 = 103, DQM1 = 99
5828 23:25:15.559383 DQ Delay:
5829 23:25:15.562786 DQ0 =111, DQ1 =99, DQ2 =95, DQ3 =99
5830 23:25:15.566219 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5831 23:25:15.569311 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5832 23:25:15.572756 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5833 23:25:15.572845
5834 23:25:15.572909
5835 23:25:15.575814 ==
5836 23:25:15.575922 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 23:25:15.582607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 23:25:15.582715 ==
5839 23:25:15.582817
5840 23:25:15.582910
5841 23:25:15.585661 TX Vref Scan disable
5842 23:25:15.585760 == TX Byte 0 ==
5843 23:25:15.589065 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5844 23:25:15.595380 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5845 23:25:15.595456 == TX Byte 1 ==
5846 23:25:15.598701 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5847 23:25:15.605341 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5848 23:25:15.605445 ==
5849 23:25:15.608913 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 23:25:15.611935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 23:25:15.612039 ==
5852 23:25:15.612144
5853 23:25:15.612234
5854 23:25:15.615589 TX Vref Scan disable
5855 23:25:15.618682 == TX Byte 0 ==
5856 23:25:15.622069 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5857 23:25:15.625311 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5858 23:25:15.628789 == TX Byte 1 ==
5859 23:25:15.631901 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5860 23:25:15.635092 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5861 23:25:15.635205
5862 23:25:15.638538 [DATLAT]
5863 23:25:15.638648 Freq=933, CH1 RK1
5864 23:25:15.638750
5865 23:25:15.641988 DATLAT Default: 0xb
5866 23:25:15.642097 0, 0xFFFF, sum = 0
5867 23:25:15.645265 1, 0xFFFF, sum = 0
5868 23:25:15.645375 2, 0xFFFF, sum = 0
5869 23:25:15.648482 3, 0xFFFF, sum = 0
5870 23:25:15.648592 4, 0xFFFF, sum = 0
5871 23:25:15.652151 5, 0xFFFF, sum = 0
5872 23:25:15.652271 6, 0xFFFF, sum = 0
5873 23:25:15.655285 7, 0xFFFF, sum = 0
5874 23:25:15.655392 8, 0xFFFF, sum = 0
5875 23:25:15.658758 9, 0xFFFF, sum = 0
5876 23:25:15.658871 10, 0x0, sum = 1
5877 23:25:15.661780 11, 0x0, sum = 2
5878 23:25:15.661866 12, 0x0, sum = 3
5879 23:25:15.665257 13, 0x0, sum = 4
5880 23:25:15.665365 best_step = 11
5881 23:25:15.665459
5882 23:25:15.665547 ==
5883 23:25:15.668598 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 23:25:15.671737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 23:25:15.675209 ==
5886 23:25:15.675321 RX Vref Scan: 0
5887 23:25:15.675413
5888 23:25:15.678625 RX Vref 0 -> 0, step: 1
5889 23:25:15.678730
5890 23:25:15.681740 RX Delay -45 -> 252, step: 4
5891 23:25:15.685245 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5892 23:25:15.688314 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5893 23:25:15.695149 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5894 23:25:15.698407 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5895 23:25:15.701921 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5896 23:25:15.705152 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5897 23:25:15.708502 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5898 23:25:15.711575 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5899 23:25:15.718501 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5900 23:25:15.721501 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5901 23:25:15.724925 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5902 23:25:15.728378 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5903 23:25:15.731702 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5904 23:25:15.738457 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5905 23:25:15.741754 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5906 23:25:15.745009 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5907 23:25:15.745099 ==
5908 23:25:15.748283 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 23:25:15.751694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 23:25:15.755070 ==
5911 23:25:15.755175 DQS Delay:
5912 23:25:15.755267 DQS0 = 0, DQS1 = 0
5913 23:25:15.758252 DQM Delay:
5914 23:25:15.758356 DQM0 = 105, DQM1 = 101
5915 23:25:15.761507 DQ Delay:
5916 23:25:15.765037 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5917 23:25:15.768221 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5918 23:25:15.771581 DQ8 =92, DQ9 =88, DQ10 =102, DQ11 =94
5919 23:25:15.774949 DQ12 =108, DQ13 =108, DQ14 =106, DQ15 =110
5920 23:25:15.775049
5921 23:25:15.775143
5922 23:25:15.781360 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5923 23:25:15.785079 CH1 RK1: MR19=505, MR18=2F03
5924 23:25:15.791472 CH1_RK1: MR19=0x505, MR18=0x2F03, DQSOSC=407, MR23=63, INC=65, DEC=43
5925 23:25:15.795041 [RxdqsGatingPostProcess] freq 933
5926 23:25:15.801490 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5927 23:25:15.801604 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 23:25:15.804983 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 23:25:15.808117 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 23:25:15.811418 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 23:25:15.814722 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 23:25:15.818198 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 23:25:15.821315 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 23:25:15.824622 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 23:25:15.828060 Pre-setting of DQS Precalculation
5936 23:25:15.831092 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5937 23:25:15.841083 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5938 23:25:15.847879 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5939 23:25:15.848002
5940 23:25:15.848113
5941 23:25:15.851144 [Calibration Summary] 1866 Mbps
5942 23:25:15.851248 CH 0, Rank 0
5943 23:25:15.854464 SW Impedance : PASS
5944 23:25:15.854571 DUTY Scan : NO K
5945 23:25:15.857930 ZQ Calibration : PASS
5946 23:25:15.861285 Jitter Meter : NO K
5947 23:25:15.861385 CBT Training : PASS
5948 23:25:15.864458 Write leveling : PASS
5949 23:25:15.867730 RX DQS gating : PASS
5950 23:25:15.867830 RX DQ/DQS(RDDQC) : PASS
5951 23:25:15.871152 TX DQ/DQS : PASS
5952 23:25:15.874353 RX DATLAT : PASS
5953 23:25:15.874486 RX DQ/DQS(Engine): PASS
5954 23:25:15.877724 TX OE : NO K
5955 23:25:15.877850 All Pass.
5956 23:25:15.877965
5957 23:25:15.880997 CH 0, Rank 1
5958 23:25:15.881123 SW Impedance : PASS
5959 23:25:15.884598 DUTY Scan : NO K
5960 23:25:15.888009 ZQ Calibration : PASS
5961 23:25:15.888110 Jitter Meter : NO K
5962 23:25:15.891278 CBT Training : PASS
5963 23:25:15.894347 Write leveling : PASS
5964 23:25:15.894450 RX DQS gating : PASS
5965 23:25:15.897729 RX DQ/DQS(RDDQC) : PASS
5966 23:25:15.897831 TX DQ/DQS : PASS
5967 23:25:15.900999 RX DATLAT : PASS
5968 23:25:15.904196 RX DQ/DQS(Engine): PASS
5969 23:25:15.904325 TX OE : NO K
5970 23:25:15.907532 All Pass.
5971 23:25:15.907639
5972 23:25:15.907734 CH 1, Rank 0
5973 23:25:15.910683 SW Impedance : PASS
5974 23:25:15.910788 DUTY Scan : NO K
5975 23:25:15.914071 ZQ Calibration : PASS
5976 23:25:15.917345 Jitter Meter : NO K
5977 23:25:15.917428 CBT Training : PASS
5978 23:25:15.920728 Write leveling : PASS
5979 23:25:15.924228 RX DQS gating : PASS
5980 23:25:15.924329 RX DQ/DQS(RDDQC) : PASS
5981 23:25:15.927209 TX DQ/DQS : PASS
5982 23:25:15.930688 RX DATLAT : PASS
5983 23:25:15.930773 RX DQ/DQS(Engine): PASS
5984 23:25:15.933903 TX OE : NO K
5985 23:25:15.933981 All Pass.
5986 23:25:15.934045
5987 23:25:15.937188 CH 1, Rank 1
5988 23:25:15.937261 SW Impedance : PASS
5989 23:25:15.940691 DUTY Scan : NO K
5990 23:25:15.943783 ZQ Calibration : PASS
5991 23:25:15.943891 Jitter Meter : NO K
5992 23:25:15.947429 CBT Training : PASS
5993 23:25:15.950421 Write leveling : PASS
5994 23:25:15.950524 RX DQS gating : PASS
5995 23:25:15.953913 RX DQ/DQS(RDDQC) : PASS
5996 23:25:15.957223 TX DQ/DQS : PASS
5997 23:25:15.957301 RX DATLAT : PASS
5998 23:25:15.960680 RX DQ/DQS(Engine): PASS
5999 23:25:15.963655 TX OE : NO K
6000 23:25:15.963731 All Pass.
6001 23:25:15.963794
6002 23:25:15.963859 DramC Write-DBI off
6003 23:25:15.966971 PER_BANK_REFRESH: Hybrid Mode
6004 23:25:15.970524 TX_TRACKING: ON
6005 23:25:15.976854 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6006 23:25:15.980115 [FAST_K] Save calibration result to emmc
6007 23:25:15.987112 dramc_set_vcore_voltage set vcore to 650000
6008 23:25:15.987230 Read voltage for 400, 6
6009 23:25:15.990121 Vio18 = 0
6010 23:25:15.990199 Vcore = 650000
6011 23:25:15.990273 Vdram = 0
6012 23:25:15.990335 Vddq = 0
6013 23:25:15.993549 Vmddr = 0
6014 23:25:15.996909 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6015 23:25:16.003411 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6016 23:25:16.006811 MEM_TYPE=3, freq_sel=20
6017 23:25:16.006923 sv_algorithm_assistance_LP4_800
6018 23:25:16.013530 ============ PULL DRAM RESETB DOWN ============
6019 23:25:16.016685 ========== PULL DRAM RESETB DOWN end =========
6020 23:25:16.020057 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6021 23:25:16.023315 ===================================
6022 23:25:16.026815 LPDDR4 DRAM CONFIGURATION
6023 23:25:16.030058 ===================================
6024 23:25:16.033109 EX_ROW_EN[0] = 0x0
6025 23:25:16.033215 EX_ROW_EN[1] = 0x0
6026 23:25:16.036607 LP4Y_EN = 0x0
6027 23:25:16.036684 WORK_FSP = 0x0
6028 23:25:16.039941 WL = 0x2
6029 23:25:16.040049 RL = 0x2
6030 23:25:16.043231 BL = 0x2
6031 23:25:16.043310 RPST = 0x0
6032 23:25:16.046231 RD_PRE = 0x0
6033 23:25:16.046332 WR_PRE = 0x1
6034 23:25:16.049627 WR_PST = 0x0
6035 23:25:16.053059 DBI_WR = 0x0
6036 23:25:16.053138 DBI_RD = 0x0
6037 23:25:16.056172 OTF = 0x1
6038 23:25:16.059514 ===================================
6039 23:25:16.062984 ===================================
6040 23:25:16.063096 ANA top config
6041 23:25:16.066433 ===================================
6042 23:25:16.069531 DLL_ASYNC_EN = 0
6043 23:25:16.072914 ALL_SLAVE_EN = 1
6044 23:25:16.072998 NEW_RANK_MODE = 1
6045 23:25:16.076241 DLL_IDLE_MODE = 1
6046 23:25:16.079566 LP45_APHY_COMB_EN = 1
6047 23:25:16.082847 TX_ODT_DIS = 1
6048 23:25:16.082952 NEW_8X_MODE = 1
6049 23:25:16.086175 ===================================
6050 23:25:16.089527 ===================================
6051 23:25:16.092585 data_rate = 800
6052 23:25:16.095993 CKR = 1
6053 23:25:16.099379 DQ_P2S_RATIO = 4
6054 23:25:16.102417 ===================================
6055 23:25:16.105777 CA_P2S_RATIO = 4
6056 23:25:16.109013 DQ_CA_OPEN = 0
6057 23:25:16.112392 DQ_SEMI_OPEN = 1
6058 23:25:16.112492 CA_SEMI_OPEN = 1
6059 23:25:16.115791 CA_FULL_RATE = 0
6060 23:25:16.119211 DQ_CKDIV4_EN = 0
6061 23:25:16.122218 CA_CKDIV4_EN = 1
6062 23:25:16.125631 CA_PREDIV_EN = 0
6063 23:25:16.125709 PH8_DLY = 0
6064 23:25:16.129047 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6065 23:25:16.132233 DQ_AAMCK_DIV = 0
6066 23:25:16.135778 CA_AAMCK_DIV = 0
6067 23:25:16.139116 CA_ADMCK_DIV = 4
6068 23:25:16.142451 DQ_TRACK_CA_EN = 0
6069 23:25:16.145700 CA_PICK = 800
6070 23:25:16.145784 CA_MCKIO = 400
6071 23:25:16.148693 MCKIO_SEMI = 400
6072 23:25:16.152164 PLL_FREQ = 3016
6073 23:25:16.155642 DQ_UI_PI_RATIO = 32
6074 23:25:16.159018 CA_UI_PI_RATIO = 32
6075 23:25:16.162420 ===================================
6076 23:25:16.165340 ===================================
6077 23:25:16.168854 memory_type:LPDDR4
6078 23:25:16.168938 GP_NUM : 10
6079 23:25:16.172193 SRAM_EN : 1
6080 23:25:16.172276 MD32_EN : 0
6081 23:25:16.175699 ===================================
6082 23:25:16.179080 [ANA_INIT] >>>>>>>>>>>>>>
6083 23:25:16.181943 <<<<<< [CONFIGURE PHASE]: ANA_TX
6084 23:25:16.185673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6085 23:25:16.189111 ===================================
6086 23:25:16.192071 data_rate = 800,PCW = 0X7400
6087 23:25:16.195445 ===================================
6088 23:25:16.198788 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6089 23:25:16.205315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 23:25:16.215356 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 23:25:16.218630 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6092 23:25:16.222139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6093 23:25:16.225476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6094 23:25:16.228524 [ANA_INIT] flow start
6095 23:25:16.231947 [ANA_INIT] PLL >>>>>>>>
6096 23:25:16.232060 [ANA_INIT] PLL <<<<<<<<
6097 23:25:16.235501 [ANA_INIT] MIDPI >>>>>>>>
6098 23:25:16.238759 [ANA_INIT] MIDPI <<<<<<<<
6099 23:25:16.241946 [ANA_INIT] DLL >>>>>>>>
6100 23:25:16.242051 [ANA_INIT] flow end
6101 23:25:16.245217 ============ LP4 DIFF to SE enter ============
6102 23:25:16.251950 ============ LP4 DIFF to SE exit ============
6103 23:25:16.252059 [ANA_INIT] <<<<<<<<<<<<<
6104 23:25:16.255264 [Flow] Enable top DCM control >>>>>
6105 23:25:16.258277 [Flow] Enable top DCM control <<<<<
6106 23:25:16.261737 Enable DLL master slave shuffle
6107 23:25:16.268505 ==============================================================
6108 23:25:16.268635 Gating Mode config
6109 23:25:16.275205 ==============================================================
6110 23:25:16.278626 Config description:
6111 23:25:16.285352 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6112 23:25:16.294871 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6113 23:25:16.298193 SELPH_MODE 0: By rank 1: By Phase
6114 23:25:16.304672 ==============================================================
6115 23:25:16.308074 GAT_TRACK_EN = 0
6116 23:25:16.308187 RX_GATING_MODE = 2
6117 23:25:16.311421 RX_GATING_TRACK_MODE = 2
6118 23:25:16.314971 SELPH_MODE = 1
6119 23:25:16.317946 PICG_EARLY_EN = 1
6120 23:25:16.321156 VALID_LAT_VALUE = 1
6121 23:25:16.328108 ==============================================================
6122 23:25:16.331216 Enter into Gating configuration >>>>
6123 23:25:16.334634 Exit from Gating configuration <<<<
6124 23:25:16.338129 Enter into DVFS_PRE_config >>>>>
6125 23:25:16.347954 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6126 23:25:16.351223 Exit from DVFS_PRE_config <<<<<
6127 23:25:16.354419 Enter into PICG configuration >>>>
6128 23:25:16.357889 Exit from PICG configuration <<<<
6129 23:25:16.361202 [RX_INPUT] configuration >>>>>
6130 23:25:16.364584 [RX_INPUT] configuration <<<<<
6131 23:25:16.368099 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6132 23:25:16.374563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6133 23:25:16.381389 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 23:25:16.384328 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 23:25:16.391135 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 23:25:16.397958 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 23:25:16.401158 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6138 23:25:16.407879 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6139 23:25:16.410831 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6140 23:25:16.414292 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6141 23:25:16.417703 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6142 23:25:16.424300 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6143 23:25:16.427989 ===================================
6144 23:25:16.428084 LPDDR4 DRAM CONFIGURATION
6145 23:25:16.431336 ===================================
6146 23:25:16.434351 EX_ROW_EN[0] = 0x0
6147 23:25:16.437877 EX_ROW_EN[1] = 0x0
6148 23:25:16.438004 LP4Y_EN = 0x0
6149 23:25:16.440859 WORK_FSP = 0x0
6150 23:25:16.440945 WL = 0x2
6151 23:25:16.444392 RL = 0x2
6152 23:25:16.444477 BL = 0x2
6153 23:25:16.447720 RPST = 0x0
6154 23:25:16.447835 RD_PRE = 0x0
6155 23:25:16.451245 WR_PRE = 0x1
6156 23:25:16.451385 WR_PST = 0x0
6157 23:25:16.454212 DBI_WR = 0x0
6158 23:25:16.454345 DBI_RD = 0x0
6159 23:25:16.457684 OTF = 0x1
6160 23:25:16.461079 ===================================
6161 23:25:16.464369 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6162 23:25:16.467523 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6163 23:25:16.474127 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 23:25:16.477443 ===================================
6165 23:25:16.477571 LPDDR4 DRAM CONFIGURATION
6166 23:25:16.480890 ===================================
6167 23:25:16.484318 EX_ROW_EN[0] = 0x10
6168 23:25:16.484405 EX_ROW_EN[1] = 0x0
6169 23:25:16.487371 LP4Y_EN = 0x0
6170 23:25:16.490780 WORK_FSP = 0x0
6171 23:25:16.490867 WL = 0x2
6172 23:25:16.494109 RL = 0x2
6173 23:25:16.494192 BL = 0x2
6174 23:25:16.497387 RPST = 0x0
6175 23:25:16.497470 RD_PRE = 0x0
6176 23:25:16.501075 WR_PRE = 0x1
6177 23:25:16.501158 WR_PST = 0x0
6178 23:25:16.504120 DBI_WR = 0x0
6179 23:25:16.504252 DBI_RD = 0x0
6180 23:25:16.507540 OTF = 0x1
6181 23:25:16.510805 ===================================
6182 23:25:16.517286 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6183 23:25:16.520692 nWR fixed to 30
6184 23:25:16.520779 [ModeRegInit_LP4] CH0 RK0
6185 23:25:16.523948 [ModeRegInit_LP4] CH0 RK1
6186 23:25:16.527177 [ModeRegInit_LP4] CH1 RK0
6187 23:25:16.527273 [ModeRegInit_LP4] CH1 RK1
6188 23:25:16.530593 match AC timing 19
6189 23:25:16.533735 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6190 23:25:16.540612 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6191 23:25:16.544067 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6192 23:25:16.547012 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6193 23:25:16.553943 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6194 23:25:16.554030 ==
6195 23:25:16.557026 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 23:25:16.560514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6197 23:25:16.560651 ==
6198 23:25:16.567092 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6199 23:25:16.570571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6200 23:25:16.573862 [CA 0] Center 36 (8~64) winsize 57
6201 23:25:16.576996 [CA 1] Center 36 (8~64) winsize 57
6202 23:25:16.580185 [CA 2] Center 36 (8~64) winsize 57
6203 23:25:16.583783 [CA 3] Center 36 (8~64) winsize 57
6204 23:25:16.587143 [CA 4] Center 36 (8~64) winsize 57
6205 23:25:16.590127 [CA 5] Center 36 (8~64) winsize 57
6206 23:25:16.590252
6207 23:25:16.593551 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6208 23:25:16.593694
6209 23:25:16.597085 [CATrainingPosCal] consider 1 rank data
6210 23:25:16.600075 u2DelayCellTimex100 = 270/100 ps
6211 23:25:16.603646 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 23:25:16.606609 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 23:25:16.613663 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 23:25:16.616747 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 23:25:16.620196 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 23:25:16.623533 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 23:25:16.623616
6218 23:25:16.627157 CA PerBit enable=1, Macro0, CA PI delay=36
6219 23:25:16.627266
6220 23:25:16.630130 [CBTSetCACLKResult] CA Dly = 36
6221 23:25:16.630221 CS Dly: 1 (0~32)
6222 23:25:16.630295 ==
6223 23:25:16.633482 Dram Type= 6, Freq= 0, CH_0, rank 1
6224 23:25:16.640011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 23:25:16.640096 ==
6226 23:25:16.643322 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 23:25:16.650034 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6228 23:25:16.653378 [CA 0] Center 36 (8~64) winsize 57
6229 23:25:16.656657 [CA 1] Center 36 (8~64) winsize 57
6230 23:25:16.660031 [CA 2] Center 36 (8~64) winsize 57
6231 23:25:16.663135 [CA 3] Center 36 (8~64) winsize 57
6232 23:25:16.666448 [CA 4] Center 36 (8~64) winsize 57
6233 23:25:16.669876 [CA 5] Center 36 (8~64) winsize 57
6234 23:25:16.669959
6235 23:25:16.673381 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6236 23:25:16.673458
6237 23:25:16.676671 [CATrainingPosCal] consider 2 rank data
6238 23:25:16.679674 u2DelayCellTimex100 = 270/100 ps
6239 23:25:16.683112 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 23:25:16.686357 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 23:25:16.689954 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 23:25:16.693291 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 23:25:16.696673 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 23:25:16.703113 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 23:25:16.703228
6246 23:25:16.706371 CA PerBit enable=1, Macro0, CA PI delay=36
6247 23:25:16.706474
6248 23:25:16.709724 [CBTSetCACLKResult] CA Dly = 36
6249 23:25:16.709836 CS Dly: 1 (0~32)
6250 23:25:16.709939
6251 23:25:16.713369 ----->DramcWriteLeveling(PI) begin...
6252 23:25:16.713464 ==
6253 23:25:16.716611 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 23:25:16.719874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 23:25:16.722907 ==
6256 23:25:16.723019 Write leveling (Byte 0): 40 => 8
6257 23:25:16.726124 Write leveling (Byte 1): 40 => 8
6258 23:25:16.729667 DramcWriteLeveling(PI) end<-----
6259 23:25:16.729771
6260 23:25:16.729881 ==
6261 23:25:16.733095 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 23:25:16.739456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 23:25:16.739544 ==
6264 23:25:16.739611 [Gating] SW mode calibration
6265 23:25:16.749698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6266 23:25:16.752854 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6267 23:25:16.759354 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 23:25:16.762813 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 23:25:16.766279 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 23:25:16.769568 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 23:25:16.776324 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 23:25:16.779666 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 23:25:16.782985 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 23:25:16.789526 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 23:25:16.792909 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 23:25:16.796048 Total UI for P1: 0, mck2ui 16
6277 23:25:16.799627 best dqsien dly found for B0: ( 0, 14, 24)
6278 23:25:16.802618 Total UI for P1: 0, mck2ui 16
6279 23:25:16.806062 best dqsien dly found for B1: ( 0, 14, 24)
6280 23:25:16.809409 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6281 23:25:16.812653 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6282 23:25:16.812734
6283 23:25:16.815791 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 23:25:16.822911 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 23:25:16.822991 [Gating] SW calibration Done
6286 23:25:16.823058 ==
6287 23:25:16.826020 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 23:25:16.832534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 23:25:16.832645 ==
6290 23:25:16.832741 RX Vref Scan: 0
6291 23:25:16.832828
6292 23:25:16.836000 RX Vref 0 -> 0, step: 1
6293 23:25:16.836081
6294 23:25:16.839448 RX Delay -410 -> 252, step: 16
6295 23:25:16.842543 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6296 23:25:16.845998 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6297 23:25:16.852368 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6298 23:25:16.855931 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6299 23:25:16.858950 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6300 23:25:16.862333 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6301 23:25:16.869090 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6302 23:25:16.872433 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6303 23:25:16.875742 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6304 23:25:16.878770 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6305 23:25:16.885695 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6306 23:25:16.888639 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6307 23:25:16.892173 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6308 23:25:16.895465 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6309 23:25:16.902075 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6310 23:25:16.905244 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6311 23:25:16.905331 ==
6312 23:25:16.908747 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 23:25:16.912000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 23:25:16.912106 ==
6315 23:25:16.915150 DQS Delay:
6316 23:25:16.915237 DQS0 = 27, DQS1 = 35
6317 23:25:16.918747 DQM Delay:
6318 23:25:16.918856 DQM0 = 9, DQM1 = 12
6319 23:25:16.918951 DQ Delay:
6320 23:25:16.921731 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6321 23:25:16.925207 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6322 23:25:16.928516 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6323 23:25:16.931558 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6324 23:25:16.931639
6325 23:25:16.931703
6326 23:25:16.931763 ==
6327 23:25:16.935222 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 23:25:16.941607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 23:25:16.941692 ==
6330 23:25:16.941756
6331 23:25:16.941816
6332 23:25:16.941872 TX Vref Scan disable
6333 23:25:16.945011 == TX Byte 0 ==
6334 23:25:16.948338 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 23:25:16.951683 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 23:25:16.955029 == TX Byte 1 ==
6337 23:25:16.958099 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 23:25:16.961484 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 23:25:16.961566 ==
6340 23:25:16.964922 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 23:25:16.971328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 23:25:16.971411 ==
6343 23:25:16.971475
6344 23:25:16.971535
6345 23:25:16.971592 TX Vref Scan disable
6346 23:25:16.974877 == TX Byte 0 ==
6347 23:25:16.978091 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 23:25:16.981580 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 23:25:16.984619 == TX Byte 1 ==
6350 23:25:16.988033 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 23:25:16.991500 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 23:25:16.991578
6353 23:25:16.994637 [DATLAT]
6354 23:25:16.994766 Freq=400, CH0 RK0
6355 23:25:16.994881
6356 23:25:16.998120 DATLAT Default: 0xf
6357 23:25:16.998240 0, 0xFFFF, sum = 0
6358 23:25:17.001518 1, 0xFFFF, sum = 0
6359 23:25:17.001644 2, 0xFFFF, sum = 0
6360 23:25:17.004802 3, 0xFFFF, sum = 0
6361 23:25:17.004926 4, 0xFFFF, sum = 0
6362 23:25:17.008148 5, 0xFFFF, sum = 0
6363 23:25:17.008254 6, 0xFFFF, sum = 0
6364 23:25:17.011321 7, 0xFFFF, sum = 0
6365 23:25:17.011404 8, 0xFFFF, sum = 0
6366 23:25:17.014661 9, 0xFFFF, sum = 0
6367 23:25:17.018170 10, 0xFFFF, sum = 0
6368 23:25:17.018258 11, 0xFFFF, sum = 0
6369 23:25:17.021187 12, 0xFFFF, sum = 0
6370 23:25:17.021273 13, 0x0, sum = 1
6371 23:25:17.024631 14, 0x0, sum = 2
6372 23:25:17.024714 15, 0x0, sum = 3
6373 23:25:17.024780 16, 0x0, sum = 4
6374 23:25:17.028061 best_step = 14
6375 23:25:17.028142
6376 23:25:17.028206 ==
6377 23:25:17.031315 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 23:25:17.034564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 23:25:17.034646 ==
6380 23:25:17.038064 RX Vref Scan: 1
6381 23:25:17.038188
6382 23:25:17.038300 RX Vref 0 -> 0, step: 1
6383 23:25:17.041308
6384 23:25:17.041412 RX Delay -311 -> 252, step: 8
6385 23:25:17.041503
6386 23:25:17.044610 Set Vref, RX VrefLevel [Byte0]: 55
6387 23:25:17.048052 [Byte1]: 48
6388 23:25:17.053127
6389 23:25:17.053208 Final RX Vref Byte 0 = 55 to rank0
6390 23:25:17.056091 Final RX Vref Byte 1 = 48 to rank0
6391 23:25:17.059485 Final RX Vref Byte 0 = 55 to rank1
6392 23:25:17.063129 Final RX Vref Byte 1 = 48 to rank1==
6393 23:25:17.066198 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 23:25:17.072983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 23:25:17.073068 ==
6396 23:25:17.073134 DQS Delay:
6397 23:25:17.076363 DQS0 = 28, DQS1 = 36
6398 23:25:17.076448 DQM Delay:
6399 23:25:17.076513 DQM0 = 11, DQM1 = 13
6400 23:25:17.079291 DQ Delay:
6401 23:25:17.082569 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6402 23:25:17.082651 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6403 23:25:17.086372 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6404 23:25:17.089447 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6405 23:25:17.089529
6406 23:25:17.092951
6407 23:25:17.099208 [DQSOSCAuto] RK0, (LSB)MR18= 0xc9b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6408 23:25:17.102864 CH0 RK0: MR19=C0C, MR18=C9B7
6409 23:25:17.109234 CH0_RK0: MR19=0xC0C, MR18=0xC9B7, DQSOSC=384, MR23=63, INC=400, DEC=267
6410 23:25:17.109318 ==
6411 23:25:17.112722 Dram Type= 6, Freq= 0, CH_0, rank 1
6412 23:25:17.116226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 23:25:17.116338 ==
6414 23:25:17.119332 [Gating] SW mode calibration
6415 23:25:17.126033 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6416 23:25:17.132527 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6417 23:25:17.136074 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 23:25:17.139182 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 23:25:17.142706 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 23:25:17.149305 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 23:25:17.152612 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 23:25:17.155894 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 23:25:17.162782 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 23:25:17.165834 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 23:25:17.169173 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 23:25:17.172771 Total UI for P1: 0, mck2ui 16
6427 23:25:17.175727 best dqsien dly found for B0: ( 0, 14, 24)
6428 23:25:17.179183 Total UI for P1: 0, mck2ui 16
6429 23:25:17.182557 best dqsien dly found for B1: ( 0, 14, 24)
6430 23:25:17.185920 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6431 23:25:17.192407 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6432 23:25:17.192491
6433 23:25:17.195767 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 23:25:17.199284 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 23:25:17.202234 [Gating] SW calibration Done
6436 23:25:17.202311 ==
6437 23:25:17.205824 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 23:25:17.209007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 23:25:17.209091 ==
6440 23:25:17.209158 RX Vref Scan: 0
6441 23:25:17.212393
6442 23:25:17.212503 RX Vref 0 -> 0, step: 1
6443 23:25:17.212597
6444 23:25:17.215845 RX Delay -410 -> 252, step: 16
6445 23:25:17.218943 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6446 23:25:17.225809 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6447 23:25:17.229117 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6448 23:25:17.232151 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6449 23:25:17.235584 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6450 23:25:17.242139 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6451 23:25:17.245552 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6452 23:25:17.248849 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6453 23:25:17.252017 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6454 23:25:17.258589 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6455 23:25:17.262187 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6456 23:25:17.265485 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6457 23:25:17.268841 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6458 23:25:17.275187 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6459 23:25:17.278511 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6460 23:25:17.282142 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6461 23:25:17.282237 ==
6462 23:25:17.285443 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 23:25:17.292143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 23:25:17.292263 ==
6465 23:25:17.292361 DQS Delay:
6466 23:25:17.292444 DQS0 = 19, DQS1 = 27
6467 23:25:17.295082 DQM Delay:
6468 23:25:17.295163 DQM0 = 5, DQM1 = 6
6469 23:25:17.298406 DQ Delay:
6470 23:25:17.298512 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6471 23:25:17.301989 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6472 23:25:17.304978 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6473 23:25:17.308374 DQ12 =8, DQ13 =8, DQ14 =16, DQ15 =8
6474 23:25:17.308519
6475 23:25:17.308636
6476 23:25:17.308764 ==
6477 23:25:17.311714 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 23:25:17.318295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 23:25:17.318409 ==
6480 23:25:17.318508
6481 23:25:17.318608
6482 23:25:17.318701 TX Vref Scan disable
6483 23:25:17.321769 == TX Byte 0 ==
6484 23:25:17.324928 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6485 23:25:17.328317 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6486 23:25:17.331663 == TX Byte 1 ==
6487 23:25:17.335090 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6488 23:25:17.338245 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6489 23:25:17.338362 ==
6490 23:25:17.341517 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 23:25:17.348519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 23:25:17.348660 ==
6493 23:25:17.348785
6494 23:25:17.348909
6495 23:25:17.349025 TX Vref Scan disable
6496 23:25:17.351467 == TX Byte 0 ==
6497 23:25:17.354969 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6498 23:25:17.358362 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6499 23:25:17.361794 == TX Byte 1 ==
6500 23:25:17.365226 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6501 23:25:17.368218 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6502 23:25:17.368334
6503 23:25:17.371480 [DATLAT]
6504 23:25:17.371589 Freq=400, CH0 RK1
6505 23:25:17.371684
6506 23:25:17.374901 DATLAT Default: 0xe
6507 23:25:17.374991 0, 0xFFFF, sum = 0
6508 23:25:17.378307 1, 0xFFFF, sum = 0
6509 23:25:17.378415 2, 0xFFFF, sum = 0
6510 23:25:17.381513 3, 0xFFFF, sum = 0
6511 23:25:17.381640 4, 0xFFFF, sum = 0
6512 23:25:17.385247 5, 0xFFFF, sum = 0
6513 23:25:17.385359 6, 0xFFFF, sum = 0
6514 23:25:17.388276 7, 0xFFFF, sum = 0
6515 23:25:17.388394 8, 0xFFFF, sum = 0
6516 23:25:17.391782 9, 0xFFFF, sum = 0
6517 23:25:17.391907 10, 0xFFFF, sum = 0
6518 23:25:17.394907 11, 0xFFFF, sum = 0
6519 23:25:17.398309 12, 0xFFFF, sum = 0
6520 23:25:17.398442 13, 0x0, sum = 1
6521 23:25:17.401510 14, 0x0, sum = 2
6522 23:25:17.401638 15, 0x0, sum = 3
6523 23:25:17.401755 16, 0x0, sum = 4
6524 23:25:17.404713 best_step = 14
6525 23:25:17.404804
6526 23:25:17.404902 ==
6527 23:25:17.407985 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 23:25:17.411597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 23:25:17.411725 ==
6530 23:25:17.414615 RX Vref Scan: 0
6531 23:25:17.414717
6532 23:25:17.414808 RX Vref 0 -> 0, step: 1
6533 23:25:17.418048
6534 23:25:17.418170 RX Delay -295 -> 252, step: 8
6535 23:25:17.426053 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6536 23:25:17.429607 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6537 23:25:17.433167 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6538 23:25:17.436421 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6539 23:25:17.442679 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6540 23:25:17.445998 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6541 23:25:17.449427 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6542 23:25:17.452926 iDelay=217, Bit 7, Center -4 (-223 ~ 216) 440
6543 23:25:17.459333 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6544 23:25:17.462813 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6545 23:25:17.466280 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6546 23:25:17.469470 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6547 23:25:17.475947 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6548 23:25:17.479296 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6549 23:25:17.482586 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6550 23:25:17.489281 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6551 23:25:17.489390 ==
6552 23:25:17.492335 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 23:25:17.495902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 23:25:17.496047 ==
6555 23:25:17.496196 DQS Delay:
6556 23:25:17.499254 DQS0 = 24, DQS1 = 32
6557 23:25:17.499406 DQM Delay:
6558 23:25:17.502783 DQM0 = 8, DQM1 = 9
6559 23:25:17.502898 DQ Delay:
6560 23:25:17.505765 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6561 23:25:17.509357 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =20
6562 23:25:17.512472 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6563 23:25:17.515794 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6564 23:25:17.515929
6565 23:25:17.516044
6566 23:25:17.522462 [DQSOSCAuto] RK1, (LSB)MR18= 0xb555, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6567 23:25:17.525548 CH0 RK1: MR19=C0C, MR18=B555
6568 23:25:17.532388 CH0_RK1: MR19=0xC0C, MR18=0xB555, DQSOSC=387, MR23=63, INC=394, DEC=262
6569 23:25:17.535674 [RxdqsGatingPostProcess] freq 400
6570 23:25:17.541963 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6571 23:25:17.542091 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 23:25:17.545351 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 23:25:17.548893 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 23:25:17.551856 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 23:25:17.555293 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 23:25:17.558417 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 23:25:17.561934 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 23:25:17.565397 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 23:25:17.568571 Pre-setting of DQS Precalculation
6580 23:25:17.575267 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6581 23:25:17.575355 ==
6582 23:25:17.578741 Dram Type= 6, Freq= 0, CH_1, rank 0
6583 23:25:17.581823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 23:25:17.581908 ==
6585 23:25:17.588417 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6586 23:25:17.591856 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6587 23:25:17.595142 [CA 0] Center 36 (8~64) winsize 57
6588 23:25:17.598548 [CA 1] Center 36 (8~64) winsize 57
6589 23:25:17.601738 [CA 2] Center 36 (8~64) winsize 57
6590 23:25:17.605206 [CA 3] Center 36 (8~64) winsize 57
6591 23:25:17.608278 [CA 4] Center 36 (8~64) winsize 57
6592 23:25:17.611635 [CA 5] Center 36 (8~64) winsize 57
6593 23:25:17.611723
6594 23:25:17.615209 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6595 23:25:17.615292
6596 23:25:17.618313 [CATrainingPosCal] consider 1 rank data
6597 23:25:17.621622 u2DelayCellTimex100 = 270/100 ps
6598 23:25:17.624929 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 23:25:17.628265 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 23:25:17.631364 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 23:25:17.638068 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 23:25:17.641520 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 23:25:17.644826 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 23:25:17.644909
6605 23:25:17.648036 CA PerBit enable=1, Macro0, CA PI delay=36
6606 23:25:17.648109
6607 23:25:17.651254 [CBTSetCACLKResult] CA Dly = 36
6608 23:25:17.651331 CS Dly: 1 (0~32)
6609 23:25:17.651400 ==
6610 23:25:17.654756 Dram Type= 6, Freq= 0, CH_1, rank 1
6611 23:25:17.661368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 23:25:17.661457 ==
6613 23:25:17.664852 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 23:25:17.671497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6615 23:25:17.674730 [CA 0] Center 36 (8~64) winsize 57
6616 23:25:17.677996 [CA 1] Center 36 (8~64) winsize 57
6617 23:25:17.681200 [CA 2] Center 36 (8~64) winsize 57
6618 23:25:17.684589 [CA 3] Center 36 (8~64) winsize 57
6619 23:25:17.687970 [CA 4] Center 36 (8~64) winsize 57
6620 23:25:17.691474 [CA 5] Center 36 (8~64) winsize 57
6621 23:25:17.691551
6622 23:25:17.694474 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6623 23:25:17.694553
6624 23:25:17.697946 [CATrainingPosCal] consider 2 rank data
6625 23:25:17.701394 u2DelayCellTimex100 = 270/100 ps
6626 23:25:17.704470 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 23:25:17.707720 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 23:25:17.711491 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 23:25:17.714770 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 23:25:17.717994 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 23:25:17.721623 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 23:25:17.721698
6633 23:25:17.727950 CA PerBit enable=1, Macro0, CA PI delay=36
6634 23:25:17.728061
6635 23:25:17.731344 [CBTSetCACLKResult] CA Dly = 36
6636 23:25:17.731434 CS Dly: 1 (0~32)
6637 23:25:17.731502
6638 23:25:17.734353 ----->DramcWriteLeveling(PI) begin...
6639 23:25:17.734430 ==
6640 23:25:17.737702 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 23:25:17.740920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 23:25:17.741022 ==
6643 23:25:17.744381 Write leveling (Byte 0): 40 => 8
6644 23:25:17.747692 Write leveling (Byte 1): 40 => 8
6645 23:25:17.750770 DramcWriteLeveling(PI) end<-----
6646 23:25:17.750881
6647 23:25:17.750976 ==
6648 23:25:17.754188 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 23:25:17.757468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 23:25:17.761042 ==
6651 23:25:17.761121 [Gating] SW mode calibration
6652 23:25:17.770845 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6653 23:25:17.774318 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6654 23:25:17.777671 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 23:25:17.784452 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 23:25:17.787549 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 23:25:17.791106 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 23:25:17.797701 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 23:25:17.800825 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 23:25:17.804274 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 23:25:17.811098 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 23:25:17.814377 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 23:25:17.817358 Total UI for P1: 0, mck2ui 16
6664 23:25:17.820781 best dqsien dly found for B0: ( 0, 14, 24)
6665 23:25:17.824036 Total UI for P1: 0, mck2ui 16
6666 23:25:17.827408 best dqsien dly found for B1: ( 0, 14, 24)
6667 23:25:17.830641 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6668 23:25:17.833881 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6669 23:25:17.833964
6670 23:25:17.837375 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 23:25:17.840476 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 23:25:17.843935 [Gating] SW calibration Done
6673 23:25:17.844017 ==
6674 23:25:17.847437 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 23:25:17.850811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 23:25:17.854014 ==
6677 23:25:17.854099 RX Vref Scan: 0
6678 23:25:17.854186
6679 23:25:17.857293 RX Vref 0 -> 0, step: 1
6680 23:25:17.857404
6681 23:25:17.860515 RX Delay -410 -> 252, step: 16
6682 23:25:17.863874 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6683 23:25:17.867350 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6684 23:25:17.870847 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6685 23:25:17.877152 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6686 23:25:17.880361 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6687 23:25:17.884069 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6688 23:25:17.887143 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6689 23:25:17.893842 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6690 23:25:17.897225 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6691 23:25:17.900646 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6692 23:25:17.903713 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6693 23:25:17.910456 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6694 23:25:17.913949 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6695 23:25:17.917241 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6696 23:25:17.920363 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6697 23:25:17.927145 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6698 23:25:17.927259 ==
6699 23:25:17.930295 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 23:25:17.933566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 23:25:17.933652 ==
6702 23:25:17.933716 DQS Delay:
6703 23:25:17.936910 DQS0 = 35, DQS1 = 35
6704 23:25:17.936982 DQM Delay:
6705 23:25:17.940158 DQM0 = 18, DQM1 = 14
6706 23:25:17.940257 DQ Delay:
6707 23:25:17.943648 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6708 23:25:17.946922 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6709 23:25:17.950107 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6710 23:25:17.953595 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6711 23:25:17.953684
6712 23:25:17.953763
6713 23:25:17.953826 ==
6714 23:25:17.956717 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 23:25:17.960097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 23:25:17.963273 ==
6717 23:25:17.963350
6718 23:25:17.963414
6719 23:25:17.963489 TX Vref Scan disable
6720 23:25:17.966675 == TX Byte 0 ==
6721 23:25:17.970089 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 23:25:17.973406 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 23:25:17.976895 == TX Byte 1 ==
6724 23:25:17.980028 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 23:25:17.983478 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 23:25:17.983561 ==
6727 23:25:17.986525 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 23:25:17.993198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 23:25:17.993287 ==
6730 23:25:17.993367
6731 23:25:17.993430
6732 23:25:17.993489 TX Vref Scan disable
6733 23:25:17.996618 == TX Byte 0 ==
6734 23:25:17.999984 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 23:25:18.003604 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 23:25:18.006799 == TX Byte 1 ==
6737 23:25:18.009899 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 23:25:18.013256 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 23:25:18.013340
6740 23:25:18.016516 [DATLAT]
6741 23:25:18.016598 Freq=400, CH1 RK0
6742 23:25:18.016674
6743 23:25:18.020026 DATLAT Default: 0xf
6744 23:25:18.020109 0, 0xFFFF, sum = 0
6745 23:25:18.023198 1, 0xFFFF, sum = 0
6746 23:25:18.023282 2, 0xFFFF, sum = 0
6747 23:25:18.026334 3, 0xFFFF, sum = 0
6748 23:25:18.026418 4, 0xFFFF, sum = 0
6749 23:25:18.029962 5, 0xFFFF, sum = 0
6750 23:25:18.030046 6, 0xFFFF, sum = 0
6751 23:25:18.033275 7, 0xFFFF, sum = 0
6752 23:25:18.033359 8, 0xFFFF, sum = 0
6753 23:25:18.036553 9, 0xFFFF, sum = 0
6754 23:25:18.036638 10, 0xFFFF, sum = 0
6755 23:25:18.039557 11, 0xFFFF, sum = 0
6756 23:25:18.042926 12, 0xFFFF, sum = 0
6757 23:25:18.043013 13, 0x0, sum = 1
6758 23:25:18.043080 14, 0x0, sum = 2
6759 23:25:18.046228 15, 0x0, sum = 3
6760 23:25:18.046312 16, 0x0, sum = 4
6761 23:25:18.049565 best_step = 14
6762 23:25:18.049648
6763 23:25:18.049713 ==
6764 23:25:18.052975 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 23:25:18.056391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 23:25:18.056501 ==
6767 23:25:18.059486 RX Vref Scan: 1
6768 23:25:18.059569
6769 23:25:18.059634 RX Vref 0 -> 0, step: 1
6770 23:25:18.059694
6771 23:25:18.063008 RX Delay -311 -> 252, step: 8
6772 23:25:18.063092
6773 23:25:18.066558 Set Vref, RX VrefLevel [Byte0]: 54
6774 23:25:18.069605 [Byte1]: 53
6775 23:25:18.074328
6776 23:25:18.077541 Final RX Vref Byte 0 = 54 to rank0
6777 23:25:18.077625 Final RX Vref Byte 1 = 53 to rank0
6778 23:25:18.080983 Final RX Vref Byte 0 = 54 to rank1
6779 23:25:18.084135 Final RX Vref Byte 1 = 53 to rank1==
6780 23:25:18.087422 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 23:25:18.093997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 23:25:18.094082 ==
6783 23:25:18.094148 DQS Delay:
6784 23:25:18.097483 DQS0 = 32, DQS1 = 32
6785 23:25:18.097566 DQM Delay:
6786 23:25:18.097632 DQM0 = 13, DQM1 = 10
6787 23:25:18.100614 DQ Delay:
6788 23:25:18.103961 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6789 23:25:18.107138 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6790 23:25:18.107222 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6791 23:25:18.113854 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6792 23:25:18.113937
6793 23:25:18.114002
6794 23:25:18.120408 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6795 23:25:18.123769 CH1 RK0: MR19=C0C, MR18=93CC
6796 23:25:18.130388 CH1_RK0: MR19=0xC0C, MR18=0x93CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6797 23:25:18.130497 ==
6798 23:25:18.133800 Dram Type= 6, Freq= 0, CH_1, rank 1
6799 23:25:18.137109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 23:25:18.137192 ==
6801 23:25:18.140137 [Gating] SW mode calibration
6802 23:25:18.146897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6803 23:25:18.153605 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6804 23:25:18.157250 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 23:25:18.160133 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 23:25:18.166923 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 23:25:18.170424 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 23:25:18.173839 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 23:25:18.180427 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 23:25:18.183885 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 23:25:18.187020 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 23:25:18.193560 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 23:25:18.193643 Total UI for P1: 0, mck2ui 16
6814 23:25:18.200163 best dqsien dly found for B0: ( 0, 14, 24)
6815 23:25:18.200247 Total UI for P1: 0, mck2ui 16
6816 23:25:18.203355 best dqsien dly found for B1: ( 0, 14, 24)
6817 23:25:18.210315 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6818 23:25:18.213290 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6819 23:25:18.213374
6820 23:25:18.216785 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 23:25:18.220246 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 23:25:18.223576 [Gating] SW calibration Done
6823 23:25:18.223659 ==
6824 23:25:18.226874 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 23:25:18.230249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 23:25:18.230333 ==
6827 23:25:18.233262 RX Vref Scan: 0
6828 23:25:18.233345
6829 23:25:18.233411 RX Vref 0 -> 0, step: 1
6830 23:25:18.233473
6831 23:25:18.236616 RX Delay -410 -> 252, step: 16
6832 23:25:18.243500 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6833 23:25:18.246781 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6834 23:25:18.250004 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6835 23:25:18.253170 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6836 23:25:18.256506 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6837 23:25:18.263202 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6838 23:25:18.266514 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6839 23:25:18.269800 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6840 23:25:18.273266 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6841 23:25:18.279758 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6842 23:25:18.283214 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6843 23:25:18.286313 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6844 23:25:18.293066 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6845 23:25:18.296582 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6846 23:25:18.299561 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6847 23:25:18.302937 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6848 23:25:18.303046 ==
6849 23:25:18.306275 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 23:25:18.312966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 23:25:18.313045 ==
6852 23:25:18.313136 DQS Delay:
6853 23:25:18.316124 DQS0 = 35, DQS1 = 35
6854 23:25:18.316226 DQM Delay:
6855 23:25:18.319518 DQM0 = 17, DQM1 = 14
6856 23:25:18.319602 DQ Delay:
6857 23:25:18.322796 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6858 23:25:18.326443 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6859 23:25:18.329878 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6860 23:25:18.333028 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6861 23:25:18.333110
6862 23:25:18.333222
6863 23:25:18.333297 ==
6864 23:25:18.336298 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 23:25:18.339719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 23:25:18.339807 ==
6867 23:25:18.339908
6868 23:25:18.339970
6869 23:25:18.343096 TX Vref Scan disable
6870 23:25:18.343178 == TX Byte 0 ==
6871 23:25:18.349708 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6872 23:25:18.353100 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6873 23:25:18.353182 == TX Byte 1 ==
6874 23:25:18.356261 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6875 23:25:18.363147 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6876 23:25:18.363230 ==
6877 23:25:18.366143 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 23:25:18.369494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 23:25:18.369577 ==
6880 23:25:18.369642
6881 23:25:18.369703
6882 23:25:18.372947 TX Vref Scan disable
6883 23:25:18.373049 == TX Byte 0 ==
6884 23:25:18.379490 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6885 23:25:18.383048 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6886 23:25:18.383172 == TX Byte 1 ==
6887 23:25:18.386115 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6888 23:25:18.393078 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6889 23:25:18.393242
6890 23:25:18.393354 [DATLAT]
6891 23:25:18.396148 Freq=400, CH1 RK1
6892 23:25:18.396294
6893 23:25:18.396423 DATLAT Default: 0xe
6894 23:25:18.399527 0, 0xFFFF, sum = 0
6895 23:25:18.399655 1, 0xFFFF, sum = 0
6896 23:25:18.402596 2, 0xFFFF, sum = 0
6897 23:25:18.402741 3, 0xFFFF, sum = 0
6898 23:25:18.406019 4, 0xFFFF, sum = 0
6899 23:25:18.406111 5, 0xFFFF, sum = 0
6900 23:25:18.409493 6, 0xFFFF, sum = 0
6901 23:25:18.409627 7, 0xFFFF, sum = 0
6902 23:25:18.412619 8, 0xFFFF, sum = 0
6903 23:25:18.412750 9, 0xFFFF, sum = 0
6904 23:25:18.416050 10, 0xFFFF, sum = 0
6905 23:25:18.416180 11, 0xFFFF, sum = 0
6906 23:25:18.419556 12, 0xFFFF, sum = 0
6907 23:25:18.419684 13, 0x0, sum = 1
6908 23:25:18.423079 14, 0x0, sum = 2
6909 23:25:18.423208 15, 0x0, sum = 3
6910 23:25:18.426264 16, 0x0, sum = 4
6911 23:25:18.426373 best_step = 14
6912 23:25:18.426477
6913 23:25:18.426570 ==
6914 23:25:18.429138 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 23:25:18.435712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 23:25:18.435816 ==
6917 23:25:18.435909 RX Vref Scan: 0
6918 23:25:18.436015
6919 23:25:18.439361 RX Vref 0 -> 0, step: 1
6920 23:25:18.439473
6921 23:25:18.442257 RX Delay -311 -> 252, step: 8
6922 23:25:18.449103 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6923 23:25:18.452427 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6924 23:25:18.455830 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6925 23:25:18.459312 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6926 23:25:18.465636 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6927 23:25:18.469137 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6928 23:25:18.472507 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6929 23:25:18.475430 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6930 23:25:18.482406 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6931 23:25:18.485358 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6932 23:25:18.488901 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6933 23:25:18.492278 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6934 23:25:18.498803 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6935 23:25:18.502026 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6936 23:25:18.505636 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6937 23:25:18.508651 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6938 23:25:18.512123 ==
6939 23:25:18.515362 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 23:25:18.518801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 23:25:18.518907 ==
6942 23:25:18.519001 DQS Delay:
6943 23:25:18.522244 DQS0 = 28, DQS1 = 36
6944 23:25:18.522321 DQM Delay:
6945 23:25:18.525261 DQM0 = 11, DQM1 = 14
6946 23:25:18.525346 DQ Delay:
6947 23:25:18.528702 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6948 23:25:18.532104 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6949 23:25:18.535142 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6950 23:25:18.538476 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6951 23:25:18.538575
6952 23:25:18.538666
6953 23:25:18.545157 [DQSOSCAuto] RK1, (LSB)MR18= 0xc051, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
6954 23:25:18.548536 CH1 RK1: MR19=C0C, MR18=C051
6955 23:25:18.554902 CH1_RK1: MR19=0xC0C, MR18=0xC051, DQSOSC=386, MR23=63, INC=396, DEC=264
6956 23:25:18.558405 [RxdqsGatingPostProcess] freq 400
6957 23:25:18.564923 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6958 23:25:18.565006 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 23:25:18.568110 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 23:25:18.571577 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 23:25:18.574920 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 23:25:18.578384 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 23:25:18.581753 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 23:25:18.584732 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 23:25:18.588218 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 23:25:18.591568 Pre-setting of DQS Precalculation
6967 23:25:18.595153 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6968 23:25:18.604992 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6969 23:25:18.611686 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6970 23:25:18.611769
6971 23:25:18.611835
6972 23:25:18.615141 [Calibration Summary] 800 Mbps
6973 23:25:18.615224 CH 0, Rank 0
6974 23:25:18.617911 SW Impedance : PASS
6975 23:25:18.617995 DUTY Scan : NO K
6976 23:25:18.621583 ZQ Calibration : PASS
6977 23:25:18.624721 Jitter Meter : NO K
6978 23:25:18.624805 CBT Training : PASS
6979 23:25:18.628128 Write leveling : PASS
6980 23:25:18.631385 RX DQS gating : PASS
6981 23:25:18.631496 RX DQ/DQS(RDDQC) : PASS
6982 23:25:18.634724 TX DQ/DQS : PASS
6983 23:25:18.638157 RX DATLAT : PASS
6984 23:25:18.638260 RX DQ/DQS(Engine): PASS
6985 23:25:18.641153 TX OE : NO K
6986 23:25:18.641256 All Pass.
6987 23:25:18.641356
6988 23:25:18.644551 CH 0, Rank 1
6989 23:25:18.644641 SW Impedance : PASS
6990 23:25:18.647736 DUTY Scan : NO K
6991 23:25:18.651454 ZQ Calibration : PASS
6992 23:25:18.651536 Jitter Meter : NO K
6993 23:25:18.654500 CBT Training : PASS
6994 23:25:18.657968 Write leveling : NO K
6995 23:25:18.658076 RX DQS gating : PASS
6996 23:25:18.661029 RX DQ/DQS(RDDQC) : PASS
6997 23:25:18.661117 TX DQ/DQS : PASS
6998 23:25:18.664374 RX DATLAT : PASS
6999 23:25:18.667852 RX DQ/DQS(Engine): PASS
7000 23:25:18.667953 TX OE : NO K
7001 23:25:18.670939 All Pass.
7002 23:25:18.671038
7003 23:25:18.671136 CH 1, Rank 0
7004 23:25:18.674199 SW Impedance : PASS
7005 23:25:18.674274 DUTY Scan : NO K
7006 23:25:18.677675 ZQ Calibration : PASS
7007 23:25:18.680916 Jitter Meter : NO K
7008 23:25:18.680992 CBT Training : PASS
7009 23:25:18.684277 Write leveling : PASS
7010 23:25:18.687455 RX DQS gating : PASS
7011 23:25:18.687559 RX DQ/DQS(RDDQC) : PASS
7012 23:25:18.691069 TX DQ/DQS : PASS
7013 23:25:18.694288 RX DATLAT : PASS
7014 23:25:18.694397 RX DQ/DQS(Engine): PASS
7015 23:25:18.697515 TX OE : NO K
7016 23:25:18.697619 All Pass.
7017 23:25:18.697711
7018 23:25:18.700610 CH 1, Rank 1
7019 23:25:18.700708 SW Impedance : PASS
7020 23:25:18.704142 DUTY Scan : NO K
7021 23:25:18.707374 ZQ Calibration : PASS
7022 23:25:18.707486 Jitter Meter : NO K
7023 23:25:18.710753 CBT Training : PASS
7024 23:25:18.714115 Write leveling : NO K
7025 23:25:18.714227 RX DQS gating : PASS
7026 23:25:18.717180 RX DQ/DQS(RDDQC) : PASS
7027 23:25:18.720703 TX DQ/DQS : PASS
7028 23:25:18.720788 RX DATLAT : PASS
7029 23:25:18.724089 RX DQ/DQS(Engine): PASS
7030 23:25:18.724173 TX OE : NO K
7031 23:25:18.727497 All Pass.
7032 23:25:18.727580
7033 23:25:18.727646 DramC Write-DBI off
7034 23:25:18.730747 PER_BANK_REFRESH: Hybrid Mode
7035 23:25:18.733911 TX_TRACKING: ON
7036 23:25:18.740605 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7037 23:25:18.744086 [FAST_K] Save calibration result to emmc
7038 23:25:18.750823 dramc_set_vcore_voltage set vcore to 725000
7039 23:25:18.750908 Read voltage for 1600, 0
7040 23:25:18.750975 Vio18 = 0
7041 23:25:18.754063 Vcore = 725000
7042 23:25:18.754147 Vdram = 0
7043 23:25:18.754213 Vddq = 0
7044 23:25:18.757392 Vmddr = 0
7045 23:25:18.760738 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7046 23:25:18.767330 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7047 23:25:18.770836 MEM_TYPE=3, freq_sel=13
7048 23:25:18.770921 sv_algorithm_assistance_LP4_3733
7049 23:25:18.777339 ============ PULL DRAM RESETB DOWN ============
7050 23:25:18.780716 ========== PULL DRAM RESETB DOWN end =========
7051 23:25:18.784039 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7052 23:25:18.787431 ===================================
7053 23:25:18.790759 LPDDR4 DRAM CONFIGURATION
7054 23:25:18.793823 ===================================
7055 23:25:18.797375 EX_ROW_EN[0] = 0x0
7056 23:25:18.797460 EX_ROW_EN[1] = 0x0
7057 23:25:18.800886 LP4Y_EN = 0x0
7058 23:25:18.800970 WORK_FSP = 0x1
7059 23:25:18.804093 WL = 0x5
7060 23:25:18.804176 RL = 0x5
7061 23:25:18.807365 BL = 0x2
7062 23:25:18.807480 RPST = 0x0
7063 23:25:18.810355 RD_PRE = 0x0
7064 23:25:18.810439 WR_PRE = 0x1
7065 23:25:18.813536 WR_PST = 0x1
7066 23:25:18.813620 DBI_WR = 0x0
7067 23:25:18.817077 DBI_RD = 0x0
7068 23:25:18.817161 OTF = 0x1
7069 23:25:18.820546 ===================================
7070 23:25:18.823549 ===================================
7071 23:25:18.826999 ANA top config
7072 23:25:18.830529 ===================================
7073 23:25:18.833549 DLL_ASYNC_EN = 0
7074 23:25:18.833634 ALL_SLAVE_EN = 0
7075 23:25:18.836943 NEW_RANK_MODE = 1
7076 23:25:18.840326 DLL_IDLE_MODE = 1
7077 23:25:18.843667 LP45_APHY_COMB_EN = 1
7078 23:25:18.843750 TX_ODT_DIS = 0
7079 23:25:18.846857 NEW_8X_MODE = 1
7080 23:25:18.850396 ===================================
7081 23:25:18.853682 ===================================
7082 23:25:18.856915 data_rate = 3200
7083 23:25:18.860260 CKR = 1
7084 23:25:18.863446 DQ_P2S_RATIO = 8
7085 23:25:18.866663 ===================================
7086 23:25:18.870161 CA_P2S_RATIO = 8
7087 23:25:18.870244 DQ_CA_OPEN = 0
7088 23:25:18.873592 DQ_SEMI_OPEN = 0
7089 23:25:18.877073 CA_SEMI_OPEN = 0
7090 23:25:18.880003 CA_FULL_RATE = 0
7091 23:25:18.883510 DQ_CKDIV4_EN = 0
7092 23:25:18.886526 CA_CKDIV4_EN = 0
7093 23:25:18.886610 CA_PREDIV_EN = 0
7094 23:25:18.889989 PH8_DLY = 12
7095 23:25:18.893405 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7096 23:25:18.897160 DQ_AAMCK_DIV = 4
7097 23:25:18.900139 CA_AAMCK_DIV = 4
7098 23:25:18.903666 CA_ADMCK_DIV = 4
7099 23:25:18.903749 DQ_TRACK_CA_EN = 0
7100 23:25:18.906633 CA_PICK = 1600
7101 23:25:18.910008 CA_MCKIO = 1600
7102 23:25:18.913539 MCKIO_SEMI = 0
7103 23:25:18.916679 PLL_FREQ = 3068
7104 23:25:18.920125 DQ_UI_PI_RATIO = 32
7105 23:25:18.923265 CA_UI_PI_RATIO = 0
7106 23:25:18.926817 ===================================
7107 23:25:18.929767 ===================================
7108 23:25:18.929851 memory_type:LPDDR4
7109 23:25:18.933261 GP_NUM : 10
7110 23:25:18.936687 SRAM_EN : 1
7111 23:25:18.936769 MD32_EN : 0
7112 23:25:18.939621 ===================================
7113 23:25:18.943164 [ANA_INIT] >>>>>>>>>>>>>>
7114 23:25:18.946480 <<<<<< [CONFIGURE PHASE]: ANA_TX
7115 23:25:18.949532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7116 23:25:18.952818 ===================================
7117 23:25:18.956191 data_rate = 3200,PCW = 0X7600
7118 23:25:18.959692 ===================================
7119 23:25:18.962792 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7120 23:25:18.966176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 23:25:18.972939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 23:25:18.975877 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7123 23:25:18.982710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7124 23:25:18.986307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7125 23:25:18.986392 [ANA_INIT] flow start
7126 23:25:18.989636 [ANA_INIT] PLL >>>>>>>>
7127 23:25:18.992679 [ANA_INIT] PLL <<<<<<<<
7128 23:25:18.992760 [ANA_INIT] MIDPI >>>>>>>>
7129 23:25:18.996136 [ANA_INIT] MIDPI <<<<<<<<
7130 23:25:18.999308 [ANA_INIT] DLL >>>>>>>>
7131 23:25:18.999404 [ANA_INIT] DLL <<<<<<<<
7132 23:25:19.002904 [ANA_INIT] flow end
7133 23:25:19.005897 ============ LP4 DIFF to SE enter ============
7134 23:25:19.009378 ============ LP4 DIFF to SE exit ============
7135 23:25:19.012354 [ANA_INIT] <<<<<<<<<<<<<
7136 23:25:19.015715 [Flow] Enable top DCM control >>>>>
7137 23:25:19.019187 [Flow] Enable top DCM control <<<<<
7138 23:25:19.022524 Enable DLL master slave shuffle
7139 23:25:19.028978 ==============================================================
7140 23:25:19.029061 Gating Mode config
7141 23:25:19.035671 ==============================================================
7142 23:25:19.035756 Config description:
7143 23:25:19.045632 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7144 23:25:19.052244 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7145 23:25:19.059009 SELPH_MODE 0: By rank 1: By Phase
7146 23:25:19.062105 ==============================================================
7147 23:25:19.065515 GAT_TRACK_EN = 1
7148 23:25:19.068949 RX_GATING_MODE = 2
7149 23:25:19.072478 RX_GATING_TRACK_MODE = 2
7150 23:25:19.075598 SELPH_MODE = 1
7151 23:25:19.079123 PICG_EARLY_EN = 1
7152 23:25:19.082060 VALID_LAT_VALUE = 1
7153 23:25:19.088868 ==============================================================
7154 23:25:19.092031 Enter into Gating configuration >>>>
7155 23:25:19.095343 Exit from Gating configuration <<<<
7156 23:25:19.095430 Enter into DVFS_PRE_config >>>>>
7157 23:25:19.108931 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7158 23:25:19.112062 Exit from DVFS_PRE_config <<<<<
7159 23:25:19.115353 Enter into PICG configuration >>>>
7160 23:25:19.118885 Exit from PICG configuration <<<<
7161 23:25:19.118967 [RX_INPUT] configuration >>>>>
7162 23:25:19.122286 [RX_INPUT] configuration <<<<<
7163 23:25:19.128672 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7164 23:25:19.131988 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7165 23:25:19.138701 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 23:25:19.145442 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 23:25:19.152143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 23:25:19.158609 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 23:25:19.162004 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7170 23:25:19.165442 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7171 23:25:19.171913 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7172 23:25:19.175398 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7173 23:25:19.178421 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7174 23:25:19.182008 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 23:25:19.185176 ===================================
7176 23:25:19.188625 LPDDR4 DRAM CONFIGURATION
7177 23:25:19.191693 ===================================
7178 23:25:19.195186 EX_ROW_EN[0] = 0x0
7179 23:25:19.195265 EX_ROW_EN[1] = 0x0
7180 23:25:19.198695 LP4Y_EN = 0x0
7181 23:25:19.198772 WORK_FSP = 0x1
7182 23:25:19.202016 WL = 0x5
7183 23:25:19.202090 RL = 0x5
7184 23:25:19.205156 BL = 0x2
7185 23:25:19.205228 RPST = 0x0
7186 23:25:19.208216 RD_PRE = 0x0
7187 23:25:19.208321 WR_PRE = 0x1
7188 23:25:19.211690 WR_PST = 0x1
7189 23:25:19.214947 DBI_WR = 0x0
7190 23:25:19.215021 DBI_RD = 0x0
7191 23:25:19.218293 OTF = 0x1
7192 23:25:19.221593 ===================================
7193 23:25:19.224898 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7194 23:25:19.228197 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7195 23:25:19.231481 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 23:25:19.234854 ===================================
7197 23:25:19.238221 LPDDR4 DRAM CONFIGURATION
7198 23:25:19.241471 ===================================
7199 23:25:19.244957 EX_ROW_EN[0] = 0x10
7200 23:25:19.245035 EX_ROW_EN[1] = 0x0
7201 23:25:19.248406 LP4Y_EN = 0x0
7202 23:25:19.248481 WORK_FSP = 0x1
7203 23:25:19.251722 WL = 0x5
7204 23:25:19.251806 RL = 0x5
7205 23:25:19.255186 BL = 0x2
7206 23:25:19.255262 RPST = 0x0
7207 23:25:19.258242 RD_PRE = 0x0
7208 23:25:19.258329 WR_PRE = 0x1
7209 23:25:19.261612 WR_PST = 0x1
7210 23:25:19.261688 DBI_WR = 0x0
7211 23:25:19.264907 DBI_RD = 0x0
7212 23:25:19.264981 OTF = 0x1
7213 23:25:19.268185 ===================================
7214 23:25:19.274604 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7215 23:25:19.274686 ==
7216 23:25:19.278091 Dram Type= 6, Freq= 0, CH_0, rank 0
7217 23:25:19.284753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7218 23:25:19.284835 ==
7219 23:25:19.284901 [Duty_Offset_Calibration]
7220 23:25:19.288083 B0:2 B1:1 CA:1
7221 23:25:19.288167
7222 23:25:19.291109 [DutyScan_Calibration_Flow] k_type=0
7223 23:25:19.300997
7224 23:25:19.301078 ==CLK 0==
7225 23:25:19.303966 Final CLK duty delay cell = 0
7226 23:25:19.307410 [0] MAX Duty = 5156%(X100), DQS PI = 22
7227 23:25:19.310761 [0] MIN Duty = 4876%(X100), DQS PI = 48
7228 23:25:19.313863 [0] AVG Duty = 5016%(X100)
7229 23:25:19.313948
7230 23:25:19.317455 CH0 CLK Duty spec in!! Max-Min= 280%
7231 23:25:19.320891 [DutyScan_Calibration_Flow] ====Done====
7232 23:25:19.320971
7233 23:25:19.324005 [DutyScan_Calibration_Flow] k_type=1
7234 23:25:19.340185
7235 23:25:19.340310 ==DQS 0 ==
7236 23:25:19.343219 Final DQS duty delay cell = -4
7237 23:25:19.346560 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7238 23:25:19.349834 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7239 23:25:19.353054 [-4] AVG Duty = 4891%(X100)
7240 23:25:19.353133
7241 23:25:19.353198 ==DQS 1 ==
7242 23:25:19.356513 Final DQS duty delay cell = 0
7243 23:25:19.359665 [0] MAX Duty = 5218%(X100), DQS PI = 22
7244 23:25:19.363312 [0] MIN Duty = 5062%(X100), DQS PI = 32
7245 23:25:19.366732 [0] AVG Duty = 5140%(X100)
7246 23:25:19.366814
7247 23:25:19.369837 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7248 23:25:19.369919
7249 23:25:19.373276 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7250 23:25:19.376676 [DutyScan_Calibration_Flow] ====Done====
7251 23:25:19.376754
7252 23:25:19.379932 [DutyScan_Calibration_Flow] k_type=3
7253 23:25:19.397446
7254 23:25:19.397531 ==DQM 0 ==
7255 23:25:19.400598 Final DQM duty delay cell = 0
7256 23:25:19.404063 [0] MAX Duty = 5218%(X100), DQS PI = 34
7257 23:25:19.407441 [0] MIN Duty = 4907%(X100), DQS PI = 56
7258 23:25:19.410883 [0] AVG Duty = 5062%(X100)
7259 23:25:19.410971
7260 23:25:19.411037 ==DQM 1 ==
7261 23:25:19.414021 Final DQM duty delay cell = 0
7262 23:25:19.417490 [0] MAX Duty = 5187%(X100), DQS PI = 2
7263 23:25:19.420368 [0] MIN Duty = 5062%(X100), DQS PI = 14
7264 23:25:19.423513 [0] AVG Duty = 5124%(X100)
7265 23:25:19.423589
7266 23:25:19.426900 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7267 23:25:19.427017
7268 23:25:19.430404 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7269 23:25:19.433865 [DutyScan_Calibration_Flow] ====Done====
7270 23:25:19.433953
7271 23:25:19.436698 [DutyScan_Calibration_Flow] k_type=2
7272 23:25:19.454691
7273 23:25:19.454776 ==DQ 0 ==
7274 23:25:19.457795 Final DQ duty delay cell = 0
7275 23:25:19.460996 [0] MAX Duty = 5062%(X100), DQS PI = 26
7276 23:25:19.464303 [0] MIN Duty = 4907%(X100), DQS PI = 0
7277 23:25:19.464380 [0] AVG Duty = 4984%(X100)
7278 23:25:19.467882
7279 23:25:19.467963 ==DQ 1 ==
7280 23:25:19.470937 Final DQ duty delay cell = 0
7281 23:25:19.474534 [0] MAX Duty = 5125%(X100), DQS PI = 6
7282 23:25:19.477674 [0] MIN Duty = 4907%(X100), DQS PI = 34
7283 23:25:19.477754 [0] AVG Duty = 5016%(X100)
7284 23:25:19.477820
7285 23:25:19.481288 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7286 23:25:19.481372
7287 23:25:19.484461 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7288 23:25:19.491358 [DutyScan_Calibration_Flow] ====Done====
7289 23:25:19.491442 ==
7290 23:25:19.494689 Dram Type= 6, Freq= 0, CH_1, rank 0
7291 23:25:19.497812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 23:25:19.497896 ==
7293 23:25:19.501132 [Duty_Offset_Calibration]
7294 23:25:19.501245 B0:1 B1:0 CA:0
7295 23:25:19.501341
7296 23:25:19.504538 [DutyScan_Calibration_Flow] k_type=0
7297 23:25:19.513995
7298 23:25:19.514083 ==CLK 0==
7299 23:25:19.517082 Final CLK duty delay cell = -4
7300 23:25:19.520569 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7301 23:25:19.523427 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7302 23:25:19.526933 [-4] AVG Duty = 4906%(X100)
7303 23:25:19.527054
7304 23:25:19.530182 CH1 CLK Duty spec in!! Max-Min= 125%
7305 23:25:19.533762 [DutyScan_Calibration_Flow] ====Done====
7306 23:25:19.533843
7307 23:25:19.536894 [DutyScan_Calibration_Flow] k_type=1
7308 23:25:19.553801
7309 23:25:19.553933 ==DQS 0 ==
7310 23:25:19.557037 Final DQS duty delay cell = 0
7311 23:25:19.560510 [0] MAX Duty = 5094%(X100), DQS PI = 16
7312 23:25:19.563987 [0] MIN Duty = 4844%(X100), DQS PI = 48
7313 23:25:19.567094 [0] AVG Duty = 4969%(X100)
7314 23:25:19.567210
7315 23:25:19.567318 ==DQS 1 ==
7316 23:25:19.570573 Final DQS duty delay cell = 0
7317 23:25:19.573782 [0] MAX Duty = 5249%(X100), DQS PI = 16
7318 23:25:19.576957 [0] MIN Duty = 4969%(X100), DQS PI = 6
7319 23:25:19.580174 [0] AVG Duty = 5109%(X100)
7320 23:25:19.580294
7321 23:25:19.583566 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7322 23:25:19.583687
7323 23:25:19.587235 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7324 23:25:19.590421 [DutyScan_Calibration_Flow] ====Done====
7325 23:25:19.590519
7326 23:25:19.593424 [DutyScan_Calibration_Flow] k_type=3
7327 23:25:19.610589
7328 23:25:19.610702 ==DQM 0 ==
7329 23:25:19.613781 Final DQM duty delay cell = 0
7330 23:25:19.617307 [0] MAX Duty = 5218%(X100), DQS PI = 18
7331 23:25:19.620434 [0] MIN Duty = 4969%(X100), DQS PI = 48
7332 23:25:19.623912 [0] AVG Duty = 5093%(X100)
7333 23:25:19.624014
7334 23:25:19.624116 ==DQM 1 ==
7335 23:25:19.627199 Final DQM duty delay cell = 0
7336 23:25:19.630636 [0] MAX Duty = 5093%(X100), DQS PI = 40
7337 23:25:19.633998 [0] MIN Duty = 4907%(X100), DQS PI = 34
7338 23:25:19.637298 [0] AVG Duty = 5000%(X100)
7339 23:25:19.637376
7340 23:25:19.640657 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7341 23:25:19.640745
7342 23:25:19.644139 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7343 23:25:19.647325 [DutyScan_Calibration_Flow] ====Done====
7344 23:25:19.647402
7345 23:25:19.650348 [DutyScan_Calibration_Flow] k_type=2
7346 23:25:19.666861
7347 23:25:19.666944 ==DQ 0 ==
7348 23:25:19.669983 Final DQ duty delay cell = -4
7349 23:25:19.673437 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7350 23:25:19.676568 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7351 23:25:19.680109 [-4] AVG Duty = 4968%(X100)
7352 23:25:19.680227
7353 23:25:19.680325 ==DQ 1 ==
7354 23:25:19.683214 Final DQ duty delay cell = 0
7355 23:25:19.686803 [0] MAX Duty = 5093%(X100), DQS PI = 16
7356 23:25:19.690221 [0] MIN Duty = 4938%(X100), DQS PI = 8
7357 23:25:19.693584 [0] AVG Duty = 5015%(X100)
7358 23:25:19.693667
7359 23:25:19.696707 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7360 23:25:19.696791
7361 23:25:19.699937 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7362 23:25:19.703431 [DutyScan_Calibration_Flow] ====Done====
7363 23:25:19.706521 nWR fixed to 30
7364 23:25:19.706636 [ModeRegInit_LP4] CH0 RK0
7365 23:25:19.709943 [ModeRegInit_LP4] CH0 RK1
7366 23:25:19.713113 [ModeRegInit_LP4] CH1 RK0
7367 23:25:19.716574 [ModeRegInit_LP4] CH1 RK1
7368 23:25:19.716676 match AC timing 5
7369 23:25:19.723429 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7370 23:25:19.726405 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7371 23:25:19.730112 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7372 23:25:19.736821 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7373 23:25:19.740139 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7374 23:25:19.740254 [MiockJmeterHQA]
7375 23:25:19.740370
7376 23:25:19.743152 [DramcMiockJmeter] u1RxGatingPI = 0
7377 23:25:19.746447 0 : 4253, 4026
7378 23:25:19.746525 4 : 4253, 4026
7379 23:25:19.749894 8 : 4252, 4027
7380 23:25:19.750043 12 : 4257, 4029
7381 23:25:19.750135 16 : 4252, 4027
7382 23:25:19.752992 20 : 4363, 4137
7383 23:25:19.753079 24 : 4252, 4027
7384 23:25:19.756586 28 : 4254, 4029
7385 23:25:19.756668 32 : 4252, 4027
7386 23:25:19.759941 36 : 4252, 4027
7387 23:25:19.760019 40 : 4250, 4027
7388 23:25:19.763046 44 : 4253, 4027
7389 23:25:19.763123 48 : 4361, 4137
7390 23:25:19.763186 52 : 4360, 4138
7391 23:25:19.766308 56 : 4248, 4024
7392 23:25:19.766381 60 : 4250, 4026
7393 23:25:19.769676 64 : 4250, 4027
7394 23:25:19.769751 68 : 4250, 4026
7395 23:25:19.773255 72 : 4361, 4137
7396 23:25:19.773346 76 : 4250, 4027
7397 23:25:19.776230 80 : 4361, 4138
7398 23:25:19.776361 84 : 4250, 4027
7399 23:25:19.776426 88 : 4250, 107
7400 23:25:19.779754 92 : 4361, 0
7401 23:25:19.779859 96 : 4252, 0
7402 23:25:19.782944 100 : 4252, 0
7403 23:25:19.783046 104 : 4250, 0
7404 23:25:19.783154 108 : 4250, 0
7405 23:25:19.786348 112 : 4250, 0
7406 23:25:19.786478 116 : 4363, 0
7407 23:25:19.786616 120 : 4252, 0
7408 23:25:19.789339 124 : 4250, 0
7409 23:25:19.789426 128 : 4363, 0
7410 23:25:19.792803 132 : 4250, 0
7411 23:25:19.792878 136 : 4250, 0
7412 23:25:19.792964 140 : 4250, 0
7413 23:25:19.795878 144 : 4251, 0
7414 23:25:19.795977 148 : 4360, 0
7415 23:25:19.799249 152 : 4361, 0
7416 23:25:19.799348 156 : 4363, 0
7417 23:25:19.799411 160 : 4250, 0
7418 23:25:19.802900 164 : 4361, 0
7419 23:25:19.803017 168 : 4361, 0
7420 23:25:19.806229 172 : 4255, 0
7421 23:25:19.806305 176 : 4250, 0
7422 23:25:19.806369 180 : 4363, 0
7423 23:25:19.809235 184 : 4250, 0
7424 23:25:19.809318 188 : 4250, 0
7425 23:25:19.809401 192 : 4250, 0
7426 23:25:19.812641 196 : 4250, 0
7427 23:25:19.812745 200 : 4360, 0
7428 23:25:19.816187 204 : 4361, 1248
7429 23:25:19.816306 208 : 4361, 4093
7430 23:25:19.819301 212 : 4250, 4026
7431 23:25:19.819388 216 : 4360, 4138
7432 23:25:19.822674 220 : 4252, 4029
7433 23:25:19.822753 224 : 4250, 4026
7434 23:25:19.826042 228 : 4250, 4027
7435 23:25:19.826119 232 : 4252, 4029
7436 23:25:19.826193 236 : 4252, 4029
7437 23:25:19.829250 240 : 4361, 4138
7438 23:25:19.829361 244 : 4250, 4027
7439 23:25:19.832638 248 : 4250, 4027
7440 23:25:19.832729 252 : 4250, 4026
7441 23:25:19.835946 256 : 4363, 4140
7442 23:25:19.836062 260 : 4361, 4137
7443 23:25:19.839380 264 : 4247, 4024
7444 23:25:19.839484 268 : 4363, 4140
7445 23:25:19.842629 272 : 4252, 4029
7446 23:25:19.842732 276 : 4250, 4026
7447 23:25:19.846159 280 : 4250, 4027
7448 23:25:19.846237 284 : 4252, 4029
7449 23:25:19.846320 288 : 4252, 4029
7450 23:25:19.849340 292 : 4363, 4140
7451 23:25:19.849417 296 : 4250, 4027
7452 23:25:19.852858 300 : 4252, 4029
7453 23:25:19.852945 304 : 4250, 4026
7454 23:25:19.855796 308 : 4363, 4004
7455 23:25:19.855874 312 : 4361, 2269
7456 23:25:19.859317 316 : 4249, 17
7457 23:25:19.859428
7458 23:25:19.859522 MIOCK jitter meter ch=0
7459 23:25:19.862640
7460 23:25:19.862757 1T = (316-88) = 228 dly cells
7461 23:25:19.869362 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7462 23:25:19.869442 ==
7463 23:25:19.872505 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 23:25:19.875842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7465 23:25:19.875921 ==
7466 23:25:19.882360 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7467 23:25:19.885768 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7468 23:25:19.892202 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7469 23:25:19.895821 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7470 23:25:19.905742 [CA 0] Center 42 (12~73) winsize 62
7471 23:25:19.909140 [CA 1] Center 42 (12~73) winsize 62
7472 23:25:19.912676 [CA 2] Center 37 (8~67) winsize 60
7473 23:25:19.915935 [CA 3] Center 37 (7~67) winsize 61
7474 23:25:19.919363 [CA 4] Center 36 (6~66) winsize 61
7475 23:25:19.922576 [CA 5] Center 35 (6~64) winsize 59
7476 23:25:19.922653
7477 23:25:19.925990 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7478 23:25:19.926081
7479 23:25:19.929219 [CATrainingPosCal] consider 1 rank data
7480 23:25:19.932702 u2DelayCellTimex100 = 285/100 ps
7481 23:25:19.936017 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7482 23:25:19.942532 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7483 23:25:19.945869 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7484 23:25:19.949324 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7485 23:25:19.952762 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7486 23:25:19.955836 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7487 23:25:19.955919
7488 23:25:19.959137 CA PerBit enable=1, Macro0, CA PI delay=35
7489 23:25:19.959247
7490 23:25:19.962571 [CBTSetCACLKResult] CA Dly = 35
7491 23:25:19.962654 CS Dly: 9 (0~40)
7492 23:25:19.969174 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7493 23:25:19.972240 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7494 23:25:19.972334 ==
7495 23:25:19.976101 Dram Type= 6, Freq= 0, CH_0, rank 1
7496 23:25:19.979032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7497 23:25:19.979114 ==
7498 23:25:19.985736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7499 23:25:19.989123 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7500 23:25:19.995413 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7501 23:25:19.998936 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7502 23:25:20.009044 [CA 0] Center 42 (12~73) winsize 62
7503 23:25:20.012536 [CA 1] Center 42 (12~73) winsize 62
7504 23:25:20.016006 [CA 2] Center 38 (8~68) winsize 61
7505 23:25:20.018936 [CA 3] Center 37 (7~67) winsize 61
7506 23:25:20.022295 [CA 4] Center 35 (6~65) winsize 60
7507 23:25:20.025556 [CA 5] Center 35 (5~65) winsize 61
7508 23:25:20.025639
7509 23:25:20.029124 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7510 23:25:20.029207
7511 23:25:20.032408 [CATrainingPosCal] consider 2 rank data
7512 23:25:20.035540 u2DelayCellTimex100 = 285/100 ps
7513 23:25:20.038983 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7514 23:25:20.045922 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7515 23:25:20.049048 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7516 23:25:20.052586 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7517 23:25:20.055837 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7518 23:25:20.059169 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7519 23:25:20.059276
7520 23:25:20.062459 CA PerBit enable=1, Macro0, CA PI delay=35
7521 23:25:20.062565
7522 23:25:20.065858 [CBTSetCACLKResult] CA Dly = 35
7523 23:25:20.065971 CS Dly: 10 (0~42)
7524 23:25:20.072472 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7525 23:25:20.075400 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7526 23:25:20.075518
7527 23:25:20.078943 ----->DramcWriteLeveling(PI) begin...
7528 23:25:20.079023 ==
7529 23:25:20.082417 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 23:25:20.085452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 23:25:20.089063 ==
7532 23:25:20.089165 Write leveling (Byte 0): 36 => 36
7533 23:25:20.092113 Write leveling (Byte 1): 28 => 28
7534 23:25:20.095677 DramcWriteLeveling(PI) end<-----
7535 23:25:20.095760
7536 23:25:20.095825 ==
7537 23:25:20.099086 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 23:25:20.105687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 23:25:20.105776 ==
7540 23:25:20.105841 [Gating] SW mode calibration
7541 23:25:20.115330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7542 23:25:20.118649 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7543 23:25:20.125208 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7544 23:25:20.128747 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7545 23:25:20.132250 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7546 23:25:20.135471 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
7547 23:25:20.141926 1 4 16 | B1->B0 | 2323 3838 | 0 1 | (0 0) (1 1)
7548 23:25:20.145388 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 23:25:20.151885 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7550 23:25:20.154906 1 4 28 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7551 23:25:20.158332 1 5 0 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
7552 23:25:20.161589 1 5 4 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7553 23:25:20.168388 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7554 23:25:20.171842 1 5 12 | B1->B0 | 3434 2827 | 1 1 | (1 1) (1 0)
7555 23:25:20.175230 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7556 23:25:20.181944 1 5 20 | B1->B0 | 2323 2625 | 0 1 | (1 0) (0 0)
7557 23:25:20.185010 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7558 23:25:20.188339 1 5 28 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7559 23:25:20.194797 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7560 23:25:20.198211 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7561 23:25:20.201710 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7562 23:25:20.207980 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7563 23:25:20.211328 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7564 23:25:20.214867 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7565 23:25:20.221415 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 23:25:20.224817 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 23:25:20.228040 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 23:25:20.234488 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 23:25:20.238062 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 23:25:20.241493 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 23:25:20.248030 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7572 23:25:20.251232 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7573 23:25:20.254509 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 23:25:20.260962 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 23:25:20.264209 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 23:25:20.267763 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 23:25:20.274563 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 23:25:20.277735 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 23:25:20.280887 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 23:25:20.287466 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 23:25:20.291147 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 23:25:20.294459 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 23:25:20.300918 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 23:25:20.304386 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 23:25:20.307384 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7586 23:25:20.314215 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7587 23:25:20.317638 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7588 23:25:20.320708 Total UI for P1: 0, mck2ui 16
7589 23:25:20.324041 best dqsien dly found for B0: ( 1, 9, 10)
7590 23:25:20.327465 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7591 23:25:20.330833 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 23:25:20.333914 Total UI for P1: 0, mck2ui 16
7593 23:25:20.337530 best dqsien dly found for B1: ( 1, 9, 18)
7594 23:25:20.343996 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7595 23:25:20.347414 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7596 23:25:20.347494
7597 23:25:20.350450 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7598 23:25:20.353698 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7599 23:25:20.357299 [Gating] SW calibration Done
7600 23:25:20.357414 ==
7601 23:25:20.360580 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 23:25:20.363756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 23:25:20.363863 ==
7604 23:25:20.367176 RX Vref Scan: 0
7605 23:25:20.367284
7606 23:25:20.367376 RX Vref 0 -> 0, step: 1
7607 23:25:20.367442
7608 23:25:20.370404 RX Delay 0 -> 252, step: 8
7609 23:25:20.373852 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7610 23:25:20.377079 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7611 23:25:20.383861 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7612 23:25:20.387048 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7613 23:25:20.390372 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7614 23:25:20.393599 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7615 23:25:20.397215 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7616 23:25:20.403673 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7617 23:25:20.407262 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7618 23:25:20.410305 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7619 23:25:20.413644 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7620 23:25:20.417444 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7621 23:25:20.423816 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7622 23:25:20.427285 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7623 23:25:20.430664 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7624 23:25:20.433972 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7625 23:25:20.434083 ==
7626 23:25:20.436974 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 23:25:20.443919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 23:25:20.444005 ==
7629 23:25:20.444082 DQS Delay:
7630 23:25:20.446962 DQS0 = 0, DQS1 = 0
7631 23:25:20.447045 DQM Delay:
7632 23:25:20.447110 DQM0 = 137, DQM1 = 129
7633 23:25:20.450503 DQ Delay:
7634 23:25:20.453642 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7635 23:25:20.457165 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7636 23:25:20.460241 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7637 23:25:20.463615 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7638 23:25:20.463731
7639 23:25:20.463826
7640 23:25:20.463924 ==
7641 23:25:20.467049 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 23:25:20.470411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 23:25:20.473428 ==
7644 23:25:20.473512
7645 23:25:20.473588
7646 23:25:20.473654 TX Vref Scan disable
7647 23:25:20.477017 == TX Byte 0 ==
7648 23:25:20.480470 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7649 23:25:20.483622 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7650 23:25:20.486942 == TX Byte 1 ==
7651 23:25:20.490127 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7652 23:25:20.493530 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7653 23:25:20.493643 ==
7654 23:25:20.496934 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 23:25:20.503390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 23:25:20.503502 ==
7657 23:25:20.515984
7658 23:25:20.519586 TX Vref early break, caculate TX vref
7659 23:25:20.522588 TX Vref=16, minBit 0, minWin=23, winSum=377
7660 23:25:20.525987 TX Vref=18, minBit 1, minWin=23, winSum=383
7661 23:25:20.529279 TX Vref=20, minBit 0, minWin=24, winSum=396
7662 23:25:20.532676 TX Vref=22, minBit 3, minWin=24, winSum=408
7663 23:25:20.535995 TX Vref=24, minBit 0, minWin=25, winSum=415
7664 23:25:20.542694 TX Vref=26, minBit 0, minWin=25, winSum=422
7665 23:25:20.546069 TX Vref=28, minBit 2, minWin=25, winSum=421
7666 23:25:20.549174 TX Vref=30, minBit 2, minWin=24, winSum=416
7667 23:25:20.552649 TX Vref=32, minBit 6, minWin=23, winSum=401
7668 23:25:20.556224 TX Vref=34, minBit 1, minWin=23, winSum=393
7669 23:25:20.562639 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
7670 23:25:20.562724
7671 23:25:20.566048 Final TX Range 0 Vref 26
7672 23:25:20.566125
7673 23:25:20.566193 ==
7674 23:25:20.569454 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 23:25:20.572822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 23:25:20.572901 ==
7677 23:25:20.572970
7678 23:25:20.573030
7679 23:25:20.575767 TX Vref Scan disable
7680 23:25:20.582612 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7681 23:25:20.582720 == TX Byte 0 ==
7682 23:25:20.585567 u2DelayCellOfst[0]=10 cells (3 PI)
7683 23:25:20.589157 u2DelayCellOfst[1]=13 cells (4 PI)
7684 23:25:20.592445 u2DelayCellOfst[2]=10 cells (3 PI)
7685 23:25:20.595874 u2DelayCellOfst[3]=10 cells (3 PI)
7686 23:25:20.598895 u2DelayCellOfst[4]=6 cells (2 PI)
7687 23:25:20.602378 u2DelayCellOfst[5]=0 cells (0 PI)
7688 23:25:20.605479 u2DelayCellOfst[6]=13 cells (4 PI)
7689 23:25:20.608919 u2DelayCellOfst[7]=13 cells (4 PI)
7690 23:25:20.612249 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7691 23:25:20.615622 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7692 23:25:20.619140 == TX Byte 1 ==
7693 23:25:20.619222 u2DelayCellOfst[8]=3 cells (1 PI)
7694 23:25:20.622622 u2DelayCellOfst[9]=0 cells (0 PI)
7695 23:25:20.625617 u2DelayCellOfst[10]=6 cells (2 PI)
7696 23:25:20.628971 u2DelayCellOfst[11]=3 cells (1 PI)
7697 23:25:20.632579 u2DelayCellOfst[12]=10 cells (3 PI)
7698 23:25:20.635695 u2DelayCellOfst[13]=13 cells (4 PI)
7699 23:25:20.639213 u2DelayCellOfst[14]=13 cells (4 PI)
7700 23:25:20.642409 u2DelayCellOfst[15]=10 cells (3 PI)
7701 23:25:20.645541 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7702 23:25:20.652201 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7703 23:25:20.652316 DramC Write-DBI on
7704 23:25:20.652387 ==
7705 23:25:20.655756 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 23:25:20.658991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 23:25:20.662327 ==
7708 23:25:20.662407
7709 23:25:20.662474
7710 23:25:20.662536 TX Vref Scan disable
7711 23:25:20.665906 == TX Byte 0 ==
7712 23:25:20.668964 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7713 23:25:20.672322 == TX Byte 1 ==
7714 23:25:20.675727 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7715 23:25:20.678739 DramC Write-DBI off
7716 23:25:20.678814
7717 23:25:20.678876 [DATLAT]
7718 23:25:20.678947 Freq=1600, CH0 RK0
7719 23:25:20.679026
7720 23:25:20.682263 DATLAT Default: 0xf
7721 23:25:20.682335 0, 0xFFFF, sum = 0
7722 23:25:20.685359 1, 0xFFFF, sum = 0
7723 23:25:20.688804 2, 0xFFFF, sum = 0
7724 23:25:20.688882 3, 0xFFFF, sum = 0
7725 23:25:20.692168 4, 0xFFFF, sum = 0
7726 23:25:20.692275 5, 0xFFFF, sum = 0
7727 23:25:20.695390 6, 0xFFFF, sum = 0
7728 23:25:20.695477 7, 0xFFFF, sum = 0
7729 23:25:20.698801 8, 0xFFFF, sum = 0
7730 23:25:20.698887 9, 0xFFFF, sum = 0
7731 23:25:20.701943 10, 0xFFFF, sum = 0
7732 23:25:20.702021 11, 0xFFFF, sum = 0
7733 23:25:20.705339 12, 0xFFFF, sum = 0
7734 23:25:20.705420 13, 0xFFFF, sum = 0
7735 23:25:20.708936 14, 0x0, sum = 1
7736 23:25:20.709015 15, 0x0, sum = 2
7737 23:25:20.712004 16, 0x0, sum = 3
7738 23:25:20.712081 17, 0x0, sum = 4
7739 23:25:20.715493 best_step = 15
7740 23:25:20.715573
7741 23:25:20.715635 ==
7742 23:25:20.718852 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 23:25:20.721965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 23:25:20.722076 ==
7745 23:25:20.725517 RX Vref Scan: 1
7746 23:25:20.725599
7747 23:25:20.725678 Set Vref Range= 24 -> 127
7748 23:25:20.725743
7749 23:25:20.728561 RX Vref 24 -> 127, step: 1
7750 23:25:20.728646
7751 23:25:20.732132 RX Delay 19 -> 252, step: 4
7752 23:25:20.732250
7753 23:25:20.735425 Set Vref, RX VrefLevel [Byte0]: 24
7754 23:25:20.738531 [Byte1]: 24
7755 23:25:20.738633
7756 23:25:20.741973 Set Vref, RX VrefLevel [Byte0]: 25
7757 23:25:20.745450 [Byte1]: 25
7758 23:25:20.745534
7759 23:25:20.748479 Set Vref, RX VrefLevel [Byte0]: 26
7760 23:25:20.751914 [Byte1]: 26
7761 23:25:20.755951
7762 23:25:20.756059 Set Vref, RX VrefLevel [Byte0]: 27
7763 23:25:20.759094 [Byte1]: 27
7764 23:25:20.763631
7765 23:25:20.763734 Set Vref, RX VrefLevel [Byte0]: 28
7766 23:25:20.766628 [Byte1]: 28
7767 23:25:20.771002
7768 23:25:20.771083 Set Vref, RX VrefLevel [Byte0]: 29
7769 23:25:20.774414 [Byte1]: 29
7770 23:25:20.778963
7771 23:25:20.779094 Set Vref, RX VrefLevel [Byte0]: 30
7772 23:25:20.782011 [Byte1]: 30
7773 23:25:20.786215
7774 23:25:20.786337 Set Vref, RX VrefLevel [Byte0]: 31
7775 23:25:20.789575 [Byte1]: 31
7776 23:25:20.794012
7777 23:25:20.794130 Set Vref, RX VrefLevel [Byte0]: 32
7778 23:25:20.796895 [Byte1]: 32
7779 23:25:20.801494
7780 23:25:20.801618 Set Vref, RX VrefLevel [Byte0]: 33
7781 23:25:20.804475 [Byte1]: 33
7782 23:25:20.808798
7783 23:25:20.808927 Set Vref, RX VrefLevel [Byte0]: 34
7784 23:25:20.812210 [Byte1]: 34
7785 23:25:20.816625
7786 23:25:20.816751 Set Vref, RX VrefLevel [Byte0]: 35
7787 23:25:20.819991 [Byte1]: 35
7788 23:25:20.824216
7789 23:25:20.824345 Set Vref, RX VrefLevel [Byte0]: 36
7790 23:25:20.827347 [Byte1]: 36
7791 23:25:20.831714
7792 23:25:20.831800 Set Vref, RX VrefLevel [Byte0]: 37
7793 23:25:20.835102 [Byte1]: 37
7794 23:25:20.839193
7795 23:25:20.839280 Set Vref, RX VrefLevel [Byte0]: 38
7796 23:25:20.842702 [Byte1]: 38
7797 23:25:20.847026
7798 23:25:20.847109 Set Vref, RX VrefLevel [Byte0]: 39
7799 23:25:20.850082 [Byte1]: 39
7800 23:25:20.854455
7801 23:25:20.854534 Set Vref, RX VrefLevel [Byte0]: 40
7802 23:25:20.857946 [Byte1]: 40
7803 23:25:20.862073
7804 23:25:20.862155 Set Vref, RX VrefLevel [Byte0]: 41
7805 23:25:20.865192 [Byte1]: 41
7806 23:25:20.869538
7807 23:25:20.869643 Set Vref, RX VrefLevel [Byte0]: 42
7808 23:25:20.872981 [Byte1]: 42
7809 23:25:20.877356
7810 23:25:20.877441 Set Vref, RX VrefLevel [Byte0]: 43
7811 23:25:20.880389 [Byte1]: 43
7812 23:25:20.884644
7813 23:25:20.884727 Set Vref, RX VrefLevel [Byte0]: 44
7814 23:25:20.888056 [Byte1]: 44
7815 23:25:20.892279
7816 23:25:20.892372 Set Vref, RX VrefLevel [Byte0]: 45
7817 23:25:20.895788 [Byte1]: 45
7818 23:25:20.899893
7819 23:25:20.900002 Set Vref, RX VrefLevel [Byte0]: 46
7820 23:25:20.902972 [Byte1]: 46
7821 23:25:20.907239
7822 23:25:20.907322 Set Vref, RX VrefLevel [Byte0]: 47
7823 23:25:20.910739 [Byte1]: 47
7824 23:25:20.914900
7825 23:25:20.915010 Set Vref, RX VrefLevel [Byte0]: 48
7826 23:25:20.918321 [Byte1]: 48
7827 23:25:20.922563
7828 23:25:20.922673 Set Vref, RX VrefLevel [Byte0]: 49
7829 23:25:20.925674 [Byte1]: 49
7830 23:25:20.930135
7831 23:25:20.930218 Set Vref, RX VrefLevel [Byte0]: 50
7832 23:25:20.933482 [Byte1]: 50
7833 23:25:20.937871
7834 23:25:20.937979 Set Vref, RX VrefLevel [Byte0]: 51
7835 23:25:20.940891 [Byte1]: 51
7836 23:25:20.945319
7837 23:25:20.945427 Set Vref, RX VrefLevel [Byte0]: 52
7838 23:25:20.948589 [Byte1]: 52
7839 23:25:20.952856
7840 23:25:20.952939 Set Vref, RX VrefLevel [Byte0]: 53
7841 23:25:20.956229 [Byte1]: 53
7842 23:25:20.960540
7843 23:25:20.960623 Set Vref, RX VrefLevel [Byte0]: 54
7844 23:25:20.963746 [Byte1]: 54
7845 23:25:20.968022
7846 23:25:20.968108 Set Vref, RX VrefLevel [Byte0]: 55
7847 23:25:20.971175 [Byte1]: 55
7848 23:25:20.975416
7849 23:25:20.975499 Set Vref, RX VrefLevel [Byte0]: 56
7850 23:25:20.978914 [Byte1]: 56
7851 23:25:20.983121
7852 23:25:20.983205 Set Vref, RX VrefLevel [Byte0]: 57
7853 23:25:20.986431 [Byte1]: 57
7854 23:25:20.990839
7855 23:25:20.990952 Set Vref, RX VrefLevel [Byte0]: 58
7856 23:25:20.994191 [Byte1]: 58
7857 23:25:20.998361
7858 23:25:20.998448 Set Vref, RX VrefLevel [Byte0]: 59
7859 23:25:21.001466 [Byte1]: 59
7860 23:25:21.005796
7861 23:25:21.005882 Set Vref, RX VrefLevel [Byte0]: 60
7862 23:25:21.008955 [Byte1]: 60
7863 23:25:21.013196
7864 23:25:21.013281 Set Vref, RX VrefLevel [Byte0]: 61
7865 23:25:21.016674 [Byte1]: 61
7866 23:25:21.021014
7867 23:25:21.021097 Set Vref, RX VrefLevel [Byte0]: 62
7868 23:25:21.024396 [Byte1]: 62
7869 23:25:21.028514
7870 23:25:21.028623 Set Vref, RX VrefLevel [Byte0]: 63
7871 23:25:21.031694 [Byte1]: 63
7872 23:25:21.036042
7873 23:25:21.036155 Set Vref, RX VrefLevel [Byte0]: 64
7874 23:25:21.039305 [Byte1]: 64
7875 23:25:21.043595
7876 23:25:21.043678 Set Vref, RX VrefLevel [Byte0]: 65
7877 23:25:21.046892 [Byte1]: 65
7878 23:25:21.051435
7879 23:25:21.051518 Set Vref, RX VrefLevel [Byte0]: 66
7880 23:25:21.054499 [Byte1]: 66
7881 23:25:21.058985
7882 23:25:21.059072 Set Vref, RX VrefLevel [Byte0]: 67
7883 23:25:21.061973 [Byte1]: 67
7884 23:25:21.066241
7885 23:25:21.066321 Set Vref, RX VrefLevel [Byte0]: 68
7886 23:25:21.069568 [Byte1]: 68
7887 23:25:21.074092
7888 23:25:21.074201 Set Vref, RX VrefLevel [Byte0]: 69
7889 23:25:21.077203 [Byte1]: 69
7890 23:25:21.081365
7891 23:25:21.081452 Set Vref, RX VrefLevel [Byte0]: 70
7892 23:25:21.084890 [Byte1]: 70
7893 23:25:21.089228
7894 23:25:21.089309 Set Vref, RX VrefLevel [Byte0]: 71
7895 23:25:21.092298 [Byte1]: 71
7896 23:25:21.096542
7897 23:25:21.096624 Set Vref, RX VrefLevel [Byte0]: 72
7898 23:25:21.100048 [Byte1]: 72
7899 23:25:21.104199
7900 23:25:21.104318 Set Vref, RX VrefLevel [Byte0]: 73
7901 23:25:21.107687 [Byte1]: 73
7902 23:25:21.111961
7903 23:25:21.112042 Set Vref, RX VrefLevel [Byte0]: 74
7904 23:25:21.115164 [Byte1]: 74
7905 23:25:21.119278
7906 23:25:21.119357 Set Vref, RX VrefLevel [Byte0]: 75
7907 23:25:21.122571 [Byte1]: 75
7908 23:25:21.127140
7909 23:25:21.127250 Set Vref, RX VrefLevel [Byte0]: 76
7910 23:25:21.130272 [Byte1]: 76
7911 23:25:21.134516
7912 23:25:21.134595 Final RX Vref Byte 0 = 61 to rank0
7913 23:25:21.138409 Final RX Vref Byte 1 = 59 to rank0
7914 23:25:21.141067 Final RX Vref Byte 0 = 61 to rank1
7915 23:25:21.144450 Final RX Vref Byte 1 = 59 to rank1==
7916 23:25:21.148005 Dram Type= 6, Freq= 0, CH_0, rank 0
7917 23:25:21.154389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7918 23:25:21.154473 ==
7919 23:25:21.154539 DQS Delay:
7920 23:25:21.154601 DQS0 = 0, DQS1 = 0
7921 23:25:21.157622 DQM Delay:
7922 23:25:21.157705 DQM0 = 134, DQM1 = 127
7923 23:25:21.160896 DQ Delay:
7924 23:25:21.164248 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7925 23:25:21.167805 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7926 23:25:21.170909 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7927 23:25:21.174151 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =134
7928 23:25:21.174259
7929 23:25:21.174352
7930 23:25:21.174442
7931 23:25:21.177622 [DramC_TX_OE_Calibration] TA2
7932 23:25:21.180902 Original DQ_B0 (3 6) =30, OEN = 27
7933 23:25:21.184466 Original DQ_B1 (3 6) =30, OEN = 27
7934 23:25:21.187659 24, 0x0, End_B0=24 End_B1=24
7935 23:25:21.187786 25, 0x0, End_B0=25 End_B1=25
7936 23:25:21.190785 26, 0x0, End_B0=26 End_B1=26
7937 23:25:21.194353 27, 0x0, End_B0=27 End_B1=27
7938 23:25:21.197457 28, 0x0, End_B0=28 End_B1=28
7939 23:25:21.200901 29, 0x0, End_B0=29 End_B1=29
7940 23:25:21.201027 30, 0x0, End_B0=30 End_B1=30
7941 23:25:21.204438 31, 0x4141, End_B0=30 End_B1=30
7942 23:25:21.207798 Byte0 end_step=30 best_step=27
7943 23:25:21.210917 Byte1 end_step=30 best_step=27
7944 23:25:21.214249 Byte0 TX OE(2T, 0.5T) = (3, 3)
7945 23:25:21.217750 Byte1 TX OE(2T, 0.5T) = (3, 3)
7946 23:25:21.217882
7947 23:25:21.217998
7948 23:25:21.224303 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7949 23:25:21.227665 CH0 RK0: MR19=303, MR18=2723
7950 23:25:21.234150 CH0_RK0: MR19=0x303, MR18=0x2723, DQSOSC=390, MR23=63, INC=24, DEC=16
7951 23:25:21.234232
7952 23:25:21.237649 ----->DramcWriteLeveling(PI) begin...
7953 23:25:21.237776 ==
7954 23:25:21.240638 Dram Type= 6, Freq= 0, CH_0, rank 1
7955 23:25:21.243978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7956 23:25:21.244107 ==
7957 23:25:21.247425 Write leveling (Byte 0): 35 => 35
7958 23:25:21.250570 Write leveling (Byte 1): 28 => 28
7959 23:25:21.254152 DramcWriteLeveling(PI) end<-----
7960 23:25:21.254272
7961 23:25:21.254388 ==
7962 23:25:21.257173 Dram Type= 6, Freq= 0, CH_0, rank 1
7963 23:25:21.260626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7964 23:25:21.260706 ==
7965 23:25:21.264004 [Gating] SW mode calibration
7966 23:25:21.270327 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7967 23:25:21.277101 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7968 23:25:21.280353 1 4 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7969 23:25:21.287015 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 23:25:21.290550 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 23:25:21.293593 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
7972 23:25:21.296792 1 4 16 | B1->B0 | 2d2d 3535 | 1 0 | (0 0) (1 1)
7973 23:25:21.303534 1 4 20 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7974 23:25:21.306849 1 4 24 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (0 0)
7975 23:25:21.310317 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7976 23:25:21.317079 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7977 23:25:21.320313 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7978 23:25:21.323603 1 5 8 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7979 23:25:21.330275 1 5 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
7980 23:25:21.333313 1 5 16 | B1->B0 | 2f2f 2828 | 0 0 | (0 1) (0 0)
7981 23:25:21.337162 1 5 20 | B1->B0 | 2424 2424 | 0 0 | (0 0) (1 1)
7982 23:25:21.343404 1 5 24 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (1 1)
7983 23:25:21.346870 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (1 1)
7984 23:25:21.350130 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7985 23:25:21.356737 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7986 23:25:21.360222 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7987 23:25:21.363263 1 6 12 | B1->B0 | 2323 3b3a | 0 1 | (0 0) (0 0)
7988 23:25:21.370144 1 6 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7989 23:25:21.373206 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7990 23:25:21.376522 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 23:25:21.383495 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 23:25:21.386591 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 23:25:21.390157 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 23:25:21.396524 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 23:25:21.399944 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7996 23:25:21.403298 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7997 23:25:21.409984 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 23:25:21.413456 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 23:25:21.416636 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 23:25:21.423272 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 23:25:21.426377 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 23:25:21.429911 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 23:25:21.436542 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 23:25:21.439915 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 23:25:21.443297 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 23:25:21.446647 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 23:25:21.453250 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 23:25:21.456703 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 23:25:21.459814 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 23:25:21.466385 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8011 23:25:21.469839 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8012 23:25:21.473234 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8013 23:25:21.479861 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 23:25:21.482916 Total UI for P1: 0, mck2ui 16
8015 23:25:21.486444 best dqsien dly found for B0: ( 1, 9, 12)
8016 23:25:21.486570 Total UI for P1: 0, mck2ui 16
8017 23:25:21.493085 best dqsien dly found for B1: ( 1, 9, 14)
8018 23:25:21.496244 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8019 23:25:21.499668 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8020 23:25:21.499788
8021 23:25:21.503146 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8022 23:25:21.506530 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8023 23:25:21.509855 [Gating] SW calibration Done
8024 23:25:21.509985 ==
8025 23:25:21.513192 Dram Type= 6, Freq= 0, CH_0, rank 1
8026 23:25:21.516195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8027 23:25:21.516322 ==
8028 23:25:21.519899 RX Vref Scan: 0
8029 23:25:21.520024
8030 23:25:21.520137 RX Vref 0 -> 0, step: 1
8031 23:25:21.520256
8032 23:25:21.522824 RX Delay 0 -> 252, step: 8
8033 23:25:21.526363 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8034 23:25:21.533031 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8035 23:25:21.536233 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8036 23:25:21.539514 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8037 23:25:21.542933 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8038 23:25:21.546263 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8039 23:25:21.553111 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8040 23:25:21.556057 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8041 23:25:21.559555 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8042 23:25:21.562899 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8043 23:25:21.566258 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8044 23:25:21.572987 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8045 23:25:21.576114 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8046 23:25:21.579365 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8047 23:25:21.583001 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8048 23:25:21.586305 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8049 23:25:21.589506 ==
8050 23:25:21.592594 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 23:25:21.596396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 23:25:21.596477 ==
8053 23:25:21.596546 DQS Delay:
8054 23:25:21.599373 DQS0 = 0, DQS1 = 0
8055 23:25:21.599472 DQM Delay:
8056 23:25:21.602850 DQM0 = 137, DQM1 = 128
8057 23:25:21.602924 DQ Delay:
8058 23:25:21.606331 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
8059 23:25:21.609376 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8060 23:25:21.612900 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8061 23:25:21.615966 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8062 23:25:21.616087
8063 23:25:21.616201
8064 23:25:21.616326 ==
8065 23:25:21.619573 Dram Type= 6, Freq= 0, CH_0, rank 1
8066 23:25:21.626327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8067 23:25:21.626410 ==
8068 23:25:21.626476
8069 23:25:21.626537
8070 23:25:21.626595 TX Vref Scan disable
8071 23:25:21.629448 == TX Byte 0 ==
8072 23:25:21.633052 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8073 23:25:21.639524 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8074 23:25:21.639607 == TX Byte 1 ==
8075 23:25:21.642981 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8076 23:25:21.649662 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8077 23:25:21.649746 ==
8078 23:25:21.652969 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 23:25:21.655942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 23:25:21.656025 ==
8081 23:25:21.670710
8082 23:25:21.674141 TX Vref early break, caculate TX vref
8083 23:25:21.677480 TX Vref=16, minBit 1, minWin=22, winSum=386
8084 23:25:21.680545 TX Vref=18, minBit 1, minWin=22, winSum=395
8085 23:25:21.683888 TX Vref=20, minBit 0, minWin=24, winSum=402
8086 23:25:21.687228 TX Vref=22, minBit 0, minWin=25, winSum=413
8087 23:25:21.690813 TX Vref=24, minBit 1, minWin=24, winSum=422
8088 23:25:21.697237 TX Vref=26, minBit 1, minWin=25, winSum=428
8089 23:25:21.700453 TX Vref=28, minBit 4, minWin=25, winSum=425
8090 23:25:21.703902 TX Vref=30, minBit 0, minWin=25, winSum=416
8091 23:25:21.707351 TX Vref=32, minBit 0, minWin=24, winSum=409
8092 23:25:21.710677 TX Vref=34, minBit 1, minWin=24, winSum=406
8093 23:25:21.714007 TX Vref=36, minBit 4, minWin=23, winSum=392
8094 23:25:21.720675 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 26
8095 23:25:21.720759
8096 23:25:21.724040 Final TX Range 0 Vref 26
8097 23:25:21.724144
8098 23:25:21.724237 ==
8099 23:25:21.727309 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 23:25:21.730633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 23:25:21.730757 ==
8102 23:25:21.730876
8103 23:25:21.730984
8104 23:25:21.734192 TX Vref Scan disable
8105 23:25:21.740686 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8106 23:25:21.740816 == TX Byte 0 ==
8107 23:25:21.744081 u2DelayCellOfst[0]=13 cells (4 PI)
8108 23:25:21.747074 u2DelayCellOfst[1]=17 cells (5 PI)
8109 23:25:21.750294 u2DelayCellOfst[2]=10 cells (3 PI)
8110 23:25:21.753988 u2DelayCellOfst[3]=6 cells (2 PI)
8111 23:25:21.757322 u2DelayCellOfst[4]=6 cells (2 PI)
8112 23:25:21.760650 u2DelayCellOfst[5]=0 cells (0 PI)
8113 23:25:21.763685 u2DelayCellOfst[6]=13 cells (4 PI)
8114 23:25:21.767221 u2DelayCellOfst[7]=13 cells (4 PI)
8115 23:25:21.770769 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8116 23:25:21.773820 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8117 23:25:21.776982 == TX Byte 1 ==
8118 23:25:21.780361 u2DelayCellOfst[8]=3 cells (1 PI)
8119 23:25:21.780488 u2DelayCellOfst[9]=0 cells (0 PI)
8120 23:25:21.783625 u2DelayCellOfst[10]=6 cells (2 PI)
8121 23:25:21.787119 u2DelayCellOfst[11]=6 cells (2 PI)
8122 23:25:21.790160 u2DelayCellOfst[12]=10 cells (3 PI)
8123 23:25:21.793625 u2DelayCellOfst[13]=13 cells (4 PI)
8124 23:25:21.796659 u2DelayCellOfst[14]=13 cells (4 PI)
8125 23:25:21.800131 u2DelayCellOfst[15]=10 cells (3 PI)
8126 23:25:21.803474 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8127 23:25:21.809977 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8128 23:25:21.810101 DramC Write-DBI on
8129 23:25:21.810218 ==
8130 23:25:21.813404 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 23:25:21.820059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 23:25:21.820190 ==
8133 23:25:21.820321
8134 23:25:21.820433
8135 23:25:21.820541 TX Vref Scan disable
8136 23:25:21.824027 == TX Byte 0 ==
8137 23:25:21.827144 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8138 23:25:21.830316 == TX Byte 1 ==
8139 23:25:21.833846 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8140 23:25:21.837261 DramC Write-DBI off
8141 23:25:21.837391
8142 23:25:21.837505 [DATLAT]
8143 23:25:21.837621 Freq=1600, CH0 RK1
8144 23:25:21.837731
8145 23:25:21.840481 DATLAT Default: 0xf
8146 23:25:21.840609 0, 0xFFFF, sum = 0
8147 23:25:21.843643 1, 0xFFFF, sum = 0
8148 23:25:21.847062 2, 0xFFFF, sum = 0
8149 23:25:21.847193 3, 0xFFFF, sum = 0
8150 23:25:21.850489 4, 0xFFFF, sum = 0
8151 23:25:21.850596 5, 0xFFFF, sum = 0
8152 23:25:21.853553 6, 0xFFFF, sum = 0
8153 23:25:21.853630 7, 0xFFFF, sum = 0
8154 23:25:21.856895 8, 0xFFFF, sum = 0
8155 23:25:21.856976 9, 0xFFFF, sum = 0
8156 23:25:21.860176 10, 0xFFFF, sum = 0
8157 23:25:21.860276 11, 0xFFFF, sum = 0
8158 23:25:21.863448 12, 0xFFFF, sum = 0
8159 23:25:21.863520 13, 0xFFFF, sum = 0
8160 23:25:21.867095 14, 0x0, sum = 1
8161 23:25:21.867172 15, 0x0, sum = 2
8162 23:25:21.870377 16, 0x0, sum = 3
8163 23:25:21.870452 17, 0x0, sum = 4
8164 23:25:21.873751 best_step = 15
8165 23:25:21.873835
8166 23:25:21.873903 ==
8167 23:25:21.877171 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 23:25:21.880062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 23:25:21.880137 ==
8170 23:25:21.883452 RX Vref Scan: 0
8171 23:25:21.883521
8172 23:25:21.883585 RX Vref 0 -> 0, step: 1
8173 23:25:21.883643
8174 23:25:21.886807 RX Delay 19 -> 252, step: 4
8175 23:25:21.890151 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8176 23:25:21.896838 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8177 23:25:21.899937 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8178 23:25:21.903348 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8179 23:25:21.906690 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8180 23:25:21.910162 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8181 23:25:21.916680 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8182 23:25:21.920141 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8183 23:25:21.923243 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8184 23:25:21.926623 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8185 23:25:21.930109 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8186 23:25:21.936806 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8187 23:25:21.940205 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8188 23:25:21.943219 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8189 23:25:21.946549 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8190 23:25:21.953351 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8191 23:25:21.953458 ==
8192 23:25:21.956398 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 23:25:21.959935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 23:25:21.960057 ==
8195 23:25:21.960169 DQS Delay:
8196 23:25:21.963092 DQS0 = 0, DQS1 = 0
8197 23:25:21.963209 DQM Delay:
8198 23:25:21.966629 DQM0 = 134, DQM1 = 127
8199 23:25:21.966752 DQ Delay:
8200 23:25:21.969946 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8201 23:25:21.973121 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8202 23:25:21.976500 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8203 23:25:21.979896 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8204 23:25:21.980014
8205 23:25:21.980124
8206 23:25:21.980235
8207 23:25:21.983199 [DramC_TX_OE_Calibration] TA2
8208 23:25:21.986349 Original DQ_B0 (3 6) =30, OEN = 27
8209 23:25:21.989662 Original DQ_B1 (3 6) =30, OEN = 27
8210 23:25:21.993016 24, 0x0, End_B0=24 End_B1=24
8211 23:25:21.996352 25, 0x0, End_B0=25 End_B1=25
8212 23:25:21.996478 26, 0x0, End_B0=26 End_B1=26
8213 23:25:21.999626 27, 0x0, End_B0=27 End_B1=27
8214 23:25:22.003144 28, 0x0, End_B0=28 End_B1=28
8215 23:25:22.006533 29, 0x0, End_B0=29 End_B1=29
8216 23:25:22.009583 30, 0x0, End_B0=30 End_B1=30
8217 23:25:22.009687 31, 0x4141, End_B0=30 End_B1=30
8218 23:25:22.013072 Byte0 end_step=30 best_step=27
8219 23:25:22.016494 Byte1 end_step=30 best_step=27
8220 23:25:22.019956 Byte0 TX OE(2T, 0.5T) = (3, 3)
8221 23:25:22.022872 Byte1 TX OE(2T, 0.5T) = (3, 3)
8222 23:25:22.022955
8223 23:25:22.023020
8224 23:25:22.029896 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8225 23:25:22.033029 CH0 RK1: MR19=303, MR18=2109
8226 23:25:22.039892 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8227 23:25:22.042962 [RxdqsGatingPostProcess] freq 1600
8228 23:25:22.049777 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8229 23:25:22.049913 best DQS0 dly(2T, 0.5T) = (1, 1)
8230 23:25:22.053087 best DQS1 dly(2T, 0.5T) = (1, 1)
8231 23:25:22.056217 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8232 23:25:22.059702 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8233 23:25:22.063206 best DQS0 dly(2T, 0.5T) = (1, 1)
8234 23:25:22.066203 best DQS1 dly(2T, 0.5T) = (1, 1)
8235 23:25:22.069569 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8236 23:25:22.072815 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8237 23:25:22.076378 Pre-setting of DQS Precalculation
8238 23:25:22.079632 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8239 23:25:22.079757 ==
8240 23:25:22.082945 Dram Type= 6, Freq= 0, CH_1, rank 0
8241 23:25:22.089720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 23:25:22.089891 ==
8243 23:25:22.092931 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8244 23:25:22.099501 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8245 23:25:22.102660 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8246 23:25:22.109176 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8247 23:25:22.117056 [CA 0] Center 41 (12~71) winsize 60
8248 23:25:22.120371 [CA 1] Center 41 (12~71) winsize 60
8249 23:25:22.123612 [CA 2] Center 38 (9~68) winsize 60
8250 23:25:22.126980 [CA 3] Center 37 (9~66) winsize 58
8251 23:25:22.130396 [CA 4] Center 37 (8~67) winsize 60
8252 23:25:22.133437 [CA 5] Center 36 (7~66) winsize 60
8253 23:25:22.133562
8254 23:25:22.136925 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8255 23:25:22.137047
8256 23:25:22.140102 [CATrainingPosCal] consider 1 rank data
8257 23:25:22.143526 u2DelayCellTimex100 = 285/100 ps
8258 23:25:22.146868 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8259 23:25:22.153499 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8260 23:25:22.156878 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8261 23:25:22.160297 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8262 23:25:22.163455 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8263 23:25:22.166881 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8264 23:25:22.166989
8265 23:25:22.169936 CA PerBit enable=1, Macro0, CA PI delay=36
8266 23:25:22.170014
8267 23:25:22.173381 [CBTSetCACLKResult] CA Dly = 36
8268 23:25:22.176864 CS Dly: 10 (0~41)
8269 23:25:22.179950 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8270 23:25:22.183372 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8271 23:25:22.183456 ==
8272 23:25:22.186749 Dram Type= 6, Freq= 0, CH_1, rank 1
8273 23:25:22.189909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 23:25:22.193067 ==
8275 23:25:22.196514 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8276 23:25:22.199936 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8277 23:25:22.206728 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8278 23:25:22.209736 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8279 23:25:22.220171 [CA 0] Center 42 (12~72) winsize 61
8280 23:25:22.223432 [CA 1] Center 42 (13~71) winsize 59
8281 23:25:22.226963 [CA 2] Center 38 (9~68) winsize 60
8282 23:25:22.230114 [CA 3] Center 37 (8~67) winsize 60
8283 23:25:22.233262 [CA 4] Center 38 (8~68) winsize 61
8284 23:25:22.236458 [CA 5] Center 37 (8~67) winsize 60
8285 23:25:22.236536
8286 23:25:22.240087 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8287 23:25:22.240195
8288 23:25:22.243205 [CATrainingPosCal] consider 2 rank data
8289 23:25:22.246687 u2DelayCellTimex100 = 285/100 ps
8290 23:25:22.249685 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8291 23:25:22.256345 CA1 delay=42 (13~71),Diff = 5 PI (17 cell)
8292 23:25:22.259850 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8293 23:25:22.263183 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8294 23:25:22.266595 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8295 23:25:22.269590 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8296 23:25:22.269673
8297 23:25:22.273149 CA PerBit enable=1, Macro0, CA PI delay=37
8298 23:25:22.273227
8299 23:25:22.276233 [CBTSetCACLKResult] CA Dly = 37
8300 23:25:22.279836 CS Dly: 12 (0~45)
8301 23:25:22.282932 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8302 23:25:22.286082 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8303 23:25:22.286189
8304 23:25:22.289464 ----->DramcWriteLeveling(PI) begin...
8305 23:25:22.289579 ==
8306 23:25:22.292892 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 23:25:22.299643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 23:25:22.299749 ==
8309 23:25:22.303048 Write leveling (Byte 0): 24 => 24
8310 23:25:22.303167 Write leveling (Byte 1): 28 => 28
8311 23:25:22.306027 DramcWriteLeveling(PI) end<-----
8312 23:25:22.306140
8313 23:25:22.309437 ==
8314 23:25:22.309544 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 23:25:22.316317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 23:25:22.316413 ==
8317 23:25:22.319318 [Gating] SW mode calibration
8318 23:25:22.325912 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8319 23:25:22.329333 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8320 23:25:22.335955 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 23:25:22.339091 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 23:25:22.342574 1 4 8 | B1->B0 | 2323 2d2d | 1 0 | (1 1) (0 0)
8323 23:25:22.349292 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 23:25:22.352714 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 23:25:22.355992 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 23:25:22.362317 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 23:25:22.365920 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 23:25:22.369118 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 23:25:22.375857 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 23:25:22.379179 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8331 23:25:22.382416 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
8332 23:25:22.388973 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 23:25:22.392412 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 23:25:22.395533 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 23:25:22.402420 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 23:25:22.405519 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 23:25:22.408719 1 6 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8338 23:25:22.415517 1 6 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
8339 23:25:22.418931 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8340 23:25:22.422327 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 23:25:22.428705 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 23:25:22.432126 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 23:25:22.435215 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 23:25:22.441762 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 23:25:22.445080 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 23:25:22.448565 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8347 23:25:22.452043 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8348 23:25:22.458540 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 23:25:22.461950 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 23:25:22.465114 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 23:25:22.471719 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 23:25:22.475207 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 23:25:22.478470 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 23:25:22.485195 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 23:25:22.488283 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 23:25:22.491523 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 23:25:22.498233 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 23:25:22.501459 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 23:25:22.504944 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 23:25:22.511752 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 23:25:22.514948 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 23:25:22.518301 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8363 23:25:22.524994 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8364 23:25:22.525079 Total UI for P1: 0, mck2ui 16
8365 23:25:22.531869 best dqsien dly found for B0: ( 1, 9, 8)
8366 23:25:22.534855 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 23:25:22.538079 Total UI for P1: 0, mck2ui 16
8368 23:25:22.541736 best dqsien dly found for B1: ( 1, 9, 10)
8369 23:25:22.544795 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8370 23:25:22.548228 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8371 23:25:22.548320
8372 23:25:22.551351 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8373 23:25:22.554743 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8374 23:25:22.557902 [Gating] SW calibration Done
8375 23:25:22.557985 ==
8376 23:25:22.561350 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 23:25:22.564753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 23:25:22.567839 ==
8379 23:25:22.567964 RX Vref Scan: 0
8380 23:25:22.568073
8381 23:25:22.571320 RX Vref 0 -> 0, step: 1
8382 23:25:22.571442
8383 23:25:22.571555 RX Delay 0 -> 252, step: 8
8384 23:25:22.578010 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8385 23:25:22.581197 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8386 23:25:22.584917 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8387 23:25:22.587869 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8388 23:25:22.591270 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8389 23:25:22.598197 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8390 23:25:22.601225 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8391 23:25:22.604588 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8392 23:25:22.607884 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8393 23:25:22.611284 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8394 23:25:22.618077 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8395 23:25:22.621374 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8396 23:25:22.624717 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8397 23:25:22.627995 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8398 23:25:22.631453 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8399 23:25:22.637978 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8400 23:25:22.638063 ==
8401 23:25:22.641474 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 23:25:22.644713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 23:25:22.644822 ==
8404 23:25:22.644917 DQS Delay:
8405 23:25:22.648178 DQS0 = 0, DQS1 = 0
8406 23:25:22.648295 DQM Delay:
8407 23:25:22.651295 DQM0 = 136, DQM1 = 132
8408 23:25:22.651379 DQ Delay:
8409 23:25:22.654769 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8410 23:25:22.658229 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8411 23:25:22.661227 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8412 23:25:22.664627 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8413 23:25:22.664713
8414 23:25:22.664778
8415 23:25:22.668106 ==
8416 23:25:22.671121 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 23:25:22.674637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 23:25:22.674721 ==
8419 23:25:22.674786
8420 23:25:22.674847
8421 23:25:22.678068 TX Vref Scan disable
8422 23:25:22.678151 == TX Byte 0 ==
8423 23:25:22.681452 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8424 23:25:22.687902 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8425 23:25:22.687984 == TX Byte 1 ==
8426 23:25:22.691334 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8427 23:25:22.697684 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8428 23:25:22.697790 ==
8429 23:25:22.701322 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 23:25:22.704549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 23:25:22.704628 ==
8432 23:25:22.717666
8433 23:25:22.720750 TX Vref early break, caculate TX vref
8434 23:25:22.724133 TX Vref=16, minBit 9, minWin=22, winSum=373
8435 23:25:22.727410 TX Vref=18, minBit 0, minWin=23, winSum=383
8436 23:25:22.730731 TX Vref=20, minBit 3, minWin=24, winSum=396
8437 23:25:22.734406 TX Vref=22, minBit 6, minWin=24, winSum=407
8438 23:25:22.737814 TX Vref=24, minBit 0, minWin=25, winSum=412
8439 23:25:22.744159 TX Vref=26, minBit 0, minWin=25, winSum=421
8440 23:25:22.747537 TX Vref=28, minBit 0, minWin=26, winSum=429
8441 23:25:22.750690 TX Vref=30, minBit 0, minWin=25, winSum=420
8442 23:25:22.754143 TX Vref=32, minBit 0, minWin=24, winSum=413
8443 23:25:22.757707 TX Vref=34, minBit 10, minWin=23, winSum=400
8444 23:25:22.764269 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8445 23:25:22.764388
8446 23:25:22.767375 Final TX Range 0 Vref 28
8447 23:25:22.767459
8448 23:25:22.767524 ==
8449 23:25:22.770889 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 23:25:22.774009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 23:25:22.774093 ==
8452 23:25:22.774158
8453 23:25:22.774218
8454 23:25:22.777368 TX Vref Scan disable
8455 23:25:22.784216 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8456 23:25:22.784330 == TX Byte 0 ==
8457 23:25:22.787291 u2DelayCellOfst[0]=17 cells (5 PI)
8458 23:25:22.790674 u2DelayCellOfst[1]=10 cells (3 PI)
8459 23:25:22.794058 u2DelayCellOfst[2]=0 cells (0 PI)
8460 23:25:22.797279 u2DelayCellOfst[3]=6 cells (2 PI)
8461 23:25:22.800623 u2DelayCellOfst[4]=10 cells (3 PI)
8462 23:25:22.803894 u2DelayCellOfst[5]=17 cells (5 PI)
8463 23:25:22.807280 u2DelayCellOfst[6]=17 cells (5 PI)
8464 23:25:22.810631 u2DelayCellOfst[7]=6 cells (2 PI)
8465 23:25:22.814094 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8466 23:25:22.817204 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8467 23:25:22.820579 == TX Byte 1 ==
8468 23:25:22.820661 u2DelayCellOfst[8]=0 cells (0 PI)
8469 23:25:22.823924 u2DelayCellOfst[9]=6 cells (2 PI)
8470 23:25:22.827055 u2DelayCellOfst[10]=13 cells (4 PI)
8471 23:25:22.830582 u2DelayCellOfst[11]=6 cells (2 PI)
8472 23:25:22.833585 u2DelayCellOfst[12]=17 cells (5 PI)
8473 23:25:22.837149 u2DelayCellOfst[13]=17 cells (5 PI)
8474 23:25:22.840519 u2DelayCellOfst[14]=20 cells (6 PI)
8475 23:25:22.843682 u2DelayCellOfst[15]=17 cells (5 PI)
8476 23:25:22.847135 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8477 23:25:22.853654 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8478 23:25:22.853737 DramC Write-DBI on
8479 23:25:22.853803 ==
8480 23:25:22.856914 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 23:25:22.860456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 23:25:22.863365 ==
8483 23:25:22.863447
8484 23:25:22.863511
8485 23:25:22.863572 TX Vref Scan disable
8486 23:25:22.867066 == TX Byte 0 ==
8487 23:25:22.870369 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8488 23:25:22.873767 == TX Byte 1 ==
8489 23:25:22.877030 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8490 23:25:22.880183 DramC Write-DBI off
8491 23:25:22.880297
8492 23:25:22.880383 [DATLAT]
8493 23:25:22.880468 Freq=1600, CH1 RK0
8494 23:25:22.880549
8495 23:25:22.883740 DATLAT Default: 0xf
8496 23:25:22.883823 0, 0xFFFF, sum = 0
8497 23:25:22.886961 1, 0xFFFF, sum = 0
8498 23:25:22.890442 2, 0xFFFF, sum = 0
8499 23:25:22.890526 3, 0xFFFF, sum = 0
8500 23:25:22.893849 4, 0xFFFF, sum = 0
8501 23:25:22.893965 5, 0xFFFF, sum = 0
8502 23:25:22.896794 6, 0xFFFF, sum = 0
8503 23:25:22.896878 7, 0xFFFF, sum = 0
8504 23:25:22.900484 8, 0xFFFF, sum = 0
8505 23:25:22.900568 9, 0xFFFF, sum = 0
8506 23:25:22.903582 10, 0xFFFF, sum = 0
8507 23:25:22.903666 11, 0xFFFF, sum = 0
8508 23:25:22.907007 12, 0xFFFF, sum = 0
8509 23:25:22.907089 13, 0xFFFF, sum = 0
8510 23:25:22.910463 14, 0x0, sum = 1
8511 23:25:22.910545 15, 0x0, sum = 2
8512 23:25:22.913600 16, 0x0, sum = 3
8513 23:25:22.913708 17, 0x0, sum = 4
8514 23:25:22.917185 best_step = 15
8515 23:25:22.917326
8516 23:25:22.917457 ==
8517 23:25:22.920325 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 23:25:22.923775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 23:25:22.923851 ==
8520 23:25:22.923930 RX Vref Scan: 1
8521 23:25:22.927206
8522 23:25:22.927286 Set Vref Range= 24 -> 127
8523 23:25:22.927349
8524 23:25:22.930239 RX Vref 24 -> 127, step: 1
8525 23:25:22.930318
8526 23:25:22.933646 RX Delay 27 -> 252, step: 4
8527 23:25:22.933727
8528 23:25:22.936766 Set Vref, RX VrefLevel [Byte0]: 24
8529 23:25:22.940330 [Byte1]: 24
8530 23:25:22.940424
8531 23:25:22.943788 Set Vref, RX VrefLevel [Byte0]: 25
8532 23:25:22.946698 [Byte1]: 25
8533 23:25:22.946778
8534 23:25:22.950267 Set Vref, RX VrefLevel [Byte0]: 26
8535 23:25:22.953377 [Byte1]: 26
8536 23:25:22.957283
8537 23:25:22.957379 Set Vref, RX VrefLevel [Byte0]: 27
8538 23:25:22.960704 [Byte1]: 27
8539 23:25:22.965005
8540 23:25:22.965088 Set Vref, RX VrefLevel [Byte0]: 28
8541 23:25:22.968136 [Byte1]: 28
8542 23:25:22.972467
8543 23:25:22.972549 Set Vref, RX VrefLevel [Byte0]: 29
8544 23:25:22.975576 [Byte1]: 29
8545 23:25:22.979803
8546 23:25:22.982847 Set Vref, RX VrefLevel [Byte0]: 30
8547 23:25:22.986153 [Byte1]: 30
8548 23:25:22.986251
8549 23:25:22.989382 Set Vref, RX VrefLevel [Byte0]: 31
8550 23:25:22.992659 [Byte1]: 31
8551 23:25:22.992742
8552 23:25:22.996107 Set Vref, RX VrefLevel [Byte0]: 32
8553 23:25:22.999448 [Byte1]: 32
8554 23:25:22.999586
8555 23:25:23.002950 Set Vref, RX VrefLevel [Byte0]: 33
8556 23:25:23.005900 [Byte1]: 33
8557 23:25:23.009891
8558 23:25:23.009975 Set Vref, RX VrefLevel [Byte0]: 34
8559 23:25:23.013314 [Byte1]: 34
8560 23:25:23.017403
8561 23:25:23.017486 Set Vref, RX VrefLevel [Byte0]: 35
8562 23:25:23.020801 [Byte1]: 35
8563 23:25:23.024897
8564 23:25:23.024982 Set Vref, RX VrefLevel [Byte0]: 36
8565 23:25:23.028266 [Byte1]: 36
8566 23:25:23.032464
8567 23:25:23.032546 Set Vref, RX VrefLevel [Byte0]: 37
8568 23:25:23.036005 [Byte1]: 37
8569 23:25:23.039932
8570 23:25:23.040014 Set Vref, RX VrefLevel [Byte0]: 38
8571 23:25:23.043424 [Byte1]: 38
8572 23:25:23.047768
8573 23:25:23.047853 Set Vref, RX VrefLevel [Byte0]: 39
8574 23:25:23.050903 [Byte1]: 39
8575 23:25:23.055166
8576 23:25:23.055249 Set Vref, RX VrefLevel [Byte0]: 40
8577 23:25:23.058569 [Byte1]: 40
8578 23:25:23.062442
8579 23:25:23.062555 Set Vref, RX VrefLevel [Byte0]: 41
8580 23:25:23.065944 [Byte1]: 41
8581 23:25:23.070220
8582 23:25:23.070328 Set Vref, RX VrefLevel [Byte0]: 42
8583 23:25:23.073542 [Byte1]: 42
8584 23:25:23.077764
8585 23:25:23.077845 Set Vref, RX VrefLevel [Byte0]: 43
8586 23:25:23.081004 [Byte1]: 43
8587 23:25:23.085203
8588 23:25:23.085309 Set Vref, RX VrefLevel [Byte0]: 44
8589 23:25:23.088638 [Byte1]: 44
8590 23:25:23.092929
8591 23:25:23.093039 Set Vref, RX VrefLevel [Byte0]: 45
8592 23:25:23.095882 [Byte1]: 45
8593 23:25:23.100265
8594 23:25:23.100380 Set Vref, RX VrefLevel [Byte0]: 46
8595 23:25:23.103514 [Byte1]: 46
8596 23:25:23.107910
8597 23:25:23.108012 Set Vref, RX VrefLevel [Byte0]: 47
8598 23:25:23.111297 [Byte1]: 47
8599 23:25:23.115314
8600 23:25:23.115396 Set Vref, RX VrefLevel [Byte0]: 48
8601 23:25:23.118528 [Byte1]: 48
8602 23:25:23.122850
8603 23:25:23.122954 Set Vref, RX VrefLevel [Byte0]: 49
8604 23:25:23.126203 [Byte1]: 49
8605 23:25:23.130368
8606 23:25:23.130478 Set Vref, RX VrefLevel [Byte0]: 50
8607 23:25:23.133922 [Byte1]: 50
8608 23:25:23.137752
8609 23:25:23.137857 Set Vref, RX VrefLevel [Byte0]: 51
8610 23:25:23.141382 [Byte1]: 51
8611 23:25:23.145668
8612 23:25:23.145774 Set Vref, RX VrefLevel [Byte0]: 52
8613 23:25:23.148604 [Byte1]: 52
8614 23:25:23.152937
8615 23:25:23.153017 Set Vref, RX VrefLevel [Byte0]: 53
8616 23:25:23.156360 [Byte1]: 53
8617 23:25:23.160415
8618 23:25:23.160507 Set Vref, RX VrefLevel [Byte0]: 54
8619 23:25:23.163661 [Byte1]: 54
8620 23:25:23.167980
8621 23:25:23.168084 Set Vref, RX VrefLevel [Byte0]: 55
8622 23:25:23.171499 [Byte1]: 55
8623 23:25:23.175755
8624 23:25:23.175854 Set Vref, RX VrefLevel [Byte0]: 56
8625 23:25:23.178922 [Byte1]: 56
8626 23:25:23.183120
8627 23:25:23.183222 Set Vref, RX VrefLevel [Byte0]: 57
8628 23:25:23.186531 [Byte1]: 57
8629 23:25:23.190779
8630 23:25:23.190877 Set Vref, RX VrefLevel [Byte0]: 58
8631 23:25:23.194176 [Byte1]: 58
8632 23:25:23.198127
8633 23:25:23.198209 Set Vref, RX VrefLevel [Byte0]: 59
8634 23:25:23.201566 [Byte1]: 59
8635 23:25:23.205569
8636 23:25:23.205655 Set Vref, RX VrefLevel [Byte0]: 60
8637 23:25:23.209125 [Byte1]: 60
8638 23:25:23.213327
8639 23:25:23.213410 Set Vref, RX VrefLevel [Byte0]: 61
8640 23:25:23.216438 [Byte1]: 61
8641 23:25:23.220909
8642 23:25:23.220999 Set Vref, RX VrefLevel [Byte0]: 62
8643 23:25:23.223877 [Byte1]: 62
8644 23:25:23.228241
8645 23:25:23.228360 Set Vref, RX VrefLevel [Byte0]: 63
8646 23:25:23.231756 [Byte1]: 63
8647 23:25:23.236037
8648 23:25:23.236139 Set Vref, RX VrefLevel [Byte0]: 64
8649 23:25:23.239303 [Byte1]: 64
8650 23:25:23.243080
8651 23:25:23.246895 Set Vref, RX VrefLevel [Byte0]: 65
8652 23:25:23.249896 [Byte1]: 65
8653 23:25:23.249973
8654 23:25:23.252999 Set Vref, RX VrefLevel [Byte0]: 66
8655 23:25:23.256355 [Byte1]: 66
8656 23:25:23.256431
8657 23:25:23.260075 Set Vref, RX VrefLevel [Byte0]: 67
8658 23:25:23.263051 [Byte1]: 67
8659 23:25:23.263152
8660 23:25:23.266307 Set Vref, RX VrefLevel [Byte0]: 68
8661 23:25:23.269841 [Byte1]: 68
8662 23:25:23.273563
8663 23:25:23.273673 Set Vref, RX VrefLevel [Byte0]: 69
8664 23:25:23.277001 [Byte1]: 69
8665 23:25:23.280918
8666 23:25:23.281004 Set Vref, RX VrefLevel [Byte0]: 70
8667 23:25:23.284293 [Byte1]: 70
8668 23:25:23.288688
8669 23:25:23.288794 Set Vref, RX VrefLevel [Byte0]: 71
8670 23:25:23.291727 [Byte1]: 71
8671 23:25:23.295939
8672 23:25:23.296043 Set Vref, RX VrefLevel [Byte0]: 72
8673 23:25:23.299407 [Byte1]: 72
8674 23:25:23.303572
8675 23:25:23.303681 Set Vref, RX VrefLevel [Byte0]: 73
8676 23:25:23.307062 [Byte1]: 73
8677 23:25:23.311329
8678 23:25:23.311421 Set Vref, RX VrefLevel [Byte0]: 74
8679 23:25:23.314322 [Byte1]: 74
8680 23:25:23.318598
8681 23:25:23.318704 Set Vref, RX VrefLevel [Byte0]: 75
8682 23:25:23.321979 [Byte1]: 75
8683 23:25:23.326360
8684 23:25:23.326467 Set Vref, RX VrefLevel [Byte0]: 76
8685 23:25:23.329591 [Byte1]: 76
8686 23:25:23.333734
8687 23:25:23.333816 Set Vref, RX VrefLevel [Byte0]: 77
8688 23:25:23.337061 [Byte1]: 77
8689 23:25:23.341392
8690 23:25:23.341470 Set Vref, RX VrefLevel [Byte0]: 78
8691 23:25:23.344416 [Byte1]: 78
8692 23:25:23.348712
8693 23:25:23.348818 Set Vref, RX VrefLevel [Byte0]: 79
8694 23:25:23.352029 [Byte1]: 79
8695 23:25:23.356350
8696 23:25:23.356463 Final RX Vref Byte 0 = 58 to rank0
8697 23:25:23.359665 Final RX Vref Byte 1 = 55 to rank0
8698 23:25:23.363075 Final RX Vref Byte 0 = 58 to rank1
8699 23:25:23.366383 Final RX Vref Byte 1 = 55 to rank1==
8700 23:25:23.369845 Dram Type= 6, Freq= 0, CH_1, rank 0
8701 23:25:23.376213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8702 23:25:23.376352 ==
8703 23:25:23.376463 DQS Delay:
8704 23:25:23.376571 DQS0 = 0, DQS1 = 0
8705 23:25:23.379563 DQM Delay:
8706 23:25:23.379669 DQM0 = 134, DQM1 = 131
8707 23:25:23.382986 DQ Delay:
8708 23:25:23.386537 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8709 23:25:23.389535 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8710 23:25:23.392828 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8711 23:25:23.396153 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8712 23:25:23.396257
8713 23:25:23.396365
8714 23:25:23.396462
8715 23:25:23.399563 [DramC_TX_OE_Calibration] TA2
8716 23:25:23.403003 Original DQ_B0 (3 6) =30, OEN = 27
8717 23:25:23.406466 Original DQ_B1 (3 6) =30, OEN = 27
8718 23:25:23.409889 24, 0x0, End_B0=24 End_B1=24
8719 23:25:23.410000 25, 0x0, End_B0=25 End_B1=25
8720 23:25:23.412872 26, 0x0, End_B0=26 End_B1=26
8721 23:25:23.416407 27, 0x0, End_B0=27 End_B1=27
8722 23:25:23.419424 28, 0x0, End_B0=28 End_B1=28
8723 23:25:23.419503 29, 0x0, End_B0=29 End_B1=29
8724 23:25:23.422756 30, 0x0, End_B0=30 End_B1=30
8725 23:25:23.426237 31, 0x4141, End_B0=30 End_B1=30
8726 23:25:23.429593 Byte0 end_step=30 best_step=27
8727 23:25:23.432813 Byte1 end_step=30 best_step=27
8728 23:25:23.436052 Byte0 TX OE(2T, 0.5T) = (3, 3)
8729 23:25:23.436155 Byte1 TX OE(2T, 0.5T) = (3, 3)
8730 23:25:23.439455
8731 23:25:23.439533
8732 23:25:23.446101 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8733 23:25:23.449539 CH1 RK0: MR19=303, MR18=1523
8734 23:25:23.456119 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8735 23:25:23.456224
8736 23:25:23.459145 ----->DramcWriteLeveling(PI) begin...
8737 23:25:23.459248 ==
8738 23:25:23.462894 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 23:25:23.465833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 23:25:23.465919 ==
8741 23:25:23.469252 Write leveling (Byte 0): 26 => 26
8742 23:25:23.472678 Write leveling (Byte 1): 28 => 28
8743 23:25:23.476042 DramcWriteLeveling(PI) end<-----
8744 23:25:23.476151
8745 23:25:23.476244 ==
8746 23:25:23.479041 Dram Type= 6, Freq= 0, CH_1, rank 1
8747 23:25:23.482334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 23:25:23.482442 ==
8749 23:25:23.485848 [Gating] SW mode calibration
8750 23:25:23.492193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8751 23:25:23.498893 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8752 23:25:23.502292 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 23:25:23.508873 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 23:25:23.512305 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8755 23:25:23.515269 1 4 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 0)
8756 23:25:23.522345 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 23:25:23.525441 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 23:25:23.528914 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 23:25:23.531960 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 23:25:23.538567 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 23:25:23.542013 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8762 23:25:23.545333 1 5 8 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
8763 23:25:23.551995 1 5 12 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 1)
8764 23:25:23.555360 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 23:25:23.558753 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 23:25:23.565160 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 23:25:23.568836 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 23:25:23.572189 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 23:25:23.578909 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 23:25:23.581748 1 6 8 | B1->B0 | 3838 2323 | 0 0 | (0 0) (0 0)
8771 23:25:23.585214 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 23:25:23.591915 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 23:25:23.595373 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 23:25:23.598440 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 23:25:23.605161 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 23:25:23.608610 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 23:25:23.611947 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8778 23:25:23.618279 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8779 23:25:23.621603 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8780 23:25:23.625247 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 23:25:23.631680 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 23:25:23.635194 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 23:25:23.638677 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 23:25:23.645197 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 23:25:23.648297 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 23:25:23.651735 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 23:25:23.655165 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 23:25:23.661663 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 23:25:23.665114 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 23:25:23.668501 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 23:25:23.675161 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 23:25:23.678419 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 23:25:23.681709 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 23:25:23.688361 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8795 23:25:23.691984 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8796 23:25:23.694983 Total UI for P1: 0, mck2ui 16
8797 23:25:23.698696 best dqsien dly found for B1: ( 1, 9, 8)
8798 23:25:23.701618 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 23:25:23.705069 Total UI for P1: 0, mck2ui 16
8800 23:25:23.708220 best dqsien dly found for B0: ( 1, 9, 10)
8801 23:25:23.711562 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8802 23:25:23.715049 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8803 23:25:23.715152
8804 23:25:23.721561 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8805 23:25:23.725106 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8806 23:25:23.725210 [Gating] SW calibration Done
8807 23:25:23.728347 ==
8808 23:25:23.731578 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 23:25:23.734949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 23:25:23.735055 ==
8811 23:25:23.735148 RX Vref Scan: 0
8812 23:25:23.735241
8813 23:25:23.738116 RX Vref 0 -> 0, step: 1
8814 23:25:23.738215
8815 23:25:23.741609 RX Delay 0 -> 252, step: 8
8816 23:25:23.744704 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8817 23:25:23.748299 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8818 23:25:23.751367 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8819 23:25:23.758221 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8820 23:25:23.761251 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8821 23:25:23.764553 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8822 23:25:23.767919 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8823 23:25:23.771454 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8824 23:25:23.778171 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8825 23:25:23.781184 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8826 23:25:23.784414 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8827 23:25:23.788166 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8828 23:25:23.791418 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8829 23:25:23.798069 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8830 23:25:23.801463 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8831 23:25:23.804619 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8832 23:25:23.804726 ==
8833 23:25:23.808120 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 23:25:23.811100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 23:25:23.814449 ==
8836 23:25:23.814555 DQS Delay:
8837 23:25:23.814648 DQS0 = 0, DQS1 = 0
8838 23:25:23.817837 DQM Delay:
8839 23:25:23.817951 DQM0 = 136, DQM1 = 133
8840 23:25:23.821216 DQ Delay:
8841 23:25:23.824392 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8842 23:25:23.827889 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8843 23:25:23.831377 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8844 23:25:23.834436 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8845 23:25:23.834518
8846 23:25:23.834583
8847 23:25:23.834644 ==
8848 23:25:23.837938 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 23:25:23.840940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 23:25:23.841023 ==
8851 23:25:23.844174
8852 23:25:23.844256
8853 23:25:23.844332 TX Vref Scan disable
8854 23:25:23.847657 == TX Byte 0 ==
8855 23:25:23.850747 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8856 23:25:23.854511 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8857 23:25:23.857444 == TX Byte 1 ==
8858 23:25:23.861040 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8859 23:25:23.864462 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8860 23:25:23.864563 ==
8861 23:25:23.867521 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 23:25:23.874389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 23:25:23.874474 ==
8864 23:25:23.885758
8865 23:25:23.889173 TX Vref early break, caculate TX vref
8866 23:25:23.892516 TX Vref=16, minBit 1, minWin=22, winSum=383
8867 23:25:23.895756 TX Vref=18, minBit 0, minWin=23, winSum=394
8868 23:25:23.899156 TX Vref=20, minBit 0, minWin=24, winSum=402
8869 23:25:23.902426 TX Vref=22, minBit 0, minWin=25, winSum=408
8870 23:25:23.905598 TX Vref=24, minBit 0, minWin=25, winSum=417
8871 23:25:23.912493 TX Vref=26, minBit 0, minWin=25, winSum=427
8872 23:25:23.915961 TX Vref=28, minBit 5, minWin=25, winSum=423
8873 23:25:23.919247 TX Vref=30, minBit 0, minWin=26, winSum=421
8874 23:25:23.922500 TX Vref=32, minBit 0, minWin=24, winSum=410
8875 23:25:23.925805 TX Vref=34, minBit 0, minWin=24, winSum=404
8876 23:25:23.932406 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 30
8877 23:25:23.932494
8878 23:25:23.935805 Final TX Range 0 Vref 30
8879 23:25:23.935904
8880 23:25:23.936003 ==
8881 23:25:23.939227 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 23:25:23.942181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 23:25:23.942290 ==
8884 23:25:23.942381
8885 23:25:23.942471
8886 23:25:23.945651 TX Vref Scan disable
8887 23:25:23.952185 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8888 23:25:23.952305 == TX Byte 0 ==
8889 23:25:23.955756 u2DelayCellOfst[0]=20 cells (6 PI)
8890 23:25:23.959029 u2DelayCellOfst[1]=13 cells (4 PI)
8891 23:25:23.962116 u2DelayCellOfst[2]=0 cells (0 PI)
8892 23:25:23.965592 u2DelayCellOfst[3]=6 cells (2 PI)
8893 23:25:23.968955 u2DelayCellOfst[4]=6 cells (2 PI)
8894 23:25:23.972104 u2DelayCellOfst[5]=17 cells (5 PI)
8895 23:25:23.972181 u2DelayCellOfst[6]=20 cells (6 PI)
8896 23:25:23.975692 u2DelayCellOfst[7]=6 cells (2 PI)
8897 23:25:23.982122 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8898 23:25:23.985803 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8899 23:25:23.985886 == TX Byte 1 ==
8900 23:25:23.988789 u2DelayCellOfst[8]=0 cells (0 PI)
8901 23:25:23.992400 u2DelayCellOfst[9]=3 cells (1 PI)
8902 23:25:23.995596 u2DelayCellOfst[10]=10 cells (3 PI)
8903 23:25:23.998772 u2DelayCellOfst[11]=3 cells (1 PI)
8904 23:25:24.002288 u2DelayCellOfst[12]=13 cells (4 PI)
8905 23:25:24.005615 u2DelayCellOfst[13]=13 cells (4 PI)
8906 23:25:24.009425 u2DelayCellOfst[14]=13 cells (4 PI)
8907 23:25:24.012326 u2DelayCellOfst[15]=17 cells (5 PI)
8908 23:25:24.015685 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8909 23:25:24.018797 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8910 23:25:24.022227 DramC Write-DBI on
8911 23:25:24.022312 ==
8912 23:25:24.025581 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 23:25:24.028828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 23:25:24.028913 ==
8915 23:25:24.028979
8916 23:25:24.029040
8917 23:25:24.032361 TX Vref Scan disable
8918 23:25:24.035397 == TX Byte 0 ==
8919 23:25:24.038773 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8920 23:25:24.041919 == TX Byte 1 ==
8921 23:25:24.045339 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8922 23:25:24.045423 DramC Write-DBI off
8923 23:25:24.045489
8924 23:25:24.048852 [DATLAT]
8925 23:25:24.048935 Freq=1600, CH1 RK1
8926 23:25:24.049002
8927 23:25:24.051995 DATLAT Default: 0xf
8928 23:25:24.052123 0, 0xFFFF, sum = 0
8929 23:25:24.055342 1, 0xFFFF, sum = 0
8930 23:25:24.055473 2, 0xFFFF, sum = 0
8931 23:25:24.058803 3, 0xFFFF, sum = 0
8932 23:25:24.058927 4, 0xFFFF, sum = 0
8933 23:25:24.061843 5, 0xFFFF, sum = 0
8934 23:25:24.061973 6, 0xFFFF, sum = 0
8935 23:25:24.065097 7, 0xFFFF, sum = 0
8936 23:25:24.065231 8, 0xFFFF, sum = 0
8937 23:25:24.068741 9, 0xFFFF, sum = 0
8938 23:25:24.072175 10, 0xFFFF, sum = 0
8939 23:25:24.072308 11, 0xFFFF, sum = 0
8940 23:25:24.075227 12, 0xFFFF, sum = 0
8941 23:25:24.075317 13, 0xFFFF, sum = 0
8942 23:25:24.078659 14, 0x0, sum = 1
8943 23:25:24.078745 15, 0x0, sum = 2
8944 23:25:24.081992 16, 0x0, sum = 3
8945 23:25:24.082078 17, 0x0, sum = 4
8946 23:25:24.082145 best_step = 15
8947 23:25:24.082206
8948 23:25:24.085022 ==
8949 23:25:24.088630 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 23:25:24.092061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 23:25:24.092197 ==
8952 23:25:24.092319 RX Vref Scan: 0
8953 23:25:24.092446
8954 23:25:24.095338 RX Vref 0 -> 0, step: 1
8955 23:25:24.095462
8956 23:25:24.098396 RX Delay 19 -> 252, step: 4
8957 23:25:24.101830 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8958 23:25:24.105130 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8959 23:25:24.111803 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8960 23:25:24.115094 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8961 23:25:24.118683 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8962 23:25:24.121927 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8963 23:25:24.125122 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8964 23:25:24.128660 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8965 23:25:24.135201 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8966 23:25:24.138710 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8967 23:25:24.142188 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8968 23:25:24.145124 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8969 23:25:24.148510 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8970 23:25:24.155292 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8971 23:25:24.158341 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8972 23:25:24.161699 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8973 23:25:24.161835 ==
8974 23:25:24.164854 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 23:25:24.168271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 23:25:24.171753 ==
8977 23:25:24.171876 DQS Delay:
8978 23:25:24.172001 DQS0 = 0, DQS1 = 0
8979 23:25:24.174939 DQM Delay:
8980 23:25:24.175073 DQM0 = 134, DQM1 = 130
8981 23:25:24.178449 DQ Delay:
8982 23:25:24.181515 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8983 23:25:24.184922 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8984 23:25:24.188425 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =126
8985 23:25:24.191918 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8986 23:25:24.192051
8987 23:25:24.192168
8988 23:25:24.192295
8989 23:25:24.194767 [DramC_TX_OE_Calibration] TA2
8990 23:25:24.198122 Original DQ_B0 (3 6) =30, OEN = 27
8991 23:25:24.201669 Original DQ_B1 (3 6) =30, OEN = 27
8992 23:25:24.204836 24, 0x0, End_B0=24 End_B1=24
8993 23:25:24.204922 25, 0x0, End_B0=25 End_B1=25
8994 23:25:24.208059 26, 0x0, End_B0=26 End_B1=26
8995 23:25:24.211556 27, 0x0, End_B0=27 End_B1=27
8996 23:25:24.214940 28, 0x0, End_B0=28 End_B1=28
8997 23:25:24.215025 29, 0x0, End_B0=29 End_B1=29
8998 23:25:24.218297 30, 0x0, End_B0=30 End_B1=30
8999 23:25:24.221532 31, 0x4545, End_B0=30 End_B1=30
9000 23:25:24.224703 Byte0 end_step=30 best_step=27
9001 23:25:24.228146 Byte1 end_step=30 best_step=27
9002 23:25:24.231322 Byte0 TX OE(2T, 0.5T) = (3, 3)
9003 23:25:24.231406 Byte1 TX OE(2T, 0.5T) = (3, 3)
9004 23:25:24.234700
9005 23:25:24.234782
9006 23:25:24.241488 [DQSOSCAuto] RK1, (LSB)MR18= 0x2308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9007 23:25:24.244553 CH1 RK1: MR19=303, MR18=2308
9008 23:25:24.251378 CH1_RK1: MR19=0x303, MR18=0x2308, DQSOSC=392, MR23=63, INC=24, DEC=16
9009 23:25:24.254487 [RxdqsGatingPostProcess] freq 1600
9010 23:25:24.257996 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9011 23:25:24.261400 best DQS0 dly(2T, 0.5T) = (1, 1)
9012 23:25:24.264533 best DQS1 dly(2T, 0.5T) = (1, 1)
9013 23:25:24.267837 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9014 23:25:24.271260 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9015 23:25:24.274749 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 23:25:24.277845 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 23:25:24.281239 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 23:25:24.284687 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 23:25:24.287687 Pre-setting of DQS Precalculation
9020 23:25:24.291167 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9021 23:25:24.297604 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9022 23:25:24.304456 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9023 23:25:24.304592
9024 23:25:24.304712
9025 23:25:24.307675 [Calibration Summary] 3200 Mbps
9026 23:25:24.311208 CH 0, Rank 0
9027 23:25:24.311335 SW Impedance : PASS
9028 23:25:24.314440 DUTY Scan : NO K
9029 23:25:24.317526 ZQ Calibration : PASS
9030 23:25:24.317667 Jitter Meter : NO K
9031 23:25:24.321016 CBT Training : PASS
9032 23:25:24.324007 Write leveling : PASS
9033 23:25:24.324144 RX DQS gating : PASS
9034 23:25:24.327567 RX DQ/DQS(RDDQC) : PASS
9035 23:25:24.331073 TX DQ/DQS : PASS
9036 23:25:24.331209 RX DATLAT : PASS
9037 23:25:24.333997 RX DQ/DQS(Engine): PASS
9038 23:25:24.337515 TX OE : PASS
9039 23:25:24.337655 All Pass.
9040 23:25:24.337773
9041 23:25:24.337897 CH 0, Rank 1
9042 23:25:24.340904 SW Impedance : PASS
9043 23:25:24.344096 DUTY Scan : NO K
9044 23:25:24.344207 ZQ Calibration : PASS
9045 23:25:24.347233 Jitter Meter : NO K
9046 23:25:24.347359 CBT Training : PASS
9047 23:25:24.350548 Write leveling : PASS
9048 23:25:24.353892 RX DQS gating : PASS
9049 23:25:24.354016 RX DQ/DQS(RDDQC) : PASS
9050 23:25:24.357217 TX DQ/DQS : PASS
9051 23:25:24.360681 RX DATLAT : PASS
9052 23:25:24.360804 RX DQ/DQS(Engine): PASS
9053 23:25:24.364051 TX OE : PASS
9054 23:25:24.364170 All Pass.
9055 23:25:24.364293
9056 23:25:24.367302 CH 1, Rank 0
9057 23:25:24.367423 SW Impedance : PASS
9058 23:25:24.370779 DUTY Scan : NO K
9059 23:25:24.373859 ZQ Calibration : PASS
9060 23:25:24.373983 Jitter Meter : NO K
9061 23:25:24.377211 CBT Training : PASS
9062 23:25:24.380694 Write leveling : PASS
9063 23:25:24.380820 RX DQS gating : PASS
9064 23:25:24.383717 RX DQ/DQS(RDDQC) : PASS
9065 23:25:24.387034 TX DQ/DQS : PASS
9066 23:25:24.387153 RX DATLAT : PASS
9067 23:25:24.390545 RX DQ/DQS(Engine): PASS
9068 23:25:24.393854 TX OE : PASS
9069 23:25:24.393945 All Pass.
9070 23:25:24.394013
9071 23:25:24.394082 CH 1, Rank 1
9072 23:25:24.397325 SW Impedance : PASS
9073 23:25:24.400483 DUTY Scan : NO K
9074 23:25:24.400560 ZQ Calibration : PASS
9075 23:25:24.403979 Jitter Meter : NO K
9076 23:25:24.404110 CBT Training : PASS
9077 23:25:24.406926 Write leveling : PASS
9078 23:25:24.410382 RX DQS gating : PASS
9079 23:25:24.410508 RX DQ/DQS(RDDQC) : PASS
9080 23:25:24.413914 TX DQ/DQS : PASS
9081 23:25:24.416923 RX DATLAT : PASS
9082 23:25:24.417046 RX DQ/DQS(Engine): PASS
9083 23:25:24.420423 TX OE : PASS
9084 23:25:24.420550 All Pass.
9085 23:25:24.420679
9086 23:25:24.423923 DramC Write-DBI on
9087 23:25:24.426945 PER_BANK_REFRESH: Hybrid Mode
9088 23:25:24.427071 TX_TRACKING: ON
9089 23:25:24.437113 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9090 23:25:24.443892 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9091 23:25:24.450252 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9092 23:25:24.453537 [FAST_K] Save calibration result to emmc
9093 23:25:24.456976 sync common calibartion params.
9094 23:25:24.460513 sync cbt_mode0:1, 1:1
9095 23:25:24.463570 dram_init: ddr_geometry: 2
9096 23:25:24.463646 dram_init: ddr_geometry: 2
9097 23:25:24.467154 dram_init: ddr_geometry: 2
9098 23:25:24.470206 0:dram_rank_size:100000000
9099 23:25:24.473636 1:dram_rank_size:100000000
9100 23:25:24.476652 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9101 23:25:24.479997 DFS_SHUFFLE_HW_MODE: ON
9102 23:25:24.483301 dramc_set_vcore_voltage set vcore to 725000
9103 23:25:24.486636 Read voltage for 1600, 0
9104 23:25:24.486773 Vio18 = 0
9105 23:25:24.486886 Vcore = 725000
9106 23:25:24.490148 Vdram = 0
9107 23:25:24.490266 Vddq = 0
9108 23:25:24.490387 Vmddr = 0
9109 23:25:24.493597 switch to 3200 Mbps bootup
9110 23:25:24.496544 [DramcRunTimeConfig]
9111 23:25:24.496672 PHYPLL
9112 23:25:24.496787 DPM_CONTROL_AFTERK: ON
9113 23:25:24.500068 PER_BANK_REFRESH: ON
9114 23:25:24.503525 REFRESH_OVERHEAD_REDUCTION: ON
9115 23:25:24.503662 CMD_PICG_NEW_MODE: OFF
9116 23:25:24.506613 XRTWTW_NEW_MODE: ON
9117 23:25:24.510097 XRTRTR_NEW_MODE: ON
9118 23:25:24.510225 TX_TRACKING: ON
9119 23:25:24.513521 RDSEL_TRACKING: OFF
9120 23:25:24.513642 DQS Precalculation for DVFS: ON
9121 23:25:24.516476 RX_TRACKING: OFF
9122 23:25:24.516612 HW_GATING DBG: ON
9123 23:25:24.519943 ZQCS_ENABLE_LP4: ON
9124 23:25:24.520065 RX_PICG_NEW_MODE: ON
9125 23:25:24.523270 TX_PICG_NEW_MODE: ON
9126 23:25:24.526741 ENABLE_RX_DCM_DPHY: ON
9127 23:25:24.530102 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9128 23:25:24.530228 DUMMY_READ_FOR_TRACKING: OFF
9129 23:25:24.533167 !!! SPM_CONTROL_AFTERK: OFF
9130 23:25:24.536586 !!! SPM could not control APHY
9131 23:25:24.540034 IMPEDANCE_TRACKING: ON
9132 23:25:24.540141 TEMP_SENSOR: ON
9133 23:25:24.543348 HW_SAVE_FOR_SR: OFF
9134 23:25:24.543426 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9135 23:25:24.549753 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9136 23:25:24.549832 Read ODT Tracking: ON
9137 23:25:24.553228 Refresh Rate DeBounce: ON
9138 23:25:24.553305 DFS_NO_QUEUE_FLUSH: ON
9139 23:25:24.556755 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9140 23:25:24.560103 ENABLE_DFS_RUNTIME_MRW: OFF
9141 23:25:24.563208 DDR_RESERVE_NEW_MODE: ON
9142 23:25:24.563281 MR_CBT_SWITCH_FREQ: ON
9143 23:25:24.566456 =========================
9144 23:25:24.585822 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9145 23:25:24.589309 dram_init: ddr_geometry: 2
9146 23:25:24.607596 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9147 23:25:24.610876 dram_init: dram init end (result: 0)
9148 23:25:24.617421 DRAM-K: Full calibration passed in 24483 msecs
9149 23:25:24.620796 MRC: failed to locate region type 0.
9150 23:25:24.620902 DRAM rank0 size:0x100000000,
9151 23:25:24.624191 DRAM rank1 size=0x100000000
9152 23:25:24.634030 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9153 23:25:24.641023 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9154 23:25:24.647616 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9155 23:25:24.654123 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9156 23:25:24.657418 DRAM rank0 size:0x100000000,
9157 23:25:24.660608 DRAM rank1 size=0x100000000
9158 23:25:24.660692 CBMEM:
9159 23:25:24.664073 IMD: root @ 0xfffff000 254 entries.
9160 23:25:24.667500 IMD: root @ 0xffffec00 62 entries.
9161 23:25:24.670892 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9162 23:25:24.673814 WARNING: RO_VPD is uninitialized or empty.
9163 23:25:24.680460 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9164 23:25:24.687388 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9165 23:25:24.700218 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9166 23:25:24.711711 BS: romstage times (exec / console): total (unknown) / 24012 ms
9167 23:25:24.711840
9168 23:25:24.711911
9169 23:25:24.721726 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9170 23:25:24.725049 ARM64: Exception handlers installed.
9171 23:25:24.728117 ARM64: Testing exception
9172 23:25:24.731578 ARM64: Done test exception
9173 23:25:24.731734 Enumerating buses...
9174 23:25:24.735123 Show all devs... Before device enumeration.
9175 23:25:24.738110 Root Device: enabled 1
9176 23:25:24.741602 CPU_CLUSTER: 0: enabled 1
9177 23:25:24.741745 CPU: 00: enabled 1
9178 23:25:24.744698 Compare with tree...
9179 23:25:24.744835 Root Device: enabled 1
9180 23:25:24.748206 CPU_CLUSTER: 0: enabled 1
9181 23:25:24.751578 CPU: 00: enabled 1
9182 23:25:24.751695 Root Device scanning...
9183 23:25:24.754636 scan_static_bus for Root Device
9184 23:25:24.758142 CPU_CLUSTER: 0 enabled
9185 23:25:24.761625 scan_static_bus for Root Device done
9186 23:25:24.764776 scan_bus: bus Root Device finished in 8 msecs
9187 23:25:24.764883 done
9188 23:25:24.771547 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9189 23:25:24.774587 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9190 23:25:24.781517 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9191 23:25:24.784578 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9192 23:25:24.788106 Allocating resources...
9193 23:25:24.791388 Reading resources...
9194 23:25:24.794429 Root Device read_resources bus 0 link: 0
9195 23:25:24.794517 DRAM rank0 size:0x100000000,
9196 23:25:24.797777 DRAM rank1 size=0x100000000
9197 23:25:24.801304 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9198 23:25:24.804708 CPU: 00 missing read_resources
9199 23:25:24.808027 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9200 23:25:24.814387 Root Device read_resources bus 0 link: 0 done
9201 23:25:24.814471 Done reading resources.
9202 23:25:24.821196 Show resources in subtree (Root Device)...After reading.
9203 23:25:24.824356 Root Device child on link 0 CPU_CLUSTER: 0
9204 23:25:24.827560 CPU_CLUSTER: 0 child on link 0 CPU: 00
9205 23:25:24.837553 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9206 23:25:24.837641 CPU: 00
9207 23:25:24.841160 Root Device assign_resources, bus 0 link: 0
9208 23:25:24.844216 CPU_CLUSTER: 0 missing set_resources
9209 23:25:24.851237 Root Device assign_resources, bus 0 link: 0 done
9210 23:25:24.851365 Done setting resources.
9211 23:25:24.857760 Show resources in subtree (Root Device)...After assigning values.
9212 23:25:24.861244 Root Device child on link 0 CPU_CLUSTER: 0
9213 23:25:24.864611 CPU_CLUSTER: 0 child on link 0 CPU: 00
9214 23:25:24.874530 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9215 23:25:24.874617 CPU: 00
9216 23:25:24.877626 Done allocating resources.
9217 23:25:24.881081 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9218 23:25:24.884561 Enabling resources...
9219 23:25:24.884644 done.
9220 23:25:24.891021 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9221 23:25:24.891108 Initializing devices...
9222 23:25:24.894419 Root Device init
9223 23:25:24.894505 init hardware done!
9224 23:25:24.897973 0x00000018: ctrlr->caps
9225 23:25:24.900965 52.000 MHz: ctrlr->f_max
9226 23:25:24.901054 0.400 MHz: ctrlr->f_min
9227 23:25:24.904440 0x40ff8080: ctrlr->voltages
9228 23:25:24.904529 sclk: 390625
9229 23:25:24.907920 Bus Width = 1
9230 23:25:24.908007 sclk: 390625
9231 23:25:24.910755 Bus Width = 1
9232 23:25:24.910841 Early init status = 3
9233 23:25:24.917453 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9234 23:25:24.920929 in-header: 03 fc 00 00 01 00 00 00
9235 23:25:24.921016 in-data: 00
9236 23:25:24.927534 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9237 23:25:24.931131 in-header: 03 fd 00 00 00 00 00 00
9238 23:25:24.934430 in-data:
9239 23:25:24.937490 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9240 23:25:24.941186 in-header: 03 fc 00 00 01 00 00 00
9241 23:25:24.944500 in-data: 00
9242 23:25:24.947679 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9243 23:25:24.953641 in-header: 03 fd 00 00 00 00 00 00
9244 23:25:24.956599 in-data:
9245 23:25:24.959868 [SSUSB] Setting up USB HOST controller...
9246 23:25:24.963313 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9247 23:25:24.966619 [SSUSB] phy power-on done.
9248 23:25:24.970100 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9249 23:25:24.976578 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9250 23:25:24.979703 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9251 23:25:24.986402 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9252 23:25:24.993323 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9253 23:25:25.000102 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9254 23:25:25.006504 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9255 23:25:25.013113 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9256 23:25:25.016545 SPM: binary array size = 0x9dc
9257 23:25:25.020125 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9258 23:25:25.026804 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9259 23:25:25.033247 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9260 23:25:25.036447 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9261 23:25:25.039693 configure_display: Starting display init
9262 23:25:25.076579 anx7625_power_on_init: Init interface.
9263 23:25:25.080078 anx7625_disable_pd_protocol: Disabled PD feature.
9264 23:25:25.083071 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9265 23:25:25.111273 anx7625_start_dp_work: Secure OCM version=00
9266 23:25:25.114653 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9267 23:25:25.129201 sp_tx_get_edid_block: EDID Block = 1
9268 23:25:25.231556 Extracted contents:
9269 23:25:25.235019 header: 00 ff ff ff ff ff ff 00
9270 23:25:25.238325 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9271 23:25:25.241799 version: 01 04
9272 23:25:25.244772 basic params: 95 1f 11 78 0a
9273 23:25:25.248256 chroma info: 76 90 94 55 54 90 27 21 50 54
9274 23:25:25.251567 established: 00 00 00
9275 23:25:25.257946 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9276 23:25:25.261177 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9277 23:25:25.268178 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9278 23:25:25.274613 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9279 23:25:25.281182 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9280 23:25:25.284677 extensions: 00
9281 23:25:25.284760 checksum: fb
9282 23:25:25.284826
9283 23:25:25.287756 Manufacturer: IVO Model 57d Serial Number 0
9284 23:25:25.291270 Made week 0 of 2020
9285 23:25:25.291354 EDID version: 1.4
9286 23:25:25.294276 Digital display
9287 23:25:25.297854 6 bits per primary color channel
9288 23:25:25.297940 DisplayPort interface
9289 23:25:25.301090 Maximum image size: 31 cm x 17 cm
9290 23:25:25.304541 Gamma: 220%
9291 23:25:25.304624 Check DPMS levels
9292 23:25:25.307885 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9293 23:25:25.314529 First detailed timing is preferred timing
9294 23:25:25.314651 Established timings supported:
9295 23:25:25.317928 Standard timings supported:
9296 23:25:25.320868 Detailed timings
9297 23:25:25.324470 Hex of detail: 383680a07038204018303c0035ae10000019
9298 23:25:25.328017 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9299 23:25:25.334600 0780 0798 07c8 0820 hborder 0
9300 23:25:25.337681 0438 043b 0447 0458 vborder 0
9301 23:25:25.341147 -hsync -vsync
9302 23:25:25.341230 Did detailed timing
9303 23:25:25.347592 Hex of detail: 000000000000000000000000000000000000
9304 23:25:25.351115 Manufacturer-specified data, tag 0
9305 23:25:25.354545 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9306 23:25:25.357590 ASCII string: InfoVision
9307 23:25:25.361000 Hex of detail: 000000fe00523134304e574635205248200a
9308 23:25:25.364232 ASCII string: R140NWF5 RH
9309 23:25:25.364337 Checksum
9310 23:25:25.367503 Checksum: 0xfb (valid)
9311 23:25:25.371053 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9312 23:25:25.374069 DSI data_rate: 832800000 bps
9313 23:25:25.380615 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9314 23:25:25.384214 anx7625_parse_edid: pixelclock(138800).
9315 23:25:25.387723 hactive(1920), hsync(48), hfp(24), hbp(88)
9316 23:25:25.390687 vactive(1080), vsync(12), vfp(3), vbp(17)
9317 23:25:25.394143 anx7625_dsi_config: config dsi.
9318 23:25:25.400513 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9319 23:25:25.413690 anx7625_dsi_config: success to config DSI
9320 23:25:25.416859 anx7625_dp_start: MIPI phy setup OK.
9321 23:25:25.420192 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9322 23:25:25.423787 mtk_ddp_mode_set invalid vrefresh 60
9323 23:25:25.426945 main_disp_path_setup
9324 23:25:25.427027 ovl_layer_smi_id_en
9325 23:25:25.430272 ovl_layer_smi_id_en
9326 23:25:25.430380 ccorr_config
9327 23:25:25.430477 aal_config
9328 23:25:25.433684 gamma_config
9329 23:25:25.433766 postmask_config
9330 23:25:25.436946 dither_config
9331 23:25:25.440142 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9332 23:25:25.446653 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9333 23:25:25.450135 Root Device init finished in 553 msecs
9334 23:25:25.453608 CPU_CLUSTER: 0 init
9335 23:25:25.460245 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9336 23:25:25.463629 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9337 23:25:25.466921 APU_MBOX 0x190000b0 = 0x10001
9338 23:25:25.470355 APU_MBOX 0x190001b0 = 0x10001
9339 23:25:25.473646 APU_MBOX 0x190005b0 = 0x10001
9340 23:25:25.476520 APU_MBOX 0x190006b0 = 0x10001
9341 23:25:25.480102 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9342 23:25:25.492842 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9343 23:25:25.505179 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9344 23:25:25.511962 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9345 23:25:25.523195 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9346 23:25:25.532622 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9347 23:25:25.535971 CPU_CLUSTER: 0 init finished in 81 msecs
9348 23:25:25.539374 Devices initialized
9349 23:25:25.542685 Show all devs... After init.
9350 23:25:25.542767 Root Device: enabled 1
9351 23:25:25.545986 CPU_CLUSTER: 0: enabled 1
9352 23:25:25.549202 CPU: 00: enabled 1
9353 23:25:25.552696 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9354 23:25:25.556002 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9355 23:25:25.559000 ELOG: NV offset 0x57f000 size 0x1000
9356 23:25:25.565647 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9357 23:25:25.572103 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9358 23:25:25.575735 ELOG: Event(17) added with size 13 at 2024-04-03 23:22:31 UTC
9359 23:25:25.579122 out: cmd=0x121: 03 db 21 01 00 00 00 00
9360 23:25:25.582940 in-header: 03 c3 00 00 2c 00 00 00
9361 23:25:25.596408 in-data: 9c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9362 23:25:25.602962 ELOG: Event(A1) added with size 10 at 2024-04-03 23:22:31 UTC
9363 23:25:25.609375 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9364 23:25:25.616226 ELOG: Event(A0) added with size 9 at 2024-04-03 23:22:31 UTC
9365 23:25:25.619333 elog_add_boot_reason: Logged dev mode boot
9366 23:25:25.622764 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9367 23:25:25.626039 Finalize devices...
9368 23:25:25.626125 Devices finalized
9369 23:25:25.632440 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9370 23:25:25.635738 Writing coreboot table at 0xffe64000
9371 23:25:25.639309 0. 000000000010a000-0000000000113fff: RAMSTAGE
9372 23:25:25.642437 1. 0000000040000000-00000000400fffff: RAM
9373 23:25:25.649085 2. 0000000040100000-000000004032afff: RAMSTAGE
9374 23:25:25.652502 3. 000000004032b000-00000000545fffff: RAM
9375 23:25:25.655639 4. 0000000054600000-000000005465ffff: BL31
9376 23:25:25.659161 5. 0000000054660000-00000000ffe63fff: RAM
9377 23:25:25.665999 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9378 23:25:25.669122 7. 0000000100000000-000000023fffffff: RAM
9379 23:25:25.669253 Passing 5 GPIOs to payload:
9380 23:25:25.675686 NAME | PORT | POLARITY | VALUE
9381 23:25:25.679058 EC in RW | 0x000000aa | low | undefined
9382 23:25:25.685677 EC interrupt | 0x00000005 | low | undefined
9383 23:25:25.689111 TPM interrupt | 0x000000ab | high | undefined
9384 23:25:25.692459 SD card detect | 0x00000011 | high | undefined
9385 23:25:25.698733 speaker enable | 0x00000093 | high | undefined
9386 23:25:25.702279 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9387 23:25:25.705722 in-header: 03 f9 00 00 02 00 00 00
9388 23:25:25.705845 in-data: 02 00
9389 23:25:25.708693 ADC[4]: Raw value=904357 ID=7
9390 23:25:25.712457 ADC[3]: Raw value=213441 ID=1
9391 23:25:25.712583 RAM Code: 0x71
9392 23:25:25.715393 ADC[6]: Raw value=75701 ID=0
9393 23:25:25.718700 ADC[5]: Raw value=213072 ID=1
9394 23:25:25.718824 SKU Code: 0x1
9395 23:25:25.725385 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 6fab
9396 23:25:25.728869 coreboot table: 964 bytes.
9397 23:25:25.731938 IMD ROOT 0. 0xfffff000 0x00001000
9398 23:25:25.735624 IMD SMALL 1. 0xffffe000 0x00001000
9399 23:25:25.738745 RO MCACHE 2. 0xffffc000 0x00001104
9400 23:25:25.742080 CONSOLE 3. 0xfff7c000 0x00080000
9401 23:25:25.745309 FMAP 4. 0xfff7b000 0x00000452
9402 23:25:25.748493 TIME STAMP 5. 0xfff7a000 0x00000910
9403 23:25:25.751919 VBOOT WORK 6. 0xfff66000 0x00014000
9404 23:25:25.755150 RAMOOPS 7. 0xffe66000 0x00100000
9405 23:25:25.758643 COREBOOT 8. 0xffe64000 0x00002000
9406 23:25:25.758726 IMD small region:
9407 23:25:25.761974 IMD ROOT 0. 0xffffec00 0x00000400
9408 23:25:25.765355 VPD 1. 0xffffeb80 0x0000006c
9409 23:25:25.768386 MMC STATUS 2. 0xffffeb60 0x00000004
9410 23:25:25.775456 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9411 23:25:25.778589 Probing TPM: done!
9412 23:25:25.781930 Connected to device vid:did:rid of 1ae0:0028:00
9413 23:25:25.791766 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9414 23:25:25.795353 Initialized TPM device CR50 revision 0
9415 23:25:25.799293 Checking cr50 for pending updates
9416 23:25:25.802544 Reading cr50 TPM mode
9417 23:25:25.811112 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9418 23:25:25.817463 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9419 23:25:25.857819 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9420 23:25:25.861112 Checking segment from ROM address 0x40100000
9421 23:25:25.864237 Checking segment from ROM address 0x4010001c
9422 23:25:25.871228 Loading segment from ROM address 0x40100000
9423 23:25:25.871351 code (compression=0)
9424 23:25:25.878046 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9425 23:25:25.887991 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9426 23:25:25.888107 it's not compressed!
9427 23:25:25.894553 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9428 23:25:25.897616 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9429 23:25:25.918066 Loading segment from ROM address 0x4010001c
9430 23:25:25.918160 Entry Point 0x80000000
9431 23:25:25.921412 Loaded segments
9432 23:25:25.924995 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9433 23:25:25.931445 Jumping to boot code at 0x80000000(0xffe64000)
9434 23:25:25.938053 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9435 23:25:25.944722 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9436 23:25:25.952762 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9437 23:25:25.955860 Checking segment from ROM address 0x40100000
9438 23:25:25.959604 Checking segment from ROM address 0x4010001c
9439 23:25:25.966116 Loading segment from ROM address 0x40100000
9440 23:25:25.966202 code (compression=1)
9441 23:25:25.972793 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9442 23:25:25.982586 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9443 23:25:25.982727 using LZMA
9444 23:25:25.990969 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9445 23:25:25.997753 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9446 23:25:26.001004 Loading segment from ROM address 0x4010001c
9447 23:25:26.001136 Entry Point 0x54601000
9448 23:25:26.004370 Loaded segments
9449 23:25:26.007493 NOTICE: MT8192 bl31_setup
9450 23:25:26.014740 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9451 23:25:26.017916 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9452 23:25:26.021209 WARNING: region 0:
9453 23:25:26.024523 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 23:25:26.024651 WARNING: region 1:
9455 23:25:26.031238 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9456 23:25:26.034629 WARNING: region 2:
9457 23:25:26.038215 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9458 23:25:26.041296 WARNING: region 3:
9459 23:25:26.044800 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 23:25:26.048225 WARNING: region 4:
9461 23:25:26.051602 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9462 23:25:26.054920 WARNING: region 5:
9463 23:25:26.057939 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 23:25:26.061443 WARNING: region 6:
9465 23:25:26.064864 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 23:25:26.064991 WARNING: region 7:
9467 23:25:26.071539 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 23:25:26.078387 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9469 23:25:26.081481 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9470 23:25:26.084971 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9471 23:25:26.091745 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9472 23:25:26.095059 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9473 23:25:26.098405 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9474 23:25:26.104798 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9475 23:25:26.108136 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9476 23:25:26.111541 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9477 23:25:26.118561 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9478 23:25:26.121734 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9479 23:25:26.125117 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9480 23:25:26.131501 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9481 23:25:26.134838 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9482 23:25:26.141622 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9483 23:25:26.144878 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9484 23:25:26.148230 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9485 23:25:26.155092 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9486 23:25:26.158404 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9487 23:25:26.161787 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9488 23:25:26.168546 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9489 23:25:26.172027 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9490 23:25:26.178498 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9491 23:25:26.181955 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9492 23:25:26.185427 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9493 23:25:26.192129 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9494 23:25:26.195123 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9495 23:25:26.202100 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9496 23:25:26.205397 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9497 23:25:26.208685 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9498 23:25:26.215374 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9499 23:25:26.218646 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9500 23:25:26.222145 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9501 23:25:26.228607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9502 23:25:26.232106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9503 23:25:26.235631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9504 23:25:26.239002 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9505 23:25:26.242361 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9506 23:25:26.248993 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9507 23:25:26.252356 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9508 23:25:26.255566 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9509 23:25:26.259076 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9510 23:25:26.265433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9511 23:25:26.268865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9512 23:25:26.272195 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9513 23:25:26.275596 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9514 23:25:26.282464 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9515 23:25:26.285831 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9516 23:25:26.288847 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9517 23:25:26.295597 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9518 23:25:26.299109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9519 23:25:26.305628 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9520 23:25:26.309092 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9521 23:25:26.312590 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9522 23:25:26.319112 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9523 23:25:26.322438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9524 23:25:26.329120 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9525 23:25:26.332483 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9526 23:25:26.339050 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9527 23:25:26.342286 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9528 23:25:26.345901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9529 23:25:26.352485 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9530 23:25:26.355734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9531 23:25:26.362283 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9532 23:25:26.365851 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9533 23:25:26.372398 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9534 23:25:26.375763 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9535 23:25:26.382193 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9536 23:25:26.385715 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9537 23:25:26.389104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9538 23:25:26.395554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9539 23:25:26.398978 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9540 23:25:26.405892 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9541 23:25:26.409011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9542 23:25:26.415974 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9543 23:25:26.419112 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9544 23:25:26.422505 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9545 23:25:26.429067 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9546 23:25:26.432655 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9547 23:25:26.439143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9548 23:25:26.442436 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9549 23:25:26.449012 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9550 23:25:26.452405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9551 23:25:26.455771 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9552 23:25:26.462240 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9553 23:25:26.465693 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9554 23:25:26.472553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9555 23:25:26.475959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9556 23:25:26.482431 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9557 23:25:26.485827 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9558 23:25:26.489118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9559 23:25:26.495962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9560 23:25:26.499282 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9561 23:25:26.505893 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9562 23:25:26.509202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9563 23:25:26.516146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9564 23:25:26.519127 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9565 23:25:26.522565 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9566 23:25:26.526081 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9567 23:25:26.532493 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9568 23:25:26.535915 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9569 23:25:26.539420 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9570 23:25:26.545949 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9571 23:25:26.549367 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9572 23:25:26.552802 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9573 23:25:26.559297 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9574 23:25:26.562763 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9575 23:25:26.569120 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9576 23:25:26.572834 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9577 23:25:26.576143 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9578 23:25:26.582837 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9579 23:25:26.585977 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9580 23:25:26.592489 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9581 23:25:26.595933 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9582 23:25:26.599343 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9583 23:25:26.606105 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9584 23:25:26.609270 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9585 23:25:26.612492 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9586 23:25:26.619225 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9587 23:25:26.622676 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9588 23:25:26.626121 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9589 23:25:26.629195 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9590 23:25:26.632720 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9591 23:25:26.639329 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9592 23:25:26.642750 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9593 23:25:26.649611 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9594 23:25:26.652567 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9595 23:25:26.656039 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9596 23:25:26.663015 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9597 23:25:26.666154 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9598 23:25:26.669715 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9599 23:25:26.676118 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9600 23:25:26.679385 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9601 23:25:26.686221 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9602 23:25:26.689507 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9603 23:25:26.692744 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9604 23:25:26.699549 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9605 23:25:26.702836 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9606 23:25:26.709444 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9607 23:25:26.712720 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9608 23:25:26.716261 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9609 23:25:26.722763 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9610 23:25:26.726092 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9611 23:25:26.733038 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9612 23:25:26.736389 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9613 23:25:26.739554 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9614 23:25:26.746278 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9615 23:25:26.749798 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9616 23:25:26.752976 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9617 23:25:26.759719 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9618 23:25:26.762796 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9619 23:25:26.769649 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9620 23:25:26.772700 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9621 23:25:26.775917 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9622 23:25:26.783038 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9623 23:25:26.786394 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9624 23:25:26.789837 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9625 23:25:26.796142 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9626 23:25:26.799568 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9627 23:25:26.806403 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9628 23:25:26.809296 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9629 23:25:26.812832 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9630 23:25:26.819409 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9631 23:25:26.822641 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9632 23:25:26.829085 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9633 23:25:26.832455 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9634 23:25:26.835895 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9635 23:25:26.842391 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9636 23:25:26.845946 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9637 23:25:26.852598 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9638 23:25:26.855672 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9639 23:25:26.859121 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9640 23:25:26.865800 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9641 23:25:26.869147 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9642 23:25:26.875578 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9643 23:25:26.879086 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9644 23:25:26.882585 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9645 23:25:26.888925 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9646 23:25:26.892298 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9647 23:25:26.895702 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9648 23:25:26.902494 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9649 23:25:26.905757 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9650 23:25:26.912256 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9651 23:25:26.915790 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9652 23:25:26.918873 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9653 23:25:26.925596 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9654 23:25:26.928725 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9655 23:25:26.935609 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9656 23:25:26.938805 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9657 23:25:26.945499 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9658 23:25:26.948958 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9659 23:25:26.952016 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9660 23:25:26.958506 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9661 23:25:26.961843 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9662 23:25:26.968518 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9663 23:25:26.971929 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9664 23:25:26.975231 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9665 23:25:26.982001 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9666 23:25:26.985157 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9667 23:25:26.991869 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9668 23:25:26.994902 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9669 23:25:27.001869 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9670 23:25:27.005199 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9671 23:25:27.008364 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9672 23:25:27.015071 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9673 23:25:27.018209 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9674 23:25:27.025082 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9675 23:25:27.028467 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9676 23:25:27.031982 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9677 23:25:27.038297 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9678 23:25:27.041671 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9679 23:25:27.047941 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9680 23:25:27.051461 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9681 23:25:27.058108 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9682 23:25:27.061684 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9683 23:25:27.064763 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9684 23:25:27.071438 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9685 23:25:27.074724 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9686 23:25:27.081081 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9687 23:25:27.084570 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9688 23:25:27.091476 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9689 23:25:27.094735 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9690 23:25:27.097836 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9691 23:25:27.104790 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9692 23:25:27.107895 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9693 23:25:27.114590 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9694 23:25:27.117864 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9695 23:25:27.121218 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9696 23:25:27.127878 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9697 23:25:27.130942 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9698 23:25:27.134316 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9699 23:25:27.137729 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9700 23:25:27.144466 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9701 23:25:27.147557 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9702 23:25:27.151011 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9703 23:25:27.157538 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9704 23:25:27.161086 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9705 23:25:27.164463 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9706 23:25:27.170904 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9707 23:25:27.174364 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9708 23:25:27.177713 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9709 23:25:27.184178 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9710 23:25:27.187741 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9711 23:25:27.191217 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9712 23:25:27.197589 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9713 23:25:27.200974 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9714 23:25:27.207597 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9715 23:25:27.210671 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9716 23:25:27.214027 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9717 23:25:27.220536 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9718 23:25:27.223934 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9719 23:25:27.230835 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9720 23:25:27.234026 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9721 23:25:27.237171 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9722 23:25:27.243977 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9723 23:25:27.247109 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9724 23:25:27.250374 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9725 23:25:27.257205 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9726 23:25:27.260345 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9727 23:25:27.263670 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9728 23:25:27.270303 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9729 23:25:27.273636 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9730 23:25:27.280534 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9731 23:25:27.283534 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9732 23:25:27.287045 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9733 23:25:27.293516 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9734 23:25:27.297040 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9735 23:25:27.300485 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9736 23:25:27.306958 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9737 23:25:27.310352 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9738 23:25:27.313339 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9739 23:25:27.316752 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9740 23:25:27.323587 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9741 23:25:27.326613 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9742 23:25:27.330023 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9743 23:25:27.333310 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9744 23:25:27.339851 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9745 23:25:27.343192 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9746 23:25:27.346629 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9747 23:25:27.350047 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9748 23:25:27.356696 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9749 23:25:27.360187 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9750 23:25:27.363380 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9751 23:25:27.369749 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9752 23:25:27.373317 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9753 23:25:27.379770 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9754 23:25:27.383178 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9755 23:25:27.386504 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9756 23:25:27.393032 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9757 23:25:27.396647 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9758 23:25:27.402943 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9759 23:25:27.406533 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9760 23:25:27.409958 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9761 23:25:27.416643 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9762 23:25:27.419676 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9763 23:25:27.426599 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9764 23:25:27.429678 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9765 23:25:27.433130 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9766 23:25:27.439561 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9767 23:25:27.443033 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9768 23:25:27.449830 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9769 23:25:27.452911 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9770 23:25:27.459877 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9771 23:25:27.462877 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9772 23:25:27.466346 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9773 23:25:27.473145 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9774 23:25:27.476106 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9775 23:25:27.482667 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9776 23:25:27.486171 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9777 23:25:27.489462 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9778 23:25:27.496028 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9779 23:25:27.499601 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9780 23:25:27.506054 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9781 23:25:27.509531 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9782 23:25:27.512893 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9783 23:25:27.519241 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9784 23:25:27.522589 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9785 23:25:27.529156 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9786 23:25:27.532601 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9787 23:25:27.539075 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9788 23:25:27.542575 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9789 23:25:27.545924 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9790 23:25:27.552371 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9791 23:25:27.555736 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9792 23:25:27.562141 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9793 23:25:27.565645 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9794 23:25:27.569057 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9795 23:25:27.575529 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9796 23:25:27.578755 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9797 23:25:27.585335 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9798 23:25:27.588767 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9799 23:25:27.591866 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9800 23:25:27.598658 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9801 23:25:27.602003 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9802 23:25:27.608652 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9803 23:25:27.612065 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9804 23:25:27.618663 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9805 23:25:27.622177 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9806 23:25:27.625483 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9807 23:25:27.631951 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9808 23:25:27.635319 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9809 23:25:27.641900 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9810 23:25:27.645438 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9811 23:25:27.648565 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9812 23:25:27.655120 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9813 23:25:27.658484 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9814 23:25:27.665069 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9815 23:25:27.668594 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9816 23:25:27.672059 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9817 23:25:27.678578 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9818 23:25:27.681893 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9819 23:25:27.688484 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9820 23:25:27.691565 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9821 23:25:27.694936 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9822 23:25:27.701463 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9823 23:25:27.704827 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9824 23:25:27.711570 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9825 23:25:27.714749 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9826 23:25:27.721401 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9827 23:25:27.724726 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9828 23:25:27.731729 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9829 23:25:27.735042 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9830 23:25:27.738073 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9831 23:25:27.744683 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9832 23:25:27.748416 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9833 23:25:27.754939 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9834 23:25:27.758118 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9835 23:25:27.764782 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9836 23:25:27.768029 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9837 23:25:27.771337 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9838 23:25:27.778244 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9839 23:25:27.781202 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9840 23:25:27.787857 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9841 23:25:27.791254 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9842 23:25:27.798091 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9843 23:25:27.801226 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9844 23:25:27.808137 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9845 23:25:27.811167 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9846 23:25:27.814435 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9847 23:25:27.821146 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9848 23:25:27.824504 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9849 23:25:27.831129 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9850 23:25:27.834508 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9851 23:25:27.840924 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9852 23:25:27.844222 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9853 23:25:27.847727 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9854 23:25:27.854433 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9855 23:25:27.857780 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9856 23:25:27.864101 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9857 23:25:27.867915 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9858 23:25:27.874411 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9859 23:25:27.877444 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9860 23:25:27.880923 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9861 23:25:27.887430 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9862 23:25:27.891060 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9863 23:25:27.897415 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9864 23:25:27.900793 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9865 23:25:27.907318 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9866 23:25:27.910602 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9867 23:25:27.914105 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9868 23:25:27.920539 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9869 23:25:27.924055 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9870 23:25:27.930682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9871 23:25:27.933849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9872 23:25:27.937473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9873 23:25:27.943943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9874 23:25:27.947268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9875 23:25:27.953927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9876 23:25:27.957383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9877 23:25:27.963773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9878 23:25:27.967130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9879 23:25:27.974073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9880 23:25:27.977135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9881 23:25:27.984042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9882 23:25:27.987258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9883 23:25:27.993807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9884 23:25:27.997196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9885 23:25:28.003784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9886 23:25:28.006875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9887 23:25:28.013918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9888 23:25:28.017333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9889 23:25:28.023951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9890 23:25:28.027111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9891 23:25:28.034065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9892 23:25:28.037193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9893 23:25:28.043709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9894 23:25:28.047228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9895 23:25:28.053352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9896 23:25:28.056826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9897 23:25:28.063468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9898 23:25:28.066908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9899 23:25:28.073628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9900 23:25:28.076782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9901 23:25:28.083584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9902 23:25:28.087057 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9903 23:25:28.090103 INFO: [APUAPC] vio 0
9904 23:25:28.093594 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9905 23:25:28.096962 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9906 23:25:28.099893 INFO: [APUAPC] D0_APC_0: 0x400510
9907 23:25:28.103203 INFO: [APUAPC] D0_APC_1: 0x0
9908 23:25:28.106812 INFO: [APUAPC] D0_APC_2: 0x1540
9909 23:25:28.110138 INFO: [APUAPC] D0_APC_3: 0x0
9910 23:25:28.113467 INFO: [APUAPC] D1_APC_0: 0xffffffff
9911 23:25:28.116610 INFO: [APUAPC] D1_APC_1: 0xffffffff
9912 23:25:28.119836 INFO: [APUAPC] D1_APC_2: 0x3fffff
9913 23:25:28.123422 INFO: [APUAPC] D1_APC_3: 0x0
9914 23:25:28.126541 INFO: [APUAPC] D2_APC_0: 0xffffffff
9915 23:25:28.129662 INFO: [APUAPC] D2_APC_1: 0xffffffff
9916 23:25:28.133241 INFO: [APUAPC] D2_APC_2: 0x3fffff
9917 23:25:28.136618 INFO: [APUAPC] D2_APC_3: 0x0
9918 23:25:28.139580 INFO: [APUAPC] D3_APC_0: 0xffffffff
9919 23:25:28.143086 INFO: [APUAPC] D3_APC_1: 0xffffffff
9920 23:25:28.146517 INFO: [APUAPC] D3_APC_2: 0x3fffff
9921 23:25:28.149947 INFO: [APUAPC] D3_APC_3: 0x0
9922 23:25:28.153020 INFO: [APUAPC] D4_APC_0: 0xffffffff
9923 23:25:28.156468 INFO: [APUAPC] D4_APC_1: 0xffffffff
9924 23:25:28.159733 INFO: [APUAPC] D4_APC_2: 0x3fffff
9925 23:25:28.162872 INFO: [APUAPC] D4_APC_3: 0x0
9926 23:25:28.166485 INFO: [APUAPC] D5_APC_0: 0xffffffff
9927 23:25:28.169721 INFO: [APUAPC] D5_APC_1: 0xffffffff
9928 23:25:28.172881 INFO: [APUAPC] D5_APC_2: 0x3fffff
9929 23:25:28.176367 INFO: [APUAPC] D5_APC_3: 0x0
9930 23:25:28.179698 INFO: [APUAPC] D6_APC_0: 0xffffffff
9931 23:25:28.183093 INFO: [APUAPC] D6_APC_1: 0xffffffff
9932 23:25:28.186062 INFO: [APUAPC] D6_APC_2: 0x3fffff
9933 23:25:28.189503 INFO: [APUAPC] D6_APC_3: 0x0
9934 23:25:28.193092 INFO: [APUAPC] D7_APC_0: 0xffffffff
9935 23:25:28.196170 INFO: [APUAPC] D7_APC_1: 0xffffffff
9936 23:25:28.199551 INFO: [APUAPC] D7_APC_2: 0x3fffff
9937 23:25:28.202562 INFO: [APUAPC] D7_APC_3: 0x0
9938 23:25:28.205980 INFO: [APUAPC] D8_APC_0: 0xffffffff
9939 23:25:28.209195 INFO: [APUAPC] D8_APC_1: 0xffffffff
9940 23:25:28.212620 INFO: [APUAPC] D8_APC_2: 0x3fffff
9941 23:25:28.216056 INFO: [APUAPC] D8_APC_3: 0x0
9942 23:25:28.219409 INFO: [APUAPC] D9_APC_0: 0xffffffff
9943 23:25:28.222367 INFO: [APUAPC] D9_APC_1: 0xffffffff
9944 23:25:28.225787 INFO: [APUAPC] D9_APC_2: 0x3fffff
9945 23:25:28.225867 INFO: [APUAPC] D9_APC_3: 0x0
9946 23:25:28.232264 INFO: [APUAPC] D10_APC_0: 0xffffffff
9947 23:25:28.235799 INFO: [APUAPC] D10_APC_1: 0xffffffff
9948 23:25:28.239273 INFO: [APUAPC] D10_APC_2: 0x3fffff
9949 23:25:28.239355 INFO: [APUAPC] D10_APC_3: 0x0
9950 23:25:28.245719 INFO: [APUAPC] D11_APC_0: 0xffffffff
9951 23:25:28.248838 INFO: [APUAPC] D11_APC_1: 0xffffffff
9952 23:25:28.252332 INFO: [APUAPC] D11_APC_2: 0x3fffff
9953 23:25:28.255833 INFO: [APUAPC] D11_APC_3: 0x0
9954 23:25:28.258943 INFO: [APUAPC] D12_APC_0: 0xffffffff
9955 23:25:28.262045 INFO: [APUAPC] D12_APC_1: 0xffffffff
9956 23:25:28.265442 INFO: [APUAPC] D12_APC_2: 0x3fffff
9957 23:25:28.268796 INFO: [APUAPC] D12_APC_3: 0x0
9958 23:25:28.272321 INFO: [APUAPC] D13_APC_0: 0xffffffff
9959 23:25:28.275582 INFO: [APUAPC] D13_APC_1: 0xffffffff
9960 23:25:28.278685 INFO: [APUAPC] D13_APC_2: 0x3fffff
9961 23:25:28.282035 INFO: [APUAPC] D13_APC_3: 0x0
9962 23:25:28.285472 INFO: [APUAPC] D14_APC_0: 0xffffffff
9963 23:25:28.288724 INFO: [APUAPC] D14_APC_1: 0xffffffff
9964 23:25:28.291974 INFO: [APUAPC] D14_APC_2: 0x3fffff
9965 23:25:28.295205 INFO: [APUAPC] D14_APC_3: 0x0
9966 23:25:28.298643 INFO: [APUAPC] D15_APC_0: 0xffffffff
9967 23:25:28.302135 INFO: [APUAPC] D15_APC_1: 0xffffffff
9968 23:25:28.305217 INFO: [APUAPC] D15_APC_2: 0x3fffff
9969 23:25:28.308742 INFO: [APUAPC] D15_APC_3: 0x0
9970 23:25:28.311763 INFO: [APUAPC] APC_CON: 0x4
9971 23:25:28.311847 INFO: [NOCDAPC] D0_APC_0: 0x0
9972 23:25:28.315269 INFO: [NOCDAPC] D0_APC_1: 0x0
9973 23:25:28.318455 INFO: [NOCDAPC] D1_APC_0: 0x0
9974 23:25:28.321702 INFO: [NOCDAPC] D1_APC_1: 0xfff
9975 23:25:28.325059 INFO: [NOCDAPC] D2_APC_0: 0x0
9976 23:25:28.328542 INFO: [NOCDAPC] D2_APC_1: 0xfff
9977 23:25:28.331574 INFO: [NOCDAPC] D3_APC_0: 0x0
9978 23:25:28.335131 INFO: [NOCDAPC] D3_APC_1: 0xfff
9979 23:25:28.338549 INFO: [NOCDAPC] D4_APC_0: 0x0
9980 23:25:28.341871 INFO: [NOCDAPC] D4_APC_1: 0xfff
9981 23:25:28.341955 INFO: [NOCDAPC] D5_APC_0: 0x0
9982 23:25:28.344902 INFO: [NOCDAPC] D5_APC_1: 0xfff
9983 23:25:28.348024 INFO: [NOCDAPC] D6_APC_0: 0x0
9984 23:25:28.351570 INFO: [NOCDAPC] D6_APC_1: 0xfff
9985 23:25:28.354778 INFO: [NOCDAPC] D7_APC_0: 0x0
9986 23:25:28.358257 INFO: [NOCDAPC] D7_APC_1: 0xfff
9987 23:25:28.361653 INFO: [NOCDAPC] D8_APC_0: 0x0
9988 23:25:28.364662 INFO: [NOCDAPC] D8_APC_1: 0xfff
9989 23:25:28.368167 INFO: [NOCDAPC] D9_APC_0: 0x0
9990 23:25:28.371600 INFO: [NOCDAPC] D9_APC_1: 0xfff
9991 23:25:28.374694 INFO: [NOCDAPC] D10_APC_0: 0x0
9992 23:25:28.378042 INFO: [NOCDAPC] D10_APC_1: 0xfff
9993 23:25:28.378146 INFO: [NOCDAPC] D11_APC_0: 0x0
9994 23:25:28.381659 INFO: [NOCDAPC] D11_APC_1: 0xfff
9995 23:25:28.384955 INFO: [NOCDAPC] D12_APC_0: 0x0
9996 23:25:28.388202 INFO: [NOCDAPC] D12_APC_1: 0xfff
9997 23:25:28.391768 INFO: [NOCDAPC] D13_APC_0: 0x0
9998 23:25:28.394973 INFO: [NOCDAPC] D13_APC_1: 0xfff
9999 23:25:28.398174 INFO: [NOCDAPC] D14_APC_0: 0x0
10000 23:25:28.401319 INFO: [NOCDAPC] D14_APC_1: 0xfff
10001 23:25:28.404748 INFO: [NOCDAPC] D15_APC_0: 0x0
10002 23:25:28.407955 INFO: [NOCDAPC] D15_APC_1: 0xfff
10003 23:25:28.411417 INFO: [NOCDAPC] APC_CON: 0x4
10004 23:25:28.414552 INFO: [APUAPC] set_apusys_apc done
10005 23:25:28.418133 INFO: [DEVAPC] devapc_init done
10006 23:25:28.421521 INFO: GICv3 without legacy support detected.
10007 23:25:28.424509 INFO: ARM GICv3 driver initialized in EL3
10008 23:25:28.428082 INFO: Maximum SPI INTID supported: 639
10009 23:25:28.431254 INFO: BL31: Initializing runtime services
10010 23:25:28.437991 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10011 23:25:28.441037 INFO: SPM: enable CPC mode
10012 23:25:28.448126 INFO: mcdi ready for mcusys-off-idle and system suspend
10013 23:25:28.451358 INFO: BL31: Preparing for EL3 exit to normal world
10014 23:25:28.454491 INFO: Entry point address = 0x80000000
10015 23:25:28.457607 INFO: SPSR = 0x8
10016 23:25:28.462533
10017 23:25:28.462622
10018 23:25:28.462726
10019 23:25:28.465770 Starting depthcharge on Spherion...
10020 23:25:28.465854
10021 23:25:28.465932 Wipe memory regions:
10022 23:25:28.466041
10023 23:25:28.466930 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10024 23:25:28.467063 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10025 23:25:28.467176 Setting prompt string to ['asurada:']
10026 23:25:28.467285 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10027 23:25:28.469181 [0x00000040000000, 0x00000054600000)
10028 23:25:28.591714
10029 23:25:28.591842 [0x00000054660000, 0x00000080000000)
10030 23:25:28.852138
10031 23:25:28.852334 [0x000000821a7280, 0x000000ffe64000)
10032 23:25:29.597066
10033 23:25:29.597204 [0x00000100000000, 0x00000240000000)
10034 23:25:31.487875
10035 23:25:31.491007 Initializing XHCI USB controller at 0x11200000.
10036 23:25:32.528879
10037 23:25:32.531801 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10038 23:25:32.531891
10039 23:25:32.531956
10040 23:25:32.532016
10041 23:25:32.532312 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10043 23:25:32.632652 asurada: tftpboot 192.168.201.1 13248445/tftp-deploy-wwg_t9yx/kernel/image.itb 13248445/tftp-deploy-wwg_t9yx/kernel/cmdline
10044 23:25:32.632854 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10045 23:25:32.632976 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10046 23:25:32.637077 tftpboot 192.168.201.1 13248445/tftp-deploy-wwg_t9yx/kernel/image.ittp-deploy-wwg_t9yx/kernel/cmdline
10047 23:25:32.637183
10048 23:25:32.637276 Waiting for link
10049 23:25:32.797234
10050 23:25:32.797398 R8152: Initializing
10051 23:25:32.797499
10052 23:25:32.800520 Version 9 (ocp_data = 6010)
10053 23:25:32.800627
10054 23:25:32.803817 R8152: Done initializing
10055 23:25:32.803923
10056 23:25:32.804016 Adding net device
10057 23:25:34.677015
10058 23:25:34.677213 done.
10059 23:25:34.677333
10060 23:25:34.677449 MAC: 00:e0:4c:78:7a:aa
10061 23:25:34.677563
10062 23:25:34.680566 Sending DHCP discover... done.
10063 23:25:34.680668
10064 23:25:34.683949 Waiting for reply... done.
10065 23:25:34.684081
10066 23:25:34.687235 Sending DHCP request... done.
10067 23:25:34.687344
10068 23:25:34.687444 Waiting for reply... done.
10069 23:25:34.687527
10070 23:25:34.690300 My ip is 192.168.201.12
10071 23:25:34.690397
10072 23:25:34.693878 The DHCP server ip is 192.168.201.1
10073 23:25:34.693979
10074 23:25:34.697259 TFTP server IP predefined by user: 192.168.201.1
10075 23:25:34.697350
10076 23:25:34.703551 Bootfile predefined by user: 13248445/tftp-deploy-wwg_t9yx/kernel/image.itb
10077 23:25:34.703662
10078 23:25:34.706932 Sending tftp read request... done.
10079 23:25:34.707018
10080 23:25:34.710383 Waiting for the transfer...
10081 23:25:34.710479
10082 23:25:34.969299 00000000 ################################################################
10083 23:25:34.969455
10084 23:25:35.222284 00080000 ################################################################
10085 23:25:35.222431
10086 23:25:35.477070 00100000 ################################################################
10087 23:25:35.477226
10088 23:25:35.729881 00180000 ################################################################
10089 23:25:35.730056
10090 23:25:35.992389 00200000 ################################################################
10091 23:25:35.992572
10092 23:25:36.254672 00280000 ################################################################
10093 23:25:36.254855
10094 23:25:36.514237 00300000 ################################################################
10095 23:25:36.514414
10096 23:25:36.782298 00380000 ################################################################
10097 23:25:36.782453
10098 23:25:37.047273 00400000 ################################################################
10099 23:25:37.047433
10100 23:25:37.299045 00480000 ################################################################
10101 23:25:37.299267
10102 23:25:37.550238 00500000 ################################################################
10103 23:25:37.550419
10104 23:25:37.803568 00580000 ################################################################
10105 23:25:37.803756
10106 23:25:38.056160 00600000 ################################################################
10107 23:25:38.056392
10108 23:25:38.308916 00680000 ################################################################
10109 23:25:38.309066
10110 23:25:38.562106 00700000 ################################################################
10111 23:25:38.562321
10112 23:25:38.821415 00780000 ################################################################
10113 23:25:38.821596
10114 23:25:39.071374 00800000 ################################################################
10115 23:25:39.071522
10116 23:25:39.328468 00880000 ################################################################
10117 23:25:39.328622
10118 23:25:39.589932 00900000 ################################################################
10119 23:25:39.590144
10120 23:25:39.843332 00980000 ################################################################
10121 23:25:39.843545
10122 23:25:40.094051 00a00000 ################################################################
10123 23:25:40.094269
10124 23:25:40.344382 00a80000 ################################################################
10125 23:25:40.344583
10126 23:25:40.607012 00b00000 ################################################################
10127 23:25:40.607167
10128 23:25:40.859807 00b80000 ################################################################
10129 23:25:40.859965
10130 23:25:41.110359 00c00000 ################################################################
10131 23:25:41.110520
10132 23:25:41.360574 00c80000 ################################################################
10133 23:25:41.360725
10134 23:25:41.615409 00d00000 ################################################################
10135 23:25:41.615626
10136 23:25:41.878825 00d80000 ################################################################
10137 23:25:41.879007
10138 23:25:42.134670 00e00000 ################################################################
10139 23:25:42.134865
10140 23:25:42.388025 00e80000 ################################################################
10141 23:25:42.388229
10142 23:25:42.645615 00f00000 ################################################################
10143 23:25:42.645827
10144 23:25:42.899580 00f80000 ################################################################
10145 23:25:42.899716
10146 23:25:43.160915 01000000 ################################################################
10147 23:25:43.161118
10148 23:25:43.415913 01080000 ################################################################
10149 23:25:43.416089
10150 23:25:43.677135 01100000 ################################################################
10151 23:25:43.677293
10152 23:25:43.935231 01180000 ################################################################
10153 23:25:43.935422
10154 23:25:44.182878 01200000 ################################################################
10155 23:25:44.183095
10156 23:25:44.432293 01280000 ################################################################
10157 23:25:44.432466
10158 23:25:44.682588 01300000 ################################################################
10159 23:25:44.682795
10160 23:25:44.934759 01380000 ################################################################
10161 23:25:44.934896
10162 23:25:45.185860 01400000 ################################################################
10163 23:25:45.186031
10164 23:25:45.441628 01480000 ################################################################
10165 23:25:45.441793
10166 23:25:45.695217 01500000 ################################################################
10167 23:25:45.695422
10168 23:25:45.946016 01580000 ################################################################
10169 23:25:45.946192
10170 23:25:46.199076 01600000 ################################################################
10171 23:25:46.199266
10172 23:25:46.453620 01680000 ################################################################
10173 23:25:46.453756
10174 23:25:46.709927 01700000 ################################################################
10175 23:25:46.710104
10176 23:25:46.961236 01780000 ################################################################
10177 23:25:46.961369
10178 23:25:47.212191 01800000 ################################################################
10179 23:25:47.212372
10180 23:25:47.461670 01880000 ################################################################
10181 23:25:47.461868
10182 23:25:47.711183 01900000 ################################################################
10183 23:25:47.711331
10184 23:25:47.996510 01980000 ################################################################
10185 23:25:47.996663
10186 23:25:48.260455 01a00000 ################################################################
10187 23:25:48.260605
10188 23:25:48.542865 01a80000 ################################################################
10189 23:25:48.543059
10190 23:25:48.814860 01b00000 ################################################################
10191 23:25:48.815005
10192 23:25:49.089887 01b80000 ################################################################
10193 23:25:49.090019
10194 23:25:49.377900 01c00000 ################################################################
10195 23:25:49.378042
10196 23:25:49.668905 01c80000 ################################################################
10197 23:25:49.669062
10198 23:25:49.963152 01d00000 ################################################################
10199 23:25:49.963341
10200 23:25:50.237532 01d80000 ################################################################
10201 23:25:50.237672
10202 23:25:50.497951 01e00000 ################################################################
10203 23:25:50.498142
10204 23:25:50.763475 01e80000 ################################################################
10205 23:25:50.763661
10206 23:25:51.031222 01f00000 ################################################################
10207 23:25:51.031354
10208 23:25:51.288665 01f80000 ################################################################
10209 23:25:51.288828
10210 23:25:51.549127 02000000 ################################################################
10211 23:25:51.549259
10212 23:25:51.802270 02080000 ################################################################
10213 23:25:51.802402
10214 23:25:52.062272 02100000 ################################################################
10215 23:25:52.062466
10216 23:25:52.343582 02180000 ################################################################
10217 23:25:52.343740
10218 23:25:52.627548 02200000 ################################################################
10219 23:25:52.627678
10220 23:25:52.896130 02280000 ################################################################
10221 23:25:52.896264
10222 23:25:53.178524 02300000 ################################################################
10223 23:25:53.178651
10224 23:25:53.456842 02380000 ################################################################
10225 23:25:53.456976
10226 23:25:53.749481 02400000 ################################################################
10227 23:25:53.749650
10228 23:25:54.013048 02480000 ################################################################
10229 23:25:54.013240
10230 23:25:54.278131 02500000 ################################################################
10231 23:25:54.278266
10232 23:25:54.535996 02580000 ################################################################
10233 23:25:54.536161
10234 23:25:54.789251 02600000 ################################################################
10235 23:25:54.789387
10236 23:25:55.061906 02680000 ################################################################
10237 23:25:55.062067
10238 23:25:55.322567 02700000 ################################################################
10239 23:25:55.322729
10240 23:25:55.603105 02780000 ################################################################
10241 23:25:55.603283
10242 23:25:55.871136 02800000 ################################################################
10243 23:25:55.871302
10244 23:25:56.139050 02880000 ################################################################
10245 23:25:56.139207
10246 23:25:56.415970 02900000 ################################################################
10247 23:25:56.416138
10248 23:25:56.668675 02980000 ################################################################
10249 23:25:56.668869
10250 23:25:56.931859 02a00000 ################################################################
10251 23:25:56.932017
10252 23:25:57.199683 02a80000 ################################################################
10253 23:25:57.199822
10254 23:25:57.470200 02b00000 ################################################################
10255 23:25:57.470333
10256 23:25:57.739242 02b80000 ################################################################
10257 23:25:57.739390
10258 23:25:58.002293 02c00000 ################################################################
10259 23:25:58.002426
10260 23:25:58.284164 02c80000 ################################################################
10261 23:25:58.284368
10262 23:25:58.564689 02d00000 ################################################################
10263 23:25:58.564818
10264 23:25:58.834392 02d80000 ################################################################
10265 23:25:58.834529
10266 23:25:59.093112 02e00000 ################################################################
10267 23:25:59.093247
10268 23:25:59.343896 02e80000 ################################################################
10269 23:25:59.344030
10270 23:25:59.601186 02f00000 ################################################################
10271 23:25:59.601322
10272 23:25:59.860669 02f80000 ################################################################
10273 23:25:59.860807
10274 23:26:00.116779 03000000 ################################################################
10275 23:26:00.116966
10276 23:26:00.382869 03080000 ################################################################
10277 23:26:00.383044
10278 23:26:00.654553 03100000 ################################################################
10279 23:26:00.654692
10280 23:26:00.928028 03180000 ################################################################
10281 23:26:00.928180
10282 23:26:01.189922 03200000 ################################################################
10283 23:26:01.190057
10284 23:26:01.465427 03280000 ################################################################
10285 23:26:01.465563
10286 23:26:01.737434 03300000 ################################################################
10287 23:26:01.737583
10288 23:26:02.020699 03380000 ################################################################
10289 23:26:02.020845
10290 23:26:02.282772 03400000 ################################################################
10291 23:26:02.282914
10292 23:26:02.527523 03480000 ################################################################
10293 23:26:02.527676
10294 23:26:02.785462 03500000 ################################################################
10295 23:26:02.785599
10296 23:26:03.051825 03580000 ################################################################
10297 23:26:03.051970
10298 23:26:03.314345 03600000 ################################################################
10299 23:26:03.314485
10300 23:26:03.579769 03680000 ################################################################
10301 23:26:03.579905
10302 23:26:03.842765 03700000 ################################################################
10303 23:26:03.842902
10304 23:26:04.112230 03780000 ################################################################
10305 23:26:04.112410
10306 23:26:04.373309 03800000 ################################################################
10307 23:26:04.373514
10308 23:26:04.633180 03880000 ################################################################
10309 23:26:04.633322
10310 23:26:04.902387 03900000 ################################################################
10311 23:26:04.902522
10312 23:26:05.179389 03980000 ################################################################
10313 23:26:05.179551
10314 23:26:05.440195 03a00000 ################################################################
10315 23:26:05.440382
10316 23:26:05.695042 03a80000 ################################################################
10317 23:26:05.695172
10318 23:26:05.957807 03b00000 ################################################################
10319 23:26:05.957947
10320 23:26:06.224149 03b80000 ################################################################
10321 23:26:06.224328
10322 23:26:06.487496 03c00000 ################################################################
10323 23:26:06.487629
10324 23:26:06.745622 03c80000 ################################################################
10325 23:26:06.745815
10326 23:26:07.014023 03d00000 ################################################################
10327 23:26:07.014184
10328 23:26:07.276977 03d80000 ################################################################
10329 23:26:07.277188
10330 23:26:07.543109 03e00000 ################################################################
10331 23:26:07.543289
10332 23:26:07.816569 03e80000 ################################################################
10333 23:26:07.816726
10334 23:26:08.087788 03f00000 ################################################################
10335 23:26:08.087925
10336 23:26:08.361425 03f80000 ################################################################
10337 23:26:08.361559
10338 23:26:08.630466 04000000 ################################################################
10339 23:26:08.630659
10340 23:26:08.895537 04080000 ################################################################
10341 23:26:08.895741
10342 23:26:09.162476 04100000 ################################################################
10343 23:26:09.162626
10344 23:26:09.420331 04180000 ################################################################
10345 23:26:09.420470
10346 23:26:09.689349 04200000 ################################################################
10347 23:26:09.689485
10348 23:26:09.952492 04280000 ################################################################
10349 23:26:09.952652
10350 23:26:10.207659 04300000 ################################################################
10351 23:26:10.207827
10352 23:26:10.479479 04380000 ################################################################
10353 23:26:10.479620
10354 23:26:10.735496 04400000 ################################################################
10355 23:26:10.735626
10356 23:26:10.995122 04480000 ################################################################
10357 23:26:10.995255
10358 23:26:11.276730 04500000 ################################################################
10359 23:26:11.276862
10360 23:26:11.557221 04580000 ################################################################
10361 23:26:11.557352
10362 23:26:11.828048 04600000 ################################################################
10363 23:26:11.828185
10364 23:26:11.868901 04680000 ########### done.
10365 23:26:11.868996
10366 23:26:11.872039 The bootfile was 74006746 bytes long.
10367 23:26:11.872151
10368 23:26:11.875363 Sending tftp read request... done.
10369 23:26:11.875446
10370 23:26:11.875517 Waiting for the transfer...
10371 23:26:11.875591
10372 23:26:11.878710 00000000 # done.
10373 23:26:11.878796
10374 23:26:11.885292 Command line loaded dynamically from TFTP file: 13248445/tftp-deploy-wwg_t9yx/kernel/cmdline
10375 23:26:11.885402
10376 23:26:11.898678 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10377 23:26:11.898765
10378 23:26:11.902013 Loading FIT.
10379 23:26:11.902095
10380 23:26:11.905210 Image ramdisk-1 has 61050210 bytes.
10381 23:26:11.905294
10382 23:26:11.908423 Image fdt-1 has 47230 bytes.
10383 23:26:11.908506
10384 23:26:11.908571 Image kernel-1 has 12907270 bytes.
10385 23:26:11.908633
10386 23:26:11.918364 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10387 23:26:11.918474
10388 23:26:11.934852 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10389 23:26:11.938412
10390 23:26:11.941635 Choosing best match conf-1 for compat google,spherion-rev2.
10391 23:26:11.945966
10392 23:26:11.950859 Connected to device vid:did:rid of 1ae0:0028:00
10393 23:26:11.958892
10394 23:26:11.961864 tpm_get_response: command 0x17b, return code 0x0
10395 23:26:11.961954
10396 23:26:11.965390 ec_init: CrosEC protocol v3 supported (256, 248)
10397 23:26:11.968713
10398 23:26:11.972294 tpm_cleanup: add release locality here.
10399 23:26:11.972378
10400 23:26:11.975469 Shutting down all USB controllers.
10401 23:26:11.975578
10402 23:26:11.978847 Removing current net device
10403 23:26:11.978949
10404 23:26:11.982090 Exiting depthcharge with code 4 at timestamp: 72822656
10405 23:26:11.982174
10406 23:26:11.985319 LZMA decompressing kernel-1 to 0x821a6718
10407 23:26:11.985428
10408 23:26:11.991732 LZMA decompressing kernel-1 to 0x40000000
10409 23:26:13.584193
10410 23:26:13.584392 jumping to kernel
10411 23:26:13.585305 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10412 23:26:13.585470 start: 2.2.5 auto-login-action (timeout 00:03:40) [common]
10413 23:26:13.585603 Setting prompt string to ['Linux version [0-9]']
10414 23:26:13.585730 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10415 23:26:13.585856 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10416 23:26:13.667355
10417 23:26:13.670852 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10418 23:26:13.674500 start: 2.2.5.1 login-action (timeout 00:03:40) [common]
10419 23:26:13.674643 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10420 23:26:13.674783 Setting prompt string to []
10421 23:26:13.674963 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10422 23:26:13.675098 Using line separator: #'\n'#
10423 23:26:13.675241 No login prompt set.
10424 23:26:13.675352 Parsing kernel messages
10425 23:26:13.675495 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10426 23:26:13.675704 [login-action] Waiting for messages, (timeout 00:03:40)
10427 23:26:13.675833 Waiting using forced prompt support (timeout 00:01:50)
10428 23:26:13.694100 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10429 23:26:13.697507 [ 0.000000] random: crng init done
10430 23:26:13.703888 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10431 23:26:13.703988 [ 0.000000] efi: UEFI not found.
10432 23:26:13.713716 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10433 23:26:13.720678 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10434 23:26:13.730369 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10435 23:26:13.740426 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10436 23:26:13.746817 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10437 23:26:13.753416 [ 0.000000] printk: bootconsole [mtk8250] enabled
10438 23:26:13.760165 [ 0.000000] NUMA: No NUMA configuration found
10439 23:26:13.766845 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10440 23:26:13.770275 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10441 23:26:13.773469 [ 0.000000] Zone ranges:
10442 23:26:13.780120 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10443 23:26:13.783226 [ 0.000000] DMA32 empty
10444 23:26:13.790045 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10445 23:26:13.793444 [ 0.000000] Movable zone start for each node
10446 23:26:13.796530 [ 0.000000] Early memory node ranges
10447 23:26:13.803191 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10448 23:26:13.809927 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10449 23:26:13.816178 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10450 23:26:13.822988 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10451 23:26:13.826260 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10452 23:26:13.836176 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10453 23:26:13.891291 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10454 23:26:13.897765 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10455 23:26:13.904466 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10456 23:26:13.907585 [ 0.000000] psci: probing for conduit method from DT.
10457 23:26:13.914390 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10458 23:26:13.917954 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10459 23:26:13.924307 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10460 23:26:13.927482 [ 0.000000] psci: SMC Calling Convention v1.2
10461 23:26:13.934405 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10462 23:26:13.937637 [ 0.000000] Detected VIPT I-cache on CPU0
10463 23:26:13.944243 [ 0.000000] CPU features: detected: GIC system register CPU interface
10464 23:26:13.950850 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10465 23:26:13.957602 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10466 23:26:13.963888 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10467 23:26:13.970533 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10468 23:26:13.980545 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10469 23:26:13.983831 [ 0.000000] alternatives: applying boot alternatives
10470 23:26:13.987360 [ 0.000000] Fallback order for Node 0: 0
10471 23:26:13.997309 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10472 23:26:14.000783 [ 0.000000] Policy zone: Normal
10473 23:26:14.013850 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10474 23:26:14.023700 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10475 23:26:14.035491 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10476 23:26:14.045327 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10477 23:26:14.052024 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10478 23:26:14.055024 <6>[ 0.000000] software IO TLB: area num 8.
10479 23:26:14.111993 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10480 23:26:14.260926 <6>[ 0.000000] Memory: 7904948K/8385536K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 447820K reserved, 32768K cma-reserved)
10481 23:26:14.267647 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10482 23:26:14.274222 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10483 23:26:14.277297 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10484 23:26:14.284035 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10485 23:26:14.290735 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10486 23:26:14.293898 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10487 23:26:14.303932 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10488 23:26:14.310259 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10489 23:26:14.317031 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10490 23:26:14.323536 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10491 23:26:14.326767 <6>[ 0.000000] GICv3: 608 SPIs implemented
10492 23:26:14.330269 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10493 23:26:14.336769 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10494 23:26:14.340081 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10495 23:26:14.346741 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10496 23:26:14.360087 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10497 23:26:14.373400 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10498 23:26:14.380031 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10499 23:26:14.387647 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10500 23:26:14.400798 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10501 23:26:14.407393 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10502 23:26:14.413886 <6>[ 0.009176] Console: colour dummy device 80x25
10503 23:26:14.424078 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10504 23:26:14.430579 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10505 23:26:14.433870 <6>[ 0.029248] LSM: Security Framework initializing
10506 23:26:14.440389 <6>[ 0.034186] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10507 23:26:14.450605 <6>[ 0.042001] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10508 23:26:14.457027 <6>[ 0.051426] cblist_init_generic: Setting adjustable number of callback queues.
10509 23:26:14.463635 <6>[ 0.058870] cblist_init_generic: Setting shift to 3 and lim to 1.
10510 23:26:14.473804 <6>[ 0.065210] cblist_init_generic: Setting adjustable number of callback queues.
10511 23:26:14.480393 <6>[ 0.072636] cblist_init_generic: Setting shift to 3 and lim to 1.
10512 23:26:14.483763 <6>[ 0.079077] rcu: Hierarchical SRCU implementation.
10513 23:26:14.490108 <6>[ 0.084093] rcu: Max phase no-delay instances is 1000.
10514 23:26:14.496901 <6>[ 0.091112] EFI services will not be available.
10515 23:26:14.499866 <6>[ 0.096066] smp: Bringing up secondary CPUs ...
10516 23:26:14.508069 <6>[ 0.101144] Detected VIPT I-cache on CPU1
10517 23:26:14.514815 <6>[ 0.101215] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10518 23:26:14.521375 <6>[ 0.101245] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10519 23:26:14.524676 <6>[ 0.101579] Detected VIPT I-cache on CPU2
10520 23:26:14.531572 <6>[ 0.101633] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10521 23:26:14.541213 <6>[ 0.101652] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10522 23:26:14.544612 <6>[ 0.101908] Detected VIPT I-cache on CPU3
10523 23:26:14.551197 <6>[ 0.101956] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10524 23:26:14.557654 <6>[ 0.101971] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10525 23:26:14.561109 <6>[ 0.102274] CPU features: detected: Spectre-v4
10526 23:26:14.567860 <6>[ 0.102281] CPU features: detected: Spectre-BHB
10527 23:26:14.571160 <6>[ 0.102286] Detected PIPT I-cache on CPU4
10528 23:26:14.577839 <6>[ 0.102344] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10529 23:26:14.584264 <6>[ 0.102360] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10530 23:26:14.590996 <6>[ 0.102654] Detected PIPT I-cache on CPU5
10531 23:26:14.597528 <6>[ 0.102716] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10532 23:26:14.604055 <6>[ 0.102733] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10533 23:26:14.607472 <6>[ 0.103013] Detected PIPT I-cache on CPU6
10534 23:26:14.613922 <6>[ 0.103078] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10535 23:26:14.620497 <6>[ 0.103095] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10536 23:26:14.627271 <6>[ 0.103392] Detected PIPT I-cache on CPU7
10537 23:26:14.634060 <6>[ 0.103459] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10538 23:26:14.640583 <6>[ 0.103475] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10539 23:26:14.643894 <6>[ 0.103521] smp: Brought up 1 node, 8 CPUs
10540 23:26:14.650673 <6>[ 0.244781] SMP: Total of 8 processors activated.
10541 23:26:14.653836 <6>[ 0.249702] CPU features: detected: 32-bit EL0 Support
10542 23:26:14.663849 <6>[ 0.255066] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10543 23:26:14.670203 <6>[ 0.263867] CPU features: detected: Common not Private translations
10544 23:26:14.676852 <6>[ 0.270343] CPU features: detected: CRC32 instructions
10545 23:26:14.680314 <6>[ 0.275694] CPU features: detected: RCpc load-acquire (LDAPR)
10546 23:26:14.686987 <6>[ 0.281654] CPU features: detected: LSE atomic instructions
10547 23:26:14.693627 <6>[ 0.287472] CPU features: detected: Privileged Access Never
10548 23:26:14.699965 <6>[ 0.293252] CPU features: detected: RAS Extension Support
10549 23:26:14.706746 <6>[ 0.298861] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10550 23:26:14.710020 <6>[ 0.306081] CPU: All CPU(s) started at EL2
10551 23:26:14.716779 <6>[ 0.310398] alternatives: applying system-wide alternatives
10552 23:26:14.725822 <6>[ 0.321228] devtmpfs: initialized
10553 23:26:14.738371 <6>[ 0.330133] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10554 23:26:14.748024 <6>[ 0.340092] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10555 23:26:14.754733 <6>[ 0.348356] pinctrl core: initialized pinctrl subsystem
10556 23:26:14.758055 <6>[ 0.355025] DMI not present or invalid.
10557 23:26:14.764921 <6>[ 0.359434] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10558 23:26:14.774361 <6>[ 0.366333] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10559 23:26:14.781017 <6>[ 0.373904] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10560 23:26:14.790877 <6>[ 0.382131] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10561 23:26:14.794224 <6>[ 0.390372] audit: initializing netlink subsys (disabled)
10562 23:26:14.804234 <5>[ 0.396070] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10563 23:26:14.810869 <6>[ 0.396777] thermal_sys: Registered thermal governor 'step_wise'
10564 23:26:14.817664 <6>[ 0.404035] thermal_sys: Registered thermal governor 'power_allocator'
10565 23:26:14.820804 <6>[ 0.410292] cpuidle: using governor menu
10566 23:26:14.827235 <6>[ 0.421250] NET: Registered PF_QIPCRTR protocol family
10567 23:26:14.834056 <6>[ 0.426729] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10568 23:26:14.840657 <6>[ 0.433831] ASID allocator initialised with 32768 entries
10569 23:26:14.843582 <6>[ 0.440399] Serial: AMBA PL011 UART driver
10570 23:26:14.853962 <4>[ 0.449234] Trying to register duplicate clock ID: 134
10571 23:26:14.908308 <6>[ 0.506944] KASLR enabled
10572 23:26:14.922452 <6>[ 0.514702] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10573 23:26:14.929379 <6>[ 0.521714] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10574 23:26:14.935940 <6>[ 0.528205] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10575 23:26:14.942547 <6>[ 0.535210] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10576 23:26:14.949176 <6>[ 0.541692] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10577 23:26:14.955893 <6>[ 0.548698] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10578 23:26:14.962327 <6>[ 0.555185] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10579 23:26:14.969414 <6>[ 0.562191] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10580 23:26:14.972457 <6>[ 0.569720] ACPI: Interpreter disabled.
10581 23:26:14.980924 <6>[ 0.576214] iommu: Default domain type: Translated
10582 23:26:14.987672 <6>[ 0.581326] iommu: DMA domain TLB invalidation policy: strict mode
10583 23:26:14.990929 <5>[ 0.587983] SCSI subsystem initialized
10584 23:26:14.997374 <6>[ 0.592133] usbcore: registered new interface driver usbfs
10585 23:26:15.004274 <6>[ 0.597864] usbcore: registered new interface driver hub
10586 23:26:15.007540 <6>[ 0.603416] usbcore: registered new device driver usb
10587 23:26:15.014016 <6>[ 0.609511] pps_core: LinuxPPS API ver. 1 registered
10588 23:26:15.024190 <6>[ 0.614701] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10589 23:26:15.027509 <6>[ 0.624046] PTP clock support registered
10590 23:26:15.030507 <6>[ 0.628287] EDAC MC: Ver: 3.0.0
10591 23:26:15.038246 <6>[ 0.633463] FPGA manager framework
10592 23:26:15.041330 <6>[ 0.637144] Advanced Linux Sound Architecture Driver Initialized.
10593 23:26:15.045174 <6>[ 0.643927] vgaarb: loaded
10594 23:26:15.051932 <6>[ 0.647093] clocksource: Switched to clocksource arch_sys_counter
10595 23:26:15.058332 <5>[ 0.653536] VFS: Disk quotas dquot_6.6.0
10596 23:26:15.065145 <6>[ 0.657724] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10597 23:26:15.068239 <6>[ 0.664914] pnp: PnP ACPI: disabled
10598 23:26:15.076432 <6>[ 0.671581] NET: Registered PF_INET protocol family
10599 23:26:15.086218 <6>[ 0.677194] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10600 23:26:15.097472 <6>[ 0.689500] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10601 23:26:15.107342 <6>[ 0.698311] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10602 23:26:15.113972 <6>[ 0.706279] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10603 23:26:15.123789 <6>[ 0.714974] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10604 23:26:15.130312 <6>[ 0.724727] TCP: Hash tables configured (established 65536 bind 65536)
10605 23:26:15.137194 <6>[ 0.731588] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10606 23:26:15.147142 <6>[ 0.738788] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10607 23:26:15.150635 <6>[ 0.746491] NET: Registered PF_UNIX/PF_LOCAL protocol family
10608 23:26:15.157318 <6>[ 0.752640] RPC: Registered named UNIX socket transport module.
10609 23:26:15.164013 <6>[ 0.758791] RPC: Registered udp transport module.
10610 23:26:15.167336 <6>[ 0.763721] RPC: Registered tcp transport module.
10611 23:26:15.173938 <6>[ 0.768651] RPC: Registered tcp NFSv4.1 backchannel transport module.
10612 23:26:15.180488 <6>[ 0.775319] PCI: CLS 0 bytes, default 64
10613 23:26:15.183930 <6>[ 0.779661] Unpacking initramfs...
10614 23:26:15.207216 <6>[ 0.799202] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10615 23:26:15.217271 <6>[ 0.807869] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10616 23:26:15.220482 <6>[ 0.816737] kvm [1]: IPA Size Limit: 40 bits
10617 23:26:15.227437 <6>[ 0.821265] kvm [1]: GICv3: no GICV resource entry
10618 23:26:15.230416 <6>[ 0.826285] kvm [1]: disabling GICv2 emulation
10619 23:26:15.237069 <6>[ 0.830971] kvm [1]: GIC system register CPU interface enabled
10620 23:26:15.240416 <6>[ 0.837135] kvm [1]: vgic interrupt IRQ18
10621 23:26:15.247121 <6>[ 0.841498] kvm [1]: VHE mode initialized successfully
10622 23:26:15.253554 <5>[ 0.847973] Initialise system trusted keyrings
10623 23:26:15.260437 <6>[ 0.852774] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10624 23:26:15.267595 <6>[ 0.862740] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10625 23:26:15.273940 <5>[ 0.869148] NFS: Registering the id_resolver key type
10626 23:26:15.277264 <5>[ 0.874449] Key type id_resolver registered
10627 23:26:15.284054 <5>[ 0.878864] Key type id_legacy registered
10628 23:26:15.290496 <6>[ 0.883146] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10629 23:26:15.297330 <6>[ 0.890067] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10630 23:26:15.303565 <6>[ 0.897791] 9p: Installing v9fs 9p2000 file system support
10631 23:26:15.340736 <5>[ 0.936007] Key type asymmetric registered
10632 23:26:15.344036 <5>[ 0.940342] Asymmetric key parser 'x509' registered
10633 23:26:15.354031 <6>[ 0.945503] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10634 23:26:15.357227 <6>[ 0.953121] io scheduler mq-deadline registered
10635 23:26:15.360464 <6>[ 0.957884] io scheduler kyber registered
10636 23:26:15.379899 <6>[ 0.975370] EINJ: ACPI disabled.
10637 23:26:15.413115 <4>[ 1.001782] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10638 23:26:15.423207 <4>[ 1.012418] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10639 23:26:15.438068 <6>[ 1.033375] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10640 23:26:15.446246 <6>[ 1.041513] printk: console [ttyS0] disabled
10641 23:26:15.474171 <6>[ 1.066146] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10642 23:26:15.481068 <6>[ 1.075622] printk: console [ttyS0] enabled
10643 23:26:15.484111 <6>[ 1.075622] printk: console [ttyS0] enabled
10644 23:26:15.490698 <6>[ 1.084516] printk: bootconsole [mtk8250] disabled
10645 23:26:15.493772 <6>[ 1.084516] printk: bootconsole [mtk8250] disabled
10646 23:26:15.500579 <6>[ 1.095901] SuperH (H)SCI(F) driver initialized
10647 23:26:15.504060 <6>[ 1.101215] msm_serial: driver initialized
10648 23:26:15.518422 <6>[ 1.110340] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10649 23:26:15.528515 <6>[ 1.118889] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10650 23:26:15.535142 <6>[ 1.127433] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10651 23:26:15.544896 <6>[ 1.136061] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10652 23:26:15.554838 <6>[ 1.144767] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10653 23:26:15.561558 <6>[ 1.153485] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10654 23:26:15.571287 <6>[ 1.162027] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10655 23:26:15.577853 <6>[ 1.170850] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10656 23:26:15.587905 <6>[ 1.179394] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10657 23:26:15.599864 <6>[ 1.195106] loop: module loaded
10658 23:26:15.606431 <6>[ 1.201086] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10659 23:26:15.628957 <4>[ 1.224477] mtk-pmic-keys: Failed to locate of_node [id: -1]
10660 23:26:15.636202 <6>[ 1.231400] megasas: 07.719.03.00-rc1
10661 23:26:15.645704 <6>[ 1.241140] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10662 23:26:15.659178 <6>[ 1.254465] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10663 23:26:15.676047 <6>[ 1.271199] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10664 23:26:15.732279 <6>[ 1.321339] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10665 23:26:17.877872 <6>[ 3.473391] Freeing initrd memory: 59616K
10666 23:26:17.889338 <6>[ 3.485191] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10667 23:26:17.900666 <6>[ 3.496397] tun: Universal TUN/TAP device driver, 1.6
10668 23:26:17.903972 <6>[ 3.502480] thunder_xcv, ver 1.0
10669 23:26:17.907454 <6>[ 3.505987] thunder_bgx, ver 1.0
10670 23:26:17.910842 <6>[ 3.509484] nicpf, ver 1.0
10671 23:26:17.920967 <6>[ 3.513524] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10672 23:26:17.924350 <6>[ 3.521000] hns3: Copyright (c) 2017 Huawei Corporation.
10673 23:26:17.930880 <6>[ 3.526590] hclge is initializing
10674 23:26:17.934409 <6>[ 3.530170] e1000: Intel(R) PRO/1000 Network Driver
10675 23:26:17.941193 <6>[ 3.535299] e1000: Copyright (c) 1999-2006 Intel Corporation.
10676 23:26:17.944301 <6>[ 3.541312] e1000e: Intel(R) PRO/1000 Network Driver
10677 23:26:17.950914 <6>[ 3.546528] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10678 23:26:17.957889 <6>[ 3.552719] igb: Intel(R) Gigabit Ethernet Network Driver
10679 23:26:17.964536 <6>[ 3.558369] igb: Copyright (c) 2007-2014 Intel Corporation.
10680 23:26:17.970928 <6>[ 3.564205] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10681 23:26:17.977772 <6>[ 3.570723] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10682 23:26:17.980872 <6>[ 3.577200] sky2: driver version 1.30
10683 23:26:17.987248 <6>[ 3.582220] VFIO - User Level meta-driver version: 0.3
10684 23:26:17.994959 <6>[ 3.590517] usbcore: registered new interface driver usb-storage
10685 23:26:18.001272 <6>[ 3.596978] usbcore: registered new device driver onboard-usb-hub
10686 23:26:18.010820 <6>[ 3.606190] mt6397-rtc mt6359-rtc: registered as rtc0
10687 23:26:18.020162 <6>[ 3.611656] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:23:24 UTC (1712186604)
10688 23:26:18.023687 <6>[ 3.621225] i2c_dev: i2c /dev entries driver
10689 23:26:18.041024 <6>[ 3.633182] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10690 23:26:18.047500 <4>[ 3.641922] cpu cpu0: supply cpu not found, using dummy regulator
10691 23:26:18.054125 <4>[ 3.648347] cpu cpu1: supply cpu not found, using dummy regulator
10692 23:26:18.060908 <4>[ 3.654753] cpu cpu2: supply cpu not found, using dummy regulator
10693 23:26:18.067483 <4>[ 3.661158] cpu cpu3: supply cpu not found, using dummy regulator
10694 23:26:18.074077 <4>[ 3.667573] cpu cpu4: supply cpu not found, using dummy regulator
10695 23:26:18.080594 <4>[ 3.673970] cpu cpu5: supply cpu not found, using dummy regulator
10696 23:26:18.087434 <4>[ 3.680370] cpu cpu6: supply cpu not found, using dummy regulator
10697 23:26:18.093878 <4>[ 3.686765] cpu cpu7: supply cpu not found, using dummy regulator
10698 23:26:18.111728 <6>[ 3.707418] cpu cpu0: EM: created perf domain
10699 23:26:18.115017 <6>[ 3.712356] cpu cpu4: EM: created perf domain
10700 23:26:18.122336 <6>[ 3.718007] sdhci: Secure Digital Host Controller Interface driver
10701 23:26:18.128753 <6>[ 3.724439] sdhci: Copyright(c) Pierre Ossman
10702 23:26:18.135601 <6>[ 3.729396] Synopsys Designware Multimedia Card Interface Driver
10703 23:26:18.142161 <6>[ 3.736042] sdhci-pltfm: SDHCI platform and OF driver helper
10704 23:26:18.145161 <6>[ 3.736089] mmc0: CQHCI version 5.10
10705 23:26:18.151893 <6>[ 3.746288] ledtrig-cpu: registered to indicate activity on CPUs
10706 23:26:18.158728 <6>[ 3.753440] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10707 23:26:18.165333 <6>[ 3.760496] usbcore: registered new interface driver usbhid
10708 23:26:18.168909 <6>[ 3.766320] usbhid: USB HID core driver
10709 23:26:18.175249 <6>[ 3.770526] spi_master spi0: will run message pump with realtime priority
10710 23:26:18.224540 <6>[ 3.813222] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10711 23:26:18.244425 <6>[ 3.829511] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10712 23:26:18.247643 <6>[ 3.843955] mmc0: Command Queue Engine enabled
10713 23:26:18.254496 <6>[ 3.844394] cros-ec-spi spi0.0: Chrome EC device registered
10714 23:26:18.261344 <6>[ 3.848739] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10715 23:26:18.264535 <6>[ 3.861769] mmcblk0: mmc0:0001 DA4128 116 GiB
10716 23:26:18.275442 <6>[ 3.867747] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10717 23:26:18.282134 <6>[ 3.871637] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10718 23:26:18.288998 <6>[ 3.878053] NET: Registered PF_PACKET protocol family
10719 23:26:18.291850 <6>[ 3.884521] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10720 23:26:18.298452 <6>[ 3.888370] 9pnet: Installing 9P2000 support
10721 23:26:18.302158 <6>[ 3.894171] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10722 23:26:18.308319 <5>[ 3.898061] Key type dns_resolver registered
10723 23:26:18.315064 <6>[ 3.903929] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10724 23:26:18.318409 <6>[ 3.908187] registered taskstats version 1
10725 23:26:18.321666 <5>[ 3.918663] Loading compiled-in X.509 certificates
10726 23:26:18.352383 <4>[ 3.941452] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10727 23:26:18.362375 <4>[ 3.952173] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10728 23:26:18.368901 <3>[ 3.962704] debugfs: File 'uA_load' in directory '/' already present!
10729 23:26:18.375442 <3>[ 3.969404] debugfs: File 'min_uV' in directory '/' already present!
10730 23:26:18.382325 <3>[ 3.976088] debugfs: File 'max_uV' in directory '/' already present!
10731 23:26:18.388603 <3>[ 3.982708] debugfs: File 'constraint_flags' in directory '/' already present!
10732 23:26:18.400380 <3>[ 3.992622] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10733 23:26:18.409418 <6>[ 4.005105] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10734 23:26:18.416151 <6>[ 4.011870] xhci-mtk 11200000.usb: xHCI Host Controller
10735 23:26:18.422947 <6>[ 4.017378] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10736 23:26:18.432885 <6>[ 4.025225] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10737 23:26:18.439564 <6>[ 4.034649] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10738 23:26:18.446129 <6>[ 4.040713] xhci-mtk 11200000.usb: xHCI Host Controller
10739 23:26:18.452538 <6>[ 4.046187] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10740 23:26:18.459340 <6>[ 4.053832] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10741 23:26:18.466185 <6>[ 4.061659] hub 1-0:1.0: USB hub found
10742 23:26:18.469338 <6>[ 4.065701] hub 1-0:1.0: 1 port detected
10743 23:26:18.476095 <6>[ 4.069979] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10744 23:26:18.483114 <6>[ 4.078746] hub 2-0:1.0: USB hub found
10745 23:26:18.486142 <6>[ 4.082791] hub 2-0:1.0: 1 port detected
10746 23:26:18.495824 <6>[ 4.091391] mtk-msdc 11f70000.mmc: Got CD GPIO
10747 23:26:18.507512 <6>[ 4.099864] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10748 23:26:18.514094 <6>[ 4.108142] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10749 23:26:18.524283 <4>[ 4.116054] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10750 23:26:18.534078 <6>[ 4.125613] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10751 23:26:18.540829 <6>[ 4.133711] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10752 23:26:18.550511 <6>[ 4.141890] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10753 23:26:18.557273 <6>[ 4.149820] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10754 23:26:18.563928 <6>[ 4.157637] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10755 23:26:18.573874 <6>[ 4.165454] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10756 23:26:18.583740 <6>[ 4.175907] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10757 23:26:18.593504 <6>[ 4.184282] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10758 23:26:18.600192 <6>[ 4.192621] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10759 23:26:18.609831 <6>[ 4.200967] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10760 23:26:18.616680 <6>[ 4.209306] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10761 23:26:18.626573 <6>[ 4.217643] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10762 23:26:18.633514 <6>[ 4.225981] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10763 23:26:18.643260 <6>[ 4.234318] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10764 23:26:18.649795 <6>[ 4.242660] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10765 23:26:18.659968 <6>[ 4.250998] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10766 23:26:18.666556 <6>[ 4.259336] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10767 23:26:18.676293 <6>[ 4.267672] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10768 23:26:18.682770 <6>[ 4.276010] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10769 23:26:18.692918 <6>[ 4.284348] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10770 23:26:18.699674 <6>[ 4.292685] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10771 23:26:18.706145 <6>[ 4.301519] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10772 23:26:18.713024 <6>[ 4.308837] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10773 23:26:18.720183 <6>[ 4.315805] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10774 23:26:18.730384 <6>[ 4.322710] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10775 23:26:18.737012 <6>[ 4.329750] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10776 23:26:18.743698 <6>[ 4.336625] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10777 23:26:18.753360 <6>[ 4.345755] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10778 23:26:18.763570 <6>[ 4.354874] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10779 23:26:18.773346 <6>[ 4.364184] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10780 23:26:18.783455 <6>[ 4.373652] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10781 23:26:18.789839 <6>[ 4.383118] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10782 23:26:18.799746 <6>[ 4.392238] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10783 23:26:18.809990 <6>[ 4.401704] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10784 23:26:18.819532 <6>[ 4.410822] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10785 23:26:18.829685 <6>[ 4.420115] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10786 23:26:18.839747 <6>[ 4.430276] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10787 23:26:18.849825 <6>[ 4.442252] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10788 23:26:18.874913 <6>[ 4.467625] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10789 23:26:18.903173 <6>[ 4.499107] hub 2-1:1.0: USB hub found
10790 23:26:18.906773 <6>[ 4.503585] hub 2-1:1.0: 3 ports detected
10791 23:26:18.914964 <6>[ 4.510749] hub 2-1:1.0: USB hub found
10792 23:26:18.918420 <6>[ 4.515180] hub 2-1:1.0: 3 ports detected
10793 23:26:19.026846 <6>[ 4.619387] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10794 23:26:19.181577 <6>[ 4.777530] hub 1-1:1.0: USB hub found
10795 23:26:19.185047 <6>[ 4.782026] hub 1-1:1.0: 4 ports detected
10796 23:26:19.194128 <6>[ 4.789940] hub 1-1:1.0: USB hub found
10797 23:26:19.197256 <6>[ 4.794259] hub 1-1:1.0: 4 ports detected
10798 23:26:19.266945 <6>[ 4.859583] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10799 23:26:19.519076 <6>[ 5.111405] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10800 23:26:19.651516 <6>[ 5.247298] hub 1-1.4:1.0: USB hub found
10801 23:26:19.654616 <6>[ 5.251961] hub 1-1.4:1.0: 2 ports detected
10802 23:26:19.664351 <6>[ 5.260226] hub 1-1.4:1.0: USB hub found
10803 23:26:19.667667 <6>[ 5.264809] hub 1-1.4:1.0: 2 ports detected
10804 23:26:19.966848 <6>[ 5.559385] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10805 23:26:20.158935 <6>[ 5.751419] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10806 23:26:31.152055 <6>[ 16.752491] ALSA device list:
10807 23:26:31.158434 <6>[ 16.755793] No soundcards found.
10808 23:26:31.166888 <6>[ 16.764011] Freeing unused kernel memory: 8448K
10809 23:26:31.170174 <6>[ 16.769477] Run /init as init process
10810 23:26:31.202204 <6>[ 16.799034] NET: Registered PF_INET6 protocol family
10811 23:26:31.208591 <6>[ 16.805555] Segment Routing with IPv6
10812 23:26:31.211908 <6>[ 16.809502] In-situ OAM (IOAM) with IPv6
10813 23:26:31.255895 <30>[ 16.826712] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10814 23:26:31.262821 <30>[ 16.859846] systemd[1]: Detected architecture arm64.
10815 23:26:31.262946
10816 23:26:31.269526 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10817 23:26:31.269656
10818 23:26:31.269772
10819 23:26:31.282279 <30>[ 16.879412] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10820 23:26:31.425739 <30>[ 17.019764] systemd[1]: Queued start job for default target graphical.target.
10821 23:26:31.474694 <30>[ 17.068620] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10822 23:26:31.481588 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10823 23:26:31.481698
10824 23:26:31.502361 <30>[ 17.095999] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10825 23:26:31.512119 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10826 23:26:31.512270
10827 23:26:31.531125 <30>[ 17.125124] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10828 23:26:31.541260 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10829 23:26:31.541414
10830 23:26:31.558720 <30>[ 17.152560] systemd[1]: Created slice user.slice - User and Session Slice.
10831 23:26:31.565482 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10832 23:26:31.565576
10833 23:26:31.585099 <30>[ 17.175407] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10834 23:26:31.591618 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10835 23:26:31.591719
10836 23:26:31.613398 <30>[ 17.203944] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10837 23:26:31.619980 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10838 23:26:31.620072
10839 23:26:31.647741 <30>[ 17.231817] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10840 23:26:31.657644 <30>[ 17.251674] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10841 23:26:31.664542 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10842 23:26:31.664669
10843 23:26:31.681890 <30>[ 17.275710] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10844 23:26:31.688522 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10845 23:26:31.691639
10846 23:26:31.705819 <30>[ 17.299375] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10847 23:26:31.715421 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10848 23:26:31.715520
10849 23:26:31.730916 <30>[ 17.327904] systemd[1]: Reached target paths.target - Path Units.
10850 23:26:31.737711 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10851 23:26:31.737847
10852 23:26:31.757778 <30>[ 17.351832] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10853 23:26:31.764454 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10854 23:26:31.764549
10855 23:26:31.778149 <30>[ 17.375347] systemd[1]: Reached target slices.target - Slice Units.
10856 23:26:31.788516 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10857 23:26:31.788605
10858 23:26:31.802733 <30>[ 17.399862] systemd[1]: Reached target swap.target - Swaps.
10859 23:26:31.809485 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10860 23:26:31.809593
10861 23:26:31.830157 <30>[ 17.423854] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10862 23:26:31.839963 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10863 23:26:31.840074
10864 23:26:31.857931 <30>[ 17.451838] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10865 23:26:31.867921 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10866 23:26:31.868076
10867 23:26:31.887752 <30>[ 17.481575] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10868 23:26:31.897695 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10869 23:26:31.897844
10870 23:26:31.914356 <30>[ 17.508227] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10871 23:26:31.924164 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10872 23:26:31.924302
10873 23:26:31.942469 <30>[ 17.536205] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10874 23:26:31.948796 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10875 23:26:31.948893
10876 23:26:31.966294 <30>[ 17.560134] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10877 23:26:31.975826 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10878 23:26:31.975973
10879 23:26:31.994807 <30>[ 17.588668] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10880 23:26:32.001648 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10881 23:26:32.004885
10882 23:26:32.045836 <30>[ 17.639563] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10883 23:26:32.052502 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10884 23:26:32.052614
10885 23:26:32.074307 <30>[ 17.668193] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10886 23:26:32.080887 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10887 23:26:32.080983
10888 23:26:32.106479 <30>[ 17.700296] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10889 23:26:32.113188 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10890 23:26:32.113372
10891 23:26:32.140502 <30>[ 17.727893] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10892 23:26:32.182135 <30>[ 17.775781] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10893 23:26:32.191821 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10894 23:26:32.191977
10895 23:26:32.215447 <30>[ 17.809182] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10896 23:26:32.222009 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10897 23:26:32.222148
10898 23:26:32.247389 <30>[ 17.841316] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10899 23:26:32.260767 Starting [0;1;39mmodpr<6>[ 17.852576] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10900 23:26:32.263997 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10901 23:26:32.264097
10902 23:26:32.305752 <30>[ 17.899769] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10903 23:26:32.312260 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10904 23:26:32.312391
10905 23:26:32.335142 <30>[ 17.929004] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10906 23:26:32.341947 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10907 23:26:32.345189
10908 23:26:32.367407 <30>[ 17.961178] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10909 23:26:32.373915 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10910 23:26:32.374007
10911 23:26:32.426160 <30>[ 18.019884] systemd[1]: Starting systemd-journald.service - Journal Service...
10912 23:26:32.432548 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10913 23:26:32.432647
10914 23:26:32.452755 <30>[ 18.046542] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10915 23:26:32.459180 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10916 23:26:32.459269
10917 23:26:32.484383 <30>[ 18.074836] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10918 23:26:32.490890 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10919 23:26:32.490976
10920 23:26:32.513392 <30>[ 18.107468] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10921 23:26:32.523448 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10922 23:26:32.523548
10923 23:26:32.545500 <30>[ 18.139337] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10924 23:26:32.552178 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10925 23:26:32.552304
10926 23:26:32.578687 <30>[ 18.172355] systemd[1]: Started systemd-journald.service - Journal Service.
10927 23:26:32.585000 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10928 23:26:32.585091
10929 23:26:32.604401 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10930 23:26:32.604494
10931 23:26:32.622203 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10932 23:26:32.622289
10933 23:26:32.642554 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10934 23:26:32.642643
10935 23:26:32.662776 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10936 23:26:32.662867
10937 23:26:32.684667 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10938 23:26:32.684773
10939 23:26:32.704526 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10940 23:26:32.704613
10941 23:26:32.724917 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10942 23:26:32.725002
10943 23:26:32.745277 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10944 23:26:32.745364
10945 23:26:32.769263 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10946 23:26:32.769348
10947 23:26:32.788209 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10948 23:26:32.788323
10949 23:26:32.811378 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10950 23:26:32.811470
10951 23:26:32.836083 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10952 23:26:32.836170
10953 23:26:32.854137 See 'systemctl status systemd-remount-fs.service' for details.
10954 23:26:32.854220
10955 23:26:32.875162 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10956 23:26:32.875246
10957 23:26:32.896839 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10958 23:26:32.896925
10959 23:26:32.950096 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10960 23:26:32.950207
10961 23:26:32.974744 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10962 23:26:32.974830
10963 23:26:32.996832 Startin<46>[ 18.591004] systemd-journald[186]: Received client request to flush runtime journal.
10964 23:26:33.003518 g [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10965 23:26:33.003602
10966 23:26:33.029302 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10967 23:26:33.029438
10968 23:26:33.053641 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10969 23:26:33.053729
10970 23:26:33.075575 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10971 23:26:33.075667
10972 23:26:33.099433 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10973 23:26:33.099523
10974 23:26:33.118825 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10975 23:26:33.118956
10976 23:26:33.142849 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10977 23:26:33.142961
10978 23:26:33.162701 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10979 23:26:33.162787
10980 23:26:33.222780 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10981 23:26:33.222902
10982 23:26:33.251089 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10983 23:26:33.251200
10984 23:26:33.269640 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10985 23:26:33.269726
10986 23:26:33.289652 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10987 23:26:33.289738
10988 23:26:33.341998 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10989 23:26:33.342108
10990 23:26:33.366134 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10991 23:26:33.366228
10992 23:26:33.386861 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10993 23:26:33.386948
10994 23:26:33.408793 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10995 23:26:33.408893
10996 23:26:33.465922 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10997 23:26:33.466115
10998 23:26:33.643206 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10999 23:26:33.643390
11000 23:26:33.668451 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11001 23:26:33.668605
11002 23:26:33.715273 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11003 23:26:33.715424
11004 23:26:33.736211 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11005 23:26:33.736444
11006 23:26:33.756261 <6>[ 19.350379] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11007 23:26:33.766466 [[0;32m OK [<6>[ 19.360269] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11008 23:26:33.776151 0m] Created slice [0;1;39msyste<6>[ 19.371557] usbcore: registered new device driver r8152-cfgselector
11009 23:26:33.786127 m-syste…- Slic<6>[ 19.373952] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11010 23:26:33.789554 e /system/systemd-backlight.
11011 23:26:33.789706
11012 23:26:33.800228 <3>[ 19.394206] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11013 23:26:33.810221 [[0;32m OK [<3>[ 19.403569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11014 23:26:33.816797 <4>[ 19.405531] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11015 23:26:33.826831 <3>[ 19.413723] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11016 23:26:33.836528 0m] Reached target [0;1;39mtime-set.target[0m <4>[ 19.431582] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11017 23:26:33.846563 - System Time Se<3>[ 19.438647] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11018 23:26:33.846710 t.
11019 23:26:33.846780
11020 23:26:33.856361 <3>[ 19.449925] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11021 23:26:33.859693 <6>[ 19.453531] mc: Linux media interface: v0.10
11022 23:26:33.869721 <3>[ 19.458106] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11023 23:26:33.876150 <6>[ 19.462063] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11024 23:26:33.886199 <6>[ 19.465895] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11025 23:26:33.892878 <3>[ 19.471148] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11026 23:26:33.902794 <6>[ 19.492045] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11027 23:26:33.909254 <3>[ 19.495282] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11028 23:26:33.919293 <4>[ 19.502175] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11029 23:26:33.929434 <4>[ 19.502186] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11030 23:26:33.935916 <6>[ 19.505635] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11031 23:26:33.945838 <6>[ 19.512412] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11032 23:26:33.949384 <6>[ 19.512418] pci_bus 0000:00: root bus resource [bus 00-ff]
11033 23:26:33.956261 <6>[ 19.512422] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11034 23:26:33.966330 <6>[ 19.512428] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11035 23:26:33.973267 <6>[ 19.512454] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11036 23:26:33.979820 <6>[ 19.512467] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11037 23:26:33.986429 <6>[ 19.512530] pci 0000:00:00.0: supports D1 D2
11038 23:26:33.992900 <6>[ 19.512532] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11039 23:26:33.999753 <6>[ 19.513393] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11040 23:26:34.006217 <6>[ 19.513471] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11041 23:26:34.016337 <3>[ 19.513491] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11042 23:26:34.022911 <6>[ 19.513497] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11043 23:26:34.029392 <6>[ 19.513514] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11044 23:26:34.039397 <3>[ 19.513525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11045 23:26:34.045998 <3>[ 19.513527] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11046 23:26:34.052559 <3>[ 19.513530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11047 23:26:34.062464 <3>[ 19.513575] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11048 23:26:34.069252 <3>[ 19.513578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11049 23:26:34.079329 <3>[ 19.513580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11050 23:26:34.085827 <3>[ 19.513583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11051 23:26:34.095934 <3>[ 19.513586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11052 23:26:34.102264 <3>[ 19.513596] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11053 23:26:34.112272 <4>[ 19.533710] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11054 23:26:34.115649 <4>[ 19.533710] Fallback method does not support PEC.
11055 23:26:34.125295 <6>[ 19.540202] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11056 23:26:34.132409 <6>[ 19.550579] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11057 23:26:34.139383 <6>[ 19.552513] pci 0000:01:00.0: supports D1 D2
11058 23:26:34.145782 <6>[ 19.552514] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11059 23:26:34.149045 <6>[ 19.552664] r8152 2-1.3:1.0 eth0: v1.12.13
11060 23:26:34.159392 <3>[ 19.564515] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11061 23:26:34.162427 <6>[ 19.569960] usbcore: registered new interface driver r8152
11062 23:26:34.169357 <6>[ 19.571168] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11063 23:26:34.179295 <6>[ 19.571199] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11064 23:26:34.185558 <6>[ 19.571202] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11065 23:26:34.195808 <6>[ 19.571210] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11066 23:26:34.202293 <6>[ 19.571223] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11067 23:26:34.209151 <6>[ 19.571236] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11068 23:26:34.216906 <6>[ 19.571248] pci 0000:00:00.0: PCI bridge to [bus 01]
11069 23:26:34.223878 <6>[ 19.571253] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11070 23:26:34.230122 <6>[ 19.571404] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11071 23:26:34.236717 <6>[ 19.572022] pcieport 0000:00:00.0: PME: Signaling with IRQ 281
11072 23:26:34.240232 <6>[ 19.576592] pcieport 0000:00:00.0: AER: enabled with IRQ 281
11073 23:26:34.247613 <6>[ 19.578199] videodev: Linux video capture interface: v2.00
11074 23:26:34.254094 <6>[ 19.586387] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11075 23:26:34.260946 <6>[ 19.595794] usbcore: registered new interface driver cdc_ether
11076 23:26:34.267409 <6>[ 19.605698] remoteproc remoteproc0: scp is available
11077 23:26:34.270705 <6>[ 19.610326] Bluetooth: Core ver 2.22
11078 23:26:34.274066 <6>[ 19.617941] remoteproc remoteproc0: powering up scp
11079 23:26:34.280833 <6>[ 19.625002] NET: Registered PF_BLUETOOTH protocol family
11080 23:26:34.287299 <6>[ 19.625205] usbcore: registered new interface driver r8153_ecm
11081 23:26:34.293867 <6>[ 19.633417] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11082 23:26:34.300529 <6>[ 19.640526] Bluetooth: HCI device and connection manager initialized
11083 23:26:34.308111 <6>[ 19.640546] Bluetooth: HCI socket layer initialized
11084 23:26:34.311234 <6>[ 19.648686] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11085 23:26:34.317762 <6>[ 19.656702] Bluetooth: L2CAP socket layer initialized
11086 23:26:34.324513 <6>[ 19.656727] Bluetooth: SCO socket layer initialized
11087 23:26:34.331208 <6>[ 19.658006] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11088 23:26:34.341544 <6>[ 19.659206] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11089 23:26:34.348138 <6>[ 19.659527] usbcore: registered new interface driver uvcvideo
11090 23:26:34.354904 <6>[ 19.679183] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11091 23:26:34.364860 <5>[ 19.680461] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11092 23:26:34.368243 <6>[ 19.682315] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11093 23:26:34.374993 <5>[ 19.697868] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11094 23:26:34.382201 <6>[ 19.727060] usbcore: registered new interface driver btusb
11095 23:26:34.392122 <4>[ 19.727763] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11096 23:26:34.398540 <3>[ 19.727772] Bluetooth: hci0: Failed to load firmware file (-2)
11097 23:26:34.405437 <3>[ 19.727774] Bluetooth: hci0: Failed to set up firmware (-2)
11098 23:26:34.415514 <4>[ 19.727775] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11099 23:26:34.421947 <5>[ 19.736079] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11100 23:26:34.431826 <6>[ 19.790953] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11101 23:26:34.438283 <6>[ 19.790990] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11102 23:26:34.445046 <6>[ 19.791007] remoteproc remoteproc0: remote processor scp is now up
11103 23:26:34.454708 <4>[ 19.797953] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11104 23:26:34.461260 <3>[ 19.816250] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11105 23:26:34.471513 <3>[ 19.817060] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
11106 23:26:34.474669 <6>[ 19.818185] cfg80211: failed to load regulatory.db
11107 23:26:34.484507 <3>[ 19.819928] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11108 23:26:34.494822 <6>[ 19.821205] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11109 23:26:34.501499 <3>[ 19.822250] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11110 23:26:34.508773 <6>[ 19.823738] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11111 23:26:34.518959 <3>[ 19.846319] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11112 23:26:34.525575 <6>[ 19.884574] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11113 23:26:34.535532 <3>[ 19.911350] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11114 23:26:34.540964 <6>[ 19.915514] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11115 23:26:34.548946 <3>[ 19.942009] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11116 23:26:34.555123 <6>[ 19.963355] mt7921e 0000:01:00.0: ASIC revision: 79610010
11117 23:26:34.561876 <3>[ 19.988959] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11118 23:26:34.572040 <6>[ 20.085898] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11119 23:26:34.572162 <6>[ 20.085898]
11120 23:26:34.581848 <3>[ 20.108076] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11121 23:26:34.588572 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11122 23:26:34.588710
11123 23:26:34.611752 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11124 23:26:34.611925
11125 23:26:34.664087 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11126 23:26:34.664216
11127 23:26:34.681710 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11128 23:26:34.681837
11129 23:26:34.697857 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11130 23:26:34.698010
11131 23:26:34.717490 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11132 23:26:34.717629
11133 23:26:34.733313 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11134 23:26:34.733464
11135 23:26:34.749937 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11136 23:26:34.750052
11137 23:26:34.769586 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11138 23:26:34.769705
11139 23:26:34.775981 <6>[ 20.371428] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11140 23:26:34.785905 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11141 23:26:34.786038
11142 23:26:34.805942 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11143 23:26:34.806076
11144 23:26:34.842405 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11145 23:26:34.842543
11146 23:26:34.871988 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11147 23:26:34.872185
11148 23:26:34.895281 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11149 23:26:34.895417
11150 23:26:34.928891 [[0;32m OK [<46>[ 20.509792] systemd-journald[186]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.0 (1536 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
11151 23:26:34.945293 0m] Started [0;<46>[ 20.532309] systemd-journald[186]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11152 23:26:34.951813 1;39mdbus.service[0m - D-Bus System Message Bus.
11153 23:26:34.951946
11154 23:26:34.978377 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11155 23:26:34.978516
11156 23:26:35.018795 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11157 23:26:35.018929
11158 23:26:35.039199 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11159 23:26:35.039329
11160 23:26:35.057817 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11161 23:26:35.057937
11162 23:26:35.094275 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11163 23:26:35.094410
11164 23:26:35.114871 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11165 23:26:35.115025
11166 23:26:35.134719 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11167 23:26:35.134866
11168 23:26:35.156448 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11169 23:26:35.156599
11170 23:26:35.174211 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11171 23:26:35.174352
11172 23:26:35.215240 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11173 23:26:35.215368
11174 23:26:35.258138 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11175 23:26:35.258348
11176 23:26:35.306698
11177 23:26:35.306895
11178 23:26:35.309855 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11179 23:26:35.309944
11180 23:26:35.313236 debian-bookworm-arm64 login: root (automatic login)
11181 23:26:35.313318
11182 23:26:35.313382
11183 23:26:35.328250 Linux debian-bookworm-arm64 6.1.83-cip18 #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024 aarch64
11184 23:26:35.328372
11185 23:26:35.334673 The programs included with the Debian GNU/Linux system are free software;
11186 23:26:35.341103 the exact distribution terms for each program are described in the
11187 23:26:35.344590 individual files in /usr/share/doc/*/copyright.
11188 23:26:35.344671
11189 23:26:35.351224 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11190 23:26:35.354532 permitted by applicable law.
11191 23:26:35.354916 Matched prompt #10: / #
11193 23:26:35.355120 Setting prompt string to ['/ #']
11194 23:26:35.355213 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11196 23:26:35.355404 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11197 23:26:35.355491 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
11198 23:26:35.355563 Setting prompt string to ['/ #']
11199 23:26:35.355623 Forcing a shell prompt, looking for ['/ #']
11201 23:26:35.405830 / #
11202 23:26:35.405937 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11203 23:26:35.406051 Waiting using forced prompt support (timeout 00:02:30)
11204 23:26:35.410311
11205 23:26:35.410584 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11206 23:26:35.410676 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
11207 23:26:35.410768 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11208 23:26:35.410853 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
11209 23:26:35.410936 end: 2 depthcharge-action (duration 00:01:42) [common]
11210 23:26:35.411021 start: 3 lava-test-retry (timeout 00:07:50) [common]
11211 23:26:35.411108 start: 3.1 lava-test-shell (timeout 00:07:50) [common]
11212 23:26:35.411181 Using namespace: common
11214 23:26:35.511513 / # #
11215 23:26:35.511639 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11216 23:26:35.516239 #
11217 23:26:35.516556 Using /lava-13248445
11219 23:26:35.616891 / # export SHELL=/bin/sh
11220 23:26:35.621504 export SHELL=/bin/sh
11222 23:26:35.722030 / # . /lava-13248445/environment
11223 23:26:35.722180 <6>[ 21.251462] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11224 23:26:35.726558 . /lava-13248445/environment
11226 23:26:35.827093 / # /lava-13248445/bin/lava-test-runner /lava-13248445/0
11227 23:26:35.827360 Test shell timeout: 10s (minimum of the action and connection timeout)
11228 23:26:35.832202 /lava-13248445/bin/lava-test-runner /lava-13248445/0
11229 23:26:35.864230 + export TESTRUN_ID=0_igt-kms-medi<8>[ 21.460318] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 13248445_1.5.2.3.1>
11230 23:26:35.864636 Received signal: <STARTRUN> 0_igt-kms-mediatek 13248445_1.5.2.3.1
11231 23:26:35.864775 Starting test lava.0_igt-kms-mediatek (13248445_1.5.2.3.1)
11232 23:26:35.864970 Skipping test definition patterns.
11233 23:26:35.867455 atek
11234 23:26:35.871094 + cd /lava-13248445/0/tests/0_igt-kms-mediatek
11235 23:26:35.871219 + cat uuid
11236 23:26:35.874226 + UUID=13248445_1.5.2.3.1
11237 23:26:35.874425 + set +x
11238 23:26:35.893724 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11239 23:26:35.904634 <8>[ 21.502097] <LAVA_SIGNAL_TESTSET START core_auth>
11240 23:26:35.904966 Received signal: <TESTSET> START core_auth
11241 23:26:35.905094 Starting test_set core_auth
11242 23:26:35.934185 <14>[ 21.531656] [IGT] core_auth: executing
11243 23:26:35.940633 IGT-Version: 1.2<14>[ 21.536295] [IGT] core_auth: starting subtest getclient-simple
11244 23:26:35.950682 8-ga44ebfe (aarc<14>[ 21.543872] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11245 23:26:35.954101 h64) (Linux: 6.1<14>[ 21.552108] [IGT] core_auth: exiting, ret=0
11246 23:26:35.957393 .83-cip18 aarch64)
11247 23:26:35.960359 Using IGT_SRANDOM=1712186622 for randomisation
11248 23:26:35.970666 Starting sub<8>[ 21.564376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11249 23:26:35.970797 test: getclient-simple
11250 23:26:35.971096 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11252 23:26:35.973562 Opened device: /dev/dri/card0
11253 23:26:35.979972 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11254 23:26:35.996656 <14>[ 21.594399] [IGT] core_auth: executing
11255 23:26:36.003218 IGT-Version: 1.2<14>[ 21.598926] [IGT] core_auth: starting subtest getclient-master-drop
11256 23:26:36.013075 8-ga44ebfe (aarc<14>[ 21.607152] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11257 23:26:36.020012 h64) (Linux: 6.1<14>[ 21.615574] [IGT] core_auth: exiting, ret=0
11258 23:26:36.020143 .83-cip18 aarch64)
11259 23:26:36.026494 Using IGT_SRANDOM=1712186622 for randomisation
11260 23:26:36.036281 Starting subtest: getclient-<8>[ 21.628815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11261 23:26:36.036416 master-drop
11262 23:26:36.036719 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11264 23:26:36.039343 Opened device: /dev/dri/card0
11265 23:26:36.042698 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11266 23:26:36.054361 <14>[ 21.652052] [IGT] core_auth: executing
11267 23:26:36.061057 IGT-Version: 1.2<14>[ 21.656495] [IGT] core_auth: starting subtest basic-auth
11268 23:26:36.067721 8-ga44ebfe (aarc<14>[ 21.663433] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11269 23:26:36.074108 <14>[ 21.671208] [IGT] core_auth: exiting, ret=0
11270 23:26:36.077708 h64) (Linux: 6.1.83-cip18 aarch64)
11271 23:26:36.087489 Using IGT_SRANDOM=1712186622 for randomisati<8>[ 21.681962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11272 23:26:36.087580 on
11273 23:26:36.087825 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11275 23:26:36.090951 Opened device: /dev/dri/card0
11276 23:26:36.091055 Starting subtest: basic-auth
11277 23:26:36.097426 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11278 23:26:36.115059 <14>[ 21.712568] [IGT] core_auth: executing
11279 23:26:36.121556 IGT-Version: 1.2<14>[ 21.717346] [IGT] core_auth: starting subtest many-magics
11280 23:26:36.124849 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11281 23:26:36.131452 Using IGT_SRANDOM=1712186622 for randomisation
11282 23:26:36.138001 Opened device: /dev/dri/card<14>[ 21.734944] [IGT] core_auth: finished subtest many-magics, SUCCESS
11283 23:26:36.138128 0
11284 23:26:36.144798 Starting subt<14>[ 21.741868] [IGT] core_auth: exiting, ret=0
11285 23:26:36.147958 est: many-magics
11286 23:26:36.151298 Reopening device failed after 1020 opens
11287 23:26:36.161176 [1mSubtest many-magics: SUCCESS (0.<8>[ 21.754860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11288 23:26:36.161261 011s)[0m
11289 23:26:36.161504 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11291 23:26:36.164470 <8>[ 21.764689] <LAVA_SIGNAL_TESTSET STOP>
11292 23:26:36.164754 Received signal: <TESTSET> STOP
11293 23:26:36.164861 Closing test_set core_auth
11294 23:26:36.216886 <14>[ 21.814469] [IGT] core_getclient: executing
11295 23:26:36.223337 IGT-Version: 1.2<14>[ 21.819826] [IGT] core_getclient: exiting, ret=0
11296 23:26:36.226748 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11297 23:26:36.236688 Using IGT_SRANDOM=1712186622<8>[ 21.832123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11298 23:26:36.236996 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11300 23:26:36.240006 for randomisation
11301 23:26:36.243225 Opened device: /dev/dri/card0
11302 23:26:36.243350 SUCCESS (0.006s)
11303 23:26:36.286689 <14>[ 21.884258] [IGT] core_getstats: executing
11304 23:26:36.293141 IGT-Version: 1.2<14>[ 21.889451] [IGT] core_getstats: exiting, ret=0
11305 23:26:36.296399 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11306 23:26:36.299824 Using IGT_SRANDOM=1712186622 for randomisation
11307 23:26:36.309847 Opened devic<8>[ 21.904196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11308 23:26:36.309964 e: /dev/dri/card0
11309 23:26:36.310234 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11311 23:26:36.313085 SUCCESS (0.006s)
11312 23:26:36.358463 <14>[ 21.955938] [IGT] core_getversion: executing
11313 23:26:36.365015 IGT-Version: 1.2<14>[ 21.961262] [IGT] core_getversion: exiting, ret=0
11314 23:26:36.367959 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11315 23:26:36.378030 Using IGT_SRANDOM=1712186622<8>[ 21.973482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11316 23:26:36.378313 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11318 23:26:36.381773 for randomisation
11319 23:26:36.384819 Opened device: /dev/dri/card0
11320 23:26:36.384930 SUCCESS (0.006s)
11321 23:26:36.428745 <14>[ 22.026318] [IGT] core_setmaster_vs_auth: executing
11322 23:26:36.435319 IGT-Version: 1.2<14>[ 22.032340] [IGT] core_setmaster_vs_auth: exiting, ret=0
11323 23:26:36.442003 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11324 23:26:36.451909 Using IGT_SRANDOM=1712186622<8>[ 22.045093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11325 23:26:36.452004 for randomisation
11326 23:26:36.452248 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11328 23:26:36.455146 Opened device: /dev/dri/card0
11329 23:26:36.458387 SUCCESS (0.007s)
11330 23:26:36.474950 <8>[ 22.072792] <LAVA_SIGNAL_TESTSET START drm_read>
11331 23:26:36.475214 Received signal: <TESTSET> START drm_read
11332 23:26:36.475288 Starting test_set drm_read
11333 23:26:36.504508 <14>[ 22.102194] [IGT] drm_read: executing
11334 23:26:36.511081 IGT-Version: 1.2<14>[ 22.107156] [IGT] drm_read: exiting, ret=77
11335 23:26:36.514761 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11336 23:26:36.524352 Using IGT_SRANDOM=1712186622<8>[ 22.118724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11337 23:26:36.524488 for randomisation
11338 23:26:36.524790 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11340 23:26:36.527489 Opened device: /dev/dri/card0
11341 23:26:36.534556 No KMS driver or no outputs, pipes: 16, outputs: 0
11342 23:26:36.537519 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11343 23:26:36.544477 <14>[ 22.142178] [IGT] drm_read: executing
11344 23:26:36.547662 IGT-Version: 1.2<14>[ 22.146689] [IGT] drm_read: exiting, ret=77
11345 23:26:36.554639 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11346 23:26:36.564487 Using IGT_SRANDOM=1712186623<8>[ 22.158371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11347 23:26:36.564620 for randomisation
11348 23:26:36.564920 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11350 23:26:36.567641 Opened device: /dev/dri/card0
11351 23:26:36.571050 No KMS driver or no outputs, pipes: 16, outputs: 0
11352 23:26:36.577377 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11353 23:26:36.584158 <14>[ 22.181756] [IGT] drm_read: executing
11354 23:26:36.587382 IGT-Version: 1.2<14>[ 22.186254] [IGT] drm_read: exiting, ret=77
11355 23:26:36.594209 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11356 23:26:36.604024 Using IGT_SRANDOM=1712186623<8>[ 22.198107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11357 23:26:36.604161 for randomisation
11358 23:26:36.604456 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11360 23:26:36.607226 Opened device: /dev/dri/card0
11361 23:26:36.610849 No KMS driver or no outputs, pipes: 16, outputs: 0
11362 23:26:36.614260 [1mSubtest empty-block: SKIP (0.000s)[0m
11363 23:26:36.621461 <14>[ 22.219215] [IGT] drm_read: executing
11364 23:26:36.628098 IGT-Version: 1.2<14>[ 22.223701] [IGT] drm_read: exiting, ret=77
11365 23:26:36.631519 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11366 23:26:36.641460 Using IGT_SRANDOM=1712186623<8>[ 22.235773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11367 23:26:36.641599 for randomisation
11368 23:26:36.641898 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11370 23:26:36.644562 Opened device: /dev/dri/card0
11371 23:26:36.651254 No KMS driver or no outputs, pipes: 16, outputs: 0
11372 23:26:36.654378 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11373 23:26:36.657887 <14>[ 22.256875] [IGT] drm_read: executing
11374 23:26:36.664446 IGT-Version: 1.2<14>[ 22.261450] [IGT] drm_read: exiting, ret=77
11375 23:26:36.667736 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11376 23:26:36.677524 Using IGT_SRANDOM=1712186623<8>[ 22.273292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11377 23:26:36.677811 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11379 23:26:36.681041 for randomisation
11380 23:26:36.684503 Opened device: /dev/dri/card0
11381 23:26:36.687828 No KMS driver or no outputs, pipes: 16, outputs: 0
11382 23:26:36.691095 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11383 23:26:36.706845 <14>[ 22.304387] [IGT] drm_read: executing
11384 23:26:36.713335 IGT-Version: 1.2<14>[ 22.309214] [IGT] drm_read: exiting, ret=77
11385 23:26:36.716776 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11386 23:26:36.726940 Using IGT_SRANDOM=1712186623<8>[ 22.320642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11387 23:26:36.727201 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11389 23:26:36.730234 for randomisation
11390 23:26:36.730311 Opened device: /dev/dri/card0
11391 23:26:36.736807 No KMS driver or no outputs, pipes: 16, outputs: 0
11392 23:26:36.740236 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11393 23:26:36.755113 <14>[ 22.352816] [IGT] drm_read: executing
11394 23:26:36.761816 IGT-Version: 1.2<14>[ 22.357594] [IGT] drm_read: exiting, ret=77
11395 23:26:36.765142 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11396 23:26:36.774977 Using IGT_SRANDOM=1712186623<8>[ 22.369051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11397 23:26:36.775094 for randomisation
11398 23:26:36.775367 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11400 23:26:36.781598 Opened devic<8>[ 22.379503] <LAVA_SIGNAL_TESTSET STOP>
11401 23:26:36.781703 e: /dev/dri/card0
11402 23:26:36.781977 Received signal: <TESTSET> STOP
11403 23:26:36.782068 Closing test_set drm_read
11404 23:26:36.788494 No KMS driver or no outputs, pipes: 16, outputs: 0
11405 23:26:36.791457 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11406 23:26:36.813158 <8>[ 22.410908] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11407 23:26:36.813481 Received signal: <TESTSET> START kms_addfb_basic
11408 23:26:36.813604 Starting test_set kms_addfb_basic
11409 23:26:36.840247 <14>[ 22.438131] [IGT] kms_addfb_basic: executing
11410 23:26:36.853757 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch6<14>[ 22.448110] [IGT] kms_addfb_basic: starting subtest unused-handle
11411 23:26:36.853877 4)
11412 23:26:36.860193 Using IGT_SR<14>[ 22.455463] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11413 23:26:36.863516 ANDOM=1712186623 for randomisation
11414 23:26:36.867006 Opened device: /dev/dri/card0
11415 23:26:36.870107 Starting subtest: unused-handle
11416 23:26:36.876875 [1mSubtest <14>[ 22.472778] [IGT] kms_addfb_basic: exiting, ret=0
11417 23:26:36.880383 unused-handle: SUCCESS (0.000s)[0m
11418 23:26:36.890186 Test requirement not met in function igt_require_intel, fil<8>[ 22.485812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11419 23:26:36.890475 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11421 23:26:36.893717 e ../lib/drmtest.c:880:
11422 23:26:36.896821 Test requirement: is_intel_device(fd)
11423 23:26:36.903459 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11424 23:26:36.909995 Test requirement: is_intel_d<14>[ 22.508788] [IGT] kms_addfb_basic: executing
11425 23:26:36.913174 evice(fd)
11426 23:26:36.916516 No KMS driver or no outputs, pipes: 16, outputs: 0
11427 23:26:36.923488 I<14>[ 22.518729] [IGT] kms_addfb_basic: starting subtest unused-pitches
11428 23:26:36.933215 GT-Version: 1.28<14>[ 22.526703] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11429 23:26:36.936327 -ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11430 23:26:36.946239 Using IGT_SRANDOM=1712186623 for randomisatio<14>[ 22.543388] [IGT] kms_addfb_basic: exiting, ret=0
11431 23:26:36.946330 n
11432 23:26:36.949765 Opened device: /dev/dri/card0
11433 23:26:36.953123 Starting subtest: unused-pitches
11434 23:26:36.959946 [1mSubtest <8>[ 22.555620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11435 23:26:36.960216 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11437 23:26:36.963107 unused-pitches: SUCCESS (0.000s)[0m
11438 23:26:36.969940 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11439 23:26:36.973094 Test requirement: is_intel_device(fd)
11440 23:26:36.983036 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11441 23:26:36.986408 Test requirement: is_intel_device(fd)
11442 23:26:36.989627 No K<14>[ 22.586417] [IGT] kms_addfb_basic: executing
11443 23:26:36.992877 MS driver or no outputs, pipes: 16, outputs: 0
11444 23:26:37.002532 IGT-Version: 1.2<14>[ 22.597489] [IGT] kms_addfb_basic: starting subtest unused-offsets
11445 23:26:37.009384 8-ga44ebfe (aarc<14>[ 22.604716] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11446 23:26:37.012685 h64) (Linux: 6.1.83-cip18 aarch64)
11447 23:26:37.019374 Using IGT_SRANDOM=1712186623 for randomisation
11448 23:26:37.026024 Opened device: /dev/dri/card<14>[ 22.622317] [IGT] kms_addfb_basic: exiting, ret=0
11449 23:26:37.026113 0
11450 23:26:37.029265 Starting subtest: unused-offsets
11451 23:26:37.032312 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11452 23:26:37.042200 Test requ<8>[ 22.635458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11453 23:26:37.042469 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11455 23:26:37.049123 irement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11456 23:26:37.052238 Test requirement: is_intel_device(fd)
11457 23:26:37.061997 Test requirement not met in function igt_require_intel, file .<14>[ 22.657787] [IGT] kms_addfb_basic: executing
11458 23:26:37.062111 ./lib/drmtest.c:880:
11459 23:26:37.065049 Test requirement: is_intel_device(fd)
11460 23:26:37.071721 No <14>[ 22.668180] [IGT] kms_addfb_basic: starting subtest unused-modifier
11461 23:26:37.081596 KMS driver or no<14>[ 22.676053] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11462 23:26:37.084934 outputs, pipes: 16, outputs: 0
11463 23:26:37.095137 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch<14>[ 22.692839] [IGT] kms_addfb_basic: exiting, ret=0
11464 23:26:37.095307 64)
11465 23:26:37.101434 Using IGT_SRANDOM=1712186623 for randomisation
11466 23:26:37.108080 Opened device: /dev/dri/car<8>[ 22.704943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11467 23:26:37.108419 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11469 23:26:37.111340 d0
11470 23:26:37.114529 Starting subtest: unused-modifier
11471 23:26:37.117895 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11472 23:26:37.124414 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11473 23:26:37.131225 Te<14>[ 22.726834] [IGT] kms_addfb_basic: executing
11474 23:26:37.134449 st requirement: is_intel_device(fd)
11475 23:26:37.141304 Test requirement not met in<14>[ 22.736739] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11476 23:26:37.150890 function igt_re<14>[ 22.745113] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11477 23:26:37.154604 quire_intel, file ../lib/drmtest.c:880:
11478 23:26:37.157471 Test requirement: is_intel_device(fd)
11479 23:26:37.164195 No KMS driver or<14>[ 22.761902] [IGT] kms_addfb_basic: exiting, ret=77
11480 23:26:37.167410 no outputs, pipes: 16, outputs: 0
11481 23:26:37.180774 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aa<8>[ 22.774473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11482 23:26:37.180909 rch64)
11483 23:26:37.181212 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11485 23:26:37.184153 Using IGT_SRANDOM=1712186623 for randomisation
11486 23:26:37.187324 Opened device: /dev/dri/card0
11487 23:26:37.190492 Starting subtest: clobberred-modifier
11488 23:26:37.197281 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:885:
11489 23:26:37.200642 Test requirement: is_i915_device(fd)
11490 23:26:37.210340 [1mSubtest clobberred-modifier: SKIP (0.<14>[ 22.806981] [IGT] kms_addfb_basic: executing
11491 23:26:37.210433 000s)[0m
11492 23:26:37.223805 Test requirement not met in function igt_require_inte<14>[ 22.818001] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11493 23:26:37.233792 l, file ../lib/d<14>[ 22.826316] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11494 23:26:37.233894 rmtest.c:880:
11495 23:26:37.236998 Test requirement: is_intel_device(fd)
11496 23:26:37.246924 Test requirement not met in function igt_require_intel, fi<14>[ 22.844731] [IGT] kms_addfb_basic: exiting, ret=77
11497 23:26:37.250222 le ../lib/drmtest.c:880:
11498 23:26:37.253388 Test requirement: is_intel_device(fd)
11499 23:26:37.263510 No KMS driver or no outputs, pi<8>[ 22.857718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11500 23:26:37.263811 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11502 23:26:37.266915 pes: 16, outputs: 0
11503 23:26:37.273466 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11504 23:26:37.276740 Using IGT_SRANDOM=1712186623 for randomisation
11505 23:26:37.279950 Opened device: /dev/dri/card0
11506 23:26:37.283570 Starting subtest: invalid-smem-bo-on-discrete
11507 23:26:37.293489 Test requirement not met in function igt_require_intel, f<14>[ 22.890789] [IGT] kms_addfb_basic: executing
11508 23:26:37.296566 ile ../lib/drmtest.c:880:
11509 23:26:37.306578 Test requirement: is_intel_device(fd)<14>[ 22.900450] [IGT] kms_addfb_basic: starting subtest legacy-format
11510 23:26:37.306743
11511 23:26:37.309901 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11512 23:26:37.323005 Test requirement not met in function igt_require_intel, file ../li<14>[ 22.917862] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11513 23:26:37.326218 b/drmtest.c:880:
11514 23:26:37.329613 Test requirement: is_intel_device(fd)
11515 23:26:37.339708 Test requirement not met in function igt_require_intel,<14>[ 22.934822] [IGT] kms_addfb_basic: exiting, ret=0
11516 23:26:37.339857 file ../lib/drmtest.c:880:
11517 23:26:37.343055 Test requirement: is_intel_device(fd)
11518 23:26:37.353035 No KMS drive<8>[ 22.947591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11519 23:26:37.353367 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11521 23:26:37.356213 r or no outputs, pipes: 16, outputs: 0
11522 23:26:37.363046 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11523 23:26:37.366283 Using IGT_SRANDOM=1712186623 for randomisation
11524 23:26:37.369557 Open<14>[ 22.968575] [IGT] kms_addfb_basic: executing
11525 23:26:37.373208 ed device: /dev/dri/card0
11526 23:26:37.376161 Starting subtest: legacy-format
11527 23:26:37.383068 Successfully fuzzed <14>[ 22.980175] [IGT] kms_addfb_basic: starting subtest no-handle
11528 23:26:37.392862 10000 {bpp, dept<14>[ 22.986702] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11529 23:26:37.392955 h} variations
11530 23:26:37.399166 [1mSubtest legacy-format: SUCCESS (0.010s)[0m
11531 23:26:37.402609 Test requirement<14>[ 23.000833] [IGT] kms_addfb_basic: exiting, ret=0
11532 23:26:37.409335 not met in function igt_require_intel, file ../lib/drmtest.c:880:
11533 23:26:37.419364 Test require<8>[ 23.013830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11534 23:26:37.419537 ment: is_intel_device(fd)
11535 23:26:37.419860 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11537 23:26:37.428924 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11538 23:26:37.432237 Test requirement: is_intel_device(fd)
11539 23:26:37.438823 No KMS driver or no output<14>[ 23.034900] [IGT] kms_addfb_basic: executing
11540 23:26:37.438974 s, pipes: 16, outputs: 0
11541 23:26:37.448829 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-ci<14>[ 23.047389] [IGT] kms_addfb_basic: starting subtest basic
11542 23:26:37.452298 p18 aarch64)
11543 23:26:37.458939 Us<14>[ 23.053528] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11544 23:26:37.462119 ing IGT_SRANDOM=1712186623 for randomisation
11545 23:26:37.465573 Opened device: /dev/dri/card0
11546 23:26:37.472443 Sta<14>[ 23.067188] [IGT] kms_addfb_basic: exiting, ret=0
11547 23:26:37.472577 rting subtest: no-handle
11548 23:26:37.475671 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11549 23:26:37.485552 Test requ<8>[ 23.080085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11550 23:26:37.485865 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11552 23:26:37.492139 irement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11553 23:26:37.495319 Test requirement: is_intel_device(fd)
11554 23:26:37.502178 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11555 23:26:37.505527 Test requirement: is_intel_device(fd)
11556 23:26:37.508585 No KMS driver or no outputs, pipes: 16, outputs: 0
11557 23:26:37.515134 <14>[ 23.110424] [IGT] kms_addfb_basic: executing
11558 23:26:37.515241
11559 23:26:37.518681 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11560 23:26:37.528778 Using IGT_SRANDOM=171218662<14>[ 23.123867] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11561 23:26:37.535106 3 for randomisat<14>[ 23.131277] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11562 23:26:37.538550 ion
11563 23:26:37.538633 Opened device: /dev/dri/card0
11564 23:26:37.541875 Starting subtest: basic
11565 23:26:37.548248 [1mSubtest basic: <14>[ 23.146032] [IGT] kms_addfb_basic: exiting, ret=0
11566 23:26:37.551555 SUCCESS (0.000s)[0m
11567 23:26:37.565073 Test requirement not met in function igt_require_intel, file ../lib/drmtes<8>[ 23.158713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11568 23:26:37.565160 t.c:880:
11569 23:26:37.565403 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11571 23:26:37.568094 Test requirement: is_intel_device(fd)
11572 23:26:37.574816 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11573 23:26:37.577886 Test requirement: is_intel_device(fd)
11574 23:26:37.584885 No KMS driver or no outputs, pipes: 16, outputs: 0
11575 23:26:37.594687 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch6<14>[ 23.191055] [IGT] kms_addfb_basic: executing
11576 23:26:37.594771 4)
11577 23:26:37.597997 Using IGT_SRANDOM=1712186624 for randomisation
11578 23:26:37.601247 Opened device: /dev/dri/card0
11579 23:26:37.607964 Starting subt<14>[ 23.203814] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11580 23:26:37.618111 est: bad-pitch-0<14>[ 23.211345] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11581 23:26:37.618204
11582 23:26:37.621238 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11583 23:26:37.627987 Test requirement not met in fun<14>[ 23.226192] [IGT] kms_addfb_basic: exiting, ret=0
11584 23:26:37.634297 ction igt_require_intel, file ../lib/drmtest.c:880:
11585 23:26:37.637807 Test requirement: is_intel_device(fd)
11586 23:26:37.644452 Test<8>[ 23.238685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11587 23:26:37.644751 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11589 23:26:37.650917 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11590 23:26:37.654214 Test requirement: is_intel_device(fd)
11591 23:26:37.657597 No KMS driver or no outputs, pipes: 16, outputs: 0
11592 23:26:37.664501 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11593 23:26:37.667657 Using IGT_SRANDOM=1712186624 for randomisation
11594 23:26:37.674258 O<14>[ 23.270773] [IGT] kms_addfb_basic: executing
11595 23:26:37.677534 pened device: /dev/dri/card0
11596 23:26:37.681014 Starting subtest: bad-pitch-32
11597 23:26:37.687393 [1mSubtest bad-pitch-32: SUCCESS <14>[ 23.284106] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11598 23:26:37.691004 (0.000s)[0m
11599 23:26:37.697253 Te<14>[ 23.291584] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11600 23:26:37.710524 st requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:<14>[ 23.306480] [IGT] kms_addfb_basic: exiting, ret=0
11601 23:26:37.710612
11602 23:26:37.713866 Test requirement: is_intel_device(fd)
11603 23:26:37.724034 Test requirement not met in function ig<8>[ 23.318979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11604 23:26:37.724316 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11606 23:26:37.727131 t_require_intel, file ../lib/drmtest.c:880:
11607 23:26:37.730562 Test requirement: is_intel_device(fd)
11608 23:26:37.734053 No KMS driver or no outputs, pipes: 16, outputs: 0
11609 23:26:37.743606 IGT-Version: 1.28-ga44ebfe (aarch64) (Li<14>[ 23.340261] [IGT] kms_addfb_basic: executing
11610 23:26:37.747146 nux: 6.1.83-cip18 aarch64)
11611 23:26:37.750363 Using IGT_SRANDOM=1712186624 for randomisation
11612 23:26:37.757009 Open<14>[ 23.352708] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11613 23:26:37.766921 ed device: /dev/<14>[ 23.359542] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11614 23:26:37.767049 dri/card0
11615 23:26:37.770252 Starting subtest: bad-pitch-63
11616 23:26:37.776900 [1mSubtest bad-pitch-63: SUCCESS (0.<14>[ 23.373951] [IGT] kms_addfb_basic: exiting, ret=0
11617 23:26:37.777026 000s)[0m
11618 23:26:37.790150 Test requirement not met in function igt_require_intel, file ../lib/d<8>[ 23.386983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11619 23:26:37.790413 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11621 23:26:37.793441 rmtest.c:880:
11622 23:26:37.796504 Test requirement: is_intel_device(fd)
11623 23:26:37.803437 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11624 23:26:37.806399 Test requirement: is_intel_device(fd)
11625 23:26:37.810022 <14>[ 23.409186] [IGT] kms_addfb_basic: executing
11626 23:26:37.810105
11627 23:26:37.816506 No KMS driver or no outputs, pipes: 16, outputs: 0
11628 23:26:37.823160 IGT-Version: 1.28-ga44ebfe <14>[ 23.420786] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11629 23:26:37.833137 (aarch64) (Linux<14>[ 23.427728] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11630 23:26:37.836557 : 6.1.83-cip18 aarch64)
11631 23:26:37.839820 Using IGT_SRANDOM=1712186624 for randomisation
11632 23:26:37.846448 Opened <14>[ 23.442213] [IGT] kms_addfb_basic: exiting, ret=0
11633 23:26:37.846549 device: /dev/dri/card0
11634 23:26:37.849689 Starting subtest: bad-pitch-128
11635 23:26:37.859338 [1mSubtest bad-pitch-1<8>[ 23.455019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11636 23:26:37.859597 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11638 23:26:37.862880 28: SUCCESS (0.000s)[0m
11639 23:26:37.869361 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11640 23:26:37.873031 Test requirement: is_intel_device(fd)
11641 23:26:37.879572 Test requirement not met in<14>[ 23.477450] [IGT] kms_addfb_basic: executing
11642 23:26:37.882671 function igt_require_intel, file ../lib/drmtest.c:880:
11643 23:26:37.892730 Test requirement: is_in<14>[ 23.488899] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11644 23:26:37.896061 tel_device(fd)
11645 23:26:37.902791 <14>[ 23.495937] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11646 23:26:37.906006 No KMS driver or no outputs, pipes: 16, outputs: 0
11647 23:26:37.912555 IGT-Version: 1.28-ga44ebfe (<14>[ 23.510489] [IGT] kms_addfb_basic: exiting, ret=0
11648 23:26:37.915943 aarch64) (Linux: 6.1.83-cip18 aarch64)
11649 23:26:37.922546 Using IGT_SRANDOM=1712186624 for randomisation
11650 23:26:37.929304 Opened d<8>[ 23.523757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11651 23:26:37.929616 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11653 23:26:37.932404 evice: /dev/dri/card0
11654 23:26:37.935993 Starting subtest: bad-pitch-256
11655 23:26:37.939180 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11656 23:26:37.949042 Test requirement not met in function igt_require_intel, file ../lib/drm<14>[ 23.546801] [IGT] kms_addfb_basic: executing
11657 23:26:37.949167 test.c:880:
11658 23:26:37.952358 Test requirement: is_intel_device(fd)
11659 23:26:37.962192 Test requirement not met in <14>[ 23.558608] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11660 23:26:37.971942 function igt_req<14>[ 23.565781] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11661 23:26:37.975222 uire_intel, file ../lib/drmtest.c:880:
11662 23:26:37.978555 Test requirement: is_intel_device(fd)
11663 23:26:37.981892 N<14>[ 23.580192] [IGT] kms_addfb_basic: exiting, ret=0
11664 23:26:37.988380 o KMS driver or no outputs, pipes: 16, outputs: 0
11665 23:26:37.998243 IGT-Version: 1.28-ga44ebfe (a<8>[ 23.592909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11666 23:26:37.998562 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11668 23:26:38.001560 arch64) (Linux: 6.1.83-cip18 aarch64)
11669 23:26:38.005168 Using IGT_SRANDOM=1712186624 for randomisation
11670 23:26:38.008440 Opened device: /dev/dri/card0
11671 23:26:38.011549 Starting subtest: bad-pitch-1024
11672 23:26:38.014954 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11673 23:26:38.021597 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11674 23:26:38.028129 Te<14>[ 23.624010] [IGT] kms_addfb_basic: executing
11675 23:26:38.031332 st requirement: is_intel_device(fd)
11676 23:26:38.041291 Test requirement not met in function igt_require_intel, fil<14>[ 23.637420] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11677 23:26:38.051288 e ../lib/drmtest<14>[ 23.645082] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11678 23:26:38.051414 .c:880:
11679 23:26:38.054436 Test requirement: is_intel_device(fd)
11680 23:26:38.064401 No KMS driver or no outputs, pip<14>[ 23.660268] [IGT] kms_addfb_basic: exiting, ret=0
11681 23:26:38.064525 es: 16, outputs: 0
11682 23:26:38.077607 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aa<8>[ 23.672797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11683 23:26:38.077734 rch64)
11684 23:26:38.078029 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11686 23:26:38.081384 Using IGT_SRANDOM=1712186624 for randomisation
11687 23:26:38.084077 Opened device: /dev/dri/card0
11688 23:26:38.087510 Starting subtest: bad-pitch-999
11689 23:26:38.094294 [1mSubtest bad-pitch-999: SUCCESS (0.00<14>[ 23.693949] [IGT] kms_addfb_basic: executing
11690 23:26:38.097592 0s)[0m
11691 23:26:38.103987 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11692 23:26:38.114077 Test requirement: i<14>[ 23.707064] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11693 23:26:38.120674 s_intel_device(f<14>[ 23.715720] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11694 23:26:38.120798 d)
11695 23:26:38.130749 Test requirement not met in function igt_req<14>[ 23.728827] [IGT] kms_addfb_basic: exiting, ret=0
11696 23:26:38.133973 uire_intel, file ../lib/drmtest.c:880:
11697 23:26:38.137217 Test requirement: is_intel_device(fd)
11698 23:26:38.143957 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11700 23:26:38.147127 N<8>[ 23.740897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11701 23:26:38.150596 o KMS driver or no outputs, pipes: 16, outputs: 0
11702 23:26:38.157267 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11703 23:26:38.160582 Using IGT_SRANDOM=1712186624 for randomisation
11704 23:26:38.163729 Opened device: /dev/dri/card0
11705 23:26:38.167359 Starting subtest: bad-pitch-65536
11706 23:26:38.174109 [1mSubtest bad-pitch-65536: SUCCESS (0<14>[ 23.772240] [IGT] kms_addfb_basic: executing
11707 23:26:38.174231 .000s)[0m
11708 23:26:38.183623 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11709 23:26:38.190382 Test requirement<14>[ 23.786564] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11710 23:26:38.200484 : is_intel_devic<14>[ 23.793514] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11711 23:26:38.200568 e(fd)
11712 23:26:38.210505 Test requirement not met in function igt_require_intel, f<14>[ 23.806861] [IGT] kms_addfb_basic: exiting, ret=0
11713 23:26:38.213617 ile ../lib/drmtest.c:880:
11714 23:26:38.217085 Test requirement: is_intel_device(fd)
11715 23:26:38.223434 No KMS driver <8>[ 23.819904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11716 23:26:38.223695 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11718 23:26:38.227035 or no outputs, pipes: 16, outputs: 0
11719 23:26:38.233417 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11720 23:26:38.236869 Using IGT_SRANDOM=1712186624 for randomisation
11721 23:26:38.240113 Opened device: /dev/dri/card0
11722 23:26:38.246834 Starting subtest: inval<14>[ 23.844129] [IGT] kms_addfb_basic: executing
11723 23:26:38.249918 id-get-prop-any
11724 23:26:38.253505 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11725 23:26:38.263210 Test requirement not met in function ig<14>[ 23.858483] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11726 23:26:38.273213 t_require_intel,<14>[ 23.867015] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11727 23:26:38.276390 file ../lib/drmtest.c:880:
11728 23:26:38.282922 Test requirement: i<14>[ 23.880162] [IGT] kms_addfb_basic: exiting, ret=0
11729 23:26:38.283006 s_intel_device(fd)
11730 23:26:38.295929 Test requirement not met in function igt_require_intel, file<8>[ 23.892158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11731 23:26:38.296189 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11733 23:26:38.299327 ../lib/drmtest.c:880:
11734 23:26:38.302617 Test requirement: is_intel_device(fd)
11735 23:26:38.306167 No KMS driver or no outputs, pipes: 16, outputs: 0
11736 23:26:38.312622 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11737 23:26:38.315918 Using IGT_SRANDOM=1712186624 for randomisation
11738 23:26:38.319170 Opened device: /dev/dri/card0
11739 23:26:38.326030 Starting subtest: invalid-<14>[ 23.924160] [IGT] kms_addfb_basic: executing
11740 23:26:38.329167 get-prop
11741 23:26:38.332582 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11742 23:26:38.342546 Test requirement not met in function igt_require_i<14>[ 23.939378] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11743 23:26:38.352661 ntel, file ../li<14>[ 23.946375] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11744 23:26:38.352747 b/drmtest.c:880:
11745 23:26:38.355764 Test requirement: is_intel_device(fd)
11746 23:26:38.362638 Test re<14>[ 23.959683] [IGT] kms_addfb_basic: exiting, ret=0
11747 23:26:38.369103 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11748 23:26:38.379006 Test requirement: i<8>[ 23.972871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11749 23:26:38.379090 s_intel_device(fd)
11750 23:26:38.379330 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11752 23:26:38.385585 No KMS driver or no outputs, pipes: 16, outputs: 0
11753 23:26:38.392115 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11754 23:26:38.398802 Using IGT_SRANDOM=1712186624 for ran<14>[ 23.996242] [IGT] kms_addfb_basic: executing
11755 23:26:38.398884 domisation
11756 23:26:38.402247 Opened device: /dev/dri/card0
11757 23:26:38.405398 Starting subtest: invalid-set-prop-any
11758 23:26:38.415380 [1mSubtest invalid-set-prop-any: SUCCESS (0.<14>[ 24.011947] [IGT] kms_addfb_basic: starting subtest master-rmfb
11759 23:26:38.415464 000s)[0m
11760 23:26:38.425201 Test <14>[ 24.019316] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11761 23:26:38.431768 requirement not met in function <14>[ 24.029620] [IGT] kms_addfb_basic: exiting, ret=0
11762 23:26:38.435355 igt_require_intel, file ../lib/drmtest.c:880:
11763 23:26:38.444976 Test requirement: is_intel_device<8>[ 24.042131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11764 23:26:38.445250 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11766 23:26:38.448418 (fd)
11767 23:26:38.454855 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11768 23:26:38.458332 Test requirement: is_intel_device(fd)
11769 23:26:38.464685 No KMS driver or no outputs, pipes: 16, outputs<14>[ 24.063558] [IGT] kms_addfb_basic: executing
11770 23:26:38.468446 : 0
11771 23:26:38.471564 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11772 23:26:38.478044 Using IGT_SRANDOM=1712186624 for randomisation
11773 23:26:38.484835 Opened device: /dev/dri<14>[ 24.081342] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11774 23:26:38.487824 /card0
11775 23:26:38.494702 Starting<14>[ 24.089350] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11776 23:26:38.501154 subtest: invali<14>[ 24.098989] [IGT] kms_addfb_basic: exiting, ret=0
11777 23:26:38.504274 d-set-prop
11778 23:26:38.507898 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11779 23:26:38.517920 Test requirement<8>[ 24.111964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11780 23:26:38.518180 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11782 23:26:38.524327 not met in function igt_require_intel, file ../lib/drmtest.c:880:
11783 23:26:38.527526 Test requirement: is_intel_device(fd)
11784 23:26:38.537828 Test requirement not met in function igt_require_intel, file ../lib/d<14>[ 24.135518] [IGT] kms_addfb_basic: executing
11785 23:26:38.537912 rmtest.c:880:
11786 23:26:38.540984 Test requirement: is_intel_device(fd)
11787 23:26:38.547591 No KMS driver or no outputs, pipes: 16, outputs: 0
11788 23:26:38.557721 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-ci<14>[ 24.153281] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11789 23:26:38.560887 p18 aarch64)
11790 23:26:38.564182 Using IGT_SRANDOM=1712186624 for randomisation
11791 23:26:38.574167 Opened device: /de<14>[ 24.167069] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11792 23:26:38.574267 v/dri/card0
11793 23:26:38.580638 Sta<14>[ 24.176109] [IGT] kms_addfb_basic: exiting, ret=98
11794 23:26:38.580735 rting subtest: master-rmfb
11795 23:26:38.587151 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11796 23:26:38.593848 Test <8>[ 24.189026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11797 23:26:38.594107 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11799 23:26:38.600548 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11800 23:26:38.603969 Test requirement: is_intel_device(fd)
11801 23:26:38.610214 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11802 23:26:38.613486 Test requirement: is_intel_device(fd)
11803 23:26:38.623436 No KMS driver or no outputs, pi<14>[ 24.220307] [IGT] kms_addfb_basic: executing
11804 23:26:38.623524 pes: 16, outputs: 0
11805 23:26:38.630324 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11806 23:26:38.633550 Using IGT_SRANDOM=1712186624 for randomisation
11807 23:26:38.636738 Opened device: /dev/dri/card0
11808 23:26:38.643509 Starting<14>[ 24.239443] [IGT] kms_addfb_basic: exiting, ret=77
11809 23:26:38.646641 subtest: addfb25-modifier-no-flag
11810 23:26:38.649850 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11811 23:26:38.659847 <8>[ 24.252957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11812 23:26:38.660107 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11814 23:26:38.666647 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11815 23:26:38.669818 Test requirement: is_intel_device(fd)
11816 23:26:38.679926 Test requirement not met in function igt_require_intel, file ../lib/d<14>[ 24.278316] [IGT] kms_addfb_basic: executing
11817 23:26:38.683060 rmtest.c:880:
11818 23:26:38.686517 Test requirement: is_intel_device(fd)
11819 23:26:38.689652 No KMS driver or no outputs, pipes: 16, outputs: 0
11820 23:26:38.699888 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-ci<14>[ 24.296830] [IGT] kms_addfb_basic: exiting, ret=77
11821 23:26:38.703075 p18 aarch64)
11822 23:26:38.706593 Using IGT_SRANDOM=1712186625 for randomisation
11823 23:26:38.716274 Opened device: /de<8>[ 24.310001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11824 23:26:38.716379 v/dri/card0
11825 23:26:38.716619 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11827 23:26:38.719590 Starting subtest: addfb25-bad-modifier
11828 23:26:38.729561 (kms_addfb_basic:437) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11829 23:26:38.742557 (kms_addfb_basic:437) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('<14>[ 24.341348] [IGT] kms_addfb_basic: executing
11830 23:26:38.752715 d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11831 23:26:38.755969 (kms_addfb_basic:437) CRITICAL: error: 0 != -1
11832 23:26:38.759281 Stack trace:
11833 23:26:38.762579 #0 ../li<14>[ 24.360428] [IGT] kms_addfb_basic: exiting, ret=77
11834 23:26:38.765939 b/igt_core.c:1989 __igt_fail_assert()
11835 23:26:38.769078 #1 [<unknown>+0xd6554358]
11836 23:26:38.772421 #2 [<unknown>+0xd6555fbc]
11837 23:26:38.782276 #3 [<unknown><8>[ 24.376294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11838 23:26:38.782359 +0xd655156c]
11839 23:26:38.782599 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11841 23:26:38.785680 #4 [__libc_init_first+0x80]
11842 23:26:38.789149 #5 [__libc_start_main+0x98]
11843 23:26:38.792253 #6 [<unknown>+0xd65515b0]
11844 23:26:38.795536 Subtest addfb25-bad-modifier failed.
11845 23:26:38.795617 **** DEBUG ****
11846 23:26:38.802288 (kms_addfb_basic<14>[ 24.399922] [IGT] kms_addfb_basic: executing
11847 23:26:38.809008 :437) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11848 23:26:38.822340 (kms_addfb_basic:437) CRITICAL: Test assertion failure function addfb25_tests, fi<14>[ 24.418027] [IGT] kms_addfb_basic: exiting, ret=77
11849 23:26:38.825528 le ../tests/kms_addfb_basic.c:714:
11850 23:26:38.835474 (kms_addfb_basic:437) CRITICAL: Failed asser<8>[ 24.430903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11851 23:26:38.835731 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11853 23:26:38.848897 tion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11854 23:26:38.855504 (kms_addfb_basic:437) CRITICAL: error: 0 != -1
11855 23:26:38.858568 (kms_addfb_basic:437) igt_core-INFO: Stack trace:
11856 23:26:38.865133 (kms_addfb_<14>[ 24.462518] [IGT] kms_addfb_basic: executing
11857 23:26:38.871942 basic:437) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11858 23:26:38.875252 (kms_addfb_basic:437) igt_core-INFO: #1 [<unknown>+0xd6554358]
11859 23:26:38.885292 (kms_addfb_basic:437) igt_core-INFO<14>[ 24.481493] [IGT] kms_addfb_basic: exiting, ret=77
11860 23:26:38.888448 : #2 [<unknown>+0xd6555fbc]
11861 23:26:38.891833 (kms_addfb_basic:437) igt_core-INFO: #3 [<unknown>+0xd655156c]
11862 23:26:38.901565 <8>[ 24.494902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11863 23:26:38.901647
11864 23:26:38.901886 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11866 23:26:38.908197 (kms_addfb_basic:437) igt_core-INFO: #4 [__libc_init_first+0x80]
11867 23:26:38.914719 (kms_addfb_basic:437) igt_core-INFO: #5 [__libc_start_main+0x98]
11868 23:26:38.921196 (kms_addfb_basic:437) igt_core-INFO: <14>[ 24.518599] [IGT] kms_addfb_basic: executing
11869 23:26:38.924747 #6 [<unknown>+0xd65515b0]
11870 23:26:38.924829 **** END ****
11871 23:26:38.931152 [1mSubtest addfb25-bad-modifier: FAIL (0.006s)[0m
11872 23:26:38.941071 Test requirement not met in function igt_require_intel, file ..<14>[ 24.537035] [IGT] kms_addfb_basic: exiting, ret=77
11873 23:26:38.941155 /lib/drmtest.c:880:
11874 23:26:38.944334 Test requirement: is_intel_device(fd)
11875 23:26:38.954317 Test requirement not<8>[ 24.549889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11876 23:26:38.954574 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11878 23:26:38.960997 met in function igt_require_intel, file ../lib/drmtest.c:880:
11879 23:26:38.964059 Test requirement: is_intel_device(fd)
11880 23:26:38.967295 No KMS driver or no outputs, pipes: 16, outputs: 0
11881 23:26:38.974077 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11882 23:26:38.977212 Using IGT_SRANDOM=1712186625 for randomisation
11883 23:26:38.984109 O<14>[ 24.580972] [IGT] kms_addfb_basic: executing
11884 23:26:38.987381 pened device: /dev/dri/card0
11885 23:26:38.993820 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11886 23:26:38.997117 Test requirement: is_intel_device(fd)
11887 23:26:39.003623 [1mSubtest addfb25-x-t<14>[ 24.600400] [IGT] kms_addfb_basic: exiting, ret=77
11888 23:26:39.007009 iled-mismatch-legacy: SKIP (0.000s)[0m
11889 23:26:39.020216 Test requirement not met in function igt_require_intel,<8>[ 24.613880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11890 23:26:39.020512 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11892 23:26:39.023409 file ../lib/drmtest.c:880:
11893 23:26:39.026965 Test requirement: is_intel_device(fd)
11894 23:26:39.030123 No KMS driver or no outputs, pipes: 16, outputs: 0
11895 23:26:39.040145 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip1<14>[ 24.637066] [IGT] kms_addfb_basic: executing
11896 23:26:39.040227 8 aarch64)
11897 23:26:39.043280 Using IGT_SRANDOM=1712186625 for randomisation
11898 23:26:39.046632 Opened device: /dev/dri/card0
11899 23:26:39.060020 Test requirement not met in function igt_require_intel, file ../lib/d<14>[ 24.655423] [IGT] kms_addfb_basic: exiting, ret=77
11900 23:26:39.060104 rmtest.c:880:
11901 23:26:39.063261 Test requirement: is_intel_device(fd)
11902 23:26:39.072777 [1mSubtest addfb25-x-tile<8>[ 24.667866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11903 23:26:39.073056 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11905 23:26:39.076073 d-legacy: SKIP (0.000s)[0m
11906 23:26:39.083006 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11907 23:26:39.086262 Test requirement: is_intel_device(fd)
11908 23:26:39.089359 No KMS d<14>[ 24.688333] [IGT] kms_addfb_basic: executing
11909 23:26:39.095925 river or no outputs, pipes: 16, outputs: 0
11910 23:26:39.099189 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11911 23:26:39.106099 Using IGT_SRANDOM=1712186625 for randomisation
11912 23:26:39.109200 <14>[ 24.706626] [IGT] kms_addfb_basic: exiting, ret=77
11913 23:26:39.112550 Opened device: /dev/dri/card0
11914 23:26:39.122515 Test requirement not met in function igt_require_<8>[ 24.719693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11915 23:26:39.122767 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11917 23:26:39.125913 intel, file ../lib/drmtest.c:880:
11918 23:26:39.129074 Test requirement: is_intel_device(fd)
11919 23:26:39.135830 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11920 23:26:39.142506 Test requirement not met in function<14>[ 24.741084] [IGT] kms_addfb_basic: executing
11921 23:26:39.149225 igt_require_intel, file ../lib/drmtest.c:880:
11922 23:26:39.152503 Test requirement: is_intel_device(fd)
11923 23:26:39.155631 No KMS driver or no outputs, pipes: 16, outputs: 0
11924 23:26:39.162580 IGT-Version: 1.28-ga4<14>[ 24.759399] [IGT] kms_addfb_basic: exiting, ret=77
11925 23:26:39.165776 4ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11926 23:26:39.175759 Using IGT_SRANDOM=1712186625 for <8>[ 24.772286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11927 23:26:39.176024 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11929 23:26:39.179112 randomisation
11930 23:26:39.179200 Opened device: /dev/dri/card0
11931 23:26:39.188909 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11932 23:26:39.195431 Test requirement: is_intel_dev<14>[ 24.792348] [IGT] kms_addfb_basic: executing
11933 23:26:39.195512 ice(fd)
11934 23:26:39.201903 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11935 23:26:39.205178 Test requirement: is_intel_device(fd)
11936 23:26:39.215170 [1mSubtest basic-x-tiled-le<14>[ 24.810662] [IGT] kms_addfb_basic: exiting, ret=77
11937 23:26:39.215254 gacy: SKIP (0.000s)[0m
11938 23:26:39.221912 No KMS driver or no outputs, pipes: 16, outputs: 0
11939 23:26:39.228239 IGT<8>[ 24.823709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11940 23:26:39.228530 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11942 23:26:39.234869 -Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11943 23:26:39.238296 Using IGT_SRANDOM=1712186625 for randomisation
11944 23:26:39.241811 Opened device: /dev/dri/card0
11945 23:26:39.248171 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11946 23:26:39.251702 Test requirement: is_intel_device(fd)
11947 23:26:39.254861 Test <14>[ 24.854405] [IGT] kms_addfb_basic: executing
11948 23:26:39.261578 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11949 23:26:39.268451 Test requirement: is_intel_device(fd)
11950 23:26:39.271387 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11951 23:26:39.278291 <14>[ 24.873828] [IGT] kms_addfb_basic: exiting, ret=77
11952 23:26:39.281212 No KMS driver or no outputs, pipes: 16, outputs: 0
11953 23:26:39.287901 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11954 23:26:39.294682 Using IG<8>[ 24.889951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11955 23:26:39.294938 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11957 23:26:39.297943 T_SRANDOM=1712186625 for randomisation
11958 23:26:39.301249 Opened device: /dev/dri/card0
11959 23:26:39.308050 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11960 23:26:39.314468 Test requirement: is_<14>[ 24.911698] [IGT] kms_addfb_basic: executing
11961 23:26:39.317841 intel_device(fd)
11962 23:26:39.324653 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11963 23:26:39.327640 Test requirement: is_intel_device(fd)
11964 23:26:39.334070 [1mSubtest tile-pi<14>[ 24.930278] [IGT] kms_addfb_basic: exiting, ret=77
11965 23:26:39.337596 tch-mismatch: SKIP (0.000s)[0m
11966 23:26:39.347607 No KMS driver or no outputs, pipes: 16, outputs<8>[ 24.943534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11967 23:26:39.347888 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11969 23:26:39.350816 : 0
11970 23:26:39.353927 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11971 23:26:39.360798 Using IGT_SRANDOM=1712186625 for randomisation
11972 23:26:39.360879 Opened device: /dev/dri/card0
11973 23:26:39.370656 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11974 23:26:39.377479 Test requirement: is_intel_device(fd<14>[ 24.975317] [IGT] kms_addfb_basic: executing
11975 23:26:39.377563 )
11976 23:26:39.384128 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11977 23:26:39.387081 Test requirement: is_intel_device(fd)
11978 23:26:39.397158 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0<14>[ 24.994400] [IGT] kms_addfb_basic: exiting, ret=77
11979 23:26:39.397256 m
11980 23:26:39.403700 No KMS driver or no outputs, pipes: 16, outputs: 0
11981 23:26:39.413527 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<8>[ 25.007704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11982 23:26:39.413787 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11984 23:26:39.417052 ux: 6.1.83-cip18 aarch64)
11985 23:26:39.420177 Using IGT_SRANDOM=1712186625 for randomisation
11986 23:26:39.423519 Opened device: /dev/dri/card0
11987 23:26:39.430007 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11988 23:26:39.433669 Test requirement: is_intel_device(fd)
11989 23:26:39.443252 Test requirement not met in function igt_re<14>[ 25.040194] [IGT] kms_addfb_basic: executing
11990 23:26:39.446621 quire_intel, file ../lib/drmtest.c:880:
11991 23:26:39.450201 Test requirement: is_intel_device(fd)
11992 23:26:39.453398 No KMS driver or no outputs, pipes: 16, outputs: 0
11993 23:26:39.456711 [1mSubtest size-max: SKIP (0.000s)[0m
11994 23:26:39.463275 IGT<14>[ 25.059323] [IGT] kms_addfb_basic: exiting, ret=77
11995 23:26:39.466805 -Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
11996 23:26:39.479894 Using IGT_SRANDOM=1712186625 fo<8>[ 25.072844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11997 23:26:39.480009 r randomisation
11998 23:26:39.480337 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
12000 23:26:39.483128 Opened device: /dev/dri/card0
12001 23:26:39.489579 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12002 23:26:39.493021 Test requirement: is_intel_device(fd)
12003 23:26:39.499476 Test <14>[ 25.095681] [IGT] kms_addfb_basic: executing
12004 23:26:39.506490 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12005 23:26:39.509729 Test requirement: is_intel_device(fd)
12006 23:26:39.516268 No KMS driver or no output<14>[ 25.114238] [IGT] kms_addfb_basic: exiting, ret=77
12007 23:26:39.519525 s, pipes: 16, outputs: 0
12008 23:26:39.523110 [1mSubtest too-wide: SKIP (0.000s)[0m
12009 23:26:39.532824 IGT-Version: <8>[ 25.126130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
12010 23:26:39.533080 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
12012 23:26:39.536106 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12013 23:26:39.539472 Using IGT_SRANDOM=1712186625 for randomisation
12014 23:26:39.542839 Opened device: /dev/dri/card0
12015 23:26:39.549503 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12016 23:26:39.552639 Test requirement: is_intel_device(fd)
12017 23:26:39.562297 Test requirement not met in fun<14>[ 25.158636] [IGT] kms_addfb_basic: executing
12018 23:26:39.565982 ction igt_require_intel, file ../lib/drmtest.c:880:
12019 23:26:39.569226 Test requirement: is_intel_device(fd)
12020 23:26:39.572587 No KMS driver or no outputs, pipes: 16, outputs: 0
12021 23:26:39.582416 [1mSubtest too-high: SKIP (0.00<14>[ 25.178785] [IGT] kms_addfb_basic: exiting, ret=77
12022 23:26:39.582503 0s)[0m
12023 23:26:39.588870 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12024 23:26:39.599016 Using IGT_SRANDOM=1<8>[ 25.192037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
12025 23:26:39.599099 712186625 for randomisation
12026 23:26:39.599337 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
12028 23:26:39.605688 Ope<8>[ 25.202591] <LAVA_SIGNAL_TESTSET STOP>
12029 23:26:39.605772 ned device: /dev/dri/card0
12030 23:26:39.606019 Received signal: <TESTSET> STOP
12031 23:26:39.606086 Closing test_set kms_addfb_basic
12032 23:26:39.615575 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12033 23:26:39.618956 Test requirement: is_intel_device(fd)
12034 23:26:39.625250 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12035 23:26:39.628677 Test requirement: is_intel_device(fd)
12036 23:26:39.631845 No KMS driver or no outputs, pipes: 16, outputs: 0
12037 23:26:39.638647 [1mSubtes<8>[ 25.235802] <LAVA_SIGNAL_TESTSET START kms_atomic>
12038 23:26:39.638926 Received signal: <TESTSET> START kms_atomic
12039 23:26:39.639021 Starting test_set kms_atomic
12040 23:26:39.641822 t bo-too-small: SKIP (0.000s)[0m
12041 23:26:39.648710 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12042 23:26:39.652013 Using IGT_SRANDOM=1712186625 for randomisation
12043 23:26:39.655260 Opened device: /dev/dri/card0
12044 23:26:39.665136 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 25.263302] [IGT] kms_atomic: executing
12045 23:26:39.665219 t.c:880:
12046 23:26:39.671823 Test r<14>[ 25.268813] [IGT] kms_atomic: exiting, ret=77
12047 23:26:39.675205 equirement: is_intel_device(fd)
12048 23:26:39.681682 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12049 23:26:39.688497 Test requir<8>[ 25.283936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
12050 23:26:39.688752 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
12052 23:26:39.691843 ement: is_intel_device(fd)
12053 23:26:39.698416 No KMS driver or no outputs, pipes: 16, outputs: 0
12054 23:26:39.701551 [1mSubtest small-bo: SKIP (0.000s)[0m
12055 23:26:39.704997 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12056 23:26:39.711659 Using IGT_SRANDOM=1712186625 for randomisation
12057 23:26:39.711740 Opened device: /dev/dri/card0
12058 23:26:39.721562 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12059 23:26:39.724759 Test requirement<14>[ 25.323720] [IGT] kms_atomic: executing
12060 23:26:39.731569 : is_intel_devic<14>[ 25.329962] [IGT] kms_atomic: exiting, ret=77
12061 23:26:39.731651 e(fd)
12062 23:26:39.748073 Test requirement not met in function igt_require_intel, file ../lib/drmte<8>[ 25.341437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
12063 23:26:39.748157 st.c:880:
12064 23:26:39.748395 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
12066 23:26:39.751165 Test requirement: is_intel_device(fd)
12067 23:26:39.754576 No KMS driver or no outputs, pipes: 16, outputs: 0
12068 23:26:39.761153 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
12069 23:26:39.767680 IGT-Version: 1.<14>[ 25.364465] [IGT] kms_atomic: executing
12070 23:26:39.771290 28-ga44ebfe (aar<14>[ 25.369880] [IGT] kms_atomic: exiting, ret=77
12071 23:26:39.774436 ch64) (Linux: 6.1.83-cip18 aarch64)
12072 23:26:39.781022 Using IGT_SRANDOM=1712186625 for randomisation
12073 23:26:39.790974 Opened devi<8>[ 25.382581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
12074 23:26:39.791057 ce: /dev/dri/card0
12075 23:26:39.791293 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
12077 23:26:39.797594 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12078 23:26:39.801077 Test requirement: is_intel_device(fd)
12079 23:26:39.810963 Test requirement not met in funct<14>[ 25.406925] [IGT] kms_atomic: executing
12080 23:26:39.814253 ion igt_require_<14>[ 25.412887] [IGT] kms_atomic: exiting, ret=77
12081 23:26:39.817646 intel, file ../lib/drmtest.c:880:
12082 23:26:39.820970 Test requirement: is_intel_device(fd)
12083 23:26:39.830975 No KMS<8>[ 25.425070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
12084 23:26:39.831254 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
12086 23:26:39.834056 driver or no outputs, pipes: 16, outputs: 0
12087 23:26:39.837491 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
12088 23:26:39.843805 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12089 23:26:39.850517 Using I<14>[ 25.448207] [IGT] kms_atomic: executing
12090 23:26:39.857382 GT_SRANDOM=17121<14>[ 25.453096] [IGT] kms_atomic: exiting, ret=77
12091 23:26:39.857467 86625 for randomisation
12092 23:26:39.860635 Opened device: /dev/dri/card0
12093 23:26:39.870630 Test requirement not met in function igt<8>[ 25.465695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
12094 23:26:39.870889 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
12096 23:26:39.873684 _require_intel, file ../lib/drmtest.c:880:
12097 23:26:39.876858 Test requirement: is_intel_device(fd)
12098 23:26:39.887173 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12099 23:26:39.890056 Test requirement: is_intel_device(fd)
12100 23:26:39.893512 No KMS driver or no outputs, pipes: 16, outputs: 0
12101 23:26:39.900268 [1mSubtest ad<14>[ 25.496950] [IGT] kms_atomic: executing
12102 23:26:39.903401 dfb25-yf-tiled-l<14>[ 25.502619] [IGT] kms_atomic: exiting, ret=77
12103 23:26:39.906710 egacy: SKIP (0.000s)[0m
12104 23:26:39.913360 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12105 23:26:39.923550 Using IGT_SRANDOM=<8>[ 25.517082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
12106 23:26:39.923635 1712186625 for randomisation
12107 23:26:39.923899 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
12109 23:26:39.927112 Opened device: /dev/dri/card0
12110 23:26:39.933402 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12111 23:26:39.936501 Test requirement: is_intel_device(fd)
12112 23:26:39.946872 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12113 23:26:39.949952 Test requirement: is<14>[ 25.549917] [IGT] kms_atomic: executing
12114 23:26:39.956805 _intel_device(fd<14>[ 25.555063] [IGT] kms_atomic: exiting, ret=77
12115 23:26:39.956890 )
12116 23:26:39.963222 No KMS driver or no outputs, pipes: 16, outputs: 0
12117 23:26:39.966332 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
12118 23:26:39.976482 IGT-Version:<8>[ 25.570467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
12119 23:26:39.976737 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
12121 23:26:39.979775 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12122 23:26:39.986344 Using IGT_SRANDOM=1712186626 for randomisation
12123 23:26:39.986424 Opened device: /dev/dri/card0
12124 23:26:39.996169 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12125 23:26:39.999820 Test requirement: is_intel_device(fd)
12126 23:26:40.006120 Test requirement not met in fu<14>[ 25.602859] [IGT] kms_atomic: executing
12127 23:26:40.012857 nction igt_requi<14>[ 25.609250] [IGT] kms_atomic: exiting, ret=77
12128 23:26:40.016117 re_intel, file ../lib/drmtest.c:880:
12129 23:26:40.019383 Test requirement: is_intel_device(fd)
12130 23:26:40.026271 No <8>[ 25.620832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
12131 23:26:40.026526 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12133 23:26:40.029442 KMS driver or no outputs, pipes: 16, outputs: 0
12134 23:26:40.036142 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
12135 23:26:40.042711 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12136 23:26:40.045921 Using IGT_SRANDOM=171218662<14>[ 25.645408] [IGT] kms_atomic: executing
12137 23:26:40.052778 6 for randomisat<14>[ 25.651120] [IGT] kms_atomic: exiting, ret=77
12138 23:26:40.052862 ion
12139 23:26:40.055878 Opened device: /dev/dri/card0
12140 23:26:40.069278 No KMS driver or no outputs, pipes: 16, outp<8>[ 25.662935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12141 23:26:40.069417 uts: 0
12142 23:26:40.069655 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12144 23:26:40.072704 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
12145 23:26:40.079080 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12146 23:26:40.082691 Using IGT_SRANDOM=1712186626 for randomisation
12147 23:26:40.085822 Opened device: /dev/dri/card0
12148 23:26:40.092417 No KMS driver or no outputs, pipes: 16, outputs: 0
12149 23:26:40.095705 [1mSubtest <14>[ 25.694747] [IGT] kms_atomic: executing
12150 23:26:40.102493 plane-primary-le<14>[ 25.699989] [IGT] kms_atomic: exiting, ret=77
12151 23:26:40.105866 gacy: SKIP (0.000s)[0m
12152 23:26:40.109106 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12153 23:26:40.122201 Using IGT_SRANDOM=1712186626 for ra<8>[ 25.715378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12154 23:26:40.122284 ndomisation
12155 23:26:40.122520 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12157 23:26:40.125709 Opened device: /dev/dri/card0
12158 23:26:40.128931 No KMS driver or no outputs, pipes: 16, outputs: 0
12159 23:26:40.135273 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
12160 23:26:40.141945 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12161 23:26:40.145534 Using IGT_SRANDOM=1712186626 for randomisation
12162 23:26:40.151902 Opened de<14>[ 25.748419] [IGT] kms_atomic: executing
12163 23:26:40.155308 vice: /dev/dri/c<14>[ 25.754502] [IGT] kms_atomic: exiting, ret=77
12164 23:26:40.158495 ard0
12165 23:26:40.161633 No KMS driver or no outputs, pipes: 16, outputs: 0
12166 23:26:40.171893 [1mSubtest plane-immu<8>[ 25.765570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12167 23:26:40.172152 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12169 23:26:40.175065 table-zpos: SKIP (0.000s)[0m
12170 23:26:40.178698 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12171 23:26:40.185097 Using IGT_SRANDOM=1712186626 for randomisation
12172 23:26:40.188339 Opened device: /dev/dri/card0
12173 23:26:40.191619 No KMS driver or no outputs, pipes: 16, outputs: 0
12174 23:26:40.195306 [1mSubtest test-only: SKIP (0.000s)[0m
12175 23:26:40.202016 IGT-Version: 1.2<14>[ 25.799021] [IGT] kms_atomic: executing
12176 23:26:40.205233 8-ga44ebfe (aarc<14>[ 25.804578] [IGT] kms_atomic: exiting, ret=77
12177 23:26:40.208714 h64) (Linux: 6.1.83-cip18 aarch64)
12178 23:26:40.215036 Using IGT_SRANDOM=1712186626 for randomisation
12179 23:26:40.218651 Opened device: /dev/dri/card0
12180 23:26:40.225104 No KMS driver<8>[ 25.820287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12181 23:26:40.225360 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12183 23:26:40.231937 or no outputs, pipes: 16, outpu<8>[ 25.830654] <LAVA_SIGNAL_TESTSET STOP>
12184 23:26:40.232020 ts: 0
12185 23:26:40.232253 Received signal: <TESTSET> STOP
12186 23:26:40.232363 Closing test_set kms_atomic
12187 23:26:40.238264 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12188 23:26:40.245037 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12189 23:26:40.248365 Using IGT_SRANDOM=1712186626 for randomisation
12190 23:26:40.251625 Opened device: /dev/dri/card0
12191 23:26:40.255035 No KMS driver or no outputs, pipes: 16, outputs: 0
12192 23:26:40.258404 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
12193 23:26:40.264903 IGT-Versi<8>[ 25.862275] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12194 23:26:40.265161 Received signal: <TESTSET> START kms_flip_event_leak
12195 23:26:40.265236 Starting test_set kms_flip_event_leak
12196 23:26:40.271353 on: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12197 23:26:40.274848 Using IGT_SRANDOM=1712186626 for randomisation
12198 23:26:40.278041 Opened device: /dev/dri/card0
12199 23:26:40.281112 No KMS driver or no outputs, pipes: 16, outputs: 0
12200 23:26:40.287862 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
12201 23:26:40.294396 IGT-Ver<14>[ 25.890994] [IGT] kms_flip_event_leak: executing
12202 23:26:40.301059 sion: 1.28-ga44e<14>[ 25.897328] [IGT] kms_flip_event_leak: exiting, ret=77
12203 23:26:40.304551 bfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12204 23:26:40.314491 Using IGT_SRANDOM=1712186626 for ra<8>[ 25.909625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12205 23:26:40.314577 ndomisation
12206 23:26:40.314837 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12208 23:26:40.321265 Opened device: /dev<8>[ 25.918242] <LAVA_SIGNAL_TESTSET STOP>
12209 23:26:40.321350 /dri/card0
12210 23:26:40.321607 Received signal: <TESTSET> STOP
12211 23:26:40.321681 Closing test_set kms_flip_event_leak
12212 23:26:40.324503 No KMS driver or no outputs, pipes: 16, outputs: 0
12213 23:26:40.330881 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12214 23:26:40.337528 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12215 23:26:40.340825 Using IGT_SRANDOM=1712186626 for randomisation
12216 23:26:40.344297 Opened device: /dev/dri/card0
12217 23:26:40.347538 No KMS driver or no outputs, pipes: 16, outputs: 0
12218 23:26:40.354013 [1mSubtest crtc-inva<8>[ 25.951211] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12219 23:26:40.354269 Received signal: <TESTSET> START kms_prop_blob
12220 23:26:40.354345 Starting test_set kms_prop_blob
12221 23:26:40.357637 lid-params-fence: SKIP (0.000s)[0m
12222 23:26:40.364241 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12223 23:26:40.367553 Using IGT_SRANDOM=1712186626 for randomisation
12224 23:26:40.370668 Opened device: /dev/dri/card0
12225 23:26:40.374064 No KMS driver or no outputs, pipes: 16, outputs: 0
12226 23:26:40.384008 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m<14>[ 25.981518] [IGT] kms_prop_blob: executing
12227 23:26:40.384092
12228 23:26:40.390677 IGT-Version: 1<14>[ 25.987991] [IGT] kms_prop_blob: starting subtest basic
12229 23:26:40.400634 .28-ga44ebfe (aa<14>[ 25.994446] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12230 23:26:40.403834 rch64) (Linux: 6<14>[ 26.002226] [IGT] kms_prop_blob: exiting, ret=0
12231 23:26:40.407076 .1.83-cip18 aarch64)
12232 23:26:40.410364 Using IGT_SRANDOM=1712186626 for randomisation
12233 23:26:40.417070 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12235 23:26:40.420238 Opened dev<8>[ 26.015297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12236 23:26:40.420361 ice: /dev/dri/card0
12237 23:26:40.423450 No KMS driver or no outputs, pipes: 16, outputs: 0
12238 23:26:40.430314 [1mSubtest atomic-plane-damage: SKIP (0.000s)[0m
12239 23:26:40.437008 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12240 23:26:40.440230 Using IGT_SRANDOM=1712186626 for randomisation
12241 23:26:40.443395 Opened device: /dev/dri/card0
12242 23:26:40.446609 <14>[ 26.045030] [IGT] kms_prop_blob: executing
12243 23:26:40.453382 No KMS driver or<14>[ 26.050429] [IGT] kms_prop_blob: starting subtest blob-prop-core
12244 23:26:40.463458 no outputs, pip<14>[ 26.057732] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12245 23:26:40.469789 es: 16, outputs:<14>[ 26.066314] [IGT] kms_prop_blob: exiting, ret=0
12246 23:26:40.469902 0
12247 23:26:40.473187 [1mSubtest basic: SKIP (0.000s)[0m
12248 23:26:40.483155 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-ci<8>[ 26.079615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12249 23:26:40.483410 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12251 23:26:40.486469 p18 aarch64)
12252 23:26:40.489932 Using IGT_SRANDOM=1712186626 for randomisation
12253 23:26:40.493227 Opened device: /dev/dri/card0
12254 23:26:40.496470 Starting subtest: basic
12255 23:26:40.500090 [1mSubtest basic: SUCCESS (0.000s)[0m
12256 23:26:40.503098 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12257 23:26:40.512821 Using IGT_SRANDOM=1712186626 for randomisatio<14>[ 26.111397] [IGT] kms_prop_blob: executing
12258 23:26:40.512904 n
12259 23:26:40.519452 Opened device<14>[ 26.116711] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12260 23:26:40.529782 : /dev/dri/card0<14>[ 26.124448] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12261 23:26:40.529864
12262 23:26:40.536266 Starting subte<14>[ 26.133288] [IGT] kms_prop_blob: exiting, ret=0
12263 23:26:40.539293 st: blob-prop-core
12264 23:26:40.542705 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12265 23:26:40.549561 IGT-Versio<8>[ 26.146245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12266 23:26:40.549815 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12268 23:26:40.556252 n: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12269 23:26:40.559483 Using IGT_SRANDOM=1712186627 for randomisation
12270 23:26:40.562661 Opened device: /dev/dri/card0
12271 23:26:40.566115 Starting subtest: blob-prop-validate
12272 23:26:40.569305 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12273 23:26:40.579168 <14>[ 26.177047] [IGT] kms_prop_blob: executing
12274 23:26:40.585592 IGT-Version: 1.2<14>[ 26.182105] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12275 23:26:40.595539 8-ga44ebfe (aarc<14>[ 26.190052] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12276 23:26:40.602087 h64) (Linux: 6.1<14>[ 26.198896] [IGT] kms_prop_blob: exiting, ret=0
12277 23:26:40.602169 .83-cip18 aarch64)
12278 23:26:40.608902 Using IGT_SRANDOM=1712186627 for randomisation
12279 23:26:40.615656 Opened devic<8>[ 26.211838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12280 23:26:40.615912 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12282 23:26:40.618762 e: /dev/dri/card0
12283 23:26:40.622223 Starting subtest: blob-prop-lifetime
12284 23:26:40.625433 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12285 23:26:40.646031 <14>[ 26.244310] [IGT] kms_prop_blob: executing
12286 23:26:40.652774 IGT-Version: 1.2<14>[ 26.249335] [IGT] kms_prop_blob: starting subtest blob-multiple
12287 23:26:40.662957 8-ga44ebfe (aarc<14>[ 26.256957] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12288 23:26:40.669317 h64) (Linux: 6.1<14>[ 26.265226] [IGT] kms_prop_blob: exiting, ret=0
12289 23:26:40.669409 .83-cip18 aarch64)
12290 23:26:40.679267 Using IGT_SRANDOM=1712186627 for randomisati<8>[ 26.276824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12291 23:26:40.679526 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12293 23:26:40.682837 on
12294 23:26:40.682918 Opened device: /dev/dri/card0
12295 23:26:40.686027 Starting subtest: blob-multiple
12296 23:26:40.692708 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12297 23:26:40.699890 <14>[ 26.298169] [IGT] kms_prop_blob: executing
12298 23:26:40.706619 IGT-Version: 1.2<14>[ 26.302950] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12299 23:26:40.716625 8-ga44ebfe (aarc<14>[ 26.311001] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12300 23:26:40.723176 h64) (Linux: 6.1<14>[ 26.320121] [IGT] kms_prop_blob: exiting, ret=0
12301 23:26:40.726715 .83-cip18 aarch64)
12302 23:26:40.736688 Using IGT_SRANDOM=1712186627<8>[ 26.330488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12303 23:26:40.736769 for randomisation
12304 23:26:40.737006 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12306 23:26:40.740146 Opened device: /dev/dri/card0
12307 23:26:40.743337 Starting subtest: invalid-get-prop-any
12308 23:26:40.746548 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12309 23:26:40.753923 <14>[ 26.351947] [IGT] kms_prop_blob: executing
12310 23:26:40.760173 IGT-Version: 1.2<14>[ 26.356738] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12311 23:26:40.770350 8-ga44ebfe (aarc<14>[ 26.364545] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12312 23:26:40.776826 h64) (Linux: 6.1<14>[ 26.373217] [IGT] kms_prop_blob: exiting, ret=0
12313 23:26:40.776909 .83-cip18 aarch64)
12314 23:26:40.783662 Using IGT_SRANDOM=1712186627 for randomisation
12315 23:26:40.790206 Opened devic<8>[ 26.385060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12316 23:26:40.790478 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12318 23:26:40.793381 e: /dev/dri/card0
12319 23:26:40.796869 Starting subtest: invalid-get-prop
12320 23:26:40.799947 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12321 23:26:40.819191 <14>[ 26.417111] [IGT] kms_prop_blob: executing
12322 23:26:40.825826 IGT-Version: 1.2<14>[ 26.422151] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12323 23:26:40.835487 8-ga44ebfe (aarc<14>[ 26.430143] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12324 23:26:40.842114 h64) (Linux: 6.1<14>[ 26.439272] [IGT] kms_prop_blob: exiting, ret=0
12325 23:26:40.845590 .83-cip18 aarch64)
12326 23:26:40.848990 Using IGT_SRANDOM=1712186627 for randomisation
12327 23:26:40.852247 Opened device: /dev/dri/card0
12328 23:26:40.862214 Starting subtest: invalid-set<8>[ 26.455679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12329 23:26:40.862296 -prop-any
12330 23:26:40.862534 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12332 23:26:40.865483 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12333 23:26:40.883548 <14>[ 26.481821] [IGT] kms_prop_blob: executing
12334 23:26:40.890432 IGT-Version: 1.2<14>[ 26.486622] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12335 23:26:40.900098 8-ga44ebfe (aarc<14>[ 26.494345] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12336 23:26:40.906942 h64) (Linux: 6.1<14>[ 26.503119] [IGT] kms_prop_blob: exiting, ret=0
12337 23:26:40.907025 .83-cip18 aarch64)
12338 23:26:40.913632 Using IGT_SRANDOM=1712186627 for randomisation
12339 23:26:40.920166 Opened devic<8>[ 26.515760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12340 23:26:40.920448 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12342 23:26:40.923504 e: /dev/dri/card0
12343 23:26:40.927038 Starting subt<8>[ 26.524969] <LAVA_SIGNAL_TESTSET STOP>
12344 23:26:40.927289 Received signal: <TESTSET> STOP
12345 23:26:40.927360 Closing test_set kms_prop_blob
12346 23:26:40.930160 est: invalid-set-prop
12347 23:26:40.933353 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12348 23:26:40.959259 <8>[ 26.557493] <LAVA_SIGNAL_TESTSET START kms_setmode>
12349 23:26:40.959511 Received signal: <TESTSET> START kms_setmode
12350 23:26:40.959578 Starting test_set kms_setmode
12351 23:26:40.993220 <14>[ 26.591452] [IGT] kms_setmode: executing
12352 23:26:40.999957 IGT-Version: 1.2<14>[ 26.596585] [IGT] kms_setmode: starting subtest basic
12353 23:26:41.006372 8-ga44ebfe (aarc<14>[ 26.603019] [IGT] kms_setmode: finished subtest basic, SKIP
12354 23:26:41.012937 h64) (Linux: 6.1<14>[ 26.610386] [IGT] kms_setmode: exiting, ret=77
12355 23:26:41.016515 .83-cip18 aarch64)
12356 23:26:41.019830 Using IGT_SRANDOM=1712186627 for randomisation
12357 23:26:41.026311 Opened devic<8>[ 26.622359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12358 23:26:41.026566 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12360 23:26:41.029647 e: /dev/dri/card0
12361 23:26:41.029727 Starting subtest: basic
12362 23:26:41.032792 No dynamic tests executed.
12363 23:26:41.035976 [1mSubtest basic: SKIP (0.000s)[0m
12364 23:26:41.045954 <14>[ 26.644081] [IGT] kms_setmode: executing
12365 23:26:41.052664 IGT-Version: 1.2<14>[ 26.648853] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12366 23:26:41.062545 8-ga44ebfe (aarc<14>[ 26.656938] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12367 23:26:41.068960 h64) (Linux: 6.1<14>[ 26.665872] [IGT] kms_setmode: exiting, ret=77
12368 23:26:41.069042 .83-cip18 aarch64)
12369 23:26:41.075654 Using IGT_SRANDOM=1712186627 for randomisation
12370 23:26:41.082001 Opened devic<8>[ 26.677772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12371 23:26:41.082256 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12373 23:26:41.085369 e: /dev/dri/card0
12374 23:26:41.088594 Starting subtest: basic-clone-single-crtc
12375 23:26:41.092406 No dynamic tests executed.
12376 23:26:41.095642 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12377 23:26:41.105075 <14>[ 26.703477] [IGT] kms_setmode: executing
12378 23:26:41.111947 IGT-Version: 1.2<14>[ 26.708212] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12379 23:26:41.121703 8-ga44ebfe (aarc<14>[ 26.716494] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12380 23:26:41.128268 h64) (Linux: 6.1<14>[ 26.725691] [IGT] kms_setmode: exiting, ret=77
12381 23:26:41.131608 .83-cip18 aarch64)
12382 23:26:41.141843 Using IGT_SRANDOM=1712186627 for randomisati<8>[ 26.736865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12383 23:26:41.141925 on
12384 23:26:41.142162 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12386 23:26:41.144799 Opened device: /dev/dri/card0
12387 23:26:41.148438 Starting subtest: invalid-clone-single-crtc
12388 23:26:41.151597 No dynamic tests executed.
12389 23:26:41.161538 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)<14>[ 26.759316] [IGT] kms_setmode: executing
12390 23:26:41.161620 [0m
12391 23:26:41.168228 <14>[ 26.764060] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12392 23:26:41.178140 IGT-Version: 1.2<14>[ 26.771821] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12393 23:26:41.184742 8-ga44ebfe (aarc<14>[ 26.781092] [IGT] kms_setmode: exiting, ret=77
12394 23:26:41.188068 h64) (Linux: 6.1.83-cip18 aarch64)
12395 23:26:41.198134 Using IGT_SRANDOM=1712186627 for randomisati<8>[ 26.792897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12396 23:26:41.198389 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12398 23:26:41.201171 on
12399 23:26:41.201263 Opened device: /dev/dri/card0
12400 23:26:41.208018 Starting subtest: invalid-clone-exclusive-crtc
12401 23:26:41.208124 No dynamic tests executed.
12402 23:26:41.214624 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12403 23:26:41.228017 <14>[ 26.826114] [IGT] kms_setmode: executing
12404 23:26:41.234746 IGT-Version: 1.2<14>[ 26.831118] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12405 23:26:41.244641 8-ga44ebfe (aarc<14>[ 26.838794] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12406 23:26:41.251333 h64) (Linux: 6.1<14>[ 26.847450] [IGT] kms_setmode: exiting, ret=77
12407 23:26:41.251414 .83-cip18 aarch64)
12408 23:26:41.257821 Using IGT_SRANDOM=1712186627 for randomisation
12409 23:26:41.267774 Opened device: /dev/dri/card<8>[ 26.860920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12410 23:26:41.267856 0
12411 23:26:41.268096 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12413 23:26:41.271110 Starting subtest: clone-exclusive-crtc
12414 23:26:41.271190 No dynamic tests executed.
12415 23:26:41.277652 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12416 23:26:41.288114 <14>[ 26.886545] [IGT] kms_setmode: executing
12417 23:26:41.298251 IGT-Version: 1.2<14>[ 26.891288] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12418 23:26:41.308509 8-ga44ebfe (aarc<14>[ 26.900340] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12419 23:26:41.311637 h64) (Linux: 6.1<14>[ 26.910234] [IGT] kms_setmode: exiting, ret=77
12420 23:26:41.314843 .83-cip18 aarch64)
12421 23:26:41.327898 Using IGT_SRANDOM=1712186627 for randomisati<8>[ 26.921683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12422 23:26:41.327982 on
12423 23:26:41.328220 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12425 23:26:41.334861 Opened device: /dev/dri/card<8>[ 26.932419] <LAVA_SIGNAL_TESTSET STOP>
12426 23:26:41.334944 0
12427 23:26:41.335179 Received signal: <TESTSET> STOP
12428 23:26:41.335245 Closing test_set kms_setmode
12429 23:26:41.337861 Starting subtest: invalid-clone-single-crtc-stealing
12430 23:26:41.341300 No dynamic tests executed.
12431 23:26:41.348052 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12432 23:26:41.366909 <8>[ 26.965121] <LAVA_SIGNAL_TESTSET START kms_vblank>
12433 23:26:41.367162 Received signal: <TESTSET> START kms_vblank
12434 23:26:41.367231 Starting test_set kms_vblank
12435 23:26:41.401913 <14>[ 27.000210] [IGT] kms_vblank: executing
12436 23:26:41.408735 IGT-Version: 1.2<14>[ 27.005192] [IGT] kms_vblank: exiting, ret=77
12437 23:26:41.412178 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12438 23:26:41.421820 Using IGT_SRANDOM=1712186627 for randomisati<8>[ 27.018665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12439 23:26:41.421904 on
12440 23:26:41.422142 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12442 23:26:41.425081 Opened device: /dev/dri/card0
12443 23:26:41.428739 No KMS driver or no outputs, pipes: 16, outputs: 0
12444 23:26:41.435120 [1mSubtest invalid: SKIP (0.000s)[0m
12445 23:26:41.441855 <14>[ 27.039812] [IGT] kms_vblank: executing
12446 23:26:41.448265 IGT-Version: 1.2<14>[ 27.044460] [IGT] kms_vblank: exiting, ret=77
12447 23:26:41.451818 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12448 23:26:41.461714 Using IGT_SRANDOM=1712186627<8>[ 27.056163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12449 23:26:41.461822 for randomisation
12450 23:26:41.462089 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12452 23:26:41.464954 Opened device: /dev/dri/card0
12453 23:26:41.468236 No KMS driver or no outputs, pipes: 16, outputs: 0
12454 23:26:41.471534 [1mSubtest crtc-id: SKIP (0.000s)[0m
12455 23:26:41.481951 <14>[ 27.080202] [IGT] kms_vblank: executing
12456 23:26:41.488817 IGT-Version: 1.2<14>[ 27.084865] [IGT] kms_vblank: exiting, ret=77
12457 23:26:41.492026 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12458 23:26:41.501978 Using IGT_SRANDOM=1712186627<8>[ 27.096170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12459 23:26:41.502060 for randomisation
12460 23:26:41.502294 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12462 23:26:41.505252 Opened device: /dev/dri/card0
12463 23:26:41.512061 No KMS driver or no outputs, pipes: 16, outputs: 0
12464 23:26:41.515364 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12465 23:26:41.522144 <14>[ 27.120388] [IGT] kms_vblank: executing
12466 23:26:41.528804 IGT-Version: 1.2<14>[ 27.125057] [IGT] kms_vblank: exiting, ret=77
12467 23:26:41.532139 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12468 23:26:41.542009 Using IGT_SRANDOM=1712186628<8>[ 27.136630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12469 23:26:41.542117 for randomisation
12470 23:26:41.542382 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12472 23:26:41.545282 Opened device: /dev/dri/card0
12473 23:26:41.548502 No KMS driver or no outputs, pipes: 16, outputs: 0
12474 23:26:41.555301 [1mSubtest query-idle: SKIP (0.000s)[0m
12475 23:26:41.562028 <14>[ 27.160320] [IGT] kms_vblank: executing
12476 23:26:41.568767 IGT-Version: 1.2<14>[ 27.164988] [IGT] kms_vblank: exiting, ret=77
12477 23:26:41.572077 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12478 23:26:41.582084 Using IGT_SRANDOM=1712186628<8>[ 27.176589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12479 23:26:41.582198 for randomisation
12480 23:26:41.582437 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12482 23:26:41.585416 Opened device: /dev/dri/card0
12483 23:26:41.591935 No KMS driver or no outputs, pipes: 16, outputs: 0
12484 23:26:41.594932 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12485 23:26:41.602329 <14>[ 27.200756] [IGT] kms_vblank: executing
12486 23:26:41.608903 IGT-Version: 1.2<14>[ 27.205512] [IGT] kms_vblank: exiting, ret=77
12487 23:26:41.612610 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12488 23:26:41.622516 Using IGT_SRANDOM=1712186628<8>[ 27.216891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12489 23:26:41.622598 for randomisation
12490 23:26:41.622833 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12492 23:26:41.625425 Opened device: /dev/dri/card0
12493 23:26:41.632167 No KMS driver or no outputs, pipes: 16, outputs: 0
12494 23:26:41.635423 [1mSubtest query-forked: SKIP (0.000s)[0m
12495 23:26:41.643967 <14>[ 27.242218] [IGT] kms_vblank: executing
12496 23:26:41.650737 IGT-Version: 1.2<14>[ 27.246948] [IGT] kms_vblank: exiting, ret=77
12497 23:26:41.653988 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12498 23:26:41.663661 Using IGT_SR<8>[ 27.258076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12499 23:26:41.663933 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12501 23:26:41.667085 ANDOM=1712186628 for randomisation
12502 23:26:41.667165 Opened device: /dev/dri/card0
12503 23:26:41.673536 No KMS driver or no outputs, pipes: 16, outputs: 0
12504 23:26:41.680301 [1mSubtest query-forked-hang: SKIP (0.00<14>[ 27.279459] [IGT] kms_vblank: executing
12505 23:26:41.680396 0s)[0m
12506 23:26:41.687001 <14>[ 27.284277] [IGT] kms_vblank: exiting, ret=77
12507 23:26:41.693374 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12508 23:26:41.700429 Using IGT_SR<8>[ 27.296144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12509 23:26:41.700682 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12511 23:26:41.703534 ANDOM=1712186628 for randomisation
12512 23:26:41.706919 Opened device: /dev/dri/card0
12513 23:26:41.710307 No KMS driver or no outputs, pipes: 16, outputs: 0
12514 23:26:41.713268 [1mSubtest query-busy: SKIP (0.000s)[0m
12515 23:26:41.721479 <14>[ 27.319767] [IGT] kms_vblank: executing
12516 23:26:41.728216 IGT-Version: 1.2<14>[ 27.324553] [IGT] kms_vblank: exiting, ret=77
12517 23:26:41.731260 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12518 23:26:41.741399 Using IGT_SRANDOM=1712186628<8>[ 27.335948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12519 23:26:41.741507 for randomisation
12520 23:26:41.741773 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12522 23:26:41.744634 Opened device: /dev/dri/card0
12523 23:26:41.751532 No KMS driver or no outputs, pipes: 16, outputs: 0
12524 23:26:41.754717 [1mSubtest query-busy-hang: SKIP (0.000s)[0m
12525 23:26:41.762434 <14>[ 27.360505] [IGT] kms_vblank: executing
12526 23:26:41.768819 IGT-Version: 1.2<14>[ 27.365223] [IGT] kms_vblank: exiting, ret=77
12527 23:26:41.772087 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12528 23:26:41.782315 Using IGT_SRANDOM=1712186628<8>[ 27.376615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12529 23:26:41.782409 for randomisation
12530 23:26:41.782643 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12532 23:26:41.785608 Opened device: /dev/dri/card0
12533 23:26:41.792099 No KMS driver or no outputs, pipes: 16, outputs: 0
12534 23:26:41.795444 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12535 23:26:41.798738 <14>[ 27.398900] [IGT] kms_vblank: executing
12536 23:26:41.805395 IGT-Version: 1.2<14>[ 27.403624] [IGT] kms_vblank: exiting, ret=77
12537 23:26:41.811940 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12538 23:26:41.818550 Using IGT_SR<8>[ 27.414729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12539 23:26:41.818805 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12541 23:26:41.821824 ANDOM=1712186628 for randomisation
12542 23:26:41.825206 Opened device: /dev/dri/card0
12543 23:26:41.828577 No KMS driver or no outputs, pipes: 16, outputs: 0
12544 23:26:41.834903 [1mSubtest query-forked-busy-hang: SKIP (0.000s)[0m
12545 23:26:41.848598 <14>[ 27.446656] [IGT] kms_vblank: executing
12546 23:26:41.855177 IGT-Version: 1.2<14>[ 27.451763] [IGT] kms_vblank: exiting, ret=77
12547 23:26:41.858491 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12548 23:26:41.868402 Using IGT_SRANDOM=1712186628 for randomisati<8>[ 27.464548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12549 23:26:41.868484 on
12550 23:26:41.868722 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12552 23:26:41.871504 Opened device: /dev/dri/card0
12553 23:26:41.878407 No KMS driver or no outputs, pipes: 16, outputs: 0
12554 23:26:41.881469 [1mSubtest wait-idle: SKIP (0.000s)[0m
12555 23:26:41.889946 <14>[ 27.488430] [IGT] kms_vblank: executing
12556 23:26:41.896741 IGT-Version: 1.2<14>[ 27.493155] [IGT] kms_vblank: exiting, ret=77
12557 23:26:41.900160 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12558 23:26:41.909918 Using IGT_SRANDOM=1712186628<8>[ 27.504925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12559 23:26:41.909999 for randomisation
12560 23:26:41.910235 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12562 23:26:41.913226 Opened device: /dev/dri/card0
12563 23:26:41.919750 No KMS driver or no outputs, pipes: 16, outputs: 0
12564 23:26:41.923242 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12565 23:26:41.931859 <14>[ 27.530082] [IGT] kms_vblank: executing
12566 23:26:41.938418 IGT-Version: 1.2<14>[ 27.534793] [IGT] kms_vblank: exiting, ret=77
12567 23:26:41.941563 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12568 23:26:41.951691 Using IGT_SRANDOM=1712186628<8>[ 27.546072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12569 23:26:41.951774 for randomisation
12570 23:26:41.952010 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12572 23:26:41.955102 Opened device: /dev/dri/card0
12573 23:26:41.961537 No KMS driver or no outputs, pipes: 16, outputs: 0
12574 23:26:41.964931 [1mSubtest wait-forked: SKIP (0.000s)[0m
12575 23:26:41.968245 <14>[ 27.568398] [IGT] kms_vblank: executing
12576 23:26:41.975121 IGT-Version: 1.2<14>[ 27.573144] [IGT] kms_vblank: exiting, ret=77
12577 23:26:41.981635 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12578 23:26:41.988417 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12580 23:26:41.991519 Using IGT_SRANDOM=1712186628<8>[ 27.585443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12581 23:26:41.991601 for randomisation
12582 23:26:41.994718 Opened device: /dev/dri/card0
12583 23:26:41.997939 No KMS driver or no outputs, pipes: 16, outputs: 0
12584 23:26:42.004642 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12585 23:26:42.007855 <14>[ 27.606773] [IGT] kms_vblank: executing
12586 23:26:42.014620 IGT-Version: 1.2<14>[ 27.611666] [IGT] kms_vblank: exiting, ret=77
12587 23:26:42.018005 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12588 23:26:42.024912 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12590 23:26:42.027999 Using IGT_SR<8>[ 27.622707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12591 23:26:42.028080 ANDOM=1712186628 for randomisation
12592 23:26:42.031426 Opened device: /dev/dri/card0
12593 23:26:42.037678 No KMS driver or no outputs, pipes: 16, outputs: 0
12594 23:26:42.040994 [1mSubtest wait-busy: SKIP (0.000s)[0m
12595 23:26:42.044522 <14>[ 27.643407] [IGT] kms_vblank: executing
12596 23:26:42.044628
12597 23:26:42.051092 IGT-Version: 1.2<14>[ 27.648313] [IGT] kms_vblank: exiting, ret=77
12598 23:26:42.054217 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12599 23:26:42.064126 Using IGT_SRANDOM=1712186628<8>[ 27.659632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12600 23:26:42.064434 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12602 23:26:42.067436 for randomisation
12603 23:26:42.070749 Opened device: /dev/dri/card0
12604 23:26:42.074283 No KMS driver or no outputs, pipes: 16, outputs: 0
12605 23:26:42.077275 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12606 23:26:42.085712 <14>[ 27.684156] [IGT] kms_vblank: executing
12607 23:26:42.092381 IGT-Version: 1.2<14>[ 27.688799] [IGT] kms_vblank: exiting, ret=77
12608 23:26:42.095695 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12609 23:26:42.105793 Using IGT_SRANDOM=1712186628<8>[ 27.701283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12610 23:26:42.105875 for randomisation
12611 23:26:42.106111 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12613 23:26:42.109208 Opened device: /dev/dri/card0
12614 23:26:42.115492 No KMS driver or no outputs, pipes: 16, outputs: 0
12615 23:26:42.119031 [1mSubtest wait-forked-busy: SKIP (0.000s)[0m
12616 23:26:42.122182 <14>[ 27.722284] [IGT] kms_vblank: executing
12617 23:26:42.128635 IGT-Version: 1.2<14>[ 27.727080] [IGT] kms_vblank: exiting, ret=77
12618 23:26:42.135196 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12619 23:26:42.145260 Using IGT_SRANDOM=1712186628<8>[ 27.738478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12620 23:26:42.145378 for randomisation
12621 23:26:42.145644 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12623 23:26:42.148675 Opened device: /dev/dri/card0
12624 23:26:42.151981 No KMS driver or no outputs, pipes: 16, outputs: 0
12625 23:26:42.158424 [1mSubtest wait-forked-busy-hang: SKIP (0.000s)[0m
12626 23:26:42.161668 <14>[ 27.761209] [IGT] kms_vblank: executing
12627 23:26:42.168062 IGT-Version: 1.2<14>[ 27.765893] [IGT] kms_vblank: exiting, ret=77
12628 23:26:42.171606 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12629 23:26:42.181365 Using IGT_SRANDOM=1712186628<8>[ 27.777476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12630 23:26:42.181620 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12632 23:26:42.185117 for randomisation
12633 23:26:42.188253 Opened device: /dev/dri/card0
12634 23:26:42.191613 No KMS driver or no outputs, pipes: 16, outputs: 0
12635 23:26:42.194778 [1mSubtest ts-continuation-idle: SKIP (0.000s)[0m
12636 23:26:42.201932 <14>[ 27.800356] [IGT] kms_vblank: executing
12637 23:26:42.208731 IGT-Version: 1.2<14>[ 27.805026] [IGT] kms_vblank: exiting, ret=77
12638 23:26:42.211849 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12639 23:26:42.221713 Using IGT_SRANDOM=1712186628<8>[ 27.817404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12640 23:26:42.221970 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12642 23:26:42.225349 for randomisation
12643 23:26:42.228566 Opened device: /dev/dri/card0
12644 23:26:42.231947 No KMS driver or no outputs, pipes: 16, outputs: 0
12645 23:26:42.235109 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12646 23:26:42.241958 <14>[ 27.839677] [IGT] kms_vblank: executing
12647 23:26:42.242041
12648 23:26:42.248126 IGT-Version: 1.2<14>[ 27.844402] [IGT] kms_vblank: exiting, ret=77
12649 23:26:42.251807 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12650 23:26:42.261639 Using IGT_SRANDOM=1712186628<8>[ 27.856864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12651 23:26:42.261894 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12653 23:26:42.265217 for randomisation
12654 23:26:42.265299 Opened device: /dev/dri/card0
12655 23:26:42.271559 No KMS driver or no outputs, pipes: 16, outputs: 0
12656 23:26:42.274783 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12657 23:26:42.283622 <14>[ 27.881802] [IGT] kms_vblank: executing
12658 23:26:42.289980 IGT-Version: 1.2<14>[ 27.886522] [IGT] kms_vblank: exiting, ret=77
12659 23:26:42.293624 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12660 23:26:42.303313 Using IGT_SRANDOM=1712186628<8>[ 27.898004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12661 23:26:42.303569 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12663 23:26:42.306873 for randomisation
12664 23:26:42.310177 Opened device: /dev/dri/card0
12665 23:26:42.313448 No KMS driver or no outputs, pipes: 16, outputs: 0
12666 23:26:42.323087 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[<14>[ 27.921178] [IGT] kms_vblank: executing
12667 23:26:42.323171 0m
12668 23:26:42.330049 IGT-Version: 1.2<14>[ 27.926280] [IGT] kms_vblank: exiting, ret=77
12669 23:26:42.332910 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12670 23:26:42.343003 Using IGT_SRANDOM=1712186628<8>[ 27.937802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12671 23:26:42.343280 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12673 23:26:42.346196 for randomisation
12674 23:26:42.349450 Opened device: /dev/dri/card0
12675 23:26:42.352965 No KMS driver or no outputs, pipes: 16, outputs: 0
12676 23:26:42.359293 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12677 23:26:42.362557 <14>[ 27.960942] [IGT] kms_vblank: executing
12678 23:26:42.369350 IGT-Version: 1.2<14>[ 27.965712] [IGT] kms_vblank: exiting, ret=77
12679 23:26:42.372460 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12680 23:26:42.382357 Using IGT_SRANDOM=1712186628<8>[ 27.978124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12681 23:26:42.382611 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12683 23:26:42.385667 for randomisation
12684 23:26:42.385747 Opened device: /dev/dri/card0
12685 23:26:42.392464 No KMS driver or no outputs, pipes: 16, outputs: 0
12686 23:26:42.395643 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12687 23:26:42.402394 <14>[ 28.000672] [IGT] kms_vblank: executing
12688 23:26:42.408958 IGT-Version: 1.2<14>[ 28.005295] [IGT] kms_vblank: exiting, ret=77
12689 23:26:42.412519 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12690 23:26:42.422412 Using IGT_SRANDOM=1712186628<8>[ 28.017630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12691 23:26:42.422666 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12693 23:26:42.425601 for randomisation
12694 23:26:42.428848 Opened device: /dev/dri/card0
12695 23:26:42.431945 No KMS driver or no outputs, pipes: 16, outputs: 0
12696 23:26:42.438865 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12697 23:26:42.442186 <14>[ 28.040246] [IGT] kms_vblank: executing
12698 23:26:42.448393 IGT-Version: 1.2<14>[ 28.045259] [IGT] kms_vblank: exiting, ret=77
12699 23:26:42.451881 8-ga44ebfe (aarch64) (Linux: 6.1.83-cip18 aarch64)
12700 23:26:42.461568 Using IGT_SRANDOM=1712186628<8>[ 28.056822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12701 23:26:42.461821 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12703 23:26:42.465047 for randomisation
12704 23:26:42.468434 Opened devic<8>[ 28.067861] <LAVA_SIGNAL_TESTSET STOP>
12705 23:26:42.468706 Received signal: <TESTSET> STOP
12706 23:26:42.468836 Closing test_set kms_vblank
12707 23:26:42.478293 e: /dev/dri/card<8>[ 28.073936] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 13248445_1.5.2.3.1>
12708 23:26:42.478375 0
12709 23:26:42.478610 Received signal: <ENDRUN> 0_igt-kms-mediatek 13248445_1.5.2.3.1
12710 23:26:42.478688 Ending use of test pattern.
12711 23:26:42.478777 Ending test lava.0_igt-kms-mediatek (13248445_1.5.2.3.1), duration 6.61
12713 23:26:42.481592 No KMS driver or no outputs, pipes: 16, outputs: 0
12714 23:26:42.488020 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12715 23:26:42.488119 + set +x
12716 23:26:42.491145 <LAVA_TEST_RUNNER EXIT>
12717 23:26:42.491397 ok: lava_test_shell seems to have completed
12718 23:26:42.493015 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12719 23:26:42.493180 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12720 23:26:42.493296 end: 3 lava-test-retry (duration 00:00:07) [common]
12721 23:26:42.493412 start: 4 finalize (timeout 00:07:43) [common]
12722 23:26:42.493532 start: 4.1 power-off (timeout 00:00:30) [common]
12723 23:26:42.493729 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
12724 23:26:42.570562 >> Command sent successfully.
12725 23:26:42.573094 Returned 0 in 0 seconds
12726 23:26:42.673550 end: 4.1 power-off (duration 00:00:00) [common]
12728 23:26:42.673875 start: 4.2 read-feedback (timeout 00:07:43) [common]
12729 23:26:42.674133 Listened to connection for namespace 'common' for up to 1s
12730 23:26:43.675089 Finalising connection for namespace 'common'
12731 23:26:43.675255 Disconnecting from shell: Finalise
12732 23:26:43.675337 / #
12733 23:26:43.775673 end: 4.2 read-feedback (duration 00:00:01) [common]
12734 23:26:43.775834 end: 4 finalize (duration 00:00:01) [common]
12735 23:26:43.775953 Cleaning after the job
12736 23:26:43.776054 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/ramdisk
12737 23:26:43.784894 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/kernel
12738 23:26:43.794501 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/dtb
12739 23:26:43.794706 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248445/tftp-deploy-wwg_t9yx/modules
12740 23:26:43.802165 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248445
12741 23:26:43.934084 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248445
12742 23:26:43.934266 Job finished correctly