Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
1 23:17:49.484622 lava-dispatcher, installed at version: 2024.01
2 23:17:49.484890 start: 0 validate
3 23:17:49.485025 Start time: 2024-04-03 23:17:49.485017+00:00 (UTC)
4 23:17:49.485154 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:17:49.485283 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:17:49.754489 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:17:49.755198 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:18:27.532576 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:18:27.533321 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:18:27.794646 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:18:27.795375 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:18:28.308462 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:18:28.309228 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:18:32.821168 validate duration: 43.34
16 23:18:32.822420 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:18:32.822947 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:18:32.823423 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:18:32.824063 Not decompressing ramdisk as can be used compressed.
20 23:18:32.824532 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:18:32.825001 saving as /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/ramdisk/initrd.cpio.gz
22 23:18:32.825389 total size: 5628169 (5 MB)
23 23:18:33.087280 progress 0 % (0 MB)
24 23:18:33.089177 progress 5 % (0 MB)
25 23:18:33.090761 progress 10 % (0 MB)
26 23:18:33.092169 progress 15 % (0 MB)
27 23:18:33.093775 progress 20 % (1 MB)
28 23:18:33.095187 progress 25 % (1 MB)
29 23:18:33.096889 progress 30 % (1 MB)
30 23:18:33.098431 progress 35 % (1 MB)
31 23:18:33.099810 progress 40 % (2 MB)
32 23:18:33.101428 progress 45 % (2 MB)
33 23:18:33.102842 progress 50 % (2 MB)
34 23:18:33.104492 progress 55 % (2 MB)
35 23:18:33.106057 progress 60 % (3 MB)
36 23:18:33.107453 progress 65 % (3 MB)
37 23:18:33.109136 progress 70 % (3 MB)
38 23:18:33.110544 progress 75 % (4 MB)
39 23:18:33.112190 progress 80 % (4 MB)
40 23:18:33.113633 progress 85 % (4 MB)
41 23:18:33.115222 progress 90 % (4 MB)
42 23:18:33.116849 progress 95 % (5 MB)
43 23:18:33.118271 progress 100 % (5 MB)
44 23:18:33.118487 5 MB downloaded in 0.29 s (18.31 MB/s)
45 23:18:33.118648 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:18:33.118898 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:18:33.119049 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:18:33.119166 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:18:33.119306 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:18:33.119377 saving as /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/kernel/Image
52 23:18:33.119443 total size: 54286848 (51 MB)
53 23:18:33.119506 No compression specified
54 23:18:33.120732 progress 0 % (0 MB)
55 23:18:33.135658 progress 5 % (2 MB)
56 23:18:33.150280 progress 10 % (5 MB)
57 23:18:33.164971 progress 15 % (7 MB)
58 23:18:33.179392 progress 20 % (10 MB)
59 23:18:33.194322 progress 25 % (12 MB)
60 23:18:33.208848 progress 30 % (15 MB)
61 23:18:33.223200 progress 35 % (18 MB)
62 23:18:33.238551 progress 40 % (20 MB)
63 23:18:33.253380 progress 45 % (23 MB)
64 23:18:33.268344 progress 50 % (25 MB)
65 23:18:33.283195 progress 55 % (28 MB)
66 23:18:33.297920 progress 60 % (31 MB)
67 23:18:33.312210 progress 65 % (33 MB)
68 23:18:33.326395 progress 70 % (36 MB)
69 23:18:33.341056 progress 75 % (38 MB)
70 23:18:33.356067 progress 80 % (41 MB)
71 23:18:33.370647 progress 85 % (44 MB)
72 23:18:33.384933 progress 90 % (46 MB)
73 23:18:33.398801 progress 95 % (49 MB)
74 23:18:33.412607 progress 100 % (51 MB)
75 23:18:33.412871 51 MB downloaded in 0.29 s (176.44 MB/s)
76 23:18:33.413035 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:18:33.413277 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:18:33.413379 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:18:33.413469 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:18:33.413613 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:18:33.413683 saving as /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/dtb/mt8192-asurada-spherion-r0.dtb
83 23:18:33.413745 total size: 47230 (0 MB)
84 23:18:33.413806 No compression specified
85 23:18:33.414908 progress 69 % (0 MB)
86 23:18:33.415187 progress 100 % (0 MB)
87 23:18:33.415344 0 MB downloaded in 0.00 s (28.20 MB/s)
88 23:18:33.415468 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:18:33.415688 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:18:33.415774 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:18:33.415856 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:18:33.415977 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:18:33.416046 saving as /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/nfsrootfs/full.rootfs.tar
95 23:18:33.416107 total size: 120894716 (115 MB)
96 23:18:33.416170 Using unxz to decompress xz
97 23:18:33.420498 progress 0 % (0 MB)
98 23:18:33.772280 progress 5 % (5 MB)
99 23:18:34.134988 progress 10 % (11 MB)
100 23:18:34.488835 progress 15 % (17 MB)
101 23:18:34.821170 progress 20 % (23 MB)
102 23:18:35.112415 progress 25 % (28 MB)
103 23:18:35.471342 progress 30 % (34 MB)
104 23:18:35.813191 progress 35 % (40 MB)
105 23:18:35.977376 progress 40 % (46 MB)
106 23:18:36.155034 progress 45 % (51 MB)
107 23:18:36.464603 progress 50 % (57 MB)
108 23:18:36.841533 progress 55 % (63 MB)
109 23:18:37.184843 progress 60 % (69 MB)
110 23:18:37.528143 progress 65 % (74 MB)
111 23:18:37.877413 progress 70 % (80 MB)
112 23:18:38.242038 progress 75 % (86 MB)
113 23:18:38.590675 progress 80 % (92 MB)
114 23:18:38.937167 progress 85 % (98 MB)
115 23:18:39.317068 progress 90 % (103 MB)
116 23:18:39.665086 progress 95 % (109 MB)
117 23:18:40.035905 progress 100 % (115 MB)
118 23:18:40.041540 115 MB downloaded in 6.63 s (17.40 MB/s)
119 23:18:40.041868 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:18:40.042152 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:18:40.042245 start: 1.5 download-retry (timeout 00:09:53) [common]
123 23:18:40.042335 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 23:18:40.042498 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:18:40.042568 saving as /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/modules/modules.tar
126 23:18:40.042629 total size: 8629908 (8 MB)
127 23:18:40.042694 Using unxz to decompress xz
128 23:18:40.303985 progress 0 % (0 MB)
129 23:18:40.323493 progress 5 % (0 MB)
130 23:18:40.349623 progress 10 % (0 MB)
131 23:18:40.375832 progress 15 % (1 MB)
132 23:18:40.399967 progress 20 % (1 MB)
133 23:18:40.425164 progress 25 % (2 MB)
134 23:18:40.451686 progress 30 % (2 MB)
135 23:18:40.477052 progress 35 % (2 MB)
136 23:18:40.503000 progress 40 % (3 MB)
137 23:18:40.527179 progress 45 % (3 MB)
138 23:18:40.553074 progress 50 % (4 MB)
139 23:18:40.579389 progress 55 % (4 MB)
140 23:18:40.608031 progress 60 % (4 MB)
141 23:18:40.633657 progress 65 % (5 MB)
142 23:18:40.659847 progress 70 % (5 MB)
143 23:18:40.686147 progress 75 % (6 MB)
144 23:18:40.712921 progress 80 % (6 MB)
145 23:18:40.740832 progress 85 % (7 MB)
146 23:18:40.771218 progress 90 % (7 MB)
147 23:18:40.802345 progress 95 % (7 MB)
148 23:18:40.830375 progress 100 % (8 MB)
149 23:18:40.835979 8 MB downloaded in 0.79 s (10.37 MB/s)
150 23:18:40.836302 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:18:40.836591 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:18:40.836685 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 23:18:40.836827 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 23:18:44.438486 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13248407/extract-nfsrootfs-dbda60ix
156 23:18:44.438713 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:18:44.438820 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:18:44.439000 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq
159 23:18:44.439133 makedir: /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin
160 23:18:44.439236 makedir: /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/tests
161 23:18:44.439335 makedir: /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/results
162 23:18:44.439439 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-add-keys
163 23:18:44.439590 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-add-sources
164 23:18:44.439730 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-background-process-start
165 23:18:44.439868 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-background-process-stop
166 23:18:44.440005 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-common-functions
167 23:18:44.440138 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-echo-ipv4
168 23:18:44.440276 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-install-packages
169 23:18:44.440409 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-installed-packages
170 23:18:44.440539 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-os-build
171 23:18:44.440669 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-probe-channel
172 23:18:44.440854 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-probe-ip
173 23:18:44.440984 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-target-ip
174 23:18:44.441115 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-target-mac
175 23:18:44.441242 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-target-storage
176 23:18:44.441373 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-test-case
177 23:18:44.441504 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-test-event
178 23:18:44.441632 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-test-feedback
179 23:18:44.441758 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-test-raise
180 23:18:44.441888 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-test-reference
181 23:18:44.442092 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-test-runner
182 23:18:44.442223 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-test-set
183 23:18:44.442350 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-test-shell
184 23:18:44.442479 Updating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-add-keys (debian)
185 23:18:44.442637 Updating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-add-sources (debian)
186 23:18:44.442781 Updating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-install-packages (debian)
187 23:18:44.442920 Updating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-installed-packages (debian)
188 23:18:44.443059 Updating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/bin/lava-os-build (debian)
189 23:18:44.443182 Creating /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/environment
190 23:18:44.443279 LAVA metadata
191 23:18:44.443350 - LAVA_JOB_ID=13248407
192 23:18:44.443417 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:18:44.443597 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:18:44.443670 skipped lava-vland-overlay
195 23:18:44.443748 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:18:44.443829 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:18:44.443891 skipped lava-multinode-overlay
198 23:18:44.443962 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:18:44.444040 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:18:44.444116 Loading test definitions
201 23:18:44.444205 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:18:44.444275 Using /lava-13248407 at stage 0
203 23:18:44.444580 uuid=13248407_1.6.2.3.1 testdef=None
204 23:18:44.444668 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:18:44.444780 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:18:44.445265 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:18:44.445487 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:18:44.446046 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:18:44.446274 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:18:44.446922 runner path: /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/0/tests/0_timesync-off test_uuid 13248407_1.6.2.3.1
213 23:18:44.447084 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:18:44.447306 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:18:44.447377 Using /lava-13248407 at stage 0
217 23:18:44.447474 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:18:44.447560 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/0/tests/1_kselftest-alsa'
219 23:18:46.907398 Running '/usr/bin/git checkout kernelci.org
220 23:18:47.057510 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 23:18:47.058295 uuid=13248407_1.6.2.3.5 testdef=None
222 23:18:47.058459 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 23:18:47.058707 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 23:18:47.059476 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:18:47.059708 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 23:18:47.060699 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:18:47.060983 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 23:18:47.061931 runner path: /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/0/tests/1_kselftest-alsa test_uuid 13248407_1.6.2.3.5
232 23:18:47.062025 BOARD='mt8192-asurada-spherion-r0'
233 23:18:47.062090 BRANCH='cip'
234 23:18:47.062150 SKIPFILE='/dev/null'
235 23:18:47.062207 SKIP_INSTALL='True'
236 23:18:47.062263 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:18:47.062323 TST_CASENAME=''
238 23:18:47.062378 TST_CMDFILES='alsa'
239 23:18:47.062519 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:18:47.062727 Creating lava-test-runner.conf files
242 23:18:47.062791 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248407/lava-overlay-gbrnvkfq/lava-13248407/0 for stage 0
243 23:18:47.062889 - 0_timesync-off
244 23:18:47.062956 - 1_kselftest-alsa
245 23:18:47.063054 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 23:18:47.063143 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 23:18:54.546432 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 23:18:54.546589 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 23:18:54.546679 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:18:54.546805 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 23:18:54.546894 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 23:18:54.718031 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:18:54.718436 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 23:18:54.718555 extracting modules file /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248407/extract-nfsrootfs-dbda60ix
255 23:18:54.939511 extracting modules file /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248407/extract-overlay-ramdisk-1cmaq21y/ramdisk
256 23:18:55.164868 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:18:55.165044 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 23:18:55.165134 [common] Applying overlay to NFS
259 23:18:55.165201 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248407/compress-overlay-tent46b8/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248407/extract-nfsrootfs-dbda60ix
260 23:18:56.083864 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:18:56.084038 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 23:18:56.084131 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:18:56.084222 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 23:18:56.084305 Building ramdisk /var/lib/lava/dispatcher/tmp/13248407/extract-overlay-ramdisk-1cmaq21y/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248407/extract-overlay-ramdisk-1cmaq21y/ramdisk
265 23:18:56.450890 >> 130593 blocks
266 23:18:58.484317 rename /var/lib/lava/dispatcher/tmp/13248407/extract-overlay-ramdisk-1cmaq21y/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/ramdisk/ramdisk.cpio.gz
267 23:18:58.484802 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:18:58.484927 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 23:18:58.485034 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 23:18:58.485140 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/kernel/Image'
271 23:19:12.038748 Returned 0 in 13 seconds
272 23:19:12.139374 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/kernel/image.itb
273 23:19:12.526689 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:19:12.527103 output: Created: Thu Apr 4 00:19:12 2024
275 23:19:12.527212 output: Image 0 (kernel-1)
276 23:19:12.527314 output: Description:
277 23:19:12.527407 output: Created: Thu Apr 4 00:19:12 2024
278 23:19:12.527509 output: Type: Kernel Image
279 23:19:12.527600 output: Compression: lzma compressed
280 23:19:12.527690 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
281 23:19:12.527773 output: Architecture: AArch64
282 23:19:12.527834 output: OS: Linux
283 23:19:12.527893 output: Load Address: 0x00000000
284 23:19:12.527954 output: Entry Point: 0x00000000
285 23:19:12.528051 output: Hash algo: crc32
286 23:19:12.528138 output: Hash value: d7c9dcc1
287 23:19:12.528236 output: Image 1 (fdt-1)
288 23:19:12.528323 output: Description: mt8192-asurada-spherion-r0
289 23:19:12.528408 output: Created: Thu Apr 4 00:19:12 2024
290 23:19:12.528502 output: Type: Flat Device Tree
291 23:19:12.528586 output: Compression: uncompressed
292 23:19:12.528671 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 23:19:12.528801 output: Architecture: AArch64
294 23:19:12.528885 output: Hash algo: crc32
295 23:19:12.528976 output: Hash value: 4bf0d1ac
296 23:19:12.529061 output: Image 2 (ramdisk-1)
297 23:19:12.529175 output: Description: unavailable
298 23:19:12.529269 output: Created: Thu Apr 4 00:19:12 2024
299 23:19:12.529352 output: Type: RAMDisk Image
300 23:19:12.529461 output: Compression: Unknown Compression
301 23:19:12.529562 output: Data Size: 18771651 Bytes = 18331.69 KiB = 17.90 MiB
302 23:19:12.529645 output: Architecture: AArch64
303 23:19:12.529770 output: OS: Linux
304 23:19:12.529853 output: Load Address: unavailable
305 23:19:12.529943 output: Entry Point: unavailable
306 23:19:12.530029 output: Hash algo: crc32
307 23:19:12.530111 output: Hash value: 2b5c7403
308 23:19:12.530202 output: Default Configuration: 'conf-1'
309 23:19:12.530291 output: Configuration 0 (conf-1)
310 23:19:12.530374 output: Description: mt8192-asurada-spherion-r0
311 23:19:12.530467 output: Kernel: kernel-1
312 23:19:12.530550 output: Init Ramdisk: ramdisk-1
313 23:19:12.530632 output: FDT: fdt-1
314 23:19:12.530724 output: Loadables: kernel-1
315 23:19:12.530807 output:
316 23:19:12.531062 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 23:19:12.531203 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 23:19:12.531338 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 23:19:12.531472 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 23:19:12.531587 No LXC device requested
321 23:19:12.531712 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:19:12.531835 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 23:19:12.531957 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:19:12.532059 Checking files for TFTP limit of 4294967296 bytes.
325 23:19:12.532787 end: 1 tftp-deploy (duration 00:00:40) [common]
326 23:19:12.532934 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:19:12.533064 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:19:12.533263 substitutions:
329 23:19:12.533363 - {DTB}: 13248407/tftp-deploy-a33avefh/dtb/mt8192-asurada-spherion-r0.dtb
330 23:19:12.533467 - {INITRD}: 13248407/tftp-deploy-a33avefh/ramdisk/ramdisk.cpio.gz
331 23:19:12.533556 - {KERNEL}: 13248407/tftp-deploy-a33avefh/kernel/Image
332 23:19:12.533655 - {LAVA_MAC}: None
333 23:19:12.533743 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13248407/extract-nfsrootfs-dbda60ix
334 23:19:12.533829 - {NFS_SERVER_IP}: 192.168.201.1
335 23:19:12.533927 - {PRESEED_CONFIG}: None
336 23:19:12.534017 - {PRESEED_LOCAL}: None
337 23:19:12.534106 - {RAMDISK}: 13248407/tftp-deploy-a33avefh/ramdisk/ramdisk.cpio.gz
338 23:19:12.534199 - {ROOT_PART}: None
339 23:19:12.534283 - {ROOT}: None
340 23:19:12.534376 - {SERVER_IP}: 192.168.201.1
341 23:19:12.534461 - {TEE}: None
342 23:19:12.534545 Parsed boot commands:
343 23:19:12.534636 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:19:12.534880 Parsed boot commands: tftpboot 192.168.201.1 13248407/tftp-deploy-a33avefh/kernel/image.itb 13248407/tftp-deploy-a33avefh/kernel/cmdline
345 23:19:12.535001 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:19:12.535128 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:19:12.535256 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:19:12.535384 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:19:12.535487 Not connected, no need to disconnect.
350 23:19:12.535601 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:19:12.535715 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:19:12.535818 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 23:19:12.540263 Setting prompt string to ['lava-test: # ']
354 23:19:12.540760 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:19:12.540884 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:19:12.540994 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:19:12.541109 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:19:12.541366 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 23:19:17.675406 >> Command sent successfully.
360 23:19:17.677892 Returned 0 in 5 seconds
361 23:19:17.778259 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:19:17.778584 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:19:17.778686 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:19:17.778782 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:19:17.778850 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:19:17.778922 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:19:17.779195 [Enter `^Ec?' for help]
369 23:19:17.961300
370 23:19:17.961439
371 23:19:17.961518 F0: 102B 0000
372 23:19:17.961629
373 23:19:17.961770 F3: 1001 0000 [0200]
374 23:19:17.961904
375 23:19:17.964718 F3: 1001 0000
376 23:19:17.964834
377 23:19:17.964929 F7: 102D 0000
378 23:19:17.965016
379 23:19:17.968470 F1: 0000 0000
380 23:19:17.968546
381 23:19:17.968611 V0: 0000 0000 [0001]
382 23:19:17.968727
383 23:19:17.968839 00: 0007 8000
384 23:19:17.968930
385 23:19:17.972437 01: 0000 0000
386 23:19:17.972540
387 23:19:17.972631 BP: 0C00 0209 [0000]
388 23:19:17.972760
389 23:19:17.976814 G0: 1182 0000
390 23:19:17.976917
391 23:19:17.977010 EC: 0000 0021 [4000]
392 23:19:17.977098
393 23:19:17.979784 S7: 0000 0000 [0000]
394 23:19:17.979886
395 23:19:17.979980 CC: 0000 0000 [0001]
396 23:19:17.980068
397 23:19:17.982830 T0: 0000 0040 [010F]
398 23:19:17.982929
399 23:19:17.983021 Jump to BL
400 23:19:17.983109
401 23:19:18.008830
402 23:19:18.008920
403 23:19:18.008988
404 23:19:18.015315 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:19:18.018393 ARM64: Exception handlers installed.
406 23:19:18.022836 ARM64: Testing exception
407 23:19:18.025438 ARM64: Done test exception
408 23:19:18.031646 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:19:18.042472 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:19:18.048826 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:19:18.059002 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:19:18.065765 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:19:18.075673 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:19:18.086798 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:19:18.093219 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:19:18.111076 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:19:18.114756 WDT: Last reset was cold boot
418 23:19:18.117610 SPI1(PAD0) initialized at 2873684 Hz
419 23:19:18.121742 SPI5(PAD0) initialized at 992727 Hz
420 23:19:18.124336 VBOOT: Loading verstage.
421 23:19:18.130830 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:19:18.134813 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:19:18.138181 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:19:18.141057 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:19:18.148235 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:19:18.154940 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:19:18.165999 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
428 23:19:18.166080
429 23:19:18.166183
430 23:19:18.176433 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:19:18.179449 ARM64: Exception handlers installed.
432 23:19:18.182623 ARM64: Testing exception
433 23:19:18.182728 ARM64: Done test exception
434 23:19:18.189341 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:19:18.192468 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:19:18.207590 Probing TPM: . done!
437 23:19:18.207704 TPM ready after 0 ms
438 23:19:18.213602 Connected to device vid:did:rid of 1ae0:0028:00
439 23:19:18.220382 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 23:19:18.223948 Initialized TPM device CR50 revision 0
441 23:19:18.275195 tlcl_send_startup: Startup return code is 0
442 23:19:18.275314 TPM: setup succeeded
443 23:19:18.286398 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:19:18.295477 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:19:18.305473 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:19:18.313895 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:19:18.317539 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:19:18.320812 in-header: 03 07 00 00 08 00 00 00
449 23:19:18.324057 in-data: aa e4 47 04 13 02 00 00
450 23:19:18.327382 Chrome EC: UHEPI supported
451 23:19:18.333815 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:19:18.337461 in-header: 03 9d 00 00 08 00 00 00
453 23:19:18.340672 in-data: 10 20 20 08 00 00 00 00
454 23:19:18.340795 Phase 1
455 23:19:18.344062 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:19:18.351163 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:19:18.357055 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:19:18.361079 Recovery requested (1009000e)
459 23:19:18.368001 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:19:18.373161 tlcl_extend: response is 0
461 23:19:18.380980 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:19:18.386234 tlcl_extend: response is 0
463 23:19:18.393166 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:19:18.413802 read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps
465 23:19:18.420320 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:19:18.420424
467 23:19:18.420519
468 23:19:18.429775 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:19:18.432991 ARM64: Exception handlers installed.
470 23:19:18.436884 ARM64: Testing exception
471 23:19:18.436961 ARM64: Done test exception
472 23:19:18.458878 pmic_efuse_setting: Set efuses in 11 msecs
473 23:19:18.462841 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:19:18.468567 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:19:18.472474 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:19:18.478995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:19:18.483262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:19:18.486627 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:19:18.493503 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:19:18.497169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:19:18.500607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:19:18.506836 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:19:18.510232 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:19:18.516818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:19:18.521038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:19:18.523506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:19:18.531081 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:19:18.537258 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:19:18.544308 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:19:18.547001 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:19:18.554448 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:19:18.558584 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:19:18.564966 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:19:18.571491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:19:18.575219 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:19:18.581593 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:19:18.588742 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:19:18.591642 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:19:18.597983 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:19:18.605350 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:19:18.608361 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:19:18.612160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:19:18.618191 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:19:18.621965 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:19:18.628406 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:19:18.631908 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:19:18.638219 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:19:18.641914 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:19:18.648188 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:19:18.651950 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:19:18.658308 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:19:18.661825 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:19:18.665989 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:19:18.672101 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:19:18.675086 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:19:18.678204 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:19:18.685048 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:19:18.688628 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:19:18.691861 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:19:18.698713 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:19:18.702020 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:19:18.705419 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:19:18.708447 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:19:18.715509 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:19:18.722256 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:19:18.732192 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:19:18.735098 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:19:18.741935 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:19:18.751988 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:19:18.755819 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:19:18.761469 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:19:18.765418 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:19:18.771629 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 23:19:18.778188 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:19:18.781714 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 23:19:18.785189 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:19:18.796416 [RTC]rtc_get_frequency_meter,154: input=15, output=764
538 23:19:18.805777 [RTC]rtc_get_frequency_meter,154: input=23, output=949
539 23:19:18.815382 [RTC]rtc_get_frequency_meter,154: input=19, output=856
540 23:19:18.825447 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 23:19:18.834423 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 23:19:18.844022 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 23:19:18.853104 [RTC]rtc_get_frequency_meter,154: input=17, output=810
544 23:19:18.856741 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 23:19:18.864596 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 23:19:18.867487 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:19:18.871261 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 23:19:18.877078 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:19:18.880112 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 23:19:18.883814 ADC[4]: Raw value=670432 ID=5
551 23:19:18.883915 ADC[3]: Raw value=212549 ID=1
552 23:19:18.886818 RAM Code: 0x51
553 23:19:18.890398 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:19:18.897567 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:19:18.903930 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 23:19:18.910364 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 23:19:18.913538 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:19:18.916855 in-header: 03 07 00 00 08 00 00 00
559 23:19:18.920395 in-data: aa e4 47 04 13 02 00 00
560 23:19:18.923358 Chrome EC: UHEPI supported
561 23:19:18.930280 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:19:18.933348 in-header: 03 d5 00 00 08 00 00 00
563 23:19:18.937274 in-data: 98 20 60 08 00 00 00 00
564 23:19:18.940241 MRC: failed to locate region type 0.
565 23:19:18.946789 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:19:18.946898 DRAM-K: Running full calibration
567 23:19:18.953495 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 23:19:18.956629 header.status = 0x0
569 23:19:18.960372 header.version = 0x6 (expected: 0x6)
570 23:19:18.963204 header.size = 0xd00 (expected: 0xd00)
571 23:19:18.963311 header.flags = 0x0
572 23:19:18.970140 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:19:18.988642 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
574 23:19:18.995307 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:19:18.998333 dram_init: ddr_geometry: 0
576 23:19:18.998417 [EMI] MDL number = 0
577 23:19:19.001457 [EMI] Get MDL freq = 0
578 23:19:19.004678 dram_init: ddr_type: 0
579 23:19:19.004803 is_discrete_lpddr4: 1
580 23:19:19.008680 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:19:19.008777
582 23:19:19.008844
583 23:19:19.012281 [Bian_co] ETT version 0.0.0.1
584 23:19:19.015713 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 23:19:19.015797
586 23:19:19.022138 dramc_set_vcore_voltage set vcore to 650000
587 23:19:19.022222 Read voltage for 800, 4
588 23:19:19.025587 Vio18 = 0
589 23:19:19.025670 Vcore = 650000
590 23:19:19.025736 Vdram = 0
591 23:19:19.029172 Vddq = 0
592 23:19:19.029256 Vmddr = 0
593 23:19:19.032285 dram_init: config_dvfs: 1
594 23:19:19.035539 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:19:19.042560 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:19:19.045567 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 23:19:19.048897 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 23:19:19.052730 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 23:19:19.055694 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 23:19:19.059013 MEM_TYPE=3, freq_sel=18
601 23:19:19.062077 sv_algorithm_assistance_LP4_1600
602 23:19:19.066008 ============ PULL DRAM RESETB DOWN ============
603 23:19:19.068872 ========== PULL DRAM RESETB DOWN end =========
604 23:19:19.075349 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:19:19.079346 ===================================
606 23:19:19.079430 LPDDR4 DRAM CONFIGURATION
607 23:19:19.081932 ===================================
608 23:19:19.085295 EX_ROW_EN[0] = 0x0
609 23:19:19.085379 EX_ROW_EN[1] = 0x0
610 23:19:19.088398 LP4Y_EN = 0x0
611 23:19:19.091684 WORK_FSP = 0x0
612 23:19:19.091768 WL = 0x2
613 23:19:19.095351 RL = 0x2
614 23:19:19.095434 BL = 0x2
615 23:19:19.098456 RPST = 0x0
616 23:19:19.098539 RD_PRE = 0x0
617 23:19:19.101909 WR_PRE = 0x1
618 23:19:19.101992 WR_PST = 0x0
619 23:19:19.105379 DBI_WR = 0x0
620 23:19:19.105462 DBI_RD = 0x0
621 23:19:19.109490 OTF = 0x1
622 23:19:19.111837 ===================================
623 23:19:19.115460 ===================================
624 23:19:19.115544 ANA top config
625 23:19:19.118915 ===================================
626 23:19:19.121915 DLL_ASYNC_EN = 0
627 23:19:19.125670 ALL_SLAVE_EN = 1
628 23:19:19.125755 NEW_RANK_MODE = 1
629 23:19:19.128398 DLL_IDLE_MODE = 1
630 23:19:19.131832 LP45_APHY_COMB_EN = 1
631 23:19:19.135462 TX_ODT_DIS = 1
632 23:19:19.138284 NEW_8X_MODE = 1
633 23:19:19.142186 ===================================
634 23:19:19.145314 ===================================
635 23:19:19.145398 data_rate = 1600
636 23:19:19.148909 CKR = 1
637 23:19:19.152210 DQ_P2S_RATIO = 8
638 23:19:19.155021 ===================================
639 23:19:19.158248 CA_P2S_RATIO = 8
640 23:19:19.162585 DQ_CA_OPEN = 0
641 23:19:19.165377 DQ_SEMI_OPEN = 0
642 23:19:19.165460 CA_SEMI_OPEN = 0
643 23:19:19.168235 CA_FULL_RATE = 0
644 23:19:19.171602 DQ_CKDIV4_EN = 1
645 23:19:19.175089 CA_CKDIV4_EN = 1
646 23:19:19.178363 CA_PREDIV_EN = 0
647 23:19:19.182140 PH8_DLY = 0
648 23:19:19.182360 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:19:19.184832 DQ_AAMCK_DIV = 4
650 23:19:19.188305 CA_AAMCK_DIV = 4
651 23:19:19.191723 CA_ADMCK_DIV = 4
652 23:19:19.195179 DQ_TRACK_CA_EN = 0
653 23:19:19.198846 CA_PICK = 800
654 23:19:19.202042 CA_MCKIO = 800
655 23:19:19.202126 MCKIO_SEMI = 0
656 23:19:19.204569 PLL_FREQ = 3068
657 23:19:19.208007 DQ_UI_PI_RATIO = 32
658 23:19:19.212190 CA_UI_PI_RATIO = 0
659 23:19:19.215056 ===================================
660 23:19:19.217862 ===================================
661 23:19:19.221401 memory_type:LPDDR4
662 23:19:19.221484 GP_NUM : 10
663 23:19:19.224585 SRAM_EN : 1
664 23:19:19.224696 MD32_EN : 0
665 23:19:19.228573 ===================================
666 23:19:19.232101 [ANA_INIT] >>>>>>>>>>>>>>
667 23:19:19.235175 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:19:19.238171 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:19:19.241664 ===================================
670 23:19:19.244590 data_rate = 1600,PCW = 0X7600
671 23:19:19.248507 ===================================
672 23:19:19.251234 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:19:19.258062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:19:19.261617 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:19:19.267952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:19:19.271913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:19:19.274737 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:19:19.274839 [ANA_INIT] flow start
679 23:19:19.278002 [ANA_INIT] PLL >>>>>>>>
680 23:19:19.281967 [ANA_INIT] PLL <<<<<<<<
681 23:19:19.282072 [ANA_INIT] MIDPI >>>>>>>>
682 23:19:19.285629 [ANA_INIT] MIDPI <<<<<<<<
683 23:19:19.288658 [ANA_INIT] DLL >>>>>>>>
684 23:19:19.288782 [ANA_INIT] flow end
685 23:19:19.294702 ============ LP4 DIFF to SE enter ============
686 23:19:19.298433 ============ LP4 DIFF to SE exit ============
687 23:19:19.298517 [ANA_INIT] <<<<<<<<<<<<<
688 23:19:19.301775 [Flow] Enable top DCM control >>>>>
689 23:19:19.305438 [Flow] Enable top DCM control <<<<<
690 23:19:19.308617 Enable DLL master slave shuffle
691 23:19:19.314787 ==============================================================
692 23:19:19.314870 Gating Mode config
693 23:19:19.321295 ==============================================================
694 23:19:19.324865 Config description:
695 23:19:19.334464 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:19:19.341605 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:19:19.344489 SELPH_MODE 0: By rank 1: By Phase
698 23:19:19.352225 ==============================================================
699 23:19:19.355112 GAT_TRACK_EN = 1
700 23:19:19.358606 RX_GATING_MODE = 2
701 23:19:19.358735 RX_GATING_TRACK_MODE = 2
702 23:19:19.361559 SELPH_MODE = 1
703 23:19:19.364673 PICG_EARLY_EN = 1
704 23:19:19.368127 VALID_LAT_VALUE = 1
705 23:19:19.374634 ==============================================================
706 23:19:19.378271 Enter into Gating configuration >>>>
707 23:19:19.381309 Exit from Gating configuration <<<<
708 23:19:19.384655 Enter into DVFS_PRE_config >>>>>
709 23:19:19.394950 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:19:19.398748 Exit from DVFS_PRE_config <<<<<
711 23:19:19.401409 Enter into PICG configuration >>>>
712 23:19:19.405295 Exit from PICG configuration <<<<
713 23:19:19.408694 [RX_INPUT] configuration >>>>>
714 23:19:19.411367 [RX_INPUT] configuration <<<<<
715 23:19:19.414686 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:19:19.422070 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:19:19.428224 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:19:19.432037 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:19:19.438299 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:19:19.445105 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:19:19.448347 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:19:19.451437 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:19:19.458254 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:19:19.462356 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:19:19.464725 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:19:19.471663 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:19:19.474961 ===================================
728 23:19:19.475044 LPDDR4 DRAM CONFIGURATION
729 23:19:19.478512 ===================================
730 23:19:19.481225 EX_ROW_EN[0] = 0x0
731 23:19:19.481307 EX_ROW_EN[1] = 0x0
732 23:19:19.484894 LP4Y_EN = 0x0
733 23:19:19.484977 WORK_FSP = 0x0
734 23:19:19.488367 WL = 0x2
735 23:19:19.492116 RL = 0x2
736 23:19:19.492198 BL = 0x2
737 23:19:19.494861 RPST = 0x0
738 23:19:19.494943 RD_PRE = 0x0
739 23:19:19.498027 WR_PRE = 0x1
740 23:19:19.498109 WR_PST = 0x0
741 23:19:19.501593 DBI_WR = 0x0
742 23:19:19.501676 DBI_RD = 0x0
743 23:19:19.504915 OTF = 0x1
744 23:19:19.508494 ===================================
745 23:19:19.511740 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:19:19.515200 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:19:19.517835 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:19:19.521636 ===================================
749 23:19:19.525323 LPDDR4 DRAM CONFIGURATION
750 23:19:19.528960 ===================================
751 23:19:19.531774 EX_ROW_EN[0] = 0x10
752 23:19:19.531856 EX_ROW_EN[1] = 0x0
753 23:19:19.534563 LP4Y_EN = 0x0
754 23:19:19.534650 WORK_FSP = 0x0
755 23:19:19.538024 WL = 0x2
756 23:19:19.538107 RL = 0x2
757 23:19:19.541353 BL = 0x2
758 23:19:19.541435 RPST = 0x0
759 23:19:19.544623 RD_PRE = 0x0
760 23:19:19.544709 WR_PRE = 0x1
761 23:19:19.548315 WR_PST = 0x0
762 23:19:19.551336 DBI_WR = 0x0
763 23:19:19.551419 DBI_RD = 0x0
764 23:19:19.554782 OTF = 0x1
765 23:19:19.557813 ===================================
766 23:19:19.561224 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:19:19.566496 nWR fixed to 40
768 23:19:19.569889 [ModeRegInit_LP4] CH0 RK0
769 23:19:19.569971 [ModeRegInit_LP4] CH0 RK1
770 23:19:19.572972 [ModeRegInit_LP4] CH1 RK0
771 23:19:19.576172 [ModeRegInit_LP4] CH1 RK1
772 23:19:19.576254 match AC timing 12
773 23:19:19.583141 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 23:19:19.586651 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:19:19.589741 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:19:19.596857 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:19:19.599775 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:19:19.599857 [EMI DOE] emi_dcm 0
779 23:19:19.606982 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:19:19.607065 ==
781 23:19:19.609516 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:19:19.613507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 23:19:19.613591 ==
784 23:19:19.620252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:19:19.626431 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:19:19.633540 [CA 0] Center 37 (7~68) winsize 62
787 23:19:19.637051 [CA 1] Center 37 (6~68) winsize 63
788 23:19:19.640374 [CA 2] Center 35 (5~66) winsize 62
789 23:19:19.643662 [CA 3] Center 35 (5~66) winsize 62
790 23:19:19.647157 [CA 4] Center 34 (3~65) winsize 63
791 23:19:19.650318 [CA 5] Center 34 (3~65) winsize 63
792 23:19:19.650400
793 23:19:19.653608 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 23:19:19.653691
795 23:19:19.656742 [CATrainingPosCal] consider 1 rank data
796 23:19:19.660133 u2DelayCellTimex100 = 270/100 ps
797 23:19:19.664416 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
798 23:19:19.670461 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
799 23:19:19.673566 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
800 23:19:19.676898 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
801 23:19:19.680343 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
802 23:19:19.683798 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
803 23:19:19.683906
804 23:19:19.686977 CA PerBit enable=1, Macro0, CA PI delay=34
805 23:19:19.687077
806 23:19:19.690838 [CBTSetCACLKResult] CA Dly = 34
807 23:19:19.690927 CS Dly: 5 (0~36)
808 23:19:19.693754 ==
809 23:19:19.693842 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:19:19.700237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 23:19:19.700325 ==
812 23:19:19.703615 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:19:19.710044 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:19:19.719462 [CA 0] Center 37 (7~68) winsize 62
815 23:19:19.723312 [CA 1] Center 37 (7~68) winsize 62
816 23:19:19.726425 [CA 2] Center 35 (4~66) winsize 63
817 23:19:19.729674 [CA 3] Center 35 (4~66) winsize 63
818 23:19:19.732949 [CA 4] Center 33 (3~64) winsize 62
819 23:19:19.736882 [CA 5] Center 33 (3~64) winsize 62
820 23:19:19.736957
821 23:19:19.739656 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 23:19:19.739754
823 23:19:19.743360 [CATrainingPosCal] consider 2 rank data
824 23:19:19.746735 u2DelayCellTimex100 = 270/100 ps
825 23:19:19.749503 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 23:19:19.756284 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 23:19:19.760246 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 23:19:19.762610 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
829 23:19:19.766787 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 23:19:19.769566 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 23:19:19.769639
832 23:19:19.773647 CA PerBit enable=1, Macro0, CA PI delay=33
833 23:19:19.773736
834 23:19:19.776320 [CBTSetCACLKResult] CA Dly = 33
835 23:19:19.776418 CS Dly: 6 (0~38)
836 23:19:19.779349
837 23:19:19.782891 ----->DramcWriteLeveling(PI) begin...
838 23:19:19.782991 ==
839 23:19:19.786191 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:19:19.789295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 23:19:19.789369 ==
842 23:19:19.792833 Write leveling (Byte 0): 28 => 28
843 23:19:19.796448 Write leveling (Byte 1): 28 => 28
844 23:19:19.799418 DramcWriteLeveling(PI) end<-----
845 23:19:19.799525
846 23:19:19.799616 ==
847 23:19:19.803279 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:19:19.806527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 23:19:19.806633 ==
850 23:19:19.809542 [Gating] SW mode calibration
851 23:19:19.816090 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:19:19.822970 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:19:19.826199 0 6 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
854 23:19:19.829165 0 6 4 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
855 23:19:19.836805 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:19:19.839963 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:19:19.843232 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:19:19.846128 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:19:19.852676 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:19:19.856390 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:19:19.859683 0 7 0 | B1->B0 | 2929 2f2f | 1 0 | (0 0) (1 1)
862 23:19:19.866843 0 7 4 | B1->B0 | 3e3e 3d3d | 0 0 | (0 0) (1 1)
863 23:19:19.869684 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 23:19:19.872927 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 23:19:19.879572 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 23:19:19.883405 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 23:19:19.886175 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 23:19:19.892537 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 23:19:19.896070 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 23:19:19.899560 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 23:19:19.906387 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 23:19:19.909925 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 23:19:19.912827 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 23:19:19.916095 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 23:19:19.923286 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 23:19:19.926900 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 23:19:19.929892 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 23:19:19.936198 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 23:19:19.939764 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 23:19:19.943373 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 23:19:19.949613 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 23:19:19.952669 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 23:19:19.956430 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 23:19:19.963129 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 23:19:19.965956 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
886 23:19:19.969470 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 23:19:19.972874 Total UI for P1: 0, mck2ui 16
888 23:19:19.976442 best dqsien dly found for B0: ( 0, 10, 0)
889 23:19:19.979782 Total UI for P1: 0, mck2ui 16
890 23:19:19.983163 best dqsien dly found for B1: ( 0, 10, 0)
891 23:19:19.986142 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
892 23:19:19.989744 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 23:19:19.989828
894 23:19:19.992869 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 23:19:20.000071 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 23:19:20.000173 [Gating] SW calibration Done
897 23:19:20.002752 ==
898 23:19:20.002827 Dram Type= 6, Freq= 0, CH_0, rank 0
899 23:19:20.010803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 23:19:20.010893 ==
901 23:19:20.010957 RX Vref Scan: 0
902 23:19:20.011017
903 23:19:20.013596 RX Vref 0 -> 0, step: 1
904 23:19:20.013682
905 23:19:20.017124 RX Delay -130 -> 252, step: 16
906 23:19:20.019892 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 23:19:20.023365 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 23:19:20.026906 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 23:19:20.029750 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 23:19:20.036988 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 23:19:20.040041 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 23:19:20.043407 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 23:19:20.046749 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 23:19:20.049769 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
915 23:19:20.056619 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 23:19:20.060453 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 23:19:20.063794 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 23:19:20.067293 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 23:19:20.070296 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 23:19:20.076876 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 23:19:20.080359 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 23:19:20.080466 ==
923 23:19:20.083151 Dram Type= 6, Freq= 0, CH_0, rank 0
924 23:19:20.087177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 23:19:20.087278 ==
926 23:19:20.090378 DQS Delay:
927 23:19:20.090450 DQS0 = 0, DQS1 = 0
928 23:19:20.090513 DQM Delay:
929 23:19:20.093488 DQM0 = 82, DQM1 = 75
930 23:19:20.093571 DQ Delay:
931 23:19:20.097178 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 23:19:20.100397 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
933 23:19:20.103878 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
934 23:19:20.106624 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 23:19:20.106696
936 23:19:20.106756
937 23:19:20.106812 ==
938 23:19:20.110276 Dram Type= 6, Freq= 0, CH_0, rank 0
939 23:19:20.117007 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 23:19:20.117082 ==
941 23:19:20.117154
942 23:19:20.117215
943 23:19:20.117272 TX Vref Scan disable
944 23:19:20.120896 == TX Byte 0 ==
945 23:19:20.123346 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
946 23:19:20.127018 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
947 23:19:20.130666 == TX Byte 1 ==
948 23:19:20.133255 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
949 23:19:20.140601 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
950 23:19:20.140715 ==
951 23:19:20.143214 Dram Type= 6, Freq= 0, CH_0, rank 0
952 23:19:20.146793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 23:19:20.146899 ==
954 23:19:20.159266 TX Vref=22, minBit 0, minWin=27, winSum=443
955 23:19:20.162409 TX Vref=24, minBit 0, minWin=27, winSum=447
956 23:19:20.165535 TX Vref=26, minBit 0, minWin=28, winSum=452
957 23:19:20.168851 TX Vref=28, minBit 2, minWin=28, winSum=457
958 23:19:20.172302 TX Vref=30, minBit 0, minWin=28, winSum=456
959 23:19:20.175467 TX Vref=32, minBit 0, minWin=28, winSum=453
960 23:19:20.182241 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 28
961 23:19:20.182348
962 23:19:20.185483 Final TX Range 1 Vref 28
963 23:19:20.185557
964 23:19:20.185618 ==
965 23:19:20.189035 Dram Type= 6, Freq= 0, CH_0, rank 0
966 23:19:20.192360 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 23:19:20.192433 ==
968 23:19:20.192496
969 23:19:20.195532
970 23:19:20.195629 TX Vref Scan disable
971 23:19:20.199173 == TX Byte 0 ==
972 23:19:20.202094 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
973 23:19:20.205702 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
974 23:19:20.209279 == TX Byte 1 ==
975 23:19:20.212584 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
976 23:19:20.215609 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
977 23:19:20.219094
978 23:19:20.219177 [DATLAT]
979 23:19:20.219242 Freq=800, CH0 RK0
980 23:19:20.219303
981 23:19:20.222240 DATLAT Default: 0xa
982 23:19:20.222322 0, 0xFFFF, sum = 0
983 23:19:20.225801 1, 0xFFFF, sum = 0
984 23:19:20.225915 2, 0xFFFF, sum = 0
985 23:19:20.229155 3, 0xFFFF, sum = 0
986 23:19:20.229231 4, 0xFFFF, sum = 0
987 23:19:20.232702 5, 0xFFFF, sum = 0
988 23:19:20.232802 6, 0xFFFF, sum = 0
989 23:19:20.236065 7, 0xFFFF, sum = 0
990 23:19:20.236156 8, 0x0, sum = 1
991 23:19:20.239112 9, 0x0, sum = 2
992 23:19:20.239209 10, 0x0, sum = 3
993 23:19:20.242456 11, 0x0, sum = 4
994 23:19:20.242562 best_step = 9
995 23:19:20.242645
996 23:19:20.242721 ==
997 23:19:20.245673 Dram Type= 6, Freq= 0, CH_0, rank 0
998 23:19:20.252418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 23:19:20.252534 ==
1000 23:19:20.252624 RX Vref Scan: 1
1001 23:19:20.252718
1002 23:19:20.255455 Set Vref Range= 32 -> 127
1003 23:19:20.255568
1004 23:19:20.259380 RX Vref 32 -> 127, step: 1
1005 23:19:20.259505
1006 23:19:20.259602 RX Delay -111 -> 252, step: 8
1007 23:19:20.262337
1008 23:19:20.262465 Set Vref, RX VrefLevel [Byte0]: 32
1009 23:19:20.265778 [Byte1]: 32
1010 23:19:20.269536
1011 23:19:20.269666 Set Vref, RX VrefLevel [Byte0]: 33
1012 23:19:20.273184 [Byte1]: 33
1013 23:19:20.277633
1014 23:19:20.277755 Set Vref, RX VrefLevel [Byte0]: 34
1015 23:19:20.281553 [Byte1]: 34
1016 23:19:20.285302
1017 23:19:20.285425 Set Vref, RX VrefLevel [Byte0]: 35
1018 23:19:20.288449 [Byte1]: 35
1019 23:19:20.292728
1020 23:19:20.292824 Set Vref, RX VrefLevel [Byte0]: 36
1021 23:19:20.296480 [Byte1]: 36
1022 23:19:20.300967
1023 23:19:20.301055 Set Vref, RX VrefLevel [Byte0]: 37
1024 23:19:20.303579 [Byte1]: 37
1025 23:19:20.307958
1026 23:19:20.308039 Set Vref, RX VrefLevel [Byte0]: 38
1027 23:19:20.311627 [Byte1]: 38
1028 23:19:20.315437
1029 23:19:20.315518 Set Vref, RX VrefLevel [Byte0]: 39
1030 23:19:20.320006 [Byte1]: 39
1031 23:19:20.323329
1032 23:19:20.323410 Set Vref, RX VrefLevel [Byte0]: 40
1033 23:19:20.327692 [Byte1]: 40
1034 23:19:20.331219
1035 23:19:20.331300 Set Vref, RX VrefLevel [Byte0]: 41
1036 23:19:20.334040 [Byte1]: 41
1037 23:19:20.338571
1038 23:19:20.338652 Set Vref, RX VrefLevel [Byte0]: 42
1039 23:19:20.342881 [Byte1]: 42
1040 23:19:20.346427
1041 23:19:20.346508 Set Vref, RX VrefLevel [Byte0]: 43
1042 23:19:20.349799 [Byte1]: 43
1043 23:19:20.353829
1044 23:19:20.353911 Set Vref, RX VrefLevel [Byte0]: 44
1045 23:19:20.357682 [Byte1]: 44
1046 23:19:20.361564
1047 23:19:20.361644 Set Vref, RX VrefLevel [Byte0]: 45
1048 23:19:20.364627 [Byte1]: 45
1049 23:19:20.369500
1050 23:19:20.369581 Set Vref, RX VrefLevel [Byte0]: 46
1051 23:19:20.372620 [Byte1]: 46
1052 23:19:20.376875
1053 23:19:20.376956 Set Vref, RX VrefLevel [Byte0]: 47
1054 23:19:20.380350 [Byte1]: 47
1055 23:19:20.384630
1056 23:19:20.384723 Set Vref, RX VrefLevel [Byte0]: 48
1057 23:19:20.388285 [Byte1]: 48
1058 23:19:20.392600
1059 23:19:20.392682 Set Vref, RX VrefLevel [Byte0]: 49
1060 23:19:20.395689 [Byte1]: 49
1061 23:19:20.399613
1062 23:19:20.399694 Set Vref, RX VrefLevel [Byte0]: 50
1063 23:19:20.403428 [Byte1]: 50
1064 23:19:20.408355
1065 23:19:20.408437 Set Vref, RX VrefLevel [Byte0]: 51
1066 23:19:20.410747 [Byte1]: 51
1067 23:19:20.415078
1068 23:19:20.415164 Set Vref, RX VrefLevel [Byte0]: 52
1069 23:19:20.418428 [Byte1]: 52
1070 23:19:20.423407
1071 23:19:20.423488 Set Vref, RX VrefLevel [Byte0]: 53
1072 23:19:20.426212 [Byte1]: 53
1073 23:19:20.430531
1074 23:19:20.430613 Set Vref, RX VrefLevel [Byte0]: 54
1075 23:19:20.434410 [Byte1]: 54
1076 23:19:20.437876
1077 23:19:20.437957 Set Vref, RX VrefLevel [Byte0]: 55
1078 23:19:20.441920 [Byte1]: 55
1079 23:19:20.446150
1080 23:19:20.446233 Set Vref, RX VrefLevel [Byte0]: 56
1081 23:19:20.449011 [Byte1]: 56
1082 23:19:20.453692
1083 23:19:20.453784 Set Vref, RX VrefLevel [Byte0]: 57
1084 23:19:20.456543 [Byte1]: 57
1085 23:19:20.460902
1086 23:19:20.460984 Set Vref, RX VrefLevel [Byte0]: 58
1087 23:19:20.464583 [Byte1]: 58
1088 23:19:20.468863
1089 23:19:20.468944 Set Vref, RX VrefLevel [Byte0]: 59
1090 23:19:20.471989 [Byte1]: 59
1091 23:19:20.476611
1092 23:19:20.476694 Set Vref, RX VrefLevel [Byte0]: 60
1093 23:19:20.479746 [Byte1]: 60
1094 23:19:20.483804
1095 23:19:20.483936 Set Vref, RX VrefLevel [Byte0]: 61
1096 23:19:20.487133 [Byte1]: 61
1097 23:19:20.491200
1098 23:19:20.491282 Set Vref, RX VrefLevel [Byte0]: 62
1099 23:19:20.494872 [Byte1]: 62
1100 23:19:20.499534
1101 23:19:20.499616 Set Vref, RX VrefLevel [Byte0]: 63
1102 23:19:20.502358 [Byte1]: 63
1103 23:19:20.506687
1104 23:19:20.506769 Set Vref, RX VrefLevel [Byte0]: 64
1105 23:19:20.510079 [Byte1]: 64
1106 23:19:20.514881
1107 23:19:20.514962 Set Vref, RX VrefLevel [Byte0]: 65
1108 23:19:20.518003 [Byte1]: 65
1109 23:19:20.522249
1110 23:19:20.522331 Set Vref, RX VrefLevel [Byte0]: 66
1111 23:19:20.525130 [Byte1]: 66
1112 23:19:20.529821
1113 23:19:20.529903 Set Vref, RX VrefLevel [Byte0]: 67
1114 23:19:20.532807 [Byte1]: 67
1115 23:19:20.537706
1116 23:19:20.537789 Set Vref, RX VrefLevel [Byte0]: 68
1117 23:19:20.541175 [Byte1]: 68
1118 23:19:20.544983
1119 23:19:20.545065 Set Vref, RX VrefLevel [Byte0]: 69
1120 23:19:20.548027 [Byte1]: 69
1121 23:19:20.552688
1122 23:19:20.552777 Set Vref, RX VrefLevel [Byte0]: 70
1123 23:19:20.556221 [Byte1]: 70
1124 23:19:20.560268
1125 23:19:20.560349 Set Vref, RX VrefLevel [Byte0]: 71
1126 23:19:20.563450 [Byte1]: 71
1127 23:19:20.568611
1128 23:19:20.568693 Set Vref, RX VrefLevel [Byte0]: 72
1129 23:19:20.571740 [Byte1]: 72
1130 23:19:20.576269
1131 23:19:20.576353 Set Vref, RX VrefLevel [Byte0]: 73
1132 23:19:20.579281 [Byte1]: 73
1133 23:19:20.583369
1134 23:19:20.583451 Final RX Vref Byte 0 = 52 to rank0
1135 23:19:20.586395 Final RX Vref Byte 1 = 54 to rank0
1136 23:19:20.590612 Final RX Vref Byte 0 = 52 to rank1
1137 23:19:20.593229 Final RX Vref Byte 1 = 54 to rank1==
1138 23:19:20.596824 Dram Type= 6, Freq= 0, CH_0, rank 0
1139 23:19:20.603303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1140 23:19:20.603385 ==
1141 23:19:20.603450 DQS Delay:
1142 23:19:20.603510 DQS0 = 0, DQS1 = 0
1143 23:19:20.606651 DQM Delay:
1144 23:19:20.606732 DQM0 = 84, DQM1 = 73
1145 23:19:20.609912 DQ Delay:
1146 23:19:20.614237 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1147 23:19:20.614320 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1148 23:19:20.616482 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1149 23:19:20.619863 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1150 23:19:20.623069
1151 23:19:20.623151
1152 23:19:20.629844 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1153 23:19:20.633702 CH0 RK0: MR19=606, MR18=3C3C
1154 23:19:20.640043 CH0_RK0: MR19=0x606, MR18=0x3C3C, DQSOSC=394, MR23=63, INC=95, DEC=63
1155 23:19:20.640127
1156 23:19:20.642862 ----->DramcWriteLeveling(PI) begin...
1157 23:19:20.642946 ==
1158 23:19:20.646987 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 23:19:20.649934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1160 23:19:20.650017 ==
1161 23:19:20.653436 Write leveling (Byte 0): 31 => 31
1162 23:19:20.656186 Write leveling (Byte 1): 27 => 27
1163 23:19:20.659681 DramcWriteLeveling(PI) end<-----
1164 23:19:20.659762
1165 23:19:20.659826 ==
1166 23:19:20.662747 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 23:19:20.666910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1168 23:19:20.667012 ==
1169 23:19:20.669604 [Gating] SW mode calibration
1170 23:19:20.676196 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1171 23:19:20.683184 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1172 23:19:20.687047 0 6 0 | B1->B0 | 3333 3232 | 0 1 | (0 1) (1 0)
1173 23:19:20.690452 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1174 23:19:20.696885 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:19:20.700519 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:19:20.703068 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:19:20.709841 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:19:20.713025 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 23:19:20.716520 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 23:19:20.722929 0 7 0 | B1->B0 | 3030 3232 | 0 1 | (0 0) (0 0)
1181 23:19:20.726303 0 7 4 | B1->B0 | 4242 4444 | 0 0 | (0 0) (0 0)
1182 23:19:20.730570 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 23:19:20.736984 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 23:19:20.740195 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 23:19:20.743200 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 23:19:20.749415 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 23:19:20.752731 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 23:19:20.756428 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1189 23:19:20.762872 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 23:19:20.767079 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 23:19:20.769408 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 23:19:20.776510 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 23:19:20.779300 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 23:19:20.782420 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 23:19:20.789745 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 23:19:20.792327 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 23:19:20.796496 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 23:19:20.799118 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 23:19:20.805876 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 23:19:20.809587 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 23:19:20.812636 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 23:19:20.819133 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:19:20.822743 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:19:20.825871 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1205 23:19:20.829133 Total UI for P1: 0, mck2ui 16
1206 23:19:20.832494 best dqsien dly found for B1: ( 0, 9, 30)
1207 23:19:20.838854 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 23:19:20.838937 Total UI for P1: 0, mck2ui 16
1209 23:19:20.846242 best dqsien dly found for B0: ( 0, 10, 0)
1210 23:19:20.849146 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1211 23:19:20.852377 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1212 23:19:20.852459
1213 23:19:20.855983 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1214 23:19:20.859066 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1215 23:19:20.862498 [Gating] SW calibration Done
1216 23:19:20.862580 ==
1217 23:19:20.865753 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 23:19:20.869702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1219 23:19:20.869785 ==
1220 23:19:20.872776 RX Vref Scan: 0
1221 23:19:20.872858
1222 23:19:20.872922 RX Vref 0 -> 0, step: 1
1223 23:19:20.872983
1224 23:19:20.875672 RX Delay -130 -> 252, step: 16
1225 23:19:20.879341 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1226 23:19:20.886758 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1227 23:19:20.930440 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1228 23:19:20.930529 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1229 23:19:20.930782 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1230 23:19:20.931416 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1231 23:19:20.931683 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1232 23:19:20.931752 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1233 23:19:20.932064 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1234 23:19:20.932432 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1235 23:19:20.932513 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1236 23:19:20.932898 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1237 23:19:20.933574 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1238 23:19:20.959373 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1239 23:19:20.959456 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1240 23:19:20.959707 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1241 23:19:20.959773 ==
1242 23:19:20.960287 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 23:19:20.960554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1244 23:19:20.960623 ==
1245 23:19:20.960685 DQS Delay:
1246 23:19:20.960790 DQS0 = 0, DQS1 = 0
1247 23:19:20.960848 DQM Delay:
1248 23:19:20.962102 DQM0 = 82, DQM1 = 74
1249 23:19:20.962183 DQ Delay:
1250 23:19:20.962247 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1251 23:19:20.964128 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1252 23:19:20.967889 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1253 23:19:20.967970 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1254 23:19:20.968035
1255 23:19:20.968097
1256 23:19:20.968173 ==
1257 23:19:20.970706 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 23:19:20.977441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1259 23:19:20.977523 ==
1260 23:19:20.977587
1261 23:19:20.977646
1262 23:19:20.977703 TX Vref Scan disable
1263 23:19:20.981147 == TX Byte 0 ==
1264 23:19:20.984893 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1265 23:19:20.987805 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1266 23:19:20.991684 == TX Byte 1 ==
1267 23:19:20.995304 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1268 23:19:20.998501 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1269 23:19:21.002312 ==
1270 23:19:21.004974 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 23:19:21.007604 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1272 23:19:21.007689 ==
1273 23:19:21.020765 TX Vref=22, minBit 0, minWin=27, winSum=445
1274 23:19:21.023834 TX Vref=24, minBit 14, minWin=27, winSum=452
1275 23:19:21.026946 TX Vref=26, minBit 1, minWin=28, winSum=451
1276 23:19:21.030661 TX Vref=28, minBit 0, minWin=28, winSum=459
1277 23:19:21.034238 TX Vref=30, minBit 0, minWin=28, winSum=458
1278 23:19:21.040563 TX Vref=32, minBit 0, minWin=28, winSum=453
1279 23:19:21.043733 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
1280 23:19:21.043815
1281 23:19:21.047095 Final TX Range 1 Vref 28
1282 23:19:21.047177
1283 23:19:21.047242 ==
1284 23:19:21.050615 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 23:19:21.053987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1286 23:19:21.054070 ==
1287 23:19:21.054133
1288 23:19:21.057117
1289 23:19:21.057198 TX Vref Scan disable
1290 23:19:21.060762 == TX Byte 0 ==
1291 23:19:21.064200 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1292 23:19:21.067095 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1293 23:19:21.070731 == TX Byte 1 ==
1294 23:19:21.074276 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1295 23:19:21.080932 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1296 23:19:21.081040
1297 23:19:21.081126 [DATLAT]
1298 23:19:21.081188 Freq=800, CH0 RK1
1299 23:19:21.081247
1300 23:19:21.084033 DATLAT Default: 0x9
1301 23:19:21.084115 0, 0xFFFF, sum = 0
1302 23:19:21.087548 1, 0xFFFF, sum = 0
1303 23:19:21.087634 2, 0xFFFF, sum = 0
1304 23:19:21.090489 3, 0xFFFF, sum = 0
1305 23:19:21.094017 4, 0xFFFF, sum = 0
1306 23:19:21.094100 5, 0xFFFF, sum = 0
1307 23:19:21.097244 6, 0xFFFF, sum = 0
1308 23:19:21.097327 7, 0xFFFF, sum = 0
1309 23:19:21.097393 8, 0x0, sum = 1
1310 23:19:21.100597 9, 0x0, sum = 2
1311 23:19:21.100680 10, 0x0, sum = 3
1312 23:19:21.103640 11, 0x0, sum = 4
1313 23:19:21.103723 best_step = 9
1314 23:19:21.103787
1315 23:19:21.103845 ==
1316 23:19:21.107437 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 23:19:21.113665 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1318 23:19:21.113747 ==
1319 23:19:21.113812 RX Vref Scan: 0
1320 23:19:21.113871
1321 23:19:21.117197 RX Vref 0 -> 0, step: 1
1322 23:19:21.117278
1323 23:19:21.120928 RX Delay -111 -> 252, step: 8
1324 23:19:21.123706 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1325 23:19:21.127044 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1326 23:19:21.133823 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1327 23:19:21.137365 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1328 23:19:21.140445 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1329 23:19:21.144355 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1330 23:19:21.147399 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1331 23:19:21.154162 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1332 23:19:21.156850 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1333 23:19:21.161421 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1334 23:19:21.163529 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1335 23:19:21.167254 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1336 23:19:21.173689 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1337 23:19:21.176850 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1338 23:19:21.180636 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1339 23:19:21.183801 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1340 23:19:21.183882 ==
1341 23:19:21.187064 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 23:19:21.193677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1343 23:19:21.193760 ==
1344 23:19:21.193825 DQS Delay:
1345 23:19:21.193885 DQS0 = 0, DQS1 = 0
1346 23:19:21.197166 DQM Delay:
1347 23:19:21.197247 DQM0 = 85, DQM1 = 74
1348 23:19:21.200345 DQ Delay:
1349 23:19:21.203751 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1350 23:19:21.207016 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1351 23:19:21.207098 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1352 23:19:21.213736 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1353 23:19:21.213818
1354 23:19:21.213882
1355 23:19:21.220590 [DQSOSCAuto] RK1, (LSB)MR18= 0x4444, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1356 23:19:21.223472 CH0 RK1: MR19=606, MR18=4444
1357 23:19:21.230841 CH0_RK1: MR19=0x606, MR18=0x4444, DQSOSC=392, MR23=63, INC=96, DEC=64
1358 23:19:21.234054 [RxdqsGatingPostProcess] freq 800
1359 23:19:21.237056 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1360 23:19:21.240269 Pre-setting of DQS Precalculation
1361 23:19:21.247143 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1362 23:19:21.247226 ==
1363 23:19:21.250479 Dram Type= 6, Freq= 0, CH_1, rank 0
1364 23:19:21.253967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1365 23:19:21.254049 ==
1366 23:19:21.257187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1367 23:19:21.263987 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1368 23:19:21.273466 [CA 0] Center 36 (6~67) winsize 62
1369 23:19:21.277163 [CA 1] Center 36 (6~67) winsize 62
1370 23:19:21.280294 [CA 2] Center 34 (4~65) winsize 62
1371 23:19:21.283468 [CA 3] Center 34 (4~65) winsize 62
1372 23:19:21.287129 [CA 4] Center 33 (3~63) winsize 61
1373 23:19:21.290036 [CA 5] Center 33 (3~63) winsize 61
1374 23:19:21.290117
1375 23:19:21.293984 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1376 23:19:21.294066
1377 23:19:21.296862 [CATrainingPosCal] consider 1 rank data
1378 23:19:21.300343 u2DelayCellTimex100 = 270/100 ps
1379 23:19:21.303425 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1380 23:19:21.306628 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1381 23:19:21.313718 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1382 23:19:21.316545 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1383 23:19:21.320921 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
1384 23:19:21.323584 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1385 23:19:21.323682
1386 23:19:21.327288 CA PerBit enable=1, Macro0, CA PI delay=33
1387 23:19:21.327369
1388 23:19:21.330161 [CBTSetCACLKResult] CA Dly = 33
1389 23:19:21.330241 CS Dly: 4 (0~35)
1390 23:19:21.330320 ==
1391 23:19:21.333262 Dram Type= 6, Freq= 0, CH_1, rank 1
1392 23:19:21.339879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1393 23:19:21.339984 ==
1394 23:19:21.343265 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1395 23:19:21.349854 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1396 23:19:21.359212 [CA 0] Center 36 (6~67) winsize 62
1397 23:19:21.363197 [CA 1] Center 36 (5~68) winsize 64
1398 23:19:21.366440 [CA 2] Center 34 (4~65) winsize 62
1399 23:19:21.369545 [CA 3] Center 34 (4~65) winsize 62
1400 23:19:21.372555 [CA 4] Center 33 (2~64) winsize 63
1401 23:19:21.376373 [CA 5] Center 33 (2~64) winsize 63
1402 23:19:21.376472
1403 23:19:21.379289 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1404 23:19:21.379387
1405 23:19:21.382881 [CATrainingPosCal] consider 2 rank data
1406 23:19:21.385785 u2DelayCellTimex100 = 270/100 ps
1407 23:19:21.389662 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1408 23:19:21.392244 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1409 23:19:21.400046 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1410 23:19:21.402473 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1411 23:19:21.405770 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
1412 23:19:21.409144 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1413 23:19:21.409224
1414 23:19:21.412875 CA PerBit enable=1, Macro0, CA PI delay=33
1415 23:19:21.412955
1416 23:19:21.416169 [CBTSetCACLKResult] CA Dly = 33
1417 23:19:21.416248 CS Dly: 4 (0~36)
1418 23:19:21.416310
1419 23:19:21.419578 ----->DramcWriteLeveling(PI) begin...
1420 23:19:21.423219 ==
1421 23:19:21.423297 Dram Type= 6, Freq= 0, CH_1, rank 0
1422 23:19:21.429573 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1423 23:19:21.429656 ==
1424 23:19:21.432718 Write leveling (Byte 0): 25 => 25
1425 23:19:21.436045 Write leveling (Byte 1): 26 => 26
1426 23:19:21.439061 DramcWriteLeveling(PI) end<-----
1427 23:19:21.439141
1428 23:19:21.439203 ==
1429 23:19:21.442293 Dram Type= 6, Freq= 0, CH_1, rank 0
1430 23:19:21.445741 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1431 23:19:21.445823 ==
1432 23:19:21.449102 [Gating] SW mode calibration
1433 23:19:21.456166 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1434 23:19:21.458949 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1435 23:19:21.466106 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
1436 23:19:21.469370 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1437 23:19:21.472523 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1438 23:19:21.479882 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 23:19:21.482564 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 23:19:21.485990 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 23:19:21.492736 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 23:19:21.495470 0 6 28 | B1->B0 | 2626 3131 | 0 0 | (0 0) (1 1)
1443 23:19:21.499254 0 7 0 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)
1444 23:19:21.505578 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1445 23:19:21.509481 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1446 23:19:21.512042 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 23:19:21.519753 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 23:19:21.522308 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 23:19:21.525502 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1450 23:19:21.532892 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1451 23:19:21.535864 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1452 23:19:21.539338 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1453 23:19:21.545766 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 23:19:21.548632 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 23:19:21.551990 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 23:19:21.559062 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 23:19:21.561865 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 23:19:21.565796 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 23:19:21.572469 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 23:19:21.575374 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 23:19:21.578857 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 23:19:21.581859 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 23:19:21.588852 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 23:19:21.591942 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 23:19:21.596203 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 23:19:21.602301 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 23:19:21.605602 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1468 23:19:21.609230 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1469 23:19:21.612172 Total UI for P1: 0, mck2ui 16
1470 23:19:21.615244 best dqsien dly found for B0: ( 0, 10, 0)
1471 23:19:21.618635 Total UI for P1: 0, mck2ui 16
1472 23:19:21.622210 best dqsien dly found for B1: ( 0, 10, 0)
1473 23:19:21.625411 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1474 23:19:21.628671 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1475 23:19:21.628793
1476 23:19:21.636127 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1477 23:19:21.638610 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1478 23:19:21.638703 [Gating] SW calibration Done
1479 23:19:21.642044 ==
1480 23:19:21.646009 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 23:19:21.648697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1482 23:19:21.648790 ==
1483 23:19:21.648851 RX Vref Scan: 0
1484 23:19:21.648909
1485 23:19:21.653065 RX Vref 0 -> 0, step: 1
1486 23:19:21.653134
1487 23:19:21.655232 RX Delay -130 -> 252, step: 16
1488 23:19:21.659249 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1489 23:19:21.661871 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1490 23:19:21.668601 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1491 23:19:21.671762 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1492 23:19:21.675310 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1493 23:19:21.679122 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1494 23:19:21.682179 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1495 23:19:21.685535 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1496 23:19:21.691851 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1497 23:19:21.695439 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1498 23:19:21.698533 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1499 23:19:21.702311 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1500 23:19:21.708684 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1501 23:19:21.711810 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1502 23:19:21.715367 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1503 23:19:21.719289 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1504 23:19:21.719369 ==
1505 23:19:21.722082 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 23:19:21.725291 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1507 23:19:21.729401 ==
1508 23:19:21.729494 DQS Delay:
1509 23:19:21.729559 DQS0 = 0, DQS1 = 0
1510 23:19:21.732441 DQM Delay:
1511 23:19:21.732547 DQM0 = 81, DQM1 = 71
1512 23:19:21.736193 DQ Delay:
1513 23:19:21.736273 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1514 23:19:21.738664 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1515 23:19:21.742845 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1516 23:19:21.745559 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1517 23:19:21.745656
1518 23:19:21.749647
1519 23:19:21.749742 ==
1520 23:19:21.751760 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 23:19:21.755442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1522 23:19:21.755512 ==
1523 23:19:21.755574
1524 23:19:21.755639
1525 23:19:21.758412 TX Vref Scan disable
1526 23:19:21.758483 == TX Byte 0 ==
1527 23:19:21.765449 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1528 23:19:21.768903 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1529 23:19:21.768974 == TX Byte 1 ==
1530 23:19:21.775534 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1531 23:19:21.778482 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1532 23:19:21.778553 ==
1533 23:19:21.782208 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 23:19:21.785311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1535 23:19:21.785420 ==
1536 23:19:21.798275 TX Vref=22, minBit 0, minWin=27, winSum=450
1537 23:19:21.801950 TX Vref=24, minBit 0, minWin=27, winSum=456
1538 23:19:21.804974 TX Vref=26, minBit 1, minWin=28, winSum=456
1539 23:19:21.808812 TX Vref=28, minBit 3, minWin=28, winSum=459
1540 23:19:21.811800 TX Vref=30, minBit 3, minWin=28, winSum=458
1541 23:19:21.815437 TX Vref=32, minBit 8, minWin=28, winSum=459
1542 23:19:21.821815 [TxChooseVref] Worse bit 3, Min win 28, Win sum 459, Final Vref 28
1543 23:19:21.821896
1544 23:19:21.825043 Final TX Range 1 Vref 28
1545 23:19:21.825123
1546 23:19:21.825185 ==
1547 23:19:21.828468 Dram Type= 6, Freq= 0, CH_1, rank 0
1548 23:19:21.832192 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1549 23:19:21.832273 ==
1550 23:19:21.832337
1551 23:19:21.834812
1552 23:19:21.834892 TX Vref Scan disable
1553 23:19:21.838338 == TX Byte 0 ==
1554 23:19:21.841882 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1555 23:19:21.848023 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1556 23:19:21.848125 == TX Byte 1 ==
1557 23:19:21.851680 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1558 23:19:21.858687 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1559 23:19:21.858768
1560 23:19:21.858832 [DATLAT]
1561 23:19:21.858890 Freq=800, CH1 RK0
1562 23:19:21.858947
1563 23:19:21.861271 DATLAT Default: 0xa
1564 23:19:21.861351 0, 0xFFFF, sum = 0
1565 23:19:21.865017 1, 0xFFFF, sum = 0
1566 23:19:21.865098 2, 0xFFFF, sum = 0
1567 23:19:21.868099 3, 0xFFFF, sum = 0
1568 23:19:21.871786 4, 0xFFFF, sum = 0
1569 23:19:21.871868 5, 0xFFFF, sum = 0
1570 23:19:21.875198 6, 0xFFFF, sum = 0
1571 23:19:21.875283 7, 0xFFFF, sum = 0
1572 23:19:21.877842 8, 0x0, sum = 1
1573 23:19:21.877923 9, 0x0, sum = 2
1574 23:19:21.877987 10, 0x0, sum = 3
1575 23:19:21.881219 11, 0x0, sum = 4
1576 23:19:21.881300 best_step = 9
1577 23:19:21.881364
1578 23:19:21.881423 ==
1579 23:19:21.885184 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 23:19:21.891664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1581 23:19:21.891744 ==
1582 23:19:21.891807 RX Vref Scan: 1
1583 23:19:21.891865
1584 23:19:21.894725 Set Vref Range= 32 -> 127
1585 23:19:21.894804
1586 23:19:21.898048 RX Vref 32 -> 127, step: 1
1587 23:19:21.898128
1588 23:19:21.901186 RX Delay -111 -> 252, step: 8
1589 23:19:21.901266
1590 23:19:21.904776 Set Vref, RX VrefLevel [Byte0]: 32
1591 23:19:21.907847 [Byte1]: 32
1592 23:19:21.907927
1593 23:19:21.912053 Set Vref, RX VrefLevel [Byte0]: 33
1594 23:19:21.914546 [Byte1]: 33
1595 23:19:21.914627
1596 23:19:21.917974 Set Vref, RX VrefLevel [Byte0]: 34
1597 23:19:21.921308 [Byte1]: 34
1598 23:19:21.924505
1599 23:19:21.924577 Set Vref, RX VrefLevel [Byte0]: 35
1600 23:19:21.927982 [Byte1]: 35
1601 23:19:21.932158
1602 23:19:21.932235 Set Vref, RX VrefLevel [Byte0]: 36
1603 23:19:21.935384 [Byte1]: 36
1604 23:19:21.940254
1605 23:19:21.940331 Set Vref, RX VrefLevel [Byte0]: 37
1606 23:19:21.943237 [Byte1]: 37
1607 23:19:21.948014
1608 23:19:21.948120 Set Vref, RX VrefLevel [Byte0]: 38
1609 23:19:21.950842 [Byte1]: 38
1610 23:19:21.955948
1611 23:19:21.956026 Set Vref, RX VrefLevel [Byte0]: 39
1612 23:19:21.958834 [Byte1]: 39
1613 23:19:21.962653
1614 23:19:21.962734 Set Vref, RX VrefLevel [Byte0]: 40
1615 23:19:21.966561 [Byte1]: 40
1616 23:19:21.970859
1617 23:19:21.970939 Set Vref, RX VrefLevel [Byte0]: 41
1618 23:19:21.973726 [Byte1]: 41
1619 23:19:21.978302
1620 23:19:21.978382 Set Vref, RX VrefLevel [Byte0]: 42
1621 23:19:21.981661 [Byte1]: 42
1622 23:19:21.985531
1623 23:19:21.985642 Set Vref, RX VrefLevel [Byte0]: 43
1624 23:19:21.989171 [Byte1]: 43
1625 23:19:21.993454
1626 23:19:21.993534 Set Vref, RX VrefLevel [Byte0]: 44
1627 23:19:21.997056 [Byte1]: 44
1628 23:19:22.001252
1629 23:19:22.001332 Set Vref, RX VrefLevel [Byte0]: 45
1630 23:19:22.004022 [Byte1]: 45
1631 23:19:22.009992
1632 23:19:22.010072 Set Vref, RX VrefLevel [Byte0]: 46
1633 23:19:22.012049 [Byte1]: 46
1634 23:19:22.016662
1635 23:19:22.016761 Set Vref, RX VrefLevel [Byte0]: 47
1636 23:19:22.020140 [Byte1]: 47
1637 23:19:22.024745
1638 23:19:22.024839 Set Vref, RX VrefLevel [Byte0]: 48
1639 23:19:22.027487 [Byte1]: 48
1640 23:19:22.031996
1641 23:19:22.032076 Set Vref, RX VrefLevel [Byte0]: 49
1642 23:19:22.034760 [Byte1]: 49
1643 23:19:22.039397
1644 23:19:22.039476 Set Vref, RX VrefLevel [Byte0]: 50
1645 23:19:22.042592 [Byte1]: 50
1646 23:19:22.047162
1647 23:19:22.047241 Set Vref, RX VrefLevel [Byte0]: 51
1648 23:19:22.050274 [Byte1]: 51
1649 23:19:22.054735
1650 23:19:22.054815 Set Vref, RX VrefLevel [Byte0]: 52
1651 23:19:22.058422 [Byte1]: 52
1652 23:19:22.062403
1653 23:19:22.062511 Set Vref, RX VrefLevel [Byte0]: 53
1654 23:19:22.065746 [Byte1]: 53
1655 23:19:22.070267
1656 23:19:22.070374 Set Vref, RX VrefLevel [Byte0]: 54
1657 23:19:22.073323 [Byte1]: 54
1658 23:19:22.077990
1659 23:19:22.078070 Set Vref, RX VrefLevel [Byte0]: 55
1660 23:19:22.080753 [Byte1]: 55
1661 23:19:22.085116
1662 23:19:22.085196 Set Vref, RX VrefLevel [Byte0]: 56
1663 23:19:22.088464 [Byte1]: 56
1664 23:19:22.093307
1665 23:19:22.093387 Set Vref, RX VrefLevel [Byte0]: 57
1666 23:19:22.096870 [Byte1]: 57
1667 23:19:22.100828
1668 23:19:22.100902 Set Vref, RX VrefLevel [Byte0]: 58
1669 23:19:22.104306 [Byte1]: 58
1670 23:19:22.107957
1671 23:19:22.108047 Set Vref, RX VrefLevel [Byte0]: 59
1672 23:19:22.111553 [Byte1]: 59
1673 23:19:22.116239
1674 23:19:22.116345 Set Vref, RX VrefLevel [Byte0]: 60
1675 23:19:22.119123 [Byte1]: 60
1676 23:19:22.123266
1677 23:19:22.123376 Set Vref, RX VrefLevel [Byte0]: 61
1678 23:19:22.126979 [Byte1]: 61
1679 23:19:22.130881
1680 23:19:22.131001 Set Vref, RX VrefLevel [Byte0]: 62
1681 23:19:22.134318 [Byte1]: 62
1682 23:19:22.139304
1683 23:19:22.139401 Set Vref, RX VrefLevel [Byte0]: 63
1684 23:19:22.142303 [Byte1]: 63
1685 23:19:22.146437
1686 23:19:22.146518 Set Vref, RX VrefLevel [Byte0]: 64
1687 23:19:22.149720 [Byte1]: 64
1688 23:19:22.154081
1689 23:19:22.154154 Set Vref, RX VrefLevel [Byte0]: 65
1690 23:19:22.157053 [Byte1]: 65
1691 23:19:22.161683
1692 23:19:22.161755 Set Vref, RX VrefLevel [Byte0]: 66
1693 23:19:22.165200 [Byte1]: 66
1694 23:19:22.169612
1695 23:19:22.169699 Set Vref, RX VrefLevel [Byte0]: 67
1696 23:19:22.172320 [Byte1]: 67
1697 23:19:22.176942
1698 23:19:22.177018 Set Vref, RX VrefLevel [Byte0]: 68
1699 23:19:22.183568 [Byte1]: 68
1700 23:19:22.183670
1701 23:19:22.186384 Set Vref, RX VrefLevel [Byte0]: 69
1702 23:19:22.190275 [Byte1]: 69
1703 23:19:22.190377
1704 23:19:22.193749 Set Vref, RX VrefLevel [Byte0]: 70
1705 23:19:22.196519 [Byte1]: 70
1706 23:19:22.199749
1707 23:19:22.199851 Set Vref, RX VrefLevel [Byte0]: 71
1708 23:19:22.203269 [Byte1]: 71
1709 23:19:22.207721
1710 23:19:22.207796 Set Vref, RX VrefLevel [Byte0]: 72
1711 23:19:22.211278 [Byte1]: 72
1712 23:19:22.215143
1713 23:19:22.215237 Set Vref, RX VrefLevel [Byte0]: 73
1714 23:19:22.218137 [Byte1]: 73
1715 23:19:22.223227
1716 23:19:22.223329 Set Vref, RX VrefLevel [Byte0]: 74
1717 23:19:22.226315 [Byte1]: 74
1718 23:19:22.230406
1719 23:19:22.230511 Final RX Vref Byte 0 = 59 to rank0
1720 23:19:22.233810 Final RX Vref Byte 1 = 58 to rank0
1721 23:19:22.236799 Final RX Vref Byte 0 = 59 to rank1
1722 23:19:22.240126 Final RX Vref Byte 1 = 58 to rank1==
1723 23:19:22.243883 Dram Type= 6, Freq= 0, CH_1, rank 0
1724 23:19:22.250314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1725 23:19:22.250428 ==
1726 23:19:22.250534 DQS Delay:
1727 23:19:22.250633 DQS0 = 0, DQS1 = 0
1728 23:19:22.253827 DQM Delay:
1729 23:19:22.253900 DQM0 = 79, DQM1 = 69
1730 23:19:22.257375 DQ Delay:
1731 23:19:22.260310 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1732 23:19:22.264114 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1733 23:19:22.264213 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =60
1734 23:19:22.270370 DQ12 =76, DQ13 =80, DQ14 =76, DQ15 =76
1735 23:19:22.270470
1736 23:19:22.270562
1737 23:19:22.277351 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1738 23:19:22.280672 CH1 RK0: MR19=606, MR18=4A4A
1739 23:19:22.286841 CH1_RK0: MR19=0x606, MR18=0x4A4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1740 23:19:22.286929
1741 23:19:22.290888 ----->DramcWriteLeveling(PI) begin...
1742 23:19:22.290967 ==
1743 23:19:22.293743 Dram Type= 6, Freq= 0, CH_1, rank 1
1744 23:19:22.297764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1745 23:19:22.297863 ==
1746 23:19:22.300818 Write leveling (Byte 0): 25 => 25
1747 23:19:22.304060 Write leveling (Byte 1): 26 => 26
1748 23:19:22.307184 DramcWriteLeveling(PI) end<-----
1749 23:19:22.307301
1750 23:19:22.307393 ==
1751 23:19:22.310599 Dram Type= 6, Freq= 0, CH_1, rank 1
1752 23:19:22.313413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1753 23:19:22.313495 ==
1754 23:19:22.317029 [Gating] SW mode calibration
1755 23:19:22.323948 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1756 23:19:22.330440 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1757 23:19:22.333742 0 6 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
1758 23:19:22.337400 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1759 23:19:22.343724 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1760 23:19:22.347150 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1761 23:19:22.350999 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1762 23:19:22.356839 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1763 23:19:22.360428 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1764 23:19:22.363655 0 6 28 | B1->B0 | 2424 3131 | 0 0 | (1 1) (0 0)
1765 23:19:22.370192 0 7 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1766 23:19:22.373875 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1767 23:19:22.376890 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1768 23:19:22.383447 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1769 23:19:22.387432 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1770 23:19:22.390359 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1771 23:19:22.397064 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1772 23:19:22.400158 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1773 23:19:22.403783 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1774 23:19:22.409848 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1775 23:19:22.413841 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1776 23:19:22.416884 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1777 23:19:22.419966 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 23:19:22.427038 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1779 23:19:22.430195 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1780 23:19:22.433222 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 23:19:22.440257 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 23:19:22.443492 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 23:19:22.446465 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 23:19:22.453397 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 23:19:22.457614 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 23:19:22.460056 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 23:19:22.466834 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 23:19:22.469925 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1789 23:19:22.473101 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1790 23:19:22.476387 Total UI for P1: 0, mck2ui 16
1791 23:19:22.480365 best dqsien dly found for B0: ( 0, 9, 28)
1792 23:19:22.483134 Total UI for P1: 0, mck2ui 16
1793 23:19:22.486715 best dqsien dly found for B1: ( 0, 9, 28)
1794 23:19:22.490081 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1795 23:19:22.493105 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1796 23:19:22.493187
1797 23:19:22.499606 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1798 23:19:22.503063 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1799 23:19:22.506984 [Gating] SW calibration Done
1800 23:19:22.507065 ==
1801 23:19:22.509740 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 23:19:22.512908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1803 23:19:22.512989 ==
1804 23:19:22.513054 RX Vref Scan: 0
1805 23:19:22.513113
1806 23:19:22.516355 RX Vref 0 -> 0, step: 1
1807 23:19:22.516436
1808 23:19:22.519589 RX Delay -130 -> 252, step: 16
1809 23:19:22.523365 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1810 23:19:22.526268 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1811 23:19:22.533323 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1812 23:19:22.536523 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1813 23:19:22.539915 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1814 23:19:22.543232 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1815 23:19:22.546825 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1816 23:19:22.553767 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1817 23:19:22.556122 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1818 23:19:22.559833 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1819 23:19:22.563227 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1820 23:19:22.566427 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1821 23:19:22.573620 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1822 23:19:22.576908 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1823 23:19:22.579651 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1824 23:19:22.583268 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1825 23:19:22.583350 ==
1826 23:19:22.586098 Dram Type= 6, Freq= 0, CH_1, rank 1
1827 23:19:22.593129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1828 23:19:22.593212 ==
1829 23:19:22.593277 DQS Delay:
1830 23:19:22.593337 DQS0 = 0, DQS1 = 0
1831 23:19:22.596111 DQM Delay:
1832 23:19:22.596193 DQM0 = 81, DQM1 = 71
1833 23:19:22.599497 DQ Delay:
1834 23:19:22.602804 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1835 23:19:22.606357 DQ4 =77, DQ5 =101, DQ6 =85, DQ7 =77
1836 23:19:22.609475 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1837 23:19:22.613346 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1838 23:19:22.613427
1839 23:19:22.613490
1840 23:19:22.613549 ==
1841 23:19:22.616201 Dram Type= 6, Freq= 0, CH_1, rank 1
1842 23:19:22.619307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1843 23:19:22.619389 ==
1844 23:19:22.619453
1845 23:19:22.619512
1846 23:19:22.622696 TX Vref Scan disable
1847 23:19:22.622777 == TX Byte 0 ==
1848 23:19:22.629620 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1849 23:19:22.632669 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1850 23:19:22.632793 == TX Byte 1 ==
1851 23:19:22.639345 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1852 23:19:22.643307 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1853 23:19:22.643389 ==
1854 23:19:22.645755 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 23:19:22.649341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1856 23:19:22.649423 ==
1857 23:19:22.663488 TX Vref=22, minBit 10, minWin=27, winSum=447
1858 23:19:22.667213 TX Vref=24, minBit 0, minWin=28, winSum=451
1859 23:19:22.669592 TX Vref=26, minBit 0, minWin=28, winSum=454
1860 23:19:22.673023 TX Vref=28, minBit 0, minWin=28, winSum=456
1861 23:19:22.676498 TX Vref=30, minBit 0, minWin=28, winSum=453
1862 23:19:22.683688 TX Vref=32, minBit 0, minWin=28, winSum=452
1863 23:19:22.686454 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
1864 23:19:22.686538
1865 23:19:22.690128 Final TX Range 1 Vref 28
1866 23:19:22.690211
1867 23:19:22.690275 ==
1868 23:19:22.693475 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 23:19:22.696390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1870 23:19:22.696474 ==
1871 23:19:22.699972
1872 23:19:22.700053
1873 23:19:22.700117 TX Vref Scan disable
1874 23:19:22.703265 == TX Byte 0 ==
1875 23:19:22.706629 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1876 23:19:22.710038 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1877 23:19:22.713311 == TX Byte 1 ==
1878 23:19:22.716839 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1879 23:19:22.720257 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1880 23:19:22.723357
1881 23:19:22.723438 [DATLAT]
1882 23:19:22.723502 Freq=800, CH1 RK1
1883 23:19:22.723562
1884 23:19:22.726463 DATLAT Default: 0x9
1885 23:19:22.726544 0, 0xFFFF, sum = 0
1886 23:19:22.729787 1, 0xFFFF, sum = 0
1887 23:19:22.729870 2, 0xFFFF, sum = 0
1888 23:19:22.733376 3, 0xFFFF, sum = 0
1889 23:19:22.733459 4, 0xFFFF, sum = 0
1890 23:19:22.736417 5, 0xFFFF, sum = 0
1891 23:19:22.739482 6, 0xFFFF, sum = 0
1892 23:19:22.739565 7, 0xFFFF, sum = 0
1893 23:19:22.739631 8, 0x0, sum = 1
1894 23:19:22.742993 9, 0x0, sum = 2
1895 23:19:22.743076 10, 0x0, sum = 3
1896 23:19:22.747406 11, 0x0, sum = 4
1897 23:19:22.747489 best_step = 9
1898 23:19:22.747553
1899 23:19:22.747612 ==
1900 23:19:22.749760 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 23:19:22.756311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1902 23:19:22.756393 ==
1903 23:19:22.756458 RX Vref Scan: 0
1904 23:19:22.756517
1905 23:19:22.759792 RX Vref 0 -> 0, step: 1
1906 23:19:22.759873
1907 23:19:22.763262 RX Delay -111 -> 252, step: 8
1908 23:19:22.766539 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1909 23:19:22.769891 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1910 23:19:22.776874 iDelay=217, Bit 2, Center 68 (-55 ~ 192) 248
1911 23:19:22.779638 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1912 23:19:22.783527 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1913 23:19:22.787026 iDelay=217, Bit 5, Center 92 (-31 ~ 216) 248
1914 23:19:22.789848 iDelay=217, Bit 6, Center 88 (-31 ~ 208) 240
1915 23:19:22.796182 iDelay=217, Bit 7, Center 76 (-47 ~ 200) 248
1916 23:19:22.799878 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1917 23:19:22.802871 iDelay=217, Bit 9, Center 56 (-63 ~ 176) 240
1918 23:19:22.806790 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1919 23:19:22.809405 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1920 23:19:22.816326 iDelay=217, Bit 12, Center 84 (-39 ~ 208) 248
1921 23:19:22.819406 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1922 23:19:22.822959 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1923 23:19:22.826160 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1924 23:19:22.826241 ==
1925 23:19:22.829186 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 23:19:22.836154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1927 23:19:22.836237 ==
1928 23:19:22.836301 DQS Delay:
1929 23:19:22.839198 DQS0 = 0, DQS1 = 0
1930 23:19:22.839278 DQM Delay:
1931 23:19:22.839341 DQM0 = 80, DQM1 = 71
1932 23:19:22.842675 DQ Delay:
1933 23:19:22.847470 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =80
1934 23:19:22.849616 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1935 23:19:22.853017 DQ8 =56, DQ9 =56, DQ10 =72, DQ11 =64
1936 23:19:22.856252 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
1937 23:19:22.856353
1938 23:19:22.856447
1939 23:19:22.862915 [DQSOSCAuto] RK1, (LSB)MR18= 0x3737, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1940 23:19:22.865993 CH1 RK1: MR19=606, MR18=3737
1941 23:19:22.872491 CH1_RK1: MR19=0x606, MR18=0x3737, DQSOSC=395, MR23=63, INC=94, DEC=63
1942 23:19:22.876138 [RxdqsGatingPostProcess] freq 800
1943 23:19:22.879801 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1944 23:19:22.882952 Pre-setting of DQS Precalculation
1945 23:19:22.889380 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1946 23:19:22.895728 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1947 23:19:22.902785 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1948 23:19:22.902864
1949 23:19:22.902934
1950 23:19:22.906482 [Calibration Summary] 1600 Mbps
1951 23:19:22.906553 CH 0, Rank 0
1952 23:19:22.909405 SW Impedance : PASS
1953 23:19:22.912361 DUTY Scan : NO K
1954 23:19:22.912457 ZQ Calibration : PASS
1955 23:19:22.915986 Jitter Meter : NO K
1956 23:19:22.916081 CBT Training : PASS
1957 23:19:22.919425 Write leveling : PASS
1958 23:19:22.923017 RX DQS gating : PASS
1959 23:19:22.923091 RX DQ/DQS(RDDQC) : PASS
1960 23:19:22.926155 TX DQ/DQS : PASS
1961 23:19:22.929297 RX DATLAT : PASS
1962 23:19:22.929373 RX DQ/DQS(Engine): PASS
1963 23:19:22.932631 TX OE : NO K
1964 23:19:22.932745 All Pass.
1965 23:19:22.932841
1966 23:19:22.936425 CH 0, Rank 1
1967 23:19:22.936508 SW Impedance : PASS
1968 23:19:22.939612 DUTY Scan : NO K
1969 23:19:22.942766 ZQ Calibration : PASS
1970 23:19:22.942849 Jitter Meter : NO K
1971 23:19:22.945879 CBT Training : PASS
1972 23:19:22.950118 Write leveling : PASS
1973 23:19:22.950202 RX DQS gating : PASS
1974 23:19:22.953121 RX DQ/DQS(RDDQC) : PASS
1975 23:19:22.953220 TX DQ/DQS : PASS
1976 23:19:22.955996 RX DATLAT : PASS
1977 23:19:22.959302 RX DQ/DQS(Engine): PASS
1978 23:19:22.959384 TX OE : NO K
1979 23:19:22.963138 All Pass.
1980 23:19:22.963221
1981 23:19:22.963304 CH 1, Rank 0
1982 23:19:22.966901 SW Impedance : PASS
1983 23:19:22.966984 DUTY Scan : NO K
1984 23:19:22.969235 ZQ Calibration : PASS
1985 23:19:22.972418 Jitter Meter : NO K
1986 23:19:22.972500 CBT Training : PASS
1987 23:19:22.976231 Write leveling : PASS
1988 23:19:22.979075 RX DQS gating : PASS
1989 23:19:22.979158 RX DQ/DQS(RDDQC) : PASS
1990 23:19:22.982552 TX DQ/DQS : PASS
1991 23:19:22.986290 RX DATLAT : PASS
1992 23:19:22.986373 RX DQ/DQS(Engine): PASS
1993 23:19:22.989545 TX OE : NO K
1994 23:19:22.989627 All Pass.
1995 23:19:22.989711
1996 23:19:22.992538 CH 1, Rank 1
1997 23:19:22.992649 SW Impedance : PASS
1998 23:19:22.996471 DUTY Scan : NO K
1999 23:19:22.999047 ZQ Calibration : PASS
2000 23:19:22.999130 Jitter Meter : NO K
2001 23:19:23.003514 CBT Training : PASS
2002 23:19:23.003608 Write leveling : PASS
2003 23:19:23.005877 RX DQS gating : PASS
2004 23:19:23.008994 RX DQ/DQS(RDDQC) : PASS
2005 23:19:23.009077 TX DQ/DQS : PASS
2006 23:19:23.013228 RX DATLAT : PASS
2007 23:19:23.016137 RX DQ/DQS(Engine): PASS
2008 23:19:23.016219 TX OE : NO K
2009 23:19:23.019015 All Pass.
2010 23:19:23.019097
2011 23:19:23.019180 DramC Write-DBI off
2012 23:19:23.022200 PER_BANK_REFRESH: Hybrid Mode
2013 23:19:23.026729 TX_TRACKING: ON
2014 23:19:23.029801 [GetDramInforAfterCalByMRR] Vendor 6.
2015 23:19:23.032743 [GetDramInforAfterCalByMRR] Revision 606.
2016 23:19:23.036337 [GetDramInforAfterCalByMRR] Revision 2 0.
2017 23:19:23.036418 MR0 0x3939
2018 23:19:23.036481 MR8 0x1111
2019 23:19:23.042819 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2020 23:19:23.042900
2021 23:19:23.042963 MR0 0x3939
2022 23:19:23.043022 MR8 0x1111
2023 23:19:23.045657 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2024 23:19:23.045737
2025 23:19:23.056071 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2026 23:19:23.058851 [FAST_K] Save calibration result to emmc
2027 23:19:23.062313 [FAST_K] Save calibration result to emmc
2028 23:19:23.065744 dram_init: config_dvfs: 1
2029 23:19:23.069092 dramc_set_vcore_voltage set vcore to 662500
2030 23:19:23.072281 Read voltage for 1200, 2
2031 23:19:23.072361 Vio18 = 0
2032 23:19:23.072425 Vcore = 662500
2033 23:19:23.075603 Vdram = 0
2034 23:19:23.075683 Vddq = 0
2035 23:19:23.075746 Vmddr = 0
2036 23:19:23.082999 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2037 23:19:23.085837 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2038 23:19:23.089472 MEM_TYPE=3, freq_sel=15
2039 23:19:23.092618 sv_algorithm_assistance_LP4_1600
2040 23:19:23.095570 ============ PULL DRAM RESETB DOWN ============
2041 23:19:23.098785 ========== PULL DRAM RESETB DOWN end =========
2042 23:19:23.106312 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2043 23:19:23.108781 ===================================
2044 23:19:23.112318 LPDDR4 DRAM CONFIGURATION
2045 23:19:23.112398 ===================================
2046 23:19:23.116061 EX_ROW_EN[0] = 0x0
2047 23:19:23.118901 EX_ROW_EN[1] = 0x0
2048 23:19:23.118982 LP4Y_EN = 0x0
2049 23:19:23.122854 WORK_FSP = 0x0
2050 23:19:23.122934 WL = 0x4
2051 23:19:23.125915 RL = 0x4
2052 23:19:23.125996 BL = 0x2
2053 23:19:23.129955 RPST = 0x0
2054 23:19:23.130037 RD_PRE = 0x0
2055 23:19:23.132573 WR_PRE = 0x1
2056 23:19:23.132669 WR_PST = 0x0
2057 23:19:23.135703 DBI_WR = 0x0
2058 23:19:23.135783 DBI_RD = 0x0
2059 23:19:23.138941 OTF = 0x1
2060 23:19:23.142866 ===================================
2061 23:19:23.145641 ===================================
2062 23:19:23.145735 ANA top config
2063 23:19:23.149840 ===================================
2064 23:19:23.152209 DLL_ASYNC_EN = 0
2065 23:19:23.155784 ALL_SLAVE_EN = 0
2066 23:19:23.158708 NEW_RANK_MODE = 1
2067 23:19:23.158790 DLL_IDLE_MODE = 1
2068 23:19:23.162181 LP45_APHY_COMB_EN = 1
2069 23:19:23.165737 TX_ODT_DIS = 1
2070 23:19:23.168969 NEW_8X_MODE = 1
2071 23:19:23.172175 ===================================
2072 23:19:23.175391 ===================================
2073 23:19:23.178565 data_rate = 2400
2074 23:19:23.178646 CKR = 1
2075 23:19:23.182485 DQ_P2S_RATIO = 8
2076 23:19:23.186058 ===================================
2077 23:19:23.189319 CA_P2S_RATIO = 8
2078 23:19:23.192442 DQ_CA_OPEN = 0
2079 23:19:23.195924 DQ_SEMI_OPEN = 0
2080 23:19:23.196006 CA_SEMI_OPEN = 0
2081 23:19:23.199466 CA_FULL_RATE = 0
2082 23:19:23.202553 DQ_CKDIV4_EN = 0
2083 23:19:23.205490 CA_CKDIV4_EN = 0
2084 23:19:23.208537 CA_PREDIV_EN = 0
2085 23:19:23.212247 PH8_DLY = 17
2086 23:19:23.215567 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2087 23:19:23.215648 DQ_AAMCK_DIV = 4
2088 23:19:23.219278 CA_AAMCK_DIV = 4
2089 23:19:23.222300 CA_ADMCK_DIV = 4
2090 23:19:23.225740 DQ_TRACK_CA_EN = 0
2091 23:19:23.228673 CA_PICK = 1200
2092 23:19:23.232344 CA_MCKIO = 1200
2093 23:19:23.232427 MCKIO_SEMI = 0
2094 23:19:23.235701 PLL_FREQ = 2366
2095 23:19:23.238752 DQ_UI_PI_RATIO = 32
2096 23:19:23.241963 CA_UI_PI_RATIO = 0
2097 23:19:23.245698 ===================================
2098 23:19:23.248894 ===================================
2099 23:19:23.252041 memory_type:LPDDR4
2100 23:19:23.252123 GP_NUM : 10
2101 23:19:23.256133 SRAM_EN : 1
2102 23:19:23.259535 MD32_EN : 0
2103 23:19:23.261992 ===================================
2104 23:19:23.262072 [ANA_INIT] >>>>>>>>>>>>>>
2105 23:19:23.265528 <<<<<< [CONFIGURE PHASE]: ANA_TX
2106 23:19:23.269162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2107 23:19:23.272155 ===================================
2108 23:19:23.275483 data_rate = 2400,PCW = 0X5b00
2109 23:19:23.279136 ===================================
2110 23:19:23.282010 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2111 23:19:23.289368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2112 23:19:23.292876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2113 23:19:23.299258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2114 23:19:23.302439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2115 23:19:23.306506 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2116 23:19:23.306588 [ANA_INIT] flow start
2117 23:19:23.308985 [ANA_INIT] PLL >>>>>>>>
2118 23:19:23.312409 [ANA_INIT] PLL <<<<<<<<
2119 23:19:23.312490 [ANA_INIT] MIDPI >>>>>>>>
2120 23:19:23.315697 [ANA_INIT] MIDPI <<<<<<<<
2121 23:19:23.319369 [ANA_INIT] DLL >>>>>>>>
2122 23:19:23.319450 [ANA_INIT] DLL <<<<<<<<
2123 23:19:23.322164 [ANA_INIT] flow end
2124 23:19:23.325356 ============ LP4 DIFF to SE enter ============
2125 23:19:23.328720 ============ LP4 DIFF to SE exit ============
2126 23:19:23.333232 [ANA_INIT] <<<<<<<<<<<<<
2127 23:19:23.336413 [Flow] Enable top DCM control >>>>>
2128 23:19:23.339756 [Flow] Enable top DCM control <<<<<
2129 23:19:23.342355 Enable DLL master slave shuffle
2130 23:19:23.349367 ==============================================================
2131 23:19:23.349464 Gating Mode config
2132 23:19:23.355728 ==============================================================
2133 23:19:23.355830 Config description:
2134 23:19:23.366034 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2135 23:19:23.372819 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2136 23:19:23.379055 SELPH_MODE 0: By rank 1: By Phase
2137 23:19:23.382690 ==============================================================
2138 23:19:23.386971 GAT_TRACK_EN = 1
2139 23:19:23.389135 RX_GATING_MODE = 2
2140 23:19:23.392641 RX_GATING_TRACK_MODE = 2
2141 23:19:23.396066 SELPH_MODE = 1
2142 23:19:23.399058 PICG_EARLY_EN = 1
2143 23:19:23.402247 VALID_LAT_VALUE = 1
2144 23:19:23.409661 ==============================================================
2145 23:19:23.412465 Enter into Gating configuration >>>>
2146 23:19:23.416026 Exit from Gating configuration <<<<
2147 23:19:23.420354 Enter into DVFS_PRE_config >>>>>
2148 23:19:23.428777 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2149 23:19:23.432121 Exit from DVFS_PRE_config <<<<<
2150 23:19:23.435854 Enter into PICG configuration >>>>
2151 23:19:23.438861 Exit from PICG configuration <<<<
2152 23:19:23.442117 [RX_INPUT] configuration >>>>>
2153 23:19:23.442580 [RX_INPUT] configuration <<<<<
2154 23:19:23.449313 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2155 23:19:23.455929 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2156 23:19:23.459181 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2157 23:19:23.466123 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2158 23:19:23.472114 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2159 23:19:23.479208 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2160 23:19:23.483505 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2161 23:19:23.486523 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2162 23:19:23.492432 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2163 23:19:23.495592 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2164 23:19:23.499090 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2165 23:19:23.505822 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2166 23:19:23.509474 ===================================
2167 23:19:23.510029 LPDDR4 DRAM CONFIGURATION
2168 23:19:23.512207 ===================================
2169 23:19:23.515762 EX_ROW_EN[0] = 0x0
2170 23:19:23.516320 EX_ROW_EN[1] = 0x0
2171 23:19:23.519422 LP4Y_EN = 0x0
2172 23:19:23.519985 WORK_FSP = 0x0
2173 23:19:23.523094 WL = 0x4
2174 23:19:23.523629 RL = 0x4
2175 23:19:23.525472 BL = 0x2
2176 23:19:23.525947 RPST = 0x0
2177 23:19:23.528971 RD_PRE = 0x0
2178 23:19:23.532244 WR_PRE = 0x1
2179 23:19:23.532701 WR_PST = 0x0
2180 23:19:23.536015 DBI_WR = 0x0
2181 23:19:23.536574 DBI_RD = 0x0
2182 23:19:23.539188 OTF = 0x1
2183 23:19:23.542777 ===================================
2184 23:19:23.545341 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2185 23:19:23.549083 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2186 23:19:23.552520 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2187 23:19:23.555214 ===================================
2188 23:19:23.558908 LPDDR4 DRAM CONFIGURATION
2189 23:19:23.562419 ===================================
2190 23:19:23.566046 EX_ROW_EN[0] = 0x10
2191 23:19:23.566580 EX_ROW_EN[1] = 0x0
2192 23:19:23.569258 LP4Y_EN = 0x0
2193 23:19:23.569817 WORK_FSP = 0x0
2194 23:19:23.572179 WL = 0x4
2195 23:19:23.572639 RL = 0x4
2196 23:19:23.575479 BL = 0x2
2197 23:19:23.575936 RPST = 0x0
2198 23:19:23.579010 RD_PRE = 0x0
2199 23:19:23.579469 WR_PRE = 0x1
2200 23:19:23.582532 WR_PST = 0x0
2201 23:19:23.583081 DBI_WR = 0x0
2202 23:19:23.585486 DBI_RD = 0x0
2203 23:19:23.585949 OTF = 0x1
2204 23:19:23.590086 ===================================
2205 23:19:23.596206 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2206 23:19:23.596670 ==
2207 23:19:23.599098 Dram Type= 6, Freq= 0, CH_0, rank 0
2208 23:19:23.605842 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2209 23:19:23.606399 ==
2210 23:19:23.606767 [Duty_Offset_Calibration]
2211 23:19:23.608780 B0:0 B1:2 CA:1
2212 23:19:23.609335
2213 23:19:23.612231 [DutyScan_Calibration_Flow] k_type=0
2214 23:19:23.621078
2215 23:19:23.621630 ==CLK 0==
2216 23:19:23.624520 Final CLK duty delay cell = 0
2217 23:19:23.628165 [0] MAX Duty = 5093%(X100), DQS PI = 12
2218 23:19:23.631185 [0] MIN Duty = 4938%(X100), DQS PI = 52
2219 23:19:23.631881 [0] AVG Duty = 5015%(X100)
2220 23:19:23.634340
2221 23:19:23.638553 CH0 CLK Duty spec in!! Max-Min= 155%
2222 23:19:23.640805 [DutyScan_Calibration_Flow] ====Done====
2223 23:19:23.641283
2224 23:19:23.644427 [DutyScan_Calibration_Flow] k_type=1
2225 23:19:23.660590
2226 23:19:23.661224 ==DQS 0 ==
2227 23:19:23.663880 Final DQS duty delay cell = 0
2228 23:19:23.666990 [0] MAX Duty = 5125%(X100), DQS PI = 30
2229 23:19:23.670715 [0] MIN Duty = 5031%(X100), DQS PI = 6
2230 23:19:23.673518 [0] AVG Duty = 5078%(X100)
2231 23:19:23.674043
2232 23:19:23.674406 ==DQS 1 ==
2233 23:19:23.677102 Final DQS duty delay cell = 0
2234 23:19:23.680191 [0] MAX Duty = 5031%(X100), DQS PI = 52
2235 23:19:23.683800 [0] MIN Duty = 4906%(X100), DQS PI = 16
2236 23:19:23.687304 [0] AVG Duty = 4968%(X100)
2237 23:19:23.687993
2238 23:19:23.689786 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2239 23:19:23.690270
2240 23:19:23.693581 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2241 23:19:23.696753 [DutyScan_Calibration_Flow] ====Done====
2242 23:19:23.697213
2243 23:19:23.700426 [DutyScan_Calibration_Flow] k_type=3
2244 23:19:23.716731
2245 23:19:23.717300 ==DQM 0 ==
2246 23:19:23.719845 Final DQM duty delay cell = 0
2247 23:19:23.723075 [0] MAX Duty = 5156%(X100), DQS PI = 22
2248 23:19:23.726880 [0] MIN Duty = 4969%(X100), DQS PI = 54
2249 23:19:23.727441 [0] AVG Duty = 5062%(X100)
2250 23:19:23.730150
2251 23:19:23.730609 ==DQM 1 ==
2252 23:19:23.733261 Final DQM duty delay cell = 0
2253 23:19:23.736690 [0] MAX Duty = 4969%(X100), DQS PI = 54
2254 23:19:23.740831 [0] MIN Duty = 4844%(X100), DQS PI = 0
2255 23:19:23.741445 [0] AVG Duty = 4906%(X100)
2256 23:19:23.741808
2257 23:19:23.746914 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2258 23:19:23.747390
2259 23:19:23.750399 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2260 23:19:23.753640 [DutyScan_Calibration_Flow] ====Done====
2261 23:19:23.754148
2262 23:19:23.756562 [DutyScan_Calibration_Flow] k_type=2
2263 23:19:23.772518
2264 23:19:23.773089 ==DQ 0 ==
2265 23:19:23.774738 Final DQ duty delay cell = -4
2266 23:19:23.778436 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2267 23:19:23.781956 [-4] MIN Duty = 4813%(X100), DQS PI = 10
2268 23:19:23.784598 [-4] AVG Duty = 4937%(X100)
2269 23:19:23.785219
2270 23:19:23.785604 ==DQ 1 ==
2271 23:19:23.788285 Final DQ duty delay cell = -4
2272 23:19:23.791574 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2273 23:19:23.795049 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2274 23:19:23.798128 [-4] AVG Duty = 4969%(X100)
2275 23:19:23.798847
2276 23:19:23.801548 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2277 23:19:23.801964
2278 23:19:23.804521 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2279 23:19:23.808369 [DutyScan_Calibration_Flow] ====Done====
2280 23:19:23.808832 ==
2281 23:19:23.812630 Dram Type= 6, Freq= 0, CH_1, rank 0
2282 23:19:23.814782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2283 23:19:23.815316 ==
2284 23:19:23.817865 [Duty_Offset_Calibration]
2285 23:19:23.818280 B0:0 B1:4 CA:-5
2286 23:19:23.818607
2287 23:19:23.821429 [DutyScan_Calibration_Flow] k_type=0
2288 23:19:23.832066
2289 23:19:23.832596 ==CLK 0==
2290 23:19:23.836346 Final CLK duty delay cell = 0
2291 23:19:23.839141 [0] MAX Duty = 5094%(X100), DQS PI = 24
2292 23:19:23.842407 [0] MIN Duty = 4875%(X100), DQS PI = 46
2293 23:19:23.842931 [0] AVG Duty = 4984%(X100)
2294 23:19:23.845394
2295 23:19:23.848834 CH1 CLK Duty spec in!! Max-Min= 219%
2296 23:19:23.852472 [DutyScan_Calibration_Flow] ====Done====
2297 23:19:23.852933
2298 23:19:23.855842 [DutyScan_Calibration_Flow] k_type=1
2299 23:19:23.870593
2300 23:19:23.871082 ==DQS 0 ==
2301 23:19:23.873999 Final DQS duty delay cell = 0
2302 23:19:23.877347 [0] MAX Duty = 5125%(X100), DQS PI = 16
2303 23:19:23.880769 [0] MIN Duty = 4875%(X100), DQS PI = 40
2304 23:19:23.884897 [0] AVG Duty = 5000%(X100)
2305 23:19:23.885410
2306 23:19:23.885742 ==DQS 1 ==
2307 23:19:23.887654 Final DQS duty delay cell = -4
2308 23:19:23.890840 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2309 23:19:23.894520 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2310 23:19:23.897550 [-4] AVG Duty = 4953%(X100)
2311 23:19:23.897967
2312 23:19:23.901048 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2313 23:19:23.901476
2314 23:19:23.904564 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2315 23:19:23.907472 [DutyScan_Calibration_Flow] ====Done====
2316 23:19:23.907999
2317 23:19:23.910800 [DutyScan_Calibration_Flow] k_type=3
2318 23:19:23.925800
2319 23:19:23.926278 ==DQM 0 ==
2320 23:19:23.929088 Final DQM duty delay cell = -4
2321 23:19:23.932546 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2322 23:19:23.935529 [-4] MIN Duty = 4844%(X100), DQS PI = 42
2323 23:19:23.938889 [-4] AVG Duty = 4968%(X100)
2324 23:19:23.939389
2325 23:19:23.939719 ==DQM 1 ==
2326 23:19:23.942970 Final DQM duty delay cell = -4
2327 23:19:23.945992 [-4] MAX Duty = 5093%(X100), DQS PI = 20
2328 23:19:23.949121 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2329 23:19:23.953064 [-4] AVG Duty = 4984%(X100)
2330 23:19:23.953555
2331 23:19:23.955713 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2332 23:19:23.956130
2333 23:19:23.958991 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2334 23:19:23.962175 [DutyScan_Calibration_Flow] ====Done====
2335 23:19:23.962666
2336 23:19:23.966227 [DutyScan_Calibration_Flow] k_type=2
2337 23:19:23.983337
2338 23:19:23.983822 ==DQ 0 ==
2339 23:19:23.986239 Final DQ duty delay cell = 0
2340 23:19:23.989925 [0] MAX Duty = 5062%(X100), DQS PI = 0
2341 23:19:23.992943 [0] MIN Duty = 4938%(X100), DQS PI = 44
2342 23:19:23.993364 [0] AVG Duty = 5000%(X100)
2343 23:19:23.993694
2344 23:19:23.997205 ==DQ 1 ==
2345 23:19:23.999720 Final DQ duty delay cell = 0
2346 23:19:24.003667 [0] MAX Duty = 5000%(X100), DQS PI = 8
2347 23:19:24.006415 [0] MIN Duty = 4907%(X100), DQS PI = 0
2348 23:19:24.006934 [0] AVG Duty = 4953%(X100)
2349 23:19:24.007265
2350 23:19:24.009918 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2351 23:19:24.010351
2352 23:19:24.013249 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2353 23:19:24.017277 [DutyScan_Calibration_Flow] ====Done====
2354 23:19:24.021684 nWR fixed to 30
2355 23:19:24.025636 [ModeRegInit_LP4] CH0 RK0
2356 23:19:24.026151 [ModeRegInit_LP4] CH0 RK1
2357 23:19:24.029318 [ModeRegInit_LP4] CH1 RK0
2358 23:19:24.032162 [ModeRegInit_LP4] CH1 RK1
2359 23:19:24.032597 match AC timing 6
2360 23:19:24.038409 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2361 23:19:24.041403 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2362 23:19:24.044630 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2363 23:19:24.051353 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2364 23:19:24.054969 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2365 23:19:24.055386 ==
2366 23:19:24.058872 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 23:19:24.061721 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2368 23:19:24.062209 ==
2369 23:19:24.068422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2370 23:19:24.075382 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2371 23:19:24.082296 [CA 0] Center 39 (9~70) winsize 62
2372 23:19:24.086070 [CA 1] Center 39 (8~70) winsize 63
2373 23:19:24.089450 [CA 2] Center 36 (5~67) winsize 63
2374 23:19:24.092355 [CA 3] Center 35 (4~66) winsize 63
2375 23:19:24.096355 [CA 4] Center 34 (3~65) winsize 63
2376 23:19:24.098875 [CA 5] Center 33 (3~64) winsize 62
2377 23:19:24.099292
2378 23:19:24.102879 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2379 23:19:24.103413
2380 23:19:24.106405 [CATrainingPosCal] consider 1 rank data
2381 23:19:24.109385 u2DelayCellTimex100 = 270/100 ps
2382 23:19:24.113197 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2383 23:19:24.115936 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2384 23:19:24.122473 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2385 23:19:24.126502 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2386 23:19:24.129121 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2387 23:19:24.132813 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2388 23:19:24.133561
2389 23:19:24.135454 CA PerBit enable=1, Macro0, CA PI delay=33
2390 23:19:24.135911
2391 23:19:24.139344 [CBTSetCACLKResult] CA Dly = 33
2392 23:19:24.139911 CS Dly: 7 (0~38)
2393 23:19:24.142672 ==
2394 23:19:24.145949 Dram Type= 6, Freq= 0, CH_0, rank 1
2395 23:19:24.149106 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2396 23:19:24.149567 ==
2397 23:19:24.152821 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2398 23:19:24.159313 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2399 23:19:24.168488 [CA 0] Center 39 (8~70) winsize 63
2400 23:19:24.171921 [CA 1] Center 38 (8~69) winsize 62
2401 23:19:24.174836 [CA 2] Center 35 (5~66) winsize 62
2402 23:19:24.178298 [CA 3] Center 35 (4~66) winsize 63
2403 23:19:24.181406 [CA 4] Center 33 (3~64) winsize 62
2404 23:19:24.184824 [CA 5] Center 34 (3~65) winsize 63
2405 23:19:24.185338
2406 23:19:24.188169 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2407 23:19:24.188655
2408 23:19:24.191420 [CATrainingPosCal] consider 2 rank data
2409 23:19:24.194339 u2DelayCellTimex100 = 270/100 ps
2410 23:19:24.197739 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2411 23:19:24.204652 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2412 23:19:24.208225 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2413 23:19:24.211406 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2414 23:19:24.214303 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2415 23:19:24.218221 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2416 23:19:24.218782
2417 23:19:24.221168 CA PerBit enable=1, Macro0, CA PI delay=33
2418 23:19:24.221728
2419 23:19:24.224538 [CBTSetCACLKResult] CA Dly = 33
2420 23:19:24.225152 CS Dly: 7 (0~39)
2421 23:19:24.228533
2422 23:19:24.231762 ----->DramcWriteLeveling(PI) begin...
2423 23:19:24.232326 ==
2424 23:19:24.234068 Dram Type= 6, Freq= 0, CH_0, rank 0
2425 23:19:24.237886 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2426 23:19:24.238344 ==
2427 23:19:24.241378 Write leveling (Byte 0): 28 => 28
2428 23:19:24.244461 Write leveling (Byte 1): 26 => 26
2429 23:19:24.247855 DramcWriteLeveling(PI) end<-----
2430 23:19:24.248420
2431 23:19:24.248837 ==
2432 23:19:24.250944 Dram Type= 6, Freq= 0, CH_0, rank 0
2433 23:19:24.254310 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2434 23:19:24.254906 ==
2435 23:19:24.257990 [Gating] SW mode calibration
2436 23:19:24.264021 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2437 23:19:24.270524 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2438 23:19:24.273901 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2439 23:19:24.277436 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2440 23:19:24.284238 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2441 23:19:24.287282 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2442 23:19:24.291006 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2443 23:19:24.297628 0 11 20 | B1->B0 | 2d2d 2828 | 1 0 | (1 0) (0 0)
2444 23:19:24.300523 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2445 23:19:24.304036 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2446 23:19:24.311357 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2447 23:19:24.314577 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2448 23:19:24.317539 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2449 23:19:24.320833 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2450 23:19:24.327749 0 12 16 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
2451 23:19:24.330990 0 12 20 | B1->B0 | 3838 3c3c | 1 0 | (0 0) (0 0)
2452 23:19:24.334012 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2453 23:19:24.341124 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2454 23:19:24.343900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2455 23:19:24.347519 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2456 23:19:24.354113 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2457 23:19:24.357586 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2458 23:19:24.360885 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2459 23:19:24.366854 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2460 23:19:24.370404 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2461 23:19:24.373972 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2462 23:19:24.380300 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2463 23:19:24.384335 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2464 23:19:24.386651 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2465 23:19:24.393695 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2466 23:19:24.397276 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 23:19:24.400231 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 23:19:24.407073 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 23:19:24.410370 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 23:19:24.413687 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 23:19:24.420500 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 23:19:24.423786 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 23:19:24.427214 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 23:19:24.433258 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 23:19:24.436799 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2476 23:19:24.440266 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2477 23:19:24.443754 Total UI for P1: 0, mck2ui 16
2478 23:19:24.447402 best dqsien dly found for B0: ( 0, 15, 20)
2479 23:19:24.450971 Total UI for P1: 0, mck2ui 16
2480 23:19:24.453176 best dqsien dly found for B1: ( 0, 15, 20)
2481 23:19:24.456996 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2482 23:19:24.460062 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2483 23:19:24.460618
2484 23:19:24.464052 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2485 23:19:24.470130 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2486 23:19:24.470962 [Gating] SW calibration Done
2487 23:19:24.473564 ==
2488 23:19:24.474112 Dram Type= 6, Freq= 0, CH_0, rank 0
2489 23:19:24.480184 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2490 23:19:24.480795 ==
2491 23:19:24.481177 RX Vref Scan: 0
2492 23:19:24.481520
2493 23:19:24.483698 RX Vref 0 -> 0, step: 1
2494 23:19:24.484254
2495 23:19:24.487011 RX Delay -40 -> 252, step: 8
2496 23:19:24.490285 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2497 23:19:24.494061 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2498 23:19:24.497065 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2499 23:19:24.503397 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2500 23:19:24.506717 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2501 23:19:24.509814 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2502 23:19:24.513576 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2503 23:19:24.516563 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2504 23:19:24.523639 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2505 23:19:24.526371 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2506 23:19:24.529922 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2507 23:19:24.532964 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2508 23:19:24.536610 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2509 23:19:24.543007 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2510 23:19:24.546428 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2511 23:19:24.550422 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2512 23:19:24.550986 ==
2513 23:19:24.553266 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 23:19:24.557112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2515 23:19:24.557681 ==
2516 23:19:24.560103 DQS Delay:
2517 23:19:24.560665 DQS0 = 0, DQS1 = 0
2518 23:19:24.562849 DQM Delay:
2519 23:19:24.563306 DQM0 = 115, DQM1 = 106
2520 23:19:24.563671 DQ Delay:
2521 23:19:24.566482 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2522 23:19:24.573442 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2523 23:19:24.576142 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2524 23:19:24.579789 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2525 23:19:24.580362
2526 23:19:24.580762
2527 23:19:24.581107 ==
2528 23:19:24.583048 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 23:19:24.586846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2530 23:19:24.587415 ==
2531 23:19:24.587781
2532 23:19:24.588115
2533 23:19:24.590448 TX Vref Scan disable
2534 23:19:24.592969 == TX Byte 0 ==
2535 23:19:24.596507 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2536 23:19:24.599798 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2537 23:19:24.603341 == TX Byte 1 ==
2538 23:19:24.607246 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2539 23:19:24.610076 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2540 23:19:24.610635 ==
2541 23:19:24.613656 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 23:19:24.617084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2543 23:19:24.617645 ==
2544 23:19:24.629840 TX Vref=22, minBit 9, minWin=25, winSum=417
2545 23:19:24.633265 TX Vref=24, minBit 8, minWin=25, winSum=424
2546 23:19:24.635937 TX Vref=26, minBit 10, minWin=25, winSum=429
2547 23:19:24.639916 TX Vref=28, minBit 8, minWin=25, winSum=431
2548 23:19:24.643076 TX Vref=30, minBit 8, minWin=26, winSum=432
2549 23:19:24.649356 TX Vref=32, minBit 8, minWin=26, winSum=437
2550 23:19:24.652862 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 32
2551 23:19:24.653428
2552 23:19:24.656354 Final TX Range 1 Vref 32
2553 23:19:24.656971
2554 23:19:24.657456 ==
2555 23:19:24.659275 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 23:19:24.663255 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2557 23:19:24.663838 ==
2558 23:19:24.665720
2559 23:19:24.666193
2560 23:19:24.666670 TX Vref Scan disable
2561 23:19:24.669759 == TX Byte 0 ==
2562 23:19:24.672564 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2563 23:19:24.676514 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2564 23:19:24.679227 == TX Byte 1 ==
2565 23:19:24.683322 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2566 23:19:24.689607 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2567 23:19:24.690284
2568 23:19:24.690770 [DATLAT]
2569 23:19:24.691221 Freq=1200, CH0 RK0
2570 23:19:24.691667
2571 23:19:24.692464 DATLAT Default: 0xd
2572 23:19:24.692909 0, 0xFFFF, sum = 0
2573 23:19:24.696001 1, 0xFFFF, sum = 0
2574 23:19:24.696484 2, 0xFFFF, sum = 0
2575 23:19:24.699344 3, 0xFFFF, sum = 0
2576 23:19:24.703060 4, 0xFFFF, sum = 0
2577 23:19:24.703643 5, 0xFFFF, sum = 0
2578 23:19:24.705946 6, 0xFFFF, sum = 0
2579 23:19:24.706520 7, 0xFFFF, sum = 0
2580 23:19:24.709661 8, 0xFFFF, sum = 0
2581 23:19:24.710242 9, 0xFFFF, sum = 0
2582 23:19:24.713055 10, 0xFFFF, sum = 0
2583 23:19:24.713635 11, 0x0, sum = 1
2584 23:19:24.716063 12, 0x0, sum = 2
2585 23:19:24.716645 13, 0x0, sum = 3
2586 23:19:24.719682 14, 0x0, sum = 4
2587 23:19:24.720263 best_step = 12
2588 23:19:24.720782
2589 23:19:24.721247 ==
2590 23:19:24.722620 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 23:19:24.726224 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2592 23:19:24.726802 ==
2593 23:19:24.729419 RX Vref Scan: 1
2594 23:19:24.729987
2595 23:19:24.733164 Set Vref Range= 32 -> 127
2596 23:19:24.733730
2597 23:19:24.734218 RX Vref 32 -> 127, step: 1
2598 23:19:24.734671
2599 23:19:24.735750 RX Delay -21 -> 252, step: 4
2600 23:19:24.736227
2601 23:19:24.740013 Set Vref, RX VrefLevel [Byte0]: 32
2602 23:19:24.743239 [Byte1]: 32
2603 23:19:24.746113
2604 23:19:24.746632 Set Vref, RX VrefLevel [Byte0]: 33
2605 23:19:24.749302 [Byte1]: 33
2606 23:19:24.753952
2607 23:19:24.754520 Set Vref, RX VrefLevel [Byte0]: 34
2608 23:19:24.757997 [Byte1]: 34
2609 23:19:24.762689
2610 23:19:24.763241 Set Vref, RX VrefLevel [Byte0]: 35
2611 23:19:24.765216 [Byte1]: 35
2612 23:19:24.769945
2613 23:19:24.770501 Set Vref, RX VrefLevel [Byte0]: 36
2614 23:19:24.773403 [Byte1]: 36
2615 23:19:24.777975
2616 23:19:24.778436 Set Vref, RX VrefLevel [Byte0]: 37
2617 23:19:24.781450 [Byte1]: 37
2618 23:19:24.785672
2619 23:19:24.786232 Set Vref, RX VrefLevel [Byte0]: 38
2620 23:19:24.788883 [Byte1]: 38
2621 23:19:24.794351
2622 23:19:24.794812 Set Vref, RX VrefLevel [Byte0]: 39
2623 23:19:24.796538 [Byte1]: 39
2624 23:19:24.801574
2625 23:19:24.802031 Set Vref, RX VrefLevel [Byte0]: 40
2626 23:19:24.805312 [Byte1]: 40
2627 23:19:24.809606
2628 23:19:24.810149 Set Vref, RX VrefLevel [Byte0]: 41
2629 23:19:24.812869 [Byte1]: 41
2630 23:19:24.817170
2631 23:19:24.817721 Set Vref, RX VrefLevel [Byte0]: 42
2632 23:19:24.820555 [Byte1]: 42
2633 23:19:24.825447
2634 23:19:24.825999 Set Vref, RX VrefLevel [Byte0]: 43
2635 23:19:24.829563 [Byte1]: 43
2636 23:19:24.833762
2637 23:19:24.834316 Set Vref, RX VrefLevel [Byte0]: 44
2638 23:19:24.836565 [Byte1]: 44
2639 23:19:24.841051
2640 23:19:24.841527 Set Vref, RX VrefLevel [Byte0]: 45
2641 23:19:24.844644 [Byte1]: 45
2642 23:19:24.848981
2643 23:19:24.849723 Set Vref, RX VrefLevel [Byte0]: 46
2644 23:19:24.852211 [Byte1]: 46
2645 23:19:24.856674
2646 23:19:24.857163 Set Vref, RX VrefLevel [Byte0]: 47
2647 23:19:24.860125 [Byte1]: 47
2648 23:19:24.864889
2649 23:19:24.865347 Set Vref, RX VrefLevel [Byte0]: 48
2650 23:19:24.868784 [Byte1]: 48
2651 23:19:24.873197
2652 23:19:24.873891 Set Vref, RX VrefLevel [Byte0]: 49
2653 23:19:24.876207 [Byte1]: 49
2654 23:19:24.880848
2655 23:19:24.881475 Set Vref, RX VrefLevel [Byte0]: 50
2656 23:19:24.884385 [Byte1]: 50
2657 23:19:24.888516
2658 23:19:24.889078 Set Vref, RX VrefLevel [Byte0]: 51
2659 23:19:24.892047 [Byte1]: 51
2660 23:19:24.896549
2661 23:19:24.897215 Set Vref, RX VrefLevel [Byte0]: 52
2662 23:19:24.900507 [Byte1]: 52
2663 23:19:24.904757
2664 23:19:24.905309 Set Vref, RX VrefLevel [Byte0]: 53
2665 23:19:24.907681 [Byte1]: 53
2666 23:19:24.912042
2667 23:19:24.912501 Set Vref, RX VrefLevel [Byte0]: 54
2668 23:19:24.915969 [Byte1]: 54
2669 23:19:24.920271
2670 23:19:24.920796 Set Vref, RX VrefLevel [Byte0]: 55
2671 23:19:24.923679 [Byte1]: 55
2672 23:19:24.928259
2673 23:19:24.928863 Set Vref, RX VrefLevel [Byte0]: 56
2674 23:19:24.932040 [Byte1]: 56
2675 23:19:24.936413
2676 23:19:24.937012 Set Vref, RX VrefLevel [Byte0]: 57
2677 23:19:24.939677 [Byte1]: 57
2678 23:19:24.944496
2679 23:19:24.945096 Set Vref, RX VrefLevel [Byte0]: 58
2680 23:19:24.947654 [Byte1]: 58
2681 23:19:24.952763
2682 23:19:24.953322 Set Vref, RX VrefLevel [Byte0]: 59
2683 23:19:24.955258 [Byte1]: 59
2684 23:19:24.960285
2685 23:19:24.960882 Set Vref, RX VrefLevel [Byte0]: 60
2686 23:19:24.963412 [Byte1]: 60
2687 23:19:24.968513
2688 23:19:24.969099 Set Vref, RX VrefLevel [Byte0]: 61
2689 23:19:24.971473 [Byte1]: 61
2690 23:19:24.975549
2691 23:19:24.976188 Set Vref, RX VrefLevel [Byte0]: 62
2692 23:19:24.979093 [Byte1]: 62
2693 23:19:24.984233
2694 23:19:24.984827 Set Vref, RX VrefLevel [Byte0]: 63
2695 23:19:24.987524 [Byte1]: 63
2696 23:19:24.992211
2697 23:19:24.992799 Set Vref, RX VrefLevel [Byte0]: 64
2698 23:19:24.994785 [Byte1]: 64
2699 23:19:24.999785
2700 23:19:25.000247 Set Vref, RX VrefLevel [Byte0]: 65
2701 23:19:25.002927 [Byte1]: 65
2702 23:19:25.007659
2703 23:19:25.008230 Set Vref, RX VrefLevel [Byte0]: 66
2704 23:19:25.010762 [Byte1]: 66
2705 23:19:25.015293
2706 23:19:25.015849 Final RX Vref Byte 0 = 55 to rank0
2707 23:19:25.019236 Final RX Vref Byte 1 = 48 to rank0
2708 23:19:25.022592 Final RX Vref Byte 0 = 55 to rank1
2709 23:19:25.025670 Final RX Vref Byte 1 = 48 to rank1==
2710 23:19:25.029019 Dram Type= 6, Freq= 0, CH_0, rank 0
2711 23:19:25.035537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2712 23:19:25.036106 ==
2713 23:19:25.036475 DQS Delay:
2714 23:19:25.036871 DQS0 = 0, DQS1 = 0
2715 23:19:25.038671 DQM Delay:
2716 23:19:25.039239 DQM0 = 114, DQM1 = 105
2717 23:19:25.043307 DQ Delay:
2718 23:19:25.046146 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =110
2719 23:19:25.048842 DQ4 =118, DQ5 =106, DQ6 =122, DQ7 =120
2720 23:19:25.052510 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2721 23:19:25.055637 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2722 23:19:25.056193
2723 23:19:25.056557
2724 23:19:25.062088 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2725 23:19:25.065799 CH0 RK0: MR19=404, MR18=A0A
2726 23:19:25.072427 CH0_RK0: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
2727 23:19:25.073010
2728 23:19:25.076196 ----->DramcWriteLeveling(PI) begin...
2729 23:19:25.076811 ==
2730 23:19:25.078532 Dram Type= 6, Freq= 0, CH_0, rank 1
2731 23:19:25.082210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2732 23:19:25.082674 ==
2733 23:19:25.085396 Write leveling (Byte 0): 27 => 27
2734 23:19:25.089145 Write leveling (Byte 1): 26 => 26
2735 23:19:25.092363 DramcWriteLeveling(PI) end<-----
2736 23:19:25.092934
2737 23:19:25.093570 ==
2738 23:19:25.095127 Dram Type= 6, Freq= 0, CH_0, rank 1
2739 23:19:25.098889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2740 23:19:25.102025 ==
2741 23:19:25.102486 [Gating] SW mode calibration
2742 23:19:25.108770 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2743 23:19:25.115575 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2744 23:19:25.118936 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2745 23:19:25.125722 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2746 23:19:25.129215 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2747 23:19:25.131666 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2748 23:19:25.138855 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2749 23:19:25.141646 0 11 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2750 23:19:25.145178 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2751 23:19:25.152473 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2752 23:19:25.155480 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2753 23:19:25.159216 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2754 23:19:25.162543 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2755 23:19:25.169228 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2756 23:19:25.172526 0 12 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2757 23:19:25.175377 0 12 20 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
2758 23:19:25.182384 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2759 23:19:25.184987 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2760 23:19:25.188642 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2761 23:19:25.195780 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2762 23:19:25.198606 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2763 23:19:25.202082 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2764 23:19:25.208444 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2765 23:19:25.212115 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2766 23:19:25.214972 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2767 23:19:25.221653 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2768 23:19:25.225205 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2769 23:19:25.228974 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2770 23:19:25.235987 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2771 23:19:25.238438 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2772 23:19:25.241655 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 23:19:25.248439 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 23:19:25.251790 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 23:19:25.254802 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 23:19:25.262649 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 23:19:25.265079 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 23:19:25.268776 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 23:19:25.275162 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 23:19:25.278284 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2781 23:19:25.281847 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2782 23:19:25.286177 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2783 23:19:25.288553 Total UI for P1: 0, mck2ui 16
2784 23:19:25.292591 best dqsien dly found for B0: ( 0, 15, 18)
2785 23:19:25.295158 Total UI for P1: 0, mck2ui 16
2786 23:19:25.298329 best dqsien dly found for B1: ( 0, 15, 20)
2787 23:19:25.301916 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2788 23:19:25.308440 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2789 23:19:25.309009
2790 23:19:25.311728 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2791 23:19:25.314899 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2792 23:19:25.318858 [Gating] SW calibration Done
2793 23:19:25.319415 ==
2794 23:19:25.321840 Dram Type= 6, Freq= 0, CH_0, rank 1
2795 23:19:25.324815 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2796 23:19:25.325286 ==
2797 23:19:25.328287 RX Vref Scan: 0
2798 23:19:25.328779
2799 23:19:25.329152 RX Vref 0 -> 0, step: 1
2800 23:19:25.329493
2801 23:19:25.332270 RX Delay -40 -> 252, step: 8
2802 23:19:25.335497 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2803 23:19:25.338453 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2804 23:19:25.344969 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2805 23:19:25.348043 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2806 23:19:25.351668 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2807 23:19:25.354974 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2808 23:19:25.358567 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2809 23:19:25.364527 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2810 23:19:25.368475 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2811 23:19:25.371430 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2812 23:19:25.374580 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2813 23:19:25.378473 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2814 23:19:25.384504 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2815 23:19:25.388034 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2816 23:19:25.391385 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2817 23:19:25.394763 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2818 23:19:25.394921 ==
2819 23:19:25.397543 Dram Type= 6, Freq= 0, CH_0, rank 1
2820 23:19:25.404522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2821 23:19:25.404683 ==
2822 23:19:25.404828 DQS Delay:
2823 23:19:25.404945 DQS0 = 0, DQS1 = 0
2824 23:19:25.407492 DQM Delay:
2825 23:19:25.407648 DQM0 = 114, DQM1 = 107
2826 23:19:25.411031 DQ Delay:
2827 23:19:25.414236 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2828 23:19:25.417555 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2829 23:19:25.421303 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2830 23:19:25.424550 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2831 23:19:25.424773
2832 23:19:25.424901
2833 23:19:25.425016 ==
2834 23:19:25.428529 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 23:19:25.430865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2836 23:19:25.431024 ==
2837 23:19:25.431148
2838 23:19:25.434431
2839 23:19:25.434608 TX Vref Scan disable
2840 23:19:25.438351 == TX Byte 0 ==
2841 23:19:25.441798 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2842 23:19:25.444233 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2843 23:19:25.447826 == TX Byte 1 ==
2844 23:19:25.451442 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2845 23:19:25.454011 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2846 23:19:25.454167 ==
2847 23:19:25.458303 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 23:19:25.464065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2849 23:19:25.464224 ==
2850 23:19:25.474818 TX Vref=22, minBit 5, minWin=25, winSum=416
2851 23:19:25.478015 TX Vref=24, minBit 9, minWin=25, winSum=421
2852 23:19:25.481408 TX Vref=26, minBit 1, minWin=26, winSum=431
2853 23:19:25.484820 TX Vref=28, minBit 8, minWin=26, winSum=429
2854 23:19:25.488098 TX Vref=30, minBit 10, minWin=25, winSum=430
2855 23:19:25.496225 TX Vref=32, minBit 5, minWin=26, winSum=434
2856 23:19:25.498107 [TxChooseVref] Worse bit 5, Min win 26, Win sum 434, Final Vref 32
2857 23:19:25.498289
2858 23:19:25.501635 Final TX Range 1 Vref 32
2859 23:19:25.501848
2860 23:19:25.502015 ==
2861 23:19:25.504925 Dram Type= 6, Freq= 0, CH_0, rank 1
2862 23:19:25.508449 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2863 23:19:25.508732 ==
2864 23:19:25.511787
2865 23:19:25.512109
2866 23:19:25.512362 TX Vref Scan disable
2867 23:19:25.514864 == TX Byte 0 ==
2868 23:19:25.518105 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2869 23:19:25.521860 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2870 23:19:25.524864 == TX Byte 1 ==
2871 23:19:25.528153 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2872 23:19:25.531595 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2873 23:19:25.534945
2874 23:19:25.535402 [DATLAT]
2875 23:19:25.535769 Freq=1200, CH0 RK1
2876 23:19:25.536110
2877 23:19:25.538511 DATLAT Default: 0xc
2878 23:19:25.538980 0, 0xFFFF, sum = 0
2879 23:19:25.541555 1, 0xFFFF, sum = 0
2880 23:19:25.541992 2, 0xFFFF, sum = 0
2881 23:19:25.544969 3, 0xFFFF, sum = 0
2882 23:19:25.548775 4, 0xFFFF, sum = 0
2883 23:19:25.549197 5, 0xFFFF, sum = 0
2884 23:19:25.551756 6, 0xFFFF, sum = 0
2885 23:19:25.552174 7, 0xFFFF, sum = 0
2886 23:19:25.555179 8, 0xFFFF, sum = 0
2887 23:19:25.555598 9, 0xFFFF, sum = 0
2888 23:19:25.558776 10, 0xFFFF, sum = 0
2889 23:19:25.559298 11, 0x0, sum = 1
2890 23:19:25.561895 12, 0x0, sum = 2
2891 23:19:25.562314 13, 0x0, sum = 3
2892 23:19:25.562644 14, 0x0, sum = 4
2893 23:19:25.565096 best_step = 12
2894 23:19:25.565505
2895 23:19:25.565828 ==
2896 23:19:25.568404 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 23:19:25.571648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2898 23:19:25.572061 ==
2899 23:19:25.574854 RX Vref Scan: 0
2900 23:19:25.575498
2901 23:19:25.577872 RX Vref 0 -> 0, step: 1
2902 23:19:25.578282
2903 23:19:25.578605 RX Delay -21 -> 252, step: 4
2904 23:19:25.585933 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2905 23:19:25.588654 iDelay=199, Bit 1, Center 116 (47 ~ 186) 140
2906 23:19:25.592170 iDelay=199, Bit 2, Center 112 (43 ~ 182) 140
2907 23:19:25.595553 iDelay=199, Bit 3, Center 110 (39 ~ 182) 144
2908 23:19:25.598700 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2909 23:19:25.605804 iDelay=199, Bit 5, Center 106 (39 ~ 174) 136
2910 23:19:25.608513 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2911 23:19:25.612192 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2912 23:19:25.615051 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2913 23:19:25.618707 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2914 23:19:25.625529 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2915 23:19:25.628696 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2916 23:19:25.631950 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2917 23:19:25.635086 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2918 23:19:25.638730 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2919 23:19:25.645509 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2920 23:19:25.645931 ==
2921 23:19:25.648567 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 23:19:25.651987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2923 23:19:25.652473 ==
2924 23:19:25.652853 DQS Delay:
2925 23:19:25.655730 DQS0 = 0, DQS1 = 0
2926 23:19:25.656225 DQM Delay:
2927 23:19:25.658588 DQM0 = 114, DQM1 = 105
2928 23:19:25.659076 DQ Delay:
2929 23:19:25.661936 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =110
2930 23:19:25.665243 DQ4 =118, DQ5 =106, DQ6 =122, DQ7 =124
2931 23:19:25.669029 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2932 23:19:25.672193 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2933 23:19:25.672702
2934 23:19:25.673091
2935 23:19:25.682638 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2936 23:19:25.685219 CH0 RK1: MR19=404, MR18=E0E
2937 23:19:25.688507 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2938 23:19:25.692281 [RxdqsGatingPostProcess] freq 1200
2939 23:19:25.698834 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2940 23:19:25.701792 Pre-setting of DQS Precalculation
2941 23:19:25.705484 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2942 23:19:25.706153 ==
2943 23:19:25.708566 Dram Type= 6, Freq= 0, CH_1, rank 0
2944 23:19:25.716848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2945 23:19:25.717375 ==
2946 23:19:25.719154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2947 23:19:25.725791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2948 23:19:25.733576 [CA 0] Center 37 (7~68) winsize 62
2949 23:19:25.736837 [CA 1] Center 37 (7~68) winsize 62
2950 23:19:25.740275 [CA 2] Center 34 (4~65) winsize 62
2951 23:19:25.744122 [CA 3] Center 33 (3~64) winsize 62
2952 23:19:25.747566 [CA 4] Center 32 (1~63) winsize 63
2953 23:19:25.750416 [CA 5] Center 32 (2~63) winsize 62
2954 23:19:25.750879
2955 23:19:25.753556 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2956 23:19:25.754055
2957 23:19:25.757611 [CATrainingPosCal] consider 1 rank data
2958 23:19:25.760571 u2DelayCellTimex100 = 270/100 ps
2959 23:19:25.763988 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2960 23:19:25.767329 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2961 23:19:25.774273 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2962 23:19:25.777594 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2963 23:19:25.780274 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2964 23:19:25.784139 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2965 23:19:25.784953
2966 23:19:25.787791 CA PerBit enable=1, Macro0, CA PI delay=32
2967 23:19:25.788332
2968 23:19:25.790653 [CBTSetCACLKResult] CA Dly = 32
2969 23:19:25.791113 CS Dly: 5 (0~36)
2970 23:19:25.791474 ==
2971 23:19:25.794066 Dram Type= 6, Freq= 0, CH_1, rank 1
2972 23:19:25.801080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2973 23:19:25.801631 ==
2974 23:19:25.804787 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2975 23:19:25.810848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2976 23:19:25.819263 [CA 0] Center 37 (7~68) winsize 62
2977 23:19:25.822971 [CA 1] Center 37 (7~68) winsize 62
2978 23:19:25.825548 [CA 2] Center 34 (3~65) winsize 63
2979 23:19:25.829120 [CA 3] Center 33 (3~64) winsize 62
2980 23:19:25.832146 [CA 4] Center 32 (2~63) winsize 62
2981 23:19:25.835577 [CA 5] Center 32 (1~63) winsize 63
2982 23:19:25.836036
2983 23:19:25.839369 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2984 23:19:25.839938
2985 23:19:25.842559 [CATrainingPosCal] consider 2 rank data
2986 23:19:25.845928 u2DelayCellTimex100 = 270/100 ps
2987 23:19:25.849317 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2988 23:19:25.852304 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2989 23:19:25.859056 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2990 23:19:25.861985 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2991 23:19:25.865428 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2992 23:19:25.868832 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2993 23:19:25.869299
2994 23:19:25.872397 CA PerBit enable=1, Macro0, CA PI delay=32
2995 23:19:25.872910
2996 23:19:25.875556 [CBTSetCACLKResult] CA Dly = 32
2997 23:19:25.876024 CS Dly: 6 (0~38)
2998 23:19:25.876390
2999 23:19:25.882304 ----->DramcWriteLeveling(PI) begin...
3000 23:19:25.882836 ==
3001 23:19:25.885431 Dram Type= 6, Freq= 0, CH_1, rank 0
3002 23:19:25.888884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3003 23:19:25.889426 ==
3004 23:19:25.891922 Write leveling (Byte 0): 22 => 22
3005 23:19:25.895609 Write leveling (Byte 1): 22 => 22
3006 23:19:25.898475 DramcWriteLeveling(PI) end<-----
3007 23:19:25.899026
3008 23:19:25.899423 ==
3009 23:19:25.902472 Dram Type= 6, Freq= 0, CH_1, rank 0
3010 23:19:25.905622 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3011 23:19:25.906186 ==
3012 23:19:25.908866 [Gating] SW mode calibration
3013 23:19:25.916403 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3014 23:19:25.921615 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3015 23:19:25.924937 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3016 23:19:25.928077 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3017 23:19:25.934750 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3018 23:19:25.940097 0 11 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3019 23:19:25.941618 0 11 16 | B1->B0 | 3030 2626 | 1 1 | (1 1) (1 0)
3020 23:19:25.947838 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3021 23:19:25.951181 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3022 23:19:25.955059 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3023 23:19:25.961593 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3024 23:19:25.964620 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3025 23:19:25.968105 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3026 23:19:25.975573 0 12 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3027 23:19:25.978279 0 12 16 | B1->B0 | 3838 4444 | 0 1 | (1 1) (0 0)
3028 23:19:25.981712 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3029 23:19:25.987740 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3030 23:19:25.991079 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3031 23:19:25.994844 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3032 23:19:25.997968 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3033 23:19:26.004280 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3034 23:19:26.008155 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 23:19:26.011546 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3036 23:19:26.017609 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3037 23:19:26.021235 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3038 23:19:26.024686 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3039 23:19:26.031595 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3040 23:19:26.034674 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3041 23:19:26.037817 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3042 23:19:26.045242 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 23:19:26.048103 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 23:19:26.051577 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 23:19:26.057984 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 23:19:26.061532 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 23:19:26.064323 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 23:19:26.071815 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 23:19:26.074592 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 23:19:26.077424 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 23:19:26.084088 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3052 23:19:26.088169 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3053 23:19:26.091481 Total UI for P1: 0, mck2ui 16
3054 23:19:26.094368 best dqsien dly found for B0: ( 0, 15, 16)
3055 23:19:26.097721 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3056 23:19:26.100826 Total UI for P1: 0, mck2ui 16
3057 23:19:26.103953 best dqsien dly found for B1: ( 0, 15, 20)
3058 23:19:26.107536 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3059 23:19:26.111511 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3060 23:19:26.112055
3061 23:19:26.118058 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3062 23:19:26.121206 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3063 23:19:26.121709 [Gating] SW calibration Done
3064 23:19:26.124286 ==
3065 23:19:26.124744 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 23:19:26.131406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3067 23:19:26.131913 ==
3068 23:19:26.132341 RX Vref Scan: 0
3069 23:19:26.132660
3070 23:19:26.134528 RX Vref 0 -> 0, step: 1
3071 23:19:26.135142
3072 23:19:26.137508 RX Delay -40 -> 252, step: 8
3073 23:19:26.141171 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3074 23:19:26.144060 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3075 23:19:26.147771 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3076 23:19:26.154157 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3077 23:19:26.157960 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3078 23:19:26.161488 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3079 23:19:26.165482 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3080 23:19:26.167727 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3081 23:19:26.174548 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3082 23:19:26.177761 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3083 23:19:26.180846 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3084 23:19:26.184153 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3085 23:19:26.188264 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3086 23:19:26.194245 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3087 23:19:26.197995 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3088 23:19:26.200807 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3089 23:19:26.201395 ==
3090 23:19:26.204225 Dram Type= 6, Freq= 0, CH_1, rank 0
3091 23:19:26.207753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3092 23:19:26.208267 ==
3093 23:19:26.211131 DQS Delay:
3094 23:19:26.211650 DQS0 = 0, DQS1 = 0
3095 23:19:26.214704 DQM Delay:
3096 23:19:26.215335 DQM0 = 116, DQM1 = 109
3097 23:19:26.215680 DQ Delay:
3098 23:19:26.217499 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3099 23:19:26.224426 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3100 23:19:26.227950 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =103
3101 23:19:26.230949 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3102 23:19:26.231464
3103 23:19:26.231796
3104 23:19:26.232100 ==
3105 23:19:26.234133 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 23:19:26.237837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3107 23:19:26.238404 ==
3108 23:19:26.238747
3109 23:19:26.239057
3110 23:19:26.241183 TX Vref Scan disable
3111 23:19:26.241647 == TX Byte 0 ==
3112 23:19:26.247707 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3113 23:19:26.251103 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3114 23:19:26.251639 == TX Byte 1 ==
3115 23:19:26.258028 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3116 23:19:26.261019 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3117 23:19:26.261446 ==
3118 23:19:26.264058 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 23:19:26.268065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3120 23:19:26.268487 ==
3121 23:19:26.280365 TX Vref=22, minBit 0, minWin=25, winSum=415
3122 23:19:26.283366 TX Vref=24, minBit 9, minWin=25, winSum=422
3123 23:19:26.287165 TX Vref=26, minBit 10, minWin=25, winSum=427
3124 23:19:26.290650 TX Vref=28, minBit 1, minWin=26, winSum=432
3125 23:19:26.293830 TX Vref=30, minBit 0, minWin=26, winSum=431
3126 23:19:26.297162 TX Vref=32, minBit 8, minWin=26, winSum=430
3127 23:19:26.303950 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 28
3128 23:19:26.304499
3129 23:19:26.306762 Final TX Range 1 Vref 28
3130 23:19:26.307256
3131 23:19:26.307703 ==
3132 23:19:26.310334 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 23:19:26.314942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3134 23:19:26.315458 ==
3135 23:19:26.315790
3136 23:19:26.317464
3137 23:19:26.317878 TX Vref Scan disable
3138 23:19:26.320451 == TX Byte 0 ==
3139 23:19:26.323920 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3140 23:19:26.327244 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3141 23:19:26.330666 == TX Byte 1 ==
3142 23:19:26.333379 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3143 23:19:26.336795 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3144 23:19:26.337307
3145 23:19:26.340465 [DATLAT]
3146 23:19:26.340997 Freq=1200, CH1 RK0
3147 23:19:26.341336
3148 23:19:26.343919 DATLAT Default: 0xd
3149 23:19:26.344435 0, 0xFFFF, sum = 0
3150 23:19:26.346969 1, 0xFFFF, sum = 0
3151 23:19:26.347392 2, 0xFFFF, sum = 0
3152 23:19:26.350258 3, 0xFFFF, sum = 0
3153 23:19:26.350683 4, 0xFFFF, sum = 0
3154 23:19:26.353483 5, 0xFFFF, sum = 0
3155 23:19:26.353908 6, 0xFFFF, sum = 0
3156 23:19:26.356671 7, 0xFFFF, sum = 0
3157 23:19:26.357150 8, 0xFFFF, sum = 0
3158 23:19:26.360204 9, 0xFFFF, sum = 0
3159 23:19:26.363313 10, 0xFFFF, sum = 0
3160 23:19:26.363739 11, 0x0, sum = 1
3161 23:19:26.364074 12, 0x0, sum = 2
3162 23:19:26.367039 13, 0x0, sum = 3
3163 23:19:26.367468 14, 0x0, sum = 4
3164 23:19:26.370466 best_step = 12
3165 23:19:26.370883
3166 23:19:26.371209 ==
3167 23:19:26.373545 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 23:19:26.376872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3169 23:19:26.377382 ==
3170 23:19:26.380239 RX Vref Scan: 1
3171 23:19:26.380654
3172 23:19:26.381018 Set Vref Range= 32 -> 127
3173 23:19:26.381324
3174 23:19:26.384230 RX Vref 32 -> 127, step: 1
3175 23:19:26.384649
3176 23:19:26.387383 RX Delay -29 -> 252, step: 4
3177 23:19:26.387800
3178 23:19:26.390497 Set Vref, RX VrefLevel [Byte0]: 32
3179 23:19:26.394017 [Byte1]: 32
3180 23:19:26.394436
3181 23:19:26.396765 Set Vref, RX VrefLevel [Byte0]: 33
3182 23:19:26.400447 [Byte1]: 33
3183 23:19:26.404808
3184 23:19:26.405335 Set Vref, RX VrefLevel [Byte0]: 34
3185 23:19:26.408883 [Byte1]: 34
3186 23:19:26.412856
3187 23:19:26.413346 Set Vref, RX VrefLevel [Byte0]: 35
3188 23:19:26.415990 [Byte1]: 35
3189 23:19:26.420841
3190 23:19:26.421359 Set Vref, RX VrefLevel [Byte0]: 36
3191 23:19:26.423900 [Byte1]: 36
3192 23:19:26.429093
3193 23:19:26.429643 Set Vref, RX VrefLevel [Byte0]: 37
3194 23:19:26.432293 [Byte1]: 37
3195 23:19:26.436511
3196 23:19:26.437125 Set Vref, RX VrefLevel [Byte0]: 38
3197 23:19:26.439863 [Byte1]: 38
3198 23:19:26.444389
3199 23:19:26.444968 Set Vref, RX VrefLevel [Byte0]: 39
3200 23:19:26.447776 [Byte1]: 39
3201 23:19:26.452837
3202 23:19:26.453454 Set Vref, RX VrefLevel [Byte0]: 40
3203 23:19:26.455662 [Byte1]: 40
3204 23:19:26.460973
3205 23:19:26.461506 Set Vref, RX VrefLevel [Byte0]: 41
3206 23:19:26.463942 [Byte1]: 41
3207 23:19:26.468149
3208 23:19:26.468606 Set Vref, RX VrefLevel [Byte0]: 42
3209 23:19:26.471858 [Byte1]: 42
3210 23:19:26.476551
3211 23:19:26.477090 Set Vref, RX VrefLevel [Byte0]: 43
3212 23:19:26.479695 [Byte1]: 43
3213 23:19:26.484685
3214 23:19:26.485303 Set Vref, RX VrefLevel [Byte0]: 44
3215 23:19:26.487982 [Byte1]: 44
3216 23:19:26.492164
3217 23:19:26.492836 Set Vref, RX VrefLevel [Byte0]: 45
3218 23:19:26.495733 [Byte1]: 45
3219 23:19:26.500599
3220 23:19:26.501306 Set Vref, RX VrefLevel [Byte0]: 46
3221 23:19:26.503501 [Byte1]: 46
3222 23:19:26.508068
3223 23:19:26.508613 Set Vref, RX VrefLevel [Byte0]: 47
3224 23:19:26.511183 [Byte1]: 47
3225 23:19:26.516316
3226 23:19:26.516924 Set Vref, RX VrefLevel [Byte0]: 48
3227 23:19:26.519454 [Byte1]: 48
3228 23:19:26.524203
3229 23:19:26.524805 Set Vref, RX VrefLevel [Byte0]: 49
3230 23:19:26.528052 [Byte1]: 49
3231 23:19:26.532290
3232 23:19:26.532888 Set Vref, RX VrefLevel [Byte0]: 50
3233 23:19:26.535453 [Byte1]: 50
3234 23:19:26.540399
3235 23:19:26.540999 Set Vref, RX VrefLevel [Byte0]: 51
3236 23:19:26.543338 [Byte1]: 51
3237 23:19:26.548309
3238 23:19:26.548885 Set Vref, RX VrefLevel [Byte0]: 52
3239 23:19:26.551599 [Byte1]: 52
3240 23:19:26.555965
3241 23:19:26.556519 Set Vref, RX VrefLevel [Byte0]: 53
3242 23:19:26.559561 [Byte1]: 53
3243 23:19:26.563832
3244 23:19:26.564288 Set Vref, RX VrefLevel [Byte0]: 54
3245 23:19:26.567187 [Byte1]: 54
3246 23:19:26.571642
3247 23:19:26.572193 Set Vref, RX VrefLevel [Byte0]: 55
3248 23:19:26.575473 [Byte1]: 55
3249 23:19:26.579656
3250 23:19:26.580116 Set Vref, RX VrefLevel [Byte0]: 56
3251 23:19:26.584256 [Byte1]: 56
3252 23:19:26.587672
3253 23:19:26.588147 Set Vref, RX VrefLevel [Byte0]: 57
3254 23:19:26.590998 [Byte1]: 57
3255 23:19:26.595552
3256 23:19:26.596009 Set Vref, RX VrefLevel [Byte0]: 58
3257 23:19:26.598901 [Byte1]: 58
3258 23:19:26.603338
3259 23:19:26.603946 Set Vref, RX VrefLevel [Byte0]: 59
3260 23:19:26.607121 [Byte1]: 59
3261 23:19:26.612109
3262 23:19:26.612662 Set Vref, RX VrefLevel [Byte0]: 60
3263 23:19:26.614881 [Byte1]: 60
3264 23:19:26.619924
3265 23:19:26.620483 Set Vref, RX VrefLevel [Byte0]: 61
3266 23:19:26.623102 [Byte1]: 61
3267 23:19:26.628477
3268 23:19:26.629040 Set Vref, RX VrefLevel [Byte0]: 62
3269 23:19:26.630960 [Byte1]: 62
3270 23:19:26.635597
3271 23:19:26.636154 Set Vref, RX VrefLevel [Byte0]: 63
3272 23:19:26.638743 [Byte1]: 63
3273 23:19:26.643517
3274 23:19:26.644081 Set Vref, RX VrefLevel [Byte0]: 64
3275 23:19:26.646992 [Byte1]: 64
3276 23:19:26.651128
3277 23:19:26.651590 Final RX Vref Byte 0 = 54 to rank0
3278 23:19:26.654803 Final RX Vref Byte 1 = 49 to rank0
3279 23:19:26.658302 Final RX Vref Byte 0 = 54 to rank1
3280 23:19:26.661541 Final RX Vref Byte 1 = 49 to rank1==
3281 23:19:26.664749 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 23:19:26.668084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3283 23:19:26.671547 ==
3284 23:19:26.672008 DQS Delay:
3285 23:19:26.672367 DQS0 = 0, DQS1 = 0
3286 23:19:26.674834 DQM Delay:
3287 23:19:26.675397 DQM0 = 115, DQM1 = 105
3288 23:19:26.678041 DQ Delay:
3289 23:19:26.681018 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3290 23:19:26.684853 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3291 23:19:26.688108 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3292 23:19:26.692017 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =114
3293 23:19:26.692591
3294 23:19:26.693123
3295 23:19:26.697533 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
3296 23:19:26.701381 CH1 RK0: MR19=404, MR18=1313
3297 23:19:26.707610 CH1_RK0: MR19=0x404, MR18=0x1313, DQSOSC=402, MR23=63, INC=40, DEC=27
3298 23:19:26.708140
3299 23:19:26.711436 ----->DramcWriteLeveling(PI) begin...
3300 23:19:26.712002 ==
3301 23:19:26.714637 Dram Type= 6, Freq= 0, CH_1, rank 1
3302 23:19:26.718175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3303 23:19:26.718741 ==
3304 23:19:26.721477 Write leveling (Byte 0): 22 => 22
3305 23:19:26.724945 Write leveling (Byte 1): 22 => 22
3306 23:19:26.728124 DramcWriteLeveling(PI) end<-----
3307 23:19:26.728683
3308 23:19:26.729145 ==
3309 23:19:26.731726 Dram Type= 6, Freq= 0, CH_1, rank 1
3310 23:19:26.738342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3311 23:19:26.738906 ==
3312 23:19:26.739278 [Gating] SW mode calibration
3313 23:19:26.748319 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3314 23:19:26.751462 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3315 23:19:26.754942 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3316 23:19:26.761707 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3317 23:19:26.764612 0 11 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3318 23:19:26.768329 0 11 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
3319 23:19:26.775310 0 11 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
3320 23:19:26.778491 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3321 23:19:26.781696 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3322 23:19:26.788240 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3323 23:19:26.791285 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3324 23:19:26.794620 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3325 23:19:26.801055 0 12 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3326 23:19:26.804423 0 12 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
3327 23:19:26.807505 0 12 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
3328 23:19:26.814594 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3329 23:19:26.817952 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3330 23:19:26.821553 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3331 23:19:26.827854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3332 23:19:26.831429 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3333 23:19:26.834572 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3334 23:19:26.841361 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3335 23:19:26.844907 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3336 23:19:26.847913 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3337 23:19:26.851426 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3338 23:19:26.857980 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3339 23:19:26.860689 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3340 23:19:26.864837 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3341 23:19:26.871581 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3342 23:19:26.874665 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3343 23:19:26.878223 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3344 23:19:26.885085 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3345 23:19:26.888097 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3346 23:19:26.891026 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3347 23:19:26.898522 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3348 23:19:26.901222 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 23:19:26.904143 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 23:19:26.911261 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3351 23:19:26.913843 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3352 23:19:26.917898 Total UI for P1: 0, mck2ui 16
3353 23:19:26.920687 best dqsien dly found for B0: ( 0, 15, 12)
3354 23:19:26.923892 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3355 23:19:26.927224 Total UI for P1: 0, mck2ui 16
3356 23:19:26.930884 best dqsien dly found for B1: ( 0, 15, 14)
3357 23:19:26.934339 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3358 23:19:26.937242 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3359 23:19:26.937706
3360 23:19:26.943838 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3361 23:19:26.948295 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3362 23:19:26.950856 [Gating] SW calibration Done
3363 23:19:26.951313 ==
3364 23:19:26.953934 Dram Type= 6, Freq= 0, CH_1, rank 1
3365 23:19:26.957336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3366 23:19:26.957790 ==
3367 23:19:26.958140 RX Vref Scan: 0
3368 23:19:26.958467
3369 23:19:26.960515 RX Vref 0 -> 0, step: 1
3370 23:19:26.961081
3371 23:19:26.963929 RX Delay -40 -> 252, step: 8
3372 23:19:26.967180 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3373 23:19:26.970499 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3374 23:19:26.977133 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3375 23:19:26.980316 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3376 23:19:26.983636 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3377 23:19:26.986952 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3378 23:19:26.991189 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3379 23:19:26.993671 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3380 23:19:27.000966 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3381 23:19:27.003833 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3382 23:19:27.007463 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3383 23:19:27.010583 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3384 23:19:27.014413 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3385 23:19:27.021537 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3386 23:19:27.023931 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3387 23:19:27.027196 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3388 23:19:27.027712 ==
3389 23:19:27.030850 Dram Type= 6, Freq= 0, CH_1, rank 1
3390 23:19:27.034548 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3391 23:19:27.035071 ==
3392 23:19:27.037673 DQS Delay:
3393 23:19:27.038118 DQS0 = 0, DQS1 = 0
3394 23:19:27.040687 DQM Delay:
3395 23:19:27.041147 DQM0 = 115, DQM1 = 106
3396 23:19:27.041479 DQ Delay:
3397 23:19:27.046999 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3398 23:19:27.050874 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3399 23:19:27.054343 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
3400 23:19:27.057989 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3401 23:19:27.058509
3402 23:19:27.058841
3403 23:19:27.059148 ==
3404 23:19:27.060323 Dram Type= 6, Freq= 0, CH_1, rank 1
3405 23:19:27.064794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3406 23:19:27.065304 ==
3407 23:19:27.065636
3408 23:19:27.065937
3409 23:19:27.067357 TX Vref Scan disable
3410 23:19:27.067774 == TX Byte 0 ==
3411 23:19:27.074751 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3412 23:19:27.077129 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3413 23:19:27.081395 == TX Byte 1 ==
3414 23:19:27.083926 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3415 23:19:27.087531 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3416 23:19:27.088056 ==
3417 23:19:27.090440 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 23:19:27.094463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3419 23:19:27.095048 ==
3420 23:19:27.107182 TX Vref=22, minBit 11, minWin=25, winSum=423
3421 23:19:27.110454 TX Vref=24, minBit 0, minWin=26, winSum=423
3422 23:19:27.113352 TX Vref=26, minBit 9, minWin=25, winSum=428
3423 23:19:27.117129 TX Vref=28, minBit 8, minWin=26, winSum=433
3424 23:19:27.121417 TX Vref=30, minBit 9, minWin=26, winSum=433
3425 23:19:27.123974 TX Vref=32, minBit 0, minWin=26, winSum=428
3426 23:19:27.130448 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 28
3427 23:19:27.130977
3428 23:19:27.133737 Final TX Range 1 Vref 28
3429 23:19:27.134272
3430 23:19:27.134610 ==
3431 23:19:27.136865 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 23:19:27.140588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3433 23:19:27.141176 ==
3434 23:19:27.143992
3435 23:19:27.144519
3436 23:19:27.144912 TX Vref Scan disable
3437 23:19:27.147156 == TX Byte 0 ==
3438 23:19:27.150178 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3439 23:19:27.153595 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3440 23:19:27.156775 == TX Byte 1 ==
3441 23:19:27.160179 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3442 23:19:27.163291 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3443 23:19:27.163818
3444 23:19:27.166598 [DATLAT]
3445 23:19:27.167020 Freq=1200, CH1 RK1
3446 23:19:27.167355
3447 23:19:27.170005 DATLAT Default: 0xc
3448 23:19:27.170424 0, 0xFFFF, sum = 0
3449 23:19:27.173440 1, 0xFFFF, sum = 0
3450 23:19:27.173868 2, 0xFFFF, sum = 0
3451 23:19:27.176458 3, 0xFFFF, sum = 0
3452 23:19:27.176939 4, 0xFFFF, sum = 0
3453 23:19:27.180544 5, 0xFFFF, sum = 0
3454 23:19:27.181022 6, 0xFFFF, sum = 0
3455 23:19:27.183484 7, 0xFFFF, sum = 0
3456 23:19:27.186849 8, 0xFFFF, sum = 0
3457 23:19:27.187277 9, 0xFFFF, sum = 0
3458 23:19:27.190415 10, 0xFFFF, sum = 0
3459 23:19:27.190962 11, 0x0, sum = 1
3460 23:19:27.191306 12, 0x0, sum = 2
3461 23:19:27.193884 13, 0x0, sum = 3
3462 23:19:27.194314 14, 0x0, sum = 4
3463 23:19:27.197099 best_step = 12
3464 23:19:27.197532
3465 23:19:27.197861 ==
3466 23:19:27.199916 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 23:19:27.203376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3468 23:19:27.203887 ==
3469 23:19:27.206782 RX Vref Scan: 0
3470 23:19:27.207201
3471 23:19:27.207532 RX Vref 0 -> 0, step: 1
3472 23:19:27.207840
3473 23:19:27.210189 RX Delay -29 -> 252, step: 4
3474 23:19:27.217579 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3475 23:19:27.220423 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3476 23:19:27.224034 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3477 23:19:27.228394 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3478 23:19:27.230181 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3479 23:19:27.237570 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3480 23:19:27.240690 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3481 23:19:27.244113 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3482 23:19:27.247173 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3483 23:19:27.250401 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3484 23:19:27.256762 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3485 23:19:27.260538 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3486 23:19:27.263562 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3487 23:19:27.267407 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3488 23:19:27.270805 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3489 23:19:27.277212 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3490 23:19:27.277644 ==
3491 23:19:27.280581 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 23:19:27.283851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3493 23:19:27.284615 ==
3494 23:19:27.285367 DQS Delay:
3495 23:19:27.286892 DQS0 = 0, DQS1 = 0
3496 23:19:27.287492 DQM Delay:
3497 23:19:27.290114 DQM0 = 114, DQM1 = 103
3498 23:19:27.290533 DQ Delay:
3499 23:19:27.293266 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =112
3500 23:19:27.296874 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3501 23:19:27.300914 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3502 23:19:27.303956 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =110
3503 23:19:27.304549
3504 23:19:27.305091
3505 23:19:27.314215 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3506 23:19:27.317256 CH1 RK1: MR19=404, MR18=D0D
3507 23:19:27.320809 CH1_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3508 23:19:27.323651 [RxdqsGatingPostProcess] freq 1200
3509 23:19:27.330854 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3510 23:19:27.334224 Pre-setting of DQS Precalculation
3511 23:19:27.337119 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3512 23:19:27.346663 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3513 23:19:27.353670 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3514 23:19:27.354164
3515 23:19:27.354499
3516 23:19:27.357102 [Calibration Summary] 2400 Mbps
3517 23:19:27.357524 CH 0, Rank 0
3518 23:19:27.360816 SW Impedance : PASS
3519 23:19:27.361241 DUTY Scan : NO K
3520 23:19:27.363417 ZQ Calibration : PASS
3521 23:19:27.367123 Jitter Meter : NO K
3522 23:19:27.367721 CBT Training : PASS
3523 23:19:27.370999 Write leveling : PASS
3524 23:19:27.373684 RX DQS gating : PASS
3525 23:19:27.374110 RX DQ/DQS(RDDQC) : PASS
3526 23:19:27.377075 TX DQ/DQS : PASS
3527 23:19:27.377499 RX DATLAT : PASS
3528 23:19:27.380184 RX DQ/DQS(Engine): PASS
3529 23:19:27.383771 TX OE : NO K
3530 23:19:27.384193 All Pass.
3531 23:19:27.384522
3532 23:19:27.384873 CH 0, Rank 1
3533 23:19:27.386762 SW Impedance : PASS
3534 23:19:27.390575 DUTY Scan : NO K
3535 23:19:27.391102 ZQ Calibration : PASS
3536 23:19:27.393690 Jitter Meter : NO K
3537 23:19:27.396835 CBT Training : PASS
3538 23:19:27.397348 Write leveling : PASS
3539 23:19:27.400258 RX DQS gating : PASS
3540 23:19:27.403851 RX DQ/DQS(RDDQC) : PASS
3541 23:19:27.404495 TX DQ/DQS : PASS
3542 23:19:27.407159 RX DATLAT : PASS
3543 23:19:27.410812 RX DQ/DQS(Engine): PASS
3544 23:19:27.411539 TX OE : NO K
3545 23:19:27.413790 All Pass.
3546 23:19:27.414252
3547 23:19:27.414758 CH 1, Rank 0
3548 23:19:27.416658 SW Impedance : PASS
3549 23:19:27.417222 DUTY Scan : NO K
3550 23:19:27.421118 ZQ Calibration : PASS
3551 23:19:27.423605 Jitter Meter : NO K
3552 23:19:27.424165 CBT Training : PASS
3553 23:19:27.427174 Write leveling : PASS
3554 23:19:27.427917 RX DQS gating : PASS
3555 23:19:27.430586 RX DQ/DQS(RDDQC) : PASS
3556 23:19:27.433698 TX DQ/DQS : PASS
3557 23:19:27.434244 RX DATLAT : PASS
3558 23:19:27.436793 RX DQ/DQS(Engine): PASS
3559 23:19:27.440346 TX OE : NO K
3560 23:19:27.440950 All Pass.
3561 23:19:27.441322
3562 23:19:27.441666 CH 1, Rank 1
3563 23:19:27.443503 SW Impedance : PASS
3564 23:19:27.446894 DUTY Scan : NO K
3565 23:19:27.447356 ZQ Calibration : PASS
3566 23:19:27.449943 Jitter Meter : NO K
3567 23:19:27.453361 CBT Training : PASS
3568 23:19:27.453846 Write leveling : PASS
3569 23:19:27.457081 RX DQS gating : PASS
3570 23:19:27.460535 RX DQ/DQS(RDDQC) : PASS
3571 23:19:27.461119 TX DQ/DQS : PASS
3572 23:19:27.463591 RX DATLAT : PASS
3573 23:19:27.466770 RX DQ/DQS(Engine): PASS
3574 23:19:27.467335 TX OE : NO K
3575 23:19:27.469935 All Pass.
3576 23:19:27.470493
3577 23:19:27.470855 DramC Write-DBI off
3578 23:19:27.473620 PER_BANK_REFRESH: Hybrid Mode
3579 23:19:27.474076 TX_TRACKING: ON
3580 23:19:27.483373 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3581 23:19:27.487223 [FAST_K] Save calibration result to emmc
3582 23:19:27.490109 dramc_set_vcore_voltage set vcore to 650000
3583 23:19:27.493505 Read voltage for 600, 5
3584 23:19:27.494197 Vio18 = 0
3585 23:19:27.496843 Vcore = 650000
3586 23:19:27.497307 Vdram = 0
3587 23:19:27.497690 Vddq = 0
3588 23:19:27.498031 Vmddr = 0
3589 23:19:27.502965 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3590 23:19:27.509764 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3591 23:19:27.510230 MEM_TYPE=3, freq_sel=19
3592 23:19:27.513280 sv_algorithm_assistance_LP4_1600
3593 23:19:27.517137 ============ PULL DRAM RESETB DOWN ============
3594 23:19:27.523487 ========== PULL DRAM RESETB DOWN end =========
3595 23:19:27.526693 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3596 23:19:27.530691 ===================================
3597 23:19:27.533359 LPDDR4 DRAM CONFIGURATION
3598 23:19:27.537073 ===================================
3599 23:19:27.537622 EX_ROW_EN[0] = 0x0
3600 23:19:27.540137 EX_ROW_EN[1] = 0x0
3601 23:19:27.540695 LP4Y_EN = 0x0
3602 23:19:27.543093 WORK_FSP = 0x0
3603 23:19:27.543608 WL = 0x2
3604 23:19:27.546988 RL = 0x2
3605 23:19:27.547529 BL = 0x2
3606 23:19:27.550040 RPST = 0x0
3607 23:19:27.552958 RD_PRE = 0x0
3608 23:19:27.553505 WR_PRE = 0x1
3609 23:19:27.556742 WR_PST = 0x0
3610 23:19:27.557214 DBI_WR = 0x0
3611 23:19:27.559577 DBI_RD = 0x0
3612 23:19:27.560033 OTF = 0x1
3613 23:19:27.563363 ===================================
3614 23:19:27.566376 ===================================
3615 23:19:27.566833 ANA top config
3616 23:19:27.569583 ===================================
3617 23:19:27.572852 DLL_ASYNC_EN = 0
3618 23:19:27.576350 ALL_SLAVE_EN = 1
3619 23:19:27.579616 NEW_RANK_MODE = 1
3620 23:19:27.582742 DLL_IDLE_MODE = 1
3621 23:19:27.583293 LP45_APHY_COMB_EN = 1
3622 23:19:27.586866 TX_ODT_DIS = 1
3623 23:19:27.590068 NEW_8X_MODE = 1
3624 23:19:27.592556 ===================================
3625 23:19:27.596116 ===================================
3626 23:19:27.599685 data_rate = 1200
3627 23:19:27.602971 CKR = 1
3628 23:19:27.603504 DQ_P2S_RATIO = 8
3629 23:19:27.605930 ===================================
3630 23:19:27.609347 CA_P2S_RATIO = 8
3631 23:19:27.612525 DQ_CA_OPEN = 0
3632 23:19:27.615809 DQ_SEMI_OPEN = 0
3633 23:19:27.619951 CA_SEMI_OPEN = 0
3634 23:19:27.623247 CA_FULL_RATE = 0
3635 23:19:27.623824 DQ_CKDIV4_EN = 1
3636 23:19:27.626024 CA_CKDIV4_EN = 1
3637 23:19:27.630208 CA_PREDIV_EN = 0
3638 23:19:27.632801 PH8_DLY = 0
3639 23:19:27.636223 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3640 23:19:27.639575 DQ_AAMCK_DIV = 4
3641 23:19:27.640133 CA_AAMCK_DIV = 4
3642 23:19:27.643133 CA_ADMCK_DIV = 4
3643 23:19:27.646214 DQ_TRACK_CA_EN = 0
3644 23:19:27.648924 CA_PICK = 600
3645 23:19:27.653022 CA_MCKIO = 600
3646 23:19:27.655662 MCKIO_SEMI = 0
3647 23:19:27.659007 PLL_FREQ = 2288
3648 23:19:27.662383 DQ_UI_PI_RATIO = 32
3649 23:19:27.662945 CA_UI_PI_RATIO = 0
3650 23:19:27.665866 ===================================
3651 23:19:27.668632 ===================================
3652 23:19:27.672268 memory_type:LPDDR4
3653 23:19:27.676037 GP_NUM : 10
3654 23:19:27.676491 SRAM_EN : 1
3655 23:19:27.679581 MD32_EN : 0
3656 23:19:27.681947 ===================================
3657 23:19:27.685927 [ANA_INIT] >>>>>>>>>>>>>>
3658 23:19:27.688813 <<<<<< [CONFIGURE PHASE]: ANA_TX
3659 23:19:27.692104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3660 23:19:27.694997 ===================================
3661 23:19:27.695488 data_rate = 1200,PCW = 0X5800
3662 23:19:27.699239 ===================================
3663 23:19:27.702003 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3664 23:19:27.708501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3665 23:19:27.714928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3666 23:19:27.718849 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3667 23:19:27.721728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3668 23:19:27.725423 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3669 23:19:27.728577 [ANA_INIT] flow start
3670 23:19:27.731610 [ANA_INIT] PLL >>>>>>>>
3671 23:19:27.732138 [ANA_INIT] PLL <<<<<<<<
3672 23:19:27.735434 [ANA_INIT] MIDPI >>>>>>>>
3673 23:19:27.739338 [ANA_INIT] MIDPI <<<<<<<<
3674 23:19:27.739988 [ANA_INIT] DLL >>>>>>>>
3675 23:19:27.742542 [ANA_INIT] flow end
3676 23:19:27.745036 ============ LP4 DIFF to SE enter ============
3677 23:19:27.748166 ============ LP4 DIFF to SE exit ============
3678 23:19:27.751537 [ANA_INIT] <<<<<<<<<<<<<
3679 23:19:27.755071 [Flow] Enable top DCM control >>>>>
3680 23:19:27.758454 [Flow] Enable top DCM control <<<<<
3681 23:19:27.761969 Enable DLL master slave shuffle
3682 23:19:27.768479 ==============================================================
3683 23:19:27.769007 Gating Mode config
3684 23:19:27.774885 ==============================================================
3685 23:19:27.775410 Config description:
3686 23:19:27.784755 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3687 23:19:27.792278 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3688 23:19:27.797828 SELPH_MODE 0: By rank 1: By Phase
3689 23:19:27.801232 ==============================================================
3690 23:19:27.804207 GAT_TRACK_EN = 1
3691 23:19:27.807996 RX_GATING_MODE = 2
3692 23:19:27.811959 RX_GATING_TRACK_MODE = 2
3693 23:19:27.814280 SELPH_MODE = 1
3694 23:19:27.817742 PICG_EARLY_EN = 1
3695 23:19:27.821375 VALID_LAT_VALUE = 1
3696 23:19:27.827462 ==============================================================
3697 23:19:27.831297 Enter into Gating configuration >>>>
3698 23:19:27.834575 Exit from Gating configuration <<<<
3699 23:19:27.838006 Enter into DVFS_PRE_config >>>>>
3700 23:19:27.848831 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3701 23:19:27.851065 Exit from DVFS_PRE_config <<<<<
3702 23:19:27.854069 Enter into PICG configuration >>>>
3703 23:19:27.857668 Exit from PICG configuration <<<<
3704 23:19:27.860444 [RX_INPUT] configuration >>>>>
3705 23:19:27.860958 [RX_INPUT] configuration <<<<<
3706 23:19:27.867079 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3707 23:19:27.874147 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3708 23:19:27.880867 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3709 23:19:27.883486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3710 23:19:27.890654 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3711 23:19:27.897257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3712 23:19:27.900455 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3713 23:19:27.904009 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3714 23:19:27.910162 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3715 23:19:27.913794 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3716 23:19:27.916873 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3717 23:19:27.923729 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3718 23:19:27.926835 ===================================
3719 23:19:27.927395 LPDDR4 DRAM CONFIGURATION
3720 23:19:27.930443 ===================================
3721 23:19:27.933772 EX_ROW_EN[0] = 0x0
3722 23:19:27.937495 EX_ROW_EN[1] = 0x0
3723 23:19:27.938057 LP4Y_EN = 0x0
3724 23:19:27.940073 WORK_FSP = 0x0
3725 23:19:27.940536 WL = 0x2
3726 23:19:27.943646 RL = 0x2
3727 23:19:27.944208 BL = 0x2
3728 23:19:27.947135 RPST = 0x0
3729 23:19:27.947697 RD_PRE = 0x0
3730 23:19:27.950404 WR_PRE = 0x1
3731 23:19:27.950974 WR_PST = 0x0
3732 23:19:27.953317 DBI_WR = 0x0
3733 23:19:27.954041 DBI_RD = 0x0
3734 23:19:27.957062 OTF = 0x1
3735 23:19:27.959702 ===================================
3736 23:19:27.964174 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3737 23:19:27.966577 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3738 23:19:27.974171 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3739 23:19:27.976804 ===================================
3740 23:19:27.977408 LPDDR4 DRAM CONFIGURATION
3741 23:19:27.979865 ===================================
3742 23:19:27.983384 EX_ROW_EN[0] = 0x10
3743 23:19:27.986669 EX_ROW_EN[1] = 0x0
3744 23:19:27.987145 LP4Y_EN = 0x0
3745 23:19:27.989871 WORK_FSP = 0x0
3746 23:19:27.990493 WL = 0x2
3747 23:19:27.992850 RL = 0x2
3748 23:19:27.993314 BL = 0x2
3749 23:19:27.996475 RPST = 0x0
3750 23:19:27.997017 RD_PRE = 0x0
3751 23:19:27.999404 WR_PRE = 0x1
3752 23:19:27.999904 WR_PST = 0x0
3753 23:19:28.003144 DBI_WR = 0x0
3754 23:19:28.003608 DBI_RD = 0x0
3755 23:19:28.006743 OTF = 0x1
3756 23:19:28.010620 ===================================
3757 23:19:28.016386 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3758 23:19:28.019733 nWR fixed to 30
3759 23:19:28.020281 [ModeRegInit_LP4] CH0 RK0
3760 23:19:28.022604 [ModeRegInit_LP4] CH0 RK1
3761 23:19:28.026382 [ModeRegInit_LP4] CH1 RK0
3762 23:19:28.030521 [ModeRegInit_LP4] CH1 RK1
3763 23:19:28.031078 match AC timing 16
3764 23:19:28.036585 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3765 23:19:28.040206 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3766 23:19:28.043115 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3767 23:19:28.049380 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3768 23:19:28.053178 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3769 23:19:28.053708 ==
3770 23:19:28.056240 Dram Type= 6, Freq= 0, CH_0, rank 0
3771 23:19:28.059807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3772 23:19:28.060378 ==
3773 23:19:28.065736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3774 23:19:28.073697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3775 23:19:28.075753 [CA 0] Center 35 (5~66) winsize 62
3776 23:19:28.079322 [CA 1] Center 35 (5~66) winsize 62
3777 23:19:28.082917 [CA 2] Center 34 (4~65) winsize 62
3778 23:19:28.086158 [CA 3] Center 34 (3~65) winsize 63
3779 23:19:28.089196 [CA 4] Center 33 (3~64) winsize 62
3780 23:19:28.092246 [CA 5] Center 33 (3~64) winsize 62
3781 23:19:28.092754
3782 23:19:28.095749 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3783 23:19:28.096229
3784 23:19:28.098991 [CATrainingPosCal] consider 1 rank data
3785 23:19:28.102752 u2DelayCellTimex100 = 270/100 ps
3786 23:19:28.106015 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3787 23:19:28.109333 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3788 23:19:28.112952 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3789 23:19:28.115717 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3790 23:19:28.119226 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3791 23:19:28.121998 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3792 23:19:28.122481
3793 23:19:28.128563 CA PerBit enable=1, Macro0, CA PI delay=33
3794 23:19:28.129173
3795 23:19:28.129661 [CBTSetCACLKResult] CA Dly = 33
3796 23:19:28.132821 CS Dly: 5 (0~36)
3797 23:19:28.133366 ==
3798 23:19:28.135758 Dram Type= 6, Freq= 0, CH_0, rank 1
3799 23:19:28.139026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3800 23:19:28.139602 ==
3801 23:19:28.145946 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3802 23:19:28.152440 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3803 23:19:28.155522 [CA 0] Center 35 (5~66) winsize 62
3804 23:19:28.158555 [CA 1] Center 35 (5~66) winsize 62
3805 23:19:28.161697 [CA 2] Center 34 (4~65) winsize 62
3806 23:19:28.165604 [CA 3] Center 34 (4~65) winsize 62
3807 23:19:28.168498 [CA 4] Center 33 (3~64) winsize 62
3808 23:19:28.172000 [CA 5] Center 33 (3~64) winsize 62
3809 23:19:28.172582
3810 23:19:28.175408 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3811 23:19:28.175884
3812 23:19:28.178578 [CATrainingPosCal] consider 2 rank data
3813 23:19:28.181981 u2DelayCellTimex100 = 270/100 ps
3814 23:19:28.184994 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3815 23:19:28.188757 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3816 23:19:28.192203 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3817 23:19:28.195139 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3818 23:19:28.198629 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3819 23:19:28.205030 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3820 23:19:28.205572
3821 23:19:28.207942 CA PerBit enable=1, Macro0, CA PI delay=33
3822 23:19:28.208406
3823 23:19:28.211623 [CBTSetCACLKResult] CA Dly = 33
3824 23:19:28.212186 CS Dly: 5 (0~36)
3825 23:19:28.212556
3826 23:19:28.215008 ----->DramcWriteLeveling(PI) begin...
3827 23:19:28.215480 ==
3828 23:19:28.217983 Dram Type= 6, Freq= 0, CH_0, rank 0
3829 23:19:28.224622 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3830 23:19:28.225210 ==
3831 23:19:28.227914 Write leveling (Byte 0): 31 => 31
3832 23:19:28.228391 Write leveling (Byte 1): 29 => 29
3833 23:19:28.231512 DramcWriteLeveling(PI) end<-----
3834 23:19:28.232069
3835 23:19:28.232437 ==
3836 23:19:28.235330 Dram Type= 6, Freq= 0, CH_0, rank 0
3837 23:19:28.241495 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3838 23:19:28.242070 ==
3839 23:19:28.244973 [Gating] SW mode calibration
3840 23:19:28.251671 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3841 23:19:28.255307 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3842 23:19:28.261230 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3843 23:19:28.264845 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3844 23:19:28.267770 0 5 8 | B1->B0 | 3131 2f2f | 1 1 | (1 1) (1 0)
3845 23:19:28.274611 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3846 23:19:28.278117 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3847 23:19:28.281430 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3848 23:19:28.288245 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3849 23:19:28.291481 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3850 23:19:28.294628 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3851 23:19:28.300829 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3852 23:19:28.304823 0 6 8 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (1 1)
3853 23:19:28.308313 0 6 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
3854 23:19:28.311318 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3855 23:19:28.317776 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3856 23:19:28.320986 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3857 23:19:28.324541 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3858 23:19:28.330958 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3859 23:19:28.334325 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3860 23:19:28.338063 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3861 23:19:28.343914 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3862 23:19:28.348045 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3863 23:19:28.350709 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3864 23:19:28.357241 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3865 23:19:28.361498 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3866 23:19:28.364501 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3867 23:19:28.371009 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3868 23:19:28.374191 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3869 23:19:28.377834 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3870 23:19:28.384393 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3871 23:19:28.387727 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3872 23:19:28.390758 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 23:19:28.397274 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 23:19:28.400286 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 23:19:28.404085 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 23:19:28.409834 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3877 23:19:28.413579 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3878 23:19:28.416693 Total UI for P1: 0, mck2ui 16
3879 23:19:28.420159 best dqsien dly found for B0: ( 0, 9, 8)
3880 23:19:28.423415 Total UI for P1: 0, mck2ui 16
3881 23:19:28.427323 best dqsien dly found for B1: ( 0, 9, 8)
3882 23:19:28.430130 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3883 23:19:28.433421 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3884 23:19:28.433901
3885 23:19:28.436139 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3886 23:19:28.439944 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3887 23:19:28.443248 [Gating] SW calibration Done
3888 23:19:28.443835 ==
3889 23:19:28.446615 Dram Type= 6, Freq= 0, CH_0, rank 0
3890 23:19:28.453496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3891 23:19:28.453981 ==
3892 23:19:28.454470 RX Vref Scan: 0
3893 23:19:28.454929
3894 23:19:28.456647 RX Vref 0 -> 0, step: 1
3895 23:19:28.457166
3896 23:19:28.459453 RX Delay -230 -> 252, step: 16
3897 23:19:28.462697 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
3898 23:19:28.466412 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3899 23:19:28.469730 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3900 23:19:28.476076 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
3901 23:19:28.480862 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3902 23:19:28.482879 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
3903 23:19:28.486393 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3904 23:19:28.493359 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3905 23:19:28.495969 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3906 23:19:28.499480 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3907 23:19:28.502377 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
3908 23:19:28.508883 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3909 23:19:28.512551 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3910 23:19:28.516050 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3911 23:19:28.519231 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3912 23:19:28.523198 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3913 23:19:28.525873 ==
3914 23:19:28.529258 Dram Type= 6, Freq= 0, CH_0, rank 0
3915 23:19:28.532436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3916 23:19:28.532971 ==
3917 23:19:28.533337 DQS Delay:
3918 23:19:28.536456 DQS0 = 0, DQS1 = 0
3919 23:19:28.537089 DQM Delay:
3920 23:19:28.539480 DQM0 = 43, DQM1 = 34
3921 23:19:28.540084 DQ Delay:
3922 23:19:28.542593 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
3923 23:19:28.545545 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3924 23:19:28.549213 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
3925 23:19:28.552269 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3926 23:19:28.552766
3927 23:19:28.553137
3928 23:19:28.553470 ==
3929 23:19:28.555666 Dram Type= 6, Freq= 0, CH_0, rank 0
3930 23:19:28.559005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3931 23:19:28.559467 ==
3932 23:19:28.560108
3933 23:19:28.560474
3934 23:19:28.562058 TX Vref Scan disable
3935 23:19:28.565590 == TX Byte 0 ==
3936 23:19:28.568879 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3937 23:19:28.572539 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3938 23:19:28.575690 == TX Byte 1 ==
3939 23:19:28.579230 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3940 23:19:28.581934 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3941 23:19:28.582462 ==
3942 23:19:28.584931 Dram Type= 6, Freq= 0, CH_0, rank 0
3943 23:19:28.592386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3944 23:19:28.593014 ==
3945 23:19:28.593383
3946 23:19:28.593719
3947 23:19:28.594035 TX Vref Scan disable
3948 23:19:28.596484 == TX Byte 0 ==
3949 23:19:28.599705 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3950 23:19:28.605982 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3951 23:19:28.606455 == TX Byte 1 ==
3952 23:19:28.609887 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3953 23:19:28.616060 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3954 23:19:28.616583
3955 23:19:28.617035 [DATLAT]
3956 23:19:28.617379 Freq=600, CH0 RK0
3957 23:19:28.617706
3958 23:19:28.619494 DATLAT Default: 0x9
3959 23:19:28.620046 0, 0xFFFF, sum = 0
3960 23:19:28.622894 1, 0xFFFF, sum = 0
3961 23:19:28.626331 2, 0xFFFF, sum = 0
3962 23:19:28.626793 3, 0xFFFF, sum = 0
3963 23:19:28.629590 4, 0xFFFF, sum = 0
3964 23:19:28.630055 5, 0xFFFF, sum = 0
3965 23:19:28.632392 6, 0xFFFF, sum = 0
3966 23:19:28.632979 7, 0x0, sum = 1
3967 23:19:28.636201 8, 0x0, sum = 2
3968 23:19:28.636822 9, 0x0, sum = 3
3969 23:19:28.637200 10, 0x0, sum = 4
3970 23:19:28.639670 best_step = 8
3971 23:19:28.640128
3972 23:19:28.640484 ==
3973 23:19:28.642554 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 23:19:28.645715 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3975 23:19:28.646177 ==
3976 23:19:28.649523 RX Vref Scan: 1
3977 23:19:28.650099
3978 23:19:28.650461 RX Vref 0 -> 0, step: 1
3979 23:19:28.650793
3980 23:19:28.653210 RX Delay -195 -> 252, step: 8
3981 23:19:28.653829
3982 23:19:28.655833 Set Vref, RX VrefLevel [Byte0]: 55
3983 23:19:28.659308 [Byte1]: 48
3984 23:19:28.663055
3985 23:19:28.663515 Final RX Vref Byte 0 = 55 to rank0
3986 23:19:28.667137 Final RX Vref Byte 1 = 48 to rank0
3987 23:19:28.669752 Final RX Vref Byte 0 = 55 to rank1
3988 23:19:28.674241 Final RX Vref Byte 1 = 48 to rank1==
3989 23:19:28.676622 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 23:19:28.683180 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3991 23:19:28.683780 ==
3992 23:19:28.684171 DQS Delay:
3993 23:19:28.686966 DQS0 = 0, DQS1 = 0
3994 23:19:28.687513 DQM Delay:
3995 23:19:28.687872 DQM0 = 39, DQM1 = 30
3996 23:19:28.689952 DQ Delay:
3997 23:19:28.692997 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3998 23:19:28.696886 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
3999 23:19:28.699608 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =24
4000 23:19:28.702970 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4001 23:19:28.703620
4002 23:19:28.703992
4003 23:19:28.709872 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4004 23:19:28.713643 CH0 RK0: MR19=808, MR18=5C5C
4005 23:19:28.720095 CH0_RK0: MR19=0x808, MR18=0x5C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4006 23:19:28.720656
4007 23:19:28.722918 ----->DramcWriteLeveling(PI) begin...
4008 23:19:28.723476 ==
4009 23:19:28.726622 Dram Type= 6, Freq= 0, CH_0, rank 1
4010 23:19:28.729908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4011 23:19:28.730474 ==
4012 23:19:28.732861 Write leveling (Byte 0): 31 => 31
4013 23:19:28.736678 Write leveling (Byte 1): 28 => 28
4014 23:19:28.739714 DramcWriteLeveling(PI) end<-----
4015 23:19:28.740263
4016 23:19:28.740623 ==
4017 23:19:28.742917 Dram Type= 6, Freq= 0, CH_0, rank 1
4018 23:19:28.745942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4019 23:19:28.746540 ==
4020 23:19:28.749381 [Gating] SW mode calibration
4021 23:19:28.756514 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4022 23:19:28.763148 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4023 23:19:28.766277 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 23:19:28.772925 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 23:19:28.775903 0 5 8 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 0)
4026 23:19:28.780294 0 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4027 23:19:28.785915 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 23:19:28.789373 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 23:19:28.792174 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 23:19:28.799053 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 23:19:28.802510 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 23:19:28.806118 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 23:19:28.812298 0 6 8 | B1->B0 | 2e2e 3333 | 0 1 | (0 0) (0 0)
4034 23:19:28.816379 0 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4035 23:19:28.818759 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 23:19:28.825990 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 23:19:28.828880 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 23:19:28.833340 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 23:19:28.839303 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 23:19:28.842835 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 23:19:28.845645 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4042 23:19:28.851969 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4043 23:19:28.855976 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 23:19:28.859395 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 23:19:28.861895 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 23:19:28.869133 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 23:19:28.871979 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 23:19:28.875189 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 23:19:28.882063 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 23:19:28.885549 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 23:19:28.888759 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 23:19:28.895762 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 23:19:28.898366 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 23:19:28.901689 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 23:19:28.908181 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 23:19:28.911895 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 23:19:28.914836 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4058 23:19:28.918793 Total UI for P1: 0, mck2ui 16
4059 23:19:28.921508 best dqsien dly found for B0: ( 0, 9, 6)
4060 23:19:28.928290 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4061 23:19:28.931788 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 23:19:28.935064 Total UI for P1: 0, mck2ui 16
4063 23:19:28.938388 best dqsien dly found for B1: ( 0, 9, 12)
4064 23:19:28.941801 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4065 23:19:28.945705 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
4066 23:19:28.946265
4067 23:19:28.948120 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4068 23:19:28.951853 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
4069 23:19:28.955189 [Gating] SW calibration Done
4070 23:19:28.955750 ==
4071 23:19:28.958345 Dram Type= 6, Freq= 0, CH_0, rank 1
4072 23:19:28.964562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4073 23:19:28.965194 ==
4074 23:19:28.965563 RX Vref Scan: 0
4075 23:19:28.965903
4076 23:19:28.968045 RX Vref 0 -> 0, step: 1
4077 23:19:28.968663
4078 23:19:28.970894 RX Delay -230 -> 252, step: 16
4079 23:19:28.974887 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4080 23:19:28.977703 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4081 23:19:28.980883 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4082 23:19:28.988285 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4083 23:19:28.991236 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4084 23:19:28.994528 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4085 23:19:28.997769 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4086 23:19:29.004759 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4087 23:19:29.007337 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4088 23:19:29.011222 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4089 23:19:29.014134 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4090 23:19:29.017334 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4091 23:19:29.023903 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4092 23:19:29.027191 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4093 23:19:29.030571 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4094 23:19:29.033963 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4095 23:19:29.037563 ==
4096 23:19:29.041307 Dram Type= 6, Freq= 0, CH_0, rank 1
4097 23:19:29.043626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4098 23:19:29.044188 ==
4099 23:19:29.044549 DQS Delay:
4100 23:19:29.047524 DQS0 = 0, DQS1 = 0
4101 23:19:29.048080 DQM Delay:
4102 23:19:29.050543 DQM0 = 40, DQM1 = 31
4103 23:19:29.051099 DQ Delay:
4104 23:19:29.053751 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4105 23:19:29.057713 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4106 23:19:29.060373 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4107 23:19:29.063172 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4108 23:19:29.063748
4109 23:19:29.064117
4110 23:19:29.064529 ==
4111 23:19:29.066707 Dram Type= 6, Freq= 0, CH_0, rank 1
4112 23:19:29.070500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4113 23:19:29.070959 ==
4114 23:19:29.071318
4115 23:19:29.071648
4116 23:19:29.073517 TX Vref Scan disable
4117 23:19:29.077407 == TX Byte 0 ==
4118 23:19:29.080610 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4119 23:19:29.083591 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4120 23:19:29.086842 == TX Byte 1 ==
4121 23:19:29.090507 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4122 23:19:29.093529 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4123 23:19:29.093993 ==
4124 23:19:29.097152 Dram Type= 6, Freq= 0, CH_0, rank 1
4125 23:19:29.103340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4126 23:19:29.103908 ==
4127 23:19:29.104272
4128 23:19:29.104692
4129 23:19:29.105069 TX Vref Scan disable
4130 23:19:29.107312 == TX Byte 0 ==
4131 23:19:29.111231 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4132 23:19:29.117795 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4133 23:19:29.118341 == TX Byte 1 ==
4134 23:19:29.120879 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4135 23:19:29.127642 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4136 23:19:29.128208
4137 23:19:29.128575 [DATLAT]
4138 23:19:29.129030 Freq=600, CH0 RK1
4139 23:19:29.129386
4140 23:19:29.131041 DATLAT Default: 0x8
4141 23:19:29.131500 0, 0xFFFF, sum = 0
4142 23:19:29.134413 1, 0xFFFF, sum = 0
4143 23:19:29.137718 2, 0xFFFF, sum = 0
4144 23:19:29.138286 3, 0xFFFF, sum = 0
4145 23:19:29.142048 4, 0xFFFF, sum = 0
4146 23:19:29.142615 5, 0xFFFF, sum = 0
4147 23:19:29.143659 6, 0xFFFF, sum = 0
4148 23:19:29.144124 7, 0x0, sum = 1
4149 23:19:29.147479 8, 0x0, sum = 2
4150 23:19:29.148051 9, 0x0, sum = 3
4151 23:19:29.148422 10, 0x0, sum = 4
4152 23:19:29.151193 best_step = 8
4153 23:19:29.151753
4154 23:19:29.152114 ==
4155 23:19:29.153573 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 23:19:29.157167 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4157 23:19:29.157731 ==
4158 23:19:29.161075 RX Vref Scan: 0
4159 23:19:29.161641
4160 23:19:29.162008 RX Vref 0 -> 0, step: 1
4161 23:19:29.162344
4162 23:19:29.163658 RX Delay -195 -> 252, step: 8
4163 23:19:29.171989 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4164 23:19:29.174788 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4165 23:19:29.178023 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4166 23:19:29.181107 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4167 23:19:29.187983 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4168 23:19:29.191626 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4169 23:19:29.194881 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4170 23:19:29.198217 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4171 23:19:29.200861 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4172 23:19:29.207900 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4173 23:19:29.211144 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4174 23:19:29.214625 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4175 23:19:29.218432 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4176 23:19:29.224111 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4177 23:19:29.227492 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4178 23:19:29.231655 iDelay=205, Bit 15, Center 40 (-107 ~ 188) 296
4179 23:19:29.232229 ==
4180 23:19:29.234835 Dram Type= 6, Freq= 0, CH_0, rank 1
4181 23:19:29.241495 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4182 23:19:29.242077 ==
4183 23:19:29.242448 DQS Delay:
4184 23:19:29.242783 DQS0 = 0, DQS1 = 0
4185 23:19:29.244809 DQM Delay:
4186 23:19:29.245270 DQM0 = 41, DQM1 = 32
4187 23:19:29.247879 DQ Delay:
4188 23:19:29.250827 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4189 23:19:29.254150 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4190 23:19:29.254718 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =24
4191 23:19:29.261249 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4192 23:19:29.261811
4193 23:19:29.262172
4194 23:19:29.268390 [DQSOSCAuto] RK1, (LSB)MR18= 0x6767, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4195 23:19:29.271235 CH0 RK1: MR19=808, MR18=6767
4196 23:19:29.277715 CH0_RK1: MR19=0x808, MR18=0x6767, DQSOSC=390, MR23=63, INC=172, DEC=114
4197 23:19:29.280583 [RxdqsGatingPostProcess] freq 600
4198 23:19:29.284312 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4199 23:19:29.287729 Pre-setting of DQS Precalculation
4200 23:19:29.294569 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4201 23:19:29.295127 ==
4202 23:19:29.297153 Dram Type= 6, Freq= 0, CH_1, rank 0
4203 23:19:29.300839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4204 23:19:29.301301 ==
4205 23:19:29.307003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4206 23:19:29.310624 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4207 23:19:29.314914 [CA 0] Center 35 (5~66) winsize 62
4208 23:19:29.318525 [CA 1] Center 35 (4~66) winsize 63
4209 23:19:29.321801 [CA 2] Center 33 (3~64) winsize 62
4210 23:19:29.324587 [CA 3] Center 33 (3~64) winsize 62
4211 23:19:29.328228 [CA 4] Center 33 (2~64) winsize 63
4212 23:19:29.332209 [CA 5] Center 32 (2~63) winsize 62
4213 23:19:29.332674
4214 23:19:29.334634 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4215 23:19:29.335097
4216 23:19:29.338294 [CATrainingPosCal] consider 1 rank data
4217 23:19:29.341489 u2DelayCellTimex100 = 270/100 ps
4218 23:19:29.345409 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4219 23:19:29.351201 CA1 delay=35 (4~66),Diff = 3 PI (28 cell)
4220 23:19:29.355426 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4221 23:19:29.357919 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4222 23:19:29.361224 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4223 23:19:29.364157 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4224 23:19:29.364617
4225 23:19:29.368494 CA PerBit enable=1, Macro0, CA PI delay=32
4226 23:19:29.369109
4227 23:19:29.371464 [CBTSetCACLKResult] CA Dly = 32
4228 23:19:29.375156 CS Dly: 4 (0~35)
4229 23:19:29.375709 ==
4230 23:19:29.378374 Dram Type= 6, Freq= 0, CH_1, rank 1
4231 23:19:29.380855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4232 23:19:29.381321 ==
4233 23:19:29.387362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4234 23:19:29.391137 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4235 23:19:29.395450 [CA 0] Center 35 (5~65) winsize 61
4236 23:19:29.398040 [CA 1] Center 34 (4~65) winsize 62
4237 23:19:29.401315 [CA 2] Center 33 (3~64) winsize 62
4238 23:19:29.405376 [CA 3] Center 33 (3~64) winsize 62
4239 23:19:29.408332 [CA 4] Center 32 (2~63) winsize 62
4240 23:19:29.411461 [CA 5] Center 32 (2~63) winsize 62
4241 23:19:29.412148
4242 23:19:29.415317 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4243 23:19:29.415776
4244 23:19:29.418324 [CATrainingPosCal] consider 2 rank data
4245 23:19:29.422260 u2DelayCellTimex100 = 270/100 ps
4246 23:19:29.424990 CA0 delay=35 (5~65),Diff = 3 PI (28 cell)
4247 23:19:29.428419 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4248 23:19:29.434540 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4249 23:19:29.437844 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4250 23:19:29.441218 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4251 23:19:29.444617 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4252 23:19:29.445255
4253 23:19:29.447855 CA PerBit enable=1, Macro0, CA PI delay=32
4254 23:19:29.448291
4255 23:19:29.451665 [CBTSetCACLKResult] CA Dly = 32
4256 23:19:29.452092 CS Dly: 5 (0~37)
4257 23:19:29.454801
4258 23:19:29.457915 ----->DramcWriteLeveling(PI) begin...
4259 23:19:29.458337 ==
4260 23:19:29.461548 Dram Type= 6, Freq= 0, CH_1, rank 0
4261 23:19:29.464441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4262 23:19:29.465024 ==
4263 23:19:29.467861 Write leveling (Byte 0): 29 => 29
4264 23:19:29.471240 Write leveling (Byte 1): 26 => 26
4265 23:19:29.474543 DramcWriteLeveling(PI) end<-----
4266 23:19:29.475060
4267 23:19:29.475390 ==
4268 23:19:29.477616 Dram Type= 6, Freq= 0, CH_1, rank 0
4269 23:19:29.480827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4270 23:19:29.481252 ==
4271 23:19:29.485185 [Gating] SW mode calibration
4272 23:19:29.491349 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4273 23:19:29.497910 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4274 23:19:29.500991 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4275 23:19:29.505069 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (0 0) (1 0)
4276 23:19:29.510986 0 5 8 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (0 0)
4277 23:19:29.514957 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4278 23:19:29.517374 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4279 23:19:29.525062 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4280 23:19:29.527721 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 23:19:29.531152 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 23:19:29.537512 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 23:19:29.540753 0 6 4 | B1->B0 | 2525 3131 | 0 1 | (0 0) (0 0)
4284 23:19:29.543839 0 6 8 | B1->B0 | 3737 4545 | 1 0 | (0 0) (0 0)
4285 23:19:29.550599 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 23:19:29.553613 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 23:19:29.557466 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4288 23:19:29.564197 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 23:19:29.567409 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 23:19:29.570304 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 23:19:29.573476 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4292 23:19:29.580319 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 23:19:29.583944 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 23:19:29.587252 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 23:19:29.593903 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 23:19:29.597356 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 23:19:29.600109 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 23:19:29.607105 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 23:19:29.610187 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 23:19:29.613462 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 23:19:29.620131 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 23:19:29.624052 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 23:19:29.626961 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 23:19:29.633604 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 23:19:29.636946 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 23:19:29.640450 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 23:19:29.647008 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4308 23:19:29.650672 Total UI for P1: 0, mck2ui 16
4309 23:19:29.653196 best dqsien dly found for B0: ( 0, 9, 2)
4310 23:19:29.656681 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4311 23:19:29.659713 Total UI for P1: 0, mck2ui 16
4312 23:19:29.663171 best dqsien dly found for B1: ( 0, 9, 6)
4313 23:19:29.666207 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4314 23:19:29.669475 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4315 23:19:29.670008
4316 23:19:29.673106 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4317 23:19:29.676903 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4318 23:19:29.680147 [Gating] SW calibration Done
4319 23:19:29.680606 ==
4320 23:19:29.683903 Dram Type= 6, Freq= 0, CH_1, rank 0
4321 23:19:29.686685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4322 23:19:29.689222 ==
4323 23:19:29.689685 RX Vref Scan: 0
4324 23:19:29.690142
4325 23:19:29.693097 RX Vref 0 -> 0, step: 1
4326 23:19:29.693557
4327 23:19:29.696274 RX Delay -230 -> 252, step: 16
4328 23:19:29.699994 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4329 23:19:29.702917 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4330 23:19:29.706428 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4331 23:19:29.712844 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4332 23:19:29.716673 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4333 23:19:29.719705 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4334 23:19:29.723070 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4335 23:19:29.725550 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4336 23:19:29.732306 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4337 23:19:29.736030 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4338 23:19:29.739737 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4339 23:19:29.742756 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4340 23:19:29.749392 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4341 23:19:29.752984 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4342 23:19:29.756977 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4343 23:19:29.758696 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4344 23:19:29.762578 ==
4345 23:19:29.763133 Dram Type= 6, Freq= 0, CH_1, rank 0
4346 23:19:29.769279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4347 23:19:29.769743 ==
4348 23:19:29.770105 DQS Delay:
4349 23:19:29.771792 DQS0 = 0, DQS1 = 0
4350 23:19:29.772252 DQM Delay:
4351 23:19:29.775465 DQM0 = 39, DQM1 = 31
4352 23:19:29.776016 DQ Delay:
4353 23:19:29.778871 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4354 23:19:29.782107 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4355 23:19:29.785417 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4356 23:19:29.788833 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =41
4357 23:19:29.789294
4358 23:19:29.789653
4359 23:19:29.789986 ==
4360 23:19:29.791861 Dram Type= 6, Freq= 0, CH_1, rank 0
4361 23:19:29.795095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4362 23:19:29.795514 ==
4363 23:19:29.795839
4364 23:19:29.796188
4365 23:19:29.798678 TX Vref Scan disable
4366 23:19:29.802359 == TX Byte 0 ==
4367 23:19:29.805751 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4368 23:19:29.809219 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4369 23:19:29.812172 == TX Byte 1 ==
4370 23:19:29.815610 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4371 23:19:29.818623 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4372 23:19:29.819077 ==
4373 23:19:29.821531 Dram Type= 6, Freq= 0, CH_1, rank 0
4374 23:19:29.828528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4375 23:19:29.829079 ==
4376 23:19:29.829409
4377 23:19:29.829709
4378 23:19:29.829992 TX Vref Scan disable
4379 23:19:29.833042 == TX Byte 0 ==
4380 23:19:29.836243 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4381 23:19:29.842772 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4382 23:19:29.843300 == TX Byte 1 ==
4383 23:19:29.846407 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4384 23:19:29.853397 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4385 23:19:29.853958
4386 23:19:29.854318 [DATLAT]
4387 23:19:29.854649 Freq=600, CH1 RK0
4388 23:19:29.854966
4389 23:19:29.856081 DATLAT Default: 0x9
4390 23:19:29.856535 0, 0xFFFF, sum = 0
4391 23:19:29.859600 1, 0xFFFF, sum = 0
4392 23:19:29.860165 2, 0xFFFF, sum = 0
4393 23:19:29.863085 3, 0xFFFF, sum = 0
4394 23:19:29.866068 4, 0xFFFF, sum = 0
4395 23:19:29.866530 5, 0xFFFF, sum = 0
4396 23:19:29.869825 6, 0xFFFF, sum = 0
4397 23:19:29.870340 7, 0x0, sum = 1
4398 23:19:29.870721 8, 0x0, sum = 2
4399 23:19:29.872777 9, 0x0, sum = 3
4400 23:19:29.873264 10, 0x0, sum = 4
4401 23:19:29.876428 best_step = 8
4402 23:19:29.877032
4403 23:19:29.877392 ==
4404 23:19:29.879503 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 23:19:29.882626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4406 23:19:29.883184 ==
4407 23:19:29.885965 RX Vref Scan: 1
4408 23:19:29.886419
4409 23:19:29.886776 RX Vref 0 -> 0, step: 1
4410 23:19:29.887110
4411 23:19:29.889116 RX Delay -195 -> 252, step: 8
4412 23:19:29.889571
4413 23:19:29.892380 Set Vref, RX VrefLevel [Byte0]: 54
4414 23:19:29.895795 [Byte1]: 49
4415 23:19:29.900089
4416 23:19:29.900886 Final RX Vref Byte 0 = 54 to rank0
4417 23:19:29.903310 Final RX Vref Byte 1 = 49 to rank0
4418 23:19:29.906458 Final RX Vref Byte 0 = 54 to rank1
4419 23:19:29.909896 Final RX Vref Byte 1 = 49 to rank1==
4420 23:19:29.912781 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 23:19:29.919415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4422 23:19:29.919974 ==
4423 23:19:29.920334 DQS Delay:
4424 23:19:29.923155 DQS0 = 0, DQS1 = 0
4425 23:19:29.923717 DQM Delay:
4426 23:19:29.924079 DQM0 = 38, DQM1 = 30
4427 23:19:29.925877 DQ Delay:
4428 23:19:29.929188 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4429 23:19:29.933127 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4430 23:19:29.936635 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4431 23:19:29.939931 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4432 23:19:29.940488
4433 23:19:29.941066
4434 23:19:29.946491 [DQSOSCAuto] RK0, (LSB)MR18= 0x7272, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4435 23:19:29.949761 CH1 RK0: MR19=808, MR18=7272
4436 23:19:29.956491 CH1_RK0: MR19=0x808, MR18=0x7272, DQSOSC=388, MR23=63, INC=174, DEC=116
4437 23:19:29.957110
4438 23:19:29.959469 ----->DramcWriteLeveling(PI) begin...
4439 23:19:29.960035 ==
4440 23:19:29.962833 Dram Type= 6, Freq= 0, CH_1, rank 1
4441 23:19:29.965869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4442 23:19:29.966329 ==
4443 23:19:29.968847 Write leveling (Byte 0): 28 => 28
4444 23:19:29.972490 Write leveling (Byte 1): 28 => 28
4445 23:19:29.976056 DramcWriteLeveling(PI) end<-----
4446 23:19:29.976622
4447 23:19:29.977054 ==
4448 23:19:29.979091 Dram Type= 6, Freq= 0, CH_1, rank 1
4449 23:19:29.982035 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4450 23:19:29.986023 ==
4451 23:19:29.986581 [Gating] SW mode calibration
4452 23:19:29.995478 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4453 23:19:29.998491 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4454 23:19:30.002373 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4455 23:19:30.008642 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 1)
4456 23:19:30.011583 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4457 23:19:30.015485 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 23:19:30.022275 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 23:19:30.025491 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 23:19:30.028922 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 23:19:30.035604 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 23:19:30.039067 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 23:19:30.041399 0 6 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4464 23:19:30.048136 0 6 8 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
4465 23:19:30.051770 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 23:19:30.055752 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 23:19:30.061577 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 23:19:30.064897 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 23:19:30.069086 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 23:19:30.075319 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 23:19:30.077982 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4472 23:19:30.082192 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 23:19:30.087868 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 23:19:30.091271 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 23:19:30.095200 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 23:19:30.101064 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 23:19:30.104625 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 23:19:30.107843 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 23:19:30.114185 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 23:19:30.117628 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 23:19:30.121087 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 23:19:30.127111 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 23:19:30.130851 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 23:19:30.133749 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 23:19:30.140383 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 23:19:30.143723 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 23:19:30.147616 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4488 23:19:30.150209 Total UI for P1: 0, mck2ui 16
4489 23:19:30.153980 best dqsien dly found for B0: ( 0, 9, 2)
4490 23:19:30.160229 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 23:19:30.160831 Total UI for P1: 0, mck2ui 16
4492 23:19:30.166801 best dqsien dly found for B1: ( 0, 9, 4)
4493 23:19:30.170739 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4494 23:19:30.174272 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4495 23:19:30.174834
4496 23:19:30.176903 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4497 23:19:30.180953 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4498 23:19:30.183337 [Gating] SW calibration Done
4499 23:19:30.183931 ==
4500 23:19:30.188081 Dram Type= 6, Freq= 0, CH_1, rank 1
4501 23:19:30.190197 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4502 23:19:30.190763 ==
4503 23:19:30.193093 RX Vref Scan: 0
4504 23:19:30.193553
4505 23:19:30.193914 RX Vref 0 -> 0, step: 1
4506 23:19:30.194252
4507 23:19:30.196317 RX Delay -230 -> 252, step: 16
4508 23:19:30.203304 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4509 23:19:30.207206 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4510 23:19:30.209707 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4511 23:19:30.213105 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4512 23:19:30.217070 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4513 23:19:30.223623 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4514 23:19:30.227046 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4515 23:19:30.229631 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4516 23:19:30.233103 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4517 23:19:30.239431 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4518 23:19:30.243364 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4519 23:19:30.246024 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4520 23:19:30.249720 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4521 23:19:30.256068 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4522 23:19:30.259528 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4523 23:19:30.263843 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4524 23:19:30.264405 ==
4525 23:19:30.265796 Dram Type= 6, Freq= 0, CH_1, rank 1
4526 23:19:30.269062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4527 23:19:30.273025 ==
4528 23:19:30.273487 DQS Delay:
4529 23:19:30.273850 DQS0 = 0, DQS1 = 0
4530 23:19:30.276095 DQM Delay:
4531 23:19:30.276560 DQM0 = 39, DQM1 = 32
4532 23:19:30.279540 DQ Delay:
4533 23:19:30.280113 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4534 23:19:30.282417 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4535 23:19:30.285856 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4536 23:19:30.288654 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4537 23:19:30.292911
4538 23:19:30.293370
4539 23:19:30.293734 ==
4540 23:19:30.295945 Dram Type= 6, Freq= 0, CH_1, rank 1
4541 23:19:30.298935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4542 23:19:30.299494 ==
4543 23:19:30.299862
4544 23:19:30.300199
4545 23:19:30.302480 TX Vref Scan disable
4546 23:19:30.302943 == TX Byte 0 ==
4547 23:19:30.309035 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4548 23:19:30.311968 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4549 23:19:30.312449 == TX Byte 1 ==
4550 23:19:30.319188 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4551 23:19:30.322771 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4552 23:19:30.323339 ==
4553 23:19:30.325715 Dram Type= 6, Freq= 0, CH_1, rank 1
4554 23:19:30.329390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4555 23:19:30.329954 ==
4556 23:19:30.330317
4557 23:19:30.330649
4558 23:19:30.331830 TX Vref Scan disable
4559 23:19:30.335132 == TX Byte 0 ==
4560 23:19:30.338977 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4561 23:19:30.342066 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4562 23:19:30.345126 == TX Byte 1 ==
4563 23:19:30.348265 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4564 23:19:30.351689 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4565 23:19:30.355096
4566 23:19:30.355681 [DATLAT]
4567 23:19:30.356053 Freq=600, CH1 RK1
4568 23:19:30.356396
4569 23:19:30.358587 DATLAT Default: 0x8
4570 23:19:30.359049 0, 0xFFFF, sum = 0
4571 23:19:30.362332 1, 0xFFFF, sum = 0
4572 23:19:30.362800 2, 0xFFFF, sum = 0
4573 23:19:30.365208 3, 0xFFFF, sum = 0
4574 23:19:30.368884 4, 0xFFFF, sum = 0
4575 23:19:30.369473 5, 0xFFFF, sum = 0
4576 23:19:30.371313 6, 0xFFFF, sum = 0
4577 23:19:30.371829 7, 0x0, sum = 1
4578 23:19:30.372198 8, 0x0, sum = 2
4579 23:19:30.375026 9, 0x0, sum = 3
4580 23:19:30.375572 10, 0x0, sum = 4
4581 23:19:30.378233 best_step = 8
4582 23:19:30.378691
4583 23:19:30.379051 ==
4584 23:19:30.381638 Dram Type= 6, Freq= 0, CH_1, rank 1
4585 23:19:30.386236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4586 23:19:30.386696 ==
4587 23:19:30.388680 RX Vref Scan: 0
4588 23:19:30.389180
4589 23:19:30.389594 RX Vref 0 -> 0, step: 1
4590 23:19:30.389935
4591 23:19:30.391310 RX Delay -195 -> 252, step: 8
4592 23:19:30.398917 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4593 23:19:30.401976 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4594 23:19:30.405574 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4595 23:19:30.409158 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4596 23:19:30.415589 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4597 23:19:30.418882 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4598 23:19:30.422498 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4599 23:19:30.425333 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4600 23:19:30.432560 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4601 23:19:30.435789 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4602 23:19:30.438771 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4603 23:19:30.442455 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4604 23:19:30.445700 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4605 23:19:30.451785 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4606 23:19:30.455723 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4607 23:19:30.458228 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4608 23:19:30.458795 ==
4609 23:19:30.461662 Dram Type= 6, Freq= 0, CH_1, rank 1
4610 23:19:30.468543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4611 23:19:30.469141 ==
4612 23:19:30.469510 DQS Delay:
4613 23:19:30.469848 DQS0 = 0, DQS1 = 0
4614 23:19:30.471514 DQM Delay:
4615 23:19:30.472042 DQM0 = 36, DQM1 = 29
4616 23:19:30.475011 DQ Delay:
4617 23:19:30.478314 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4618 23:19:30.481255 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4619 23:19:30.484584 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =24
4620 23:19:30.488696 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4621 23:19:30.489296
4622 23:19:30.489660
4623 23:19:30.495025 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4624 23:19:30.497810 CH1 RK1: MR19=808, MR18=5C5C
4625 23:19:30.505196 CH1_RK1: MR19=0x808, MR18=0x5C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4626 23:19:30.508232 [RxdqsGatingPostProcess] freq 600
4627 23:19:30.511111 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4628 23:19:30.514917 Pre-setting of DQS Precalculation
4629 23:19:30.521388 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4630 23:19:30.528149 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4631 23:19:30.534802 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4632 23:19:30.535326
4633 23:19:30.535659
4634 23:19:30.537836 [Calibration Summary] 1200 Mbps
4635 23:19:30.538302 CH 0, Rank 0
4636 23:19:30.541430 SW Impedance : PASS
4637 23:19:30.544630 DUTY Scan : NO K
4638 23:19:30.545286 ZQ Calibration : PASS
4639 23:19:30.548063 Jitter Meter : NO K
4640 23:19:30.551043 CBT Training : PASS
4641 23:19:30.551501 Write leveling : PASS
4642 23:19:30.554701 RX DQS gating : PASS
4643 23:19:30.557903 RX DQ/DQS(RDDQC) : PASS
4644 23:19:30.558321 TX DQ/DQS : PASS
4645 23:19:30.561465 RX DATLAT : PASS
4646 23:19:30.561882 RX DQ/DQS(Engine): PASS
4647 23:19:30.564630 TX OE : NO K
4648 23:19:30.565194 All Pass.
4649 23:19:30.565530
4650 23:19:30.567589 CH 0, Rank 1
4651 23:19:30.568040 SW Impedance : PASS
4652 23:19:30.571792 DUTY Scan : NO K
4653 23:19:30.574469 ZQ Calibration : PASS
4654 23:19:30.575044 Jitter Meter : NO K
4655 23:19:30.577847 CBT Training : PASS
4656 23:19:30.580811 Write leveling : PASS
4657 23:19:30.581419 RX DQS gating : PASS
4658 23:19:30.584066 RX DQ/DQS(RDDQC) : PASS
4659 23:19:30.587231 TX DQ/DQS : PASS
4660 23:19:30.587694 RX DATLAT : PASS
4661 23:19:30.591337 RX DQ/DQS(Engine): PASS
4662 23:19:30.594401 TX OE : NO K
4663 23:19:30.594973 All Pass.
4664 23:19:30.595339
4665 23:19:30.595674 CH 1, Rank 0
4666 23:19:30.597609 SW Impedance : PASS
4667 23:19:30.600413 DUTY Scan : NO K
4668 23:19:30.600918 ZQ Calibration : PASS
4669 23:19:30.603640 Jitter Meter : NO K
4670 23:19:30.607262 CBT Training : PASS
4671 23:19:30.607721 Write leveling : PASS
4672 23:19:30.611012 RX DQS gating : PASS
4673 23:19:30.613852 RX DQ/DQS(RDDQC) : PASS
4674 23:19:30.614307 TX DQ/DQS : PASS
4675 23:19:30.617939 RX DATLAT : PASS
4676 23:19:30.621032 RX DQ/DQS(Engine): PASS
4677 23:19:30.621494 TX OE : NO K
4678 23:19:30.621858 All Pass.
4679 23:19:30.624382
4680 23:19:30.624985 CH 1, Rank 1
4681 23:19:30.627058 SW Impedance : PASS
4682 23:19:30.627615 DUTY Scan : NO K
4683 23:19:30.630950 ZQ Calibration : PASS
4684 23:19:30.634644 Jitter Meter : NO K
4685 23:19:30.635205 CBT Training : PASS
4686 23:19:30.636934 Write leveling : PASS
4687 23:19:30.637398 RX DQS gating : PASS
4688 23:19:30.640497 RX DQ/DQS(RDDQC) : PASS
4689 23:19:30.643656 TX DQ/DQS : PASS
4690 23:19:30.644225 RX DATLAT : PASS
4691 23:19:30.646931 RX DQ/DQS(Engine): PASS
4692 23:19:30.651253 TX OE : NO K
4693 23:19:30.651823 All Pass.
4694 23:19:30.652189
4695 23:19:30.654034 DramC Write-DBI off
4696 23:19:30.654495 PER_BANK_REFRESH: Hybrid Mode
4697 23:19:30.656877 TX_TRACKING: ON
4698 23:19:30.667271 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4699 23:19:30.670697 [FAST_K] Save calibration result to emmc
4700 23:19:30.673123 dramc_set_vcore_voltage set vcore to 662500
4701 23:19:30.673584 Read voltage for 933, 3
4702 23:19:30.677739 Vio18 = 0
4703 23:19:30.678300 Vcore = 662500
4704 23:19:30.678665 Vdram = 0
4705 23:19:30.680134 Vddq = 0
4706 23:19:30.680594 Vmddr = 0
4707 23:19:30.683186 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4708 23:19:30.690062 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4709 23:19:30.693322 MEM_TYPE=3, freq_sel=17
4710 23:19:30.696771 sv_algorithm_assistance_LP4_1600
4711 23:19:30.700311 ============ PULL DRAM RESETB DOWN ============
4712 23:19:30.703223 ========== PULL DRAM RESETB DOWN end =========
4713 23:19:30.710008 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4714 23:19:30.713044 ===================================
4715 23:19:30.713506 LPDDR4 DRAM CONFIGURATION
4716 23:19:30.715982 ===================================
4717 23:19:30.719435 EX_ROW_EN[0] = 0x0
4718 23:19:30.722929 EX_ROW_EN[1] = 0x0
4719 23:19:30.723640 LP4Y_EN = 0x0
4720 23:19:30.726314 WORK_FSP = 0x0
4721 23:19:30.727031 WL = 0x3
4722 23:19:30.729694 RL = 0x3
4723 23:19:30.730416 BL = 0x2
4724 23:19:30.733232 RPST = 0x0
4725 23:19:30.733920 RD_PRE = 0x0
4726 23:19:30.736746 WR_PRE = 0x1
4727 23:19:30.737458 WR_PST = 0x0
4728 23:19:30.739696 DBI_WR = 0x0
4729 23:19:30.740390 DBI_RD = 0x0
4730 23:19:30.743188 OTF = 0x1
4731 23:19:30.746126 ===================================
4732 23:19:30.749484 ===================================
4733 23:19:30.749856 ANA top config
4734 23:19:30.752361 ===================================
4735 23:19:30.755461 DLL_ASYNC_EN = 0
4736 23:19:30.759340 ALL_SLAVE_EN = 1
4737 23:19:30.759553 NEW_RANK_MODE = 1
4738 23:19:30.762186 DLL_IDLE_MODE = 1
4739 23:19:30.766324 LP45_APHY_COMB_EN = 1
4740 23:19:30.768661 TX_ODT_DIS = 1
4741 23:19:30.772302 NEW_8X_MODE = 1
4742 23:19:30.775250 ===================================
4743 23:19:30.779005 ===================================
4744 23:19:30.782753 data_rate = 1866
4745 23:19:30.782857 CKR = 1
4746 23:19:30.785382 DQ_P2S_RATIO = 8
4747 23:19:30.788572 ===================================
4748 23:19:30.792179 CA_P2S_RATIO = 8
4749 23:19:30.795525 DQ_CA_OPEN = 0
4750 23:19:30.798547 DQ_SEMI_OPEN = 0
4751 23:19:30.798651 CA_SEMI_OPEN = 0
4752 23:19:30.802521 CA_FULL_RATE = 0
4753 23:19:30.805132 DQ_CKDIV4_EN = 1
4754 23:19:30.808632 CA_CKDIV4_EN = 1
4755 23:19:30.812340 CA_PREDIV_EN = 0
4756 23:19:30.815254 PH8_DLY = 0
4757 23:19:30.819195 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4758 23:19:30.819387 DQ_AAMCK_DIV = 4
4759 23:19:30.822099 CA_AAMCK_DIV = 4
4760 23:19:30.825327 CA_ADMCK_DIV = 4
4761 23:19:30.829010 DQ_TRACK_CA_EN = 0
4762 23:19:30.832974 CA_PICK = 933
4763 23:19:30.835327 CA_MCKIO = 933
4764 23:19:30.835558 MCKIO_SEMI = 0
4765 23:19:30.839036 PLL_FREQ = 3732
4766 23:19:30.841820 DQ_UI_PI_RATIO = 32
4767 23:19:30.846175 CA_UI_PI_RATIO = 0
4768 23:19:30.848633 ===================================
4769 23:19:30.852463 ===================================
4770 23:19:30.855540 memory_type:LPDDR4
4771 23:19:30.855842 GP_NUM : 10
4772 23:19:30.858711 SRAM_EN : 1
4773 23:19:30.862258 MD32_EN : 0
4774 23:19:30.865785 ===================================
4775 23:19:30.866217 [ANA_INIT] >>>>>>>>>>>>>>
4776 23:19:30.868764 <<<<<< [CONFIGURE PHASE]: ANA_TX
4777 23:19:30.871597 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4778 23:19:30.875162 ===================================
4779 23:19:30.879091 data_rate = 1866,PCW = 0X8f00
4780 23:19:30.881543 ===================================
4781 23:19:30.885680 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4782 23:19:30.891868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4783 23:19:30.895364 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4784 23:19:30.901710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4785 23:19:30.905603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4786 23:19:30.908576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4787 23:19:30.909100 [ANA_INIT] flow start
4788 23:19:30.911748 [ANA_INIT] PLL >>>>>>>>
4789 23:19:30.914935 [ANA_INIT] PLL <<<<<<<<
4790 23:19:30.918531 [ANA_INIT] MIDPI >>>>>>>>
4791 23:19:30.919257 [ANA_INIT] MIDPI <<<<<<<<
4792 23:19:30.922079 [ANA_INIT] DLL >>>>>>>>
4793 23:19:30.922539 [ANA_INIT] flow end
4794 23:19:30.928556 ============ LP4 DIFF to SE enter ============
4795 23:19:30.931593 ============ LP4 DIFF to SE exit ============
4796 23:19:30.936182 [ANA_INIT] <<<<<<<<<<<<<
4797 23:19:30.939172 [Flow] Enable top DCM control >>>>>
4798 23:19:30.942043 [Flow] Enable top DCM control <<<<<
4799 23:19:30.945100 Enable DLL master slave shuffle
4800 23:19:30.948602 ==============================================================
4801 23:19:30.951689 Gating Mode config
4802 23:19:30.955294 ==============================================================
4803 23:19:30.958120 Config description:
4804 23:19:30.968587 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4805 23:19:30.974511 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4806 23:19:30.977706 SELPH_MODE 0: By rank 1: By Phase
4807 23:19:30.984366 ==============================================================
4808 23:19:30.988317 GAT_TRACK_EN = 1
4809 23:19:30.991983 RX_GATING_MODE = 2
4810 23:19:30.995002 RX_GATING_TRACK_MODE = 2
4811 23:19:30.997969 SELPH_MODE = 1
4812 23:19:31.001090 PICG_EARLY_EN = 1
4813 23:19:31.004921 VALID_LAT_VALUE = 1
4814 23:19:31.008075 ==============================================================
4815 23:19:31.011187 Enter into Gating configuration >>>>
4816 23:19:31.014637 Exit from Gating configuration <<<<
4817 23:19:31.017705 Enter into DVFS_PRE_config >>>>>
4818 23:19:31.027913 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4819 23:19:31.031831 Exit from DVFS_PRE_config <<<<<
4820 23:19:31.035147 Enter into PICG configuration >>>>
4821 23:19:31.038079 Exit from PICG configuration <<<<
4822 23:19:31.041893 [RX_INPUT] configuration >>>>>
4823 23:19:31.044610 [RX_INPUT] configuration <<<<<
4824 23:19:31.051539 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4825 23:19:31.054422 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4826 23:19:31.060781 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4827 23:19:31.067936 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4828 23:19:31.074314 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4829 23:19:31.081487 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4830 23:19:31.084027 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4831 23:19:31.087895 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4832 23:19:31.091165 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4833 23:19:31.097760 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4834 23:19:31.100920 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4835 23:19:31.104306 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4836 23:19:31.107912 ===================================
4837 23:19:31.110892 LPDDR4 DRAM CONFIGURATION
4838 23:19:31.114079 ===================================
4839 23:19:31.114541 EX_ROW_EN[0] = 0x0
4840 23:19:31.117696 EX_ROW_EN[1] = 0x0
4841 23:19:31.118258 LP4Y_EN = 0x0
4842 23:19:31.121538 WORK_FSP = 0x0
4843 23:19:31.124280 WL = 0x3
4844 23:19:31.124884 RL = 0x3
4845 23:19:31.127343 BL = 0x2
4846 23:19:31.127951 RPST = 0x0
4847 23:19:31.131240 RD_PRE = 0x0
4848 23:19:31.131828 WR_PRE = 0x1
4849 23:19:31.133465 WR_PST = 0x0
4850 23:19:31.133925 DBI_WR = 0x0
4851 23:19:31.137449 DBI_RD = 0x0
4852 23:19:31.138164 OTF = 0x1
4853 23:19:31.140469 ===================================
4854 23:19:31.144604 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4855 23:19:31.150983 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4856 23:19:31.154259 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4857 23:19:31.156657 ===================================
4858 23:19:31.160752 LPDDR4 DRAM CONFIGURATION
4859 23:19:31.164288 ===================================
4860 23:19:31.164899 EX_ROW_EN[0] = 0x10
4861 23:19:31.167903 EX_ROW_EN[1] = 0x0
4862 23:19:31.168460 LP4Y_EN = 0x0
4863 23:19:31.169824 WORK_FSP = 0x0
4864 23:19:31.173368 WL = 0x3
4865 23:19:31.173831 RL = 0x3
4866 23:19:31.177449 BL = 0x2
4867 23:19:31.177907 RPST = 0x0
4868 23:19:31.180475 RD_PRE = 0x0
4869 23:19:31.181091 WR_PRE = 0x1
4870 23:19:31.183489 WR_PST = 0x0
4871 23:19:31.184050 DBI_WR = 0x0
4872 23:19:31.186887 DBI_RD = 0x0
4873 23:19:31.187448 OTF = 0x1
4874 23:19:31.190170 ===================================
4875 23:19:31.197338 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4876 23:19:31.201599 nWR fixed to 30
4877 23:19:31.204005 [ModeRegInit_LP4] CH0 RK0
4878 23:19:31.204462 [ModeRegInit_LP4] CH0 RK1
4879 23:19:31.207605 [ModeRegInit_LP4] CH1 RK0
4880 23:19:31.211095 [ModeRegInit_LP4] CH1 RK1
4881 23:19:31.211685 match AC timing 8
4882 23:19:31.217517 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4883 23:19:31.221016 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4884 23:19:31.224348 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4885 23:19:31.231122 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4886 23:19:31.234546 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4887 23:19:31.235113 ==
4888 23:19:31.237487 Dram Type= 6, Freq= 0, CH_0, rank 0
4889 23:19:31.240572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4890 23:19:31.241082 ==
4891 23:19:31.247186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4892 23:19:31.253632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4893 23:19:31.257691 [CA 0] Center 38 (8~69) winsize 62
4894 23:19:31.260897 [CA 1] Center 38 (8~69) winsize 62
4895 23:19:31.263651 [CA 2] Center 36 (6~67) winsize 62
4896 23:19:31.267048 [CA 3] Center 36 (6~66) winsize 61
4897 23:19:31.270094 [CA 4] Center 34 (4~65) winsize 62
4898 23:19:31.273272 [CA 5] Center 34 (4~65) winsize 62
4899 23:19:31.273812
4900 23:19:31.276599 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4901 23:19:31.277146
4902 23:19:31.280333 [CATrainingPosCal] consider 1 rank data
4903 23:19:31.284675 u2DelayCellTimex100 = 270/100 ps
4904 23:19:31.287582 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4905 23:19:31.290716 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4906 23:19:31.293234 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4907 23:19:31.296909 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4908 23:19:31.303232 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4909 23:19:31.306530 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4910 23:19:31.306995
4911 23:19:31.309962 CA PerBit enable=1, Macro0, CA PI delay=34
4912 23:19:31.310507
4913 23:19:31.313065 [CBTSetCACLKResult] CA Dly = 34
4914 23:19:31.313540 CS Dly: 7 (0~38)
4915 23:19:31.313903 ==
4916 23:19:31.316648 Dram Type= 6, Freq= 0, CH_0, rank 1
4917 23:19:31.322915 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4918 23:19:31.323653 ==
4919 23:19:31.326210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4920 23:19:31.333350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4921 23:19:31.336742 [CA 0] Center 38 (8~69) winsize 62
4922 23:19:31.339620 [CA 1] Center 38 (7~69) winsize 63
4923 23:19:31.343513 [CA 2] Center 36 (5~67) winsize 63
4924 23:19:31.346961 [CA 3] Center 35 (5~66) winsize 62
4925 23:19:31.349378 [CA 4] Center 34 (4~65) winsize 62
4926 23:19:31.352899 [CA 5] Center 34 (4~65) winsize 62
4927 23:19:31.353464
4928 23:19:31.356431 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4929 23:19:31.357063
4930 23:19:31.359490 [CATrainingPosCal] consider 2 rank data
4931 23:19:31.363217 u2DelayCellTimex100 = 270/100 ps
4932 23:19:31.366140 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4933 23:19:31.368893 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4934 23:19:31.375838 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4935 23:19:31.379306 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4936 23:19:31.382401 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4937 23:19:31.387032 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4938 23:19:31.387598
4939 23:19:31.389044 CA PerBit enable=1, Macro0, CA PI delay=34
4940 23:19:31.389508
4941 23:19:31.392674 [CBTSetCACLKResult] CA Dly = 34
4942 23:19:31.393166 CS Dly: 7 (0~39)
4943 23:19:31.396054
4944 23:19:31.399229 ----->DramcWriteLeveling(PI) begin...
4945 23:19:31.399710 ==
4946 23:19:31.401987 Dram Type= 6, Freq= 0, CH_0, rank 0
4947 23:19:31.405812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4948 23:19:31.406273 ==
4949 23:19:31.408546 Write leveling (Byte 0): 27 => 27
4950 23:19:31.412331 Write leveling (Byte 1): 27 => 27
4951 23:19:31.415660 DramcWriteLeveling(PI) end<-----
4952 23:19:31.416177
4953 23:19:31.416507 ==
4954 23:19:31.419409 Dram Type= 6, Freq= 0, CH_0, rank 0
4955 23:19:31.422610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4956 23:19:31.423173 ==
4957 23:19:31.426049 [Gating] SW mode calibration
4958 23:19:31.432633 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4959 23:19:31.439075 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4960 23:19:31.441672 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4961 23:19:31.445294 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4962 23:19:31.452216 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4963 23:19:31.456112 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4964 23:19:31.458670 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4965 23:19:31.465693 0 10 20 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
4966 23:19:31.468662 0 10 24 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
4967 23:19:31.472150 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4968 23:19:31.478483 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4969 23:19:31.482176 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4970 23:19:31.484674 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4971 23:19:31.491428 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4972 23:19:31.497695 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4973 23:19:31.498969 0 11 20 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
4974 23:19:31.504611 0 11 24 | B1->B0 | 3535 4242 | 0 0 | (0 0) (0 0)
4975 23:19:31.508404 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4976 23:19:31.511315 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4977 23:19:31.517958 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4978 23:19:31.521374 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4979 23:19:31.524437 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4980 23:19:31.531863 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4981 23:19:31.534350 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4982 23:19:31.537884 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4983 23:19:31.544360 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4984 23:19:31.547505 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4985 23:19:31.551462 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4986 23:19:31.557630 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4987 23:19:31.561030 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4988 23:19:31.564175 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4989 23:19:31.571150 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4990 23:19:31.574778 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4991 23:19:31.577192 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4992 23:19:31.583926 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4993 23:19:31.587883 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4994 23:19:31.590793 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 23:19:31.597188 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 23:19:31.600473 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4997 23:19:31.606226 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4998 23:19:31.611834 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4999 23:19:31.613870 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5000 23:19:31.617178 Total UI for P1: 0, mck2ui 16
5001 23:19:31.620745 best dqsien dly found for B0: ( 0, 14, 20)
5002 23:19:31.623528 Total UI for P1: 0, mck2ui 16
5003 23:19:31.627585 best dqsien dly found for B1: ( 0, 14, 20)
5004 23:19:31.630344 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5005 23:19:31.633337 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5006 23:19:31.633796
5007 23:19:31.637216 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5008 23:19:31.639849 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5009 23:19:31.643957 [Gating] SW calibration Done
5010 23:19:31.644420 ==
5011 23:19:31.646824 Dram Type= 6, Freq= 0, CH_0, rank 0
5012 23:19:31.650222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5013 23:19:31.653257 ==
5014 23:19:31.653671 RX Vref Scan: 0
5015 23:19:31.653997
5016 23:19:31.656801 RX Vref 0 -> 0, step: 1
5017 23:19:31.657317
5018 23:19:31.659941 RX Delay -80 -> 252, step: 8
5019 23:19:31.663218 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5020 23:19:31.666797 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5021 23:19:31.669765 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5022 23:19:31.672817 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5023 23:19:31.676558 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5024 23:19:31.683293 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5025 23:19:31.686286 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5026 23:19:31.689520 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5027 23:19:31.692468 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5028 23:19:31.696572 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5029 23:19:31.702877 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5030 23:19:31.706479 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5031 23:19:31.709363 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5032 23:19:31.712307 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5033 23:19:31.716446 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5034 23:19:31.722775 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5035 23:19:31.723294 ==
5036 23:19:31.725649 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 23:19:31.729445 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5038 23:19:31.730045 ==
5039 23:19:31.730383 DQS Delay:
5040 23:19:31.732597 DQS0 = 0, DQS1 = 0
5041 23:19:31.733109 DQM Delay:
5042 23:19:31.736494 DQM0 = 95, DQM1 = 84
5043 23:19:31.737200 DQ Delay:
5044 23:19:31.738738 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5045 23:19:31.742753 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5046 23:19:31.746649 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5047 23:19:31.749229 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5048 23:19:31.749642
5049 23:19:31.749964
5050 23:19:31.750265 ==
5051 23:19:31.752363 Dram Type= 6, Freq= 0, CH_0, rank 0
5052 23:19:31.755769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5053 23:19:31.759563 ==
5054 23:19:31.760076
5055 23:19:31.760403
5056 23:19:31.760703 TX Vref Scan disable
5057 23:19:31.762826 == TX Byte 0 ==
5058 23:19:31.765429 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5059 23:19:31.769068 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5060 23:19:31.772507 == TX Byte 1 ==
5061 23:19:31.775782 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5062 23:19:31.778650 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5063 23:19:31.782388 ==
5064 23:19:31.782907 Dram Type= 6, Freq= 0, CH_0, rank 0
5065 23:19:31.788841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5066 23:19:31.789355 ==
5067 23:19:31.789685
5068 23:19:31.789986
5069 23:19:31.792050 TX Vref Scan disable
5070 23:19:31.792461 == TX Byte 0 ==
5071 23:19:31.798819 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5072 23:19:31.801515 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5073 23:19:31.801974 == TX Byte 1 ==
5074 23:19:31.809229 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5075 23:19:31.812005 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5076 23:19:31.812577
5077 23:19:31.813006 [DATLAT]
5078 23:19:31.814747 Freq=933, CH0 RK0
5079 23:19:31.815204
5080 23:19:31.815636 DATLAT Default: 0xd
5081 23:19:31.818927 0, 0xFFFF, sum = 0
5082 23:19:31.819394 1, 0xFFFF, sum = 0
5083 23:19:31.822612 2, 0xFFFF, sum = 0
5084 23:19:31.823134 3, 0xFFFF, sum = 0
5085 23:19:31.825191 4, 0xFFFF, sum = 0
5086 23:19:31.825606 5, 0xFFFF, sum = 0
5087 23:19:31.828084 6, 0xFFFF, sum = 0
5088 23:19:31.831974 7, 0xFFFF, sum = 0
5089 23:19:31.832499 8, 0xFFFF, sum = 0
5090 23:19:31.835074 9, 0xFFFF, sum = 0
5091 23:19:31.835597 10, 0x0, sum = 1
5092 23:19:31.836108 11, 0x0, sum = 2
5093 23:19:31.838970 12, 0x0, sum = 3
5094 23:19:31.839561 13, 0x0, sum = 4
5095 23:19:31.842112 best_step = 11
5096 23:19:31.842628
5097 23:19:31.842954 ==
5098 23:19:31.845176 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 23:19:31.848127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5100 23:19:31.848647 ==
5101 23:19:31.851913 RX Vref Scan: 1
5102 23:19:31.852425
5103 23:19:31.852791 RX Vref 0 -> 0, step: 1
5104 23:19:31.854651
5105 23:19:31.855065 RX Delay -69 -> 252, step: 4
5106 23:19:31.855390
5107 23:19:31.857737 Set Vref, RX VrefLevel [Byte0]: 55
5108 23:19:31.861620 [Byte1]: 48
5109 23:19:31.865978
5110 23:19:31.866536 Final RX Vref Byte 0 = 55 to rank0
5111 23:19:31.869504 Final RX Vref Byte 1 = 48 to rank0
5112 23:19:31.873101 Final RX Vref Byte 0 = 55 to rank1
5113 23:19:31.875478 Final RX Vref Byte 1 = 48 to rank1==
5114 23:19:31.879193 Dram Type= 6, Freq= 0, CH_0, rank 0
5115 23:19:31.885483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5116 23:19:31.885943 ==
5117 23:19:31.886302 DQS Delay:
5118 23:19:31.888979 DQS0 = 0, DQS1 = 0
5119 23:19:31.889470 DQM Delay:
5120 23:19:31.889834 DQM0 = 96, DQM1 = 87
5121 23:19:31.892396 DQ Delay:
5122 23:19:31.895639 DQ0 =92, DQ1 =96, DQ2 =96, DQ3 =96
5123 23:19:31.899124 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =102
5124 23:19:31.902343 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =78
5125 23:19:31.905364 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =98
5126 23:19:31.905823
5127 23:19:31.906181
5128 23:19:31.913071 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 413 ps
5129 23:19:31.915797 CH0 RK0: MR19=505, MR18=1B1B
5130 23:19:31.921822 CH0_RK0: MR19=0x505, MR18=0x1B1B, DQSOSC=413, MR23=63, INC=63, DEC=42
5131 23:19:31.922382
5132 23:19:31.926000 ----->DramcWriteLeveling(PI) begin...
5133 23:19:31.926567 ==
5134 23:19:31.928789 Dram Type= 6, Freq= 0, CH_0, rank 1
5135 23:19:31.931897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5136 23:19:31.932458 ==
5137 23:19:31.935375 Write leveling (Byte 0): 27 => 27
5138 23:19:31.938665 Write leveling (Byte 1): 27 => 27
5139 23:19:31.942182 DramcWriteLeveling(PI) end<-----
5140 23:19:31.942742
5141 23:19:31.943098 ==
5142 23:19:31.945406 Dram Type= 6, Freq= 0, CH_0, rank 1
5143 23:19:31.948504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5144 23:19:31.951957 ==
5145 23:19:31.952513 [Gating] SW mode calibration
5146 23:19:31.961748 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5147 23:19:31.965117 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5148 23:19:31.968177 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 23:19:31.975223 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 23:19:31.977936 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 23:19:31.981232 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 23:19:31.987932 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 23:19:31.991668 0 10 20 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
5154 23:19:31.994729 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
5155 23:19:32.001139 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 23:19:32.004339 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 23:19:32.008092 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 23:19:32.014364 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 23:19:32.017451 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 23:19:32.020937 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5161 23:19:32.027975 0 11 20 | B1->B0 | 2f2f 3333 | 0 1 | (0 0) (0 0)
5162 23:19:32.031885 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5163 23:19:32.034674 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 23:19:32.040796 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 23:19:32.044979 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 23:19:32.047628 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 23:19:32.054225 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 23:19:32.057844 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 23:19:32.061319 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5170 23:19:32.067970 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5171 23:19:32.070926 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 23:19:32.074633 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 23:19:32.080204 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 23:19:32.084343 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 23:19:32.087414 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 23:19:32.093584 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 23:19:32.097505 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 23:19:32.099984 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 23:19:32.107452 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 23:19:32.110632 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 23:19:32.114081 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 23:19:32.120266 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 23:19:32.123561 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 23:19:32.127426 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5185 23:19:32.133252 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5186 23:19:32.137129 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5187 23:19:32.139896 Total UI for P1: 0, mck2ui 16
5188 23:19:32.143530 best dqsien dly found for B0: ( 0, 14, 18)
5189 23:19:32.147039 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 23:19:32.149813 Total UI for P1: 0, mck2ui 16
5191 23:19:32.153181 best dqsien dly found for B1: ( 0, 14, 22)
5192 23:19:32.156889 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5193 23:19:32.160362 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5194 23:19:32.160963
5195 23:19:32.166287 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5196 23:19:32.170480 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5197 23:19:32.173684 [Gating] SW calibration Done
5198 23:19:32.174256 ==
5199 23:19:32.176643 Dram Type= 6, Freq= 0, CH_0, rank 1
5200 23:19:32.179544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5201 23:19:32.180030 ==
5202 23:19:32.180742 RX Vref Scan: 0
5203 23:19:32.181182
5204 23:19:32.183318 RX Vref 0 -> 0, step: 1
5205 23:19:32.183879
5206 23:19:32.186715 RX Delay -80 -> 252, step: 8
5207 23:19:32.190319 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5208 23:19:32.192841 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5209 23:19:32.196202 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5210 23:19:32.203131 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5211 23:19:32.206048 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5212 23:19:32.209204 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5213 23:19:32.213108 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5214 23:19:32.215874 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5215 23:19:32.219636 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5216 23:19:32.226152 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5217 23:19:32.229090 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5218 23:19:32.232493 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5219 23:19:32.236509 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5220 23:19:32.242992 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5221 23:19:32.245770 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5222 23:19:32.249602 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5223 23:19:32.250067 ==
5224 23:19:32.252480 Dram Type= 6, Freq= 0, CH_0, rank 1
5225 23:19:32.256522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5226 23:19:32.257142 ==
5227 23:19:32.259864 DQS Delay:
5228 23:19:32.260429 DQS0 = 0, DQS1 = 0
5229 23:19:32.260841 DQM Delay:
5230 23:19:32.262759 DQM0 = 96, DQM1 = 84
5231 23:19:32.263325 DQ Delay:
5232 23:19:32.266400 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5233 23:19:32.269230 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5234 23:19:32.272477 DQ8 =71, DQ9 =71, DQ10 =87, DQ11 =79
5235 23:19:32.275487 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5236 23:19:32.276058
5237 23:19:32.276421
5238 23:19:32.276815 ==
5239 23:19:32.279252 Dram Type= 6, Freq= 0, CH_0, rank 1
5240 23:19:32.285927 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5241 23:19:32.286499 ==
5242 23:19:32.286866
5243 23:19:32.287202
5244 23:19:32.287525 TX Vref Scan disable
5245 23:19:32.289697 == TX Byte 0 ==
5246 23:19:32.292611 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5247 23:19:32.299646 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5248 23:19:32.300215 == TX Byte 1 ==
5249 23:19:32.302264 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5250 23:19:32.309369 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5251 23:19:32.309949 ==
5252 23:19:32.313024 Dram Type= 6, Freq= 0, CH_0, rank 1
5253 23:19:32.316260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5254 23:19:32.316764 ==
5255 23:19:32.317141
5256 23:19:32.317500
5257 23:19:32.319471 TX Vref Scan disable
5258 23:19:32.319931 == TX Byte 0 ==
5259 23:19:32.325765 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5260 23:19:32.329026 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5261 23:19:32.329452 == TX Byte 1 ==
5262 23:19:32.335740 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5263 23:19:32.338873 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5264 23:19:32.339474
5265 23:19:32.339818 [DATLAT]
5266 23:19:32.342160 Freq=933, CH0 RK1
5267 23:19:32.342591
5268 23:19:32.342920 DATLAT Default: 0xb
5269 23:19:32.345818 0, 0xFFFF, sum = 0
5270 23:19:32.346250 1, 0xFFFF, sum = 0
5271 23:19:32.348871 2, 0xFFFF, sum = 0
5272 23:19:32.352465 3, 0xFFFF, sum = 0
5273 23:19:32.353047 4, 0xFFFF, sum = 0
5274 23:19:32.355988 5, 0xFFFF, sum = 0
5275 23:19:32.356532 6, 0xFFFF, sum = 0
5276 23:19:32.359004 7, 0xFFFF, sum = 0
5277 23:19:32.359532 8, 0xFFFF, sum = 0
5278 23:19:32.362025 9, 0xFFFF, sum = 0
5279 23:19:32.362556 10, 0x0, sum = 1
5280 23:19:32.365689 11, 0x0, sum = 2
5281 23:19:32.366222 12, 0x0, sum = 3
5282 23:19:32.369134 13, 0x0, sum = 4
5283 23:19:32.369667 best_step = 11
5284 23:19:32.370001
5285 23:19:32.370308 ==
5286 23:19:32.372123 Dram Type= 6, Freq= 0, CH_0, rank 1
5287 23:19:32.375732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5288 23:19:32.376261 ==
5289 23:19:32.378773 RX Vref Scan: 0
5290 23:19:32.379193
5291 23:19:32.381902 RX Vref 0 -> 0, step: 1
5292 23:19:32.382324
5293 23:19:32.382654 RX Delay -69 -> 252, step: 4
5294 23:19:32.389895 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5295 23:19:32.393064 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5296 23:19:32.396870 iDelay=203, Bit 2, Center 94 (-1 ~ 190) 192
5297 23:19:32.399588 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5298 23:19:32.403384 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5299 23:19:32.409638 iDelay=203, Bit 5, Center 88 (-1 ~ 178) 180
5300 23:19:32.413182 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5301 23:19:32.415953 iDelay=203, Bit 7, Center 106 (11 ~ 202) 192
5302 23:19:32.419929 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5303 23:19:32.423036 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5304 23:19:32.429671 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5305 23:19:32.432914 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5306 23:19:32.436415 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5307 23:19:32.439466 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5308 23:19:32.442830 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5309 23:19:32.446339 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5310 23:19:32.449325 ==
5311 23:19:32.452561 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 23:19:32.455783 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5313 23:19:32.456246 ==
5314 23:19:32.456604 DQS Delay:
5315 23:19:32.458974 DQS0 = 0, DQS1 = 0
5316 23:19:32.459427 DQM Delay:
5317 23:19:32.463054 DQM0 = 97, DQM1 = 86
5318 23:19:32.463662 DQ Delay:
5319 23:19:32.466213 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5320 23:19:32.468912 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5321 23:19:32.472815 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5322 23:19:32.475607 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =96
5323 23:19:32.476169
5324 23:19:32.476530
5325 23:19:32.482493 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d2d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5326 23:19:32.485606 CH0 RK1: MR19=505, MR18=2D2D
5327 23:19:32.492110 CH0_RK1: MR19=0x505, MR18=0x2D2D, DQSOSC=407, MR23=63, INC=65, DEC=43
5328 23:19:32.495474 [RxdqsGatingPostProcess] freq 933
5329 23:19:32.501950 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5330 23:19:32.505738 Pre-setting of DQS Precalculation
5331 23:19:32.508458 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5332 23:19:32.508981 ==
5333 23:19:32.512118 Dram Type= 6, Freq= 0, CH_1, rank 0
5334 23:19:32.514976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5335 23:19:32.518442 ==
5336 23:19:32.521946 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5337 23:19:32.529195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5338 23:19:32.531704 [CA 0] Center 37 (6~68) winsize 63
5339 23:19:32.535061 [CA 1] Center 37 (6~68) winsize 63
5340 23:19:32.538790 [CA 2] Center 34 (4~65) winsize 62
5341 23:19:32.541877 [CA 3] Center 34 (4~65) winsize 62
5342 23:19:32.545195 [CA 4] Center 33 (3~64) winsize 62
5343 23:19:32.548224 [CA 5] Center 33 (3~64) winsize 62
5344 23:19:32.548855
5345 23:19:32.551957 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5346 23:19:32.552534
5347 23:19:32.556022 [CATrainingPosCal] consider 1 rank data
5348 23:19:32.558295 u2DelayCellTimex100 = 270/100 ps
5349 23:19:32.561375 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5350 23:19:32.564937 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5351 23:19:32.568173 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5352 23:19:32.571482 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5353 23:19:32.578047 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5354 23:19:32.580893 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5355 23:19:32.581595
5356 23:19:32.584565 CA PerBit enable=1, Macro0, CA PI delay=33
5357 23:19:32.585111
5358 23:19:32.588541 [CBTSetCACLKResult] CA Dly = 33
5359 23:19:32.589208 CS Dly: 5 (0~36)
5360 23:19:32.589580 ==
5361 23:19:32.591306 Dram Type= 6, Freq= 0, CH_1, rank 1
5362 23:19:32.597877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5363 23:19:32.598331 ==
5364 23:19:32.602123 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5365 23:19:32.607592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5366 23:19:32.611677 [CA 0] Center 37 (6~68) winsize 63
5367 23:19:32.614304 [CA 1] Center 37 (6~68) winsize 63
5368 23:19:32.617492 [CA 2] Center 34 (4~65) winsize 62
5369 23:19:32.621851 [CA 3] Center 34 (4~65) winsize 62
5370 23:19:32.624496 [CA 4] Center 33 (3~63) winsize 61
5371 23:19:32.628335 [CA 5] Center 33 (3~63) winsize 61
5372 23:19:32.628900
5373 23:19:32.631902 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5374 23:19:32.632450
5375 23:19:32.633727 [CATrainingPosCal] consider 2 rank data
5376 23:19:32.637558 u2DelayCellTimex100 = 270/100 ps
5377 23:19:32.640902 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5378 23:19:32.644542 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5379 23:19:32.650483 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5380 23:19:32.653720 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5381 23:19:32.657713 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5382 23:19:32.660254 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5383 23:19:32.660664
5384 23:19:32.664252 CA PerBit enable=1, Macro0, CA PI delay=33
5385 23:19:32.664830
5386 23:19:32.666805 [CBTSetCACLKResult] CA Dly = 33
5387 23:19:32.667243 CS Dly: 5 (0~37)
5388 23:19:32.667564
5389 23:19:32.673641 ----->DramcWriteLeveling(PI) begin...
5390 23:19:32.674158 ==
5391 23:19:32.677478 Dram Type= 6, Freq= 0, CH_1, rank 0
5392 23:19:32.681101 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5393 23:19:32.681637 ==
5394 23:19:32.684240 Write leveling (Byte 0): 24 => 24
5395 23:19:32.687483 Write leveling (Byte 1): 24 => 24
5396 23:19:32.690546 DramcWriteLeveling(PI) end<-----
5397 23:19:32.691109
5398 23:19:32.691443 ==
5399 23:19:32.693484 Dram Type= 6, Freq= 0, CH_1, rank 0
5400 23:19:32.696801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5401 23:19:32.697513 ==
5402 23:19:32.700629 [Gating] SW mode calibration
5403 23:19:32.706701 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5404 23:19:32.714176 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5405 23:19:32.716592 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5406 23:19:32.720097 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 23:19:32.726553 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 23:19:32.730362 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 23:19:32.734059 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5410 23:19:32.739691 0 10 20 | B1->B0 | 3333 2323 | 1 0 | (0 0) (1 0)
5411 23:19:32.743312 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5412 23:19:32.746754 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5413 23:19:32.753240 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5414 23:19:32.756476 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 23:19:32.759949 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 23:19:32.766561 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 23:19:32.769550 0 11 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
5418 23:19:32.772838 0 11 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
5419 23:19:32.779813 0 11 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5420 23:19:32.782534 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5421 23:19:32.786798 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 23:19:32.793419 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 23:19:32.795818 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 23:19:32.798932 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 23:19:32.805962 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5426 23:19:32.809053 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5427 23:19:32.812400 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 23:19:32.818889 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 23:19:32.822422 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 23:19:32.825492 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 23:19:32.833433 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 23:19:32.835803 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 23:19:32.839431 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 23:19:32.846014 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 23:19:32.848875 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 23:19:32.853023 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 23:19:32.859011 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 23:19:32.862158 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 23:19:32.865412 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 23:19:32.868926 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 23:19:32.875910 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5442 23:19:32.878415 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5443 23:19:32.882237 Total UI for P1: 0, mck2ui 16
5444 23:19:32.885066 best dqsien dly found for B0: ( 0, 14, 16)
5445 23:19:32.888574 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 23:19:32.891878 Total UI for P1: 0, mck2ui 16
5447 23:19:32.895408 best dqsien dly found for B1: ( 0, 14, 18)
5448 23:19:32.901266 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5449 23:19:32.904965 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5450 23:19:32.905531
5451 23:19:32.908631 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5452 23:19:32.912770 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5453 23:19:32.915326 [Gating] SW calibration Done
5454 23:19:32.915843 ==
5455 23:19:32.917978 Dram Type= 6, Freq= 0, CH_1, rank 0
5456 23:19:32.921935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5457 23:19:32.922507 ==
5458 23:19:32.924876 RX Vref Scan: 0
5459 23:19:32.925442
5460 23:19:32.925935 RX Vref 0 -> 0, step: 1
5461 23:19:32.926392
5462 23:19:32.927897 RX Delay -80 -> 252, step: 8
5463 23:19:32.931615 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5464 23:19:32.937787 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5465 23:19:32.940940 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5466 23:19:32.944524 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5467 23:19:32.948156 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5468 23:19:32.951737 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5469 23:19:32.954536 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5470 23:19:32.961491 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5471 23:19:32.965500 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5472 23:19:32.968124 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5473 23:19:32.971093 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5474 23:19:32.974418 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5475 23:19:32.981182 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5476 23:19:32.984462 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5477 23:19:32.987823 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5478 23:19:32.990871 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5479 23:19:32.991423 ==
5480 23:19:32.994033 Dram Type= 6, Freq= 0, CH_1, rank 0
5481 23:19:33.000773 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5482 23:19:33.001357 ==
5483 23:19:33.001724 DQS Delay:
5484 23:19:33.002056 DQS0 = 0, DQS1 = 0
5485 23:19:33.003984 DQM Delay:
5486 23:19:33.004439 DQM0 = 94, DQM1 = 87
5487 23:19:33.007695 DQ Delay:
5488 23:19:33.011179 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5489 23:19:33.014309 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5490 23:19:33.017420 DQ8 =71, DQ9 =79, DQ10 =87, DQ11 =79
5491 23:19:33.020806 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5492 23:19:33.021362
5493 23:19:33.021723
5494 23:19:33.022056 ==
5495 23:19:33.023535 Dram Type= 6, Freq= 0, CH_1, rank 0
5496 23:19:33.027301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5497 23:19:33.027866 ==
5498 23:19:33.028230
5499 23:19:33.028562
5500 23:19:33.030365 TX Vref Scan disable
5501 23:19:33.030822 == TX Byte 0 ==
5502 23:19:33.037376 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5503 23:19:33.040283 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5504 23:19:33.040776 == TX Byte 1 ==
5505 23:19:33.047162 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5506 23:19:33.050776 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5507 23:19:33.051259 ==
5508 23:19:33.053784 Dram Type= 6, Freq= 0, CH_1, rank 0
5509 23:19:33.057446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5510 23:19:33.058004 ==
5511 23:19:33.060177
5512 23:19:33.060788
5513 23:19:33.061166 TX Vref Scan disable
5514 23:19:33.063584 == TX Byte 0 ==
5515 23:19:33.067646 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5516 23:19:33.073795 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5517 23:19:33.074347 == TX Byte 1 ==
5518 23:19:33.077264 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5519 23:19:33.083405 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5520 23:19:33.083966
5521 23:19:33.084460 [DATLAT]
5522 23:19:33.085003 Freq=933, CH1 RK0
5523 23:19:33.085454
5524 23:19:33.086898 DATLAT Default: 0xd
5525 23:19:33.087373 0, 0xFFFF, sum = 0
5526 23:19:33.090285 1, 0xFFFF, sum = 0
5527 23:19:33.092978 2, 0xFFFF, sum = 0
5528 23:19:33.093462 3, 0xFFFF, sum = 0
5529 23:19:33.097297 4, 0xFFFF, sum = 0
5530 23:19:33.097797 5, 0xFFFF, sum = 0
5531 23:19:33.099612 6, 0xFFFF, sum = 0
5532 23:19:33.100092 7, 0xFFFF, sum = 0
5533 23:19:33.103390 8, 0xFFFF, sum = 0
5534 23:19:33.104030 9, 0xFFFF, sum = 0
5535 23:19:33.106425 10, 0x0, sum = 1
5536 23:19:33.106908 11, 0x0, sum = 2
5537 23:19:33.110058 12, 0x0, sum = 3
5538 23:19:33.110536 13, 0x0, sum = 4
5539 23:19:33.111021 best_step = 11
5540 23:19:33.113019
5541 23:19:33.113507 ==
5542 23:19:33.116176 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 23:19:33.119842 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5544 23:19:33.120419 ==
5545 23:19:33.120969 RX Vref Scan: 1
5546 23:19:33.121429
5547 23:19:33.122580 RX Vref 0 -> 0, step: 1
5548 23:19:33.123053
5549 23:19:33.126302 RX Delay -69 -> 252, step: 4
5550 23:19:33.126876
5551 23:19:33.129506 Set Vref, RX VrefLevel [Byte0]: 54
5552 23:19:33.133826 [Byte1]: 49
5553 23:19:33.134397
5554 23:19:33.136269 Final RX Vref Byte 0 = 54 to rank0
5555 23:19:33.139875 Final RX Vref Byte 1 = 49 to rank0
5556 23:19:33.143086 Final RX Vref Byte 0 = 54 to rank1
5557 23:19:33.146293 Final RX Vref Byte 1 = 49 to rank1==
5558 23:19:33.149389 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 23:19:33.156504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5560 23:19:33.157113 ==
5561 23:19:33.157603 DQS Delay:
5562 23:19:33.158059 DQS0 = 0, DQS1 = 0
5563 23:19:33.159621 DQM Delay:
5564 23:19:33.160094 DQM0 = 94, DQM1 = 88
5565 23:19:33.162524 DQ Delay:
5566 23:19:33.165614 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5567 23:19:33.169679 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5568 23:19:33.172103 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5569 23:19:33.176590 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5570 23:19:33.177260
5571 23:19:33.177743
5572 23:19:33.182861 [DQSOSCAuto] RK0, (LSB)MR18= 0x3333, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5573 23:19:33.186095 CH1 RK0: MR19=505, MR18=3333
5574 23:19:33.192249 CH1_RK0: MR19=0x505, MR18=0x3333, DQSOSC=405, MR23=63, INC=66, DEC=44
5575 23:19:33.192869
5576 23:19:33.196514 ----->DramcWriteLeveling(PI) begin...
5577 23:19:33.197148 ==
5578 23:19:33.200136 Dram Type= 6, Freq= 0, CH_1, rank 1
5579 23:19:33.202377 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5580 23:19:33.202941 ==
5581 23:19:33.205593 Write leveling (Byte 0): 25 => 25
5582 23:19:33.209226 Write leveling (Byte 1): 25 => 25
5583 23:19:33.212450 DramcWriteLeveling(PI) end<-----
5584 23:19:33.213046
5585 23:19:33.213415 ==
5586 23:19:33.216358 Dram Type= 6, Freq= 0, CH_1, rank 1
5587 23:19:33.218792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5588 23:19:33.219252 ==
5589 23:19:33.221754 [Gating] SW mode calibration
5590 23:19:33.228793 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5591 23:19:33.235271 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5592 23:19:33.238406 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 23:19:33.245323 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 23:19:33.249542 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 23:19:33.251836 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 23:19:33.258619 0 10 16 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
5597 23:19:33.262516 0 10 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5598 23:19:33.264956 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 23:19:33.271984 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 23:19:33.274828 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 23:19:33.278199 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 23:19:33.285078 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 23:19:33.288430 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 23:19:33.291815 0 11 16 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
5605 23:19:33.298969 0 11 20 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
5606 23:19:33.300994 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 23:19:33.304204 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 23:19:33.311611 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 23:19:33.314850 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 23:19:33.317942 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 23:19:33.324531 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5612 23:19:33.327913 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5613 23:19:33.331371 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5614 23:19:33.338194 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 23:19:33.341379 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:19:33.344489 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:19:33.351091 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:19:33.354571 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 23:19:33.357500 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 23:19:33.364942 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 23:19:33.368698 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 23:19:33.370572 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 23:19:33.377385 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 23:19:33.380818 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 23:19:33.383834 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 23:19:33.390641 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 23:19:33.393964 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5628 23:19:33.397100 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5629 23:19:33.403764 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 23:19:33.404356 Total UI for P1: 0, mck2ui 16
5631 23:19:33.410678 best dqsien dly found for B0: ( 0, 14, 14)
5632 23:19:33.411240 Total UI for P1: 0, mck2ui 16
5633 23:19:33.414505 best dqsien dly found for B1: ( 0, 14, 16)
5634 23:19:33.420790 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5635 23:19:33.423968 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5636 23:19:33.424517
5637 23:19:33.426980 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5638 23:19:33.430145 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5639 23:19:33.433432 [Gating] SW calibration Done
5640 23:19:33.433927 ==
5641 23:19:33.436870 Dram Type= 6, Freq= 0, CH_1, rank 1
5642 23:19:33.440581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5643 23:19:33.441200 ==
5644 23:19:33.443363 RX Vref Scan: 0
5645 23:19:33.443933
5646 23:19:33.444419 RX Vref 0 -> 0, step: 1
5647 23:19:33.444979
5648 23:19:33.446789 RX Delay -80 -> 252, step: 8
5649 23:19:33.450531 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5650 23:19:33.456678 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5651 23:19:33.459805 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5652 23:19:33.463345 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5653 23:19:33.466559 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5654 23:19:33.470049 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5655 23:19:33.472870 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5656 23:19:33.480693 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5657 23:19:33.482881 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5658 23:19:33.486194 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5659 23:19:33.489701 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5660 23:19:33.493713 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5661 23:19:33.499841 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5662 23:19:33.503453 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5663 23:19:33.506419 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5664 23:19:33.509710 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5665 23:19:33.510192 ==
5666 23:19:33.513544 Dram Type= 6, Freq= 0, CH_1, rank 1
5667 23:19:33.515936 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5668 23:19:33.519344 ==
5669 23:19:33.519821 DQS Delay:
5670 23:19:33.520309 DQS0 = 0, DQS1 = 0
5671 23:19:33.522592 DQM Delay:
5672 23:19:33.523066 DQM0 = 95, DQM1 = 85
5673 23:19:33.526103 DQ Delay:
5674 23:19:33.530182 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =91
5675 23:19:33.530677 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5676 23:19:33.532758 DQ8 =71, DQ9 =75, DQ10 =83, DQ11 =79
5677 23:19:33.539315 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =95
5678 23:19:33.539887
5679 23:19:33.540372
5680 23:19:33.540951 ==
5681 23:19:33.543255 Dram Type= 6, Freq= 0, CH_1, rank 1
5682 23:19:33.545480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5683 23:19:33.545962 ==
5684 23:19:33.546443
5685 23:19:33.546893
5686 23:19:33.548847 TX Vref Scan disable
5687 23:19:33.549325 == TX Byte 0 ==
5688 23:19:33.556297 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5689 23:19:33.559554 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5690 23:19:33.560134 == TX Byte 1 ==
5691 23:19:33.565943 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5692 23:19:33.569245 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5693 23:19:33.569819 ==
5694 23:19:33.572660 Dram Type= 6, Freq= 0, CH_1, rank 1
5695 23:19:33.575641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5696 23:19:33.576214 ==
5697 23:19:33.576702
5698 23:19:33.578813
5699 23:19:33.579283 TX Vref Scan disable
5700 23:19:33.582323 == TX Byte 0 ==
5701 23:19:33.585202 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5702 23:19:33.588576 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5703 23:19:33.592092 == TX Byte 1 ==
5704 23:19:33.595560 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5705 23:19:33.599272 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5706 23:19:33.601772
5707 23:19:33.602245 [DATLAT]
5708 23:19:33.602724 Freq=933, CH1 RK1
5709 23:19:33.603177
5710 23:19:33.605705 DATLAT Default: 0xb
5711 23:19:33.606179 0, 0xFFFF, sum = 0
5712 23:19:33.608732 1, 0xFFFF, sum = 0
5713 23:19:33.609223 2, 0xFFFF, sum = 0
5714 23:19:33.612596 3, 0xFFFF, sum = 0
5715 23:19:33.613145 4, 0xFFFF, sum = 0
5716 23:19:33.615437 5, 0xFFFF, sum = 0
5717 23:19:33.618665 6, 0xFFFF, sum = 0
5718 23:19:33.619274 7, 0xFFFF, sum = 0
5719 23:19:33.622445 8, 0xFFFF, sum = 0
5720 23:19:33.623025 9, 0xFFFF, sum = 0
5721 23:19:33.624936 10, 0x0, sum = 1
5722 23:19:33.625420 11, 0x0, sum = 2
5723 23:19:33.625908 12, 0x0, sum = 3
5724 23:19:33.628297 13, 0x0, sum = 4
5725 23:19:33.628870 best_step = 11
5726 23:19:33.629355
5727 23:19:33.632045 ==
5728 23:19:33.635100 Dram Type= 6, Freq= 0, CH_1, rank 1
5729 23:19:33.638479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5730 23:19:33.639052 ==
5731 23:19:33.639546 RX Vref Scan: 0
5732 23:19:33.640010
5733 23:19:33.641691 RX Vref 0 -> 0, step: 1
5734 23:19:33.642165
5735 23:19:33.645240 RX Delay -77 -> 252, step: 4
5736 23:19:33.648802 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5737 23:19:33.655235 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5738 23:19:33.659275 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5739 23:19:33.662133 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5740 23:19:33.665375 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5741 23:19:33.668969 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5742 23:19:33.672112 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5743 23:19:33.678738 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5744 23:19:33.682181 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5745 23:19:33.685747 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5746 23:19:33.688014 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5747 23:19:33.691672 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5748 23:19:33.698260 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5749 23:19:33.701353 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5750 23:19:33.704928 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5751 23:19:33.708043 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5752 23:19:33.708747 ==
5753 23:19:33.711463 Dram Type= 6, Freq= 0, CH_1, rank 1
5754 23:19:33.715023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5755 23:19:33.717992 ==
5756 23:19:33.718467 DQS Delay:
5757 23:19:33.718950 DQS0 = 0, DQS1 = 0
5758 23:19:33.721248 DQM Delay:
5759 23:19:33.721727 DQM0 = 96, DQM1 = 87
5760 23:19:33.724773 DQ Delay:
5761 23:19:33.725345 DQ0 =98, DQ1 =92, DQ2 =88, DQ3 =92
5762 23:19:33.728051 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5763 23:19:33.731936 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5764 23:19:33.739312 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96
5765 23:19:33.739873
5766 23:19:33.740239
5767 23:19:33.744669 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5768 23:19:33.748335 CH1 RK1: MR19=505, MR18=2929
5769 23:19:33.755069 CH1_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5770 23:19:33.758378 [RxdqsGatingPostProcess] freq 933
5771 23:19:33.762045 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5772 23:19:33.764747 Pre-setting of DQS Precalculation
5773 23:19:33.771258 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5774 23:19:33.778093 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5775 23:19:33.785242 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5776 23:19:33.785801
5777 23:19:33.786165
5778 23:19:33.787676 [Calibration Summary] 1866 Mbps
5779 23:19:33.788155 CH 0, Rank 0
5780 23:19:33.791432 SW Impedance : PASS
5781 23:19:33.794993 DUTY Scan : NO K
5782 23:19:33.795469 ZQ Calibration : PASS
5783 23:19:33.797944 Jitter Meter : NO K
5784 23:19:33.801187 CBT Training : PASS
5785 23:19:33.801757 Write leveling : PASS
5786 23:19:33.805117 RX DQS gating : PASS
5787 23:19:33.808257 RX DQ/DQS(RDDQC) : PASS
5788 23:19:33.808946 TX DQ/DQS : PASS
5789 23:19:33.811155 RX DATLAT : PASS
5790 23:19:33.811695 RX DQ/DQS(Engine): PASS
5791 23:19:33.814157 TX OE : NO K
5792 23:19:33.814731 All Pass.
5793 23:19:33.815217
5794 23:19:33.817448 CH 0, Rank 1
5795 23:19:33.818033 SW Impedance : PASS
5796 23:19:33.821277 DUTY Scan : NO K
5797 23:19:33.824180 ZQ Calibration : PASS
5798 23:19:33.824656 Jitter Meter : NO K
5799 23:19:33.827941 CBT Training : PASS
5800 23:19:33.830954 Write leveling : PASS
5801 23:19:33.831527 RX DQS gating : PASS
5802 23:19:33.833881 RX DQ/DQS(RDDQC) : PASS
5803 23:19:33.837442 TX DQ/DQS : PASS
5804 23:19:33.838046 RX DATLAT : PASS
5805 23:19:33.841373 RX DQ/DQS(Engine): PASS
5806 23:19:33.844156 TX OE : NO K
5807 23:19:33.844636 All Pass.
5808 23:19:33.845160
5809 23:19:33.845618 CH 1, Rank 0
5810 23:19:33.847543 SW Impedance : PASS
5811 23:19:33.850629 DUTY Scan : NO K
5812 23:19:33.851112 ZQ Calibration : PASS
5813 23:19:33.854105 Jitter Meter : NO K
5814 23:19:33.858080 CBT Training : PASS
5815 23:19:33.858631 Write leveling : PASS
5816 23:19:33.860813 RX DQS gating : PASS
5817 23:19:33.863912 RX DQ/DQS(RDDQC) : PASS
5818 23:19:33.864467 TX DQ/DQS : PASS
5819 23:19:33.867008 RX DATLAT : PASS
5820 23:19:33.871002 RX DQ/DQS(Engine): PASS
5821 23:19:33.871564 TX OE : NO K
5822 23:19:33.871932 All Pass.
5823 23:19:33.874288
5824 23:19:33.874839 CH 1, Rank 1
5825 23:19:33.877221 SW Impedance : PASS
5826 23:19:33.877676 DUTY Scan : NO K
5827 23:19:33.881062 ZQ Calibration : PASS
5828 23:19:33.881516 Jitter Meter : NO K
5829 23:19:33.883793 CBT Training : PASS
5830 23:19:33.887413 Write leveling : PASS
5831 23:19:33.887885 RX DQS gating : PASS
5832 23:19:33.890691 RX DQ/DQS(RDDQC) : PASS
5833 23:19:33.893641 TX DQ/DQS : PASS
5834 23:19:33.894112 RX DATLAT : PASS
5835 23:19:33.896769 RX DQ/DQS(Engine): PASS
5836 23:19:33.900209 TX OE : NO K
5837 23:19:33.900664 All Pass.
5838 23:19:33.901075
5839 23:19:33.903563 DramC Write-DBI off
5840 23:19:33.904120 PER_BANK_REFRESH: Hybrid Mode
5841 23:19:33.907166 TX_TRACKING: ON
5842 23:19:33.916544 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5843 23:19:33.919979 [FAST_K] Save calibration result to emmc
5844 23:19:33.923279 dramc_set_vcore_voltage set vcore to 650000
5845 23:19:33.923739 Read voltage for 400, 6
5846 23:19:33.926688 Vio18 = 0
5847 23:19:33.927141 Vcore = 650000
5848 23:19:33.927495 Vdram = 0
5849 23:19:33.929919 Vddq = 0
5850 23:19:33.930375 Vmddr = 0
5851 23:19:33.932897 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5852 23:19:33.939794 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5853 23:19:33.943337 MEM_TYPE=3, freq_sel=20
5854 23:19:33.947349 sv_algorithm_assistance_LP4_800
5855 23:19:33.950133 ============ PULL DRAM RESETB DOWN ============
5856 23:19:33.953233 ========== PULL DRAM RESETB DOWN end =========
5857 23:19:33.959758 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5858 23:19:33.963026 ===================================
5859 23:19:33.963442 LPDDR4 DRAM CONFIGURATION
5860 23:19:33.966439 ===================================
5861 23:19:33.969839 EX_ROW_EN[0] = 0x0
5862 23:19:33.970256 EX_ROW_EN[1] = 0x0
5863 23:19:33.973260 LP4Y_EN = 0x0
5864 23:19:33.973823 WORK_FSP = 0x0
5865 23:19:33.976329 WL = 0x2
5866 23:19:33.979830 RL = 0x2
5867 23:19:33.980306 BL = 0x2
5868 23:19:33.983623 RPST = 0x0
5869 23:19:33.984196 RD_PRE = 0x0
5870 23:19:33.986143 WR_PRE = 0x1
5871 23:19:33.986618 WR_PST = 0x0
5872 23:19:33.989860 DBI_WR = 0x0
5873 23:19:33.990333 DBI_RD = 0x0
5874 23:19:33.992792 OTF = 0x1
5875 23:19:33.996496 ===================================
5876 23:19:33.999705 ===================================
5877 23:19:34.000282 ANA top config
5878 23:19:34.002895 ===================================
5879 23:19:34.006348 DLL_ASYNC_EN = 0
5880 23:19:34.010437 ALL_SLAVE_EN = 1
5881 23:19:34.011011 NEW_RANK_MODE = 1
5882 23:19:34.013127 DLL_IDLE_MODE = 1
5883 23:19:34.016340 LP45_APHY_COMB_EN = 1
5884 23:19:34.019495 TX_ODT_DIS = 1
5885 23:19:34.022916 NEW_8X_MODE = 1
5886 23:19:34.026452 ===================================
5887 23:19:34.029702 ===================================
5888 23:19:34.030272 data_rate = 800
5889 23:19:34.032581 CKR = 1
5890 23:19:34.036037 DQ_P2S_RATIO = 4
5891 23:19:34.039647 ===================================
5892 23:19:34.043052 CA_P2S_RATIO = 4
5893 23:19:34.046665 DQ_CA_OPEN = 0
5894 23:19:34.049337 DQ_SEMI_OPEN = 1
5895 23:19:34.049910 CA_SEMI_OPEN = 1
5896 23:19:34.053441 CA_FULL_RATE = 0
5897 23:19:34.056035 DQ_CKDIV4_EN = 0
5898 23:19:34.059208 CA_CKDIV4_EN = 1
5899 23:19:34.062347 CA_PREDIV_EN = 0
5900 23:19:34.065348 PH8_DLY = 0
5901 23:19:34.065828 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5902 23:19:34.068729 DQ_AAMCK_DIV = 0
5903 23:19:34.072218 CA_AAMCK_DIV = 0
5904 23:19:34.075669 CA_ADMCK_DIV = 4
5905 23:19:34.078964 DQ_TRACK_CA_EN = 0
5906 23:19:34.082269 CA_PICK = 800
5907 23:19:34.085332 CA_MCKIO = 400
5908 23:19:34.085793 MCKIO_SEMI = 400
5909 23:19:34.088639 PLL_FREQ = 3016
5910 23:19:34.092224 DQ_UI_PI_RATIO = 32
5911 23:19:34.095932 CA_UI_PI_RATIO = 32
5912 23:19:34.098894 ===================================
5913 23:19:34.102146 ===================================
5914 23:19:34.105749 memory_type:LPDDR4
5915 23:19:34.106211 GP_NUM : 10
5916 23:19:34.108878 SRAM_EN : 1
5917 23:19:34.111748 MD32_EN : 0
5918 23:19:34.115550 ===================================
5919 23:19:34.116111 [ANA_INIT] >>>>>>>>>>>>>>
5920 23:19:34.118541 <<<<<< [CONFIGURE PHASE]: ANA_TX
5921 23:19:34.121863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5922 23:19:34.125371 ===================================
5923 23:19:34.128968 data_rate = 800,PCW = 0X7400
5924 23:19:34.131979 ===================================
5925 23:19:34.135106 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5926 23:19:34.141831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5927 23:19:34.152163 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5928 23:19:34.158328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5929 23:19:34.161231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5930 23:19:34.165102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5931 23:19:34.165664 [ANA_INIT] flow start
5932 23:19:34.168519 [ANA_INIT] PLL >>>>>>>>
5933 23:19:34.171876 [ANA_INIT] PLL <<<<<<<<
5934 23:19:34.172459 [ANA_INIT] MIDPI >>>>>>>>
5935 23:19:34.174364 [ANA_INIT] MIDPI <<<<<<<<
5936 23:19:34.178178 [ANA_INIT] DLL >>>>>>>>
5937 23:19:34.178741 [ANA_INIT] flow end
5938 23:19:34.184647 ============ LP4 DIFF to SE enter ============
5939 23:19:34.187857 ============ LP4 DIFF to SE exit ============
5940 23:19:34.191364 [ANA_INIT] <<<<<<<<<<<<<
5941 23:19:34.194702 [Flow] Enable top DCM control >>>>>
5942 23:19:34.197587 [Flow] Enable top DCM control <<<<<
5943 23:19:34.198051 Enable DLL master slave shuffle
5944 23:19:34.205062 ==============================================================
5945 23:19:34.208488 Gating Mode config
5946 23:19:34.211615 ==============================================================
5947 23:19:34.215303 Config description:
5948 23:19:34.225071 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5949 23:19:34.231776 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5950 23:19:34.235512 SELPH_MODE 0: By rank 1: By Phase
5951 23:19:34.241010 ==============================================================
5952 23:19:34.245004 GAT_TRACK_EN = 0
5953 23:19:34.247315 RX_GATING_MODE = 2
5954 23:19:34.250893 RX_GATING_TRACK_MODE = 2
5955 23:19:34.254273 SELPH_MODE = 1
5956 23:19:34.257220 PICG_EARLY_EN = 1
5957 23:19:34.257684 VALID_LAT_VALUE = 1
5958 23:19:34.265226 ==============================================================
5959 23:19:34.268243 Enter into Gating configuration >>>>
5960 23:19:34.270690 Exit from Gating configuration <<<<
5961 23:19:34.274931 Enter into DVFS_PRE_config >>>>>
5962 23:19:34.284418 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5963 23:19:34.287201 Exit from DVFS_PRE_config <<<<<
5964 23:19:34.290621 Enter into PICG configuration >>>>
5965 23:19:34.293344 Exit from PICG configuration <<<<
5966 23:19:34.297130 [RX_INPUT] configuration >>>>>
5967 23:19:34.300387 [RX_INPUT] configuration <<<<<
5968 23:19:34.303827 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5969 23:19:34.310272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5970 23:19:34.317081 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5971 23:19:34.323935 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5972 23:19:34.330642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5973 23:19:34.337633 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5974 23:19:34.340425 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5975 23:19:34.344163 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5976 23:19:34.347146 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5977 23:19:34.350557 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5978 23:19:34.356896 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5979 23:19:34.360244 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5980 23:19:34.363793 ===================================
5981 23:19:34.368192 LPDDR4 DRAM CONFIGURATION
5982 23:19:34.370922 ===================================
5983 23:19:34.371497 EX_ROW_EN[0] = 0x0
5984 23:19:34.373943 EX_ROW_EN[1] = 0x0
5985 23:19:34.374499 LP4Y_EN = 0x0
5986 23:19:34.376769 WORK_FSP = 0x0
5987 23:19:34.377325 WL = 0x2
5988 23:19:34.380474 RL = 0x2
5989 23:19:34.383877 BL = 0x2
5990 23:19:34.384430 RPST = 0x0
5991 23:19:34.386914 RD_PRE = 0x0
5992 23:19:34.387469 WR_PRE = 0x1
5993 23:19:34.389828 WR_PST = 0x0
5994 23:19:34.390288 DBI_WR = 0x0
5995 23:19:34.394006 DBI_RD = 0x0
5996 23:19:34.394467 OTF = 0x1
5997 23:19:34.396777 ===================================
5998 23:19:34.399726 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5999 23:19:34.406385 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6000 23:19:34.409728 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6001 23:19:34.413362 ===================================
6002 23:19:34.416875 LPDDR4 DRAM CONFIGURATION
6003 23:19:34.419824 ===================================
6004 23:19:34.420286 EX_ROW_EN[0] = 0x10
6005 23:19:34.422817 EX_ROW_EN[1] = 0x0
6006 23:19:34.423293 LP4Y_EN = 0x0
6007 23:19:34.426132 WORK_FSP = 0x0
6008 23:19:34.426590 WL = 0x2
6009 23:19:34.429671 RL = 0x2
6010 23:19:34.434075 BL = 0x2
6011 23:19:34.434632 RPST = 0x0
6012 23:19:34.436491 RD_PRE = 0x0
6013 23:19:34.436990 WR_PRE = 0x1
6014 23:19:34.441122 WR_PST = 0x0
6015 23:19:34.441682 DBI_WR = 0x0
6016 23:19:34.443067 DBI_RD = 0x0
6017 23:19:34.443529 OTF = 0x1
6018 23:19:34.446061 ===================================
6019 23:19:34.453359 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6020 23:19:34.456826 nWR fixed to 30
6021 23:19:34.460164 [ModeRegInit_LP4] CH0 RK0
6022 23:19:34.460774 [ModeRegInit_LP4] CH0 RK1
6023 23:19:34.463407 [ModeRegInit_LP4] CH1 RK0
6024 23:19:34.467327 [ModeRegInit_LP4] CH1 RK1
6025 23:19:34.467881 match AC timing 18
6026 23:19:34.473643 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6027 23:19:34.477441 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6028 23:19:34.480366 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6029 23:19:34.486647 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6030 23:19:34.490422 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6031 23:19:34.491022 ==
6032 23:19:34.493354 Dram Type= 6, Freq= 0, CH_0, rank 0
6033 23:19:34.496824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6034 23:19:34.497445 ==
6035 23:19:34.502891 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6036 23:19:34.509812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6037 23:19:34.513503 [CA 0] Center 36 (8~64) winsize 57
6038 23:19:34.516595 [CA 1] Center 36 (8~64) winsize 57
6039 23:19:34.519998 [CA 2] Center 36 (8~64) winsize 57
6040 23:19:34.520461 [CA 3] Center 36 (8~64) winsize 57
6041 23:19:34.523437 [CA 4] Center 36 (8~64) winsize 57
6042 23:19:34.526269 [CA 5] Center 36 (8~64) winsize 57
6043 23:19:34.526730
6044 23:19:34.533291 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6045 23:19:34.533847
6046 23:19:34.537190 [CATrainingPosCal] consider 1 rank data
6047 23:19:34.537750 u2DelayCellTimex100 = 270/100 ps
6048 23:19:34.544042 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6049 23:19:34.547007 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6050 23:19:34.549559 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6051 23:19:34.553507 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6052 23:19:34.556396 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6053 23:19:34.559870 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6054 23:19:34.560431
6055 23:19:34.563683 CA PerBit enable=1, Macro0, CA PI delay=36
6056 23:19:34.564237
6057 23:19:34.566675 [CBTSetCACLKResult] CA Dly = 36
6058 23:19:34.569717 CS Dly: 1 (0~32)
6059 23:19:34.570180 ==
6060 23:19:34.573497 Dram Type= 6, Freq= 0, CH_0, rank 1
6061 23:19:34.576511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6062 23:19:34.577125 ==
6063 23:19:34.583048 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6064 23:19:34.586992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6065 23:19:34.590392 [CA 0] Center 36 (8~64) winsize 57
6066 23:19:34.593068 [CA 1] Center 36 (8~64) winsize 57
6067 23:19:34.595945 [CA 2] Center 36 (8~64) winsize 57
6068 23:19:34.599644 [CA 3] Center 36 (8~64) winsize 57
6069 23:19:34.602959 [CA 4] Center 36 (8~64) winsize 57
6070 23:19:34.606615 [CA 5] Center 36 (8~64) winsize 57
6071 23:19:34.607078
6072 23:19:34.609320 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6073 23:19:34.609780
6074 23:19:34.612799 [CATrainingPosCal] consider 2 rank data
6075 23:19:34.616168 u2DelayCellTimex100 = 270/100 ps
6076 23:19:34.619473 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6077 23:19:34.623269 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6078 23:19:34.629293 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6079 23:19:34.632752 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6080 23:19:34.636948 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6081 23:19:34.638720 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6082 23:19:34.639180
6083 23:19:34.642938 CA PerBit enable=1, Macro0, CA PI delay=36
6084 23:19:34.643502
6085 23:19:34.645861 [CBTSetCACLKResult] CA Dly = 36
6086 23:19:34.646323 CS Dly: 1 (0~32)
6087 23:19:34.648933
6088 23:19:34.652460 ----->DramcWriteLeveling(PI) begin...
6089 23:19:34.653087 ==
6090 23:19:34.655572 Dram Type= 6, Freq= 0, CH_0, rank 0
6091 23:19:34.659252 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6092 23:19:34.659826 ==
6093 23:19:34.661651 Write leveling (Byte 0): 32 => 0
6094 23:19:34.665208 Write leveling (Byte 1): 32 => 0
6095 23:19:34.669178 DramcWriteLeveling(PI) end<-----
6096 23:19:34.669740
6097 23:19:34.670106 ==
6098 23:19:34.671863 Dram Type= 6, Freq= 0, CH_0, rank 0
6099 23:19:34.675412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6100 23:19:34.675979 ==
6101 23:19:34.678925 [Gating] SW mode calibration
6102 23:19:34.685806 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6103 23:19:34.691740 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6104 23:19:34.695390 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6105 23:19:34.698966 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6106 23:19:34.704833 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6107 23:19:34.707832 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6108 23:19:34.711729 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6109 23:19:34.717984 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6110 23:19:34.721405 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6111 23:19:34.724666 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6112 23:19:34.731356 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6113 23:19:34.731905 Total UI for P1: 0, mck2ui 16
6114 23:19:34.738032 best dqsien dly found for B0: ( 0, 10, 16)
6115 23:19:34.738608 Total UI for P1: 0, mck2ui 16
6116 23:19:34.741863 best dqsien dly found for B1: ( 0, 10, 16)
6117 23:19:34.748051 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6118 23:19:34.751330 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6119 23:19:34.751889
6120 23:19:34.754612 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6121 23:19:34.757598 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6122 23:19:34.761092 [Gating] SW calibration Done
6123 23:19:34.761648 ==
6124 23:19:34.764074 Dram Type= 6, Freq= 0, CH_0, rank 0
6125 23:19:34.767890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6126 23:19:34.768389 ==
6127 23:19:34.771025 RX Vref Scan: 0
6128 23:19:34.771594
6129 23:19:34.772011 RX Vref 0 -> 0, step: 1
6130 23:19:34.772371
6131 23:19:34.774186 RX Delay -410 -> 252, step: 16
6132 23:19:34.781314 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6133 23:19:34.784183 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6134 23:19:34.787966 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6135 23:19:34.790931 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6136 23:19:34.797564 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6137 23:19:34.801569 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6138 23:19:34.804115 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6139 23:19:34.807276 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6140 23:19:34.814043 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6141 23:19:34.817097 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6142 23:19:34.820554 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6143 23:19:34.823607 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6144 23:19:34.830602 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6145 23:19:34.833673 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6146 23:19:34.836826 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6147 23:19:34.843727 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6148 23:19:34.844286 ==
6149 23:19:34.846935 Dram Type= 6, Freq= 0, CH_0, rank 0
6150 23:19:34.850846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6151 23:19:34.851316 ==
6152 23:19:34.851684 DQS Delay:
6153 23:19:34.853212 DQS0 = 51, DQS1 = 59
6154 23:19:34.853678 DQM Delay:
6155 23:19:34.856973 DQM0 = 12, DQM1 = 13
6156 23:19:34.857541 DQ Delay:
6157 23:19:34.861084 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6158 23:19:34.864016 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6159 23:19:34.866835 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6160 23:19:34.870235 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6161 23:19:34.870800
6162 23:19:34.871213
6163 23:19:34.871566 ==
6164 23:19:34.873811 Dram Type= 6, Freq= 0, CH_0, rank 0
6165 23:19:34.876879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6166 23:19:34.877602 ==
6167 23:19:34.878075
6168 23:19:34.878426
6169 23:19:34.880109 TX Vref Scan disable
6170 23:19:34.883342 == TX Byte 0 ==
6171 23:19:34.886451 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6172 23:19:34.890299 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6173 23:19:34.893304 == TX Byte 1 ==
6174 23:19:34.896499 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6175 23:19:34.900304 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6176 23:19:34.900951 ==
6177 23:19:34.903657 Dram Type= 6, Freq= 0, CH_0, rank 0
6178 23:19:34.907156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6179 23:19:34.907748 ==
6180 23:19:34.909726
6181 23:19:34.910185
6182 23:19:34.910546 TX Vref Scan disable
6183 23:19:34.912844 == TX Byte 0 ==
6184 23:19:34.916541 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6185 23:19:34.920167 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6186 23:19:34.923038 == TX Byte 1 ==
6187 23:19:34.926099 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6188 23:19:34.929975 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6189 23:19:34.930555
6190 23:19:34.933127 [DATLAT]
6191 23:19:34.933684 Freq=400, CH0 RK0
6192 23:19:34.934057
6193 23:19:34.936611 DATLAT Default: 0xf
6194 23:19:34.937217 0, 0xFFFF, sum = 0
6195 23:19:34.940272 1, 0xFFFF, sum = 0
6196 23:19:34.940916 2, 0xFFFF, sum = 0
6197 23:19:34.943222 3, 0xFFFF, sum = 0
6198 23:19:34.943788 4, 0xFFFF, sum = 0
6199 23:19:34.946364 5, 0xFFFF, sum = 0
6200 23:19:34.946930 6, 0xFFFF, sum = 0
6201 23:19:34.949800 7, 0xFFFF, sum = 0
6202 23:19:34.950366 8, 0xFFFF, sum = 0
6203 23:19:34.953320 9, 0xFFFF, sum = 0
6204 23:19:34.953794 10, 0xFFFF, sum = 0
6205 23:19:34.956266 11, 0xFFFF, sum = 0
6206 23:19:34.956877 12, 0x0, sum = 1
6207 23:19:34.959519 13, 0x0, sum = 2
6208 23:19:34.959994 14, 0x0, sum = 3
6209 23:19:34.963442 15, 0x0, sum = 4
6210 23:19:34.964012 best_step = 13
6211 23:19:34.964377
6212 23:19:34.964759 ==
6213 23:19:34.965993 Dram Type= 6, Freq= 0, CH_0, rank 0
6214 23:19:34.972561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6215 23:19:34.973160 ==
6216 23:19:34.973527 RX Vref Scan: 1
6217 23:19:34.973871
6218 23:19:34.975746 RX Vref 0 -> 0, step: 1
6219 23:19:34.976208
6220 23:19:34.979570 RX Delay -359 -> 252, step: 8
6221 23:19:34.980033
6222 23:19:34.982743 Set Vref, RX VrefLevel [Byte0]: 55
6223 23:19:34.985882 [Byte1]: 48
6224 23:19:34.989051
6225 23:19:34.989514 Final RX Vref Byte 0 = 55 to rank0
6226 23:19:34.992258 Final RX Vref Byte 1 = 48 to rank0
6227 23:19:34.996351 Final RX Vref Byte 0 = 55 to rank1
6228 23:19:34.998991 Final RX Vref Byte 1 = 48 to rank1==
6229 23:19:35.003078 Dram Type= 6, Freq= 0, CH_0, rank 0
6230 23:19:35.009010 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6231 23:19:35.009475 ==
6232 23:19:35.009841 DQS Delay:
6233 23:19:35.012595 DQS0 = 56, DQS1 = 68
6234 23:19:35.013282 DQM Delay:
6235 23:19:35.013789 DQM0 = 12, DQM1 = 17
6236 23:19:35.015857 DQ Delay:
6237 23:19:35.019845 DQ0 =8, DQ1 =12, DQ2 =12, DQ3 =12
6238 23:19:35.022303 DQ4 =16, DQ5 =0, DQ6 =20, DQ7 =20
6239 23:19:35.023087 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6240 23:19:35.028815 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6241 23:19:35.029485
6242 23:19:35.030163
6243 23:19:35.036319 [DQSOSCAuto] RK0, (LSB)MR18= 0xaaaa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6244 23:19:35.039009 CH0 RK0: MR19=C0C, MR18=AAAA
6245 23:19:35.045609 CH0_RK0: MR19=0xC0C, MR18=0xAAAA, DQSOSC=388, MR23=63, INC=392, DEC=261
6246 23:19:35.046172 ==
6247 23:19:35.048611 Dram Type= 6, Freq= 0, CH_0, rank 1
6248 23:19:35.051832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6249 23:19:35.052364 ==
6250 23:19:35.055088 [Gating] SW mode calibration
6251 23:19:35.061511 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6252 23:19:35.068573 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6253 23:19:35.071449 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6254 23:19:35.075209 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6255 23:19:35.081669 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6256 23:19:35.084836 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6257 23:19:35.087963 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6258 23:19:35.094723 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6259 23:19:35.098574 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6260 23:19:35.101259 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6261 23:19:35.107993 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6262 23:19:35.108554 Total UI for P1: 0, mck2ui 16
6263 23:19:35.115120 best dqsien dly found for B0: ( 0, 10, 16)
6264 23:19:35.115576 Total UI for P1: 0, mck2ui 16
6265 23:19:35.121245 best dqsien dly found for B1: ( 0, 10, 16)
6266 23:19:35.125410 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6267 23:19:35.127918 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6268 23:19:35.128381
6269 23:19:35.131272 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6270 23:19:35.134977 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6271 23:19:35.138482 [Gating] SW calibration Done
6272 23:19:35.139004 ==
6273 23:19:35.141210 Dram Type= 6, Freq= 0, CH_0, rank 1
6274 23:19:35.144481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6275 23:19:35.144985 ==
6276 23:19:35.147897 RX Vref Scan: 0
6277 23:19:35.148455
6278 23:19:35.148867 RX Vref 0 -> 0, step: 1
6279 23:19:35.151327
6280 23:19:35.152000 RX Delay -410 -> 252, step: 16
6281 23:19:35.157427 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6282 23:19:35.161014 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6283 23:19:35.164361 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6284 23:19:35.167989 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6285 23:19:35.174836 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6286 23:19:35.177701 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6287 23:19:35.181320 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6288 23:19:35.184067 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6289 23:19:35.191261 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6290 23:19:35.193949 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6291 23:19:35.197556 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6292 23:19:35.201177 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6293 23:19:35.208639 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6294 23:19:35.210573 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6295 23:19:35.214353 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6296 23:19:35.220888 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6297 23:19:35.221515 ==
6298 23:19:35.223849 Dram Type= 6, Freq= 0, CH_0, rank 1
6299 23:19:35.227878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6300 23:19:35.228440 ==
6301 23:19:35.228873 DQS Delay:
6302 23:19:35.231033 DQS0 = 43, DQS1 = 59
6303 23:19:35.231593 DQM Delay:
6304 23:19:35.233667 DQM0 = 7, DQM1 = 15
6305 23:19:35.234173 DQ Delay:
6306 23:19:35.237234 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6307 23:19:35.240349 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6308 23:19:35.243853 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6309 23:19:35.247669 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6310 23:19:35.248228
6311 23:19:35.248590
6312 23:19:35.248973 ==
6313 23:19:35.250394 Dram Type= 6, Freq= 0, CH_0, rank 1
6314 23:19:35.254122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6315 23:19:35.254660 ==
6316 23:19:35.255018
6317 23:19:35.255349
6318 23:19:35.256561 TX Vref Scan disable
6319 23:19:35.260114 == TX Byte 0 ==
6320 23:19:35.263193 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6321 23:19:35.267735 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6322 23:19:35.268292 == TX Byte 1 ==
6323 23:19:35.273663 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6324 23:19:35.276849 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6325 23:19:35.277408 ==
6326 23:19:35.279760 Dram Type= 6, Freq= 0, CH_0, rank 1
6327 23:19:35.283203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6328 23:19:35.283667 ==
6329 23:19:35.284028
6330 23:19:35.286223
6331 23:19:35.286610 TX Vref Scan disable
6332 23:19:35.289676 == TX Byte 0 ==
6333 23:19:35.293817 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6334 23:19:35.295922 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6335 23:19:35.299556 == TX Byte 1 ==
6336 23:19:35.302631 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6337 23:19:35.306197 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6338 23:19:35.306749
6339 23:19:35.307114 [DATLAT]
6340 23:19:35.309479 Freq=400, CH0 RK1
6341 23:19:35.309935
6342 23:19:35.310292 DATLAT Default: 0xd
6343 23:19:35.312843 0, 0xFFFF, sum = 0
6344 23:19:35.316269 1, 0xFFFF, sum = 0
6345 23:19:35.316775 2, 0xFFFF, sum = 0
6346 23:19:35.319449 3, 0xFFFF, sum = 0
6347 23:19:35.319985 4, 0xFFFF, sum = 0
6348 23:19:35.322533 5, 0xFFFF, sum = 0
6349 23:19:35.322998 6, 0xFFFF, sum = 0
6350 23:19:35.326291 7, 0xFFFF, sum = 0
6351 23:19:35.326757 8, 0xFFFF, sum = 0
6352 23:19:35.329727 9, 0xFFFF, sum = 0
6353 23:19:35.330197 10, 0xFFFF, sum = 0
6354 23:19:35.333366 11, 0xFFFF, sum = 0
6355 23:19:35.333832 12, 0x0, sum = 1
6356 23:19:35.336228 13, 0x0, sum = 2
6357 23:19:35.336852 14, 0x0, sum = 3
6358 23:19:35.339838 15, 0x0, sum = 4
6359 23:19:35.340399 best_step = 13
6360 23:19:35.340805
6361 23:19:35.341145 ==
6362 23:19:35.342656 Dram Type= 6, Freq= 0, CH_0, rank 1
6363 23:19:35.345671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6364 23:19:35.348924 ==
6365 23:19:35.349398 RX Vref Scan: 0
6366 23:19:35.349763
6367 23:19:35.352826 RX Vref 0 -> 0, step: 1
6368 23:19:35.353287
6369 23:19:35.355813 RX Delay -359 -> 252, step: 8
6370 23:19:35.362615 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6371 23:19:35.365156 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6372 23:19:35.368915 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6373 23:19:35.372217 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6374 23:19:35.379141 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6375 23:19:35.382251 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6376 23:19:35.386072 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6377 23:19:35.389418 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6378 23:19:35.395430 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6379 23:19:35.398771 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6380 23:19:35.402160 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6381 23:19:35.405385 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6382 23:19:35.411769 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6383 23:19:35.415368 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6384 23:19:35.419233 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6385 23:19:35.424999 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6386 23:19:35.425460 ==
6387 23:19:35.428879 Dram Type= 6, Freq= 0, CH_0, rank 1
6388 23:19:35.432983 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6389 23:19:35.433545 ==
6390 23:19:35.433908 DQS Delay:
6391 23:19:35.436296 DQS0 = 52, DQS1 = 64
6392 23:19:35.436888 DQM Delay:
6393 23:19:35.438635 DQM0 = 10, DQM1 = 13
6394 23:19:35.439201 DQ Delay:
6395 23:19:35.442064 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6396 23:19:35.445380 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6397 23:19:35.448743 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6398 23:19:35.451917 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6399 23:19:35.452467
6400 23:19:35.452880
6401 23:19:35.457820 [DQSOSCAuto] RK1, (LSB)MR18= 0xc6c6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6402 23:19:35.461682 CH0 RK1: MR19=C0C, MR18=C6C6
6403 23:19:35.468054 CH0_RK1: MR19=0xC0C, MR18=0xC6C6, DQSOSC=385, MR23=63, INC=398, DEC=265
6404 23:19:35.472018 [RxdqsGatingPostProcess] freq 400
6405 23:19:35.478246 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6406 23:19:35.478705 Pre-setting of DQS Precalculation
6407 23:19:35.485380 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6408 23:19:35.485937 ==
6409 23:19:35.488024 Dram Type= 6, Freq= 0, CH_1, rank 0
6410 23:19:35.491314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6411 23:19:35.491882 ==
6412 23:19:35.498349 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6413 23:19:35.504698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6414 23:19:35.508370 [CA 0] Center 36 (8~64) winsize 57
6415 23:19:35.511254 [CA 1] Center 36 (8~64) winsize 57
6416 23:19:35.514041 [CA 2] Center 36 (8~64) winsize 57
6417 23:19:35.518150 [CA 3] Center 36 (8~64) winsize 57
6418 23:19:35.518703 [CA 4] Center 36 (8~64) winsize 57
6419 23:19:35.520654 [CA 5] Center 36 (8~64) winsize 57
6420 23:19:35.524227
6421 23:19:35.527545 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6422 23:19:35.528100
6423 23:19:35.531165 [CATrainingPosCal] consider 1 rank data
6424 23:19:35.533756 u2DelayCellTimex100 = 270/100 ps
6425 23:19:35.537444 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6426 23:19:35.540480 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6427 23:19:35.544873 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6428 23:19:35.547795 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6429 23:19:35.550663 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6430 23:19:35.553923 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6431 23:19:35.554478
6432 23:19:35.557002 CA PerBit enable=1, Macro0, CA PI delay=36
6433 23:19:35.557554
6434 23:19:35.560832 [CBTSetCACLKResult] CA Dly = 36
6435 23:19:35.564159 CS Dly: 1 (0~32)
6436 23:19:35.564753 ==
6437 23:19:35.567662 Dram Type= 6, Freq= 0, CH_1, rank 1
6438 23:19:35.570557 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6439 23:19:35.571116 ==
6440 23:19:35.577298 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6441 23:19:35.583595 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6442 23:19:35.586741 [CA 0] Center 36 (8~64) winsize 57
6443 23:19:35.590318 [CA 1] Center 36 (8~64) winsize 57
6444 23:19:35.590877 [CA 2] Center 36 (8~64) winsize 57
6445 23:19:35.593417 [CA 3] Center 36 (8~64) winsize 57
6446 23:19:35.597435 [CA 4] Center 36 (8~64) winsize 57
6447 23:19:35.600816 [CA 5] Center 36 (8~64) winsize 57
6448 23:19:35.601276
6449 23:19:35.603909 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6450 23:19:35.604673
6451 23:19:35.611507 [CATrainingPosCal] consider 2 rank data
6452 23:19:35.612106 u2DelayCellTimex100 = 270/100 ps
6453 23:19:35.617945 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6454 23:19:35.620127 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6455 23:19:35.623265 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6456 23:19:35.626983 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6457 23:19:35.630842 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6458 23:19:35.633465 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6459 23:19:35.633929
6460 23:19:35.637634 CA PerBit enable=1, Macro0, CA PI delay=36
6461 23:19:35.638190
6462 23:19:35.640444 [CBTSetCACLKResult] CA Dly = 36
6463 23:19:35.643512 CS Dly: 1 (0~32)
6464 23:19:35.644062
6465 23:19:35.646996 ----->DramcWriteLeveling(PI) begin...
6466 23:19:35.647556 ==
6467 23:19:35.650267 Dram Type= 6, Freq= 0, CH_1, rank 0
6468 23:19:35.653382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6469 23:19:35.653942 ==
6470 23:19:35.656220 Write leveling (Byte 0): 32 => 0
6471 23:19:35.660231 Write leveling (Byte 1): 32 => 0
6472 23:19:35.662921 DramcWriteLeveling(PI) end<-----
6473 23:19:35.663479
6474 23:19:35.663841 ==
6475 23:19:35.666763 Dram Type= 6, Freq= 0, CH_1, rank 0
6476 23:19:35.669538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6477 23:19:35.670102 ==
6478 23:19:35.672973 [Gating] SW mode calibration
6479 23:19:35.679571 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6480 23:19:35.686603 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6481 23:19:35.689247 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6482 23:19:35.692968 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6483 23:19:35.699449 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6484 23:19:35.702620 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6485 23:19:35.706285 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 23:19:35.712820 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 23:19:35.715570 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 23:19:35.719845 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6489 23:19:35.726151 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6490 23:19:35.726616 Total UI for P1: 0, mck2ui 16
6491 23:19:35.732305 best dqsien dly found for B0: ( 0, 10, 16)
6492 23:19:35.732895 Total UI for P1: 0, mck2ui 16
6493 23:19:35.738886 best dqsien dly found for B1: ( 0, 10, 16)
6494 23:19:35.742851 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6495 23:19:35.745578 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6496 23:19:35.746133
6497 23:19:35.748970 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6498 23:19:35.752770 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6499 23:19:35.755350 [Gating] SW calibration Done
6500 23:19:35.755907 ==
6501 23:19:35.759323 Dram Type= 6, Freq= 0, CH_1, rank 0
6502 23:19:35.762987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6503 23:19:35.763543 ==
6504 23:19:35.765229 RX Vref Scan: 0
6505 23:19:35.765690
6506 23:19:35.768592 RX Vref 0 -> 0, step: 1
6507 23:19:35.769091
6508 23:19:35.769457 RX Delay -410 -> 252, step: 16
6509 23:19:35.775847 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6510 23:19:35.778740 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6511 23:19:35.781833 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6512 23:19:35.789108 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6513 23:19:35.791911 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6514 23:19:35.795919 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6515 23:19:35.798584 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6516 23:19:35.805525 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6517 23:19:35.807981 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6518 23:19:35.811840 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6519 23:19:35.815077 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6520 23:19:35.822416 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6521 23:19:35.824618 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6522 23:19:35.828146 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6523 23:19:35.831928 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6524 23:19:35.837895 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6525 23:19:35.838451 ==
6526 23:19:35.841549 Dram Type= 6, Freq= 0, CH_1, rank 0
6527 23:19:35.844636 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6528 23:19:35.845225 ==
6529 23:19:35.845598 DQS Delay:
6530 23:19:35.847777 DQS0 = 43, DQS1 = 59
6531 23:19:35.848235 DQM Delay:
6532 23:19:35.851822 DQM0 = 6, DQM1 = 15
6533 23:19:35.852375 DQ Delay:
6534 23:19:35.854245 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6535 23:19:35.857733 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6536 23:19:35.861407 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6537 23:19:35.864757 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6538 23:19:35.865320
6539 23:19:35.865685
6540 23:19:35.866025 ==
6541 23:19:35.867231 Dram Type= 6, Freq= 0, CH_1, rank 0
6542 23:19:35.870817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6543 23:19:35.871281 ==
6544 23:19:35.871645
6545 23:19:35.874237
6546 23:19:35.874789 TX Vref Scan disable
6547 23:19:35.878036 == TX Byte 0 ==
6548 23:19:35.880926 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6549 23:19:35.883814 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6550 23:19:35.887354 == TX Byte 1 ==
6551 23:19:35.891092 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6552 23:19:35.894123 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6553 23:19:35.894700 ==
6554 23:19:35.897046 Dram Type= 6, Freq= 0, CH_1, rank 0
6555 23:19:35.904081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6556 23:19:35.904560 ==
6557 23:19:35.905013
6558 23:19:35.905358
6559 23:19:35.905682 TX Vref Scan disable
6560 23:19:35.907722 == TX Byte 0 ==
6561 23:19:35.910665 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6562 23:19:35.914100 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6563 23:19:35.916812 == TX Byte 1 ==
6564 23:19:35.920298 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6565 23:19:35.923993 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6566 23:19:35.924550
6567 23:19:35.926939 [DATLAT]
6568 23:19:35.927592 Freq=400, CH1 RK0
6569 23:19:35.927989
6570 23:19:35.930622 DATLAT Default: 0xf
6571 23:19:35.931170 0, 0xFFFF, sum = 0
6572 23:19:35.933695 1, 0xFFFF, sum = 0
6573 23:19:35.934163 2, 0xFFFF, sum = 0
6574 23:19:35.937450 3, 0xFFFF, sum = 0
6575 23:19:35.938018 4, 0xFFFF, sum = 0
6576 23:19:35.940948 5, 0xFFFF, sum = 0
6577 23:19:35.941516 6, 0xFFFF, sum = 0
6578 23:19:35.944305 7, 0xFFFF, sum = 0
6579 23:19:35.947177 8, 0xFFFF, sum = 0
6580 23:19:35.947742 9, 0xFFFF, sum = 0
6581 23:19:35.950906 10, 0xFFFF, sum = 0
6582 23:19:35.951470 11, 0xFFFF, sum = 0
6583 23:19:35.953703 12, 0x0, sum = 1
6584 23:19:35.954170 13, 0x0, sum = 2
6585 23:19:35.957310 14, 0x0, sum = 3
6586 23:19:35.957878 15, 0x0, sum = 4
6587 23:19:35.958253 best_step = 13
6588 23:19:35.959703
6589 23:19:35.960161 ==
6590 23:19:35.964110 Dram Type= 6, Freq= 0, CH_1, rank 0
6591 23:19:35.967103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6592 23:19:35.967662 ==
6593 23:19:35.968030 RX Vref Scan: 1
6594 23:19:35.968371
6595 23:19:35.969620 RX Vref 0 -> 0, step: 1
6596 23:19:35.970081
6597 23:19:35.973968 RX Delay -359 -> 252, step: 8
6598 23:19:35.974520
6599 23:19:35.976933 Set Vref, RX VrefLevel [Byte0]: 54
6600 23:19:35.979879 [Byte1]: 49
6601 23:19:35.983959
6602 23:19:35.984512 Final RX Vref Byte 0 = 54 to rank0
6603 23:19:35.987213 Final RX Vref Byte 1 = 49 to rank0
6604 23:19:35.990391 Final RX Vref Byte 0 = 54 to rank1
6605 23:19:35.993592 Final RX Vref Byte 1 = 49 to rank1==
6606 23:19:35.997161 Dram Type= 6, Freq= 0, CH_1, rank 0
6607 23:19:36.003461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6608 23:19:36.003925 ==
6609 23:19:36.004285 DQS Delay:
6610 23:19:36.006792 DQS0 = 48, DQS1 = 64
6611 23:19:36.007167 DQM Delay:
6612 23:19:36.007497 DQM0 = 8, DQM1 = 16
6613 23:19:36.009817 DQ Delay:
6614 23:19:36.013847 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6615 23:19:36.014305 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6616 23:19:36.016981 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6617 23:19:36.020887 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6618 23:19:36.021440
6619 23:19:36.023581
6620 23:19:36.029913 [DQSOSCAuto] RK0, (LSB)MR18= 0xd3d3, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6621 23:19:36.033806 CH1 RK0: MR19=C0C, MR18=D3D3
6622 23:19:36.040391 CH1_RK0: MR19=0xC0C, MR18=0xD3D3, DQSOSC=383, MR23=63, INC=402, DEC=268
6623 23:19:36.041050 ==
6624 23:19:36.043548 Dram Type= 6, Freq= 0, CH_1, rank 1
6625 23:19:36.046886 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6626 23:19:36.047445 ==
6627 23:19:36.049846 [Gating] SW mode calibration
6628 23:19:36.056550 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6629 23:19:36.063069 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6630 23:19:36.066350 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6631 23:19:36.070222 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6632 23:19:36.076197 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6633 23:19:36.079485 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6634 23:19:36.083309 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6635 23:19:36.090139 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6636 23:19:36.092701 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6637 23:19:36.096363 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6638 23:19:36.099857 Total UI for P1: 0, mck2ui 16
6639 23:19:36.103092 best dqsien dly found for B0: ( 0, 10, 8)
6640 23:19:36.106314 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6641 23:19:36.109263 Total UI for P1: 0, mck2ui 16
6642 23:19:36.112949 best dqsien dly found for B1: ( 0, 10, 16)
6643 23:19:36.119473 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6644 23:19:36.123257 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6645 23:19:36.123917
6646 23:19:36.126286 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6647 23:19:36.128755 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6648 23:19:36.132401 [Gating] SW calibration Done
6649 23:19:36.133015 ==
6650 23:19:36.135789 Dram Type= 6, Freq= 0, CH_1, rank 1
6651 23:19:36.139336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6652 23:19:36.139903 ==
6653 23:19:36.143104 RX Vref Scan: 0
6654 23:19:36.143660
6655 23:19:36.144026 RX Vref 0 -> 0, step: 1
6656 23:19:36.144360
6657 23:19:36.145585 RX Delay -410 -> 252, step: 16
6658 23:19:36.153065 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6659 23:19:36.155452 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6660 23:19:36.158828 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6661 23:19:36.162308 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6662 23:19:36.168912 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6663 23:19:36.172244 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6664 23:19:36.176046 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6665 23:19:36.179219 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6666 23:19:36.185241 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6667 23:19:36.189440 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6668 23:19:36.191986 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6669 23:19:36.195225 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6670 23:19:36.201723 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6671 23:19:36.205814 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6672 23:19:36.209149 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6673 23:19:36.211682 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6674 23:19:36.215023 ==
6675 23:19:36.218873 Dram Type= 6, Freq= 0, CH_1, rank 1
6676 23:19:36.221783 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6677 23:19:36.222572 ==
6678 23:19:36.222947 DQS Delay:
6679 23:19:36.225226 DQS0 = 43, DQS1 = 59
6680 23:19:36.225682 DQM Delay:
6681 23:19:36.228838 DQM0 = 9, DQM1 = 17
6682 23:19:36.229420 DQ Delay:
6683 23:19:36.231807 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6684 23:19:36.235136 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6685 23:19:36.238741 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6686 23:19:36.242619 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6687 23:19:36.243195
6688 23:19:36.243553
6689 23:19:36.243885 ==
6690 23:19:36.245066 Dram Type= 6, Freq= 0, CH_1, rank 1
6691 23:19:36.248756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6692 23:19:36.249221 ==
6693 23:19:36.249580
6694 23:19:36.249909
6695 23:19:36.252104 TX Vref Scan disable
6696 23:19:36.252813 == TX Byte 0 ==
6697 23:19:36.255188 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6698 23:19:36.261652 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6699 23:19:36.262198 == TX Byte 1 ==
6700 23:19:36.265069 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6701 23:19:36.271299 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6702 23:19:36.271939 ==
6703 23:19:36.274918 Dram Type= 6, Freq= 0, CH_1, rank 1
6704 23:19:36.278607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6705 23:19:36.279068 ==
6706 23:19:36.279429
6707 23:19:36.279872
6708 23:19:36.281049 TX Vref Scan disable
6709 23:19:36.281505 == TX Byte 0 ==
6710 23:19:36.289074 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6711 23:19:36.291796 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6712 23:19:36.292351 == TX Byte 1 ==
6713 23:19:36.297779 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6714 23:19:36.301453 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6715 23:19:36.301910
6716 23:19:36.302264 [DATLAT]
6717 23:19:36.304769 Freq=400, CH1 RK1
6718 23:19:36.305228
6719 23:19:36.305586 DATLAT Default: 0xd
6720 23:19:36.308084 0, 0xFFFF, sum = 0
6721 23:19:36.308629 1, 0xFFFF, sum = 0
6722 23:19:36.311105 2, 0xFFFF, sum = 0
6723 23:19:36.311666 3, 0xFFFF, sum = 0
6724 23:19:36.314071 4, 0xFFFF, sum = 0
6725 23:19:36.314536 5, 0xFFFF, sum = 0
6726 23:19:36.317710 6, 0xFFFF, sum = 0
6727 23:19:36.318216 7, 0xFFFF, sum = 0
6728 23:19:36.321112 8, 0xFFFF, sum = 0
6729 23:19:36.321641 9, 0xFFFF, sum = 0
6730 23:19:36.324252 10, 0xFFFF, sum = 0
6731 23:19:36.327810 11, 0xFFFF, sum = 0
6732 23:19:36.328300 12, 0x0, sum = 1
6733 23:19:36.328663 13, 0x0, sum = 2
6734 23:19:36.331023 14, 0x0, sum = 3
6735 23:19:36.331499 15, 0x0, sum = 4
6736 23:19:36.334131 best_step = 13
6737 23:19:36.334635
6738 23:19:36.334997 ==
6739 23:19:36.337313 Dram Type= 6, Freq= 0, CH_1, rank 1
6740 23:19:36.341284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6741 23:19:36.341744 ==
6742 23:19:36.344928 RX Vref Scan: 0
6743 23:19:36.345387
6744 23:19:36.345746 RX Vref 0 -> 0, step: 1
6745 23:19:36.346081
6746 23:19:36.347173 RX Delay -359 -> 252, step: 8
6747 23:19:36.356304 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6748 23:19:36.359128 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6749 23:19:36.363050 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6750 23:19:36.369247 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6751 23:19:36.372343 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6752 23:19:36.375600 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6753 23:19:36.379125 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6754 23:19:36.385496 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6755 23:19:36.388540 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6756 23:19:36.392297 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6757 23:19:36.395635 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6758 23:19:36.401844 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6759 23:19:36.405211 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6760 23:19:36.408781 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6761 23:19:36.412441 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6762 23:19:36.418844 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6763 23:19:36.419404 ==
6764 23:19:36.422109 Dram Type= 6, Freq= 0, CH_1, rank 1
6765 23:19:36.425774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6766 23:19:36.426254 ==
6767 23:19:36.426614 DQS Delay:
6768 23:19:36.428630 DQS0 = 48, DQS1 = 64
6769 23:19:36.429151 DQM Delay:
6770 23:19:36.431270 DQM0 = 9, DQM1 = 15
6771 23:19:36.431723 DQ Delay:
6772 23:19:36.434769 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6773 23:19:36.438307 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6774 23:19:36.441717 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6775 23:19:36.445773 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6776 23:19:36.446333
6777 23:19:36.446696
6778 23:19:36.452339 [DQSOSCAuto] RK1, (LSB)MR18= 0xa9a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6779 23:19:36.455602 CH1 RK1: MR19=C0C, MR18=A9A9
6780 23:19:36.461950 CH1_RK1: MR19=0xC0C, MR18=0xA9A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6781 23:19:36.465845 [RxdqsGatingPostProcess] freq 400
6782 23:19:36.471998 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6783 23:19:36.475585 Pre-setting of DQS Precalculation
6784 23:19:36.478186 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6785 23:19:36.486233 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6786 23:19:36.491758 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6787 23:19:36.492351
6788 23:19:36.494689
6789 23:19:36.495143 [Calibration Summary] 800 Mbps
6790 23:19:36.497819 CH 0, Rank 0
6791 23:19:36.498293 SW Impedance : PASS
6792 23:19:36.501319 DUTY Scan : NO K
6793 23:19:36.504584 ZQ Calibration : PASS
6794 23:19:36.505110 Jitter Meter : NO K
6795 23:19:36.507699 CBT Training : PASS
6796 23:19:36.511167 Write leveling : PASS
6797 23:19:36.511739 RX DQS gating : PASS
6798 23:19:36.514414 RX DQ/DQS(RDDQC) : PASS
6799 23:19:36.518690 TX DQ/DQS : PASS
6800 23:19:36.519261 RX DATLAT : PASS
6801 23:19:36.520885 RX DQ/DQS(Engine): PASS
6802 23:19:36.524911 TX OE : NO K
6803 23:19:36.525593 All Pass.
6804 23:19:36.525964
6805 23:19:36.526299 CH 0, Rank 1
6806 23:19:36.527502 SW Impedance : PASS
6807 23:19:36.531550 DUTY Scan : NO K
6808 23:19:36.532005 ZQ Calibration : PASS
6809 23:19:36.534416 Jitter Meter : NO K
6810 23:19:36.534978 CBT Training : PASS
6811 23:19:36.538564 Write leveling : NO K
6812 23:19:36.541323 RX DQS gating : PASS
6813 23:19:36.541781 RX DQ/DQS(RDDQC) : PASS
6814 23:19:36.544414 TX DQ/DQS : PASS
6815 23:19:36.547586 RX DATLAT : PASS
6816 23:19:36.548144 RX DQ/DQS(Engine): PASS
6817 23:19:36.551330 TX OE : NO K
6818 23:19:36.551981 All Pass.
6819 23:19:36.552357
6820 23:19:36.554209 CH 1, Rank 0
6821 23:19:36.554661 SW Impedance : PASS
6822 23:19:36.557623 DUTY Scan : NO K
6823 23:19:36.561060 ZQ Calibration : PASS
6824 23:19:36.561519 Jitter Meter : NO K
6825 23:19:36.564215 CBT Training : PASS
6826 23:19:36.567621 Write leveling : PASS
6827 23:19:36.568083 RX DQS gating : PASS
6828 23:19:36.571415 RX DQ/DQS(RDDQC) : PASS
6829 23:19:36.574375 TX DQ/DQS : PASS
6830 23:19:36.574935 RX DATLAT : PASS
6831 23:19:36.577323 RX DQ/DQS(Engine): PASS
6832 23:19:36.581501 TX OE : NO K
6833 23:19:36.582059 All Pass.
6834 23:19:36.582421
6835 23:19:36.582752 CH 1, Rank 1
6836 23:19:36.583992 SW Impedance : PASS
6837 23:19:36.587825 DUTY Scan : NO K
6838 23:19:36.588382 ZQ Calibration : PASS
6839 23:19:36.590461 Jitter Meter : NO K
6840 23:19:36.594335 CBT Training : PASS
6841 23:19:36.594793 Write leveling : NO K
6842 23:19:36.598071 RX DQS gating : PASS
6843 23:19:36.598624 RX DQ/DQS(RDDQC) : PASS
6844 23:19:36.601192 TX DQ/DQS : PASS
6845 23:19:36.604478 RX DATLAT : PASS
6846 23:19:36.605133 RX DQ/DQS(Engine): PASS
6847 23:19:36.607014 TX OE : NO K
6848 23:19:36.607474 All Pass.
6849 23:19:36.607834
6850 23:19:36.610123 DramC Write-DBI off
6851 23:19:36.613281 PER_BANK_REFRESH: Hybrid Mode
6852 23:19:36.613733 TX_TRACKING: ON
6853 23:19:36.623232 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6854 23:19:36.626452 [FAST_K] Save calibration result to emmc
6855 23:19:36.630493 dramc_set_vcore_voltage set vcore to 725000
6856 23:19:36.633305 Read voltage for 1600, 0
6857 23:19:36.633764 Vio18 = 0
6858 23:19:36.636600 Vcore = 725000
6859 23:19:36.637320 Vdram = 0
6860 23:19:36.637836 Vddq = 0
6861 23:19:36.638187 Vmddr = 0
6862 23:19:36.643501 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6863 23:19:36.651189 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6864 23:19:36.651765 MEM_TYPE=3, freq_sel=13
6865 23:19:36.653335 sv_algorithm_assistance_LP4_3733
6866 23:19:36.656976 ============ PULL DRAM RESETB DOWN ============
6867 23:19:36.662961 ========== PULL DRAM RESETB DOWN end =========
6868 23:19:36.666625 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6869 23:19:36.669640 ===================================
6870 23:19:36.673211 LPDDR4 DRAM CONFIGURATION
6871 23:19:36.676454 ===================================
6872 23:19:36.677077 EX_ROW_EN[0] = 0x0
6873 23:19:36.679499 EX_ROW_EN[1] = 0x0
6874 23:19:36.683287 LP4Y_EN = 0x0
6875 23:19:36.683845 WORK_FSP = 0x1
6876 23:19:36.686889 WL = 0x5
6877 23:19:36.687450 RL = 0x5
6878 23:19:36.689312 BL = 0x2
6879 23:19:36.689771 RPST = 0x0
6880 23:19:36.693543 RD_PRE = 0x0
6881 23:19:36.694102 WR_PRE = 0x1
6882 23:19:36.696067 WR_PST = 0x1
6883 23:19:36.696525 DBI_WR = 0x0
6884 23:19:36.699394 DBI_RD = 0x0
6885 23:19:36.699849 OTF = 0x1
6886 23:19:36.703170 ===================================
6887 23:19:36.705894 ===================================
6888 23:19:36.709168 ANA top config
6889 23:19:36.713003 ===================================
6890 23:19:36.713565 DLL_ASYNC_EN = 0
6891 23:19:36.715829 ALL_SLAVE_EN = 0
6892 23:19:36.719665 NEW_RANK_MODE = 1
6893 23:19:36.722434 DLL_IDLE_MODE = 1
6894 23:19:36.725784 LP45_APHY_COMB_EN = 1
6895 23:19:36.726343 TX_ODT_DIS = 0
6896 23:19:36.729262 NEW_8X_MODE = 1
6897 23:19:36.732810 ===================================
6898 23:19:36.736329 ===================================
6899 23:19:36.739098 data_rate = 3200
6900 23:19:36.742694 CKR = 1
6901 23:19:36.745863 DQ_P2S_RATIO = 8
6902 23:19:36.749262 ===================================
6903 23:19:36.752635 CA_P2S_RATIO = 8
6904 23:19:36.753225 DQ_CA_OPEN = 0
6905 23:19:36.755632 DQ_SEMI_OPEN = 0
6906 23:19:36.758888 CA_SEMI_OPEN = 0
6907 23:19:36.762068 CA_FULL_RATE = 0
6908 23:19:36.765314 DQ_CKDIV4_EN = 0
6909 23:19:36.768805 CA_CKDIV4_EN = 0
6910 23:19:36.769367 CA_PREDIV_EN = 0
6911 23:19:36.772598 PH8_DLY = 12
6912 23:19:36.775864 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6913 23:19:36.778477 DQ_AAMCK_DIV = 4
6914 23:19:36.781924 CA_AAMCK_DIV = 4
6915 23:19:36.785406 CA_ADMCK_DIV = 4
6916 23:19:36.785971 DQ_TRACK_CA_EN = 0
6917 23:19:36.789298 CA_PICK = 1600
6918 23:19:36.791994 CA_MCKIO = 1600
6919 23:19:36.795573 MCKIO_SEMI = 0
6920 23:19:36.799170 PLL_FREQ = 3068
6921 23:19:36.802333 DQ_UI_PI_RATIO = 32
6922 23:19:36.805371 CA_UI_PI_RATIO = 0
6923 23:19:36.808325 ===================================
6924 23:19:36.812261 ===================================
6925 23:19:36.812881 memory_type:LPDDR4
6926 23:19:36.814931 GP_NUM : 10
6927 23:19:36.818379 SRAM_EN : 1
6928 23:19:36.818842 MD32_EN : 0
6929 23:19:36.822024 ===================================
6930 23:19:36.825199 [ANA_INIT] >>>>>>>>>>>>>>
6931 23:19:36.828913 <<<<<< [CONFIGURE PHASE]: ANA_TX
6932 23:19:36.831819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6933 23:19:36.835508 ===================================
6934 23:19:36.838641 data_rate = 3200,PCW = 0X7600
6935 23:19:36.841689 ===================================
6936 23:19:36.845078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6937 23:19:36.847843 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6938 23:19:36.855244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6939 23:19:36.857855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6940 23:19:36.861527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6941 23:19:36.864905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6942 23:19:36.868227 [ANA_INIT] flow start
6943 23:19:36.871586 [ANA_INIT] PLL >>>>>>>>
6944 23:19:36.872141 [ANA_INIT] PLL <<<<<<<<
6945 23:19:36.874510 [ANA_INIT] MIDPI >>>>>>>>
6946 23:19:36.877456 [ANA_INIT] MIDPI <<<<<<<<
6947 23:19:36.881109 [ANA_INIT] DLL >>>>>>>>
6948 23:19:36.881682 [ANA_INIT] DLL <<<<<<<<
6949 23:19:36.884411 [ANA_INIT] flow end
6950 23:19:36.887864 ============ LP4 DIFF to SE enter ============
6951 23:19:36.891699 ============ LP4 DIFF to SE exit ============
6952 23:19:36.894713 [ANA_INIT] <<<<<<<<<<<<<
6953 23:19:36.897631 [Flow] Enable top DCM control >>>>>
6954 23:19:36.901016 [Flow] Enable top DCM control <<<<<
6955 23:19:36.904119 Enable DLL master slave shuffle
6956 23:19:36.911480 ==============================================================
6957 23:19:36.912039 Gating Mode config
6958 23:19:36.917531 ==============================================================
6959 23:19:36.918002 Config description:
6960 23:19:36.928164 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6961 23:19:36.934518 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6962 23:19:36.940885 SELPH_MODE 0: By rank 1: By Phase
6963 23:19:36.947203 ==============================================================
6964 23:19:36.947753 GAT_TRACK_EN = 1
6965 23:19:36.950452 RX_GATING_MODE = 2
6966 23:19:36.954187 RX_GATING_TRACK_MODE = 2
6967 23:19:36.957009 SELPH_MODE = 1
6968 23:19:36.960598 PICG_EARLY_EN = 1
6969 23:19:36.963827 VALID_LAT_VALUE = 1
6970 23:19:36.970516 ==============================================================
6971 23:19:36.973838 Enter into Gating configuration >>>>
6972 23:19:36.977153 Exit from Gating configuration <<<<
6973 23:19:36.980420 Enter into DVFS_PRE_config >>>>>
6974 23:19:36.991053 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6975 23:19:36.993583 Exit from DVFS_PRE_config <<<<<
6976 23:19:36.996902 Enter into PICG configuration >>>>
6977 23:19:36.999776 Exit from PICG configuration <<<<
6978 23:19:37.003637 [RX_INPUT] configuration >>>>>
6979 23:19:37.004118 [RX_INPUT] configuration <<<<<
6980 23:19:37.009620 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6981 23:19:37.016776 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6982 23:19:37.023720 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6983 23:19:37.026369 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6984 23:19:37.033142 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6985 23:19:37.040093 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6986 23:19:37.043575 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6987 23:19:37.049333 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6988 23:19:37.053102 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6989 23:19:37.056352 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6990 23:19:37.060192 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6991 23:19:37.066203 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6992 23:19:37.070018 ===================================
6993 23:19:37.070579 LPDDR4 DRAM CONFIGURATION
6994 23:19:37.072754 ===================================
6995 23:19:37.076032 EX_ROW_EN[0] = 0x0
6996 23:19:37.079403 EX_ROW_EN[1] = 0x0
6997 23:19:37.079869 LP4Y_EN = 0x0
6998 23:19:37.083283 WORK_FSP = 0x1
6999 23:19:37.083838 WL = 0x5
7000 23:19:37.085942 RL = 0x5
7001 23:19:37.086406 BL = 0x2
7002 23:19:37.089167 RPST = 0x0
7003 23:19:37.089723 RD_PRE = 0x0
7004 23:19:37.092854 WR_PRE = 0x1
7005 23:19:37.093416 WR_PST = 0x1
7006 23:19:37.096271 DBI_WR = 0x0
7007 23:19:37.096873 DBI_RD = 0x0
7008 23:19:37.099495 OTF = 0x1
7009 23:19:37.102296 ===================================
7010 23:19:37.105618 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7011 23:19:37.109121 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7012 23:19:37.115640 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7013 23:19:37.119153 ===================================
7014 23:19:37.119635 LPDDR4 DRAM CONFIGURATION
7015 23:19:37.122842 ===================================
7016 23:19:37.125610 EX_ROW_EN[0] = 0x10
7017 23:19:37.129072 EX_ROW_EN[1] = 0x0
7018 23:19:37.129527 LP4Y_EN = 0x0
7019 23:19:37.132584 WORK_FSP = 0x1
7020 23:19:37.133109 WL = 0x5
7021 23:19:37.135909 RL = 0x5
7022 23:19:37.136465 BL = 0x2
7023 23:19:37.138989 RPST = 0x0
7024 23:19:37.139547 RD_PRE = 0x0
7025 23:19:37.142688 WR_PRE = 0x1
7026 23:19:37.143253 WR_PST = 0x1
7027 23:19:37.145850 DBI_WR = 0x0
7028 23:19:37.146409 DBI_RD = 0x0
7029 23:19:37.148405 OTF = 0x1
7030 23:19:37.151784 ===================================
7031 23:19:37.159939 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7032 23:19:37.160517 ==
7033 23:19:37.162142 Dram Type= 6, Freq= 0, CH_0, rank 0
7034 23:19:37.165607 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7035 23:19:37.166100 ==
7036 23:19:37.168212 [Duty_Offset_Calibration]
7037 23:19:37.168687 B0:0 B1:2 CA:1
7038 23:19:37.169223
7039 23:19:37.171685 [DutyScan_Calibration_Flow] k_type=0
7040 23:19:37.183117
7041 23:19:37.183691 ==CLK 0==
7042 23:19:37.185952 Final CLK duty delay cell = 0
7043 23:19:37.189619 [0] MAX Duty = 5187%(X100), DQS PI = 24
7044 23:19:37.192663 [0] MIN Duty = 4938%(X100), DQS PI = 54
7045 23:19:37.195769 [0] AVG Duty = 5062%(X100)
7046 23:19:37.196302
7047 23:19:37.199058 CH0 CLK Duty spec in!! Max-Min= 249%
7048 23:19:37.202515 [DutyScan_Calibration_Flow] ====Done====
7049 23:19:37.203064
7050 23:19:37.206641 [DutyScan_Calibration_Flow] k_type=1
7051 23:19:37.222856
7052 23:19:37.223429 ==DQS 0 ==
7053 23:19:37.226209 Final DQS duty delay cell = 0
7054 23:19:37.228963 [0] MAX Duty = 5125%(X100), DQS PI = 2
7055 23:19:37.232694 [0] MIN Duty = 5000%(X100), DQS PI = 8
7056 23:19:37.233329 [0] AVG Duty = 5062%(X100)
7057 23:19:37.235781
7058 23:19:37.236238 ==DQS 1 ==
7059 23:19:37.239746 Final DQS duty delay cell = 0
7060 23:19:37.243110 [0] MAX Duty = 5031%(X100), DQS PI = 6
7061 23:19:37.245666 [0] MIN Duty = 4876%(X100), DQS PI = 18
7062 23:19:37.246135 [0] AVG Duty = 4953%(X100)
7063 23:19:37.249409
7064 23:19:37.252551 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7065 23:19:37.253157
7066 23:19:37.255923 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7067 23:19:37.258749 [DutyScan_Calibration_Flow] ====Done====
7068 23:19:37.259215
7069 23:19:37.262343 [DutyScan_Calibration_Flow] k_type=3
7070 23:19:37.280084
7071 23:19:37.280649 ==DQM 0 ==
7072 23:19:37.282842 Final DQM duty delay cell = 0
7073 23:19:37.286821 [0] MAX Duty = 5187%(X100), DQS PI = 22
7074 23:19:37.289854 [0] MIN Duty = 4907%(X100), DQS PI = 42
7075 23:19:37.293314 [0] AVG Duty = 5047%(X100)
7076 23:19:37.293878
7077 23:19:37.294243 ==DQM 1 ==
7078 23:19:37.295960 Final DQM duty delay cell = 0
7079 23:19:37.300487 [0] MAX Duty = 5031%(X100), DQS PI = 4
7080 23:19:37.303703 [0] MIN Duty = 4782%(X100), DQS PI = 14
7081 23:19:37.305993 [0] AVG Duty = 4906%(X100)
7082 23:19:37.306457
7083 23:19:37.309371 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7084 23:19:37.309835
7085 23:19:37.312621 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7086 23:19:37.316346 [DutyScan_Calibration_Flow] ====Done====
7087 23:19:37.316930
7088 23:19:37.319004 [DutyScan_Calibration_Flow] k_type=2
7089 23:19:37.335630
7090 23:19:37.336189 ==DQ 0 ==
7091 23:19:37.339004 Final DQ duty delay cell = 0
7092 23:19:37.342857 [0] MAX Duty = 5218%(X100), DQS PI = 18
7093 23:19:37.345425 [0] MIN Duty = 4938%(X100), DQS PI = 56
7094 23:19:37.345893 [0] AVG Duty = 5078%(X100)
7095 23:19:37.349064
7096 23:19:37.349523 ==DQ 1 ==
7097 23:19:37.352054 Final DQ duty delay cell = -4
7098 23:19:37.355673 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7099 23:19:37.358579 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7100 23:19:37.362561 [-4] AVG Duty = 4969%(X100)
7101 23:19:37.363127
7102 23:19:37.366007 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7103 23:19:37.366659
7104 23:19:37.368641 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7105 23:19:37.371880 [DutyScan_Calibration_Flow] ====Done====
7106 23:19:37.372342 ==
7107 23:19:37.375505 Dram Type= 6, Freq= 0, CH_1, rank 0
7108 23:19:37.378612 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7109 23:19:37.379167 ==
7110 23:19:37.382097 [Duty_Offset_Calibration]
7111 23:19:37.382559 B0:0 B1:4 CA:-5
7112 23:19:37.382919
7113 23:19:37.385272 [DutyScan_Calibration_Flow] k_type=0
7114 23:19:37.396426
7115 23:19:37.396945 ==CLK 0==
7116 23:19:37.399385 Final CLK duty delay cell = 0
7117 23:19:37.402955 [0] MAX Duty = 5156%(X100), DQS PI = 22
7118 23:19:37.406382 [0] MIN Duty = 4906%(X100), DQS PI = 50
7119 23:19:37.409798 [0] AVG Duty = 5031%(X100)
7120 23:19:37.410270
7121 23:19:37.412541 CH1 CLK Duty spec in!! Max-Min= 250%
7122 23:19:37.415748 [DutyScan_Calibration_Flow] ====Done====
7123 23:19:37.416248
7124 23:19:37.419064 [DutyScan_Calibration_Flow] k_type=1
7125 23:19:37.435925
7126 23:19:37.436485 ==DQS 0 ==
7127 23:19:37.439119 Final DQS duty delay cell = 0
7128 23:19:37.442600 [0] MAX Duty = 5187%(X100), DQS PI = 20
7129 23:19:37.445321 [0] MIN Duty = 4876%(X100), DQS PI = 42
7130 23:19:37.445787 [0] AVG Duty = 5031%(X100)
7131 23:19:37.448541
7132 23:19:37.449055 ==DQS 1 ==
7133 23:19:37.452204 Final DQS duty delay cell = -4
7134 23:19:37.455586 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7135 23:19:37.458750 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7136 23:19:37.461630 [-4] AVG Duty = 4922%(X100)
7137 23:19:37.462092
7138 23:19:37.465605 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7139 23:19:37.466170
7140 23:19:37.469035 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7141 23:19:37.472132 [DutyScan_Calibration_Flow] ====Done====
7142 23:19:37.472592
7143 23:19:37.474739 [DutyScan_Calibration_Flow] k_type=3
7144 23:19:37.490798
7145 23:19:37.491398 ==DQM 0 ==
7146 23:19:37.494033 Final DQM duty delay cell = -4
7147 23:19:37.497657 [-4] MAX Duty = 5062%(X100), DQS PI = 32
7148 23:19:37.500967 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7149 23:19:37.504056 [-4] AVG Duty = 4922%(X100)
7150 23:19:37.504519
7151 23:19:37.504934 ==DQM 1 ==
7152 23:19:37.508482 Final DQM duty delay cell = -4
7153 23:19:37.510472 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7154 23:19:37.513679 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7155 23:19:37.517367 [-4] AVG Duty = 5000%(X100)
7156 23:19:37.517829
7157 23:19:37.521175 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7158 23:19:37.521636
7159 23:19:37.524056 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7160 23:19:37.527198 [DutyScan_Calibration_Flow] ====Done====
7161 23:19:37.527661
7162 23:19:37.530672 [DutyScan_Calibration_Flow] k_type=2
7163 23:19:37.548551
7164 23:19:37.549159 ==DQ 0 ==
7165 23:19:37.552856 Final DQ duty delay cell = 0
7166 23:19:37.555738 [0] MAX Duty = 5093%(X100), DQS PI = 4
7167 23:19:37.558924 [0] MIN Duty = 4969%(X100), DQS PI = 46
7168 23:19:37.559446 [0] AVG Duty = 5031%(X100)
7169 23:19:37.559830
7170 23:19:37.562093 ==DQ 1 ==
7171 23:19:37.565038 Final DQ duty delay cell = 0
7172 23:19:37.568899 [0] MAX Duty = 5031%(X100), DQS PI = 4
7173 23:19:37.571699 [0] MIN Duty = 4876%(X100), DQS PI = 26
7174 23:19:37.572160 [0] AVG Duty = 4953%(X100)
7175 23:19:37.572528
7176 23:19:37.574842 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7177 23:19:37.575311
7178 23:19:37.582548 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7179 23:19:37.585133 [DutyScan_Calibration_Flow] ====Done====
7180 23:19:37.588495 nWR fixed to 30
7181 23:19:37.589104 [ModeRegInit_LP4] CH0 RK0
7182 23:19:37.592046 [ModeRegInit_LP4] CH0 RK1
7183 23:19:37.595569 [ModeRegInit_LP4] CH1 RK0
7184 23:19:37.596118 [ModeRegInit_LP4] CH1 RK1
7185 23:19:37.598155 match AC timing 4
7186 23:19:37.601540 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7187 23:19:37.608509 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7188 23:19:37.612420 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7189 23:19:37.618441 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7190 23:19:37.621232 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7191 23:19:37.621758 [MiockJmeterHQA]
7192 23:19:37.622267
7193 23:19:37.624807 [DramcMiockJmeter] u1RxGatingPI = 0
7194 23:19:37.629293 0 : 4252, 4027
7195 23:19:37.629763 4 : 4255, 4030
7196 23:19:37.631343 8 : 4252, 4027
7197 23:19:37.631809 12 : 4363, 4137
7198 23:19:37.632179 16 : 4362, 4137
7199 23:19:37.634861 20 : 4253, 4027
7200 23:19:37.635329 24 : 4257, 4029
7201 23:19:37.637866 28 : 4363, 4137
7202 23:19:37.638334 32 : 4252, 4027
7203 23:19:37.641255 36 : 4365, 4140
7204 23:19:37.641722 40 : 4250, 4027
7205 23:19:37.642093 44 : 4253, 4026
7206 23:19:37.645569 48 : 4250, 4026
7207 23:19:37.646037 52 : 4252, 4027
7208 23:19:37.647619 56 : 4254, 4029
7209 23:19:37.648038 60 : 4250, 4027
7210 23:19:37.651410 64 : 4363, 4140
7211 23:19:37.651921 68 : 4363, 4140
7212 23:19:37.655424 72 : 4249, 4027
7213 23:19:37.655917 76 : 4252, 4029
7214 23:19:37.656256 80 : 4361, 4137
7215 23:19:37.657990 84 : 4250, 4027
7216 23:19:37.658411 88 : 4363, 4140
7217 23:19:37.660880 92 : 4250, 4027
7218 23:19:37.661305 96 : 4250, 4027
7219 23:19:37.664547 100 : 4250, 986
7220 23:19:37.665201 104 : 4249, 0
7221 23:19:37.665545 108 : 4250, 0
7222 23:19:37.668155 112 : 4252, 0
7223 23:19:37.668578 116 : 4252, 0
7224 23:19:37.670707 120 : 4250, 0
7225 23:19:37.671129 124 : 4366, 0
7226 23:19:37.671458 128 : 4361, 0
7227 23:19:37.674946 132 : 4250, 0
7228 23:19:37.675372 136 : 4361, 0
7229 23:19:37.677789 140 : 4250, 0
7230 23:19:37.678215 144 : 4250, 0
7231 23:19:37.678549 148 : 4250, 0
7232 23:19:37.681214 152 : 4250, 0
7233 23:19:37.681736 156 : 4252, 0
7234 23:19:37.684557 160 : 4250, 0
7235 23:19:37.685142 164 : 4250, 0
7236 23:19:37.685486 168 : 4254, 0
7237 23:19:37.687433 172 : 4360, 0
7238 23:19:37.687887 176 : 4250, 0
7239 23:19:37.688224 180 : 4250, 0
7240 23:19:37.691254 184 : 4250, 0
7241 23:19:37.691677 188 : 4361, 0
7242 23:19:37.694173 192 : 4249, 0
7243 23:19:37.694701 196 : 4250, 0
7244 23:19:37.695037 200 : 4250, 0
7245 23:19:37.697605 204 : 4361, 0
7246 23:19:37.698119 208 : 4250, 0
7247 23:19:37.701212 212 : 4250, 0
7248 23:19:37.701653 216 : 4250, 0
7249 23:19:37.701989 220 : 4254, 1298
7250 23:19:37.704585 224 : 4250, 4026
7251 23:19:37.705169 228 : 4250, 4026
7252 23:19:37.707838 232 : 4363, 4140
7253 23:19:37.708266 236 : 4253, 4029
7254 23:19:37.710700 240 : 4360, 4137
7255 23:19:37.711133 244 : 4361, 4137
7256 23:19:37.714149 248 : 4361, 4137
7257 23:19:37.714667 252 : 4250, 4026
7258 23:19:37.717261 256 : 4363, 4139
7259 23:19:37.717729 260 : 4252, 4029
7260 23:19:37.721401 264 : 4250, 4027
7261 23:19:37.721838 268 : 4255, 4029
7262 23:19:37.724399 272 : 4252, 4029
7263 23:19:37.724978 276 : 4254, 4029
7264 23:19:37.725327 280 : 4361, 4137
7265 23:19:37.728174 284 : 4250, 4027
7266 23:19:37.728609 288 : 4249, 4027
7267 23:19:37.731133 292 : 4250, 4027
7268 23:19:37.731574 296 : 4252, 4029
7269 23:19:37.734560 300 : 4250, 4027
7270 23:19:37.735001 304 : 4252, 4029
7271 23:19:37.737818 308 : 4249, 4027
7272 23:19:37.738256 312 : 4250, 4026
7273 23:19:37.740306 316 : 4250, 4026
7274 23:19:37.740777 320 : 4255, 4029
7275 23:19:37.744218 324 : 4249, 4027
7276 23:19:37.744814 328 : 4250, 4026
7277 23:19:37.747333 332 : 4361, 4137
7278 23:19:37.747888 336 : 4250, 3322
7279 23:19:37.748351 340 : 4252, 875
7280 23:19:37.751069
7281 23:19:37.751607 MIOCK jitter meter ch=0
7282 23:19:37.752053
7283 23:19:37.753654 1T = (340-100) = 240 dly cells
7284 23:19:37.760580 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7285 23:19:37.761179 ==
7286 23:19:37.763588 Dram Type= 6, Freq= 0, CH_0, rank 0
7287 23:19:37.767585 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7288 23:19:37.768021 ==
7289 23:19:37.774411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7290 23:19:37.777214 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7291 23:19:37.781068 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7292 23:19:37.786820 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7293 23:19:37.796006 [CA 0] Center 42 (12~72) winsize 61
7294 23:19:37.798475 [CA 1] Center 41 (11~72) winsize 62
7295 23:19:37.802026 [CA 2] Center 37 (7~67) winsize 61
7296 23:19:37.805720 [CA 3] Center 37 (7~67) winsize 61
7297 23:19:37.808228 [CA 4] Center 35 (5~66) winsize 62
7298 23:19:37.812292 [CA 5] Center 35 (5~65) winsize 61
7299 23:19:37.812796
7300 23:19:37.815558 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7301 23:19:37.816109
7302 23:19:37.822408 [CATrainingPosCal] consider 1 rank data
7303 23:19:37.822871 u2DelayCellTimex100 = 271/100 ps
7304 23:19:37.828148 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7305 23:19:37.831393 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7306 23:19:37.835264 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7307 23:19:37.838454 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7308 23:19:37.841775 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7309 23:19:37.844894 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7310 23:19:37.845401
7311 23:19:37.848569 CA PerBit enable=1, Macro0, CA PI delay=35
7312 23:19:37.849139
7313 23:19:37.851815 [CBTSetCACLKResult] CA Dly = 35
7314 23:19:37.855457 CS Dly: 11 (0~42)
7315 23:19:37.858818 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7316 23:19:37.862324 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7317 23:19:37.862846 ==
7318 23:19:37.865337 Dram Type= 6, Freq= 0, CH_0, rank 1
7319 23:19:37.872114 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7320 23:19:37.872851 ==
7321 23:19:37.874807 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7322 23:19:37.881348 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7323 23:19:37.884340 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7324 23:19:37.891473 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7325 23:19:37.901493 [CA 0] Center 42 (12~73) winsize 62
7326 23:19:37.902038 [CA 1] Center 41 (11~72) winsize 62
7327 23:19:37.904890 [CA 2] Center 38 (8~68) winsize 61
7328 23:19:37.908345 [CA 3] Center 37 (7~67) winsize 61
7329 23:19:37.911527 [CA 4] Center 35 (5~65) winsize 61
7330 23:19:37.914564 [CA 5] Center 35 (5~66) winsize 62
7331 23:19:37.915029
7332 23:19:37.917745 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7333 23:19:37.918206
7334 23:19:37.921340 [CATrainingPosCal] consider 2 rank data
7335 23:19:37.924780 u2DelayCellTimex100 = 271/100 ps
7336 23:19:37.931328 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7337 23:19:37.934696 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7338 23:19:37.937424 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7339 23:19:37.940832 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7340 23:19:37.944397 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7341 23:19:37.947304 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7342 23:19:37.947781
7343 23:19:37.951217 CA PerBit enable=1, Macro0, CA PI delay=35
7344 23:19:37.951759
7345 23:19:37.954431 [CBTSetCACLKResult] CA Dly = 35
7346 23:19:37.957505 CS Dly: 11 (0~43)
7347 23:19:37.961128 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7348 23:19:37.964168 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7349 23:19:37.964603
7350 23:19:37.967317 ----->DramcWriteLeveling(PI) begin...
7351 23:19:37.967752 ==
7352 23:19:37.971386 Dram Type= 6, Freq= 0, CH_0, rank 0
7353 23:19:37.977104 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7354 23:19:37.977544 ==
7355 23:19:37.980612 Write leveling (Byte 0): 29 => 29
7356 23:19:37.984160 Write leveling (Byte 1): 26 => 26
7357 23:19:37.984669 DramcWriteLeveling(PI) end<-----
7358 23:19:37.985056
7359 23:19:37.987257 ==
7360 23:19:37.990688 Dram Type= 6, Freq= 0, CH_0, rank 0
7361 23:19:37.993654 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7362 23:19:37.994068 ==
7363 23:19:37.997398 [Gating] SW mode calibration
7364 23:19:38.003726 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7365 23:19:38.008425 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7366 23:19:38.013233 0 12 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
7367 23:19:38.016923 0 12 4 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
7368 23:19:38.020199 0 12 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7369 23:19:38.026817 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7370 23:19:38.030222 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7371 23:19:38.033157 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7372 23:19:38.039584 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7373 23:19:38.043208 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7374 23:19:38.046946 0 13 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
7375 23:19:38.053904 0 13 4 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
7376 23:19:38.056975 0 13 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7377 23:19:38.060082 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7378 23:19:38.067153 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7379 23:19:38.070248 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7380 23:19:38.073421 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7381 23:19:38.079931 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7382 23:19:38.083952 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7383 23:19:38.086522 0 14 4 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7384 23:19:38.093499 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7385 23:19:38.096290 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7386 23:19:38.100204 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7387 23:19:38.106556 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7388 23:19:38.109757 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7389 23:19:38.113579 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7390 23:19:38.119452 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7391 23:19:38.123503 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7392 23:19:38.126405 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7393 23:19:38.133393 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7394 23:19:38.136033 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7395 23:19:38.139315 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7396 23:19:38.146043 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7397 23:19:38.149728 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7398 23:19:38.153146 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7399 23:19:38.159100 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7400 23:19:38.162651 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7401 23:19:38.165682 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7402 23:19:38.172510 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7403 23:19:38.175460 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7404 23:19:38.179038 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7405 23:19:38.185457 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7406 23:19:38.188823 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7407 23:19:38.192959 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7408 23:19:38.195256 Total UI for P1: 0, mck2ui 16
7409 23:19:38.198515 best dqsien dly found for B0: ( 1, 0, 30)
7410 23:19:38.205662 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7411 23:19:38.206221 Total UI for P1: 0, mck2ui 16
7412 23:19:38.212066 best dqsien dly found for B1: ( 1, 1, 4)
7413 23:19:38.215628 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7414 23:19:38.218957 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7415 23:19:38.219415
7416 23:19:38.222062 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7417 23:19:38.224903 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7418 23:19:38.229202 [Gating] SW calibration Done
7419 23:19:38.229760 ==
7420 23:19:38.231997 Dram Type= 6, Freq= 0, CH_0, rank 0
7421 23:19:38.235066 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7422 23:19:38.235557 ==
7423 23:19:38.238762 RX Vref Scan: 0
7424 23:19:38.239329
7425 23:19:38.239689 RX Vref 0 -> 0, step: 1
7426 23:19:38.240115
7427 23:19:38.241703 RX Delay 0 -> 252, step: 8
7428 23:19:38.245151 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7429 23:19:38.251850 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7430 23:19:38.256062 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7431 23:19:38.258582 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7432 23:19:38.261354 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7433 23:19:38.265043 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7434 23:19:38.271040 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7435 23:19:38.274708 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
7436 23:19:38.278113 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7437 23:19:38.281351 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7438 23:19:38.284689 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7439 23:19:38.291235 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7440 23:19:38.294471 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7441 23:19:38.298308 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7442 23:19:38.300845 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7443 23:19:38.307969 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7444 23:19:38.308428 ==
7445 23:19:38.311288 Dram Type= 6, Freq= 0, CH_0, rank 0
7446 23:19:38.314662 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7447 23:19:38.315349 ==
7448 23:19:38.315772 DQS Delay:
7449 23:19:38.317370 DQS0 = 0, DQS1 = 0
7450 23:19:38.317952 DQM Delay:
7451 23:19:38.320750 DQM0 = 130, DQM1 = 124
7452 23:19:38.321215 DQ Delay:
7453 23:19:38.323938 DQ0 =131, DQ1 =131, DQ2 =123, DQ3 =127
7454 23:19:38.327304 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7455 23:19:38.330404 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7456 23:19:38.333871 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7457 23:19:38.334327
7458 23:19:38.334683
7459 23:19:38.337557 ==
7460 23:19:38.338015 Dram Type= 6, Freq= 0, CH_0, rank 0
7461 23:19:38.343846 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7462 23:19:38.344378 ==
7463 23:19:38.344810
7464 23:19:38.345191
7465 23:19:38.347502 TX Vref Scan disable
7466 23:19:38.348050 == TX Byte 0 ==
7467 23:19:38.351315 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7468 23:19:38.357975 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7469 23:19:38.358482 == TX Byte 1 ==
7470 23:19:38.360521 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7471 23:19:38.366835 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7472 23:19:38.367301 ==
7473 23:19:38.370337 Dram Type= 6, Freq= 0, CH_0, rank 0
7474 23:19:38.373495 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7475 23:19:38.373956 ==
7476 23:19:38.387352
7477 23:19:38.390550 TX Vref early break, caculate TX vref
7478 23:19:38.393616 TX Vref=16, minBit 8, minWin=21, winSum=371
7479 23:19:38.396999 TX Vref=18, minBit 8, minWin=22, winSum=382
7480 23:19:38.400096 TX Vref=20, minBit 8, minWin=23, winSum=389
7481 23:19:38.403960 TX Vref=22, minBit 8, minWin=23, winSum=398
7482 23:19:38.406605 TX Vref=24, minBit 8, minWin=24, winSum=403
7483 23:19:38.413278 TX Vref=26, minBit 9, minWin=24, winSum=410
7484 23:19:38.416622 TX Vref=28, minBit 1, minWin=25, winSum=413
7485 23:19:38.420285 TX Vref=30, minBit 0, minWin=25, winSum=408
7486 23:19:38.423464 TX Vref=32, minBit 8, minWin=23, winSum=399
7487 23:19:38.426461 TX Vref=34, minBit 8, minWin=23, winSum=389
7488 23:19:38.433586 [TxChooseVref] Worse bit 1, Min win 25, Win sum 413, Final Vref 28
7489 23:19:38.434064
7490 23:19:38.436670 Final TX Range 0 Vref 28
7491 23:19:38.437193
7492 23:19:38.437556 ==
7493 23:19:38.439835 Dram Type= 6, Freq= 0, CH_0, rank 0
7494 23:19:38.443422 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7495 23:19:38.444004 ==
7496 23:19:38.444371
7497 23:19:38.444745
7498 23:19:38.446577 TX Vref Scan disable
7499 23:19:38.453466 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7500 23:19:38.454030 == TX Byte 0 ==
7501 23:19:38.456654 u2DelayCellOfst[0]=10 cells (3 PI)
7502 23:19:38.459528 u2DelayCellOfst[1]=18 cells (5 PI)
7503 23:19:38.462849 u2DelayCellOfst[2]=14 cells (4 PI)
7504 23:19:38.466386 u2DelayCellOfst[3]=14 cells (4 PI)
7505 23:19:38.469985 u2DelayCellOfst[4]=10 cells (3 PI)
7506 23:19:38.472671 u2DelayCellOfst[5]=0 cells (0 PI)
7507 23:19:38.476314 u2DelayCellOfst[6]=18 cells (5 PI)
7508 23:19:38.479178 u2DelayCellOfst[7]=18 cells (5 PI)
7509 23:19:38.483098 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7510 23:19:38.485887 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7511 23:19:38.488830 == TX Byte 1 ==
7512 23:19:38.492823 u2DelayCellOfst[8]=3 cells (1 PI)
7513 23:19:38.496110 u2DelayCellOfst[9]=0 cells (0 PI)
7514 23:19:38.499330 u2DelayCellOfst[10]=10 cells (3 PI)
7515 23:19:38.499794 u2DelayCellOfst[11]=3 cells (1 PI)
7516 23:19:38.502960 u2DelayCellOfst[12]=14 cells (4 PI)
7517 23:19:38.505909 u2DelayCellOfst[13]=18 cells (5 PI)
7518 23:19:38.509332 u2DelayCellOfst[14]=18 cells (5 PI)
7519 23:19:38.512450 u2DelayCellOfst[15]=18 cells (5 PI)
7520 23:19:38.519562 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7521 23:19:38.522237 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7522 23:19:38.522697 DramC Write-DBI on
7523 23:19:38.523058 ==
7524 23:19:38.525989 Dram Type= 6, Freq= 0, CH_0, rank 0
7525 23:19:38.532901 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7526 23:19:38.533369 ==
7527 23:19:38.533733
7528 23:19:38.534069
7529 23:19:38.534388 TX Vref Scan disable
7530 23:19:38.536933 == TX Byte 0 ==
7531 23:19:38.539704 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7532 23:19:38.543189 == TX Byte 1 ==
7533 23:19:38.546259 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7534 23:19:38.549679 DramC Write-DBI off
7535 23:19:38.550248
7536 23:19:38.550615 [DATLAT]
7537 23:19:38.550952 Freq=1600, CH0 RK0
7538 23:19:38.551278
7539 23:19:38.553445 DATLAT Default: 0xf
7540 23:19:38.554014 0, 0xFFFF, sum = 0
7541 23:19:38.556843 1, 0xFFFF, sum = 0
7542 23:19:38.560278 2, 0xFFFF, sum = 0
7543 23:19:38.560896 3, 0xFFFF, sum = 0
7544 23:19:38.563166 4, 0xFFFF, sum = 0
7545 23:19:38.563743 5, 0xFFFF, sum = 0
7546 23:19:38.566193 6, 0xFFFF, sum = 0
7547 23:19:38.566660 7, 0xFFFF, sum = 0
7548 23:19:38.569648 8, 0xFFFF, sum = 0
7549 23:19:38.570236 9, 0xFFFF, sum = 0
7550 23:19:38.572646 10, 0xFFFF, sum = 0
7551 23:19:38.573267 11, 0xFFFF, sum = 0
7552 23:19:38.575885 12, 0xFFF, sum = 0
7553 23:19:38.576454 13, 0x0, sum = 1
7554 23:19:38.579422 14, 0x0, sum = 2
7555 23:19:38.579910 15, 0x0, sum = 3
7556 23:19:38.582707 16, 0x0, sum = 4
7557 23:19:38.583176 best_step = 14
7558 23:19:38.583539
7559 23:19:38.583877 ==
7560 23:19:38.586070 Dram Type= 6, Freq= 0, CH_0, rank 0
7561 23:19:38.589449 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7562 23:19:38.592561 ==
7563 23:19:38.593184 RX Vref Scan: 1
7564 23:19:38.593554
7565 23:19:38.595988 Set Vref Range= 24 -> 127
7566 23:19:38.596557
7567 23:19:38.599496 RX Vref 24 -> 127, step: 1
7568 23:19:38.600100
7569 23:19:38.600471 RX Delay 11 -> 252, step: 4
7570 23:19:38.600863
7571 23:19:38.602669 Set Vref, RX VrefLevel [Byte0]: 24
7572 23:19:38.605755 [Byte1]: 24
7573 23:19:38.609887
7574 23:19:38.610453 Set Vref, RX VrefLevel [Byte0]: 25
7575 23:19:38.613186 [Byte1]: 25
7576 23:19:38.617309
7577 23:19:38.617825 Set Vref, RX VrefLevel [Byte0]: 26
7578 23:19:38.621375 [Byte1]: 26
7579 23:19:38.625295
7580 23:19:38.625755 Set Vref, RX VrefLevel [Byte0]: 27
7581 23:19:38.628775 [Byte1]: 27
7582 23:19:38.632772
7583 23:19:38.633388 Set Vref, RX VrefLevel [Byte0]: 28
7584 23:19:38.635769 [Byte1]: 28
7585 23:19:38.640400
7586 23:19:38.641035 Set Vref, RX VrefLevel [Byte0]: 29
7587 23:19:38.643068 [Byte1]: 29
7588 23:19:38.647481
7589 23:19:38.648044 Set Vref, RX VrefLevel [Byte0]: 30
7590 23:19:38.651133 [Byte1]: 30
7591 23:19:38.655739
7592 23:19:38.656305 Set Vref, RX VrefLevel [Byte0]: 31
7593 23:19:38.659194 [Byte1]: 31
7594 23:19:38.663747
7595 23:19:38.664317 Set Vref, RX VrefLevel [Byte0]: 32
7596 23:19:38.666549 [Byte1]: 32
7597 23:19:38.671243
7598 23:19:38.671807 Set Vref, RX VrefLevel [Byte0]: 33
7599 23:19:38.674433 [Byte1]: 33
7600 23:19:38.678572
7601 23:19:38.679136 Set Vref, RX VrefLevel [Byte0]: 34
7602 23:19:38.682461 [Byte1]: 34
7603 23:19:38.685981
7604 23:19:38.686547 Set Vref, RX VrefLevel [Byte0]: 35
7605 23:19:38.689523 [Byte1]: 35
7606 23:19:38.693856
7607 23:19:38.694388 Set Vref, RX VrefLevel [Byte0]: 36
7608 23:19:38.697393 [Byte1]: 36
7609 23:19:38.701006
7610 23:19:38.701467 Set Vref, RX VrefLevel [Byte0]: 37
7611 23:19:38.704306 [Byte1]: 37
7612 23:19:38.708605
7613 23:19:38.709117 Set Vref, RX VrefLevel [Byte0]: 38
7614 23:19:38.711857 [Byte1]: 38
7615 23:19:38.716509
7616 23:19:38.717092 Set Vref, RX VrefLevel [Byte0]: 39
7617 23:19:38.719301 [Byte1]: 39
7618 23:19:38.723608
7619 23:19:38.724069 Set Vref, RX VrefLevel [Byte0]: 40
7620 23:19:38.727195 [Byte1]: 40
7621 23:19:38.731212
7622 23:19:38.731672 Set Vref, RX VrefLevel [Byte0]: 41
7623 23:19:38.735010 [Byte1]: 41
7624 23:19:38.739109
7625 23:19:38.739675 Set Vref, RX VrefLevel [Byte0]: 42
7626 23:19:38.742401 [Byte1]: 42
7627 23:19:38.746760
7628 23:19:38.747336 Set Vref, RX VrefLevel [Byte0]: 43
7629 23:19:38.750310 [Byte1]: 43
7630 23:19:38.754454
7631 23:19:38.755010 Set Vref, RX VrefLevel [Byte0]: 44
7632 23:19:38.757750 [Byte1]: 44
7633 23:19:38.762015
7634 23:19:38.762575 Set Vref, RX VrefLevel [Byte0]: 45
7635 23:19:38.765375 [Byte1]: 45
7636 23:19:38.771030
7637 23:19:38.771585 Set Vref, RX VrefLevel [Byte0]: 46
7638 23:19:38.772866 [Byte1]: 46
7639 23:19:38.777568
7640 23:19:38.778124 Set Vref, RX VrefLevel [Byte0]: 47
7641 23:19:38.780884 [Byte1]: 47
7642 23:19:38.785103
7643 23:19:38.785658 Set Vref, RX VrefLevel [Byte0]: 48
7644 23:19:38.788540 [Byte1]: 48
7645 23:19:38.792501
7646 23:19:38.793120 Set Vref, RX VrefLevel [Byte0]: 49
7647 23:19:38.796052 [Byte1]: 49
7648 23:19:38.800308
7649 23:19:38.800909 Set Vref, RX VrefLevel [Byte0]: 50
7650 23:19:38.803331 [Byte1]: 50
7651 23:19:38.807784
7652 23:19:38.808311 Set Vref, RX VrefLevel [Byte0]: 51
7653 23:19:38.811626 [Byte1]: 51
7654 23:19:38.815417
7655 23:19:38.815881 Set Vref, RX VrefLevel [Byte0]: 52
7656 23:19:38.818327 [Byte1]: 52
7657 23:19:38.823388
7658 23:19:38.823948 Set Vref, RX VrefLevel [Byte0]: 53
7659 23:19:38.826261 [Byte1]: 53
7660 23:19:38.830168
7661 23:19:38.830736 Set Vref, RX VrefLevel [Byte0]: 54
7662 23:19:38.833673 [Byte1]: 54
7663 23:19:38.838000
7664 23:19:38.838552 Set Vref, RX VrefLevel [Byte0]: 55
7665 23:19:38.841326 [Byte1]: 55
7666 23:19:38.845499
7667 23:19:38.845965 Set Vref, RX VrefLevel [Byte0]: 56
7668 23:19:38.848601 [Byte1]: 56
7669 23:19:38.853431
7670 23:19:38.853987 Set Vref, RX VrefLevel [Byte0]: 57
7671 23:19:38.856560 [Byte1]: 57
7672 23:19:38.861250
7673 23:19:38.861711 Set Vref, RX VrefLevel [Byte0]: 58
7674 23:19:38.864530 [Byte1]: 58
7675 23:19:38.868765
7676 23:19:38.869236 Set Vref, RX VrefLevel [Byte0]: 59
7677 23:19:38.871945 [Byte1]: 59
7678 23:19:38.876549
7679 23:19:38.877175 Set Vref, RX VrefLevel [Byte0]: 60
7680 23:19:38.879636 [Byte1]: 60
7681 23:19:38.883747
7682 23:19:38.884325 Set Vref, RX VrefLevel [Byte0]: 61
7683 23:19:38.886942 [Byte1]: 61
7684 23:19:38.891804
7685 23:19:38.892385 Set Vref, RX VrefLevel [Byte0]: 62
7686 23:19:38.894807 [Byte1]: 62
7687 23:19:38.899174
7688 23:19:38.899739 Set Vref, RX VrefLevel [Byte0]: 63
7689 23:19:38.902271 [Byte1]: 63
7690 23:19:38.907272
7691 23:19:38.907835 Set Vref, RX VrefLevel [Byte0]: 64
7692 23:19:38.910214 [Byte1]: 64
7693 23:19:38.914559
7694 23:19:38.915128 Set Vref, RX VrefLevel [Byte0]: 65
7695 23:19:38.917658 [Byte1]: 65
7696 23:19:38.922454
7697 23:19:38.922916 Set Vref, RX VrefLevel [Byte0]: 66
7698 23:19:38.924912 [Byte1]: 66
7699 23:19:38.929443
7700 23:19:38.930009 Set Vref, RX VrefLevel [Byte0]: 67
7701 23:19:38.932896 [Byte1]: 67
7702 23:19:38.936843
7703 23:19:38.937422 Set Vref, RX VrefLevel [Byte0]: 68
7704 23:19:38.940359 [Byte1]: 68
7705 23:19:38.944828
7706 23:19:38.945382 Set Vref, RX VrefLevel [Byte0]: 69
7707 23:19:38.948159 [Byte1]: 69
7708 23:19:38.952341
7709 23:19:38.952956 Set Vref, RX VrefLevel [Byte0]: 70
7710 23:19:38.955311 [Byte1]: 70
7711 23:19:38.960352
7712 23:19:38.960943 Set Vref, RX VrefLevel [Byte0]: 71
7713 23:19:38.963602 [Byte1]: 71
7714 23:19:38.967438
7715 23:19:38.968000 Final RX Vref Byte 0 = 52 to rank0
7716 23:19:38.971310 Final RX Vref Byte 1 = 55 to rank0
7717 23:19:38.975817 Final RX Vref Byte 0 = 52 to rank1
7718 23:19:38.977225 Final RX Vref Byte 1 = 55 to rank1==
7719 23:19:38.980686 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 23:19:38.987644 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7721 23:19:38.988206 ==
7722 23:19:38.988576 DQS Delay:
7723 23:19:38.990709 DQS0 = 0, DQS1 = 0
7724 23:19:38.991182 DQM Delay:
7725 23:19:38.991547 DQM0 = 127, DQM1 = 121
7726 23:19:38.994071 DQ Delay:
7727 23:19:38.997337 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =124
7728 23:19:39.001086 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7729 23:19:39.004225 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7730 23:19:39.007114 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =132
7731 23:19:39.007674
7732 23:19:39.008038
7733 23:19:39.008374
7734 23:19:39.012056 [DramC_TX_OE_Calibration] TA2
7735 23:19:39.013491 Original DQ_B0 (3 6) =30, OEN = 27
7736 23:19:39.017055 Original DQ_B1 (3 6) =30, OEN = 27
7737 23:19:39.020203 24, 0x0, End_B0=24 End_B1=24
7738 23:19:39.020672 25, 0x0, End_B0=25 End_B1=25
7739 23:19:39.023637 26, 0x0, End_B0=26 End_B1=26
7740 23:19:39.027195 27, 0x0, End_B0=27 End_B1=27
7741 23:19:39.030747 28, 0x0, End_B0=28 End_B1=28
7742 23:19:39.033638 29, 0x0, End_B0=29 End_B1=29
7743 23:19:39.034124 30, 0x0, End_B0=30 End_B1=30
7744 23:19:39.037063 31, 0x4141, End_B0=30 End_B1=30
7745 23:19:39.040348 Byte0 end_step=30 best_step=27
7746 23:19:39.043441 Byte1 end_step=30 best_step=27
7747 23:19:39.046845 Byte0 TX OE(2T, 0.5T) = (3, 3)
7748 23:19:39.050458 Byte1 TX OE(2T, 0.5T) = (3, 3)
7749 23:19:39.051018
7750 23:19:39.051382
7751 23:19:39.057345 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
7752 23:19:39.060179 CH0 RK0: MR19=303, MR18=1919
7753 23:19:39.067139 CH0_RK0: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15
7754 23:19:39.067692
7755 23:19:39.069682 ----->DramcWriteLeveling(PI) begin...
7756 23:19:39.070146 ==
7757 23:19:39.073606 Dram Type= 6, Freq= 0, CH_0, rank 1
7758 23:19:39.076896 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7759 23:19:39.077359 ==
7760 23:19:39.079919 Write leveling (Byte 0): 29 => 29
7761 23:19:39.083488 Write leveling (Byte 1): 25 => 25
7762 23:19:39.087852 DramcWriteLeveling(PI) end<-----
7763 23:19:39.088416
7764 23:19:39.088928 ==
7765 23:19:39.089635 Dram Type= 6, Freq= 0, CH_0, rank 1
7766 23:19:39.092889 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7767 23:19:39.096777 ==
7768 23:19:39.097330 [Gating] SW mode calibration
7769 23:19:39.106328 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7770 23:19:39.109423 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7771 23:19:39.112860 0 12 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7772 23:19:39.119594 0 12 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7773 23:19:39.122582 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7774 23:19:39.125836 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7775 23:19:39.132784 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7776 23:19:39.135543 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7777 23:19:39.139530 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7778 23:19:39.145808 0 12 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7779 23:19:39.148914 0 13 0 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
7780 23:19:39.152104 0 13 4 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
7781 23:19:39.158852 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7782 23:19:39.161791 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7783 23:19:39.165699 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7784 23:19:39.171703 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7785 23:19:39.174965 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7786 23:19:39.179043 0 13 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7787 23:19:39.184772 0 14 0 | B1->B0 | 2323 3d3c | 0 1 | (0 0) (0 0)
7788 23:19:39.188395 0 14 4 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
7789 23:19:39.191895 0 14 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7790 23:19:39.198516 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7791 23:19:39.201497 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7792 23:19:39.205234 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7793 23:19:39.211504 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7794 23:19:39.214285 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7795 23:19:39.217501 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7796 23:19:39.224256 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7797 23:19:39.228277 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7798 23:19:39.231366 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7799 23:19:39.237653 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7800 23:19:39.240581 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7801 23:19:39.244273 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7802 23:19:39.251171 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7803 23:19:39.254020 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7804 23:19:39.257365 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7805 23:19:39.264123 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7806 23:19:39.267147 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7807 23:19:39.270503 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7808 23:19:39.277353 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7809 23:19:39.280930 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7810 23:19:39.283924 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7811 23:19:39.290985 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7812 23:19:39.294032 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7813 23:19:39.297338 Total UI for P1: 0, mck2ui 16
7814 23:19:39.300983 best dqsien dly found for B0: ( 1, 0, 30)
7815 23:19:39.304085 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7816 23:19:39.311039 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7817 23:19:39.311614 Total UI for P1: 0, mck2ui 16
7818 23:19:39.317603 best dqsien dly found for B1: ( 1, 1, 4)
7819 23:19:39.320395 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7820 23:19:39.323874 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7821 23:19:39.324440
7822 23:19:39.327245 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7823 23:19:39.330469 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7824 23:19:39.334468 [Gating] SW calibration Done
7825 23:19:39.335038 ==
7826 23:19:39.337007 Dram Type= 6, Freq= 0, CH_0, rank 1
7827 23:19:39.340630 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7828 23:19:39.341265 ==
7829 23:19:39.344241 RX Vref Scan: 0
7830 23:19:39.344859
7831 23:19:39.345236 RX Vref 0 -> 0, step: 1
7832 23:19:39.345581
7833 23:19:39.347069 RX Delay 0 -> 252, step: 8
7834 23:19:39.350156 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7835 23:19:39.357708 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7836 23:19:39.360922 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7837 23:19:39.364097 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7838 23:19:39.366822 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7839 23:19:39.370473 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7840 23:19:39.377068 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7841 23:19:39.380356 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7842 23:19:39.383842 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7843 23:19:39.386653 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7844 23:19:39.390823 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7845 23:19:39.396668 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7846 23:19:39.399838 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7847 23:19:39.403045 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7848 23:19:39.406830 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7849 23:19:39.412891 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7850 23:19:39.413356 ==
7851 23:19:39.416336 Dram Type= 6, Freq= 0, CH_0, rank 1
7852 23:19:39.419710 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7853 23:19:39.420185 ==
7854 23:19:39.420553 DQS Delay:
7855 23:19:39.423337 DQS0 = 0, DQS1 = 0
7856 23:19:39.423731 DQM Delay:
7857 23:19:39.426902 DQM0 = 130, DQM1 = 124
7858 23:19:39.427625 DQ Delay:
7859 23:19:39.429285 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7860 23:19:39.432634 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7861 23:19:39.435836 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7862 23:19:39.439537 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7863 23:19:39.440098
7864 23:19:39.440461
7865 23:19:39.442776 ==
7866 23:19:39.445949 Dram Type= 6, Freq= 0, CH_0, rank 1
7867 23:19:39.449636 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7868 23:19:39.450197 ==
7869 23:19:39.450559
7870 23:19:39.450896
7871 23:19:39.452308 TX Vref Scan disable
7872 23:19:39.452837 == TX Byte 0 ==
7873 23:19:39.456587 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7874 23:19:39.462760 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7875 23:19:39.463322 == TX Byte 1 ==
7876 23:19:39.468837 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7877 23:19:39.472589 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7878 23:19:39.473204 ==
7879 23:19:39.476276 Dram Type= 6, Freq= 0, CH_0, rank 1
7880 23:19:39.479197 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7881 23:19:39.479774 ==
7882 23:19:39.493703
7883 23:19:39.496995 TX Vref early break, caculate TX vref
7884 23:19:39.501352 TX Vref=16, minBit 8, minWin=22, winSum=373
7885 23:19:39.503762 TX Vref=18, minBit 8, minWin=23, winSum=383
7886 23:19:39.507156 TX Vref=20, minBit 1, minWin=23, winSum=390
7887 23:19:39.509941 TX Vref=22, minBit 8, minWin=24, winSum=399
7888 23:19:39.513618 TX Vref=24, minBit 8, minWin=24, winSum=404
7889 23:19:39.520398 TX Vref=26, minBit 1, minWin=24, winSum=410
7890 23:19:39.523346 TX Vref=28, minBit 1, minWin=24, winSum=414
7891 23:19:39.526667 TX Vref=30, minBit 4, minWin=25, winSum=410
7892 23:19:39.530692 TX Vref=32, minBit 8, minWin=24, winSum=405
7893 23:19:39.535210 TX Vref=34, minBit 8, minWin=23, winSum=394
7894 23:19:39.536991 TX Vref=36, minBit 1, minWin=23, winSum=388
7895 23:19:39.543900 [TxChooseVref] Worse bit 4, Min win 25, Win sum 410, Final Vref 30
7896 23:19:39.544470
7897 23:19:39.547044 Final TX Range 0 Vref 30
7898 23:19:39.547611
7899 23:19:39.547979 ==
7900 23:19:39.550073 Dram Type= 6, Freq= 0, CH_0, rank 1
7901 23:19:39.553727 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7902 23:19:39.554254 ==
7903 23:19:39.554619
7904 23:19:39.557047
7905 23:19:39.557505 TX Vref Scan disable
7906 23:19:39.563480 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7907 23:19:39.564028 == TX Byte 0 ==
7908 23:19:39.566530 u2DelayCellOfst[0]=14 cells (4 PI)
7909 23:19:39.570295 u2DelayCellOfst[1]=21 cells (6 PI)
7910 23:19:39.573892 u2DelayCellOfst[2]=14 cells (4 PI)
7911 23:19:39.576907 u2DelayCellOfst[3]=14 cells (4 PI)
7912 23:19:39.580091 u2DelayCellOfst[4]=10 cells (3 PI)
7913 23:19:39.583422 u2DelayCellOfst[5]=0 cells (0 PI)
7914 23:19:39.586661 u2DelayCellOfst[6]=18 cells (5 PI)
7915 23:19:39.589804 u2DelayCellOfst[7]=18 cells (5 PI)
7916 23:19:39.593168 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7917 23:19:39.596471 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7918 23:19:39.599965 == TX Byte 1 ==
7919 23:19:39.603979 u2DelayCellOfst[8]=3 cells (1 PI)
7920 23:19:39.607150 u2DelayCellOfst[9]=0 cells (0 PI)
7921 23:19:39.609645 u2DelayCellOfst[10]=10 cells (3 PI)
7922 23:19:39.610105 u2DelayCellOfst[11]=7 cells (2 PI)
7923 23:19:39.613439 u2DelayCellOfst[12]=14 cells (4 PI)
7924 23:19:39.617338 u2DelayCellOfst[13]=18 cells (5 PI)
7925 23:19:39.619703 u2DelayCellOfst[14]=18 cells (5 PI)
7926 23:19:39.622885 u2DelayCellOfst[15]=18 cells (5 PI)
7927 23:19:39.629531 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7928 23:19:39.632913 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7929 23:19:39.633425 DramC Write-DBI on
7930 23:19:39.633791 ==
7931 23:19:39.635788 Dram Type= 6, Freq= 0, CH_0, rank 1
7932 23:19:39.642675 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7933 23:19:39.643138 ==
7934 23:19:39.643496
7935 23:19:39.643828
7936 23:19:39.644146 TX Vref Scan disable
7937 23:19:39.647278 == TX Byte 0 ==
7938 23:19:39.650823 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7939 23:19:39.654179 == TX Byte 1 ==
7940 23:19:39.656962 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7941 23:19:39.660620 DramC Write-DBI off
7942 23:19:39.661262
7943 23:19:39.661635 [DATLAT]
7944 23:19:39.661973 Freq=1600, CH0 RK1
7945 23:19:39.662297
7946 23:19:39.663734 DATLAT Default: 0xe
7947 23:19:39.667320 0, 0xFFFF, sum = 0
7948 23:19:39.667789 1, 0xFFFF, sum = 0
7949 23:19:39.670145 2, 0xFFFF, sum = 0
7950 23:19:39.670611 3, 0xFFFF, sum = 0
7951 23:19:39.673612 4, 0xFFFF, sum = 0
7952 23:19:39.674176 5, 0xFFFF, sum = 0
7953 23:19:39.677526 6, 0xFFFF, sum = 0
7954 23:19:39.678093 7, 0xFFFF, sum = 0
7955 23:19:39.680218 8, 0xFFFF, sum = 0
7956 23:19:39.680814 9, 0xFFFF, sum = 0
7957 23:19:39.683746 10, 0xFFFF, sum = 0
7958 23:19:39.684312 11, 0xFFFF, sum = 0
7959 23:19:39.686835 12, 0x8FFF, sum = 0
7960 23:19:39.687402 13, 0x0, sum = 1
7961 23:19:39.690807 14, 0x0, sum = 2
7962 23:19:39.691398 15, 0x0, sum = 3
7963 23:19:39.693572 16, 0x0, sum = 4
7964 23:19:39.694045 best_step = 14
7965 23:19:39.694410
7966 23:19:39.694753 ==
7967 23:19:39.696831 Dram Type= 6, Freq= 0, CH_0, rank 1
7968 23:19:39.700156 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7969 23:19:39.703790 ==
7970 23:19:39.704361 RX Vref Scan: 0
7971 23:19:39.704774
7972 23:19:39.706832 RX Vref 0 -> 0, step: 1
7973 23:19:39.707396
7974 23:19:39.710514 RX Delay 11 -> 252, step: 4
7975 23:19:39.713419 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7976 23:19:39.717108 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7977 23:19:39.720277 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7978 23:19:39.726142 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7979 23:19:39.729512 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7980 23:19:39.732760 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7981 23:19:39.736420 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
7982 23:19:39.739501 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7983 23:19:39.746935 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7984 23:19:39.749482 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
7985 23:19:39.753618 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7986 23:19:39.756688 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7987 23:19:39.759972 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7988 23:19:39.766838 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7989 23:19:39.769331 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7990 23:19:39.773750 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7991 23:19:39.774316 ==
7992 23:19:39.776765 Dram Type= 6, Freq= 0, CH_0, rank 1
7993 23:19:39.780063 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7994 23:19:39.783097 ==
7995 23:19:39.783671 DQS Delay:
7996 23:19:39.784036 DQS0 = 0, DQS1 = 0
7997 23:19:39.786276 DQM Delay:
7998 23:19:39.786842 DQM0 = 128, DQM1 = 120
7999 23:19:39.789248 DQ Delay:
8000 23:19:39.793352 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
8001 23:19:39.796077 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =138
8002 23:19:39.799289 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
8003 23:19:39.802507 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
8004 23:19:39.803077
8005 23:19:39.803444
8006 23:19:39.803778
8007 23:19:39.805434 [DramC_TX_OE_Calibration] TA2
8008 23:19:39.809090 Original DQ_B0 (3 6) =30, OEN = 27
8009 23:19:39.812465 Original DQ_B1 (3 6) =30, OEN = 27
8010 23:19:39.815890 24, 0x0, End_B0=24 End_B1=24
8011 23:19:39.816465 25, 0x0, End_B0=25 End_B1=25
8012 23:19:39.818763 26, 0x0, End_B0=26 End_B1=26
8013 23:19:39.822463 27, 0x0, End_B0=27 End_B1=27
8014 23:19:39.825312 28, 0x0, End_B0=28 End_B1=28
8015 23:19:39.825784 29, 0x0, End_B0=29 End_B1=29
8016 23:19:39.829291 30, 0x0, End_B0=30 End_B1=30
8017 23:19:39.832505 31, 0x4141, End_B0=30 End_B1=30
8018 23:19:39.835600 Byte0 end_step=30 best_step=27
8019 23:19:39.839367 Byte1 end_step=30 best_step=27
8020 23:19:39.842021 Byte0 TX OE(2T, 0.5T) = (3, 3)
8021 23:19:39.845012 Byte1 TX OE(2T, 0.5T) = (3, 3)
8022 23:19:39.845478
8023 23:19:39.845843
8024 23:19:39.852555 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8025 23:19:39.856222 CH0 RK1: MR19=303, MR18=2222
8026 23:19:39.861925 CH0_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16
8027 23:19:39.865338 [RxdqsGatingPostProcess] freq 1600
8028 23:19:39.869017 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8029 23:19:39.872032 Pre-setting of DQS Precalculation
8030 23:19:39.878711 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8031 23:19:39.879282 ==
8032 23:19:39.882093 Dram Type= 6, Freq= 0, CH_1, rank 0
8033 23:19:39.885560 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8034 23:19:39.886148 ==
8035 23:19:39.891549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8036 23:19:39.895302 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8037 23:19:39.898616 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8038 23:19:39.905054 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8039 23:19:39.914203 [CA 0] Center 41 (11~71) winsize 61
8040 23:19:39.917632 [CA 1] Center 41 (11~72) winsize 62
8041 23:19:39.919665 [CA 2] Center 37 (7~67) winsize 61
8042 23:19:39.923099 [CA 3] Center 36 (7~66) winsize 60
8043 23:19:39.926844 [CA 4] Center 34 (4~64) winsize 61
8044 23:19:39.929911 [CA 5] Center 34 (5~64) winsize 60
8045 23:19:39.930481
8046 23:19:39.933391 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8047 23:19:39.933856
8048 23:19:39.936443 [CATrainingPosCal] consider 1 rank data
8049 23:19:39.939857 u2DelayCellTimex100 = 271/100 ps
8050 23:19:39.946272 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8051 23:19:39.949475 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8052 23:19:39.953181 CA2 delay=37 (7~67),Diff = 3 PI (10 cell)
8053 23:19:39.956324 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8054 23:19:39.960008 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8055 23:19:39.963533 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8056 23:19:39.964099
8057 23:19:39.966135 CA PerBit enable=1, Macro0, CA PI delay=34
8058 23:19:39.966601
8059 23:19:39.969652 [CBTSetCACLKResult] CA Dly = 34
8060 23:19:39.972681 CS Dly: 8 (0~39)
8061 23:19:39.976889 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8062 23:19:39.979133 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8063 23:19:39.979704 ==
8064 23:19:39.982274 Dram Type= 6, Freq= 0, CH_1, rank 1
8065 23:19:39.989296 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8066 23:19:39.989867 ==
8067 23:19:39.992746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8068 23:19:39.995972 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8069 23:19:40.002893 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8070 23:19:40.009736 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8071 23:19:40.015758 [CA 0] Center 41 (11~71) winsize 61
8072 23:19:40.019184 [CA 1] Center 41 (11~71) winsize 61
8073 23:19:40.022494 [CA 2] Center 36 (7~66) winsize 60
8074 23:19:40.025879 [CA 3] Center 36 (7~65) winsize 59
8075 23:19:40.029215 [CA 4] Center 34 (5~64) winsize 60
8076 23:19:40.032245 [CA 5] Center 33 (4~63) winsize 60
8077 23:19:40.032859
8078 23:19:40.035947 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8079 23:19:40.036526
8080 23:19:40.039381 [CATrainingPosCal] consider 2 rank data
8081 23:19:40.042520 u2DelayCellTimex100 = 271/100 ps
8082 23:19:40.045604 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8083 23:19:40.052291 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8084 23:19:40.055781 CA2 delay=36 (7~66),Diff = 2 PI (7 cell)
8085 23:19:40.059193 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8086 23:19:40.062084 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8087 23:19:40.065835 CA5 delay=34 (5~63),Diff = 0 PI (0 cell)
8088 23:19:40.066403
8089 23:19:40.068814 CA PerBit enable=1, Macro0, CA PI delay=34
8090 23:19:40.069283
8091 23:19:40.072946 [CBTSetCACLKResult] CA Dly = 34
8092 23:19:40.076761 CS Dly: 9 (0~41)
8093 23:19:40.080323 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8094 23:19:40.081684 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8095 23:19:40.082186
8096 23:19:40.085359 ----->DramcWriteLeveling(PI) begin...
8097 23:19:40.085921 ==
8098 23:19:40.088875 Dram Type= 6, Freq= 0, CH_1, rank 0
8099 23:19:40.095375 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8100 23:19:40.095959 ==
8101 23:19:40.098363 Write leveling (Byte 0): 23 => 23
8102 23:19:40.098922 Write leveling (Byte 1): 21 => 21
8103 23:19:40.101576 DramcWriteLeveling(PI) end<-----
8104 23:19:40.102153
8105 23:19:40.104804 ==
8106 23:19:40.105262 Dram Type= 6, Freq= 0, CH_1, rank 0
8107 23:19:40.112059 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8108 23:19:40.112602 ==
8109 23:19:40.115336 [Gating] SW mode calibration
8110 23:19:40.121189 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8111 23:19:40.124537 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8112 23:19:40.131831 0 12 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8113 23:19:40.135222 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8114 23:19:40.138573 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8115 23:19:40.144547 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8116 23:19:40.148853 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8117 23:19:40.151826 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8118 23:19:40.157907 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
8119 23:19:40.161277 0 12 28 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8120 23:19:40.164779 0 13 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8121 23:19:40.171214 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8122 23:19:40.174751 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8123 23:19:40.177671 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8124 23:19:40.185029 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8125 23:19:40.188072 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8126 23:19:40.191352 0 13 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8127 23:19:40.197978 0 13 28 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8128 23:19:40.201898 0 14 0 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8129 23:19:40.204159 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8130 23:19:40.211205 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8131 23:19:40.214039 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8132 23:19:40.217180 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8133 23:19:40.224163 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 23:19:40.228314 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8135 23:19:40.230347 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8136 23:19:40.237149 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8137 23:19:40.240755 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8138 23:19:40.243801 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 23:19:40.250972 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 23:19:40.253917 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 23:19:40.257291 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 23:19:40.264014 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 23:19:40.266997 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 23:19:40.270586 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 23:19:40.273832 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 23:19:40.280455 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 23:19:40.283652 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 23:19:40.290223 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 23:19:40.293462 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 23:19:40.297420 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8151 23:19:40.303837 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8152 23:19:40.307092 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8153 23:19:40.310042 Total UI for P1: 0, mck2ui 16
8154 23:19:40.313594 best dqsien dly found for B0: ( 1, 0, 26)
8155 23:19:40.316823 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8156 23:19:40.320358 Total UI for P1: 0, mck2ui 16
8157 23:19:40.323252 best dqsien dly found for B1: ( 1, 1, 0)
8158 23:19:40.327116 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8159 23:19:40.329776 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8160 23:19:40.330236
8161 23:19:40.332692 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8162 23:19:40.339838 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8163 23:19:40.340396 [Gating] SW calibration Done
8164 23:19:40.340847 ==
8165 23:19:40.343267 Dram Type= 6, Freq= 0, CH_1, rank 0
8166 23:19:40.350107 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8167 23:19:40.350674 ==
8168 23:19:40.351037 RX Vref Scan: 0
8169 23:19:40.351370
8170 23:19:40.352908 RX Vref 0 -> 0, step: 1
8171 23:19:40.353365
8172 23:19:40.356621 RX Delay 0 -> 252, step: 8
8173 23:19:40.360090 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8174 23:19:40.362945 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8175 23:19:40.366293 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8176 23:19:40.370138 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8177 23:19:40.376579 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8178 23:19:40.380154 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8179 23:19:40.383442 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8180 23:19:40.386311 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8181 23:19:40.389584 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8182 23:19:40.395901 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8183 23:19:40.399905 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8184 23:19:40.402730 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8185 23:19:40.407094 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8186 23:19:40.412584 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8187 23:19:40.416102 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8188 23:19:40.419426 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8189 23:19:40.419987 ==
8190 23:19:40.422704 Dram Type= 6, Freq= 0, CH_1, rank 0
8191 23:19:40.426002 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8192 23:19:40.426465 ==
8193 23:19:40.429407 DQS Delay:
8194 23:19:40.429863 DQS0 = 0, DQS1 = 0
8195 23:19:40.432621 DQM Delay:
8196 23:19:40.433223 DQM0 = 130, DQM1 = 126
8197 23:19:40.433590 DQ Delay:
8198 23:19:40.439936 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8199 23:19:40.442651 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8200 23:19:40.446502 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =115
8201 23:19:40.449087 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8202 23:19:40.449577
8203 23:19:40.449941
8204 23:19:40.450276 ==
8205 23:19:40.452063 Dram Type= 6, Freq= 0, CH_1, rank 0
8206 23:19:40.455805 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8207 23:19:40.456379 ==
8208 23:19:40.456798
8209 23:19:40.457146
8210 23:19:40.459073 TX Vref Scan disable
8211 23:19:40.461862 == TX Byte 0 ==
8212 23:19:40.465831 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8213 23:19:40.469488 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8214 23:19:40.472549 == TX Byte 1 ==
8215 23:19:40.475257 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8216 23:19:40.478966 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8217 23:19:40.479525 ==
8218 23:19:40.482335 Dram Type= 6, Freq= 0, CH_1, rank 0
8219 23:19:40.488238 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8220 23:19:40.488783 ==
8221 23:19:40.499920
8222 23:19:40.502541 TX Vref early break, caculate TX vref
8223 23:19:40.506478 TX Vref=16, minBit 0, minWin=22, winSum=368
8224 23:19:40.509512 TX Vref=18, minBit 3, minWin=21, winSum=374
8225 23:19:40.513107 TX Vref=20, minBit 3, minWin=22, winSum=385
8226 23:19:40.515785 TX Vref=22, minBit 3, minWin=22, winSum=394
8227 23:19:40.521059 TX Vref=24, minBit 0, minWin=24, winSum=404
8228 23:19:40.525915 TX Vref=26, minBit 3, minWin=24, winSum=416
8229 23:19:40.528858 TX Vref=28, minBit 0, minWin=25, winSum=413
8230 23:19:40.532953 TX Vref=30, minBit 0, minWin=24, winSum=408
8231 23:19:40.535731 TX Vref=32, minBit 0, minWin=24, winSum=399
8232 23:19:40.538654 TX Vref=34, minBit 1, minWin=23, winSum=392
8233 23:19:40.545498 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8234 23:19:40.545618
8235 23:19:40.548954 Final TX Range 0 Vref 28
8236 23:19:40.549058
8237 23:19:40.549139 ==
8238 23:19:40.551982 Dram Type= 6, Freq= 0, CH_1, rank 0
8239 23:19:40.555363 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8240 23:19:40.555458 ==
8241 23:19:40.555530
8242 23:19:40.555597
8243 23:19:40.559045 TX Vref Scan disable
8244 23:19:40.565661 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8245 23:19:40.565743 == TX Byte 0 ==
8246 23:19:40.568412 u2DelayCellOfst[0]=14 cells (4 PI)
8247 23:19:40.572675 u2DelayCellOfst[1]=10 cells (3 PI)
8248 23:19:40.575331 u2DelayCellOfst[2]=0 cells (0 PI)
8249 23:19:40.579145 u2DelayCellOfst[3]=7 cells (2 PI)
8250 23:19:40.582115 u2DelayCellOfst[4]=7 cells (2 PI)
8251 23:19:40.585100 u2DelayCellOfst[5]=14 cells (4 PI)
8252 23:19:40.588585 u2DelayCellOfst[6]=14 cells (4 PI)
8253 23:19:40.588692 u2DelayCellOfst[7]=7 cells (2 PI)
8254 23:19:40.595307 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8255 23:19:40.598506 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8256 23:19:40.598589 == TX Byte 1 ==
8257 23:19:40.602225 u2DelayCellOfst[8]=0 cells (0 PI)
8258 23:19:40.605787 u2DelayCellOfst[9]=7 cells (2 PI)
8259 23:19:40.609237 u2DelayCellOfst[10]=10 cells (3 PI)
8260 23:19:40.612653 u2DelayCellOfst[11]=3 cells (1 PI)
8261 23:19:40.615208 u2DelayCellOfst[12]=18 cells (5 PI)
8262 23:19:40.619467 u2DelayCellOfst[13]=18 cells (5 PI)
8263 23:19:40.621991 u2DelayCellOfst[14]=18 cells (5 PI)
8264 23:19:40.625159 u2DelayCellOfst[15]=18 cells (5 PI)
8265 23:19:40.629649 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8266 23:19:40.634986 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8267 23:19:40.635148 DramC Write-DBI on
8268 23:19:40.635237 ==
8269 23:19:40.639189 Dram Type= 6, Freq= 0, CH_1, rank 0
8270 23:19:40.641460 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8271 23:19:40.645245 ==
8272 23:19:40.645430
8273 23:19:40.645532
8274 23:19:40.645621 TX Vref Scan disable
8275 23:19:40.648236 == TX Byte 0 ==
8276 23:19:40.651598 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8277 23:19:40.654685 == TX Byte 1 ==
8278 23:19:40.659018 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8279 23:19:40.661555 DramC Write-DBI off
8280 23:19:40.661742
8281 23:19:40.661890 [DATLAT]
8282 23:19:40.662014 Freq=1600, CH1 RK0
8283 23:19:40.662132
8284 23:19:40.665770 DATLAT Default: 0xf
8285 23:19:40.666011 0, 0xFFFF, sum = 0
8286 23:19:40.669152 1, 0xFFFF, sum = 0
8287 23:19:40.672424 2, 0xFFFF, sum = 0
8288 23:19:40.672700 3, 0xFFFF, sum = 0
8289 23:19:40.675516 4, 0xFFFF, sum = 0
8290 23:19:40.675730 5, 0xFFFF, sum = 0
8291 23:19:40.678538 6, 0xFFFF, sum = 0
8292 23:19:40.678885 7, 0xFFFF, sum = 0
8293 23:19:40.681682 8, 0xFFFF, sum = 0
8294 23:19:40.682098 9, 0xFFFF, sum = 0
8295 23:19:40.684927 10, 0xFFFF, sum = 0
8296 23:19:40.685291 11, 0xFFFF, sum = 0
8297 23:19:40.688026 12, 0x8FFF, sum = 0
8298 23:19:40.688682 13, 0x0, sum = 1
8299 23:19:40.691506 14, 0x0, sum = 2
8300 23:19:40.691965 15, 0x0, sum = 3
8301 23:19:40.694990 16, 0x0, sum = 4
8302 23:19:40.695459 best_step = 14
8303 23:19:40.695826
8304 23:19:40.696162 ==
8305 23:19:40.698290 Dram Type= 6, Freq= 0, CH_1, rank 0
8306 23:19:40.701546 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8307 23:19:40.704997 ==
8308 23:19:40.705599 RX Vref Scan: 1
8309 23:19:40.705983
8310 23:19:40.708796 Set Vref Range= 24 -> 127
8311 23:19:40.709262
8312 23:19:40.711455 RX Vref 24 -> 127, step: 1
8313 23:19:40.711914
8314 23:19:40.712270 RX Delay 11 -> 252, step: 4
8315 23:19:40.712608
8316 23:19:40.714655 Set Vref, RX VrefLevel [Byte0]: 24
8317 23:19:40.717777 [Byte1]: 24
8318 23:19:40.721942
8319 23:19:40.722451 Set Vref, RX VrefLevel [Byte0]: 25
8320 23:19:40.725199 [Byte1]: 25
8321 23:19:40.729390
8322 23:19:40.729853 Set Vref, RX VrefLevel [Byte0]: 26
8323 23:19:40.732785 [Byte1]: 26
8324 23:19:40.737262
8325 23:19:40.737727 Set Vref, RX VrefLevel [Byte0]: 27
8326 23:19:40.741010 [Byte1]: 27
8327 23:19:40.745141
8328 23:19:40.745619 Set Vref, RX VrefLevel [Byte0]: 28
8329 23:19:40.747846 [Byte1]: 28
8330 23:19:40.752526
8331 23:19:40.752815 Set Vref, RX VrefLevel [Byte0]: 29
8332 23:19:40.756075 [Byte1]: 29
8333 23:19:40.759488
8334 23:19:40.759713 Set Vref, RX VrefLevel [Byte0]: 30
8335 23:19:40.763339 [Byte1]: 30
8336 23:19:40.767282
8337 23:19:40.767433 Set Vref, RX VrefLevel [Byte0]: 31
8338 23:19:40.770883 [Byte1]: 31
8339 23:19:40.774922
8340 23:19:40.775075 Set Vref, RX VrefLevel [Byte0]: 32
8341 23:19:40.778702 [Byte1]: 32
8342 23:19:40.782751
8343 23:19:40.782860 Set Vref, RX VrefLevel [Byte0]: 33
8344 23:19:40.786108 [Byte1]: 33
8345 23:19:40.791097
8346 23:19:40.791260 Set Vref, RX VrefLevel [Byte0]: 34
8347 23:19:40.793615 [Byte1]: 34
8348 23:19:40.797720
8349 23:19:40.801431 Set Vref, RX VrefLevel [Byte0]: 35
8350 23:19:40.804447 [Byte1]: 35
8351 23:19:40.804593
8352 23:19:40.807722 Set Vref, RX VrefLevel [Byte0]: 36
8353 23:19:40.810853 [Byte1]: 36
8354 23:19:40.810996
8355 23:19:40.814155 Set Vref, RX VrefLevel [Byte0]: 37
8356 23:19:40.817244 [Byte1]: 37
8357 23:19:40.817400
8358 23:19:40.820430 Set Vref, RX VrefLevel [Byte0]: 38
8359 23:19:40.823960 [Byte1]: 38
8360 23:19:40.828152
8361 23:19:40.828305 Set Vref, RX VrefLevel [Byte0]: 39
8362 23:19:40.831257 [Byte1]: 39
8363 23:19:40.835666
8364 23:19:40.835778 Set Vref, RX VrefLevel [Byte0]: 40
8365 23:19:40.839120 [Byte1]: 40
8366 23:19:40.843379
8367 23:19:40.843606 Set Vref, RX VrefLevel [Byte0]: 41
8368 23:19:40.847247 [Byte1]: 41
8369 23:19:40.851261
8370 23:19:40.851502 Set Vref, RX VrefLevel [Byte0]: 42
8371 23:19:40.854706 [Byte1]: 42
8372 23:19:40.858483
8373 23:19:40.858693 Set Vref, RX VrefLevel [Byte0]: 43
8374 23:19:40.861800 [Byte1]: 43
8375 23:19:40.867169
8376 23:19:40.867490 Set Vref, RX VrefLevel [Byte0]: 44
8377 23:19:40.869913 [Byte1]: 44
8378 23:19:40.874520
8379 23:19:40.875133 Set Vref, RX VrefLevel [Byte0]: 45
8380 23:19:40.877326 [Byte1]: 45
8381 23:19:40.882511
8382 23:19:40.883054 Set Vref, RX VrefLevel [Byte0]: 46
8383 23:19:40.885587 [Byte1]: 46
8384 23:19:40.889649
8385 23:19:40.890311 Set Vref, RX VrefLevel [Byte0]: 47
8386 23:19:40.894021 [Byte1]: 47
8387 23:19:40.898006
8388 23:19:40.898506 Set Vref, RX VrefLevel [Byte0]: 48
8389 23:19:40.900225 [Byte1]: 48
8390 23:19:40.904360
8391 23:19:40.904990 Set Vref, RX VrefLevel [Byte0]: 49
8392 23:19:40.907700 [Byte1]: 49
8393 23:19:40.912342
8394 23:19:40.913054 Set Vref, RX VrefLevel [Byte0]: 50
8395 23:19:40.915445 [Byte1]: 50
8396 23:19:40.919943
8397 23:19:40.920361 Set Vref, RX VrefLevel [Byte0]: 51
8398 23:19:40.923617 [Byte1]: 51
8399 23:19:40.928209
8400 23:19:40.928694 Set Vref, RX VrefLevel [Byte0]: 52
8401 23:19:40.930914 [Byte1]: 52
8402 23:19:40.934734
8403 23:19:40.935191 Set Vref, RX VrefLevel [Byte0]: 53
8404 23:19:40.938399 [Byte1]: 53
8405 23:19:40.942635
8406 23:19:40.943053 Set Vref, RX VrefLevel [Byte0]: 54
8407 23:19:40.946014 [Byte1]: 54
8408 23:19:40.950325
8409 23:19:40.950811 Set Vref, RX VrefLevel [Byte0]: 55
8410 23:19:40.953827 [Byte1]: 55
8411 23:19:40.958249
8412 23:19:40.958755 Set Vref, RX VrefLevel [Byte0]: 56
8413 23:19:40.961233 [Byte1]: 56
8414 23:19:40.965361
8415 23:19:40.965780 Set Vref, RX VrefLevel [Byte0]: 57
8416 23:19:40.969025 [Byte1]: 57
8417 23:19:40.973495
8418 23:19:40.973914 Set Vref, RX VrefLevel [Byte0]: 58
8419 23:19:40.976834 [Byte1]: 58
8420 23:19:40.981480
8421 23:19:40.981935 Set Vref, RX VrefLevel [Byte0]: 59
8422 23:19:40.984424 [Byte1]: 59
8423 23:19:40.988803
8424 23:19:40.989297 Set Vref, RX VrefLevel [Byte0]: 60
8425 23:19:40.992073 [Byte1]: 60
8426 23:19:40.996265
8427 23:19:40.996777 Set Vref, RX VrefLevel [Byte0]: 61
8428 23:19:40.999522 [Byte1]: 61
8429 23:19:41.004289
8430 23:19:41.004854 Set Vref, RX VrefLevel [Byte0]: 62
8431 23:19:41.007026 [Byte1]: 62
8432 23:19:41.012052
8433 23:19:41.012604 Set Vref, RX VrefLevel [Byte0]: 63
8434 23:19:41.014796 [Byte1]: 63
8435 23:19:41.019373
8436 23:19:41.019916 Set Vref, RX VrefLevel [Byte0]: 64
8437 23:19:41.022395 [Byte1]: 64
8438 23:19:41.026187
8439 23:19:41.026879 Set Vref, RX VrefLevel [Byte0]: 65
8440 23:19:41.029962 [Byte1]: 65
8441 23:19:41.033979
8442 23:19:41.034438 Set Vref, RX VrefLevel [Byte0]: 66
8443 23:19:41.037346 [Byte1]: 66
8444 23:19:41.042216
8445 23:19:41.042817 Set Vref, RX VrefLevel [Byte0]: 67
8446 23:19:41.044836 [Byte1]: 67
8447 23:19:41.049278
8448 23:19:41.049690 Set Vref, RX VrefLevel [Byte0]: 68
8449 23:19:41.052221 [Byte1]: 68
8450 23:19:41.057670
8451 23:19:41.058335 Set Vref, RX VrefLevel [Byte0]: 69
8452 23:19:41.060227 [Byte1]: 69
8453 23:19:41.065906
8454 23:19:41.066409 Set Vref, RX VrefLevel [Byte0]: 70
8455 23:19:41.067536 [Byte1]: 70
8456 23:19:41.071914
8457 23:19:41.072394 Set Vref, RX VrefLevel [Byte0]: 71
8458 23:19:41.075391 [Byte1]: 71
8459 23:19:41.080207
8460 23:19:41.080808 Set Vref, RX VrefLevel [Byte0]: 72
8461 23:19:41.083095 [Byte1]: 72
8462 23:19:41.087783
8463 23:19:41.088309 Set Vref, RX VrefLevel [Byte0]: 73
8464 23:19:41.091352 [Byte1]: 73
8465 23:19:41.095290
8466 23:19:41.095707 Final RX Vref Byte 0 = 59 to rank0
8467 23:19:41.098736 Final RX Vref Byte 1 = 53 to rank0
8468 23:19:41.102213 Final RX Vref Byte 0 = 59 to rank1
8469 23:19:41.105461 Final RX Vref Byte 1 = 53 to rank1==
8470 23:19:41.108765 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 23:19:41.114675 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8472 23:19:41.115185 ==
8473 23:19:41.115523 DQS Delay:
8474 23:19:41.115834 DQS0 = 0, DQS1 = 0
8475 23:19:41.118348 DQM Delay:
8476 23:19:41.118768 DQM0 = 129, DQM1 = 122
8477 23:19:41.121460 DQ Delay:
8478 23:19:41.125005 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8479 23:19:41.128467 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8480 23:19:41.131626 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =114
8481 23:19:41.135194 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132
8482 23:19:41.135679
8483 23:19:41.136034
8484 23:19:41.136347
8485 23:19:41.137817 [DramC_TX_OE_Calibration] TA2
8486 23:19:41.142419 Original DQ_B0 (3 6) =30, OEN = 27
8487 23:19:41.144791 Original DQ_B1 (3 6) =30, OEN = 27
8488 23:19:41.147843 24, 0x0, End_B0=24 End_B1=24
8489 23:19:41.148340 25, 0x0, End_B0=25 End_B1=25
8490 23:19:41.151051 26, 0x0, End_B0=26 End_B1=26
8491 23:19:41.154881 27, 0x0, End_B0=27 End_B1=27
8492 23:19:41.157963 28, 0x0, End_B0=28 End_B1=28
8493 23:19:41.161566 29, 0x0, End_B0=29 End_B1=29
8494 23:19:41.161994 30, 0x0, End_B0=30 End_B1=30
8495 23:19:41.164687 31, 0x4141, End_B0=30 End_B1=30
8496 23:19:41.167578 Byte0 end_step=30 best_step=27
8497 23:19:41.171644 Byte1 end_step=30 best_step=27
8498 23:19:41.174536 Byte0 TX OE(2T, 0.5T) = (3, 3)
8499 23:19:41.177433 Byte1 TX OE(2T, 0.5T) = (3, 3)
8500 23:19:41.178030
8501 23:19:41.178371
8502 23:19:41.184136 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8503 23:19:41.187989 CH1 RK0: MR19=303, MR18=2929
8504 23:19:41.194216 CH1_RK0: MR19=0x303, MR18=0x2929, DQSOSC=389, MR23=63, INC=24, DEC=16
8505 23:19:41.194699
8506 23:19:41.198095 ----->DramcWriteLeveling(PI) begin...
8507 23:19:41.198522 ==
8508 23:19:41.204572 Dram Type= 6, Freq= 0, CH_1, rank 1
8509 23:19:41.205119 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8510 23:19:41.205464 ==
8511 23:19:41.208015 Write leveling (Byte 0): 22 => 22
8512 23:19:41.211213 Write leveling (Byte 1): 20 => 20
8513 23:19:41.214507 DramcWriteLeveling(PI) end<-----
8514 23:19:41.214929
8515 23:19:41.215264 ==
8516 23:19:41.217288 Dram Type= 6, Freq= 0, CH_1, rank 1
8517 23:19:41.220849 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8518 23:19:41.221340 ==
8519 23:19:41.223990 [Gating] SW mode calibration
8520 23:19:41.230443 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8521 23:19:41.237445 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8522 23:19:41.240573 0 12 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8523 23:19:41.247393 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8524 23:19:41.251770 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8525 23:19:41.253534 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8526 23:19:41.260252 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8527 23:19:41.263477 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8528 23:19:41.266866 0 12 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8529 23:19:41.273320 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8530 23:19:41.277241 0 13 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8531 23:19:41.280547 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8532 23:19:41.286552 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8533 23:19:41.289795 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8534 23:19:41.293304 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8535 23:19:41.299919 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8536 23:19:41.303604 0 13 24 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (1 1)
8537 23:19:41.306944 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8538 23:19:41.313548 0 14 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8539 23:19:41.316870 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8540 23:19:41.320086 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8541 23:19:41.326155 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8542 23:19:41.329968 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8543 23:19:41.332595 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8544 23:19:41.339689 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8545 23:19:41.342408 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8546 23:19:41.346685 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8547 23:19:41.353535 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8548 23:19:41.356357 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8549 23:19:41.359201 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8550 23:19:41.366424 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8551 23:19:41.369301 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8552 23:19:41.372879 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8553 23:19:41.379321 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8554 23:19:41.382217 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8555 23:19:41.386527 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8556 23:19:41.392384 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8557 23:19:41.395482 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8558 23:19:41.399033 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8559 23:19:41.405639 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8560 23:19:41.409166 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8561 23:19:41.412109 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8562 23:19:41.415718 Total UI for P1: 0, mck2ui 16
8563 23:19:41.419105 best dqsien dly found for B0: ( 1, 0, 22)
8564 23:19:41.421927 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8565 23:19:41.429245 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8566 23:19:41.432388 Total UI for P1: 0, mck2ui 16
8567 23:19:41.435526 best dqsien dly found for B1: ( 1, 0, 30)
8568 23:19:41.438879 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8569 23:19:41.442091 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8570 23:19:41.442564
8571 23:19:41.445432 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8572 23:19:41.448784 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8573 23:19:41.452084 [Gating] SW calibration Done
8574 23:19:41.452605 ==
8575 23:19:41.455030 Dram Type= 6, Freq= 0, CH_1, rank 1
8576 23:19:41.458801 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8577 23:19:41.459334 ==
8578 23:19:41.462548 RX Vref Scan: 0
8579 23:19:41.463079
8580 23:19:41.464941 RX Vref 0 -> 0, step: 1
8581 23:19:41.465367
8582 23:19:41.465806 RX Delay 0 -> 252, step: 8
8583 23:19:41.471818 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8584 23:19:41.474978 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8585 23:19:41.478239 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8586 23:19:41.481675 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8587 23:19:41.484981 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8588 23:19:41.491403 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8589 23:19:41.495005 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8590 23:19:41.498295 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8591 23:19:41.501953 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8592 23:19:41.504454 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8593 23:19:41.512193 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8594 23:19:41.515834 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8595 23:19:41.518099 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8596 23:19:41.521343 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8597 23:19:41.528432 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8598 23:19:41.531491 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8599 23:19:41.531949 ==
8600 23:19:41.534335 Dram Type= 6, Freq= 0, CH_1, rank 1
8601 23:19:41.537678 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8602 23:19:41.538136 ==
8603 23:19:41.541609 DQS Delay:
8604 23:19:41.542060 DQS0 = 0, DQS1 = 0
8605 23:19:41.542416 DQM Delay:
8606 23:19:41.544833 DQM0 = 129, DQM1 = 125
8607 23:19:41.545291 DQ Delay:
8608 23:19:41.547534 DQ0 =131, DQ1 =123, DQ2 =115, DQ3 =131
8609 23:19:41.550912 DQ4 =123, DQ5 =143, DQ6 =139, DQ7 =131
8610 23:19:41.555166 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8611 23:19:41.561100 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8612 23:19:41.561644
8613 23:19:41.562001
8614 23:19:41.562332 ==
8615 23:19:41.564137 Dram Type= 6, Freq= 0, CH_1, rank 1
8616 23:19:41.567623 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8617 23:19:41.568182 ==
8618 23:19:41.568542
8619 23:19:41.568949
8620 23:19:41.571331 TX Vref Scan disable
8621 23:19:41.571788 == TX Byte 0 ==
8622 23:19:41.577584 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8623 23:19:41.580939 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8624 23:19:41.581492 == TX Byte 1 ==
8625 23:19:41.587335 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8626 23:19:41.590366 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8627 23:19:41.590828 ==
8628 23:19:41.594035 Dram Type= 6, Freq= 0, CH_1, rank 1
8629 23:19:41.597247 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8630 23:19:41.597808 ==
8631 23:19:41.610949
8632 23:19:41.614555 TX Vref early break, caculate TX vref
8633 23:19:41.617358 TX Vref=16, minBit 3, minWin=21, winSum=377
8634 23:19:41.622121 TX Vref=18, minBit 0, minWin=23, winSum=387
8635 23:19:41.624003 TX Vref=20, minBit 0, minWin=23, winSum=401
8636 23:19:41.627611 TX Vref=22, minBit 0, minWin=24, winSum=407
8637 23:19:41.630820 TX Vref=24, minBit 2, minWin=24, winSum=409
8638 23:19:41.637729 TX Vref=26, minBit 0, minWin=25, winSum=418
8639 23:19:41.640853 TX Vref=28, minBit 0, minWin=25, winSum=425
8640 23:19:41.643969 TX Vref=30, minBit 0, minWin=22, winSum=412
8641 23:19:41.648338 TX Vref=32, minBit 5, minWin=23, winSum=411
8642 23:19:41.650631 TX Vref=34, minBit 0, minWin=22, winSum=396
8643 23:19:41.658006 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8644 23:19:41.658595
8645 23:19:41.660525 Final TX Range 0 Vref 28
8646 23:19:41.661035
8647 23:19:41.661402 ==
8648 23:19:41.665092 Dram Type= 6, Freq= 0, CH_1, rank 1
8649 23:19:41.667257 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8650 23:19:41.667833 ==
8651 23:19:41.668199
8652 23:19:41.668532
8653 23:19:41.670968 TX Vref Scan disable
8654 23:19:41.677692 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8655 23:19:41.678261 == TX Byte 0 ==
8656 23:19:41.681450 u2DelayCellOfst[0]=18 cells (5 PI)
8657 23:19:41.684126 u2DelayCellOfst[1]=10 cells (3 PI)
8658 23:19:41.687300 u2DelayCellOfst[2]=0 cells (0 PI)
8659 23:19:41.690533 u2DelayCellOfst[3]=7 cells (2 PI)
8660 23:19:41.694536 u2DelayCellOfst[4]=10 cells (3 PI)
8661 23:19:41.698026 u2DelayCellOfst[5]=18 cells (5 PI)
8662 23:19:41.700675 u2DelayCellOfst[6]=18 cells (5 PI)
8663 23:19:41.703943 u2DelayCellOfst[7]=7 cells (2 PI)
8664 23:19:41.706859 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8665 23:19:41.710392 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8666 23:19:41.713489 == TX Byte 1 ==
8667 23:19:41.713963 u2DelayCellOfst[8]=0 cells (0 PI)
8668 23:19:41.716801 u2DelayCellOfst[9]=7 cells (2 PI)
8669 23:19:41.720610 u2DelayCellOfst[10]=7 cells (2 PI)
8670 23:19:41.723130 u2DelayCellOfst[11]=3 cells (1 PI)
8671 23:19:41.726424 u2DelayCellOfst[12]=14 cells (4 PI)
8672 23:19:41.730050 u2DelayCellOfst[13]=18 cells (5 PI)
8673 23:19:41.734138 u2DelayCellOfst[14]=18 cells (5 PI)
8674 23:19:41.736632 u2DelayCellOfst[15]=18 cells (5 PI)
8675 23:19:41.740200 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8676 23:19:41.747961 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8677 23:19:41.748549 DramC Write-DBI on
8678 23:19:41.749083 ==
8679 23:19:41.750196 Dram Type= 6, Freq= 0, CH_1, rank 1
8680 23:19:41.753588 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8681 23:19:41.757547 ==
8682 23:19:41.758109
8683 23:19:41.758471
8684 23:19:41.758803 TX Vref Scan disable
8685 23:19:41.760313 == TX Byte 0 ==
8686 23:19:41.764187 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8687 23:19:41.766853 == TX Byte 1 ==
8688 23:19:41.771041 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8689 23:19:41.773268 DramC Write-DBI off
8690 23:19:41.773731
8691 23:19:41.774093 [DATLAT]
8692 23:19:41.774430 Freq=1600, CH1 RK1
8693 23:19:41.774755
8694 23:19:41.776792 DATLAT Default: 0xe
8695 23:19:41.780350 0, 0xFFFF, sum = 0
8696 23:19:41.780964 1, 0xFFFF, sum = 0
8697 23:19:41.783972 2, 0xFFFF, sum = 0
8698 23:19:41.784537 3, 0xFFFF, sum = 0
8699 23:19:41.787356 4, 0xFFFF, sum = 0
8700 23:19:41.787822 5, 0xFFFF, sum = 0
8701 23:19:41.789720 6, 0xFFFF, sum = 0
8702 23:19:41.790280 7, 0xFFFF, sum = 0
8703 23:19:41.793243 8, 0xFFFF, sum = 0
8704 23:19:41.793712 9, 0xFFFF, sum = 0
8705 23:19:41.797073 10, 0xFFFF, sum = 0
8706 23:19:41.797539 11, 0xFFFF, sum = 0
8707 23:19:41.800194 12, 0xF7F, sum = 0
8708 23:19:41.800795 13, 0x0, sum = 1
8709 23:19:41.803282 14, 0x0, sum = 2
8710 23:19:41.803766 15, 0x0, sum = 3
8711 23:19:41.806714 16, 0x0, sum = 4
8712 23:19:41.807186 best_step = 14
8713 23:19:41.807555
8714 23:19:41.807895 ==
8715 23:19:41.810018 Dram Type= 6, Freq= 0, CH_1, rank 1
8716 23:19:41.813529 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8717 23:19:41.816666 ==
8718 23:19:41.817295 RX Vref Scan: 0
8719 23:19:41.817690
8720 23:19:41.820435 RX Vref 0 -> 0, step: 1
8721 23:19:41.821062
8722 23:19:41.821434 RX Delay 3 -> 252, step: 4
8723 23:19:41.827477 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8724 23:19:41.830424 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8725 23:19:41.833727 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8726 23:19:41.837307 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8727 23:19:41.840505 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8728 23:19:41.847908 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8729 23:19:41.850702 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8730 23:19:41.853485 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8731 23:19:41.857193 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8732 23:19:41.860335 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8733 23:19:41.867141 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8734 23:19:41.870261 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8735 23:19:41.873120 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8736 23:19:41.876903 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8737 23:19:41.883427 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8738 23:19:41.887389 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8739 23:19:41.887960 ==
8740 23:19:41.890529 Dram Type= 6, Freq= 0, CH_1, rank 1
8741 23:19:41.894005 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8742 23:19:41.894576 ==
8743 23:19:41.896300 DQS Delay:
8744 23:19:41.896809 DQS0 = 0, DQS1 = 0
8745 23:19:41.897182 DQM Delay:
8746 23:19:41.899871 DQM0 = 127, DQM1 = 122
8747 23:19:41.900337 DQ Delay:
8748 23:19:41.904090 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8749 23:19:41.906672 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8750 23:19:41.909758 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8751 23:19:41.916409 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132
8752 23:19:41.917010
8753 23:19:41.917376
8754 23:19:41.917710
8755 23:19:41.920240 [DramC_TX_OE_Calibration] TA2
8756 23:19:41.920851 Original DQ_B0 (3 6) =30, OEN = 27
8757 23:19:41.923584 Original DQ_B1 (3 6) =30, OEN = 27
8758 23:19:41.926545 24, 0x0, End_B0=24 End_B1=24
8759 23:19:41.929999 25, 0x0, End_B0=25 End_B1=25
8760 23:19:41.933006 26, 0x0, End_B0=26 End_B1=26
8761 23:19:41.936861 27, 0x0, End_B0=27 End_B1=27
8762 23:19:41.937426 28, 0x0, End_B0=28 End_B1=28
8763 23:19:41.939528 29, 0x0, End_B0=29 End_B1=29
8764 23:19:41.943526 30, 0x0, End_B0=30 End_B1=30
8765 23:19:41.947021 31, 0x5151, End_B0=30 End_B1=30
8766 23:19:41.950201 Byte0 end_step=30 best_step=27
8767 23:19:41.950771 Byte1 end_step=30 best_step=27
8768 23:19:41.953209 Byte0 TX OE(2T, 0.5T) = (3, 3)
8769 23:19:41.956398 Byte1 TX OE(2T, 0.5T) = (3, 3)
8770 23:19:41.956997
8771 23:19:41.957362
8772 23:19:41.967625 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8773 23:19:41.968193 CH1 RK1: MR19=303, MR18=1C1C
8774 23:19:41.973076 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8775 23:19:41.977108 [RxdqsGatingPostProcess] freq 1600
8776 23:19:41.983432 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8777 23:19:41.986424 Pre-setting of DQS Precalculation
8778 23:19:41.990188 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8779 23:19:41.999524 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8780 23:19:42.006181 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8781 23:19:42.006645
8782 23:19:42.007008
8783 23:19:42.008850 [Calibration Summary] 3200 Mbps
8784 23:19:42.009312 CH 0, Rank 0
8785 23:19:42.013415 SW Impedance : PASS
8786 23:19:42.014003 DUTY Scan : NO K
8787 23:19:42.015762 ZQ Calibration : PASS
8788 23:19:42.019966 Jitter Meter : NO K
8789 23:19:42.020530 CBT Training : PASS
8790 23:19:42.022965 Write leveling : PASS
8791 23:19:42.026002 RX DQS gating : PASS
8792 23:19:42.026470 RX DQ/DQS(RDDQC) : PASS
8793 23:19:42.029898 TX DQ/DQS : PASS
8794 23:19:42.032777 RX DATLAT : PASS
8795 23:19:42.033247 RX DQ/DQS(Engine): PASS
8796 23:19:42.035857 TX OE : PASS
8797 23:19:42.036427 All Pass.
8798 23:19:42.036854
8799 23:19:42.039222 CH 0, Rank 1
8800 23:19:42.039689 SW Impedance : PASS
8801 23:19:42.043121 DUTY Scan : NO K
8802 23:19:42.043692 ZQ Calibration : PASS
8803 23:19:42.046073 Jitter Meter : NO K
8804 23:19:42.049003 CBT Training : PASS
8805 23:19:42.049470 Write leveling : PASS
8806 23:19:42.052492 RX DQS gating : PASS
8807 23:19:42.056944 RX DQ/DQS(RDDQC) : PASS
8808 23:19:42.057510 TX DQ/DQS : PASS
8809 23:19:42.058892 RX DATLAT : PASS
8810 23:19:42.063316 RX DQ/DQS(Engine): PASS
8811 23:19:42.064030 TX OE : PASS
8812 23:19:42.065340 All Pass.
8813 23:19:42.065802
8814 23:19:42.066162 CH 1, Rank 0
8815 23:19:42.069467 SW Impedance : PASS
8816 23:19:42.070031 DUTY Scan : NO K
8817 23:19:42.072014 ZQ Calibration : PASS
8818 23:19:42.075702 Jitter Meter : NO K
8819 23:19:42.076270 CBT Training : PASS
8820 23:19:42.079024 Write leveling : PASS
8821 23:19:42.082494 RX DQS gating : PASS
8822 23:19:42.083057 RX DQ/DQS(RDDQC) : PASS
8823 23:19:42.085608 TX DQ/DQS : PASS
8824 23:19:42.088806 RX DATLAT : PASS
8825 23:19:42.089369 RX DQ/DQS(Engine): PASS
8826 23:19:42.092155 TX OE : PASS
8827 23:19:42.092766 All Pass.
8828 23:19:42.093135
8829 23:19:42.095756 CH 1, Rank 1
8830 23:19:42.096316 SW Impedance : PASS
8831 23:19:42.099181 DUTY Scan : NO K
8832 23:19:42.102376 ZQ Calibration : PASS
8833 23:19:42.102846 Jitter Meter : NO K
8834 23:19:42.105576 CBT Training : PASS
8835 23:19:42.108482 Write leveling : PASS
8836 23:19:42.108967 RX DQS gating : PASS
8837 23:19:42.111652 RX DQ/DQS(RDDQC) : PASS
8838 23:19:42.112203 TX DQ/DQS : PASS
8839 23:19:42.114902 RX DATLAT : PASS
8840 23:19:42.118705 RX DQ/DQS(Engine): PASS
8841 23:19:42.119266 TX OE : PASS
8842 23:19:42.122305 All Pass.
8843 23:19:42.122847
8844 23:19:42.123210 DramC Write-DBI on
8845 23:19:42.125385 PER_BANK_REFRESH: Hybrid Mode
8846 23:19:42.128737 TX_TRACKING: ON
8847 23:19:42.135373 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8848 23:19:42.144568 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8849 23:19:42.151255 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8850 23:19:42.155247 [FAST_K] Save calibration result to emmc
8851 23:19:42.157848 sync common calibartion params.
8852 23:19:42.158310 sync cbt_mode0:0, 1:0
8853 23:19:42.161066 dram_init: ddr_geometry: 0
8854 23:19:42.164916 dram_init: ddr_geometry: 0
8855 23:19:42.168347 dram_init: ddr_geometry: 0
8856 23:19:42.168951 0:dram_rank_size:80000000
8857 23:19:42.174185 1:dram_rank_size:80000000
8858 23:19:42.177895 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8859 23:19:42.178476 DFS_SHUFFLE_HW_MODE: ON
8860 23:19:42.182406 dramc_set_vcore_voltage set vcore to 725000
8861 23:19:42.184891 Read voltage for 1600, 0
8862 23:19:42.185468 Vio18 = 0
8863 23:19:42.188634 Vcore = 725000
8864 23:19:42.189256 Vdram = 0
8865 23:19:42.189744 Vddq = 0
8866 23:19:42.190993 Vmddr = 0
8867 23:19:42.191469 switch to 3200 Mbps bootup
8868 23:19:42.195067 [DramcRunTimeConfig]
8869 23:19:42.195639 PHYPLL
8870 23:19:42.197443 DPM_CONTROL_AFTERK: ON
8871 23:19:42.197923 PER_BANK_REFRESH: ON
8872 23:19:42.201564 REFRESH_OVERHEAD_REDUCTION: ON
8873 23:19:42.204463 CMD_PICG_NEW_MODE: OFF
8874 23:19:42.205093 XRTWTW_NEW_MODE: ON
8875 23:19:42.207656 XRTRTR_NEW_MODE: ON
8876 23:19:42.208234 TX_TRACKING: ON
8877 23:19:42.211788 RDSEL_TRACKING: OFF
8878 23:19:42.213948 DQS Precalculation for DVFS: ON
8879 23:19:42.214428 RX_TRACKING: OFF
8880 23:19:42.218030 HW_GATING DBG: ON
8881 23:19:42.218601 ZQCS_ENABLE_LP4: ON
8882 23:19:42.221320 RX_PICG_NEW_MODE: ON
8883 23:19:42.221906 TX_PICG_NEW_MODE: ON
8884 23:19:42.223909 ENABLE_RX_DCM_DPHY: ON
8885 23:19:42.227561 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8886 23:19:42.230740 DUMMY_READ_FOR_TRACKING: OFF
8887 23:19:42.234236 !!! SPM_CONTROL_AFTERK: OFF
8888 23:19:42.234856 !!! SPM could not control APHY
8889 23:19:42.237088 IMPEDANCE_TRACKING: ON
8890 23:19:42.237568 TEMP_SENSOR: ON
8891 23:19:42.240799 HW_SAVE_FOR_SR: OFF
8892 23:19:42.245025 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8893 23:19:42.247856 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8894 23:19:42.250340 Read ODT Tracking: ON
8895 23:19:42.250803 Refresh Rate DeBounce: ON
8896 23:19:42.254493 DFS_NO_QUEUE_FLUSH: ON
8897 23:19:42.257282 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8898 23:19:42.260378 ENABLE_DFS_RUNTIME_MRW: OFF
8899 23:19:42.260968 DDR_RESERVE_NEW_MODE: ON
8900 23:19:42.264650 MR_CBT_SWITCH_FREQ: ON
8901 23:19:42.267836 =========================
8902 23:19:42.285224 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8903 23:19:42.288996 dram_init: ddr_geometry: 0
8904 23:19:42.306458 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8905 23:19:42.309521 dram_init: dram init end (result: 0)
8906 23:19:42.315864 DRAM-K: Full calibration passed in 23355 msecs
8907 23:19:42.320178 MRC: failed to locate region type 0.
8908 23:19:42.320805 DRAM rank0 size:0x80000000,
8909 23:19:42.322703 DRAM rank1 size=0x80000000
8910 23:19:42.332496 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8911 23:19:42.338984 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8912 23:19:42.345847 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8913 23:19:42.352232 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8914 23:19:42.355479 DRAM rank0 size:0x80000000,
8915 23:19:42.358454 DRAM rank1 size=0x80000000
8916 23:19:42.358953 CBMEM:
8917 23:19:42.361932 IMD: root @ 0xfffff000 254 entries.
8918 23:19:42.365045 IMD: root @ 0xffffec00 62 entries.
8919 23:19:42.368476 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8920 23:19:42.371619 WARNING: RO_VPD is uninitialized or empty.
8921 23:19:42.378659 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8922 23:19:42.385056 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8923 23:19:42.398619 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8924 23:19:42.410078 BS: romstage times (exec / console): total (unknown) / 22906 ms
8925 23:19:42.410249
8926 23:19:42.410355
8927 23:19:42.419199 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8928 23:19:42.423473 ARM64: Exception handlers installed.
8929 23:19:42.425737 ARM64: Testing exception
8930 23:19:42.429123 ARM64: Done test exception
8931 23:19:42.429220 Enumerating buses...
8932 23:19:42.433456 Show all devs... Before device enumeration.
8933 23:19:42.436274 Root Device: enabled 1
8934 23:19:42.439053 CPU_CLUSTER: 0: enabled 1
8935 23:19:42.439173 CPU: 00: enabled 1
8936 23:19:42.442559 Compare with tree...
8937 23:19:42.442760 Root Device: enabled 1
8938 23:19:42.445502 CPU_CLUSTER: 0: enabled 1
8939 23:19:42.449115 CPU: 00: enabled 1
8940 23:19:42.449361 Root Device scanning...
8941 23:19:42.452249 scan_static_bus for Root Device
8942 23:19:42.455769 CPU_CLUSTER: 0 enabled
8943 23:19:42.459271 scan_static_bus for Root Device done
8944 23:19:42.462892 scan_bus: bus Root Device finished in 8 msecs
8945 23:19:42.463091 done
8946 23:19:42.468928 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8947 23:19:42.472673 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8948 23:19:42.479105 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8949 23:19:42.482397 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8950 23:19:42.486082 Allocating resources...
8951 23:19:42.489496 Reading resources...
8952 23:19:42.493345 Root Device read_resources bus 0 link: 0
8953 23:19:42.493914 DRAM rank0 size:0x80000000,
8954 23:19:42.496413 DRAM rank1 size=0x80000000
8955 23:19:42.499086 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8956 23:19:42.502183 CPU: 00 missing read_resources
8957 23:19:42.509614 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8958 23:19:42.512774 Root Device read_resources bus 0 link: 0 done
8959 23:19:42.513246 Done reading resources.
8960 23:19:42.518984 Show resources in subtree (Root Device)...After reading.
8961 23:19:42.522166 Root Device child on link 0 CPU_CLUSTER: 0
8962 23:19:42.525439 CPU_CLUSTER: 0 child on link 0 CPU: 00
8963 23:19:42.535677 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8964 23:19:42.536264 CPU: 00
8965 23:19:42.538523 Root Device assign_resources, bus 0 link: 0
8966 23:19:42.541801 CPU_CLUSTER: 0 missing set_resources
8967 23:19:42.549774 Root Device assign_resources, bus 0 link: 0 done
8968 23:19:42.550344 Done setting resources.
8969 23:19:42.555081 Show resources in subtree (Root Device)...After assigning values.
8970 23:19:42.558525 Root Device child on link 0 CPU_CLUSTER: 0
8971 23:19:42.561801 CPU_CLUSTER: 0 child on link 0 CPU: 00
8972 23:19:42.572131 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8973 23:19:42.572703 CPU: 00
8974 23:19:42.575140 Done allocating resources.
8975 23:19:42.581689 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8976 23:19:42.582273 Enabling resources...
8977 23:19:42.582647 done.
8978 23:19:42.588636 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8979 23:19:42.589238 Initializing devices...
8980 23:19:42.591713 Root Device init
8981 23:19:42.594613 init hardware done!
8982 23:19:42.595173 0x00000018: ctrlr->caps
8983 23:19:42.598513 52.000 MHz: ctrlr->f_max
8984 23:19:42.601405 0.400 MHz: ctrlr->f_min
8985 23:19:42.601902 0x40ff8080: ctrlr->voltages
8986 23:19:42.604869 sclk: 390625
8987 23:19:42.605537 Bus Width = 1
8988 23:19:42.605911 sclk: 390625
8989 23:19:42.608632 Bus Width = 1
8990 23:19:42.609258 Early init status = 3
8991 23:19:42.614608 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8992 23:19:42.617751 in-header: 03 fc 00 00 01 00 00 00
8993 23:19:42.621066 in-data: 00
8994 23:19:42.624844 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8995 23:19:42.630564 in-header: 03 fd 00 00 00 00 00 00
8996 23:19:42.632778 in-data:
8997 23:19:42.636305 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8998 23:19:42.639973 in-header: 03 fc 00 00 01 00 00 00
8999 23:19:42.643333 in-data: 00
9000 23:19:42.647340 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9001 23:19:42.651731 in-header: 03 fd 00 00 00 00 00 00
9002 23:19:42.655191 in-data:
9003 23:19:42.658518 [SSUSB] Setting up USB HOST controller...
9004 23:19:42.661810 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9005 23:19:42.664615 [SSUSB] phy power-on done.
9006 23:19:42.668121 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9007 23:19:42.674476 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9008 23:19:42.678260 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9009 23:19:42.684455 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9010 23:19:42.691406 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9011 23:19:42.697801 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9012 23:19:42.704805 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9013 23:19:42.711384 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9014 23:19:42.714707 SPM: binary array size = 0x9dc
9015 23:19:42.718529 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9016 23:19:42.724489 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9017 23:19:42.731312 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9018 23:19:42.737323 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9019 23:19:42.740484 configure_display: Starting display init
9020 23:19:42.774910 anx7625_power_on_init: Init interface.
9021 23:19:42.778452 anx7625_disable_pd_protocol: Disabled PD feature.
9022 23:19:42.781719 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9023 23:19:42.809718 anx7625_start_dp_work: Secure OCM version=00
9024 23:19:42.813128 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9025 23:19:42.827512 sp_tx_get_edid_block: EDID Block = 1
9026 23:19:42.929854 Extracted contents:
9027 23:19:42.933416 header: 00 ff ff ff ff ff ff 00
9028 23:19:42.936193 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9029 23:19:42.939777 version: 01 04
9030 23:19:42.944435 basic params: 95 1f 11 78 0a
9031 23:19:42.946034 chroma info: 76 90 94 55 54 90 27 21 50 54
9032 23:19:42.949311 established: 00 00 00
9033 23:19:42.956957 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9034 23:19:42.959984 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9035 23:19:42.966697 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9036 23:19:42.972767 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9037 23:19:42.979502 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9038 23:19:42.982422 extensions: 00
9039 23:19:42.982893 checksum: fb
9040 23:19:42.983217
9041 23:19:42.986285 Manufacturer: IVO Model 57d Serial Number 0
9042 23:19:42.989711 Made week 0 of 2020
9043 23:19:42.993192 EDID version: 1.4
9044 23:19:42.993608 Digital display
9045 23:19:42.996147 6 bits per primary color channel
9046 23:19:42.996569 DisplayPort interface
9047 23:19:43.000120 Maximum image size: 31 cm x 17 cm
9048 23:19:43.002986 Gamma: 220%
9049 23:19:43.003399 Check DPMS levels
9050 23:19:43.006542 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9051 23:19:43.012538 First detailed timing is preferred timing
9052 23:19:43.013133 Established timings supported:
9053 23:19:43.015612 Standard timings supported:
9054 23:19:43.018767 Detailed timings
9055 23:19:43.022588 Hex of detail: 383680a07038204018303c0035ae10000019
9056 23:19:43.028812 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9057 23:19:43.032047 0780 0798 07c8 0820 hborder 0
9058 23:19:43.035981 0438 043b 0447 0458 vborder 0
9059 23:19:43.039694 -hsync -vsync
9060 23:19:43.040145 Did detailed timing
9061 23:19:43.045142 Hex of detail: 000000000000000000000000000000000000
9062 23:19:43.048768 Manufacturer-specified data, tag 0
9063 23:19:43.051511 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9064 23:19:43.055553 ASCII string: InfoVision
9065 23:19:43.058525 Hex of detail: 000000fe00523134304e574635205248200a
9066 23:19:43.061672 ASCII string: R140NWF5 RH
9067 23:19:43.062150 Checksum
9068 23:19:43.065101 Checksum: 0xfb (valid)
9069 23:19:43.068778 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9070 23:19:43.071949 DSI data_rate: 832800000 bps
9071 23:19:43.078532 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9072 23:19:43.081329 anx7625_parse_edid: pixelclock(138800).
9073 23:19:43.085014 hactive(1920), hsync(48), hfp(24), hbp(88)
9074 23:19:43.088918 vactive(1080), vsync(12), vfp(3), vbp(17)
9075 23:19:43.091750 anx7625_dsi_config: config dsi.
9076 23:19:43.098400 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9077 23:19:43.112632 anx7625_dsi_config: success to config DSI
9078 23:19:43.115526 anx7625_dp_start: MIPI phy setup OK.
9079 23:19:43.118905 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9080 23:19:43.122355 mtk_ddp_mode_set invalid vrefresh 60
9081 23:19:43.126093 main_disp_path_setup
9082 23:19:43.126552 ovl_layer_smi_id_en
9083 23:19:43.128335 ovl_layer_smi_id_en
9084 23:19:43.128845 ccorr_config
9085 23:19:43.129216 aal_config
9086 23:19:43.131980 gamma_config
9087 23:19:43.132536 postmask_config
9088 23:19:43.134986 dither_config
9089 23:19:43.138520 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9090 23:19:43.145230 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9091 23:19:43.148910 Root Device init finished in 553 msecs
9092 23:19:43.151638 CPU_CLUSTER: 0 init
9093 23:19:43.158490 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9094 23:19:43.161569 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9095 23:19:43.165127 APU_MBOX 0x190000b0 = 0x10001
9096 23:19:43.168683 APU_MBOX 0x190001b0 = 0x10001
9097 23:19:43.172314 APU_MBOX 0x190005b0 = 0x10001
9098 23:19:43.174512 APU_MBOX 0x190006b0 = 0x10001
9099 23:19:43.181610 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9100 23:19:43.191472 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9101 23:19:43.203661 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9102 23:19:43.210321 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9103 23:19:43.221634 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9104 23:19:43.230733 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9105 23:19:43.234056 CPU_CLUSTER: 0 init finished in 81 msecs
9106 23:19:43.237436 Devices initialized
9107 23:19:43.240283 Show all devs... After init.
9108 23:19:43.241009 Root Device: enabled 1
9109 23:19:43.244370 CPU_CLUSTER: 0: enabled 1
9110 23:19:43.247535 CPU: 00: enabled 1
9111 23:19:43.250730 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9112 23:19:43.254166 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9113 23:19:43.256913 ELOG: NV offset 0x57f000 size 0x1000
9114 23:19:43.263568 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9115 23:19:43.270045 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9116 23:19:43.274436 ELOG: Event(17) added with size 13 at 2024-04-03 23:19:44 UTC
9117 23:19:43.280137 out: cmd=0x121: 03 db 21 01 00 00 00 00
9118 23:19:43.283628 in-header: 03 40 00 00 2c 00 00 00
9119 23:19:43.293954 in-data: 23 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9120 23:19:43.300660 ELOG: Event(A1) added with size 10 at 2024-04-03 23:19:44 UTC
9121 23:19:43.307320 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9122 23:19:43.313636 ELOG: Event(A0) added with size 9 at 2024-04-03 23:19:44 UTC
9123 23:19:43.317390 elog_add_boot_reason: Logged dev mode boot
9124 23:19:43.323330 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9125 23:19:43.323901 Finalize devices...
9126 23:19:43.326447 Devices finalized
9127 23:19:43.329842 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9128 23:19:43.333504 Writing coreboot table at 0xffe64000
9129 23:19:43.336231 0. 000000000010a000-0000000000113fff: RAMSTAGE
9130 23:19:43.342980 1. 0000000040000000-00000000400fffff: RAM
9131 23:19:43.346335 2. 0000000040100000-000000004032afff: RAMSTAGE
9132 23:19:43.349535 3. 000000004032b000-00000000545fffff: RAM
9133 23:19:43.353206 4. 0000000054600000-000000005465ffff: BL31
9134 23:19:43.356144 5. 0000000054660000-00000000ffe63fff: RAM
9135 23:19:43.362994 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9136 23:19:43.366682 7. 0000000100000000-000000013fffffff: RAM
9137 23:19:43.369455 Passing 5 GPIOs to payload:
9138 23:19:43.373179 NAME | PORT | POLARITY | VALUE
9139 23:19:43.379882 EC in RW | 0x000000aa | low | undefined
9140 23:19:43.382731 EC interrupt | 0x00000005 | low | undefined
9141 23:19:43.387431 TPM interrupt | 0x000000ab | high | undefined
9142 23:19:43.392272 SD card detect | 0x00000011 | high | undefined
9143 23:19:43.396086 speaker enable | 0x00000093 | high | undefined
9144 23:19:43.399358 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9145 23:19:43.402759 in-header: 03 f8 00 00 02 00 00 00
9146 23:19:43.406383 in-data: 03 00
9147 23:19:43.408997 ADC[4]: Raw value=668958 ID=5
9148 23:19:43.409461 ADC[3]: Raw value=212549 ID=1
9149 23:19:43.412772 RAM Code: 0x51
9150 23:19:43.416899 ADC[6]: Raw value=74778 ID=0
9151 23:19:43.417476 ADC[5]: Raw value=211444 ID=1
9152 23:19:43.420033 SKU Code: 0x1
9153 23:19:43.425456 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c27f
9154 23:19:43.426010 coreboot table: 964 bytes.
9155 23:19:43.428925 IMD ROOT 0. 0xfffff000 0x00001000
9156 23:19:43.432115 IMD SMALL 1. 0xffffe000 0x00001000
9157 23:19:43.435300 RO MCACHE 2. 0xffffc000 0x00001104
9158 23:19:43.438808 CONSOLE 3. 0xfff7c000 0x00080000
9159 23:19:43.442261 FMAP 4. 0xfff7b000 0x00000452
9160 23:19:43.444834 TIME STAMP 5. 0xfff7a000 0x00000910
9161 23:19:43.448244 VBOOT WORK 6. 0xfff66000 0x00014000
9162 23:19:43.451639 RAMOOPS 7. 0xffe66000 0x00100000
9163 23:19:43.455171 COREBOOT 8. 0xffe64000 0x00002000
9164 23:19:43.458475 IMD small region:
9165 23:19:43.462550 IMD ROOT 0. 0xffffec00 0x00000400
9166 23:19:43.465537 VPD 1. 0xffffeb80 0x0000006c
9167 23:19:43.468897 MMC STATUS 2. 0xffffeb60 0x00000004
9168 23:19:43.471723 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9169 23:19:43.474911 Probing TPM: done!
9170 23:19:43.478678 Connected to device vid:did:rid of 1ae0:0028:00
9171 23:19:43.489994 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9172 23:19:43.493151 Initialized TPM device CR50 revision 0
9173 23:19:43.497457 Checking cr50 for pending updates
9174 23:19:43.500269 Reading cr50 TPM mode
9175 23:19:43.509494 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9176 23:19:43.515740 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9177 23:19:43.555737 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9178 23:19:43.559294 Checking segment from ROM address 0x40100000
9179 23:19:43.570531 Checking segment from ROM address 0x4010001c
9180 23:19:43.571090 Loading segment from ROM address 0x40100000
9181 23:19:43.571456 code (compression=0)
9182 23:19:43.578940 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9183 23:19:43.585836 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9184 23:19:43.586384 it's not compressed!
9185 23:19:43.591970 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9186 23:19:43.596311 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9187 23:19:43.616261 Loading segment from ROM address 0x4010001c
9188 23:19:43.616865 Entry Point 0x80000000
9189 23:19:43.619547 Loaded segments
9190 23:19:43.622955 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9191 23:19:43.629586 Jumping to boot code at 0x80000000(0xffe64000)
9192 23:19:43.635894 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9193 23:19:43.642569 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9194 23:19:43.650916 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9195 23:19:43.653676 Checking segment from ROM address 0x40100000
9196 23:19:43.657217 Checking segment from ROM address 0x4010001c
9197 23:19:43.663532 Loading segment from ROM address 0x40100000
9198 23:19:43.664199 code (compression=1)
9199 23:19:43.670432 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9200 23:19:43.680430 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9201 23:19:43.681211 using LZMA
9202 23:19:43.688313 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9203 23:19:43.694771 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9204 23:19:43.698370 Loading segment from ROM address 0x4010001c
9205 23:19:43.698621 Entry Point 0x54601000
9206 23:19:43.702025 Loaded segments
9207 23:19:43.705111 NOTICE: MT8192 bl31_setup
9208 23:19:43.715222 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9209 23:19:43.717098 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9210 23:19:43.720312 WARNING: region 0:
9211 23:19:43.722219 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9212 23:19:43.722357 WARNING: region 1:
9213 23:19:43.728636 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9214 23:19:43.732092 WARNING: region 2:
9215 23:19:43.735418 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9216 23:19:43.739009 WARNING: region 3:
9217 23:19:43.741672 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9218 23:19:43.745090 WARNING: region 4:
9219 23:19:43.752037 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9220 23:19:43.752174 WARNING: region 5:
9221 23:19:43.755342 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9222 23:19:43.758756 WARNING: region 6:
9223 23:19:43.761671 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9224 23:19:43.765158 WARNING: region 7:
9225 23:19:43.769075 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9226 23:19:43.775147 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9227 23:19:43.778611 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9228 23:19:43.781657 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9229 23:19:43.789045 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9230 23:19:43.792380 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9231 23:19:43.795266 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9232 23:19:43.802205 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9233 23:19:43.805103 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9234 23:19:43.812567 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9235 23:19:43.816312 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9236 23:19:43.819154 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9237 23:19:43.829956 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9238 23:19:43.830850 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9239 23:19:43.832210 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9240 23:19:43.838722 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9241 23:19:43.842597 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9242 23:19:43.849207 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9243 23:19:43.851860 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9244 23:19:43.858120 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9245 23:19:43.862884 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9246 23:19:43.866627 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9247 23:19:43.871064 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9248 23:19:43.875159 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9249 23:19:43.878542 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9250 23:19:43.885671 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9251 23:19:43.888905 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9252 23:19:43.892157 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9253 23:19:43.898667 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9254 23:19:43.902059 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9255 23:19:43.908435 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9256 23:19:43.912014 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9257 23:19:43.915371 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9258 23:19:43.921638 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9259 23:19:43.927148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9260 23:19:43.928531 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9261 23:19:43.932042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9262 23:19:43.938883 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9263 23:19:43.941549 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9264 23:19:43.945087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9265 23:19:43.948597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9266 23:19:43.954906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9267 23:19:43.958189 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9268 23:19:43.962106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9269 23:19:43.965137 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9270 23:19:43.971981 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9271 23:19:43.975620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9272 23:19:43.978736 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9273 23:19:43.981789 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9274 23:19:43.988437 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9275 23:19:43.992541 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9276 23:19:43.998155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9277 23:19:44.001925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9278 23:19:44.008297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9279 23:19:44.011503 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9280 23:19:44.014596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9281 23:19:44.022120 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9282 23:19:44.025313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9283 23:19:44.031178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9284 23:19:44.035600 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9285 23:19:44.041768 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9286 23:19:44.044509 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9287 23:19:44.051861 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9288 23:19:44.054867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9289 23:19:44.058776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9290 23:19:44.066680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9291 23:19:44.070029 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9292 23:19:44.075467 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9293 23:19:44.078558 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9294 23:19:44.084850 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9295 23:19:44.090181 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9296 23:19:44.091751 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9297 23:19:44.098178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9298 23:19:44.101543 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9299 23:19:44.108324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9300 23:19:44.112693 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9301 23:19:44.118696 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9302 23:19:44.121848 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9303 23:19:44.124691 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9304 23:19:44.131654 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9305 23:19:44.134606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9306 23:19:44.141243 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9307 23:19:44.144659 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9308 23:19:44.152143 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9309 23:19:44.155683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9310 23:19:44.157972 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9311 23:19:44.164832 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9312 23:19:44.167975 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9313 23:19:44.174669 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9314 23:19:44.177904 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9315 23:19:44.184439 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9316 23:19:44.188579 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9317 23:19:44.194621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9318 23:19:44.197898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9319 23:19:44.201366 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9320 23:19:44.208064 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9321 23:19:44.211504 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9322 23:19:44.217702 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9323 23:19:44.221306 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9324 23:19:44.224988 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9325 23:19:44.228068 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9326 23:19:44.234802 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9327 23:19:44.237550 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9328 23:19:44.240907 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9329 23:19:44.247645 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9330 23:19:44.251186 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9331 23:19:44.257568 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9332 23:19:44.262788 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9333 23:19:44.264784 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9334 23:19:44.270833 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9335 23:19:44.274140 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9336 23:19:44.281163 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9337 23:19:44.284031 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9338 23:19:44.287995 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9339 23:19:44.294780 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9340 23:19:44.297950 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9341 23:19:44.304341 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9342 23:19:44.307884 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9343 23:19:44.311725 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9344 23:19:44.318189 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9345 23:19:44.321038 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9346 23:19:44.325235 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9347 23:19:44.327482 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9348 23:19:44.330789 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9349 23:19:44.337662 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9350 23:19:44.341385 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9351 23:19:44.347859 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9352 23:19:44.350638 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9353 23:19:44.353888 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9354 23:19:44.360842 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9355 23:19:44.364443 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9356 23:19:44.367417 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9357 23:19:44.374389 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9358 23:19:44.379490 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9359 23:19:44.383731 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9360 23:19:44.387202 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9361 23:19:44.391640 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9362 23:19:44.397295 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9363 23:19:44.400600 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9364 23:19:44.408563 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9365 23:19:44.410311 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9366 23:19:44.414645 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9367 23:19:44.420878 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9368 23:19:44.423925 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9369 23:19:44.430886 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9370 23:19:44.434029 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9371 23:19:44.438154 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9372 23:19:44.443895 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9373 23:19:44.447837 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9374 23:19:44.450518 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9375 23:19:44.457831 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9376 23:19:44.460851 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9377 23:19:44.467635 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9378 23:19:44.470176 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9379 23:19:44.473568 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9380 23:19:44.481199 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9381 23:19:44.484494 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9382 23:19:44.492520 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9383 23:19:44.493643 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9384 23:19:44.497283 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9385 23:19:44.503909 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9386 23:19:44.507302 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9387 23:19:44.514124 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9388 23:19:44.517471 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9389 23:19:44.520911 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9390 23:19:44.527036 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9391 23:19:44.530916 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9392 23:19:44.533314 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9393 23:19:44.540427 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9394 23:19:44.544025 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9395 23:19:44.550208 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9396 23:19:44.554056 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9397 23:19:44.561172 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9398 23:19:44.563514 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9399 23:19:44.567421 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9400 23:19:44.572908 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9401 23:19:44.576567 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9402 23:19:44.579985 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9403 23:19:44.587697 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9404 23:19:44.589462 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9405 23:19:44.597121 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9406 23:19:44.599973 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9407 23:19:44.603794 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9408 23:19:44.609734 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9409 23:19:44.613360 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9410 23:19:44.619627 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9411 23:19:44.623493 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9412 23:19:44.626166 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9413 23:19:44.632545 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9414 23:19:44.636265 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9415 23:19:44.642781 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9416 23:19:44.645972 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9417 23:19:44.652906 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9418 23:19:44.656674 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9419 23:19:44.660441 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9420 23:19:44.665644 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9421 23:19:44.669530 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9422 23:19:44.675890 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9423 23:19:44.679216 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9424 23:19:44.682383 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9425 23:19:44.689750 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9426 23:19:44.692355 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9427 23:19:44.699300 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9428 23:19:44.702389 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9429 23:19:44.708545 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9430 23:19:44.712284 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9431 23:19:44.716081 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9432 23:19:44.721562 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9433 23:19:44.725787 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9434 23:19:44.731951 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9435 23:19:44.735585 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9436 23:19:44.742677 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9437 23:19:44.745034 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9438 23:19:44.748254 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9439 23:19:44.755470 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9440 23:19:44.758928 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9441 23:19:44.765022 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9442 23:19:44.768587 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9443 23:19:44.771681 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9444 23:19:44.779415 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9445 23:19:44.781261 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9446 23:19:44.788554 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9447 23:19:44.791795 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9448 23:19:44.798010 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9449 23:19:44.801403 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9450 23:19:44.804809 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9451 23:19:44.811778 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9452 23:19:44.814756 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9453 23:19:44.821752 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9454 23:19:44.826103 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9455 23:19:44.827728 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9456 23:19:44.834659 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9457 23:19:44.837712 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9458 23:19:44.841778 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9459 23:19:44.844129 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9460 23:19:44.851353 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9461 23:19:44.854633 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9462 23:19:44.857922 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9463 23:19:44.864405 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9464 23:19:44.867769 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9465 23:19:44.871236 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9466 23:19:44.878898 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9467 23:19:44.880415 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9468 23:19:44.887670 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9469 23:19:44.891332 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9470 23:19:44.894118 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9471 23:19:44.901575 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9472 23:19:44.904088 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9473 23:19:44.911155 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9474 23:19:44.913658 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9475 23:19:44.918459 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9476 23:19:44.924151 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9477 23:19:44.927530 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9478 23:19:44.931274 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9479 23:19:44.937262 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9480 23:19:44.941145 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9481 23:19:44.943160 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9482 23:19:44.950333 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9483 23:19:44.953182 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9484 23:19:44.956928 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9485 23:19:44.963591 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9486 23:19:44.966647 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9487 23:19:44.973735 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9488 23:19:44.976571 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9489 23:19:44.979945 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9490 23:19:44.987232 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9491 23:19:44.990262 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9492 23:19:44.996447 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9493 23:19:45.000428 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9494 23:19:45.002462 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9495 23:19:45.009130 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9496 23:19:45.012690 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9497 23:19:45.016486 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9498 23:19:45.019646 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9499 23:19:45.022514 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9500 23:19:45.030078 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9501 23:19:45.033098 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9502 23:19:45.036358 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9503 23:19:45.039223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9504 23:19:45.048839 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9505 23:19:45.049731 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9506 23:19:45.052686 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9507 23:19:45.059172 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9508 23:19:45.062465 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9509 23:19:45.065409 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9510 23:19:45.072209 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9511 23:19:45.075701 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9512 23:19:45.082524 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9513 23:19:45.085543 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9514 23:19:45.093468 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9515 23:19:45.095632 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9516 23:19:45.099453 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9517 23:19:45.105645 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9518 23:19:45.108575 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9519 23:19:45.116271 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9520 23:19:45.118891 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9521 23:19:45.121960 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9522 23:19:45.129950 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9523 23:19:45.131837 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9524 23:19:45.138842 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9525 23:19:45.143091 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9526 23:19:45.145083 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9527 23:19:45.151699 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9528 23:19:45.157442 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9529 23:19:45.162203 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9530 23:19:45.164644 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9531 23:19:45.172188 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9532 23:19:45.174870 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9533 23:19:45.178006 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9534 23:19:45.184800 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9535 23:19:45.187845 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9536 23:19:45.194514 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9537 23:19:45.198230 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9538 23:19:45.204947 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9539 23:19:45.208516 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9540 23:19:45.211543 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9541 23:19:45.218007 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9542 23:19:45.220995 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9543 23:19:45.228611 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9544 23:19:45.231034 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9545 23:19:45.234402 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9546 23:19:45.241341 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9547 23:19:45.243930 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9548 23:19:45.251164 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9549 23:19:45.255398 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9550 23:19:45.257449 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9551 23:19:45.264599 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9552 23:19:45.267787 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9553 23:19:45.274246 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9554 23:19:45.277388 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9555 23:19:45.280440 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9556 23:19:45.287506 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9557 23:19:45.290414 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9558 23:19:45.297324 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9559 23:19:45.300290 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9560 23:19:45.307591 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9561 23:19:45.310471 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9562 23:19:45.313388 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9563 23:19:45.320414 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9564 23:19:45.324621 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9565 23:19:45.330310 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9566 23:19:45.334257 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9567 23:19:45.336670 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9568 23:19:45.343961 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9569 23:19:45.346572 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9570 23:19:45.353200 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9571 23:19:45.357566 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9572 23:19:45.360339 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9573 23:19:45.366526 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9574 23:19:45.370379 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9575 23:19:45.376896 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9576 23:19:45.380009 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9577 23:19:45.386371 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9578 23:19:45.390044 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9579 23:19:45.392944 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9580 23:19:45.399301 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9581 23:19:45.403371 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9582 23:19:45.409671 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9583 23:19:45.412832 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9584 23:19:45.419502 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9585 23:19:45.423128 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9586 23:19:45.429305 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9587 23:19:45.432482 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9588 23:19:45.435728 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9589 23:19:45.443504 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9590 23:19:45.446011 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9591 23:19:45.452331 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9592 23:19:45.456200 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9593 23:19:45.462349 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9594 23:19:45.466877 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9595 23:19:45.470370 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9596 23:19:45.476503 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9597 23:19:45.478854 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9598 23:19:45.485841 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9599 23:19:45.489184 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9600 23:19:45.495792 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9601 23:19:45.498815 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9602 23:19:45.505466 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9603 23:19:45.508767 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9604 23:19:45.512310 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9605 23:19:45.518698 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9606 23:19:45.521725 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9607 23:19:45.528507 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9608 23:19:45.531966 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9609 23:19:45.539002 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9610 23:19:45.542120 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9611 23:19:45.545090 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9612 23:19:45.552074 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9613 23:19:45.555477 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9614 23:19:45.561340 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9615 23:19:45.564678 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9616 23:19:45.572050 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9617 23:19:45.576256 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9618 23:19:45.581471 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9619 23:19:45.585223 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9620 23:19:45.589815 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9621 23:19:45.594947 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9622 23:19:45.598531 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9623 23:19:45.604654 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9624 23:19:45.607915 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9625 23:19:45.615115 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9626 23:19:45.618738 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9627 23:19:45.621605 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9628 23:19:45.627792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9629 23:19:45.631008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9630 23:19:45.637878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9631 23:19:45.641344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9632 23:19:45.647807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9633 23:19:45.651067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9634 23:19:45.657512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9635 23:19:45.661389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9636 23:19:45.667874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9637 23:19:45.671462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9638 23:19:45.677706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9639 23:19:45.681596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9640 23:19:45.687801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9641 23:19:45.691376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9642 23:19:45.695235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9643 23:19:45.701353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9644 23:19:45.703927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9645 23:19:45.710680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9646 23:19:45.714373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9647 23:19:45.720619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9648 23:19:45.724201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9649 23:19:45.730539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9650 23:19:45.733864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9651 23:19:45.740772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9652 23:19:45.743641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9653 23:19:45.750353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9654 23:19:45.753908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9655 23:19:45.760323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9656 23:19:45.763855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9657 23:19:45.770456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9658 23:19:45.773737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9659 23:19:45.780280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9660 23:19:45.783658 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9661 23:19:45.786895 INFO: [APUAPC] vio 0
9662 23:19:45.792490 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9663 23:19:45.799563 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9664 23:19:45.800510 INFO: [APUAPC] D0_APC_0: 0x400510
9665 23:19:45.803829 INFO: [APUAPC] D0_APC_1: 0x0
9666 23:19:45.807284 INFO: [APUAPC] D0_APC_2: 0x1540
9667 23:19:45.807845 INFO: [APUAPC] D0_APC_3: 0x0
9668 23:19:45.812947 INFO: [APUAPC] D1_APC_0: 0xffffffff
9669 23:19:45.816625 INFO: [APUAPC] D1_APC_1: 0xffffffff
9670 23:19:45.819611 INFO: [APUAPC] D1_APC_2: 0x3fffff
9671 23:19:45.820252 INFO: [APUAPC] D1_APC_3: 0x0
9672 23:19:45.823157 INFO: [APUAPC] D2_APC_0: 0xffffffff
9673 23:19:45.826488 INFO: [APUAPC] D2_APC_1: 0xffffffff
9674 23:19:45.829903 INFO: [APUAPC] D2_APC_2: 0x3fffff
9675 23:19:45.833365 INFO: [APUAPC] D2_APC_3: 0x0
9676 23:19:45.836805 INFO: [APUAPC] D3_APC_0: 0xffffffff
9677 23:19:45.840023 INFO: [APUAPC] D3_APC_1: 0xffffffff
9678 23:19:45.843230 INFO: [APUAPC] D3_APC_2: 0x3fffff
9679 23:19:45.846665 INFO: [APUAPC] D3_APC_3: 0x0
9680 23:19:45.849403 INFO: [APUAPC] D4_APC_0: 0xffffffff
9681 23:19:45.853001 INFO: [APUAPC] D4_APC_1: 0xffffffff
9682 23:19:45.856508 INFO: [APUAPC] D4_APC_2: 0x3fffff
9683 23:19:45.859779 INFO: [APUAPC] D4_APC_3: 0x0
9684 23:19:45.862792 INFO: [APUAPC] D5_APC_0: 0xffffffff
9685 23:19:45.865989 INFO: [APUAPC] D5_APC_1: 0xffffffff
9686 23:19:45.869393 INFO: [APUAPC] D5_APC_2: 0x3fffff
9687 23:19:45.872805 INFO: [APUAPC] D5_APC_3: 0x0
9688 23:19:45.875988 INFO: [APUAPC] D6_APC_0: 0xffffffff
9689 23:19:45.879363 INFO: [APUAPC] D6_APC_1: 0xffffffff
9690 23:19:45.882729 INFO: [APUAPC] D6_APC_2: 0x3fffff
9691 23:19:45.886001 INFO: [APUAPC] D6_APC_3: 0x0
9692 23:19:45.889352 INFO: [APUAPC] D7_APC_0: 0xffffffff
9693 23:19:45.892936 INFO: [APUAPC] D7_APC_1: 0xffffffff
9694 23:19:45.895998 INFO: [APUAPC] D7_APC_2: 0x3fffff
9695 23:19:45.899820 INFO: [APUAPC] D7_APC_3: 0x0
9696 23:19:45.903433 INFO: [APUAPC] D8_APC_0: 0xffffffff
9697 23:19:45.905593 INFO: [APUAPC] D8_APC_1: 0xffffffff
9698 23:19:45.909987 INFO: [APUAPC] D8_APC_2: 0x3fffff
9699 23:19:45.913615 INFO: [APUAPC] D8_APC_3: 0x0
9700 23:19:45.917102 INFO: [APUAPC] D9_APC_0: 0xffffffff
9701 23:19:45.919814 INFO: [APUAPC] D9_APC_1: 0xffffffff
9702 23:19:45.923331 INFO: [APUAPC] D9_APC_2: 0x3fffff
9703 23:19:45.926034 INFO: [APUAPC] D9_APC_3: 0x0
9704 23:19:45.928871 INFO: [APUAPC] D10_APC_0: 0xffffffff
9705 23:19:45.932852 INFO: [APUAPC] D10_APC_1: 0xffffffff
9706 23:19:45.936071 INFO: [APUAPC] D10_APC_2: 0x3fffff
9707 23:19:45.939110 INFO: [APUAPC] D10_APC_3: 0x0
9708 23:19:45.942791 INFO: [APUAPC] D11_APC_0: 0xffffffff
9709 23:19:45.945634 INFO: [APUAPC] D11_APC_1: 0xffffffff
9710 23:19:45.949242 INFO: [APUAPC] D11_APC_2: 0x3fffff
9711 23:19:45.953060 INFO: [APUAPC] D11_APC_3: 0x0
9712 23:19:45.956614 INFO: [APUAPC] D12_APC_0: 0xffffffff
9713 23:19:45.959398 INFO: [APUAPC] D12_APC_1: 0xffffffff
9714 23:19:45.962195 INFO: [APUAPC] D12_APC_2: 0x3fffff
9715 23:19:45.965539 INFO: [APUAPC] D12_APC_3: 0x0
9716 23:19:45.968833 INFO: [APUAPC] D13_APC_0: 0xffffffff
9717 23:19:45.973015 INFO: [APUAPC] D13_APC_1: 0xffffffff
9718 23:19:45.976232 INFO: [APUAPC] D13_APC_2: 0x3fffff
9719 23:19:45.978925 INFO: [APUAPC] D13_APC_3: 0x0
9720 23:19:45.982364 INFO: [APUAPC] D14_APC_0: 0xffffffff
9721 23:19:45.985762 INFO: [APUAPC] D14_APC_1: 0xffffffff
9722 23:19:45.989307 INFO: [APUAPC] D14_APC_2: 0x3fffff
9723 23:19:45.991907 INFO: [APUAPC] D14_APC_3: 0x0
9724 23:19:45.996147 INFO: [APUAPC] D15_APC_0: 0xffffffff
9725 23:19:45.999132 INFO: [APUAPC] D15_APC_1: 0xffffffff
9726 23:19:46.001915 INFO: [APUAPC] D15_APC_2: 0x3fffff
9727 23:19:46.006591 INFO: [APUAPC] D15_APC_3: 0x0
9728 23:19:46.011055 INFO: [APUAPC] APC_CON: 0x4
9729 23:19:46.012196 INFO: [NOCDAPC] D0_APC_0: 0x0
9730 23:19:46.016022 INFO: [NOCDAPC] D0_APC_1: 0x0
9731 23:19:46.018400 INFO: [NOCDAPC] D1_APC_0: 0x0
9732 23:19:46.018862 INFO: [NOCDAPC] D1_APC_1: 0xfff
9733 23:19:46.022062 INFO: [NOCDAPC] D2_APC_0: 0x0
9734 23:19:46.025125 INFO: [NOCDAPC] D2_APC_1: 0xfff
9735 23:19:46.028488 INFO: [NOCDAPC] D3_APC_0: 0x0
9736 23:19:46.031967 INFO: [NOCDAPC] D3_APC_1: 0xfff
9737 23:19:46.035874 INFO: [NOCDAPC] D4_APC_0: 0x0
9738 23:19:46.038556 INFO: [NOCDAPC] D4_APC_1: 0xfff
9739 23:19:46.041675 INFO: [NOCDAPC] D5_APC_0: 0x0
9740 23:19:46.045691 INFO: [NOCDAPC] D5_APC_1: 0xfff
9741 23:19:46.048305 INFO: [NOCDAPC] D6_APC_0: 0x0
9742 23:19:46.051559 INFO: [NOCDAPC] D6_APC_1: 0xfff
9743 23:19:46.052020 INFO: [NOCDAPC] D7_APC_0: 0x0
9744 23:19:46.054526 INFO: [NOCDAPC] D7_APC_1: 0xfff
9745 23:19:46.058430 INFO: [NOCDAPC] D8_APC_0: 0x0
9746 23:19:46.061655 INFO: [NOCDAPC] D8_APC_1: 0xfff
9747 23:19:46.064572 INFO: [NOCDAPC] D9_APC_0: 0x0
9748 23:19:46.068193 INFO: [NOCDAPC] D9_APC_1: 0xfff
9749 23:19:46.071792 INFO: [NOCDAPC] D10_APC_0: 0x0
9750 23:19:46.074904 INFO: [NOCDAPC] D10_APC_1: 0xfff
9751 23:19:46.077613 INFO: [NOCDAPC] D11_APC_0: 0x0
9752 23:19:46.081174 INFO: [NOCDAPC] D11_APC_1: 0xfff
9753 23:19:46.084191 INFO: [NOCDAPC] D12_APC_0: 0x0
9754 23:19:46.087994 INFO: [NOCDAPC] D12_APC_1: 0xfff
9755 23:19:46.091190 INFO: [NOCDAPC] D13_APC_0: 0x0
9756 23:19:46.094116 INFO: [NOCDAPC] D13_APC_1: 0xfff
9757 23:19:46.094368 INFO: [NOCDAPC] D14_APC_0: 0x0
9758 23:19:46.097600 INFO: [NOCDAPC] D14_APC_1: 0xfff
9759 23:19:46.100490 INFO: [NOCDAPC] D15_APC_0: 0x0
9760 23:19:46.104570 INFO: [NOCDAPC] D15_APC_1: 0xfff
9761 23:19:46.107477 INFO: [NOCDAPC] APC_CON: 0x4
9762 23:19:46.111536 INFO: [APUAPC] set_apusys_apc done
9763 23:19:46.113794 INFO: [DEVAPC] devapc_init done
9764 23:19:46.117300 INFO: GICv3 without legacy support detected.
9765 23:19:46.124694 INFO: ARM GICv3 driver initialized in EL3
9766 23:19:46.127056 INFO: Maximum SPI INTID supported: 639
9767 23:19:46.130655 INFO: BL31: Initializing runtime services
9768 23:19:46.137218 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9769 23:19:46.141208 INFO: SPM: enable CPC mode
9770 23:19:46.144062 INFO: mcdi ready for mcusys-off-idle and system suspend
9771 23:19:46.149932 INFO: BL31: Preparing for EL3 exit to normal world
9772 23:19:46.154005 INFO: Entry point address = 0x80000000
9773 23:19:46.154250 INFO: SPSR = 0x8
9774 23:19:46.160456
9775 23:19:46.160917
9776 23:19:46.161239
9777 23:19:46.163953 Starting depthcharge on Spherion...
9778 23:19:46.164427
9779 23:19:46.164767 Wipe memory regions:
9780 23:19:46.165057
9781 23:19:46.167675 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9782 23:19:46.168219 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9783 23:19:46.168665 Setting prompt string to ['asurada:']
9784 23:19:46.169158 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9785 23:19:46.169869 [0x00000040000000, 0x00000054600000)
9786 23:19:46.289612
9787 23:19:46.290169 [0x00000054660000, 0x00000080000000)
9788 23:19:46.551613
9789 23:19:46.552163 [0x000000821a7280, 0x000000ffe64000)
9790 23:19:47.295154
9791 23:19:47.295800 [0x00000100000000, 0x00000140000000)
9792 23:19:47.676189
9793 23:19:47.679221 Initializing XHCI USB controller at 0x11200000.
9794 23:19:48.717647
9795 23:19:48.719800 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9796 23:19:48.720352
9797 23:19:48.720770
9798 23:19:48.721130
9799 23:19:48.721947 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9801 23:19:48.823318 asurada: tftpboot 192.168.201.1 13248407/tftp-deploy-a33avefh/kernel/image.itb 13248407/tftp-deploy-a33avefh/kernel/cmdline
9802 23:19:48.823985 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9803 23:19:48.824465 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9804 23:19:48.829779 tftpboot 192.168.201.1 13248407/tftp-deploy-a33avefh/kernel/image.itp-deploy-a33avefh/kernel/cmdline
9805 23:19:48.830252
9806 23:19:48.830650 Waiting for link
9807 23:19:48.989639
9808 23:19:48.990195 R8152: Initializing
9809 23:19:48.990565
9810 23:19:48.993472 Version 9 (ocp_data = 6010)
9811 23:19:48.994087
9812 23:19:48.996010 R8152: Done initializing
9813 23:19:48.996565
9814 23:19:48.996979 Adding net device
9815 23:19:50.934699
9816 23:19:50.935251 done.
9817 23:19:50.935642
9818 23:19:50.935988 MAC: 00:e0:4c:68:03:bd
9819 23:19:50.936317
9820 23:19:50.938324 Sending DHCP discover... done.
9821 23:19:50.938782
9822 23:19:50.941049 Waiting for reply... done.
9823 23:19:50.941506
9824 23:19:50.945033 Sending DHCP request... done.
9825 23:19:50.945620
9826 23:19:50.948361 Waiting for reply... done.
9827 23:19:50.948852
9828 23:19:50.949221 My ip is 192.168.201.16
9829 23:19:50.949561
9830 23:19:50.951565 The DHCP server ip is 192.168.201.1
9831 23:19:50.952023
9832 23:19:50.958035 TFTP server IP predefined by user: 192.168.201.1
9833 23:19:50.958609
9834 23:19:50.964876 Bootfile predefined by user: 13248407/tftp-deploy-a33avefh/kernel/image.itb
9835 23:19:50.965433
9836 23:19:50.967590 Sending tftp read request... done.
9837 23:19:50.968050
9838 23:19:50.972700 Waiting for the transfer...
9839 23:19:50.973301
9840 23:19:51.380172 00000000 ################################################################
9841 23:19:51.380755
9842 23:19:51.757491 00080000 ################################################################
9843 23:19:51.758010
9844 23:19:52.071924 00100000 ################################################################
9845 23:19:52.072103
9846 23:19:52.423744 00180000 ################################################################
9847 23:19:52.423894
9848 23:19:52.724896 00200000 ################################################################
9849 23:19:52.725038
9850 23:19:53.027414 00280000 ################################################################
9851 23:19:53.027576
9852 23:19:53.329774 00300000 ################################################################
9853 23:19:53.329920
9854 23:19:53.631654 00380000 ################################################################
9855 23:19:53.631793
9856 23:19:53.932288 00400000 ################################################################
9857 23:19:53.932430
9858 23:19:54.231071 00480000 ################################################################
9859 23:19:54.231207
9860 23:19:54.527411 00500000 ################################################################
9861 23:19:54.527613
9862 23:19:54.908565 00580000 ################################################################
9863 23:19:54.909122
9864 23:19:55.301962 00600000 ################################################################
9865 23:19:55.302489
9866 23:19:55.698850 00680000 ################################################################
9867 23:19:55.699455
9868 23:19:56.113186 00700000 ################################################################
9869 23:19:56.113693
9870 23:19:56.512993 00780000 ################################################################
9871 23:19:56.513138
9872 23:19:56.781686 00800000 ################################################################
9873 23:19:56.781827
9874 23:19:57.075063 00880000 ################################################################
9875 23:19:57.075227
9876 23:19:57.379898 00900000 ################################################################
9877 23:19:57.380064
9878 23:19:57.679970 00980000 ################################################################
9879 23:19:57.680145
9880 23:19:58.014904 00a00000 ################################################################
9881 23:19:58.015429
9882 23:19:58.437207 00a80000 ################################################################
9883 23:19:58.437834
9884 23:19:58.856044 00b00000 ################################################################
9885 23:19:58.856768
9886 23:19:59.238236 00b80000 ################################################################
9887 23:19:59.238828
9888 23:19:59.619145 00c00000 ################################################################
9889 23:19:59.619797
9890 23:19:59.997550 00c80000 ################################################################
9891 23:19:59.998065
9892 23:20:00.366298 00d00000 ################################################################
9893 23:20:00.366820
9894 23:20:00.744467 00d80000 ################################################################
9895 23:20:00.745071
9896 23:20:01.101648 00e00000 ################################################################
9897 23:20:01.101792
9898 23:20:01.394051 00e80000 ################################################################
9899 23:20:01.394192
9900 23:20:01.691329 00f00000 ################################################################
9901 23:20:01.691471
9902 23:20:01.993180 00f80000 ################################################################
9903 23:20:01.993324
9904 23:20:02.292167 01000000 ################################################################
9905 23:20:02.292310
9906 23:20:02.587835 01080000 ################################################################
9907 23:20:02.587977
9908 23:20:02.890060 01100000 ################################################################
9909 23:20:02.890197
9910 23:20:03.192255 01180000 ################################################################
9911 23:20:03.192388
9912 23:20:03.488307 01200000 ################################################################
9913 23:20:03.488449
9914 23:20:03.786012 01280000 ################################################################
9915 23:20:03.786153
9916 23:20:04.076669 01300000 ################################################################
9917 23:20:04.076816
9918 23:20:04.378958 01380000 ################################################################
9919 23:20:04.379103
9920 23:20:04.639142 01400000 ################################################################
9921 23:20:04.639289
9922 23:20:04.889160 01480000 ################################################################
9923 23:20:04.889299
9924 23:20:05.139587 01500000 ################################################################
9925 23:20:05.139754
9926 23:20:05.393058 01580000 ################################################################
9927 23:20:05.393191
9928 23:20:05.664019 01600000 ################################################################
9929 23:20:05.664191
9930 23:20:05.923970 01680000 ################################################################
9931 23:20:05.924105
9932 23:20:06.216074 01700000 ################################################################
9933 23:20:06.216216
9934 23:20:06.483020 01780000 ################################################################
9935 23:20:06.483188
9936 23:20:06.757895 01800000 ################################################################
9937 23:20:06.758040
9938 23:20:07.151867 01880000 ################################################################
9939 23:20:07.152392
9940 23:20:07.470388 01900000 ################################################################
9941 23:20:07.470523
9942 23:20:07.785669 01980000 ################################################################
9943 23:20:07.785832
9944 23:20:08.117431 01a00000 ################################################################
9945 23:20:08.117573
9946 23:20:08.472636 01a80000 ################################################################
9947 23:20:08.473421
9948 23:20:08.875948 01b00000 ################################################################
9949 23:20:08.876495
9950 23:20:09.283788 01b80000 ################################################################
9951 23:20:09.284324
9952 23:20:09.683282 01c00000 ################################################################
9953 23:20:09.683797
9954 23:20:10.063300 01c80000 ################################################################
9955 23:20:10.063818
9956 23:20:10.447625 01d00000 ################################################################
9957 23:20:10.448348
9958 23:20:10.845248 01d80000 ################################################################
9959 23:20:10.845781
9960 23:20:11.050584 01e00000 ################################## done.
9961 23:20:11.051069
9962 23:20:11.054185 The bootfile was 31728186 bytes long.
9963 23:20:11.054608
9964 23:20:11.057351 Sending tftp read request... done.
9965 23:20:11.057812
9966 23:20:11.060306 Waiting for the transfer...
9967 23:20:11.060748
9968 23:20:11.061090 00000000 # done.
9969 23:20:11.061406
9970 23:20:11.071166 Command line loaded dynamically from TFTP file: 13248407/tftp-deploy-a33avefh/kernel/cmdline
9971 23:20:11.071691
9972 23:20:11.090623 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248407/extract-nfsrootfs-dbda60ix,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9973 23:20:11.091157
9974 23:20:11.094254 Loading FIT.
9975 23:20:11.094667
9976 23:20:11.097066 Image ramdisk-1 has 18771651 bytes.
9977 23:20:11.097482
9978 23:20:11.097810 Image fdt-1 has 47230 bytes.
9979 23:20:11.098120
9980 23:20:11.100845 Image kernel-1 has 12907270 bytes.
9981 23:20:11.101361
9982 23:20:11.110751 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9983 23:20:11.111264
9984 23:20:11.126892 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9985 23:20:11.127532
9986 23:20:11.133458 Choosing best match conf-1 for compat google,spherion-rev3.
9987 23:20:11.138215
9988 23:20:11.142597 Connected to device vid:did:rid of 1ae0:0028:00
9989 23:20:11.150282
9990 23:20:11.154011 tpm_get_response: command 0x17b, return code 0x0
9991 23:20:11.154433
9992 23:20:11.156563 ec_init: CrosEC protocol v3 supported (256, 248)
9993 23:20:11.161102
9994 23:20:11.164658 tpm_cleanup: add release locality here.
9995 23:20:11.165213
9996 23:20:11.165548 Shutting down all USB controllers.
9997 23:20:11.167576
9998 23:20:11.167995 Removing current net device
9999 23:20:11.168325
10000 23:20:11.174222 Exiting depthcharge with code 4 at timestamp: 53162143
10001 23:20:11.174727
10002 23:20:11.177385 LZMA decompressing kernel-1 to 0x821a6718
10003 23:20:11.177800
10004 23:20:11.181853 LZMA decompressing kernel-1 to 0x40000000
10005 23:20:12.773530
10006 23:20:12.774083 jumping to kernel
10007 23:20:12.775825 end: 2.2.4 bootloader-commands (duration 00:00:27) [common]
10008 23:20:12.776418 start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
10009 23:20:12.776858 Setting prompt string to ['Linux version [0-9]']
10010 23:20:12.777270 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10011 23:20:12.777710 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10012 23:20:12.823936
10013 23:20:12.827680 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10014 23:20:12.831888 start: 2.2.5.1 login-action (timeout 00:04:00) [common]
10015 23:20:12.832477 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10016 23:20:12.832913 Setting prompt string to []
10017 23:20:12.833331 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10018 23:20:12.833718 Using line separator: #'\n'#
10019 23:20:12.834042 No login prompt set.
10020 23:20:12.834383 Parsing kernel messages
10021 23:20:12.834685 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10022 23:20:12.835283 [login-action] Waiting for messages, (timeout 00:04:00)
10023 23:20:12.835664 Waiting using forced prompt support (timeout 00:02:00)
10024 23:20:12.850151 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10025 23:20:12.854223 [ 0.000000] random: crng init done
10026 23:20:12.860426 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10027 23:20:12.863597 [ 0.000000] efi: UEFI not found.
10028 23:20:12.871076 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10029 23:20:12.876853 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10030 23:20:12.887143 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10031 23:20:12.897376 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10032 23:20:12.903401 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10033 23:20:12.910090 [ 0.000000] printk: bootconsole [mtk8250] enabled
10034 23:20:12.917284 [ 0.000000] NUMA: No NUMA configuration found
10035 23:20:12.924512 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10036 23:20:12.926470 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10037 23:20:12.930450 [ 0.000000] Zone ranges:
10038 23:20:12.936696 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10039 23:20:12.939864 [ 0.000000] DMA32 empty
10040 23:20:12.946947 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10041 23:20:12.949425 [ 0.000000] Movable zone start for each node
10042 23:20:12.952519 [ 0.000000] Early memory node ranges
10043 23:20:12.959338 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10044 23:20:12.965788 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10045 23:20:12.973305 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10046 23:20:12.980891 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10047 23:20:12.986179 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10048 23:20:12.992462 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10049 23:20:13.022204 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10050 23:20:13.031313 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10051 23:20:13.035311 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10052 23:20:13.038894 [ 0.000000] psci: probing for conduit method from DT.
10053 23:20:13.046408 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10054 23:20:13.048504 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10055 23:20:13.055893 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10056 23:20:13.058454 [ 0.000000] psci: SMC Calling Convention v1.2
10057 23:20:13.065066 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10058 23:20:13.068768 [ 0.000000] Detected VIPT I-cache on CPU0
10059 23:20:13.076098 [ 0.000000] CPU features: detected: GIC system register CPU interface
10060 23:20:13.082742 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10061 23:20:13.088446 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10062 23:20:13.094858 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10063 23:20:13.101842 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10064 23:20:13.112035 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10065 23:20:13.115509 [ 0.000000] alternatives: applying boot alternatives
10066 23:20:13.121848 [ 0.000000] Fallback order for Node 0: 0
10067 23:20:13.128472 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10068 23:20:13.131781 [ 0.000000] Policy zone: Normal
10069 23:20:13.154682 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248407/extract-nfsrootfs-dbda60ix,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10070 23:20:13.165064 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10071 23:20:13.175126 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10072 23:20:13.181155 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10073 23:20:13.187779 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10074 23:20:13.194022 <6>[ 0.000000] software IO TLB: area num 8.
10075 23:20:13.249185 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10076 23:20:13.329808 <6>[ 0.000000] Memory: 3831828K/4191232K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 326636K reserved, 32768K cma-reserved)
10077 23:20:13.336476 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10078 23:20:13.343541 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10079 23:20:13.346233 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10080 23:20:13.352768 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10081 23:20:13.359734 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10082 23:20:13.363387 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10083 23:20:13.372643 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10084 23:20:13.379060 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10085 23:20:13.387063 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10086 23:20:13.392528 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10087 23:20:13.395957 <6>[ 0.000000] GICv3: 608 SPIs implemented
10088 23:20:13.399719 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10089 23:20:13.406475 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10090 23:20:13.409457 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10091 23:20:13.416142 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10092 23:20:13.429627 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10093 23:20:13.441767 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10094 23:20:13.448807 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10095 23:20:13.457096 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10096 23:20:13.470169 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10097 23:20:13.476000 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10098 23:20:13.485728 <6>[ 0.009177] Console: colour dummy device 80x25
10099 23:20:13.492266 <6>[ 0.013903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10100 23:20:13.499363 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10101 23:20:13.502359 <6>[ 0.029217] LSM: Security Framework initializing
10102 23:20:13.508657 <6>[ 0.034160] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10103 23:20:13.518782 <6>[ 0.041766] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10104 23:20:13.525223 <6>[ 0.051054] cblist_init_generic: Setting adjustable number of callback queues.
10105 23:20:13.532438 <6>[ 0.058498] cblist_init_generic: Setting shift to 3 and lim to 1.
10106 23:20:13.541812 <6>[ 0.064837] cblist_init_generic: Setting adjustable number of callback queues.
10107 23:20:13.546424 <6>[ 0.072310] cblist_init_generic: Setting shift to 3 and lim to 1.
10108 23:20:13.552207 <6>[ 0.078711] rcu: Hierarchical SRCU implementation.
10109 23:20:13.558837 <6>[ 0.083725] rcu: Max phase no-delay instances is 1000.
10110 23:20:13.565312 <6>[ 0.090776] EFI services will not be available.
10111 23:20:13.568364 <6>[ 0.095763] smp: Bringing up secondary CPUs ...
10112 23:20:13.576489 <6>[ 0.100815] Detected VIPT I-cache on CPU1
10113 23:20:13.583469 <6>[ 0.100886] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10114 23:20:13.590629 <6>[ 0.100917] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10115 23:20:13.593227 <6>[ 0.101245] Detected VIPT I-cache on CPU2
10116 23:20:13.599387 <6>[ 0.101294] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10117 23:20:13.609604 <6>[ 0.101311] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10118 23:20:13.612557 <6>[ 0.101556] Detected VIPT I-cache on CPU3
10119 23:20:13.619583 <6>[ 0.101598] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10120 23:20:13.626433 <6>[ 0.101612] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10121 23:20:13.629687 <6>[ 0.101901] CPU features: detected: Spectre-v4
10122 23:20:13.636091 <6>[ 0.101907] CPU features: detected: Spectre-BHB
10123 23:20:13.639330 <6>[ 0.101912] Detected PIPT I-cache on CPU4
10124 23:20:13.645908 <6>[ 0.101968] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10125 23:20:13.652699 <6>[ 0.101984] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10126 23:20:13.660031 <6>[ 0.102273] Detected PIPT I-cache on CPU5
10127 23:20:13.665779 <6>[ 0.102336] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10128 23:20:13.671967 <6>[ 0.102352] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10129 23:20:13.676116 <6>[ 0.102631] Detected PIPT I-cache on CPU6
10130 23:20:13.682448 <6>[ 0.102693] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10131 23:20:13.688960 <6>[ 0.102709] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10132 23:20:13.696116 <6>[ 0.103008] Detected PIPT I-cache on CPU7
10133 23:20:13.701921 <6>[ 0.103073] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10134 23:20:13.708883 <6>[ 0.103089] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10135 23:20:13.712051 <6>[ 0.103136] smp: Brought up 1 node, 8 CPUs
10136 23:20:13.718837 <6>[ 0.244445] SMP: Total of 8 processors activated.
10137 23:20:13.721633 <6>[ 0.249366] CPU features: detected: 32-bit EL0 Support
10138 23:20:13.732840 <6>[ 0.254762] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10139 23:20:13.738538 <6>[ 0.263562] CPU features: detected: Common not Private translations
10140 23:20:13.745040 <6>[ 0.270078] CPU features: detected: CRC32 instructions
10141 23:20:13.751690 <6>[ 0.275430] CPU features: detected: RCpc load-acquire (LDAPR)
10142 23:20:13.754716 <6>[ 0.281390] CPU features: detected: LSE atomic instructions
10143 23:20:13.761407 <6>[ 0.287171] CPU features: detected: Privileged Access Never
10144 23:20:13.769320 <6>[ 0.292987] CPU features: detected: RAS Extension Support
10145 23:20:13.774384 <6>[ 0.298596] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10146 23:20:13.777440 <6>[ 0.305860] CPU: All CPU(s) started at EL2
10147 23:20:13.784167 <6>[ 0.310176] alternatives: applying system-wide alternatives
10148 23:20:13.793824 <6>[ 0.320184] devtmpfs: initialized
10149 23:20:13.808374 <6>[ 0.328463] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10150 23:20:13.815150 <6>[ 0.338423] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10151 23:20:13.821386 <6>[ 0.346674] pinctrl core: initialized pinctrl subsystem
10152 23:20:13.825262 <6>[ 0.353318] DMI not present or invalid.
10153 23:20:13.832015 <6>[ 0.357721] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10154 23:20:13.841488 <6>[ 0.364615] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10155 23:20:13.848691 <6>[ 0.372064] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10156 23:20:13.858026 <6>[ 0.380156] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10157 23:20:13.861583 <6>[ 0.388308] audit: initializing netlink subsys (disabled)
10158 23:20:13.871457 <5>[ 0.394005] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10159 23:20:13.878034 <6>[ 0.394706] thermal_sys: Registered thermal governor 'step_wise'
10160 23:20:13.885250 <6>[ 0.401971] thermal_sys: Registered thermal governor 'power_allocator'
10161 23:20:13.887560 <6>[ 0.408224] cpuidle: using governor menu
10162 23:20:13.894183 <6>[ 0.419187] NET: Registered PF_QIPCRTR protocol family
10163 23:20:13.900860 <6>[ 0.424684] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10164 23:20:13.907586 <6>[ 0.431785] ASID allocator initialised with 32768 entries
10165 23:20:13.910439 <6>[ 0.438341] Serial: AMBA PL011 UART driver
10166 23:20:13.921408 <4>[ 0.447165] Trying to register duplicate clock ID: 134
10167 23:20:13.976822 <6>[ 0.505066] KASLR enabled
10168 23:20:13.989796 <6>[ 0.512791] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10169 23:20:13.996702 <6>[ 0.519808] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10170 23:20:14.003161 <6>[ 0.526301] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10171 23:20:14.009167 <6>[ 0.533306] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10172 23:20:14.015716 <6>[ 0.539793] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10173 23:20:14.022763 <6>[ 0.546796] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10174 23:20:14.029331 <6>[ 0.553281] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10175 23:20:14.037024 <6>[ 0.560285] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10176 23:20:14.040359 <6>[ 0.567805] ACPI: Interpreter disabled.
10177 23:20:14.047859 <6>[ 0.574330] iommu: Default domain type: Translated
10178 23:20:14.054077 <6>[ 0.579444] iommu: DMA domain TLB invalidation policy: strict mode
10179 23:20:14.058033 <5>[ 0.586101] SCSI subsystem initialized
10180 23:20:14.064931 <6>[ 0.590268] usbcore: registered new interface driver usbfs
10181 23:20:14.071684 <6>[ 0.596002] usbcore: registered new interface driver hub
10182 23:20:14.074286 <6>[ 0.601555] usbcore: registered new device driver usb
10183 23:20:14.081090 <6>[ 0.607657] pps_core: LinuxPPS API ver. 1 registered
10184 23:20:14.090660 <6>[ 0.612850] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10185 23:20:14.095133 <6>[ 0.622195] PTP clock support registered
10186 23:20:14.097368 <6>[ 0.626437] EDAC MC: Ver: 3.0.0
10187 23:20:14.105159 <6>[ 0.631605] FPGA manager framework
10188 23:20:14.112207 <6>[ 0.635282] Advanced Linux Sound Architecture Driver Initialized.
10189 23:20:14.117929 <6>[ 0.642060] vgaarb: loaded
10190 23:20:14.121665 <6>[ 0.645236] clocksource: Switched to clocksource arch_sys_counter
10191 23:20:14.124832 <5>[ 0.651674] VFS: Disk quotas dquot_6.6.0
10192 23:20:14.131577 <6>[ 0.655859] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10193 23:20:14.134909 <6>[ 0.663047] pnp: PnP ACPI: disabled
10194 23:20:14.143519 <6>[ 0.669674] NET: Registered PF_INET protocol family
10195 23:20:14.149872 <6>[ 0.675076] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10196 23:20:14.162364 <6>[ 0.685088] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10197 23:20:14.172252 <6>[ 0.693876] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10198 23:20:14.178275 <6>[ 0.701845] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10199 23:20:14.185017 <6>[ 0.710248] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10200 23:20:14.195878 <6>[ 0.718900] TCP: Hash tables configured (established 32768 bind 32768)
10201 23:20:14.202325 <6>[ 0.725755] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10202 23:20:14.209166 <6>[ 0.732774] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10203 23:20:14.215383 <6>[ 0.740288] NET: Registered PF_UNIX/PF_LOCAL protocol family
10204 23:20:14.221732 <6>[ 0.746354] RPC: Registered named UNIX socket transport module.
10205 23:20:14.226190 <6>[ 0.752501] RPC: Registered udp transport module.
10206 23:20:14.231985 <6>[ 0.757436] RPC: Registered tcp transport module.
10207 23:20:14.239122 <6>[ 0.762365] RPC: Registered tcp NFSv4.1 backchannel transport module.
10208 23:20:14.242345 <6>[ 0.769028] PCI: CLS 0 bytes, default 64
10209 23:20:14.245179 <6>[ 0.773313] Unpacking initramfs...
10210 23:20:14.255100 <6>[ 0.777333] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10211 23:20:14.261498 <6>[ 0.785963] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10212 23:20:14.268991 <6>[ 0.794792] kvm [1]: IPA Size Limit: 40 bits
10213 23:20:14.272488 <6>[ 0.799316] kvm [1]: GICv3: no GICV resource entry
10214 23:20:14.278082 <6>[ 0.804335] kvm [1]: disabling GICv2 emulation
10215 23:20:14.284949 <6>[ 0.809021] kvm [1]: GIC system register CPU interface enabled
10216 23:20:14.288835 <6>[ 0.815170] kvm [1]: vgic interrupt IRQ18
10217 23:20:14.294803 <6>[ 0.819525] kvm [1]: VHE mode initialized successfully
10218 23:20:14.299041 <5>[ 0.826029] Initialise system trusted keyrings
10219 23:20:14.304288 <6>[ 0.830868] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10220 23:20:14.314138 <6>[ 0.840772] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10221 23:20:14.323600 <5>[ 0.847144] NFS: Registering the id_resolver key type
10222 23:20:14.324914 <5>[ 0.852439] Key type id_resolver registered
10223 23:20:14.331434 <5>[ 0.856854] Key type id_legacy registered
10224 23:20:14.337363 <6>[ 0.861132] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10225 23:20:14.344115 <6>[ 0.868054] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10226 23:20:14.350583 <6>[ 0.875760] 9p: Installing v9fs 9p2000 file system support
10227 23:20:14.386439 <5>[ 0.912626] Key type asymmetric registered
10228 23:20:14.389363 <5>[ 0.916953] Asymmetric key parser 'x509' registered
10229 23:20:14.399365 <6>[ 0.922092] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10230 23:20:14.402447 <6>[ 0.929708] io scheduler mq-deadline registered
10231 23:20:14.405769 <6>[ 0.934468] io scheduler kyber registered
10232 23:20:14.425858 <6>[ 0.951778] EINJ: ACPI disabled.
10233 23:20:14.457364 <4>[ 0.977910] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10234 23:20:14.467920 <4>[ 0.988538] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10235 23:20:14.482964 <6>[ 1.009418] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10236 23:20:14.491860 <6>[ 1.017489] printk: console [ttyS0] disabled
10237 23:20:14.518946 <6>[ 1.042120] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10238 23:20:14.526868 <6>[ 1.051609] printk: console [ttyS0] enabled
10239 23:20:14.528775 <6>[ 1.051609] printk: console [ttyS0] enabled
10240 23:20:14.536278 <6>[ 1.060507] printk: bootconsole [mtk8250] disabled
10241 23:20:14.539031 <6>[ 1.060507] printk: bootconsole [mtk8250] disabled
10242 23:20:14.545478 <6>[ 1.071770] SuperH (H)SCI(F) driver initialized
10243 23:20:14.548593 <6>[ 1.077049] msm_serial: driver initialized
10244 23:20:14.562807 <6>[ 1.086065] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10245 23:20:14.573212 <6>[ 1.094612] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10246 23:20:14.579073 <6>[ 1.103155] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10247 23:20:14.589447 <6>[ 1.111783] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10248 23:20:14.596595 <6>[ 1.120490] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10249 23:20:14.605471 <6>[ 1.129204] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10250 23:20:14.615631 <6>[ 1.137746] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10251 23:20:14.622505 <6>[ 1.146555] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10252 23:20:14.636139 <6>[ 1.155101] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10253 23:20:14.644146 <6>[ 1.170595] loop: module loaded
10254 23:20:14.650852 <6>[ 1.176459] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10255 23:20:14.673341 <4>[ 1.199731] mtk-pmic-keys: Failed to locate of_node [id: -1]
10256 23:20:14.680028 <6>[ 1.206765] megasas: 07.719.03.00-rc1
10257 23:20:14.689995 <6>[ 1.216501] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10258 23:20:14.697801 <6>[ 1.224593] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10259 23:20:14.714366 <6>[ 1.240967] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10260 23:20:14.769805 <6>[ 1.289675] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10261 23:20:15.077924 <6>[ 1.604924] Freeing initrd memory: 18328K
10262 23:20:15.089800 <6>[ 1.616557] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10263 23:20:15.101088 <6>[ 1.627528] tun: Universal TUN/TAP device driver, 1.6
10264 23:20:15.104469 <6>[ 1.633621] thunder_xcv, ver 1.0
10265 23:20:15.107057 <6>[ 1.637118] thunder_bgx, ver 1.0
10266 23:20:15.110981 <6>[ 1.640617] nicpf, ver 1.0
10267 23:20:15.121353 <6>[ 1.644648] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10268 23:20:15.124957 <6>[ 1.652127] hns3: Copyright (c) 2017 Huawei Corporation.
10269 23:20:15.128998 <6>[ 1.657715] hclge is initializing
10270 23:20:15.137555 <6>[ 1.661297] e1000: Intel(R) PRO/1000 Network Driver
10271 23:20:15.141475 <6>[ 1.666425] e1000: Copyright (c) 1999-2006 Intel Corporation.
10272 23:20:15.144324 <6>[ 1.672440] e1000e: Intel(R) PRO/1000 Network Driver
10273 23:20:15.151168 <6>[ 1.677656] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10274 23:20:15.158084 <6>[ 1.683841] igb: Intel(R) Gigabit Ethernet Network Driver
10275 23:20:15.164453 <6>[ 1.689490] igb: Copyright (c) 2007-2014 Intel Corporation.
10276 23:20:15.172136 <6>[ 1.695326] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10277 23:20:15.178030 <6>[ 1.701844] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10278 23:20:15.181198 <6>[ 1.708318] sky2: driver version 1.30
10279 23:20:15.187878 <6>[ 1.713328] VFIO - User Level meta-driver version: 0.3
10280 23:20:15.194678 <6>[ 1.721603] usbcore: registered new interface driver usb-storage
10281 23:20:15.201777 <6>[ 1.728049] usbcore: registered new device driver onboard-usb-hub
10282 23:20:15.210746 <6>[ 1.737252] mt6397-rtc mt6359-rtc: registered as rtc0
10283 23:20:15.221630 <6>[ 1.742712] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:20:16 UTC (1712186416)
10284 23:20:15.223562 <6>[ 1.752279] i2c_dev: i2c /dev entries driver
10285 23:20:15.242007 <6>[ 1.764092] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10286 23:20:15.247839 <4>[ 1.772831] cpu cpu0: supply cpu not found, using dummy regulator
10287 23:20:15.254225 <4>[ 1.779253] cpu cpu1: supply cpu not found, using dummy regulator
10288 23:20:15.260908 <4>[ 1.785661] cpu cpu2: supply cpu not found, using dummy regulator
10289 23:20:15.268075 <4>[ 1.792075] cpu cpu3: supply cpu not found, using dummy regulator
10290 23:20:15.274337 <4>[ 1.798474] cpu cpu4: supply cpu not found, using dummy regulator
10291 23:20:15.280393 <4>[ 1.804872] cpu cpu5: supply cpu not found, using dummy regulator
10292 23:20:15.287279 <4>[ 1.811270] cpu cpu6: supply cpu not found, using dummy regulator
10293 23:20:15.290671 <4>[ 1.817666] cpu cpu7: supply cpu not found, using dummy regulator
10294 23:20:15.311377 <6>[ 1.838295] cpu cpu0: EM: created perf domain
10295 23:20:15.315720 <6>[ 1.843203] cpu cpu4: EM: created perf domain
10296 23:20:15.322154 <6>[ 1.848751] sdhci: Secure Digital Host Controller Interface driver
10297 23:20:15.328791 <6>[ 1.855182] sdhci: Copyright(c) Pierre Ossman
10298 23:20:15.335122 <6>[ 1.860099] Synopsys Designware Multimedia Card Interface Driver
10299 23:20:15.342454 <6>[ 1.866708] sdhci-pltfm: SDHCI platform and OF driver helper
10300 23:20:15.345399 <6>[ 1.866888] mmc0: CQHCI version 5.10
10301 23:20:15.351939 <6>[ 1.876727] ledtrig-cpu: registered to indicate activity on CPUs
10302 23:20:15.358985 <6>[ 1.883649] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10303 23:20:15.365662 <6>[ 1.890673] usbcore: registered new interface driver usbhid
10304 23:20:15.369361 <6>[ 1.896496] usbhid: USB HID core driver
10305 23:20:15.375158 <6>[ 1.900695] spi_master spi0: will run message pump with realtime priority
10306 23:20:15.416003 <6>[ 1.936090] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10307 23:20:15.434800 <6>[ 1.951541] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10308 23:20:15.438626 <6>[ 1.965117] mmc0: Command Queue Engine enabled
10309 23:20:15.444909 <6>[ 1.969867] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10310 23:20:15.452008 <6>[ 1.976785] cros-ec-spi spi0.0: Chrome EC device registered
10311 23:20:15.455109 <6>[ 1.977094] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10312 23:20:15.465377 <6>[ 1.992266] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10313 23:20:15.473595 <6>[ 1.999563] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10314 23:20:15.479443 <6>[ 2.005500] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10315 23:20:15.486053 <6>[ 2.011419] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10316 23:20:15.501165 <6>[ 2.024429] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10317 23:20:15.508095 <6>[ 2.034969] NET: Registered PF_PACKET protocol family
10318 23:20:15.511653 <6>[ 2.040385] 9pnet: Installing 9P2000 support
10319 23:20:15.518087 <5>[ 2.044948] Key type dns_resolver registered
10320 23:20:15.521309 <6>[ 2.049900] registered taskstats version 1
10321 23:20:15.528308 <5>[ 2.054281] Loading compiled-in X.509 certificates
10322 23:20:15.561026 <4>[ 2.078461] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10323 23:20:15.568353 <4>[ 2.089292] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10324 23:20:15.575862 <3>[ 2.099838] debugfs: File 'uA_load' in directory '/' already present!
10325 23:20:15.581316 <3>[ 2.106538] debugfs: File 'min_uV' in directory '/' already present!
10326 23:20:15.589112 <3>[ 2.113146] debugfs: File 'max_uV' in directory '/' already present!
10327 23:20:15.594529 <3>[ 2.119752] debugfs: File 'constraint_flags' in directory '/' already present!
10328 23:20:15.606232 <3>[ 2.129318] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10329 23:20:15.616619 <6>[ 2.143024] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10330 23:20:15.623202 <6>[ 2.149812] xhci-mtk 11200000.usb: xHCI Host Controller
10331 23:20:15.629994 <6>[ 2.155343] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10332 23:20:15.640578 <6>[ 2.163187] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10333 23:20:15.646583 <6>[ 2.172607] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10334 23:20:15.653299 <6>[ 2.178674] xhci-mtk 11200000.usb: xHCI Host Controller
10335 23:20:15.659637 <6>[ 2.184152] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10336 23:20:15.665918 <6>[ 2.191800] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10337 23:20:15.674852 <6>[ 2.199557] hub 1-0:1.0: USB hub found
10338 23:20:15.676243 <6>[ 2.203585] hub 1-0:1.0: 1 port detected
10339 23:20:15.682813 <6>[ 2.207860] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10340 23:20:15.689911 <6>[ 2.216477] hub 2-0:1.0: USB hub found
10341 23:20:15.692967 <6>[ 2.220494] hub 2-0:1.0: 1 port detected
10342 23:20:15.700558 <6>[ 2.226974] mtk-msdc 11f70000.mmc: Got CD GPIO
10343 23:20:15.713107 <6>[ 2.236345] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10344 23:20:15.719750 <6>[ 2.244377] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10345 23:20:15.729567 <4>[ 2.252287] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10346 23:20:15.739830 <6>[ 2.261811] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10347 23:20:15.746116 <6>[ 2.269889] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10348 23:20:15.753210 <6>[ 2.277948] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10349 23:20:15.763568 <6>[ 2.285882] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10350 23:20:15.769581 <6>[ 2.293706] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10351 23:20:15.779724 <6>[ 2.301525] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10352 23:20:15.789168 <6>[ 2.311723] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10353 23:20:15.797195 <6>[ 2.320109] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10354 23:20:15.805852 <6>[ 2.328456] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10355 23:20:15.812755 <6>[ 2.336795] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10356 23:20:15.822760 <6>[ 2.345134] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10357 23:20:15.828643 <6>[ 2.353472] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10358 23:20:15.838734 <6>[ 2.361809] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10359 23:20:15.845279 <6>[ 2.370146] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10360 23:20:15.855234 <6>[ 2.378484] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10361 23:20:15.862138 <6>[ 2.386835] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10362 23:20:15.872088 <6>[ 2.395173] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10363 23:20:15.878266 <6>[ 2.403509] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10364 23:20:15.888624 <6>[ 2.411846] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10365 23:20:15.898820 <6>[ 2.420184] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10366 23:20:15.904896 <6>[ 2.428521] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10367 23:20:15.911687 <6>[ 2.437232] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10368 23:20:15.918096 <6>[ 2.444426] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10369 23:20:15.925286 <6>[ 2.451251] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10370 23:20:15.936222 <6>[ 2.458059] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10371 23:20:15.941045 <6>[ 2.465009] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10372 23:20:15.947695 <6>[ 2.471857] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10373 23:20:15.958174 <6>[ 2.480987] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10374 23:20:15.968375 <6>[ 2.490106] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10375 23:20:15.977787 <6>[ 2.499401] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10376 23:20:15.987601 <6>[ 2.508867] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10377 23:20:15.998538 <6>[ 2.518333] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10378 23:20:16.003814 <6>[ 2.527454] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10379 23:20:16.013887 <6>[ 2.536920] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10380 23:20:16.024289 <6>[ 2.546038] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10381 23:20:16.034404 <6>[ 2.555330] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10382 23:20:16.044257 <6>[ 2.565490] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10383 23:20:16.054383 <6>[ 2.577068] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10384 23:20:16.060134 <6>[ 2.586740] Trying to probe devices needed for running init ...
10385 23:20:16.094224 <6>[ 2.617497] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10386 23:20:16.248662 <6>[ 2.775418] hub 1-1:1.0: USB hub found
10387 23:20:16.252361 <6>[ 2.779950] hub 1-1:1.0: 4 ports detected
10388 23:20:16.263485 <6>[ 2.788776] hub 1-1:1.0: USB hub found
10389 23:20:16.265261 <6>[ 2.793166] hub 1-1:1.0: 4 ports detected
10390 23:20:16.374933 <6>[ 2.897878] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10391 23:20:16.400439 <6>[ 2.927378] hub 2-1:1.0: USB hub found
10392 23:20:16.403846 <6>[ 2.931887] hub 2-1:1.0: 3 ports detected
10393 23:20:16.413485 <6>[ 2.940314] hub 2-1:1.0: USB hub found
10394 23:20:16.416817 <6>[ 2.944793] hub 2-1:1.0: 3 ports detected
10395 23:20:16.589675 <6>[ 3.113539] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10396 23:20:16.722440 <6>[ 3.249312] hub 1-1.4:1.0: USB hub found
10397 23:20:16.725527 <6>[ 3.253985] hub 1-1.4:1.0: 2 ports detected
10398 23:20:16.734508 <6>[ 3.261004] hub 1-1.4:1.0: USB hub found
10399 23:20:16.737393 <6>[ 3.265588] hub 1-1.4:1.0: 2 ports detected
10400 23:20:16.802388 <6>[ 3.325672] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10401 23:20:17.033627 <6>[ 3.557558] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10402 23:20:17.225723 <6>[ 3.749558] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10403 23:20:28.331635 <6>[ 14.862648] ALSA device list:
10404 23:20:28.337455 <6>[ 14.865938] No soundcards found.
10405 23:20:28.345253 <6>[ 14.873865] Freeing unused kernel memory: 8448K
10406 23:20:28.349871 <6>[ 14.879477] Run /init as init process
10407 23:20:28.359566 Loading, please wait...
10408 23:20:28.386183 Starting systemd-udevd version 252.22-1~deb12u1
10409 23:20:28.386387
10410 23:20:28.613652 <6>[ 15.138489] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10411 23:20:28.621488 <6>[ 15.138579] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10412 23:20:28.630497 <6>[ 15.147633] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10413 23:20:28.639774 <6>[ 15.162962] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10414 23:20:28.647306 <6>[ 15.174043] remoteproc remoteproc0: scp is available
10415 23:20:28.649876 <6>[ 15.179352] remoteproc remoteproc0: powering up scp
10416 23:20:28.660304 <3>[ 15.180992] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10417 23:20:28.666297 <6>[ 15.184493] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10418 23:20:28.673102 <6>[ 15.184510] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10419 23:20:28.679962 <6>[ 15.185448] usbcore: registered new device driver r8152-cfgselector
10420 23:20:28.690046 <3>[ 15.193063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10421 23:20:28.696167 <4>[ 15.203625] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10422 23:20:28.703569 <3>[ 15.207730] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10423 23:20:28.709217 <4>[ 15.219203] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10424 23:20:28.719391 <3>[ 15.221995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10425 23:20:28.723518 <6>[ 15.222115] mc: Linux media interface: v0.10
10426 23:20:28.726312 <6>[ 15.230342] Bluetooth: Core ver 2.22
10427 23:20:28.736262 <6>[ 15.230386] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10428 23:20:28.742329 <3>[ 15.236943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10429 23:20:28.751779 <3>[ 15.236962] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10430 23:20:28.759919 <3>[ 15.236978] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10431 23:20:28.765691 <6>[ 15.247087] NET: Registered PF_BLUETOOTH protocol family
10432 23:20:28.772642 <3>[ 15.252351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10433 23:20:28.782785 <3>[ 15.252400] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10434 23:20:28.789036 <6>[ 15.257152] Bluetooth: HCI device and connection manager initialized
10435 23:20:28.795817 <3>[ 15.260811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10436 23:20:28.803042 <6>[ 15.268445] Bluetooth: HCI socket layer initialized
10437 23:20:28.809142 <3>[ 15.276445] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10438 23:20:28.816006 <6>[ 15.284551] Bluetooth: L2CAP socket layer initialized
10439 23:20:28.822151 <3>[ 15.292596] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10440 23:20:28.829081 <6>[ 15.297856] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10441 23:20:28.836042 <6>[ 15.297860] pci_bus 0000:00: root bus resource [bus 00-ff]
10442 23:20:28.842659 <6>[ 15.297864] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10443 23:20:28.852390 <6>[ 15.297867] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10444 23:20:28.858643 <6>[ 15.297893] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10445 23:20:28.865470 <6>[ 15.297905] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10446 23:20:28.872917 <6>[ 15.297975] pci 0000:00:00.0: supports D1 D2
10447 23:20:28.878281 <6>[ 15.297977] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10448 23:20:28.882118 <6>[ 15.298380] Bluetooth: SCO socket layer initialized
10449 23:20:28.891612 <6>[ 15.298943] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10450 23:20:28.898551 <6>[ 15.299024] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10451 23:20:28.905126 <6>[ 15.299049] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10452 23:20:28.911758 <6>[ 15.299065] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10453 23:20:28.918250 <6>[ 15.299080] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10454 23:20:28.924889 <6>[ 15.299188] pci 0000:01:00.0: supports D1 D2
10455 23:20:28.932838 <6>[ 15.299190] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10456 23:20:28.938016 <4>[ 15.302673] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10457 23:20:28.944442 <4>[ 15.302673] Fallback method does not support PEC.
10458 23:20:28.951512 <3>[ 15.306292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10459 23:20:28.961595 <6>[ 15.310229] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10460 23:20:28.968156 <6>[ 15.310236] remoteproc remoteproc0: remote processor scp is now up
10461 23:20:28.974844 <6>[ 15.310247] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10462 23:20:28.984485 <3>[ 15.316912] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10463 23:20:28.991483 <6>[ 15.317482] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10464 23:20:29.000667 <3>[ 15.320962] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10465 23:20:29.007694 <3>[ 15.320967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10466 23:20:29.017190 <3>[ 15.320974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10467 23:20:29.023818 <6>[ 15.321032] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10468 23:20:29.031270 <6>[ 15.321064] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10469 23:20:29.040489 <6>[ 15.321068] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10470 23:20:29.047835 <6>[ 15.321075] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10471 23:20:29.054097 <6>[ 15.321088] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10472 23:20:29.064042 <6>[ 15.321100] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10473 23:20:29.067398 <6>[ 15.321112] pci 0000:00:00.0: PCI bridge to [bus 01]
10474 23:20:29.077653 <6>[ 15.321116] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10475 23:20:29.084164 <6>[ 15.321309] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10476 23:20:29.090494 <6>[ 15.321757] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10477 23:20:29.093797 <6>[ 15.322212] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10478 23:20:29.104461 <6>[ 15.323097] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10479 23:20:29.110260 <6>[ 15.325630] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10480 23:20:29.120320 <6>[ 15.330017] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10481 23:20:29.130068 <3>[ 15.334177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10482 23:20:29.137105 <3>[ 15.334190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10483 23:20:29.149358 <6>[ 15.399493] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10484 23:20:29.156674 <6>[ 15.404527] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10485 23:20:29.166159 <4>[ 15.407143] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10486 23:20:29.173297 <4>[ 15.407159] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10487 23:20:29.176274 <6>[ 15.457496] r8152 2-1.3:1.0 eth0: v1.12.13
10488 23:20:29.183202 <6>[ 15.478416] videodev: Linux video capture interface: v2.00
10489 23:20:29.190080 <6>[ 15.486651] usbcore: registered new interface driver r8152
10490 23:20:29.196280 <5>[ 15.497518] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10491 23:20:29.202603 <6>[ 15.537445] usbcore: registered new interface driver cdc_ether
10492 23:20:29.209531 <6>[ 15.542493] usbcore: registered new interface driver btusb
10493 23:20:29.219456 <4>[ 15.543374] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10494 23:20:29.226601 <3>[ 15.543391] Bluetooth: hci0: Failed to load firmware file (-2)
10495 23:20:29.232771 <3>[ 15.543396] Bluetooth: hci0: Failed to set up firmware (-2)
10496 23:20:29.242582 <4>[ 15.543401] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10497 23:20:29.251206 <6>[ 15.551060] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10498 23:20:29.256197 <6>[ 15.557469] usbcore: registered new interface driver r8153_ecm
10499 23:20:29.262024 <5>[ 15.560103] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10500 23:20:29.268550 <5>[ 15.560336] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10501 23:20:29.279205 <4>[ 15.560387] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10502 23:20:29.282381 <6>[ 15.560392] cfg80211: failed to load regulatory.db
10503 23:20:29.295319 <6>[ 15.567190] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10504 23:20:29.301797 <6>[ 15.573574] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10505 23:20:29.308661 <6>[ 15.580923] usbcore: registered new interface driver uvcvideo
10506 23:20:29.318368 <3>[ 15.583880] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10507 23:20:29.324509 <6>[ 15.590104] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10508 23:20:29.331487 <6>[ 15.654836] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10509 23:20:29.337985 <6>[ 15.864220] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10510 23:20:29.360485 <6>[ 15.889474] mt7921e 0000:01:00.0: ASIC revision: 79610010
10511 23:20:29.463284 <6>[ 15.988557] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10512 23:20:29.466079 <6>[ 15.988557]
10513 23:20:29.481548 Begin: Loading essential drivers ... done.
10514 23:20:29.484369 Begin: Running /scripts/init-premount ... done.
10515 23:20:29.491223 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10516 23:20:29.501478 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10517 23:20:29.504413 Device /sys/class/net/enx00e04c6803bd found
10518 23:20:29.504508 done.
10519 23:20:29.528930 Begin: Waiting up to 180 secs for any network device to become available ... done.
10520 23:20:29.592159 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10521 23:20:29.734599 <6>[ 16.259313] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10522 23:20:30.525037 <6>[ 17.052911] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10523 23:20:30.597249 <6>[ 17.125489] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10524 23:20:30.714085 IP-Config: no response after 2 secs - giving up
10525 23:20:30.748547 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10526 23:20:30.768825 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10527 23:20:31.444602 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10528 23:20:31.450820 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10529 23:20:31.457772 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10530 23:20:31.465066 host : mt8192-asurada-spherion-r0-cbg-4
10531 23:20:31.470653 domain : lava-rack
10532 23:20:31.477132 rootserver: 192.168.201.1 rootpath:
10533 23:20:31.477218 filename :
10534 23:20:31.553177 done.
10535 23:20:31.555931 Begin: Running /scripts/nfs-bottom ... done.
10536 23:20:31.570657 Begin: Running /scripts/init-bottom ... done.
10537 23:20:32.885723 <6>[ 19.415017] NET: Registered PF_INET6 protocol family
10538 23:20:32.893582 <6>[ 19.423043] Segment Routing with IPv6
10539 23:20:32.896997 <6>[ 19.427059] In-situ OAM (IOAM) with IPv6
10540 23:20:33.088184 <30>[ 19.591406] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10541 23:20:33.095654 <30>[ 19.624526] systemd[1]: Detected architecture arm64.
10542 23:20:33.102636
10543 23:20:33.106444 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10544 23:20:33.106530
10545 23:20:33.106614
10546 23:20:33.132938 <30>[ 19.662552] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10547 23:20:34.016325 <30>[ 20.541827] systemd[1]: Queued start job for default target graphical.target.
10548 23:20:34.059047 <30>[ 20.584975] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10549 23:20:34.065326 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10550 23:20:34.065437
10551 23:20:34.088849 <30>[ 20.614981] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10552 23:20:34.098632 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10553 23:20:34.098733
10554 23:20:34.117318 <30>[ 20.643448] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10555 23:20:34.127121 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10556 23:20:34.127231
10557 23:20:34.145393 <30>[ 20.671176] systemd[1]: Created slice user.slice - User and Session Slice.
10558 23:20:34.151172 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10559 23:20:34.151259
10560 23:20:34.176072 <30>[ 20.698490] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10561 23:20:34.186848 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10562 23:20:34.186955
10563 23:20:34.208202 <30>[ 20.730428] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10564 23:20:34.214832 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10565 23:20:34.214922
10566 23:20:34.241613 <30>[ 20.757771] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10567 23:20:34.251361 <30>[ 20.777632] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10568 23:20:34.257663 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10569 23:20:34.257751
10570 23:20:34.276585 <30>[ 20.801960] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10571 23:20:34.285377 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10572 23:20:34.285475
10573 23:20:34.304110 <30>[ 20.830093] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10574 23:20:34.313865 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10575 23:20:34.313949
10576 23:20:34.328653 <30>[ 20.858149] systemd[1]: Reached target paths.target - Path Units.
10577 23:20:34.335430 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10578 23:20:34.339044
10579 23:20:34.355873 <30>[ 20.881624] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10580 23:20:34.361938 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10581 23:20:34.362032
10582 23:20:34.376408 <30>[ 20.905555] systemd[1]: Reached target slices.target - Slice Units.
10583 23:20:34.386191 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10584 23:20:34.386281
10585 23:20:34.401164 <30>[ 20.930043] systemd[1]: Reached target swap.target - Swaps.
10586 23:20:34.407666 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10587 23:20:34.407752
10588 23:20:34.427935 <30>[ 20.954063] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10589 23:20:34.438255 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10590 23:20:34.438348
10591 23:20:34.456445 <30>[ 20.982545] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10592 23:20:34.466141 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10593 23:20:34.466243
10594 23:20:34.485919 <30>[ 21.011684] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10595 23:20:34.496577 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10596 23:20:34.496668
10597 23:20:34.513179 <30>[ 21.038931] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10598 23:20:34.522699 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10599 23:20:34.522795
10600 23:20:34.540003 <30>[ 21.066266] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10601 23:20:34.546491 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10602 23:20:34.546578
10603 23:20:34.564687 <30>[ 21.091040] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10604 23:20:34.575733 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10605 23:20:34.575836
10606 23:20:34.594770 <30>[ 21.120713] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10607 23:20:34.605667 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10608 23:20:34.605754
10609 23:20:34.620309 <30>[ 21.146097] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10610 23:20:34.629792 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10611 23:20:34.629881
10612 23:20:34.687433 <30>[ 21.213697] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10613 23:20:34.694004 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10614 23:20:34.694096
10615 23:20:34.718806 <30>[ 21.244741] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10616 23:20:34.725406 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10617 23:20:34.725540
10618 23:20:34.753302 <30>[ 21.279440] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10619 23:20:34.760580 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10620 23:20:34.760675
10621 23:20:34.786265 <30>[ 21.306113] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10622 23:20:34.823986 <30>[ 21.350261] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10623 23:20:34.834206 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10624 23:20:34.834314
10625 23:20:34.858009 <30>[ 21.383961] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10626 23:20:34.864452 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10627 23:20:34.864552
10628 23:20:34.887658 <30>[ 21.413502] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10629 23:20:34.893995 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10630 23:20:34.894090
10631 23:20:34.922363 <30>[ 21.448407] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10632 23:20:34.935275 Starting [0;1;39mmodprobe@drm.service<6>[ 21.459697] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10633 23:20:34.938808 [0m - Load Kernel Module drm...
10634 23:20:34.938893
10635 23:20:34.961367 <30>[ 21.487738] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10636 23:20:34.971323 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10637 23:20:34.971426
10638 23:20:35.008217 <30>[ 21.534318] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10639 23:20:35.014949 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10640 23:20:35.015046
10641 23:20:35.041818 <30>[ 21.567932] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10642 23:20:35.048151 Startin<6>[ 21.577182] fuse: init (API version 7.37)
10643 23:20:35.054888 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10644 23:20:35.054983
10645 23:20:35.086994 <30>[ 21.612588] systemd[1]: Starting systemd-journald.service - Journal Service...
10646 23:20:35.093236 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10647 23:20:35.093336
10648 23:20:35.123333 <30>[ 21.649380] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10649 23:20:35.132275 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10650 23:20:35.132363
10651 23:20:35.161197 <30>[ 21.684163] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10652 23:20:35.168852 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10653 23:20:35.168944
10654 23:20:35.193137 <30>[ 21.719612] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10655 23:20:35.203261 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10656 23:20:35.203364
10657 23:20:35.215341 <3>[ 21.740807] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10658 23:20:35.230195 <30>[ 21.756258] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10659 23:20:35.236884 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10660 23:20:35.237004
10661 23:20:35.250714 <3>[ 21.777143] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10662 23:20:35.266731 <30>[ 21.792503] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10663 23:20:35.273017 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10664 23:20:35.273115
10665 23:20:35.283328 <3>[ 21.808593] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10666 23:20:35.296320 <30>[ 21.822075] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10667 23:20:35.310327 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 21.836270] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10668 23:20:35.312993 File System.
10669 23:20:35.313080
10670 23:20:35.332100 <30>[ 21.858039] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10671 23:20:35.339028 <3>[ 21.865951] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10672 23:20:35.349551 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10673 23:20:35.349642
10674 23:20:35.359716 <3>[ 21.886012] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10675 23:20:35.370119 <30>[ 21.896548] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10676 23:20:35.380639 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10677 23:20:35.380774
10678 23:20:35.388065 <30>[ 21.916171] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10679 23:20:35.397344 <3>[ 21.919141] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10680 23:20:35.407436 <30>[ 21.924363] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10681 23:20:35.414224 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10682 23:20:35.414312
10683 23:20:35.427368 <3>[ 21.953028] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10684 23:20:35.436538 <30>[ 21.963233] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10685 23:20:35.443473 <30>[ 21.971042] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10686 23:20:35.460641 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Mo<3>[ 21.985156] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10687 23:20:35.460777 dule dm_mod.
10688 23:20:35.460864
10689 23:20:35.482385 <30>[ 22.011306] systemd[1]: modprobe@drm.service: Deactivated successfully.
10690 23:20:35.492006 <3>[ 22.015886] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10691 23:20:35.498906 <30>[ 22.019040] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10692 23:20:35.508458 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10693 23:20:35.508544
10694 23:20:35.529370 <30>[ 22.054566] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10695 23:20:35.536091 <30>[ 22.062977] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10696 23:20:35.546350 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10697 23:20:35.546439
10698 23:20:35.563920 <30>[ 22.090252] systemd[1]: Started systemd-journald.service - Journal Service.
10699 23:20:35.570268 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10700 23:20:35.570360
10701 23:20:35.596219 <4>[ 22.116162] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10702 23:20:35.606784 <3>[ 22.131829] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10703 23:20:35.612624 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10704 23:20:35.612736
10705 23:20:35.639657 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10706 23:20:35.639776
10707 23:20:35.657296 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10708 23:20:35.657389
10709 23:20:35.677933 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10710 23:20:35.678035
10711 23:20:35.696894 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10712 23:20:35.696987
10713 23:20:35.717358 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10714 23:20:35.717455
10715 23:20:35.739519 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10716 23:20:35.739612
10717 23:20:35.796234 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10718 23:20:35.796380
10719 23:20:35.821244 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10720 23:20:35.821351
10721 23:20:35.845762 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10722 23:20:35.845865
10723 23:20:35.871447 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10724 23:20:35.871569
10725 23:20:35.897917 <46>[ 22.422500] systemd-journald[300]: Received client request to flush runtime journal.
10726 23:20:35.903093 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10727 23:20:35.903186
10728 23:20:35.932282 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10729 23:20:35.932406
10730 23:20:36.219831 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10731 23:20:36.220004
10732 23:20:36.244220 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10733 23:20:36.244348
10734 23:20:36.265274 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10735 23:20:36.265384
10736 23:20:36.491285 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10737 23:20:36.491453
10738 23:20:37.170236 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10739 23:20:37.170406
10740 23:20:37.232675 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10741 23:20:37.232862
10742 23:20:37.337916 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10743 23:20:37.338063
10744 23:20:37.452051 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10745 23:20:37.452201
10746 23:20:37.468594 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10747 23:20:37.468702
10748 23:20:37.487562 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10749 23:20:37.487673
10750 23:20:37.540381 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10751 23:20:37.540549
10752 23:20:37.568018 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10753 23:20:37.568168
10754 23:20:37.745672 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10755 23:20:37.745826
10756 23:20:37.793237 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10757 23:20:37.793386
10758 23:20:37.887337 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10759 23:20:37.887487
10760 23:20:38.123113 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10761 23:20:38.123252
10762 23:20:38.197939 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10763 23:20:38.198083
10764 23:20:38.215515 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10765 23:20:38.215612
10766 23:20:38.269420 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10767 23:20:38.269562
10768 23:20:38.363576 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10769 23:20:38.363712
10770 23:20:38.383350 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10771 23:20:38.383503
10772 23:20:38.404931 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10773 23:20:38.405035
10774 23:20:38.476457 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10775 23:20:38.476594
10776 23:20:38.497471 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10777 23:20:38.497572
10778 23:20:38.516728 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10779 23:20:38.516829
10780 23:20:38.573341 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10781 23:20:38.573479
10782 23:20:38.596275 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10783 23:20:38.596394
10784 23:20:38.616684 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10785 23:20:38.616783
10786 23:20:38.642227 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Sw<46>[ 25.168271] systemd-journald[300]: Time jumped backwards, rotating.
10787 23:20:38.642324 itch Status.
10788 23:20:38.642391
10789 23:20:38.663772 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10790 23:20:38.663880
10791 23:20:38.683461 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10792 23:20:38.683624
10793 23:20:38.703413 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10794 23:20:38.703548
10795 23:20:38.725459 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10796 23:20:38.725576
10797 23:20:39.089611 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10798 23:20:39.089757
10799 23:20:39.107418 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10800 23:20:39.107507
10801 23:20:39.447447 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10802 23:20:39.447621
10803 23:20:39.776609 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10804 23:20:39.776782
10805 23:20:39.794988 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10806 23:20:39.795106
10807 23:20:39.972569 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10808 23:20:39.972746
10809 23:20:39.990678 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10810 23:20:39.990767
10811 23:20:40.011305 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10812 23:20:40.011391
10813 23:20:40.176710 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10814 23:20:40.176852
10815 23:20:40.206184 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10816 23:20:40.206274
10817 23:20:40.266226 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10818 23:20:40.266329
10819 23:20:40.311937 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10820 23:20:40.312035
10821 23:20:40.504064 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10822 23:20:40.504214
10823 23:20:40.556204 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10824 23:20:40.556372
10825 23:20:40.605160 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10826 23:20:40.605312
10827 23:20:40.623576 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10828 23:20:40.623716
10829 23:20:40.639856 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10830 23:20:40.639961
10831 23:20:40.677440 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10832 23:20:40.677586
10833 23:20:40.702559 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10834 23:20:40.702694
10835 23:20:40.731835 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10836 23:20:40.731953
10837 23:20:40.751834 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10838 23:20:40.751938
10839 23:20:40.807282 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
10840 23:20:40.807429
10841 23:20:40.832691 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10842 23:20:40.832815
10843 23:20:40.869174 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10844 23:20:40.869302
10845 23:20:40.956494 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
10846 23:20:40.956644
10847 23:20:41.037141
10848 23:20:41.037287
10849 23:20:41.039885 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10850 23:20:41.039967
10851 23:20:41.042991 debian-bookworm-arm64 login: root (automatic login)
10852 23:20:41.043087
10853 23:20:41.043164
10854 23:20:41.336350 Linux debian-bookworm-arm64 6.1.83-cip18 #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024 aarch64
10855 23:20:41.336499
10856 23:20:41.343419 The programs included with the Debian GNU/Linux system are free software;
10857 23:20:41.350339 the exact distribution terms for each program are described in the
10858 23:20:41.353420 individual files in /usr/share/doc/*/copyright.
10859 23:20:41.353504
10860 23:20:41.359170 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10861 23:20:41.362574 permitted by applicable law.
10862 23:20:42.253029 Matched prompt #10: / #
10864 23:20:42.253538 Setting prompt string to ['/ #']
10865 23:20:42.253711 end: 2.2.5.1 login-action (duration 00:00:29) [common]
10867 23:20:42.254125 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
10868 23:20:42.254295 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
10869 23:20:42.254435 Setting prompt string to ['/ #']
10870 23:20:42.254559 Forcing a shell prompt, looking for ['/ #']
10872 23:20:42.304895 / #
10873 23:20:42.305139 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10874 23:20:42.305281 Waiting using forced prompt support (timeout 00:02:30)
10875 23:20:42.310737
10876 23:20:42.311092 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10877 23:20:42.311253 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
10879 23:20:42.411725 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248407/extract-nfsrootfs-dbda60ix'
10880 23:20:42.417702 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248407/extract-nfsrootfs-dbda60ix'
10882 23:20:42.518421 / # export NFS_SERVER_IP='192.168.201.1'
10883 23:20:42.524546 export NFS_SERVER_IP='192.168.201.1'
10884 23:20:42.524868 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10885 23:20:42.525009 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
10886 23:20:42.525107 end: 2 depthcharge-action (duration 00:01:30) [common]
10887 23:20:42.525261 start: 3 lava-test-retry (timeout 00:07:50) [common]
10888 23:20:42.525458 start: 3.1 lava-test-shell (timeout 00:07:50) [common]
10889 23:20:42.525640 Using namespace: common
10891 23:20:42.626277 / # #
10892 23:20:42.626837 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10893 23:20:42.633396 #
10894 23:20:42.634173 Using /lava-13248407
10896 23:20:42.735205 / # export SHELL=/bin/bash
10897 23:20:42.741377 export SHELL=/bin/bash
10899 23:20:42.843025 / # . /lava-13248407/environment
10900 23:20:42.849924 . /lava-13248407/environment
10902 23:20:42.958061 / # /lava-13248407/bin/lava-test-runner /lava-13248407/0
10903 23:20:42.958640 Test shell timeout: 10s (minimum of the action and connection timeout)
10904 23:20:42.964497 /lava-13248407/bin/lava-test-runner /lava-13248407/0
10905 23:20:43.201867 + export TESTRUN_ID=0_timesync-off
10906 23:20:43.205269 + TESTRUN_ID=0_timesync-off
10907 23:20:43.208255 + cd /lava-13248407/0/tests/0_timesync-off
10908 23:20:43.211692 ++ cat uuid
10909 23:20:43.216066 + UUID=13248407_1.6.2.3.1
10910 23:20:43.216485 + set +x
10911 23:20:43.222390 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13248407_1.6.2.3.1>
10912 23:20:43.223055 Received signal: <STARTRUN> 0_timesync-off 13248407_1.6.2.3.1
10913 23:20:43.223393 Starting test lava.0_timesync-off (13248407_1.6.2.3.1)
10914 23:20:43.223777 Skipping test definition patterns.
10915 23:20:43.226164 + systemctl stop systemd-timesyncd
10916 23:20:43.292711 + set +x
10917 23:20:43.296240 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13248407_1.6.2.3.1>
10918 23:20:43.296530 Received signal: <ENDRUN> 0_timesync-off 13248407_1.6.2.3.1
10919 23:20:43.296658 Ending use of test pattern.
10920 23:20:43.296766 Ending test lava.0_timesync-off (13248407_1.6.2.3.1), duration 0.07
10922 23:20:43.349938 + export TESTRUN_ID=1_kselftest-alsa
10923 23:20:43.352912 + TESTRUN_ID=1_kselftest-alsa
10924 23:20:43.359761 + cd /lava-13248407/0/tests/1_kselftest-alsa
10925 23:20:43.359847 ++ cat uuid
10926 23:20:43.362532 + UUID=13248407_1.6.2.3.5
10927 23:20:43.362616 + set +x
10928 23:20:43.367693 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 13248407_1.6.2.3.5>
10929 23:20:43.367951 Received signal: <STARTRUN> 1_kselftest-alsa 13248407_1.6.2.3.5
10930 23:20:43.368024 Starting test lava.1_kselftest-alsa (13248407_1.6.2.3.5)
10931 23:20:43.368106 Skipping test definition patterns.
10932 23:20:43.370631 + cd ./automated/linux/kselftest/
10933 23:20:43.395715 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10934 23:20:43.421207 INFO: install_deps skipped
10935 23:20:43.919684 --2024-04-03 23:20:43-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10936 23:20:43.926067 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10937 23:20:44.055999 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10938 23:20:44.184470 HTTP request sent, awaiting response... 200 OK
10939 23:20:44.187461 Length: 1651420 (1.6M) [application/octet-stream]
10940 23:20:44.190759 Saving to: 'kselftest_armhf.tar.gz'
10941 23:20:44.190846
10942 23:20:44.190911
10943 23:20:44.442177 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
10944 23:20:44.700108 kselftest_armhf.tar 3%[ ] 49.22K 191KB/s
10945 23:20:45.034210 kselftest_armhf.tar 13%[=> ] 218.91K 425KB/s
10946 23:20:45.341933 kselftest_armhf.tar 50%[=========> ] 814.23K 958KB/s
10947 23:20:45.470513 kselftest_armhf.tar 88%[================> ] 1.39M 1.20MB/s
10948 23:20:45.476766 kselftest_armhf.tar 100%[===================>] 1.57M 1.22MB/s in 1.3s
10949 23:20:45.476855
10950 23:20:45.622527 2024-04-03 23:20:45 (1.22 MB/s) - 'kselftest_armhf.tar.gz' saved [1651420/1651420]
10951 23:20:45.622676
10952 23:20:49.520264 skiplist:
10953 23:20:49.523571 ========================================
10954 23:20:49.526697 ========================================
10955 23:20:49.570569 alsa:mixer-test
10956 23:20:49.590327 ============== Tests to run ===============
10957 23:20:49.590419 alsa:mixer-test
10958 23:20:49.593584 ===========End Tests to run ===============
10959 23:20:49.597185 shardfile-alsa pass
10960 23:20:49.692200 <12>[ 36.223485] kselftest: Running tests in alsa
10961 23:20:49.701660 TAP version 13
10962 23:20:49.714240 1..1
10963 23:20:49.728154 # selftests: alsa: mixer-test
10964 23:20:50.236813 # TAP version 13
10965 23:20:50.236966 # 1..0
10966 23:20:50.243680 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
10967 23:20:50.246830 ok 1 selftests: alsa: mixer-test
10968 23:20:51.755194 alsa_mixer-test pass
10969 23:20:51.833376 + ../../utils/send-to-lava.sh ./output/result.txt
10970 23:20:51.883430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
10971 23:20:51.883720 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
10973 23:20:51.920050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10974 23:20:51.920204 + set +x
10975 23:20:51.920481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10977 23:20:51.927062 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 13248407_1.6.2.3.5>
10978 23:20:51.927314 Received signal: <ENDRUN> 1_kselftest-alsa 13248407_1.6.2.3.5
10979 23:20:51.927387 Ending use of test pattern.
10980 23:20:51.927448 Ending test lava.1_kselftest-alsa (13248407_1.6.2.3.5), duration 8.56
10982 23:20:51.930048 <LAVA_TEST_RUNNER EXIT>
10983 23:20:51.930298 ok: lava_test_shell seems to have completed
10984 23:20:51.930407 alsa_mixer-test: pass
shardfile-alsa: pass
10985 23:20:51.930495 end: 3.1 lava-test-shell (duration 00:00:09) [common]
10986 23:20:51.930578 end: 3 lava-test-retry (duration 00:00:09) [common]
10987 23:20:51.930663 start: 4 finalize (timeout 00:07:41) [common]
10988 23:20:51.930754 start: 4.1 power-off (timeout 00:00:30) [common]
10989 23:20:51.930904 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10990 23:20:52.002324 >> Command sent successfully.
10991 23:20:52.004860 Returned 0 in 0 seconds
10992 23:20:52.105231 end: 4.1 power-off (duration 00:00:00) [common]
10994 23:20:52.105523 start: 4.2 read-feedback (timeout 00:07:41) [common]
10995 23:20:52.105773 Listened to connection for namespace 'common' for up to 1s
10996 23:20:53.106737 Finalising connection for namespace 'common'
10997 23:20:53.106911 Disconnecting from shell: Finalise
10998 23:20:53.106988 / #
10999 23:20:53.207307 end: 4.2 read-feedback (duration 00:00:01) [common]
11000 23:20:53.207489 end: 4 finalize (duration 00:00:01) [common]
11001 23:20:53.207612 Cleaning after the job
11002 23:20:53.207705 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/ramdisk
11003 23:20:53.210572 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/kernel
11004 23:20:53.224912 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/dtb
11005 23:20:53.225141 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/nfsrootfs
11006 23:20:53.309470 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248407/tftp-deploy-a33avefh/modules
11007 23:20:53.317026 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248407
11008 23:20:53.962019 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248407
11009 23:20:53.962203 Job finished correctly