Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
1 23:17:35.248944 lava-dispatcher, installed at version: 2024.01
2 23:17:35.249155 start: 0 validate
3 23:17:35.249285 Start time: 2024-04-03 23:17:35.249276+00:00 (UTC)
4 23:17:35.249407 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:17:35.249542 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:17:35.508008 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:17:35.508171 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:17:53.756136 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:17:53.756297 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:17:54.024186 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:17:54.024360 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:17:54.554000 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:17:54.554167 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:17:57.059507 validate duration: 21.81
16 23:17:57.059921 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:17:57.060084 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:17:57.060232 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:17:57.060437 Not decompressing ramdisk as can be used compressed.
20 23:17:57.060581 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:17:57.060696 saving as /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/ramdisk/initrd.cpio.gz
22 23:17:57.060822 total size: 5628169 (5 MB)
23 23:17:57.327631 progress 0 % (0 MB)
24 23:17:57.329384 progress 5 % (0 MB)
25 23:17:57.331023 progress 10 % (0 MB)
26 23:17:57.332544 progress 15 % (0 MB)
27 23:17:57.334407 progress 20 % (1 MB)
28 23:17:57.336034 progress 25 % (1 MB)
29 23:17:57.337760 progress 30 % (1 MB)
30 23:17:57.339546 progress 35 % (1 MB)
31 23:17:57.341315 progress 40 % (2 MB)
32 23:17:57.342894 progress 45 % (2 MB)
33 23:17:57.344345 progress 50 % (2 MB)
34 23:17:57.345990 progress 55 % (2 MB)
35 23:17:57.347668 progress 60 % (3 MB)
36 23:17:57.349185 progress 65 % (3 MB)
37 23:17:57.350847 progress 70 % (3 MB)
38 23:17:57.352351 progress 75 % (4 MB)
39 23:17:57.354128 progress 80 % (4 MB)
40 23:17:57.355574 progress 85 % (4 MB)
41 23:17:57.357346 progress 90 % (4 MB)
42 23:17:57.359056 progress 95 % (5 MB)
43 23:17:57.360721 progress 100 % (5 MB)
44 23:17:57.361010 5 MB downloaded in 0.30 s (17.88 MB/s)
45 23:17:57.361172 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:17:57.361457 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:17:57.361547 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:17:57.361634 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:17:57.361770 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:17:57.361840 saving as /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/kernel/Image
52 23:17:57.361906 total size: 54286848 (51 MB)
53 23:17:57.361986 No compression specified
54 23:17:57.363091 progress 0 % (0 MB)
55 23:17:57.379857 progress 5 % (2 MB)
56 23:17:57.401677 progress 10 % (5 MB)
57 23:17:57.420477 progress 15 % (7 MB)
58 23:17:57.440014 progress 20 % (10 MB)
59 23:17:57.461722 progress 25 % (12 MB)
60 23:17:57.483496 progress 30 % (15 MB)
61 23:17:57.505080 progress 35 % (18 MB)
62 23:17:57.522286 progress 40 % (20 MB)
63 23:17:57.539027 progress 45 % (23 MB)
64 23:17:57.560643 progress 50 % (25 MB)
65 23:17:57.582642 progress 55 % (28 MB)
66 23:17:57.597952 progress 60 % (31 MB)
67 23:17:57.617059 progress 65 % (33 MB)
68 23:17:57.639271 progress 70 % (36 MB)
69 23:17:57.660823 progress 75 % (38 MB)
70 23:17:57.681820 progress 80 % (41 MB)
71 23:17:57.696165 progress 85 % (44 MB)
72 23:17:57.711125 progress 90 % (46 MB)
73 23:17:57.725242 progress 95 % (49 MB)
74 23:17:57.743493 progress 100 % (51 MB)
75 23:17:57.743899 51 MB downloaded in 0.38 s (135.53 MB/s)
76 23:17:57.744158 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:17:57.744591 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:17:57.744739 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:17:57.744892 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:17:57.745114 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:17:57.745233 saving as /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/dtb/mt8192-asurada-spherion-r0.dtb
83 23:17:57.745351 total size: 47230 (0 MB)
84 23:17:57.745468 No compression specified
85 23:17:57.747237 progress 69 % (0 MB)
86 23:17:57.747650 progress 100 % (0 MB)
87 23:17:57.747897 0 MB downloaded in 0.00 s (17.72 MB/s)
88 23:17:57.748113 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:17:57.748516 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:17:57.748663 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:17:57.748812 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:17:57.749003 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:17:57.749125 saving as /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/nfsrootfs/full.rootfs.tar
95 23:17:57.749240 total size: 120894716 (115 MB)
96 23:17:57.749356 Using unxz to decompress xz
97 23:17:57.755015 progress 0 % (0 MB)
98 23:17:58.139403 progress 5 % (5 MB)
99 23:17:58.535740 progress 10 % (11 MB)
100 23:17:58.909468 progress 15 % (17 MB)
101 23:17:59.312558 progress 20 % (23 MB)
102 23:17:59.644048 progress 25 % (28 MB)
103 23:18:00.066883 progress 30 % (34 MB)
104 23:18:00.473446 progress 35 % (40 MB)
105 23:18:00.656609 progress 40 % (46 MB)
106 23:18:00.851861 progress 45 % (51 MB)
107 23:18:01.220800 progress 50 % (57 MB)
108 23:18:01.663471 progress 55 % (63 MB)
109 23:18:02.086984 progress 60 % (69 MB)
110 23:18:02.471526 progress 65 % (74 MB)
111 23:18:02.856099 progress 70 % (80 MB)
112 23:18:03.251751 progress 75 % (86 MB)
113 23:18:03.711504 progress 80 % (92 MB)
114 23:18:04.134324 progress 85 % (98 MB)
115 23:18:04.564375 progress 90 % (103 MB)
116 23:18:04.959395 progress 95 % (109 MB)
117 23:18:05.357208 progress 100 % (115 MB)
118 23:18:05.363038 115 MB downloaded in 7.61 s (15.14 MB/s)
119 23:18:05.363433 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:18:05.363885 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:18:05.364030 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:18:05.364172 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:18:05.364399 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:18:05.364515 saving as /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/modules/modules.tar
126 23:18:05.364625 total size: 8629908 (8 MB)
127 23:18:05.364736 Using unxz to decompress xz
128 23:18:05.626405 progress 0 % (0 MB)
129 23:18:05.646392 progress 5 % (0 MB)
130 23:18:05.672038 progress 10 % (0 MB)
131 23:18:05.697073 progress 15 % (1 MB)
132 23:18:05.721244 progress 20 % (1 MB)
133 23:18:05.747790 progress 25 % (2 MB)
134 23:18:05.774744 progress 30 % (2 MB)
135 23:18:05.803514 progress 35 % (2 MB)
136 23:18:05.830103 progress 40 % (3 MB)
137 23:18:05.855273 progress 45 % (3 MB)
138 23:18:05.881026 progress 50 % (4 MB)
139 23:18:05.906656 progress 55 % (4 MB)
140 23:18:05.935538 progress 60 % (4 MB)
141 23:18:05.961565 progress 65 % (5 MB)
142 23:18:05.987824 progress 70 % (5 MB)
143 23:18:06.013049 progress 75 % (6 MB)
144 23:18:06.039627 progress 80 % (6 MB)
145 23:18:06.066541 progress 85 % (7 MB)
146 23:18:06.095352 progress 90 % (7 MB)
147 23:18:06.126088 progress 95 % (7 MB)
148 23:18:06.153064 progress 100 % (8 MB)
149 23:18:06.158643 8 MB downloaded in 0.79 s (10.37 MB/s)
150 23:18:06.159016 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:18:06.159510 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:18:06.159664 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:18:06.159821 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:18:10.631653 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13248440/extract-nfsrootfs-5ayrqzms
156 23:18:10.631878 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:18:10.631989 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 23:18:10.632172 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx
159 23:18:10.632307 makedir: /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin
160 23:18:10.632411 makedir: /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/tests
161 23:18:10.632511 makedir: /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/results
162 23:18:10.632616 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-add-keys
163 23:18:10.632765 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-add-sources
164 23:18:10.632898 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-background-process-start
165 23:18:10.633030 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-background-process-stop
166 23:18:10.633161 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-common-functions
167 23:18:10.633290 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-echo-ipv4
168 23:18:10.633420 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-install-packages
169 23:18:10.633551 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-installed-packages
170 23:18:10.633679 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-os-build
171 23:18:10.633807 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-probe-channel
172 23:18:10.633935 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-probe-ip
173 23:18:10.634063 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-target-ip
174 23:18:10.634191 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-target-mac
175 23:18:10.634317 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-target-storage
176 23:18:10.634447 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-test-case
177 23:18:10.634577 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-test-event
178 23:18:10.634703 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-test-feedback
179 23:18:10.634830 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-test-raise
180 23:18:10.634957 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-test-reference
181 23:18:10.635084 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-test-runner
182 23:18:10.635212 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-test-set
183 23:18:10.635338 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-test-shell
184 23:18:10.635481 Updating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-add-keys (debian)
185 23:18:10.635639 Updating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-add-sources (debian)
186 23:18:10.635786 Updating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-install-packages (debian)
187 23:18:10.635928 Updating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-installed-packages (debian)
188 23:18:10.636069 Updating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/bin/lava-os-build (debian)
189 23:18:10.636193 Creating /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/environment
190 23:18:10.636292 LAVA metadata
191 23:18:10.636364 - LAVA_JOB_ID=13248440
192 23:18:10.636428 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:18:10.636535 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 23:18:10.636602 skipped lava-vland-overlay
195 23:18:10.636677 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:18:10.636757 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 23:18:10.636817 skipped lava-multinode-overlay
198 23:18:10.636889 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:18:10.636982 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 23:18:10.637061 Loading test definitions
201 23:18:10.637153 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 23:18:10.637227 Using /lava-13248440 at stage 0
203 23:18:10.637517 uuid=13248440_1.6.2.3.1 testdef=None
204 23:18:10.637607 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:18:10.637692 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 23:18:10.638162 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:18:10.638387 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 23:18:10.638963 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:18:10.639198 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 23:18:10.639951 runner path: /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/0/tests/0_timesync-off test_uuid 13248440_1.6.2.3.1
213 23:18:10.640118 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:18:10.640350 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 23:18:10.640423 Using /lava-13248440 at stage 0
217 23:18:10.640522 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:18:10.640610 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/0/tests/1_kselftest-arm64'
219 23:18:14.665170 Running '/usr/bin/git checkout kernelci.org
220 23:18:14.818290 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 23:18:14.819327 uuid=13248440_1.6.2.3.5 testdef=None
222 23:18:14.819567 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 23:18:14.819941 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 23:18:14.821175 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:18:14.821549 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 23:18:14.823505 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:18:14.823947 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 23:18:14.825771 runner path: /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/0/tests/1_kselftest-arm64 test_uuid 13248440_1.6.2.3.5
232 23:18:14.825933 BOARD='mt8192-asurada-spherion-r0'
233 23:18:14.826051 BRANCH='cip'
234 23:18:14.826158 SKIPFILE='/dev/null'
235 23:18:14.826270 SKIP_INSTALL='True'
236 23:18:14.826384 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:18:14.826497 TST_CASENAME=''
238 23:18:14.826609 TST_CMDFILES='arm64'
239 23:18:14.826854 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:18:14.827274 Creating lava-test-runner.conf files
242 23:18:14.827402 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248440/lava-overlay-vvpp1dnx/lava-13248440/0 for stage 0
243 23:18:14.827569 - 0_timesync-off
244 23:18:14.827696 - 1_kselftest-arm64
245 23:18:14.827870 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 23:18:14.828028 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 23:18:22.656633 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:18:22.656816 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 23:18:22.656952 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:18:22.657085 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 23:18:22.657209 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 23:18:22.840020 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:18:22.840425 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 23:18:22.840579 extracting modules file /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248440/extract-nfsrootfs-5ayrqzms
255 23:18:23.185078 extracting modules file /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248440/extract-overlay-ramdisk-450tugcy/ramdisk
256 23:18:23.478003 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 23:18:23.478214 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 23:18:23.478320 [common] Applying overlay to NFS
259 23:18:23.478397 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248440/compress-overlay-p5xbr6b7/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248440/extract-nfsrootfs-5ayrqzms
260 23:18:24.484009 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:18:24.484200 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 23:18:24.484311 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:18:24.484404 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 23:18:24.484485 Building ramdisk /var/lib/lava/dispatcher/tmp/13248440/extract-overlay-ramdisk-450tugcy/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248440/extract-overlay-ramdisk-450tugcy/ramdisk
265 23:18:24.856674 >> 130593 blocks
266 23:18:26.941865 rename /var/lib/lava/dispatcher/tmp/13248440/extract-overlay-ramdisk-450tugcy/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/ramdisk/ramdisk.cpio.gz
267 23:18:26.942326 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:18:26.942451 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 23:18:26.942555 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 23:18:26.942667 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/kernel/Image'
271 23:18:41.075091 Returned 0 in 14 seconds
272 23:18:41.175839 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/kernel/image.itb
273 23:18:41.583857 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:18:41.584278 output: Created: Thu Apr 4 00:18:41 2024
275 23:18:41.584391 output: Image 0 (kernel-1)
276 23:18:41.584493 output: Description:
277 23:18:41.584588 output: Created: Thu Apr 4 00:18:41 2024
278 23:18:41.584680 output: Type: Kernel Image
279 23:18:41.584771 output: Compression: lzma compressed
280 23:18:41.584863 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
281 23:18:41.584952 output: Architecture: AArch64
282 23:18:41.585039 output: OS: Linux
283 23:18:41.585124 output: Load Address: 0x00000000
284 23:18:41.585212 output: Entry Point: 0x00000000
285 23:18:41.585304 output: Hash algo: crc32
286 23:18:41.585393 output: Hash value: d7c9dcc1
287 23:18:41.585480 output: Image 1 (fdt-1)
288 23:18:41.585568 output: Description: mt8192-asurada-spherion-r0
289 23:18:41.585653 output: Created: Thu Apr 4 00:18:41 2024
290 23:18:41.585738 output: Type: Flat Device Tree
291 23:18:41.585823 output: Compression: uncompressed
292 23:18:41.585907 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 23:18:41.585992 output: Architecture: AArch64
294 23:18:41.586075 output: Hash algo: crc32
295 23:18:41.586159 output: Hash value: 4bf0d1ac
296 23:18:41.586243 output: Image 2 (ramdisk-1)
297 23:18:41.586327 output: Description: unavailable
298 23:18:41.586410 output: Created: Thu Apr 4 00:18:41 2024
299 23:18:41.586495 output: Type: RAMDisk Image
300 23:18:41.586579 output: Compression: Unknown Compression
301 23:18:41.586662 output: Data Size: 18767102 Bytes = 18327.25 KiB = 17.90 MiB
302 23:18:41.586747 output: Architecture: AArch64
303 23:18:41.586830 output: OS: Linux
304 23:18:41.586913 output: Load Address: unavailable
305 23:18:41.587008 output: Entry Point: unavailable
306 23:18:41.587094 output: Hash algo: crc32
307 23:18:41.587177 output: Hash value: 8ad121f8
308 23:18:41.587261 output: Default Configuration: 'conf-1'
309 23:18:41.587345 output: Configuration 0 (conf-1)
310 23:18:41.587418 output: Description: mt8192-asurada-spherion-r0
311 23:18:41.587474 output: Kernel: kernel-1
312 23:18:41.587529 output: Init Ramdisk: ramdisk-1
313 23:18:41.587583 output: FDT: fdt-1
314 23:18:41.587637 output: Loadables: kernel-1
315 23:18:41.587691 output:
316 23:18:41.587908 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 23:18:41.588011 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 23:18:41.588118 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 23:18:41.588217 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:15) [common]
320 23:18:41.588300 No LXC device requested
321 23:18:41.588384 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:18:41.588470 start: 1.8 deploy-device-env (timeout 00:09:15) [common]
323 23:18:41.588549 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:18:41.588626 Checking files for TFTP limit of 4294967296 bytes.
325 23:18:41.589139 end: 1 tftp-deploy (duration 00:00:45) [common]
326 23:18:41.589257 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:18:41.589363 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:18:41.589503 substitutions:
329 23:18:41.589574 - {DTB}: 13248440/tftp-deploy-tcaniien/dtb/mt8192-asurada-spherion-r0.dtb
330 23:18:41.589642 - {INITRD}: 13248440/tftp-deploy-tcaniien/ramdisk/ramdisk.cpio.gz
331 23:18:41.589702 - {KERNEL}: 13248440/tftp-deploy-tcaniien/kernel/Image
332 23:18:41.589761 - {LAVA_MAC}: None
333 23:18:41.589818 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13248440/extract-nfsrootfs-5ayrqzms
334 23:18:41.589875 - {NFS_SERVER_IP}: 192.168.201.1
335 23:18:41.589931 - {PRESEED_CONFIG}: None
336 23:18:41.589986 - {PRESEED_LOCAL}: None
337 23:18:41.590041 - {RAMDISK}: 13248440/tftp-deploy-tcaniien/ramdisk/ramdisk.cpio.gz
338 23:18:41.590097 - {ROOT_PART}: None
339 23:18:41.590152 - {ROOT}: None
340 23:18:41.590207 - {SERVER_IP}: 192.168.201.1
341 23:18:41.590262 - {TEE}: None
342 23:18:41.590316 Parsed boot commands:
343 23:18:41.590370 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:18:41.590559 Parsed boot commands: tftpboot 192.168.201.1 13248440/tftp-deploy-tcaniien/kernel/image.itb 13248440/tftp-deploy-tcaniien/kernel/cmdline
345 23:18:41.590650 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:18:41.590748 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:18:41.590852 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:18:41.590941 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:18:41.591019 Not connected, no need to disconnect.
350 23:18:41.591094 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:18:41.591179 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:18:41.591249 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 23:18:41.596014 Setting prompt string to ['lava-test: # ']
354 23:18:41.596570 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:18:41.596756 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:18:41.596914 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:18:41.597070 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:18:41.597436 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 23:18:46.735122 >> Command sent successfully.
360 23:18:46.737936 Returned 0 in 5 seconds
361 23:18:46.838344 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:18:46.838688 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:18:46.838789 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:18:46.838874 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:18:46.838939 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:18:46.839006 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:18:46.839272 [Enter `^Ec?' for help]
369 23:18:47.014723
370 23:18:47.014954
371 23:18:47.015081 F0: 102B 0000
372 23:18:47.015203
373 23:18:47.015319 F3: 1001 0000 [0200]
374 23:18:47.015442
375 23:18:47.018025 F3: 1001 0000
376 23:18:47.018152
377 23:18:47.018271 F7: 102D 0000
378 23:18:47.018386
379 23:18:47.018499 F1: 0000 0000
380 23:18:47.022226
381 23:18:47.022355 V0: 0000 0000 [0001]
382 23:18:47.022480
383 23:18:47.022593 00: 0007 8000
384 23:18:47.022709
385 23:18:47.025333 01: 0000 0000
386 23:18:47.025463
387 23:18:47.025581 BP: 0C00 0209 [0000]
388 23:18:47.025697
389 23:18:47.029859 G0: 1182 0000
390 23:18:47.029985
391 23:18:47.030108 EC: 0000 0021 [4000]
392 23:18:47.030222
393 23:18:47.033220 S7: 0000 0000 [0000]
394 23:18:47.033348
395 23:18:47.033466 CC: 0000 0000 [0001]
396 23:18:47.033582
397 23:18:47.036250 T0: 0000 0040 [010F]
398 23:18:47.036379
399 23:18:47.036472 Jump to BL
400 23:18:47.036538
401 23:18:47.061378
402 23:18:47.061502
403 23:18:47.061574
404 23:18:47.068181 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:18:47.071656 ARM64: Exception handlers installed.
406 23:18:47.075987 ARM64: Testing exception
407 23:18:47.079201 ARM64: Done test exception
408 23:18:47.086986 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:18:47.094264 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:18:47.101294 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:18:47.112336 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:18:47.118509 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:18:47.129138 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:18:47.139728 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:18:47.146208 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:18:47.164112 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:18:47.167430 WDT: Last reset was cold boot
418 23:18:47.170960 SPI1(PAD0) initialized at 2873684 Hz
419 23:18:47.174216 SPI5(PAD0) initialized at 992727 Hz
420 23:18:47.177345 VBOOT: Loading verstage.
421 23:18:47.184522 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:18:47.187430 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:18:47.190700 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:18:47.194298 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:18:47.201608 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:18:47.208273 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:18:47.219050 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 23:18:47.219138
429 23:18:47.219206
430 23:18:47.229248 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:18:47.232459 ARM64: Exception handlers installed.
432 23:18:47.235774 ARM64: Testing exception
433 23:18:47.235859 ARM64: Done test exception
434 23:18:47.242976 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:18:47.246933 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:18:47.260184 Probing TPM: . done!
437 23:18:47.260321 TPM ready after 0 ms
438 23:18:47.267389 Connected to device vid:did:rid of 1ae0:0028:00
439 23:18:47.274227 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 23:18:47.332319 Initialized TPM device CR50 revision 0
441 23:18:47.344350 tlcl_send_startup: Startup return code is 0
442 23:18:47.344440 TPM: setup succeeded
443 23:18:47.355493 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:18:47.364352 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:18:47.376288 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:18:47.386753 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:18:47.389806 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:18:47.394999 in-header: 03 07 00 00 08 00 00 00
449 23:18:47.399285 in-data: aa e4 47 04 13 02 00 00
450 23:18:47.402432 Chrome EC: UHEPI supported
451 23:18:47.409680 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:18:47.413913 in-header: 03 95 00 00 08 00 00 00
453 23:18:47.417244 in-data: 18 20 20 08 00 00 00 00
454 23:18:47.417352 Phase 1
455 23:18:47.421107 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:18:47.428514 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:18:47.431639 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:18:47.435730 Recovery requested (1009000e)
459 23:18:47.444103 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:18:47.450091 tlcl_extend: response is 0
461 23:18:47.459135 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:18:47.464441 tlcl_extend: response is 0
463 23:18:47.471658 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:18:47.491778 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 23:18:47.497762 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:18:47.497892
467 23:18:47.498006
468 23:18:47.507497 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:18:47.511068 ARM64: Exception handlers installed.
470 23:18:47.514980 ARM64: Testing exception
471 23:18:47.515066 ARM64: Done test exception
472 23:18:47.537055 pmic_efuse_setting: Set efuses in 11 msecs
473 23:18:47.540057 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:18:47.546877 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:18:47.549982 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:18:47.557438 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:18:47.560374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:18:47.564394 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:18:47.571201 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:18:47.574851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:18:47.578939 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:18:47.582557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:18:47.589864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:18:47.593924 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:18:47.597100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:18:47.601008 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:18:47.608726 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:18:47.616518 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:18:47.619895 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:18:47.627340 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:18:47.631036 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:18:47.638298 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:18:47.641714 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:18:47.649106 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:18:47.652838 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:18:47.660068 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:18:47.663986 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:18:47.670821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:18:47.674667 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:18:47.682034 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:18:47.685648 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:18:47.692652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:18:47.696532 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:18:47.699999 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:18:47.707538 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:18:47.711076 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:18:47.714502 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:18:47.722187 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:18:47.725740 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:18:47.729665 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:18:47.737629 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:18:47.740434 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:18:47.744079 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:18:47.748026 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:18:47.755356 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:18:47.758576 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:18:47.762262 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:18:47.766300 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:18:47.770143 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:18:47.773455 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:18:47.780921 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:18:47.785217 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:18:47.788353 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:18:47.792191 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:18:47.799767 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:18:47.806670 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:18:47.814046 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:18:47.821755 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:18:47.828897 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:18:47.832763 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:18:47.836307 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:18:47.844528 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:18:47.848028 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x21
534 23:18:47.855487 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:18:47.858641 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 23:18:47.865393 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:18:47.874356 [RTC]rtc_get_frequency_meter,154: input=15, output=852
538 23:18:47.883625 [RTC]rtc_get_frequency_meter,154: input=7, output=724
539 23:18:47.893451 [RTC]rtc_get_frequency_meter,154: input=11, output=788
540 23:18:47.902837 [RTC]rtc_get_frequency_meter,154: input=13, output=819
541 23:18:47.912028 [RTC]rtc_get_frequency_meter,154: input=12, output=804
542 23:18:47.922063 [RTC]rtc_get_frequency_meter,154: input=11, output=788
543 23:18:47.931830 [RTC]rtc_get_frequency_meter,154: input=12, output=805
544 23:18:47.935591 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 23:18:47.939117 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 23:18:47.942608 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:18:47.950131 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 23:18:47.953581 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:18:47.957518 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 23:18:47.961369 ADC[4]: Raw value=905172 ID=7
551 23:18:47.961488 ADC[3]: Raw value=213916 ID=1
552 23:18:47.964707 RAM Code: 0x71
553 23:18:47.968070 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:18:47.975559 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:18:47.982889 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:18:47.990197 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:18:47.994022 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:18:47.997960 in-header: 03 07 00 00 08 00 00 00
559 23:18:47.998049 in-data: aa e4 47 04 13 02 00 00
560 23:18:48.002085 Chrome EC: UHEPI supported
561 23:18:48.009028 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:18:48.012734 in-header: 03 95 00 00 08 00 00 00
563 23:18:48.016238 in-data: 18 20 20 08 00 00 00 00
564 23:18:48.020068 MRC: failed to locate region type 0.
565 23:18:48.023553 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:18:48.027600 DRAM-K: Running full calibration
567 23:18:48.034913 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:18:48.035029 header.status = 0x0
569 23:18:48.038646 header.version = 0x6 (expected: 0x6)
570 23:18:48.042186 header.size = 0xd00 (expected: 0xd00)
571 23:18:48.045982 header.flags = 0x0
572 23:18:48.049482 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:18:48.069169 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 23:18:48.076503 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:18:48.080333 dram_init: ddr_geometry: 2
576 23:18:48.080421 [EMI] MDL number = 2
577 23:18:48.084217 [EMI] Get MDL freq = 0
578 23:18:48.084303 dram_init: ddr_type: 0
579 23:18:48.087721 is_discrete_lpddr4: 1
580 23:18:48.091116 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:18:48.091229
582 23:18:48.091336
583 23:18:48.091422 [Bian_co] ETT version 0.0.0.1
584 23:18:48.098848 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:18:48.098936
586 23:18:48.102281 dramc_set_vcore_voltage set vcore to 650000
587 23:18:48.102392 Read voltage for 800, 4
588 23:18:48.106313 Vio18 = 0
589 23:18:48.106426 Vcore = 650000
590 23:18:48.106525 Vdram = 0
591 23:18:48.106619 Vddq = 0
592 23:18:48.109413 Vmddr = 0
593 23:18:48.109525 dram_init: config_dvfs: 1
594 23:18:48.116680 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:18:48.119784 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:18:48.123265 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 23:18:48.129746 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 23:18:48.133671 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 23:18:48.136527 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 23:18:48.140785 MEM_TYPE=3, freq_sel=18
601 23:18:48.140909 sv_algorithm_assistance_LP4_1600
602 23:18:48.144242 ============ PULL DRAM RESETB DOWN ============
603 23:18:48.152233 ========== PULL DRAM RESETB DOWN end =========
604 23:18:48.155620 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:18:48.159109 ===================================
606 23:18:48.159216 LPDDR4 DRAM CONFIGURATION
607 23:18:48.161940 ===================================
608 23:18:48.165283 EX_ROW_EN[0] = 0x0
609 23:18:48.169364 EX_ROW_EN[1] = 0x0
610 23:18:48.169476 LP4Y_EN = 0x0
611 23:18:48.172579 WORK_FSP = 0x0
612 23:18:48.172692 WL = 0x2
613 23:18:48.176008 RL = 0x2
614 23:18:48.176123 BL = 0x2
615 23:18:48.179823 RPST = 0x0
616 23:18:48.179907 RD_PRE = 0x0
617 23:18:48.179992 WR_PRE = 0x1
618 23:18:48.182812 WR_PST = 0x0
619 23:18:48.186117 DBI_WR = 0x0
620 23:18:48.186234 DBI_RD = 0x0
621 23:18:48.189285 OTF = 0x1
622 23:18:48.192526 ===================================
623 23:18:48.195677 ===================================
624 23:18:48.195754 ANA top config
625 23:18:48.199649 ===================================
626 23:18:48.203058 DLL_ASYNC_EN = 0
627 23:18:48.206308 ALL_SLAVE_EN = 1
628 23:18:48.206385 NEW_RANK_MODE = 1
629 23:18:48.209622 DLL_IDLE_MODE = 1
630 23:18:48.212360 LP45_APHY_COMB_EN = 1
631 23:18:48.215753 TX_ODT_DIS = 1
632 23:18:48.215839 NEW_8X_MODE = 1
633 23:18:48.219232 ===================================
634 23:18:48.222721 ===================================
635 23:18:48.225664 data_rate = 1600
636 23:18:48.229227 CKR = 1
637 23:18:48.232338 DQ_P2S_RATIO = 8
638 23:18:48.235800 ===================================
639 23:18:48.239584 CA_P2S_RATIO = 8
640 23:18:48.242961 DQ_CA_OPEN = 0
641 23:18:48.243050 DQ_SEMI_OPEN = 0
642 23:18:48.246723 CA_SEMI_OPEN = 0
643 23:18:48.249533 CA_FULL_RATE = 0
644 23:18:48.253009 DQ_CKDIV4_EN = 1
645 23:18:48.256147 CA_CKDIV4_EN = 1
646 23:18:48.256260 CA_PREDIV_EN = 0
647 23:18:48.259481 PH8_DLY = 0
648 23:18:48.262664 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:18:48.266398 DQ_AAMCK_DIV = 4
650 23:18:48.269288 CA_AAMCK_DIV = 4
651 23:18:48.272596 CA_ADMCK_DIV = 4
652 23:18:48.272683 DQ_TRACK_CA_EN = 0
653 23:18:48.276309 CA_PICK = 800
654 23:18:48.279859 CA_MCKIO = 800
655 23:18:48.283101 MCKIO_SEMI = 0
656 23:18:48.286475 PLL_FREQ = 3068
657 23:18:48.290606 DQ_UI_PI_RATIO = 32
658 23:18:48.290691 CA_UI_PI_RATIO = 0
659 23:18:48.294137 ===================================
660 23:18:48.297718 ===================================
661 23:18:48.301260 memory_type:LPDDR4
662 23:18:48.301349 GP_NUM : 10
663 23:18:48.305249 SRAM_EN : 1
664 23:18:48.305337 MD32_EN : 0
665 23:18:48.308856 ===================================
666 23:18:48.312381 [ANA_INIT] >>>>>>>>>>>>>>
667 23:18:48.316227 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:18:48.319982 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:18:48.324379 ===================================
670 23:18:48.324465 data_rate = 1600,PCW = 0X7600
671 23:18:48.327306 ===================================
672 23:18:48.329857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:18:48.336288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:18:48.342970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:18:48.346468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:18:48.350069 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:18:48.353289 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:18:48.356858 [ANA_INIT] flow start
679 23:18:48.359990 [ANA_INIT] PLL >>>>>>>>
680 23:18:48.360075 [ANA_INIT] PLL <<<<<<<<
681 23:18:48.362986 [ANA_INIT] MIDPI >>>>>>>>
682 23:18:48.366175 [ANA_INIT] MIDPI <<<<<<<<
683 23:18:48.366262 [ANA_INIT] DLL >>>>>>>>
684 23:18:48.369843 [ANA_INIT] flow end
685 23:18:48.373233 ============ LP4 DIFF to SE enter ============
686 23:18:48.376255 ============ LP4 DIFF to SE exit ============
687 23:18:48.379848 [ANA_INIT] <<<<<<<<<<<<<
688 23:18:48.383386 [Flow] Enable top DCM control >>>>>
689 23:18:48.386657 [Flow] Enable top DCM control <<<<<
690 23:18:48.390124 Enable DLL master slave shuffle
691 23:18:48.396446 ==============================================================
692 23:18:48.396565 Gating Mode config
693 23:18:48.403106 ==============================================================
694 23:18:48.403215 Config description:
695 23:18:48.412712 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:18:48.419191 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:18:48.425994 SELPH_MODE 0: By rank 1: By Phase
698 23:18:48.429399 ==============================================================
699 23:18:48.432548 GAT_TRACK_EN = 1
700 23:18:48.436592 RX_GATING_MODE = 2
701 23:18:48.439444 RX_GATING_TRACK_MODE = 2
702 23:18:48.442985 SELPH_MODE = 1
703 23:18:48.446012 PICG_EARLY_EN = 1
704 23:18:48.449120 VALID_LAT_VALUE = 1
705 23:18:48.455824 ==============================================================
706 23:18:48.459140 Enter into Gating configuration >>>>
707 23:18:48.462787 Exit from Gating configuration <<<<
708 23:18:48.462902 Enter into DVFS_PRE_config >>>>>
709 23:18:48.476415 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:18:48.479355 Exit from DVFS_PRE_config <<<<<
711 23:18:48.482681 Enter into PICG configuration >>>>
712 23:18:48.486020 Exit from PICG configuration <<<<
713 23:18:48.486099 [RX_INPUT] configuration >>>>>
714 23:18:48.489175 [RX_INPUT] configuration <<<<<
715 23:18:48.495624 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:18:48.502430 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:18:48.505660 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:18:48.511748 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:18:48.518761 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:18:48.524995 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:18:48.528369 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:18:48.531922 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:18:48.538812 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:18:48.541820 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:18:48.545095 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:18:48.552130 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:18:48.555060 ===================================
728 23:18:48.555181 LPDDR4 DRAM CONFIGURATION
729 23:18:48.558413 ===================================
730 23:18:48.561663 EX_ROW_EN[0] = 0x0
731 23:18:48.561772 EX_ROW_EN[1] = 0x0
732 23:18:48.565366 LP4Y_EN = 0x0
733 23:18:48.565500 WORK_FSP = 0x0
734 23:18:48.568546 WL = 0x2
735 23:18:48.568675 RL = 0x2
736 23:18:48.571784 BL = 0x2
737 23:18:48.574930 RPST = 0x0
738 23:18:48.575060 RD_PRE = 0x0
739 23:18:48.578689 WR_PRE = 0x1
740 23:18:48.578803 WR_PST = 0x0
741 23:18:48.581739 DBI_WR = 0x0
742 23:18:48.581857 DBI_RD = 0x0
743 23:18:48.585723 OTF = 0x1
744 23:18:48.588752 ===================================
745 23:18:48.591802 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:18:48.594900 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:18:48.598652 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:18:48.601796 ===================================
749 23:18:48.604924 LPDDR4 DRAM CONFIGURATION
750 23:18:48.608282 ===================================
751 23:18:48.611594 EX_ROW_EN[0] = 0x10
752 23:18:48.611722 EX_ROW_EN[1] = 0x0
753 23:18:48.614843 LP4Y_EN = 0x0
754 23:18:48.614961 WORK_FSP = 0x0
755 23:18:48.618168 WL = 0x2
756 23:18:48.618294 RL = 0x2
757 23:18:48.621770 BL = 0x2
758 23:18:48.621894 RPST = 0x0
759 23:18:48.624962 RD_PRE = 0x0
760 23:18:48.625088 WR_PRE = 0x1
761 23:18:48.628569 WR_PST = 0x0
762 23:18:48.631462 DBI_WR = 0x0
763 23:18:48.631589 DBI_RD = 0x0
764 23:18:48.635045 OTF = 0x1
765 23:18:48.638242 ===================================
766 23:18:48.641380 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:18:48.646904 nWR fixed to 40
768 23:18:48.650063 [ModeRegInit_LP4] CH0 RK0
769 23:18:48.650152 [ModeRegInit_LP4] CH0 RK1
770 23:18:48.653628 [ModeRegInit_LP4] CH1 RK0
771 23:18:48.656866 [ModeRegInit_LP4] CH1 RK1
772 23:18:48.656962 match AC timing 13
773 23:18:48.663735 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:18:48.666694 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:18:48.670264 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:18:48.676886 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:18:48.680223 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:18:48.680349 [EMI DOE] emi_dcm 0
779 23:18:48.686703 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:18:48.686829 ==
781 23:18:48.690100 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:18:48.693239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:18:48.693367 ==
784 23:18:48.700129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:18:48.706642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:18:48.714334 [CA 0] Center 37 (7~68) winsize 62
787 23:18:48.717766 [CA 1] Center 37 (6~68) winsize 63
788 23:18:48.721227 [CA 2] Center 34 (4~65) winsize 62
789 23:18:48.724802 [CA 3] Center 35 (4~66) winsize 63
790 23:18:48.728119 [CA 4] Center 33 (3~64) winsize 62
791 23:18:48.731588 [CA 5] Center 33 (3~64) winsize 62
792 23:18:48.731719
793 23:18:48.734303 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 23:18:48.734417
795 23:18:48.737712 [CATrainingPosCal] consider 1 rank data
796 23:18:48.741274 u2DelayCellTimex100 = 270/100 ps
797 23:18:48.744684 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 23:18:48.747504 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 23:18:48.754188 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 23:18:48.757376 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 23:18:48.760664 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 23:18:48.763922 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 23:18:48.764014
804 23:18:48.767200 CA PerBit enable=1, Macro0, CA PI delay=33
805 23:18:48.767289
806 23:18:48.770393 [CBTSetCACLKResult] CA Dly = 33
807 23:18:48.770508 CS Dly: 5 (0~36)
808 23:18:48.774011 ==
809 23:18:48.777084 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:18:48.780450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:18:48.780563 ==
812 23:18:48.786966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:18:48.790621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:18:48.800731 [CA 0] Center 38 (7~69) winsize 63
815 23:18:48.803838 [CA 1] Center 37 (7~68) winsize 62
816 23:18:48.807524 [CA 2] Center 35 (4~66) winsize 63
817 23:18:48.810277 [CA 3] Center 35 (4~66) winsize 63
818 23:18:48.813647 [CA 4] Center 34 (3~65) winsize 63
819 23:18:48.817193 [CA 5] Center 33 (3~64) winsize 62
820 23:18:48.817280
821 23:18:48.820093 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 23:18:48.820182
823 23:18:48.823454 [CATrainingPosCal] consider 2 rank data
824 23:18:48.826898 u2DelayCellTimex100 = 270/100 ps
825 23:18:48.830466 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 23:18:48.836753 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 23:18:48.840274 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 23:18:48.843931 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 23:18:48.846952 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 23:18:48.850219 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 23:18:48.850305
832 23:18:48.853350 CA PerBit enable=1, Macro0, CA PI delay=33
833 23:18:48.853438
834 23:18:48.857038 [CBTSetCACLKResult] CA Dly = 33
835 23:18:48.860241 CS Dly: 6 (0~38)
836 23:18:48.860327
837 23:18:48.863907 ----->DramcWriteLeveling(PI) begin...
838 23:18:48.864008 ==
839 23:18:48.867535 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:18:48.871028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:18:48.871116 ==
842 23:18:48.874430 Write leveling (Byte 0): 32 => 32
843 23:18:48.878138 Write leveling (Byte 1): 27 => 27
844 23:18:48.878225 DramcWriteLeveling(PI) end<-----
845 23:18:48.878293
846 23:18:48.878355 ==
847 23:18:48.881944 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:18:48.888502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:18:48.888590 ==
850 23:18:48.888658 [Gating] SW mode calibration
851 23:18:48.896004 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:18:48.902339 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:18:48.905771 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:18:48.912430 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 23:18:48.915478 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
856 23:18:48.919100 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 23:18:48.925496 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:18:48.928783 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:18:48.932027 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:18:48.939307 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:18:48.942019 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:18:48.945259 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:18:48.952312 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:18:48.955625 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:18:48.958634 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:18:48.961916 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:18:48.968880 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:18:48.972099 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:18:48.975389 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:18:48.981814 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
871 23:18:48.985285 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
872 23:18:48.988646 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:18:48.995276 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:18:48.998685 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:18:49.001958 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:18:49.008451 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:18:49.011681 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:18:49.015348 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:18:49.021935 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
880 23:18:49.024638 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
881 23:18:49.028761 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:18:49.035218 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:18:49.038070 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:18:49.041337 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:18:49.047939 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:18:49.051455 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
887 23:18:49.055165 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
888 23:18:49.061189 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
889 23:18:49.064894 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:18:49.068291 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:18:49.074622 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:18:49.077777 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:18:49.081260 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:18:49.087580 0 11 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
895 23:18:49.091409 0 11 8 | B1->B0 | 2b2b 4242 | 0 0 | (0 0) (0 0)
896 23:18:49.094425 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
897 23:18:49.101013 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:18:49.104642 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:18:49.107668 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:18:49.114569 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:18:49.117752 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:18:49.121313 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 23:18:49.127757 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 23:18:49.131042 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:18:49.134232 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:18:49.140953 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:18:49.144607 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:18:49.147505 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:18:49.150644 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:18:49.157374 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:18:49.160692 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:18:49.164098 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:18:49.170682 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:18:49.174297 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:18:49.177612 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:18:49.183914 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:18:49.187178 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:18:49.190722 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 23:18:49.197584 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 23:18:49.200515 Total UI for P1: 0, mck2ui 16
921 23:18:49.203999 best dqsien dly found for B0: ( 0, 14, 6)
922 23:18:49.207320 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
923 23:18:49.210739 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 23:18:49.213891 Total UI for P1: 0, mck2ui 16
925 23:18:49.217383 best dqsien dly found for B1: ( 0, 14, 10)
926 23:18:49.220729 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
927 23:18:49.223945 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 23:18:49.227147
929 23:18:49.230359 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 23:18:49.233882 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 23:18:49.237173 [Gating] SW calibration Done
932 23:18:49.237259 ==
933 23:18:49.241163 Dram Type= 6, Freq= 0, CH_0, rank 0
934 23:18:49.244646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 23:18:49.244764 ==
936 23:18:49.244867 RX Vref Scan: 0
937 23:18:49.244935
938 23:18:49.247629 RX Vref 0 -> 0, step: 1
939 23:18:49.247714
940 23:18:49.251232 RX Delay -130 -> 252, step: 16
941 23:18:49.254614 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 23:18:49.257696 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 23:18:49.261182 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 23:18:49.267716 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 23:18:49.271285 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
946 23:18:49.274226 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 23:18:49.277357 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
948 23:18:49.281338 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
949 23:18:49.287275 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 23:18:49.290819 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
951 23:18:49.294243 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
952 23:18:49.297433 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 23:18:49.303839 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 23:18:49.307341 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
955 23:18:49.310149 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 23:18:49.313840 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 23:18:49.313928 ==
958 23:18:49.316992 Dram Type= 6, Freq= 0, CH_0, rank 0
959 23:18:49.320524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 23:18:49.323662 ==
961 23:18:49.323749 DQS Delay:
962 23:18:49.323816 DQS0 = 0, DQS1 = 0
963 23:18:49.327006 DQM Delay:
964 23:18:49.327092 DQM0 = 88, DQM1 = 75
965 23:18:49.330220 DQ Delay:
966 23:18:49.333674 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 23:18:49.337053 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
968 23:18:49.337165 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
969 23:18:49.343589 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
970 23:18:49.343702
971 23:18:49.343800
972 23:18:49.343892 ==
973 23:18:49.347048 Dram Type= 6, Freq= 0, CH_0, rank 0
974 23:18:49.350356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 23:18:49.350443 ==
976 23:18:49.350511
977 23:18:49.350575
978 23:18:49.353934 TX Vref Scan disable
979 23:18:49.354020 == TX Byte 0 ==
980 23:18:49.360235 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
981 23:18:49.363549 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
982 23:18:49.363637 == TX Byte 1 ==
983 23:18:49.370207 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
984 23:18:49.373666 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
985 23:18:49.373753 ==
986 23:18:49.376777 Dram Type= 6, Freq= 0, CH_0, rank 0
987 23:18:49.380158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 23:18:49.380290 ==
989 23:18:49.394680 TX Vref=22, minBit 0, minWin=27, winSum=438
990 23:18:49.398202 TX Vref=24, minBit 0, minWin=27, winSum=443
991 23:18:49.401420 TX Vref=26, minBit 1, minWin=27, winSum=443
992 23:18:49.405029 TX Vref=28, minBit 3, minWin=27, winSum=451
993 23:18:49.407826 TX Vref=30, minBit 0, minWin=28, winSum=451
994 23:18:49.411583 TX Vref=32, minBit 2, minWin=27, winSum=448
995 23:18:49.418243 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
996 23:18:49.418376
997 23:18:49.421332 Final TX Range 1 Vref 30
998 23:18:49.421459
999 23:18:49.421577 ==
1000 23:18:49.424505 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 23:18:49.428232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 23:18:49.428361 ==
1003 23:18:49.428478
1004 23:18:49.431080
1005 23:18:49.431207 TX Vref Scan disable
1006 23:18:49.434433 == TX Byte 0 ==
1007 23:18:49.437666 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1008 23:18:49.444348 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1009 23:18:49.444479 == TX Byte 1 ==
1010 23:18:49.448013 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1011 23:18:49.454381 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1012 23:18:49.454510
1013 23:18:49.454622 [DATLAT]
1014 23:18:49.454735 Freq=800, CH0 RK0
1015 23:18:49.454849
1016 23:18:49.457781 DATLAT Default: 0xa
1017 23:18:49.457908 0, 0xFFFF, sum = 0
1018 23:18:49.461404 1, 0xFFFF, sum = 0
1019 23:18:49.461535 2, 0xFFFF, sum = 0
1020 23:18:49.464239 3, 0xFFFF, sum = 0
1021 23:18:49.467483 4, 0xFFFF, sum = 0
1022 23:18:49.467615 5, 0xFFFF, sum = 0
1023 23:18:49.470977 6, 0xFFFF, sum = 0
1024 23:18:49.471107 7, 0xFFFF, sum = 0
1025 23:18:49.474246 8, 0xFFFF, sum = 0
1026 23:18:49.474357 9, 0x0, sum = 1
1027 23:18:49.477642 10, 0x0, sum = 2
1028 23:18:49.477777 11, 0x0, sum = 3
1029 23:18:49.477899 12, 0x0, sum = 4
1030 23:18:49.480750 best_step = 10
1031 23:18:49.480877
1032 23:18:49.480992 ==
1033 23:18:49.484295 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 23:18:49.487296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 23:18:49.487431 ==
1036 23:18:49.491114 RX Vref Scan: 1
1037 23:18:49.491240
1038 23:18:49.493928 Set Vref Range= 32 -> 127
1039 23:18:49.494055
1040 23:18:49.494172 RX Vref 32 -> 127, step: 1
1041 23:18:49.494286
1042 23:18:49.497269 RX Delay -111 -> 252, step: 8
1043 23:18:49.497394
1044 23:18:49.500655 Set Vref, RX VrefLevel [Byte0]: 32
1045 23:18:49.503948 [Byte1]: 32
1046 23:18:49.507468
1047 23:18:49.507594 Set Vref, RX VrefLevel [Byte0]: 33
1048 23:18:49.510656 [Byte1]: 33
1049 23:18:49.514848
1050 23:18:49.514974 Set Vref, RX VrefLevel [Byte0]: 34
1051 23:18:49.518272 [Byte1]: 34
1052 23:18:49.522893
1053 23:18:49.523016 Set Vref, RX VrefLevel [Byte0]: 35
1054 23:18:49.526214 [Byte1]: 35
1055 23:18:49.530898
1056 23:18:49.531030 Set Vref, RX VrefLevel [Byte0]: 36
1057 23:18:49.534086 [Byte1]: 36
1058 23:18:49.538124
1059 23:18:49.538248 Set Vref, RX VrefLevel [Byte0]: 37
1060 23:18:49.541246 [Byte1]: 37
1061 23:18:49.545906
1062 23:18:49.546032 Set Vref, RX VrefLevel [Byte0]: 38
1063 23:18:49.549263 [Byte1]: 38
1064 23:18:49.553621
1065 23:18:49.553744 Set Vref, RX VrefLevel [Byte0]: 39
1066 23:18:49.557405 [Byte1]: 39
1067 23:18:49.561553
1068 23:18:49.561678 Set Vref, RX VrefLevel [Byte0]: 40
1069 23:18:49.565155 [Byte1]: 40
1070 23:18:49.568755
1071 23:18:49.568835 Set Vref, RX VrefLevel [Byte0]: 41
1072 23:18:49.572193 [Byte1]: 41
1073 23:18:49.576667
1074 23:18:49.576743 Set Vref, RX VrefLevel [Byte0]: 42
1075 23:18:49.579608 [Byte1]: 42
1076 23:18:49.584352
1077 23:18:49.584481 Set Vref, RX VrefLevel [Byte0]: 43
1078 23:18:49.587381 [Byte1]: 43
1079 23:18:49.591479
1080 23:18:49.591604 Set Vref, RX VrefLevel [Byte0]: 44
1081 23:18:49.594629 [Byte1]: 44
1082 23:18:49.598920
1083 23:18:49.599044 Set Vref, RX VrefLevel [Byte0]: 45
1084 23:18:49.602342 [Byte1]: 45
1085 23:18:49.606932
1086 23:18:49.607055 Set Vref, RX VrefLevel [Byte0]: 46
1087 23:18:49.610083 [Byte1]: 46
1088 23:18:49.614665
1089 23:18:49.614794 Set Vref, RX VrefLevel [Byte0]: 47
1090 23:18:49.617788 [Byte1]: 47
1091 23:18:49.622150
1092 23:18:49.622274 Set Vref, RX VrefLevel [Byte0]: 48
1093 23:18:49.625753 [Byte1]: 48
1094 23:18:49.629792
1095 23:18:49.629914 Set Vref, RX VrefLevel [Byte0]: 49
1096 23:18:49.632947 [Byte1]: 49
1097 23:18:49.637428
1098 23:18:49.637552 Set Vref, RX VrefLevel [Byte0]: 50
1099 23:18:49.640684 [Byte1]: 50
1100 23:18:49.644921
1101 23:18:49.645049 Set Vref, RX VrefLevel [Byte0]: 51
1102 23:18:49.648256 [Byte1]: 51
1103 23:18:49.652689
1104 23:18:49.652813 Set Vref, RX VrefLevel [Byte0]: 52
1105 23:18:49.655967 [Byte1]: 52
1106 23:18:49.660499
1107 23:18:49.660624 Set Vref, RX VrefLevel [Byte0]: 53
1108 23:18:49.663714 [Byte1]: 53
1109 23:18:49.668017
1110 23:18:49.668145 Set Vref, RX VrefLevel [Byte0]: 54
1111 23:18:49.671345 [Byte1]: 54
1112 23:18:49.675617
1113 23:18:49.675743 Set Vref, RX VrefLevel [Byte0]: 55
1114 23:18:49.679194 [Byte1]: 55
1115 23:18:49.683260
1116 23:18:49.683387 Set Vref, RX VrefLevel [Byte0]: 56
1117 23:18:49.686457 [Byte1]: 56
1118 23:18:49.690863
1119 23:18:49.690988 Set Vref, RX VrefLevel [Byte0]: 57
1120 23:18:49.694282 [Byte1]: 57
1121 23:18:49.698534
1122 23:18:49.698660 Set Vref, RX VrefLevel [Byte0]: 58
1123 23:18:49.702013 [Byte1]: 58
1124 23:18:49.706264
1125 23:18:49.706392 Set Vref, RX VrefLevel [Byte0]: 59
1126 23:18:49.709272 [Byte1]: 59
1127 23:18:49.713777
1128 23:18:49.713904 Set Vref, RX VrefLevel [Byte0]: 60
1129 23:18:49.716931 [Byte1]: 60
1130 23:18:49.721516
1131 23:18:49.721644 Set Vref, RX VrefLevel [Byte0]: 61
1132 23:18:49.724514 [Byte1]: 61
1133 23:18:49.728797
1134 23:18:49.728920 Set Vref, RX VrefLevel [Byte0]: 62
1135 23:18:49.732223 [Byte1]: 62
1136 23:18:49.737218
1137 23:18:49.737341 Set Vref, RX VrefLevel [Byte0]: 63
1138 23:18:49.739867 [Byte1]: 63
1139 23:18:49.744311
1140 23:18:49.744437 Set Vref, RX VrefLevel [Byte0]: 64
1141 23:18:49.747487 [Byte1]: 64
1142 23:18:49.751975
1143 23:18:49.752095 Set Vref, RX VrefLevel [Byte0]: 65
1144 23:18:49.755478 [Byte1]: 65
1145 23:18:49.759880
1146 23:18:49.760005 Set Vref, RX VrefLevel [Byte0]: 66
1147 23:18:49.763062 [Byte1]: 66
1148 23:18:49.767227
1149 23:18:49.767356 Set Vref, RX VrefLevel [Byte0]: 67
1150 23:18:49.770762 [Byte1]: 67
1151 23:18:49.775426
1152 23:18:49.775553 Set Vref, RX VrefLevel [Byte0]: 68
1153 23:18:49.778509 [Byte1]: 68
1154 23:18:49.782460
1155 23:18:49.782586 Set Vref, RX VrefLevel [Byte0]: 69
1156 23:18:49.786352 [Byte1]: 69
1157 23:18:49.790415
1158 23:18:49.790540 Set Vref, RX VrefLevel [Byte0]: 70
1159 23:18:49.793548 [Byte1]: 70
1160 23:18:49.797829
1161 23:18:49.797949 Set Vref, RX VrefLevel [Byte0]: 71
1162 23:18:49.801111 [Byte1]: 71
1163 23:18:49.805526
1164 23:18:49.805650 Set Vref, RX VrefLevel [Byte0]: 72
1165 23:18:49.809052 [Byte1]: 72
1166 23:18:49.813346
1167 23:18:49.813474 Set Vref, RX VrefLevel [Byte0]: 73
1168 23:18:49.816686 [Byte1]: 73
1169 23:18:49.820851
1170 23:18:49.820977 Final RX Vref Byte 0 = 57 to rank0
1171 23:18:49.823887 Final RX Vref Byte 1 = 58 to rank0
1172 23:18:49.827442 Final RX Vref Byte 0 = 57 to rank1
1173 23:18:49.830524 Final RX Vref Byte 1 = 58 to rank1==
1174 23:18:49.834137 Dram Type= 6, Freq= 0, CH_0, rank 0
1175 23:18:49.841505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 23:18:49.841637 ==
1177 23:18:49.841753 DQS Delay:
1178 23:18:49.841866 DQS0 = 0, DQS1 = 0
1179 23:18:49.843795 DQM Delay:
1180 23:18:49.843918 DQM0 = 88, DQM1 = 76
1181 23:18:49.847301 DQ Delay:
1182 23:18:49.850770 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1183 23:18:49.854047 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1184 23:18:49.856992 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1185 23:18:49.860686 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1186 23:18:49.860811
1187 23:18:49.860908
1188 23:18:49.867082 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1189 23:18:49.871311 CH0 RK0: MR19=606, MR18=2F29
1190 23:18:49.877319 CH0_RK0: MR19=0x606, MR18=0x2F29, DQSOSC=397, MR23=63, INC=93, DEC=62
1191 23:18:49.877446
1192 23:18:49.880655 ----->DramcWriteLeveling(PI) begin...
1193 23:18:49.880780 ==
1194 23:18:49.884208 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 23:18:49.887062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 23:18:49.887190 ==
1197 23:18:49.890829 Write leveling (Byte 0): 33 => 33
1198 23:18:49.893625 Write leveling (Byte 1): 29 => 29
1199 23:18:49.896922 DramcWriteLeveling(PI) end<-----
1200 23:18:49.897047
1201 23:18:49.897164 ==
1202 23:18:49.900305 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 23:18:49.903810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 23:18:49.903935 ==
1205 23:18:49.906803 [Gating] SW mode calibration
1206 23:18:49.914169 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1207 23:18:49.919948 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1208 23:18:49.923302 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1209 23:18:49.970842 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1210 23:18:49.970974 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1211 23:18:49.971265 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 23:18:49.971856 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 23:18:49.972248 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 23:18:49.972347 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 23:18:49.972623 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 23:18:49.972716 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 23:18:49.972995 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 23:18:49.973577 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 23:18:49.973673 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:18:50.005097 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:18:50.005585 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:18:50.006438 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:18:50.006694 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:18:50.006791 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:18:50.007140 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1226 23:18:50.007787 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1227 23:18:50.010243 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:18:50.013547 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:18:50.016686 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:18:50.020615 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:18:50.026521 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:18:50.030490 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:18:50.033279 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:18:50.039890 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
1235 23:18:50.043233 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 23:18:50.046738 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 23:18:50.050439 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 23:18:50.056585 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 23:18:50.059877 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 23:18:50.063444 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 23:18:50.070091 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
1242 23:18:50.073090 0 10 8 | B1->B0 | 3131 2626 | 0 0 | (0 1) (1 0)
1243 23:18:50.076708 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:18:50.082961 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:18:50.086562 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:18:50.089949 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:18:50.096363 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 23:18:50.099671 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 23:18:50.103115 0 11 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
1250 23:18:50.109563 0 11 8 | B1->B0 | 3030 4444 | 0 0 | (0 0) (0 0)
1251 23:18:50.113889 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1252 23:18:50.117223 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 23:18:50.120829 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 23:18:50.124946 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 23:18:50.131803 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 23:18:50.134997 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 23:18:50.138275 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1258 23:18:50.145417 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1259 23:18:50.148736 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 23:18:50.151769 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 23:18:50.158251 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 23:18:50.161971 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 23:18:50.164852 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 23:18:50.171597 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 23:18:50.174958 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 23:18:50.178751 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 23:18:50.185121 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 23:18:50.188067 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 23:18:50.191640 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 23:18:50.198061 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:18:50.201808 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:18:50.204958 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:18:50.211492 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1274 23:18:50.215012 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 23:18:50.217793 Total UI for P1: 0, mck2ui 16
1276 23:18:50.221584 best dqsien dly found for B0: ( 0, 14, 4)
1277 23:18:50.224377 Total UI for P1: 0, mck2ui 16
1278 23:18:50.227961 best dqsien dly found for B1: ( 0, 14, 6)
1279 23:18:50.231271 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1280 23:18:50.234588 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1281 23:18:50.234715
1282 23:18:50.238041 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1283 23:18:50.241129 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1284 23:18:50.244340 [Gating] SW calibration Done
1285 23:18:50.244424 ==
1286 23:18:50.247921 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 23:18:50.251148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 23:18:50.251270 ==
1289 23:18:50.254353 RX Vref Scan: 0
1290 23:18:50.254463
1291 23:18:50.254561 RX Vref 0 -> 0, step: 1
1292 23:18:50.257832
1293 23:18:50.257920 RX Delay -130 -> 252, step: 16
1294 23:18:50.264607 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1295 23:18:50.267713 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1296 23:18:50.271120 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1297 23:18:50.274817 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1298 23:18:50.277870 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1299 23:18:50.284304 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1300 23:18:50.287957 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1301 23:18:50.291082 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1302 23:18:50.294365 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1303 23:18:50.297638 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1304 23:18:50.301580 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1305 23:18:50.307724 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1306 23:18:50.311616 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1307 23:18:50.314611 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1308 23:18:50.317367 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1309 23:18:50.324280 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1310 23:18:50.324386 ==
1311 23:18:50.327318 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 23:18:50.330615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 23:18:50.330727 ==
1314 23:18:50.330821 DQS Delay:
1315 23:18:50.333884 DQS0 = 0, DQS1 = 0
1316 23:18:50.333984 DQM Delay:
1317 23:18:50.337548 DQM0 = 86, DQM1 = 77
1318 23:18:50.337649 DQ Delay:
1319 23:18:50.340750 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1320 23:18:50.343784 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1321 23:18:50.347260 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1322 23:18:50.350377 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1323 23:18:50.350481
1324 23:18:50.350584
1325 23:18:50.350673 ==
1326 23:18:50.354242 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 23:18:50.357367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 23:18:50.360578 ==
1329 23:18:50.360689
1330 23:18:50.360782
1331 23:18:50.360873 TX Vref Scan disable
1332 23:18:50.364073 == TX Byte 0 ==
1333 23:18:50.367366 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1334 23:18:50.370228 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1335 23:18:50.373816 == TX Byte 1 ==
1336 23:18:50.377375 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1337 23:18:50.380652 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1338 23:18:50.383752 ==
1339 23:18:50.387173 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 23:18:50.390281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 23:18:50.390379 ==
1342 23:18:50.402904 TX Vref=22, minBit 1, minWin=27, winSum=445
1343 23:18:50.406403 TX Vref=24, minBit 1, minWin=27, winSum=447
1344 23:18:50.409937 TX Vref=26, minBit 2, minWin=27, winSum=451
1345 23:18:50.412772 TX Vref=28, minBit 2, minWin=27, winSum=453
1346 23:18:50.416031 TX Vref=30, minBit 5, minWin=27, winSum=452
1347 23:18:50.419448 TX Vref=32, minBit 4, minWin=27, winSum=450
1348 23:18:50.426274 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 28
1349 23:18:50.426381
1350 23:18:50.429329 Final TX Range 1 Vref 28
1351 23:18:50.429430
1352 23:18:50.429532 ==
1353 23:18:50.432717 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 23:18:50.436170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 23:18:50.436277 ==
1356 23:18:50.439147
1357 23:18:50.439245
1358 23:18:50.439336 TX Vref Scan disable
1359 23:18:50.442822 == TX Byte 0 ==
1360 23:18:50.446158 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1361 23:18:50.452843 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1362 23:18:50.452953 == TX Byte 1 ==
1363 23:18:50.456287 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1364 23:18:50.462891 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1365 23:18:50.462994
1366 23:18:50.463096 [DATLAT]
1367 23:18:50.463186 Freq=800, CH0 RK1
1368 23:18:50.463284
1369 23:18:50.466224 DATLAT Default: 0xa
1370 23:18:50.466327 0, 0xFFFF, sum = 0
1371 23:18:50.469281 1, 0xFFFF, sum = 0
1372 23:18:50.469396 2, 0xFFFF, sum = 0
1373 23:18:50.472685 3, 0xFFFF, sum = 0
1374 23:18:50.476298 4, 0xFFFF, sum = 0
1375 23:18:50.476400 5, 0xFFFF, sum = 0
1376 23:18:50.479436 6, 0xFFFF, sum = 0
1377 23:18:50.479539 7, 0xFFFF, sum = 0
1378 23:18:50.482587 8, 0xFFFF, sum = 0
1379 23:18:50.482663 9, 0x0, sum = 1
1380 23:18:50.485962 10, 0x0, sum = 2
1381 23:18:50.486064 11, 0x0, sum = 3
1382 23:18:50.486156 12, 0x0, sum = 4
1383 23:18:50.489409 best_step = 10
1384 23:18:50.489499
1385 23:18:50.489563 ==
1386 23:18:50.492559 Dram Type= 6, Freq= 0, CH_0, rank 1
1387 23:18:50.496026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 23:18:50.496121 ==
1389 23:18:50.499623 RX Vref Scan: 0
1390 23:18:50.499699
1391 23:18:50.499762 RX Vref 0 -> 0, step: 1
1392 23:18:50.499821
1393 23:18:50.502940 RX Delay -95 -> 252, step: 8
1394 23:18:50.509380 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1395 23:18:50.512741 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1396 23:18:50.516444 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1397 23:18:50.519701 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1398 23:18:50.522843 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1399 23:18:50.529805 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1400 23:18:50.533186 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1401 23:18:50.536292 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1402 23:18:50.539312 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1403 23:18:50.542771 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1404 23:18:50.549353 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1405 23:18:50.552755 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1406 23:18:50.555924 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1407 23:18:50.559453 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1408 23:18:50.565946 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1409 23:18:50.569201 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1410 23:18:50.569285 ==
1411 23:18:50.572384 Dram Type= 6, Freq= 0, CH_0, rank 1
1412 23:18:50.575631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 23:18:50.575741 ==
1414 23:18:50.575835 DQS Delay:
1415 23:18:50.578904 DQS0 = 0, DQS1 = 0
1416 23:18:50.578987 DQM Delay:
1417 23:18:50.582673 DQM0 = 86, DQM1 = 76
1418 23:18:50.582764 DQ Delay:
1419 23:18:50.586124 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1420 23:18:50.589261 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1421 23:18:50.592333 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1422 23:18:50.596116 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1423 23:18:50.596225
1424 23:18:50.596329
1425 23:18:50.605567 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1426 23:18:50.605674 CH0 RK1: MR19=606, MR18=2B28
1427 23:18:50.612317 CH0_RK1: MR19=0x606, MR18=0x2B28, DQSOSC=398, MR23=63, INC=93, DEC=62
1428 23:18:50.615496 [RxdqsGatingPostProcess] freq 800
1429 23:18:50.622332 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1430 23:18:50.625451 Pre-setting of DQS Precalculation
1431 23:18:50.628814 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1432 23:18:50.628889 ==
1433 23:18:50.632412 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 23:18:50.638925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 23:18:50.639028 ==
1436 23:18:50.642415 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1437 23:18:50.648587 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1438 23:18:50.657908 [CA 0] Center 37 (6~68) winsize 63
1439 23:18:50.661329 [CA 1] Center 37 (6~68) winsize 63
1440 23:18:50.664301 [CA 2] Center 35 (5~66) winsize 62
1441 23:18:50.667842 [CA 3] Center 34 (4~65) winsize 62
1442 23:18:50.670979 [CA 4] Center 35 (4~66) winsize 63
1443 23:18:50.674385 [CA 5] Center 34 (4~65) winsize 62
1444 23:18:50.674489
1445 23:18:50.677830 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1446 23:18:50.677931
1447 23:18:50.680955 [CATrainingPosCal] consider 1 rank data
1448 23:18:50.684404 u2DelayCellTimex100 = 270/100 ps
1449 23:18:50.687950 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1450 23:18:50.694639 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1451 23:18:50.697497 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1452 23:18:50.700866 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1453 23:18:50.704342 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1454 23:18:50.708037 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1455 23:18:50.708114
1456 23:18:50.711192 CA PerBit enable=1, Macro0, CA PI delay=34
1457 23:18:50.711289
1458 23:18:50.714270 [CBTSetCACLKResult] CA Dly = 34
1459 23:18:50.714372 CS Dly: 4 (0~35)
1460 23:18:50.717569 ==
1461 23:18:50.721103 Dram Type= 6, Freq= 0, CH_1, rank 1
1462 23:18:50.724264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 23:18:50.724412 ==
1464 23:18:50.727563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1465 23:18:50.734131 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1466 23:18:50.743984 [CA 0] Center 36 (6~67) winsize 62
1467 23:18:50.747353 [CA 1] Center 36 (6~67) winsize 62
1468 23:18:50.750882 [CA 2] Center 35 (4~66) winsize 63
1469 23:18:50.753897 [CA 3] Center 34 (4~65) winsize 62
1470 23:18:50.757673 [CA 4] Center 34 (4~65) winsize 62
1471 23:18:50.760725 [CA 5] Center 34 (4~65) winsize 62
1472 23:18:50.760845
1473 23:18:50.763827 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1474 23:18:50.763937
1475 23:18:50.767115 [CATrainingPosCal] consider 2 rank data
1476 23:18:50.770624 u2DelayCellTimex100 = 270/100 ps
1477 23:18:50.774025 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1478 23:18:50.777566 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1479 23:18:50.781095 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1480 23:18:50.784729 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1481 23:18:50.788136 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 23:18:50.791700 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1483 23:18:50.795324
1484 23:18:50.799356 CA PerBit enable=1, Macro0, CA PI delay=34
1485 23:18:50.799466
1486 23:18:50.799531 [CBTSetCACLKResult] CA Dly = 34
1487 23:18:50.802807 CS Dly: 5 (0~37)
1488 23:18:50.802914
1489 23:18:50.806771 ----->DramcWriteLeveling(PI) begin...
1490 23:18:50.806856 ==
1491 23:18:50.810572 Dram Type= 6, Freq= 0, CH_1, rank 0
1492 23:18:50.814752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 23:18:50.814839 ==
1494 23:18:50.817381 Write leveling (Byte 0): 28 => 28
1495 23:18:50.820335 Write leveling (Byte 1): 29 => 29
1496 23:18:50.823680 DramcWriteLeveling(PI) end<-----
1497 23:18:50.823762
1498 23:18:50.823827 ==
1499 23:18:50.827108 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 23:18:50.830575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 23:18:50.830652 ==
1502 23:18:50.833866 [Gating] SW mode calibration
1503 23:18:50.840713 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1504 23:18:50.846862 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1505 23:18:50.850961 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1506 23:18:50.853605 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1507 23:18:50.857115 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1508 23:18:50.863588 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 23:18:50.866914 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 23:18:50.870409 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 23:18:50.877053 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 23:18:50.880221 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 23:18:50.883629 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 23:18:50.890259 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 23:18:50.893690 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 23:18:50.896860 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 23:18:50.903567 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:18:50.906643 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:18:50.910035 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:18:50.916676 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:18:50.919922 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1522 23:18:50.923282 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1523 23:18:50.930096 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:18:50.933129 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:18:50.936396 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:18:50.943565 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:18:50.946741 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:18:50.949838 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:18:50.956383 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:18:50.959586 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:18:50.963312 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1532 23:18:50.969415 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 23:18:50.973089 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 23:18:50.975983 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 23:18:50.982892 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 23:18:50.985784 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 23:18:50.989582 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 23:18:50.996242 0 10 4 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
1539 23:18:50.999282 0 10 8 | B1->B0 | 2c2c 2525 | 0 0 | (1 1) (0 0)
1540 23:18:51.002462 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:18:51.009448 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:18:51.012732 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:18:51.015729 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:18:51.022460 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 23:18:51.026580 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 23:18:51.029352 0 11 4 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
1547 23:18:51.035886 0 11 8 | B1->B0 | 3636 4242 | 0 0 | (0 0) (0 0)
1548 23:18:51.039273 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 23:18:51.043000 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 23:18:51.049251 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 23:18:51.052370 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 23:18:51.055813 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 23:18:51.058998 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 23:18:51.065659 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1555 23:18:51.068953 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1556 23:18:51.072319 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 23:18:51.078623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 23:18:51.082099 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 23:18:51.085365 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 23:18:51.091906 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 23:18:51.095442 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 23:18:51.099078 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 23:18:51.105737 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 23:18:51.108965 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 23:18:51.112144 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 23:18:51.118798 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 23:18:51.122170 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:18:51.125242 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 23:18:51.131919 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:18:51.135515 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:18:51.138697 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 23:18:51.141780 Total UI for P1: 0, mck2ui 16
1573 23:18:51.144983 best dqsien dly found for B0: ( 0, 14, 6)
1574 23:18:51.148400 Total UI for P1: 0, mck2ui 16
1575 23:18:51.151595 best dqsien dly found for B1: ( 0, 14, 6)
1576 23:18:51.155496 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1577 23:18:51.158383 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1578 23:18:51.158509
1579 23:18:51.165248 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1580 23:18:51.168243 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1581 23:18:51.168367 [Gating] SW calibration Done
1582 23:18:51.171744 ==
1583 23:18:51.175167 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 23:18:51.178448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 23:18:51.178567 ==
1586 23:18:51.178659 RX Vref Scan: 0
1587 23:18:51.178752
1588 23:18:51.181745 RX Vref 0 -> 0, step: 1
1589 23:18:51.181816
1590 23:18:51.185193 RX Delay -130 -> 252, step: 16
1591 23:18:51.188533 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1592 23:18:51.191515 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1593 23:18:51.198442 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1594 23:18:51.201697 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1595 23:18:51.204950 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1596 23:18:51.208472 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1597 23:18:51.211356 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1598 23:18:51.218138 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1599 23:18:51.221454 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1600 23:18:51.224584 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1601 23:18:51.228002 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1602 23:18:51.231193 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1603 23:18:51.238062 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1604 23:18:51.241554 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1605 23:18:51.244855 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1606 23:18:51.247827 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1607 23:18:51.247910 ==
1608 23:18:51.251055 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 23:18:51.257845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 23:18:51.257947 ==
1611 23:18:51.258014 DQS Delay:
1612 23:18:51.261321 DQS0 = 0, DQS1 = 0
1613 23:18:51.261409 DQM Delay:
1614 23:18:51.261472 DQM0 = 88, DQM1 = 81
1615 23:18:51.264501 DQ Delay:
1616 23:18:51.267869 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1617 23:18:51.271385 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1618 23:18:51.274370 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1619 23:18:51.277967 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =93
1620 23:18:51.278116
1621 23:18:51.278235
1622 23:18:51.278338 ==
1623 23:18:51.281230 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 23:18:51.284554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 23:18:51.284677 ==
1626 23:18:51.284797
1627 23:18:51.284907
1628 23:18:51.288476 TX Vref Scan disable
1629 23:18:51.288560 == TX Byte 0 ==
1630 23:18:51.294863 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1631 23:18:51.298139 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1632 23:18:51.298262 == TX Byte 1 ==
1633 23:18:51.304893 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1634 23:18:51.308133 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1635 23:18:51.308229 ==
1636 23:18:51.311381 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 23:18:51.314678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 23:18:51.314758 ==
1639 23:18:51.328989 TX Vref=22, minBit 0, minWin=26, winSum=438
1640 23:18:51.332095 TX Vref=24, minBit 3, minWin=26, winSum=444
1641 23:18:51.335449 TX Vref=26, minBit 0, minWin=27, winSum=445
1642 23:18:51.338530 TX Vref=28, minBit 2, minWin=27, winSum=449
1643 23:18:51.341936 TX Vref=30, minBit 1, minWin=27, winSum=452
1644 23:18:51.348364 TX Vref=32, minBit 0, minWin=27, winSum=449
1645 23:18:51.352099 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30
1646 23:18:51.352226
1647 23:18:51.355052 Final TX Range 1 Vref 30
1648 23:18:51.355176
1649 23:18:51.355291 ==
1650 23:18:51.358968 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 23:18:51.362897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 23:18:51.363025 ==
1653 23:18:51.363142
1654 23:18:51.363251
1655 23:18:51.365808 TX Vref Scan disable
1656 23:18:51.369148 == TX Byte 0 ==
1657 23:18:51.372316 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1658 23:18:51.375476 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1659 23:18:51.379245 == TX Byte 1 ==
1660 23:18:51.382311 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1661 23:18:51.385927 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1662 23:18:51.386052
1663 23:18:51.389024 [DATLAT]
1664 23:18:51.389128 Freq=800, CH1 RK0
1665 23:18:51.389222
1666 23:18:51.392362 DATLAT Default: 0xa
1667 23:18:51.392461 0, 0xFFFF, sum = 0
1668 23:18:51.396010 1, 0xFFFF, sum = 0
1669 23:18:51.396108 2, 0xFFFF, sum = 0
1670 23:18:51.398847 3, 0xFFFF, sum = 0
1671 23:18:51.398921 4, 0xFFFF, sum = 0
1672 23:18:51.402146 5, 0xFFFF, sum = 0
1673 23:18:51.402231 6, 0xFFFF, sum = 0
1674 23:18:51.405885 7, 0xFFFF, sum = 0
1675 23:18:51.405971 8, 0xFFFF, sum = 0
1676 23:18:51.408931 9, 0x0, sum = 1
1677 23:18:51.409016 10, 0x0, sum = 2
1678 23:18:51.412169 11, 0x0, sum = 3
1679 23:18:51.412281 12, 0x0, sum = 4
1680 23:18:51.415931 best_step = 10
1681 23:18:51.416013
1682 23:18:51.416078 ==
1683 23:18:51.418686 Dram Type= 6, Freq= 0, CH_1, rank 0
1684 23:18:51.422217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1685 23:18:51.422325 ==
1686 23:18:51.425575 RX Vref Scan: 1
1687 23:18:51.425656
1688 23:18:51.425720 Set Vref Range= 32 -> 127
1689 23:18:51.425779
1690 23:18:51.429029 RX Vref 32 -> 127, step: 1
1691 23:18:51.429110
1692 23:18:51.432545 RX Delay -95 -> 252, step: 8
1693 23:18:51.432626
1694 23:18:51.435488 Set Vref, RX VrefLevel [Byte0]: 32
1695 23:18:51.438863 [Byte1]: 32
1696 23:18:51.438970
1697 23:18:51.441974 Set Vref, RX VrefLevel [Byte0]: 33
1698 23:18:51.445389 [Byte1]: 33
1699 23:18:51.449085
1700 23:18:51.449166 Set Vref, RX VrefLevel [Byte0]: 34
1701 23:18:51.452269 [Byte1]: 34
1702 23:18:51.456208
1703 23:18:51.456334 Set Vref, RX VrefLevel [Byte0]: 35
1704 23:18:51.459854 [Byte1]: 35
1705 23:18:51.464021
1706 23:18:51.464139 Set Vref, RX VrefLevel [Byte0]: 36
1707 23:18:51.467943 [Byte1]: 36
1708 23:18:51.472182
1709 23:18:51.472268 Set Vref, RX VrefLevel [Byte0]: 37
1710 23:18:51.475098 [Byte1]: 37
1711 23:18:51.479252
1712 23:18:51.479334 Set Vref, RX VrefLevel [Byte0]: 38
1713 23:18:51.482651 [Byte1]: 38
1714 23:18:51.486855
1715 23:18:51.486937 Set Vref, RX VrefLevel [Byte0]: 39
1716 23:18:51.490314 [Byte1]: 39
1717 23:18:51.494463
1718 23:18:51.494545 Set Vref, RX VrefLevel [Byte0]: 40
1719 23:18:51.497758 [Byte1]: 40
1720 23:18:51.501940
1721 23:18:51.502022 Set Vref, RX VrefLevel [Byte0]: 41
1722 23:18:51.505481 [Byte1]: 41
1723 23:18:51.510035
1724 23:18:51.510136 Set Vref, RX VrefLevel [Byte0]: 42
1725 23:18:51.513015 [Byte1]: 42
1726 23:18:51.517036
1727 23:18:51.517118 Set Vref, RX VrefLevel [Byte0]: 43
1728 23:18:51.520967 [Byte1]: 43
1729 23:18:51.524745
1730 23:18:51.524827 Set Vref, RX VrefLevel [Byte0]: 44
1731 23:18:51.528195 [Byte1]: 44
1732 23:18:51.532664
1733 23:18:51.532749 Set Vref, RX VrefLevel [Byte0]: 45
1734 23:18:51.535506 [Byte1]: 45
1735 23:18:51.540494
1736 23:18:51.540577 Set Vref, RX VrefLevel [Byte0]: 46
1737 23:18:51.543046 [Byte1]: 46
1738 23:18:51.547906
1739 23:18:51.547988 Set Vref, RX VrefLevel [Byte0]: 47
1740 23:18:51.551170 [Byte1]: 47
1741 23:18:51.555562
1742 23:18:51.555644 Set Vref, RX VrefLevel [Byte0]: 48
1743 23:18:51.558372 [Byte1]: 48
1744 23:18:51.563002
1745 23:18:51.563084 Set Vref, RX VrefLevel [Byte0]: 49
1746 23:18:51.565922 [Byte1]: 49
1747 23:18:51.570859
1748 23:18:51.570941 Set Vref, RX VrefLevel [Byte0]: 50
1749 23:18:51.573737 [Byte1]: 50
1750 23:18:51.578040
1751 23:18:51.578122 Set Vref, RX VrefLevel [Byte0]: 51
1752 23:18:51.581101 [Byte1]: 51
1753 23:18:51.585555
1754 23:18:51.585637 Set Vref, RX VrefLevel [Byte0]: 52
1755 23:18:51.588984 [Byte1]: 52
1756 23:18:51.593262
1757 23:18:51.593344 Set Vref, RX VrefLevel [Byte0]: 53
1758 23:18:51.596203 [Byte1]: 53
1759 23:18:51.600660
1760 23:18:51.600743 Set Vref, RX VrefLevel [Byte0]: 54
1761 23:18:51.604208 [Byte1]: 54
1762 23:18:51.608285
1763 23:18:51.608367 Set Vref, RX VrefLevel [Byte0]: 55
1764 23:18:51.611557 [Byte1]: 55
1765 23:18:51.616322
1766 23:18:51.616404 Set Vref, RX VrefLevel [Byte0]: 56
1767 23:18:51.619350 [Byte1]: 56
1768 23:18:51.623508
1769 23:18:51.623590 Set Vref, RX VrefLevel [Byte0]: 57
1770 23:18:51.627434 [Byte1]: 57
1771 23:18:51.631243
1772 23:18:51.631344 Set Vref, RX VrefLevel [Byte0]: 58
1773 23:18:51.634776 [Byte1]: 58
1774 23:18:51.639075
1775 23:18:51.639204 Set Vref, RX VrefLevel [Byte0]: 59
1776 23:18:51.641863 [Byte1]: 59
1777 23:18:51.646638
1778 23:18:51.646763 Set Vref, RX VrefLevel [Byte0]: 60
1779 23:18:51.649488 [Byte1]: 60
1780 23:18:51.654060
1781 23:18:51.654182 Set Vref, RX VrefLevel [Byte0]: 61
1782 23:18:51.657007 [Byte1]: 61
1783 23:18:51.661761
1784 23:18:51.661886 Set Vref, RX VrefLevel [Byte0]: 62
1785 23:18:51.664598 [Byte1]: 62
1786 23:18:51.669309
1787 23:18:51.669431 Set Vref, RX VrefLevel [Byte0]: 63
1788 23:18:51.672522 [Byte1]: 63
1789 23:18:51.676702
1790 23:18:51.676825 Set Vref, RX VrefLevel [Byte0]: 64
1791 23:18:51.680581 [Byte1]: 64
1792 23:18:51.684359
1793 23:18:51.684479 Set Vref, RX VrefLevel [Byte0]: 65
1794 23:18:51.687580 [Byte1]: 65
1795 23:18:51.691840
1796 23:18:51.691972 Set Vref, RX VrefLevel [Byte0]: 66
1797 23:18:51.695269 [Byte1]: 66
1798 23:18:51.699524
1799 23:18:51.699643 Set Vref, RX VrefLevel [Byte0]: 67
1800 23:18:51.702736 [Byte1]: 67
1801 23:18:51.707250
1802 23:18:51.707401 Set Vref, RX VrefLevel [Byte0]: 68
1803 23:18:51.710202 [Byte1]: 68
1804 23:18:51.714647
1805 23:18:51.714766 Set Vref, RX VrefLevel [Byte0]: 69
1806 23:18:51.718361 [Byte1]: 69
1807 23:18:51.722159
1808 23:18:51.722279 Set Vref, RX VrefLevel [Byte0]: 70
1809 23:18:51.725467 [Byte1]: 70
1810 23:18:51.730165
1811 23:18:51.730285 Set Vref, RX VrefLevel [Byte0]: 71
1812 23:18:51.733409 [Byte1]: 71
1813 23:18:51.737527
1814 23:18:51.737648 Set Vref, RX VrefLevel [Byte0]: 72
1815 23:18:51.740601 [Byte1]: 72
1816 23:18:51.744898
1817 23:18:51.745026 Set Vref, RX VrefLevel [Byte0]: 73
1818 23:18:51.748569 [Byte1]: 73
1819 23:18:51.753164
1820 23:18:51.753285 Set Vref, RX VrefLevel [Byte0]: 74
1821 23:18:51.756530 [Byte1]: 74
1822 23:18:51.760193
1823 23:18:51.760315 Set Vref, RX VrefLevel [Byte0]: 75
1824 23:18:51.763897 [Byte1]: 75
1825 23:18:51.768096
1826 23:18:51.768218 Set Vref, RX VrefLevel [Byte0]: 76
1827 23:18:51.771346 [Byte1]: 76
1828 23:18:51.775827
1829 23:18:51.775950 Final RX Vref Byte 0 = 60 to rank0
1830 23:18:51.778654 Final RX Vref Byte 1 = 53 to rank0
1831 23:18:51.782042 Final RX Vref Byte 0 = 60 to rank1
1832 23:18:51.785509 Final RX Vref Byte 1 = 53 to rank1==
1833 23:18:51.789033 Dram Type= 6, Freq= 0, CH_1, rank 0
1834 23:18:51.795380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1835 23:18:51.795500 ==
1836 23:18:51.795614 DQS Delay:
1837 23:18:51.798676 DQS0 = 0, DQS1 = 0
1838 23:18:51.798803 DQM Delay:
1839 23:18:51.798916 DQM0 = 87, DQM1 = 81
1840 23:18:51.801973 DQ Delay:
1841 23:18:51.804949 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1842 23:18:51.808480 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1843 23:18:51.811771 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
1844 23:18:51.815064 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1845 23:18:51.815185
1846 23:18:51.815296
1847 23:18:51.821742 [DQSOSCAuto] RK0, (LSB)MR18= 0x192c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1848 23:18:51.824993 CH1 RK0: MR19=606, MR18=192C
1849 23:18:51.831826 CH1_RK0: MR19=0x606, MR18=0x192C, DQSOSC=398, MR23=63, INC=93, DEC=62
1850 23:18:51.831951
1851 23:18:51.834911 ----->DramcWriteLeveling(PI) begin...
1852 23:18:51.835043 ==
1853 23:18:51.838380 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 23:18:51.841693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 23:18:51.841815 ==
1856 23:18:51.845264 Write leveling (Byte 0): 29 => 29
1857 23:18:51.848073 Write leveling (Byte 1): 29 => 29
1858 23:18:51.851549 DramcWriteLeveling(PI) end<-----
1859 23:18:51.851679
1860 23:18:51.851788 ==
1861 23:18:51.854894 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 23:18:51.858519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1863 23:18:51.858650 ==
1864 23:18:51.861336 [Gating] SW mode calibration
1865 23:18:51.868354 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1866 23:18:51.874970 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1867 23:18:51.878119 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1868 23:18:51.885083 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1869 23:18:51.887958 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:18:51.891512 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:18:51.897915 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:18:51.901464 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:18:51.904908 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:18:51.908247 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:18:51.914535 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:18:51.918024 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:18:51.921498 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:18:51.927838 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:18:51.931160 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:18:51.934770 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:18:51.941417 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:18:51.944669 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:18:51.948193 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1884 23:18:51.954525 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1885 23:18:51.957590 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:18:51.961535 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:18:51.967647 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 23:18:51.971295 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 23:18:51.974318 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:18:51.980880 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:18:51.984466 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:18:51.987558 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1893 23:18:51.994549 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1894 23:18:51.998263 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 23:18:52.000864 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 23:18:52.007621 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 23:18:52.010801 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 23:18:52.014168 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 23:18:52.020643 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 23:18:52.024217 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (0 0) (1 0)
1901 23:18:52.027792 0 10 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1902 23:18:52.034252 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 23:18:52.037578 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 23:18:52.041165 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 23:18:52.047086 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 23:18:52.050983 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:18:52.054225 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 23:18:52.060579 0 11 4 | B1->B0 | 2525 3939 | 0 1 | (1 1) (0 0)
1909 23:18:52.064059 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1910 23:18:52.067108 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 23:18:52.074154 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 23:18:52.077305 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 23:18:52.081065 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 23:18:52.084074 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 23:18:52.090530 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 23:18:52.094141 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1917 23:18:52.097139 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:18:52.104166 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:18:52.107735 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:18:52.110534 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:18:52.116964 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:18:52.120472 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:18:52.123756 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:18:52.130594 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:18:52.133419 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 23:18:52.137310 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 23:18:52.143769 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 23:18:52.146745 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 23:18:52.150374 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:18:52.156867 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:18:52.160613 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 23:18:52.163562 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1933 23:18:52.167154 Total UI for P1: 0, mck2ui 16
1934 23:18:52.170493 best dqsien dly found for B0: ( 0, 14, 2)
1935 23:18:52.177214 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1936 23:18:52.180416 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 23:18:52.183540 Total UI for P1: 0, mck2ui 16
1938 23:18:52.186799 best dqsien dly found for B1: ( 0, 14, 6)
1939 23:18:52.190324 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1940 23:18:52.193271 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1941 23:18:52.193354
1942 23:18:52.196736 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1943 23:18:52.199978 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1944 23:18:52.203652 [Gating] SW calibration Done
1945 23:18:52.203734 ==
1946 23:18:52.206512 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 23:18:52.210036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 23:18:52.210140 ==
1949 23:18:52.213122 RX Vref Scan: 0
1950 23:18:52.213220
1951 23:18:52.216434 RX Vref 0 -> 0, step: 1
1952 23:18:52.216517
1953 23:18:52.216583 RX Delay -130 -> 252, step: 16
1954 23:18:52.223279 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1955 23:18:52.226701 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1956 23:18:52.230455 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1957 23:18:52.233406 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1958 23:18:52.236588 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1959 23:18:52.243226 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1960 23:18:52.246853 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1961 23:18:52.249793 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1962 23:18:52.253172 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1963 23:18:52.256498 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1964 23:18:52.263261 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1965 23:18:52.266164 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1966 23:18:52.269952 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1967 23:18:52.272946 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1968 23:18:52.279558 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1969 23:18:52.283057 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1970 23:18:52.283185 ==
1971 23:18:52.286401 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 23:18:52.289677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 23:18:52.289807 ==
1974 23:18:52.293120 DQS Delay:
1975 23:18:52.293302 DQS0 = 0, DQS1 = 0
1976 23:18:52.293445 DQM Delay:
1977 23:18:52.296008 DQM0 = 84, DQM1 = 84
1978 23:18:52.296135 DQ Delay:
1979 23:18:52.299355 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =77
1980 23:18:52.302579 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1981 23:18:52.305906 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =69
1982 23:18:52.309468 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1983 23:18:52.309591
1984 23:18:52.309699
1985 23:18:52.309810 ==
1986 23:18:52.312935 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 23:18:52.319537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 23:18:52.319669 ==
1989 23:18:52.319785
1990 23:18:52.319894
1991 23:18:52.320014 TX Vref Scan disable
1992 23:18:52.322497 == TX Byte 0 ==
1993 23:18:52.325959 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1994 23:18:52.329575 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1995 23:18:52.332842 == TX Byte 1 ==
1996 23:18:52.336091 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1997 23:18:52.339786 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1998 23:18:52.342655 ==
1999 23:18:52.345784 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 23:18:52.349007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 23:18:52.349091 ==
2002 23:18:52.361416 TX Vref=22, minBit 2, minWin=26, winSum=442
2003 23:18:52.364808 TX Vref=24, minBit 1, minWin=27, winSum=447
2004 23:18:52.368581 TX Vref=26, minBit 3, minWin=26, winSum=445
2005 23:18:52.371325 TX Vref=28, minBit 0, minWin=27, winSum=451
2006 23:18:52.374814 TX Vref=30, minBit 2, minWin=27, winSum=454
2007 23:18:52.381371 TX Vref=32, minBit 0, minWin=27, winSum=451
2008 23:18:52.384970 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 30
2009 23:18:52.385052
2010 23:18:52.388268 Final TX Range 1 Vref 30
2011 23:18:52.388373
2012 23:18:52.388445 ==
2013 23:18:52.391284 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 23:18:52.394717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 23:18:52.394829 ==
2016 23:18:52.398212
2017 23:18:52.398331
2018 23:18:52.398395 TX Vref Scan disable
2019 23:18:52.401562 == TX Byte 0 ==
2020 23:18:52.404659 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2021 23:18:52.411518 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2022 23:18:52.411635 == TX Byte 1 ==
2023 23:18:52.414842 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2024 23:18:52.421565 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2025 23:18:52.421676
2026 23:18:52.421772 [DATLAT]
2027 23:18:52.421864 Freq=800, CH1 RK1
2028 23:18:52.421954
2029 23:18:52.424715 DATLAT Default: 0xa
2030 23:18:52.424798 0, 0xFFFF, sum = 0
2031 23:18:52.427717 1, 0xFFFF, sum = 0
2032 23:18:52.427803 2, 0xFFFF, sum = 0
2033 23:18:52.431158 3, 0xFFFF, sum = 0
2034 23:18:52.434789 4, 0xFFFF, sum = 0
2035 23:18:52.434873 5, 0xFFFF, sum = 0
2036 23:18:52.437997 6, 0xFFFF, sum = 0
2037 23:18:52.438081 7, 0xFFFF, sum = 0
2038 23:18:52.441299 8, 0xFFFF, sum = 0
2039 23:18:52.441392 9, 0x0, sum = 1
2040 23:18:52.441490 10, 0x0, sum = 2
2041 23:18:52.444759 11, 0x0, sum = 3
2042 23:18:52.444846 12, 0x0, sum = 4
2043 23:18:52.448000 best_step = 10
2044 23:18:52.448084
2045 23:18:52.448151 ==
2046 23:18:52.451171 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 23:18:52.454449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 23:18:52.454534 ==
2049 23:18:52.458160 RX Vref Scan: 0
2050 23:18:52.458245
2051 23:18:52.458312 RX Vref 0 -> 0, step: 1
2052 23:18:52.461049
2053 23:18:52.461133 RX Delay -95 -> 252, step: 8
2054 23:18:52.468194 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2055 23:18:52.472117 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2056 23:18:52.475147 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2057 23:18:52.478045 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
2058 23:18:52.481055 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2059 23:18:52.487823 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2060 23:18:52.491234 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2061 23:18:52.494567 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2062 23:18:52.497894 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2063 23:18:52.501403 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2064 23:18:52.508321 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2065 23:18:52.511202 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2066 23:18:52.515112 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2067 23:18:52.518005 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2068 23:18:52.524573 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2069 23:18:52.527764 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2070 23:18:52.527848 ==
2071 23:18:52.531263 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 23:18:52.534522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 23:18:52.534604 ==
2074 23:18:52.534669 DQS Delay:
2075 23:18:52.537832 DQS0 = 0, DQS1 = 0
2076 23:18:52.537915 DQM Delay:
2077 23:18:52.540928 DQM0 = 88, DQM1 = 82
2078 23:18:52.541010 DQ Delay:
2079 23:18:52.544511 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2080 23:18:52.547692 DQ4 =88, DQ5 =100, DQ6 =96, DQ7 =84
2081 23:18:52.551234 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =76
2082 23:18:52.554403 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =88
2083 23:18:52.554485
2084 23:18:52.554551
2085 23:18:52.564260 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 402 ps
2086 23:18:52.564347 CH1 RK1: MR19=606, MR18=1F3B
2087 23:18:52.570990 CH1_RK1: MR19=0x606, MR18=0x1F3B, DQSOSC=394, MR23=63, INC=95, DEC=63
2088 23:18:52.574117 [RxdqsGatingPostProcess] freq 800
2089 23:18:52.580907 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 23:18:52.584175 Pre-setting of DQS Precalculation
2091 23:18:52.587296 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 23:18:52.594618 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 23:18:52.603997 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 23:18:52.604081
2095 23:18:52.604161
2096 23:18:52.607255 [Calibration Summary] 1600 Mbps
2097 23:18:52.607372 CH 0, Rank 0
2098 23:18:52.611218 SW Impedance : PASS
2099 23:18:52.611328 DUTY Scan : NO K
2100 23:18:52.613613 ZQ Calibration : PASS
2101 23:18:52.617327 Jitter Meter : NO K
2102 23:18:52.617409 CBT Training : PASS
2103 23:18:52.620408 Write leveling : PASS
2104 23:18:52.623539 RX DQS gating : PASS
2105 23:18:52.623620 RX DQ/DQS(RDDQC) : PASS
2106 23:18:52.626800 TX DQ/DQS : PASS
2107 23:18:52.630301 RX DATLAT : PASS
2108 23:18:52.630389 RX DQ/DQS(Engine): PASS
2109 23:18:52.633881 TX OE : NO K
2110 23:18:52.633958 All Pass.
2111 23:18:52.634025
2112 23:18:52.636556 CH 0, Rank 1
2113 23:18:52.636630 SW Impedance : PASS
2114 23:18:52.640124 DUTY Scan : NO K
2115 23:18:52.640195 ZQ Calibration : PASS
2116 23:18:52.644107 Jitter Meter : NO K
2117 23:18:52.646826 CBT Training : PASS
2118 23:18:52.646923 Write leveling : PASS
2119 23:18:52.650123 RX DQS gating : PASS
2120 23:18:52.653564 RX DQ/DQS(RDDQC) : PASS
2121 23:18:52.653647 TX DQ/DQS : PASS
2122 23:18:52.657007 RX DATLAT : PASS
2123 23:18:52.660506 RX DQ/DQS(Engine): PASS
2124 23:18:52.660596 TX OE : NO K
2125 23:18:52.663268 All Pass.
2126 23:18:52.663390
2127 23:18:52.663470 CH 1, Rank 0
2128 23:18:52.666499 SW Impedance : PASS
2129 23:18:52.666597 DUTY Scan : NO K
2130 23:18:52.669795 ZQ Calibration : PASS
2131 23:18:52.673555 Jitter Meter : NO K
2132 23:18:52.673651 CBT Training : PASS
2133 23:18:52.676948 Write leveling : PASS
2134 23:18:52.679914 RX DQS gating : PASS
2135 23:18:52.680026 RX DQ/DQS(RDDQC) : PASS
2136 23:18:52.683040 TX DQ/DQS : PASS
2137 23:18:52.686565 RX DATLAT : PASS
2138 23:18:52.686642 RX DQ/DQS(Engine): PASS
2139 23:18:52.689792 TX OE : NO K
2140 23:18:52.689864 All Pass.
2141 23:18:52.689926
2142 23:18:52.693053 CH 1, Rank 1
2143 23:18:52.693163 SW Impedance : PASS
2144 23:18:52.696289 DUTY Scan : NO K
2145 23:18:52.699372 ZQ Calibration : PASS
2146 23:18:52.699457 Jitter Meter : NO K
2147 23:18:52.703030 CBT Training : PASS
2148 23:18:52.703102 Write leveling : PASS
2149 23:18:52.706171 RX DQS gating : PASS
2150 23:18:52.709737 RX DQ/DQS(RDDQC) : PASS
2151 23:18:52.709846 TX DQ/DQS : PASS
2152 23:18:52.712906 RX DATLAT : PASS
2153 23:18:52.716141 RX DQ/DQS(Engine): PASS
2154 23:18:52.716232 TX OE : NO K
2155 23:18:52.719665 All Pass.
2156 23:18:52.719744
2157 23:18:52.719810 DramC Write-DBI off
2158 23:18:52.723103 PER_BANK_REFRESH: Hybrid Mode
2159 23:18:52.725904 TX_TRACKING: ON
2160 23:18:52.729893 [GetDramInforAfterCalByMRR] Vendor 6.
2161 23:18:52.732972 [GetDramInforAfterCalByMRR] Revision 606.
2162 23:18:52.736160 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 23:18:52.736245 MR0 0x3b3b
2164 23:18:52.736311 MR8 0x5151
2165 23:18:52.743078 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 23:18:52.743157
2167 23:18:52.743223 MR0 0x3b3b
2168 23:18:52.743283 MR8 0x5151
2169 23:18:52.745725 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 23:18:52.745807
2171 23:18:52.755769 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 23:18:52.759820 [FAST_K] Save calibration result to emmc
2173 23:18:52.762515 [FAST_K] Save calibration result to emmc
2174 23:18:52.765913 dram_init: config_dvfs: 1
2175 23:18:52.769180 dramc_set_vcore_voltage set vcore to 662500
2176 23:18:52.772468 Read voltage for 1200, 2
2177 23:18:52.772550 Vio18 = 0
2178 23:18:52.772629 Vcore = 662500
2179 23:18:52.775885 Vdram = 0
2180 23:18:52.775970 Vddq = 0
2181 23:18:52.776037 Vmddr = 0
2182 23:18:52.782441 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 23:18:52.786334 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 23:18:52.789221 MEM_TYPE=3, freq_sel=15
2185 23:18:52.792667 sv_algorithm_assistance_LP4_1600
2186 23:18:52.796072 ============ PULL DRAM RESETB DOWN ============
2187 23:18:52.799287 ========== PULL DRAM RESETB DOWN end =========
2188 23:18:52.806198 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 23:18:52.809403 ===================================
2190 23:18:52.812525 LPDDR4 DRAM CONFIGURATION
2191 23:18:52.815765 ===================================
2192 23:18:52.815850 EX_ROW_EN[0] = 0x0
2193 23:18:52.819373 EX_ROW_EN[1] = 0x0
2194 23:18:52.819458 LP4Y_EN = 0x0
2195 23:18:52.822794 WORK_FSP = 0x0
2196 23:18:52.822872 WL = 0x4
2197 23:18:52.825826 RL = 0x4
2198 23:18:52.825911 BL = 0x2
2199 23:18:52.829121 RPST = 0x0
2200 23:18:52.829209 RD_PRE = 0x0
2201 23:18:52.832235 WR_PRE = 0x1
2202 23:18:52.832320 WR_PST = 0x0
2203 23:18:52.835863 DBI_WR = 0x0
2204 23:18:52.835944 DBI_RD = 0x0
2205 23:18:52.839193 OTF = 0x1
2206 23:18:52.842829 ===================================
2207 23:18:52.845681 ===================================
2208 23:18:52.845766 ANA top config
2209 23:18:52.849568 ===================================
2210 23:18:52.852508 DLL_ASYNC_EN = 0
2211 23:18:52.855474 ALL_SLAVE_EN = 0
2212 23:18:52.858751 NEW_RANK_MODE = 1
2213 23:18:52.858837 DLL_IDLE_MODE = 1
2214 23:18:52.862254 LP45_APHY_COMB_EN = 1
2215 23:18:52.865845 TX_ODT_DIS = 1
2216 23:18:52.868951 NEW_8X_MODE = 1
2217 23:18:52.872321 ===================================
2218 23:18:52.875709 ===================================
2219 23:18:52.879308 data_rate = 2400
2220 23:18:52.879401 CKR = 1
2221 23:18:52.882310 DQ_P2S_RATIO = 8
2222 23:18:52.885603 ===================================
2223 23:18:52.889397 CA_P2S_RATIO = 8
2224 23:18:52.892192 DQ_CA_OPEN = 0
2225 23:18:52.895379 DQ_SEMI_OPEN = 0
2226 23:18:52.898992 CA_SEMI_OPEN = 0
2227 23:18:52.899077 CA_FULL_RATE = 0
2228 23:18:52.902034 DQ_CKDIV4_EN = 0
2229 23:18:52.905343 CA_CKDIV4_EN = 0
2230 23:18:52.908470 CA_PREDIV_EN = 0
2231 23:18:52.912172 PH8_DLY = 17
2232 23:18:52.915260 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 23:18:52.918437 DQ_AAMCK_DIV = 4
2234 23:18:52.918520 CA_AAMCK_DIV = 4
2235 23:18:52.921845 CA_ADMCK_DIV = 4
2236 23:18:52.925364 DQ_TRACK_CA_EN = 0
2237 23:18:52.928851 CA_PICK = 1200
2238 23:18:52.931853 CA_MCKIO = 1200
2239 23:18:52.935210 MCKIO_SEMI = 0
2240 23:18:52.938950 PLL_FREQ = 2366
2241 23:18:52.939058 DQ_UI_PI_RATIO = 32
2242 23:18:52.941649 CA_UI_PI_RATIO = 0
2243 23:18:52.945154 ===================================
2244 23:18:52.948707 ===================================
2245 23:18:52.952060 memory_type:LPDDR4
2246 23:18:52.955097 GP_NUM : 10
2247 23:18:52.955180 SRAM_EN : 1
2248 23:18:52.958563 MD32_EN : 0
2249 23:18:52.962239 ===================================
2250 23:18:52.962321 [ANA_INIT] >>>>>>>>>>>>>>
2251 23:18:52.964847 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 23:18:52.969196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 23:18:52.971750 ===================================
2254 23:18:52.975153 data_rate = 2400,PCW = 0X5b00
2255 23:18:52.978511 ===================================
2256 23:18:52.981593 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 23:18:52.988135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 23:18:52.994736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 23:18:52.998269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 23:18:53.001603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 23:18:53.004822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 23:18:53.008051 [ANA_INIT] flow start
2263 23:18:53.008133 [ANA_INIT] PLL >>>>>>>>
2264 23:18:53.011605 [ANA_INIT] PLL <<<<<<<<
2265 23:18:53.014716 [ANA_INIT] MIDPI >>>>>>>>
2266 23:18:53.014799 [ANA_INIT] MIDPI <<<<<<<<
2267 23:18:53.018183 [ANA_INIT] DLL >>>>>>>>
2268 23:18:53.021586 [ANA_INIT] DLL <<<<<<<<
2269 23:18:53.021668 [ANA_INIT] flow end
2270 23:18:53.028417 ============ LP4 DIFF to SE enter ============
2271 23:18:53.031297 ============ LP4 DIFF to SE exit ============
2272 23:18:53.034999 [ANA_INIT] <<<<<<<<<<<<<
2273 23:18:53.038056 [Flow] Enable top DCM control >>>>>
2274 23:18:53.041107 [Flow] Enable top DCM control <<<<<
2275 23:18:53.041191 Enable DLL master slave shuffle
2276 23:18:53.047985 ==============================================================
2277 23:18:53.051418 Gating Mode config
2278 23:18:53.054589 ==============================================================
2279 23:18:53.057973 Config description:
2280 23:18:53.068071 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 23:18:53.075077 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 23:18:53.077839 SELPH_MODE 0: By rank 1: By Phase
2283 23:18:53.084764 ==============================================================
2284 23:18:53.087899 GAT_TRACK_EN = 1
2285 23:18:53.091258 RX_GATING_MODE = 2
2286 23:18:53.094603 RX_GATING_TRACK_MODE = 2
2287 23:18:53.094727 SELPH_MODE = 1
2288 23:18:53.097819 PICG_EARLY_EN = 1
2289 23:18:53.101232 VALID_LAT_VALUE = 1
2290 23:18:53.108007 ==============================================================
2291 23:18:53.111158 Enter into Gating configuration >>>>
2292 23:18:53.114166 Exit from Gating configuration <<<<
2293 23:18:53.117305 Enter into DVFS_PRE_config >>>>>
2294 23:18:53.127902 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 23:18:53.130613 Exit from DVFS_PRE_config <<<<<
2296 23:18:53.134173 Enter into PICG configuration >>>>
2297 23:18:53.137623 Exit from PICG configuration <<<<
2298 23:18:53.140782 [RX_INPUT] configuration >>>>>
2299 23:18:53.144212 [RX_INPUT] configuration <<<<<
2300 23:18:53.147351 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 23:18:53.154312 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 23:18:53.160904 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 23:18:53.167299 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 23:18:53.174137 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 23:18:53.177253 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 23:18:53.184408 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 23:18:53.187478 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 23:18:53.190639 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 23:18:53.193925 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 23:18:53.200667 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 23:18:53.204393 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 23:18:53.207358 ===================================
2313 23:18:53.210465 LPDDR4 DRAM CONFIGURATION
2314 23:18:53.213983 ===================================
2315 23:18:53.214065 EX_ROW_EN[0] = 0x0
2316 23:18:53.217203 EX_ROW_EN[1] = 0x0
2317 23:18:53.217285 LP4Y_EN = 0x0
2318 23:18:53.220745 WORK_FSP = 0x0
2319 23:18:53.220829 WL = 0x4
2320 23:18:53.223915 RL = 0x4
2321 23:18:53.224001 BL = 0x2
2322 23:18:53.227461 RPST = 0x0
2323 23:18:53.227543 RD_PRE = 0x0
2324 23:18:53.230715 WR_PRE = 0x1
2325 23:18:53.230838 WR_PST = 0x0
2326 23:18:53.233945 DBI_WR = 0x0
2327 23:18:53.237524 DBI_RD = 0x0
2328 23:18:53.237648 OTF = 0x1
2329 23:18:53.240554 ===================================
2330 23:18:53.243820 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 23:18:53.247506 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 23:18:53.254146 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 23:18:53.257285 ===================================
2334 23:18:53.257368 LPDDR4 DRAM CONFIGURATION
2335 23:18:53.260289 ===================================
2336 23:18:53.263942 EX_ROW_EN[0] = 0x10
2337 23:18:53.267058 EX_ROW_EN[1] = 0x0
2338 23:18:53.267180 LP4Y_EN = 0x0
2339 23:18:53.270440 WORK_FSP = 0x0
2340 23:18:53.270562 WL = 0x4
2341 23:18:53.273730 RL = 0x4
2342 23:18:53.273853 BL = 0x2
2343 23:18:53.277136 RPST = 0x0
2344 23:18:53.277256 RD_PRE = 0x0
2345 23:18:53.280616 WR_PRE = 0x1
2346 23:18:53.280739 WR_PST = 0x0
2347 23:18:53.283780 DBI_WR = 0x0
2348 23:18:53.283904 DBI_RD = 0x0
2349 23:18:53.287194 OTF = 0x1
2350 23:18:53.290652 ===================================
2351 23:18:53.297117 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 23:18:53.297242 ==
2353 23:18:53.300540 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 23:18:53.303935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 23:18:53.304061 ==
2356 23:18:53.306851 [Duty_Offset_Calibration]
2357 23:18:53.306974 B0:2 B1:0 CA:4
2358 23:18:53.307082
2359 23:18:53.310400 [DutyScan_Calibration_Flow] k_type=0
2360 23:18:53.320168
2361 23:18:53.320295 ==CLK 0==
2362 23:18:53.323143 Final CLK duty delay cell = -4
2363 23:18:53.326809 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2364 23:18:53.329862 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2365 23:18:53.333223 [-4] AVG Duty = 4937%(X100)
2366 23:18:53.333341
2367 23:18:53.336576 CH0 CLK Duty spec in!! Max-Min= 187%
2368 23:18:53.340030 [DutyScan_Calibration_Flow] ====Done====
2369 23:18:53.340154
2370 23:18:53.343686 [DutyScan_Calibration_Flow] k_type=1
2371 23:18:53.359616
2372 23:18:53.359744 ==DQS 0 ==
2373 23:18:53.363094 Final DQS duty delay cell = 0
2374 23:18:53.366568 [0] MAX Duty = 5156%(X100), DQS PI = 18
2375 23:18:53.370061 [0] MIN Duty = 5093%(X100), DQS PI = 0
2376 23:18:53.370197 [0] AVG Duty = 5124%(X100)
2377 23:18:53.372937
2378 23:18:53.373020 ==DQS 1 ==
2379 23:18:53.376652 Final DQS duty delay cell = 0
2380 23:18:53.379565 [0] MAX Duty = 5093%(X100), DQS PI = 4
2381 23:18:53.382818 [0] MIN Duty = 5000%(X100), DQS PI = 0
2382 23:18:53.382902 [0] AVG Duty = 5046%(X100)
2383 23:18:53.382969
2384 23:18:53.389334 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2385 23:18:53.389442
2386 23:18:53.392738 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2387 23:18:53.396058 [DutyScan_Calibration_Flow] ====Done====
2388 23:18:53.396137
2389 23:18:53.399512 [DutyScan_Calibration_Flow] k_type=3
2390 23:18:53.415875
2391 23:18:53.415988 ==DQM 0 ==
2392 23:18:53.419378 Final DQM duty delay cell = 0
2393 23:18:53.422699 [0] MAX Duty = 5094%(X100), DQS PI = 20
2394 23:18:53.426214 [0] MIN Duty = 4844%(X100), DQS PI = 50
2395 23:18:53.429051 [0] AVG Duty = 4969%(X100)
2396 23:18:53.429133
2397 23:18:53.429198 ==DQM 1 ==
2398 23:18:53.432393 Final DQM duty delay cell = 0
2399 23:18:53.435951 [0] MAX Duty = 5000%(X100), DQS PI = 6
2400 23:18:53.438825 [0] MIN Duty = 4875%(X100), DQS PI = 14
2401 23:18:53.442326 [0] AVG Duty = 4937%(X100)
2402 23:18:53.442410
2403 23:18:53.445915 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2404 23:18:53.446069
2405 23:18:53.449074 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2406 23:18:53.452252 [DutyScan_Calibration_Flow] ====Done====
2407 23:18:53.452334
2408 23:18:53.455634 [DutyScan_Calibration_Flow] k_type=2
2409 23:18:53.472160
2410 23:18:53.472280 ==DQ 0 ==
2411 23:18:53.475673 Final DQ duty delay cell = 0
2412 23:18:53.479037 [0] MAX Duty = 5156%(X100), DQS PI = 18
2413 23:18:53.482008 [0] MIN Duty = 4969%(X100), DQS PI = 50
2414 23:18:53.482115 [0] AVG Duty = 5062%(X100)
2415 23:18:53.485500
2416 23:18:53.485602 ==DQ 1 ==
2417 23:18:53.488604 Final DQ duty delay cell = 0
2418 23:18:53.491974 [0] MAX Duty = 5125%(X100), DQS PI = 4
2419 23:18:53.495706 [0] MIN Duty = 4938%(X100), DQS PI = 14
2420 23:18:53.495815 [0] AVG Duty = 5031%(X100)
2421 23:18:53.495910
2422 23:18:53.499098 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2423 23:18:53.502010
2424 23:18:53.506018 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2425 23:18:53.508693 [DutyScan_Calibration_Flow] ====Done====
2426 23:18:53.508836 ==
2427 23:18:53.512548 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 23:18:53.515991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 23:18:53.516093 ==
2430 23:18:53.518735 [Duty_Offset_Calibration]
2431 23:18:53.518834 B0:0 B1:-1 CA:3
2432 23:18:53.518925
2433 23:18:53.522201 [DutyScan_Calibration_Flow] k_type=0
2434 23:18:53.532078
2435 23:18:53.532161 ==CLK 0==
2436 23:18:53.535595 Final CLK duty delay cell = 0
2437 23:18:53.538802 [0] MAX Duty = 5156%(X100), DQS PI = 12
2438 23:18:53.542187 [0] MIN Duty = 5000%(X100), DQS PI = 2
2439 23:18:53.542292 [0] AVG Duty = 5078%(X100)
2440 23:18:53.545815
2441 23:18:53.548812 CH1 CLK Duty spec in!! Max-Min= 156%
2442 23:18:53.552114 [DutyScan_Calibration_Flow] ====Done====
2443 23:18:53.552187
2444 23:18:53.555240 [DutyScan_Calibration_Flow] k_type=1
2445 23:18:53.571725
2446 23:18:53.571835 ==DQS 0 ==
2447 23:18:53.574841 Final DQS duty delay cell = 0
2448 23:18:53.578074 [0] MAX Duty = 5187%(X100), DQS PI = 50
2449 23:18:53.581434 [0] MIN Duty = 4907%(X100), DQS PI = 6
2450 23:18:53.581513 [0] AVG Duty = 5047%(X100)
2451 23:18:53.584967
2452 23:18:53.585039 ==DQS 1 ==
2453 23:18:53.588143 Final DQS duty delay cell = 0
2454 23:18:53.591886 [0] MAX Duty = 5156%(X100), DQS PI = 28
2455 23:18:53.594945 [0] MIN Duty = 5000%(X100), DQS PI = 58
2456 23:18:53.597900 [0] AVG Duty = 5078%(X100)
2457 23:18:53.597973
2458 23:18:53.601566 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2459 23:18:53.601664
2460 23:18:53.604739 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2461 23:18:53.608113 [DutyScan_Calibration_Flow] ====Done====
2462 23:18:53.608260
2463 23:18:53.611371 [DutyScan_Calibration_Flow] k_type=3
2464 23:18:53.628216
2465 23:18:53.628295 ==DQM 0 ==
2466 23:18:53.631055 Final DQM duty delay cell = 0
2467 23:18:53.635271 [0] MAX Duty = 5031%(X100), DQS PI = 60
2468 23:18:53.637774 [0] MIN Duty = 4813%(X100), DQS PI = 6
2469 23:18:53.641173 [0] AVG Duty = 4922%(X100)
2470 23:18:53.641273
2471 23:18:53.641363 ==DQM 1 ==
2472 23:18:53.644439 Final DQM duty delay cell = 0
2473 23:18:53.647844 [0] MAX Duty = 4969%(X100), DQS PI = 2
2474 23:18:53.651051 [0] MIN Duty = 4844%(X100), DQS PI = 30
2475 23:18:53.654514 [0] AVG Duty = 4906%(X100)
2476 23:18:53.654588
2477 23:18:53.657732 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2478 23:18:53.657803
2479 23:18:53.661499 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2480 23:18:53.664271 [DutyScan_Calibration_Flow] ====Done====
2481 23:18:53.664385
2482 23:18:53.667914 [DutyScan_Calibration_Flow] k_type=2
2483 23:18:53.684618
2484 23:18:53.684726 ==DQ 0 ==
2485 23:18:53.687890 Final DQ duty delay cell = -4
2486 23:18:53.690830 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2487 23:18:53.694477 [-4] MIN Duty = 4844%(X100), DQS PI = 4
2488 23:18:53.697597 [-4] AVG Duty = 4922%(X100)
2489 23:18:53.697711
2490 23:18:53.697827 ==DQ 1 ==
2491 23:18:53.700694 Final DQ duty delay cell = 4
2492 23:18:53.704353 [4] MAX Duty = 5156%(X100), DQS PI = 0
2493 23:18:53.708300 [4] MIN Duty = 5062%(X100), DQS PI = 8
2494 23:18:53.708376 [4] AVG Duty = 5109%(X100)
2495 23:18:53.708457
2496 23:18:53.714573 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2497 23:18:53.714700
2498 23:18:53.718057 CH1 DQ 1 Duty spec in!! Max-Min= 94%
2499 23:18:53.720890 [DutyScan_Calibration_Flow] ====Done====
2500 23:18:53.724440 nWR fixed to 30
2501 23:18:53.724564 [ModeRegInit_LP4] CH0 RK0
2502 23:18:53.727457 [ModeRegInit_LP4] CH0 RK1
2503 23:18:53.731179 [ModeRegInit_LP4] CH1 RK0
2504 23:18:53.731301 [ModeRegInit_LP4] CH1 RK1
2505 23:18:53.734330 match AC timing 7
2506 23:18:53.737901 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 23:18:53.741115 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 23:18:53.747600 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 23:18:53.751176 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 23:18:53.757542 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 23:18:53.757656 ==
2512 23:18:53.760967 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 23:18:53.764308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 23:18:53.764393 ==
2515 23:18:53.770899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 23:18:53.777067 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2517 23:18:53.784572 [CA 0] Center 39 (9~70) winsize 62
2518 23:18:53.788189 [CA 1] Center 39 (9~69) winsize 61
2519 23:18:53.791323 [CA 2] Center 35 (5~66) winsize 62
2520 23:18:53.794575 [CA 3] Center 35 (5~66) winsize 62
2521 23:18:53.797903 [CA 4] Center 33 (3~64) winsize 62
2522 23:18:53.800881 [CA 5] Center 33 (3~63) winsize 61
2523 23:18:53.801008
2524 23:18:53.804325 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2525 23:18:53.804448
2526 23:18:53.807435 [CATrainingPosCal] consider 1 rank data
2527 23:18:53.811017 u2DelayCellTimex100 = 270/100 ps
2528 23:18:53.814883 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2529 23:18:53.817748 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2530 23:18:53.824103 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2531 23:18:53.827475 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2532 23:18:53.830709 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2533 23:18:53.834772 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2534 23:18:53.834857
2535 23:18:53.837512 CA PerBit enable=1, Macro0, CA PI delay=33
2536 23:18:53.837607
2537 23:18:53.840779 [CBTSetCACLKResult] CA Dly = 33
2538 23:18:53.840890 CS Dly: 7 (0~38)
2539 23:18:53.843875 ==
2540 23:18:53.847121 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 23:18:53.850482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 23:18:53.850622 ==
2543 23:18:53.853868 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 23:18:53.860627 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2545 23:18:53.869952 [CA 0] Center 39 (9~70) winsize 62
2546 23:18:53.873150 [CA 1] Center 39 (9~70) winsize 62
2547 23:18:53.876425 [CA 2] Center 35 (5~66) winsize 62
2548 23:18:53.879977 [CA 3] Center 35 (5~66) winsize 62
2549 23:18:53.883303 [CA 4] Center 34 (4~65) winsize 62
2550 23:18:53.886545 [CA 5] Center 33 (3~64) winsize 62
2551 23:18:53.886666
2552 23:18:53.889772 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2553 23:18:53.889909
2554 23:18:53.893423 [CATrainingPosCal] consider 2 rank data
2555 23:18:53.896364 u2DelayCellTimex100 = 270/100 ps
2556 23:18:53.899548 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2557 23:18:53.906092 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2558 23:18:53.909834 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2559 23:18:53.913156 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2560 23:18:53.916249 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2561 23:18:53.919735 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2562 23:18:53.919817
2563 23:18:53.922770 CA PerBit enable=1, Macro0, CA PI delay=33
2564 23:18:53.922848
2565 23:18:53.926007 [CBTSetCACLKResult] CA Dly = 33
2566 23:18:53.929214 CS Dly: 8 (0~41)
2567 23:18:53.929345
2568 23:18:53.932912 ----->DramcWriteLeveling(PI) begin...
2569 23:18:53.933037 ==
2570 23:18:53.935803 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 23:18:53.939620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 23:18:53.939751 ==
2573 23:18:53.943154 Write leveling (Byte 0): 31 => 31
2574 23:18:53.945911 Write leveling (Byte 1): 27 => 27
2575 23:18:53.949140 DramcWriteLeveling(PI) end<-----
2576 23:18:53.949264
2577 23:18:53.949378 ==
2578 23:18:53.952353 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 23:18:53.955839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 23:18:53.955965 ==
2581 23:18:53.959273 [Gating] SW mode calibration
2582 23:18:53.965578 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 23:18:53.972241 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 23:18:53.975557 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2585 23:18:53.978887 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2586 23:18:53.985761 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 23:18:53.988898 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 23:18:53.992604 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 23:18:53.998849 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 23:18:54.002299 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 23:18:54.005568 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
2592 23:18:54.012259 1 0 0 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2593 23:18:54.015840 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2594 23:18:54.018884 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 23:18:54.025442 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 23:18:54.028756 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 23:18:54.032499 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 23:18:54.038601 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2599 23:18:54.042331 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2600 23:18:54.045577 1 1 0 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
2601 23:18:54.051915 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
2602 23:18:54.055133 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 23:18:54.058877 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 23:18:54.065065 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 23:18:54.068714 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 23:18:54.071596 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 23:18:54.078774 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 23:18:54.081707 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2609 23:18:54.084987 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2610 23:18:54.091769 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:18:54.094665 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:18:54.098325 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:18:54.104633 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:18:54.108254 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:18:54.111423 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:18:54.118115 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 23:18:54.121890 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 23:18:54.124951 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 23:18:54.128292 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 23:18:54.134803 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 23:18:54.138209 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 23:18:54.141516 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2623 23:18:54.148000 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2624 23:18:54.151574 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2625 23:18:54.155137 Total UI for P1: 0, mck2ui 16
2626 23:18:54.157876 best dqsien dly found for B0: ( 1, 3, 26)
2627 23:18:54.161203 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 23:18:54.164936 Total UI for P1: 0, mck2ui 16
2629 23:18:54.167903 best dqsien dly found for B1: ( 1, 4, 0)
2630 23:18:54.171123 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2631 23:18:54.174913 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2632 23:18:54.177699
2633 23:18:54.181305 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2634 23:18:54.184280 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2635 23:18:54.187550 [Gating] SW calibration Done
2636 23:18:54.187630 ==
2637 23:18:54.190990 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 23:18:54.194975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 23:18:54.195054 ==
2640 23:18:54.195119 RX Vref Scan: 0
2641 23:18:54.195181
2642 23:18:54.197770 RX Vref 0 -> 0, step: 1
2643 23:18:54.197848
2644 23:18:54.201138 RX Delay -40 -> 252, step: 8
2645 23:18:54.204290 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2646 23:18:54.207786 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2647 23:18:54.214586 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2648 23:18:54.217925 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2649 23:18:54.221234 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2650 23:18:54.224629 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2651 23:18:54.227786 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2652 23:18:54.231113 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2653 23:18:54.238441 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2654 23:18:54.241490 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2655 23:18:54.244859 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2656 23:18:54.247644 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2657 23:18:54.251372 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2658 23:18:54.257861 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2659 23:18:54.261039 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2660 23:18:54.264255 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2661 23:18:54.264337 ==
2662 23:18:54.268184 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 23:18:54.270817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 23:18:54.274119 ==
2665 23:18:54.274199 DQS Delay:
2666 23:18:54.274265 DQS0 = 0, DQS1 = 0
2667 23:18:54.277772 DQM Delay:
2668 23:18:54.277849 DQM0 = 118, DQM1 = 107
2669 23:18:54.280913 DQ Delay:
2670 23:18:54.283959 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2671 23:18:54.287447 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2672 23:18:54.290546 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2673 23:18:54.294222 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2674 23:18:54.294301
2675 23:18:54.294369
2676 23:18:54.294430 ==
2677 23:18:54.297063 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 23:18:54.300583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 23:18:54.300662 ==
2680 23:18:54.303964
2681 23:18:54.304040
2682 23:18:54.304125 TX Vref Scan disable
2683 23:18:54.307004 == TX Byte 0 ==
2684 23:18:54.310692 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2685 23:18:54.314017 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2686 23:18:54.316993 == TX Byte 1 ==
2687 23:18:54.320432 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2688 23:18:54.323848 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2689 23:18:54.323928 ==
2690 23:18:54.327462 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 23:18:54.333738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 23:18:54.333822 ==
2693 23:18:54.344648 TX Vref=22, minBit 3, minWin=25, winSum=409
2694 23:18:54.348405 TX Vref=24, minBit 1, minWin=25, winSum=412
2695 23:18:54.351444 TX Vref=26, minBit 1, minWin=26, winSum=424
2696 23:18:54.354617 TX Vref=28, minBit 5, minWin=26, winSum=428
2697 23:18:54.357593 TX Vref=30, minBit 3, minWin=26, winSum=429
2698 23:18:54.364471 TX Vref=32, minBit 5, minWin=25, winSum=423
2699 23:18:54.367500 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 30
2700 23:18:54.367610
2701 23:18:54.371091 Final TX Range 1 Vref 30
2702 23:18:54.371172
2703 23:18:54.371237 ==
2704 23:18:54.374286 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 23:18:54.377854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 23:18:54.377933 ==
2707 23:18:54.380965
2708 23:18:54.381041
2709 23:18:54.381104 TX Vref Scan disable
2710 23:18:54.384577 == TX Byte 0 ==
2711 23:18:54.388084 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2712 23:18:54.394054 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2713 23:18:54.394138 == TX Byte 1 ==
2714 23:18:54.397418 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2715 23:18:54.404004 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2716 23:18:54.404085
2717 23:18:54.404150 [DATLAT]
2718 23:18:54.404212 Freq=1200, CH0 RK0
2719 23:18:54.404271
2720 23:18:54.407429 DATLAT Default: 0xd
2721 23:18:54.407509 0, 0xFFFF, sum = 0
2722 23:18:54.410772 1, 0xFFFF, sum = 0
2723 23:18:54.410847 2, 0xFFFF, sum = 0
2724 23:18:54.413970 3, 0xFFFF, sum = 0
2725 23:18:54.417993 4, 0xFFFF, sum = 0
2726 23:18:54.418079 5, 0xFFFF, sum = 0
2727 23:18:54.421029 6, 0xFFFF, sum = 0
2728 23:18:54.421109 7, 0xFFFF, sum = 0
2729 23:18:54.424454 8, 0xFFFF, sum = 0
2730 23:18:54.424530 9, 0xFFFF, sum = 0
2731 23:18:54.427342 10, 0xFFFF, sum = 0
2732 23:18:54.427455 11, 0xFFFF, sum = 0
2733 23:18:54.430634 12, 0x0, sum = 1
2734 23:18:54.430712 13, 0x0, sum = 2
2735 23:18:54.434011 14, 0x0, sum = 3
2736 23:18:54.434086 15, 0x0, sum = 4
2737 23:18:54.437134 best_step = 13
2738 23:18:54.437207
2739 23:18:54.437269 ==
2740 23:18:54.440750 Dram Type= 6, Freq= 0, CH_0, rank 0
2741 23:18:54.444019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2742 23:18:54.444094 ==
2743 23:18:54.444157 RX Vref Scan: 1
2744 23:18:54.444220
2745 23:18:54.447194 Set Vref Range= 32 -> 127
2746 23:18:54.447265
2747 23:18:54.450687 RX Vref 32 -> 127, step: 1
2748 23:18:54.450763
2749 23:18:54.454307 RX Delay -21 -> 252, step: 4
2750 23:18:54.454382
2751 23:18:54.457867 Set Vref, RX VrefLevel [Byte0]: 32
2752 23:18:54.460825 [Byte1]: 32
2753 23:18:54.460903
2754 23:18:54.463801 Set Vref, RX VrefLevel [Byte0]: 33
2755 23:18:54.467044 [Byte1]: 33
2756 23:18:54.471025
2757 23:18:54.471109 Set Vref, RX VrefLevel [Byte0]: 34
2758 23:18:54.474226 [Byte1]: 34
2759 23:18:54.478680
2760 23:18:54.478764 Set Vref, RX VrefLevel [Byte0]: 35
2761 23:18:54.481987 [Byte1]: 35
2762 23:18:54.486338
2763 23:18:54.486412 Set Vref, RX VrefLevel [Byte0]: 36
2764 23:18:54.489643 [Byte1]: 36
2765 23:18:54.494453
2766 23:18:54.494528 Set Vref, RX VrefLevel [Byte0]: 37
2767 23:18:54.497619 [Byte1]: 37
2768 23:18:54.502944
2769 23:18:54.503024 Set Vref, RX VrefLevel [Byte0]: 38
2770 23:18:54.505783 [Byte1]: 38
2771 23:18:54.510128
2772 23:18:54.510213 Set Vref, RX VrefLevel [Byte0]: 39
2773 23:18:54.513727 [Byte1]: 39
2774 23:18:54.518321
2775 23:18:54.518416 Set Vref, RX VrefLevel [Byte0]: 40
2776 23:18:54.521604 [Byte1]: 40
2777 23:18:54.526142
2778 23:18:54.526226 Set Vref, RX VrefLevel [Byte0]: 41
2779 23:18:54.529832 [Byte1]: 41
2780 23:18:54.534722
2781 23:18:54.534807 Set Vref, RX VrefLevel [Byte0]: 42
2782 23:18:54.537526 [Byte1]: 42
2783 23:18:54.541804
2784 23:18:54.541881 Set Vref, RX VrefLevel [Byte0]: 43
2785 23:18:54.545295 [Byte1]: 43
2786 23:18:54.549961
2787 23:18:54.550039 Set Vref, RX VrefLevel [Byte0]: 44
2788 23:18:54.553137 [Byte1]: 44
2789 23:18:54.558137
2790 23:18:54.558216 Set Vref, RX VrefLevel [Byte0]: 45
2791 23:18:54.561383 [Byte1]: 45
2792 23:18:54.566042
2793 23:18:54.566124 Set Vref, RX VrefLevel [Byte0]: 46
2794 23:18:54.568983 [Byte1]: 46
2795 23:18:54.573974
2796 23:18:54.574056 Set Vref, RX VrefLevel [Byte0]: 47
2797 23:18:54.576997 [Byte1]: 47
2798 23:18:54.581815
2799 23:18:54.581906 Set Vref, RX VrefLevel [Byte0]: 48
2800 23:18:54.584968 [Byte1]: 48
2801 23:18:54.589799
2802 23:18:54.589891 Set Vref, RX VrefLevel [Byte0]: 49
2803 23:18:54.593081 [Byte1]: 49
2804 23:18:54.597636
2805 23:18:54.597740 Set Vref, RX VrefLevel [Byte0]: 50
2806 23:18:54.600875 [Byte1]: 50
2807 23:18:54.605349
2808 23:18:54.605430 Set Vref, RX VrefLevel [Byte0]: 51
2809 23:18:54.609175 [Byte1]: 51
2810 23:18:54.613774
2811 23:18:54.613889 Set Vref, RX VrefLevel [Byte0]: 52
2812 23:18:54.616722 [Byte1]: 52
2813 23:18:54.621606
2814 23:18:54.621690 Set Vref, RX VrefLevel [Byte0]: 53
2815 23:18:54.624861 [Byte1]: 53
2816 23:18:54.629047
2817 23:18:54.629126 Set Vref, RX VrefLevel [Byte0]: 54
2818 23:18:54.632381 [Byte1]: 54
2819 23:18:54.637080
2820 23:18:54.637160 Set Vref, RX VrefLevel [Byte0]: 55
2821 23:18:54.640332 [Byte1]: 55
2822 23:18:54.644955
2823 23:18:54.645035 Set Vref, RX VrefLevel [Byte0]: 56
2824 23:18:54.648204 [Byte1]: 56
2825 23:18:54.653393
2826 23:18:54.653477 Set Vref, RX VrefLevel [Byte0]: 57
2827 23:18:54.656229 [Byte1]: 57
2828 23:18:54.660950
2829 23:18:54.661027 Set Vref, RX VrefLevel [Byte0]: 58
2830 23:18:54.664083 [Byte1]: 58
2831 23:18:54.668914
2832 23:18:54.668994 Set Vref, RX VrefLevel [Byte0]: 59
2833 23:18:54.672623 [Byte1]: 59
2834 23:18:54.676962
2835 23:18:54.677047 Set Vref, RX VrefLevel [Byte0]: 60
2836 23:18:54.679827 [Byte1]: 60
2837 23:18:54.685004
2838 23:18:54.685080 Set Vref, RX VrefLevel [Byte0]: 61
2839 23:18:54.687765 [Byte1]: 61
2840 23:18:54.693219
2841 23:18:54.693320 Set Vref, RX VrefLevel [Byte0]: 62
2842 23:18:54.695793 [Byte1]: 62
2843 23:18:54.700418
2844 23:18:54.700529 Set Vref, RX VrefLevel [Byte0]: 63
2845 23:18:54.703753 [Byte1]: 63
2846 23:18:54.708552
2847 23:18:54.708633 Set Vref, RX VrefLevel [Byte0]: 64
2848 23:18:54.711677 [Byte1]: 64
2849 23:18:54.716353
2850 23:18:54.716437 Set Vref, RX VrefLevel [Byte0]: 65
2851 23:18:54.719682 [Byte1]: 65
2852 23:18:54.724076
2853 23:18:54.724152 Set Vref, RX VrefLevel [Byte0]: 66
2854 23:18:54.727527 [Byte1]: 66
2855 23:18:54.732126
2856 23:18:54.732204 Set Vref, RX VrefLevel [Byte0]: 67
2857 23:18:54.735972 [Byte1]: 67
2858 23:18:54.740307
2859 23:18:54.740410 Final RX Vref Byte 0 = 52 to rank0
2860 23:18:54.743566 Final RX Vref Byte 1 = 50 to rank0
2861 23:18:54.746843 Final RX Vref Byte 0 = 52 to rank1
2862 23:18:54.750482 Final RX Vref Byte 1 = 50 to rank1==
2863 23:18:54.753985 Dram Type= 6, Freq= 0, CH_0, rank 0
2864 23:18:54.756800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2865 23:18:54.760251 ==
2866 23:18:54.760355 DQS Delay:
2867 23:18:54.760452 DQS0 = 0, DQS1 = 0
2868 23:18:54.763389 DQM Delay:
2869 23:18:54.763496 DQM0 = 117, DQM1 = 105
2870 23:18:54.766775 DQ Delay:
2871 23:18:54.770426 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2872 23:18:54.773170 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2873 23:18:54.776726 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =100
2874 23:18:54.780055 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =112
2875 23:18:54.780137
2876 23:18:54.780207
2877 23:18:54.786660 [DQSOSCAuto] RK0, (LSB)MR18= 0x500, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2878 23:18:54.789899 CH0 RK0: MR19=404, MR18=500
2879 23:18:54.796428 CH0_RK0: MR19=0x404, MR18=0x500, DQSOSC=408, MR23=63, INC=39, DEC=26
2880 23:18:54.796517
2881 23:18:54.799917 ----->DramcWriteLeveling(PI) begin...
2882 23:18:54.800008 ==
2883 23:18:54.803226 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 23:18:54.806550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 23:18:54.809854 ==
2886 23:18:54.809936 Write leveling (Byte 0): 31 => 31
2887 23:18:54.813016 Write leveling (Byte 1): 25 => 25
2888 23:18:54.816297 DramcWriteLeveling(PI) end<-----
2889 23:18:54.816407
2890 23:18:54.816501 ==
2891 23:18:54.819411 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 23:18:54.826089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 23:18:54.826183 ==
2894 23:18:54.829782 [Gating] SW mode calibration
2895 23:18:54.836044 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2896 23:18:54.839406 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2897 23:18:54.846098 0 15 0 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
2898 23:18:54.849192 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 23:18:54.852422 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 23:18:54.858997 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 23:18:54.862531 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 23:18:54.865610 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 23:18:54.872739 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2904 23:18:54.875565 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2905 23:18:54.879275 1 0 0 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
2906 23:18:54.885426 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 23:18:54.889018 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 23:18:54.892215 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 23:18:54.899225 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 23:18:54.902207 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 23:18:54.905739 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2912 23:18:54.912156 1 0 28 | B1->B0 | 2727 4545 | 0 0 | (1 1) (0 0)
2913 23:18:54.915639 1 1 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2914 23:18:54.918891 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 23:18:54.925173 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 23:18:54.928570 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 23:18:54.932548 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 23:18:54.938723 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 23:18:54.941784 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2920 23:18:54.945052 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2921 23:18:54.951779 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2922 23:18:54.955252 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2923 23:18:54.958357 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 23:18:54.961863 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 23:18:54.968373 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 23:18:54.971566 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 23:18:54.975036 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 23:18:54.981779 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 23:18:54.985217 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 23:18:54.988462 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:18:54.995072 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:18:54.998106 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 23:18:55.001587 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 23:18:55.007963 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 23:18:55.011800 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2936 23:18:55.014690 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2937 23:18:55.018225 Total UI for P1: 0, mck2ui 16
2938 23:18:55.021702 best dqsien dly found for B0: ( 1, 3, 24)
2939 23:18:55.028133 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 23:18:55.028220 Total UI for P1: 0, mck2ui 16
2941 23:18:55.034964 best dqsien dly found for B1: ( 1, 3, 28)
2942 23:18:55.037990 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2943 23:18:55.041702 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2944 23:18:55.041787
2945 23:18:55.044746 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2946 23:18:55.048193 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2947 23:18:55.051427 [Gating] SW calibration Done
2948 23:18:55.051514 ==
2949 23:18:55.055172 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 23:18:55.058173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 23:18:55.058255 ==
2952 23:18:55.061369 RX Vref Scan: 0
2953 23:18:55.061449
2954 23:18:55.061512 RX Vref 0 -> 0, step: 1
2955 23:18:55.061572
2956 23:18:55.064986 RX Delay -40 -> 252, step: 8
2957 23:18:55.068258 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2958 23:18:55.074655 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2959 23:18:55.078081 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2960 23:18:55.081190 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2961 23:18:55.084579 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2962 23:18:55.088033 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2963 23:18:55.094554 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2964 23:18:55.097778 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2965 23:18:55.101121 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2966 23:18:55.104410 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2967 23:18:55.107711 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2968 23:18:55.114440 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2969 23:18:55.118110 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2970 23:18:55.121486 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2971 23:18:55.124468 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2972 23:18:55.127873 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2973 23:18:55.131504 ==
2974 23:18:55.134637 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 23:18:55.137538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 23:18:55.137663 ==
2977 23:18:55.137794 DQS Delay:
2978 23:18:55.141050 DQS0 = 0, DQS1 = 0
2979 23:18:55.141251 DQM Delay:
2980 23:18:55.144442 DQM0 = 115, DQM1 = 107
2981 23:18:55.144524 DQ Delay:
2982 23:18:55.147906 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2983 23:18:55.151015 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2984 23:18:55.154211 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2985 23:18:55.157789 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2986 23:18:55.157862
2987 23:18:55.157923
2988 23:18:55.157988 ==
2989 23:18:55.160977 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 23:18:55.167474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 23:18:55.167617 ==
2992 23:18:55.167717
2993 23:18:55.167790
2994 23:18:55.167869 TX Vref Scan disable
2995 23:18:55.170892 == TX Byte 0 ==
2996 23:18:55.174327 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2997 23:18:55.180952 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2998 23:18:55.181031 == TX Byte 1 ==
2999 23:18:55.184248 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3000 23:18:55.190771 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3001 23:18:55.190903 ==
3002 23:18:55.194561 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 23:18:55.197360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 23:18:55.197481 ==
3005 23:18:55.209493 TX Vref=22, minBit 4, minWin=25, winSum=416
3006 23:18:55.212636 TX Vref=24, minBit 2, minWin=25, winSum=415
3007 23:18:55.215885 TX Vref=26, minBit 0, minWin=26, winSum=424
3008 23:18:55.219255 TX Vref=28, minBit 5, minWin=25, winSum=424
3009 23:18:55.222877 TX Vref=30, minBit 0, minWin=26, winSum=428
3010 23:18:55.226044 TX Vref=32, minBit 5, minWin=25, winSum=423
3011 23:18:55.232585 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
3012 23:18:55.232712
3013 23:18:55.235752 Final TX Range 1 Vref 30
3014 23:18:55.235879
3015 23:18:55.235996 ==
3016 23:18:55.239440 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 23:18:55.242567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 23:18:55.242691 ==
3019 23:18:55.245924
3020 23:18:55.246051
3021 23:18:55.246169 TX Vref Scan disable
3022 23:18:55.249314 == TX Byte 0 ==
3023 23:18:55.252845 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3024 23:18:55.255872 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3025 23:18:55.258998 == TX Byte 1 ==
3026 23:18:55.262409 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3027 23:18:55.268911 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3028 23:18:55.269044
3029 23:18:55.269160 [DATLAT]
3030 23:18:55.269274 Freq=1200, CH0 RK1
3031 23:18:55.269387
3032 23:18:55.272161 DATLAT Default: 0xd
3033 23:18:55.272285 0, 0xFFFF, sum = 0
3034 23:18:55.275810 1, 0xFFFF, sum = 0
3035 23:18:55.279026 2, 0xFFFF, sum = 0
3036 23:18:55.279155 3, 0xFFFF, sum = 0
3037 23:18:55.282269 4, 0xFFFF, sum = 0
3038 23:18:55.282394 5, 0xFFFF, sum = 0
3039 23:18:55.285699 6, 0xFFFF, sum = 0
3040 23:18:55.285791 7, 0xFFFF, sum = 0
3041 23:18:55.288891 8, 0xFFFF, sum = 0
3042 23:18:55.288967 9, 0xFFFF, sum = 0
3043 23:18:55.292208 10, 0xFFFF, sum = 0
3044 23:18:55.292285 11, 0xFFFF, sum = 0
3045 23:18:55.295338 12, 0x0, sum = 1
3046 23:18:55.295434 13, 0x0, sum = 2
3047 23:18:55.299109 14, 0x0, sum = 3
3048 23:18:55.299214 15, 0x0, sum = 4
3049 23:18:55.302494 best_step = 13
3050 23:18:55.302571
3051 23:18:55.302639 ==
3052 23:18:55.305341 Dram Type= 6, Freq= 0, CH_0, rank 1
3053 23:18:55.308623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 23:18:55.308697 ==
3055 23:18:55.308760 RX Vref Scan: 0
3056 23:18:55.312285
3057 23:18:55.312385 RX Vref 0 -> 0, step: 1
3058 23:18:55.312475
3059 23:18:55.315406 RX Delay -21 -> 252, step: 4
3060 23:18:55.321954 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3061 23:18:55.325247 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3062 23:18:55.329008 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3063 23:18:55.332152 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3064 23:18:55.335512 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3065 23:18:55.338518 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3066 23:18:55.345228 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3067 23:18:55.348851 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3068 23:18:55.351966 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3069 23:18:55.355618 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3070 23:18:55.358972 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3071 23:18:55.365322 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3072 23:18:55.368399 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3073 23:18:55.371904 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3074 23:18:55.375215 iDelay=195, Bit 14, Center 118 (51 ~ 186) 136
3075 23:18:55.381780 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3076 23:18:55.381859 ==
3077 23:18:55.385216 Dram Type= 6, Freq= 0, CH_0, rank 1
3078 23:18:55.388388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 23:18:55.388464 ==
3080 23:18:55.388530 DQS Delay:
3081 23:18:55.391683 DQS0 = 0, DQS1 = 0
3082 23:18:55.391758 DQM Delay:
3083 23:18:55.394934 DQM0 = 115, DQM1 = 105
3084 23:18:55.395015 DQ Delay:
3085 23:18:55.398268 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3086 23:18:55.401431 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3087 23:18:55.405100 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =98
3088 23:18:55.408393 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3089 23:18:55.408473
3090 23:18:55.408545
3091 23:18:55.418415 [DQSOSCAuto] RK1, (LSB)MR18= 0xfaf7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
3092 23:18:55.421424 CH0 RK1: MR19=303, MR18=FAF7
3093 23:18:55.424691 CH0_RK1: MR19=0x303, MR18=0xFAF7, DQSOSC=412, MR23=63, INC=38, DEC=25
3094 23:18:55.427849 [RxdqsGatingPostProcess] freq 1200
3095 23:18:55.434530 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3096 23:18:55.437710 best DQS0 dly(2T, 0.5T) = (0, 11)
3097 23:18:55.441548 best DQS1 dly(2T, 0.5T) = (0, 12)
3098 23:18:55.444569 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3099 23:18:55.447774 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3100 23:18:55.451021 best DQS0 dly(2T, 0.5T) = (0, 11)
3101 23:18:55.454587 best DQS1 dly(2T, 0.5T) = (0, 11)
3102 23:18:55.457580 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3103 23:18:55.460975 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3104 23:18:55.464189 Pre-setting of DQS Precalculation
3105 23:18:55.467333 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3106 23:18:55.467424 ==
3107 23:18:55.470811 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 23:18:55.474061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 23:18:55.477577 ==
3110 23:18:55.480723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3111 23:18:55.487461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3112 23:18:55.495624 [CA 0] Center 38 (8~68) winsize 61
3113 23:18:55.498555 [CA 1] Center 37 (7~68) winsize 62
3114 23:18:55.501806 [CA 2] Center 35 (5~65) winsize 61
3115 23:18:55.505502 [CA 3] Center 34 (4~64) winsize 61
3116 23:18:55.508646 [CA 4] Center 34 (4~65) winsize 62
3117 23:18:55.512404 [CA 5] Center 33 (3~63) winsize 61
3118 23:18:55.512532
3119 23:18:55.515269 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3120 23:18:55.515367
3121 23:18:55.518459 [CATrainingPosCal] consider 1 rank data
3122 23:18:55.521972 u2DelayCellTimex100 = 270/100 ps
3123 23:18:55.525382 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3124 23:18:55.531861 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3125 23:18:55.535054 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3126 23:18:55.538506 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3127 23:18:55.541838 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3128 23:18:55.545155 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3129 23:18:55.545287
3130 23:18:55.548453 CA PerBit enable=1, Macro0, CA PI delay=33
3131 23:18:55.548578
3132 23:18:55.552043 [CBTSetCACLKResult] CA Dly = 33
3133 23:18:55.552164 CS Dly: 5 (0~36)
3134 23:18:55.555000 ==
3135 23:18:55.555129 Dram Type= 6, Freq= 0, CH_1, rank 1
3136 23:18:55.561555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 23:18:55.561636 ==
3138 23:18:55.565213 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3139 23:18:55.571845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3140 23:18:55.580820 [CA 0] Center 37 (7~68) winsize 62
3141 23:18:55.584256 [CA 1] Center 38 (8~68) winsize 61
3142 23:18:55.587814 [CA 2] Center 34 (4~65) winsize 62
3143 23:18:55.590761 [CA 3] Center 33 (3~64) winsize 62
3144 23:18:55.594048 [CA 4] Center 33 (3~64) winsize 62
3145 23:18:55.597692 [CA 5] Center 33 (3~64) winsize 62
3146 23:18:55.597826
3147 23:18:55.601121 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3148 23:18:55.601252
3149 23:18:55.604344 [CATrainingPosCal] consider 2 rank data
3150 23:18:55.607677 u2DelayCellTimex100 = 270/100 ps
3151 23:18:55.611255 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3152 23:18:55.617632 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3153 23:18:55.620668 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3154 23:18:55.623878 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 23:18:55.627258 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 23:18:55.630591 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3157 23:18:55.630672
3158 23:18:55.634081 CA PerBit enable=1, Macro0, CA PI delay=33
3159 23:18:55.634158
3160 23:18:55.637635 [CBTSetCACLKResult] CA Dly = 33
3161 23:18:55.637721 CS Dly: 6 (0~39)
3162 23:18:55.640887
3163 23:18:55.643882 ----->DramcWriteLeveling(PI) begin...
3164 23:18:55.643963 ==
3165 23:18:55.647005 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 23:18:55.650464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 23:18:55.650624 ==
3168 23:18:55.653711 Write leveling (Byte 0): 25 => 25
3169 23:18:55.657406 Write leveling (Byte 1): 26 => 26
3170 23:18:55.660392 DramcWriteLeveling(PI) end<-----
3171 23:18:55.660470
3172 23:18:55.660534 ==
3173 23:18:55.664227 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 23:18:55.667092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 23:18:55.667195 ==
3176 23:18:55.670427 [Gating] SW mode calibration
3177 23:18:55.676812 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3178 23:18:55.683657 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3179 23:18:55.687064 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
3180 23:18:55.690042 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 23:18:55.697034 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 23:18:55.700156 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 23:18:55.703631 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 23:18:55.709990 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 23:18:55.713855 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
3186 23:18:55.716704 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
3187 23:18:55.723977 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 23:18:55.726969 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 23:18:55.730386 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 23:18:55.737082 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 23:18:55.739973 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 23:18:55.743530 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 23:18:55.750061 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3194 23:18:55.753349 1 0 28 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
3195 23:18:55.756865 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 23:18:55.760037 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 23:18:55.766587 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 23:18:55.770248 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 23:18:55.773493 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 23:18:55.780003 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 23:18:55.783178 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3202 23:18:55.786660 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3203 23:18:55.793011 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 23:18:55.796378 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 23:18:55.799896 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 23:18:55.806380 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 23:18:55.809506 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 23:18:55.812734 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 23:18:55.819409 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 23:18:55.823238 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 23:18:55.826663 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 23:18:55.832533 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:18:55.836134 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:18:55.839482 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:18:55.845790 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:18:55.849221 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 23:18:55.852922 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3218 23:18:55.859213 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3219 23:18:55.862502 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 23:18:55.866048 Total UI for P1: 0, mck2ui 16
3221 23:18:55.869219 best dqsien dly found for B0: ( 1, 3, 26)
3222 23:18:55.872691 Total UI for P1: 0, mck2ui 16
3223 23:18:55.875790 best dqsien dly found for B1: ( 1, 3, 28)
3224 23:18:55.879270 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3225 23:18:55.882608 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3226 23:18:55.882691
3227 23:18:55.885671 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3228 23:18:55.889356 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3229 23:18:55.892801 [Gating] SW calibration Done
3230 23:18:55.892912 ==
3231 23:18:55.895690 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 23:18:55.899082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 23:18:55.902751 ==
3234 23:18:55.902834 RX Vref Scan: 0
3235 23:18:55.902900
3236 23:18:55.905995 RX Vref 0 -> 0, step: 1
3237 23:18:55.906078
3238 23:18:55.908712 RX Delay -40 -> 252, step: 8
3239 23:18:55.912104 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3240 23:18:55.915524 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3241 23:18:55.918972 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3242 23:18:55.922458 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3243 23:18:55.928626 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3244 23:18:55.931939 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3245 23:18:55.935534 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3246 23:18:55.938486 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3247 23:18:55.941803 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3248 23:18:55.948599 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3249 23:18:55.951806 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3250 23:18:55.955337 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3251 23:18:55.958710 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3252 23:18:55.961810 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3253 23:18:55.968342 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3254 23:18:55.971739 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3255 23:18:55.971837 ==
3256 23:18:55.975121 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 23:18:55.978515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 23:18:55.978598 ==
3259 23:18:55.981798 DQS Delay:
3260 23:18:55.981886 DQS0 = 0, DQS1 = 0
3261 23:18:55.981951 DQM Delay:
3262 23:18:55.984971 DQM0 = 116, DQM1 = 113
3263 23:18:55.985053 DQ Delay:
3264 23:18:55.988565 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3265 23:18:55.994827 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3266 23:18:55.998184 DQ8 =103, DQ9 =103, DQ10 =111, DQ11 =107
3267 23:18:56.001721 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3268 23:18:56.001828
3269 23:18:56.001919
3270 23:18:56.002005 ==
3271 23:18:56.004859 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 23:18:56.008429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 23:18:56.008513 ==
3274 23:18:56.008579
3275 23:18:56.008639
3276 23:18:56.011671 TX Vref Scan disable
3277 23:18:56.014816 == TX Byte 0 ==
3278 23:18:56.018238 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3279 23:18:56.021251 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3280 23:18:56.024644 == TX Byte 1 ==
3281 23:18:56.028162 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3282 23:18:56.031244 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3283 23:18:56.031354 ==
3284 23:18:56.034782 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 23:18:56.038083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 23:18:56.041549 ==
3287 23:18:56.051205 TX Vref=22, minBit 8, minWin=24, winSum=406
3288 23:18:56.054423 TX Vref=24, minBit 1, minWin=25, winSum=411
3289 23:18:56.058069 TX Vref=26, minBit 6, minWin=25, winSum=418
3290 23:18:56.061680 TX Vref=28, minBit 6, minWin=25, winSum=421
3291 23:18:56.064680 TX Vref=30, minBit 2, minWin=26, winSum=427
3292 23:18:56.071293 TX Vref=32, minBit 1, minWin=26, winSum=426
3293 23:18:56.074286 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 30
3294 23:18:56.074366
3295 23:18:56.078219 Final TX Range 1 Vref 30
3296 23:18:56.078299
3297 23:18:56.078381 ==
3298 23:18:56.081238 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 23:18:56.084392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 23:18:56.084475 ==
3301 23:18:56.087636
3302 23:18:56.087718
3303 23:18:56.087784 TX Vref Scan disable
3304 23:18:56.091346 == TX Byte 0 ==
3305 23:18:56.094388 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3306 23:18:56.097618 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3307 23:18:56.101285 == TX Byte 1 ==
3308 23:18:56.104286 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3309 23:18:56.110726 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3310 23:18:56.110810
3311 23:18:56.110875 [DATLAT]
3312 23:18:56.110937 Freq=1200, CH1 RK0
3313 23:18:56.110996
3314 23:18:56.114336 DATLAT Default: 0xd
3315 23:18:56.114419 0, 0xFFFF, sum = 0
3316 23:18:56.117569 1, 0xFFFF, sum = 0
3317 23:18:56.117679 2, 0xFFFF, sum = 0
3318 23:18:56.120937 3, 0xFFFF, sum = 0
3319 23:18:56.124418 4, 0xFFFF, sum = 0
3320 23:18:56.124532 5, 0xFFFF, sum = 0
3321 23:18:56.127481 6, 0xFFFF, sum = 0
3322 23:18:56.127566 7, 0xFFFF, sum = 0
3323 23:18:56.130736 8, 0xFFFF, sum = 0
3324 23:18:56.130820 9, 0xFFFF, sum = 0
3325 23:18:56.134013 10, 0xFFFF, sum = 0
3326 23:18:56.134100 11, 0xFFFF, sum = 0
3327 23:18:56.137193 12, 0x0, sum = 1
3328 23:18:56.137277 13, 0x0, sum = 2
3329 23:18:56.140833 14, 0x0, sum = 3
3330 23:18:56.140945 15, 0x0, sum = 4
3331 23:18:56.144071 best_step = 13
3332 23:18:56.144153
3333 23:18:56.144219 ==
3334 23:18:56.147095 Dram Type= 6, Freq= 0, CH_1, rank 0
3335 23:18:56.151124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3336 23:18:56.151208 ==
3337 23:18:56.151274 RX Vref Scan: 1
3338 23:18:56.151336
3339 23:18:56.153869 Set Vref Range= 32 -> 127
3340 23:18:56.153952
3341 23:18:56.157563 RX Vref 32 -> 127, step: 1
3342 23:18:56.157674
3343 23:18:56.161036 RX Delay -13 -> 252, step: 4
3344 23:18:56.161118
3345 23:18:56.164183 Set Vref, RX VrefLevel [Byte0]: 32
3346 23:18:56.167284 [Byte1]: 32
3347 23:18:56.167412
3348 23:18:56.170511 Set Vref, RX VrefLevel [Byte0]: 33
3349 23:18:56.173713 [Byte1]: 33
3350 23:18:56.177264
3351 23:18:56.177348 Set Vref, RX VrefLevel [Byte0]: 34
3352 23:18:56.180920 [Byte1]: 34
3353 23:18:56.185013
3354 23:18:56.185095 Set Vref, RX VrefLevel [Byte0]: 35
3355 23:18:56.188563 [Byte1]: 35
3356 23:18:56.193375
3357 23:18:56.193453 Set Vref, RX VrefLevel [Byte0]: 36
3358 23:18:56.196284 [Byte1]: 36
3359 23:18:56.200862
3360 23:18:56.200962 Set Vref, RX VrefLevel [Byte0]: 37
3361 23:18:56.204084 [Byte1]: 37
3362 23:18:56.208680
3363 23:18:56.208764 Set Vref, RX VrefLevel [Byte0]: 38
3364 23:18:56.212033 [Byte1]: 38
3365 23:18:56.216656
3366 23:18:56.216755 Set Vref, RX VrefLevel [Byte0]: 39
3367 23:18:56.219771 [Byte1]: 39
3368 23:18:56.224827
3369 23:18:56.224909 Set Vref, RX VrefLevel [Byte0]: 40
3370 23:18:56.228201 [Byte1]: 40
3371 23:18:56.232404
3372 23:18:56.232521 Set Vref, RX VrefLevel [Byte0]: 41
3373 23:18:56.235926 [Byte1]: 41
3374 23:18:56.240137
3375 23:18:56.240220 Set Vref, RX VrefLevel [Byte0]: 42
3376 23:18:56.243762 [Byte1]: 42
3377 23:18:56.247996
3378 23:18:56.248080 Set Vref, RX VrefLevel [Byte0]: 43
3379 23:18:56.251344 [Byte1]: 43
3380 23:18:56.256261
3381 23:18:56.256357 Set Vref, RX VrefLevel [Byte0]: 44
3382 23:18:56.259693 [Byte1]: 44
3383 23:18:56.263755
3384 23:18:56.263850 Set Vref, RX VrefLevel [Byte0]: 45
3385 23:18:56.267236 [Byte1]: 45
3386 23:18:56.271873
3387 23:18:56.271983 Set Vref, RX VrefLevel [Byte0]: 46
3388 23:18:56.275058 [Byte1]: 46
3389 23:18:56.279797
3390 23:18:56.279880 Set Vref, RX VrefLevel [Byte0]: 47
3391 23:18:56.283075 [Byte1]: 47
3392 23:18:56.287496
3393 23:18:56.287579 Set Vref, RX VrefLevel [Byte0]: 48
3394 23:18:56.290920 [Byte1]: 48
3395 23:18:56.295302
3396 23:18:56.295410 Set Vref, RX VrefLevel [Byte0]: 49
3397 23:18:56.298665 [Byte1]: 49
3398 23:18:56.303054
3399 23:18:56.303137 Set Vref, RX VrefLevel [Byte0]: 50
3400 23:18:56.306774 [Byte1]: 50
3401 23:18:56.310938
3402 23:18:56.311021 Set Vref, RX VrefLevel [Byte0]: 51
3403 23:18:56.314679 [Byte1]: 51
3404 23:18:56.319387
3405 23:18:56.319470 Set Vref, RX VrefLevel [Byte0]: 52
3406 23:18:56.322353 [Byte1]: 52
3407 23:18:56.327309
3408 23:18:56.327424 Set Vref, RX VrefLevel [Byte0]: 53
3409 23:18:56.330392 [Byte1]: 53
3410 23:18:56.334776
3411 23:18:56.334860 Set Vref, RX VrefLevel [Byte0]: 54
3412 23:18:56.338285 [Byte1]: 54
3413 23:18:56.342879
3414 23:18:56.342962 Set Vref, RX VrefLevel [Byte0]: 55
3415 23:18:56.346214 [Byte1]: 55
3416 23:18:56.350833
3417 23:18:56.350943 Set Vref, RX VrefLevel [Byte0]: 56
3418 23:18:56.353834 [Byte1]: 56
3419 23:18:56.358919
3420 23:18:56.359028 Set Vref, RX VrefLevel [Byte0]: 57
3421 23:18:56.361781 [Byte1]: 57
3422 23:18:56.366283
3423 23:18:56.366366 Set Vref, RX VrefLevel [Byte0]: 58
3424 23:18:56.369703 [Byte1]: 58
3425 23:18:56.374375
3426 23:18:56.374458 Set Vref, RX VrefLevel [Byte0]: 59
3427 23:18:56.377761 [Byte1]: 59
3428 23:18:56.381878
3429 23:18:56.381960 Set Vref, RX VrefLevel [Byte0]: 60
3430 23:18:56.385311 [Byte1]: 60
3431 23:18:56.390129
3432 23:18:56.390212 Set Vref, RX VrefLevel [Byte0]: 61
3433 23:18:56.393316 [Byte1]: 61
3434 23:18:56.397740
3435 23:18:56.397829 Set Vref, RX VrefLevel [Byte0]: 62
3436 23:18:56.400947 [Byte1]: 62
3437 23:18:56.405825
3438 23:18:56.405913 Set Vref, RX VrefLevel [Byte0]: 63
3439 23:18:56.408950 [Byte1]: 63
3440 23:18:56.413745
3441 23:18:56.413827 Set Vref, RX VrefLevel [Byte0]: 64
3442 23:18:56.417026 [Byte1]: 64
3443 23:18:56.421617
3444 23:18:56.421696 Set Vref, RX VrefLevel [Byte0]: 65
3445 23:18:56.425139 [Byte1]: 65
3446 23:18:56.429484
3447 23:18:56.429567 Final RX Vref Byte 0 = 50 to rank0
3448 23:18:56.432958 Final RX Vref Byte 1 = 53 to rank0
3449 23:18:56.436027 Final RX Vref Byte 0 = 50 to rank1
3450 23:18:56.439153 Final RX Vref Byte 1 = 53 to rank1==
3451 23:18:56.442617 Dram Type= 6, Freq= 0, CH_1, rank 0
3452 23:18:56.449670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3453 23:18:56.449755 ==
3454 23:18:56.449821 DQS Delay:
3455 23:18:56.449883 DQS0 = 0, DQS1 = 0
3456 23:18:56.452497 DQM Delay:
3457 23:18:56.452580 DQM0 = 116, DQM1 = 115
3458 23:18:56.455799 DQ Delay:
3459 23:18:56.459416 DQ0 =122, DQ1 =112, DQ2 =106, DQ3 =116
3460 23:18:56.462536 DQ4 =112, DQ5 =124, DQ6 =128, DQ7 =110
3461 23:18:56.466066 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =110
3462 23:18:56.469204 DQ12 =124, DQ13 =122, DQ14 =122, DQ15 =124
3463 23:18:56.469288
3464 23:18:56.469353
3465 23:18:56.479116 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3466 23:18:56.479227 CH1 RK0: MR19=303, MR18=F2FF
3467 23:18:56.485789 CH1_RK0: MR19=0x303, MR18=0xF2FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3468 23:18:56.485876
3469 23:18:56.489298 ----->DramcWriteLeveling(PI) begin...
3470 23:18:56.489383 ==
3471 23:18:56.492351 Dram Type= 6, Freq= 0, CH_1, rank 1
3472 23:18:56.499105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 23:18:56.499193 ==
3474 23:18:56.502232 Write leveling (Byte 0): 25 => 25
3475 23:18:56.502317 Write leveling (Byte 1): 29 => 29
3476 23:18:56.506121 DramcWriteLeveling(PI) end<-----
3477 23:18:56.506206
3478 23:18:56.509239 ==
3479 23:18:56.509323 Dram Type= 6, Freq= 0, CH_1, rank 1
3480 23:18:56.515979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3481 23:18:56.516064 ==
3482 23:18:56.518951 [Gating] SW mode calibration
3483 23:18:56.525474 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3484 23:18:56.528874 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3485 23:18:56.535349 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3486 23:18:56.538901 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 23:18:56.542279 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 23:18:56.548638 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 23:18:56.552081 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 23:18:56.555259 0 15 20 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3491 23:18:56.562259 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
3492 23:18:56.565095 0 15 28 | B1->B0 | 3232 2323 | 0 0 | (1 0) (0 0)
3493 23:18:56.568968 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 23:18:56.575378 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 23:18:56.578781 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 23:18:56.582334 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 23:18:56.588480 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 23:18:56.592111 1 0 20 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3499 23:18:56.595188 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3500 23:18:56.598791 1 0 28 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
3501 23:18:56.605188 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 23:18:56.608507 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 23:18:56.611864 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 23:18:56.618999 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 23:18:56.621858 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 23:18:56.625404 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 23:18:56.631703 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3508 23:18:56.635299 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3509 23:18:56.638583 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 23:18:56.645295 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 23:18:56.648438 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 23:18:56.651638 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 23:18:56.658274 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 23:18:56.661360 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 23:18:56.665001 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 23:18:56.671312 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 23:18:56.674755 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 23:18:56.677958 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 23:18:56.684537 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 23:18:56.687984 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 23:18:56.691332 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 23:18:56.698128 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3523 23:18:56.701165 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3524 23:18:56.704052 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3525 23:18:56.707601 Total UI for P1: 0, mck2ui 16
3526 23:18:56.710865 best dqsien dly found for B0: ( 1, 3, 22)
3527 23:18:56.717457 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 23:18:56.720551 Total UI for P1: 0, mck2ui 16
3529 23:18:56.723997 best dqsien dly found for B1: ( 1, 3, 26)
3530 23:18:56.727712 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3531 23:18:56.730667 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3532 23:18:56.730768
3533 23:18:56.733605 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3534 23:18:56.736967 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3535 23:18:56.740873 [Gating] SW calibration Done
3536 23:18:56.740956 ==
3537 23:18:56.743556 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 23:18:56.747073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 23:18:56.747176 ==
3540 23:18:56.750443 RX Vref Scan: 0
3541 23:18:56.750543
3542 23:18:56.753707 RX Vref 0 -> 0, step: 1
3543 23:18:56.753807
3544 23:18:56.753905 RX Delay -40 -> 252, step: 8
3545 23:18:56.760141 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3546 23:18:56.763609 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3547 23:18:56.766957 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3548 23:18:56.770296 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3549 23:18:56.776715 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3550 23:18:56.779634 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3551 23:18:56.782985 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3552 23:18:56.786447 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3553 23:18:56.789419 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3554 23:18:56.796158 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3555 23:18:56.799464 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3556 23:18:56.802941 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3557 23:18:56.806014 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3558 23:18:56.809407 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3559 23:18:56.815842 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3560 23:18:56.819199 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3561 23:18:56.819304 ==
3562 23:18:56.822278 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 23:18:56.825715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 23:18:56.825801 ==
3565 23:18:56.828832 DQS Delay:
3566 23:18:56.828917 DQS0 = 0, DQS1 = 0
3567 23:18:56.832472 DQM Delay:
3568 23:18:56.832556 DQM0 = 116, DQM1 = 112
3569 23:18:56.832624 DQ Delay:
3570 23:18:56.835588 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3571 23:18:56.842511 DQ4 =119, DQ5 =127, DQ6 =123, DQ7 =111
3572 23:18:56.845656 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3573 23:18:56.849259 DQ12 =123, DQ13 =123, DQ14 =115, DQ15 =119
3574 23:18:56.849344
3575 23:18:56.849411
3576 23:18:56.849473 ==
3577 23:18:56.851961 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 23:18:56.855340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 23:18:56.855438 ==
3580 23:18:56.855506
3581 23:18:56.855569
3582 23:18:56.858772 TX Vref Scan disable
3583 23:18:56.862394 == TX Byte 0 ==
3584 23:18:56.865214 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3585 23:18:56.868804 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3586 23:18:56.871921 == TX Byte 1 ==
3587 23:18:56.875420 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3588 23:18:56.878678 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3589 23:18:56.878756 ==
3590 23:18:56.881790 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 23:18:56.885219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 23:18:56.888437 ==
3593 23:18:56.898740 TX Vref=22, minBit 7, minWin=25, winSum=418
3594 23:18:56.901740 TX Vref=24, minBit 1, minWin=26, winSum=422
3595 23:18:56.905528 TX Vref=26, minBit 1, minWin=26, winSum=427
3596 23:18:56.908374 TX Vref=28, minBit 0, minWin=26, winSum=429
3597 23:18:56.911930 TX Vref=30, minBit 10, minWin=25, winSum=427
3598 23:18:56.918554 TX Vref=32, minBit 0, minWin=26, winSum=428
3599 23:18:56.921766 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
3600 23:18:56.921871
3601 23:18:56.924863 Final TX Range 1 Vref 28
3602 23:18:56.924948
3603 23:18:56.925015 ==
3604 23:18:56.928403 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 23:18:56.931733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 23:18:56.934674 ==
3607 23:18:56.934758
3608 23:18:56.934825
3609 23:18:56.934887 TX Vref Scan disable
3610 23:18:56.938565 == TX Byte 0 ==
3611 23:18:56.941813 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3612 23:18:56.948839 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3613 23:18:56.948924 == TX Byte 1 ==
3614 23:18:56.951798 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3615 23:18:56.958839 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3616 23:18:56.958923
3617 23:18:56.958991 [DATLAT]
3618 23:18:56.959053 Freq=1200, CH1 RK1
3619 23:18:56.959114
3620 23:18:56.961719 DATLAT Default: 0xd
3621 23:18:56.965031 0, 0xFFFF, sum = 0
3622 23:18:56.965117 1, 0xFFFF, sum = 0
3623 23:18:56.968037 2, 0xFFFF, sum = 0
3624 23:18:56.968122 3, 0xFFFF, sum = 0
3625 23:18:56.971349 4, 0xFFFF, sum = 0
3626 23:18:56.971469 5, 0xFFFF, sum = 0
3627 23:18:56.974739 6, 0xFFFF, sum = 0
3628 23:18:56.974824 7, 0xFFFF, sum = 0
3629 23:18:56.977737 8, 0xFFFF, sum = 0
3630 23:18:56.977825 9, 0xFFFF, sum = 0
3631 23:18:56.981077 10, 0xFFFF, sum = 0
3632 23:18:56.981163 11, 0xFFFF, sum = 0
3633 23:18:56.984713 12, 0x0, sum = 1
3634 23:18:56.984799 13, 0x0, sum = 2
3635 23:18:56.988533 14, 0x0, sum = 3
3636 23:18:56.988619 15, 0x0, sum = 4
3637 23:18:56.991150 best_step = 13
3638 23:18:56.991233
3639 23:18:56.991300 ==
3640 23:18:56.994468 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 23:18:56.997825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 23:18:56.997910 ==
3643 23:18:57.001062 RX Vref Scan: 0
3644 23:18:57.001146
3645 23:18:57.001212 RX Vref 0 -> 0, step: 1
3646 23:18:57.001275
3647 23:18:57.004333 RX Delay -13 -> 252, step: 4
3648 23:18:57.010901 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3649 23:18:57.014117 iDelay=195, Bit 1, Center 112 (47 ~ 178) 132
3650 23:18:57.017341 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3651 23:18:57.020774 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3652 23:18:57.024195 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3653 23:18:57.030913 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3654 23:18:57.034093 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3655 23:18:57.037495 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3656 23:18:57.040750 iDelay=195, Bit 8, Center 102 (43 ~ 162) 120
3657 23:18:57.044359 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3658 23:18:57.050599 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3659 23:18:57.053995 iDelay=195, Bit 11, Center 108 (47 ~ 170) 124
3660 23:18:57.057099 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3661 23:18:57.060467 iDelay=195, Bit 13, Center 120 (59 ~ 182) 124
3662 23:18:57.067226 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3663 23:18:57.070715 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3664 23:18:57.070801 ==
3665 23:18:57.073923 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 23:18:57.076785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 23:18:57.076861 ==
3668 23:18:57.080530 DQS Delay:
3669 23:18:57.080610 DQS0 = 0, DQS1 = 0
3670 23:18:57.080675 DQM Delay:
3671 23:18:57.083867 DQM0 = 115, DQM1 = 114
3672 23:18:57.083937 DQ Delay:
3673 23:18:57.086659 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =116
3674 23:18:57.090120 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3675 23:18:57.093413 DQ8 =102, DQ9 =104, DQ10 =116, DQ11 =108
3676 23:18:57.100167 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =122
3677 23:18:57.100254
3678 23:18:57.100343
3679 23:18:57.106635 [DQSOSCAuto] RK1, (LSB)MR18= 0xf508, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
3680 23:18:57.110056 CH1 RK1: MR19=304, MR18=F508
3681 23:18:57.116230 CH1_RK1: MR19=0x304, MR18=0xF508, DQSOSC=406, MR23=63, INC=39, DEC=26
3682 23:18:57.119798 [RxdqsGatingPostProcess] freq 1200
3683 23:18:57.123069 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3684 23:18:57.126570 best DQS0 dly(2T, 0.5T) = (0, 11)
3685 23:18:57.129615 best DQS1 dly(2T, 0.5T) = (0, 11)
3686 23:18:57.133008 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3687 23:18:57.136387 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3688 23:18:57.139372 best DQS0 dly(2T, 0.5T) = (0, 11)
3689 23:18:57.142737 best DQS1 dly(2T, 0.5T) = (0, 11)
3690 23:18:57.146167 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3691 23:18:57.149248 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3692 23:18:57.152804 Pre-setting of DQS Precalculation
3693 23:18:57.159025 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3694 23:18:57.165695 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3695 23:18:57.172064 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3696 23:18:57.172149
3697 23:18:57.172235
3698 23:18:57.175747 [Calibration Summary] 2400 Mbps
3699 23:18:57.175833 CH 0, Rank 0
3700 23:18:57.178835 SW Impedance : PASS
3701 23:18:57.182320 DUTY Scan : NO K
3702 23:18:57.182400 ZQ Calibration : PASS
3703 23:18:57.185537 Jitter Meter : NO K
3704 23:18:57.188899 CBT Training : PASS
3705 23:18:57.188985 Write leveling : PASS
3706 23:18:57.192253 RX DQS gating : PASS
3707 23:18:57.195454 RX DQ/DQS(RDDQC) : PASS
3708 23:18:57.195533 TX DQ/DQS : PASS
3709 23:18:57.198585 RX DATLAT : PASS
3710 23:18:57.198659 RX DQ/DQS(Engine): PASS
3711 23:18:57.201849 TX OE : NO K
3712 23:18:57.201949 All Pass.
3713 23:18:57.202040
3714 23:18:57.205345 CH 0, Rank 1
3715 23:18:57.208866 SW Impedance : PASS
3716 23:18:57.208938 DUTY Scan : NO K
3717 23:18:57.211813 ZQ Calibration : PASS
3718 23:18:57.211886 Jitter Meter : NO K
3719 23:18:57.215382 CBT Training : PASS
3720 23:18:57.218262 Write leveling : PASS
3721 23:18:57.218360 RX DQS gating : PASS
3722 23:18:57.221735 RX DQ/DQS(RDDQC) : PASS
3723 23:18:57.225096 TX DQ/DQS : PASS
3724 23:18:57.225201 RX DATLAT : PASS
3725 23:18:57.228455 RX DQ/DQS(Engine): PASS
3726 23:18:57.231827 TX OE : NO K
3727 23:18:57.231904 All Pass.
3728 23:18:57.231968
3729 23:18:57.232029 CH 1, Rank 0
3730 23:18:57.234980 SW Impedance : PASS
3731 23:18:57.238535 DUTY Scan : NO K
3732 23:18:57.238610 ZQ Calibration : PASS
3733 23:18:57.241902 Jitter Meter : NO K
3734 23:18:57.244883 CBT Training : PASS
3735 23:18:57.244984 Write leveling : PASS
3736 23:18:57.248262 RX DQS gating : PASS
3737 23:18:57.251641 RX DQ/DQS(RDDQC) : PASS
3738 23:18:57.251743 TX DQ/DQS : PASS
3739 23:18:57.254988 RX DATLAT : PASS
3740 23:18:57.258000 RX DQ/DQS(Engine): PASS
3741 23:18:57.258100 TX OE : NO K
3742 23:18:57.261208 All Pass.
3743 23:18:57.261309
3744 23:18:57.261400 CH 1, Rank 1
3745 23:18:57.264734 SW Impedance : PASS
3746 23:18:57.264807 DUTY Scan : NO K
3747 23:18:57.268252 ZQ Calibration : PASS
3748 23:18:57.271124 Jitter Meter : NO K
3749 23:18:57.271212 CBT Training : PASS
3750 23:18:57.274272 Write leveling : PASS
3751 23:18:57.277845 RX DQS gating : PASS
3752 23:18:57.277950 RX DQ/DQS(RDDQC) : PASS
3753 23:18:57.281114 TX DQ/DQS : PASS
3754 23:18:57.281188 RX DATLAT : PASS
3755 23:18:57.284269 RX DQ/DQS(Engine): PASS
3756 23:18:57.287502 TX OE : NO K
3757 23:18:57.287590 All Pass.
3758 23:18:57.287676
3759 23:18:57.291014 DramC Write-DBI off
3760 23:18:57.294438 PER_BANK_REFRESH: Hybrid Mode
3761 23:18:57.294524 TX_TRACKING: ON
3762 23:18:57.304461 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3763 23:18:57.307173 [FAST_K] Save calibration result to emmc
3764 23:18:57.310789 dramc_set_vcore_voltage set vcore to 650000
3765 23:18:57.314162 Read voltage for 600, 5
3766 23:18:57.314246 Vio18 = 0
3767 23:18:57.314331 Vcore = 650000
3768 23:18:57.317427 Vdram = 0
3769 23:18:57.317511 Vddq = 0
3770 23:18:57.317596 Vmddr = 0
3771 23:18:57.323998 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3772 23:18:57.327329 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3773 23:18:57.330490 MEM_TYPE=3, freq_sel=19
3774 23:18:57.334172 sv_algorithm_assistance_LP4_1600
3775 23:18:57.337010 ============ PULL DRAM RESETB DOWN ============
3776 23:18:57.340395 ========== PULL DRAM RESETB DOWN end =========
3777 23:18:57.346854 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3778 23:18:57.349923 ===================================
3779 23:18:57.353894 LPDDR4 DRAM CONFIGURATION
3780 23:18:57.356940 ===================================
3781 23:18:57.357066 EX_ROW_EN[0] = 0x0
3782 23:18:57.360240 EX_ROW_EN[1] = 0x0
3783 23:18:57.360363 LP4Y_EN = 0x0
3784 23:18:57.363336 WORK_FSP = 0x0
3785 23:18:57.363436 WL = 0x2
3786 23:18:57.366644 RL = 0x2
3787 23:18:57.366718 BL = 0x2
3788 23:18:57.369795 RPST = 0x0
3789 23:18:57.369893 RD_PRE = 0x0
3790 23:18:57.373173 WR_PRE = 0x1
3791 23:18:57.373255 WR_PST = 0x0
3792 23:18:57.376662 DBI_WR = 0x0
3793 23:18:57.376745 DBI_RD = 0x0
3794 23:18:57.379787 OTF = 0x1
3795 23:18:57.383058 ===================================
3796 23:18:57.386616 ===================================
3797 23:18:57.386742 ANA top config
3798 23:18:57.389861 ===================================
3799 23:18:57.393222 DLL_ASYNC_EN = 0
3800 23:18:57.396463 ALL_SLAVE_EN = 1
3801 23:18:57.399713 NEW_RANK_MODE = 1
3802 23:18:57.402895 DLL_IDLE_MODE = 1
3803 23:18:57.403032 LP45_APHY_COMB_EN = 1
3804 23:18:57.405818 TX_ODT_DIS = 1
3805 23:18:57.409579 NEW_8X_MODE = 1
3806 23:18:57.413331 ===================================
3807 23:18:57.416252 ===================================
3808 23:18:57.418961 data_rate = 1200
3809 23:18:57.422344 CKR = 1
3810 23:18:57.426077 DQ_P2S_RATIO = 8
3811 23:18:57.426209 ===================================
3812 23:18:57.429213 CA_P2S_RATIO = 8
3813 23:18:57.432449 DQ_CA_OPEN = 0
3814 23:18:57.435818 DQ_SEMI_OPEN = 0
3815 23:18:57.439269 CA_SEMI_OPEN = 0
3816 23:18:57.442361 CA_FULL_RATE = 0
3817 23:18:57.446085 DQ_CKDIV4_EN = 1
3818 23:18:57.446214 CA_CKDIV4_EN = 1
3819 23:18:57.448586 CA_PREDIV_EN = 0
3820 23:18:57.452325 PH8_DLY = 0
3821 23:18:57.455376 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3822 23:18:57.458840 DQ_AAMCK_DIV = 4
3823 23:18:57.462476 CA_AAMCK_DIV = 4
3824 23:18:57.462568 CA_ADMCK_DIV = 4
3825 23:18:57.465465 DQ_TRACK_CA_EN = 0
3826 23:18:57.468381 CA_PICK = 600
3827 23:18:57.472087 CA_MCKIO = 600
3828 23:18:57.475068 MCKIO_SEMI = 0
3829 23:18:57.478630 PLL_FREQ = 2288
3830 23:18:57.481727 DQ_UI_PI_RATIO = 32
3831 23:18:57.481813 CA_UI_PI_RATIO = 0
3832 23:18:57.485153 ===================================
3833 23:18:57.488610 ===================================
3834 23:18:57.491918 memory_type:LPDDR4
3835 23:18:57.495063 GP_NUM : 10
3836 23:18:57.495189 SRAM_EN : 1
3837 23:18:57.498127 MD32_EN : 0
3838 23:18:57.501870 ===================================
3839 23:18:57.504847 [ANA_INIT] >>>>>>>>>>>>>>
3840 23:18:57.508404 <<<<<< [CONFIGURE PHASE]: ANA_TX
3841 23:18:57.511373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3842 23:18:57.514559 ===================================
3843 23:18:57.514687 data_rate = 1200,PCW = 0X5800
3844 23:18:57.518291 ===================================
3845 23:18:57.525012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3846 23:18:57.528016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3847 23:18:57.534536 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3848 23:18:57.537799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3849 23:18:57.541065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3850 23:18:57.544219 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3851 23:18:57.548006 [ANA_INIT] flow start
3852 23:18:57.550769 [ANA_INIT] PLL >>>>>>>>
3853 23:18:57.550899 [ANA_INIT] PLL <<<<<<<<
3854 23:18:57.554423 [ANA_INIT] MIDPI >>>>>>>>
3855 23:18:57.557468 [ANA_INIT] MIDPI <<<<<<<<
3856 23:18:57.557594 [ANA_INIT] DLL >>>>>>>>
3857 23:18:57.561001 [ANA_INIT] flow end
3858 23:18:57.564708 ============ LP4 DIFF to SE enter ============
3859 23:18:57.570982 ============ LP4 DIFF to SE exit ============
3860 23:18:57.571118 [ANA_INIT] <<<<<<<<<<<<<
3861 23:18:57.574121 [Flow] Enable top DCM control >>>>>
3862 23:18:57.577324 [Flow] Enable top DCM control <<<<<
3863 23:18:57.580872 Enable DLL master slave shuffle
3864 23:18:57.587564 ==============================================================
3865 23:18:57.587695 Gating Mode config
3866 23:18:57.593754 ==============================================================
3867 23:18:57.597333 Config description:
3868 23:18:57.606957 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3869 23:18:57.613519 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3870 23:18:57.616890 SELPH_MODE 0: By rank 1: By Phase
3871 23:18:57.623266 ==============================================================
3872 23:18:57.626678 GAT_TRACK_EN = 1
3873 23:18:57.630012 RX_GATING_MODE = 2
3874 23:18:57.630096 RX_GATING_TRACK_MODE = 2
3875 23:18:57.633290 SELPH_MODE = 1
3876 23:18:57.636599 PICG_EARLY_EN = 1
3877 23:18:57.639801 VALID_LAT_VALUE = 1
3878 23:18:57.646694 ==============================================================
3879 23:18:57.649981 Enter into Gating configuration >>>>
3880 23:18:57.653280 Exit from Gating configuration <<<<
3881 23:18:57.656258 Enter into DVFS_PRE_config >>>>>
3882 23:18:57.666519 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3883 23:18:57.670019 Exit from DVFS_PRE_config <<<<<
3884 23:18:57.672800 Enter into PICG configuration >>>>
3885 23:18:57.676009 Exit from PICG configuration <<<<
3886 23:18:57.679429 [RX_INPUT] configuration >>>>>
3887 23:18:57.683285 [RX_INPUT] configuration <<<<<
3888 23:18:57.686101 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3889 23:18:57.692599 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3890 23:18:57.699658 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3891 23:18:57.705961 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3892 23:18:57.712291 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3893 23:18:57.716110 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3894 23:18:57.722639 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3895 23:18:57.725552 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3896 23:18:57.728897 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3897 23:18:57.732462 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3898 23:18:57.738796 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3899 23:18:57.742235 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3900 23:18:57.745242 ===================================
3901 23:18:57.748704 LPDDR4 DRAM CONFIGURATION
3902 23:18:57.751809 ===================================
3903 23:18:57.751939 EX_ROW_EN[0] = 0x0
3904 23:18:57.755350 EX_ROW_EN[1] = 0x0
3905 23:18:57.755486 LP4Y_EN = 0x0
3906 23:18:57.758703 WORK_FSP = 0x0
3907 23:18:57.758811 WL = 0x2
3908 23:18:57.761949 RL = 0x2
3909 23:18:57.765258 BL = 0x2
3910 23:18:57.765362 RPST = 0x0
3911 23:18:57.768480 RD_PRE = 0x0
3912 23:18:57.768558 WR_PRE = 0x1
3913 23:18:57.771725 WR_PST = 0x0
3914 23:18:57.771800 DBI_WR = 0x0
3915 23:18:57.774875 DBI_RD = 0x0
3916 23:18:57.774952 OTF = 0x1
3917 23:18:57.778423 ===================================
3918 23:18:57.781497 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3919 23:18:57.788342 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3920 23:18:57.791333 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 23:18:57.794588 ===================================
3922 23:18:57.797796 LPDDR4 DRAM CONFIGURATION
3923 23:18:57.801157 ===================================
3924 23:18:57.801278 EX_ROW_EN[0] = 0x10
3925 23:18:57.804485 EX_ROW_EN[1] = 0x0
3926 23:18:57.807705 LP4Y_EN = 0x0
3927 23:18:57.807831 WORK_FSP = 0x0
3928 23:18:57.810867 WL = 0x2
3929 23:18:57.810991 RL = 0x2
3930 23:18:57.814646 BL = 0x2
3931 23:18:57.814730 RPST = 0x0
3932 23:18:57.817602 RD_PRE = 0x0
3933 23:18:57.817677 WR_PRE = 0x1
3934 23:18:57.820967 WR_PST = 0x0
3935 23:18:57.821045 DBI_WR = 0x0
3936 23:18:57.824047 DBI_RD = 0x0
3937 23:18:57.824122 OTF = 0x1
3938 23:18:57.827918 ===================================
3939 23:18:57.834246 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3940 23:18:57.838628 nWR fixed to 30
3941 23:18:57.841750 [ModeRegInit_LP4] CH0 RK0
3942 23:18:57.841855 [ModeRegInit_LP4] CH0 RK1
3943 23:18:57.844801 [ModeRegInit_LP4] CH1 RK0
3944 23:18:57.848156 [ModeRegInit_LP4] CH1 RK1
3945 23:18:57.848267 match AC timing 17
3946 23:18:57.855113 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3947 23:18:57.858377 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3948 23:18:57.861839 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3949 23:18:57.868399 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3950 23:18:57.871262 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3951 23:18:57.871347 ==
3952 23:18:57.874814 Dram Type= 6, Freq= 0, CH_0, rank 0
3953 23:18:57.878139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3954 23:18:57.878293 ==
3955 23:18:57.884756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3956 23:18:57.890987 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3957 23:18:57.894401 [CA 0] Center 36 (6~67) winsize 62
3958 23:18:57.898138 [CA 1] Center 36 (5~67) winsize 63
3959 23:18:57.900884 [CA 2] Center 34 (4~65) winsize 62
3960 23:18:57.904427 [CA 3] Center 34 (4~65) winsize 62
3961 23:18:57.907886 [CA 4] Center 33 (3~64) winsize 62
3962 23:18:57.910691 [CA 5] Center 33 (3~64) winsize 62
3963 23:18:57.910817
3964 23:18:57.913962 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3965 23:18:57.914090
3966 23:18:57.917931 [CATrainingPosCal] consider 1 rank data
3967 23:18:57.920606 u2DelayCellTimex100 = 270/100 ps
3968 23:18:57.924378 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3969 23:18:57.926983 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3970 23:18:57.933772 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 23:18:57.937211 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3972 23:18:57.940262 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 23:18:57.943498 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 23:18:57.943583
3975 23:18:57.946671 CA PerBit enable=1, Macro0, CA PI delay=33
3976 23:18:57.946756
3977 23:18:57.950066 [CBTSetCACLKResult] CA Dly = 33
3978 23:18:57.950171 CS Dly: 6 (0~37)
3979 23:18:57.953729 ==
3980 23:18:57.956695 Dram Type= 6, Freq= 0, CH_0, rank 1
3981 23:18:57.959742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 23:18:57.959851 ==
3983 23:18:57.966939 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3984 23:18:57.970036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3985 23:18:57.973652 [CA 0] Center 36 (6~67) winsize 62
3986 23:18:57.977389 [CA 1] Center 36 (6~67) winsize 62
3987 23:18:57.980679 [CA 2] Center 34 (4~65) winsize 62
3988 23:18:57.983887 [CA 3] Center 34 (4~65) winsize 62
3989 23:18:57.987780 [CA 4] Center 33 (3~64) winsize 62
3990 23:18:57.990832 [CA 5] Center 33 (3~64) winsize 62
3991 23:18:57.990933
3992 23:18:57.993394 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3993 23:18:57.993497
3994 23:18:57.996741 [CATrainingPosCal] consider 2 rank data
3995 23:18:58.000097 u2DelayCellTimex100 = 270/100 ps
3996 23:18:58.003460 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3997 23:18:58.010000 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3998 23:18:58.013594 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3999 23:18:58.016508 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4000 23:18:58.020085 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 23:18:58.023593 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4002 23:18:58.023713
4003 23:18:58.026338 CA PerBit enable=1, Macro0, CA PI delay=33
4004 23:18:58.026443
4005 23:18:58.030117 [CBTSetCACLKResult] CA Dly = 33
4006 23:18:58.033298 CS Dly: 6 (0~37)
4007 23:18:58.033399
4008 23:18:58.036746 ----->DramcWriteLeveling(PI) begin...
4009 23:18:58.036847 ==
4010 23:18:58.039407 Dram Type= 6, Freq= 0, CH_0, rank 0
4011 23:18:58.042980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 23:18:58.043080 ==
4013 23:18:58.046005 Write leveling (Byte 0): 33 => 33
4014 23:18:58.049725 Write leveling (Byte 1): 32 => 32
4015 23:18:58.052681 DramcWriteLeveling(PI) end<-----
4016 23:18:58.052796
4017 23:18:58.052889 ==
4018 23:18:58.056206 Dram Type= 6, Freq= 0, CH_0, rank 0
4019 23:18:58.059492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4020 23:18:58.059590 ==
4021 23:18:58.062651 [Gating] SW mode calibration
4022 23:18:58.069728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4023 23:18:58.075491 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4024 23:18:58.079266 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 23:18:58.085442 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 23:18:58.088731 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 23:18:58.092414 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4028 23:18:58.098549 0 9 16 | B1->B0 | 3030 2a2a | 0 0 | (0 0) (0 0)
4029 23:18:58.102132 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 23:18:58.105380 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 23:18:58.112013 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 23:18:58.114994 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 23:18:58.118291 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 23:18:58.125405 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 23:18:58.128334 0 10 12 | B1->B0 | 2a2a 2f2f | 0 0 | (0 0) (0 0)
4036 23:18:58.131801 0 10 16 | B1->B0 | 3e3e 4343 | 0 0 | (0 0) (1 1)
4037 23:18:58.138118 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 23:18:58.141313 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 23:18:58.144543 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 23:18:58.151170 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 23:18:58.154567 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 23:18:58.157790 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 23:18:58.164158 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 23:18:58.167602 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4045 23:18:58.170707 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 23:18:58.177363 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 23:18:58.180749 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 23:18:58.184097 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 23:18:58.190490 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 23:18:58.194328 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 23:18:58.197422 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 23:18:58.203871 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 23:18:58.207034 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 23:18:58.210744 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 23:18:58.216986 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 23:18:58.220465 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 23:18:58.223703 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 23:18:58.230081 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 23:18:58.233539 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4060 23:18:58.236809 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4061 23:18:58.240086 Total UI for P1: 0, mck2ui 16
4062 23:18:58.243335 best dqsien dly found for B0: ( 0, 13, 12)
4063 23:18:58.249894 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 23:18:58.250011 Total UI for P1: 0, mck2ui 16
4065 23:18:58.256355 best dqsien dly found for B1: ( 0, 13, 14)
4066 23:18:58.260173 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4067 23:18:58.263263 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4068 23:18:58.263372
4069 23:18:58.266486 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4070 23:18:58.269655 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4071 23:18:58.273087 [Gating] SW calibration Done
4072 23:18:58.273188 ==
4073 23:18:58.276246 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 23:18:58.279489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 23:18:58.279567 ==
4076 23:18:58.282595 RX Vref Scan: 0
4077 23:18:58.282678
4078 23:18:58.285858 RX Vref 0 -> 0, step: 1
4079 23:18:58.285940
4080 23:18:58.286005 RX Delay -230 -> 252, step: 16
4081 23:18:58.292895 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4082 23:18:58.296082 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4083 23:18:58.299695 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4084 23:18:58.302857 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4085 23:18:58.309450 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4086 23:18:58.312741 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4087 23:18:58.315984 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4088 23:18:58.319041 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4089 23:18:58.325977 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4090 23:18:58.328996 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4091 23:18:58.332337 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4092 23:18:58.335698 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4093 23:18:58.339206 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4094 23:18:58.345329 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4095 23:18:58.348631 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4096 23:18:58.352062 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4097 23:18:58.352146 ==
4098 23:18:58.355081 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 23:18:58.361970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 23:18:58.362046 ==
4101 23:18:58.362110 DQS Delay:
4102 23:18:58.364947 DQS0 = 0, DQS1 = 0
4103 23:18:58.365020 DQM Delay:
4104 23:18:58.365082 DQM0 = 40, DQM1 = 34
4105 23:18:58.368449 DQ Delay:
4106 23:18:58.371985 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4107 23:18:58.375270 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4108 23:18:58.378193 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4109 23:18:58.381485 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =33
4110 23:18:58.381597
4111 23:18:58.381693
4112 23:18:58.381783 ==
4113 23:18:58.384684 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 23:18:58.388444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 23:18:58.388558 ==
4116 23:18:58.388652
4117 23:18:58.388744
4118 23:18:58.391874 TX Vref Scan disable
4119 23:18:58.394716 == TX Byte 0 ==
4120 23:18:58.398071 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4121 23:18:58.401087 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4122 23:18:58.404416 == TX Byte 1 ==
4123 23:18:58.408151 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4124 23:18:58.411390 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4125 23:18:58.411486 ==
4126 23:18:58.414311 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 23:18:58.420999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 23:18:58.421104 ==
4129 23:18:58.421207
4130 23:18:58.421296
4131 23:18:58.421382 TX Vref Scan disable
4132 23:18:58.425192 == TX Byte 0 ==
4133 23:18:58.428331 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4134 23:18:58.435024 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4135 23:18:58.435128 == TX Byte 1 ==
4136 23:18:58.438254 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4137 23:18:58.445586 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4138 23:18:58.445695
4139 23:18:58.445822 [DATLAT]
4140 23:18:58.445911 Freq=600, CH0 RK0
4141 23:18:58.446002
4142 23:18:58.448191 DATLAT Default: 0x9
4143 23:18:58.451982 0, 0xFFFF, sum = 0
4144 23:18:58.452083 1, 0xFFFF, sum = 0
4145 23:18:58.455151 2, 0xFFFF, sum = 0
4146 23:18:58.455251 3, 0xFFFF, sum = 0
4147 23:18:58.458223 4, 0xFFFF, sum = 0
4148 23:18:58.458297 5, 0xFFFF, sum = 0
4149 23:18:58.461766 6, 0xFFFF, sum = 0
4150 23:18:58.461882 7, 0xFFFF, sum = 0
4151 23:18:58.464450 8, 0x0, sum = 1
4152 23:18:58.464524 9, 0x0, sum = 2
4153 23:18:58.467981 10, 0x0, sum = 3
4154 23:18:58.468069 11, 0x0, sum = 4
4155 23:18:58.468135 best_step = 9
4156 23:18:58.468198
4157 23:18:58.471531 ==
4158 23:18:58.474858 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 23:18:58.477883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 23:18:58.477985 ==
4161 23:18:58.478108 RX Vref Scan: 1
4162 23:18:58.478196
4163 23:18:58.481304 RX Vref 0 -> 0, step: 1
4164 23:18:58.481413
4165 23:18:58.484330 RX Delay -179 -> 252, step: 8
4166 23:18:58.484443
4167 23:18:58.487833 Set Vref, RX VrefLevel [Byte0]: 52
4168 23:18:58.491185 [Byte1]: 50
4169 23:18:58.491315
4170 23:18:58.494122 Final RX Vref Byte 0 = 52 to rank0
4171 23:18:58.497631 Final RX Vref Byte 1 = 50 to rank0
4172 23:18:58.500632 Final RX Vref Byte 0 = 52 to rank1
4173 23:18:58.504107 Final RX Vref Byte 1 = 50 to rank1==
4174 23:18:58.507204 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 23:18:58.514109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 23:18:58.514225 ==
4177 23:18:58.514323 DQS Delay:
4178 23:18:58.514415 DQS0 = 0, DQS1 = 0
4179 23:18:58.516948 DQM Delay:
4180 23:18:58.517048 DQM0 = 41, DQM1 = 33
4181 23:18:58.520632 DQ Delay:
4182 23:18:58.523927 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4183 23:18:58.526978 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4184 23:18:58.530546 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4185 23:18:58.533289 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4186 23:18:58.533373
4187 23:18:58.533439
4188 23:18:58.540285 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b42, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4189 23:18:58.543459 CH0 RK0: MR19=808, MR18=4B42
4190 23:18:58.550044 CH0_RK0: MR19=0x808, MR18=0x4B42, DQSOSC=395, MR23=63, INC=168, DEC=112
4191 23:18:58.550146
4192 23:18:58.553508 ----->DramcWriteLeveling(PI) begin...
4193 23:18:58.553581 ==
4194 23:18:58.556520 Dram Type= 6, Freq= 0, CH_0, rank 1
4195 23:18:58.560029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 23:18:58.560117 ==
4197 23:18:58.563112 Write leveling (Byte 0): 32 => 32
4198 23:18:58.566565 Write leveling (Byte 1): 30 => 30
4199 23:18:58.570174 DramcWriteLeveling(PI) end<-----
4200 23:18:58.570276
4201 23:18:58.570344 ==
4202 23:18:58.572941 Dram Type= 6, Freq= 0, CH_0, rank 1
4203 23:18:58.576766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 23:18:58.579491 ==
4205 23:18:58.579575 [Gating] SW mode calibration
4206 23:18:58.589765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4207 23:18:58.592769 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4208 23:18:58.596093 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 23:18:58.603081 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 23:18:58.605742 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4211 23:18:58.609499 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4212 23:18:58.615826 0 9 16 | B1->B0 | 3030 2424 | 0 0 | (1 1) (0 0)
4213 23:18:58.619355 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4214 23:18:58.622483 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 23:18:58.628841 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 23:18:58.632104 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 23:18:58.635661 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 23:18:58.642359 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 23:18:58.645389 0 10 12 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
4220 23:18:58.648929 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4221 23:18:58.655527 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 23:18:58.659293 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 23:18:58.662271 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 23:18:58.668624 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 23:18:58.672199 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 23:18:58.675222 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 23:18:58.682203 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4228 23:18:58.685577 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4229 23:18:58.688409 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 23:18:58.694953 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 23:18:58.698554 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 23:18:58.701740 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 23:18:58.708331 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 23:18:58.711190 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 23:18:58.714773 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 23:18:58.721202 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 23:18:58.724916 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 23:18:58.728027 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 23:18:58.734674 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 23:18:58.738476 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:18:58.741352 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:18:58.748328 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:18:58.751180 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4244 23:18:58.754709 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 23:18:58.758054 Total UI for P1: 0, mck2ui 16
4246 23:18:58.761354 best dqsien dly found for B0: ( 0, 13, 12)
4247 23:18:58.764172 Total UI for P1: 0, mck2ui 16
4248 23:18:58.768087 best dqsien dly found for B1: ( 0, 13, 14)
4249 23:18:58.770999 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4250 23:18:58.773992 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4251 23:18:58.777830
4252 23:18:58.781181 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4253 23:18:58.783897 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4254 23:18:58.787531 [Gating] SW calibration Done
4255 23:18:58.787623 ==
4256 23:18:58.790529 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 23:18:58.794220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 23:18:58.794309 ==
4259 23:18:58.797334 RX Vref Scan: 0
4260 23:18:58.797440
4261 23:18:58.797532 RX Vref 0 -> 0, step: 1
4262 23:18:58.797628
4263 23:18:58.800612 RX Delay -230 -> 252, step: 16
4264 23:18:58.803650 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4265 23:18:58.810078 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4266 23:18:58.813976 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4267 23:18:58.816770 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4268 23:18:58.820443 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4269 23:18:58.826888 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4270 23:18:58.830093 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4271 23:18:58.833443 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4272 23:18:58.836872 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4273 23:18:58.839812 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4274 23:18:58.846719 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4275 23:18:58.850437 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4276 23:18:58.853482 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4277 23:18:58.859785 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4278 23:18:58.863038 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4279 23:18:58.866509 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4280 23:18:58.866603 ==
4281 23:18:58.869797 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 23:18:58.872659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 23:18:58.872744 ==
4284 23:18:58.876142 DQS Delay:
4285 23:18:58.876226 DQS0 = 0, DQS1 = 0
4286 23:18:58.879545 DQM Delay:
4287 23:18:58.879630 DQM0 = 42, DQM1 = 32
4288 23:18:58.879697 DQ Delay:
4289 23:18:58.883081 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4290 23:18:58.885846 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4291 23:18:58.889779 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4292 23:18:58.892890 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =33
4293 23:18:58.892977
4294 23:18:58.893044
4295 23:18:58.895780 ==
4296 23:18:58.899800 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 23:18:58.902338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 23:18:58.902423 ==
4299 23:18:58.902490
4300 23:18:58.902552
4301 23:18:58.905688 TX Vref Scan disable
4302 23:18:58.905773 == TX Byte 0 ==
4303 23:18:58.912229 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4304 23:18:58.915941 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4305 23:18:58.916025 == TX Byte 1 ==
4306 23:18:58.922210 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4307 23:18:58.925696 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4308 23:18:58.925781 ==
4309 23:18:58.929276 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 23:18:58.932114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 23:18:58.932199 ==
4312 23:18:58.932266
4313 23:18:58.932328
4314 23:18:58.935414 TX Vref Scan disable
4315 23:18:58.938751 == TX Byte 0 ==
4316 23:18:58.942635 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4317 23:18:58.948781 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4318 23:18:58.948867 == TX Byte 1 ==
4319 23:18:58.951803 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4320 23:18:58.958489 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4321 23:18:58.958575
4322 23:18:58.958642 [DATLAT]
4323 23:18:58.958704 Freq=600, CH0 RK1
4324 23:18:58.958763
4325 23:18:58.961961 DATLAT Default: 0x9
4326 23:18:58.962045 0, 0xFFFF, sum = 0
4327 23:18:58.965190 1, 0xFFFF, sum = 0
4328 23:18:58.968336 2, 0xFFFF, sum = 0
4329 23:18:58.968421 3, 0xFFFF, sum = 0
4330 23:18:58.971733 4, 0xFFFF, sum = 0
4331 23:18:58.971818 5, 0xFFFF, sum = 0
4332 23:18:58.974814 6, 0xFFFF, sum = 0
4333 23:18:58.974900 7, 0xFFFF, sum = 0
4334 23:18:58.978200 8, 0x0, sum = 1
4335 23:18:58.978289 9, 0x0, sum = 2
4336 23:18:58.981330 10, 0x0, sum = 3
4337 23:18:58.981418 11, 0x0, sum = 4
4338 23:18:58.981486 best_step = 9
4339 23:18:58.981548
4340 23:18:58.984912 ==
4341 23:18:58.988215 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 23:18:58.991492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 23:18:58.991578 ==
4344 23:18:58.991652 RX Vref Scan: 0
4345 23:18:58.991717
4346 23:18:58.994682 RX Vref 0 -> 0, step: 1
4347 23:18:58.994766
4348 23:18:58.998444 RX Delay -195 -> 252, step: 8
4349 23:18:59.004636 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4350 23:18:59.007688 iDelay=197, Bit 1, Center 40 (-115 ~ 196) 312
4351 23:18:59.010829 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4352 23:18:59.014171 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4353 23:18:59.021203 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4354 23:18:59.024085 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4355 23:18:59.027735 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4356 23:18:59.031185 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4357 23:18:59.034038 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4358 23:18:59.040657 iDelay=197, Bit 9, Center 20 (-139 ~ 180) 320
4359 23:18:59.044328 iDelay=197, Bit 10, Center 32 (-123 ~ 188) 312
4360 23:18:59.047838 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4361 23:18:59.050630 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4362 23:18:59.057554 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4363 23:18:59.060308 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4364 23:18:59.063931 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4365 23:18:59.064082 ==
4366 23:18:59.067031 Dram Type= 6, Freq= 0, CH_0, rank 1
4367 23:18:59.073379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 23:18:59.073466 ==
4369 23:18:59.073535 DQS Delay:
4370 23:18:59.073598 DQS0 = 0, DQS1 = 0
4371 23:18:59.076652 DQM Delay:
4372 23:18:59.076721 DQM0 = 39, DQM1 = 33
4373 23:18:59.080095 DQ Delay:
4374 23:18:59.083214 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4375 23:18:59.086909 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4376 23:18:59.090043 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4377 23:18:59.093324 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4378 23:18:59.093447
4379 23:18:59.093560
4380 23:18:59.099732 [DQSOSCAuto] RK1, (LSB)MR18= 0x4641, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4381 23:18:59.102944 CH0 RK1: MR19=808, MR18=4641
4382 23:18:59.109574 CH0_RK1: MR19=0x808, MR18=0x4641, DQSOSC=396, MR23=63, INC=167, DEC=111
4383 23:18:59.113201 [RxdqsGatingPostProcess] freq 600
4384 23:18:59.116093 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4385 23:18:59.119485 Pre-setting of DQS Precalculation
4386 23:18:59.126110 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4387 23:18:59.126241 ==
4388 23:18:59.129162 Dram Type= 6, Freq= 0, CH_1, rank 0
4389 23:18:59.132610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 23:18:59.132715 ==
4391 23:18:59.139321 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4392 23:18:59.145936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4393 23:18:59.148825 [CA 0] Center 36 (6~66) winsize 61
4394 23:18:59.152662 [CA 1] Center 35 (5~66) winsize 62
4395 23:18:59.155734 [CA 2] Center 34 (4~65) winsize 62
4396 23:18:59.158734 [CA 3] Center 34 (3~65) winsize 63
4397 23:18:59.162250 [CA 4] Center 34 (4~65) winsize 62
4398 23:18:59.165291 [CA 5] Center 33 (3~64) winsize 62
4399 23:18:59.165398
4400 23:18:59.168887 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4401 23:18:59.168987
4402 23:18:59.172062 [CATrainingPosCal] consider 1 rank data
4403 23:18:59.175885 u2DelayCellTimex100 = 270/100 ps
4404 23:18:59.178812 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4405 23:18:59.181785 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4406 23:18:59.185367 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4407 23:18:59.188471 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4408 23:18:59.191589 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 23:18:59.198185 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4410 23:18:59.198267
4411 23:18:59.201634 CA PerBit enable=1, Macro0, CA PI delay=33
4412 23:18:59.201728
4413 23:18:59.204687 [CBTSetCACLKResult] CA Dly = 33
4414 23:18:59.204761 CS Dly: 5 (0~36)
4415 23:18:59.204846 ==
4416 23:18:59.208447 Dram Type= 6, Freq= 0, CH_1, rank 1
4417 23:18:59.215032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 23:18:59.215165 ==
4419 23:18:59.218382 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4420 23:18:59.224836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4421 23:18:59.228208 [CA 0] Center 36 (6~66) winsize 61
4422 23:18:59.231718 [CA 1] Center 36 (6~66) winsize 61
4423 23:18:59.234528 [CA 2] Center 34 (4~65) winsize 62
4424 23:18:59.237555 [CA 3] Center 34 (4~65) winsize 62
4425 23:18:59.240867 [CA 4] Center 34 (4~65) winsize 62
4426 23:18:59.244501 [CA 5] Center 34 (3~65) winsize 63
4427 23:18:59.244626
4428 23:18:59.247461 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4429 23:18:59.247588
4430 23:18:59.250999 [CATrainingPosCal] consider 2 rank data
4431 23:18:59.254738 u2DelayCellTimex100 = 270/100 ps
4432 23:18:59.257682 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4433 23:18:59.264278 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4434 23:18:59.267096 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 23:18:59.270903 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4436 23:18:59.274033 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4437 23:18:59.277153 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4438 23:18:59.277255
4439 23:18:59.280750 CA PerBit enable=1, Macro0, CA PI delay=33
4440 23:18:59.280834
4441 23:18:59.283593 [CBTSetCACLKResult] CA Dly = 33
4442 23:18:59.286883 CS Dly: 5 (0~36)
4443 23:18:59.286966
4444 23:18:59.290062 ----->DramcWriteLeveling(PI) begin...
4445 23:18:59.290147 ==
4446 23:18:59.294014 Dram Type= 6, Freq= 0, CH_1, rank 0
4447 23:18:59.296568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 23:18:59.296658 ==
4449 23:18:59.300075 Write leveling (Byte 0): 29 => 29
4450 23:18:59.303632 Write leveling (Byte 1): 29 => 29
4451 23:18:59.306873 DramcWriteLeveling(PI) end<-----
4452 23:18:59.306957
4453 23:18:59.307023 ==
4454 23:18:59.310083 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 23:18:59.313030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 23:18:59.313115 ==
4457 23:18:59.316494 [Gating] SW mode calibration
4458 23:18:59.322952 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4459 23:18:59.329643 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4460 23:18:59.333231 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 23:18:59.336210 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4462 23:18:59.342936 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 23:18:59.346248 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4464 23:18:59.352571 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 23:18:59.355980 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 23:18:59.359274 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 23:18:59.365845 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 23:18:59.369054 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 23:18:59.372350 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 23:18:59.375571 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 23:18:59.382105 0 10 12 | B1->B0 | 3232 3635 | 0 1 | (1 1) (1 1)
4472 23:18:59.386024 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 23:18:59.388786 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 23:18:59.395504 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 23:18:59.398947 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 23:18:59.402176 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 23:18:59.408977 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 23:18:59.412091 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 23:18:59.415630 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 23:18:59.421883 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 23:18:59.425422 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 23:18:59.428802 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 23:18:59.434952 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 23:18:59.438275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 23:18:59.444860 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 23:18:59.447923 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 23:18:59.451452 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 23:18:59.457941 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 23:18:59.461381 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 23:18:59.464882 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 23:18:59.471019 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 23:18:59.474938 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 23:18:59.477836 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 23:18:59.484679 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 23:18:59.487671 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4496 23:18:59.490962 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 23:18:59.494164 Total UI for P1: 0, mck2ui 16
4498 23:18:59.497787 best dqsien dly found for B0: ( 0, 13, 12)
4499 23:18:59.501155 Total UI for P1: 0, mck2ui 16
4500 23:18:59.504560 best dqsien dly found for B1: ( 0, 13, 14)
4501 23:18:59.507821 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4502 23:18:59.510685 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4503 23:18:59.510788
4504 23:18:59.517443 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4505 23:18:59.520920 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4506 23:18:59.520999 [Gating] SW calibration Done
4507 23:18:59.524182 ==
4508 23:18:59.527547 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 23:18:59.530818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 23:18:59.530922 ==
4511 23:18:59.531017 RX Vref Scan: 0
4512 23:18:59.531110
4513 23:18:59.533823 RX Vref 0 -> 0, step: 1
4514 23:18:59.533932
4515 23:18:59.537128 RX Delay -230 -> 252, step: 16
4516 23:18:59.540357 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4517 23:18:59.543740 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4518 23:18:59.550600 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4519 23:18:59.553599 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4520 23:18:59.557173 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4521 23:18:59.560176 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4522 23:18:59.566766 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4523 23:18:59.570313 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4524 23:18:59.573399 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4525 23:18:59.576746 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4526 23:18:59.580493 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4527 23:18:59.586835 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4528 23:18:59.590013 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4529 23:18:59.593361 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4530 23:18:59.596688 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4531 23:18:59.603552 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4532 23:18:59.603638 ==
4533 23:18:59.606910 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 23:18:59.609755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 23:18:59.609860 ==
4536 23:18:59.609954 DQS Delay:
4537 23:18:59.613390 DQS0 = 0, DQS1 = 0
4538 23:18:59.613471 DQM Delay:
4539 23:18:59.616310 DQM0 = 45, DQM1 = 39
4540 23:18:59.616391 DQ Delay:
4541 23:18:59.619576 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4542 23:18:59.622933 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4543 23:18:59.626289 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4544 23:18:59.629982 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4545 23:18:59.630112
4546 23:18:59.630177
4547 23:18:59.630238 ==
4548 23:18:59.632953 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 23:18:59.639565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 23:18:59.639681 ==
4551 23:18:59.639747
4552 23:18:59.639808
4553 23:18:59.639867 TX Vref Scan disable
4554 23:18:59.643028 == TX Byte 0 ==
4555 23:18:59.646484 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4556 23:18:59.652769 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4557 23:18:59.652855 == TX Byte 1 ==
4558 23:18:59.656007 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4559 23:18:59.662857 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4560 23:18:59.662940 ==
4561 23:18:59.665895 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 23:18:59.669122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 23:18:59.669205 ==
4564 23:18:59.669271
4565 23:18:59.669333
4566 23:18:59.672724 TX Vref Scan disable
4567 23:18:59.675739 == TX Byte 0 ==
4568 23:18:59.679384 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4569 23:18:59.682296 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4570 23:18:59.685775 == TX Byte 1 ==
4571 23:18:59.689024 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4572 23:18:59.692541 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4573 23:18:59.692623
4574 23:18:59.692688 [DATLAT]
4575 23:18:59.695689 Freq=600, CH1 RK0
4576 23:18:59.695771
4577 23:18:59.699096 DATLAT Default: 0x9
4578 23:18:59.699177 0, 0xFFFF, sum = 0
4579 23:18:59.702136 1, 0xFFFF, sum = 0
4580 23:18:59.702261 2, 0xFFFF, sum = 0
4581 23:18:59.705380 3, 0xFFFF, sum = 0
4582 23:18:59.705507 4, 0xFFFF, sum = 0
4583 23:18:59.709016 5, 0xFFFF, sum = 0
4584 23:18:59.709143 6, 0xFFFF, sum = 0
4585 23:18:59.712170 7, 0xFFFF, sum = 0
4586 23:18:59.712294 8, 0x0, sum = 1
4587 23:18:59.715301 9, 0x0, sum = 2
4588 23:18:59.715428 10, 0x0, sum = 3
4589 23:18:59.718930 11, 0x0, sum = 4
4590 23:18:59.719056 best_step = 9
4591 23:18:59.719169
4592 23:18:59.719280 ==
4593 23:18:59.721919 Dram Type= 6, Freq= 0, CH_1, rank 0
4594 23:18:59.725413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 23:18:59.728558 ==
4596 23:18:59.728642 RX Vref Scan: 1
4597 23:18:59.728708
4598 23:18:59.732348 RX Vref 0 -> 0, step: 1
4599 23:18:59.732432
4600 23:18:59.735187 RX Delay -179 -> 252, step: 8
4601 23:18:59.735296
4602 23:18:59.738470 Set Vref, RX VrefLevel [Byte0]: 50
4603 23:18:59.741375 [Byte1]: 53
4604 23:18:59.741459
4605 23:18:59.744761 Final RX Vref Byte 0 = 50 to rank0
4606 23:18:59.748172 Final RX Vref Byte 1 = 53 to rank0
4607 23:18:59.751187 Final RX Vref Byte 0 = 50 to rank1
4608 23:18:59.754632 Final RX Vref Byte 1 = 53 to rank1==
4609 23:18:59.757950 Dram Type= 6, Freq= 0, CH_1, rank 0
4610 23:18:59.761008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 23:18:59.761092 ==
4612 23:18:59.764596 DQS Delay:
4613 23:18:59.764679 DQS0 = 0, DQS1 = 0
4614 23:18:59.764746 DQM Delay:
4615 23:18:59.767621 DQM0 = 45, DQM1 = 36
4616 23:18:59.767704 DQ Delay:
4617 23:18:59.771181 DQ0 =52, DQ1 =44, DQ2 =32, DQ3 =44
4618 23:18:59.774323 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4619 23:18:59.777892 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =32
4620 23:18:59.780954 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4621 23:18:59.781082
4622 23:18:59.781200
4623 23:18:59.790892 [DQSOSCAuto] RK0, (LSB)MR18= 0x2842, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4624 23:18:59.793756 CH1 RK0: MR19=808, MR18=2842
4625 23:18:59.800604 CH1_RK0: MR19=0x808, MR18=0x2842, DQSOSC=397, MR23=63, INC=166, DEC=110
4626 23:18:59.800689
4627 23:18:59.803890 ----->DramcWriteLeveling(PI) begin...
4628 23:18:59.803975 ==
4629 23:18:59.807118 Dram Type= 6, Freq= 0, CH_1, rank 1
4630 23:18:59.810359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 23:18:59.810442 ==
4632 23:18:59.813728 Write leveling (Byte 0): 29 => 29
4633 23:18:59.817146 Write leveling (Byte 1): 29 => 29
4634 23:18:59.820252 DramcWriteLeveling(PI) end<-----
4635 23:18:59.820334
4636 23:18:59.820398 ==
4637 23:18:59.823562 Dram Type= 6, Freq= 0, CH_1, rank 1
4638 23:18:59.826847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 23:18:59.826959 ==
4640 23:18:59.830011 [Gating] SW mode calibration
4641 23:18:59.837002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4642 23:18:59.843516 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4643 23:18:59.846505 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4644 23:18:59.850154 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4645 23:18:59.856695 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 23:18:59.859536 0 9 12 | B1->B0 | 3131 2c2c | 1 1 | (1 1) (1 0)
4647 23:18:59.863099 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 23:18:59.869858 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 23:18:59.872812 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 23:18:59.876559 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 23:18:59.883179 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 23:18:59.886255 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 23:18:59.889809 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4654 23:18:59.896175 0 10 12 | B1->B0 | 2b2b 3d3d | 0 0 | (0 0) (0 0)
4655 23:18:59.899450 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 23:18:59.902740 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 23:18:59.909223 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 23:18:59.912431 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 23:18:59.916062 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 23:18:59.922400 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 23:18:59.925858 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 23:18:59.928730 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 23:18:59.935721 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 23:18:59.939150 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 23:18:59.942294 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 23:18:59.948810 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 23:18:59.952047 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 23:18:59.955103 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 23:18:59.961919 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 23:18:59.964969 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 23:18:59.968668 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 23:18:59.974836 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 23:18:59.978155 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 23:18:59.981491 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 23:18:59.987878 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 23:18:59.991405 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 23:18:59.994681 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4678 23:19:00.001299 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 23:19:00.004425 Total UI for P1: 0, mck2ui 16
4680 23:19:00.008006 best dqsien dly found for B0: ( 0, 13, 8)
4681 23:19:00.011291 Total UI for P1: 0, mck2ui 16
4682 23:19:00.014653 best dqsien dly found for B1: ( 0, 13, 8)
4683 23:19:00.017643 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4684 23:19:00.021197 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4685 23:19:00.021301
4686 23:19:00.024536 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4687 23:19:00.027622 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4688 23:19:00.030960 [Gating] SW calibration Done
4689 23:19:00.031037 ==
4690 23:19:00.033958 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 23:19:00.037542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 23:19:00.037622 ==
4693 23:19:00.040951 RX Vref Scan: 0
4694 23:19:00.041030
4695 23:19:00.043786 RX Vref 0 -> 0, step: 1
4696 23:19:00.043863
4697 23:19:00.043945 RX Delay -230 -> 252, step: 16
4698 23:19:00.050612 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4699 23:19:00.053864 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4700 23:19:00.057146 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4701 23:19:00.060524 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4702 23:19:00.067225 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4703 23:19:00.070271 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4704 23:19:00.073559 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4705 23:19:00.077355 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4706 23:19:00.083637 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4707 23:19:00.087268 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4708 23:19:00.090365 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4709 23:19:00.093887 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4710 23:19:00.100275 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4711 23:19:00.103589 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4712 23:19:00.106940 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4713 23:19:00.109802 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4714 23:19:00.109912 ==
4715 23:19:00.113236 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 23:19:00.120036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 23:19:00.120119 ==
4718 23:19:00.120184 DQS Delay:
4719 23:19:00.123040 DQS0 = 0, DQS1 = 0
4720 23:19:00.123121 DQM Delay:
4721 23:19:00.123187 DQM0 = 43, DQM1 = 39
4722 23:19:00.126786 DQ Delay:
4723 23:19:00.130104 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4724 23:19:00.133194 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4725 23:19:00.136288 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4726 23:19:00.139916 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4727 23:19:00.139990
4728 23:19:00.140053
4729 23:19:00.140125 ==
4730 23:19:00.142806 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 23:19:00.146383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 23:19:00.146481 ==
4733 23:19:00.146577
4734 23:19:00.146669
4735 23:19:00.150010 TX Vref Scan disable
4736 23:19:00.153273 == TX Byte 0 ==
4737 23:19:00.156412 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4738 23:19:00.159485 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4739 23:19:00.162700 == TX Byte 1 ==
4740 23:19:00.165926 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4741 23:19:00.169341 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4742 23:19:00.169478 ==
4743 23:19:00.172532 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 23:19:00.175891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 23:19:00.179581 ==
4746 23:19:00.179744
4747 23:19:00.179857
4748 23:19:00.179965 TX Vref Scan disable
4749 23:19:00.183203 == TX Byte 0 ==
4750 23:19:00.186280 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4751 23:19:00.193002 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4752 23:19:00.193125 == TX Byte 1 ==
4753 23:19:00.196486 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4754 23:19:00.202681 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4755 23:19:00.202805
4756 23:19:00.202922 [DATLAT]
4757 23:19:00.203032 Freq=600, CH1 RK1
4758 23:19:00.203143
4759 23:19:00.206248 DATLAT Default: 0x9
4760 23:19:00.209651 0, 0xFFFF, sum = 0
4761 23:19:00.209773 1, 0xFFFF, sum = 0
4762 23:19:00.212569 2, 0xFFFF, sum = 0
4763 23:19:00.212695 3, 0xFFFF, sum = 0
4764 23:19:00.215958 4, 0xFFFF, sum = 0
4765 23:19:00.216086 5, 0xFFFF, sum = 0
4766 23:19:00.219499 6, 0xFFFF, sum = 0
4767 23:19:00.219628 7, 0xFFFF, sum = 0
4768 23:19:00.222471 8, 0x0, sum = 1
4769 23:19:00.222598 9, 0x0, sum = 2
4770 23:19:00.226143 10, 0x0, sum = 3
4771 23:19:00.226272 11, 0x0, sum = 4
4772 23:19:00.226390 best_step = 9
4773 23:19:00.226501
4774 23:19:00.229363 ==
4775 23:19:00.232566 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 23:19:00.235975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 23:19:00.236101 ==
4778 23:19:00.236218 RX Vref Scan: 0
4779 23:19:00.236328
4780 23:19:00.239381 RX Vref 0 -> 0, step: 1
4781 23:19:00.239507
4782 23:19:00.242609 RX Delay -179 -> 252, step: 8
4783 23:19:00.249083 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4784 23:19:00.252546 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4785 23:19:00.255635 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4786 23:19:00.259222 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4787 23:19:00.262508 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4788 23:19:00.269046 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4789 23:19:00.272245 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4790 23:19:00.275654 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4791 23:19:00.278869 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4792 23:19:00.285298 iDelay=205, Bit 9, Center 28 (-123 ~ 180) 304
4793 23:19:00.288593 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4794 23:19:00.292088 iDelay=205, Bit 11, Center 32 (-123 ~ 188) 312
4795 23:19:00.295246 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4796 23:19:00.302033 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4797 23:19:00.305498 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4798 23:19:00.308552 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4799 23:19:00.308675 ==
4800 23:19:00.312221 Dram Type= 6, Freq= 0, CH_1, rank 1
4801 23:19:00.315482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4802 23:19:00.318666 ==
4803 23:19:00.318787 DQS Delay:
4804 23:19:00.318901 DQS0 = 0, DQS1 = 0
4805 23:19:00.321809 DQM Delay:
4806 23:19:00.321932 DQM0 = 39, DQM1 = 38
4807 23:19:00.325173 DQ Delay:
4808 23:19:00.328360 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4809 23:19:00.328441 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =36
4810 23:19:00.331533 DQ8 =24, DQ9 =28, DQ10 =40, DQ11 =32
4811 23:19:00.334697 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =48
4812 23:19:00.338085
4813 23:19:00.338160
4814 23:19:00.344967 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4815 23:19:00.347926 CH1 RK1: MR19=808, MR18=3A5E
4816 23:19:00.354597 CH1_RK1: MR19=0x808, MR18=0x3A5E, DQSOSC=392, MR23=63, INC=170, DEC=113
4817 23:19:00.357825 [RxdqsGatingPostProcess] freq 600
4818 23:19:00.361114 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4819 23:19:00.364399 Pre-setting of DQS Precalculation
4820 23:19:00.370839 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4821 23:19:00.377526 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4822 23:19:00.384448 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4823 23:19:00.384544
4824 23:19:00.384612
4825 23:19:00.387550 [Calibration Summary] 1200 Mbps
4826 23:19:00.387625 CH 0, Rank 0
4827 23:19:00.390501 SW Impedance : PASS
4828 23:19:00.394175 DUTY Scan : NO K
4829 23:19:00.394254 ZQ Calibration : PASS
4830 23:19:00.397068 Jitter Meter : NO K
4831 23:19:00.400956 CBT Training : PASS
4832 23:19:00.401035 Write leveling : PASS
4833 23:19:00.403728 RX DQS gating : PASS
4834 23:19:00.407583 RX DQ/DQS(RDDQC) : PASS
4835 23:19:00.407660 TX DQ/DQS : PASS
4836 23:19:00.410604 RX DATLAT : PASS
4837 23:19:00.413508 RX DQ/DQS(Engine): PASS
4838 23:19:00.413596 TX OE : NO K
4839 23:19:00.416945 All Pass.
4840 23:19:00.417021
4841 23:19:00.417082 CH 0, Rank 1
4842 23:19:00.420306 SW Impedance : PASS
4843 23:19:00.420382 DUTY Scan : NO K
4844 23:19:00.423618 ZQ Calibration : PASS
4845 23:19:00.426989 Jitter Meter : NO K
4846 23:19:00.427068 CBT Training : PASS
4847 23:19:00.430048 Write leveling : PASS
4848 23:19:00.433423 RX DQS gating : PASS
4849 23:19:00.433498 RX DQ/DQS(RDDQC) : PASS
4850 23:19:00.436886 TX DQ/DQS : PASS
4851 23:19:00.440160 RX DATLAT : PASS
4852 23:19:00.440233 RX DQ/DQS(Engine): PASS
4853 23:19:00.443276 TX OE : NO K
4854 23:19:00.443386 All Pass.
4855 23:19:00.443490
4856 23:19:00.446518 CH 1, Rank 0
4857 23:19:00.446603 SW Impedance : PASS
4858 23:19:00.449613 DUTY Scan : NO K
4859 23:19:00.453002 ZQ Calibration : PASS
4860 23:19:00.453085 Jitter Meter : NO K
4861 23:19:00.456408 CBT Training : PASS
4862 23:19:00.459871 Write leveling : PASS
4863 23:19:00.459971 RX DQS gating : PASS
4864 23:19:00.463015 RX DQ/DQS(RDDQC) : PASS
4865 23:19:00.463112 TX DQ/DQS : PASS
4866 23:19:00.466366 RX DATLAT : PASS
4867 23:19:00.469599 RX DQ/DQS(Engine): PASS
4868 23:19:00.469697 TX OE : NO K
4869 23:19:00.472780 All Pass.
4870 23:19:00.472855
4871 23:19:00.472917 CH 1, Rank 1
4872 23:19:00.475977 SW Impedance : PASS
4873 23:19:00.476074 DUTY Scan : NO K
4874 23:19:00.479252 ZQ Calibration : PASS
4875 23:19:00.482914 Jitter Meter : NO K
4876 23:19:00.483015 CBT Training : PASS
4877 23:19:00.486004 Write leveling : PASS
4878 23:19:00.489278 RX DQS gating : PASS
4879 23:19:00.489437 RX DQ/DQS(RDDQC) : PASS
4880 23:19:00.492433 TX DQ/DQS : PASS
4881 23:19:00.495729 RX DATLAT : PASS
4882 23:19:00.495821 RX DQ/DQS(Engine): PASS
4883 23:19:00.499094 TX OE : NO K
4884 23:19:00.499239 All Pass.
4885 23:19:00.499334
4886 23:19:00.502125 DramC Write-DBI off
4887 23:19:00.505887 PER_BANK_REFRESH: Hybrid Mode
4888 23:19:00.505987 TX_TRACKING: ON
4889 23:19:00.515582 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4890 23:19:00.518620 [FAST_K] Save calibration result to emmc
4891 23:19:00.522252 dramc_set_vcore_voltage set vcore to 662500
4892 23:19:00.525454 Read voltage for 933, 3
4893 23:19:00.525529 Vio18 = 0
4894 23:19:00.525596 Vcore = 662500
4895 23:19:00.528495 Vdram = 0
4896 23:19:00.528614 Vddq = 0
4897 23:19:00.528735 Vmddr = 0
4898 23:19:00.535019 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4899 23:19:00.542036 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4900 23:19:00.542138 MEM_TYPE=3, freq_sel=17
4901 23:19:00.544845 sv_algorithm_assistance_LP4_1600
4902 23:19:00.548352 ============ PULL DRAM RESETB DOWN ============
4903 23:19:00.554959 ========== PULL DRAM RESETB DOWN end =========
4904 23:19:00.558242 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4905 23:19:00.561741 ===================================
4906 23:19:00.565076 LPDDR4 DRAM CONFIGURATION
4907 23:19:00.568217 ===================================
4908 23:19:00.568292 EX_ROW_EN[0] = 0x0
4909 23:19:00.571429 EX_ROW_EN[1] = 0x0
4910 23:19:00.571571 LP4Y_EN = 0x0
4911 23:19:00.574510 WORK_FSP = 0x0
4912 23:19:00.578233 WL = 0x3
4913 23:19:00.578332 RL = 0x3
4914 23:19:00.581825 BL = 0x2
4915 23:19:00.581929 RPST = 0x0
4916 23:19:00.584507 RD_PRE = 0x0
4917 23:19:00.584605 WR_PRE = 0x1
4918 23:19:00.587698 WR_PST = 0x0
4919 23:19:00.587802 DBI_WR = 0x0
4920 23:19:00.591077 DBI_RD = 0x0
4921 23:19:00.591192 OTF = 0x1
4922 23:19:00.594856 ===================================
4923 23:19:00.597456 ===================================
4924 23:19:00.601371 ANA top config
4925 23:19:00.604412 ===================================
4926 23:19:00.604526 DLL_ASYNC_EN = 0
4927 23:19:00.608339 ALL_SLAVE_EN = 1
4928 23:19:00.610835 NEW_RANK_MODE = 1
4929 23:19:00.614238 DLL_IDLE_MODE = 1
4930 23:19:00.617759 LP45_APHY_COMB_EN = 1
4931 23:19:00.617862 TX_ODT_DIS = 1
4932 23:19:00.620883 NEW_8X_MODE = 1
4933 23:19:00.624209 ===================================
4934 23:19:00.627241 ===================================
4935 23:19:00.630823 data_rate = 1866
4936 23:19:00.634057 CKR = 1
4937 23:19:00.637057 DQ_P2S_RATIO = 8
4938 23:19:00.640176 ===================================
4939 23:19:00.643606 CA_P2S_RATIO = 8
4940 23:19:00.643680 DQ_CA_OPEN = 0
4941 23:19:00.647023 DQ_SEMI_OPEN = 0
4942 23:19:00.650174 CA_SEMI_OPEN = 0
4943 23:19:00.653373 CA_FULL_RATE = 0
4944 23:19:00.657252 DQ_CKDIV4_EN = 1
4945 23:19:00.660146 CA_CKDIV4_EN = 1
4946 23:19:00.660223 CA_PREDIV_EN = 0
4947 23:19:00.663772 PH8_DLY = 0
4948 23:19:00.666865 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4949 23:19:00.669883 DQ_AAMCK_DIV = 4
4950 23:19:00.673539 CA_AAMCK_DIV = 4
4951 23:19:00.676885 CA_ADMCK_DIV = 4
4952 23:19:00.676986 DQ_TRACK_CA_EN = 0
4953 23:19:00.680026 CA_PICK = 933
4954 23:19:00.683051 CA_MCKIO = 933
4955 23:19:00.686663 MCKIO_SEMI = 0
4956 23:19:00.690004 PLL_FREQ = 3732
4957 23:19:00.693011 DQ_UI_PI_RATIO = 32
4958 23:19:00.696335 CA_UI_PI_RATIO = 0
4959 23:19:00.699685 ===================================
4960 23:19:00.703277 ===================================
4961 23:19:00.703389 memory_type:LPDDR4
4962 23:19:00.706419 GP_NUM : 10
4963 23:19:00.709832 SRAM_EN : 1
4964 23:19:00.709909 MD32_EN : 0
4965 23:19:00.713418 ===================================
4966 23:19:00.716288 [ANA_INIT] >>>>>>>>>>>>>>
4967 23:19:00.719359 <<<<<< [CONFIGURE PHASE]: ANA_TX
4968 23:19:00.722636 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4969 23:19:00.726263 ===================================
4970 23:19:00.729406 data_rate = 1866,PCW = 0X8f00
4971 23:19:00.732616 ===================================
4972 23:19:00.735960 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4973 23:19:00.739227 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4974 23:19:00.745957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4975 23:19:00.752309 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4976 23:19:00.755507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4977 23:19:00.758943 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4978 23:19:00.759016 [ANA_INIT] flow start
4979 23:19:00.762198 [ANA_INIT] PLL >>>>>>>>
4980 23:19:00.765709 [ANA_INIT] PLL <<<<<<<<
4981 23:19:00.765810 [ANA_INIT] MIDPI >>>>>>>>
4982 23:19:00.768652 [ANA_INIT] MIDPI <<<<<<<<
4983 23:19:00.771956 [ANA_INIT] DLL >>>>>>>>
4984 23:19:00.772035 [ANA_INIT] flow end
4985 23:19:00.778602 ============ LP4 DIFF to SE enter ============
4986 23:19:00.782204 ============ LP4 DIFF to SE exit ============
4987 23:19:00.785170 [ANA_INIT] <<<<<<<<<<<<<
4988 23:19:00.788517 [Flow] Enable top DCM control >>>>>
4989 23:19:00.792043 [Flow] Enable top DCM control <<<<<
4990 23:19:00.792146 Enable DLL master slave shuffle
4991 23:19:00.798139 ==============================================================
4992 23:19:00.801810 Gating Mode config
4993 23:19:00.804949 ==============================================================
4994 23:19:00.807922 Config description:
4995 23:19:00.818157 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4996 23:19:00.824645 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4997 23:19:00.827681 SELPH_MODE 0: By rank 1: By Phase
4998 23:19:00.834422 ==============================================================
4999 23:19:00.837494 GAT_TRACK_EN = 1
5000 23:19:00.840772 RX_GATING_MODE = 2
5001 23:19:00.844044 RX_GATING_TRACK_MODE = 2
5002 23:19:00.847624 SELPH_MODE = 1
5003 23:19:00.850676 PICG_EARLY_EN = 1
5004 23:19:00.854428 VALID_LAT_VALUE = 1
5005 23:19:00.857782 ==============================================================
5006 23:19:00.860640 Enter into Gating configuration >>>>
5007 23:19:00.864364 Exit from Gating configuration <<<<
5008 23:19:00.867355 Enter into DVFS_PRE_config >>>>>
5009 23:19:00.880617 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5010 23:19:00.880767 Exit from DVFS_PRE_config <<<<<
5011 23:19:00.883902 Enter into PICG configuration >>>>
5012 23:19:00.887269 Exit from PICG configuration <<<<
5013 23:19:00.890347 [RX_INPUT] configuration >>>>>
5014 23:19:00.893645 [RX_INPUT] configuration <<<<<
5015 23:19:00.900145 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5016 23:19:00.903384 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5017 23:19:00.910368 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5018 23:19:00.916648 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5019 23:19:00.922888 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5020 23:19:00.929690 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5021 23:19:00.932840 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5022 23:19:00.936062 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5023 23:19:00.942683 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5024 23:19:00.946147 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5025 23:19:00.949421 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5026 23:19:00.952877 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5027 23:19:00.956254 ===================================
5028 23:19:00.959121 LPDDR4 DRAM CONFIGURATION
5029 23:19:00.962778 ===================================
5030 23:19:00.965925 EX_ROW_EN[0] = 0x0
5031 23:19:00.966050 EX_ROW_EN[1] = 0x0
5032 23:19:00.969286 LP4Y_EN = 0x0
5033 23:19:00.969413 WORK_FSP = 0x0
5034 23:19:00.972536 WL = 0x3
5035 23:19:00.972663 RL = 0x3
5036 23:19:00.975881 BL = 0x2
5037 23:19:00.976007 RPST = 0x0
5038 23:19:00.978902 RD_PRE = 0x0
5039 23:19:00.982444 WR_PRE = 0x1
5040 23:19:00.982569 WR_PST = 0x0
5041 23:19:00.985803 DBI_WR = 0x0
5042 23:19:00.985928 DBI_RD = 0x0
5043 23:19:00.989223 OTF = 0x1
5044 23:19:00.992240 ===================================
5045 23:19:00.995531 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5046 23:19:00.999129 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5047 23:19:01.002215 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5048 23:19:01.005410 ===================================
5049 23:19:01.008907 LPDDR4 DRAM CONFIGURATION
5050 23:19:01.012422 ===================================
5051 23:19:01.015737 EX_ROW_EN[0] = 0x10
5052 23:19:01.015866 EX_ROW_EN[1] = 0x0
5053 23:19:01.018556 LP4Y_EN = 0x0
5054 23:19:01.018681 WORK_FSP = 0x0
5055 23:19:01.021866 WL = 0x3
5056 23:19:01.021991 RL = 0x3
5057 23:19:01.025089 BL = 0x2
5058 23:19:01.025213 RPST = 0x0
5059 23:19:01.028660 RD_PRE = 0x0
5060 23:19:01.031690 WR_PRE = 0x1
5061 23:19:01.031815 WR_PST = 0x0
5062 23:19:01.035559 DBI_WR = 0x0
5063 23:19:01.035684 DBI_RD = 0x0
5064 23:19:01.038553 OTF = 0x1
5065 23:19:01.041757 ===================================
5066 23:19:01.044844 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5067 23:19:01.050473 nWR fixed to 30
5068 23:19:01.054370 [ModeRegInit_LP4] CH0 RK0
5069 23:19:01.054471 [ModeRegInit_LP4] CH0 RK1
5070 23:19:01.057296 [ModeRegInit_LP4] CH1 RK0
5071 23:19:01.060463 [ModeRegInit_LP4] CH1 RK1
5072 23:19:01.060575 match AC timing 9
5073 23:19:01.067111 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5074 23:19:01.070168 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5075 23:19:01.073774 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5076 23:19:01.080332 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5077 23:19:01.083585 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5078 23:19:01.083701 ==
5079 23:19:01.086920 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 23:19:01.090420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 23:19:01.090528 ==
5082 23:19:01.097233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5083 23:19:01.103412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5084 23:19:01.106958 [CA 0] Center 37 (7~68) winsize 62
5085 23:19:01.110056 [CA 1] Center 37 (7~68) winsize 62
5086 23:19:01.113631 [CA 2] Center 34 (4~65) winsize 62
5087 23:19:01.116750 [CA 3] Center 34 (4~65) winsize 62
5088 23:19:01.120080 [CA 4] Center 32 (2~63) winsize 62
5089 23:19:01.123024 [CA 5] Center 32 (2~63) winsize 62
5090 23:19:01.123102
5091 23:19:01.126583 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5092 23:19:01.126682
5093 23:19:01.129863 [CATrainingPosCal] consider 1 rank data
5094 23:19:01.133336 u2DelayCellTimex100 = 270/100 ps
5095 23:19:01.136359 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5096 23:19:01.139590 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5097 23:19:01.142835 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5098 23:19:01.149314 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5099 23:19:01.152485 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5100 23:19:01.156245 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5101 23:19:01.156357
5102 23:19:01.159159 CA PerBit enable=1, Macro0, CA PI delay=32
5103 23:19:01.159235
5104 23:19:01.162685 [CBTSetCACLKResult] CA Dly = 32
5105 23:19:01.162762 CS Dly: 5 (0~36)
5106 23:19:01.162825 ==
5107 23:19:01.165857 Dram Type= 6, Freq= 0, CH_0, rank 1
5108 23:19:01.172486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 23:19:01.172572 ==
5110 23:19:01.175852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5111 23:19:01.182185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5112 23:19:01.185691 [CA 0] Center 37 (7~68) winsize 62
5113 23:19:01.189195 [CA 1] Center 37 (7~68) winsize 62
5114 23:19:01.192256 [CA 2] Center 34 (4~65) winsize 62
5115 23:19:01.195612 [CA 3] Center 34 (4~65) winsize 62
5116 23:19:01.199104 [CA 4] Center 33 (3~64) winsize 62
5117 23:19:01.202592 [CA 5] Center 32 (2~63) winsize 62
5118 23:19:01.202701
5119 23:19:01.205569 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5120 23:19:01.205645
5121 23:19:01.208968 [CATrainingPosCal] consider 2 rank data
5122 23:19:01.212085 u2DelayCellTimex100 = 270/100 ps
5123 23:19:01.215280 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5124 23:19:01.222208 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5125 23:19:01.225171 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5126 23:19:01.228987 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5127 23:19:01.231968 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5128 23:19:01.235623 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5129 23:19:01.235698
5130 23:19:01.238511 CA PerBit enable=1, Macro0, CA PI delay=32
5131 23:19:01.238610
5132 23:19:01.241894 [CBTSetCACLKResult] CA Dly = 32
5133 23:19:01.245379 CS Dly: 6 (0~39)
5134 23:19:01.245487
5135 23:19:01.248419 ----->DramcWriteLeveling(PI) begin...
5136 23:19:01.248531 ==
5137 23:19:01.251709 Dram Type= 6, Freq= 0, CH_0, rank 0
5138 23:19:01.254881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5139 23:19:01.254960 ==
5140 23:19:01.258438 Write leveling (Byte 0): 33 => 33
5141 23:19:01.261467 Write leveling (Byte 1): 30 => 30
5142 23:19:01.265061 DramcWriteLeveling(PI) end<-----
5143 23:19:01.265135
5144 23:19:01.265197 ==
5145 23:19:01.268236 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 23:19:01.271809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 23:19:01.271918 ==
5148 23:19:01.274724 [Gating] SW mode calibration
5149 23:19:01.281478 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5150 23:19:01.288014 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5151 23:19:01.291352 0 14 0 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
5152 23:19:01.294446 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 23:19:01.301403 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 23:19:01.304258 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 23:19:01.307982 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 23:19:01.314344 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 23:19:01.317488 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5158 23:19:01.324160 0 14 28 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 1)
5159 23:19:01.327530 0 15 0 | B1->B0 | 3131 2424 | 1 0 | (1 0) (0 0)
5160 23:19:01.330991 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 23:19:01.337408 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 23:19:01.340759 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 23:19:01.344120 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 23:19:01.350580 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 23:19:01.353704 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 23:19:01.357067 0 15 28 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
5167 23:19:01.363973 1 0 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
5168 23:19:01.366873 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 23:19:01.370367 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 23:19:01.376919 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 23:19:01.379927 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 23:19:01.383306 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 23:19:01.389930 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5174 23:19:01.392804 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5175 23:19:01.396379 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5176 23:19:01.402944 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5177 23:19:01.405924 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 23:19:01.409674 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 23:19:01.415904 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 23:19:01.419777 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 23:19:01.422807 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 23:19:01.428944 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 23:19:01.432698 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 23:19:01.435531 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 23:19:01.442485 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 23:19:01.445805 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 23:19:01.448996 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 23:19:01.455550 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 23:19:01.459048 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 23:19:01.461965 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5191 23:19:01.468649 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5192 23:19:01.471935 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5193 23:19:01.475607 Total UI for P1: 0, mck2ui 16
5194 23:19:01.478620 best dqsien dly found for B0: ( 1, 2, 30)
5195 23:19:01.481797 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 23:19:01.485159 Total UI for P1: 0, mck2ui 16
5197 23:19:01.488496 best dqsien dly found for B1: ( 1, 3, 4)
5198 23:19:01.491842 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5199 23:19:01.495357 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5200 23:19:01.495490
5201 23:19:01.502203 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5202 23:19:01.504941 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5203 23:19:01.505069 [Gating] SW calibration Done
5204 23:19:01.508144 ==
5205 23:19:01.511698 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 23:19:01.514759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 23:19:01.514885 ==
5208 23:19:01.515002 RX Vref Scan: 0
5209 23:19:01.515113
5210 23:19:01.517715 RX Vref 0 -> 0, step: 1
5211 23:19:01.517839
5212 23:19:01.521274 RX Delay -80 -> 252, step: 8
5213 23:19:01.524444 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5214 23:19:01.527873 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5215 23:19:01.530999 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5216 23:19:01.537495 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5217 23:19:01.540958 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5218 23:19:01.544421 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5219 23:19:01.547389 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5220 23:19:01.550709 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5221 23:19:01.557399 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5222 23:19:01.561095 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5223 23:19:01.564226 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5224 23:19:01.567551 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5225 23:19:01.571217 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5226 23:19:01.577192 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5227 23:19:01.580937 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5228 23:19:01.583654 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5229 23:19:01.583738 ==
5230 23:19:01.587122 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 23:19:01.590449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 23:19:01.590560 ==
5233 23:19:01.593406 DQS Delay:
5234 23:19:01.593505 DQS0 = 0, DQS1 = 0
5235 23:19:01.597023 DQM Delay:
5236 23:19:01.597107 DQM0 = 100, DQM1 = 88
5237 23:19:01.597172 DQ Delay:
5238 23:19:01.600154 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5239 23:19:01.603642 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5240 23:19:01.606949 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5241 23:19:01.610773 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5242 23:19:01.610900
5243 23:19:01.613373
5244 23:19:01.613500 ==
5245 23:19:01.616718 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 23:19:01.620009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 23:19:01.620137 ==
5248 23:19:01.620253
5249 23:19:01.620366
5250 23:19:01.623264 TX Vref Scan disable
5251 23:19:01.623392 == TX Byte 0 ==
5252 23:19:01.629823 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5253 23:19:01.633201 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5254 23:19:01.633327 == TX Byte 1 ==
5255 23:19:01.639931 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5256 23:19:01.643282 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5257 23:19:01.643412 ==
5258 23:19:01.646066 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 23:19:01.649497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 23:19:01.649622 ==
5261 23:19:01.649735
5262 23:19:01.649848
5263 23:19:01.652718 TX Vref Scan disable
5264 23:19:01.656392 == TX Byte 0 ==
5265 23:19:01.659386 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5266 23:19:01.662760 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5267 23:19:01.666097 == TX Byte 1 ==
5268 23:19:01.669263 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5269 23:19:01.672818 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5270 23:19:01.672928
5271 23:19:01.676175 [DATLAT]
5272 23:19:01.676299 Freq=933, CH0 RK0
5273 23:19:01.676407
5274 23:19:01.678979 DATLAT Default: 0xd
5275 23:19:01.679079 0, 0xFFFF, sum = 0
5276 23:19:01.682476 1, 0xFFFF, sum = 0
5277 23:19:01.682590 2, 0xFFFF, sum = 0
5278 23:19:01.685690 3, 0xFFFF, sum = 0
5279 23:19:01.688840 4, 0xFFFF, sum = 0
5280 23:19:01.688926 5, 0xFFFF, sum = 0
5281 23:19:01.692483 6, 0xFFFF, sum = 0
5282 23:19:01.692578 7, 0xFFFF, sum = 0
5283 23:19:01.695541 8, 0xFFFF, sum = 0
5284 23:19:01.695626 9, 0xFFFF, sum = 0
5285 23:19:01.698694 10, 0x0, sum = 1
5286 23:19:01.698827 11, 0x0, sum = 2
5287 23:19:01.702092 12, 0x0, sum = 3
5288 23:19:01.702224 13, 0x0, sum = 4
5289 23:19:01.702342 best_step = 11
5290 23:19:01.702454
5291 23:19:01.705545 ==
5292 23:19:01.708662 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 23:19:01.712403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 23:19:01.712529 ==
5295 23:19:01.712648 RX Vref Scan: 1
5296 23:19:01.712759
5297 23:19:01.715430 RX Vref 0 -> 0, step: 1
5298 23:19:01.715554
5299 23:19:01.718567 RX Delay -61 -> 252, step: 4
5300 23:19:01.718691
5301 23:19:01.722208 Set Vref, RX VrefLevel [Byte0]: 52
5302 23:19:01.725241 [Byte1]: 50
5303 23:19:01.725365
5304 23:19:01.728718 Final RX Vref Byte 0 = 52 to rank0
5305 23:19:01.732065 Final RX Vref Byte 1 = 50 to rank0
5306 23:19:01.735158 Final RX Vref Byte 0 = 52 to rank1
5307 23:19:01.738532 Final RX Vref Byte 1 = 50 to rank1==
5308 23:19:01.741810 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 23:19:01.748185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 23:19:01.748315 ==
5311 23:19:01.748430 DQS Delay:
5312 23:19:01.748544 DQS0 = 0, DQS1 = 0
5313 23:19:01.751898 DQM Delay:
5314 23:19:01.752025 DQM0 = 99, DQM1 = 87
5315 23:19:01.754777 DQ Delay:
5316 23:19:01.758297 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5317 23:19:01.761821 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =104
5318 23:19:01.764741 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =82
5319 23:19:01.767861 DQ12 =94, DQ13 =92, DQ14 =96, DQ15 =94
5320 23:19:01.767985
5321 23:19:01.768103
5322 23:19:01.774513 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5323 23:19:01.777839 CH0 RK0: MR19=505, MR18=1B15
5324 23:19:01.784498 CH0_RK0: MR19=0x505, MR18=0x1B15, DQSOSC=413, MR23=63, INC=63, DEC=42
5325 23:19:01.784585
5326 23:19:01.787428 ----->DramcWriteLeveling(PI) begin...
5327 23:19:01.787513 ==
5328 23:19:01.791144 Dram Type= 6, Freq= 0, CH_0, rank 1
5329 23:19:01.794358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 23:19:01.794469 ==
5331 23:19:01.797472 Write leveling (Byte 0): 30 => 30
5332 23:19:01.800848 Write leveling (Byte 1): 29 => 29
5333 23:19:01.804021 DramcWriteLeveling(PI) end<-----
5334 23:19:01.804145
5335 23:19:01.804262 ==
5336 23:19:01.807578 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 23:19:01.813928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 23:19:01.814051 ==
5339 23:19:01.814164 [Gating] SW mode calibration
5340 23:19:01.823649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5341 23:19:01.827161 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5342 23:19:01.833900 0 14 0 | B1->B0 | 2828 3434 | 1 0 | (1 1) (0 0)
5343 23:19:01.837167 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 23:19:01.840167 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 23:19:01.847073 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 23:19:01.850190 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 23:19:01.853680 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 23:19:01.860300 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 23:19:01.863671 0 14 28 | B1->B0 | 3434 2929 | 1 1 | (1 1) (0 0)
5350 23:19:01.866745 0 15 0 | B1->B0 | 3131 2727 | 0 0 | (0 1) (0 0)
5351 23:19:01.873473 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 23:19:01.876528 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 23:19:01.879882 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 23:19:01.886573 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 23:19:01.889806 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 23:19:01.893137 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5357 23:19:01.899539 0 15 28 | B1->B0 | 2929 3f3f | 0 0 | (0 0) (0 0)
5358 23:19:01.903041 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5359 23:19:01.906467 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 23:19:01.912630 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 23:19:01.915708 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 23:19:01.919156 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 23:19:01.926102 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 23:19:01.929601 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 23:19:01.932574 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5366 23:19:01.938863 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 23:19:01.942024 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 23:19:01.945662 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 23:19:01.952369 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 23:19:01.955502 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 23:19:01.958766 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 23:19:01.965723 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 23:19:01.968638 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 23:19:01.971948 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 23:19:01.978582 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:19:01.981459 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:19:01.985006 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:19:01.991491 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:19:01.994843 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:19:01.997991 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5381 23:19:02.004780 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5382 23:19:02.008018 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5383 23:19:02.011238 Total UI for P1: 0, mck2ui 16
5384 23:19:02.014587 best dqsien dly found for B0: ( 1, 2, 26)
5385 23:19:02.017690 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 23:19:02.021769 Total UI for P1: 0, mck2ui 16
5387 23:19:02.024578 best dqsien dly found for B1: ( 1, 3, 0)
5388 23:19:02.027657 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5389 23:19:02.031546 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5390 23:19:02.031641
5391 23:19:02.037452 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5392 23:19:02.041031 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5393 23:19:02.041126 [Gating] SW calibration Done
5394 23:19:02.044219 ==
5395 23:19:02.047353 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 23:19:02.050839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 23:19:02.050915 ==
5398 23:19:02.050978 RX Vref Scan: 0
5399 23:19:02.051037
5400 23:19:02.054564 RX Vref 0 -> 0, step: 1
5401 23:19:02.054662
5402 23:19:02.057479 RX Delay -80 -> 252, step: 8
5403 23:19:02.060592 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5404 23:19:02.064258 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5405 23:19:02.067143 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5406 23:19:02.073774 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5407 23:19:02.077376 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5408 23:19:02.080438 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5409 23:19:02.083580 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5410 23:19:02.086929 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5411 23:19:02.090150 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5412 23:19:02.096950 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5413 23:19:02.099979 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5414 23:19:02.103440 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5415 23:19:02.106729 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5416 23:19:02.110444 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5417 23:19:02.116799 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5418 23:19:02.119630 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5419 23:19:02.119726 ==
5420 23:19:02.123257 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 23:19:02.126577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 23:19:02.126688 ==
5423 23:19:02.129859 DQS Delay:
5424 23:19:02.129969 DQS0 = 0, DQS1 = 0
5425 23:19:02.130073 DQM Delay:
5426 23:19:02.133178 DQM0 = 97, DQM1 = 89
5427 23:19:02.133278 DQ Delay:
5428 23:19:02.136306 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5429 23:19:02.140023 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5430 23:19:02.143016 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5431 23:19:02.146934 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =91
5432 23:19:02.147018
5433 23:19:02.147106
5434 23:19:02.147193 ==
5435 23:19:02.149357 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 23:19:02.156092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 23:19:02.156177 ==
5438 23:19:02.156248
5439 23:19:02.156313
5440 23:19:02.159383 TX Vref Scan disable
5441 23:19:02.159484 == TX Byte 0 ==
5442 23:19:02.162569 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5443 23:19:02.168959 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5444 23:19:02.169045 == TX Byte 1 ==
5445 23:19:02.172558 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5446 23:19:02.179305 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5447 23:19:02.179418 ==
5448 23:19:02.182594 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 23:19:02.185613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 23:19:02.185692 ==
5451 23:19:02.185769
5452 23:19:02.185832
5453 23:19:02.189465 TX Vref Scan disable
5454 23:19:02.192211 == TX Byte 0 ==
5455 23:19:02.195690 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5456 23:19:02.198688 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5457 23:19:02.201977 == TX Byte 1 ==
5458 23:19:02.205598 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5459 23:19:02.208754 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5460 23:19:02.208836
5461 23:19:02.212076 [DATLAT]
5462 23:19:02.212153 Freq=933, CH0 RK1
5463 23:19:02.212222
5464 23:19:02.215096 DATLAT Default: 0xb
5465 23:19:02.215171 0, 0xFFFF, sum = 0
5466 23:19:02.218434 1, 0xFFFF, sum = 0
5467 23:19:02.218517 2, 0xFFFF, sum = 0
5468 23:19:02.221966 3, 0xFFFF, sum = 0
5469 23:19:02.222043 4, 0xFFFF, sum = 0
5470 23:19:02.225162 5, 0xFFFF, sum = 0
5471 23:19:02.225240 6, 0xFFFF, sum = 0
5472 23:19:02.228177 7, 0xFFFF, sum = 0
5473 23:19:02.228256 8, 0xFFFF, sum = 0
5474 23:19:02.231577 9, 0xFFFF, sum = 0
5475 23:19:02.231653 10, 0x0, sum = 1
5476 23:19:02.234713 11, 0x0, sum = 2
5477 23:19:02.234791 12, 0x0, sum = 3
5478 23:19:02.238569 13, 0x0, sum = 4
5479 23:19:02.238645 best_step = 11
5480 23:19:02.238708
5481 23:19:02.238767 ==
5482 23:19:02.241810 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 23:19:02.247971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 23:19:02.248051 ==
5485 23:19:02.248117 RX Vref Scan: 0
5486 23:19:02.248183
5487 23:19:02.251676 RX Vref 0 -> 0, step: 1
5488 23:19:02.251753
5489 23:19:02.254606 RX Delay -53 -> 252, step: 4
5490 23:19:02.257844 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5491 23:19:02.264744 iDelay=195, Bit 1, Center 100 (11 ~ 190) 180
5492 23:19:02.267572 iDelay=195, Bit 2, Center 94 (3 ~ 186) 184
5493 23:19:02.271176 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5494 23:19:02.274451 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5495 23:19:02.277663 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5496 23:19:02.280801 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5497 23:19:02.287398 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5498 23:19:02.291101 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5499 23:19:02.294312 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5500 23:19:02.297565 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5501 23:19:02.300568 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5502 23:19:02.307177 iDelay=195, Bit 12, Center 92 (3 ~ 182) 180
5503 23:19:02.310876 iDelay=195, Bit 13, Center 92 (3 ~ 182) 180
5504 23:19:02.313722 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5505 23:19:02.317259 iDelay=195, Bit 15, Center 92 (3 ~ 182) 180
5506 23:19:02.317386 ==
5507 23:19:02.320405 Dram Type= 6, Freq= 0, CH_0, rank 1
5508 23:19:02.327108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 23:19:02.327236 ==
5510 23:19:02.327356 DQS Delay:
5511 23:19:02.327476 DQS0 = 0, DQS1 = 0
5512 23:19:02.330244 DQM Delay:
5513 23:19:02.330369 DQM0 = 97, DQM1 = 87
5514 23:19:02.333579 DQ Delay:
5515 23:19:02.336807 DQ0 =96, DQ1 =100, DQ2 =94, DQ3 =94
5516 23:19:02.340193 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =106
5517 23:19:02.343400 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =82
5518 23:19:02.346444 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =92
5519 23:19:02.346523
5520 23:19:02.346593
5521 23:19:02.352925 [DQSOSCAuto] RK1, (LSB)MR18= 0x100d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5522 23:19:02.356324 CH0 RK1: MR19=505, MR18=100D
5523 23:19:02.363312 CH0_RK1: MR19=0x505, MR18=0x100D, DQSOSC=416, MR23=63, INC=62, DEC=41
5524 23:19:02.366283 [RxdqsGatingPostProcess] freq 933
5525 23:19:02.372913 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5526 23:19:02.376206 best DQS0 dly(2T, 0.5T) = (0, 10)
5527 23:19:02.376286 best DQS1 dly(2T, 0.5T) = (0, 11)
5528 23:19:02.379333 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5529 23:19:02.382790 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5530 23:19:02.386261 best DQS0 dly(2T, 0.5T) = (0, 10)
5531 23:19:02.389132 best DQS1 dly(2T, 0.5T) = (0, 11)
5532 23:19:02.392572 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5533 23:19:02.395623 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5534 23:19:02.399234 Pre-setting of DQS Precalculation
5535 23:19:02.405620 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5536 23:19:02.405706 ==
5537 23:19:02.409025 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 23:19:02.412485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 23:19:02.412566 ==
5540 23:19:02.418812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5541 23:19:02.425215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5542 23:19:02.428962 [CA 0] Center 36 (6~67) winsize 62
5543 23:19:02.432000 [CA 1] Center 36 (6~67) winsize 62
5544 23:19:02.435544 [CA 2] Center 34 (4~65) winsize 62
5545 23:19:02.438871 [CA 3] Center 34 (3~65) winsize 63
5546 23:19:02.442297 [CA 4] Center 34 (4~65) winsize 62
5547 23:19:02.442376 [CA 5] Center 33 (3~64) winsize 62
5548 23:19:02.445295
5549 23:19:02.448610 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5550 23:19:02.448685
5551 23:19:02.452118 [CATrainingPosCal] consider 1 rank data
5552 23:19:02.454966 u2DelayCellTimex100 = 270/100 ps
5553 23:19:02.458402 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5554 23:19:02.461875 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5555 23:19:02.465147 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5556 23:19:02.468383 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5557 23:19:02.471634 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5558 23:19:02.474850 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5559 23:19:02.474935
5560 23:19:02.481672 CA PerBit enable=1, Macro0, CA PI delay=33
5561 23:19:02.481756
5562 23:19:02.481824 [CBTSetCACLKResult] CA Dly = 33
5563 23:19:02.485224 CS Dly: 5 (0~36)
5564 23:19:02.485308 ==
5565 23:19:02.488395 Dram Type= 6, Freq= 0, CH_1, rank 1
5566 23:19:02.491270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 23:19:02.491387 ==
5568 23:19:02.498242 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5569 23:19:02.504637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5570 23:19:02.507802 [CA 0] Center 36 (6~67) winsize 62
5571 23:19:02.511075 [CA 1] Center 36 (6~67) winsize 62
5572 23:19:02.514877 [CA 2] Center 34 (4~65) winsize 62
5573 23:19:02.518071 [CA 3] Center 33 (3~64) winsize 62
5574 23:19:02.521626 [CA 4] Center 33 (3~64) winsize 62
5575 23:19:02.524420 [CA 5] Center 33 (3~64) winsize 62
5576 23:19:02.524496
5577 23:19:02.528032 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5578 23:19:02.528112
5579 23:19:02.530992 [CATrainingPosCal] consider 2 rank data
5580 23:19:02.534503 u2DelayCellTimex100 = 270/100 ps
5581 23:19:02.537407 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5582 23:19:02.541117 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5583 23:19:02.544454 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5584 23:19:02.547269 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5585 23:19:02.550733 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5586 23:19:02.557285 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5587 23:19:02.557418
5588 23:19:02.560960 CA PerBit enable=1, Macro0, CA PI delay=33
5589 23:19:02.561085
5590 23:19:02.563829 [CBTSetCACLKResult] CA Dly = 33
5591 23:19:02.563958 CS Dly: 6 (0~38)
5592 23:19:02.564074
5593 23:19:02.567373 ----->DramcWriteLeveling(PI) begin...
5594 23:19:02.567499 ==
5595 23:19:02.570209 Dram Type= 6, Freq= 0, CH_1, rank 0
5596 23:19:02.576871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5597 23:19:02.576999 ==
5598 23:19:02.580020 Write leveling (Byte 0): 24 => 24
5599 23:19:02.583703 Write leveling (Byte 1): 25 => 25
5600 23:19:02.583809 DramcWriteLeveling(PI) end<-----
5601 23:19:02.583902
5602 23:19:02.586931 ==
5603 23:19:02.590004 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 23:19:02.593541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 23:19:02.593626 ==
5606 23:19:02.596498 [Gating] SW mode calibration
5607 23:19:02.603481 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5608 23:19:02.606529 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5609 23:19:02.613083 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 23:19:02.616451 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 23:19:02.619778 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 23:19:02.626123 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 23:19:02.629529 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 23:19:02.632639 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 23:19:02.639234 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
5616 23:19:02.642814 0 14 28 | B1->B0 | 2929 2424 | 0 0 | (0 0) (1 0)
5617 23:19:02.649114 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 23:19:02.652512 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 23:19:02.655759 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 23:19:02.662658 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 23:19:02.665795 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 23:19:02.668922 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 23:19:02.675467 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5624 23:19:02.678973 0 15 28 | B1->B0 | 3636 3737 | 0 0 | (0 0) (0 0)
5625 23:19:02.682108 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 23:19:02.688485 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 23:19:02.692118 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 23:19:02.695654 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 23:19:02.701590 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 23:19:02.704990 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 23:19:02.708656 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5632 23:19:02.715051 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5633 23:19:02.718571 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 23:19:02.721585 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 23:19:02.728282 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 23:19:02.731538 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 23:19:02.734901 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 23:19:02.741461 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 23:19:02.744460 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 23:19:02.747669 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 23:19:02.754713 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 23:19:02.757480 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 23:19:02.760969 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 23:19:02.767622 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 23:19:02.770681 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 23:19:02.774140 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 23:19:02.780842 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5648 23:19:02.783901 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5649 23:19:02.787195 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 23:19:02.790347 Total UI for P1: 0, mck2ui 16
5651 23:19:02.793809 best dqsien dly found for B0: ( 1, 2, 26)
5652 23:19:02.797245 Total UI for P1: 0, mck2ui 16
5653 23:19:02.799990 best dqsien dly found for B1: ( 1, 2, 26)
5654 23:19:02.803603 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5655 23:19:02.807145 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5656 23:19:02.807251
5657 23:19:02.813401 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5658 23:19:02.816977 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5659 23:19:02.820006 [Gating] SW calibration Done
5660 23:19:02.820086 ==
5661 23:19:02.823477 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 23:19:02.826950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 23:19:02.827056 ==
5664 23:19:02.827157 RX Vref Scan: 0
5665 23:19:02.827257
5666 23:19:02.830157 RX Vref 0 -> 0, step: 1
5667 23:19:02.830261
5668 23:19:02.832980 RX Delay -80 -> 252, step: 8
5669 23:19:02.836475 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5670 23:19:02.839924 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5671 23:19:02.846576 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5672 23:19:02.850103 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5673 23:19:02.853281 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5674 23:19:02.856426 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5675 23:19:02.859371 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5676 23:19:02.862958 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5677 23:19:02.869513 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5678 23:19:02.872638 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5679 23:19:02.876140 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5680 23:19:02.879272 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5681 23:19:02.882393 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5682 23:19:02.889034 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5683 23:19:02.892607 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5684 23:19:02.895879 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5685 23:19:02.895956 ==
5686 23:19:02.898948 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 23:19:02.902420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 23:19:02.902500 ==
5689 23:19:02.905746 DQS Delay:
5690 23:19:02.905838 DQS0 = 0, DQS1 = 0
5691 23:19:02.909124 DQM Delay:
5692 23:19:02.909195 DQM0 = 98, DQM1 = 94
5693 23:19:02.909256 DQ Delay:
5694 23:19:02.912110 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5695 23:19:02.915731 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5696 23:19:02.918723 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5697 23:19:02.925174 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5698 23:19:02.925253
5699 23:19:02.925317
5700 23:19:02.925386 ==
5701 23:19:02.928623 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 23:19:02.932245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 23:19:02.932372 ==
5704 23:19:02.932494
5705 23:19:02.932607
5706 23:19:02.935176 TX Vref Scan disable
5707 23:19:02.935302 == TX Byte 0 ==
5708 23:19:02.941619 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5709 23:19:02.944845 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5710 23:19:02.944970 == TX Byte 1 ==
5711 23:19:02.951358 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5712 23:19:02.955025 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5713 23:19:02.955130 ==
5714 23:19:02.958154 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 23:19:02.961715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 23:19:02.961845 ==
5717 23:19:02.965006
5718 23:19:02.965136
5719 23:19:02.965256 TX Vref Scan disable
5720 23:19:02.967937 == TX Byte 0 ==
5721 23:19:02.971483 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5722 23:19:02.977809 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5723 23:19:02.977937 == TX Byte 1 ==
5724 23:19:02.981116 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5725 23:19:02.987706 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5726 23:19:02.987838
5727 23:19:02.987955 [DATLAT]
5728 23:19:02.988069 Freq=933, CH1 RK0
5729 23:19:02.988186
5730 23:19:02.991208 DATLAT Default: 0xd
5731 23:19:02.994344 0, 0xFFFF, sum = 0
5732 23:19:02.994481 1, 0xFFFF, sum = 0
5733 23:19:02.997564 2, 0xFFFF, sum = 0
5734 23:19:02.997696 3, 0xFFFF, sum = 0
5735 23:19:03.000944 4, 0xFFFF, sum = 0
5736 23:19:03.001078 5, 0xFFFF, sum = 0
5737 23:19:03.004010 6, 0xFFFF, sum = 0
5738 23:19:03.004095 7, 0xFFFF, sum = 0
5739 23:19:03.007358 8, 0xFFFF, sum = 0
5740 23:19:03.007441 9, 0xFFFF, sum = 0
5741 23:19:03.010921 10, 0x0, sum = 1
5742 23:19:03.011007 11, 0x0, sum = 2
5743 23:19:03.013902 12, 0x0, sum = 3
5744 23:19:03.013975 13, 0x0, sum = 4
5745 23:19:03.017449 best_step = 11
5746 23:19:03.017524
5747 23:19:03.017587 ==
5748 23:19:03.020476 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 23:19:03.023737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 23:19:03.023822 ==
5751 23:19:03.023889 RX Vref Scan: 1
5752 23:19:03.027194
5753 23:19:03.027272 RX Vref 0 -> 0, step: 1
5754 23:19:03.027333
5755 23:19:03.030612 RX Delay -61 -> 252, step: 4
5756 23:19:03.030689
5757 23:19:03.034009 Set Vref, RX VrefLevel [Byte0]: 50
5758 23:19:03.037338 [Byte1]: 53
5759 23:19:03.040701
5760 23:19:03.040780 Final RX Vref Byte 0 = 50 to rank0
5761 23:19:03.043867 Final RX Vref Byte 1 = 53 to rank0
5762 23:19:03.047217 Final RX Vref Byte 0 = 50 to rank1
5763 23:19:03.050261 Final RX Vref Byte 1 = 53 to rank1==
5764 23:19:03.054061 Dram Type= 6, Freq= 0, CH_1, rank 0
5765 23:19:03.060251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 23:19:03.060332 ==
5767 23:19:03.060398 DQS Delay:
5768 23:19:03.063675 DQS0 = 0, DQS1 = 0
5769 23:19:03.063751 DQM Delay:
5770 23:19:03.063813 DQM0 = 98, DQM1 = 96
5771 23:19:03.067165 DQ Delay:
5772 23:19:03.069978 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =98
5773 23:19:03.073297 DQ4 =96, DQ5 =106, DQ6 =110, DQ7 =92
5774 23:19:03.076865 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =90
5775 23:19:03.079968 DQ12 =106, DQ13 =106, DQ14 =102, DQ15 =106
5776 23:19:03.080054
5777 23:19:03.080128
5778 23:19:03.086379 [DQSOSCAuto] RK0, (LSB)MR18= 0x717, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5779 23:19:03.089667 CH1 RK0: MR19=505, MR18=717
5780 23:19:03.096157 CH1_RK0: MR19=0x505, MR18=0x717, DQSOSC=414, MR23=63, INC=63, DEC=42
5781 23:19:03.096238
5782 23:19:03.099378 ----->DramcWriteLeveling(PI) begin...
5783 23:19:03.099454 ==
5784 23:19:03.102908 Dram Type= 6, Freq= 0, CH_1, rank 1
5785 23:19:03.106153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5786 23:19:03.109566 ==
5787 23:19:03.109642 Write leveling (Byte 0): 24 => 24
5788 23:19:03.112616 Write leveling (Byte 1): 25 => 25
5789 23:19:03.116122 DramcWriteLeveling(PI) end<-----
5790 23:19:03.116202
5791 23:19:03.116300 ==
5792 23:19:03.119179 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 23:19:03.125664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 23:19:03.125792 ==
5795 23:19:03.129483 [Gating] SW mode calibration
5796 23:19:03.136070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5797 23:19:03.138999 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5798 23:19:03.145628 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 23:19:03.148896 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 23:19:03.152589 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 23:19:03.158923 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 23:19:03.162215 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 23:19:03.165416 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 23:19:03.172162 0 14 24 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (0 1)
5805 23:19:03.175034 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5806 23:19:03.178539 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 23:19:03.185196 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 23:19:03.188107 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 23:19:03.191512 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 23:19:03.197911 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 23:19:03.201576 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 23:19:03.204681 0 15 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5813 23:19:03.211191 0 15 28 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5814 23:19:03.215134 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 23:19:03.218158 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 23:19:03.224600 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 23:19:03.227826 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 23:19:03.231256 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 23:19:03.237956 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 23:19:03.240906 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5821 23:19:03.244451 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5822 23:19:03.250950 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 23:19:03.254277 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 23:19:03.257572 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 23:19:03.263905 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 23:19:03.266921 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 23:19:03.270252 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 23:19:03.276959 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 23:19:03.279957 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 23:19:03.283344 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 23:19:03.290386 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 23:19:03.293105 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 23:19:03.296569 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 23:19:03.303126 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 23:19:03.306491 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 23:19:03.310052 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5837 23:19:03.316153 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5838 23:19:03.319753 Total UI for P1: 0, mck2ui 16
5839 23:19:03.322713 best dqsien dly found for B0: ( 1, 2, 24)
5840 23:19:03.326308 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 23:19:03.329443 Total UI for P1: 0, mck2ui 16
5842 23:19:03.333190 best dqsien dly found for B1: ( 1, 2, 26)
5843 23:19:03.335905 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5844 23:19:03.339449 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5845 23:19:03.339530
5846 23:19:03.342445 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5847 23:19:03.349026 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5848 23:19:03.349103 [Gating] SW calibration Done
5849 23:19:03.352568 ==
5850 23:19:03.352642 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 23:19:03.359504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 23:19:03.359579 ==
5853 23:19:03.359641 RX Vref Scan: 0
5854 23:19:03.359707
5855 23:19:03.362686 RX Vref 0 -> 0, step: 1
5856 23:19:03.362805
5857 23:19:03.365759 RX Delay -80 -> 252, step: 8
5858 23:19:03.369022 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5859 23:19:03.372306 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5860 23:19:03.375370 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5861 23:19:03.382428 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5862 23:19:03.385738 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5863 23:19:03.388911 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5864 23:19:03.391901 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5865 23:19:03.395195 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5866 23:19:03.398524 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5867 23:19:03.405407 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5868 23:19:03.408637 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5869 23:19:03.412099 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5870 23:19:03.414960 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5871 23:19:03.418596 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5872 23:19:03.424980 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5873 23:19:03.428505 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5874 23:19:03.428586 ==
5875 23:19:03.431693 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 23:19:03.434668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 23:19:03.434742 ==
5878 23:19:03.438188 DQS Delay:
5879 23:19:03.438269 DQS0 = 0, DQS1 = 0
5880 23:19:03.438330 DQM Delay:
5881 23:19:03.442014 DQM0 = 96, DQM1 = 94
5882 23:19:03.442084 DQ Delay:
5883 23:19:03.444930 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5884 23:19:03.448371 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5885 23:19:03.451220 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5886 23:19:03.454428 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5887 23:19:03.454508
5888 23:19:03.454604
5889 23:19:03.454663 ==
5890 23:19:03.458215 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 23:19:03.464446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 23:19:03.464532 ==
5893 23:19:03.464677
5894 23:19:03.464754
5895 23:19:03.467738 TX Vref Scan disable
5896 23:19:03.467809 == TX Byte 0 ==
5897 23:19:03.471083 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5898 23:19:03.477699 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5899 23:19:03.477776 == TX Byte 1 ==
5900 23:19:03.481142 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5901 23:19:03.487325 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5902 23:19:03.487433 ==
5903 23:19:03.490780 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 23:19:03.494165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 23:19:03.494265 ==
5906 23:19:03.494363
5907 23:19:03.494439
5908 23:19:03.497504 TX Vref Scan disable
5909 23:19:03.500567 == TX Byte 0 ==
5910 23:19:03.503886 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5911 23:19:03.507252 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5912 23:19:03.510346 == TX Byte 1 ==
5913 23:19:03.513753 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5914 23:19:03.517010 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5915 23:19:03.517094
5916 23:19:03.521049 [DATLAT]
5917 23:19:03.521137 Freq=933, CH1 RK1
5918 23:19:03.521202
5919 23:19:03.523463 DATLAT Default: 0xb
5920 23:19:03.523542 0, 0xFFFF, sum = 0
5921 23:19:03.526869 1, 0xFFFF, sum = 0
5922 23:19:03.527005 2, 0xFFFF, sum = 0
5923 23:19:03.530179 3, 0xFFFF, sum = 0
5924 23:19:03.530264 4, 0xFFFF, sum = 0
5925 23:19:03.533275 5, 0xFFFF, sum = 0
5926 23:19:03.533354 6, 0xFFFF, sum = 0
5927 23:19:03.536744 7, 0xFFFF, sum = 0
5928 23:19:03.536827 8, 0xFFFF, sum = 0
5929 23:19:03.540621 9, 0xFFFF, sum = 0
5930 23:19:03.540721 10, 0x0, sum = 1
5931 23:19:03.543352 11, 0x0, sum = 2
5932 23:19:03.543458 12, 0x0, sum = 3
5933 23:19:03.546548 13, 0x0, sum = 4
5934 23:19:03.546631 best_step = 11
5935 23:19:03.546697
5936 23:19:03.546772 ==
5937 23:19:03.549982 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 23:19:03.556296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 23:19:03.556381 ==
5940 23:19:03.556447 RX Vref Scan: 0
5941 23:19:03.556509
5942 23:19:03.560193 RX Vref 0 -> 0, step: 1
5943 23:19:03.560274
5944 23:19:03.563009 RX Delay -53 -> 252, step: 4
5945 23:19:03.566767 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5946 23:19:03.572990 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5947 23:19:03.576219 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5948 23:19:03.579982 iDelay=199, Bit 3, Center 96 (7 ~ 186) 180
5949 23:19:03.582846 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5950 23:19:03.586048 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5951 23:19:03.592601 iDelay=199, Bit 6, Center 106 (19 ~ 194) 176
5952 23:19:03.596011 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5953 23:19:03.599192 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5954 23:19:03.602742 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5955 23:19:03.605629 iDelay=199, Bit 10, Center 96 (7 ~ 186) 180
5956 23:19:03.609357 iDelay=199, Bit 11, Center 88 (-1 ~ 178) 180
5957 23:19:03.615569 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5958 23:19:03.619006 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5959 23:19:03.622187 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5960 23:19:03.625623 iDelay=199, Bit 15, Center 104 (15 ~ 194) 180
5961 23:19:03.625698 ==
5962 23:19:03.628810 Dram Type= 6, Freq= 0, CH_1, rank 1
5963 23:19:03.635119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5964 23:19:03.635204 ==
5965 23:19:03.635271 DQS Delay:
5966 23:19:03.638809 DQS0 = 0, DQS1 = 0
5967 23:19:03.638906 DQM Delay:
5968 23:19:03.641887 DQM0 = 97, DQM1 = 95
5969 23:19:03.641960 DQ Delay:
5970 23:19:03.645544 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5971 23:19:03.648877 DQ4 =98, DQ5 =106, DQ6 =106, DQ7 =94
5972 23:19:03.652112 DQ8 =82, DQ9 =84, DQ10 =96, DQ11 =88
5973 23:19:03.655100 DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =104
5974 23:19:03.655219
5975 23:19:03.655330
5976 23:19:03.661624 [DQSOSCAuto] RK1, (LSB)MR18= 0xc23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 418 ps
5977 23:19:03.665279 CH1 RK1: MR19=505, MR18=C23
5978 23:19:03.671636 CH1_RK1: MR19=0x505, MR18=0xC23, DQSOSC=410, MR23=63, INC=64, DEC=42
5979 23:19:03.675030 [RxdqsGatingPostProcess] freq 933
5980 23:19:03.681477 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5981 23:19:03.684484 best DQS0 dly(2T, 0.5T) = (0, 10)
5982 23:19:03.684608 best DQS1 dly(2T, 0.5T) = (0, 10)
5983 23:19:03.687989 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5984 23:19:03.691194 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5985 23:19:03.694366 best DQS0 dly(2T, 0.5T) = (0, 10)
5986 23:19:03.697943 best DQS1 dly(2T, 0.5T) = (0, 10)
5987 23:19:03.701373 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5988 23:19:03.704274 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5989 23:19:03.707553 Pre-setting of DQS Precalculation
5990 23:19:03.714138 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5991 23:19:03.720977 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5992 23:19:03.728360 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5993 23:19:03.728495
5994 23:19:03.728587
5995 23:19:03.731004 [Calibration Summary] 1866 Mbps
5996 23:19:03.731112 CH 0, Rank 0
5997 23:19:03.733968 SW Impedance : PASS
5998 23:19:03.737328 DUTY Scan : NO K
5999 23:19:03.737454 ZQ Calibration : PASS
6000 23:19:03.740411 Jitter Meter : NO K
6001 23:19:03.743718 CBT Training : PASS
6002 23:19:03.743836 Write leveling : PASS
6003 23:19:03.747021 RX DQS gating : PASS
6004 23:19:03.750276 RX DQ/DQS(RDDQC) : PASS
6005 23:19:03.750398 TX DQ/DQS : PASS
6006 23:19:03.753644 RX DATLAT : PASS
6007 23:19:03.757237 RX DQ/DQS(Engine): PASS
6008 23:19:03.757353 TX OE : NO K
6009 23:19:03.760554 All Pass.
6010 23:19:03.760672
6011 23:19:03.760800 CH 0, Rank 1
6012 23:19:03.763803 SW Impedance : PASS
6013 23:19:03.763910 DUTY Scan : NO K
6014 23:19:03.766964 ZQ Calibration : PASS
6015 23:19:03.770110 Jitter Meter : NO K
6016 23:19:03.770212 CBT Training : PASS
6017 23:19:03.773671 Write leveling : PASS
6018 23:19:03.776767 RX DQS gating : PASS
6019 23:19:03.776866 RX DQ/DQS(RDDQC) : PASS
6020 23:19:03.779744 TX DQ/DQS : PASS
6021 23:19:03.783830 RX DATLAT : PASS
6022 23:19:03.783952 RX DQ/DQS(Engine): PASS
6023 23:19:03.786738 TX OE : NO K
6024 23:19:03.786856 All Pass.
6025 23:19:03.786967
6026 23:19:03.789697 CH 1, Rank 0
6027 23:19:03.789812 SW Impedance : PASS
6028 23:19:03.793437 DUTY Scan : NO K
6029 23:19:03.796773 ZQ Calibration : PASS
6030 23:19:03.796898 Jitter Meter : NO K
6031 23:19:03.799639 CBT Training : PASS
6032 23:19:03.802917 Write leveling : PASS
6033 23:19:03.803036 RX DQS gating : PASS
6034 23:19:03.806740 RX DQ/DQS(RDDQC) : PASS
6035 23:19:03.806857 TX DQ/DQS : PASS
6036 23:19:03.810029 RX DATLAT : PASS
6037 23:19:03.812783 RX DQ/DQS(Engine): PASS
6038 23:19:03.812927 TX OE : NO K
6039 23:19:03.816272 All Pass.
6040 23:19:03.816395
6041 23:19:03.816509 CH 1, Rank 1
6042 23:19:03.819259 SW Impedance : PASS
6043 23:19:03.819385 DUTY Scan : NO K
6044 23:19:03.823095 ZQ Calibration : PASS
6045 23:19:03.826080 Jitter Meter : NO K
6046 23:19:03.826203 CBT Training : PASS
6047 23:19:03.829220 Write leveling : PASS
6048 23:19:03.832803 RX DQS gating : PASS
6049 23:19:03.832925 RX DQ/DQS(RDDQC) : PASS
6050 23:19:03.835766 TX DQ/DQS : PASS
6051 23:19:03.839273 RX DATLAT : PASS
6052 23:19:03.839421 RX DQ/DQS(Engine): PASS
6053 23:19:03.842756 TX OE : NO K
6054 23:19:03.842884 All Pass.
6055 23:19:03.843015
6056 23:19:03.845710 DramC Write-DBI off
6057 23:19:03.849284 PER_BANK_REFRESH: Hybrid Mode
6058 23:19:03.849406 TX_TRACKING: ON
6059 23:19:03.859076 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6060 23:19:03.862471 [FAST_K] Save calibration result to emmc
6061 23:19:03.866141 dramc_set_vcore_voltage set vcore to 650000
6062 23:19:03.869077 Read voltage for 400, 6
6063 23:19:03.869195 Vio18 = 0
6064 23:19:03.869306 Vcore = 650000
6065 23:19:03.872358 Vdram = 0
6066 23:19:03.872482 Vddq = 0
6067 23:19:03.872594 Vmddr = 0
6068 23:19:03.878704 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6069 23:19:03.882130 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6070 23:19:03.885485 MEM_TYPE=3, freq_sel=20
6071 23:19:03.888472 sv_algorithm_assistance_LP4_800
6072 23:19:03.892041 ============ PULL DRAM RESETB DOWN ============
6073 23:19:03.898427 ========== PULL DRAM RESETB DOWN end =========
6074 23:19:03.901567 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6075 23:19:03.904870 ===================================
6076 23:19:03.908471 LPDDR4 DRAM CONFIGURATION
6077 23:19:03.911932 ===================================
6078 23:19:03.912058 EX_ROW_EN[0] = 0x0
6079 23:19:03.915054 EX_ROW_EN[1] = 0x0
6080 23:19:03.915179 LP4Y_EN = 0x0
6081 23:19:03.918051 WORK_FSP = 0x0
6082 23:19:03.918172 WL = 0x2
6083 23:19:03.921435 RL = 0x2
6084 23:19:03.921560 BL = 0x2
6085 23:19:03.924828 RPST = 0x0
6086 23:19:03.928044 RD_PRE = 0x0
6087 23:19:03.928166 WR_PRE = 0x1
6088 23:19:03.931443 WR_PST = 0x0
6089 23:19:03.931566 DBI_WR = 0x0
6090 23:19:03.935098 DBI_RD = 0x0
6091 23:19:03.935216 OTF = 0x1
6092 23:19:03.938021 ===================================
6093 23:19:03.941128 ===================================
6094 23:19:03.944690 ANA top config
6095 23:19:03.947682 ===================================
6096 23:19:03.947805 DLL_ASYNC_EN = 0
6097 23:19:03.951249 ALL_SLAVE_EN = 1
6098 23:19:03.954577 NEW_RANK_MODE = 1
6099 23:19:03.958171 DLL_IDLE_MODE = 1
6100 23:19:03.958296 LP45_APHY_COMB_EN = 1
6101 23:19:03.960970 TX_ODT_DIS = 1
6102 23:19:03.964179 NEW_8X_MODE = 1
6103 23:19:03.967584 ===================================
6104 23:19:03.970749 ===================================
6105 23:19:03.974243 data_rate = 800
6106 23:19:03.977365 CKR = 1
6107 23:19:03.980755 DQ_P2S_RATIO = 4
6108 23:19:03.984889 ===================================
6109 23:19:03.985019 CA_P2S_RATIO = 4
6110 23:19:03.987359 DQ_CA_OPEN = 0
6111 23:19:03.990598 DQ_SEMI_OPEN = 1
6112 23:19:03.994280 CA_SEMI_OPEN = 1
6113 23:19:03.997665 CA_FULL_RATE = 0
6114 23:19:04.000540 DQ_CKDIV4_EN = 0
6115 23:19:04.000662 CA_CKDIV4_EN = 1
6116 23:19:04.004042 CA_PREDIV_EN = 0
6117 23:19:04.007166 PH8_DLY = 0
6118 23:19:04.010433 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6119 23:19:04.014111 DQ_AAMCK_DIV = 0
6120 23:19:04.017281 CA_AAMCK_DIV = 0
6121 23:19:04.020522 CA_ADMCK_DIV = 4
6122 23:19:04.020643 DQ_TRACK_CA_EN = 0
6123 23:19:04.023727 CA_PICK = 800
6124 23:19:04.026869 CA_MCKIO = 400
6125 23:19:04.029971 MCKIO_SEMI = 400
6126 23:19:04.033614 PLL_FREQ = 3016
6127 23:19:04.036385 DQ_UI_PI_RATIO = 32
6128 23:19:04.039812 CA_UI_PI_RATIO = 32
6129 23:19:04.043145 ===================================
6130 23:19:04.046544 ===================================
6131 23:19:04.046661 memory_type:LPDDR4
6132 23:19:04.049527 GP_NUM : 10
6133 23:19:04.053054 SRAM_EN : 1
6134 23:19:04.053136 MD32_EN : 0
6135 23:19:04.056623 ===================================
6136 23:19:04.060280 [ANA_INIT] >>>>>>>>>>>>>>
6137 23:19:04.063226 <<<<<< [CONFIGURE PHASE]: ANA_TX
6138 23:19:04.066223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6139 23:19:04.069436 ===================================
6140 23:19:04.072636 data_rate = 800,PCW = 0X7400
6141 23:19:04.075714 ===================================
6142 23:19:04.079533 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6143 23:19:04.082598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6144 23:19:04.095496 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6145 23:19:04.098992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6146 23:19:04.102372 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6147 23:19:04.105573 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6148 23:19:04.109043 [ANA_INIT] flow start
6149 23:19:04.112278 [ANA_INIT] PLL >>>>>>>>
6150 23:19:04.112359 [ANA_INIT] PLL <<<<<<<<
6151 23:19:04.115415 [ANA_INIT] MIDPI >>>>>>>>
6152 23:19:04.118788 [ANA_INIT] MIDPI <<<<<<<<
6153 23:19:04.122035 [ANA_INIT] DLL >>>>>>>>
6154 23:19:04.122112 [ANA_INIT] flow end
6155 23:19:04.125749 ============ LP4 DIFF to SE enter ============
6156 23:19:04.131940 ============ LP4 DIFF to SE exit ============
6157 23:19:04.132039 [ANA_INIT] <<<<<<<<<<<<<
6158 23:19:04.135247 [Flow] Enable top DCM control >>>>>
6159 23:19:04.139113 [Flow] Enable top DCM control <<<<<
6160 23:19:04.142453 Enable DLL master slave shuffle
6161 23:19:04.148318 ==============================================================
6162 23:19:04.148432 Gating Mode config
6163 23:19:04.154814 ==============================================================
6164 23:19:04.158548 Config description:
6165 23:19:04.168552 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6166 23:19:04.174972 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6167 23:19:04.178184 SELPH_MODE 0: By rank 1: By Phase
6168 23:19:04.184806 ==============================================================
6169 23:19:04.188588 GAT_TRACK_EN = 0
6170 23:19:04.191232 RX_GATING_MODE = 2
6171 23:19:04.194878 RX_GATING_TRACK_MODE = 2
6172 23:19:04.195012 SELPH_MODE = 1
6173 23:19:04.197919 PICG_EARLY_EN = 1
6174 23:19:04.201492 VALID_LAT_VALUE = 1
6175 23:19:04.207670 ==============================================================
6176 23:19:04.210828 Enter into Gating configuration >>>>
6177 23:19:04.214252 Exit from Gating configuration <<<<
6178 23:19:04.217502 Enter into DVFS_PRE_config >>>>>
6179 23:19:04.227514 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6180 23:19:04.230425 Exit from DVFS_PRE_config <<<<<
6181 23:19:04.233837 Enter into PICG configuration >>>>
6182 23:19:04.237081 Exit from PICG configuration <<<<
6183 23:19:04.240538 [RX_INPUT] configuration >>>>>
6184 23:19:04.243671 [RX_INPUT] configuration <<<<<
6185 23:19:04.247061 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6186 23:19:04.253563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6187 23:19:04.260242 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6188 23:19:04.266807 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6189 23:19:04.273614 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6190 23:19:04.280278 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6191 23:19:04.283178 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6192 23:19:04.286684 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6193 23:19:04.289836 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6194 23:19:04.296369 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6195 23:19:04.299716 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6196 23:19:04.303480 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6197 23:19:04.306483 ===================================
6198 23:19:04.309415 LPDDR4 DRAM CONFIGURATION
6199 23:19:04.312917 ===================================
6200 23:19:04.316615 EX_ROW_EN[0] = 0x0
6201 23:19:04.316719 EX_ROW_EN[1] = 0x0
6202 23:19:04.319223 LP4Y_EN = 0x0
6203 23:19:04.319296 WORK_FSP = 0x0
6204 23:19:04.323027 WL = 0x2
6205 23:19:04.323129 RL = 0x2
6206 23:19:04.326289 BL = 0x2
6207 23:19:04.326387 RPST = 0x0
6208 23:19:04.329277 RD_PRE = 0x0
6209 23:19:04.329349 WR_PRE = 0x1
6210 23:19:04.332289 WR_PST = 0x0
6211 23:19:04.332397 DBI_WR = 0x0
6212 23:19:04.335950 DBI_RD = 0x0
6213 23:19:04.336037 OTF = 0x1
6214 23:19:04.339200 ===================================
6215 23:19:04.345591 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6216 23:19:04.349421 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6217 23:19:04.352450 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6218 23:19:04.355487 ===================================
6219 23:19:04.359131 LPDDR4 DRAM CONFIGURATION
6220 23:19:04.362384 ===================================
6221 23:19:04.365431 EX_ROW_EN[0] = 0x10
6222 23:19:04.365505 EX_ROW_EN[1] = 0x0
6223 23:19:04.368851 LP4Y_EN = 0x0
6224 23:19:04.368949 WORK_FSP = 0x0
6225 23:19:04.372081 WL = 0x2
6226 23:19:04.372185 RL = 0x2
6227 23:19:04.375066 BL = 0x2
6228 23:19:04.375179 RPST = 0x0
6229 23:19:04.378604 RD_PRE = 0x0
6230 23:19:04.378700 WR_PRE = 0x1
6231 23:19:04.382043 WR_PST = 0x0
6232 23:19:04.382143 DBI_WR = 0x0
6233 23:19:04.385472 DBI_RD = 0x0
6234 23:19:04.385578 OTF = 0x1
6235 23:19:04.388361 ===================================
6236 23:19:04.394890 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6237 23:19:04.400057 nWR fixed to 30
6238 23:19:04.403514 [ModeRegInit_LP4] CH0 RK0
6239 23:19:04.403628 [ModeRegInit_LP4] CH0 RK1
6240 23:19:04.406977 [ModeRegInit_LP4] CH1 RK0
6241 23:19:04.410214 [ModeRegInit_LP4] CH1 RK1
6242 23:19:04.410297 match AC timing 19
6243 23:19:04.416953 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6244 23:19:04.420128 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6245 23:19:04.423635 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6246 23:19:04.429993 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6247 23:19:04.433081 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6248 23:19:04.433158 ==
6249 23:19:04.436663 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 23:19:04.439708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 23:19:04.439796 ==
6252 23:19:04.447162 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6253 23:19:04.452706 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6254 23:19:04.456340 [CA 0] Center 36 (8~64) winsize 57
6255 23:19:04.459257 [CA 1] Center 36 (8~64) winsize 57
6256 23:19:04.462858 [CA 2] Center 36 (8~64) winsize 57
6257 23:19:04.466054 [CA 3] Center 36 (8~64) winsize 57
6258 23:19:04.469297 [CA 4] Center 36 (8~64) winsize 57
6259 23:19:04.472769 [CA 5] Center 36 (8~64) winsize 57
6260 23:19:04.472852
6261 23:19:04.476341 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6262 23:19:04.476424
6263 23:19:04.479320 [CATrainingPosCal] consider 1 rank data
6264 23:19:04.482567 u2DelayCellTimex100 = 270/100 ps
6265 23:19:04.486208 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 23:19:04.489327 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 23:19:04.492269 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 23:19:04.495787 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 23:19:04.498743 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 23:19:04.502044 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 23:19:04.502166
6272 23:19:04.508556 CA PerBit enable=1, Macro0, CA PI delay=36
6273 23:19:04.508641
6274 23:19:04.508707 [CBTSetCACLKResult] CA Dly = 36
6275 23:19:04.511825 CS Dly: 1 (0~32)
6276 23:19:04.511964 ==
6277 23:19:04.515244 Dram Type= 6, Freq= 0, CH_0, rank 1
6278 23:19:04.518770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 23:19:04.518896 ==
6280 23:19:04.525396 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6281 23:19:04.532289 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6282 23:19:04.535314 [CA 0] Center 36 (8~64) winsize 57
6283 23:19:04.538557 [CA 1] Center 36 (8~64) winsize 57
6284 23:19:04.542021 [CA 2] Center 36 (8~64) winsize 57
6285 23:19:04.545027 [CA 3] Center 36 (8~64) winsize 57
6286 23:19:04.545153 [CA 4] Center 36 (8~64) winsize 57
6287 23:19:04.548786 [CA 5] Center 36 (8~64) winsize 57
6288 23:19:04.548913
6289 23:19:04.554791 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6290 23:19:04.554914
6291 23:19:04.558313 [CATrainingPosCal] consider 2 rank data
6292 23:19:04.561478 u2DelayCellTimex100 = 270/100 ps
6293 23:19:04.565022 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 23:19:04.568452 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 23:19:04.571558 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 23:19:04.574747 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 23:19:04.578250 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 23:19:04.581330 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 23:19:04.581414
6300 23:19:04.584577 CA PerBit enable=1, Macro0, CA PI delay=36
6301 23:19:04.584660
6302 23:19:04.587820 [CBTSetCACLKResult] CA Dly = 36
6303 23:19:04.591098 CS Dly: 1 (0~32)
6304 23:19:04.591225
6305 23:19:04.594671 ----->DramcWriteLeveling(PI) begin...
6306 23:19:04.594798 ==
6307 23:19:04.597545 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 23:19:04.600823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 23:19:04.600949 ==
6310 23:19:04.604035 Write leveling (Byte 0): 40 => 8
6311 23:19:04.607827 Write leveling (Byte 1): 40 => 8
6312 23:19:04.610723 DramcWriteLeveling(PI) end<-----
6313 23:19:04.610807
6314 23:19:04.610874 ==
6315 23:19:04.614362 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 23:19:04.617635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 23:19:04.617733 ==
6318 23:19:04.620497 [Gating] SW mode calibration
6319 23:19:04.627545 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6320 23:19:04.633829 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6321 23:19:04.636991 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6322 23:19:04.644099 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6323 23:19:04.646994 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 23:19:04.650347 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 23:19:04.657246 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 23:19:04.660272 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 23:19:04.663887 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 23:19:04.670207 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 23:19:04.673662 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 23:19:04.676801 Total UI for P1: 0, mck2ui 16
6331 23:19:04.680056 best dqsien dly found for B0: ( 0, 14, 24)
6332 23:19:04.683399 Total UI for P1: 0, mck2ui 16
6333 23:19:04.686720 best dqsien dly found for B1: ( 0, 14, 24)
6334 23:19:04.689882 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6335 23:19:04.693321 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6336 23:19:04.693432
6337 23:19:04.696545 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6338 23:19:04.699683 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6339 23:19:04.703393 [Gating] SW calibration Done
6340 23:19:04.703515 ==
6341 23:19:04.706465 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 23:19:04.713180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 23:19:04.713275 ==
6344 23:19:04.713344 RX Vref Scan: 0
6345 23:19:04.713406
6346 23:19:04.716268 RX Vref 0 -> 0, step: 1
6347 23:19:04.716375
6348 23:19:04.719475 RX Delay -410 -> 252, step: 16
6349 23:19:04.722895 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6350 23:19:04.726302 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6351 23:19:04.733476 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6352 23:19:04.736352 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6353 23:19:04.739595 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6354 23:19:04.742996 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6355 23:19:04.749307 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6356 23:19:04.752546 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6357 23:19:04.756222 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6358 23:19:04.759356 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6359 23:19:04.766127 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6360 23:19:04.769016 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6361 23:19:04.772678 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6362 23:19:04.775701 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6363 23:19:04.782306 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6364 23:19:04.785765 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6365 23:19:04.785849 ==
6366 23:19:04.788749 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 23:19:04.792227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 23:19:04.792310 ==
6369 23:19:04.795313 DQS Delay:
6370 23:19:04.795417 DQS0 = 35, DQS1 = 51
6371 23:19:04.798406 DQM Delay:
6372 23:19:04.798531 DQM0 = 5, DQM1 = 10
6373 23:19:04.802251 DQ Delay:
6374 23:19:04.802373 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6375 23:19:04.805371 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6376 23:19:04.808767 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6377 23:19:04.811881 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6378 23:19:04.812003
6379 23:19:04.812115
6380 23:19:04.812219 ==
6381 23:19:04.815269 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 23:19:04.822017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 23:19:04.822134 ==
6384 23:19:04.822244
6385 23:19:04.822352
6386 23:19:04.822455 TX Vref Scan disable
6387 23:19:04.825062 == TX Byte 0 ==
6388 23:19:04.827983 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 23:19:04.831705 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 23:19:04.834698 == TX Byte 1 ==
6391 23:19:04.838132 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 23:19:04.841304 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 23:19:04.844570 ==
6394 23:19:04.847957 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 23:19:04.851199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 23:19:04.851323 ==
6397 23:19:04.851467
6398 23:19:04.851573
6399 23:19:04.854651 TX Vref Scan disable
6400 23:19:04.854769 == TX Byte 0 ==
6401 23:19:04.857515 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 23:19:04.864022 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 23:19:04.864147 == TX Byte 1 ==
6404 23:19:04.867392 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 23:19:04.874049 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 23:19:04.874169
6407 23:19:04.874282 [DATLAT]
6408 23:19:04.874390 Freq=400, CH0 RK0
6409 23:19:04.874496
6410 23:19:04.877542 DATLAT Default: 0xf
6411 23:19:04.880667 0, 0xFFFF, sum = 0
6412 23:19:04.880749 1, 0xFFFF, sum = 0
6413 23:19:04.884052 2, 0xFFFF, sum = 0
6414 23:19:04.884176 3, 0xFFFF, sum = 0
6415 23:19:04.887548 4, 0xFFFF, sum = 0
6416 23:19:04.887630 5, 0xFFFF, sum = 0
6417 23:19:04.890801 6, 0xFFFF, sum = 0
6418 23:19:04.890926 7, 0xFFFF, sum = 0
6419 23:19:04.893862 8, 0xFFFF, sum = 0
6420 23:19:04.893986 9, 0xFFFF, sum = 0
6421 23:19:04.897166 10, 0xFFFF, sum = 0
6422 23:19:04.897286 11, 0xFFFF, sum = 0
6423 23:19:04.900409 12, 0xFFFF, sum = 0
6424 23:19:04.900544 13, 0x0, sum = 1
6425 23:19:04.903677 14, 0x0, sum = 2
6426 23:19:04.903799 15, 0x0, sum = 3
6427 23:19:04.907345 16, 0x0, sum = 4
6428 23:19:04.907489 best_step = 14
6429 23:19:04.907599
6430 23:19:04.907706 ==
6431 23:19:04.910426 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 23:19:04.917191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 23:19:04.917310 ==
6434 23:19:04.917425 RX Vref Scan: 1
6435 23:19:04.917534
6436 23:19:04.920033 RX Vref 0 -> 0, step: 1
6437 23:19:04.920153
6438 23:19:04.923299 RX Delay -343 -> 252, step: 8
6439 23:19:04.923458
6440 23:19:04.926988 Set Vref, RX VrefLevel [Byte0]: 52
6441 23:19:04.930047 [Byte1]: 50
6442 23:19:04.933213
6443 23:19:04.933334 Final RX Vref Byte 0 = 52 to rank0
6444 23:19:04.936823 Final RX Vref Byte 1 = 50 to rank0
6445 23:19:04.940344 Final RX Vref Byte 0 = 52 to rank1
6446 23:19:04.943502 Final RX Vref Byte 1 = 50 to rank1==
6447 23:19:04.946832 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 23:19:04.953071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 23:19:04.953153 ==
6450 23:19:04.953217 DQS Delay:
6451 23:19:04.956750 DQS0 = 44, DQS1 = 60
6452 23:19:04.956830 DQM Delay:
6453 23:19:04.956894 DQM0 = 10, DQM1 = 17
6454 23:19:04.960245 DQ Delay:
6455 23:19:04.963133 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6456 23:19:04.963241 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6457 23:19:04.966558 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6458 23:19:04.969912 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6459 23:19:04.973359
6460 23:19:04.973441
6461 23:19:04.979494 [DQSOSCAuto] RK0, (LSB)MR18= 0x9185, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6462 23:19:04.982809 CH0 RK0: MR19=C0C, MR18=9185
6463 23:19:04.989742 CH0_RK0: MR19=0xC0C, MR18=0x9185, DQSOSC=391, MR23=63, INC=386, DEC=257
6464 23:19:04.989871 ==
6465 23:19:04.992701 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 23:19:04.995923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 23:19:04.996051 ==
6468 23:19:04.999118 [Gating] SW mode calibration
6469 23:19:05.005656 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6470 23:19:05.012270 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6471 23:19:05.015983 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 23:19:05.019296 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6473 23:19:05.025861 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 23:19:05.028976 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 23:19:05.032534 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 23:19:05.039024 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 23:19:05.042122 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 23:19:05.045697 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 23:19:05.051944 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 23:19:05.055076 Total UI for P1: 0, mck2ui 16
6481 23:19:05.058945 best dqsien dly found for B0: ( 0, 14, 24)
6482 23:19:05.059028 Total UI for P1: 0, mck2ui 16
6483 23:19:05.065134 best dqsien dly found for B1: ( 0, 14, 24)
6484 23:19:05.068674 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6485 23:19:05.071796 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6486 23:19:05.071879
6487 23:19:05.075434 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6488 23:19:05.078461 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6489 23:19:05.082132 [Gating] SW calibration Done
6490 23:19:05.082215 ==
6491 23:19:05.085390 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 23:19:05.088604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 23:19:05.088688 ==
6494 23:19:05.091739 RX Vref Scan: 0
6495 23:19:05.091821
6496 23:19:05.091887 RX Vref 0 -> 0, step: 1
6497 23:19:05.095338
6498 23:19:05.095431 RX Delay -410 -> 252, step: 16
6499 23:19:05.101686 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6500 23:19:05.104712 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6501 23:19:05.108372 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6502 23:19:05.114459 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6503 23:19:05.118362 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6504 23:19:05.121209 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6505 23:19:05.124527 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6506 23:19:05.131035 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6507 23:19:05.134390 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6508 23:19:05.137775 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6509 23:19:05.141037 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6510 23:19:05.147548 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6511 23:19:05.151090 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6512 23:19:05.154532 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6513 23:19:05.158049 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6514 23:19:05.164074 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6515 23:19:05.164167 ==
6516 23:19:05.167770 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 23:19:05.170468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 23:19:05.170600 ==
6519 23:19:05.173743 DQS Delay:
6520 23:19:05.173867 DQS0 = 35, DQS1 = 59
6521 23:19:05.173982 DQM Delay:
6522 23:19:05.177370 DQM0 = 7, DQM1 = 17
6523 23:19:05.177493 DQ Delay:
6524 23:19:05.180414 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6525 23:19:05.183713 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6526 23:19:05.187246 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6527 23:19:05.190380 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6528 23:19:05.190503
6529 23:19:05.190620
6530 23:19:05.190733 ==
6531 23:19:05.193997 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 23:19:05.196742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 23:19:05.196865 ==
6534 23:19:05.200409
6535 23:19:05.200533
6536 23:19:05.200651 TX Vref Scan disable
6537 23:19:05.203654 == TX Byte 0 ==
6538 23:19:05.206783 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6539 23:19:05.210112 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6540 23:19:05.213480 == TX Byte 1 ==
6541 23:19:05.217155 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6542 23:19:05.220151 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6543 23:19:05.220275 ==
6544 23:19:05.223246 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 23:19:05.226720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 23:19:05.230177 ==
6547 23:19:05.230276
6548 23:19:05.230365
6549 23:19:05.230457 TX Vref Scan disable
6550 23:19:05.233226 == TX Byte 0 ==
6551 23:19:05.237128 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6552 23:19:05.239973 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6553 23:19:05.243020 == TX Byte 1 ==
6554 23:19:05.246307 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6555 23:19:05.249467 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6556 23:19:05.249551
6557 23:19:05.252719 [DATLAT]
6558 23:19:05.252801 Freq=400, CH0 RK1
6559 23:19:05.252867
6560 23:19:05.256356 DATLAT Default: 0xe
6561 23:19:05.256439 0, 0xFFFF, sum = 0
6562 23:19:05.259577 1, 0xFFFF, sum = 0
6563 23:19:05.259660 2, 0xFFFF, sum = 0
6564 23:19:05.262797 3, 0xFFFF, sum = 0
6565 23:19:05.262872 4, 0xFFFF, sum = 0
6566 23:19:05.266160 5, 0xFFFF, sum = 0
6567 23:19:05.266237 6, 0xFFFF, sum = 0
6568 23:19:05.269227 7, 0xFFFF, sum = 0
6569 23:19:05.269300 8, 0xFFFF, sum = 0
6570 23:19:05.272566 9, 0xFFFF, sum = 0
6571 23:19:05.272697 10, 0xFFFF, sum = 0
6572 23:19:05.275886 11, 0xFFFF, sum = 0
6573 23:19:05.279146 12, 0xFFFF, sum = 0
6574 23:19:05.279229 13, 0x0, sum = 1
6575 23:19:05.282459 14, 0x0, sum = 2
6576 23:19:05.282544 15, 0x0, sum = 3
6577 23:19:05.282611 16, 0x0, sum = 4
6578 23:19:05.285444 best_step = 14
6579 23:19:05.285553
6580 23:19:05.285643 ==
6581 23:19:05.289405 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 23:19:05.292529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 23:19:05.292601 ==
6584 23:19:05.295679 RX Vref Scan: 0
6585 23:19:05.295755
6586 23:19:05.298582 RX Vref 0 -> 0, step: 1
6587 23:19:05.298653
6588 23:19:05.298713 RX Delay -359 -> 252, step: 8
6589 23:19:05.307536 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6590 23:19:05.310708 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6591 23:19:05.314131 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6592 23:19:05.317545 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6593 23:19:05.324059 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6594 23:19:05.327261 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6595 23:19:05.330754 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6596 23:19:05.337251 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6597 23:19:05.340246 iDelay=209, Bit 8, Center -56 (-303 ~ 192) 496
6598 23:19:05.343650 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6599 23:19:05.347327 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6600 23:19:05.353483 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6601 23:19:05.357013 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6602 23:19:05.360062 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6603 23:19:05.363588 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6604 23:19:05.369968 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6605 23:19:05.370053 ==
6606 23:19:05.373311 Dram Type= 6, Freq= 0, CH_0, rank 1
6607 23:19:05.376876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 23:19:05.376967 ==
6609 23:19:05.379690 DQS Delay:
6610 23:19:05.379772 DQS0 = 44, DQS1 = 60
6611 23:19:05.379857 DQM Delay:
6612 23:19:05.382945 DQM0 = 9, DQM1 = 14
6613 23:19:05.383095 DQ Delay:
6614 23:19:05.386600 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6615 23:19:05.389802 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6616 23:19:05.393186 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6617 23:19:05.396104 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6618 23:19:05.396226
6619 23:19:05.396346
6620 23:19:05.406437 [DQSOSCAuto] RK1, (LSB)MR18= 0x8a84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6621 23:19:05.406566 CH0 RK1: MR19=C0C, MR18=8A84
6622 23:19:05.412459 CH0_RK1: MR19=0xC0C, MR18=0x8A84, DQSOSC=392, MR23=63, INC=384, DEC=256
6623 23:19:05.416117 [RxdqsGatingPostProcess] freq 400
6624 23:19:05.422473 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6625 23:19:05.425757 best DQS0 dly(2T, 0.5T) = (0, 10)
6626 23:19:05.428933 best DQS1 dly(2T, 0.5T) = (0, 10)
6627 23:19:05.432214 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6628 23:19:05.436024 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6629 23:19:05.438848 best DQS0 dly(2T, 0.5T) = (0, 10)
6630 23:19:05.442199 best DQS1 dly(2T, 0.5T) = (0, 10)
6631 23:19:05.445410 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6632 23:19:05.448920 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6633 23:19:05.452096 Pre-setting of DQS Precalculation
6634 23:19:05.455153 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6635 23:19:05.455281 ==
6636 23:19:05.458603 Dram Type= 6, Freq= 0, CH_1, rank 0
6637 23:19:05.461807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 23:19:05.461933 ==
6639 23:19:05.468294 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6640 23:19:05.475241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6641 23:19:05.478398 [CA 0] Center 36 (8~64) winsize 57
6642 23:19:05.482121 [CA 1] Center 36 (8~64) winsize 57
6643 23:19:05.485068 [CA 2] Center 36 (8~64) winsize 57
6644 23:19:05.488175 [CA 3] Center 36 (8~64) winsize 57
6645 23:19:05.491575 [CA 4] Center 36 (8~64) winsize 57
6646 23:19:05.495355 [CA 5] Center 36 (8~64) winsize 57
6647 23:19:05.495489
6648 23:19:05.498419 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6649 23:19:05.498551
6650 23:19:05.501338 [CATrainingPosCal] consider 1 rank data
6651 23:19:05.504796 u2DelayCellTimex100 = 270/100 ps
6652 23:19:05.508253 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 23:19:05.511659 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 23:19:05.514749 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 23:19:05.518144 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 23:19:05.521028 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 23:19:05.524520 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 23:19:05.524646
6659 23:19:05.531073 CA PerBit enable=1, Macro0, CA PI delay=36
6660 23:19:05.531201
6661 23:19:05.531320 [CBTSetCACLKResult] CA Dly = 36
6662 23:19:05.534573 CS Dly: 1 (0~32)
6663 23:19:05.534698 ==
6664 23:19:05.537768 Dram Type= 6, Freq= 0, CH_1, rank 1
6665 23:19:05.541002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 23:19:05.541128 ==
6667 23:19:05.547684 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6668 23:19:05.554181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6669 23:19:05.557905 [CA 0] Center 36 (8~64) winsize 57
6670 23:19:05.560675 [CA 1] Center 36 (8~64) winsize 57
6671 23:19:05.564266 [CA 2] Center 36 (8~64) winsize 57
6672 23:19:05.567766 [CA 3] Center 36 (8~64) winsize 57
6673 23:19:05.567853 [CA 4] Center 36 (8~64) winsize 57
6674 23:19:05.570794 [CA 5] Center 36 (8~64) winsize 57
6675 23:19:05.570879
6676 23:19:05.577127 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6677 23:19:05.577212
6678 23:19:05.581191 [CATrainingPosCal] consider 2 rank data
6679 23:19:05.583907 u2DelayCellTimex100 = 270/100 ps
6680 23:19:05.586745 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 23:19:05.590351 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 23:19:05.593538 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 23:19:05.597095 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 23:19:05.599882 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 23:19:05.603614 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 23:19:05.603723
6687 23:19:05.606908 CA PerBit enable=1, Macro0, CA PI delay=36
6688 23:19:05.607022
6689 23:19:05.610371 [CBTSetCACLKResult] CA Dly = 36
6690 23:19:05.613550 CS Dly: 1 (0~32)
6691 23:19:05.613632
6692 23:19:05.616730 ----->DramcWriteLeveling(PI) begin...
6693 23:19:05.616815 ==
6694 23:19:05.620051 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 23:19:05.623332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 23:19:05.623454 ==
6697 23:19:05.626556 Write leveling (Byte 0): 40 => 8
6698 23:19:05.629750 Write leveling (Byte 1): 40 => 8
6699 23:19:05.633436 DramcWriteLeveling(PI) end<-----
6700 23:19:05.633543
6701 23:19:05.633611 ==
6702 23:19:05.636246 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 23:19:05.639475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 23:19:05.639558 ==
6705 23:19:05.642927 [Gating] SW mode calibration
6706 23:19:05.649623 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6707 23:19:05.656173 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6708 23:19:05.659558 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6709 23:19:05.666350 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6710 23:19:05.669302 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 23:19:05.672875 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 23:19:05.679112 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 23:19:05.682486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 23:19:05.685836 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 23:19:05.692479 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 23:19:05.695752 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 23:19:05.698793 Total UI for P1: 0, mck2ui 16
6718 23:19:05.702410 best dqsien dly found for B0: ( 0, 14, 24)
6719 23:19:05.705826 Total UI for P1: 0, mck2ui 16
6720 23:19:05.708692 best dqsien dly found for B1: ( 0, 14, 24)
6721 23:19:05.712555 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6722 23:19:05.715826 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6723 23:19:05.715926
6724 23:19:05.718644 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6725 23:19:05.725315 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6726 23:19:05.725399 [Gating] SW calibration Done
6727 23:19:05.725465 ==
6728 23:19:05.728509 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 23:19:05.735251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 23:19:05.735376 ==
6731 23:19:05.735541 RX Vref Scan: 0
6732 23:19:05.735646
6733 23:19:05.738409 RX Vref 0 -> 0, step: 1
6734 23:19:05.738490
6735 23:19:05.741882 RX Delay -410 -> 252, step: 16
6736 23:19:05.745235 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6737 23:19:05.748475 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6738 23:19:05.755127 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6739 23:19:05.758651 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6740 23:19:05.761500 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6741 23:19:05.764891 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6742 23:19:05.771809 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6743 23:19:05.775122 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6744 23:19:05.778357 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6745 23:19:05.781575 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6746 23:19:05.788107 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6747 23:19:05.791248 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6748 23:19:05.794634 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6749 23:19:05.798454 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6750 23:19:05.804307 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6751 23:19:05.808073 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6752 23:19:05.808170 ==
6753 23:19:05.810915 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 23:19:05.814333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 23:19:05.814415 ==
6756 23:19:05.817802 DQS Delay:
6757 23:19:05.817898 DQS0 = 43, DQS1 = 51
6758 23:19:05.821092 DQM Delay:
6759 23:19:05.821173 DQM0 = 13, DQM1 = 13
6760 23:19:05.824709 DQ Delay:
6761 23:19:05.824791 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6762 23:19:05.827611 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6763 23:19:05.831024 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6764 23:19:05.835079 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6765 23:19:05.835160
6766 23:19:05.835225
6767 23:19:05.835284 ==
6768 23:19:05.837965 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 23:19:05.843989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 23:19:05.844071 ==
6771 23:19:05.844136
6772 23:19:05.844195
6773 23:19:05.844252 TX Vref Scan disable
6774 23:19:05.847677 == TX Byte 0 ==
6775 23:19:05.850682 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 23:19:05.854415 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 23:19:05.857458 == TX Byte 1 ==
6778 23:19:05.860842 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 23:19:05.864196 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 23:19:05.867228 ==
6781 23:19:05.870373 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 23:19:05.874074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 23:19:05.874178 ==
6784 23:19:05.874280
6785 23:19:05.874367
6786 23:19:05.876956 TX Vref Scan disable
6787 23:19:05.877035 == TX Byte 0 ==
6788 23:19:05.880306 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 23:19:05.887079 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 23:19:05.887193 == TX Byte 1 ==
6791 23:19:05.890292 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 23:19:05.896728 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 23:19:05.896807
6794 23:19:05.896871 [DATLAT]
6795 23:19:05.896932 Freq=400, CH1 RK0
6796 23:19:05.899800
6797 23:19:05.899878 DATLAT Default: 0xf
6798 23:19:05.903592 0, 0xFFFF, sum = 0
6799 23:19:05.903699 1, 0xFFFF, sum = 0
6800 23:19:05.906594 2, 0xFFFF, sum = 0
6801 23:19:05.906668 3, 0xFFFF, sum = 0
6802 23:19:05.909822 4, 0xFFFF, sum = 0
6803 23:19:05.909925 5, 0xFFFF, sum = 0
6804 23:19:05.913013 6, 0xFFFF, sum = 0
6805 23:19:05.913116 7, 0xFFFF, sum = 0
6806 23:19:05.916596 8, 0xFFFF, sum = 0
6807 23:19:05.916699 9, 0xFFFF, sum = 0
6808 23:19:05.919944 10, 0xFFFF, sum = 0
6809 23:19:05.920034 11, 0xFFFF, sum = 0
6810 23:19:05.923274 12, 0xFFFF, sum = 0
6811 23:19:05.923401 13, 0x0, sum = 1
6812 23:19:05.926066 14, 0x0, sum = 2
6813 23:19:05.926156 15, 0x0, sum = 3
6814 23:19:05.929757 16, 0x0, sum = 4
6815 23:19:05.929836 best_step = 14
6816 23:19:05.929899
6817 23:19:05.929962 ==
6818 23:19:05.932592 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 23:19:05.939244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 23:19:05.939358 ==
6821 23:19:05.939468 RX Vref Scan: 1
6822 23:19:05.939529
6823 23:19:05.942634 RX Vref 0 -> 0, step: 1
6824 23:19:05.942707
6825 23:19:05.945939 RX Delay -343 -> 252, step: 8
6826 23:19:05.946028
6827 23:19:05.949899 Set Vref, RX VrefLevel [Byte0]: 50
6828 23:19:05.952868 [Byte1]: 53
6829 23:19:05.952981
6830 23:19:05.956245 Final RX Vref Byte 0 = 50 to rank0
6831 23:19:05.959131 Final RX Vref Byte 1 = 53 to rank0
6832 23:19:05.962589 Final RX Vref Byte 0 = 50 to rank1
6833 23:19:05.965733 Final RX Vref Byte 1 = 53 to rank1==
6834 23:19:05.969138 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 23:19:05.972313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 23:19:05.976041 ==
6837 23:19:05.976126 DQS Delay:
6838 23:19:05.976196 DQS0 = 44, DQS1 = 52
6839 23:19:05.978978 DQM Delay:
6840 23:19:05.979060 DQM0 = 11, DQM1 = 10
6841 23:19:05.982466 DQ Delay:
6842 23:19:05.986103 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6843 23:19:05.986184 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6844 23:19:05.989362 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6845 23:19:05.992176 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6846 23:19:05.992257
6847 23:19:05.992336
6848 23:19:06.002349 [DQSOSCAuto] RK0, (LSB)MR18= 0x648b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6849 23:19:06.005972 CH1 RK0: MR19=C0C, MR18=648B
6850 23:19:06.012433 CH1_RK0: MR19=0xC0C, MR18=0x648B, DQSOSC=392, MR23=63, INC=384, DEC=256
6851 23:19:06.012516 ==
6852 23:19:06.015660 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 23:19:06.019062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 23:19:06.019144 ==
6855 23:19:06.021984 [Gating] SW mode calibration
6856 23:19:06.028756 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6857 23:19:06.035340 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6858 23:19:06.038652 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6859 23:19:06.041990 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6860 23:19:06.048374 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 23:19:06.051912 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 23:19:06.055078 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 23:19:06.061284 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 23:19:06.064656 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 23:19:06.067869 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 23:19:06.074324 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 23:19:06.074444 Total UI for P1: 0, mck2ui 16
6868 23:19:06.081426 best dqsien dly found for B0: ( 0, 14, 24)
6869 23:19:06.081523 Total UI for P1: 0, mck2ui 16
6870 23:19:06.087784 best dqsien dly found for B1: ( 0, 14, 24)
6871 23:19:06.091116 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6872 23:19:06.094167 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6873 23:19:06.094260
6874 23:19:06.097539 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6875 23:19:06.100864 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6876 23:19:06.104436 [Gating] SW calibration Done
6877 23:19:06.104506 ==
6878 23:19:06.107543 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 23:19:06.110741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 23:19:06.110829 ==
6881 23:19:06.113804 RX Vref Scan: 0
6882 23:19:06.113904
6883 23:19:06.117305 RX Vref 0 -> 0, step: 1
6884 23:19:06.117416
6885 23:19:06.117513 RX Delay -410 -> 252, step: 16
6886 23:19:06.124017 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6887 23:19:06.127047 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6888 23:19:06.130806 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6889 23:19:06.137179 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6890 23:19:06.140513 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6891 23:19:06.143641 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6892 23:19:06.146722 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6893 23:19:06.153334 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6894 23:19:06.156382 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6895 23:19:06.159571 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6896 23:19:06.163654 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6897 23:19:06.169812 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6898 23:19:06.173054 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6899 23:19:06.176227 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6900 23:19:06.182694 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6901 23:19:06.186294 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6902 23:19:06.186378 ==
6903 23:19:06.189420 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 23:19:06.192909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 23:19:06.192995 ==
6906 23:19:06.195968 DQS Delay:
6907 23:19:06.196054 DQS0 = 43, DQS1 = 51
6908 23:19:06.196122 DQM Delay:
6909 23:19:06.199235 DQM0 = 9, DQM1 = 13
6910 23:19:06.199319 DQ Delay:
6911 23:19:06.202865 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6912 23:19:06.206223 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6913 23:19:06.209565 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6914 23:19:06.212579 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6915 23:19:06.212661
6916 23:19:06.212725
6917 23:19:06.212785 ==
6918 23:19:06.216048 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 23:19:06.219399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 23:19:06.222835 ==
6921 23:19:06.222917
6922 23:19:06.222981
6923 23:19:06.223041 TX Vref Scan disable
6924 23:19:06.225565 == TX Byte 0 ==
6925 23:19:06.228849 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6926 23:19:06.232830 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6927 23:19:06.235654 == TX Byte 1 ==
6928 23:19:06.239023 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6929 23:19:06.242577 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6930 23:19:06.242660 ==
6931 23:19:06.245913 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 23:19:06.248921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 23:19:06.252277 ==
6934 23:19:06.252359
6935 23:19:06.252475
6936 23:19:06.252550 TX Vref Scan disable
6937 23:19:06.255475 == TX Byte 0 ==
6938 23:19:06.258789 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6939 23:19:06.262596 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6940 23:19:06.265330 == TX Byte 1 ==
6941 23:19:06.269319 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6942 23:19:06.271856 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6943 23:19:06.271937
6944 23:19:06.275645 [DATLAT]
6945 23:19:06.275727 Freq=400, CH1 RK1
6946 23:19:06.275792
6947 23:19:06.279234 DATLAT Default: 0xe
6948 23:19:06.279316 0, 0xFFFF, sum = 0
6949 23:19:06.281860 1, 0xFFFF, sum = 0
6950 23:19:06.281946 2, 0xFFFF, sum = 0
6951 23:19:06.285394 3, 0xFFFF, sum = 0
6952 23:19:06.285495 4, 0xFFFF, sum = 0
6953 23:19:06.288638 5, 0xFFFF, sum = 0
6954 23:19:06.288738 6, 0xFFFF, sum = 0
6955 23:19:06.292185 7, 0xFFFF, sum = 0
6956 23:19:06.292285 8, 0xFFFF, sum = 0
6957 23:19:06.295280 9, 0xFFFF, sum = 0
6958 23:19:06.295374 10, 0xFFFF, sum = 0
6959 23:19:06.298339 11, 0xFFFF, sum = 0
6960 23:19:06.301768 12, 0xFFFF, sum = 0
6961 23:19:06.301851 13, 0x0, sum = 1
6962 23:19:06.301947 14, 0x0, sum = 2
6963 23:19:06.304817 15, 0x0, sum = 3
6964 23:19:06.304901 16, 0x0, sum = 4
6965 23:19:06.308324 best_step = 14
6966 23:19:06.308405
6967 23:19:06.308470 ==
6968 23:19:06.311356 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 23:19:06.314722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 23:19:06.314805 ==
6971 23:19:06.318018 RX Vref Scan: 0
6972 23:19:06.318117
6973 23:19:06.321041 RX Vref 0 -> 0, step: 1
6974 23:19:06.321173
6975 23:19:06.321253 RX Delay -343 -> 252, step: 8
6976 23:19:06.329571 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6977 23:19:06.333024 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6978 23:19:06.336355 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6979 23:19:06.343123 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6980 23:19:06.346231 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6981 23:19:06.349478 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6982 23:19:06.352852 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6983 23:19:06.359561 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6984 23:19:06.362539 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6985 23:19:06.365926 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6986 23:19:06.369379 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6987 23:19:06.375854 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6988 23:19:06.379058 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6989 23:19:06.382459 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6990 23:19:06.389123 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6991 23:19:06.392136 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6992 23:19:06.392245 ==
6993 23:19:06.395550 Dram Type= 6, Freq= 0, CH_1, rank 1
6994 23:19:06.398604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6995 23:19:06.398683 ==
6996 23:19:06.402151 DQS Delay:
6997 23:19:06.402260 DQS0 = 48, DQS1 = 52
6998 23:19:06.402353 DQM Delay:
6999 23:19:06.405153 DQM0 = 12, DQM1 = 10
7000 23:19:06.405269 DQ Delay:
7001 23:19:06.408621 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7002 23:19:06.411841 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7003 23:19:06.414889 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7004 23:19:06.418621 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7005 23:19:06.418732
7006 23:19:06.418827
7007 23:19:06.428541 [DQSOSCAuto] RK1, (LSB)MR18= 0x6fa7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7008 23:19:06.428627 CH1 RK1: MR19=C0C, MR18=6FA7
7009 23:19:06.434952 CH1_RK1: MR19=0xC0C, MR18=0x6FA7, DQSOSC=389, MR23=63, INC=390, DEC=260
7010 23:19:06.438048 [RxdqsGatingPostProcess] freq 400
7011 23:19:06.445301 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7012 23:19:06.448190 best DQS0 dly(2T, 0.5T) = (0, 10)
7013 23:19:06.451179 best DQS1 dly(2T, 0.5T) = (0, 10)
7014 23:19:06.454768 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7015 23:19:06.457765 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7016 23:19:06.461229 best DQS0 dly(2T, 0.5T) = (0, 10)
7017 23:19:06.464561 best DQS1 dly(2T, 0.5T) = (0, 10)
7018 23:19:06.467960 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7019 23:19:06.471088 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7020 23:19:06.474367 Pre-setting of DQS Precalculation
7021 23:19:06.477627 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7022 23:19:06.484314 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7023 23:19:06.491317 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7024 23:19:06.491422
7025 23:19:06.491490
7026 23:19:06.494095 [Calibration Summary] 800 Mbps
7027 23:19:06.497305 CH 0, Rank 0
7028 23:19:06.497389 SW Impedance : PASS
7029 23:19:06.500617 DUTY Scan : NO K
7030 23:19:06.504075 ZQ Calibration : PASS
7031 23:19:06.504191 Jitter Meter : NO K
7032 23:19:06.507481 CBT Training : PASS
7033 23:19:06.510740 Write leveling : PASS
7034 23:19:06.510822 RX DQS gating : PASS
7035 23:19:06.513747 RX DQ/DQS(RDDQC) : PASS
7036 23:19:06.517115 TX DQ/DQS : PASS
7037 23:19:06.517228 RX DATLAT : PASS
7038 23:19:06.520297 RX DQ/DQS(Engine): PASS
7039 23:19:06.523783 TX OE : NO K
7040 23:19:06.523879 All Pass.
7041 23:19:06.523944
7042 23:19:06.524019 CH 0, Rank 1
7043 23:19:06.527192 SW Impedance : PASS
7044 23:19:06.530611 DUTY Scan : NO K
7045 23:19:06.530708 ZQ Calibration : PASS
7046 23:19:06.533593 Jitter Meter : NO K
7047 23:19:06.536906 CBT Training : PASS
7048 23:19:06.536990 Write leveling : NO K
7049 23:19:06.540459 RX DQS gating : PASS
7050 23:19:06.540543 RX DQ/DQS(RDDQC) : PASS
7051 23:19:06.543596 TX DQ/DQS : PASS
7052 23:19:06.546773 RX DATLAT : PASS
7053 23:19:06.546873 RX DQ/DQS(Engine): PASS
7054 23:19:06.550971 TX OE : NO K
7055 23:19:06.551053 All Pass.
7056 23:19:06.551133
7057 23:19:06.553680 CH 1, Rank 0
7058 23:19:06.553792 SW Impedance : PASS
7059 23:19:06.556719 DUTY Scan : NO K
7060 23:19:06.560045 ZQ Calibration : PASS
7061 23:19:06.560128 Jitter Meter : NO K
7062 23:19:06.563349 CBT Training : PASS
7063 23:19:06.566984 Write leveling : PASS
7064 23:19:06.567096 RX DQS gating : PASS
7065 23:19:06.569962 RX DQ/DQS(RDDQC) : PASS
7066 23:19:06.574013 TX DQ/DQS : PASS
7067 23:19:06.574095 RX DATLAT : PASS
7068 23:19:06.576813 RX DQ/DQS(Engine): PASS
7069 23:19:06.579956 TX OE : NO K
7070 23:19:06.580055 All Pass.
7071 23:19:06.580134
7072 23:19:06.580194 CH 1, Rank 1
7073 23:19:06.583086 SW Impedance : PASS
7074 23:19:06.586558 DUTY Scan : NO K
7075 23:19:06.586655 ZQ Calibration : PASS
7076 23:19:06.589611 Jitter Meter : NO K
7077 23:19:06.593485 CBT Training : PASS
7078 23:19:06.593575 Write leveling : NO K
7079 23:19:06.596819 RX DQS gating : PASS
7080 23:19:06.599743 RX DQ/DQS(RDDQC) : PASS
7081 23:19:06.599828 TX DQ/DQS : PASS
7082 23:19:06.602979 RX DATLAT : PASS
7083 23:19:06.606731 RX DQ/DQS(Engine): PASS
7084 23:19:06.606826 TX OE : NO K
7085 23:19:06.606891 All Pass.
7086 23:19:06.610127
7087 23:19:06.610211 DramC Write-DBI off
7088 23:19:06.613123 PER_BANK_REFRESH: Hybrid Mode
7089 23:19:06.613231 TX_TRACKING: ON
7090 23:19:06.622630 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7091 23:19:06.625795 [FAST_K] Save calibration result to emmc
7092 23:19:06.629078 dramc_set_vcore_voltage set vcore to 725000
7093 23:19:06.632542 Read voltage for 1600, 0
7094 23:19:06.632647 Vio18 = 0
7095 23:19:06.636155 Vcore = 725000
7096 23:19:06.636265 Vdram = 0
7097 23:19:06.636358 Vddq = 0
7098 23:19:06.639117 Vmddr = 0
7099 23:19:06.642441 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7100 23:19:06.649053 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7101 23:19:06.649145 MEM_TYPE=3, freq_sel=13
7102 23:19:06.652402 sv_algorithm_assistance_LP4_3733
7103 23:19:06.658890 ============ PULL DRAM RESETB DOWN ============
7104 23:19:06.662188 ========== PULL DRAM RESETB DOWN end =========
7105 23:19:06.665220 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7106 23:19:06.668950 ===================================
7107 23:19:06.672275 LPDDR4 DRAM CONFIGURATION
7108 23:19:06.675460 ===================================
7109 23:19:06.675536 EX_ROW_EN[0] = 0x0
7110 23:19:06.678965 EX_ROW_EN[1] = 0x0
7111 23:19:06.682043 LP4Y_EN = 0x0
7112 23:19:06.682117 WORK_FSP = 0x1
7113 23:19:06.685405 WL = 0x5
7114 23:19:06.685480 RL = 0x5
7115 23:19:06.688486 BL = 0x2
7116 23:19:06.688563 RPST = 0x0
7117 23:19:06.691982 RD_PRE = 0x0
7118 23:19:06.692055 WR_PRE = 0x1
7119 23:19:06.694993 WR_PST = 0x1
7120 23:19:06.695064 DBI_WR = 0x0
7121 23:19:06.698983 DBI_RD = 0x0
7122 23:19:06.699058 OTF = 0x1
7123 23:19:06.702024 ===================================
7124 23:19:06.705351 ===================================
7125 23:19:06.708425 ANA top config
7126 23:19:06.711937 ===================================
7127 23:19:06.714978 DLL_ASYNC_EN = 0
7128 23:19:06.715078 ALL_SLAVE_EN = 0
7129 23:19:06.718191 NEW_RANK_MODE = 1
7130 23:19:06.721441 DLL_IDLE_MODE = 1
7131 23:19:06.725027 LP45_APHY_COMB_EN = 1
7132 23:19:06.725159 TX_ODT_DIS = 0
7133 23:19:06.727857 NEW_8X_MODE = 1
7134 23:19:06.731225 ===================================
7135 23:19:06.734764 ===================================
7136 23:19:06.738108 data_rate = 3200
7137 23:19:06.741374 CKR = 1
7138 23:19:06.744305 DQ_P2S_RATIO = 8
7139 23:19:06.747791 ===================================
7140 23:19:06.750913 CA_P2S_RATIO = 8
7141 23:19:06.754224 DQ_CA_OPEN = 0
7142 23:19:06.754349 DQ_SEMI_OPEN = 0
7143 23:19:06.757648 CA_SEMI_OPEN = 0
7144 23:19:06.761296 CA_FULL_RATE = 0
7145 23:19:06.764085 DQ_CKDIV4_EN = 0
7146 23:19:06.767477 CA_CKDIV4_EN = 0
7147 23:19:06.770844 CA_PREDIV_EN = 0
7148 23:19:06.770965 PH8_DLY = 12
7149 23:19:06.774020 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7150 23:19:06.777462 DQ_AAMCK_DIV = 4
7151 23:19:06.780515 CA_AAMCK_DIV = 4
7152 23:19:06.783925 CA_ADMCK_DIV = 4
7153 23:19:06.787348 DQ_TRACK_CA_EN = 0
7154 23:19:06.790523 CA_PICK = 1600
7155 23:19:06.794294 CA_MCKIO = 1600
7156 23:19:06.794406 MCKIO_SEMI = 0
7157 23:19:06.797184 PLL_FREQ = 3068
7158 23:19:06.799987 DQ_UI_PI_RATIO = 32
7159 23:19:06.803613 CA_UI_PI_RATIO = 0
7160 23:19:06.806784 ===================================
7161 23:19:06.809966 ===================================
7162 23:19:06.813148 memory_type:LPDDR4
7163 23:19:06.813246 GP_NUM : 10
7164 23:19:06.816463 SRAM_EN : 1
7165 23:19:06.819734 MD32_EN : 0
7166 23:19:06.823926 ===================================
7167 23:19:06.824140 [ANA_INIT] >>>>>>>>>>>>>>
7168 23:19:06.826329 <<<<<< [CONFIGURE PHASE]: ANA_TX
7169 23:19:06.830311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7170 23:19:06.833581 ===================================
7171 23:19:06.836349 data_rate = 3200,PCW = 0X7600
7172 23:19:06.839783 ===================================
7173 23:19:06.843085 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7174 23:19:06.849891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7175 23:19:06.852679 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7176 23:19:06.859438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7177 23:19:06.862550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7178 23:19:06.865655 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7179 23:19:06.869063 [ANA_INIT] flow start
7180 23:19:06.869160 [ANA_INIT] PLL >>>>>>>>
7181 23:19:06.872803 [ANA_INIT] PLL <<<<<<<<
7182 23:19:06.875947 [ANA_INIT] MIDPI >>>>>>>>
7183 23:19:06.876029 [ANA_INIT] MIDPI <<<<<<<<
7184 23:19:06.879533 [ANA_INIT] DLL >>>>>>>>
7185 23:19:06.882743 [ANA_INIT] DLL <<<<<<<<
7186 23:19:06.882825 [ANA_INIT] flow end
7187 23:19:06.889098 ============ LP4 DIFF to SE enter ============
7188 23:19:06.892228 ============ LP4 DIFF to SE exit ============
7189 23:19:06.895672 [ANA_INIT] <<<<<<<<<<<<<
7190 23:19:06.899101 [Flow] Enable top DCM control >>>>>
7191 23:19:06.902246 [Flow] Enable top DCM control <<<<<
7192 23:19:06.902377 Enable DLL master slave shuffle
7193 23:19:06.908822 ==============================================================
7194 23:19:06.912470 Gating Mode config
7195 23:19:06.915575 ==============================================================
7196 23:19:06.918746 Config description:
7197 23:19:06.928756 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7198 23:19:06.935665 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7199 23:19:06.938344 SELPH_MODE 0: By rank 1: By Phase
7200 23:19:06.945345 ==============================================================
7201 23:19:06.948381 GAT_TRACK_EN = 1
7202 23:19:06.951608 RX_GATING_MODE = 2
7203 23:19:06.954972 RX_GATING_TRACK_MODE = 2
7204 23:19:06.958111 SELPH_MODE = 1
7205 23:19:06.961539 PICG_EARLY_EN = 1
7206 23:19:06.961668 VALID_LAT_VALUE = 1
7207 23:19:06.968419 ==============================================================
7208 23:19:06.971320 Enter into Gating configuration >>>>
7209 23:19:06.974453 Exit from Gating configuration <<<<
7210 23:19:06.977714 Enter into DVFS_PRE_config >>>>>
7211 23:19:06.987939 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7212 23:19:06.991240 Exit from DVFS_PRE_config <<<<<
7213 23:19:06.994239 Enter into PICG configuration >>>>
7214 23:19:06.997488 Exit from PICG configuration <<<<
7215 23:19:07.001062 [RX_INPUT] configuration >>>>>
7216 23:19:07.003972 [RX_INPUT] configuration <<<<<
7217 23:19:07.010930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7218 23:19:07.013993 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7219 23:19:07.020918 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7220 23:19:07.027143 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7221 23:19:07.033895 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7222 23:19:07.040376 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7223 23:19:07.044108 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7224 23:19:07.047063 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7225 23:19:07.050456 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7226 23:19:07.056814 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7227 23:19:07.060074 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7228 23:19:07.063919 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7229 23:19:07.066831 ===================================
7230 23:19:07.070126 LPDDR4 DRAM CONFIGURATION
7231 23:19:07.073924 ===================================
7232 23:19:07.077138 EX_ROW_EN[0] = 0x0
7233 23:19:07.077265 EX_ROW_EN[1] = 0x0
7234 23:19:07.080501 LP4Y_EN = 0x0
7235 23:19:07.080632 WORK_FSP = 0x1
7236 23:19:07.084463 WL = 0x5
7237 23:19:07.084583 RL = 0x5
7238 23:19:07.086859 BL = 0x2
7239 23:19:07.086984 RPST = 0x0
7240 23:19:07.090106 RD_PRE = 0x0
7241 23:19:07.090232 WR_PRE = 0x1
7242 23:19:07.093245 WR_PST = 0x1
7243 23:19:07.093370 DBI_WR = 0x0
7244 23:19:07.096687 DBI_RD = 0x0
7245 23:19:07.096773 OTF = 0x1
7246 23:19:07.099891 ===================================
7247 23:19:07.106695 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7248 23:19:07.109756 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7249 23:19:07.113215 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7250 23:19:07.116458 ===================================
7251 23:19:07.119901 LPDDR4 DRAM CONFIGURATION
7252 23:19:07.122957 ===================================
7253 23:19:07.126861 EX_ROW_EN[0] = 0x10
7254 23:19:07.126946 EX_ROW_EN[1] = 0x0
7255 23:19:07.129550 LP4Y_EN = 0x0
7256 23:19:07.129659 WORK_FSP = 0x1
7257 23:19:07.133163 WL = 0x5
7258 23:19:07.133247 RL = 0x5
7259 23:19:07.135988 BL = 0x2
7260 23:19:07.136072 RPST = 0x0
7261 23:19:07.139274 RD_PRE = 0x0
7262 23:19:07.139390 WR_PRE = 0x1
7263 23:19:07.142625 WR_PST = 0x1
7264 23:19:07.142709 DBI_WR = 0x0
7265 23:19:07.146222 DBI_RD = 0x0
7266 23:19:07.146350 OTF = 0x1
7267 23:19:07.150215 ===================================
7268 23:19:07.155895 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7269 23:19:07.155982 ==
7270 23:19:07.159572 Dram Type= 6, Freq= 0, CH_0, rank 0
7271 23:19:07.166089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7272 23:19:07.166222 ==
7273 23:19:07.166340 [Duty_Offset_Calibration]
7274 23:19:07.169100 B0:2 B1:0 CA:4
7275 23:19:07.169227
7276 23:19:07.172422 [DutyScan_Calibration_Flow] k_type=0
7277 23:19:07.181346
7278 23:19:07.181475 ==CLK 0==
7279 23:19:07.184776 Final CLK duty delay cell = -4
7280 23:19:07.187887 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7281 23:19:07.191104 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7282 23:19:07.194279 [-4] AVG Duty = 4937%(X100)
7283 23:19:07.194409
7284 23:19:07.197528 CH0 CLK Duty spec in!! Max-Min= 187%
7285 23:19:07.201080 [DutyScan_Calibration_Flow] ====Done====
7286 23:19:07.201208
7287 23:19:07.204390 [DutyScan_Calibration_Flow] k_type=1
7288 23:19:07.221627
7289 23:19:07.221760 ==DQS 0 ==
7290 23:19:07.224961 Final DQS duty delay cell = 0
7291 23:19:07.228257 [0] MAX Duty = 5249%(X100), DQS PI = 38
7292 23:19:07.231742 [0] MIN Duty = 5093%(X100), DQS PI = 4
7293 23:19:07.231868 [0] AVG Duty = 5171%(X100)
7294 23:19:07.234632
7295 23:19:07.234757 ==DQS 1 ==
7296 23:19:07.238084 Final DQS duty delay cell = 0
7297 23:19:07.241313 [0] MAX Duty = 5187%(X100), DQS PI = 2
7298 23:19:07.244802 [0] MIN Duty = 4969%(X100), DQS PI = 12
7299 23:19:07.247833 [0] AVG Duty = 5078%(X100)
7300 23:19:07.247961
7301 23:19:07.251078 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7302 23:19:07.251203
7303 23:19:07.254505 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7304 23:19:07.257940 [DutyScan_Calibration_Flow] ====Done====
7305 23:19:07.258069
7306 23:19:07.261509 [DutyScan_Calibration_Flow] k_type=3
7307 23:19:07.278789
7308 23:19:07.278917 ==DQM 0 ==
7309 23:19:07.281994 Final DQM duty delay cell = 0
7310 23:19:07.285188 [0] MAX Duty = 5124%(X100), DQS PI = 22
7311 23:19:07.288755 [0] MIN Duty = 4875%(X100), DQS PI = 52
7312 23:19:07.292041 [0] AVG Duty = 4999%(X100)
7313 23:19:07.292167
7314 23:19:07.292284 ==DQM 1 ==
7315 23:19:07.295253 Final DQM duty delay cell = 0
7316 23:19:07.298317 [0] MAX Duty = 5000%(X100), DQS PI = 2
7317 23:19:07.301610 [0] MIN Duty = 4844%(X100), DQS PI = 14
7318 23:19:07.304852 [0] AVG Duty = 4922%(X100)
7319 23:19:07.304978
7320 23:19:07.308364 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7321 23:19:07.308489
7322 23:19:07.311555 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7323 23:19:07.315013 [DutyScan_Calibration_Flow] ====Done====
7324 23:19:07.315133
7325 23:19:07.318638 [DutyScan_Calibration_Flow] k_type=2
7326 23:19:07.335719
7327 23:19:07.335843 ==DQ 0 ==
7328 23:19:07.339206 Final DQ duty delay cell = 0
7329 23:19:07.342339 [0] MAX Duty = 5124%(X100), DQS PI = 20
7330 23:19:07.345464 [0] MIN Duty = 4938%(X100), DQS PI = 12
7331 23:19:07.345591 [0] AVG Duty = 5031%(X100)
7332 23:19:07.349032
7333 23:19:07.349153 ==DQ 1 ==
7334 23:19:07.352496 Final DQ duty delay cell = 0
7335 23:19:07.355503 [0] MAX Duty = 5187%(X100), DQS PI = 2
7336 23:19:07.358909 [0] MIN Duty = 4907%(X100), DQS PI = 34
7337 23:19:07.359030 [0] AVG Duty = 5047%(X100)
7338 23:19:07.362592
7339 23:19:07.365782 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7340 23:19:07.365906
7341 23:19:07.368975 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7342 23:19:07.372172 [DutyScan_Calibration_Flow] ====Done====
7343 23:19:07.372257 ==
7344 23:19:07.375529 Dram Type= 6, Freq= 0, CH_1, rank 0
7345 23:19:07.379058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7346 23:19:07.379171 ==
7347 23:19:07.382066 [Duty_Offset_Calibration]
7348 23:19:07.382143 B0:0 B1:-1 CA:3
7349 23:19:07.382207
7350 23:19:07.385414 [DutyScan_Calibration_Flow] k_type=0
7351 23:19:07.395152
7352 23:19:07.395236 ==CLK 0==
7353 23:19:07.398276 Final CLK duty delay cell = -4
7354 23:19:07.401598 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7355 23:19:07.404977 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7356 23:19:07.408352 [-4] AVG Duty = 4922%(X100)
7357 23:19:07.408475
7358 23:19:07.411711 CH1 CLK Duty spec in!! Max-Min= 156%
7359 23:19:07.414834 [DutyScan_Calibration_Flow] ====Done====
7360 23:19:07.414960
7361 23:19:07.418194 [DutyScan_Calibration_Flow] k_type=1
7362 23:19:07.434562
7363 23:19:07.434693 ==DQS 0 ==
7364 23:19:07.437771 Final DQS duty delay cell = 0
7365 23:19:07.441109 [0] MAX Duty = 5250%(X100), DQS PI = 30
7366 23:19:07.444483 [0] MIN Duty = 4938%(X100), DQS PI = 42
7367 23:19:07.447521 [0] AVG Duty = 5094%(X100)
7368 23:19:07.447646
7369 23:19:07.447757 ==DQS 1 ==
7370 23:19:07.450727 Final DQS duty delay cell = -4
7371 23:19:07.453968 [-4] MAX Duty = 4969%(X100), DQS PI = 28
7372 23:19:07.457386 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7373 23:19:07.460560 [-4] AVG Duty = 4891%(X100)
7374 23:19:07.460683
7375 23:19:07.464330 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7376 23:19:07.464453
7377 23:19:07.467374 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7378 23:19:07.470647 [DutyScan_Calibration_Flow] ====Done====
7379 23:19:07.470769
7380 23:19:07.474169 [DutyScan_Calibration_Flow] k_type=3
7381 23:19:07.491573
7382 23:19:07.491697 ==DQM 0 ==
7383 23:19:07.494845 Final DQM duty delay cell = 0
7384 23:19:07.498062 [0] MAX Duty = 5031%(X100), DQS PI = 6
7385 23:19:07.501570 [0] MIN Duty = 4782%(X100), DQS PI = 38
7386 23:19:07.505123 [0] AVG Duty = 4906%(X100)
7387 23:19:07.505242
7388 23:19:07.505368 ==DQM 1 ==
7389 23:19:07.508307 Final DQM duty delay cell = 0
7390 23:19:07.511378 [0] MAX Duty = 4969%(X100), DQS PI = 30
7391 23:19:07.514368 [0] MIN Duty = 4813%(X100), DQS PI = 0
7392 23:19:07.517831 [0] AVG Duty = 4891%(X100)
7393 23:19:07.517952
7394 23:19:07.521533 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7395 23:19:07.521673
7396 23:19:07.524155 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7397 23:19:07.527784 [DutyScan_Calibration_Flow] ====Done====
7398 23:19:07.527907
7399 23:19:07.530802 [DutyScan_Calibration_Flow] k_type=2
7400 23:19:07.547779
7401 23:19:07.547906 ==DQ 0 ==
7402 23:19:07.551021 Final DQ duty delay cell = -4
7403 23:19:07.554477 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7404 23:19:07.557554 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7405 23:19:07.560506 [-4] AVG Duty = 4891%(X100)
7406 23:19:07.560627
7407 23:19:07.560741 ==DQ 1 ==
7408 23:19:07.564504 Final DQ duty delay cell = 0
7409 23:19:07.567026 [0] MAX Duty = 5031%(X100), DQS PI = 32
7410 23:19:07.570583 [0] MIN Duty = 4844%(X100), DQS PI = 60
7411 23:19:07.573983 [0] AVG Duty = 4937%(X100)
7412 23:19:07.574152
7413 23:19:07.577196 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7414 23:19:07.577318
7415 23:19:07.580234 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7416 23:19:07.583544 [DutyScan_Calibration_Flow] ====Done====
7417 23:19:07.587227 nWR fixed to 30
7418 23:19:07.590300 [ModeRegInit_LP4] CH0 RK0
7419 23:19:07.590411 [ModeRegInit_LP4] CH0 RK1
7420 23:19:07.593442 [ModeRegInit_LP4] CH1 RK0
7421 23:19:07.596848 [ModeRegInit_LP4] CH1 RK1
7422 23:19:07.596929 match AC timing 5
7423 23:19:07.603475 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7424 23:19:07.606407 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7425 23:19:07.609819 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7426 23:19:07.616509 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7427 23:19:07.619716 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7428 23:19:07.623351 [MiockJmeterHQA]
7429 23:19:07.623479
7430 23:19:07.626437 [DramcMiockJmeter] u1RxGatingPI = 0
7431 23:19:07.626536 0 : 4255, 4026
7432 23:19:07.626628 4 : 4252, 4026
7433 23:19:07.629836 8 : 4252, 4027
7434 23:19:07.629935 12 : 4254, 4029
7435 23:19:07.632789 16 : 4363, 4138
7436 23:19:07.632871 20 : 4252, 4026
7437 23:19:07.636177 24 : 4252, 4027
7438 23:19:07.636258 28 : 4252, 4027
7439 23:19:07.639867 32 : 4255, 4029
7440 23:19:07.639974 36 : 4363, 4138
7441 23:19:07.640109 40 : 4253, 4026
7442 23:19:07.643156 44 : 4249, 4027
7443 23:19:07.643270 48 : 4249, 4027
7444 23:19:07.646095 52 : 4253, 4029
7445 23:19:07.646180 56 : 4250, 4027
7446 23:19:07.649412 60 : 4360, 4137
7447 23:19:07.649523 64 : 4361, 4137
7448 23:19:07.652742 68 : 4249, 4027
7449 23:19:07.652821 72 : 4250, 4026
7450 23:19:07.652884 76 : 4249, 4027
7451 23:19:07.656163 80 : 4249, 4027
7452 23:19:07.656238 84 : 4252, 4030
7453 23:19:07.659302 88 : 4360, 4137
7454 23:19:07.659449 92 : 4250, 4026
7455 23:19:07.662464 96 : 4249, 3002
7456 23:19:07.662591 100 : 4250, 0
7457 23:19:07.662708 104 : 4249, 0
7458 23:19:07.665831 108 : 4250, 0
7459 23:19:07.665957 112 : 4252, 0
7460 23:19:07.669419 116 : 4249, 0
7461 23:19:07.669543 120 : 4252, 0
7462 23:19:07.669656 124 : 4250, 0
7463 23:19:07.672647 128 : 4249, 0
7464 23:19:07.672770 132 : 4363, 0
7465 23:19:07.675662 136 : 4361, 0
7466 23:19:07.675865 140 : 4360, 0
7467 23:19:07.675995 144 : 4363, 0
7468 23:19:07.679209 148 : 4250, 0
7469 23:19:07.679333 152 : 4249, 0
7470 23:19:07.682436 156 : 4249, 0
7471 23:19:07.682560 160 : 4250, 0
7472 23:19:07.682674 164 : 4250, 0
7473 23:19:07.686251 168 : 4250, 0
7474 23:19:07.686377 172 : 4252, 0
7475 23:19:07.686492 176 : 4250, 0
7476 23:19:07.688891 180 : 4249, 0
7477 23:19:07.689017 184 : 4252, 0
7478 23:19:07.692745 188 : 4361, 0
7479 23:19:07.692871 192 : 4360, 0
7480 23:19:07.692986 196 : 4363, 0
7481 23:19:07.695514 200 : 4253, 0
7482 23:19:07.695636 204 : 4253, 0
7483 23:19:07.698786 208 : 4249, 0
7484 23:19:07.698908 212 : 4250, 0
7485 23:19:07.699021 216 : 4250, 0
7486 23:19:07.702056 220 : 4249, 970
7487 23:19:07.702178 224 : 4360, 4127
7488 23:19:07.705733 228 : 4250, 4026
7489 23:19:07.705860 232 : 4361, 4137
7490 23:19:07.709019 236 : 4361, 4138
7491 23:19:07.709145 240 : 4249, 4027
7492 23:19:07.712260 244 : 4250, 4026
7493 23:19:07.712386 248 : 4363, 4140
7494 23:19:07.715489 252 : 4250, 4027
7495 23:19:07.715618 256 : 4250, 4027
7496 23:19:07.719265 260 : 4250, 4026
7497 23:19:07.719403 264 : 4253, 4029
7498 23:19:07.722072 268 : 4250, 4027
7499 23:19:07.722200 272 : 4250, 4027
7500 23:19:07.722318 276 : 4360, 4137
7501 23:19:07.725092 280 : 4250, 4026
7502 23:19:07.725219 284 : 4250, 4027
7503 23:19:07.728355 288 : 4361, 4138
7504 23:19:07.728481 292 : 4250, 4027
7505 23:19:07.731833 296 : 4250, 4026
7506 23:19:07.731960 300 : 4363, 4140
7507 23:19:07.735254 304 : 4250, 4027
7508 23:19:07.735386 308 : 4249, 4027
7509 23:19:07.738445 312 : 4250, 4026
7510 23:19:07.738572 316 : 4253, 4029
7511 23:19:07.741518 320 : 4250, 4027
7512 23:19:07.741643 324 : 4250, 4027
7513 23:19:07.744797 328 : 4360, 4137
7514 23:19:07.744924 332 : 4250, 3967
7515 23:19:07.745042 336 : 4250, 1836
7516 23:19:07.748437
7517 23:19:07.748560 MIOCK jitter meter ch=0
7518 23:19:07.748676
7519 23:19:07.751841 1T = (336-100) = 236 dly cells
7520 23:19:07.758108 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7521 23:19:07.758236 ==
7522 23:19:07.761314 Dram Type= 6, Freq= 0, CH_0, rank 0
7523 23:19:07.764875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 23:19:07.765004 ==
7525 23:19:07.771271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7526 23:19:07.774286 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7527 23:19:07.777715 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7528 23:19:07.784436 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7529 23:19:07.794175 [CA 0] Center 43 (13~73) winsize 61
7530 23:19:07.797561 [CA 1] Center 42 (12~73) winsize 62
7531 23:19:07.800601 [CA 2] Center 37 (8~67) winsize 60
7532 23:19:07.804512 [CA 3] Center 37 (7~67) winsize 61
7533 23:19:07.807456 [CA 4] Center 36 (6~66) winsize 61
7534 23:19:07.811212 [CA 5] Center 35 (5~66) winsize 62
7535 23:19:07.811337
7536 23:19:07.813751 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7537 23:19:07.813873
7538 23:19:07.817064 [CATrainingPosCal] consider 1 rank data
7539 23:19:07.820714 u2DelayCellTimex100 = 275/100 ps
7540 23:19:07.827011 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7541 23:19:07.830254 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7542 23:19:07.833716 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7543 23:19:07.837397 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7544 23:19:07.840435 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7545 23:19:07.843746 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7546 23:19:07.843873
7547 23:19:07.846579 CA PerBit enable=1, Macro0, CA PI delay=35
7548 23:19:07.846702
7549 23:19:07.850288 [CBTSetCACLKResult] CA Dly = 35
7550 23:19:07.853505 CS Dly: 11 (0~42)
7551 23:19:07.856967 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7552 23:19:07.859885 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7553 23:19:07.860009 ==
7554 23:19:07.863567 Dram Type= 6, Freq= 0, CH_0, rank 1
7555 23:19:07.869769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 23:19:07.869898 ==
7557 23:19:07.873157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7558 23:19:07.879551 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7559 23:19:07.883193 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7560 23:19:07.889800 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7561 23:19:07.897588 [CA 0] Center 43 (13~74) winsize 62
7562 23:19:07.900933 [CA 1] Center 43 (13~74) winsize 62
7563 23:19:07.904379 [CA 2] Center 38 (9~68) winsize 60
7564 23:19:07.907661 [CA 3] Center 38 (9~68) winsize 60
7565 23:19:07.910534 [CA 4] Center 36 (6~67) winsize 62
7566 23:19:07.914024 [CA 5] Center 36 (6~66) winsize 61
7567 23:19:07.914104
7568 23:19:07.917189 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7569 23:19:07.917260
7570 23:19:07.924152 [CATrainingPosCal] consider 2 rank data
7571 23:19:07.924235 u2DelayCellTimex100 = 275/100 ps
7572 23:19:07.930280 CA0 delay=43 (13~73),Diff = 7 PI (24 cell)
7573 23:19:07.933926 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7574 23:19:07.936938 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7575 23:19:07.940958 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7576 23:19:07.943807 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7577 23:19:07.947556 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7578 23:19:07.947638
7579 23:19:07.950352 CA PerBit enable=1, Macro0, CA PI delay=36
7580 23:19:07.950461
7581 23:19:07.953195 [CBTSetCACLKResult] CA Dly = 36
7582 23:19:07.956657 CS Dly: 12 (0~44)
7583 23:19:07.959997 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7584 23:19:07.963305 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7585 23:19:07.963407
7586 23:19:07.966358 ----->DramcWriteLeveling(PI) begin...
7587 23:19:07.966465 ==
7588 23:19:07.969933 Dram Type= 6, Freq= 0, CH_0, rank 0
7589 23:19:07.976329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 23:19:07.976409 ==
7591 23:19:07.979528 Write leveling (Byte 0): 36 => 36
7592 23:19:07.982924 Write leveling (Byte 1): 25 => 25
7593 23:19:07.986249 DramcWriteLeveling(PI) end<-----
7594 23:19:07.986356
7595 23:19:07.986449 ==
7596 23:19:07.989479 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 23:19:07.993067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 23:19:07.993176 ==
7599 23:19:07.995996 [Gating] SW mode calibration
7600 23:19:08.002944 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7601 23:19:08.009201 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7602 23:19:08.013023 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 23:19:08.015984 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 23:19:08.022981 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7605 23:19:08.025941 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7606 23:19:08.029190 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7607 23:19:08.035733 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7608 23:19:08.039304 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 23:19:08.042254 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 23:19:08.049245 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 23:19:08.051970 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 23:19:08.055724 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7613 23:19:08.062131 1 5 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
7614 23:19:08.065301 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7615 23:19:08.068951 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
7616 23:19:08.075137 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 23:19:08.078675 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 23:19:08.081830 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 23:19:08.088503 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 23:19:08.091776 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
7621 23:19:08.095008 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7622 23:19:08.101630 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7623 23:19:08.105012 1 6 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
7624 23:19:08.108568 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 23:19:08.114868 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 23:19:08.118167 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 23:19:08.121325 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 23:19:08.128451 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 23:19:08.131401 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7630 23:19:08.134408 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7631 23:19:08.141287 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7632 23:19:08.144173 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7633 23:19:08.148195 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 23:19:08.154606 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 23:19:08.157791 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 23:19:08.160684 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 23:19:08.167105 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 23:19:08.171104 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 23:19:08.173999 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 23:19:08.180664 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 23:19:08.184243 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 23:19:08.187190 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 23:19:08.194031 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 23:19:08.197250 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7645 23:19:08.200325 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 23:19:08.207023 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7647 23:19:08.207108 Total UI for P1: 0, mck2ui 16
7648 23:19:08.213565 best dqsien dly found for B0: ( 1, 9, 10)
7649 23:19:08.217065 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7650 23:19:08.220344 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 23:19:08.223779 Total UI for P1: 0, mck2ui 16
7652 23:19:08.227027 best dqsien dly found for B1: ( 1, 9, 22)
7653 23:19:08.229908 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7654 23:19:08.233422 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7655 23:19:08.233506
7656 23:19:08.240025 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7657 23:19:08.243247 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7658 23:19:08.243324 [Gating] SW calibration Done
7659 23:19:08.246602 ==
7660 23:19:08.249836 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 23:19:08.252957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 23:19:08.253042 ==
7663 23:19:08.253108 RX Vref Scan: 0
7664 23:19:08.253169
7665 23:19:08.256518 RX Vref 0 -> 0, step: 1
7666 23:19:08.256591
7667 23:19:08.259591 RX Delay 0 -> 252, step: 8
7668 23:19:08.262903 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7669 23:19:08.266721 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7670 23:19:08.272648 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7671 23:19:08.276426 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7672 23:19:08.279117 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7673 23:19:08.282726 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7674 23:19:08.286172 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7675 23:19:08.292586 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7676 23:19:08.295557 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7677 23:19:08.299296 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7678 23:19:08.302916 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7679 23:19:08.305671 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7680 23:19:08.311891 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7681 23:19:08.315784 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7682 23:19:08.319550 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7683 23:19:08.322347 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7684 23:19:08.322481 ==
7685 23:19:08.325457 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 23:19:08.332277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 23:19:08.332404 ==
7688 23:19:08.332517 DQS Delay:
7689 23:19:08.335562 DQS0 = 0, DQS1 = 0
7690 23:19:08.335683 DQM Delay:
7691 23:19:08.338778 DQM0 = 131, DQM1 = 127
7692 23:19:08.338900 DQ Delay:
7693 23:19:08.341736 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7694 23:19:08.345402 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7695 23:19:08.348629 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7696 23:19:08.351691 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7697 23:19:08.351814
7698 23:19:08.351928
7699 23:19:08.352034 ==
7700 23:19:08.355250 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 23:19:08.361461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 23:19:08.361581 ==
7703 23:19:08.361694
7704 23:19:08.361807
7705 23:19:08.361911 TX Vref Scan disable
7706 23:19:08.365237 == TX Byte 0 ==
7707 23:19:08.368429 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7708 23:19:08.375195 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7709 23:19:08.375334 == TX Byte 1 ==
7710 23:19:08.378556 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7711 23:19:08.385002 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7712 23:19:08.385126 ==
7713 23:19:08.388316 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 23:19:08.391654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 23:19:08.391779 ==
7716 23:19:08.406285
7717 23:19:08.410049 TX Vref early break, caculate TX vref
7718 23:19:08.413120 TX Vref=16, minBit 7, minWin=21, winSum=365
7719 23:19:08.416678 TX Vref=18, minBit 8, minWin=22, winSum=378
7720 23:19:08.419725 TX Vref=20, minBit 1, minWin=23, winSum=386
7721 23:19:08.422780 TX Vref=22, minBit 1, minWin=24, winSum=399
7722 23:19:08.426250 TX Vref=24, minBit 7, minWin=24, winSum=410
7723 23:19:08.433050 TX Vref=26, minBit 2, minWin=25, winSum=413
7724 23:19:08.435933 TX Vref=28, minBit 2, minWin=25, winSum=415
7725 23:19:08.439432 TX Vref=30, minBit 4, minWin=24, winSum=412
7726 23:19:08.442560 TX Vref=32, minBit 4, minWin=24, winSum=408
7727 23:19:08.445685 TX Vref=34, minBit 4, minWin=24, winSum=398
7728 23:19:08.452788 TX Vref=36, minBit 0, minWin=23, winSum=385
7729 23:19:08.455688 [TxChooseVref] Worse bit 2, Min win 25, Win sum 415, Final Vref 28
7730 23:19:08.455830
7731 23:19:08.458862 Final TX Range 0 Vref 28
7732 23:19:08.459014
7733 23:19:08.459137 ==
7734 23:19:08.462124 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 23:19:08.465455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 23:19:08.468642 ==
7737 23:19:08.468733
7738 23:19:08.468811
7739 23:19:08.468871 TX Vref Scan disable
7740 23:19:08.476119 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7741 23:19:08.476216 == TX Byte 0 ==
7742 23:19:08.479175 u2DelayCellOfst[0]=14 cells (4 PI)
7743 23:19:08.482364 u2DelayCellOfst[1]=17 cells (5 PI)
7744 23:19:08.485448 u2DelayCellOfst[2]=14 cells (4 PI)
7745 23:19:08.489108 u2DelayCellOfst[3]=14 cells (4 PI)
7746 23:19:08.492171 u2DelayCellOfst[4]=10 cells (3 PI)
7747 23:19:08.495745 u2DelayCellOfst[5]=0 cells (0 PI)
7748 23:19:08.499262 u2DelayCellOfst[6]=21 cells (6 PI)
7749 23:19:08.501810 u2DelayCellOfst[7]=17 cells (5 PI)
7750 23:19:08.505930 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7751 23:19:08.508602 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7752 23:19:08.512149 == TX Byte 1 ==
7753 23:19:08.515224 u2DelayCellOfst[8]=0 cells (0 PI)
7754 23:19:08.518387 u2DelayCellOfst[9]=0 cells (0 PI)
7755 23:19:08.521708 u2DelayCellOfst[10]=3 cells (1 PI)
7756 23:19:08.524970 u2DelayCellOfst[11]=0 cells (0 PI)
7757 23:19:08.528401 u2DelayCellOfst[12]=7 cells (2 PI)
7758 23:19:08.531637 u2DelayCellOfst[13]=7 cells (2 PI)
7759 23:19:08.535058 u2DelayCellOfst[14]=14 cells (4 PI)
7760 23:19:08.535135 u2DelayCellOfst[15]=10 cells (3 PI)
7761 23:19:08.541619 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7762 23:19:08.544872 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7763 23:19:08.548048 DramC Write-DBI on
7764 23:19:08.548173 ==
7765 23:19:08.551344 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 23:19:08.554872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 23:19:08.554995 ==
7768 23:19:08.555111
7769 23:19:08.555224
7770 23:19:08.558367 TX Vref Scan disable
7771 23:19:08.561414 == TX Byte 0 ==
7772 23:19:08.564556 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7773 23:19:08.564678 == TX Byte 1 ==
7774 23:19:08.571231 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7775 23:19:08.571316 DramC Write-DBI off
7776 23:19:08.571390
7777 23:19:08.571454 [DATLAT]
7778 23:19:08.574776 Freq=1600, CH0 RK0
7779 23:19:08.574849
7780 23:19:08.577893 DATLAT Default: 0xf
7781 23:19:08.577967 0, 0xFFFF, sum = 0
7782 23:19:08.580999 1, 0xFFFF, sum = 0
7783 23:19:08.581074 2, 0xFFFF, sum = 0
7784 23:19:08.584440 3, 0xFFFF, sum = 0
7785 23:19:08.584514 4, 0xFFFF, sum = 0
7786 23:19:08.587859 5, 0xFFFF, sum = 0
7787 23:19:08.587936 6, 0xFFFF, sum = 0
7788 23:19:08.591381 7, 0xFFFF, sum = 0
7789 23:19:08.591461 8, 0xFFFF, sum = 0
7790 23:19:08.594306 9, 0xFFFF, sum = 0
7791 23:19:08.594392 10, 0xFFFF, sum = 0
7792 23:19:08.597601 11, 0xFFFF, sum = 0
7793 23:19:08.597687 12, 0xFFFF, sum = 0
7794 23:19:08.601367 13, 0xFFFF, sum = 0
7795 23:19:08.601453 14, 0x0, sum = 1
7796 23:19:08.604273 15, 0x0, sum = 2
7797 23:19:08.604359 16, 0x0, sum = 3
7798 23:19:08.607945 17, 0x0, sum = 4
7799 23:19:08.608030 best_step = 15
7800 23:19:08.608097
7801 23:19:08.608160 ==
7802 23:19:08.611188 Dram Type= 6, Freq= 0, CH_0, rank 0
7803 23:19:08.617456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7804 23:19:08.617539 ==
7805 23:19:08.617605 RX Vref Scan: 1
7806 23:19:08.617666
7807 23:19:08.621386 Set Vref Range= 24 -> 127
7808 23:19:08.621472
7809 23:19:08.624055 RX Vref 24 -> 127, step: 1
7810 23:19:08.624142
7811 23:19:08.624208 RX Delay 11 -> 252, step: 4
7812 23:19:08.627316
7813 23:19:08.627439 Set Vref, RX VrefLevel [Byte0]: 24
7814 23:19:08.630891 [Byte1]: 24
7815 23:19:08.635045
7816 23:19:08.635130 Set Vref, RX VrefLevel [Byte0]: 25
7817 23:19:08.638332 [Byte1]: 25
7818 23:19:08.643198
7819 23:19:08.643281 Set Vref, RX VrefLevel [Byte0]: 26
7820 23:19:08.645760 [Byte1]: 26
7821 23:19:08.650286
7822 23:19:08.650368 Set Vref, RX VrefLevel [Byte0]: 27
7823 23:19:08.653875 [Byte1]: 27
7824 23:19:08.657805
7825 23:19:08.657889 Set Vref, RX VrefLevel [Byte0]: 28
7826 23:19:08.661788 [Byte1]: 28
7827 23:19:08.665981
7828 23:19:08.666063 Set Vref, RX VrefLevel [Byte0]: 29
7829 23:19:08.669422 [Byte1]: 29
7830 23:19:08.673191
7831 23:19:08.673274 Set Vref, RX VrefLevel [Byte0]: 30
7832 23:19:08.676305 [Byte1]: 30
7833 23:19:08.680577
7834 23:19:08.684278 Set Vref, RX VrefLevel [Byte0]: 31
7835 23:19:08.687176 [Byte1]: 31
7836 23:19:08.687300
7837 23:19:08.690817 Set Vref, RX VrefLevel [Byte0]: 32
7838 23:19:08.694308 [Byte1]: 32
7839 23:19:08.694431
7840 23:19:08.697400 Set Vref, RX VrefLevel [Byte0]: 33
7841 23:19:08.700870 [Byte1]: 33
7842 23:19:08.704092
7843 23:19:08.704215 Set Vref, RX VrefLevel [Byte0]: 34
7844 23:19:08.706993 [Byte1]: 34
7845 23:19:08.711208
7846 23:19:08.711331 Set Vref, RX VrefLevel [Byte0]: 35
7847 23:19:08.714374 [Byte1]: 35
7848 23:19:08.718643
7849 23:19:08.718748 Set Vref, RX VrefLevel [Byte0]: 36
7850 23:19:08.722135 [Byte1]: 36
7851 23:19:08.726868
7852 23:19:08.726953 Set Vref, RX VrefLevel [Byte0]: 37
7853 23:19:08.730063 [Byte1]: 37
7854 23:19:08.734153
7855 23:19:08.734235 Set Vref, RX VrefLevel [Byte0]: 38
7856 23:19:08.737167 [Byte1]: 38
7857 23:19:08.741638
7858 23:19:08.741720 Set Vref, RX VrefLevel [Byte0]: 39
7859 23:19:08.745138 [Byte1]: 39
7860 23:19:08.749584
7861 23:19:08.749668 Set Vref, RX VrefLevel [Byte0]: 40
7862 23:19:08.752510 [Byte1]: 40
7863 23:19:08.756999
7864 23:19:08.757081 Set Vref, RX VrefLevel [Byte0]: 41
7865 23:19:08.760025 [Byte1]: 41
7866 23:19:08.764694
7867 23:19:08.764775 Set Vref, RX VrefLevel [Byte0]: 42
7868 23:19:08.767870 [Byte1]: 42
7869 23:19:08.772513
7870 23:19:08.772595 Set Vref, RX VrefLevel [Byte0]: 43
7871 23:19:08.775250 [Byte1]: 43
7872 23:19:08.780092
7873 23:19:08.780174 Set Vref, RX VrefLevel [Byte0]: 44
7874 23:19:08.782858 [Byte1]: 44
7875 23:19:08.787263
7876 23:19:08.787350 Set Vref, RX VrefLevel [Byte0]: 45
7877 23:19:08.790832 [Byte1]: 45
7878 23:19:08.795284
7879 23:19:08.795410 Set Vref, RX VrefLevel [Byte0]: 46
7880 23:19:08.798158 [Byte1]: 46
7881 23:19:08.802374
7882 23:19:08.802457 Set Vref, RX VrefLevel [Byte0]: 47
7883 23:19:08.805948 [Byte1]: 47
7884 23:19:08.810170
7885 23:19:08.810252 Set Vref, RX VrefLevel [Byte0]: 48
7886 23:19:08.813735 [Byte1]: 48
7887 23:19:08.818022
7888 23:19:08.818149 Set Vref, RX VrefLevel [Byte0]: 49
7889 23:19:08.821366 [Byte1]: 49
7890 23:19:08.825693
7891 23:19:08.825813 Set Vref, RX VrefLevel [Byte0]: 50
7892 23:19:08.829001 [Byte1]: 50
7893 23:19:08.833172
7894 23:19:08.833293 Set Vref, RX VrefLevel [Byte0]: 51
7895 23:19:08.836277 [Byte1]: 51
7896 23:19:08.840445
7897 23:19:08.840569 Set Vref, RX VrefLevel [Byte0]: 52
7898 23:19:08.844157 [Byte1]: 52
7899 23:19:08.848328
7900 23:19:08.848450 Set Vref, RX VrefLevel [Byte0]: 53
7901 23:19:08.851583 [Byte1]: 53
7902 23:19:08.855944
7903 23:19:08.856064 Set Vref, RX VrefLevel [Byte0]: 54
7904 23:19:08.858917 [Byte1]: 54
7905 23:19:08.863208
7906 23:19:08.863329 Set Vref, RX VrefLevel [Byte0]: 55
7907 23:19:08.866572 [Byte1]: 55
7908 23:19:08.870911
7909 23:19:08.871033 Set Vref, RX VrefLevel [Byte0]: 56
7910 23:19:08.874100 [Byte1]: 56
7911 23:19:08.878638
7912 23:19:08.878761 Set Vref, RX VrefLevel [Byte0]: 57
7913 23:19:08.882163 [Byte1]: 57
7914 23:19:08.886631
7915 23:19:08.886752 Set Vref, RX VrefLevel [Byte0]: 58
7916 23:19:08.889605 [Byte1]: 58
7917 23:19:08.893649
7918 23:19:08.893772 Set Vref, RX VrefLevel [Byte0]: 59
7919 23:19:08.897581 [Byte1]: 59
7920 23:19:08.901906
7921 23:19:08.902027 Set Vref, RX VrefLevel [Byte0]: 60
7922 23:19:08.904904 [Byte1]: 60
7923 23:19:08.909350
7924 23:19:08.909471 Set Vref, RX VrefLevel [Byte0]: 61
7925 23:19:08.912361 [Byte1]: 61
7926 23:19:08.916721
7927 23:19:08.916844 Set Vref, RX VrefLevel [Byte0]: 62
7928 23:19:08.920008 [Byte1]: 62
7929 23:19:08.924473
7930 23:19:08.924595 Set Vref, RX VrefLevel [Byte0]: 63
7931 23:19:08.927851 [Byte1]: 63
7932 23:19:08.932075
7933 23:19:08.932196 Set Vref, RX VrefLevel [Byte0]: 64
7934 23:19:08.935241 [Byte1]: 64
7935 23:19:08.939691
7936 23:19:08.939815 Set Vref, RX VrefLevel [Byte0]: 65
7937 23:19:08.943035 [Byte1]: 65
7938 23:19:08.947236
7939 23:19:08.947359 Set Vref, RX VrefLevel [Byte0]: 66
7940 23:19:08.950671 [Byte1]: 66
7941 23:19:08.954731
7942 23:19:08.954854 Set Vref, RX VrefLevel [Byte0]: 67
7943 23:19:08.958502 [Byte1]: 67
7944 23:19:08.962404
7945 23:19:08.962526 Set Vref, RX VrefLevel [Byte0]: 68
7946 23:19:08.965875 [Byte1]: 68
7947 23:19:08.969839
7948 23:19:08.969960 Set Vref, RX VrefLevel [Byte0]: 69
7949 23:19:08.973101 [Byte1]: 69
7950 23:19:08.977894
7951 23:19:08.978017 Set Vref, RX VrefLevel [Byte0]: 70
7952 23:19:08.980691 [Byte1]: 70
7953 23:19:08.985362
7954 23:19:08.985483 Set Vref, RX VrefLevel [Byte0]: 71
7955 23:19:08.988492 [Byte1]: 71
7956 23:19:08.993109
7957 23:19:08.993228 Set Vref, RX VrefLevel [Byte0]: 72
7958 23:19:08.996363 [Byte1]: 72
7959 23:19:09.000500
7960 23:19:09.000618 Set Vref, RX VrefLevel [Byte0]: 73
7961 23:19:09.003834 [Byte1]: 73
7962 23:19:09.007893
7963 23:19:09.008014 Set Vref, RX VrefLevel [Byte0]: 74
7964 23:19:09.011217 [Byte1]: 74
7965 23:19:09.015886
7966 23:19:09.016007 Final RX Vref Byte 0 = 56 to rank0
7967 23:19:09.018979 Final RX Vref Byte 1 = 60 to rank0
7968 23:19:09.022327 Final RX Vref Byte 0 = 56 to rank1
7969 23:19:09.025926 Final RX Vref Byte 1 = 60 to rank1==
7970 23:19:09.028951 Dram Type= 6, Freq= 0, CH_0, rank 0
7971 23:19:09.035561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7972 23:19:09.035684 ==
7973 23:19:09.035798 DQS Delay:
7974 23:19:09.038401 DQS0 = 0, DQS1 = 0
7975 23:19:09.038519 DQM Delay:
7976 23:19:09.041974 DQM0 = 128, DQM1 = 123
7977 23:19:09.042096 DQ Delay:
7978 23:19:09.045178 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7979 23:19:09.048236 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =134
7980 23:19:09.052095 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7981 23:19:09.055147 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
7982 23:19:09.055266
7983 23:19:09.055387
7984 23:19:09.055494
7985 23:19:09.058755 [DramC_TX_OE_Calibration] TA2
7986 23:19:09.061496 Original DQ_B0 (3 6) =30, OEN = 27
7987 23:19:09.065109 Original DQ_B1 (3 6) =30, OEN = 27
7988 23:19:09.068315 24, 0x0, End_B0=24 End_B1=24
7989 23:19:09.071615 25, 0x0, End_B0=25 End_B1=25
7990 23:19:09.071743 26, 0x0, End_B0=26 End_B1=26
7991 23:19:09.074498 27, 0x0, End_B0=27 End_B1=27
7992 23:19:09.077721 28, 0x0, End_B0=28 End_B1=28
7993 23:19:09.081495 29, 0x0, End_B0=29 End_B1=29
7994 23:19:09.084743 30, 0x0, End_B0=30 End_B1=30
7995 23:19:09.084868 31, 0x4141, End_B0=30 End_B1=30
7996 23:19:09.087968 Byte0 end_step=30 best_step=27
7997 23:19:09.091047 Byte1 end_step=30 best_step=27
7998 23:19:09.094669 Byte0 TX OE(2T, 0.5T) = (3, 3)
7999 23:19:09.097460 Byte1 TX OE(2T, 0.5T) = (3, 3)
8000 23:19:09.097583
8001 23:19:09.097695
8002 23:19:09.104245 [DQSOSCAuto] RK0, (LSB)MR18= 0x1614, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8003 23:19:09.107449 CH0 RK0: MR19=303, MR18=1614
8004 23:19:09.113870 CH0_RK0: MR19=0x303, MR18=0x1614, DQSOSC=398, MR23=63, INC=23, DEC=15
8005 23:19:09.113995
8006 23:19:09.117288 ----->DramcWriteLeveling(PI) begin...
8007 23:19:09.117413 ==
8008 23:19:09.120447 Dram Type= 6, Freq= 0, CH_0, rank 1
8009 23:19:09.123786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 23:19:09.127392 ==
8011 23:19:09.127514 Write leveling (Byte 0): 37 => 37
8012 23:19:09.130982 Write leveling (Byte 1): 25 => 25
8013 23:19:09.133629 DramcWriteLeveling(PI) end<-----
8014 23:19:09.133716
8015 23:19:09.133786 ==
8016 23:19:09.137171 Dram Type= 6, Freq= 0, CH_0, rank 1
8017 23:19:09.143663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8018 23:19:09.143746 ==
8019 23:19:09.147011 [Gating] SW mode calibration
8020 23:19:09.153464 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8021 23:19:09.157202 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8022 23:19:09.163755 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 23:19:09.166619 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 23:19:09.170011 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 23:19:09.176200 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8026 23:19:09.179824 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8027 23:19:09.182913 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 23:19:09.189997 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 23:19:09.192869 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 23:19:09.196438 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 23:19:09.202741 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8032 23:19:09.205987 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8033 23:19:09.209257 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8034 23:19:09.215914 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8035 23:19:09.219017 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8036 23:19:09.222283 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 23:19:09.229115 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 23:19:09.232382 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 23:19:09.236039 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8040 23:19:09.242193 1 6 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8041 23:19:09.245383 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8042 23:19:09.249173 1 6 16 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
8043 23:19:09.255576 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8044 23:19:09.258801 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 23:19:09.262213 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 23:19:09.268631 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 23:19:09.271867 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8048 23:19:09.275259 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8049 23:19:09.281935 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8050 23:19:09.285227 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8051 23:19:09.288427 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8052 23:19:09.295050 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8053 23:19:09.298385 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 23:19:09.301830 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 23:19:09.308343 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 23:19:09.311636 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 23:19:09.314636 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 23:19:09.321218 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 23:19:09.324564 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 23:19:09.327988 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 23:19:09.334565 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 23:19:09.337529 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 23:19:09.341335 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 23:19:09.347313 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8065 23:19:09.350617 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8066 23:19:09.354551 Total UI for P1: 0, mck2ui 16
8067 23:19:09.357324 best dqsien dly found for B0: ( 1, 9, 8)
8068 23:19:09.360672 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8069 23:19:09.367663 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8070 23:19:09.370416 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 23:19:09.373694 Total UI for P1: 0, mck2ui 16
8072 23:19:09.376990 best dqsien dly found for B1: ( 1, 9, 18)
8073 23:19:09.380288 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8074 23:19:09.383728 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8075 23:19:09.383811
8076 23:19:09.387124 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8077 23:19:09.393503 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8078 23:19:09.393609 [Gating] SW calibration Done
8079 23:19:09.393676 ==
8080 23:19:09.397052 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 23:19:09.403835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 23:19:09.403919 ==
8083 23:19:09.403985 RX Vref Scan: 0
8084 23:19:09.404046
8085 23:19:09.406591 RX Vref 0 -> 0, step: 1
8086 23:19:09.406674
8087 23:19:09.410123 RX Delay 0 -> 252, step: 8
8088 23:19:09.413191 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
8089 23:19:09.416720 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
8090 23:19:09.419619 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
8091 23:19:09.426610 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8092 23:19:09.429945 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8093 23:19:09.433248 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8094 23:19:09.436422 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8095 23:19:09.439776 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
8096 23:19:09.446586 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
8097 23:19:09.449261 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
8098 23:19:09.452900 iDelay=192, Bit 10, Center 127 (72 ~ 183) 112
8099 23:19:09.456348 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
8100 23:19:09.462542 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
8101 23:19:09.465857 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
8102 23:19:09.469240 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
8103 23:19:09.472455 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
8104 23:19:09.472576 ==
8105 23:19:09.475767 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 23:19:09.482472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 23:19:09.482596 ==
8108 23:19:09.482709 DQS Delay:
8109 23:19:09.482821 DQS0 = 0, DQS1 = 0
8110 23:19:09.486120 DQM Delay:
8111 23:19:09.486240 DQM0 = 131, DQM1 = 127
8112 23:19:09.488700 DQ Delay:
8113 23:19:09.492336 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8114 23:19:09.495625 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8115 23:19:09.499086 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
8116 23:19:09.501863 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8117 23:19:09.501982
8118 23:19:09.502093
8119 23:19:09.502202 ==
8120 23:19:09.505536 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 23:19:09.508654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 23:19:09.511978 ==
8123 23:19:09.512101
8124 23:19:09.512213
8125 23:19:09.512323 TX Vref Scan disable
8126 23:19:09.515283 == TX Byte 0 ==
8127 23:19:09.518480 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8128 23:19:09.522054 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8129 23:19:09.525052 == TX Byte 1 ==
8130 23:19:09.528804 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8131 23:19:09.535015 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8132 23:19:09.535097 ==
8133 23:19:09.538302 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 23:19:09.541760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 23:19:09.541860 ==
8136 23:19:09.556628
8137 23:19:09.559660 TX Vref early break, caculate TX vref
8138 23:19:09.563442 TX Vref=16, minBit 1, minWin=23, winSum=381
8139 23:19:09.566696 TX Vref=18, minBit 8, minWin=23, winSum=386
8140 23:19:09.570058 TX Vref=20, minBit 0, minWin=24, winSum=396
8141 23:19:09.573125 TX Vref=22, minBit 2, minWin=24, winSum=401
8142 23:19:09.576569 TX Vref=24, minBit 3, minWin=25, winSum=409
8143 23:19:09.582983 TX Vref=26, minBit 8, minWin=25, winSum=415
8144 23:19:09.586338 TX Vref=28, minBit 10, minWin=25, winSum=415
8145 23:19:09.589317 TX Vref=30, minBit 0, minWin=25, winSum=409
8146 23:19:09.592728 TX Vref=32, minBit 0, minWin=25, winSum=406
8147 23:19:09.595906 TX Vref=34, minBit 1, minWin=24, winSum=398
8148 23:19:09.602953 TX Vref=36, minBit 11, minWin=23, winSum=384
8149 23:19:09.605759 [TxChooseVref] Worse bit 8, Min win 25, Win sum 415, Final Vref 26
8150 23:19:09.605842
8151 23:19:09.608967 Final TX Range 0 Vref 26
8152 23:19:09.609050
8153 23:19:09.609115 ==
8154 23:19:09.613081 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 23:19:09.618793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 23:19:09.618876 ==
8157 23:19:09.618944
8158 23:19:09.619008
8159 23:19:09.619068 TX Vref Scan disable
8160 23:19:09.626626 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8161 23:19:09.626709 == TX Byte 0 ==
8162 23:19:09.629761 u2DelayCellOfst[0]=17 cells (5 PI)
8163 23:19:09.632728 u2DelayCellOfst[1]=17 cells (5 PI)
8164 23:19:09.636481 u2DelayCellOfst[2]=10 cells (3 PI)
8165 23:19:09.639640 u2DelayCellOfst[3]=14 cells (4 PI)
8166 23:19:09.642753 u2DelayCellOfst[4]=7 cells (2 PI)
8167 23:19:09.645877 u2DelayCellOfst[5]=0 cells (0 PI)
8168 23:19:09.649648 u2DelayCellOfst[6]=17 cells (5 PI)
8169 23:19:09.652826 u2DelayCellOfst[7]=21 cells (6 PI)
8170 23:19:09.656226 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8171 23:19:09.659270 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8172 23:19:09.662844 == TX Byte 1 ==
8173 23:19:09.665946 u2DelayCellOfst[8]=3 cells (1 PI)
8174 23:19:09.669536 u2DelayCellOfst[9]=0 cells (0 PI)
8175 23:19:09.672716 u2DelayCellOfst[10]=7 cells (2 PI)
8176 23:19:09.672802 u2DelayCellOfst[11]=7 cells (2 PI)
8177 23:19:09.675836 u2DelayCellOfst[12]=10 cells (3 PI)
8178 23:19:09.679078 u2DelayCellOfst[13]=10 cells (3 PI)
8179 23:19:09.682817 u2DelayCellOfst[14]=17 cells (5 PI)
8180 23:19:09.686486 u2DelayCellOfst[15]=14 cells (4 PI)
8181 23:19:09.692760 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8182 23:19:09.695767 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8183 23:19:09.695850 DramC Write-DBI on
8184 23:19:09.699059 ==
8185 23:19:09.702335 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 23:19:09.705455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 23:19:09.705538 ==
8188 23:19:09.705603
8189 23:19:09.705662
8190 23:19:09.708982 TX Vref Scan disable
8191 23:19:09.709064 == TX Byte 0 ==
8192 23:19:09.715671 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8193 23:19:09.715754 == TX Byte 1 ==
8194 23:19:09.718710 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8195 23:19:09.721998 DramC Write-DBI off
8196 23:19:09.722107
8197 23:19:09.722233 [DATLAT]
8198 23:19:09.725075 Freq=1600, CH0 RK1
8199 23:19:09.725157
8200 23:19:09.725222 DATLAT Default: 0xf
8201 23:19:09.728614 0, 0xFFFF, sum = 0
8202 23:19:09.728701 1, 0xFFFF, sum = 0
8203 23:19:09.731817 2, 0xFFFF, sum = 0
8204 23:19:09.731901 3, 0xFFFF, sum = 0
8205 23:19:09.735331 4, 0xFFFF, sum = 0
8206 23:19:09.738525 5, 0xFFFF, sum = 0
8207 23:19:09.738609 6, 0xFFFF, sum = 0
8208 23:19:09.741874 7, 0xFFFF, sum = 0
8209 23:19:09.741957 8, 0xFFFF, sum = 0
8210 23:19:09.745732 9, 0xFFFF, sum = 0
8211 23:19:09.745815 10, 0xFFFF, sum = 0
8212 23:19:09.748438 11, 0xFFFF, sum = 0
8213 23:19:09.748522 12, 0xFFFF, sum = 0
8214 23:19:09.752169 13, 0xFFFF, sum = 0
8215 23:19:09.752252 14, 0x0, sum = 1
8216 23:19:09.755157 15, 0x0, sum = 2
8217 23:19:09.755241 16, 0x0, sum = 3
8218 23:19:09.758422 17, 0x0, sum = 4
8219 23:19:09.758506 best_step = 15
8220 23:19:09.758571
8221 23:19:09.758631 ==
8222 23:19:09.761821 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 23:19:09.768061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 23:19:09.768144 ==
8225 23:19:09.768209 RX Vref Scan: 0
8226 23:19:09.768271
8227 23:19:09.771316 RX Vref 0 -> 0, step: 1
8228 23:19:09.771423
8229 23:19:09.774649 RX Delay 19 -> 252, step: 4
8230 23:19:09.778226 iDelay=187, Bit 0, Center 126 (75 ~ 178) 104
8231 23:19:09.781780 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8232 23:19:09.784476 iDelay=187, Bit 2, Center 124 (75 ~ 174) 100
8233 23:19:09.791090 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8234 23:19:09.794786 iDelay=187, Bit 4, Center 130 (83 ~ 178) 96
8235 23:19:09.797515 iDelay=187, Bit 5, Center 118 (63 ~ 174) 112
8236 23:19:09.800735 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8237 23:19:09.804423 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8238 23:19:09.810719 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8239 23:19:09.814315 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8240 23:19:09.817207 iDelay=187, Bit 10, Center 124 (71 ~ 178) 108
8241 23:19:09.820995 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8242 23:19:09.827089 iDelay=187, Bit 12, Center 128 (75 ~ 182) 108
8243 23:19:09.830454 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8244 23:19:09.833775 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8245 23:19:09.837103 iDelay=187, Bit 15, Center 130 (75 ~ 186) 112
8246 23:19:09.837175 ==
8247 23:19:09.840701 Dram Type= 6, Freq= 0, CH_0, rank 1
8248 23:19:09.847426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8249 23:19:09.847507 ==
8250 23:19:09.847578 DQS Delay:
8251 23:19:09.850453 DQS0 = 0, DQS1 = 0
8252 23:19:09.850540 DQM Delay:
8253 23:19:09.850604 DQM0 = 128, DQM1 = 123
8254 23:19:09.853754 DQ Delay:
8255 23:19:09.856664 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8256 23:19:09.860499 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
8257 23:19:09.863802 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8258 23:19:09.866845 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =130
8259 23:19:09.866926
8260 23:19:09.866991
8261 23:19:09.867051
8262 23:19:09.870236 [DramC_TX_OE_Calibration] TA2
8263 23:19:09.873337 Original DQ_B0 (3 6) =30, OEN = 27
8264 23:19:09.876472 Original DQ_B1 (3 6) =30, OEN = 27
8265 23:19:09.879829 24, 0x0, End_B0=24 End_B1=24
8266 23:19:09.879912 25, 0x0, End_B0=25 End_B1=25
8267 23:19:09.883069 26, 0x0, End_B0=26 End_B1=26
8268 23:19:09.886386 27, 0x0, End_B0=27 End_B1=27
8269 23:19:09.890034 28, 0x0, End_B0=28 End_B1=28
8270 23:19:09.893022 29, 0x0, End_B0=29 End_B1=29
8271 23:19:09.893104 30, 0x0, End_B0=30 End_B1=30
8272 23:19:09.896177 31, 0x4141, End_B0=30 End_B1=30
8273 23:19:09.899698 Byte0 end_step=30 best_step=27
8274 23:19:09.902754 Byte1 end_step=30 best_step=27
8275 23:19:09.906442 Byte0 TX OE(2T, 0.5T) = (3, 3)
8276 23:19:09.909679 Byte1 TX OE(2T, 0.5T) = (3, 3)
8277 23:19:09.909762
8278 23:19:09.909827
8279 23:19:09.916186 [DQSOSCAuto] RK1, (LSB)MR18= 0x1110, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
8280 23:19:09.919868 CH0 RK1: MR19=303, MR18=1110
8281 23:19:09.926040 CH0_RK1: MR19=0x303, MR18=0x1110, DQSOSC=401, MR23=63, INC=22, DEC=15
8282 23:19:09.929613 [RxdqsGatingPostProcess] freq 1600
8283 23:19:09.936072 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8284 23:19:09.936155 best DQS0 dly(2T, 0.5T) = (1, 1)
8285 23:19:09.939263 best DQS1 dly(2T, 0.5T) = (1, 1)
8286 23:19:09.942729 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8287 23:19:09.945623 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8288 23:19:09.949419 best DQS0 dly(2T, 0.5T) = (1, 1)
8289 23:19:09.952622 best DQS1 dly(2T, 0.5T) = (1, 1)
8290 23:19:09.955721 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8291 23:19:09.958940 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8292 23:19:09.962131 Pre-setting of DQS Precalculation
8293 23:19:09.965564 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8294 23:19:09.969134 ==
8295 23:19:09.969217 Dram Type= 6, Freq= 0, CH_1, rank 0
8296 23:19:09.976095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 23:19:09.976177 ==
8298 23:19:09.978965 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8299 23:19:09.985370 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8300 23:19:09.988517 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8301 23:19:09.995244 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8302 23:19:10.003091 [CA 0] Center 42 (13~72) winsize 60
8303 23:19:10.006771 [CA 1] Center 42 (12~72) winsize 61
8304 23:19:10.010227 [CA 2] Center 38 (9~68) winsize 60
8305 23:19:10.013437 [CA 3] Center 37 (8~67) winsize 60
8306 23:19:10.016468 [CA 4] Center 38 (9~68) winsize 60
8307 23:19:10.019905 [CA 5] Center 37 (7~67) winsize 61
8308 23:19:10.020012
8309 23:19:10.023059 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8310 23:19:10.023141
8311 23:19:10.030114 [CATrainingPosCal] consider 1 rank data
8312 23:19:10.030197 u2DelayCellTimex100 = 275/100 ps
8313 23:19:10.036136 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8314 23:19:10.039376 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8315 23:19:10.042596 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8316 23:19:10.046343 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8317 23:19:10.049463 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8318 23:19:10.052800 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8319 23:19:10.052915
8320 23:19:10.055997 CA PerBit enable=1, Macro0, CA PI delay=37
8321 23:19:10.056096
8322 23:19:10.058927 [CBTSetCACLKResult] CA Dly = 37
8323 23:19:10.062620 CS Dly: 7 (0~38)
8324 23:19:10.065790 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8325 23:19:10.069461 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8326 23:19:10.069543 ==
8327 23:19:10.072484 Dram Type= 6, Freq= 0, CH_1, rank 1
8328 23:19:10.078997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 23:19:10.079080 ==
8330 23:19:10.082013 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8331 23:19:10.088653 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8332 23:19:10.092566 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8333 23:19:10.098638 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8334 23:19:10.106410 [CA 0] Center 42 (12~72) winsize 61
8335 23:19:10.109943 [CA 1] Center 42 (13~72) winsize 60
8336 23:19:10.113214 [CA 2] Center 38 (9~67) winsize 59
8337 23:19:10.116351 [CA 3] Center 36 (7~66) winsize 60
8338 23:19:10.119506 [CA 4] Center 37 (8~67) winsize 60
8339 23:19:10.122721 [CA 5] Center 36 (7~66) winsize 60
8340 23:19:10.122804
8341 23:19:10.126069 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8342 23:19:10.126151
8343 23:19:10.129468 [CATrainingPosCal] consider 2 rank data
8344 23:19:10.132589 u2DelayCellTimex100 = 275/100 ps
8345 23:19:10.139498 CA0 delay=42 (13~72),Diff = 6 PI (21 cell)
8346 23:19:10.142321 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8347 23:19:10.145747 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8348 23:19:10.149111 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8349 23:19:10.152326 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8350 23:19:10.155549 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8351 23:19:10.155632
8352 23:19:10.158808 CA PerBit enable=1, Macro0, CA PI delay=36
8353 23:19:10.158890
8354 23:19:10.162105 [CBTSetCACLKResult] CA Dly = 36
8355 23:19:10.165405 CS Dly: 9 (0~42)
8356 23:19:10.168989 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8357 23:19:10.171995 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8358 23:19:10.172077
8359 23:19:10.175264 ----->DramcWriteLeveling(PI) begin...
8360 23:19:10.175381 ==
8361 23:19:10.178751 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 23:19:10.185215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 23:19:10.185297 ==
8364 23:19:10.188345 Write leveling (Byte 0): 26 => 26
8365 23:19:10.192159 Write leveling (Byte 1): 27 => 27
8366 23:19:10.194961 DramcWriteLeveling(PI) end<-----
8367 23:19:10.195043
8368 23:19:10.195108 ==
8369 23:19:10.198205 Dram Type= 6, Freq= 0, CH_1, rank 0
8370 23:19:10.201571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8371 23:19:10.201654 ==
8372 23:19:10.204824 [Gating] SW mode calibration
8373 23:19:10.211798 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8374 23:19:10.218203 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8375 23:19:10.221289 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 23:19:10.224493 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 23:19:10.231653 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
8378 23:19:10.234901 1 4 12 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
8379 23:19:10.237713 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 23:19:10.244449 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 23:19:10.247679 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 23:19:10.251157 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 23:19:10.257554 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 23:19:10.261143 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 23:19:10.264530 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 23:19:10.270947 1 5 12 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (1 0)
8387 23:19:10.274101 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8388 23:19:10.277577 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 23:19:10.284175 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 23:19:10.287299 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 23:19:10.290368 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 23:19:10.297168 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 23:19:10.300242 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8394 23:19:10.303689 1 6 12 | B1->B0 | 2727 4141 | 0 0 | (0 0) (0 0)
8395 23:19:10.310737 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 23:19:10.314272 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 23:19:10.317485 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 23:19:10.323719 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 23:19:10.327136 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 23:19:10.330269 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 23:19:10.336852 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 23:19:10.339984 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8403 23:19:10.343523 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8404 23:19:10.350040 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 23:19:10.353396 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 23:19:10.356332 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 23:19:10.363519 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 23:19:10.366661 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 23:19:10.369986 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 23:19:10.376762 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 23:19:10.379530 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 23:19:10.383102 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 23:19:10.389404 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 23:19:10.392783 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 23:19:10.396447 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 23:19:10.399624 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 23:19:10.406364 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8418 23:19:10.409590 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8419 23:19:10.413058 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8420 23:19:10.416342 Total UI for P1: 0, mck2ui 16
8421 23:19:10.419560 best dqsien dly found for B0: ( 1, 9, 10)
8422 23:19:10.426178 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 23:19:10.429300 Total UI for P1: 0, mck2ui 16
8424 23:19:10.432770 best dqsien dly found for B1: ( 1, 9, 14)
8425 23:19:10.435868 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8426 23:19:10.439258 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8427 23:19:10.439376
8428 23:19:10.442428 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8429 23:19:10.446021 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8430 23:19:10.449363 [Gating] SW calibration Done
8431 23:19:10.449498 ==
8432 23:19:10.452289 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 23:19:10.455513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8434 23:19:10.455636 ==
8435 23:19:10.458954 RX Vref Scan: 0
8436 23:19:10.459079
8437 23:19:10.462309 RX Vref 0 -> 0, step: 1
8438 23:19:10.462430
8439 23:19:10.462542 RX Delay 0 -> 252, step: 8
8440 23:19:10.468514 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8441 23:19:10.471917 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8442 23:19:10.475698 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8443 23:19:10.478868 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8444 23:19:10.482574 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8445 23:19:10.488665 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8446 23:19:10.491543 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8447 23:19:10.495170 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8448 23:19:10.498610 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8449 23:19:10.501921 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8450 23:19:10.508443 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8451 23:19:10.511631 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8452 23:19:10.515068 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8453 23:19:10.518032 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8454 23:19:10.524731 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8455 23:19:10.527895 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8456 23:19:10.527995 ==
8457 23:19:10.531132 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 23:19:10.534667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 23:19:10.534751 ==
8460 23:19:10.537720 DQS Delay:
8461 23:19:10.537802 DQS0 = 0, DQS1 = 0
8462 23:19:10.540998 DQM Delay:
8463 23:19:10.541081 DQM0 = 134, DQM1 = 129
8464 23:19:10.541146 DQ Delay:
8465 23:19:10.544213 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8466 23:19:10.551051 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8467 23:19:10.554088 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =123
8468 23:19:10.557413 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8469 23:19:10.557496
8470 23:19:10.557561
8471 23:19:10.557686 ==
8472 23:19:10.560365 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 23:19:10.563817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 23:19:10.563899 ==
8475 23:19:10.563963
8476 23:19:10.564023
8477 23:19:10.567313 TX Vref Scan disable
8478 23:19:10.570657 == TX Byte 0 ==
8479 23:19:10.573752 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8480 23:19:10.577222 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8481 23:19:10.580385 == TX Byte 1 ==
8482 23:19:10.583620 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8483 23:19:10.587212 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8484 23:19:10.587328 ==
8485 23:19:10.590346 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 23:19:10.596742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 23:19:10.596845 ==
8488 23:19:10.609529
8489 23:19:10.612879 TX Vref early break, caculate TX vref
8490 23:19:10.616021 TX Vref=16, minBit 8, minWin=21, winSum=366
8491 23:19:10.619663 TX Vref=18, minBit 9, minWin=21, winSum=379
8492 23:19:10.622394 TX Vref=20, minBit 8, minWin=23, winSum=384
8493 23:19:10.625844 TX Vref=22, minBit 8, minWin=23, winSum=395
8494 23:19:10.628975 TX Vref=24, minBit 9, minWin=24, winSum=408
8495 23:19:10.635773 TX Vref=26, minBit 3, minWin=25, winSum=415
8496 23:19:10.639492 TX Vref=28, minBit 9, minWin=24, winSum=414
8497 23:19:10.642759 TX Vref=30, minBit 0, minWin=25, winSum=415
8498 23:19:10.645653 TX Vref=32, minBit 9, minWin=24, winSum=406
8499 23:19:10.649316 TX Vref=34, minBit 0, minWin=24, winSum=398
8500 23:19:10.652546 TX Vref=36, minBit 0, minWin=23, winSum=384
8501 23:19:10.658708 [TxChooseVref] Worse bit 3, Min win 25, Win sum 415, Final Vref 26
8502 23:19:10.658792
8503 23:19:10.662232 Final TX Range 0 Vref 26
8504 23:19:10.662316
8505 23:19:10.662381 ==
8506 23:19:10.665420 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 23:19:10.668525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 23:19:10.668608 ==
8509 23:19:10.672368
8510 23:19:10.672450
8511 23:19:10.672515 TX Vref Scan disable
8512 23:19:10.678650 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8513 23:19:10.678733 == TX Byte 0 ==
8514 23:19:10.681749 u2DelayCellOfst[0]=14 cells (4 PI)
8515 23:19:10.685011 u2DelayCellOfst[1]=10 cells (3 PI)
8516 23:19:10.688969 u2DelayCellOfst[2]=0 cells (0 PI)
8517 23:19:10.691604 u2DelayCellOfst[3]=7 cells (2 PI)
8518 23:19:10.695116 u2DelayCellOfst[4]=10 cells (3 PI)
8519 23:19:10.698230 u2DelayCellOfst[5]=14 cells (4 PI)
8520 23:19:10.702024 u2DelayCellOfst[6]=14 cells (4 PI)
8521 23:19:10.704981 u2DelayCellOfst[7]=3 cells (1 PI)
8522 23:19:10.708575 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8523 23:19:10.711552 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8524 23:19:10.714973 == TX Byte 1 ==
8525 23:19:10.718143 u2DelayCellOfst[8]=0 cells (0 PI)
8526 23:19:10.721341 u2DelayCellOfst[9]=3 cells (1 PI)
8527 23:19:10.724806 u2DelayCellOfst[10]=14 cells (4 PI)
8528 23:19:10.728306 u2DelayCellOfst[11]=7 cells (2 PI)
8529 23:19:10.731276 u2DelayCellOfst[12]=14 cells (4 PI)
8530 23:19:10.734550 u2DelayCellOfst[13]=14 cells (4 PI)
8531 23:19:10.734638 u2DelayCellOfst[14]=17 cells (5 PI)
8532 23:19:10.737911 u2DelayCellOfst[15]=17 cells (5 PI)
8533 23:19:10.744473 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8534 23:19:10.747826 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8535 23:19:10.751288 DramC Write-DBI on
8536 23:19:10.751395 ==
8537 23:19:10.754491 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 23:19:10.758184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 23:19:10.758267 ==
8540 23:19:10.758333
8541 23:19:10.758395
8542 23:19:10.760866 TX Vref Scan disable
8543 23:19:10.760948 == TX Byte 0 ==
8544 23:19:10.767807 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8545 23:19:10.767914 == TX Byte 1 ==
8546 23:19:10.771118 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8547 23:19:10.773960 DramC Write-DBI off
8548 23:19:10.774034
8549 23:19:10.774095 [DATLAT]
8550 23:19:10.777621 Freq=1600, CH1 RK0
8551 23:19:10.777698
8552 23:19:10.777759 DATLAT Default: 0xf
8553 23:19:10.780825 0, 0xFFFF, sum = 0
8554 23:19:10.780899 1, 0xFFFF, sum = 0
8555 23:19:10.784244 2, 0xFFFF, sum = 0
8556 23:19:10.787139 3, 0xFFFF, sum = 0
8557 23:19:10.787218 4, 0xFFFF, sum = 0
8558 23:19:10.790864 5, 0xFFFF, sum = 0
8559 23:19:10.790946 6, 0xFFFF, sum = 0
8560 23:19:10.794285 7, 0xFFFF, sum = 0
8561 23:19:10.794363 8, 0xFFFF, sum = 0
8562 23:19:10.797185 9, 0xFFFF, sum = 0
8563 23:19:10.797263 10, 0xFFFF, sum = 0
8564 23:19:10.800621 11, 0xFFFF, sum = 0
8565 23:19:10.800695 12, 0xFFFF, sum = 0
8566 23:19:10.803897 13, 0xFFFF, sum = 0
8567 23:19:10.804021 14, 0x0, sum = 1
8568 23:19:10.807048 15, 0x0, sum = 2
8569 23:19:10.807127 16, 0x0, sum = 3
8570 23:19:10.810599 17, 0x0, sum = 4
8571 23:19:10.810714 best_step = 15
8572 23:19:10.810792
8573 23:19:10.810852 ==
8574 23:19:10.813711 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 23:19:10.820001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 23:19:10.820088 ==
8577 23:19:10.820155 RX Vref Scan: 1
8578 23:19:10.820216
8579 23:19:10.823576 Set Vref Range= 24 -> 127
8580 23:19:10.823698
8581 23:19:10.826975 RX Vref 24 -> 127, step: 1
8582 23:19:10.827073
8583 23:19:10.827153 RX Delay 11 -> 252, step: 4
8584 23:19:10.829890
8585 23:19:10.829972 Set Vref, RX VrefLevel [Byte0]: 24
8586 23:19:10.833188 [Byte1]: 24
8587 23:19:10.837409
8588 23:19:10.837494 Set Vref, RX VrefLevel [Byte0]: 25
8589 23:19:10.841026 [Byte1]: 25
8590 23:19:10.845058
8591 23:19:10.845156 Set Vref, RX VrefLevel [Byte0]: 26
8592 23:19:10.848277 [Byte1]: 26
8593 23:19:10.852586
8594 23:19:10.852668 Set Vref, RX VrefLevel [Byte0]: 27
8595 23:19:10.855968 [Byte1]: 27
8596 23:19:10.860207
8597 23:19:10.860315 Set Vref, RX VrefLevel [Byte0]: 28
8598 23:19:10.863878 [Byte1]: 28
8599 23:19:10.867877
8600 23:19:10.867975 Set Vref, RX VrefLevel [Byte0]: 29
8601 23:19:10.871082 [Byte1]: 29
8602 23:19:10.875944
8603 23:19:10.876026 Set Vref, RX VrefLevel [Byte0]: 30
8604 23:19:10.878836 [Byte1]: 30
8605 23:19:10.883336
8606 23:19:10.883431 Set Vref, RX VrefLevel [Byte0]: 31
8607 23:19:10.886727 [Byte1]: 31
8608 23:19:10.890815
8609 23:19:10.890927 Set Vref, RX VrefLevel [Byte0]: 32
8610 23:19:10.894332 [Byte1]: 32
8611 23:19:10.898834
8612 23:19:10.898918 Set Vref, RX VrefLevel [Byte0]: 33
8613 23:19:10.901852 [Byte1]: 33
8614 23:19:10.906221
8615 23:19:10.906305 Set Vref, RX VrefLevel [Byte0]: 34
8616 23:19:10.909184 [Byte1]: 34
8617 23:19:10.913406
8618 23:19:10.913491 Set Vref, RX VrefLevel [Byte0]: 35
8619 23:19:10.916893 [Byte1]: 35
8620 23:19:10.921100
8621 23:19:10.921185 Set Vref, RX VrefLevel [Byte0]: 36
8622 23:19:10.924403 [Byte1]: 36
8623 23:19:10.928961
8624 23:19:10.929046 Set Vref, RX VrefLevel [Byte0]: 37
8625 23:19:10.931873 [Byte1]: 37
8626 23:19:10.936296
8627 23:19:10.936381 Set Vref, RX VrefLevel [Byte0]: 38
8628 23:19:10.939555 [Byte1]: 38
8629 23:19:10.944509
8630 23:19:10.944620 Set Vref, RX VrefLevel [Byte0]: 39
8631 23:19:10.947203 [Byte1]: 39
8632 23:19:10.951965
8633 23:19:10.952078 Set Vref, RX VrefLevel [Byte0]: 40
8634 23:19:10.955140 [Byte1]: 40
8635 23:19:10.959641
8636 23:19:10.959751 Set Vref, RX VrefLevel [Byte0]: 41
8637 23:19:10.962645 [Byte1]: 41
8638 23:19:10.967107
8639 23:19:10.967218 Set Vref, RX VrefLevel [Byte0]: 42
8640 23:19:10.970609 [Byte1]: 42
8641 23:19:10.974658
8642 23:19:10.974747 Set Vref, RX VrefLevel [Byte0]: 43
8643 23:19:10.977941 [Byte1]: 43
8644 23:19:10.982124
8645 23:19:10.982208 Set Vref, RX VrefLevel [Byte0]: 44
8646 23:19:10.985677 [Byte1]: 44
8647 23:19:10.989714
8648 23:19:10.989798 Set Vref, RX VrefLevel [Byte0]: 45
8649 23:19:10.993256 [Byte1]: 45
8650 23:19:10.997678
8651 23:19:10.997802 Set Vref, RX VrefLevel [Byte0]: 46
8652 23:19:11.000774 [Byte1]: 46
8653 23:19:11.005371
8654 23:19:11.005456 Set Vref, RX VrefLevel [Byte0]: 47
8655 23:19:11.008511 [Byte1]: 47
8656 23:19:11.012484
8657 23:19:11.012566 Set Vref, RX VrefLevel [Byte0]: 48
8658 23:19:11.016082 [Byte1]: 48
8659 23:19:11.020448
8660 23:19:11.020530 Set Vref, RX VrefLevel [Byte0]: 49
8661 23:19:11.023599 [Byte1]: 49
8662 23:19:11.028048
8663 23:19:11.028175 Set Vref, RX VrefLevel [Byte0]: 50
8664 23:19:11.031183 [Byte1]: 50
8665 23:19:11.035326
8666 23:19:11.035429 Set Vref, RX VrefLevel [Byte0]: 51
8667 23:19:11.038756 [Byte1]: 51
8668 23:19:11.042919
8669 23:19:11.043029 Set Vref, RX VrefLevel [Byte0]: 52
8670 23:19:11.046276 [Byte1]: 52
8671 23:19:11.050736
8672 23:19:11.050819 Set Vref, RX VrefLevel [Byte0]: 53
8673 23:19:11.053861 [Byte1]: 53
8674 23:19:11.058431
8675 23:19:11.058544 Set Vref, RX VrefLevel [Byte0]: 54
8676 23:19:11.061610 [Byte1]: 54
8677 23:19:11.065736
8678 23:19:11.065849 Set Vref, RX VrefLevel [Byte0]: 55
8679 23:19:11.068982 [Byte1]: 55
8680 23:19:11.073558
8681 23:19:11.073639 Set Vref, RX VrefLevel [Byte0]: 56
8682 23:19:11.076892 [Byte1]: 56
8683 23:19:11.080924
8684 23:19:11.081053 Set Vref, RX VrefLevel [Byte0]: 57
8685 23:19:11.084578 [Byte1]: 57
8686 23:19:11.088809
8687 23:19:11.088921 Set Vref, RX VrefLevel [Byte0]: 58
8688 23:19:11.092285 [Byte1]: 58
8689 23:19:11.096465
8690 23:19:11.096547 Set Vref, RX VrefLevel [Byte0]: 59
8691 23:19:11.099484 [Byte1]: 59
8692 23:19:11.104508
8693 23:19:11.104590 Set Vref, RX VrefLevel [Byte0]: 60
8694 23:19:11.107572 [Byte1]: 60
8695 23:19:11.111595
8696 23:19:11.111677 Set Vref, RX VrefLevel [Byte0]: 61
8697 23:19:11.114824 [Byte1]: 61
8698 23:19:11.119114
8699 23:19:11.119197 Set Vref, RX VrefLevel [Byte0]: 62
8700 23:19:11.122638 [Byte1]: 62
8701 23:19:11.126885
8702 23:19:11.126991 Set Vref, RX VrefLevel [Byte0]: 63
8703 23:19:11.130134 [Byte1]: 63
8704 23:19:11.134763
8705 23:19:11.134882 Set Vref, RX VrefLevel [Byte0]: 64
8706 23:19:11.137633 [Byte1]: 64
8707 23:19:11.142258
8708 23:19:11.142340 Set Vref, RX VrefLevel [Byte0]: 65
8709 23:19:11.148244 [Byte1]: 65
8710 23:19:11.148327
8711 23:19:11.151952 Set Vref, RX VrefLevel [Byte0]: 66
8712 23:19:11.154982 [Byte1]: 66
8713 23:19:11.155064
8714 23:19:11.158205 Set Vref, RX VrefLevel [Byte0]: 67
8715 23:19:11.161535 [Byte1]: 67
8716 23:19:11.164806
8717 23:19:11.164888 Set Vref, RX VrefLevel [Byte0]: 68
8718 23:19:11.168365 [Byte1]: 68
8719 23:19:11.172537
8720 23:19:11.172620 Set Vref, RX VrefLevel [Byte0]: 69
8721 23:19:11.175991 [Byte1]: 69
8722 23:19:11.180043
8723 23:19:11.180126 Set Vref, RX VrefLevel [Byte0]: 70
8724 23:19:11.183633 [Byte1]: 70
8725 23:19:11.187848
8726 23:19:11.187941 Final RX Vref Byte 0 = 57 to rank0
8727 23:19:11.190714 Final RX Vref Byte 1 = 60 to rank0
8728 23:19:11.194549 Final RX Vref Byte 0 = 57 to rank1
8729 23:19:11.197975 Final RX Vref Byte 1 = 60 to rank1==
8730 23:19:11.200614 Dram Type= 6, Freq= 0, CH_1, rank 0
8731 23:19:11.207231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 23:19:11.207317 ==
8733 23:19:11.207414 DQS Delay:
8734 23:19:11.210996 DQS0 = 0, DQS1 = 0
8735 23:19:11.211077 DQM Delay:
8736 23:19:11.211163 DQM0 = 131, DQM1 = 128
8737 23:19:11.214752 DQ Delay:
8738 23:19:11.217775 DQ0 =138, DQ1 =128, DQ2 =118, DQ3 =130
8739 23:19:11.220633 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8740 23:19:11.224633 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8741 23:19:11.227601 DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =138
8742 23:19:11.227715
8743 23:19:11.227783
8744 23:19:11.227860
8745 23:19:11.231003 [DramC_TX_OE_Calibration] TA2
8746 23:19:11.233981 Original DQ_B0 (3 6) =30, OEN = 27
8747 23:19:11.237276 Original DQ_B1 (3 6) =30, OEN = 27
8748 23:19:11.240987 24, 0x0, End_B0=24 End_B1=24
8749 23:19:11.241069 25, 0x0, End_B0=25 End_B1=25
8750 23:19:11.243914 26, 0x0, End_B0=26 End_B1=26
8751 23:19:11.247514 27, 0x0, End_B0=27 End_B1=27
8752 23:19:11.250341 28, 0x0, End_B0=28 End_B1=28
8753 23:19:11.253671 29, 0x0, End_B0=29 End_B1=29
8754 23:19:11.253803 30, 0x0, End_B0=30 End_B1=30
8755 23:19:11.257009 31, 0x4141, End_B0=30 End_B1=30
8756 23:19:11.260410 Byte0 end_step=30 best_step=27
8757 23:19:11.263602 Byte1 end_step=30 best_step=27
8758 23:19:11.266962 Byte0 TX OE(2T, 0.5T) = (3, 3)
8759 23:19:11.270382 Byte1 TX OE(2T, 0.5T) = (3, 3)
8760 23:19:11.270501
8761 23:19:11.270613
8762 23:19:11.276425 [DQSOSCAuto] RK0, (LSB)MR18= 0xc15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 403 ps
8763 23:19:11.280202 CH1 RK0: MR19=303, MR18=C15
8764 23:19:11.286715 CH1_RK0: MR19=0x303, MR18=0xC15, DQSOSC=399, MR23=63, INC=23, DEC=15
8765 23:19:11.286802
8766 23:19:11.289705 ----->DramcWriteLeveling(PI) begin...
8767 23:19:11.289789 ==
8768 23:19:11.292959 Dram Type= 6, Freq= 0, CH_1, rank 1
8769 23:19:11.296453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 23:19:11.296535 ==
8771 23:19:11.299625 Write leveling (Byte 0): 24 => 24
8772 23:19:11.303075 Write leveling (Byte 1): 26 => 26
8773 23:19:11.306205 DramcWriteLeveling(PI) end<-----
8774 23:19:11.306287
8775 23:19:11.306352 ==
8776 23:19:11.309484 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 23:19:11.312969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 23:19:11.316307 ==
8779 23:19:11.316412 [Gating] SW mode calibration
8780 23:19:11.325804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8781 23:19:11.329829 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8782 23:19:11.332563 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 23:19:11.339133 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8784 23:19:11.342591 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8785 23:19:11.346114 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8786 23:19:11.352212 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 23:19:11.355888 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 23:19:11.358852 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 23:19:11.365386 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 23:19:11.368491 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 23:19:11.372026 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8792 23:19:11.378718 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8793 23:19:11.381981 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8794 23:19:11.385185 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 23:19:11.391391 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 23:19:11.395098 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 23:19:11.398349 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 23:19:11.404672 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 23:19:11.408199 1 6 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8800 23:19:11.411511 1 6 8 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8801 23:19:11.417905 1 6 12 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
8802 23:19:11.421387 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 23:19:11.424879 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 23:19:11.431168 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 23:19:11.434359 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 23:19:11.438047 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 23:19:11.444412 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8808 23:19:11.447497 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8809 23:19:11.454559 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8810 23:19:11.457404 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8811 23:19:11.460820 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 23:19:11.463987 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 23:19:11.470624 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 23:19:11.473894 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 23:19:11.480760 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 23:19:11.483866 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 23:19:11.487419 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 23:19:11.493791 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 23:19:11.496703 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 23:19:11.499972 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 23:19:11.507088 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 23:19:11.510460 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 23:19:11.513199 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8824 23:19:11.520454 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8825 23:19:11.523200 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8826 23:19:11.526333 Total UI for P1: 0, mck2ui 16
8827 23:19:11.530058 best dqsien dly found for B0: ( 1, 9, 6)
8828 23:19:11.533063 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8829 23:19:11.539270 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 23:19:11.539356 Total UI for P1: 0, mck2ui 16
8831 23:19:11.546310 best dqsien dly found for B1: ( 1, 9, 14)
8832 23:19:11.549645 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8833 23:19:11.552518 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8834 23:19:11.552606
8835 23:19:11.556146 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8836 23:19:11.558923 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8837 23:19:11.562421 [Gating] SW calibration Done
8838 23:19:11.562505 ==
8839 23:19:11.565730 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 23:19:11.569289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 23:19:11.569416 ==
8842 23:19:11.572705 RX Vref Scan: 0
8843 23:19:11.572829
8844 23:19:11.572942 RX Vref 0 -> 0, step: 1
8845 23:19:11.573053
8846 23:19:11.575829 RX Delay 0 -> 252, step: 8
8847 23:19:11.578898 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8848 23:19:11.585620 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8849 23:19:11.589112 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8850 23:19:11.592555 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8851 23:19:11.595815 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8852 23:19:11.598989 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8853 23:19:11.605548 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8854 23:19:11.608776 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8855 23:19:11.612308 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8856 23:19:11.615459 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8857 23:19:11.618377 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8858 23:19:11.625705 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8859 23:19:11.628610 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8860 23:19:11.632087 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8861 23:19:11.634981 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8862 23:19:11.641505 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8863 23:19:11.641585 ==
8864 23:19:11.644773 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 23:19:11.648313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 23:19:11.648396 ==
8867 23:19:11.648502 DQS Delay:
8868 23:19:11.651320 DQS0 = 0, DQS1 = 0
8869 23:19:11.651438 DQM Delay:
8870 23:19:11.654707 DQM0 = 133, DQM1 = 130
8871 23:19:11.654788 DQ Delay:
8872 23:19:11.657978 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8873 23:19:11.661541 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8874 23:19:11.664519 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8875 23:19:11.671117 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8876 23:19:11.671199
8877 23:19:11.671264
8878 23:19:11.671323 ==
8879 23:19:11.674875 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 23:19:11.677604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 23:19:11.677687 ==
8882 23:19:11.677752
8883 23:19:11.677811
8884 23:19:11.681121 TX Vref Scan disable
8885 23:19:11.681203 == TX Byte 0 ==
8886 23:19:11.687784 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8887 23:19:11.690634 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8888 23:19:11.690749 == TX Byte 1 ==
8889 23:19:11.697482 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8890 23:19:11.700703 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8891 23:19:11.700786 ==
8892 23:19:11.704529 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 23:19:11.707278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 23:19:11.707384 ==
8895 23:19:11.722039
8896 23:19:11.725429 TX Vref early break, caculate TX vref
8897 23:19:11.729063 TX Vref=16, minBit 9, minWin=22, winSum=380
8898 23:19:11.732350 TX Vref=18, minBit 9, minWin=22, winSum=383
8899 23:19:11.735240 TX Vref=20, minBit 9, minWin=23, winSum=398
8900 23:19:11.738772 TX Vref=22, minBit 8, minWin=23, winSum=398
8901 23:19:11.741887 TX Vref=24, minBit 9, minWin=23, winSum=403
8902 23:19:11.748405 TX Vref=26, minBit 0, minWin=25, winSum=416
8903 23:19:11.751636 TX Vref=28, minBit 8, minWin=25, winSum=421
8904 23:19:11.754943 TX Vref=30, minBit 9, minWin=24, winSum=417
8905 23:19:11.758426 TX Vref=32, minBit 0, minWin=25, winSum=413
8906 23:19:11.761855 TX Vref=34, minBit 0, minWin=24, winSum=403
8907 23:19:11.765053 TX Vref=36, minBit 0, minWin=24, winSum=396
8908 23:19:11.771904 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 28
8909 23:19:11.771986
8910 23:19:11.774860 Final TX Range 0 Vref 28
8911 23:19:11.774942
8912 23:19:11.775007 ==
8913 23:19:11.778840 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 23:19:11.781794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 23:19:11.781876 ==
8916 23:19:11.784861
8917 23:19:11.784984
8918 23:19:11.785097 TX Vref Scan disable
8919 23:19:11.791590 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8920 23:19:11.791694 == TX Byte 0 ==
8921 23:19:11.794717 u2DelayCellOfst[0]=14 cells (4 PI)
8922 23:19:11.798010 u2DelayCellOfst[1]=10 cells (3 PI)
8923 23:19:11.801378 u2DelayCellOfst[2]=0 cells (0 PI)
8924 23:19:11.804676 u2DelayCellOfst[3]=7 cells (2 PI)
8925 23:19:11.808320 u2DelayCellOfst[4]=7 cells (2 PI)
8926 23:19:11.811681 u2DelayCellOfst[5]=14 cells (4 PI)
8927 23:19:11.814797 u2DelayCellOfst[6]=14 cells (4 PI)
8928 23:19:11.817865 u2DelayCellOfst[7]=7 cells (2 PI)
8929 23:19:11.821025 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8930 23:19:11.824631 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8931 23:19:11.827696 == TX Byte 1 ==
8932 23:19:11.831088 u2DelayCellOfst[8]=0 cells (0 PI)
8933 23:19:11.834708 u2DelayCellOfst[9]=0 cells (0 PI)
8934 23:19:11.837825 u2DelayCellOfst[10]=10 cells (3 PI)
8935 23:19:11.840854 u2DelayCellOfst[11]=3 cells (1 PI)
8936 23:19:11.844051 u2DelayCellOfst[12]=14 cells (4 PI)
8937 23:19:11.844184 u2DelayCellOfst[13]=14 cells (4 PI)
8938 23:19:11.847553 u2DelayCellOfst[14]=14 cells (4 PI)
8939 23:19:11.851005 u2DelayCellOfst[15]=17 cells (5 PI)
8940 23:19:11.857567 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8941 23:19:11.860734 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8942 23:19:11.863896 DramC Write-DBI on
8943 23:19:11.864017 ==
8944 23:19:11.867549 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 23:19:11.870840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 23:19:11.870963 ==
8947 23:19:11.871075
8948 23:19:11.871209
8949 23:19:11.873744 TX Vref Scan disable
8950 23:19:11.873825 == TX Byte 0 ==
8951 23:19:11.880415 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8952 23:19:11.880498 == TX Byte 1 ==
8953 23:19:11.883845 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8954 23:19:11.887544 DramC Write-DBI off
8955 23:19:11.887625
8956 23:19:11.887689 [DATLAT]
8957 23:19:11.890606 Freq=1600, CH1 RK1
8958 23:19:11.890687
8959 23:19:11.890767 DATLAT Default: 0xf
8960 23:19:11.894043 0, 0xFFFF, sum = 0
8961 23:19:11.894126 1, 0xFFFF, sum = 0
8962 23:19:11.896942 2, 0xFFFF, sum = 0
8963 23:19:11.900398 3, 0xFFFF, sum = 0
8964 23:19:11.900497 4, 0xFFFF, sum = 0
8965 23:19:11.903874 5, 0xFFFF, sum = 0
8966 23:19:11.903958 6, 0xFFFF, sum = 0
8967 23:19:11.907023 7, 0xFFFF, sum = 0
8968 23:19:11.907106 8, 0xFFFF, sum = 0
8969 23:19:11.910167 9, 0xFFFF, sum = 0
8970 23:19:11.910250 10, 0xFFFF, sum = 0
8971 23:19:11.913561 11, 0xFFFF, sum = 0
8972 23:19:11.913644 12, 0xFFFF, sum = 0
8973 23:19:11.916559 13, 0xFFFF, sum = 0
8974 23:19:11.916668 14, 0x0, sum = 1
8975 23:19:11.920232 15, 0x0, sum = 2
8976 23:19:11.920329 16, 0x0, sum = 3
8977 23:19:11.923534 17, 0x0, sum = 4
8978 23:19:11.923623 best_step = 15
8979 23:19:11.923688
8980 23:19:11.923748 ==
8981 23:19:11.926621 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 23:19:11.933527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 23:19:11.933635 ==
8984 23:19:11.933757 RX Vref Scan: 0
8985 23:19:11.933846
8986 23:19:11.936633 RX Vref 0 -> 0, step: 1
8987 23:19:11.936740
8988 23:19:11.940141 RX Delay 11 -> 252, step: 4
8989 23:19:11.942753 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8990 23:19:11.946589 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8991 23:19:11.949951 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8992 23:19:11.956043 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8993 23:19:11.959398 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8994 23:19:11.962801 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8995 23:19:11.966410 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8996 23:19:11.969383 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8997 23:19:11.975988 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8998 23:19:11.979265 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8999 23:19:11.982595 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9000 23:19:11.985933 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9001 23:19:11.992507 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9002 23:19:11.995479 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9003 23:19:11.998846 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9004 23:19:12.002657 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9005 23:19:12.002783 ==
9006 23:19:12.005915 Dram Type= 6, Freq= 0, CH_1, rank 1
9007 23:19:12.012589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9008 23:19:12.012711 ==
9009 23:19:12.012824 DQS Delay:
9010 23:19:12.015472 DQS0 = 0, DQS1 = 0
9011 23:19:12.015593 DQM Delay:
9012 23:19:12.015734 DQM0 = 131, DQM1 = 127
9013 23:19:12.019046 DQ Delay:
9014 23:19:12.022091 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
9015 23:19:12.025489 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =128
9016 23:19:12.028523 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
9017 23:19:12.032289 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =136
9018 23:19:12.032438
9019 23:19:12.032566
9020 23:19:12.032702
9021 23:19:12.034941 [DramC_TX_OE_Calibration] TA2
9022 23:19:12.038423 Original DQ_B0 (3 6) =30, OEN = 27
9023 23:19:12.041569 Original DQ_B1 (3 6) =30, OEN = 27
9024 23:19:12.044847 24, 0x0, End_B0=24 End_B1=24
9025 23:19:12.048055 25, 0x0, End_B0=25 End_B1=25
9026 23:19:12.048183 26, 0x0, End_B0=26 End_B1=26
9027 23:19:12.052207 27, 0x0, End_B0=27 End_B1=27
9028 23:19:12.054981 28, 0x0, End_B0=28 End_B1=28
9029 23:19:12.058399 29, 0x0, End_B0=29 End_B1=29
9030 23:19:12.058506 30, 0x0, End_B0=30 End_B1=30
9031 23:19:12.061429 31, 0x4141, End_B0=30 End_B1=30
9032 23:19:12.064840 Byte0 end_step=30 best_step=27
9033 23:19:12.068289 Byte1 end_step=30 best_step=27
9034 23:19:12.071246 Byte0 TX OE(2T, 0.5T) = (3, 3)
9035 23:19:12.074680 Byte1 TX OE(2T, 0.5T) = (3, 3)
9036 23:19:12.074804
9037 23:19:12.074914
9038 23:19:12.081077 [DQSOSCAuto] RK1, (LSB)MR18= 0x101e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9039 23:19:12.084952 CH1 RK1: MR19=303, MR18=101E
9040 23:19:12.091101 CH1_RK1: MR19=0x303, MR18=0x101E, DQSOSC=394, MR23=63, INC=23, DEC=15
9041 23:19:12.094244 [RxdqsGatingPostProcess] freq 1600
9042 23:19:12.100998 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9043 23:19:12.101081 best DQS0 dly(2T, 0.5T) = (1, 1)
9044 23:19:12.104115 best DQS1 dly(2T, 0.5T) = (1, 1)
9045 23:19:12.107734 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9046 23:19:12.110642 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9047 23:19:12.114437 best DQS0 dly(2T, 0.5T) = (1, 1)
9048 23:19:12.117812 best DQS1 dly(2T, 0.5T) = (1, 1)
9049 23:19:12.120865 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9050 23:19:12.123847 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9051 23:19:12.127633 Pre-setting of DQS Precalculation
9052 23:19:12.130735 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9053 23:19:12.140258 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9054 23:19:12.146885 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9055 23:19:12.147010
9056 23:19:12.147124
9057 23:19:12.150050 [Calibration Summary] 3200 Mbps
9058 23:19:12.150172 CH 0, Rank 0
9059 23:19:12.153745 SW Impedance : PASS
9060 23:19:12.157134 DUTY Scan : NO K
9061 23:19:12.157254 ZQ Calibration : PASS
9062 23:19:12.160324 Jitter Meter : NO K
9063 23:19:12.163670 CBT Training : PASS
9064 23:19:12.163794 Write leveling : PASS
9065 23:19:12.167190 RX DQS gating : PASS
9066 23:19:12.167310 RX DQ/DQS(RDDQC) : PASS
9067 23:19:12.170112 TX DQ/DQS : PASS
9068 23:19:12.173112 RX DATLAT : PASS
9069 23:19:12.173233 RX DQ/DQS(Engine): PASS
9070 23:19:12.176608 TX OE : PASS
9071 23:19:12.176728 All Pass.
9072 23:19:12.176840
9073 23:19:12.179950 CH 0, Rank 1
9074 23:19:12.180069 SW Impedance : PASS
9075 23:19:12.183341 DUTY Scan : NO K
9076 23:19:12.186536 ZQ Calibration : PASS
9077 23:19:12.186658 Jitter Meter : NO K
9078 23:19:12.189890 CBT Training : PASS
9079 23:19:12.193118 Write leveling : PASS
9080 23:19:12.193237 RX DQS gating : PASS
9081 23:19:12.196456 RX DQ/DQS(RDDQC) : PASS
9082 23:19:12.199988 TX DQ/DQS : PASS
9083 23:19:12.200089 RX DATLAT : PASS
9084 23:19:12.203256 RX DQ/DQS(Engine): PASS
9085 23:19:12.206582 TX OE : PASS
9086 23:19:12.206678 All Pass.
9087 23:19:12.206765
9088 23:19:12.206850 CH 1, Rank 0
9089 23:19:12.209723 SW Impedance : PASS
9090 23:19:12.212563 DUTY Scan : NO K
9091 23:19:12.212684 ZQ Calibration : PASS
9092 23:19:12.215821 Jitter Meter : NO K
9093 23:19:12.219077 CBT Training : PASS
9094 23:19:12.219198 Write leveling : PASS
9095 23:19:12.222853 RX DQS gating : PASS
9096 23:19:12.225920 RX DQ/DQS(RDDQC) : PASS
9097 23:19:12.226043 TX DQ/DQS : PASS
9098 23:19:12.229035 RX DATLAT : PASS
9099 23:19:12.232268 RX DQ/DQS(Engine): PASS
9100 23:19:12.232350 TX OE : PASS
9101 23:19:12.235962 All Pass.
9102 23:19:12.236043
9103 23:19:12.236107 CH 1, Rank 1
9104 23:19:12.238988 SW Impedance : PASS
9105 23:19:12.239069 DUTY Scan : NO K
9106 23:19:12.242444 ZQ Calibration : PASS
9107 23:19:12.245956 Jitter Meter : NO K
9108 23:19:12.246074 CBT Training : PASS
9109 23:19:12.248993 Write leveling : PASS
9110 23:19:12.252126 RX DQS gating : PASS
9111 23:19:12.252248 RX DQ/DQS(RDDQC) : PASS
9112 23:19:12.255483 TX DQ/DQS : PASS
9113 23:19:12.258906 RX DATLAT : PASS
9114 23:19:12.259021 RX DQ/DQS(Engine): PASS
9115 23:19:12.261759 TX OE : PASS
9116 23:19:12.261898 All Pass.
9117 23:19:12.262042
9118 23:19:12.265049 DramC Write-DBI on
9119 23:19:12.268763 PER_BANK_REFRESH: Hybrid Mode
9120 23:19:12.268891 TX_TRACKING: ON
9121 23:19:12.278452 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9122 23:19:12.284883 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9123 23:19:12.291295 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9124 23:19:12.294621 [FAST_K] Save calibration result to emmc
9125 23:19:12.297838 sync common calibartion params.
9126 23:19:12.301161 sync cbt_mode0:1, 1:1
9127 23:19:12.304587 dram_init: ddr_geometry: 2
9128 23:19:12.304706 dram_init: ddr_geometry: 2
9129 23:19:12.307615 dram_init: ddr_geometry: 2
9130 23:19:12.310808 0:dram_rank_size:100000000
9131 23:19:12.314093 1:dram_rank_size:100000000
9132 23:19:12.317843 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9133 23:19:12.320833 DFS_SHUFFLE_HW_MODE: ON
9134 23:19:12.324021 dramc_set_vcore_voltage set vcore to 725000
9135 23:19:12.327782 Read voltage for 1600, 0
9136 23:19:12.327864 Vio18 = 0
9137 23:19:12.330986 Vcore = 725000
9138 23:19:12.331121 Vdram = 0
9139 23:19:12.331228 Vddq = 0
9140 23:19:12.331317 Vmddr = 0
9141 23:19:12.333897 switch to 3200 Mbps bootup
9142 23:19:12.337401 [DramcRunTimeConfig]
9143 23:19:12.337523 PHYPLL
9144 23:19:12.340812 DPM_CONTROL_AFTERK: ON
9145 23:19:12.340933 PER_BANK_REFRESH: ON
9146 23:19:12.344165 REFRESH_OVERHEAD_REDUCTION: ON
9147 23:19:12.347379 CMD_PICG_NEW_MODE: OFF
9148 23:19:12.347506 XRTWTW_NEW_MODE: ON
9149 23:19:12.350659 XRTRTR_NEW_MODE: ON
9150 23:19:12.350779 TX_TRACKING: ON
9151 23:19:12.353781 RDSEL_TRACKING: OFF
9152 23:19:12.357729 DQS Precalculation for DVFS: ON
9153 23:19:12.357850 RX_TRACKING: OFF
9154 23:19:12.357961 HW_GATING DBG: ON
9155 23:19:12.360612 ZQCS_ENABLE_LP4: ON
9156 23:19:12.363455 RX_PICG_NEW_MODE: ON
9157 23:19:12.363572 TX_PICG_NEW_MODE: ON
9158 23:19:12.367132 ENABLE_RX_DCM_DPHY: ON
9159 23:19:12.370344 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9160 23:19:12.373908 DUMMY_READ_FOR_TRACKING: OFF
9161 23:19:12.374031 !!! SPM_CONTROL_AFTERK: OFF
9162 23:19:12.376746 !!! SPM could not control APHY
9163 23:19:12.380178 IMPEDANCE_TRACKING: ON
9164 23:19:12.380332 TEMP_SENSOR: ON
9165 23:19:12.383343 HW_SAVE_FOR_SR: OFF
9166 23:19:12.386626 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9167 23:19:12.389998 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9168 23:19:12.390119 Read ODT Tracking: ON
9169 23:19:12.393240 Refresh Rate DeBounce: ON
9170 23:19:12.396705 DFS_NO_QUEUE_FLUSH: ON
9171 23:19:12.399726 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9172 23:19:12.399849 ENABLE_DFS_RUNTIME_MRW: OFF
9173 23:19:12.403121 DDR_RESERVE_NEW_MODE: ON
9174 23:19:12.406471 MR_CBT_SWITCH_FREQ: ON
9175 23:19:12.406591 =========================
9176 23:19:12.426716 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9177 23:19:12.429940 dram_init: ddr_geometry: 2
9178 23:19:12.448461 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9179 23:19:12.451712 dram_init: dram init end (result: 0)
9180 23:19:12.458443 DRAM-K: Full calibration passed in 24418 msecs
9181 23:19:12.461471 MRC: failed to locate region type 0.
9182 23:19:12.461596 DRAM rank0 size:0x100000000,
9183 23:19:12.464929 DRAM rank1 size=0x100000000
9184 23:19:12.474844 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9185 23:19:12.481247 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9186 23:19:12.490965 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9187 23:19:12.497662 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9188 23:19:12.497776 DRAM rank0 size:0x100000000,
9189 23:19:12.501075 DRAM rank1 size=0x100000000
9190 23:19:12.501158 CBMEM:
9191 23:19:12.504474 IMD: root @ 0xfffff000 254 entries.
9192 23:19:12.507694 IMD: root @ 0xffffec00 62 entries.
9193 23:19:12.510959 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9194 23:19:12.517671 WARNING: RO_VPD is uninitialized or empty.
9195 23:19:12.520820 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9196 23:19:12.528838 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9197 23:19:12.541393 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9198 23:19:12.552419 BS: romstage times (exec / console): total (unknown) / 23944 ms
9199 23:19:12.552503
9200 23:19:12.552568
9201 23:19:12.562622 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9202 23:19:12.565907 ARM64: Exception handlers installed.
9203 23:19:12.569054 ARM64: Testing exception
9204 23:19:12.572086 ARM64: Done test exception
9205 23:19:12.572181 Enumerating buses...
9206 23:19:12.575478 Show all devs... Before device enumeration.
9207 23:19:12.578822 Root Device: enabled 1
9208 23:19:12.582523 CPU_CLUSTER: 0: enabled 1
9209 23:19:12.582604 CPU: 00: enabled 1
9210 23:19:12.585669 Compare with tree...
9211 23:19:12.585760 Root Device: enabled 1
9212 23:19:12.589537 CPU_CLUSTER: 0: enabled 1
9213 23:19:12.592189 CPU: 00: enabled 1
9214 23:19:12.592270 Root Device scanning...
9215 23:19:12.595330 scan_static_bus for Root Device
9216 23:19:12.598616 CPU_CLUSTER: 0 enabled
9217 23:19:12.602067 scan_static_bus for Root Device done
9218 23:19:12.605278 scan_bus: bus Root Device finished in 8 msecs
9219 23:19:12.605359 done
9220 23:19:12.611876 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9221 23:19:12.615271 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9222 23:19:12.621583 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9223 23:19:12.628169 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9224 23:19:12.628277 Allocating resources...
9225 23:19:12.631162 Reading resources...
9226 23:19:12.634610 Root Device read_resources bus 0 link: 0
9227 23:19:12.638099 DRAM rank0 size:0x100000000,
9228 23:19:12.638180 DRAM rank1 size=0x100000000
9229 23:19:12.644380 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9230 23:19:12.647777 CPU: 00 missing read_resources
9231 23:19:12.651068 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9232 23:19:12.654130 Root Device read_resources bus 0 link: 0 done
9233 23:19:12.657385 Done reading resources.
9234 23:19:12.660654 Show resources in subtree (Root Device)...After reading.
9235 23:19:12.664194 Root Device child on link 0 CPU_CLUSTER: 0
9236 23:19:12.670941 CPU_CLUSTER: 0 child on link 0 CPU: 00
9237 23:19:12.677393 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9238 23:19:12.677476 CPU: 00
9239 23:19:12.684134 Root Device assign_resources, bus 0 link: 0
9240 23:19:12.687298 CPU_CLUSTER: 0 missing set_resources
9241 23:19:12.690588 Root Device assign_resources, bus 0 link: 0 done
9242 23:19:12.693637 Done setting resources.
9243 23:19:12.696942 Show resources in subtree (Root Device)...After assigning values.
9244 23:19:12.703790 Root Device child on link 0 CPU_CLUSTER: 0
9245 23:19:12.706702 CPU_CLUSTER: 0 child on link 0 CPU: 00
9246 23:19:12.713290 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9247 23:19:12.717108 CPU: 00
9248 23:19:12.717215 Done allocating resources.
9249 23:19:12.723225 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9250 23:19:12.726985 Enabling resources...
9251 23:19:12.727115 done.
9252 23:19:12.730061 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9253 23:19:12.733470 Initializing devices...
9254 23:19:12.733552 Root Device init
9255 23:19:12.736432 init hardware done!
9256 23:19:12.739878 0x00000018: ctrlr->caps
9257 23:19:12.740020 52.000 MHz: ctrlr->f_max
9258 23:19:12.743222 0.400 MHz: ctrlr->f_min
9259 23:19:12.746272 0x40ff8080: ctrlr->voltages
9260 23:19:12.746355 sclk: 390625
9261 23:19:12.746420 Bus Width = 1
9262 23:19:12.749618 sclk: 390625
9263 23:19:12.749700 Bus Width = 1
9264 23:19:12.752909 Early init status = 3
9265 23:19:12.756702 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9266 23:19:12.760423 in-header: 03 fc 00 00 01 00 00 00
9267 23:19:12.763310 in-data: 00
9268 23:19:12.766776 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9269 23:19:12.771507 in-header: 03 fd 00 00 00 00 00 00
9270 23:19:12.774381 in-data:
9271 23:19:12.777707 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9272 23:19:12.782049 in-header: 03 fc 00 00 01 00 00 00
9273 23:19:12.784632 in-data: 00
9274 23:19:12.787636 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9275 23:19:12.793160 in-header: 03 fd 00 00 00 00 00 00
9276 23:19:12.795953 in-data:
9277 23:19:12.799254 [SSUSB] Setting up USB HOST controller...
9278 23:19:12.802384 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9279 23:19:12.805651 [SSUSB] phy power-on done.
9280 23:19:12.809073 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9281 23:19:12.815595 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9282 23:19:12.818793 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9283 23:19:12.825442 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9284 23:19:12.832108 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9285 23:19:12.838671 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9286 23:19:12.845489 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9287 23:19:12.851875 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9288 23:19:12.855758 SPM: binary array size = 0x9dc
9289 23:19:12.858309 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9290 23:19:12.864998 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9291 23:19:12.871987 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9292 23:19:12.878310 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9293 23:19:12.881632 configure_display: Starting display init
9294 23:19:12.916215 anx7625_power_on_init: Init interface.
9295 23:19:12.919000 anx7625_disable_pd_protocol: Disabled PD feature.
9296 23:19:12.922530 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9297 23:19:12.950431 anx7625_start_dp_work: Secure OCM version=00
9298 23:19:12.953105 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9299 23:19:12.968144 sp_tx_get_edid_block: EDID Block = 1
9300 23:19:13.070841 Extracted contents:
9301 23:19:13.074133 header: 00 ff ff ff ff ff ff 00
9302 23:19:13.077576 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9303 23:19:13.081052 version: 01 04
9304 23:19:13.084129 basic params: 95 1f 11 78 0a
9305 23:19:13.087319 chroma info: 76 90 94 55 54 90 27 21 50 54
9306 23:19:13.090588 established: 00 00 00
9307 23:19:13.096981 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9308 23:19:13.103729 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9309 23:19:13.106945 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9310 23:19:13.113453 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9311 23:19:13.120526 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9312 23:19:13.123825 extensions: 00
9313 23:19:13.123947 checksum: fb
9314 23:19:13.124063
9315 23:19:13.130277 Manufacturer: IVO Model 57d Serial Number 0
9316 23:19:13.130404 Made week 0 of 2020
9317 23:19:13.133839 EDID version: 1.4
9318 23:19:13.133965 Digital display
9319 23:19:13.136829 6 bits per primary color channel
9320 23:19:13.140254 DisplayPort interface
9321 23:19:13.140378 Maximum image size: 31 cm x 17 cm
9322 23:19:13.143182 Gamma: 220%
9323 23:19:13.143265 Check DPMS levels
9324 23:19:13.150502 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9325 23:19:13.153174 First detailed timing is preferred timing
9326 23:19:13.156169 Established timings supported:
9327 23:19:13.156253 Standard timings supported:
9328 23:19:13.159825 Detailed timings
9329 23:19:13.162874 Hex of detail: 383680a07038204018303c0035ae10000019
9330 23:19:13.169460 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9331 23:19:13.172978 0780 0798 07c8 0820 hborder 0
9332 23:19:13.175890 0438 043b 0447 0458 vborder 0
9333 23:19:13.179312 -hsync -vsync
9334 23:19:13.179418 Did detailed timing
9335 23:19:13.186368 Hex of detail: 000000000000000000000000000000000000
9336 23:19:13.189334 Manufacturer-specified data, tag 0
9337 23:19:13.192696 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9338 23:19:13.196387 ASCII string: InfoVision
9339 23:19:13.199162 Hex of detail: 000000fe00523134304e574635205248200a
9340 23:19:13.202539 ASCII string: R140NWF5 RH
9341 23:19:13.202662 Checksum
9342 23:19:13.205891 Checksum: 0xfb (valid)
9343 23:19:13.209000 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9344 23:19:13.212367 DSI data_rate: 832800000 bps
9345 23:19:13.219001 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9346 23:19:13.222609 anx7625_parse_edid: pixelclock(138800).
9347 23:19:13.225584 hactive(1920), hsync(48), hfp(24), hbp(88)
9348 23:19:13.228988 vactive(1080), vsync(12), vfp(3), vbp(17)
9349 23:19:13.232225 anx7625_dsi_config: config dsi.
9350 23:19:13.239136 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9351 23:19:13.253483 anx7625_dsi_config: success to config DSI
9352 23:19:13.256134 anx7625_dp_start: MIPI phy setup OK.
9353 23:19:13.259328 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9354 23:19:13.262643 mtk_ddp_mode_set invalid vrefresh 60
9355 23:19:13.266003 main_disp_path_setup
9356 23:19:13.266086 ovl_layer_smi_id_en
9357 23:19:13.269336 ovl_layer_smi_id_en
9358 23:19:13.269418 ccorr_config
9359 23:19:13.269483 aal_config
9360 23:19:13.272467 gamma_config
9361 23:19:13.272549 postmask_config
9362 23:19:13.275947 dither_config
9363 23:19:13.279168 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9364 23:19:13.286003 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9365 23:19:13.289117 Root Device init finished in 551 msecs
9366 23:19:13.292361 CPU_CLUSTER: 0 init
9367 23:19:13.298779 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9368 23:19:13.305243 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9369 23:19:13.305366 APU_MBOX 0x190000b0 = 0x10001
9370 23:19:13.308639 APU_MBOX 0x190001b0 = 0x10001
9371 23:19:13.312196 APU_MBOX 0x190005b0 = 0x10001
9372 23:19:13.315495 APU_MBOX 0x190006b0 = 0x10001
9373 23:19:13.321739 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9374 23:19:13.331847 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9375 23:19:13.344552 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9376 23:19:13.350827 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9377 23:19:13.362655 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9378 23:19:13.371851 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9379 23:19:13.374812 CPU_CLUSTER: 0 init finished in 81 msecs
9380 23:19:13.378122 Devices initialized
9381 23:19:13.381636 Show all devs... After init.
9382 23:19:13.381719 Root Device: enabled 1
9383 23:19:13.384615 CPU_CLUSTER: 0: enabled 1
9384 23:19:13.388185 CPU: 00: enabled 1
9385 23:19:13.391210 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9386 23:19:13.394716 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9387 23:19:13.397837 ELOG: NV offset 0x57f000 size 0x1000
9388 23:19:13.404962 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9389 23:19:13.411222 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9390 23:19:13.414943 ELOG: Event(17) added with size 13 at 2024-04-03 23:19:15 UTC
9391 23:19:13.421403 out: cmd=0x121: 03 db 21 01 00 00 00 00
9392 23:19:13.424398 in-header: 03 35 00 00 2c 00 00 00
9393 23:19:13.434190 in-data: 2a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9394 23:19:13.441357 ELOG: Event(A1) added with size 10 at 2024-04-03 23:19:15 UTC
9395 23:19:13.447617 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9396 23:19:13.454430 ELOG: Event(A0) added with size 9 at 2024-04-03 23:19:15 UTC
9397 23:19:13.457680 elog_add_boot_reason: Logged dev mode boot
9398 23:19:13.464060 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9399 23:19:13.464169 Finalize devices...
9400 23:19:13.467276 Devices finalized
9401 23:19:13.470827 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9402 23:19:13.474350 Writing coreboot table at 0xffe64000
9403 23:19:13.477538 0. 000000000010a000-0000000000113fff: RAMSTAGE
9404 23:19:13.484106 1. 0000000040000000-00000000400fffff: RAM
9405 23:19:13.487648 2. 0000000040100000-000000004032afff: RAMSTAGE
9406 23:19:13.490476 3. 000000004032b000-00000000545fffff: RAM
9407 23:19:13.493847 4. 0000000054600000-000000005465ffff: BL31
9408 23:19:13.496914 5. 0000000054660000-00000000ffe63fff: RAM
9409 23:19:13.503590 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9410 23:19:13.507158 7. 0000000100000000-000000023fffffff: RAM
9411 23:19:13.510534 Passing 5 GPIOs to payload:
9412 23:19:13.513475 NAME | PORT | POLARITY | VALUE
9413 23:19:13.520062 EC in RW | 0x000000aa | low | undefined
9414 23:19:13.523576 EC interrupt | 0x00000005 | low | undefined
9415 23:19:13.526997 TPM interrupt | 0x000000ab | high | undefined
9416 23:19:13.533578 SD card detect | 0x00000011 | high | undefined
9417 23:19:13.536892 speaker enable | 0x00000093 | high | undefined
9418 23:19:13.540070 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9419 23:19:13.543343 in-header: 03 f9 00 00 02 00 00 00
9420 23:19:13.546424 in-data: 02 00
9421 23:19:13.549888 ADC[4]: Raw value=902586 ID=7
9422 23:19:13.553310 ADC[3]: Raw value=213916 ID=1
9423 23:19:13.553392 RAM Code: 0x71
9424 23:19:13.556580 ADC[6]: Raw value=75000 ID=0
9425 23:19:13.559841 ADC[5]: Raw value=213546 ID=1
9426 23:19:13.559924 SKU Code: 0x1
9427 23:19:13.566237 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum e963
9428 23:19:13.566319 coreboot table: 964 bytes.
9429 23:19:13.569813 IMD ROOT 0. 0xfffff000 0x00001000
9430 23:19:13.572859 IMD SMALL 1. 0xffffe000 0x00001000
9431 23:19:13.576071 RO MCACHE 2. 0xffffc000 0x00001104
9432 23:19:13.579277 CONSOLE 3. 0xfff7c000 0x00080000
9433 23:19:13.583071 FMAP 4. 0xfff7b000 0x00000452
9434 23:19:13.586245 TIME STAMP 5. 0xfff7a000 0x00000910
9435 23:19:13.589783 VBOOT WORK 6. 0xfff66000 0x00014000
9436 23:19:13.592742 RAMOOPS 7. 0xffe66000 0x00100000
9437 23:19:13.595884 COREBOOT 8. 0xffe64000 0x00002000
9438 23:19:13.599107 IMD small region:
9439 23:19:13.602398 IMD ROOT 0. 0xffffec00 0x00000400
9440 23:19:13.605476 VPD 1. 0xffffeb80 0x0000006c
9441 23:19:13.609314 MMC STATUS 2. 0xffffeb60 0x00000004
9442 23:19:13.615600 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9443 23:19:13.615732 Probing TPM: done!
9444 23:19:13.622958 Connected to device vid:did:rid of 1ae0:0028:00
9445 23:19:13.629123 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9446 23:19:13.632887 Initialized TPM device CR50 revision 0
9447 23:19:13.635975 Checking cr50 for pending updates
9448 23:19:13.641546 Reading cr50 TPM mode
9449 23:19:13.650111 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9450 23:19:13.656925 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9451 23:19:13.696902 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9452 23:19:13.700248 Checking segment from ROM address 0x40100000
9453 23:19:13.703720 Checking segment from ROM address 0x4010001c
9454 23:19:13.710032 Loading segment from ROM address 0x40100000
9455 23:19:13.710137 code (compression=0)
9456 23:19:13.719885 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9457 23:19:13.726626 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9458 23:19:13.726742 it's not compressed!
9459 23:19:13.733579 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9460 23:19:13.739847 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9461 23:19:13.757302 Loading segment from ROM address 0x4010001c
9462 23:19:13.757389 Entry Point 0x80000000
9463 23:19:13.760548 Loaded segments
9464 23:19:13.763552 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9465 23:19:13.770574 Jumping to boot code at 0x80000000(0xffe64000)
9466 23:19:13.776790 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9467 23:19:13.783462 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9468 23:19:13.792008 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9469 23:19:13.794767 Checking segment from ROM address 0x40100000
9470 23:19:13.798643 Checking segment from ROM address 0x4010001c
9471 23:19:13.805442 Loading segment from ROM address 0x40100000
9472 23:19:13.805530 code (compression=1)
9473 23:19:13.811403 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9474 23:19:13.821283 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9475 23:19:13.821384 using LZMA
9476 23:19:13.830102 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9477 23:19:13.836863 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9478 23:19:13.840157 Loading segment from ROM address 0x4010001c
9479 23:19:13.840240 Entry Point 0x54601000
9480 23:19:13.843185 Loaded segments
9481 23:19:13.846529 NOTICE: MT8192 bl31_setup
9482 23:19:13.853465 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9483 23:19:13.856996 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9484 23:19:13.860034 WARNING: region 0:
9485 23:19:13.863384 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 23:19:13.863520 WARNING: region 1:
9487 23:19:13.870376 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9488 23:19:13.873548 WARNING: region 2:
9489 23:19:13.876733 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9490 23:19:13.880224 WARNING: region 3:
9491 23:19:13.883550 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9492 23:19:13.886751 WARNING: region 4:
9493 23:19:13.893427 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9494 23:19:13.893514 WARNING: region 5:
9495 23:19:13.896763 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 23:19:13.900237 WARNING: region 6:
9497 23:19:13.903684 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 23:19:13.906531 WARNING: region 7:
9499 23:19:13.909895 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 23:19:13.916698 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9501 23:19:13.920051 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9502 23:19:13.923518 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9503 23:19:13.929945 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9504 23:19:13.933368 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9505 23:19:13.939828 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9506 23:19:13.943309 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9507 23:19:13.946192 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9508 23:19:13.952892 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9509 23:19:13.956339 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9510 23:19:13.959716 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9511 23:19:13.966479 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9512 23:19:13.969538 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9513 23:19:13.976297 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9514 23:19:13.979631 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9515 23:19:13.983258 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9516 23:19:13.989508 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9517 23:19:13.992943 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9518 23:19:13.996531 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9519 23:19:14.003144 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9520 23:19:14.006176 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9521 23:19:14.012561 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9522 23:19:14.016393 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9523 23:19:14.019487 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9524 23:19:14.025843 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9525 23:19:14.029349 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9526 23:19:14.036532 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9527 23:19:14.039339 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9528 23:19:14.043124 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9529 23:19:14.049509 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9530 23:19:14.052507 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9531 23:19:14.059355 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9532 23:19:14.062993 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9533 23:19:14.065968 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9534 23:19:14.069443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9535 23:19:14.075943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9536 23:19:14.079297 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9537 23:19:14.082979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9538 23:19:14.086000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9539 23:19:14.089094 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9540 23:19:14.096349 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9541 23:19:14.099398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9542 23:19:14.102698 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9543 23:19:14.109229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9544 23:19:14.112921 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9545 23:19:14.115940 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9546 23:19:14.119200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9547 23:19:14.125748 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9548 23:19:14.129025 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9549 23:19:14.132604 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9550 23:19:14.139111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9551 23:19:14.142397 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9552 23:19:14.149312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9553 23:19:14.152254 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9554 23:19:14.159093 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9555 23:19:14.162271 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9556 23:19:14.168805 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9557 23:19:14.172232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9558 23:19:14.175903 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9559 23:19:14.182126 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9560 23:19:14.185761 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9561 23:19:14.192256 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9562 23:19:14.195346 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9563 23:19:14.201822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9564 23:19:14.205190 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9565 23:19:14.212152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9566 23:19:14.215707 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9567 23:19:14.218793 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9568 23:19:14.225173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9569 23:19:14.228457 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9570 23:19:14.234961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9571 23:19:14.238517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9572 23:19:14.244797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9573 23:19:14.248386 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9574 23:19:14.251727 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9575 23:19:14.258829 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9576 23:19:14.261883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9577 23:19:14.268885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9578 23:19:14.272125 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9579 23:19:14.278575 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9580 23:19:14.281997 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9581 23:19:14.288357 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9582 23:19:14.291794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9583 23:19:14.295059 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9584 23:19:14.301772 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9585 23:19:14.304871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9586 23:19:14.311941 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9587 23:19:14.314992 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9588 23:19:14.321911 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9589 23:19:14.324976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9590 23:19:14.328410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9591 23:19:14.334879 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9592 23:19:14.338027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9593 23:19:14.345179 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9594 23:19:14.348331 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9595 23:19:14.354976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9596 23:19:14.358344 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9597 23:19:14.361863 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9598 23:19:14.365072 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9599 23:19:14.371249 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9600 23:19:14.374674 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9601 23:19:14.377871 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9602 23:19:14.384499 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9603 23:19:14.387610 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9604 23:19:14.394078 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9605 23:19:14.397535 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9606 23:19:14.401041 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9607 23:19:14.407610 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9608 23:19:14.410966 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9609 23:19:14.418017 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9610 23:19:14.420862 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9611 23:19:14.424384 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9612 23:19:14.431317 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9613 23:19:14.434413 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9614 23:19:14.440895 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9615 23:19:14.444245 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9616 23:19:14.447785 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9617 23:19:14.454123 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9618 23:19:14.457586 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9619 23:19:14.460693 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9620 23:19:14.464163 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9621 23:19:14.470724 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9622 23:19:14.474423 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9623 23:19:14.477658 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9624 23:19:14.484321 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9625 23:19:14.487344 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9626 23:19:14.490687 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9627 23:19:14.497102 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9628 23:19:14.500565 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9629 23:19:14.507349 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9630 23:19:14.510714 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9631 23:19:14.514020 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9632 23:19:14.520772 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9633 23:19:14.523938 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9634 23:19:14.527119 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9635 23:19:14.533581 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9636 23:19:14.537134 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9637 23:19:14.543805 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9638 23:19:14.547261 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9639 23:19:14.550643 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9640 23:19:14.557215 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9641 23:19:14.560412 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9642 23:19:14.567090 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9643 23:19:14.570442 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9644 23:19:14.573857 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9645 23:19:14.580435 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9646 23:19:14.583647 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9647 23:19:14.590469 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9648 23:19:14.593389 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9649 23:19:14.596891 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9650 23:19:14.603421 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9651 23:19:14.606612 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9652 23:19:14.609926 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9653 23:19:14.616665 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9654 23:19:14.619919 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9655 23:19:14.626614 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9656 23:19:14.630532 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9657 23:19:14.633319 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9658 23:19:14.640044 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9659 23:19:14.643243 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9660 23:19:14.649775 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9661 23:19:14.653111 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9662 23:19:14.656582 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9663 23:19:14.662934 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9664 23:19:14.666074 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9665 23:19:14.673081 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9666 23:19:14.676106 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9667 23:19:14.679256 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9668 23:19:14.685749 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9669 23:19:14.689192 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9670 23:19:14.696252 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9671 23:19:14.699487 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9672 23:19:14.702730 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9673 23:19:14.708876 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9674 23:19:14.712174 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9675 23:19:14.719214 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9676 23:19:14.721964 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9677 23:19:14.728933 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9678 23:19:14.731943 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9679 23:19:14.735372 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9680 23:19:14.742143 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9681 23:19:14.745275 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9682 23:19:14.751877 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9683 23:19:14.755005 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9684 23:19:14.758401 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9685 23:19:14.765336 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9686 23:19:14.768534 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9687 23:19:14.774966 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9688 23:19:14.778099 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9689 23:19:14.781418 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9690 23:19:14.788426 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9691 23:19:14.791635 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9692 23:19:14.798337 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9693 23:19:14.801487 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9694 23:19:14.804570 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9695 23:19:14.811300 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9696 23:19:14.814259 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9697 23:19:14.821048 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9698 23:19:14.824241 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9699 23:19:14.830964 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9700 23:19:14.834031 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9701 23:19:14.840502 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9702 23:19:14.844475 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9703 23:19:14.847369 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9704 23:19:14.853987 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9705 23:19:14.857226 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9706 23:19:14.863962 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9707 23:19:14.867212 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9708 23:19:14.873902 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9709 23:19:14.877036 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9710 23:19:14.880345 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9711 23:19:14.886984 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9712 23:19:14.890154 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9713 23:19:14.896752 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9714 23:19:14.900379 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9715 23:19:14.903386 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9716 23:19:14.910076 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9717 23:19:14.913934 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9718 23:19:14.919885 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9719 23:19:14.923169 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9720 23:19:14.930172 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9721 23:19:14.933275 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9722 23:19:14.936836 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9723 23:19:14.943140 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9724 23:19:14.946139 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9725 23:19:14.953043 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9726 23:19:14.956159 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9727 23:19:14.963180 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9728 23:19:14.965919 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9729 23:19:14.970013 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9730 23:19:14.972729 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9731 23:19:14.979753 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9732 23:19:14.983243 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9733 23:19:14.985820 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9734 23:19:14.992152 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9735 23:19:14.995603 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9736 23:19:14.998784 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9737 23:19:15.005612 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9738 23:19:15.009026 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9739 23:19:15.012011 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9740 23:19:15.018943 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9741 23:19:15.021976 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9742 23:19:15.028560 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9743 23:19:15.032309 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9744 23:19:15.035185 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9745 23:19:15.041870 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9746 23:19:15.045883 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9747 23:19:15.051552 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9748 23:19:15.054838 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9749 23:19:15.058778 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9750 23:19:15.064711 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9751 23:19:15.067997 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9752 23:19:15.071690 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9753 23:19:15.078147 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9754 23:19:15.081651 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9755 23:19:15.087724 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9756 23:19:15.091063 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9757 23:19:15.094364 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9758 23:19:15.101066 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9759 23:19:15.104126 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9760 23:19:15.107793 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9761 23:19:15.114196 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9762 23:19:15.117395 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9763 23:19:15.120918 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9764 23:19:15.127617 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9765 23:19:15.130640 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9766 23:19:15.137237 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9767 23:19:15.140527 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9768 23:19:15.144001 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9769 23:19:15.150618 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9770 23:19:15.153443 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9771 23:19:15.156739 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9772 23:19:15.160599 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9773 23:19:15.163632 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9774 23:19:15.170053 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9775 23:19:15.173173 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9776 23:19:15.176821 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9777 23:19:15.183255 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9778 23:19:15.186867 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9779 23:19:15.189509 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9780 23:19:15.192870 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9781 23:19:15.199565 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9782 23:19:15.202653 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9783 23:19:15.209283 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9784 23:19:15.212662 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9785 23:19:15.219186 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9786 23:19:15.222586 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9787 23:19:15.225776 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9788 23:19:15.232511 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9789 23:19:15.235920 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9790 23:19:15.242389 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9791 23:19:15.245725 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9792 23:19:15.249074 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9793 23:19:15.255645 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9794 23:19:15.259128 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9795 23:19:15.265279 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9796 23:19:15.268679 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9797 23:19:15.275117 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9798 23:19:15.278687 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9799 23:19:15.281542 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9800 23:19:15.288505 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9801 23:19:15.291518 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9802 23:19:15.298006 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9803 23:19:15.301833 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9804 23:19:15.308013 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9805 23:19:15.311976 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9806 23:19:15.314535 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9807 23:19:15.321242 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9808 23:19:15.324736 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9809 23:19:15.331252 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9810 23:19:15.334195 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9811 23:19:15.340853 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9812 23:19:15.344204 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9813 23:19:15.347516 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9814 23:19:15.354287 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9815 23:19:15.357454 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9816 23:19:15.364036 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9817 23:19:15.367309 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9818 23:19:15.370948 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9819 23:19:15.377266 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9820 23:19:15.381172 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9821 23:19:15.387164 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9822 23:19:15.390866 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9823 23:19:15.393669 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9824 23:19:15.400150 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9825 23:19:15.404047 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9826 23:19:15.410522 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9827 23:19:15.413597 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9828 23:19:15.420277 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9829 23:19:15.423179 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9830 23:19:15.427048 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9831 23:19:15.433087 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9832 23:19:15.436599 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9833 23:19:15.443016 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9834 23:19:15.446627 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9835 23:19:15.452854 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9836 23:19:15.456396 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9837 23:19:15.459670 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9838 23:19:15.466315 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9839 23:19:15.469321 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9840 23:19:15.476130 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9841 23:19:15.479417 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9842 23:19:15.485862 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9843 23:19:15.489051 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9844 23:19:15.492581 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9845 23:19:15.498916 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9846 23:19:15.502249 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9847 23:19:15.508526 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9848 23:19:15.512323 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9849 23:19:15.515521 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9850 23:19:15.522165 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9851 23:19:15.525352 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9852 23:19:15.532104 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9853 23:19:15.535091 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9854 23:19:15.541631 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9855 23:19:15.545124 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9856 23:19:15.548405 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9857 23:19:15.555257 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9858 23:19:15.558442 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9859 23:19:15.564620 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9860 23:19:15.567966 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9861 23:19:15.574689 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9862 23:19:15.577969 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9863 23:19:15.584604 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9864 23:19:15.587601 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9865 23:19:15.591402 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9866 23:19:15.597685 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9867 23:19:15.601332 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9868 23:19:15.607262 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9869 23:19:15.610542 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9870 23:19:15.617256 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9871 23:19:15.620459 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9872 23:19:15.627075 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9873 23:19:15.630875 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9874 23:19:15.637711 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9875 23:19:15.640646 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9876 23:19:15.643550 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9877 23:19:15.650004 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9878 23:19:15.653695 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9879 23:19:15.660184 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9880 23:19:15.663637 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9881 23:19:15.670237 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9882 23:19:15.673319 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9883 23:19:15.680027 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9884 23:19:15.683701 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9885 23:19:15.686569 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9886 23:19:15.693369 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9887 23:19:15.696176 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9888 23:19:15.703355 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9889 23:19:15.706639 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9890 23:19:15.713095 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9891 23:19:15.716049 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9892 23:19:15.722739 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9893 23:19:15.725928 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9894 23:19:15.729108 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9895 23:19:15.735785 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9896 23:19:15.739087 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9897 23:19:15.745907 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9898 23:19:15.748892 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9899 23:19:15.755528 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9900 23:19:15.758742 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9901 23:19:15.765693 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9902 23:19:15.768525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9903 23:19:15.772385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9904 23:19:15.778803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9905 23:19:15.782009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9906 23:19:15.788819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9907 23:19:15.792108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9908 23:19:15.798159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9909 23:19:15.801685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9910 23:19:15.808348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9911 23:19:15.811984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9912 23:19:15.817613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9913 23:19:15.821220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9914 23:19:15.828077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9915 23:19:15.831128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9916 23:19:15.837190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9917 23:19:15.840873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9918 23:19:15.847724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9919 23:19:15.850403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9920 23:19:15.857526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9921 23:19:15.860568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9922 23:19:15.867084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9923 23:19:15.870323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9924 23:19:15.876858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9925 23:19:15.880454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9926 23:19:15.886918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9927 23:19:15.890258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9928 23:19:15.896898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9929 23:19:15.900010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9930 23:19:15.906841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9931 23:19:15.909807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9932 23:19:15.916780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9933 23:19:15.919965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9934 23:19:15.926413 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9935 23:19:15.926541 INFO: [APUAPC] vio 0
9936 23:19:15.933420 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9937 23:19:15.937191 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9938 23:19:15.940334 INFO: [APUAPC] D0_APC_0: 0x400510
9939 23:19:15.943315 INFO: [APUAPC] D0_APC_1: 0x0
9940 23:19:15.946519 INFO: [APUAPC] D0_APC_2: 0x1540
9941 23:19:15.949785 INFO: [APUAPC] D0_APC_3: 0x0
9942 23:19:15.953203 INFO: [APUAPC] D1_APC_0: 0xffffffff
9943 23:19:15.956347 INFO: [APUAPC] D1_APC_1: 0xffffffff
9944 23:19:15.959557 INFO: [APUAPC] D1_APC_2: 0x3fffff
9945 23:19:15.963212 INFO: [APUAPC] D1_APC_3: 0x0
9946 23:19:15.966180 INFO: [APUAPC] D2_APC_0: 0xffffffff
9947 23:19:15.969655 INFO: [APUAPC] D2_APC_1: 0xffffffff
9948 23:19:15.972628 INFO: [APUAPC] D2_APC_2: 0x3fffff
9949 23:19:15.976281 INFO: [APUAPC] D2_APC_3: 0x0
9950 23:19:15.979447 INFO: [APUAPC] D3_APC_0: 0xffffffff
9951 23:19:15.982533 INFO: [APUAPC] D3_APC_1: 0xffffffff
9952 23:19:15.986202 INFO: [APUAPC] D3_APC_2: 0x3fffff
9953 23:19:15.989242 INFO: [APUAPC] D3_APC_3: 0x0
9954 23:19:15.992312 INFO: [APUAPC] D4_APC_0: 0xffffffff
9955 23:19:15.995695 INFO: [APUAPC] D4_APC_1: 0xffffffff
9956 23:19:15.998929 INFO: [APUAPC] D4_APC_2: 0x3fffff
9957 23:19:16.002314 INFO: [APUAPC] D4_APC_3: 0x0
9958 23:19:16.005801 INFO: [APUAPC] D5_APC_0: 0xffffffff
9959 23:19:16.009029 INFO: [APUAPC] D5_APC_1: 0xffffffff
9960 23:19:16.012186 INFO: [APUAPC] D5_APC_2: 0x3fffff
9961 23:19:16.015402 INFO: [APUAPC] D5_APC_3: 0x0
9962 23:19:16.018931 INFO: [APUAPC] D6_APC_0: 0xffffffff
9963 23:19:16.022284 INFO: [APUAPC] D6_APC_1: 0xffffffff
9964 23:19:16.025269 INFO: [APUAPC] D6_APC_2: 0x3fffff
9965 23:19:16.028690 INFO: [APUAPC] D6_APC_3: 0x0
9966 23:19:16.031805 INFO: [APUAPC] D7_APC_0: 0xffffffff
9967 23:19:16.035242 INFO: [APUAPC] D7_APC_1: 0xffffffff
9968 23:19:16.038468 INFO: [APUAPC] D7_APC_2: 0x3fffff
9969 23:19:16.042238 INFO: [APUAPC] D7_APC_3: 0x0
9970 23:19:16.044851 INFO: [APUAPC] D8_APC_0: 0xffffffff
9971 23:19:16.048232 INFO: [APUAPC] D8_APC_1: 0xffffffff
9972 23:19:16.051745 INFO: [APUAPC] D8_APC_2: 0x3fffff
9973 23:19:16.054884 INFO: [APUAPC] D8_APC_3: 0x0
9974 23:19:16.058508 INFO: [APUAPC] D9_APC_0: 0xffffffff
9975 23:19:16.061434 INFO: [APUAPC] D9_APC_1: 0xffffffff
9976 23:19:16.064859 INFO: [APUAPC] D9_APC_2: 0x3fffff
9977 23:19:16.064983 INFO: [APUAPC] D9_APC_3: 0x0
9978 23:19:16.071289 INFO: [APUAPC] D10_APC_0: 0xffffffff
9979 23:19:16.074791 INFO: [APUAPC] D10_APC_1: 0xffffffff
9980 23:19:16.078300 INFO: [APUAPC] D10_APC_2: 0x3fffff
9981 23:19:16.081151 INFO: [APUAPC] D10_APC_3: 0x0
9982 23:19:16.084764 INFO: [APUAPC] D11_APC_0: 0xffffffff
9983 23:19:16.088078 INFO: [APUAPC] D11_APC_1: 0xffffffff
9984 23:19:16.091555 INFO: [APUAPC] D11_APC_2: 0x3fffff
9985 23:19:16.094401 INFO: [APUAPC] D11_APC_3: 0x0
9986 23:19:16.098427 INFO: [APUAPC] D12_APC_0: 0xffffffff
9987 23:19:16.100989 INFO: [APUAPC] D12_APC_1: 0xffffffff
9988 23:19:16.104684 INFO: [APUAPC] D12_APC_2: 0x3fffff
9989 23:19:16.108207 INFO: [APUAPC] D12_APC_3: 0x0
9990 23:19:16.111248 INFO: [APUAPC] D13_APC_0: 0xffffffff
9991 23:19:16.114592 INFO: [APUAPC] D13_APC_1: 0xffffffff
9992 23:19:16.117637 INFO: [APUAPC] D13_APC_2: 0x3fffff
9993 23:19:16.121082 INFO: [APUAPC] D13_APC_3: 0x0
9994 23:19:16.124079 INFO: [APUAPC] D14_APC_0: 0xffffffff
9995 23:19:16.127421 INFO: [APUAPC] D14_APC_1: 0xffffffff
9996 23:19:16.130829 INFO: [APUAPC] D14_APC_2: 0x3fffff
9997 23:19:16.133968 INFO: [APUAPC] D14_APC_3: 0x0
9998 23:19:16.137425 INFO: [APUAPC] D15_APC_0: 0xffffffff
9999 23:19:16.140439 INFO: [APUAPC] D15_APC_1: 0xffffffff
10000 23:19:16.143607 INFO: [APUAPC] D15_APC_2: 0x3fffff
10001 23:19:16.147978 INFO: [APUAPC] D15_APC_3: 0x0
10002 23:19:16.150275 INFO: [APUAPC] APC_CON: 0x4
10003 23:19:16.153470 INFO: [NOCDAPC] D0_APC_0: 0x0
10004 23:19:16.153552 INFO: [NOCDAPC] D0_APC_1: 0x0
10005 23:19:16.156949 INFO: [NOCDAPC] D1_APC_0: 0x0
10006 23:19:16.160201 INFO: [NOCDAPC] D1_APC_1: 0xfff
10007 23:19:16.163336 INFO: [NOCDAPC] D2_APC_0: 0x0
10008 23:19:16.167036 INFO: [NOCDAPC] D2_APC_1: 0xfff
10009 23:19:16.169946 INFO: [NOCDAPC] D3_APC_0: 0x0
10010 23:19:16.173487 INFO: [NOCDAPC] D3_APC_1: 0xfff
10011 23:19:16.176884 INFO: [NOCDAPC] D4_APC_0: 0x0
10012 23:19:16.179929 INFO: [NOCDAPC] D4_APC_1: 0xfff
10013 23:19:16.183661 INFO: [NOCDAPC] D5_APC_0: 0x0
10014 23:19:16.186770 INFO: [NOCDAPC] D5_APC_1: 0xfff
10015 23:19:16.186853 INFO: [NOCDAPC] D6_APC_0: 0x0
10016 23:19:16.189803 INFO: [NOCDAPC] D6_APC_1: 0xfff
10017 23:19:16.193155 INFO: [NOCDAPC] D7_APC_0: 0x0
10018 23:19:16.196488 INFO: [NOCDAPC] D7_APC_1: 0xfff
10019 23:19:16.199736 INFO: [NOCDAPC] D8_APC_0: 0x0
10020 23:19:16.203037 INFO: [NOCDAPC] D8_APC_1: 0xfff
10021 23:19:16.206438 INFO: [NOCDAPC] D9_APC_0: 0x0
10022 23:19:16.209489 INFO: [NOCDAPC] D9_APC_1: 0xfff
10023 23:19:16.213280 INFO: [NOCDAPC] D10_APC_0: 0x0
10024 23:19:16.215924 INFO: [NOCDAPC] D10_APC_1: 0xfff
10025 23:19:16.219592 INFO: [NOCDAPC] D11_APC_0: 0x0
10026 23:19:16.222746 INFO: [NOCDAPC] D11_APC_1: 0xfff
10027 23:19:16.225930 INFO: [NOCDAPC] D12_APC_0: 0x0
10028 23:19:16.229236 INFO: [NOCDAPC] D12_APC_1: 0xfff
10029 23:19:16.232932 INFO: [NOCDAPC] D13_APC_0: 0x0
10030 23:19:16.233015 INFO: [NOCDAPC] D13_APC_1: 0xfff
10031 23:19:16.235755 INFO: [NOCDAPC] D14_APC_0: 0x0
10032 23:19:16.239305 INFO: [NOCDAPC] D14_APC_1: 0xfff
10033 23:19:16.242519 INFO: [NOCDAPC] D15_APC_0: 0x0
10034 23:19:16.245793 INFO: [NOCDAPC] D15_APC_1: 0xfff
10035 23:19:16.249058 INFO: [NOCDAPC] APC_CON: 0x4
10036 23:19:16.252265 INFO: [APUAPC] set_apusys_apc done
10037 23:19:16.255730 INFO: [DEVAPC] devapc_init done
10038 23:19:16.258944 INFO: GICv3 without legacy support detected.
10039 23:19:16.265591 INFO: ARM GICv3 driver initialized in EL3
10040 23:19:16.268846 INFO: Maximum SPI INTID supported: 639
10041 23:19:16.272463 INFO: BL31: Initializing runtime services
10042 23:19:16.278559 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10043 23:19:16.282006 INFO: SPM: enable CPC mode
10044 23:19:16.285403 INFO: mcdi ready for mcusys-off-idle and system suspend
10045 23:19:16.291645 INFO: BL31: Preparing for EL3 exit to normal world
10046 23:19:16.295120 INFO: Entry point address = 0x80000000
10047 23:19:16.295204 INFO: SPSR = 0x8
10048 23:19:16.301950
10049 23:19:16.302032
10050 23:19:16.302098
10051 23:19:16.305130 Starting depthcharge on Spherion...
10052 23:19:16.305213
10053 23:19:16.305278 Wipe memory regions:
10054 23:19:16.305339
10055 23:19:16.306017 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10056 23:19:16.306120 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10057 23:19:16.306207 Setting prompt string to ['asurada:']
10058 23:19:16.306291 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10059 23:19:16.308136 [0x00000040000000, 0x00000054600000)
10060 23:19:16.430450
10061 23:19:16.430570 [0x00000054660000, 0x00000080000000)
10062 23:19:16.691250
10063 23:19:16.691447 [0x000000821a7280, 0x000000ffe64000)
10064 23:19:17.436497
10065 23:19:17.436637 [0x00000100000000, 0x00000240000000)
10066 23:19:19.326389
10067 23:19:19.329657 Initializing XHCI USB controller at 0x11200000.
10068 23:19:20.367212
10069 23:19:20.370422 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10070 23:19:20.370557
10071 23:19:20.370673
10072 23:19:20.370784
10073 23:19:20.371175 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10075 23:19:20.471677 asurada: tftpboot 192.168.201.1 13248440/tftp-deploy-tcaniien/kernel/image.itb 13248440/tftp-deploy-tcaniien/kernel/cmdline
10076 23:19:20.471833 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10077 23:19:20.471919 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10078 23:19:20.476195 tftpboot 192.168.201.1 13248440/tftp-deploy-tcaniien/kernel/image.itp-deploy-tcaniien/kernel/cmdline
10079 23:19:20.476280
10080 23:19:20.476347 Waiting for link
10081 23:19:20.636671
10082 23:19:20.636799 R8152: Initializing
10083 23:19:20.636868
10084 23:19:20.639634 Version 6 (ocp_data = 5c30)
10085 23:19:20.639717
10086 23:19:20.642876 R8152: Done initializing
10087 23:19:20.642959
10088 23:19:20.643025 Adding net device
10089 23:19:22.734671
10090 23:19:22.734811 done.
10091 23:19:22.734879
10092 23:19:22.734940 MAC: 00:24:32:30:7c:7b
10093 23:19:22.734998
10094 23:19:22.737507 Sending DHCP discover... done.
10095 23:19:22.737581
10096 23:19:22.741238 Waiting for reply... done.
10097 23:19:22.741343
10098 23:19:22.744435 Sending DHCP request... done.
10099 23:19:22.744517
10100 23:19:22.744581 Waiting for reply... done.
10101 23:19:22.747521
10102 23:19:22.747602 My ip is 192.168.201.14
10103 23:19:22.747666
10104 23:19:22.751180 The DHCP server ip is 192.168.201.1
10105 23:19:22.751287
10106 23:19:22.754002 TFTP server IP predefined by user: 192.168.201.1
10107 23:19:22.754109
10108 23:19:22.760972 Bootfile predefined by user: 13248440/tftp-deploy-tcaniien/kernel/image.itb
10109 23:19:22.761054
10110 23:19:22.764525 Sending tftp read request... done.
10111 23:19:22.764598
10112 23:19:22.770416 Waiting for the transfer...
10113 23:19:22.770496
10114 23:19:23.318929 00000000 ################################################################
10115 23:19:23.319070
10116 23:19:23.901736 00080000 ################################################################
10117 23:19:23.901886
10118 23:19:24.487101 00100000 ################################################################
10119 23:19:24.487312
10120 23:19:25.053122 00180000 ################################################################
10121 23:19:25.053289
10122 23:19:25.628152 00200000 ################################################################
10123 23:19:25.628300
10124 23:19:26.196062 00280000 ################################################################
10125 23:19:26.196212
10126 23:19:26.775040 00300000 ################################################################
10127 23:19:26.775250
10128 23:19:27.347569 00380000 ################################################################
10129 23:19:27.347720
10130 23:19:27.915056 00400000 ################################################################
10131 23:19:27.915208
10132 23:19:28.468956 00480000 ################################################################
10133 23:19:28.469093
10134 23:19:29.041226 00500000 ################################################################
10135 23:19:29.041369
10136 23:19:29.604734 00580000 ################################################################
10137 23:19:29.604946
10138 23:19:30.183872 00600000 ################################################################
10139 23:19:30.184006
10140 23:19:30.770309 00680000 ################################################################
10141 23:19:30.770446
10142 23:19:31.351008 00700000 ################################################################
10143 23:19:31.351145
10144 23:19:31.927967 00780000 ################################################################
10145 23:19:31.928117
10146 23:19:32.532312 00800000 ################################################################
10147 23:19:32.532461
10148 23:19:33.114884 00880000 ################################################################
10149 23:19:33.115028
10150 23:19:33.698384 00900000 ################################################################
10151 23:19:33.698530
10152 23:19:34.281957 00980000 ################################################################
10153 23:19:34.282110
10154 23:19:34.842353 00a00000 ################################################################
10155 23:19:34.842504
10156 23:19:35.404776 00a80000 ################################################################
10157 23:19:35.404924
10158 23:19:35.969747 00b00000 ################################################################
10159 23:19:35.969878
10160 23:19:36.529987 00b80000 ################################################################
10161 23:19:36.530119
10162 23:19:37.096881 00c00000 ################################################################
10163 23:19:37.097078
10164 23:19:37.655593 00c80000 ################################################################
10165 23:19:37.655729
10166 23:19:38.196059 00d00000 ################################################################
10167 23:19:38.196246
10168 23:19:38.738462 00d80000 ################################################################
10169 23:19:38.738673
10170 23:19:39.281967 00e00000 ################################################################
10171 23:19:39.282101
10172 23:19:39.833790 00e80000 ################################################################
10173 23:19:39.833953
10174 23:19:40.384676 00f00000 ################################################################
10175 23:19:40.384842
10176 23:19:40.936635 00f80000 ################################################################
10177 23:19:40.936786
10178 23:19:41.493003 01000000 ################################################################
10179 23:19:41.493146
10180 23:19:42.034569 01080000 ################################################################
10181 23:19:42.034727
10182 23:19:42.566154 01100000 ################################################################
10183 23:19:42.566298
10184 23:19:43.124076 01180000 ################################################################
10185 23:19:43.124240
10186 23:19:43.666111 01200000 ################################################################
10187 23:19:43.666298
10188 23:19:44.219342 01280000 ################################################################
10189 23:19:44.219548
10190 23:19:44.773941 01300000 ################################################################
10191 23:19:44.774108
10192 23:19:45.318219 01380000 ################################################################
10193 23:19:45.318397
10194 23:19:45.886636 01400000 ################################################################
10195 23:19:45.886793
10196 23:19:46.452544 01480000 ################################################################
10197 23:19:46.452698
10198 23:19:46.998281 01500000 ################################################################
10199 23:19:46.998467
10200 23:19:47.560160 01580000 ################################################################
10201 23:19:47.560313
10202 23:19:48.128536 01600000 ################################################################
10203 23:19:48.128686
10204 23:19:48.685084 01680000 ################################################################
10205 23:19:48.685224
10206 23:19:49.264282 01700000 ################################################################
10207 23:19:49.264429
10208 23:19:49.857318 01780000 ################################################################
10209 23:19:49.857468
10210 23:19:50.442741 01800000 ################################################################
10211 23:19:50.442893
10212 23:19:51.028433 01880000 ################################################################
10213 23:19:51.028635
10214 23:19:51.603754 01900000 ################################################################
10215 23:19:51.603905
10216 23:19:52.160087 01980000 ################################################################
10217 23:19:52.160238
10218 23:19:52.711662 01a00000 ################################################################
10219 23:19:52.711816
10220 23:19:53.256259 01a80000 ################################################################
10221 23:19:53.256409
10222 23:19:53.816526 01b00000 ################################################################
10223 23:19:53.816722
10224 23:19:54.376208 01b80000 ################################################################
10225 23:19:54.376420
10226 23:19:54.931174 01c00000 ################################################################
10227 23:19:54.931394
10228 23:19:55.496073 01c80000 ################################################################
10229 23:19:55.496222
10230 23:19:56.065650 01d00000 ################################################################
10231 23:19:56.065793
10232 23:19:56.625477 01d80000 ################################################################
10233 23:19:56.625653
10234 23:19:56.895453 01e00000 ################################# done.
10235 23:19:56.895601
10236 23:19:56.898470 The bootfile was 31723638 bytes long.
10237 23:19:56.898582
10238 23:19:56.902048 Sending tftp read request... done.
10239 23:19:56.902198
10240 23:19:56.902308 Waiting for the transfer...
10241 23:19:56.902375
10242 23:19:56.905868 00000000 # done.
10243 23:19:56.905958
10244 23:19:56.911922 Command line loaded dynamically from TFTP file: 13248440/tftp-deploy-tcaniien/kernel/cmdline
10245 23:19:56.912007
10246 23:19:56.935137 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248440/extract-nfsrootfs-5ayrqzms,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10247 23:19:56.935261
10248 23:19:56.935342 Loading FIT.
10249 23:19:56.935422
10250 23:19:56.938262 Image ramdisk-1 has 18767102 bytes.
10251 23:19:56.938346
10252 23:19:56.941613 Image fdt-1 has 47230 bytes.
10253 23:19:56.941702
10254 23:19:56.944586 Image kernel-1 has 12907270 bytes.
10255 23:19:56.944666
10256 23:19:56.954578 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10257 23:19:56.954668
10258 23:19:56.971000 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10259 23:19:56.971120
10260 23:19:56.978155 Choosing best match conf-1 for compat google,spherion-rev2.
10261 23:19:56.978243
10262 23:19:56.985718 Connected to device vid:did:rid of 1ae0:0028:00
10263 23:19:56.993264
10264 23:19:56.996014 tpm_get_response: command 0x17b, return code 0x0
10265 23:19:56.996095
10266 23:19:56.999241 ec_init: CrosEC protocol v3 supported (256, 248)
10267 23:19:57.003209
10268 23:19:57.006676 tpm_cleanup: add release locality here.
10269 23:19:57.006767
10270 23:19:57.006836 Shutting down all USB controllers.
10271 23:19:57.009957
10272 23:19:57.010044 Removing current net device
10273 23:19:57.010111
10274 23:19:57.016407 Exiting depthcharge with code 4 at timestamp: 69951430
10275 23:19:57.016496
10276 23:19:57.019783 LZMA decompressing kernel-1 to 0x821a6718
10277 23:19:57.019870
10278 23:19:57.023288 LZMA decompressing kernel-1 to 0x40000000
10279 23:19:58.616307
10280 23:19:58.616491 jumping to kernel
10281 23:19:58.616971 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10282 23:19:58.617089 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10283 23:19:58.617206 Setting prompt string to ['Linux version [0-9]']
10284 23:19:58.617306 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10285 23:19:58.617396 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10286 23:19:58.698686
10287 23:19:58.702206 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10288 23:19:58.705590 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10289 23:19:58.705716 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10290 23:19:58.705821 Setting prompt string to []
10291 23:19:58.705938 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10292 23:19:58.706059 Using line separator: #'\n'#
10293 23:19:58.706152 No login prompt set.
10294 23:19:58.706257 Parsing kernel messages
10295 23:19:58.706319 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10296 23:19:58.706424 [login-action] Waiting for messages, (timeout 00:03:43)
10297 23:19:58.706514 Waiting using forced prompt support (timeout 00:01:51)
10298 23:19:58.725081 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10299 23:19:58.728193 [ 0.000000] random: crng init done
10300 23:19:58.734840 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10301 23:19:58.737894 [ 0.000000] efi: UEFI not found.
10302 23:19:58.744738 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10303 23:19:58.755107 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10304 23:19:58.764432 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10305 23:19:58.770857 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10306 23:19:58.777562 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10307 23:19:58.783875 [ 0.000000] printk: bootconsole [mtk8250] enabled
10308 23:19:58.790702 [ 0.000000] NUMA: No NUMA configuration found
10309 23:19:58.797028 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10310 23:19:58.803856 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10311 23:19:58.804003 [ 0.000000] Zone ranges:
10312 23:19:58.810363 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10313 23:19:58.813675 [ 0.000000] DMA32 empty
10314 23:19:58.820355 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10315 23:19:58.823484 [ 0.000000] Movable zone start for each node
10316 23:19:58.826749 [ 0.000000] Early memory node ranges
10317 23:19:58.833688 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10318 23:19:58.840418 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10319 23:19:58.847080 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10320 23:19:58.853449 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10321 23:19:58.859956 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10322 23:19:58.866992 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10323 23:19:58.923473 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10324 23:19:58.929915 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10325 23:19:58.936537 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10326 23:19:58.940127 [ 0.000000] psci: probing for conduit method from DT.
10327 23:19:58.946755 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10328 23:19:58.949955 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10329 23:19:58.956527 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10330 23:19:58.959777 [ 0.000000] psci: SMC Calling Convention v1.2
10331 23:19:58.966025 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10332 23:19:58.969627 [ 0.000000] Detected VIPT I-cache on CPU0
10333 23:19:58.976318 [ 0.000000] CPU features: detected: GIC system register CPU interface
10334 23:19:58.982553 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10335 23:19:58.989183 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10336 23:19:58.995633 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10337 23:19:59.002883 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10338 23:19:59.012703 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10339 23:19:59.015506 [ 0.000000] alternatives: applying boot alternatives
10340 23:19:59.022244 [ 0.000000] Fallback order for Node 0: 0
10341 23:19:59.028918 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10342 23:19:59.032624 [ 0.000000] Policy zone: Normal
10343 23:19:59.055243 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248440/extract-nfsrootfs-5ayrqzms,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10344 23:19:59.065169 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10345 23:19:59.075881 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10346 23:19:59.085968 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10347 23:19:59.092123 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10348 23:19:59.095704 <6>[ 0.000000] software IO TLB: area num 8.
10349 23:19:59.152201 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10350 23:19:59.302390 <6>[ 0.000000] Memory: 7946240K/8385536K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 406528K reserved, 32768K cma-reserved)
10351 23:19:59.308136 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10352 23:19:59.314922 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10353 23:19:59.318455 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10354 23:19:59.324835 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10355 23:19:59.331282 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10356 23:19:59.334539 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10357 23:19:59.344533 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10358 23:19:59.351309 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10359 23:19:59.357746 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10360 23:19:59.364752 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10361 23:19:59.367889 <6>[ 0.000000] GICv3: 608 SPIs implemented
10362 23:19:59.370880 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10363 23:19:59.378026 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10364 23:19:59.381389 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10365 23:19:59.387758 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10366 23:19:59.400941 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10367 23:19:59.414257 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10368 23:19:59.420447 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10369 23:19:59.428186 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10370 23:19:59.441534 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10371 23:19:59.447795 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10372 23:19:59.454688 <6>[ 0.009176] Console: colour dummy device 80x25
10373 23:19:59.464374 <6>[ 0.013903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10374 23:19:59.471692 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10375 23:19:59.474639 <6>[ 0.029218] LSM: Security Framework initializing
10376 23:19:59.480816 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10377 23:19:59.491135 <6>[ 0.041973] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10378 23:19:59.500654 <6>[ 0.051397] cblist_init_generic: Setting adjustable number of callback queues.
10379 23:19:59.507373 <6>[ 0.058888] cblist_init_generic: Setting shift to 3 and lim to 1.
10380 23:19:59.514624 <6>[ 0.065227] cblist_init_generic: Setting adjustable number of callback queues.
10381 23:19:59.521220 <6>[ 0.072654] cblist_init_generic: Setting shift to 3 and lim to 1.
10382 23:19:59.523652 <6>[ 0.079054] rcu: Hierarchical SRCU implementation.
10383 23:19:59.530860 <6>[ 0.084101] rcu: Max phase no-delay instances is 1000.
10384 23:19:59.537120 <6>[ 0.091156] EFI services will not be available.
10385 23:19:59.540185 <6>[ 0.096147] smp: Bringing up secondary CPUs ...
10386 23:19:59.549122 <6>[ 0.101227] Detected VIPT I-cache on CPU1
10387 23:19:59.555975 <6>[ 0.101300] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10388 23:19:59.562700 <6>[ 0.101331] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10389 23:19:59.565779 <6>[ 0.101670] Detected VIPT I-cache on CPU2
10390 23:19:59.576326 <6>[ 0.101722] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10391 23:19:59.581985 <6>[ 0.101740] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10392 23:19:59.585414 <6>[ 0.101998] Detected VIPT I-cache on CPU3
10393 23:19:59.591845 <6>[ 0.102045] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10394 23:19:59.598407 <6>[ 0.102058] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10395 23:19:59.604967 <6>[ 0.102360] CPU features: detected: Spectre-v4
10396 23:19:59.608080 <6>[ 0.102367] CPU features: detected: Spectre-BHB
10397 23:19:59.611663 <6>[ 0.102372] Detected PIPT I-cache on CPU4
10398 23:19:59.618572 <6>[ 0.102429] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10399 23:19:59.627934 <6>[ 0.102446] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10400 23:19:59.631225 <6>[ 0.102737] Detected PIPT I-cache on CPU5
10401 23:19:59.637787 <6>[ 0.102800] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10402 23:19:59.644537 <6>[ 0.102816] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10403 23:19:59.647878 <6>[ 0.103094] Detected PIPT I-cache on CPU6
10404 23:19:59.657723 <6>[ 0.103161] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10405 23:19:59.664486 <6>[ 0.103177] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10406 23:19:59.667740 <6>[ 0.103471] Detected PIPT I-cache on CPU7
10407 23:19:59.674551 <6>[ 0.103536] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10408 23:19:59.680732 <6>[ 0.103552] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10409 23:19:59.684104 <6>[ 0.103600] smp: Brought up 1 node, 8 CPUs
10410 23:19:59.690666 <6>[ 0.244952] SMP: Total of 8 processors activated.
10411 23:19:59.697649 <6>[ 0.249874] CPU features: detected: 32-bit EL0 Support
10412 23:19:59.703955 <6>[ 0.255237] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10413 23:19:59.710435 <6>[ 0.264037] CPU features: detected: Common not Private translations
10414 23:19:59.717220 <6>[ 0.270513] CPU features: detected: CRC32 instructions
10415 23:19:59.723854 <6>[ 0.275897] CPU features: detected: RCpc load-acquire (LDAPR)
10416 23:19:59.726936 <6>[ 0.281857] CPU features: detected: LSE atomic instructions
10417 23:19:59.733713 <6>[ 0.287675] CPU features: detected: Privileged Access Never
10418 23:19:59.740944 <6>[ 0.293454] CPU features: detected: RAS Extension Support
10419 23:19:59.746733 <6>[ 0.299098] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10420 23:19:59.750001 <6>[ 0.306317] CPU: All CPU(s) started at EL2
10421 23:19:59.756370 <6>[ 0.310634] alternatives: applying system-wide alternatives
10422 23:19:59.767375 <6>[ 0.321440] devtmpfs: initialized
10423 23:19:59.779119 <6>[ 0.330438] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10424 23:19:59.788970 <6>[ 0.340393] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10425 23:19:59.795620 <6>[ 0.348616] pinctrl core: initialized pinctrl subsystem
10426 23:19:59.799067 <6>[ 0.355293] DMI not present or invalid.
10427 23:19:59.805522 <6>[ 0.359707] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10428 23:19:59.815474 <6>[ 0.366603] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10429 23:19:59.822297 <6>[ 0.374184] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10430 23:19:59.832821 <6>[ 0.382412] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10431 23:19:59.835627 <6>[ 0.390652] audit: initializing netlink subsys (disabled)
10432 23:19:59.845029 <5>[ 0.396347] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10433 23:19:59.852058 <6>[ 0.397064] thermal_sys: Registered thermal governor 'step_wise'
10434 23:19:59.858343 <6>[ 0.404312] thermal_sys: Registered thermal governor 'power_allocator'
10435 23:19:59.861969 <6>[ 0.410567] cpuidle: using governor menu
10436 23:19:59.868452 <6>[ 0.421525] NET: Registered PF_QIPCRTR protocol family
10437 23:19:59.875184 <6>[ 0.427020] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10438 23:19:59.881365 <6>[ 0.434124] ASID allocator initialised with 32768 entries
10439 23:19:59.884688 <6>[ 0.440697] Serial: AMBA PL011 UART driver
10440 23:19:59.894711 <4>[ 0.449566] Trying to register duplicate clock ID: 134
10441 23:19:59.951498 <6>[ 0.509390] KASLR enabled
10442 23:19:59.965738 <6>[ 0.517129] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10443 23:19:59.972583 <6>[ 0.524140] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10444 23:19:59.979110 <6>[ 0.530630] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10445 23:19:59.985755 <6>[ 0.537635] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10446 23:19:59.992129 <6>[ 0.544121] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10447 23:19:59.998626 <6>[ 0.551126] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10448 23:20:00.005461 <6>[ 0.557615] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10449 23:20:00.011934 <6>[ 0.564617] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10450 23:20:00.015396 <6>[ 0.572108] ACPI: Interpreter disabled.
10451 23:20:00.024379 <6>[ 0.578591] iommu: Default domain type: Translated
10452 23:20:00.030514 <6>[ 0.583738] iommu: DMA domain TLB invalidation policy: strict mode
10453 23:20:00.034422 <5>[ 0.590398] SCSI subsystem initialized
10454 23:20:00.040758 <6>[ 0.594646] usbcore: registered new interface driver usbfs
10455 23:20:00.047172 <6>[ 0.600378] usbcore: registered new interface driver hub
10456 23:20:00.050311 <6>[ 0.605930] usbcore: registered new device driver usb
10457 23:20:00.058037 <6>[ 0.612053] pps_core: LinuxPPS API ver. 1 registered
10458 23:20:00.067463 <6>[ 0.617247] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10459 23:20:00.070590 <6>[ 0.626590] PTP clock support registered
10460 23:20:00.073720 <6>[ 0.630828] EDAC MC: Ver: 3.0.0
10461 23:20:00.081474 <6>[ 0.636031] FPGA manager framework
10462 23:20:00.088027 <6>[ 0.639709] Advanced Linux Sound Architecture Driver Initialized.
10463 23:20:00.091261 <6>[ 0.646493] vgaarb: loaded
10464 23:20:00.097824 <6>[ 0.649675] clocksource: Switched to clocksource arch_sys_counter
10465 23:20:00.101511 <5>[ 0.656125] VFS: Disk quotas dquot_6.6.0
10466 23:20:00.108014 <6>[ 0.660311] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10467 23:20:00.111236 <6>[ 0.667501] pnp: PnP ACPI: disabled
10468 23:20:00.119473 <6>[ 0.674156] NET: Registered PF_INET protocol family
10469 23:20:00.129330 <6>[ 0.679748] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10470 23:20:00.140827 <6>[ 0.692050] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10471 23:20:00.150768 <6>[ 0.700869] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10472 23:20:00.157336 <6>[ 0.708837] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10473 23:20:00.167678 <6>[ 0.717535] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10474 23:20:00.173871 <6>[ 0.727260] TCP: Hash tables configured (established 65536 bind 65536)
10475 23:20:00.179805 <6>[ 0.734133] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10476 23:20:00.190377 <6>[ 0.741331] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10477 23:20:00.196719 <6>[ 0.749038] NET: Registered PF_UNIX/PF_LOCAL protocol family
10478 23:20:00.203355 <6>[ 0.755182] RPC: Registered named UNIX socket transport module.
10479 23:20:00.206472 <6>[ 0.761335] RPC: Registered udp transport module.
10480 23:20:00.212999 <6>[ 0.766267] RPC: Registered tcp transport module.
10481 23:20:00.219578 <6>[ 0.771198] RPC: Registered tcp NFSv4.1 backchannel transport module.
10482 23:20:00.222627 <6>[ 0.777861] PCI: CLS 0 bytes, default 64
10483 23:20:00.225945 <6>[ 0.782201] Unpacking initramfs...
10484 23:20:00.250570 <6>[ 0.801791] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10485 23:20:00.260190 <6>[ 0.810460] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10486 23:20:00.263764 <6>[ 0.819301] kvm [1]: IPA Size Limit: 40 bits
10487 23:20:00.270074 <6>[ 0.823831] kvm [1]: GICv3: no GICV resource entry
10488 23:20:00.273493 <6>[ 0.828851] kvm [1]: disabling GICv2 emulation
10489 23:20:00.280075 <6>[ 0.833535] kvm [1]: GIC system register CPU interface enabled
10490 23:20:00.284123 <6>[ 0.839694] kvm [1]: vgic interrupt IRQ18
10491 23:20:00.290340 <6>[ 0.844046] kvm [1]: VHE mode initialized successfully
10492 23:20:00.296946 <5>[ 0.850575] Initialise system trusted keyrings
10493 23:20:00.303620 <6>[ 0.855361] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10494 23:20:00.311160 <6>[ 0.865459] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10495 23:20:00.317748 <5>[ 0.871874] NFS: Registering the id_resolver key type
10496 23:20:00.320711 <5>[ 0.877178] Key type id_resolver registered
10497 23:20:00.327818 <5>[ 0.881595] Key type id_legacy registered
10498 23:20:00.333751 <6>[ 0.885878] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10499 23:20:00.340574 <6>[ 0.892800] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10500 23:20:00.347164 <6>[ 0.900524] 9p: Installing v9fs 9p2000 file system support
10501 23:20:00.383962 <5>[ 0.938525] Key type asymmetric registered
10502 23:20:00.387079 <5>[ 0.942858] Asymmetric key parser 'x509' registered
10503 23:20:00.397029 <6>[ 0.947998] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10504 23:20:00.400201 <6>[ 0.955611] io scheduler mq-deadline registered
10505 23:20:00.403636 <6>[ 0.960372] io scheduler kyber registered
10506 23:20:00.423034 <6>[ 0.977755] EINJ: ACPI disabled.
10507 23:20:00.455930 <4>[ 1.003788] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10508 23:20:00.465641 <4>[ 1.014529] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10509 23:20:00.481028 <6>[ 1.035568] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10510 23:20:00.489146 <6>[ 1.043643] printk: console [ttyS0] disabled
10511 23:20:00.516979 <6>[ 1.068287] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10512 23:20:00.523510 <6>[ 1.077753] printk: console [ttyS0] enabled
10513 23:20:00.527043 <6>[ 1.077753] printk: console [ttyS0] enabled
10514 23:20:00.533351 <6>[ 1.086648] printk: bootconsole [mtk8250] disabled
10515 23:20:00.536800 <6>[ 1.086648] printk: bootconsole [mtk8250] disabled
10516 23:20:00.543493 <6>[ 1.097998] SuperH (H)SCI(F) driver initialized
10517 23:20:00.546571 <6>[ 1.103270] msm_serial: driver initialized
10518 23:20:00.560910 <6>[ 1.112385] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10519 23:20:00.570985 <6>[ 1.120934] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10520 23:20:00.577823 <6>[ 1.129477] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10521 23:20:00.587570 <6>[ 1.138113] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10522 23:20:00.597514 <6>[ 1.146820] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10523 23:20:00.604129 <6>[ 1.155533] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10524 23:20:00.614177 <6>[ 1.164073] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10525 23:20:00.620518 <6>[ 1.172890] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10526 23:20:00.630288 <6>[ 1.181434] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10527 23:20:00.642925 <6>[ 1.197139] loop: module loaded
10528 23:20:00.648884 <6>[ 1.203183] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10529 23:20:00.672112 <4>[ 1.226589] mtk-pmic-keys: Failed to locate of_node [id: -1]
10530 23:20:00.679137 <6>[ 1.233509] megasas: 07.719.03.00-rc1
10531 23:20:00.688477 <6>[ 1.243166] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10532 23:20:00.695200 <6>[ 1.249037] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10533 23:20:00.711343 <6>[ 1.265772] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10534 23:20:00.767273 <6>[ 1.315635] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10535 23:20:01.013347 <6>[ 1.568023] Freeing initrd memory: 18324K
10536 23:20:01.025209 <6>[ 1.579541] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10537 23:20:01.036079 <6>[ 1.590501] tun: Universal TUN/TAP device driver, 1.6
10538 23:20:01.039349 <6>[ 1.596571] thunder_xcv, ver 1.0
10539 23:20:01.042521 <6>[ 1.600076] thunder_bgx, ver 1.0
10540 23:20:01.046032 <6>[ 1.603572] nicpf, ver 1.0
10541 23:20:01.056664 <6>[ 1.607588] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10542 23:20:01.060089 <6>[ 1.615065] hns3: Copyright (c) 2017 Huawei Corporation.
10543 23:20:01.062898 <6>[ 1.620655] hclge is initializing
10544 23:20:01.069495 <6>[ 1.624236] e1000: Intel(R) PRO/1000 Network Driver
10545 23:20:01.076240 <6>[ 1.629366] e1000: Copyright (c) 1999-2006 Intel Corporation.
10546 23:20:01.079879 <6>[ 1.635378] e1000e: Intel(R) PRO/1000 Network Driver
10547 23:20:01.085875 <6>[ 1.640594] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10548 23:20:01.092915 <6>[ 1.646779] igb: Intel(R) Gigabit Ethernet Network Driver
10549 23:20:01.099355 <6>[ 1.652430] igb: Copyright (c) 2007-2014 Intel Corporation.
10550 23:20:01.106056 <6>[ 1.658265] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10551 23:20:01.112871 <6>[ 1.664783] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10552 23:20:01.115845 <6>[ 1.671252] sky2: driver version 1.30
10553 23:20:01.122380 <6>[ 1.676250] VFIO - User Level meta-driver version: 0.3
10554 23:20:01.129775 <6>[ 1.684518] usbcore: registered new interface driver usb-storage
10555 23:20:01.136294 <6>[ 1.690966] usbcore: registered new device driver onboard-usb-hub
10556 23:20:01.145601 <6>[ 1.700112] mt6397-rtc mt6359-rtc: registered as rtc0
10557 23:20:01.155514 <6>[ 1.705577] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:20:02 UTC (1712186402)
10558 23:20:01.158807 <6>[ 1.715140] i2c_dev: i2c /dev entries driver
10559 23:20:01.175515 <6>[ 1.726909] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10560 23:20:01.182423 <4>[ 1.735665] cpu cpu0: supply cpu not found, using dummy regulator
10561 23:20:01.188873 <4>[ 1.742090] cpu cpu1: supply cpu not found, using dummy regulator
10562 23:20:01.195441 <4>[ 1.748497] cpu cpu2: supply cpu not found, using dummy regulator
10563 23:20:01.201769 <4>[ 1.754899] cpu cpu3: supply cpu not found, using dummy regulator
10564 23:20:01.208667 <4>[ 1.761296] cpu cpu4: supply cpu not found, using dummy regulator
10565 23:20:01.215534 <4>[ 1.767713] cpu cpu5: supply cpu not found, using dummy regulator
10566 23:20:01.222024 <4>[ 1.774120] cpu cpu6: supply cpu not found, using dummy regulator
10567 23:20:01.228402 <4>[ 1.780517] cpu cpu7: supply cpu not found, using dummy regulator
10568 23:20:01.247604 <6>[ 1.802155] cpu cpu0: EM: created perf domain
10569 23:20:01.250789 <6>[ 1.807091] cpu cpu4: EM: created perf domain
10570 23:20:01.257958 <6>[ 1.812686] sdhci: Secure Digital Host Controller Interface driver
10571 23:20:01.264493 <6>[ 1.819118] sdhci: Copyright(c) Pierre Ossman
10572 23:20:01.271134 <6>[ 1.824076] Synopsys Designware Multimedia Card Interface Driver
10573 23:20:01.278107 <6>[ 1.830716] sdhci-pltfm: SDHCI platform and OF driver helper
10574 23:20:01.281256 <6>[ 1.830838] mmc0: CQHCI version 5.10
10575 23:20:01.287784 <6>[ 1.841125] ledtrig-cpu: registered to indicate activity on CPUs
10576 23:20:01.294236 <6>[ 1.848156] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10577 23:20:01.301026 <6>[ 1.855219] usbcore: registered new interface driver usbhid
10578 23:20:01.304377 <6>[ 1.861044] usbhid: USB HID core driver
10579 23:20:01.310954 <6>[ 1.865215] spi_master spi0: will run message pump with realtime priority
10580 23:20:01.355372 <6>[ 1.903433] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10581 23:20:01.374630 <6>[ 1.919273] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10582 23:20:01.378224 <6>[ 1.932880] mmc0: Command Queue Engine enabled
10583 23:20:01.385254 <6>[ 1.937646] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10584 23:20:01.391494 <6>[ 1.944565] cros-ec-spi spi0.0: Chrome EC device registered
10585 23:20:01.394719 <6>[ 1.944999] mmcblk0: mmc0:0001 DA4128 116 GiB
10586 23:20:01.404848 <6>[ 1.959633] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10587 23:20:01.412797 <6>[ 1.967068] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10588 23:20:01.419577 <6>[ 1.972965] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10589 23:20:01.425562 <6>[ 1.978966] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10590 23:20:01.435588 <6>[ 1.984625] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10591 23:20:01.442265 <6>[ 1.996144] NET: Registered PF_PACKET protocol family
10592 23:20:01.445436 <6>[ 2.001549] 9pnet: Installing 9P2000 support
10593 23:20:01.452148 <5>[ 2.006117] Key type dns_resolver registered
10594 23:20:01.455567 <6>[ 2.011130] registered taskstats version 1
10595 23:20:01.461960 <5>[ 2.015512] Loading compiled-in X.509 certificates
10596 23:20:01.490729 <4>[ 2.038732] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10597 23:20:01.500630 <4>[ 2.049605] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 23:20:01.507273 <3>[ 2.060159] debugfs: File 'uA_load' in directory '/' already present!
10599 23:20:01.514457 <3>[ 2.066875] debugfs: File 'min_uV' in directory '/' already present!
10600 23:20:01.520655 <3>[ 2.073497] debugfs: File 'max_uV' in directory '/' already present!
10601 23:20:01.527289 <3>[ 2.080110] debugfs: File 'constraint_flags' in directory '/' already present!
10602 23:20:01.538762 <3>[ 2.090225] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10603 23:20:01.555403 <6>[ 2.110331] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10604 23:20:01.562371 <6>[ 2.117160] xhci-mtk 11200000.usb: xHCI Host Controller
10605 23:20:01.568905 <6>[ 2.122662] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10606 23:20:01.579042 <6>[ 2.130537] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10607 23:20:01.585461 <6>[ 2.139987] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10608 23:20:01.592575 <6>[ 2.146097] xhci-mtk 11200000.usb: xHCI Host Controller
10609 23:20:01.598918 <6>[ 2.151586] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10610 23:20:01.605552 <6>[ 2.159248] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10611 23:20:01.612423 <6>[ 2.167084] hub 1-0:1.0: USB hub found
10612 23:20:01.615497 <6>[ 2.171111] hub 1-0:1.0: 1 port detected
10613 23:20:01.625714 <6>[ 2.175452] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10614 23:20:01.629340 <6>[ 2.184285] hub 2-0:1.0: USB hub found
10615 23:20:01.632118 <6>[ 2.188312] hub 2-0:1.0: 1 port detected
10616 23:20:01.641242 <6>[ 2.196217] mtk-msdc 11f70000.mmc: Got CD GPIO
10617 23:20:01.655815 <6>[ 2.207329] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10618 23:20:01.662407 <6>[ 2.215353] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10619 23:20:01.672551 <4>[ 2.223287] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10620 23:20:01.682433 <6>[ 2.232868] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10621 23:20:01.688891 <6>[ 2.240946] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10622 23:20:01.695750 <6>[ 2.248966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10623 23:20:01.705814 <6>[ 2.256889] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10624 23:20:01.712354 <6>[ 2.264707] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10625 23:20:01.722449 <6>[ 2.272523] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10626 23:20:01.732311 <6>[ 2.282996] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10627 23:20:01.738912 <6>[ 2.291356] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10628 23:20:01.748618 <6>[ 2.299706] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10629 23:20:01.755133 <6>[ 2.308044] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10630 23:20:01.764844 <6>[ 2.316382] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10631 23:20:01.774875 <6>[ 2.324719] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10632 23:20:01.781683 <6>[ 2.333057] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10633 23:20:01.791310 <6>[ 2.341394] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10634 23:20:01.798041 <6>[ 2.349732] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10635 23:20:01.807660 <6>[ 2.358070] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10636 23:20:01.814236 <6>[ 2.366407] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10637 23:20:01.824833 <6>[ 2.374745] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10638 23:20:01.831268 <6>[ 2.383082] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10639 23:20:01.841124 <6>[ 2.391420] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10640 23:20:01.848162 <6>[ 2.399758] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10641 23:20:01.854125 <6>[ 2.408481] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10642 23:20:01.860699 <6>[ 2.415640] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10643 23:20:01.867686 <6>[ 2.422420] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10644 23:20:01.877763 <6>[ 2.429196] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10645 23:20:01.884441 <6>[ 2.436137] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10646 23:20:01.891275 <6>[ 2.442982] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10647 23:20:01.901220 <6>[ 2.452112] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10648 23:20:01.910724 <6>[ 2.461231] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10649 23:20:01.920645 <6>[ 2.470524] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10650 23:20:01.930711 <6>[ 2.479991] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10651 23:20:01.940364 <6>[ 2.489457] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10652 23:20:01.947987 <6>[ 2.498578] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10653 23:20:01.957564 <6>[ 2.508050] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10654 23:20:01.966865 <6>[ 2.517169] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10655 23:20:01.977706 <6>[ 2.526464] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10656 23:20:01.986665 <6>[ 2.536627] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10657 23:20:01.996930 <6>[ 2.548106] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10658 23:20:02.003248 <6>[ 2.557849] Trying to probe devices needed for running init ...
10659 23:20:02.046593 <6>[ 2.597947] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10660 23:20:02.200571 <6>[ 2.755517] hub 1-1:1.0: USB hub found
10661 23:20:02.203862 <6>[ 2.760050] hub 1-1:1.0: 4 ports detected
10662 23:20:02.213725 <6>[ 2.768764] hub 1-1:1.0: USB hub found
10663 23:20:02.217040 <6>[ 2.773220] hub 1-1:1.0: 4 ports detected
10664 23:20:02.326843 <6>[ 2.878162] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10665 23:20:02.353183 <6>[ 2.907545] hub 2-1:1.0: USB hub found
10666 23:20:02.356092 <6>[ 2.912041] hub 2-1:1.0: 3 ports detected
10667 23:20:02.365380 <6>[ 2.920128] hub 2-1:1.0: USB hub found
10668 23:20:02.368408 <6>[ 2.924573] hub 2-1:1.0: 3 ports detected
10669 23:20:02.538053 <6>[ 3.089829] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10670 23:20:02.671292 <6>[ 3.225847] hub 1-1.4:1.0: USB hub found
10671 23:20:02.674386 <6>[ 3.230511] hub 1-1.4:1.0: 2 ports detected
10672 23:20:02.683594 <6>[ 3.238496] hub 1-1.4:1.0: USB hub found
10673 23:20:02.687103 <6>[ 3.243081] hub 1-1.4:1.0: 2 ports detected
10674 23:20:02.750723 <6>[ 3.302159] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10675 23:20:02.982404 <6>[ 3.533990] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10676 23:20:03.174293 <6>[ 3.725980] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10677 23:20:14.303967 <6>[ 14.863027] ALSA device list:
10678 23:20:14.310243 <6>[ 14.866312] No soundcards found.
10679 23:20:14.318258 <6>[ 14.874269] Freeing unused kernel memory: 8448K
10680 23:20:14.321485 <6>[ 14.879606] Run /init as init process
10681 23:20:14.333402 Loading, please wait...
10682 23:20:14.363229 Starting systemd-udevd version 252.22-1~deb12u1
10683 23:20:14.363389
10684 23:20:14.602863 <6>[ 15.155871] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10685 23:20:14.619025 <3>[ 15.171755] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 23:20:14.625496 <6>[ 15.178639] remoteproc remoteproc0: scp is available
10687 23:20:14.632412 <3>[ 15.181163] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 23:20:14.638669 <6>[ 15.187730] remoteproc remoteproc0: powering up scp
10689 23:20:14.645521 <3>[ 15.193844] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 23:20:14.655573 <6>[ 15.198509] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10691 23:20:14.658570 <6>[ 15.198553] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10692 23:20:14.668242 <6>[ 15.209313] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10693 23:20:14.675543 <3>[ 15.210614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 23:20:14.685052 <3>[ 15.210629] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 23:20:14.691472 <3>[ 15.210633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 23:20:14.698364 <3>[ 15.210638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 23:20:14.708165 <3>[ 15.210642] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 23:20:14.715696 <3>[ 15.210692] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 23:20:14.724421 <3>[ 15.210902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 23:20:14.731668 <3>[ 15.210908] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 23:20:14.741407 <3>[ 15.210912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 23:20:14.747555 <3>[ 15.211516] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 23:20:14.757896 <3>[ 15.211538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 23:20:14.764415 <3>[ 15.211548] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 23:20:14.774324 <3>[ 15.211565] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 23:20:14.781386 <3>[ 15.211576] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 23:20:14.787110 <3>[ 15.211685] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 23:20:14.797491 <6>[ 15.212408] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10709 23:20:14.803937 <4>[ 15.223219] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10710 23:20:14.813768 <6>[ 15.228508] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10711 23:20:14.817393 <6>[ 15.233801] mc: Linux media interface: v0.10
10712 23:20:14.823616 <6>[ 15.234838] usbcore: registered new device driver r8152-cfgselector
10713 23:20:14.830779 <4>[ 15.240908] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10714 23:20:14.841000 <6>[ 15.244682] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10715 23:20:14.847481 <4>[ 15.248521] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10716 23:20:14.853847 <4>[ 15.248521] Fallback method does not support PEC.
10717 23:20:14.861010 <6>[ 15.296479] videodev: Linux video capture interface: v2.00
10718 23:20:14.868194 <6>[ 15.340394] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10719 23:20:14.874134 <6>[ 15.340433] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10720 23:20:14.881252 <6>[ 15.340443] remoteproc remoteproc0: remote processor scp is now up
10721 23:20:14.887971 <6>[ 15.367241] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10722 23:20:14.898040 <6>[ 15.377609] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10723 23:20:14.901423 <6>[ 15.378619] pci_bus 0000:00: root bus resource [bus 00-ff]
10724 23:20:14.911655 <6>[ 15.390471] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10725 23:20:14.918141 <6>[ 15.392302] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10726 23:20:14.927739 <6>[ 15.400792] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10727 23:20:14.938126 <6>[ 15.402275] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10728 23:20:14.944445 <6>[ 15.404021] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10729 23:20:14.954305 <6>[ 15.414410] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10730 23:20:14.960605 <6>[ 15.414452] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10731 23:20:14.970502 <6>[ 15.420496] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10732 23:20:14.980354 <3>[ 15.424898] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10733 23:20:14.987095 <6>[ 15.427351] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10734 23:20:14.996926 <4>[ 15.431403] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10735 23:20:15.003418 <4>[ 15.431415] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10736 23:20:15.013839 <3>[ 15.445329] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10737 23:20:15.016883 <6>[ 15.449480] pci 0000:00:00.0: supports D1 D2
10738 23:20:15.020142 <6>[ 15.464767] Bluetooth: Core ver 2.22
10739 23:20:15.026889 <6>[ 15.472493] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10740 23:20:15.036767 <6>[ 15.473613] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10741 23:20:15.040124 <6>[ 15.481936] NET: Registered PF_BLUETOOTH protocol family
10742 23:20:15.046466 <6>[ 15.485918] r8152 2-1.3:1.0 eth0: v1.12.13
10743 23:20:15.050183 <6>[ 15.485989] usbcore: registered new interface driver r8152
10744 23:20:15.056241 <6>[ 15.489868] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10745 23:20:15.066265 <6>[ 15.491197] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10746 23:20:15.076378 <6>[ 15.492335] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10747 23:20:15.082992 <6>[ 15.492416] usbcore: registered new interface driver uvcvideo
10748 23:20:15.089653 <6>[ 15.497966] Bluetooth: HCI device and connection manager initialized
10749 23:20:15.096451 <6>[ 15.506242] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10750 23:20:15.102688 <6>[ 15.506661] usbcore: registered new interface driver cdc_ether
10751 23:20:15.109059 <6>[ 15.516134] Bluetooth: HCI socket layer initialized
10752 23:20:15.115736 <6>[ 15.516314] usbcore: registered new interface driver r8153_ecm
10753 23:20:15.122354 <6>[ 15.522388] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10754 23:20:15.129135 <6>[ 15.525190] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10755 23:20:15.132737 <6>[ 15.531406] Bluetooth: L2CAP socket layer initialized
10756 23:20:15.142177 <6>[ 15.540187] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10757 23:20:15.145628 <6>[ 15.547656] Bluetooth: SCO socket layer initialized
10758 23:20:15.152696 <6>[ 15.548199] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10759 23:20:15.155269 <6>[ 15.556789] pci 0000:01:00.0: supports D1 D2
10760 23:20:15.162267 <6>[ 15.607349] usbcore: registered new interface driver btusb
10761 23:20:15.171679 <4>[ 15.608315] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10762 23:20:15.178626 <3>[ 15.608322] Bluetooth: hci0: Failed to load firmware file (-2)
10763 23:20:15.185261 <3>[ 15.608324] Bluetooth: hci0: Failed to set up firmware (-2)
10764 23:20:15.195110 <4>[ 15.608326] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10765 23:20:15.201514 <6>[ 15.612626] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10766 23:20:15.207950 <6>[ 15.625855] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10767 23:20:15.218308 <6>[ 15.770457] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10768 23:20:15.224820 <6>[ 15.778542] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10769 23:20:15.234418 <6>[ 15.786542] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10770 23:20:15.241142 <6>[ 15.794543] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10771 23:20:15.248027 <6>[ 15.802544] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10772 23:20:15.254376 <6>[ 15.810543] pci 0000:00:00.0: PCI bridge to [bus 01]
10773 23:20:15.260985 <6>[ 15.815762] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10774 23:20:15.267316 <6>[ 15.823899] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10775 23:20:15.274312 <6>[ 15.830744] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10776 23:20:15.281310 <6>[ 15.837138] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10777 23:20:15.298063 <5>[ 15.851127] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10778 23:20:15.323711 <5>[ 15.876448] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10779 23:20:15.330081 <5>[ 15.883924] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10780 23:20:15.340081 <4>[ 15.892418] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10781 23:20:15.346995 <6>[ 15.901303] cfg80211: failed to load regulatory.db
10782 23:20:15.393214 <6>[ 15.945988] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10783 23:20:15.399801 <6>[ 15.953491] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10784 23:20:15.424245 <6>[ 15.980155] mt7921e 0000:01:00.0: ASIC revision: 79610010
10785 23:20:15.529965 <6>[ 16.082564] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10786 23:20:15.533611 <6>[ 16.082564]
10787 23:20:15.536536 Begin: Loading essential drivers ... done.
10788 23:20:15.539239 Begin: Running /scripts/init-premount ... done.
10789 23:20:15.546238 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10790 23:20:15.555914 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10791 23:20:15.559328 Device /sys/class/net/enx002432307c7b found
10792 23:20:15.559452 done.
10793 23:20:15.568919 Begin: Waiting up to 180 secs for any network device to become available ... done.
10794 23:20:15.604968 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10795 23:20:15.801040 <6>[ 16.354145] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10796 23:20:16.493431 <6>[ 17.050007] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10797 23:20:16.649539 IP-Config: no response after 2 secs - giving up
10798 23:20:16.655884 IP-Config: enx0<6>[ 17.209976] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10799 23:20:16.662390 02432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10800 23:20:16.665712 ipconfig: wlan0: SIOCGIFINDEX: No such device
10801 23:20:16.702096 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10802 23:20:16.709116 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10803 23:20:16.715234 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10804 23:20:16.722316 host : mt8192-asurada-spherion-r0-cbg-2
10805 23:20:16.728978 domain : lava-rack
10806 23:20:16.735255 rootserver: 192.168.201.1 rootpath:
10807 23:20:16.735405 filename :
10808 23:20:16.840866 done.
10809 23:20:16.848654 Begin: Running /scripts/nfs-bottom ... done.
10810 23:20:16.863168 Begin: Running /scripts/init-bottom ... done.
10811 23:20:18.218267 <6>[ 18.774729] NET: Registered PF_INET6 protocol family
10812 23:20:18.225657 <6>[ 18.781805] Segment Routing with IPv6
10813 23:20:18.229012 <6>[ 18.785763] In-situ OAM (IOAM) with IPv6
10814 23:20:18.402818 <30>[ 18.932921] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10815 23:20:18.409765 <30>[ 18.966123] systemd[1]: Detected architecture arm64.
10816 23:20:18.417950
10817 23:20:18.421144 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10818 23:20:18.421235
10819 23:20:18.421301
10820 23:20:18.442459 <30>[ 18.999342] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10821 23:20:19.457773 <30>[ 20.011207] systemd[1]: Queued start job for default target graphical.target.
10822 23:20:19.505841 <30>[ 20.059154] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10823 23:20:19.512171 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10824 23:20:19.512316
10825 23:20:19.534014 <30>[ 20.087711] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10826 23:20:19.543879 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10827 23:20:19.544042
10828 23:20:19.562025 <30>[ 20.115730] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10829 23:20:19.571987 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10830 23:20:19.572105
10831 23:20:19.590846 <30>[ 20.144157] systemd[1]: Created slice user.slice - User and Session Slice.
10832 23:20:19.597233 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10833 23:20:19.597338
10834 23:20:19.620989 <30>[ 20.170823] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10835 23:20:19.630447 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10836 23:20:19.630568
10837 23:20:19.648274 <30>[ 20.198210] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10838 23:20:19.654889 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10839 23:20:19.655006
10840 23:20:19.682966 <30>[ 20.226630] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10841 23:20:19.693111 <30>[ 20.246535] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10842 23:20:19.699619 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10843 23:20:19.699766
10844 23:20:19.716714 <30>[ 20.270349] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10845 23:20:19.726496 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10846 23:20:19.726644
10847 23:20:19.744972 <30>[ 20.298469] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10848 23:20:19.754902 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10849 23:20:19.755009
10850 23:20:19.769538 <30>[ 20.326062] systemd[1]: Reached target paths.target - Path Units.
10851 23:20:19.776515 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10852 23:20:19.779888
10853 23:20:19.796656 <30>[ 20.350090] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10854 23:20:19.803562 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10855 23:20:19.803723
10856 23:20:19.817211 <30>[ 20.373951] systemd[1]: Reached target slices.target - Slice Units.
10857 23:20:19.827273 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10858 23:20:19.827438
10859 23:20:19.841856 <30>[ 20.398454] systemd[1]: Reached target swap.target - Swaps.
10860 23:20:19.848145 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10861 23:20:19.848288
10862 23:20:19.868880 <30>[ 20.422484] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10863 23:20:19.878938 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10864 23:20:19.879098
10865 23:20:19.897883 <30>[ 20.450448] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10866 23:20:19.906780 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10867 23:20:19.906937
10868 23:20:19.928021 <30>[ 20.481272] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10869 23:20:19.937527 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10870 23:20:19.937744
10871 23:20:19.954159 <30>[ 20.507378] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10872 23:20:19.964327 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10873 23:20:19.964446
10874 23:20:19.981406 <30>[ 20.534613] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10875 23:20:19.988062 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10876 23:20:19.988185
10877 23:20:20.006115 <30>[ 20.559472] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10878 23:20:20.015891 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10879 23:20:20.016048
10880 23:20:20.035437 <30>[ 20.588853] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10881 23:20:20.045175 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10882 23:20:20.045359
10883 23:20:20.061484 <30>[ 20.615133] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10884 23:20:20.071483 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10885 23:20:20.071650
10886 23:20:20.112820 <30>[ 20.666052] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10887 23:20:20.118813 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10888 23:20:20.118957
10889 23:20:20.141001 <30>[ 20.694539] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10890 23:20:20.147749 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10891 23:20:20.147959
10892 23:20:20.173337 <30>[ 20.726800] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10893 23:20:20.179865 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10894 23:20:20.180023
10895 23:20:20.207750 <30>[ 20.754599] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10896 23:20:20.265674 <30>[ 20.818593] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10897 23:20:20.274835 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10898 23:20:20.274959
10899 23:20:20.298009 <30>[ 20.851285] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10900 23:20:20.304124 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10901 23:20:20.304229
10902 23:20:20.329789 <30>[ 20.883462] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10903 23:20:20.336797 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10904 23:20:20.336903
10905 23:20:20.361158 <30>[ 20.914463] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10906 23:20:20.367520 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10907 23:20:20.367692
10908 23:20:20.377537 <6>[ 20.931026] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10909 23:20:20.392348 <30>[ 20.945015] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10910 23:20:20.401229 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10911 23:20:20.401381
10912 23:20:20.421726 <30>[ 20.975499] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10913 23:20:20.428462 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10914 23:20:20.428653
10915 23:20:20.452681 <30>[ 21.006255] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10916 23:20:20.462404 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 21.018874] fuse: init (API version 7.37)
10917 23:20:20.462562 el Module loop...
10918 23:20:20.465723
10919 23:20:20.486797 <30>[ 21.040423] systemd[1]: Starting systemd-journald.service - Journal Service...
10920 23:20:20.493139 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10921 23:20:20.493274
10922 23:20:20.527333 <30>[ 21.080378] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10923 23:20:20.533252 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10924 23:20:20.533421
10925 23:20:20.563569 <30>[ 21.113508] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10926 23:20:20.570145 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10927 23:20:20.570256
10928 23:20:20.595205 <30>[ 21.148667] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10929 23:20:20.605164 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10930 23:20:20.605269
10931 23:20:20.629327 <30>[ 21.182937] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10932 23:20:20.646700 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices..<3>[ 21.197579] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 23:20:20.646823 .
10934 23:20:20.646895
10935 23:20:20.669337 <30>[ 21.222147] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10936 23:20:20.679631 [[0;32m OK [<3>[ 21.231213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 23:20:20.685912 0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10938 23:20:20.686019
10939 23:20:20.700796 <30>[ 21.254420] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10940 23:20:20.710725 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10941 23:20:20.710897
10942 23:20:20.729169 <30>[ 21.282418] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10943 23:20:20.738904 <3>[ 21.284133] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 23:20:20.745833 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10945 23:20:20.745985
10946 23:20:20.765489 <30>[ 21.319088] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10947 23:20:20.775481 <3>[ 21.319566] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 23:20:20.781827 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10949 23:20:20.781953
10950 23:20:20.801937 <30>[ 21.354816] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10951 23:20:20.808234 <3>[ 21.359022] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 23:20:20.818464 <30>[ 21.363232] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10953 23:20:20.825323 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10954 23:20:20.825561
10955 23:20:20.841198 <3>[ 21.394638] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 23:20:20.851343 <30>[ 21.404903] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10957 23:20:20.858642 <30>[ 21.412940] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10958 23:20:20.871762 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 21.425351] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 23:20:20.874950 m_mod.s…e[0m - Load Kernel Module dm_mod.
10960 23:20:20.875106
10961 23:20:20.890763 <30>[ 21.447030] systemd[1]: modprobe@drm.service: Deactivated successfully.
10962 23:20:20.900917 <30>[ 21.454602] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10963 23:20:20.907761 <3>[ 21.457530] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 23:20:20.918920 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10965 23:20:20.919130
10966 23:20:20.939145 <30>[ 21.491801] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10967 23:20:20.945367 <3>[ 21.495080] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 23:20:20.955319 <30>[ 21.500430] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10969 23:20:20.962521 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10970 23:20:20.962609
10971 23:20:20.979792 <3>[ 21.533234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 23:20:20.990700 <30>[ 21.544302] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10973 23:20:20.997193 <30>[ 21.551950] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10974 23:20:21.007366 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10975 23:20:21.007543
10976 23:20:21.026350 <30>[ 21.579912] systemd[1]: modprobe@loop.service: Deactivated successfully.
10977 23:20:21.033124 <30>[ 21.587403] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10978 23:20:21.056708 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Mo<4>[ 21.601611] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10979 23:20:21.056843 dule loop.
10980 23:20:21.056915
10981 23:20:21.063241 <3>[ 21.618050] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10982 23:20:21.074096 <30>[ 21.627743] systemd[1]: Started systemd-journald.service - Journal Service.
10983 23:20:21.080529 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10984 23:20:21.080617
10985 23:20:21.103043 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10986 23:20:21.103172
10987 23:20:21.121947 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10988 23:20:21.122065
10989 23:20:21.142209 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10990 23:20:21.142327
10991 23:20:21.162004 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10992 23:20:21.162128
10993 23:20:21.183563 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10994 23:20:21.183675
10995 23:20:21.240908 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10996 23:20:21.241088
10997 23:20:21.263067 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10998 23:20:21.263241
10999 23:20:21.286084 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11000 23:20:21.286225
11001 23:20:21.314755 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11002 23:20:21.314934
11003 23:20:21.344856 Starting [0;1;39msystemd-sysctl.se…c<46>[ 21.898309] systemd-journald[305]: Received client request to flush runtime journal.
11004 23:20:21.347908 e[0m - Apply Kernel Variables...
11005 23:20:21.348020
11006 23:20:21.378651 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11007 23:20:21.378786
11008 23:20:21.674482 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11009 23:20:21.674682
11010 23:20:21.693168 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11011 23:20:21.693309
11012 23:20:21.714641 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11013 23:20:21.714806
11014 23:20:22.127177 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11015 23:20:22.127452
11016 23:20:22.756693 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11017 23:20:22.756909
11018 23:20:22.773860 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11019 23:20:22.773995
11020 23:20:22.813609 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11021 23:20:22.813794
11022 23:20:22.901826 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11023 23:20:22.901967
11024 23:20:22.921160 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11025 23:20:22.921254
11026 23:20:22.936206 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11027 23:20:22.936331
11028 23:20:22.997293 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11029 23:20:22.997415
11030 23:20:23.024633 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11031 23:20:23.024749
11032 23:20:23.283914 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11033 23:20:23.284129
11034 23:20:23.339077 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11035 23:20:23.339260
11036 23:20:23.392123 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11037 23:20:23.392298
11038 23:20:23.646433 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11039 23:20:23.646623
11040 23:20:23.702224 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11041 23:20:23.702346
11042 23:20:23.750519 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11043 23:20:23.750656
11044 23:20:23.792025 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11045 23:20:23.792194
11046 23:20:23.827219 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11047 23:20:23.827368
11048 23:20:23.871323 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11049 23:20:23.871470
11050 23:20:23.920667 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11051 23:20:23.920817
11052 23:20:23.936529 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11053 23:20:23.936628
11054 23:20:23.985200 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11055 23:20:23.985394
11056 23:20:24.008989 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11057 23:20:24.009145
11058 23:20:24.045725 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11059 23:20:24.045872
11060 23:20:24.083965 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11061 23:20:24.084107
11062 23:20:24.100896 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11063 23:20:24.100995
11064 23:20:24.135770 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11065 23:20:24.135876
11066 23:20:24.153161 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11067 23:20:24.153253
11068 23:20:24.159629 <46>[ 24.714391] systemd-journald[305]: Time jumped backwards, rotating.
11069 23:20:24.176587 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11070 23:20:24.176748
11071 23:20:24.192288 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11072 23:20:24.192437
11073 23:20:24.215707 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11074 23:20:24.215846
11075 23:20:24.240087 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11076 23:20:24.240220
11077 23:20:24.256758 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11078 23:20:24.256916
11079 23:20:24.603190 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11080 23:20:24.603383
11081 23:20:24.961032 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11082 23:20:24.961205
11083 23:20:24.981047 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11084 23:20:24.981145
11085 23:20:25.246754 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11086 23:20:25.246924
11087 23:20:25.264456 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11088 23:20:25.264610
11089 23:20:25.280960 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11090 23:20:25.281108
11091 23:20:25.330199 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11092 23:20:25.333032
11093 23:20:25.705136 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11094 23:20:25.705357
11095 23:20:25.800802 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11096 23:20:25.801025
11097 23:20:25.826370 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11098 23:20:25.826505
11099 23:20:25.956362 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11100 23:20:25.956579
11101 23:20:26.017287 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11102 23:20:26.017479
11103 23:20:26.084762 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11104 23:20:26.084986
11105 23:20:26.096321 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11106 23:20:26.096423
11107 23:20:26.112664 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11108 23:20:26.112764
11109 23:20:26.151655 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11110 23:20:26.151765
11111 23:20:26.173796 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11112 23:20:26.173904
11113 23:20:26.207669 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11114 23:20:26.207851
11115 23:20:26.225042 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11116 23:20:26.225138
11117 23:20:26.284399 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11118 23:20:26.284536
11119 23:20:26.309421 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11120 23:20:26.309547
11121 23:20:26.352699 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11122 23:20:26.352804
11123 23:20:26.444676 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11124 23:20:26.444820
11125 23:20:26.530895
11126 23:20:26.531043
11127 23:20:26.534379 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11128 23:20:26.534457
11129 23:20:26.537025 debian-bookworm-arm64 login: root (automatic login)
11130 23:20:26.537153
11131 23:20:26.537259
11132 23:20:26.853859 Linux debian-bookworm-arm64 6.1.83-cip18 #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024 aarch64
11133 23:20:26.854003
11134 23:20:26.860757 The programs included with the Debian GNU/Linux system are free software;
11135 23:20:26.866762 the exact distribution terms for each program are described in the
11136 23:20:26.870287 individual files in /usr/share/doc/*/copyright.
11137 23:20:26.870379
11138 23:20:26.876678 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11139 23:20:26.879878 permitted by applicable law.
11140 23:20:27.926539 Matched prompt #10: / #
11142 23:20:27.926843 Setting prompt string to ['/ #']
11143 23:20:27.926937 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11145 23:20:27.927133 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11146 23:20:27.927220 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11147 23:20:27.927290 Setting prompt string to ['/ #']
11148 23:20:27.927351 Forcing a shell prompt, looking for ['/ #']
11150 23:20:27.977621 / #
11151 23:20:27.977772 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11152 23:20:27.977853 Waiting using forced prompt support (timeout 00:02:30)
11153 23:20:27.982250
11154 23:20:27.982527 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11155 23:20:27.982657 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11157 23:20:28.083058 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248440/extract-nfsrootfs-5ayrqzms'
11158 23:20:28.088769 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248440/extract-nfsrootfs-5ayrqzms'
11160 23:20:28.189323 / # export NFS_SERVER_IP='192.168.201.1'
11161 23:20:28.194366 export NFS_SERVER_IP='192.168.201.1'
11162 23:20:28.194659 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11163 23:20:28.194759 end: 2.2 depthcharge-retry (duration 00:01:47) [common]
11164 23:20:28.194851 end: 2 depthcharge-action (duration 00:01:47) [common]
11165 23:20:28.194991 start: 3 lava-test-retry (timeout 00:07:29) [common]
11166 23:20:28.195104 start: 3.1 lava-test-shell (timeout 00:07:29) [common]
11167 23:20:28.195211 Using namespace: common
11169 23:20:28.295659 / # #
11170 23:20:28.295822 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11171 23:20:28.300408 #
11172 23:20:28.300672 Using /lava-13248440
11174 23:20:28.400988 / # export SHELL=/bin/bash
11175 23:20:28.406223 export SHELL=/bin/bash
11177 23:20:28.506878 / # . /lava-13248440/environment
11178 23:20:28.511710 . /lava-13248440/environment
11180 23:20:28.617526 / # /lava-13248440/bin/lava-test-runner /lava-13248440/0
11181 23:20:28.617735 Test shell timeout: 10s (minimum of the action and connection timeout)
11182 23:20:28.622427 /lava-13248440/bin/lava-test-runner /lava-13248440/0
11183 23:20:28.874182 + export TESTRUN_ID=0_timesync-off
11184 23:20:28.877448 + TESTRUN_ID=0_timesync-off
11185 23:20:28.880654 + cd /lava-13248440/0/tests/0_timesync-off
11186 23:20:28.883726 ++ cat uuid
11187 23:20:28.888410 + UUID=13248440_1.6.2.3.1
11188 23:20:28.888515 + set +x
11189 23:20:28.894625 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13248440_1.6.2.3.1>
11190 23:20:28.894935 Received signal: <STARTRUN> 0_timesync-off 13248440_1.6.2.3.1
11191 23:20:28.895012 Starting test lava.0_timesync-off (13248440_1.6.2.3.1)
11192 23:20:28.895100 Skipping test definition patterns.
11193 23:20:28.897595 + systemctl stop systemd-timesyncd
11194 23:20:28.973580 + set +x
11195 23:20:28.976807 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13248440_1.6.2.3.1>
11196 23:20:28.977073 Received signal: <ENDRUN> 0_timesync-off 13248440_1.6.2.3.1
11197 23:20:28.977157 Ending use of test pattern.
11198 23:20:28.977219 Ending test lava.0_timesync-off (13248440_1.6.2.3.1), duration 0.08
11200 23:20:29.055873 + export TESTRUN_ID=1_kselftest-arm64
11201 23:20:29.056018 + TESTRUN_ID=1_kselftest-arm64
11202 23:20:29.062316 + cd /lava-13248440/0/tests/1_kselftest-arm64
11203 23:20:29.062401 ++ cat uuid
11204 23:20:29.067074 + UUID=13248440_1.6.2.3.5
11205 23:20:29.067185 + set +x
11206 23:20:29.074195 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 13248440_1.6.2.3.5>
11207 23:20:29.074485 Received signal: <STARTRUN> 1_kselftest-arm64 13248440_1.6.2.3.5
11208 23:20:29.074586 Starting test lava.1_kselftest-arm64 (13248440_1.6.2.3.5)
11209 23:20:29.074707 Skipping test definition patterns.
11210 23:20:29.076972 + cd ./automated/linux/kselftest/
11211 23:20:29.103548 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11212 23:20:29.149396 INFO: install_deps skipped
11213 23:20:29.647621 --2024-04-03 23:20:29-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11214 23:20:29.660616 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11215 23:20:29.789378 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11216 23:20:29.918041 HTTP request sent, awaiting response... 200 OK
11217 23:20:29.921377 Length: 1651420 (1.6M) [application/octet-stream]
11218 23:20:29.924591 Saving to: 'kselftest_armhf.tar.gz'
11219 23:20:29.924674
11220 23:20:29.924740
11221 23:20:30.176501 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11222 23:20:30.433745 kselftest_armhf.tar 2%[ ] 47.81K 186KB/s
11223 23:20:30.869662 kselftest_armhf.tar 13%[=> ] 217.50K 422KB/s
11224 23:20:30.876520 kselftest_armhf.tar 50%[=========> ] 811.40K 853KB/s
11225 23:20:30.882746 kselftest_armhf.tar 100%[===================>] 1.57M 1.64MB/s in 1.0s
11226 23:20:30.882834
11227 23:20:31.030389 2024-04-03 23:20:30 (1.64 MB/s) - 'kselftest_armhf.tar.gz' saved [1651420/1651420]
11228 23:20:31.030617
11229 23:20:35.874867 skiplist:
11230 23:20:35.878189 ========================================
11231 23:20:35.881630 ========================================
11232 23:20:35.935390 arm64:tags_test
11233 23:20:35.938560 arm64:run_tags_test.sh
11234 23:20:35.938734 arm64:fake_sigreturn_bad_magic
11235 23:20:35.942332 arm64:fake_sigreturn_bad_size
11236 23:20:35.945563 arm64:fake_sigreturn_bad_size_for_magic0
11237 23:20:35.948491 arm64:fake_sigreturn_duplicated_fpsimd
11238 23:20:35.951654 arm64:fake_sigreturn_misaligned_sp
11239 23:20:35.955204 arm64:fake_sigreturn_missing_fpsimd
11240 23:20:35.958542 arm64:fake_sigreturn_sme_change_vl
11241 23:20:35.961767 arm64:fake_sigreturn_sve_change_vl
11242 23:20:35.965111 arm64:mangle_pstate_invalid_compat_toggle
11243 23:20:35.968445 arm64:mangle_pstate_invalid_daif_bits
11244 23:20:35.971581 arm64:mangle_pstate_invalid_mode_el1h
11245 23:20:35.975222 arm64:mangle_pstate_invalid_mode_el1t
11246 23:20:35.979146 arm64:mangle_pstate_invalid_mode_el2h
11247 23:20:35.981419 arm64:mangle_pstate_invalid_mode_el2t
11248 23:20:35.985173 arm64:mangle_pstate_invalid_mode_el3h
11249 23:20:35.991338 arm64:mangle_pstate_invalid_mode_el3t
11250 23:20:35.991485 arm64:sme_trap_no_sm
11251 23:20:35.994593 arm64:sme_trap_non_streaming
11252 23:20:35.994687 arm64:sme_trap_za
11253 23:20:35.997880 arm64:sme_vl
11254 23:20:35.997971 arm64:ssve_regs
11255 23:20:36.001667 arm64:sve_regs
11256 23:20:36.001763 arm64:sve_vl
11257 23:20:36.001831 arm64:za_no_regs
11258 23:20:36.005020 arm64:za_regs
11259 23:20:36.005117 arm64:pac
11260 23:20:36.008049 arm64:fp-stress
11261 23:20:36.008139 arm64:sve-ptrace
11262 23:20:36.011425 arm64:sve-probe-vls
11263 23:20:36.011516 arm64:vec-syscfg
11264 23:20:36.011585 arm64:za-fork
11265 23:20:36.015483 arm64:za-ptrace
11266 23:20:36.017684 arm64:check_buffer_fill
11267 23:20:36.017772 arm64:check_child_memory
11268 23:20:36.021383 arm64:check_gcr_el1_cswitch
11269 23:20:36.024435 arm64:check_ksm_options
11270 23:20:36.024529 arm64:check_mmap_options
11271 23:20:36.027983 arm64:check_prctl
11272 23:20:36.031055 arm64:check_tags_inclusion
11273 23:20:36.031156 arm64:check_user_mem
11274 23:20:36.034138 arm64:btitest
11275 23:20:36.034232 arm64:nobtitest
11276 23:20:36.034300 arm64:hwcap
11277 23:20:36.037875 arm64:ptrace
11278 23:20:36.037965 arm64:syscall-abi
11279 23:20:36.041206 arm64:tpidr2
11280 23:20:36.044696 ============== Tests to run ===============
11281 23:20:36.044793 arm64:tags_test
11282 23:20:36.047398 arm64:run_tags_test.sh
11283 23:20:36.050654 arm64:fake_sigreturn_bad_magic
11284 23:20:36.054001 arm64:fake_sigreturn_bad_size
11285 23:20:36.057551 arm64:fake_sigreturn_bad_size_for_magic0
11286 23:20:36.060939 arm64:fake_sigreturn_duplicated_fpsimd
11287 23:20:36.064181 arm64:fake_sigreturn_misaligned_sp
11288 23:20:36.067368 arm64:fake_sigreturn_missing_fpsimd
11289 23:20:36.070644 arm64:fake_sigreturn_sme_change_vl
11290 23:20:36.073969 arm64:fake_sigreturn_sve_change_vl
11291 23:20:36.077035 arm64:mangle_pstate_invalid_compat_toggle
11292 23:20:36.080909 arm64:mangle_pstate_invalid_daif_bits
11293 23:20:36.084260 arm64:mangle_pstate_invalid_mode_el1h
11294 23:20:36.086888 arm64:mangle_pstate_invalid_mode_el1t
11295 23:20:36.090423 arm64:mangle_pstate_invalid_mode_el2h
11296 23:20:36.093689 arm64:mangle_pstate_invalid_mode_el2t
11297 23:20:36.096941 arm64:mangle_pstate_invalid_mode_el3h
11298 23:20:36.100184 arm64:mangle_pstate_invalid_mode_el3t
11299 23:20:36.100296 arm64:sme_trap_no_sm
11300 23:20:36.103579 arm64:sme_trap_non_streaming
11301 23:20:36.107395 arm64:sme_trap_za
11302 23:20:36.107553 arm64:sme_vl
11303 23:20:36.110026 arm64:ssve_regs
11304 23:20:36.110164 arm64:sve_regs
11305 23:20:36.110287 arm64:sve_vl
11306 23:20:36.113339 arm64:za_no_regs
11307 23:20:36.113482 arm64:za_regs
11308 23:20:36.113603 arm64:pac
11309 23:20:36.116865 arm64:fp-stress
11310 23:20:36.117011 arm64:sve-ptrace
11311 23:20:36.119997 arm64:sve-probe-vls
11312 23:20:36.120132 arm64:vec-syscfg
11313 23:20:36.123895 arm64:za-fork
11314 23:20:36.124042 arm64:za-ptrace
11315 23:20:36.126651 arm64:check_buffer_fill
11316 23:20:36.129885 arm64:check_child_memory
11317 23:20:36.130016 arm64:check_gcr_el1_cswitch
11318 23:20:36.133078 arm64:check_ksm_options
11319 23:20:36.136326 arm64:check_mmap_options
11320 23:20:36.136452 arm64:check_prctl
11321 23:20:36.139899 arm64:check_tags_inclusion
11322 23:20:36.143009 arm64:check_user_mem
11323 23:20:36.143136 arm64:btitest
11324 23:20:36.143233 arm64:nobtitest
11325 23:20:36.146654 arm64:hwcap
11326 23:20:36.146753 arm64:ptrace
11327 23:20:36.149595 arm64:syscall-abi
11328 23:20:36.149705 arm64:tpidr2
11329 23:20:36.152864 ===========End Tests to run ===============
11330 23:20:36.156363 shardfile-arm64 pass
11331 23:20:36.383493 <12>[ 36.941735] kselftest: Running tests in arm64
11332 23:20:36.393320 TAP version 13
11333 23:20:36.408539 1..48
11334 23:20:36.428260 # selftests: arm64: tags_test
11335 23:20:36.898861 ok 1 selftests: arm64: tags_test
11336 23:20:36.917785 # selftests: arm64: run_tags_test.sh
11337 23:20:36.984805 # --------------------
11338 23:20:36.988102 # running tags test
11339 23:20:36.988225 # --------------------
11340 23:20:36.991384 # [PASS]
11341 23:20:36.994395 ok 2 selftests: arm64: run_tags_test.sh
11342 23:20:37.010751 # selftests: arm64: fake_sigreturn_bad_magic
11343 23:20:37.057455 # Registered handlers for all signals.
11344 23:20:37.057642 # Detected MINSTKSIGSZ:4720
11345 23:20:37.060607 # Testcase initialized.
11346 23:20:37.064005 # uc context validated.
11347 23:20:37.067076 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11348 23:20:37.070838 # Handled SIG_COPYCTX
11349 23:20:37.070989 # Available space:3568
11350 23:20:37.078013 # Using badly built context - ERR: BAD MAGIC !
11351 23:20:37.084213 # SIG_OK -- SP:0xFFFFC1F7CEE0 si_addr@:0xffffc1f7cee0 si_code:2 token@:0xffffc1f7bc80 offset:-4704
11352 23:20:37.087037 # ==>> completed. PASS(1)
11353 23:20:37.093658 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11354 23:20:37.100068 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC1F7BC80
11355 23:20:37.106796 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11356 23:20:37.110144 # selftests: arm64: fake_sigreturn_bad_size
11357 23:20:37.131907 # Registered handlers for all signals.
11358 23:20:37.132119 # Detected MINSTKSIGSZ:4720
11359 23:20:37.135266 # Testcase initialized.
11360 23:20:37.138600 # uc context validated.
11361 23:20:37.141439 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11362 23:20:37.144731 # Handled SIG_COPYCTX
11363 23:20:37.144864 # Available space:3568
11364 23:20:37.147992 # uc context validated.
11365 23:20:37.154662 # Using badly built context - ERR: Bad size for esr_context
11366 23:20:37.161675 # SIG_OK -- SP:0xFFFFF3ECB910 si_addr@:0xfffff3ecb910 si_code:2 token@:0xfffff3eca6b0 offset:-4704
11367 23:20:37.164639 # ==>> completed. PASS(1)
11368 23:20:37.171219 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11369 23:20:37.178074 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF3ECA6B0
11370 23:20:37.181536 ok 4 selftests: arm64: fake_sigreturn_bad_size
11371 23:20:37.187634 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11372 23:20:37.218793 # Registered handlers for all signals.
11373 23:20:37.218980 # Detected MINSTKSIGSZ:4720
11374 23:20:37.222167 # Testcase initialized.
11375 23:20:37.225201 # uc context validated.
11376 23:20:37.229458 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11377 23:20:37.232068 # Handled SIG_COPYCTX
11378 23:20:37.232210 # Available space:3568
11379 23:20:37.238451 # Using badly built context - ERR: Bad size for terminator
11380 23:20:37.248839 # SIG_OK -- SP:0xFFFFDD2086C0 si_addr@:0xffffdd2086c0 si_code:2 token@:0xffffdd207460 offset:-4704
11381 23:20:37.248990 # ==>> completed. PASS(1)
11382 23:20:37.258644 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11383 23:20:37.265301 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDD207460
11384 23:20:37.268410 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11385 23:20:37.274609 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11386 23:20:37.302846 # Registered handlers for all signals.
11387 23:20:37.303001 # Detected MINSTKSIGSZ:4720
11388 23:20:37.306045 # Testcase initialized.
11389 23:20:37.309257 # uc context validated.
11390 23:20:37.312355 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11391 23:20:37.315795 # Handled SIG_COPYCTX
11392 23:20:37.315922 # Available space:3568
11393 23:20:37.322334 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11394 23:20:37.332231 # SIG_OK -- SP:0xFFFFFE103E40 si_addr@:0xfffffe103e40 si_code:2 token@:0xfffffe102be0 offset:-4704
11395 23:20:37.332410 # ==>> completed. PASS(1)
11396 23:20:37.342150 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11397 23:20:37.348608 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFE102BE0
11398 23:20:37.352036 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11399 23:20:37.355358 # selftests: arm64: fake_sigreturn_misaligned_sp
11400 23:20:37.388847 # Registered handlers for all signals.
11401 23:20:37.389057 # Detected MINSTKSIGSZ:4720
11402 23:20:37.392789 # Testcase initialized.
11403 23:20:37.395675 # uc context validated.
11404 23:20:37.399062 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11405 23:20:37.402254 # Handled SIG_COPYCTX
11406 23:20:37.408957 # SIG_OK -- SP:0xFFFFF16AFBF3 si_addr@:0xfffff16afbf3 si_code:2 token@:0xfffff16afbf3 offset:0
11407 23:20:37.411904 # ==>> completed. PASS(1)
11408 23:20:37.418865 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11409 23:20:37.425691 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF16AFBF3
11410 23:20:37.431678 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11411 23:20:37.434882 # selftests: arm64: fake_sigreturn_missing_fpsimd
11412 23:20:37.477751 # Registered handlers for all signals.
11413 23:20:37.477964 # Detected MINSTKSIGSZ:4720
11414 23:20:37.480793 # Testcase initialized.
11415 23:20:37.484193 # uc context validated.
11416 23:20:37.488026 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11417 23:20:37.490827 # Handled SIG_COPYCTX
11418 23:20:37.494294 # Mangling template header. Spare space:4096
11419 23:20:37.497440 # Using badly built context - ERR: Missing FPSIMD
11420 23:20:37.507276 # SIG_OK -- SP:0xFFFFF68B6350 si_addr@:0xfffff68b6350 si_code:2 token@:0xfffff68b50f0 offset:-4704
11421 23:20:37.510794 # ==>> completed. PASS(1)
11422 23:20:37.517184 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11423 23:20:37.524297 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF68B50F0
11424 23:20:37.527078 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11425 23:20:37.533482 # selftests: arm64: fake_sigreturn_sme_change_vl
11426 23:20:37.573002 # Registered handlers for all signals.
11427 23:20:37.573182 # Detected MINSTKSIGSZ:4720
11428 23:20:37.577034 # ==>> completed. SKIP.
11429 23:20:37.582546 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11430 23:20:37.586117 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11431 23:20:37.599038 # selftests: arm64: fake_sigreturn_sve_change_vl
11432 23:20:37.665605 # Registered handlers for all signals.
11433 23:20:37.665789 # Detected MINSTKSIGSZ:4720
11434 23:20:37.668714 # ==>> completed. SKIP.
11435 23:20:37.675468 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11436 23:20:37.678861 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11437 23:20:37.686378 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11438 23:20:37.746376 # Registered handlers for all signals.
11439 23:20:37.746531 # Detected MINSTKSIGSZ:4720
11440 23:20:37.750274 # Testcase initialized.
11441 23:20:37.753002 # uc context validated.
11442 23:20:37.753130 # Handled SIG_TRIG
11443 23:20:37.763006 # SIG_OK -- SP:0xFFFFCB1CF920 si_addr@:0xffffcb1cf920 si_code:2 token@:(nil) offset:-281474089416992
11444 23:20:37.766412 # ==>> completed. PASS(1)
11445 23:20:37.772950 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11446 23:20:37.779615 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11447 23:20:37.783259 # selftests: arm64: mangle_pstate_invalid_daif_bits
11448 23:20:37.810738 # Registered handlers for all signals.
11449 23:20:37.810892 # Detected MINSTKSIGSZ:4720
11450 23:20:37.814343 # Testcase initialized.
11451 23:20:37.818020 # uc context validated.
11452 23:20:37.818160 # Handled SIG_TRIG
11453 23:20:37.827462 # SIG_OK -- SP:0xFFFFCEEED460 si_addr@:0xffffceeed460 si_code:2 token@:(nil) offset:-281474153501792
11454 23:20:37.830719 # ==>> completed. PASS(1)
11455 23:20:37.837772 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11456 23:20:37.840663 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11457 23:20:37.847103 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11458 23:20:37.903839 # Registered handlers for all signals.
11459 23:20:37.904033 # Detected MINSTKSIGSZ:4720
11460 23:20:37.907049 # Testcase initialized.
11461 23:20:37.910458 # uc context validated.
11462 23:20:37.910608 # Handled SIG_TRIG
11463 23:20:37.920204 # SIG_OK -- SP:0xFFFFF99CF2A0 si_addr@:0xfffff99cf2a0 si_code:2 token@:(nil) offset:-281474869555872
11464 23:20:37.923535 # ==>> completed. PASS(1)
11465 23:20:37.930585 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11466 23:20:37.933366 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11467 23:20:37.940030 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11468 23:20:37.994422 # Registered handlers for all signals.
11469 23:20:37.994618 # Detected MINSTKSIGSZ:4720
11470 23:20:37.997741 # Testcase initialized.
11471 23:20:38.001382 # uc context validated.
11472 23:20:38.001530 # Handled SIG_TRIG
11473 23:20:38.011106 # SIG_OK -- SP:0xFFFFE067CF80 si_addr@:0xffffe067cf80 si_code:2 token@:(nil) offset:-281474446643072
11474 23:20:38.014260 # ==>> completed. PASS(1)
11475 23:20:38.020670 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11476 23:20:38.024267 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11477 23:20:38.031258 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11478 23:20:38.075171 # Registered handlers for all signals.
11479 23:20:38.075357 # Detected MINSTKSIGSZ:4720
11480 23:20:38.078454 # Testcase initialized.
11481 23:20:38.081423 # uc context validated.
11482 23:20:38.081554 # Handled SIG_TRIG
11483 23:20:38.091834 # SIG_OK -- SP:0xFFFFCF0E05E0 si_addr@:0xffffcf0e05e0 si_code:2 token@:(nil) offset:-281474155546080
11484 23:20:38.095060 # ==>> completed. PASS(1)
11485 23:20:38.101590 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11486 23:20:38.104701 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11487 23:20:38.111153 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11488 23:20:38.167653 # Registered handlers for all signals.
11489 23:20:38.167806 # Detected MINSTKSIGSZ:4720
11490 23:20:38.171111 # Testcase initialized.
11491 23:20:38.174242 # uc context validated.
11492 23:20:38.174344 # Handled SIG_TRIG
11493 23:20:38.184520 # SIG_OK -- SP:0xFFFFCA2ACA30 si_addr@:0xffffca2aca30 si_code:2 token@:(nil) offset:-281474073545264
11494 23:20:38.187319 # ==>> completed. PASS(1)
11495 23:20:38.194241 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11496 23:20:38.197349 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11497 23:20:38.203760 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11498 23:20:38.259910 # Registered handlers for all signals.
11499 23:20:38.260102 # Detected MINSTKSIGSZ:4720
11500 23:20:38.263179 # Testcase initialized.
11501 23:20:38.266904 # uc context validated.
11502 23:20:38.267058 # Handled SIG_TRIG
11503 23:20:38.276752 # SIG_OK -- SP:0xFFFFDCE9C3E0 si_addr@:0xffffdce9c3e0 si_code:2 token@:(nil) offset:-281474388050912
11504 23:20:38.279756 # ==>> completed. PASS(1)
11505 23:20:38.286318 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11506 23:20:38.289726 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11507 23:20:38.295978 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11508 23:20:38.337890 # Registered handlers for all signals.
11509 23:20:38.338105 # Detected MINSTKSIGSZ:4720
11510 23:20:38.341261 # Testcase initialized.
11511 23:20:38.344586 # uc context validated.
11512 23:20:38.344679 # Handled SIG_TRIG
11513 23:20:38.354637 # SIG_OK -- SP:0xFFFFC5516130 si_addr@:0xffffc5516130 si_code:2 token@:(nil) offset:-281473992188208
11514 23:20:38.357892 # ==>> completed. PASS(1)
11515 23:20:38.364795 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11516 23:20:38.367756 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11517 23:20:38.370903 # selftests: arm64: sme_trap_no_sm
11518 23:20:38.418868 # Registered handlers for all signals.
11519 23:20:38.419026 # Detected MINSTKSIGSZ:4720
11520 23:20:38.421997 # ==>> completed. SKIP.
11521 23:20:38.432008 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11522 23:20:38.435081 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11523 23:20:38.438523 # selftests: arm64: sme_trap_non_streaming
11524 23:20:38.496471 # Registered handlers for all signals.
11525 23:20:38.496620 # Detected MINSTKSIGSZ:4720
11526 23:20:38.500057 # ==>> completed. SKIP.
11527 23:20:38.509697 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11528 23:20:38.516585 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11529 23:20:38.519588 # selftests: arm64: sme_trap_za
11530 23:20:38.576303 # Registered handlers for all signals.
11531 23:20:38.576483 # Detected MINSTKSIGSZ:4720
11532 23:20:38.580013 # Testcase initialized.
11533 23:20:38.589626 # SIG_OK -- SP:0xFFFFEEF5A170 si_addr@:0xaaaabdd02510 si_code:1 token@:(nil) offset:-187650305697040
11534 23:20:38.589768 # ==>> completed. PASS(1)
11535 23:20:38.599817 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11536 23:20:38.602736 ok 21 selftests: arm64: sme_trap_za
11537 23:20:38.602850 # selftests: arm64: sme_vl
11538 23:20:38.669362 # Registered handlers for all signals.
11539 23:20:38.669516 # Detected MINSTKSIGSZ:4720
11540 23:20:38.672170 # ==>> completed. SKIP.
11541 23:20:38.679158 # # SME VL :: Check that we get the right SME VL reported
11542 23:20:38.681897 ok 22 selftests: arm64: sme_vl # SKIP
11543 23:20:38.690283 # selftests: arm64: ssve_regs
11544 23:20:38.743423 # Registered handlers for all signals.
11545 23:20:38.743625 # Detected MINSTKSIGSZ:4720
11546 23:20:38.746532 # ==>> completed. SKIP.
11547 23:20:38.752887 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11548 23:20:38.759943 ok 23 selftests: arm64: ssve_regs # SKIP
11549 23:20:38.760141 # selftests: arm64: sve_regs
11550 23:20:38.815245 # Registered handlers for all signals.
11551 23:20:38.815454 # Detected MINSTKSIGSZ:4720
11552 23:20:38.818673 # ==>> completed. SKIP.
11553 23:20:38.825322 # # SVE registers :: Check that we get the right SVE registers reported
11554 23:20:38.828095 ok 24 selftests: arm64: sve_regs # SKIP
11555 23:20:38.832563 # selftests: arm64: sve_vl
11556 23:20:38.911151 # Registered handlers for all signals.
11557 23:20:38.911346 # Detected MINSTKSIGSZ:4720
11558 23:20:38.914411 # ==>> completed. SKIP.
11559 23:20:38.921005 # # SVE VL :: Check that we get the right SVE VL reported
11560 23:20:38.924176 ok 25 selftests: arm64: sve_vl # SKIP
11561 23:20:38.928820 # selftests: arm64: za_no_regs
11562 23:20:38.996367 # Registered handlers for all signals.
11563 23:20:38.996525 # Detected MINSTKSIGSZ:4720
11564 23:20:38.999788 # ==>> completed. SKIP.
11565 23:20:39.006391 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11566 23:20:39.009593 ok 26 selftests: arm64: za_no_regs # SKIP
11567 23:20:39.017154 # selftests: arm64: za_regs
11568 23:20:39.087342 # Registered handlers for all signals.
11569 23:20:39.087519 # Detected MINSTKSIGSZ:4720
11570 23:20:39.090457 # ==>> completed. SKIP.
11571 23:20:39.096989 # # ZA register :: Check that we get the right ZA registers reported
11572 23:20:39.100555 ok 27 selftests: arm64: za_regs # SKIP
11573 23:20:39.105485 # selftests: arm64: pac
11574 23:20:39.159129 # TAP version 13
11575 23:20:39.159312 # 1..7
11576 23:20:39.162420 # # Starting 7 tests from 1 test cases.
11577 23:20:39.165535 # # RUN global.corrupt_pac ...
11578 23:20:39.168950 # # SKIP PAUTH not enabled
11579 23:20:39.172248 # # OK global.corrupt_pac
11580 23:20:39.175394 # ok 1 # SKIP PAUTH not enabled
11581 23:20:39.182181 # # RUN global.pac_instructions_not_nop ...
11582 23:20:39.185327 # # SKIP PAUTH not enabled
11583 23:20:39.189263 # # OK global.pac_instructions_not_nop
11584 23:20:39.192682 # ok 2 # SKIP PAUTH not enabled
11585 23:20:39.198691 # # RUN global.pac_instructions_not_nop_generic ...
11586 23:20:39.202616 # # SKIP Generic PAUTH not enabled
11587 23:20:39.205937 # # OK global.pac_instructions_not_nop_generic
11588 23:20:39.208894 # ok 3 # SKIP Generic PAUTH not enabled
11589 23:20:39.215717 # # RUN global.single_thread_different_keys ...
11590 23:20:39.218756 # # SKIP PAUTH not enabled
11591 23:20:39.225173 # # OK global.single_thread_different_keys
11592 23:20:39.225337 # ok 4 # SKIP PAUTH not enabled
11593 23:20:39.231556 # # RUN global.exec_changed_keys ...
11594 23:20:39.235054 # # SKIP PAUTH not enabled
11595 23:20:39.238352 # # OK global.exec_changed_keys
11596 23:20:39.241994 # ok 5 # SKIP PAUTH not enabled
11597 23:20:39.245443 # # RUN global.context_switch_keep_keys ...
11598 23:20:39.248486 # # SKIP PAUTH not enabled
11599 23:20:39.254971 # # OK global.context_switch_keep_keys
11600 23:20:39.255151 # ok 6 # SKIP PAUTH not enabled
11601 23:20:39.261448 # # RUN global.context_switch_keep_keys_generic ...
11602 23:20:39.265374 # # SKIP Generic PAUTH not enabled
11603 23:20:39.271446 # # OK global.context_switch_keep_keys_generic
11604 23:20:39.274815 # ok 7 # SKIP Generic PAUTH not enabled
11605 23:20:39.278299 # # PASSED: 7 / 7 tests passed.
11606 23:20:39.281443 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11607 23:20:39.284871 ok 28 selftests: arm64: pac
11608 23:20:39.287888 # selftests: arm64: fp-stress
11609 23:20:45.591997 <6>[ 46.154744] vpu: disabling
11610 23:20:45.594996 <6>[ 46.157794] vproc2: disabling
11611 23:20:45.598220 <6>[ 46.161406] vproc1: disabling
11612 23:20:45.602138 <6>[ 46.165051] vaud18: disabling
11613 23:20:45.608702 <6>[ 46.168572] vsram_others: disabling
11614 23:20:45.612188 <6>[ 46.172546] va09: disabling
11615 23:20:45.615757 <6>[ 46.175750] vsram_md: disabling
11616 23:20:45.618515 <6>[ 46.179340] Vgpu: disabling
11617 23:20:49.240983 # TAP version 13
11618 23:20:49.241135 # 1..16
11619 23:20:49.243771 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11620 23:20:49.247114 # # Will run for 10s
11621 23:20:49.247197 # # Started FPSIMD-0-0
11622 23:20:49.250111 # # Started FPSIMD-0-1
11623 23:20:49.253477 # # Started FPSIMD-1-0
11624 23:20:49.253558 # # Started FPSIMD-1-1
11625 23:20:49.256757 # # Started FPSIMD-2-0
11626 23:20:49.256834 # # Started FPSIMD-2-1
11627 23:20:49.260248 # # Started FPSIMD-3-0
11628 23:20:49.263336 # # Started FPSIMD-3-1
11629 23:20:49.263431 # # Started FPSIMD-4-0
11630 23:20:49.266689 # # Started FPSIMD-4-1
11631 23:20:49.269876 # # Started FPSIMD-5-0
11632 23:20:49.269963 # # Started FPSIMD-5-1
11633 23:20:49.274338 # # Started FPSIMD-6-0
11634 23:20:49.276544 # # Started FPSIMD-6-1
11635 23:20:49.276661 # # Started FPSIMD-7-0
11636 23:20:49.279834 # # Started FPSIMD-7-1
11637 23:20:49.283126 # # FPSIMD-0-0: Vector length: 128 bits
11638 23:20:49.286874 # # FPSIMD-0-0: PID: 1168
11639 23:20:49.289725 # # FPSIMD-0-1: Vector length: 128 bits
11640 23:20:49.289854 # # FPSIMD-0-1: PID: 1169
11641 23:20:49.293783 # # FPSIMD-1-0: Vector length: 128 bits
11642 23:20:49.296647 # # FPSIMD-1-0: PID: 1170
11643 23:20:49.299754 # # FPSIMD-2-1: Vector length: 128 bits
11644 23:20:49.302962 # # FPSIMD-2-1: PID: 1173
11645 23:20:49.306221 # # FPSIMD-1-1: Vector length: 128 bits
11646 23:20:49.309825 # # FPSIMD-1-1: PID: 1171
11647 23:20:49.313186 # # FPSIMD-5-0: Vector length: 128 bits
11648 23:20:49.316286 # # FPSIMD-5-0: PID: 1178
11649 23:20:49.319336 # # FPSIMD-4-0: Vector length: 128 bits
11650 23:20:49.319429 # # FPSIMD-4-0: PID: 1176
11651 23:20:49.323122 # # FPSIMD-3-0: Vector length: 128 bits
11652 23:20:49.326168 # # FPSIMD-3-0: PID: 1174
11653 23:20:49.329227 # # FPSIMD-4-1: Vector length: 128 bits
11654 23:20:49.332574 # # FPSIMD-4-1: PID: 1177
11655 23:20:49.336451 # # FPSIMD-3-1: Vector length: 128 bits
11656 23:20:49.339771 # # FPSIMD-3-1: PID: 1175
11657 23:20:49.342628 # # FPSIMD-5-1: Vector length: 128 bits
11658 23:20:49.342708 # # FPSIMD-5-1: PID: 1179
11659 23:20:49.349090 # # FPSIMD-7-0: Vector length: 128 bits
11660 23:20:49.349191 # # FPSIMD-7-0: PID: 1182
11661 23:20:49.353355 # # FPSIMD-7-1: Vector length: 128 bits
11662 23:20:49.355969 # # FPSIMD-7-1: PID: 1183
11663 23:20:49.358910 # # FPSIMD-2-0: Vector length: 128 bits
11664 23:20:49.362451 # # FPSIMD-2-0: PID: 1172
11665 23:20:49.366336 # # FPSIMD-6-1: Vector length: 128 bits
11666 23:20:49.369105 # # FPSIMD-6-1: PID: 1181
11667 23:20:49.372142 # # FPSIMD-6-0: Vector length: 128 bits
11668 23:20:49.372226 # # FPSIMD-6-0: PID: 1180
11669 23:20:49.375858 # # Finishing up...
11670 23:20:49.382008 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=899215, signals=10
11671 23:20:49.388740 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1144101, signals=10
11672 23:20:49.395696 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1865269, signals=10
11673 23:20:49.405256 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1674146, signals=10
11674 23:20:49.411905 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1221154, signals=10
11675 23:20:49.418622 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1296363, signals=10
11676 23:20:49.424909 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=878687, signals=10
11677 23:20:49.428534 # ok 1 FPSIMD-0-0
11678 23:20:49.428623 # ok 2 FPSIMD-0-1
11679 23:20:49.431583 # ok 3 FPSIMD-1-0
11680 23:20:49.431668 # ok 4 FPSIMD-1-1
11681 23:20:49.435241 # ok 5 FPSIMD-2-0
11682 23:20:49.435355 # ok 6 FPSIMD-2-1
11683 23:20:49.438253 # ok 7 FPSIMD-3-0
11684 23:20:49.438360 # ok 8 FPSIMD-3-1
11685 23:20:49.441368 # ok 9 FPSIMD-4-0
11686 23:20:49.441473 # ok 10 FPSIMD-4-1
11687 23:20:49.445163 # ok 11 FPSIMD-5-0
11688 23:20:49.445248 # ok 12 FPSIMD-5-1
11689 23:20:49.448155 # ok 13 FPSIMD-6-0
11690 23:20:49.448242 # ok 14 FPSIMD-6-1
11691 23:20:49.451508 # ok 15 FPSIMD-7-0
11692 23:20:49.451593 # ok 16 FPSIMD-7-1
11693 23:20:49.457964 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1117042, signals=9
11694 23:20:49.468003 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1254954, signals=10
11695 23:20:49.474775 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=888510, signals=10
11696 23:20:49.481786 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1043266, signals=10
11697 23:20:49.487895 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1172806, signals=10
11698 23:20:49.494537 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1106555, signals=10
11699 23:20:49.504199 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1216040, signals=9
11700 23:20:49.511178 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1702485, signals=10
11701 23:20:49.517423 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=958768, signals=10
11702 23:20:49.520720 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11703 23:20:49.524360 ok 29 selftests: arm64: fp-stress
11704 23:20:49.527447 # selftests: arm64: sve-ptrace
11705 23:20:49.531093 # TAP version 13
11706 23:20:49.531206 # 1..4104
11707 23:20:49.534154 # ok 2 # SKIP SVE not available
11708 23:20:49.537567 # # Planned tests != run tests (4104 != 1)
11709 23:20:49.543876 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11710 23:20:49.547010 ok 30 selftests: arm64: sve-ptrace # SKIP
11711 23:20:49.550200 # selftests: arm64: sve-probe-vls
11712 23:20:49.550311 # TAP version 13
11713 23:20:49.550417 # 1..2
11714 23:20:49.554030 # ok 2 # SKIP SVE not available
11715 23:20:49.556826 # # Planned tests != run tests (2 != 1)
11716 23:20:49.563524 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11717 23:20:49.566788 ok 31 selftests: arm64: sve-probe-vls # SKIP
11718 23:20:49.570969 # selftests: arm64: vec-syscfg
11719 23:20:49.571080 # TAP version 13
11720 23:20:49.573395 # 1..20
11721 23:20:49.573504 # ok 1 # SKIP SVE not supported
11722 23:20:49.576556 # ok 2 # SKIP SVE not supported
11723 23:20:49.580119 # ok 3 # SKIP SVE not supported
11724 23:20:49.583457 # ok 4 # SKIP SVE not supported
11725 23:20:49.586527 # ok 5 # SKIP SVE not supported
11726 23:20:49.590045 # ok 6 # SKIP SVE not supported
11727 23:20:49.593021 # ok 7 # SKIP SVE not supported
11728 23:20:49.596390 # ok 8 # SKIP SVE not supported
11729 23:20:49.596476 # ok 9 # SKIP SVE not supported
11730 23:20:49.599636 # ok 10 # SKIP SVE not supported
11731 23:20:49.603064 # ok 11 # SKIP SME not supported
11732 23:20:49.606189 # ok 12 # SKIP SME not supported
11733 23:20:49.609845 # ok 13 # SKIP SME not supported
11734 23:20:49.613464 # ok 14 # SKIP SME not supported
11735 23:20:49.616296 # ok 15 # SKIP SME not supported
11736 23:20:49.620215 # ok 16 # SKIP SME not supported
11737 23:20:49.622838 # ok 17 # SKIP SME not supported
11738 23:20:49.622947 # ok 18 # SKIP SME not supported
11739 23:20:49.626276 # ok 19 # SKIP SME not supported
11740 23:20:49.629700 # ok 20 # SKIP SME not supported
11741 23:20:49.635956 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11742 23:20:49.639474 ok 32 selftests: arm64: vec-syscfg
11743 23:20:49.639558 # selftests: arm64: za-fork
11744 23:20:49.642549 # TAP version 13
11745 23:20:49.642623 # 1..1
11746 23:20:49.646123 # # PID: 1260
11747 23:20:49.646210 # # SME support not present
11748 23:20:49.649160 # ok 0 skipped
11749 23:20:49.652950 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11750 23:20:49.655820 ok 33 selftests: arm64: za-fork
11751 23:20:49.659023 # selftests: arm64: za-ptrace
11752 23:20:49.659133 # TAP version 13
11753 23:20:49.662315 # 1..1
11754 23:20:49.665751 # ok 2 # SKIP SME not available
11755 23:20:49.668881 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11756 23:20:49.672077 ok 34 selftests: arm64: za-ptrace # SKIP
11757 23:20:49.675566 # selftests: arm64: check_buffer_fill
11758 23:20:49.737173 # # SKIP: MTE features unavailable
11759 23:20:49.744563 ok 35 selftests: arm64: check_buffer_fill # SKIP
11760 23:20:49.762139 # selftests: arm64: check_child_memory
11761 23:20:49.811257 # # SKIP: MTE features unavailable
11762 23:20:49.819444 ok 36 selftests: arm64: check_child_memory # SKIP
11763 23:20:49.836686 # selftests: arm64: check_gcr_el1_cswitch
11764 23:20:49.908555 # # SKIP: MTE features unavailable
11765 23:20:49.916059 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11766 23:20:49.933259 # selftests: arm64: check_ksm_options
11767 23:20:49.982132 # # SKIP: MTE features unavailable
11768 23:20:49.989868 ok 38 selftests: arm64: check_ksm_options # SKIP
11769 23:20:50.005874 # selftests: arm64: check_mmap_options
11770 23:20:50.064233 # # SKIP: MTE features unavailable
11771 23:20:50.072411 ok 39 selftests: arm64: check_mmap_options # SKIP
11772 23:20:50.084707 # selftests: arm64: check_prctl
11773 23:20:50.126186 # TAP version 13
11774 23:20:50.126337 # 1..5
11775 23:20:50.129835 # ok 1 check_basic_read
11776 23:20:50.129934 # ok 2 NONE
11777 23:20:50.132552 # ok 3 # SKIP SYNC
11778 23:20:50.132639 # ok 4 # SKIP ASYNC
11779 23:20:50.135947 # ok 5 # SKIP SYNC+ASYNC
11780 23:20:50.139736 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11781 23:20:50.142665 ok 40 selftests: arm64: check_prctl
11782 23:20:50.150123 # selftests: arm64: check_tags_inclusion
11783 23:20:50.212462 # # SKIP: MTE features unavailable
11784 23:20:50.220375 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11785 23:20:50.231199 # selftests: arm64: check_user_mem
11786 23:20:50.299070 # # SKIP: MTE features unavailable
11787 23:20:50.308180 ok 42 selftests: arm64: check_user_mem # SKIP
11788 23:20:50.321940 # selftests: arm64: btitest
11789 23:20:50.389518 # TAP version 13
11790 23:20:50.389697 # 1..18
11791 23:20:50.393192 # # HWCAP_PACA not present
11792 23:20:50.396441 # # HWCAP2_BTI not present
11793 23:20:50.396527 # # Test binary built for BTI
11794 23:20:50.402771 # ok 1 nohint_func/call_using_br_x0 # SKIP
11795 23:20:50.406082 # ok 1 nohint_func/call_using_br_x16 # SKIP
11796 23:20:50.408952 # ok 1 nohint_func/call_using_blr # SKIP
11797 23:20:50.412411 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11798 23:20:50.415695 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11799 23:20:50.422840 # ok 1 bti_none_func/call_using_blr # SKIP
11800 23:20:50.425681 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11801 23:20:50.429126 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11802 23:20:50.432442 # ok 1 bti_c_func/call_using_blr # SKIP
11803 23:20:50.435707 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11804 23:20:50.439019 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11805 23:20:50.442393 # ok 1 bti_j_func/call_using_blr # SKIP
11806 23:20:50.445869 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11807 23:20:50.452305 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11808 23:20:50.455528 # ok 1 bti_jc_func/call_using_blr # SKIP
11809 23:20:50.458692 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11810 23:20:50.461808 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11811 23:20:50.465494 # ok 1 paciasp_func/call_using_blr # SKIP
11812 23:20:50.471994 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11813 23:20:50.475296 # # WARNING - EXPECTED TEST COUNT WRONG
11814 23:20:50.478558 ok 43 selftests: arm64: btitest
11815 23:20:50.482338 # selftests: arm64: nobtitest
11816 23:20:50.482441 # TAP version 13
11817 23:20:50.482508 # 1..18
11818 23:20:50.484971 # # HWCAP_PACA not present
11819 23:20:50.488318 # # HWCAP2_BTI not present
11820 23:20:50.491656 # # Test binary not built for BTI
11821 23:20:50.494645 # ok 1 nohint_func/call_using_br_x0 # SKIP
11822 23:20:50.497965 # ok 1 nohint_func/call_using_br_x16 # SKIP
11823 23:20:50.501606 # ok 1 nohint_func/call_using_blr # SKIP
11824 23:20:50.505296 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11825 23:20:50.511353 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11826 23:20:50.514599 # ok 1 bti_none_func/call_using_blr # SKIP
11827 23:20:50.518016 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11828 23:20:50.521514 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11829 23:20:50.524721 # ok 1 bti_c_func/call_using_blr # SKIP
11830 23:20:50.527790 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11831 23:20:50.531023 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11832 23:20:50.534335 # ok 1 bti_j_func/call_using_blr # SKIP
11833 23:20:50.541390 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11834 23:20:50.544565 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11835 23:20:50.548046 # ok 1 bti_jc_func/call_using_blr # SKIP
11836 23:20:50.551203 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11837 23:20:50.554231 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11838 23:20:50.557286 # ok 1 paciasp_func/call_using_blr # SKIP
11839 23:20:50.564167 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11840 23:20:50.567269 # # WARNING - EXPECTED TEST COUNT WRONG
11841 23:20:50.570938 ok 44 selftests: arm64: nobtitest
11842 23:20:50.574331 # selftests: arm64: hwcap
11843 23:20:50.574444 # TAP version 13
11844 23:20:50.574541 # 1..28
11845 23:20:50.577153 # ok 1 cpuinfo_match_RNG
11846 23:20:50.580542 # # SIGILL reported for RNG
11847 23:20:50.583986 # ok 2 # SKIP sigill_RNG
11848 23:20:50.584073 # ok 3 cpuinfo_match_SME
11849 23:20:50.587635 # ok 4 sigill_SME
11850 23:20:50.587728 # ok 5 cpuinfo_match_SVE
11851 23:20:50.590931 # ok 6 sigill_SVE
11852 23:20:50.593649 # ok 7 cpuinfo_match_SVE 2
11853 23:20:50.596986 # # SIGILL reported for SVE 2
11854 23:20:50.597080 # ok 8 # SKIP sigill_SVE 2
11855 23:20:50.600102 # ok 9 cpuinfo_match_SVE AES
11856 23:20:50.603773 # # SIGILL reported for SVE AES
11857 23:20:50.606591 # ok 10 # SKIP sigill_SVE AES
11858 23:20:50.610209 # ok 11 cpuinfo_match_SVE2 PMULL
11859 23:20:50.613523 # # SIGILL reported for SVE2 PMULL
11860 23:20:50.613611 # ok 12 # SKIP sigill_SVE2 PMULL
11861 23:20:50.616799 # ok 13 cpuinfo_match_SVE2 BITPERM
11862 23:20:50.619951 # # SIGILL reported for SVE2 BITPERM
11863 23:20:50.623366 # ok 14 # SKIP sigill_SVE2 BITPERM
11864 23:20:50.626363 # ok 15 cpuinfo_match_SVE2 SHA3
11865 23:20:50.629981 # # SIGILL reported for SVE2 SHA3
11866 23:20:50.633345 # ok 16 # SKIP sigill_SVE2 SHA3
11867 23:20:50.636384 # ok 17 cpuinfo_match_SVE2 SM4
11868 23:20:50.639815 # # SIGILL reported for SVE2 SM4
11869 23:20:50.643100 # ok 18 # SKIP sigill_SVE2 SM4
11870 23:20:50.646357 # ok 19 cpuinfo_match_SVE2 I8MM
11871 23:20:50.646464 # # SIGILL reported for SVE2 I8MM
11872 23:20:50.649726 # ok 20 # SKIP sigill_SVE2 I8MM
11873 23:20:50.652816 # ok 21 cpuinfo_match_SVE2 F32MM
11874 23:20:50.656319 # # SIGILL reported for SVE2 F32MM
11875 23:20:50.659418 # ok 22 # SKIP sigill_SVE2 F32MM
11876 23:20:50.662474 # ok 23 cpuinfo_match_SVE2 F64MM
11877 23:20:50.666290 # # SIGILL reported for SVE2 F64MM
11878 23:20:50.669423 # ok 24 # SKIP sigill_SVE2 F64MM
11879 23:20:50.672581 # ok 25 cpuinfo_match_SVE2 BF16
11880 23:20:50.675779 # # SIGILL reported for SVE2 BF16
11881 23:20:50.675888 # ok 26 # SKIP sigill_SVE2 BF16
11882 23:20:50.679090 # ok 27 cpuinfo_match_SVE2 EBF16
11883 23:20:50.682686 # ok 28 # SKIP sigill_SVE2 EBF16
11884 23:20:50.688925 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11885 23:20:50.692369 ok 45 selftests: arm64: hwcap
11886 23:20:50.692471 # selftests: arm64: ptrace
11887 23:20:50.695541 # TAP version 13
11888 23:20:50.695627 # 1..7
11889 23:20:50.699464 # # Parent is 1502, child is 1503
11890 23:20:50.702671 # ok 1 read_tpidr_one
11891 23:20:50.702799 # ok 2 write_tpidr_one
11892 23:20:50.705388 # ok 3 verify_tpidr_one
11893 23:20:50.705478 # ok 4 count_tpidrs
11894 23:20:50.709209 # ok 5 tpidr2_write
11895 23:20:50.711932 # ok 6 tpidr2_read
11896 23:20:50.712024 # ok 7 write_tpidr_only
11897 23:20:50.718629 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11898 23:20:50.722197 ok 46 selftests: arm64: ptrace
11899 23:20:50.722308 # selftests: arm64: syscall-abi
11900 23:20:50.742482 # TAP version 13
11901 23:20:50.742627 # 1..2
11902 23:20:50.745613 # ok 1 getpid() FPSIMD
11903 23:20:50.748791 # ok 2 sched_yield() FPSIMD
11904 23:20:50.752036 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11905 23:20:50.755621 ok 47 selftests: arm64: syscall-abi
11906 23:20:50.763285 # selftests: arm64: tpidr2
11907 23:20:50.825548 # TAP version 13
11908 23:20:50.825729 # 1..5
11909 23:20:50.828585 # # PID: 1539
11910 23:20:50.828688 # # SME support not present
11911 23:20:50.831998 # ok 0 skipped, TPIDR2 not supported
11912 23:20:50.835339 # ok 1 skipped, TPIDR2 not supported
11913 23:20:50.838359 # ok 2 skipped, TPIDR2 not supported
11914 23:20:50.841915 # ok 3 skipped, TPIDR2 not supported
11915 23:20:50.845273 # ok 4 skipped, TPIDR2 not supported
11916 23:20:50.851640 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11917 23:20:50.854823 ok 48 selftests: arm64: tpidr2
11918 23:20:52.348688 arm64_tags_test pass
11919 23:20:52.351894 arm64_run_tags_test_sh pass
11920 23:20:52.355302 arm64_fake_sigreturn_bad_magic pass
11921 23:20:52.358561 arm64_fake_sigreturn_bad_size pass
11922 23:20:52.361773 arm64_fake_sigreturn_bad_size_for_magic0 pass
11923 23:20:52.365284 arm64_fake_sigreturn_duplicated_fpsimd pass
11924 23:20:52.368616 arm64_fake_sigreturn_misaligned_sp pass
11925 23:20:52.371983 arm64_fake_sigreturn_missing_fpsimd pass
11926 23:20:52.375182 arm64_fake_sigreturn_sme_change_vl skip
11927 23:20:52.381784 arm64_fake_sigreturn_sve_change_vl skip
11928 23:20:52.385008 arm64_mangle_pstate_invalid_compat_toggle pass
11929 23:20:52.388681 arm64_mangle_pstate_invalid_daif_bits pass
11930 23:20:52.391484 arm64_mangle_pstate_invalid_mode_el1h pass
11931 23:20:52.394986 arm64_mangle_pstate_invalid_mode_el1t pass
11932 23:20:52.398306 arm64_mangle_pstate_invalid_mode_el2h pass
11933 23:20:52.405133 arm64_mangle_pstate_invalid_mode_el2t pass
11934 23:20:52.408478 arm64_mangle_pstate_invalid_mode_el3h pass
11935 23:20:52.411345 arm64_mangle_pstate_invalid_mode_el3t pass
11936 23:20:52.414641 arm64_sme_trap_no_sm skip
11937 23:20:52.417965 arm64_sme_trap_non_streaming skip
11938 23:20:52.418143 arm64_sme_trap_za pass
11939 23:20:52.421615 arm64_sme_vl skip
11940 23:20:52.421775 arm64_ssve_regs skip
11941 23:20:52.424506 arm64_sve_regs skip
11942 23:20:52.424657 arm64_sve_vl skip
11943 23:20:52.428238 arm64_za_no_regs skip
11944 23:20:52.428392 arm64_za_regs skip
11945 23:20:52.431276 arm64_pac_PAUTH_not_enabled skip
11946 23:20:52.434749 arm64_pac_PAUTH_not_enabled_dup2 skip
11947 23:20:52.438094 arm64_pac_Generic_PAUTH_not_enabled skip
11948 23:20:52.441576 arm64_pac_PAUTH_not_enabled_dup3 skip
11949 23:20:52.444786 arm64_pac_PAUTH_not_enabled_dup4 skip
11950 23:20:52.451463 arm64_pac_PAUTH_not_enabled_dup5 skip
11951 23:20:52.454607 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11952 23:20:52.454754 arm64_pac pass
11953 23:20:52.457713 arm64_fp-stress_FPSIMD-0-0 pass
11954 23:20:52.460953 arm64_fp-stress_FPSIMD-0-1 pass
11955 23:20:52.464681 arm64_fp-stress_FPSIMD-1-0 pass
11956 23:20:52.467460 arm64_fp-stress_FPSIMD-1-1 pass
11957 23:20:52.471020 arm64_fp-stress_FPSIMD-2-0 pass
11958 23:20:52.471170 arm64_fp-stress_FPSIMD-2-1 pass
11959 23:20:52.474248 arm64_fp-stress_FPSIMD-3-0 pass
11960 23:20:52.477473 arm64_fp-stress_FPSIMD-3-1 pass
11961 23:20:52.481107 arm64_fp-stress_FPSIMD-4-0 pass
11962 23:20:52.484656 arm64_fp-stress_FPSIMD-4-1 pass
11963 23:20:52.487772 arm64_fp-stress_FPSIMD-5-0 pass
11964 23:20:52.490796 arm64_fp-stress_FPSIMD-5-1 pass
11965 23:20:52.490949 arm64_fp-stress_FPSIMD-6-0 pass
11966 23:20:52.494340 arm64_fp-stress_FPSIMD-6-1 pass
11967 23:20:52.497529 arm64_fp-stress_FPSIMD-7-0 pass
11968 23:20:52.501099 arm64_fp-stress_FPSIMD-7-1 pass
11969 23:20:52.504135 arm64_fp-stress pass
11970 23:20:52.507144 arm64_sve-ptrace_SVE_not_available skip
11971 23:20:52.507302 arm64_sve-ptrace skip
11972 23:20:52.510572 arm64_sve-probe-vls_SVE_not_available skip
11973 23:20:52.513915 arm64_sve-probe-vls skip
11974 23:20:52.517327 arm64_vec-syscfg_SVE_not_supported skip
11975 23:20:52.520438 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11976 23:20:52.526973 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11977 23:20:52.530427 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11978 23:20:52.533651 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11979 23:20:52.537073 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11980 23:20:52.540613 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11981 23:20:52.547239 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11982 23:20:52.551001 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11983 23:20:52.553523 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11984 23:20:52.557012 arm64_vec-syscfg_SME_not_supported skip
11985 23:20:52.560229 arm64_vec-syscfg_SME_not_supported_dup2 skip
11986 23:20:52.566957 arm64_vec-syscfg_SME_not_supported_dup3 skip
11987 23:20:52.570157 arm64_vec-syscfg_SME_not_supported_dup4 skip
11988 23:20:52.573193 arm64_vec-syscfg_SME_not_supported_dup5 skip
11989 23:20:52.576526 arm64_vec-syscfg_SME_not_supported_dup6 skip
11990 23:20:52.580114 arm64_vec-syscfg_SME_not_supported_dup7 skip
11991 23:20:52.586683 arm64_vec-syscfg_SME_not_supported_dup8 skip
11992 23:20:52.589740 arm64_vec-syscfg_SME_not_supported_dup9 skip
11993 23:20:52.593387 arm64_vec-syscfg_SME_not_supported_dup10 skip
11994 23:20:52.596055 arm64_vec-syscfg pass
11995 23:20:52.599723 arm64_za-fork_skipped pass
11996 23:20:52.599861 arm64_za-fork pass
11997 23:20:52.602771 arm64_za-ptrace_SME_not_available skip
11998 23:20:52.606106 arm64_za-ptrace skip
11999 23:20:52.606244 arm64_check_buffer_fill skip
12000 23:20:52.610014 arm64_check_child_memory skip
12001 23:20:52.613162 arm64_check_gcr_el1_cswitch skip
12002 23:20:52.616397 arm64_check_ksm_options skip
12003 23:20:52.619799 arm64_check_mmap_options skip
12004 23:20:52.622908 arm64_check_prctl_check_basic_read pass
12005 23:20:52.626683 arm64_check_prctl_NONE pass
12006 23:20:52.626845 arm64_check_prctl_SYNC skip
12007 23:20:52.629406 arm64_check_prctl_ASYNC skip
12008 23:20:52.632468 arm64_check_prctl_SYNC_ASYNC skip
12009 23:20:52.635983 arm64_check_prctl pass
12010 23:20:52.639451 arm64_check_tags_inclusion skip
12011 23:20:52.639610 arm64_check_user_mem skip
12012 23:20:52.645744 arm64_btitest_nohint_func_call_using_br_x0 skip
12013 23:20:52.648914 arm64_btitest_nohint_func_call_using_br_x16 skip
12014 23:20:52.652583 arm64_btitest_nohint_func_call_using_blr skip
12015 23:20:52.656004 arm64_btitest_bti_none_func_call_using_br_x0 skip
12016 23:20:52.662316 arm64_btitest_bti_none_func_call_using_br_x16 skip
12017 23:20:52.665852 arm64_btitest_bti_none_func_call_using_blr skip
12018 23:20:52.668650 arm64_btitest_bti_c_func_call_using_br_x0 skip
12019 23:20:52.675455 arm64_btitest_bti_c_func_call_using_br_x16 skip
12020 23:20:52.678832 arm64_btitest_bti_c_func_call_using_blr skip
12021 23:20:52.682213 arm64_btitest_bti_j_func_call_using_br_x0 skip
12022 23:20:52.685754 arm64_btitest_bti_j_func_call_using_br_x16 skip
12023 23:20:52.692326 arm64_btitest_bti_j_func_call_using_blr skip
12024 23:20:52.695436 arm64_btitest_bti_jc_func_call_using_br_x0 skip
12025 23:20:52.698442 arm64_btitest_bti_jc_func_call_using_br_x16 skip
12026 23:20:52.705086 arm64_btitest_bti_jc_func_call_using_blr skip
12027 23:20:52.708310 arm64_btitest_paciasp_func_call_using_br_x0 skip
12028 23:20:52.712005 arm64_btitest_paciasp_func_call_using_br_x16 skip
12029 23:20:52.714872 arm64_btitest_paciasp_func_call_using_blr skip
12030 23:20:52.718113 arm64_btitest pass
12031 23:20:52.721590 arm64_nobtitest_nohint_func_call_using_br_x0 skip
12032 23:20:52.727841 arm64_nobtitest_nohint_func_call_using_br_x16 skip
12033 23:20:52.731306 arm64_nobtitest_nohint_func_call_using_blr skip
12034 23:20:52.734543 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
12035 23:20:52.741126 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
12036 23:20:52.744456 arm64_nobtitest_bti_none_func_call_using_blr skip
12037 23:20:52.748104 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
12038 23:20:52.754666 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
12039 23:20:52.757448 arm64_nobtitest_bti_c_func_call_using_blr skip
12040 23:20:52.761386 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
12041 23:20:52.767640 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
12042 23:20:52.770808 arm64_nobtitest_bti_j_func_call_using_blr skip
12043 23:20:52.774058 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
12044 23:20:52.781100 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
12045 23:20:52.784140 arm64_nobtitest_bti_jc_func_call_using_blr skip
12046 23:20:52.787243 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
12047 23:20:52.794055 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
12048 23:20:52.797255 arm64_nobtitest_paciasp_func_call_using_blr skip
12049 23:20:52.800816 arm64_nobtitest pass
12050 23:20:52.803647 arm64_hwcap_cpuinfo_match_RNG pass
12051 23:20:52.803802 arm64_hwcap_sigill_RNG skip
12052 23:20:52.806874 arm64_hwcap_cpuinfo_match_SME pass
12053 23:20:52.810525 arm64_hwcap_sigill_SME pass
12054 23:20:52.813668 arm64_hwcap_cpuinfo_match_SVE pass
12055 23:20:52.816931 arm64_hwcap_sigill_SVE pass
12056 23:20:52.820200 arm64_hwcap_cpuinfo_match_SVE_2 pass
12057 23:20:52.823785 arm64_hwcap_sigill_SVE_2 skip
12058 23:20:52.826761 arm64_hwcap_cpuinfo_match_SVE_AES pass
12059 23:20:52.829976 arm64_hwcap_sigill_SVE_AES skip
12060 23:20:52.833415 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
12061 23:20:52.836540 arm64_hwcap_sigill_SVE2_PMULL skip
12062 23:20:52.840343 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
12063 23:20:52.844256 arm64_hwcap_sigill_SVE2_BITPERM skip
12064 23:20:52.846708 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
12065 23:20:52.850323 arm64_hwcap_sigill_SVE2_SHA3 skip
12066 23:20:52.853288 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
12067 23:20:52.856421 arm64_hwcap_sigill_SVE2_SM4 skip
12068 23:20:52.859751 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
12069 23:20:52.863930 arm64_hwcap_sigill_SVE2_I8MM skip
12070 23:20:52.866632 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
12071 23:20:52.869719 arm64_hwcap_sigill_SVE2_F32MM skip
12072 23:20:52.872661 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
12073 23:20:52.876569 arm64_hwcap_sigill_SVE2_F64MM skip
12074 23:20:52.879390 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
12075 23:20:52.882793 arm64_hwcap_sigill_SVE2_BF16 skip
12076 23:20:52.886397 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
12077 23:20:52.889728 arm64_hwcap_sigill_SVE2_EBF16 skip
12078 23:20:52.893032 arm64_hwcap pass
12079 23:20:52.893200 arm64_ptrace_read_tpidr_one pass
12080 23:20:52.895992 arm64_ptrace_write_tpidr_one pass
12081 23:20:52.899578 arm64_ptrace_verify_tpidr_one pass
12082 23:20:52.903059 arm64_ptrace_count_tpidrs pass
12083 23:20:52.906580 arm64_ptrace_tpidr2_write pass
12084 23:20:52.909255 arm64_ptrace_tpidr2_read pass
12085 23:20:52.913071 arm64_ptrace_write_tpidr_only pass
12086 23:20:52.913287 arm64_ptrace pass
12087 23:20:52.915876 arm64_syscall-abi_getpid_FPSIMD pass
12088 23:20:52.919105 arm64_syscall-abi_sched_yield_FPSIMD pass
12089 23:20:52.922864 arm64_syscall-abi pass
12090 23:20:52.926041 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12091 23:20:52.932435 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
12092 23:20:52.935870 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
12093 23:20:52.939008 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
12094 23:20:52.945926 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
12095 23:20:52.946132 arm64_tpidr2 pass
12096 23:20:52.952468 + ../../utils/send-to-lava.sh ./output/result.txt
12097 23:20:52.955357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
12098 23:20:52.955769 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
12100 23:20:52.962100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12101 23:20:52.962475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12103 23:20:52.968600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12104 23:20:52.968982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12106 23:20:52.975274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12107 23:20:52.975712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12109 23:20:52.981927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12110 23:20:52.982300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12112 23:20:53.032754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12113 23:20:53.033179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12115 23:20:53.088024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12116 23:20:53.088452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12118 23:20:53.140981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12119 23:20:53.141409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12121 23:20:53.194082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12122 23:20:53.194506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12124 23:20:53.243856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12125 23:20:53.244197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12127 23:20:53.295484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12128 23:20:53.295832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12130 23:20:53.346647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12131 23:20:53.347001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12133 23:20:53.396281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12134 23:20:53.396611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12136 23:20:53.449502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12137 23:20:53.449839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12139 23:20:53.501047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12140 23:20:53.501409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12142 23:20:53.550938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12143 23:20:53.551357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12145 23:20:53.607780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12146 23:20:53.608186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12148 23:20:53.660972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12149 23:20:53.661380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12151 23:20:53.714817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12152 23:20:53.715250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12154 23:20:53.762876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12155 23:20:53.763283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12157 23:20:53.816038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12158 23:20:53.816449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12160 23:20:53.865863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12161 23:20:53.866282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12163 23:20:53.918881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12164 23:20:53.919315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12166 23:20:53.968166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12167 23:20:53.968588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12169 23:20:54.023708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12170 23:20:54.024115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12172 23:20:54.077471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12173 23:20:54.077876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12175 23:20:54.130563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12176 23:20:54.130983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12178 23:20:54.181033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12179 23:20:54.181460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12181 23:20:54.233613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12183 23:20:54.236769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12184 23:20:54.288774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
12185 23:20:54.289202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
12187 23:20:54.337749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12188 23:20:54.338181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12190 23:20:54.389519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
12191 23:20:54.389983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
12193 23:20:54.442219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
12194 23:20:54.442650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
12196 23:20:54.498605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
12197 23:20:54.499031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
12199 23:20:54.553241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
12200 23:20:54.553661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
12202 23:20:54.599526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12203 23:20:54.599947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12205 23:20:54.653575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12206 23:20:54.653979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12208 23:20:54.713998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12209 23:20:54.714417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12211 23:20:54.772730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12212 23:20:54.773118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12214 23:20:54.830585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12215 23:20:54.830943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12217 23:20:54.886502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12218 23:20:54.886900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12220 23:20:54.936067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12221 23:20:54.936457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12223 23:20:54.992800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12224 23:20:54.993203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12226 23:20:55.048805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12227 23:20:55.049211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12229 23:20:55.098170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12230 23:20:55.098527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12232 23:20:55.149269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12233 23:20:55.149638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12235 23:20:55.206073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12236 23:20:55.206476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12238 23:20:55.257751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12239 23:20:55.258081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12241 23:20:55.312674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12242 23:20:55.313031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12244 23:20:55.364708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12245 23:20:55.365112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12247 23:20:55.419531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12248 23:20:55.419936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12250 23:20:55.478146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12251 23:20:55.478532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12253 23:20:55.534932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12254 23:20:55.535349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12256 23:20:55.593134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12257 23:20:55.593455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12259 23:20:55.639992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12260 23:20:55.640320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12262 23:20:55.699224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12263 23:20:55.699587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12265 23:20:55.750808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12266 23:20:55.751141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12268 23:20:55.808983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12269 23:20:55.809313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12271 23:20:55.859097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12272 23:20:55.859406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12274 23:20:55.916916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12275 23:20:55.917252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12277 23:20:55.968941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12278 23:20:55.969279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12280 23:20:56.025623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12281 23:20:56.025938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12283 23:20:56.084376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12284 23:20:56.084715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12286 23:20:56.137903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12287 23:20:56.138292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12289 23:20:56.188166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12290 23:20:56.188513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12292 23:20:56.245133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12293 23:20:56.245465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12295 23:20:56.298649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12296 23:20:56.299046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12298 23:20:56.350871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12299 23:20:56.351268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12301 23:20:56.401592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12302 23:20:56.401991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12304 23:20:56.453818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12305 23:20:56.454177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12307 23:20:56.514572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12308 23:20:56.514917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12310 23:20:56.571227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12311 23:20:56.571569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12313 23:20:56.626739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12314 23:20:56.627068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12316 23:20:56.677180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12317 23:20:56.677588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12319 23:20:56.725600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12320 23:20:56.725959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12322 23:20:56.777492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12323 23:20:56.777888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12325 23:20:56.824840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12326 23:20:56.825170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12328 23:20:56.871647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12329 23:20:56.871974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12331 23:20:56.923300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12332 23:20:56.923669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12334 23:20:56.978527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12335 23:20:56.978859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12337 23:20:57.036880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12338 23:20:57.037214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12340 23:20:57.087507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12341 23:20:57.087880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12343 23:20:57.141673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12344 23:20:57.142071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12346 23:20:57.198859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12347 23:20:57.199258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12349 23:20:57.251080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12351 23:20:57.254323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12352 23:20:57.300175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12353 23:20:57.300545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12355 23:20:57.352551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12356 23:20:57.352888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12358 23:20:57.408391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12359 23:20:57.408751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12361 23:20:57.460562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12362 23:20:57.460996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12364 23:20:57.518494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12365 23:20:57.518830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12367 23:20:57.574775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12368 23:20:57.575105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12370 23:20:57.629014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12372 23:20:57.631838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12373 23:20:57.681258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12374 23:20:57.681585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12376 23:20:57.738021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12377 23:20:57.738380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12379 23:20:57.787016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12380 23:20:57.787380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12382 23:20:57.842429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12383 23:20:57.842806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12385 23:20:57.892864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12386 23:20:57.893205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12388 23:20:57.945328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12389 23:20:57.945661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12391 23:20:58.001681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12392 23:20:58.002043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12394 23:20:58.053103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12395 23:20:58.053464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12397 23:20:58.107351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12398 23:20:58.107699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12400 23:20:58.159863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12401 23:20:58.160243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12403 23:20:58.212663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12404 23:20:58.213002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12406 23:20:58.266899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12407 23:20:58.267274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12409 23:20:58.323806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12410 23:20:58.324135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12412 23:20:58.376225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12413 23:20:58.376557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12415 23:20:58.424810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12416 23:20:58.425149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12418 23:20:58.475793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12419 23:20:58.476209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12421 23:20:58.532777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12422 23:20:58.533181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12424 23:20:58.589824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12425 23:20:58.590211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12427 23:20:58.647036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12428 23:20:58.647374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12430 23:20:58.705290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12431 23:20:58.705632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12433 23:20:58.764464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12434 23:20:58.764886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12436 23:20:58.815823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12437 23:20:58.816158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12439 23:20:58.875475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12440 23:20:58.875807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12442 23:20:58.930034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12443 23:20:58.930364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12445 23:20:58.983980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12446 23:20:58.984315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12448 23:20:59.032806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12449 23:20:59.033170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12451 23:20:59.086961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12452 23:20:59.087333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12454 23:20:59.142250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12455 23:20:59.142600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12457 23:20:59.193284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12458 23:20:59.193643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12460 23:20:59.242768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12461 23:20:59.243113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12463 23:20:59.295459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12464 23:20:59.295797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12466 23:20:59.352170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12467 23:20:59.352544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12469 23:20:59.401007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12470 23:20:59.401382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12472 23:20:59.448325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12473 23:20:59.448685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12475 23:20:59.500160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12476 23:20:59.500548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12478 23:20:59.556497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12479 23:20:59.556852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12481 23:20:59.611621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12482 23:20:59.611981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12484 23:20:59.666636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12485 23:20:59.666996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12487 23:20:59.718910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12488 23:20:59.719318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12490 23:20:59.770244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12491 23:20:59.770647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12493 23:20:59.817069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12494 23:20:59.817467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12496 23:20:59.871498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12497 23:20:59.871832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12499 23:20:59.917352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12500 23:20:59.917756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12502 23:20:59.966872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12504 23:20:59.969843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12505 23:21:00.019993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12506 23:21:00.020324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12508 23:21:00.078822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12509 23:21:00.079225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12511 23:21:00.130836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12512 23:21:00.131233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12514 23:21:00.188396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12515 23:21:00.188761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12517 23:21:00.241568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12518 23:21:00.241967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12520 23:21:00.296542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12521 23:21:00.296867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12523 23:21:00.349027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12524 23:21:00.349368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12526 23:21:00.402449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12527 23:21:00.402775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12529 23:21:00.451553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12530 23:21:00.451908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12532 23:21:00.507812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12533 23:21:00.508200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12535 23:21:00.560731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12536 23:21:00.561102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12538 23:21:00.610779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12539 23:21:00.611115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12541 23:21:00.658779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12543 23:21:00.661600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12544 23:21:00.718571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12545 23:21:00.718938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12547 23:21:00.771231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12549 23:21:00.774408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12550 23:21:00.822777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12551 23:21:00.823179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12553 23:21:00.873305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12555 23:21:00.876220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12556 23:21:00.924506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12557 23:21:00.924869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12559 23:21:00.971029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12561 23:21:00.974383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12562 23:21:01.031834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12563 23:21:01.032173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12565 23:21:01.080713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12566 23:21:01.081142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12568 23:21:01.130699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12569 23:21:01.131045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12571 23:21:01.180397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12573 23:21:01.183918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12574 23:21:01.233273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12575 23:21:01.233678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12577 23:21:01.283801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12578 23:21:01.284135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12580 23:21:01.337626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12581 23:21:01.337963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12583 23:21:01.392854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12585 23:21:01.396883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12586 23:21:01.449519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12588 23:21:01.452948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12589 23:21:01.508191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12590 23:21:01.508549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12592 23:21:01.555509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12593 23:21:01.555862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12595 23:21:01.605817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12596 23:21:01.606186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12598 23:21:01.662257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12599 23:21:01.662620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12601 23:21:01.722483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12602 23:21:01.722851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12604 23:21:01.769547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12605 23:21:01.769915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12607 23:21:01.822553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12608 23:21:01.822936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12610 23:21:01.875979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12611 23:21:01.876384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12613 23:21:01.922267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12614 23:21:01.922664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12616 23:21:01.980742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12617 23:21:01.981141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12619 23:21:02.031453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12620 23:21:02.031823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12622 23:21:02.089825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12623 23:21:02.090161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12625 23:21:02.149417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12626 23:21:02.149754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12628 23:21:02.202059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12629 23:21:02.202394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12631 23:21:02.254014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12632 23:21:02.254174 + set +x
12633 23:21:02.254433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12635 23:21:02.260473 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 13248440_1.6.2.3.5>
12636 23:21:02.260774 Received signal: <ENDRUN> 1_kselftest-arm64 13248440_1.6.2.3.5
12637 23:21:02.260885 Ending use of test pattern.
12638 23:21:02.260983 Ending test lava.1_kselftest-arm64 (13248440_1.6.2.3.5), duration 33.19
12640 23:21:02.264015 <LAVA_TEST_RUNNER EXIT>
12641 23:21:02.264272 ok: lava_test_shell seems to have completed
12642 23:21:02.265401 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12643 23:21:02.265557 end: 3.1 lava-test-shell (duration 00:00:34) [common]
12644 23:21:02.265647 end: 3 lava-test-retry (duration 00:00:34) [common]
12645 23:21:02.265737 start: 4 finalize (timeout 00:06:55) [common]
12646 23:21:02.265828 start: 4.1 power-off (timeout 00:00:30) [common]
12647 23:21:02.265981 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
12648 23:21:02.350770 >> Command sent successfully.
12649 23:21:02.353688 Returned 0 in 0 seconds
12650 23:21:02.454133 end: 4.1 power-off (duration 00:00:00) [common]
12652 23:21:02.454658 start: 4.2 read-feedback (timeout 00:06:55) [common]
12653 23:21:02.455065 Listened to connection for namespace 'common' for up to 1s
12654 23:21:03.455430 Finalising connection for namespace 'common'
12655 23:21:03.455619 Disconnecting from shell: Finalise
12656 23:21:03.455711 / #
12657 23:21:03.556026 end: 4.2 read-feedback (duration 00:00:01) [common]
12658 23:21:03.556212 end: 4 finalize (duration 00:00:01) [common]
12659 23:21:03.556366 Cleaning after the job
12660 23:21:03.556511 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/ramdisk
12661 23:21:03.559656 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/kernel
12662 23:21:03.574040 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/dtb
12663 23:21:03.574278 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/nfsrootfs
12664 23:21:03.661593 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248440/tftp-deploy-tcaniien/modules
12665 23:21:03.669100 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248440
12666 23:21:04.404324 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248440
12667 23:21:04.404521 Job finished correctly