Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
1 23:21:35.074739 lava-dispatcher, installed at version: 2024.01
2 23:21:35.074959 start: 0 validate
3 23:21:35.075098 Start time: 2024-04-03 23:21:35.075088+00:00 (UTC)
4 23:21:35.075220 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:21:35.075350 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:21:35.335688 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:21:35.335909 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:21:35.585248 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:21:35.585402 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:21:35.843008 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:21:35.843181 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:21:36.101085 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:21:36.101259 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:21:36.361312 validate duration: 1.29
16 23:21:36.361568 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:21:36.361665 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:21:36.361751 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:21:36.361876 Not decompressing ramdisk as can be used compressed.
20 23:21:36.361962 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:21:36.362048 saving as /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/ramdisk/initrd.cpio.gz
22 23:21:36.362148 total size: 5628169 (5 MB)
23 23:21:36.363347 progress 0 % (0 MB)
24 23:21:36.365149 progress 5 % (0 MB)
25 23:21:36.366881 progress 10 % (0 MB)
26 23:21:36.368373 progress 15 % (0 MB)
27 23:21:36.370013 progress 20 % (1 MB)
28 23:21:36.371566 progress 25 % (1 MB)
29 23:21:36.373204 progress 30 % (1 MB)
30 23:21:36.374891 progress 35 % (1 MB)
31 23:21:36.376333 progress 40 % (2 MB)
32 23:21:36.377948 progress 45 % (2 MB)
33 23:21:36.379447 progress 50 % (2 MB)
34 23:21:36.381038 progress 55 % (2 MB)
35 23:21:36.382722 progress 60 % (3 MB)
36 23:21:36.384173 progress 65 % (3 MB)
37 23:21:36.385801 progress 70 % (3 MB)
38 23:21:36.387299 progress 75 % (4 MB)
39 23:21:36.388918 progress 80 % (4 MB)
40 23:21:36.390456 progress 85 % (4 MB)
41 23:21:36.392082 progress 90 % (4 MB)
42 23:21:36.393667 progress 95 % (5 MB)
43 23:21:36.395173 progress 100 % (5 MB)
44 23:21:36.395400 5 MB downloaded in 0.03 s (161.42 MB/s)
45 23:21:36.395561 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:21:36.395808 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:21:36.395896 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:21:36.395981 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:21:36.396116 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:21:36.396185 saving as /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/kernel/Image
52 23:21:36.396250 total size: 54286848 (51 MB)
53 23:21:36.396313 No compression specified
54 23:21:36.397370 progress 0 % (0 MB)
55 23:21:36.411907 progress 5 % (2 MB)
56 23:21:36.426506 progress 10 % (5 MB)
57 23:21:36.441162 progress 15 % (7 MB)
58 23:21:36.456014 progress 20 % (10 MB)
59 23:21:36.470923 progress 25 % (12 MB)
60 23:21:36.485568 progress 30 % (15 MB)
61 23:21:36.500041 progress 35 % (18 MB)
62 23:21:36.514650 progress 40 % (20 MB)
63 23:21:36.529352 progress 45 % (23 MB)
64 23:21:36.545282 progress 50 % (25 MB)
65 23:21:36.560535 progress 55 % (28 MB)
66 23:21:36.575527 progress 60 % (31 MB)
67 23:21:36.589771 progress 65 % (33 MB)
68 23:21:36.604579 progress 70 % (36 MB)
69 23:21:36.619663 progress 75 % (38 MB)
70 23:21:36.634299 progress 80 % (41 MB)
71 23:21:36.648801 progress 85 % (44 MB)
72 23:21:36.663384 progress 90 % (46 MB)
73 23:21:36.677954 progress 95 % (49 MB)
74 23:21:36.692605 progress 100 % (51 MB)
75 23:21:36.692880 51 MB downloaded in 0.30 s (174.54 MB/s)
76 23:21:36.693037 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:21:36.693276 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:21:36.693364 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:21:36.693461 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:21:36.693603 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:21:36.693673 saving as /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/dtb/mt8192-asurada-spherion-r0.dtb
83 23:21:36.693735 total size: 47230 (0 MB)
84 23:21:36.693797 No compression specified
85 23:21:36.694924 progress 69 % (0 MB)
86 23:21:36.695204 progress 100 % (0 MB)
87 23:21:36.695373 0 MB downloaded in 0.00 s (27.71 MB/s)
88 23:21:36.695506 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:21:36.695739 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:21:36.695860 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:21:36.695981 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:21:36.696127 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:21:36.696199 saving as /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/nfsrootfs/full.rootfs.tar
95 23:21:36.696263 total size: 120894716 (115 MB)
96 23:21:36.696326 Using unxz to decompress xz
97 23:21:36.700457 progress 0 % (0 MB)
98 23:21:37.047830 progress 5 % (5 MB)
99 23:21:37.414314 progress 10 % (11 MB)
100 23:21:37.806315 progress 15 % (17 MB)
101 23:21:38.141111 progress 20 % (23 MB)
102 23:21:38.458496 progress 25 % (28 MB)
103 23:21:38.832593 progress 30 % (34 MB)
104 23:21:39.178534 progress 35 % (40 MB)
105 23:21:39.348907 progress 40 % (46 MB)
106 23:21:39.529802 progress 45 % (51 MB)
107 23:21:39.847615 progress 50 % (57 MB)
108 23:21:40.257452 progress 55 % (63 MB)
109 23:21:40.607797 progress 60 % (69 MB)
110 23:21:40.952799 progress 65 % (74 MB)
111 23:21:41.303784 progress 70 % (80 MB)
112 23:21:41.664798 progress 75 % (86 MB)
113 23:21:42.012827 progress 80 % (92 MB)
114 23:21:42.359767 progress 85 % (98 MB)
115 23:21:42.765042 progress 90 % (103 MB)
116 23:21:43.108648 progress 95 % (109 MB)
117 23:21:43.472694 progress 100 % (115 MB)
118 23:21:43.478612 115 MB downloaded in 6.78 s (17.00 MB/s)
119 23:21:43.478968 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:21:43.479401 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:21:43.479580 start: 1.5 download-retry (timeout 00:09:53) [common]
123 23:21:43.479700 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 23:21:43.479927 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:21:43.480012 saving as /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/modules/modules.tar
126 23:21:43.480151 total size: 8629908 (8 MB)
127 23:21:43.480250 Using unxz to decompress xz
128 23:21:43.485039 progress 0 % (0 MB)
129 23:21:43.507420 progress 5 % (0 MB)
130 23:21:43.533666 progress 10 % (0 MB)
131 23:21:43.559442 progress 15 % (1 MB)
132 23:21:43.583764 progress 20 % (1 MB)
133 23:21:43.618960 progress 25 % (2 MB)
134 23:21:43.647936 progress 30 % (2 MB)
135 23:21:43.672511 progress 35 % (2 MB)
136 23:21:43.698292 progress 40 % (3 MB)
137 23:21:43.730264 progress 45 % (3 MB)
138 23:21:43.762492 progress 50 % (4 MB)
139 23:21:43.788306 progress 55 % (4 MB)
140 23:21:43.817153 progress 60 % (4 MB)
141 23:21:43.842440 progress 65 % (5 MB)
142 23:21:43.867622 progress 70 % (5 MB)
143 23:21:43.895234 progress 75 % (6 MB)
144 23:21:43.931885 progress 80 % (6 MB)
145 23:21:43.963588 progress 85 % (7 MB)
146 23:21:43.994370 progress 90 % (7 MB)
147 23:21:44.027305 progress 95 % (7 MB)
148 23:21:44.055452 progress 100 % (8 MB)
149 23:21:44.060941 8 MB downloaded in 0.58 s (14.17 MB/s)
150 23:21:44.061290 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:21:44.061763 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:21:44.061921 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 23:21:44.062084 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 23:21:47.840430 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13248458/extract-nfsrootfs-bhvk718l
156 23:21:47.840639 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:21:47.840736 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 23:21:47.840911 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_
159 23:21:47.841049 makedir: /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin
160 23:21:47.841153 makedir: /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/tests
161 23:21:47.841254 makedir: /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/results
162 23:21:47.841355 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-add-keys
163 23:21:47.841497 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-add-sources
164 23:21:47.841626 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-background-process-start
165 23:21:47.841754 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-background-process-stop
166 23:21:47.841883 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-common-functions
167 23:21:47.842008 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-echo-ipv4
168 23:21:47.842133 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-install-packages
169 23:21:47.842257 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-installed-packages
170 23:21:47.842380 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-os-build
171 23:21:47.842504 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-probe-channel
172 23:21:47.842630 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-probe-ip
173 23:21:47.842753 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-target-ip
174 23:21:47.842878 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-target-mac
175 23:21:47.843000 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-target-storage
176 23:21:47.843127 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-test-case
177 23:21:47.843250 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-test-event
178 23:21:47.843380 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-test-feedback
179 23:21:47.843506 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-test-raise
180 23:21:47.843629 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-test-reference
181 23:21:47.843754 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-test-runner
182 23:21:47.843877 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-test-set
183 23:21:47.844000 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-test-shell
184 23:21:47.844125 Updating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-add-keys (debian)
185 23:21:47.844276 Updating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-add-sources (debian)
186 23:21:47.844425 Updating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-install-packages (debian)
187 23:21:47.844571 Updating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-installed-packages (debian)
188 23:21:47.844710 Updating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/bin/lava-os-build (debian)
189 23:21:47.844835 Creating /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/environment
190 23:21:47.844933 LAVA metadata
191 23:21:47.845002 - LAVA_JOB_ID=13248458
192 23:21:47.845063 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:21:47.845161 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 23:21:47.845225 skipped lava-vland-overlay
195 23:21:47.845298 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:21:47.845375 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 23:21:47.845435 skipped lava-multinode-overlay
198 23:21:47.845505 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:21:47.845580 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 23:21:47.845651 Loading test definitions
201 23:21:47.845735 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 23:21:47.845806 Using /lava-13248458 at stage 0
203 23:21:47.846101 uuid=13248458_1.6.2.3.1 testdef=None
204 23:21:47.846189 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:21:47.846273 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 23:21:47.846732 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:21:47.846946 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 23:21:47.847512 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:21:47.847737 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 23:21:47.848279 runner path: /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/0/tests/0_timesync-off test_uuid 13248458_1.6.2.3.1
213 23:21:47.848436 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:21:47.848657 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 23:21:47.848730 Using /lava-13248458 at stage 0
217 23:21:47.848824 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:21:47.848908 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/0/tests/1_kselftest-dt'
219 23:21:55.646015 Running '/usr/bin/git checkout kernelci.org
220 23:21:55.830558 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 23:21:55.831787 uuid=13248458_1.6.2.3.5 testdef=None
222 23:21:55.832025 end: 1.6.2.3.5 git-repo-action (duration 00:00:08) [common]
224 23:21:55.832466 start: 1.6.2.3.6 test-overlay (timeout 00:09:41) [common]
225 23:21:55.833826 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:21:55.834239 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:41) [common]
228 23:21:55.836082 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:21:55.836500 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:41) [common]
231 23:21:55.838381 runner path: /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/0/tests/1_kselftest-dt test_uuid 13248458_1.6.2.3.5
232 23:21:55.838523 BOARD='mt8192-asurada-spherion-r0'
233 23:21:55.838636 BRANCH='cip'
234 23:21:55.838744 SKIPFILE='/dev/null'
235 23:21:55.838853 SKIP_INSTALL='True'
236 23:21:55.838959 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:21:55.839069 TST_CASENAME=''
238 23:21:55.839177 TST_CMDFILES='dt'
239 23:21:55.839442 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:21:55.839838 Creating lava-test-runner.conf files
242 23:21:55.839956 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248458/lava-overlay-k03oiqx_/lava-13248458/0 for stage 0
243 23:21:55.840115 - 0_timesync-off
244 23:21:55.840232 - 1_kselftest-dt
245 23:21:55.840402 end: 1.6.2.3 test-definition (duration 00:00:08) [common]
246 23:21:55.840547 start: 1.6.2.4 compress-overlay (timeout 00:09:41) [common]
247 23:22:03.458397 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:22:03.458592 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 23:22:03.458721 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:22:03.458854 end: 1.6.2 lava-overlay (duration 00:00:16) [common]
251 23:22:03.458977 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 23:22:03.636036 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:22:03.636478 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
254 23:22:03.636629 extracting modules file /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248458/extract-nfsrootfs-bhvk718l
255 23:22:03.960275 extracting modules file /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248458/extract-overlay-ramdisk-tu_0u1os/ramdisk
256 23:22:04.193139 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 23:22:04.193341 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
258 23:22:04.193449 [common] Applying overlay to NFS
259 23:22:04.193518 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248458/compress-overlay-h08anlrj/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248458/extract-nfsrootfs-bhvk718l
260 23:22:05.156254 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:22:05.156426 start: 1.6.6 configure-preseed-file (timeout 00:09:31) [common]
262 23:22:05.156522 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:22:05.156612 start: 1.6.7 compress-ramdisk (timeout 00:09:31) [common]
264 23:22:05.156742 Building ramdisk /var/lib/lava/dispatcher/tmp/13248458/extract-overlay-ramdisk-tu_0u1os/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248458/extract-overlay-ramdisk-tu_0u1os/ramdisk
265 23:22:05.580860 >> 130593 blocks
266 23:22:07.675528 rename /var/lib/lava/dispatcher/tmp/13248458/extract-overlay-ramdisk-tu_0u1os/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/ramdisk/ramdisk.cpio.gz
267 23:22:07.676138 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 23:22:07.676340 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 23:22:07.676500 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 23:22:07.676675 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/kernel/Image'
271 23:22:21.480986 Returned 0 in 13 seconds
272 23:22:21.581648 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/kernel/image.itb
273 23:22:21.972396 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:22:21.972765 output: Created: Thu Apr 4 00:22:21 2024
275 23:22:21.972841 output: Image 0 (kernel-1)
276 23:22:21.972904 output: Description:
277 23:22:21.972967 output: Created: Thu Apr 4 00:22:21 2024
278 23:22:21.973024 output: Type: Kernel Image
279 23:22:21.973085 output: Compression: lzma compressed
280 23:22:21.973139 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
281 23:22:21.973193 output: Architecture: AArch64
282 23:22:21.973246 output: OS: Linux
283 23:22:21.973301 output: Load Address: 0x00000000
284 23:22:21.973357 output: Entry Point: 0x00000000
285 23:22:21.973410 output: Hash algo: crc32
286 23:22:21.973466 output: Hash value: d7c9dcc1
287 23:22:21.973520 output: Image 1 (fdt-1)
288 23:22:21.973573 output: Description: mt8192-asurada-spherion-r0
289 23:22:21.973623 output: Created: Thu Apr 4 00:22:21 2024
290 23:22:21.973675 output: Type: Flat Device Tree
291 23:22:21.973726 output: Compression: uncompressed
292 23:22:21.973776 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 23:22:21.973828 output: Architecture: AArch64
294 23:22:21.973878 output: Hash algo: crc32
295 23:22:21.973929 output: Hash value: 4bf0d1ac
296 23:22:21.973980 output: Image 2 (ramdisk-1)
297 23:22:21.974030 output: Description: unavailable
298 23:22:21.974081 output: Created: Thu Apr 4 00:22:21 2024
299 23:22:21.974131 output: Type: RAMDisk Image
300 23:22:21.974182 output: Compression: Unknown Compression
301 23:22:21.974233 output: Data Size: 18766225 Bytes = 18326.39 KiB = 17.90 MiB
302 23:22:21.974284 output: Architecture: AArch64
303 23:22:21.974334 output: OS: Linux
304 23:22:21.974385 output: Load Address: unavailable
305 23:22:21.974435 output: Entry Point: unavailable
306 23:22:21.974486 output: Hash algo: crc32
307 23:22:21.974536 output: Hash value: be85e78c
308 23:22:21.974587 output: Default Configuration: 'conf-1'
309 23:22:21.974637 output: Configuration 0 (conf-1)
310 23:22:21.974688 output: Description: mt8192-asurada-spherion-r0
311 23:22:21.974739 output: Kernel: kernel-1
312 23:22:21.974790 output: Init Ramdisk: ramdisk-1
313 23:22:21.974841 output: FDT: fdt-1
314 23:22:21.974891 output: Loadables: kernel-1
315 23:22:21.974941 output:
316 23:22:21.975146 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 23:22:21.975280 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 23:22:21.975441 end: 1.6 prepare-tftp-overlay (duration 00:00:38) [common]
319 23:22:21.975538 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
320 23:22:21.975618 No LXC device requested
321 23:22:21.975694 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:22:21.975776 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
323 23:22:21.975850 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:22:21.975917 Checking files for TFTP limit of 4294967296 bytes.
325 23:22:21.976402 end: 1 tftp-deploy (duration 00:00:46) [common]
326 23:22:21.976508 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:22:21.976599 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:22:21.976727 substitutions:
329 23:22:21.976792 - {DTB}: 13248458/tftp-deploy-z0knm9t8/dtb/mt8192-asurada-spherion-r0.dtb
330 23:22:21.976854 - {INITRD}: 13248458/tftp-deploy-z0knm9t8/ramdisk/ramdisk.cpio.gz
331 23:22:21.976911 - {KERNEL}: 13248458/tftp-deploy-z0knm9t8/kernel/Image
332 23:22:21.976967 - {LAVA_MAC}: None
333 23:22:21.977021 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13248458/extract-nfsrootfs-bhvk718l
334 23:22:21.977075 - {NFS_SERVER_IP}: 192.168.201.1
335 23:22:21.977128 - {PRESEED_CONFIG}: None
336 23:22:21.977180 - {PRESEED_LOCAL}: None
337 23:22:21.977233 - {RAMDISK}: 13248458/tftp-deploy-z0knm9t8/ramdisk/ramdisk.cpio.gz
338 23:22:21.977285 - {ROOT_PART}: None
339 23:22:21.977337 - {ROOT}: None
340 23:22:21.977389 - {SERVER_IP}: 192.168.201.1
341 23:22:21.977441 - {TEE}: None
342 23:22:21.977493 Parsed boot commands:
343 23:22:21.977544 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:22:21.977727 Parsed boot commands: tftpboot 192.168.201.1 13248458/tftp-deploy-z0knm9t8/kernel/image.itb 13248458/tftp-deploy-z0knm9t8/kernel/cmdline
345 23:22:21.977814 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:22:21.977895 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:22:21.977982 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:22:21.978066 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:22:21.978136 Not connected, no need to disconnect.
350 23:22:21.978207 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:22:21.978288 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:22:21.978354 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 23:22:21.982469 Setting prompt string to ['lava-test: # ']
354 23:22:21.982906 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:22:21.983028 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:22:21.983139 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:22:21.983236 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:22:21.983467 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 23:22:27.112798 >> Command sent successfully.
360 23:22:27.115631 Returned 0 in 5 seconds
361 23:22:27.216096 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:22:27.216434 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:22:27.216577 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:22:27.216666 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:22:27.216752 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:22:27.216850 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:22:27.217164 [Enter `^Ec?' for help]
369 23:22:27.391625
370 23:22:27.391859
371 23:22:27.391974 F0: 102B 0000
372 23:22:27.392044
373 23:22:27.392104 F3: 1001 0000 [0200]
374 23:22:27.394340
375 23:22:27.394422 F3: 1001 0000
376 23:22:27.394486
377 23:22:27.394546 F7: 102D 0000
378 23:22:27.394604
379 23:22:27.398385 F1: 0000 0000
380 23:22:27.398468
381 23:22:27.398533 V0: 0000 0000 [0001]
382 23:22:27.398596
383 23:22:27.401359 00: 0007 8000
384 23:22:27.401445
385 23:22:27.401511 01: 0000 0000
386 23:22:27.401572
387 23:22:27.404634 BP: 0C00 0209 [0000]
388 23:22:27.404716
389 23:22:27.404782 G0: 1182 0000
390 23:22:27.404842
391 23:22:27.407933 EC: 0000 0021 [4000]
392 23:22:27.408031
393 23:22:27.408110 S7: 0000 0000 [0000]
394 23:22:27.408170
395 23:22:27.411696 CC: 0000 0000 [0001]
396 23:22:27.411778
397 23:22:27.411842 T0: 0000 0040 [010F]
398 23:22:27.411903
399 23:22:27.411961 Jump to BL
400 23:22:27.415132
401 23:22:27.438319
402 23:22:27.438403
403 23:22:27.438469
404 23:22:27.445181 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:22:27.448282 ARM64: Exception handlers installed.
406 23:22:27.452338 ARM64: Testing exception
407 23:22:27.455670 ARM64: Done test exception
408 23:22:27.462598 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:22:27.472372 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:22:27.479259 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:22:27.489416 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:22:27.495522 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:22:27.505592 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:22:27.515718 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:22:27.522320 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:22:27.540853 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:22:27.544500 WDT: Last reset was cold boot
418 23:22:27.547374 SPI1(PAD0) initialized at 2873684 Hz
419 23:22:27.551251 SPI5(PAD0) initialized at 992727 Hz
420 23:22:27.554055 VBOOT: Loading verstage.
421 23:22:27.560944 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:22:27.564401 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:22:27.567627 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:22:27.570697 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:22:27.578347 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:22:27.585166 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:22:27.595759 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 23:22:27.595841
429 23:22:27.595905
430 23:22:27.606316 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:22:27.609280 ARM64: Exception handlers installed.
432 23:22:27.612914 ARM64: Testing exception
433 23:22:27.612999 ARM64: Done test exception
434 23:22:27.619887 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:22:27.623203 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:22:27.636999 Probing TPM: . done!
437 23:22:27.637082 TPM ready after 0 ms
438 23:22:27.644373 Connected to device vid:did:rid of 1ae0:0028:00
439 23:22:27.650878 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 23:22:27.709419 Initialized TPM device CR50 revision 0
441 23:22:27.721226 tlcl_send_startup: Startup return code is 0
442 23:22:27.721326 TPM: setup succeeded
443 23:22:27.732665 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:22:27.741046 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:22:27.753495 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:22:27.763854 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:22:27.767037 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:22:27.771269 in-header: 03 07 00 00 08 00 00 00
449 23:22:27.774800 in-data: aa e4 47 04 13 02 00 00
450 23:22:27.779222 Chrome EC: UHEPI supported
451 23:22:27.785833 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:22:27.789774 in-header: 03 95 00 00 08 00 00 00
453 23:22:27.792972 in-data: 18 20 20 08 00 00 00 00
454 23:22:27.793094 Phase 1
455 23:22:27.796082 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:22:27.803525 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:22:27.807594 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:22:27.810881 Recovery requested (1009000e)
459 23:22:27.819998 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:22:27.825088 tlcl_extend: response is 0
461 23:22:27.834464 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:22:27.840302 tlcl_extend: response is 0
463 23:22:27.847196 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:22:27.867148 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 23:22:27.873726 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:22:27.873814
467 23:22:27.873880
468 23:22:27.883878 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:22:27.886921 ARM64: Exception handlers installed.
470 23:22:27.890648 ARM64: Testing exception
471 23:22:27.890734 ARM64: Done test exception
472 23:22:27.912419 pmic_efuse_setting: Set efuses in 11 msecs
473 23:22:27.916204 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:22:27.922734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:22:27.926097 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:22:27.933154 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:22:27.936784 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:22:27.940167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:22:27.947693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:22:27.950940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:22:27.954839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:22:27.958827 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:22:27.965766 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:22:27.969579 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:22:27.973373 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:22:27.979949 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:22:27.983912 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:22:27.990912 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:22:27.994772 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:22:28.002131 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:22:28.009263 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:22:28.012725 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:22:28.020099 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:22:28.024318 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:22:28.031465 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:22:28.034819 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:22:28.042671 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:22:28.046160 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:22:28.053523 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:22:28.057048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:22:28.060675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:22:28.067373 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:22:28.071211 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:22:28.078294 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:22:28.081902 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:22:28.085680 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:22:28.093154 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:22:28.096493 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:22:28.100226 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:22:28.107706 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:22:28.111611 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:22:28.115293 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:22:28.119021 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:22:28.126313 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:22:28.129628 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:22:28.133651 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:22:28.137235 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:22:28.141235 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:22:28.148869 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:22:28.152184 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:22:28.155683 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:22:28.159631 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:22:28.163007 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:22:28.166645 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:22:28.174476 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:22:28.185107 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:22:28.189414 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:22:28.196057 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:22:28.206933 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:22:28.210599 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:22:28.214259 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:22:28.217063 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:22:28.225928 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x21
534 23:22:28.233031 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:22:28.236688 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 23:22:28.239758 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:22:28.250387 [RTC]rtc_get_frequency_meter,154: input=15, output=851
538 23:22:28.259928 [RTC]rtc_get_frequency_meter,154: input=7, output=724
539 23:22:28.269144 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 23:22:28.278671 [RTC]rtc_get_frequency_meter,154: input=13, output=820
541 23:22:28.288622 [RTC]rtc_get_frequency_meter,154: input=12, output=804
542 23:22:28.297709 [RTC]rtc_get_frequency_meter,154: input=11, output=788
543 23:22:28.307256 [RTC]rtc_get_frequency_meter,154: input=12, output=803
544 23:22:28.311194 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 23:22:28.315270 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 23:22:28.319412 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:22:28.326382 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 23:22:28.329933 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:22:28.333780 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 23:22:28.336975 ADC[4]: Raw value=905541 ID=7
551 23:22:28.337099 ADC[3]: Raw value=213916 ID=1
552 23:22:28.340715 RAM Code: 0x71
553 23:22:28.344656 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:22:28.348220 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:22:28.359235 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:22:28.366499 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:22:28.366628 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:22:28.370250 in-header: 03 07 00 00 08 00 00 00
559 23:22:28.374320 in-data: aa e4 47 04 13 02 00 00
560 23:22:28.377595 Chrome EC: UHEPI supported
561 23:22:28.385490 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:22:28.389088 in-header: 03 95 00 00 08 00 00 00
563 23:22:28.392865 in-data: 18 20 20 08 00 00 00 00
564 23:22:28.396355 MRC: failed to locate region type 0.
565 23:22:28.400171 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:22:28.404388 DRAM-K: Running full calibration
567 23:22:28.411332 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:22:28.411470 header.status = 0x0
569 23:22:28.414718 header.version = 0x6 (expected: 0x6)
570 23:22:28.418272 header.size = 0xd00 (expected: 0xd00)
571 23:22:28.422057 header.flags = 0x0
572 23:22:28.429092 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:22:28.446517 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 23:22:28.453942 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:22:28.454070 dram_init: ddr_geometry: 2
576 23:22:28.457249 [EMI] MDL number = 2
577 23:22:28.457355 [EMI] Get MDL freq = 0
578 23:22:28.460919 dram_init: ddr_type: 0
579 23:22:28.464852 is_discrete_lpddr4: 1
580 23:22:28.464965 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:22:28.468226
582 23:22:28.468328
583 23:22:28.468420 [Bian_co] ETT version 0.0.0.1
584 23:22:28.475109 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:22:28.475196
586 23:22:28.478979 dramc_set_vcore_voltage set vcore to 650000
587 23:22:28.479065 Read voltage for 800, 4
588 23:22:28.482821 Vio18 = 0
589 23:22:28.482906 Vcore = 650000
590 23:22:28.482973 Vdram = 0
591 23:22:28.483039 Vddq = 0
592 23:22:28.486310 Vmddr = 0
593 23:22:28.486395 dram_init: config_dvfs: 1
594 23:22:28.493456 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:22:28.496616 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:22:28.499812 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 23:22:28.507012 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 23:22:28.510118 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 23:22:28.513244 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 23:22:28.517281 MEM_TYPE=3, freq_sel=18
601 23:22:28.517394 sv_algorithm_assistance_LP4_1600
602 23:22:28.520637 ============ PULL DRAM RESETB DOWN ============
603 23:22:28.528006 ========== PULL DRAM RESETB DOWN end =========
604 23:22:28.531790 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:22:28.535142 ===================================
606 23:22:28.537979 LPDDR4 DRAM CONFIGURATION
607 23:22:28.541470 ===================================
608 23:22:28.541578 EX_ROW_EN[0] = 0x0
609 23:22:28.544971 EX_ROW_EN[1] = 0x0
610 23:22:28.545057 LP4Y_EN = 0x0
611 23:22:28.548139 WORK_FSP = 0x0
612 23:22:28.548249 WL = 0x2
613 23:22:28.551384 RL = 0x2
614 23:22:28.551514 BL = 0x2
615 23:22:28.554786 RPST = 0x0
616 23:22:28.554911 RD_PRE = 0x0
617 23:22:28.558236 WR_PRE = 0x1
618 23:22:28.558362 WR_PST = 0x0
619 23:22:28.561639 DBI_WR = 0x0
620 23:22:28.561755 DBI_RD = 0x0
621 23:22:28.564668 OTF = 0x1
622 23:22:28.568071 ===================================
623 23:22:28.571292 ===================================
624 23:22:28.571389 ANA top config
625 23:22:28.575147 ===================================
626 23:22:28.578212 DLL_ASYNC_EN = 0
627 23:22:28.581631 ALL_SLAVE_EN = 1
628 23:22:28.585069 NEW_RANK_MODE = 1
629 23:22:28.585156 DLL_IDLE_MODE = 1
630 23:22:28.587861 LP45_APHY_COMB_EN = 1
631 23:22:28.591334 TX_ODT_DIS = 1
632 23:22:28.594863 NEW_8X_MODE = 1
633 23:22:28.597995 ===================================
634 23:22:28.601232 ===================================
635 23:22:28.604663 data_rate = 1600
636 23:22:28.604749 CKR = 1
637 23:22:28.607846 DQ_P2S_RATIO = 8
638 23:22:28.611206 ===================================
639 23:22:28.614632 CA_P2S_RATIO = 8
640 23:22:28.618102 DQ_CA_OPEN = 0
641 23:22:28.621417 DQ_SEMI_OPEN = 0
642 23:22:28.624873 CA_SEMI_OPEN = 0
643 23:22:28.624951 CA_FULL_RATE = 0
644 23:22:28.628111 DQ_CKDIV4_EN = 1
645 23:22:28.631697 CA_CKDIV4_EN = 1
646 23:22:28.634846 CA_PREDIV_EN = 0
647 23:22:28.638158 PH8_DLY = 0
648 23:22:28.641862 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:22:28.641977 DQ_AAMCK_DIV = 4
650 23:22:28.644689 CA_AAMCK_DIV = 4
651 23:22:28.648012 CA_ADMCK_DIV = 4
652 23:22:28.651443 DQ_TRACK_CA_EN = 0
653 23:22:28.654250 CA_PICK = 800
654 23:22:28.657599 CA_MCKIO = 800
655 23:22:28.661404 MCKIO_SEMI = 0
656 23:22:28.661547 PLL_FREQ = 3068
657 23:22:28.665703 DQ_UI_PI_RATIO = 32
658 23:22:28.668856 CA_UI_PI_RATIO = 0
659 23:22:28.672427 ===================================
660 23:22:28.676347 ===================================
661 23:22:28.676430 memory_type:LPDDR4
662 23:22:28.679873 GP_NUM : 10
663 23:22:28.679956 SRAM_EN : 1
664 23:22:28.683944 MD32_EN : 0
665 23:22:28.687479 ===================================
666 23:22:28.687563 [ANA_INIT] >>>>>>>>>>>>>>
667 23:22:28.691246 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:22:28.695139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:22:28.697937 ===================================
670 23:22:28.701567 data_rate = 1600,PCW = 0X7600
671 23:22:28.704489 ===================================
672 23:22:28.707793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:22:28.714533 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:22:28.717912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:22:28.724416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:22:28.728300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:22:28.731078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:22:28.731163 [ANA_INIT] flow start
679 23:22:28.734453 [ANA_INIT] PLL >>>>>>>>
680 23:22:28.737805 [ANA_INIT] PLL <<<<<<<<
681 23:22:28.737891 [ANA_INIT] MIDPI >>>>>>>>
682 23:22:28.741578 [ANA_INIT] MIDPI <<<<<<<<
683 23:22:28.744644 [ANA_INIT] DLL >>>>>>>>
684 23:22:28.744730 [ANA_INIT] flow end
685 23:22:28.751379 ============ LP4 DIFF to SE enter ============
686 23:22:28.754784 ============ LP4 DIFF to SE exit ============
687 23:22:28.757767 [ANA_INIT] <<<<<<<<<<<<<
688 23:22:28.761346 [Flow] Enable top DCM control >>>>>
689 23:22:28.764425 [Flow] Enable top DCM control <<<<<
690 23:22:28.764554 Enable DLL master slave shuffle
691 23:22:28.771179 ==============================================================
692 23:22:28.774284 Gating Mode config
693 23:22:28.777948 ==============================================================
694 23:22:28.781355 Config description:
695 23:22:28.790964 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:22:28.797842 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:22:28.801249 SELPH_MODE 0: By rank 1: By Phase
698 23:22:28.807546 ==============================================================
699 23:22:28.810741 GAT_TRACK_EN = 1
700 23:22:28.814579 RX_GATING_MODE = 2
701 23:22:28.817535 RX_GATING_TRACK_MODE = 2
702 23:22:28.821130 SELPH_MODE = 1
703 23:22:28.823981 PICG_EARLY_EN = 1
704 23:22:28.824077 VALID_LAT_VALUE = 1
705 23:22:28.830947 ==============================================================
706 23:22:28.833968 Enter into Gating configuration >>>>
707 23:22:28.837346 Exit from Gating configuration <<<<
708 23:22:28.840904 Enter into DVFS_PRE_config >>>>>
709 23:22:28.850754 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:22:28.853917 Exit from DVFS_PRE_config <<<<<
711 23:22:28.857568 Enter into PICG configuration >>>>
712 23:22:28.860774 Exit from PICG configuration <<<<
713 23:22:28.863769 [RX_INPUT] configuration >>>>>
714 23:22:28.867289 [RX_INPUT] configuration <<<<<
715 23:22:28.870440 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:22:28.876884 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:22:28.883484 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:22:28.890974 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:22:28.896975 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:22:28.903881 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:22:28.907207 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:22:28.910169 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:22:28.913629 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:22:28.920477 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:22:28.923263 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:22:28.926861 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:22:28.930614 ===================================
728 23:22:28.933291 LPDDR4 DRAM CONFIGURATION
729 23:22:28.937103 ===================================
730 23:22:28.937216 EX_ROW_EN[0] = 0x0
731 23:22:28.940346 EX_ROW_EN[1] = 0x0
732 23:22:28.940420 LP4Y_EN = 0x0
733 23:22:28.943124 WORK_FSP = 0x0
734 23:22:28.946515 WL = 0x2
735 23:22:28.946615 RL = 0x2
736 23:22:28.949968 BL = 0x2
737 23:22:28.950054 RPST = 0x0
738 23:22:28.953208 RD_PRE = 0x0
739 23:22:28.953292 WR_PRE = 0x1
740 23:22:28.956606 WR_PST = 0x0
741 23:22:28.956708 DBI_WR = 0x0
742 23:22:28.959825 DBI_RD = 0x0
743 23:22:28.959910 OTF = 0x1
744 23:22:28.963044 ===================================
745 23:22:28.966348 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:22:28.973419 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:22:28.976470 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:22:28.979748 ===================================
749 23:22:28.983149 LPDDR4 DRAM CONFIGURATION
750 23:22:28.986372 ===================================
751 23:22:28.986456 EX_ROW_EN[0] = 0x10
752 23:22:28.989816 EX_ROW_EN[1] = 0x0
753 23:22:28.989900 LP4Y_EN = 0x0
754 23:22:28.993150 WORK_FSP = 0x0
755 23:22:28.993237 WL = 0x2
756 23:22:28.996559 RL = 0x2
757 23:22:28.996642 BL = 0x2
758 23:22:28.999915 RPST = 0x0
759 23:22:29.003266 RD_PRE = 0x0
760 23:22:29.003382 WR_PRE = 0x1
761 23:22:29.006586 WR_PST = 0x0
762 23:22:29.006669 DBI_WR = 0x0
763 23:22:29.009731 DBI_RD = 0x0
764 23:22:29.009842 OTF = 0x1
765 23:22:29.012875 ===================================
766 23:22:29.019791 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:22:29.023375 nWR fixed to 40
768 23:22:29.026590 [ModeRegInit_LP4] CH0 RK0
769 23:22:29.026675 [ModeRegInit_LP4] CH0 RK1
770 23:22:29.030421 [ModeRegInit_LP4] CH1 RK0
771 23:22:29.033303 [ModeRegInit_LP4] CH1 RK1
772 23:22:29.033386 match AC timing 13
773 23:22:29.040090 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:22:29.043229 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:22:29.046554 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:22:29.053191 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:22:29.056886 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:22:29.056970 [EMI DOE] emi_dcm 0
779 23:22:29.062945 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:22:29.063029 ==
781 23:22:29.066686 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:22:29.069849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:22:29.069933 ==
784 23:22:29.076809 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:22:29.083227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:22:29.090869 [CA 0] Center 37 (7~68) winsize 62
787 23:22:29.094450 [CA 1] Center 37 (7~68) winsize 62
788 23:22:29.097541 [CA 2] Center 34 (4~65) winsize 62
789 23:22:29.100944 [CA 3] Center 35 (4~66) winsize 63
790 23:22:29.103927 [CA 4] Center 34 (3~65) winsize 63
791 23:22:29.107617 [CA 5] Center 33 (3~64) winsize 62
792 23:22:29.107701
793 23:22:29.110567 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 23:22:29.110647
795 23:22:29.114446 [CATrainingPosCal] consider 1 rank data
796 23:22:29.117199 u2DelayCellTimex100 = 270/100 ps
797 23:22:29.120740 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 23:22:29.123893 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 23:22:29.130658 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 23:22:29.133972 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 23:22:29.137307 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 23:22:29.140389 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 23:22:29.140499
804 23:22:29.143631 CA PerBit enable=1, Macro0, CA PI delay=33
805 23:22:29.143722
806 23:22:29.147258 [CBTSetCACLKResult] CA Dly = 33
807 23:22:29.150569 CS Dly: 6 (0~37)
808 23:22:29.150645 ==
809 23:22:29.153775 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:22:29.157076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:22:29.157166 ==
812 23:22:29.160247 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:22:29.167189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:22:29.177518 [CA 0] Center 38 (7~69) winsize 63
815 23:22:29.180901 [CA 1] Center 37 (7~68) winsize 62
816 23:22:29.183976 [CA 2] Center 35 (5~66) winsize 62
817 23:22:29.186827 [CA 3] Center 35 (4~66) winsize 63
818 23:22:29.190192 [CA 4] Center 34 (3~65) winsize 63
819 23:22:29.193649 [CA 5] Center 33 (3~64) winsize 62
820 23:22:29.193733
821 23:22:29.196794 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 23:22:29.196899
823 23:22:29.200125 [CATrainingPosCal] consider 2 rank data
824 23:22:29.203546 u2DelayCellTimex100 = 270/100 ps
825 23:22:29.207083 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 23:22:29.213565 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 23:22:29.217002 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
828 23:22:29.220292 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 23:22:29.223558 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
830 23:22:29.226980 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 23:22:29.227087
832 23:22:29.230273 CA PerBit enable=1, Macro0, CA PI delay=33
833 23:22:29.230355
834 23:22:29.233515 [CBTSetCACLKResult] CA Dly = 33
835 23:22:29.236851 CS Dly: 6 (0~38)
836 23:22:29.236950
837 23:22:29.240333 ----->DramcWriteLeveling(PI) begin...
838 23:22:29.240417 ==
839 23:22:29.244163 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:22:29.247618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:22:29.247701 ==
842 23:22:29.251857 Write leveling (Byte 0): 30 => 30
843 23:22:29.251942 Write leveling (Byte 1): 28 => 28
844 23:22:29.254917 DramcWriteLeveling(PI) end<-----
845 23:22:29.254999
846 23:22:29.255063 ==
847 23:22:29.258623 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:22:29.265226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:22:29.265312 ==
850 23:22:29.265382 [Gating] SW mode calibration
851 23:22:29.275734 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:22:29.278681 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:22:29.282255 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:22:29.288735 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 23:22:29.291885 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 23:22:29.295514 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:22:29.302151 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:22:29.305253 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:22:29.308530 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:22:29.315099 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:22:29.318714 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:22:29.321791 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:22:29.328756 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:22:29.332152 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:22:29.335529 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:22:29.342382 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:22:29.345510 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:22:29.348744 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:22:29.352101 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:22:29.358657 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 23:22:29.362087 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 23:22:29.364921 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:22:29.371968 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:22:29.375029 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:22:29.378315 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:22:29.384964 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:22:29.388517 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:22:29.391459 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:22:29.398283 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
880 23:22:29.401923 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
881 23:22:29.404956 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:22:29.411810 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:22:29.415239 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:22:29.418149 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:22:29.424902 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:22:29.428370 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
887 23:22:29.431818 0 10 8 | B1->B0 | 3333 2525 | 1 0 | (1 0) (0 0)
888 23:22:29.438487 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
889 23:22:29.441570 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:22:29.444847 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:22:29.451624 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:22:29.455225 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:22:29.457928 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:22:29.465099 0 11 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
895 23:22:29.467806 0 11 8 | B1->B0 | 2727 4545 | 1 0 | (1 1) (0 0)
896 23:22:29.471601 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
897 23:22:29.478088 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:22:29.481385 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:22:29.484535 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:22:29.491451 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:22:29.494670 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:22:29.497730 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 23:22:29.504420 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 23:22:29.507873 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:22:29.510882 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:22:29.517731 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:22:29.520941 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:22:29.524589 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:22:29.531415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:22:29.534135 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:22:29.538115 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:22:29.540913 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:22:29.547811 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:22:29.551117 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:22:29.554358 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:22:29.560743 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:22:29.563781 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:22:29.567566 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 23:22:29.574295 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 23:22:29.577196 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 23:22:29.580413 Total UI for P1: 0, mck2ui 16
922 23:22:29.583655 best dqsien dly found for B0: ( 0, 14, 8)
923 23:22:29.587336 Total UI for P1: 0, mck2ui 16
924 23:22:29.590821 best dqsien dly found for B1: ( 0, 14, 10)
925 23:22:29.594197 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 23:22:29.597467 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 23:22:29.597551
928 23:22:29.600395 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 23:22:29.604136 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 23:22:29.607121 [Gating] SW calibration Done
931 23:22:29.607228 ==
932 23:22:29.610277 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:22:29.614353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:22:29.617945 ==
935 23:22:29.618029 RX Vref Scan: 0
936 23:22:29.618114
937 23:22:29.621283 RX Vref 0 -> 0, step: 1
938 23:22:29.621362
939 23:22:29.621458 RX Delay -130 -> 252, step: 16
940 23:22:29.627820 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 23:22:29.631204 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 23:22:29.634161 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 23:22:29.637656 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 23:22:29.640959 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 23:22:29.648200 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 23:22:29.651267 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 23:22:29.654551 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 23:22:29.657907 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 23:22:29.660931 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
950 23:22:29.667411 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 23:22:29.671345 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 23:22:29.674506 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 23:22:29.677950 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 23:22:29.684079 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 23:22:29.687241 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 23:22:29.687324 ==
957 23:22:29.690534 Dram Type= 6, Freq= 0, CH_0, rank 0
958 23:22:29.693952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 23:22:29.694034 ==
960 23:22:29.697729 DQS Delay:
961 23:22:29.697842 DQS0 = 0, DQS1 = 0
962 23:22:29.697906 DQM Delay:
963 23:22:29.700952 DQM0 = 88, DQM1 = 76
964 23:22:29.701047 DQ Delay:
965 23:22:29.704284 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 23:22:29.707782 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
967 23:22:29.710587 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
968 23:22:29.714084 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 23:22:29.714171
970 23:22:29.714236
971 23:22:29.714296 ==
972 23:22:29.717408 Dram Type= 6, Freq= 0, CH_0, rank 0
973 23:22:29.724095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 23:22:29.724178 ==
975 23:22:29.724245
976 23:22:29.724310
977 23:22:29.724369 TX Vref Scan disable
978 23:22:29.727693 == TX Byte 0 ==
979 23:22:29.730789 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 23:22:29.737244 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 23:22:29.737326 == TX Byte 1 ==
982 23:22:29.740727 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 23:22:29.747420 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 23:22:29.747501 ==
985 23:22:29.750870 Dram Type= 6, Freq= 0, CH_0, rank 0
986 23:22:29.753784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 23:22:29.753888 ==
988 23:22:29.766501 TX Vref=22, minBit 1, minWin=26, winSum=436
989 23:22:29.769697 TX Vref=24, minBit 1, minWin=26, winSum=443
990 23:22:29.772947 TX Vref=26, minBit 0, minWin=27, winSum=451
991 23:22:29.776431 TX Vref=28, minBit 3, minWin=27, winSum=448
992 23:22:29.779818 TX Vref=30, minBit 2, minWin=27, winSum=451
993 23:22:29.783033 TX Vref=32, minBit 2, minWin=27, winSum=446
994 23:22:29.789714 [TxChooseVref] Worse bit 0, Min win 27, Win sum 451, Final Vref 26
995 23:22:29.789818
996 23:22:29.793013 Final TX Range 1 Vref 26
997 23:22:29.793128
998 23:22:29.793219 ==
999 23:22:29.796509 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:22:29.799795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:22:29.799871 ==
1002 23:22:29.799935
1003 23:22:29.803175
1004 23:22:29.803297 TX Vref Scan disable
1005 23:22:29.806264 == TX Byte 0 ==
1006 23:22:29.809627 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 23:22:29.812898 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 23:22:29.816526 == TX Byte 1 ==
1009 23:22:29.819694 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 23:22:29.826072 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 23:22:29.826176
1012 23:22:29.826269 [DATLAT]
1013 23:22:29.826359 Freq=800, CH0 RK0
1014 23:22:29.826446
1015 23:22:29.829192 DATLAT Default: 0xa
1016 23:22:29.832323 0, 0xFFFF, sum = 0
1017 23:22:29.832400 1, 0xFFFF, sum = 0
1018 23:22:29.835731 2, 0xFFFF, sum = 0
1019 23:22:29.835844 3, 0xFFFF, sum = 0
1020 23:22:29.839141 4, 0xFFFF, sum = 0
1021 23:22:29.839244 5, 0xFFFF, sum = 0
1022 23:22:29.842239 6, 0xFFFF, sum = 0
1023 23:22:29.842357 7, 0xFFFF, sum = 0
1024 23:22:29.845492 8, 0xFFFF, sum = 0
1025 23:22:29.845602 9, 0x0, sum = 1
1026 23:22:29.849234 10, 0x0, sum = 2
1027 23:22:29.849337 11, 0x0, sum = 3
1028 23:22:29.852102 12, 0x0, sum = 4
1029 23:22:29.852202 best_step = 10
1030 23:22:29.852293
1031 23:22:29.852380 ==
1032 23:22:29.855936 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 23:22:29.859111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 23:22:29.859192 ==
1035 23:22:29.862427 RX Vref Scan: 1
1036 23:22:29.862552
1037 23:22:29.865534 Set Vref Range= 32 -> 127
1038 23:22:29.865639
1039 23:22:29.865731 RX Vref 32 -> 127, step: 1
1040 23:22:29.865820
1041 23:22:29.869049 RX Delay -95 -> 252, step: 8
1042 23:22:29.869144
1043 23:22:29.872276 Set Vref, RX VrefLevel [Byte0]: 32
1044 23:22:29.875772 [Byte1]: 32
1045 23:22:29.879052
1046 23:22:29.879144 Set Vref, RX VrefLevel [Byte0]: 33
1047 23:22:29.882454 [Byte1]: 33
1048 23:22:29.886744
1049 23:22:29.886858 Set Vref, RX VrefLevel [Byte0]: 34
1050 23:22:29.890169 [Byte1]: 34
1051 23:22:29.894074
1052 23:22:29.894181 Set Vref, RX VrefLevel [Byte0]: 35
1053 23:22:29.897732 [Byte1]: 35
1054 23:22:29.902149
1055 23:22:29.902256 Set Vref, RX VrefLevel [Byte0]: 36
1056 23:22:29.905451 [Byte1]: 36
1057 23:22:29.909718
1058 23:22:29.909826 Set Vref, RX VrefLevel [Byte0]: 37
1059 23:22:29.913070 [Byte1]: 37
1060 23:22:29.917506
1061 23:22:29.917706 Set Vref, RX VrefLevel [Byte0]: 38
1062 23:22:29.920945 [Byte1]: 38
1063 23:22:29.924634
1064 23:22:29.924740 Set Vref, RX VrefLevel [Byte0]: 39
1065 23:22:29.927906 [Byte1]: 39
1066 23:22:29.932273
1067 23:22:29.932377 Set Vref, RX VrefLevel [Byte0]: 40
1068 23:22:29.935818 [Byte1]: 40
1069 23:22:29.939847
1070 23:22:29.939954 Set Vref, RX VrefLevel [Byte0]: 41
1071 23:22:29.943349 [Byte1]: 41
1072 23:22:29.947662
1073 23:22:29.947789 Set Vref, RX VrefLevel [Byte0]: 42
1074 23:22:29.954188 [Byte1]: 42
1075 23:22:29.954298
1076 23:22:29.957425 Set Vref, RX VrefLevel [Byte0]: 43
1077 23:22:29.960336 [Byte1]: 43
1078 23:22:29.960442
1079 23:22:29.963560 Set Vref, RX VrefLevel [Byte0]: 44
1080 23:22:29.967261 [Byte1]: 44
1081 23:22:29.967373
1082 23:22:29.970376 Set Vref, RX VrefLevel [Byte0]: 45
1083 23:22:29.973509 [Byte1]: 45
1084 23:22:29.977610
1085 23:22:29.977714 Set Vref, RX VrefLevel [Byte0]: 46
1086 23:22:29.980752 [Byte1]: 46
1087 23:22:29.985285
1088 23:22:29.985392 Set Vref, RX VrefLevel [Byte0]: 47
1089 23:22:29.988718 [Byte1]: 47
1090 23:22:29.992822
1091 23:22:29.992925 Set Vref, RX VrefLevel [Byte0]: 48
1092 23:22:29.996264 [Byte1]: 48
1093 23:22:30.000262
1094 23:22:30.000366 Set Vref, RX VrefLevel [Byte0]: 49
1095 23:22:30.003662 [Byte1]: 49
1096 23:22:30.007931
1097 23:22:30.008037 Set Vref, RX VrefLevel [Byte0]: 50
1098 23:22:30.011196 [Byte1]: 50
1099 23:22:30.015846
1100 23:22:30.015960 Set Vref, RX VrefLevel [Byte0]: 51
1101 23:22:30.019312 [Byte1]: 51
1102 23:22:30.023193
1103 23:22:30.023294 Set Vref, RX VrefLevel [Byte0]: 52
1104 23:22:30.026986 [Byte1]: 52
1105 23:22:30.030909
1106 23:22:30.031014 Set Vref, RX VrefLevel [Byte0]: 53
1107 23:22:30.034014 [Byte1]: 53
1108 23:22:30.038594
1109 23:22:30.038695 Set Vref, RX VrefLevel [Byte0]: 54
1110 23:22:30.041668 [Byte1]: 54
1111 23:22:30.046393
1112 23:22:30.046496 Set Vref, RX VrefLevel [Byte0]: 55
1113 23:22:30.049252 [Byte1]: 55
1114 23:22:30.053656
1115 23:22:30.053781 Set Vref, RX VrefLevel [Byte0]: 56
1116 23:22:30.057084 [Byte1]: 56
1117 23:22:30.061100
1118 23:22:30.061177 Set Vref, RX VrefLevel [Byte0]: 57
1119 23:22:30.065139 [Byte1]: 57
1120 23:22:30.068717
1121 23:22:30.068817 Set Vref, RX VrefLevel [Byte0]: 58
1122 23:22:30.071991 [Byte1]: 58
1123 23:22:30.076605
1124 23:22:30.076690 Set Vref, RX VrefLevel [Byte0]: 59
1125 23:22:30.079626 [Byte1]: 59
1126 23:22:30.083908
1127 23:22:30.083988 Set Vref, RX VrefLevel [Byte0]: 60
1128 23:22:30.087058 [Byte1]: 60
1129 23:22:30.091420
1130 23:22:30.091505 Set Vref, RX VrefLevel [Byte0]: 61
1131 23:22:30.094712 [Byte1]: 61
1132 23:22:30.099323
1133 23:22:30.099434 Set Vref, RX VrefLevel [Byte0]: 62
1134 23:22:30.102996 [Byte1]: 62
1135 23:22:30.106701
1136 23:22:30.106781 Set Vref, RX VrefLevel [Byte0]: 63
1137 23:22:30.110108 [Byte1]: 63
1138 23:22:30.114200
1139 23:22:30.114309 Set Vref, RX VrefLevel [Byte0]: 64
1140 23:22:30.117557 [Byte1]: 64
1141 23:22:30.122330
1142 23:22:30.122449 Set Vref, RX VrefLevel [Byte0]: 65
1143 23:22:30.125211 [Byte1]: 65
1144 23:22:30.129795
1145 23:22:30.129906 Set Vref, RX VrefLevel [Byte0]: 66
1146 23:22:30.132893 [Byte1]: 66
1147 23:22:30.137402
1148 23:22:30.137517 Set Vref, RX VrefLevel [Byte0]: 67
1149 23:22:30.140929 [Byte1]: 67
1150 23:22:30.144839
1151 23:22:30.144960 Set Vref, RX VrefLevel [Byte0]: 68
1152 23:22:30.148200 [Byte1]: 68
1153 23:22:30.152345
1154 23:22:30.152464 Set Vref, RX VrefLevel [Byte0]: 69
1155 23:22:30.155571 [Byte1]: 69
1156 23:22:30.159770
1157 23:22:30.159878 Set Vref, RX VrefLevel [Byte0]: 70
1158 23:22:30.163213 [Byte1]: 70
1159 23:22:30.167460
1160 23:22:30.167565 Set Vref, RX VrefLevel [Byte0]: 71
1161 23:22:30.170994 [Byte1]: 71
1162 23:22:30.175135
1163 23:22:30.175211 Set Vref, RX VrefLevel [Byte0]: 72
1164 23:22:30.178791 [Byte1]: 72
1165 23:22:30.182737
1166 23:22:30.182812 Set Vref, RX VrefLevel [Byte0]: 73
1167 23:22:30.186252 [Byte1]: 73
1168 23:22:30.190551
1169 23:22:30.190634 Set Vref, RX VrefLevel [Byte0]: 74
1170 23:22:30.194031 [Byte1]: 74
1171 23:22:30.197789
1172 23:22:30.197902 Final RX Vref Byte 0 = 56 to rank0
1173 23:22:30.201167 Final RX Vref Byte 1 = 59 to rank0
1174 23:22:30.204712 Final RX Vref Byte 0 = 56 to rank1
1175 23:22:30.207970 Final RX Vref Byte 1 = 59 to rank1==
1176 23:22:30.211304 Dram Type= 6, Freq= 0, CH_0, rank 0
1177 23:22:30.218221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 23:22:30.218329 ==
1179 23:22:30.218424 DQS Delay:
1180 23:22:30.218488 DQS0 = 0, DQS1 = 0
1181 23:22:30.221277 DQM Delay:
1182 23:22:30.221375 DQM0 = 88, DQM1 = 76
1183 23:22:30.224776 DQ Delay:
1184 23:22:30.227707 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1185 23:22:30.231448 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1186 23:22:30.231526 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1187 23:22:30.237967 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1188 23:22:30.238065
1189 23:22:30.238157
1190 23:22:30.244155 [DQSOSCAuto] RK0, (LSB)MR18= 0x322c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1191 23:22:30.247632 CH0 RK0: MR19=606, MR18=322C
1192 23:22:30.254316 CH0_RK0: MR19=0x606, MR18=0x322C, DQSOSC=397, MR23=63, INC=93, DEC=62
1193 23:22:30.254421
1194 23:22:30.257930 ----->DramcWriteLeveling(PI) begin...
1195 23:22:30.258029 ==
1196 23:22:30.261034 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 23:22:30.264306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 23:22:30.264381 ==
1199 23:22:30.267598 Write leveling (Byte 0): 31 => 31
1200 23:22:30.271063 Write leveling (Byte 1): 26 => 26
1201 23:22:30.274381 DramcWriteLeveling(PI) end<-----
1202 23:22:30.274456
1203 23:22:30.274548 ==
1204 23:22:30.277255 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 23:22:30.280885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 23:22:30.280983 ==
1207 23:22:30.284110 [Gating] SW mode calibration
1208 23:22:30.290860 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1209 23:22:30.297658 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1210 23:22:30.300496 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1211 23:22:30.304071 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1212 23:22:30.347992 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1213 23:22:30.348417 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 23:22:30.348526 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 23:22:30.348657 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 23:22:30.348788 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 23:22:30.348912 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 23:22:30.349020 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 23:22:30.349135 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:22:30.349416 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:22:30.349509 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:22:30.382289 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:22:30.382815 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:22:30.383108 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:22:30.383212 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:22:30.383304 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1227 23:22:30.383627 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1228 23:22:30.384107 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1229 23:22:30.386360 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:22:30.390190 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:22:30.393341 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:22:30.396483 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:22:30.402957 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:22:30.406315 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:22:30.409600 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1236 23:22:30.416288 0 9 8 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
1237 23:22:30.419455 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 23:22:30.423077 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 23:22:30.429602 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 23:22:30.432858 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 23:22:30.436171 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 23:22:30.443076 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 23:22:30.446135 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
1244 23:22:30.449239 0 10 8 | B1->B0 | 3030 2626 | 0 0 | (1 1) (0 0)
1245 23:22:30.456217 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1246 23:22:30.459176 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:22:30.462510 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 23:22:30.469039 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 23:22:30.472811 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 23:22:30.476284 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 23:22:30.482391 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1252 23:22:30.485584 0 11 8 | B1->B0 | 3232 4343 | 0 1 | (0 0) (0 0)
1253 23:22:30.489195 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 23:22:30.496451 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 23:22:30.499907 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 23:22:30.504461 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 23:22:30.507414 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 23:22:30.510559 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 23:22:30.518373 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1260 23:22:30.521378 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1261 23:22:30.524725 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 23:22:30.531645 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 23:22:30.534885 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 23:22:30.537929 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 23:22:30.544637 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 23:22:30.548111 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 23:22:30.551070 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 23:22:30.554549 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 23:22:30.561496 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 23:22:30.564699 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:22:30.568175 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:22:30.574551 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:22:30.577532 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:22:30.581183 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:22:30.588247 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1276 23:22:30.590827 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1277 23:22:30.594164 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 23:22:30.597454 Total UI for P1: 0, mck2ui 16
1279 23:22:30.600622 best dqsien dly found for B0: ( 0, 14, 6)
1280 23:22:30.604270 Total UI for P1: 0, mck2ui 16
1281 23:22:30.607579 best dqsien dly found for B1: ( 0, 14, 10)
1282 23:22:30.611025 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1283 23:22:30.614382 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1284 23:22:30.614496
1285 23:22:30.620701 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1286 23:22:30.624383 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1287 23:22:30.627952 [Gating] SW calibration Done
1288 23:22:30.628052 ==
1289 23:22:30.630633 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 23:22:30.634098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 23:22:30.634239 ==
1292 23:22:30.634332 RX Vref Scan: 0
1293 23:22:30.634423
1294 23:22:30.637304 RX Vref 0 -> 0, step: 1
1295 23:22:30.637438
1296 23:22:30.640813 RX Delay -130 -> 252, step: 16
1297 23:22:30.644033 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1298 23:22:30.647770 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1299 23:22:30.653907 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1300 23:22:30.657133 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1301 23:22:30.661190 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1302 23:22:30.664195 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1303 23:22:30.667376 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1304 23:22:30.673956 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1305 23:22:30.677703 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1306 23:22:30.680985 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1307 23:22:30.684164 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1308 23:22:30.687609 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1309 23:22:30.693954 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1310 23:22:30.697372 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1311 23:22:30.700724 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1312 23:22:30.704081 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1313 23:22:30.704180 ==
1314 23:22:30.707073 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 23:22:30.713716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 23:22:30.713831 ==
1317 23:22:30.713924 DQS Delay:
1318 23:22:30.717079 DQS0 = 0, DQS1 = 0
1319 23:22:30.717177 DQM Delay:
1320 23:22:30.717255 DQM0 = 85, DQM1 = 76
1321 23:22:30.720313 DQ Delay:
1322 23:22:30.723745 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1323 23:22:30.727402 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1324 23:22:30.730502 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1325 23:22:30.733829 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1326 23:22:30.733940
1327 23:22:30.734001
1328 23:22:30.734059 ==
1329 23:22:30.736821 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 23:22:30.740110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 23:22:30.740215 ==
1332 23:22:30.740302
1333 23:22:30.740362
1334 23:22:30.743384 TX Vref Scan disable
1335 23:22:30.746711 == TX Byte 0 ==
1336 23:22:30.749891 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1337 23:22:30.753274 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1338 23:22:30.756476 == TX Byte 1 ==
1339 23:22:30.760335 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1340 23:22:30.762937 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1341 23:22:30.763049 ==
1342 23:22:30.766433 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 23:22:30.770142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 23:22:30.772951 ==
1345 23:22:30.785212 TX Vref=22, minBit 0, minWin=27, winSum=440
1346 23:22:30.788542 TX Vref=24, minBit 1, minWin=27, winSum=443
1347 23:22:30.791170 TX Vref=26, minBit 1, minWin=27, winSum=445
1348 23:22:30.794885 TX Vref=28, minBit 1, minWin=27, winSum=448
1349 23:22:30.797746 TX Vref=30, minBit 2, minWin=27, winSum=449
1350 23:22:30.804634 TX Vref=32, minBit 1, minWin=27, winSum=451
1351 23:22:30.808249 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 32
1352 23:22:30.808357
1353 23:22:30.811151 Final TX Range 1 Vref 32
1354 23:22:30.811233
1355 23:22:30.811296 ==
1356 23:22:30.814645 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 23:22:30.818134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 23:22:30.818216 ==
1359 23:22:30.821055
1360 23:22:30.821136
1361 23:22:30.821199 TX Vref Scan disable
1362 23:22:30.824798 == TX Byte 0 ==
1363 23:22:30.828200 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1364 23:22:30.834614 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1365 23:22:30.834698 == TX Byte 1 ==
1366 23:22:30.838033 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1367 23:22:30.844796 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1368 23:22:30.844881
1369 23:22:30.844946 [DATLAT]
1370 23:22:30.845005 Freq=800, CH0 RK1
1371 23:22:30.845062
1372 23:22:30.848295 DATLAT Default: 0xa
1373 23:22:30.848383 0, 0xFFFF, sum = 0
1374 23:22:30.851256 1, 0xFFFF, sum = 0
1375 23:22:30.851357 2, 0xFFFF, sum = 0
1376 23:22:30.854464 3, 0xFFFF, sum = 0
1377 23:22:30.858116 4, 0xFFFF, sum = 0
1378 23:22:30.858198 5, 0xFFFF, sum = 0
1379 23:22:30.861293 6, 0xFFFF, sum = 0
1380 23:22:30.861411 7, 0xFFFF, sum = 0
1381 23:22:30.864662 8, 0xFFFF, sum = 0
1382 23:22:30.864769 9, 0x0, sum = 1
1383 23:22:30.864863 10, 0x0, sum = 2
1384 23:22:30.868170 11, 0x0, sum = 3
1385 23:22:30.868278 12, 0x0, sum = 4
1386 23:22:30.871521 best_step = 10
1387 23:22:30.871598
1388 23:22:30.871688 ==
1389 23:22:30.874887 Dram Type= 6, Freq= 0, CH_0, rank 1
1390 23:22:30.878145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 23:22:30.878241 ==
1392 23:22:30.881090 RX Vref Scan: 0
1393 23:22:30.881170
1394 23:22:30.881233 RX Vref 0 -> 0, step: 1
1395 23:22:30.881291
1396 23:22:30.884424 RX Delay -95 -> 252, step: 8
1397 23:22:30.891195 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1398 23:22:30.894743 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1399 23:22:30.897843 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1400 23:22:30.901212 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1401 23:22:30.904646 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1402 23:22:30.911010 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1403 23:22:30.914376 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1404 23:22:30.917861 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1405 23:22:30.921001 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1406 23:22:30.924386 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1407 23:22:30.930895 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1408 23:22:30.934597 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1409 23:22:30.938190 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1410 23:22:30.941274 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1411 23:22:30.947588 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1412 23:22:30.951162 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1413 23:22:30.951242 ==
1414 23:22:30.954066 Dram Type= 6, Freq= 0, CH_0, rank 1
1415 23:22:30.957352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 23:22:30.957433 ==
1417 23:22:30.960749 DQS Delay:
1418 23:22:30.960830 DQS0 = 0, DQS1 = 0
1419 23:22:30.960893 DQM Delay:
1420 23:22:30.963897 DQM0 = 86, DQM1 = 76
1421 23:22:30.964009 DQ Delay:
1422 23:22:30.967714 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1423 23:22:30.970719 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1424 23:22:30.974103 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1425 23:22:30.977479 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1426 23:22:30.977560
1427 23:22:30.977623
1428 23:22:30.987306 [DQSOSCAuto] RK1, (LSB)MR18= 0x231f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
1429 23:22:30.987421 CH0 RK1: MR19=606, MR18=231F
1430 23:22:30.993772 CH0_RK1: MR19=0x606, MR18=0x231F, DQSOSC=401, MR23=63, INC=91, DEC=61
1431 23:22:30.997226 [RxdqsGatingPostProcess] freq 800
1432 23:22:31.003777 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1433 23:22:31.007155 Pre-setting of DQS Precalculation
1434 23:22:31.010753 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1435 23:22:31.010842 ==
1436 23:22:31.013484 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 23:22:31.020248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 23:22:31.020331 ==
1439 23:22:31.023490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1440 23:22:31.030118 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1441 23:22:31.039574 [CA 0] Center 37 (6~68) winsize 63
1442 23:22:31.042954 [CA 1] Center 37 (6~68) winsize 63
1443 23:22:31.046067 [CA 2] Center 35 (5~65) winsize 61
1444 23:22:31.049933 [CA 3] Center 34 (4~65) winsize 62
1445 23:22:31.052817 [CA 4] Center 34 (4~65) winsize 62
1446 23:22:31.056488 [CA 5] Center 34 (3~65) winsize 63
1447 23:22:31.056564
1448 23:22:31.059541 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1449 23:22:31.059623
1450 23:22:31.062990 [CATrainingPosCal] consider 1 rank data
1451 23:22:31.066295 u2DelayCellTimex100 = 270/100 ps
1452 23:22:31.069773 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1453 23:22:31.073104 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1454 23:22:31.079768 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1455 23:22:31.082858 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 23:22:31.086419 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1457 23:22:31.089968 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1458 23:22:31.090049
1459 23:22:31.092750 CA PerBit enable=1, Macro0, CA PI delay=34
1460 23:22:31.092856
1461 23:22:31.096748 [CBTSetCACLKResult] CA Dly = 34
1462 23:22:31.096834 CS Dly: 4 (0~35)
1463 23:22:31.099233 ==
1464 23:22:31.103242 Dram Type= 6, Freq= 0, CH_1, rank 1
1465 23:22:31.106012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 23:22:31.106093 ==
1467 23:22:31.109877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1468 23:22:31.115922 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1469 23:22:31.125669 [CA 0] Center 36 (6~67) winsize 62
1470 23:22:31.128874 [CA 1] Center 36 (6~67) winsize 62
1471 23:22:31.132902 [CA 2] Center 34 (4~65) winsize 62
1472 23:22:31.135761 [CA 3] Center 33 (3~64) winsize 62
1473 23:22:31.139149 [CA 4] Center 34 (3~65) winsize 63
1474 23:22:31.142269 [CA 5] Center 34 (3~65) winsize 63
1475 23:22:31.142350
1476 23:22:31.145299 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1477 23:22:31.145415
1478 23:22:31.148938 [CATrainingPosCal] consider 2 rank data
1479 23:22:31.152411 u2DelayCellTimex100 = 270/100 ps
1480 23:22:31.155957 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 23:22:31.159414 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1482 23:22:31.163556 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1483 23:22:31.167167 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1484 23:22:31.170696 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 23:22:31.174560 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1486 23:22:31.174644
1487 23:22:31.178041 CA PerBit enable=1, Macro0, CA PI delay=34
1488 23:22:31.178163
1489 23:22:31.182051 [CBTSetCACLKResult] CA Dly = 34
1490 23:22:31.185456 CS Dly: 5 (0~37)
1491 23:22:31.185575
1492 23:22:31.189398 ----->DramcWriteLeveling(PI) begin...
1493 23:22:31.189508 ==
1494 23:22:31.189615 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 23:22:31.195533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1496 23:22:31.195617 ==
1497 23:22:31.199075 Write leveling (Byte 0): 29 => 29
1498 23:22:31.202076 Write leveling (Byte 1): 30 => 30
1499 23:22:31.205799 DramcWriteLeveling(PI) end<-----
1500 23:22:31.205910
1501 23:22:31.206010 ==
1502 23:22:31.209196 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 23:22:31.212303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 23:22:31.212405 ==
1505 23:22:31.215623 [Gating] SW mode calibration
1506 23:22:31.222242 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1507 23:22:31.225497 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1508 23:22:31.232227 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1509 23:22:31.235249 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1510 23:22:31.238811 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 23:22:31.245694 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 23:22:31.248574 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 23:22:31.251795 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 23:22:31.259083 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 23:22:31.261829 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 23:22:31.265043 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 23:22:31.272015 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:22:31.275202 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:22:31.278208 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:22:31.285148 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:22:31.288046 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:22:31.291512 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:22:31.298167 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:22:31.301610 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:22:31.304846 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1526 23:22:31.311496 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1527 23:22:31.314777 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:22:31.318245 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:22:31.324912 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:22:31.328289 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:22:31.331443 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:22:31.338263 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:22:31.341741 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1534 23:22:31.345101 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1535 23:22:31.351017 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 23:22:31.354452 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 23:22:31.358080 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 23:22:31.364408 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 23:22:31.367750 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 23:22:31.370950 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 23:22:31.377744 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
1542 23:22:31.381535 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1543 23:22:31.384582 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:22:31.390823 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 23:22:31.394607 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 23:22:31.397768 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 23:22:31.404568 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 23:22:31.407595 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 23:22:31.410803 0 11 4 | B1->B0 | 2a2a 2e2e | 0 1 | (1 1) (1 1)
1550 23:22:31.417487 0 11 8 | B1->B0 | 3f3f 4545 | 1 0 | (0 0) (0 0)
1551 23:22:31.420761 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 23:22:31.423943 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 23:22:31.430545 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 23:22:31.433904 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 23:22:31.437067 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 23:22:31.444339 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 23:22:31.447050 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1558 23:22:31.450344 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 23:22:31.457021 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 23:22:31.460446 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 23:22:31.463780 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 23:22:31.470489 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 23:22:31.473576 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 23:22:31.477114 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 23:22:31.483713 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 23:22:31.487134 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 23:22:31.490177 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:22:31.493439 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 23:22:31.500131 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:22:31.503351 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:22:31.507058 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:22:31.513963 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:22:31.517124 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1574 23:22:31.520394 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 23:22:31.523698 Total UI for P1: 0, mck2ui 16
1576 23:22:31.526775 best dqsien dly found for B0: ( 0, 14, 4)
1577 23:22:31.529861 Total UI for P1: 0, mck2ui 16
1578 23:22:31.533307 best dqsien dly found for B1: ( 0, 14, 4)
1579 23:22:31.536606 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1580 23:22:31.543111 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1581 23:22:31.543227
1582 23:22:31.546248 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1583 23:22:31.549802 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1584 23:22:31.553407 [Gating] SW calibration Done
1585 23:22:31.553568 ==
1586 23:22:31.556794 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 23:22:31.559677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 23:22:31.559803 ==
1589 23:22:31.559914 RX Vref Scan: 0
1590 23:22:31.562909
1591 23:22:31.563027 RX Vref 0 -> 0, step: 1
1592 23:22:31.563137
1593 23:22:31.566276 RX Delay -130 -> 252, step: 16
1594 23:22:31.569425 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1595 23:22:31.576055 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1596 23:22:31.579527 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1597 23:22:31.582905 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1598 23:22:31.586616 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1599 23:22:31.589591 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1600 23:22:31.592570 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1601 23:22:31.599526 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1602 23:22:31.602909 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1603 23:22:31.605703 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1604 23:22:31.608922 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1605 23:22:31.615831 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1606 23:22:31.619149 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1607 23:22:31.622456 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1608 23:22:31.625477 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1609 23:22:31.629462 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1610 23:22:31.632609 ==
1611 23:22:31.632709 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 23:22:31.639430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 23:22:31.639541 ==
1614 23:22:31.639635 DQS Delay:
1615 23:22:31.642224 DQS0 = 0, DQS1 = 0
1616 23:22:31.642321 DQM Delay:
1617 23:22:31.645798 DQM0 = 84, DQM1 = 78
1618 23:22:31.645880 DQ Delay:
1619 23:22:31.649527 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1620 23:22:31.652222 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1621 23:22:31.655899 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1622 23:22:31.659354 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1623 23:22:31.659434
1624 23:22:31.659496
1625 23:22:31.659554 ==
1626 23:22:31.662345 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 23:22:31.665826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 23:22:31.665936 ==
1629 23:22:31.666030
1630 23:22:31.666120
1631 23:22:31.668732 TX Vref Scan disable
1632 23:22:31.672696 == TX Byte 0 ==
1633 23:22:31.675861 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1634 23:22:31.678791 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1635 23:22:31.682237 == TX Byte 1 ==
1636 23:22:31.685580 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1637 23:22:31.688614 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1638 23:22:31.688741 ==
1639 23:22:31.692003 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 23:22:31.695466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 23:22:31.698688 ==
1642 23:22:31.710101 TX Vref=22, minBit 6, minWin=26, winSum=440
1643 23:22:31.713054 TX Vref=24, minBit 5, minWin=26, winSum=441
1644 23:22:31.716573 TX Vref=26, minBit 1, minWin=27, winSum=451
1645 23:22:31.719722 TX Vref=28, minBit 4, minWin=27, winSum=452
1646 23:22:31.723151 TX Vref=30, minBit 1, minWin=27, winSum=452
1647 23:22:31.726465 TX Vref=32, minBit 0, minWin=27, winSum=451
1648 23:22:31.733726 [TxChooseVref] Worse bit 4, Min win 27, Win sum 452, Final Vref 28
1649 23:22:31.733849
1650 23:22:31.737247 Final TX Range 1 Vref 28
1651 23:22:31.737370
1652 23:22:31.737482 ==
1653 23:22:31.740771 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 23:22:31.744015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 23:22:31.744097 ==
1656 23:22:31.744161
1657 23:22:31.744220
1658 23:22:31.747216 TX Vref Scan disable
1659 23:22:31.750356 == TX Byte 0 ==
1660 23:22:31.754200 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1661 23:22:31.757309 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1662 23:22:31.760606 == TX Byte 1 ==
1663 23:22:31.763872 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1664 23:22:31.767468 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1665 23:22:31.767556
1666 23:22:31.770527 [DATLAT]
1667 23:22:31.770614 Freq=800, CH1 RK0
1668 23:22:31.770702
1669 23:22:31.773792 DATLAT Default: 0xa
1670 23:22:31.773877 0, 0xFFFF, sum = 0
1671 23:22:31.777276 1, 0xFFFF, sum = 0
1672 23:22:31.777363 2, 0xFFFF, sum = 0
1673 23:22:31.780355 3, 0xFFFF, sum = 0
1674 23:22:31.780441 4, 0xFFFF, sum = 0
1675 23:22:31.783762 5, 0xFFFF, sum = 0
1676 23:22:31.783850 6, 0xFFFF, sum = 0
1677 23:22:31.787122 7, 0xFFFF, sum = 0
1678 23:22:31.787209 8, 0xFFFF, sum = 0
1679 23:22:31.790554 9, 0x0, sum = 1
1680 23:22:31.790641 10, 0x0, sum = 2
1681 23:22:31.793720 11, 0x0, sum = 3
1682 23:22:31.793806 12, 0x0, sum = 4
1683 23:22:31.797050 best_step = 10
1684 23:22:31.797135
1685 23:22:31.797237 ==
1686 23:22:31.800280 Dram Type= 6, Freq= 0, CH_1, rank 0
1687 23:22:31.803519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1688 23:22:31.803651 ==
1689 23:22:31.806755 RX Vref Scan: 1
1690 23:22:31.806877
1691 23:22:31.806989 Set Vref Range= 32 -> 127
1692 23:22:31.807104
1693 23:22:31.810202 RX Vref 32 -> 127, step: 1
1694 23:22:31.810306
1695 23:22:31.813603 RX Delay -95 -> 252, step: 8
1696 23:22:31.813685
1697 23:22:31.816936 Set Vref, RX VrefLevel [Byte0]: 32
1698 23:22:31.820221 [Byte1]: 32
1699 23:22:31.820305
1700 23:22:31.823531 Set Vref, RX VrefLevel [Byte0]: 33
1701 23:22:31.826442 [Byte1]: 33
1702 23:22:31.830136
1703 23:22:31.830262 Set Vref, RX VrefLevel [Byte0]: 34
1704 23:22:31.833385 [Byte1]: 34
1705 23:22:31.837736
1706 23:22:31.837859 Set Vref, RX VrefLevel [Byte0]: 35
1707 23:22:31.841469 [Byte1]: 35
1708 23:22:31.845202
1709 23:22:31.845323 Set Vref, RX VrefLevel [Byte0]: 36
1710 23:22:31.848718 [Byte1]: 36
1711 23:22:31.852765
1712 23:22:31.852888 Set Vref, RX VrefLevel [Byte0]: 37
1713 23:22:31.856375 [Byte1]: 37
1714 23:22:31.860414
1715 23:22:31.860532 Set Vref, RX VrefLevel [Byte0]: 38
1716 23:22:31.864153 [Byte1]: 38
1717 23:22:31.868625
1718 23:22:31.868748 Set Vref, RX VrefLevel [Byte0]: 39
1719 23:22:31.871279 [Byte1]: 39
1720 23:22:31.875898
1721 23:22:31.876018 Set Vref, RX VrefLevel [Byte0]: 40
1722 23:22:31.879093 [Byte1]: 40
1723 23:22:31.883704
1724 23:22:31.883788 Set Vref, RX VrefLevel [Byte0]: 41
1725 23:22:31.886888 [Byte1]: 41
1726 23:22:31.890803
1727 23:22:31.890886 Set Vref, RX VrefLevel [Byte0]: 42
1728 23:22:31.894055 [Byte1]: 42
1729 23:22:31.898781
1730 23:22:31.898863 Set Vref, RX VrefLevel [Byte0]: 43
1731 23:22:31.902039 [Byte1]: 43
1732 23:22:31.905994
1733 23:22:31.906103 Set Vref, RX VrefLevel [Byte0]: 44
1734 23:22:31.909213 [Byte1]: 44
1735 23:22:31.913988
1736 23:22:31.914089 Set Vref, RX VrefLevel [Byte0]: 45
1737 23:22:31.917160 [Byte1]: 45
1738 23:22:31.921339
1739 23:22:31.921461 Set Vref, RX VrefLevel [Byte0]: 46
1740 23:22:31.924930 [Byte1]: 46
1741 23:22:31.928740
1742 23:22:31.928844 Set Vref, RX VrefLevel [Byte0]: 47
1743 23:22:31.932183 [Byte1]: 47
1744 23:22:31.936976
1745 23:22:31.937091 Set Vref, RX VrefLevel [Byte0]: 48
1746 23:22:31.940189 [Byte1]: 48
1747 23:22:31.944155
1748 23:22:31.944275 Set Vref, RX VrefLevel [Byte0]: 49
1749 23:22:31.947256 [Byte1]: 49
1750 23:22:31.952174
1751 23:22:31.952289 Set Vref, RX VrefLevel [Byte0]: 50
1752 23:22:31.954748 [Byte1]: 50
1753 23:22:31.959281
1754 23:22:31.959403 Set Vref, RX VrefLevel [Byte0]: 51
1755 23:22:31.962830 [Byte1]: 51
1756 23:22:31.966959
1757 23:22:31.967068 Set Vref, RX VrefLevel [Byte0]: 52
1758 23:22:31.970024 [Byte1]: 52
1759 23:22:31.974385
1760 23:22:31.974475 Set Vref, RX VrefLevel [Byte0]: 53
1761 23:22:31.978179 [Byte1]: 53
1762 23:22:31.982047
1763 23:22:31.982155 Set Vref, RX VrefLevel [Byte0]: 54
1764 23:22:31.985828 [Byte1]: 54
1765 23:22:31.990039
1766 23:22:31.990145 Set Vref, RX VrefLevel [Byte0]: 55
1767 23:22:31.993365 [Byte1]: 55
1768 23:22:31.997054
1769 23:22:31.997167 Set Vref, RX VrefLevel [Byte0]: 56
1770 23:22:32.000599 [Byte1]: 56
1771 23:22:32.005004
1772 23:22:32.005109 Set Vref, RX VrefLevel [Byte0]: 57
1773 23:22:32.008262 [Byte1]: 57
1774 23:22:32.012614
1775 23:22:32.012716 Set Vref, RX VrefLevel [Byte0]: 58
1776 23:22:32.015750 [Byte1]: 58
1777 23:22:32.020181
1778 23:22:32.020286 Set Vref, RX VrefLevel [Byte0]: 59
1779 23:22:32.023744 [Byte1]: 59
1780 23:22:32.028102
1781 23:22:32.028204 Set Vref, RX VrefLevel [Byte0]: 60
1782 23:22:32.030808 [Byte1]: 60
1783 23:22:32.035067
1784 23:22:32.035171 Set Vref, RX VrefLevel [Byte0]: 61
1785 23:22:32.038520 [Byte1]: 61
1786 23:22:32.042972
1787 23:22:32.043076 Set Vref, RX VrefLevel [Byte0]: 62
1788 23:22:32.046664 [Byte1]: 62
1789 23:22:32.050327
1790 23:22:32.050432 Set Vref, RX VrefLevel [Byte0]: 63
1791 23:22:32.054329 [Byte1]: 63
1792 23:22:32.058166
1793 23:22:32.058270 Set Vref, RX VrefLevel [Byte0]: 64
1794 23:22:32.061379 [Byte1]: 64
1795 23:22:32.065949
1796 23:22:32.066055 Set Vref, RX VrefLevel [Byte0]: 65
1797 23:22:32.069212 [Byte1]: 65
1798 23:22:32.073467
1799 23:22:32.073546 Set Vref, RX VrefLevel [Byte0]: 66
1800 23:22:32.076749 [Byte1]: 66
1801 23:22:32.081280
1802 23:22:32.081362 Set Vref, RX VrefLevel [Byte0]: 67
1803 23:22:32.084099 [Byte1]: 67
1804 23:22:32.088348
1805 23:22:32.088429 Set Vref, RX VrefLevel [Byte0]: 68
1806 23:22:32.091626 [Byte1]: 68
1807 23:22:32.095973
1808 23:22:32.096056 Set Vref, RX VrefLevel [Byte0]: 69
1809 23:22:32.099309 [Byte1]: 69
1810 23:22:32.103909
1811 23:22:32.103991 Set Vref, RX VrefLevel [Byte0]: 70
1812 23:22:32.107171 [Byte1]: 70
1813 23:22:32.111142
1814 23:22:32.111223 Set Vref, RX VrefLevel [Byte0]: 71
1815 23:22:32.114364 [Byte1]: 71
1816 23:22:32.118862
1817 23:22:32.118942 Set Vref, RX VrefLevel [Byte0]: 72
1818 23:22:32.122293 [Byte1]: 72
1819 23:22:32.126620
1820 23:22:32.126749 Set Vref, RX VrefLevel [Byte0]: 73
1821 23:22:32.130130 [Byte1]: 73
1822 23:22:32.134307
1823 23:22:32.134419 Set Vref, RX VrefLevel [Byte0]: 74
1824 23:22:32.137395 [Byte1]: 74
1825 23:22:32.141651
1826 23:22:32.141730 Set Vref, RX VrefLevel [Byte0]: 75
1827 23:22:32.144817 [Byte1]: 75
1828 23:22:32.149550
1829 23:22:32.149629 Final RX Vref Byte 0 = 57 to rank0
1830 23:22:32.152573 Final RX Vref Byte 1 = 58 to rank0
1831 23:22:32.155754 Final RX Vref Byte 0 = 57 to rank1
1832 23:22:32.159358 Final RX Vref Byte 1 = 58 to rank1==
1833 23:22:32.162572 Dram Type= 6, Freq= 0, CH_1, rank 0
1834 23:22:32.169188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1835 23:22:32.169270 ==
1836 23:22:32.169335 DQS Delay:
1837 23:22:32.172318 DQS0 = 0, DQS1 = 0
1838 23:22:32.172409 DQM Delay:
1839 23:22:32.172472 DQM0 = 85, DQM1 = 80
1840 23:22:32.175859 DQ Delay:
1841 23:22:32.179447 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1842 23:22:32.182113 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1843 23:22:32.185852 DQ8 =68, DQ9 =72, DQ10 =76, DQ11 =72
1844 23:22:32.189010 DQ12 =88, DQ13 =92, DQ14 =84, DQ15 =88
1845 23:22:32.189186
1846 23:22:32.189352
1847 23:22:32.195752 [DQSOSCAuto] RK0, (LSB)MR18= 0x1427, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 404 ps
1848 23:22:32.199181 CH1 RK0: MR19=606, MR18=1427
1849 23:22:32.205615 CH1_RK0: MR19=0x606, MR18=0x1427, DQSOSC=400, MR23=63, INC=92, DEC=61
1850 23:22:32.205705
1851 23:22:32.208776 ----->DramcWriteLeveling(PI) begin...
1852 23:22:32.208858 ==
1853 23:22:32.211796 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 23:22:32.214988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 23:22:32.215090 ==
1856 23:22:32.219170 Write leveling (Byte 0): 26 => 26
1857 23:22:32.221736 Write leveling (Byte 1): 29 => 29
1858 23:22:32.225048 DramcWriteLeveling(PI) end<-----
1859 23:22:32.225149
1860 23:22:32.225239 ==
1861 23:22:32.228501 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 23:22:32.231967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1863 23:22:32.232040 ==
1864 23:22:32.235053 [Gating] SW mode calibration
1865 23:22:32.242032 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1866 23:22:32.248255 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1867 23:22:32.251850 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1868 23:22:32.258599 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1869 23:22:32.261854 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1870 23:22:32.264969 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:22:32.271744 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:22:32.275293 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:22:32.278377 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:22:32.285078 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:22:32.288355 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:22:32.291761 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:22:32.295100 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:22:32.301518 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:22:32.304797 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:22:32.308466 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:22:32.314880 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:22:32.318450 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:22:32.321650 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1884 23:22:32.328201 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1885 23:22:32.331711 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1886 23:22:32.334883 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:22:32.341662 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 23:22:32.344447 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 23:22:32.348372 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:22:32.354614 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:22:32.357835 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:22:32.361252 0 9 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1893 23:22:32.367960 0 9 8 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
1894 23:22:32.371140 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 23:22:32.375042 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 23:22:32.381353 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 23:22:32.384596 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 23:22:32.387818 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 23:22:32.394682 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1900 23:22:32.398009 0 10 4 | B1->B0 | 3232 2323 | 1 0 | (1 1) (1 0)
1901 23:22:32.400896 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 23:22:32.407916 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 23:22:32.410901 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 23:22:32.414648 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 23:22:32.421330 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 23:22:32.424282 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:22:32.428019 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 23:22:32.434715 0 11 4 | B1->B0 | 2525 3838 | 0 0 | (1 1) (0 0)
1909 23:22:32.437494 0 11 8 | B1->B0 | 3a39 4646 | 1 0 | (0 0) (0 0)
1910 23:22:32.440721 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 23:22:32.447439 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 23:22:32.451080 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 23:22:32.454132 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 23:22:32.460980 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 23:22:32.463875 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1916 23:22:32.467168 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1917 23:22:32.473796 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:22:32.477189 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:22:32.480489 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:22:32.484040 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:22:32.490416 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:22:32.493737 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:22:32.497519 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:22:32.503691 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:22:32.507032 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 23:22:32.510048 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 23:22:32.516771 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 23:22:32.520042 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 23:22:32.523530 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:22:32.530242 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:22:32.533564 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1932 23:22:32.537087 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1933 23:22:32.543802 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 23:22:32.546587 Total UI for P1: 0, mck2ui 16
1935 23:22:32.550111 best dqsien dly found for B0: ( 0, 14, 2)
1936 23:22:32.550193 Total UI for P1: 0, mck2ui 16
1937 23:22:32.556910 best dqsien dly found for B1: ( 0, 14, 4)
1938 23:22:32.560272 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1939 23:22:32.563653 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1940 23:22:32.563736
1941 23:22:32.567051 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1942 23:22:32.570378 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1943 23:22:32.573386 [Gating] SW calibration Done
1944 23:22:32.573468 ==
1945 23:22:32.576604 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 23:22:32.579869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 23:22:32.579946 ==
1948 23:22:32.583502 RX Vref Scan: 0
1949 23:22:32.583574
1950 23:22:32.583635 RX Vref 0 -> 0, step: 1
1951 23:22:32.583693
1952 23:22:32.586671 RX Delay -130 -> 252, step: 16
1953 23:22:32.590296 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1954 23:22:32.596589 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1955 23:22:32.599880 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1956 23:22:32.603489 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1957 23:22:32.606649 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1958 23:22:32.610186 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1959 23:22:32.616946 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1960 23:22:32.619976 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1961 23:22:32.623511 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1962 23:22:32.627173 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1963 23:22:32.630106 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1964 23:22:32.636700 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1965 23:22:32.640034 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1966 23:22:32.643304 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1967 23:22:32.646717 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1968 23:22:32.653271 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1969 23:22:32.653373 ==
1970 23:22:32.656292 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 23:22:32.659766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 23:22:32.659846 ==
1973 23:22:32.659908 DQS Delay:
1974 23:22:32.663227 DQS0 = 0, DQS1 = 0
1975 23:22:32.663321 DQM Delay:
1976 23:22:32.666676 DQM0 = 82, DQM1 = 80
1977 23:22:32.666748 DQ Delay:
1978 23:22:32.669496 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1979 23:22:32.673021 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1980 23:22:32.676468 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1981 23:22:32.679437 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1982 23:22:32.679508
1983 23:22:32.679567
1984 23:22:32.679623 ==
1985 23:22:32.683105 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 23:22:32.686588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 23:22:32.686683 ==
1988 23:22:32.686751
1989 23:22:32.686807
1990 23:22:32.689607 TX Vref Scan disable
1991 23:22:32.692879 == TX Byte 0 ==
1992 23:22:32.696671 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1993 23:22:32.699344 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1994 23:22:32.703271 == TX Byte 1 ==
1995 23:22:32.706170 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1996 23:22:32.709688 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1997 23:22:32.709782 ==
1998 23:22:32.712796 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 23:22:32.719459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 23:22:32.719538 ==
2001 23:22:32.731226 TX Vref=22, minBit 1, minWin=27, winSum=448
2002 23:22:32.734529 TX Vref=24, minBit 1, minWin=27, winSum=451
2003 23:22:32.737788 TX Vref=26, minBit 6, minWin=27, winSum=451
2004 23:22:32.741172 TX Vref=28, minBit 5, minWin=27, winSum=455
2005 23:22:32.744461 TX Vref=30, minBit 1, minWin=27, winSum=453
2006 23:22:32.747907 TX Vref=32, minBit 0, minWin=27, winSum=452
2007 23:22:32.755112 [TxChooseVref] Worse bit 5, Min win 27, Win sum 455, Final Vref 28
2008 23:22:32.755219
2009 23:22:32.758333 Final TX Range 1 Vref 28
2010 23:22:32.758429
2011 23:22:32.758494 ==
2012 23:22:32.761006 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 23:22:32.764816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 23:22:32.764919 ==
2015 23:22:32.767983
2016 23:22:32.768069
2017 23:22:32.768144 TX Vref Scan disable
2018 23:22:32.771143 == TX Byte 0 ==
2019 23:22:32.774474 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2020 23:22:32.777965 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2021 23:22:32.781157 == TX Byte 1 ==
2022 23:22:32.785129 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2023 23:22:32.788218 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2024 23:22:32.791455
2025 23:22:32.791528 [DATLAT]
2026 23:22:32.791589 Freq=800, CH1 RK1
2027 23:22:32.791647
2028 23:22:32.794670 DATLAT Default: 0xa
2029 23:22:32.794740 0, 0xFFFF, sum = 0
2030 23:22:32.798090 1, 0xFFFF, sum = 0
2031 23:22:32.798198 2, 0xFFFF, sum = 0
2032 23:22:32.801087 3, 0xFFFF, sum = 0
2033 23:22:32.801189 4, 0xFFFF, sum = 0
2034 23:22:32.804674 5, 0xFFFF, sum = 0
2035 23:22:32.807929 6, 0xFFFF, sum = 0
2036 23:22:32.808003 7, 0xFFFF, sum = 0
2037 23:22:32.811143 8, 0xFFFF, sum = 0
2038 23:22:32.811246 9, 0x0, sum = 1
2039 23:22:32.811341 10, 0x0, sum = 2
2040 23:22:32.814600 11, 0x0, sum = 3
2041 23:22:32.814671 12, 0x0, sum = 4
2042 23:22:32.817512 best_step = 10
2043 23:22:32.817609
2044 23:22:32.817710 ==
2045 23:22:32.821117 Dram Type= 6, Freq= 0, CH_1, rank 1
2046 23:22:32.824480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2047 23:22:32.824580 ==
2048 23:22:32.827579 RX Vref Scan: 0
2049 23:22:32.827652
2050 23:22:32.827712 RX Vref 0 -> 0, step: 1
2051 23:22:32.827770
2052 23:22:32.831015 RX Delay -95 -> 252, step: 8
2053 23:22:32.837721 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2054 23:22:32.841302 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2055 23:22:32.844141 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2056 23:22:32.847485 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2057 23:22:32.853951 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2058 23:22:32.857412 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2059 23:22:32.860859 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2060 23:22:32.864650 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2061 23:22:32.867746 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2062 23:22:32.873794 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2063 23:22:32.877411 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2064 23:22:32.881154 iDelay=209, Bit 11, Center 76 (-39 ~ 192) 232
2065 23:22:32.883838 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2066 23:22:32.887491 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2067 23:22:32.893879 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2068 23:22:32.897221 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2069 23:22:32.897304 ==
2070 23:22:32.900781 Dram Type= 6, Freq= 0, CH_1, rank 1
2071 23:22:32.904248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2072 23:22:32.904331 ==
2073 23:22:32.907343 DQS Delay:
2074 23:22:32.907436 DQS0 = 0, DQS1 = 0
2075 23:22:32.907501 DQM Delay:
2076 23:22:32.910594 DQM0 = 86, DQM1 = 81
2077 23:22:32.910676 DQ Delay:
2078 23:22:32.914079 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2079 23:22:32.917355 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2080 23:22:32.920655 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2081 23:22:32.924110 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
2082 23:22:32.924197
2083 23:22:32.924262
2084 23:22:32.934640 [DQSOSCAuto] RK1, (LSB)MR18= 0x1934, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2085 23:22:32.934718 CH1 RK1: MR19=606, MR18=1934
2086 23:22:32.940291 CH1_RK1: MR19=0x606, MR18=0x1934, DQSOSC=396, MR23=63, INC=94, DEC=62
2087 23:22:32.943692 [RxdqsGatingPostProcess] freq 800
2088 23:22:32.950336 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2089 23:22:32.953465 Pre-setting of DQS Precalculation
2090 23:22:32.957076 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2091 23:22:32.963961 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2092 23:22:32.973689 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2093 23:22:32.973776
2094 23:22:32.973846
2095 23:22:32.976742 [Calibration Summary] 1600 Mbps
2096 23:22:32.976869 CH 0, Rank 0
2097 23:22:32.980182 SW Impedance : PASS
2098 23:22:32.980301 DUTY Scan : NO K
2099 23:22:32.983580 ZQ Calibration : PASS
2100 23:22:32.986896 Jitter Meter : NO K
2101 23:22:32.987017 CBT Training : PASS
2102 23:22:32.990173 Write leveling : PASS
2103 23:22:32.993455 RX DQS gating : PASS
2104 23:22:32.993577 RX DQ/DQS(RDDQC) : PASS
2105 23:22:32.996639 TX DQ/DQS : PASS
2106 23:22:32.996762 RX DATLAT : PASS
2107 23:22:33.000053 RX DQ/DQS(Engine): PASS
2108 23:22:33.003601 TX OE : NO K
2109 23:22:33.003721 All Pass.
2110 23:22:33.003833
2111 23:22:33.003942 CH 0, Rank 1
2112 23:22:33.006862 SW Impedance : PASS
2113 23:22:33.010100 DUTY Scan : NO K
2114 23:22:33.010217 ZQ Calibration : PASS
2115 23:22:33.013114 Jitter Meter : NO K
2116 23:22:33.017068 CBT Training : PASS
2117 23:22:33.017187 Write leveling : PASS
2118 23:22:33.020105 RX DQS gating : PASS
2119 23:22:33.023073 RX DQ/DQS(RDDQC) : PASS
2120 23:22:33.023188 TX DQ/DQS : PASS
2121 23:22:33.026491 RX DATLAT : PASS
2122 23:22:33.030373 RX DQ/DQS(Engine): PASS
2123 23:22:33.030492 TX OE : NO K
2124 23:22:33.033011 All Pass.
2125 23:22:33.033128
2126 23:22:33.033239 CH 1, Rank 0
2127 23:22:33.036835 SW Impedance : PASS
2128 23:22:33.036956 DUTY Scan : NO K
2129 23:22:33.040084 ZQ Calibration : PASS
2130 23:22:33.043315 Jitter Meter : NO K
2131 23:22:33.043468 CBT Training : PASS
2132 23:22:33.046344 Write leveling : PASS
2133 23:22:33.049977 RX DQS gating : PASS
2134 23:22:33.050098 RX DQ/DQS(RDDQC) : PASS
2135 23:22:33.053120 TX DQ/DQS : PASS
2136 23:22:33.053236 RX DATLAT : PASS
2137 23:22:33.056476 RX DQ/DQS(Engine): PASS
2138 23:22:33.059931 TX OE : NO K
2139 23:22:33.060028 All Pass.
2140 23:22:33.060106
2141 23:22:33.060181 CH 1, Rank 1
2142 23:22:33.063051 SW Impedance : PASS
2143 23:22:33.066539 DUTY Scan : NO K
2144 23:22:33.066635 ZQ Calibration : PASS
2145 23:22:33.069575 Jitter Meter : NO K
2146 23:22:33.072871 CBT Training : PASS
2147 23:22:33.072952 Write leveling : PASS
2148 23:22:33.076238 RX DQS gating : PASS
2149 23:22:33.079612 RX DQ/DQS(RDDQC) : PASS
2150 23:22:33.079693 TX DQ/DQS : PASS
2151 23:22:33.082641 RX DATLAT : PASS
2152 23:22:33.085982 RX DQ/DQS(Engine): PASS
2153 23:22:33.086078 TX OE : NO K
2154 23:22:33.089181 All Pass.
2155 23:22:33.089263
2156 23:22:33.089327 DramC Write-DBI off
2157 23:22:33.092488 PER_BANK_REFRESH: Hybrid Mode
2158 23:22:33.092568 TX_TRACKING: ON
2159 23:22:33.099301 [GetDramInforAfterCalByMRR] Vendor 6.
2160 23:22:33.103002 [GetDramInforAfterCalByMRR] Revision 606.
2161 23:22:33.106099 [GetDramInforAfterCalByMRR] Revision 2 0.
2162 23:22:33.106179 MR0 0x3b3b
2163 23:22:33.106242 MR8 0x5151
2164 23:22:33.112569 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2165 23:22:33.112683
2166 23:22:33.112778 MR0 0x3b3b
2167 23:22:33.112868 MR8 0x5151
2168 23:22:33.115871 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 23:22:33.115987
2170 23:22:33.126085 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2171 23:22:33.129364 [FAST_K] Save calibration result to emmc
2172 23:22:33.132686 [FAST_K] Save calibration result to emmc
2173 23:22:33.135975 dram_init: config_dvfs: 1
2174 23:22:33.139186 dramc_set_vcore_voltage set vcore to 662500
2175 23:22:33.142677 Read voltage for 1200, 2
2176 23:22:33.142804 Vio18 = 0
2177 23:22:33.142912 Vcore = 662500
2178 23:22:33.146026 Vdram = 0
2179 23:22:33.146134 Vddq = 0
2180 23:22:33.146226 Vmddr = 0
2181 23:22:33.152517 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2182 23:22:33.155753 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2183 23:22:33.159043 MEM_TYPE=3, freq_sel=15
2184 23:22:33.162170 sv_algorithm_assistance_LP4_1600
2185 23:22:33.165657 ============ PULL DRAM RESETB DOWN ============
2186 23:22:33.168686 ========== PULL DRAM RESETB DOWN end =========
2187 23:22:33.175286 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2188 23:22:33.178501 ===================================
2189 23:22:33.181997 LPDDR4 DRAM CONFIGURATION
2190 23:22:33.185576 ===================================
2191 23:22:33.185657 EX_ROW_EN[0] = 0x0
2192 23:22:33.188943 EX_ROW_EN[1] = 0x0
2193 23:22:33.189024 LP4Y_EN = 0x0
2194 23:22:33.191768 WORK_FSP = 0x0
2195 23:22:33.191849 WL = 0x4
2196 23:22:33.195103 RL = 0x4
2197 23:22:33.195183 BL = 0x2
2198 23:22:33.198433 RPST = 0x0
2199 23:22:33.198513 RD_PRE = 0x0
2200 23:22:33.201885 WR_PRE = 0x1
2201 23:22:33.201960 WR_PST = 0x0
2202 23:22:33.205544 DBI_WR = 0x0
2203 23:22:33.208489 DBI_RD = 0x0
2204 23:22:33.208591 OTF = 0x1
2205 23:22:33.211952 ===================================
2206 23:22:33.215192 ===================================
2207 23:22:33.215292 ANA top config
2208 23:22:33.218583 ===================================
2209 23:22:33.221760 DLL_ASYNC_EN = 0
2210 23:22:33.225463 ALL_SLAVE_EN = 0
2211 23:22:33.228630 NEW_RANK_MODE = 1
2212 23:22:33.228735 DLL_IDLE_MODE = 1
2213 23:22:33.232089 LP45_APHY_COMB_EN = 1
2214 23:22:33.235306 TX_ODT_DIS = 1
2215 23:22:33.238475 NEW_8X_MODE = 1
2216 23:22:33.241892 ===================================
2217 23:22:33.245033 ===================================
2218 23:22:33.248279 data_rate = 2400
2219 23:22:33.251657 CKR = 1
2220 23:22:33.251740 DQ_P2S_RATIO = 8
2221 23:22:33.255109 ===================================
2222 23:22:33.258396 CA_P2S_RATIO = 8
2223 23:22:33.262197 DQ_CA_OPEN = 0
2224 23:22:33.264983 DQ_SEMI_OPEN = 0
2225 23:22:33.268406 CA_SEMI_OPEN = 0
2226 23:22:33.268490 CA_FULL_RATE = 0
2227 23:22:33.272121 DQ_CKDIV4_EN = 0
2228 23:22:33.275307 CA_CKDIV4_EN = 0
2229 23:22:33.278849 CA_PREDIV_EN = 0
2230 23:22:33.281791 PH8_DLY = 17
2231 23:22:33.284978 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2232 23:22:33.285096 DQ_AAMCK_DIV = 4
2233 23:22:33.288405 CA_AAMCK_DIV = 4
2234 23:22:33.291695 CA_ADMCK_DIV = 4
2235 23:22:33.295316 DQ_TRACK_CA_EN = 0
2236 23:22:33.298630 CA_PICK = 1200
2237 23:22:33.301525 CA_MCKIO = 1200
2238 23:22:33.305331 MCKIO_SEMI = 0
2239 23:22:33.308806 PLL_FREQ = 2366
2240 23:22:33.308888 DQ_UI_PI_RATIO = 32
2241 23:22:33.311499 CA_UI_PI_RATIO = 0
2242 23:22:33.314790 ===================================
2243 23:22:33.318298 ===================================
2244 23:22:33.321620 memory_type:LPDDR4
2245 23:22:33.325108 GP_NUM : 10
2246 23:22:33.325191 SRAM_EN : 1
2247 23:22:33.328040 MD32_EN : 0
2248 23:22:33.331299 ===================================
2249 23:22:33.334833 [ANA_INIT] >>>>>>>>>>>>>>
2250 23:22:33.334915 <<<<<< [CONFIGURE PHASE]: ANA_TX
2251 23:22:33.337750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2252 23:22:33.341315 ===================================
2253 23:22:33.345154 data_rate = 2400,PCW = 0X5b00
2254 23:22:33.348317 ===================================
2255 23:22:33.351534 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2256 23:22:33.358243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2257 23:22:33.364854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 23:22:33.367552 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2259 23:22:33.371198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2260 23:22:33.374512 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2261 23:22:33.377603 [ANA_INIT] flow start
2262 23:22:33.377685 [ANA_INIT] PLL >>>>>>>>
2263 23:22:33.381266 [ANA_INIT] PLL <<<<<<<<
2264 23:22:33.384245 [ANA_INIT] MIDPI >>>>>>>>
2265 23:22:33.387542 [ANA_INIT] MIDPI <<<<<<<<
2266 23:22:33.387625 [ANA_INIT] DLL >>>>>>>>
2267 23:22:33.390841 [ANA_INIT] DLL <<<<<<<<
2268 23:22:33.390923 [ANA_INIT] flow end
2269 23:22:33.397502 ============ LP4 DIFF to SE enter ============
2270 23:22:33.400630 ============ LP4 DIFF to SE exit ============
2271 23:22:33.403945 [ANA_INIT] <<<<<<<<<<<<<
2272 23:22:33.407110 [Flow] Enable top DCM control >>>>>
2273 23:22:33.410646 [Flow] Enable top DCM control <<<<<
2274 23:22:33.413727 Enable DLL master slave shuffle
2275 23:22:33.417143 ==============================================================
2276 23:22:33.420982 Gating Mode config
2277 23:22:33.424235 ==============================================================
2278 23:22:33.427513 Config description:
2279 23:22:33.436918 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2280 23:22:33.443891 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2281 23:22:33.446899 SELPH_MODE 0: By rank 1: By Phase
2282 23:22:33.454028 ==============================================================
2283 23:22:33.456830 GAT_TRACK_EN = 1
2284 23:22:33.460109 RX_GATING_MODE = 2
2285 23:22:33.463499 RX_GATING_TRACK_MODE = 2
2286 23:22:33.467213 SELPH_MODE = 1
2287 23:22:33.470511 PICG_EARLY_EN = 1
2288 23:22:33.473246 VALID_LAT_VALUE = 1
2289 23:22:33.477004 ==============================================================
2290 23:22:33.480107 Enter into Gating configuration >>>>
2291 23:22:33.483336 Exit from Gating configuration <<<<
2292 23:22:33.487095 Enter into DVFS_PRE_config >>>>>
2293 23:22:33.496510 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2294 23:22:33.500089 Exit from DVFS_PRE_config <<<<<
2295 23:22:33.503211 Enter into PICG configuration >>>>
2296 23:22:33.506550 Exit from PICG configuration <<<<
2297 23:22:33.509806 [RX_INPUT] configuration >>>>>
2298 23:22:33.513548 [RX_INPUT] configuration <<<<<
2299 23:22:33.520166 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2300 23:22:33.523064 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2301 23:22:33.529935 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2302 23:22:33.536580 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2303 23:22:33.543075 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2304 23:22:33.549923 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2305 23:22:33.553371 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2306 23:22:33.556648 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2307 23:22:33.559956 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2308 23:22:33.566577 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2309 23:22:33.569534 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2310 23:22:33.572762 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2311 23:22:33.576148 ===================================
2312 23:22:33.579305 LPDDR4 DRAM CONFIGURATION
2313 23:22:33.582683 ===================================
2314 23:22:33.582786 EX_ROW_EN[0] = 0x0
2315 23:22:33.586545 EX_ROW_EN[1] = 0x0
2316 23:22:33.589540 LP4Y_EN = 0x0
2317 23:22:33.589621 WORK_FSP = 0x0
2318 23:22:33.592573 WL = 0x4
2319 23:22:33.592654 RL = 0x4
2320 23:22:33.596074 BL = 0x2
2321 23:22:33.596170 RPST = 0x0
2322 23:22:33.599264 RD_PRE = 0x0
2323 23:22:33.599379 WR_PRE = 0x1
2324 23:22:33.602623 WR_PST = 0x0
2325 23:22:33.602720 DBI_WR = 0x0
2326 23:22:33.606180 DBI_RD = 0x0
2327 23:22:33.606261 OTF = 0x1
2328 23:22:33.609206 ===================================
2329 23:22:33.612673 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2330 23:22:33.619351 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2331 23:22:33.622701 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2332 23:22:33.625934 ===================================
2333 23:22:33.629143 LPDDR4 DRAM CONFIGURATION
2334 23:22:33.632699 ===================================
2335 23:22:33.632783 EX_ROW_EN[0] = 0x10
2336 23:22:33.636142 EX_ROW_EN[1] = 0x0
2337 23:22:33.639151 LP4Y_EN = 0x0
2338 23:22:33.639272 WORK_FSP = 0x0
2339 23:22:33.642884 WL = 0x4
2340 23:22:33.642965 RL = 0x4
2341 23:22:33.645781 BL = 0x2
2342 23:22:33.645862 RPST = 0x0
2343 23:22:33.649066 RD_PRE = 0x0
2344 23:22:33.649191 WR_PRE = 0x1
2345 23:22:33.652846 WR_PST = 0x0
2346 23:22:33.652927 DBI_WR = 0x0
2347 23:22:33.655945 DBI_RD = 0x0
2348 23:22:33.656026 OTF = 0x1
2349 23:22:33.659256 ===================================
2350 23:22:33.665887 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2351 23:22:33.665971 ==
2352 23:22:33.669146 Dram Type= 6, Freq= 0, CH_0, rank 0
2353 23:22:33.672609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2354 23:22:33.672708 ==
2355 23:22:33.676156 [Duty_Offset_Calibration]
2356 23:22:33.679380 B0:2 B1:0 CA:4
2357 23:22:33.679475
2358 23:22:33.682617 [DutyScan_Calibration_Flow] k_type=0
2359 23:22:33.689838
2360 23:22:33.689928 ==CLK 0==
2361 23:22:33.693159 Final CLK duty delay cell = -4
2362 23:22:33.696438 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2363 23:22:33.699990 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2364 23:22:33.703034 [-4] AVG Duty = 4937%(X100)
2365 23:22:33.703128
2366 23:22:33.706924 CH0 CLK Duty spec in!! Max-Min= 187%
2367 23:22:33.709615 [DutyScan_Calibration_Flow] ====Done====
2368 23:22:33.709698
2369 23:22:33.712935 [DutyScan_Calibration_Flow] k_type=1
2370 23:22:33.729441
2371 23:22:33.729527 ==DQS 0 ==
2372 23:22:33.733076 Final DQS duty delay cell = 0
2373 23:22:33.735732 [0] MAX Duty = 5156%(X100), DQS PI = 18
2374 23:22:33.739406 [0] MIN Duty = 5093%(X100), DQS PI = 2
2375 23:22:33.742892 [0] AVG Duty = 5124%(X100)
2376 23:22:33.742974
2377 23:22:33.743038 ==DQS 1 ==
2378 23:22:33.746103 Final DQS duty delay cell = 0
2379 23:22:33.749465 [0] MAX Duty = 5125%(X100), DQS PI = 4
2380 23:22:33.752245 [0] MIN Duty = 5000%(X100), DQS PI = 0
2381 23:22:33.756047 [0] AVG Duty = 5062%(X100)
2382 23:22:33.756130
2383 23:22:33.759260 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2384 23:22:33.759342
2385 23:22:33.762269 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2386 23:22:33.765704 [DutyScan_Calibration_Flow] ====Done====
2387 23:22:33.765786
2388 23:22:33.768655 [DutyScan_Calibration_Flow] k_type=3
2389 23:22:33.785428
2390 23:22:33.785513 ==DQM 0 ==
2391 23:22:33.789078 Final DQM duty delay cell = 0
2392 23:22:33.792060 [0] MAX Duty = 5093%(X100), DQS PI = 18
2393 23:22:33.796001 [0] MIN Duty = 4844%(X100), DQS PI = 50
2394 23:22:33.798613 [0] AVG Duty = 4968%(X100)
2395 23:22:33.798741
2396 23:22:33.798835 ==DQM 1 ==
2397 23:22:33.801782 Final DQM duty delay cell = 0
2398 23:22:33.805193 [0] MAX Duty = 5000%(X100), DQS PI = 6
2399 23:22:33.808700 [0] MIN Duty = 4875%(X100), DQS PI = 20
2400 23:22:33.811829 [0] AVG Duty = 4937%(X100)
2401 23:22:33.811940
2402 23:22:33.815049 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2403 23:22:33.815160
2404 23:22:33.818800 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2405 23:22:33.821916 [DutyScan_Calibration_Flow] ====Done====
2406 23:22:33.822019
2407 23:22:33.825176 [DutyScan_Calibration_Flow] k_type=2
2408 23:22:33.842517
2409 23:22:33.842631 ==DQ 0 ==
2410 23:22:33.845310 Final DQ duty delay cell = 0
2411 23:22:33.848849 [0] MAX Duty = 5125%(X100), DQS PI = 18
2412 23:22:33.851785 [0] MIN Duty = 4969%(X100), DQS PI = 58
2413 23:22:33.851872 [0] AVG Duty = 5047%(X100)
2414 23:22:33.855280
2415 23:22:33.855395 ==DQ 1 ==
2416 23:22:33.858762 Final DQ duty delay cell = 0
2417 23:22:33.862052 [0] MAX Duty = 5156%(X100), DQS PI = 4
2418 23:22:33.865420 [0] MIN Duty = 4938%(X100), DQS PI = 16
2419 23:22:33.865536 [0] AVG Duty = 5047%(X100)
2420 23:22:33.865630
2421 23:22:33.868637 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2422 23:22:33.871942
2423 23:22:33.875109 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2424 23:22:33.878249 [DutyScan_Calibration_Flow] ====Done====
2425 23:22:33.878329 ==
2426 23:22:33.881657 Dram Type= 6, Freq= 0, CH_1, rank 0
2427 23:22:33.885037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2428 23:22:33.885119 ==
2429 23:22:33.888631 [Duty_Offset_Calibration]
2430 23:22:33.888717 B0:0 B1:-1 CA:3
2431 23:22:33.888785
2432 23:22:33.891368 [DutyScan_Calibration_Flow] k_type=0
2433 23:22:33.901539
2434 23:22:33.901620 ==CLK 0==
2435 23:22:33.904626 Final CLK duty delay cell = -4
2436 23:22:33.908146 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2437 23:22:33.911278 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2438 23:22:33.914752 [-4] AVG Duty = 4938%(X100)
2439 23:22:33.914875
2440 23:22:33.918110 CH1 CLK Duty spec in!! Max-Min= 124%
2441 23:22:33.921340 [DutyScan_Calibration_Flow] ====Done====
2442 23:22:33.921461
2443 23:22:33.924540 [DutyScan_Calibration_Flow] k_type=1
2444 23:22:33.940732
2445 23:22:33.940871 ==DQS 0 ==
2446 23:22:33.944200 Final DQS duty delay cell = 0
2447 23:22:33.947547 [0] MAX Duty = 5187%(X100), DQS PI = 18
2448 23:22:33.950963 [0] MIN Duty = 4907%(X100), DQS PI = 38
2449 23:22:33.953917 [0] AVG Duty = 5047%(X100)
2450 23:22:33.954039
2451 23:22:33.954154 ==DQS 1 ==
2452 23:22:33.957614 Final DQS duty delay cell = 0
2453 23:22:33.960873 [0] MAX Duty = 5156%(X100), DQS PI = 8
2454 23:22:33.964235 [0] MIN Duty = 5031%(X100), DQS PI = 18
2455 23:22:33.964361 [0] AVG Duty = 5093%(X100)
2456 23:22:33.967245
2457 23:22:33.970607 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2458 23:22:33.970732
2459 23:22:33.974070 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2460 23:22:33.977225 [DutyScan_Calibration_Flow] ====Done====
2461 23:22:33.977347
2462 23:22:33.980564 [DutyScan_Calibration_Flow] k_type=3
2463 23:22:33.998209
2464 23:22:33.998333 ==DQM 0 ==
2465 23:22:34.001419 Final DQM duty delay cell = 0
2466 23:22:34.004671 [0] MAX Duty = 5031%(X100), DQS PI = 28
2467 23:22:34.007973 [0] MIN Duty = 4813%(X100), DQS PI = 38
2468 23:22:34.011880 [0] AVG Duty = 4922%(X100)
2469 23:22:34.012003
2470 23:22:34.012113 ==DQM 1 ==
2471 23:22:34.015141 Final DQM duty delay cell = 4
2472 23:22:34.017936 [4] MAX Duty = 5187%(X100), DQS PI = 32
2473 23:22:34.021410 [4] MIN Duty = 5062%(X100), DQS PI = 18
2474 23:22:34.024838 [4] AVG Duty = 5124%(X100)
2475 23:22:34.024958
2476 23:22:34.028120 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2477 23:22:34.028240
2478 23:22:34.031435 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2479 23:22:34.034512 [DutyScan_Calibration_Flow] ====Done====
2480 23:22:34.034627
2481 23:22:34.037802 [DutyScan_Calibration_Flow] k_type=2
2482 23:22:34.054848
2483 23:22:34.054972 ==DQ 0 ==
2484 23:22:34.058341 Final DQ duty delay cell = -4
2485 23:22:34.061122 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2486 23:22:34.064802 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2487 23:22:34.068449 [-4] AVG Duty = 4937%(X100)
2488 23:22:34.068569
2489 23:22:34.068682 ==DQ 1 ==
2490 23:22:34.071440 Final DQ duty delay cell = 4
2491 23:22:34.074792 [4] MAX Duty = 5156%(X100), DQS PI = 26
2492 23:22:34.078138 [4] MIN Duty = 5031%(X100), DQS PI = 62
2493 23:22:34.081333 [4] AVG Duty = 5093%(X100)
2494 23:22:34.081456
2495 23:22:34.084817 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2496 23:22:34.084939
2497 23:22:34.087599 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2498 23:22:34.091241 [DutyScan_Calibration_Flow] ====Done====
2499 23:22:34.094620 nWR fixed to 30
2500 23:22:34.097794 [ModeRegInit_LP4] CH0 RK0
2501 23:22:34.097914 [ModeRegInit_LP4] CH0 RK1
2502 23:22:34.101246 [ModeRegInit_LP4] CH1 RK0
2503 23:22:34.104411 [ModeRegInit_LP4] CH1 RK1
2504 23:22:34.104532 match AC timing 7
2505 23:22:34.111180 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2506 23:22:34.114332 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2507 23:22:34.117707 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2508 23:22:34.124690 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2509 23:22:34.127698 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2510 23:22:34.127818 ==
2511 23:22:34.130844 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 23:22:34.134272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 23:22:34.134391 ==
2514 23:22:34.140749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2515 23:22:34.147802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2516 23:22:34.155284 [CA 0] Center 39 (9~70) winsize 62
2517 23:22:34.158595 [CA 1] Center 39 (9~70) winsize 62
2518 23:22:34.161607 [CA 2] Center 35 (5~66) winsize 62
2519 23:22:34.164875 [CA 3] Center 35 (5~66) winsize 62
2520 23:22:34.168145 [CA 4] Center 34 (4~64) winsize 61
2521 23:22:34.171321 [CA 5] Center 33 (3~64) winsize 62
2522 23:22:34.171492
2523 23:22:34.174827 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2524 23:22:34.174954
2525 23:22:34.178222 [CATrainingPosCal] consider 1 rank data
2526 23:22:34.181359 u2DelayCellTimex100 = 270/100 ps
2527 23:22:34.185469 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2528 23:22:34.191606 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2529 23:22:34.194794 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2530 23:22:34.198192 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2531 23:22:34.201428 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2532 23:22:34.204935 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2533 23:22:34.205054
2534 23:22:34.208351 CA PerBit enable=1, Macro0, CA PI delay=33
2535 23:22:34.208477
2536 23:22:34.211618 [CBTSetCACLKResult] CA Dly = 33
2537 23:22:34.211738 CS Dly: 7 (0~38)
2538 23:22:34.214544 ==
2539 23:22:34.218312 Dram Type= 6, Freq= 0, CH_0, rank 1
2540 23:22:34.221432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2541 23:22:34.221530 ==
2542 23:22:34.224682 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2543 23:22:34.230859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2544 23:22:34.240878 [CA 0] Center 39 (9~70) winsize 62
2545 23:22:34.244335 [CA 1] Center 39 (9~70) winsize 62
2546 23:22:34.247319 [CA 2] Center 35 (5~66) winsize 62
2547 23:22:34.251029 [CA 3] Center 35 (5~66) winsize 62
2548 23:22:34.253986 [CA 4] Center 34 (4~65) winsize 62
2549 23:22:34.257729 [CA 5] Center 33 (3~64) winsize 62
2550 23:22:34.257858
2551 23:22:34.260616 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2552 23:22:34.260743
2553 23:22:34.263885 [CATrainingPosCal] consider 2 rank data
2554 23:22:34.267379 u2DelayCellTimex100 = 270/100 ps
2555 23:22:34.270668 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2556 23:22:34.277545 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2557 23:22:34.280655 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2558 23:22:34.284180 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2559 23:22:34.286861 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2560 23:22:34.290669 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2561 23:22:34.290787
2562 23:22:34.293583 CA PerBit enable=1, Macro0, CA PI delay=33
2563 23:22:34.293702
2564 23:22:34.296815 [CBTSetCACLKResult] CA Dly = 33
2565 23:22:34.300263 CS Dly: 8 (0~41)
2566 23:22:34.300381
2567 23:22:34.303580 ----->DramcWriteLeveling(PI) begin...
2568 23:22:34.303700 ==
2569 23:22:34.306923 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 23:22:34.310111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 23:22:34.310232 ==
2572 23:22:34.313588 Write leveling (Byte 0): 31 => 31
2573 23:22:34.316742 Write leveling (Byte 1): 27 => 27
2574 23:22:34.319822 DramcWriteLeveling(PI) end<-----
2575 23:22:34.319941
2576 23:22:34.320051 ==
2577 23:22:34.323711 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 23:22:34.326434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 23:22:34.326553 ==
2580 23:22:34.330268 [Gating] SW mode calibration
2581 23:22:34.336537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2582 23:22:34.343218 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2583 23:22:34.346522 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2584 23:22:34.350200 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2585 23:22:34.356390 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 23:22:34.359666 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 23:22:34.362963 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 23:22:34.369721 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 23:22:34.373030 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2590 23:22:34.376744 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
2591 23:22:34.383338 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
2592 23:22:34.386259 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2593 23:22:34.389694 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 23:22:34.396683 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 23:22:34.399356 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 23:22:34.403163 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 23:22:34.409599 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2598 23:22:34.413187 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2599 23:22:34.416551 1 1 0 | B1->B0 | 2424 4646 | 1 0 | (0 0) (0 0)
2600 23:22:34.423229 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2601 23:22:34.426095 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 23:22:34.429715 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 23:22:34.436109 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 23:22:34.439515 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 23:22:34.442896 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2606 23:22:34.449138 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2607 23:22:34.452482 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2608 23:22:34.456222 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2609 23:22:34.463153 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 23:22:34.465876 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:22:34.469300 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:22:34.472819 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:22:34.478954 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:22:34.482499 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:22:34.486165 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:22:34.492743 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 23:22:34.495608 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 23:22:34.499163 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 23:22:34.505615 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 23:22:34.509119 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 23:22:34.512182 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2622 23:22:34.518958 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2623 23:22:34.522369 Total UI for P1: 0, mck2ui 16
2624 23:22:34.525739 best dqsien dly found for B0: ( 1, 3, 24)
2625 23:22:34.528819 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2626 23:22:34.532221 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2627 23:22:34.539237 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 23:22:34.539346 Total UI for P1: 0, mck2ui 16
2629 23:22:34.545244 best dqsien dly found for B1: ( 1, 4, 2)
2630 23:22:34.549176 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2631 23:22:34.552315 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2632 23:22:34.552395
2633 23:22:34.555162 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2634 23:22:34.558967 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2635 23:22:34.562078 [Gating] SW calibration Done
2636 23:22:34.562189 ==
2637 23:22:34.565189 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 23:22:34.568592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 23:22:34.568674 ==
2640 23:22:34.572170 RX Vref Scan: 0
2641 23:22:34.572309
2642 23:22:34.572421 RX Vref 0 -> 0, step: 1
2643 23:22:34.572529
2644 23:22:34.575241 RX Delay -40 -> 252, step: 8
2645 23:22:34.578364 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2646 23:22:34.585232 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2647 23:22:34.588365 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2648 23:22:34.591446 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2649 23:22:34.595314 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2650 23:22:34.598415 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2651 23:22:34.605111 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2652 23:22:34.608099 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2653 23:22:34.612020 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2654 23:22:34.615068 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2655 23:22:34.618106 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2656 23:22:34.624835 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2657 23:22:34.627975 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2658 23:22:34.631260 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2659 23:22:34.634638 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2660 23:22:34.641458 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2661 23:22:34.641559 ==
2662 23:22:34.644763 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 23:22:34.648042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 23:22:34.648160 ==
2665 23:22:34.648270 DQS Delay:
2666 23:22:34.651242 DQS0 = 0, DQS1 = 0
2667 23:22:34.651383 DQM Delay:
2668 23:22:34.654409 DQM0 = 117, DQM1 = 107
2669 23:22:34.654523 DQ Delay:
2670 23:22:34.658081 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2671 23:22:34.661075 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2672 23:22:34.664407 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2673 23:22:34.668338 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2674 23:22:34.668457
2675 23:22:34.668566
2676 23:22:34.671463 ==
2677 23:22:34.671582 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 23:22:34.678088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 23:22:34.678210 ==
2680 23:22:34.678313
2681 23:22:34.678419
2682 23:22:34.681644 TX Vref Scan disable
2683 23:22:34.681784 == TX Byte 0 ==
2684 23:22:34.684442 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2685 23:22:34.690943 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2686 23:22:34.691050 == TX Byte 1 ==
2687 23:22:34.694298 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2688 23:22:34.701024 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2689 23:22:34.701120 ==
2690 23:22:34.704804 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 23:22:34.708000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 23:22:34.708083 ==
2693 23:22:34.719814 TX Vref=22, minBit 0, minWin=25, winSum=407
2694 23:22:34.723026 TX Vref=24, minBit 1, minWin=25, winSum=415
2695 23:22:34.725997 TX Vref=26, minBit 1, minWin=26, winSum=422
2696 23:22:34.730137 TX Vref=28, minBit 1, minWin=25, winSum=421
2697 23:22:34.732831 TX Vref=30, minBit 0, minWin=26, winSum=429
2698 23:22:34.739679 TX Vref=32, minBit 2, minWin=26, winSum=426
2699 23:22:34.743083 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 30
2700 23:22:34.743186
2701 23:22:34.746329 Final TX Range 1 Vref 30
2702 23:22:34.746429
2703 23:22:34.746517 ==
2704 23:22:34.749706 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 23:22:34.753119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 23:22:34.753218 ==
2707 23:22:34.756483
2708 23:22:34.756579
2709 23:22:34.756667 TX Vref Scan disable
2710 23:22:34.759495 == TX Byte 0 ==
2711 23:22:34.762822 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2712 23:22:34.766257 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2713 23:22:34.769418 == TX Byte 1 ==
2714 23:22:34.772939 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2715 23:22:34.776215 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2716 23:22:34.779334
2717 23:22:34.779425 [DATLAT]
2718 23:22:34.779487 Freq=1200, CH0 RK0
2719 23:22:34.779546
2720 23:22:34.782742 DATLAT Default: 0xd
2721 23:22:34.782836 0, 0xFFFF, sum = 0
2722 23:22:34.786132 1, 0xFFFF, sum = 0
2723 23:22:34.786235 2, 0xFFFF, sum = 0
2724 23:22:34.789437 3, 0xFFFF, sum = 0
2725 23:22:34.793009 4, 0xFFFF, sum = 0
2726 23:22:34.793112 5, 0xFFFF, sum = 0
2727 23:22:34.796343 6, 0xFFFF, sum = 0
2728 23:22:34.796446 7, 0xFFFF, sum = 0
2729 23:22:34.799092 8, 0xFFFF, sum = 0
2730 23:22:34.799190 9, 0xFFFF, sum = 0
2731 23:22:34.802860 10, 0xFFFF, sum = 0
2732 23:22:34.802944 11, 0xFFFF, sum = 0
2733 23:22:34.805670 12, 0x0, sum = 1
2734 23:22:34.805785 13, 0x0, sum = 2
2735 23:22:34.809060 14, 0x0, sum = 3
2736 23:22:34.809135 15, 0x0, sum = 4
2737 23:22:34.812598 best_step = 13
2738 23:22:34.812678
2739 23:22:34.812760 ==
2740 23:22:34.815932 Dram Type= 6, Freq= 0, CH_0, rank 0
2741 23:22:34.819495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2742 23:22:34.819576 ==
2743 23:22:34.819640 RX Vref Scan: 1
2744 23:22:34.819699
2745 23:22:34.822822 Set Vref Range= 32 -> 127
2746 23:22:34.822928
2747 23:22:34.825928 RX Vref 32 -> 127, step: 1
2748 23:22:34.826000
2749 23:22:34.829507 RX Delay -21 -> 252, step: 4
2750 23:22:34.829587
2751 23:22:34.832431 Set Vref, RX VrefLevel [Byte0]: 32
2752 23:22:34.835660 [Byte1]: 32
2753 23:22:34.835741
2754 23:22:34.838933 Set Vref, RX VrefLevel [Byte0]: 33
2755 23:22:34.842179 [Byte1]: 33
2756 23:22:34.845981
2757 23:22:34.846082 Set Vref, RX VrefLevel [Byte0]: 34
2758 23:22:34.849286 [Byte1]: 34
2759 23:22:34.853757
2760 23:22:34.853841 Set Vref, RX VrefLevel [Byte0]: 35
2761 23:22:34.857214 [Byte1]: 35
2762 23:22:34.862007
2763 23:22:34.862115 Set Vref, RX VrefLevel [Byte0]: 36
2764 23:22:34.865248 [Byte1]: 36
2765 23:22:34.869653
2766 23:22:34.869770 Set Vref, RX VrefLevel [Byte0]: 37
2767 23:22:34.873190 [Byte1]: 37
2768 23:22:34.877532
2769 23:22:34.877649 Set Vref, RX VrefLevel [Byte0]: 38
2770 23:22:34.881014 [Byte1]: 38
2771 23:22:34.885550
2772 23:22:34.885657 Set Vref, RX VrefLevel [Byte0]: 39
2773 23:22:34.888767 [Byte1]: 39
2774 23:22:34.893642
2775 23:22:34.893738 Set Vref, RX VrefLevel [Byte0]: 40
2776 23:22:34.896886 [Byte1]: 40
2777 23:22:34.901760
2778 23:22:34.901856 Set Vref, RX VrefLevel [Byte0]: 41
2779 23:22:34.905023 [Byte1]: 41
2780 23:22:34.909512
2781 23:22:34.909612 Set Vref, RX VrefLevel [Byte0]: 42
2782 23:22:34.912811 [Byte1]: 42
2783 23:22:34.917276
2784 23:22:34.917372 Set Vref, RX VrefLevel [Byte0]: 43
2785 23:22:34.920893 [Byte1]: 43
2786 23:22:34.925168
2787 23:22:34.925268 Set Vref, RX VrefLevel [Byte0]: 44
2788 23:22:34.928352 [Byte1]: 44
2789 23:22:34.933286
2790 23:22:34.933389 Set Vref, RX VrefLevel [Byte0]: 45
2791 23:22:34.936712 [Byte1]: 45
2792 23:22:34.941486
2793 23:22:34.941581 Set Vref, RX VrefLevel [Byte0]: 46
2794 23:22:34.944177 [Byte1]: 46
2795 23:22:34.949004
2796 23:22:34.949113 Set Vref, RX VrefLevel [Byte0]: 47
2797 23:22:34.952064 [Byte1]: 47
2798 23:22:34.956826
2799 23:22:34.956907 Set Vref, RX VrefLevel [Byte0]: 48
2800 23:22:34.960107 [Byte1]: 48
2801 23:22:34.964980
2802 23:22:34.965105 Set Vref, RX VrefLevel [Byte0]: 49
2803 23:22:34.967885 [Byte1]: 49
2804 23:22:34.972652
2805 23:22:34.972747 Set Vref, RX VrefLevel [Byte0]: 50
2806 23:22:34.975841 [Byte1]: 50
2807 23:22:34.980863
2808 23:22:34.980944 Set Vref, RX VrefLevel [Byte0]: 51
2809 23:22:34.984317 [Byte1]: 51
2810 23:22:34.988587
2811 23:22:34.988693 Set Vref, RX VrefLevel [Byte0]: 52
2812 23:22:34.991790 [Byte1]: 52
2813 23:22:34.996755
2814 23:22:34.996834 Set Vref, RX VrefLevel [Byte0]: 53
2815 23:22:35.000203 [Byte1]: 53
2816 23:22:35.004954
2817 23:22:35.005034 Set Vref, RX VrefLevel [Byte0]: 54
2818 23:22:35.007487 [Byte1]: 54
2819 23:22:35.012291
2820 23:22:35.012372 Set Vref, RX VrefLevel [Byte0]: 55
2821 23:22:35.015685 [Byte1]: 55
2822 23:22:35.020607
2823 23:22:35.020697 Set Vref, RX VrefLevel [Byte0]: 56
2824 23:22:35.023745 [Byte1]: 56
2825 23:22:35.028350
2826 23:22:35.028432 Set Vref, RX VrefLevel [Byte0]: 57
2827 23:22:35.031373 [Byte1]: 57
2828 23:22:35.036366
2829 23:22:35.036474 Set Vref, RX VrefLevel [Byte0]: 58
2830 23:22:35.039395 [Byte1]: 58
2831 23:22:35.044068
2832 23:22:35.044149 Set Vref, RX VrefLevel [Byte0]: 59
2833 23:22:35.047356 [Byte1]: 59
2834 23:22:35.051991
2835 23:22:35.052072 Set Vref, RX VrefLevel [Byte0]: 60
2836 23:22:35.055174 [Byte1]: 60
2837 23:22:35.060258
2838 23:22:35.060339 Set Vref, RX VrefLevel [Byte0]: 61
2839 23:22:35.063061 [Byte1]: 61
2840 23:22:35.067992
2841 23:22:35.068073 Set Vref, RX VrefLevel [Byte0]: 62
2842 23:22:35.071072 [Byte1]: 62
2843 23:22:35.075739
2844 23:22:35.075822 Set Vref, RX VrefLevel [Byte0]: 63
2845 23:22:35.079510 [Byte1]: 63
2846 23:22:35.083599
2847 23:22:35.083696 Set Vref, RX VrefLevel [Byte0]: 64
2848 23:22:35.087041 [Byte1]: 64
2849 23:22:35.091562
2850 23:22:35.091643 Set Vref, RX VrefLevel [Byte0]: 65
2851 23:22:35.094936 [Byte1]: 65
2852 23:22:35.099636
2853 23:22:35.099722 Set Vref, RX VrefLevel [Byte0]: 66
2854 23:22:35.102694 [Byte1]: 66
2855 23:22:35.107559
2856 23:22:35.107637 Set Vref, RX VrefLevel [Byte0]: 67
2857 23:22:35.110742 [Byte1]: 67
2858 23:22:35.115702
2859 23:22:35.115781 Set Vref, RX VrefLevel [Byte0]: 68
2860 23:22:35.118712 [Byte1]: 68
2861 23:22:35.123484
2862 23:22:35.123581 Set Vref, RX VrefLevel [Byte0]: 69
2863 23:22:35.126368 [Byte1]: 69
2864 23:22:35.131120
2865 23:22:35.131230 Set Vref, RX VrefLevel [Byte0]: 70
2866 23:22:35.134583 [Byte1]: 70
2867 23:22:35.138953
2868 23:22:35.139024 Final RX Vref Byte 0 = 53 to rank0
2869 23:22:35.143037 Final RX Vref Byte 1 = 59 to rank0
2870 23:22:35.146298 Final RX Vref Byte 0 = 53 to rank1
2871 23:22:35.149159 Final RX Vref Byte 1 = 59 to rank1==
2872 23:22:35.152417 Dram Type= 6, Freq= 0, CH_0, rank 0
2873 23:22:35.156410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 23:22:35.159234 ==
2875 23:22:35.159314 DQS Delay:
2876 23:22:35.159418 DQS0 = 0, DQS1 = 0
2877 23:22:35.162856 DQM Delay:
2878 23:22:35.162937 DQM0 = 117, DQM1 = 105
2879 23:22:35.165680 DQ Delay:
2880 23:22:35.169033 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2881 23:22:35.172733 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2882 23:22:35.175813 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2883 23:22:35.178865 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2884 23:22:35.178947
2885 23:22:35.179010
2886 23:22:35.186158 [DQSOSCAuto] RK0, (LSB)MR18= 0xfffb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2887 23:22:35.189293 CH0 RK0: MR19=303, MR18=FFFB
2888 23:22:35.196045 CH0_RK0: MR19=0x303, MR18=0xFFFB, DQSOSC=410, MR23=63, INC=39, DEC=26
2889 23:22:35.196126
2890 23:22:35.199414 ----->DramcWriteLeveling(PI) begin...
2891 23:22:35.199510 ==
2892 23:22:35.202371 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 23:22:35.205757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 23:22:35.208953 ==
2895 23:22:35.209032 Write leveling (Byte 0): 31 => 31
2896 23:22:35.212184 Write leveling (Byte 1): 26 => 26
2897 23:22:35.215784 DramcWriteLeveling(PI) end<-----
2898 23:22:35.215864
2899 23:22:35.215927 ==
2900 23:22:35.218832 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 23:22:35.225443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 23:22:35.225524 ==
2903 23:22:35.229083 [Gating] SW mode calibration
2904 23:22:35.235928 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2905 23:22:35.239080 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2906 23:22:35.245469 0 15 0 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
2907 23:22:35.248654 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2908 23:22:35.251978 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 23:22:35.258495 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 23:22:35.261667 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 23:22:35.265327 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 23:22:35.272291 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2913 23:22:35.275389 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
2914 23:22:35.278145 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2915 23:22:35.285366 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 23:22:35.288235 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 23:22:35.291568 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 23:22:35.298818 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 23:22:35.302000 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 23:22:35.304889 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2921 23:22:35.308507 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2922 23:22:35.315070 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2923 23:22:35.318064 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 23:22:35.321761 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 23:22:35.328074 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 23:22:35.331151 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 23:22:35.334639 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 23:22:35.341057 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2929 23:22:35.344632 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2930 23:22:35.347987 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2931 23:22:35.354761 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:22:35.358336 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 23:22:35.361367 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 23:22:35.368175 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 23:22:35.371104 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 23:22:35.374605 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 23:22:35.381380 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 23:22:35.384834 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 23:22:35.387936 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 23:22:35.394191 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 23:22:35.397705 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 23:22:35.401004 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 23:22:35.407676 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2944 23:22:35.411134 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2945 23:22:35.414166 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2946 23:22:35.417389 Total UI for P1: 0, mck2ui 16
2947 23:22:35.420939 best dqsien dly found for B0: ( 1, 3, 22)
2948 23:22:35.427334 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2949 23:22:35.431023 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 23:22:35.434234 Total UI for P1: 0, mck2ui 16
2951 23:22:35.437517 best dqsien dly found for B1: ( 1, 3, 30)
2952 23:22:35.440963 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2953 23:22:35.444193 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2954 23:22:35.444273
2955 23:22:35.447302 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2956 23:22:35.450688 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2957 23:22:35.453843 [Gating] SW calibration Done
2958 23:22:35.453952 ==
2959 23:22:35.457665 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 23:22:35.460957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 23:22:35.464388 ==
2962 23:22:35.464475 RX Vref Scan: 0
2963 23:22:35.464537
2964 23:22:35.467350 RX Vref 0 -> 0, step: 1
2965 23:22:35.467442
2966 23:22:35.470702 RX Delay -40 -> 252, step: 8
2967 23:22:35.473991 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2968 23:22:35.477239 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2969 23:22:35.480596 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2970 23:22:35.483792 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2971 23:22:35.490366 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2972 23:22:35.493907 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2973 23:22:35.497008 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2974 23:22:35.500020 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2975 23:22:35.503312 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2976 23:22:35.510226 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2977 23:22:35.513517 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2978 23:22:35.517092 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2979 23:22:35.520589 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2980 23:22:35.523774 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2981 23:22:35.530327 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2982 23:22:35.533262 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2983 23:22:35.533360 ==
2984 23:22:35.537096 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 23:22:35.539846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 23:22:35.539937 ==
2987 23:22:35.543540 DQS Delay:
2988 23:22:35.543619 DQS0 = 0, DQS1 = 0
2989 23:22:35.543681 DQM Delay:
2990 23:22:35.546682 DQM0 = 115, DQM1 = 109
2991 23:22:35.546763 DQ Delay:
2992 23:22:35.550083 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2993 23:22:35.553288 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2994 23:22:35.556781 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2995 23:22:35.563449 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2996 23:22:35.563580
2997 23:22:35.563660
2998 23:22:35.563720 ==
2999 23:22:35.566602 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 23:22:35.569866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 23:22:35.569945 ==
3002 23:22:35.570010
3003 23:22:35.570078
3004 23:22:35.573366 TX Vref Scan disable
3005 23:22:35.573460 == TX Byte 0 ==
3006 23:22:35.580434 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3007 23:22:35.583221 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3008 23:22:35.583327 == TX Byte 1 ==
3009 23:22:35.589819 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3010 23:22:35.593255 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3011 23:22:35.593351 ==
3012 23:22:35.596513 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 23:22:35.599967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 23:22:35.600070 ==
3015 23:22:35.613052 TX Vref=22, minBit 2, minWin=25, winSum=410
3016 23:22:35.616247 TX Vref=24, minBit 3, minWin=25, winSum=415
3017 23:22:35.619748 TX Vref=26, minBit 0, minWin=26, winSum=422
3018 23:22:35.622915 TX Vref=28, minBit 1, minWin=26, winSum=426
3019 23:22:35.626275 TX Vref=30, minBit 1, minWin=26, winSum=426
3020 23:22:35.633170 TX Vref=32, minBit 1, minWin=26, winSum=425
3021 23:22:35.636248 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 28
3022 23:22:35.636350
3023 23:22:35.639659 Final TX Range 1 Vref 28
3024 23:22:35.639758
3025 23:22:35.639850 ==
3026 23:22:35.642900 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 23:22:35.646138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 23:22:35.646241 ==
3029 23:22:35.649113
3030 23:22:35.649213
3031 23:22:35.649307 TX Vref Scan disable
3032 23:22:35.652736 == TX Byte 0 ==
3033 23:22:35.655885 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3034 23:22:35.662804 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3035 23:22:35.662946 == TX Byte 1 ==
3036 23:22:35.666247 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3037 23:22:35.672504 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3038 23:22:35.672633
3039 23:22:35.672748 [DATLAT]
3040 23:22:35.672855 Freq=1200, CH0 RK1
3041 23:22:35.672966
3042 23:22:35.675866 DATLAT Default: 0xd
3043 23:22:35.675990 0, 0xFFFF, sum = 0
3044 23:22:35.679454 1, 0xFFFF, sum = 0
3045 23:22:35.682378 2, 0xFFFF, sum = 0
3046 23:22:35.682502 3, 0xFFFF, sum = 0
3047 23:22:35.685861 4, 0xFFFF, sum = 0
3048 23:22:35.685986 5, 0xFFFF, sum = 0
3049 23:22:35.689083 6, 0xFFFF, sum = 0
3050 23:22:35.689206 7, 0xFFFF, sum = 0
3051 23:22:35.692668 8, 0xFFFF, sum = 0
3052 23:22:35.692788 9, 0xFFFF, sum = 0
3053 23:22:35.696010 10, 0xFFFF, sum = 0
3054 23:22:35.696114 11, 0xFFFF, sum = 0
3055 23:22:35.698786 12, 0x0, sum = 1
3056 23:22:35.698883 13, 0x0, sum = 2
3057 23:22:35.701923 14, 0x0, sum = 3
3058 23:22:35.702021 15, 0x0, sum = 4
3059 23:22:35.705325 best_step = 13
3060 23:22:35.705406
3061 23:22:35.705469 ==
3062 23:22:35.708670 Dram Type= 6, Freq= 0, CH_0, rank 1
3063 23:22:35.711942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 23:22:35.712051 ==
3065 23:22:35.715591 RX Vref Scan: 0
3066 23:22:35.715672
3067 23:22:35.715736 RX Vref 0 -> 0, step: 1
3068 23:22:35.715796
3069 23:22:35.718690 RX Delay -21 -> 252, step: 4
3070 23:22:35.725152 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3071 23:22:35.728502 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3072 23:22:35.731963 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3073 23:22:35.735094 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3074 23:22:35.738634 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3075 23:22:35.745589 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3076 23:22:35.748567 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3077 23:22:35.751785 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3078 23:22:35.755105 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3079 23:22:35.758293 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3080 23:22:35.765018 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3081 23:22:35.768310 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3082 23:22:35.771718 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3083 23:22:35.774799 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3084 23:22:35.778113 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3085 23:22:35.785033 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3086 23:22:35.785116 ==
3087 23:22:35.788210 Dram Type= 6, Freq= 0, CH_0, rank 1
3088 23:22:35.791339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 23:22:35.791435 ==
3090 23:22:35.791502 DQS Delay:
3091 23:22:35.794774 DQS0 = 0, DQS1 = 0
3092 23:22:35.794876 DQM Delay:
3093 23:22:35.798099 DQM0 = 115, DQM1 = 106
3094 23:22:35.798173 DQ Delay:
3095 23:22:35.801651 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3096 23:22:35.804865 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3097 23:22:35.807997 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3098 23:22:35.811581 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3099 23:22:35.811665
3100 23:22:35.814639
3101 23:22:35.821427 [DQSOSCAuto] RK1, (LSB)MR18= 0xfffd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3102 23:22:35.824624 CH0 RK1: MR19=303, MR18=FFFD
3103 23:22:35.831107 CH0_RK1: MR19=0x303, MR18=0xFFFD, DQSOSC=410, MR23=63, INC=39, DEC=26
3104 23:22:35.834793 [RxdqsGatingPostProcess] freq 1200
3105 23:22:35.838136 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3106 23:22:35.840932 best DQS0 dly(2T, 0.5T) = (0, 11)
3107 23:22:35.844621 best DQS1 dly(2T, 0.5T) = (0, 12)
3108 23:22:35.848225 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3109 23:22:35.851499 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3110 23:22:35.854885 best DQS0 dly(2T, 0.5T) = (0, 11)
3111 23:22:35.857927 best DQS1 dly(2T, 0.5T) = (0, 11)
3112 23:22:35.860830 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3113 23:22:35.864633 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3114 23:22:35.867714 Pre-setting of DQS Precalculation
3115 23:22:35.870786 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3116 23:22:35.870868 ==
3117 23:22:35.874049 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 23:22:35.877764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 23:22:35.881017 ==
3120 23:22:35.884157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3121 23:22:35.891003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3122 23:22:35.899049 [CA 0] Center 38 (8~68) winsize 61
3123 23:22:35.902310 [CA 1] Center 37 (7~68) winsize 62
3124 23:22:35.905645 [CA 2] Center 35 (5~65) winsize 61
3125 23:22:35.909083 [CA 3] Center 34 (4~64) winsize 61
3126 23:22:35.912653 [CA 4] Center 35 (5~65) winsize 61
3127 23:22:35.915985 [CA 5] Center 33 (3~63) winsize 61
3128 23:22:35.916092
3129 23:22:35.919228 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3130 23:22:35.919342
3131 23:22:35.922398 [CATrainingPosCal] consider 1 rank data
3132 23:22:35.925821 u2DelayCellTimex100 = 270/100 ps
3133 23:22:35.929183 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3134 23:22:35.935699 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3135 23:22:35.938915 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3136 23:22:35.942395 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3137 23:22:35.945217 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3138 23:22:35.948448 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3139 23:22:35.948549
3140 23:22:35.952333 CA PerBit enable=1, Macro0, CA PI delay=33
3141 23:22:35.952429
3142 23:22:35.955227 [CBTSetCACLKResult] CA Dly = 33
3143 23:22:35.958840 CS Dly: 4 (0~35)
3144 23:22:35.958921 ==
3145 23:22:35.961852 Dram Type= 6, Freq= 0, CH_1, rank 1
3146 23:22:35.965350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3147 23:22:35.965434 ==
3148 23:22:35.972159 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3149 23:22:35.975156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3150 23:22:35.984634 [CA 0] Center 37 (7~68) winsize 62
3151 23:22:35.987955 [CA 1] Center 37 (7~68) winsize 62
3152 23:22:35.991281 [CA 2] Center 35 (5~65) winsize 61
3153 23:22:35.994640 [CA 3] Center 33 (3~64) winsize 62
3154 23:22:35.998387 [CA 4] Center 34 (5~64) winsize 60
3155 23:22:36.001073 [CA 5] Center 33 (3~64) winsize 62
3156 23:22:36.001185
3157 23:22:36.004933 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3158 23:22:36.005040
3159 23:22:36.008165 [CATrainingPosCal] consider 2 rank data
3160 23:22:36.011262 u2DelayCellTimex100 = 270/100 ps
3161 23:22:36.014202 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3162 23:22:36.021255 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3163 23:22:36.024670 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3164 23:22:36.028037 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3165 23:22:36.031201 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3166 23:22:36.034598 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3167 23:22:36.034705
3168 23:22:36.038107 CA PerBit enable=1, Macro0, CA PI delay=33
3169 23:22:36.038212
3170 23:22:36.041252 [CBTSetCACLKResult] CA Dly = 33
3171 23:22:36.041350 CS Dly: 6 (0~39)
3172 23:22:36.044254
3173 23:22:36.047405 ----->DramcWriteLeveling(PI) begin...
3174 23:22:36.047512 ==
3175 23:22:36.050728 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 23:22:36.054007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3177 23:22:36.054112 ==
3178 23:22:36.057888 Write leveling (Byte 0): 26 => 26
3179 23:22:36.060864 Write leveling (Byte 1): 28 => 28
3180 23:22:36.064222 DramcWriteLeveling(PI) end<-----
3181 23:22:36.064323
3182 23:22:36.064412 ==
3183 23:22:36.067079 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 23:22:36.070396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 23:22:36.070493 ==
3186 23:22:36.073678 [Gating] SW mode calibration
3187 23:22:36.080672 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3188 23:22:36.087171 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3189 23:22:36.090316 0 15 0 | B1->B0 | 3030 3434 | 1 0 | (1 1) (0 0)
3190 23:22:36.093893 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 23:22:36.100202 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 23:22:36.103329 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 23:22:36.107171 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 23:22:36.113814 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 23:22:36.116943 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3196 23:22:36.120179 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
3197 23:22:36.126781 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 23:22:36.130367 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 23:22:36.133880 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 23:22:36.139906 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 23:22:36.143316 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 23:22:36.146914 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 23:22:36.153080 1 0 24 | B1->B0 | 2424 3232 | 0 1 | (0 0) (0 0)
3204 23:22:36.156436 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3205 23:22:36.159706 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 23:22:36.166594 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 23:22:36.170052 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 23:22:36.173640 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 23:22:36.180127 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 23:22:36.183347 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 23:22:36.186746 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3212 23:22:36.193157 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3213 23:22:36.196502 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:22:36.199671 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:22:36.203120 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:22:36.209894 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 23:22:36.213482 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 23:22:36.216454 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 23:22:36.222815 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 23:22:36.226572 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 23:22:36.229722 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 23:22:36.236331 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:22:36.239378 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 23:22:36.242866 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 23:22:36.249559 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 23:22:36.253151 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 23:22:36.256122 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3228 23:22:36.262821 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3229 23:22:36.266075 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 23:22:36.269479 Total UI for P1: 0, mck2ui 16
3231 23:22:36.272832 best dqsien dly found for B0: ( 1, 3, 26)
3232 23:22:36.276089 Total UI for P1: 0, mck2ui 16
3233 23:22:36.279505 best dqsien dly found for B1: ( 1, 3, 26)
3234 23:22:36.282860 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3235 23:22:36.285780 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3236 23:22:36.285851
3237 23:22:36.289070 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3238 23:22:36.292719 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3239 23:22:36.296172 [Gating] SW calibration Done
3240 23:22:36.296252 ==
3241 23:22:36.299353 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 23:22:36.306036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 23:22:36.306111 ==
3244 23:22:36.306181 RX Vref Scan: 0
3245 23:22:36.306240
3246 23:22:36.308902 RX Vref 0 -> 0, step: 1
3247 23:22:36.308981
3248 23:22:36.312446 RX Delay -40 -> 252, step: 8
3249 23:22:36.315596 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3250 23:22:36.319572 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3251 23:22:36.322046 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3252 23:22:36.325450 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3253 23:22:36.332092 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3254 23:22:36.335327 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3255 23:22:36.338660 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3256 23:22:36.341937 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3257 23:22:36.345434 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3258 23:22:36.351900 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3259 23:22:36.355337 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3260 23:22:36.358652 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3261 23:22:36.361854 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3262 23:22:36.368516 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3263 23:22:36.371960 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3264 23:22:36.375294 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3265 23:22:36.375420 ==
3266 23:22:36.378699 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 23:22:36.381862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 23:22:36.381947 ==
3269 23:22:36.385231 DQS Delay:
3270 23:22:36.385315 DQS0 = 0, DQS1 = 0
3271 23:22:36.388485 DQM Delay:
3272 23:22:36.388569 DQM0 = 116, DQM1 = 113
3273 23:22:36.388654 DQ Delay:
3274 23:22:36.395384 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3275 23:22:36.398584 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3276 23:22:36.402054 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3277 23:22:36.405393 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3278 23:22:36.405478
3279 23:22:36.405563
3280 23:22:36.405642 ==
3281 23:22:36.408239 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 23:22:36.411913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 23:22:36.411999 ==
3284 23:22:36.412083
3285 23:22:36.412162
3286 23:22:36.415514 TX Vref Scan disable
3287 23:22:36.418535 == TX Byte 0 ==
3288 23:22:36.422061 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3289 23:22:36.424960 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3290 23:22:36.428373 == TX Byte 1 ==
3291 23:22:36.431676 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3292 23:22:36.434886 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3293 23:22:36.434971 ==
3294 23:22:36.438290 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 23:22:36.441385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 23:22:36.445142 ==
3297 23:22:36.454875 TX Vref=22, minBit 3, minWin=25, winSum=411
3298 23:22:36.457975 TX Vref=24, minBit 3, minWin=25, winSum=417
3299 23:22:36.461803 TX Vref=26, minBit 0, minWin=26, winSum=424
3300 23:22:36.464600 TX Vref=28, minBit 9, minWin=26, winSum=428
3301 23:22:36.468045 TX Vref=30, minBit 8, minWin=26, winSum=427
3302 23:22:36.475056 TX Vref=32, minBit 0, minWin=26, winSum=426
3303 23:22:36.478102 [TxChooseVref] Worse bit 9, Min win 26, Win sum 428, Final Vref 28
3304 23:22:36.478180
3305 23:22:36.481243 Final TX Range 1 Vref 28
3306 23:22:36.481315
3307 23:22:36.481389 ==
3308 23:22:36.484431 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 23:22:36.487878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 23:22:36.487995 ==
3311 23:22:36.491201
3312 23:22:36.491313
3313 23:22:36.491416 TX Vref Scan disable
3314 23:22:36.494474 == TX Byte 0 ==
3315 23:22:36.498138 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3316 23:22:36.501466 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3317 23:22:36.504841 == TX Byte 1 ==
3318 23:22:36.508249 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3319 23:22:36.511107 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3320 23:22:36.514285
3321 23:22:36.514371 [DATLAT]
3322 23:22:36.514460 Freq=1200, CH1 RK0
3323 23:22:36.514543
3324 23:22:36.517721 DATLAT Default: 0xd
3325 23:22:36.517807 0, 0xFFFF, sum = 0
3326 23:22:36.521297 1, 0xFFFF, sum = 0
3327 23:22:36.521409 2, 0xFFFF, sum = 0
3328 23:22:36.524339 3, 0xFFFF, sum = 0
3329 23:22:36.527675 4, 0xFFFF, sum = 0
3330 23:22:36.527762 5, 0xFFFF, sum = 0
3331 23:22:36.530781 6, 0xFFFF, sum = 0
3332 23:22:36.530868 7, 0xFFFF, sum = 0
3333 23:22:36.534435 8, 0xFFFF, sum = 0
3334 23:22:36.534523 9, 0xFFFF, sum = 0
3335 23:22:36.537659 10, 0xFFFF, sum = 0
3336 23:22:36.537746 11, 0xFFFF, sum = 0
3337 23:22:36.541173 12, 0x0, sum = 1
3338 23:22:36.541260 13, 0x0, sum = 2
3339 23:22:36.544107 14, 0x0, sum = 3
3340 23:22:36.544197 15, 0x0, sum = 4
3341 23:22:36.547561 best_step = 13
3342 23:22:36.547647
3343 23:22:36.547733 ==
3344 23:22:36.551250 Dram Type= 6, Freq= 0, CH_1, rank 0
3345 23:22:36.554113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3346 23:22:36.554200 ==
3347 23:22:36.554286 RX Vref Scan: 1
3348 23:22:36.557200
3349 23:22:36.557286 Set Vref Range= 32 -> 127
3350 23:22:36.557372
3351 23:22:36.560918 RX Vref 32 -> 127, step: 1
3352 23:22:36.561004
3353 23:22:36.563867 RX Delay -13 -> 252, step: 4
3354 23:22:36.563953
3355 23:22:36.567440 Set Vref, RX VrefLevel [Byte0]: 32
3356 23:22:36.570780 [Byte1]: 32
3357 23:22:36.570867
3358 23:22:36.573749 Set Vref, RX VrefLevel [Byte0]: 33
3359 23:22:36.577239 [Byte1]: 33
3360 23:22:36.580654
3361 23:22:36.580741 Set Vref, RX VrefLevel [Byte0]: 34
3362 23:22:36.583865 [Byte1]: 34
3363 23:22:36.588605
3364 23:22:36.588688 Set Vref, RX VrefLevel [Byte0]: 35
3365 23:22:36.592129 [Byte1]: 35
3366 23:22:36.596653
3367 23:22:36.596736 Set Vref, RX VrefLevel [Byte0]: 36
3368 23:22:36.600085 [Byte1]: 36
3369 23:22:36.604348
3370 23:22:36.604431 Set Vref, RX VrefLevel [Byte0]: 37
3371 23:22:36.607663 [Byte1]: 37
3372 23:22:36.612224
3373 23:22:36.612392 Set Vref, RX VrefLevel [Byte0]: 38
3374 23:22:36.615564 [Byte1]: 38
3375 23:22:36.620292
3376 23:22:36.620404 Set Vref, RX VrefLevel [Byte0]: 39
3377 23:22:36.623208 [Byte1]: 39
3378 23:22:36.628042
3379 23:22:36.628131 Set Vref, RX VrefLevel [Byte0]: 40
3380 23:22:36.631211 [Byte1]: 40
3381 23:22:36.635820
3382 23:22:36.635903 Set Vref, RX VrefLevel [Byte0]: 41
3383 23:22:36.639438 [Byte1]: 41
3384 23:22:36.644145
3385 23:22:36.644228 Set Vref, RX VrefLevel [Byte0]: 42
3386 23:22:36.647340 [Byte1]: 42
3387 23:22:36.651783
3388 23:22:36.651894 Set Vref, RX VrefLevel [Byte0]: 43
3389 23:22:36.655375 [Byte1]: 43
3390 23:22:36.659688
3391 23:22:36.659769 Set Vref, RX VrefLevel [Byte0]: 44
3392 23:22:36.662919 [Byte1]: 44
3393 23:22:36.667590
3394 23:22:36.667674 Set Vref, RX VrefLevel [Byte0]: 45
3395 23:22:36.670982 [Byte1]: 45
3396 23:22:36.675211
3397 23:22:36.675295 Set Vref, RX VrefLevel [Byte0]: 46
3398 23:22:36.678894 [Byte1]: 46
3399 23:22:36.683355
3400 23:22:36.683473 Set Vref, RX VrefLevel [Byte0]: 47
3401 23:22:36.686501 [Byte1]: 47
3402 23:22:36.691041
3403 23:22:36.691124 Set Vref, RX VrefLevel [Byte0]: 48
3404 23:22:36.694660 [Byte1]: 48
3405 23:22:36.699414
3406 23:22:36.699497 Set Vref, RX VrefLevel [Byte0]: 49
3407 23:22:36.702180 [Byte1]: 49
3408 23:22:36.707193
3409 23:22:36.707301 Set Vref, RX VrefLevel [Byte0]: 50
3410 23:22:36.710442 [Byte1]: 50
3411 23:22:36.715096
3412 23:22:36.715177 Set Vref, RX VrefLevel [Byte0]: 51
3413 23:22:36.718017 [Byte1]: 51
3414 23:22:36.722420
3415 23:22:36.722529 Set Vref, RX VrefLevel [Byte0]: 52
3416 23:22:36.725686 [Byte1]: 52
3417 23:22:36.730859
3418 23:22:36.730941 Set Vref, RX VrefLevel [Byte0]: 53
3419 23:22:36.733657 [Byte1]: 53
3420 23:22:36.738807
3421 23:22:36.738925 Set Vref, RX VrefLevel [Byte0]: 54
3422 23:22:36.742078 [Byte1]: 54
3423 23:22:36.746277
3424 23:22:36.746362 Set Vref, RX VrefLevel [Byte0]: 55
3425 23:22:36.749609 [Byte1]: 55
3426 23:22:36.754442
3427 23:22:36.754531 Set Vref, RX VrefLevel [Byte0]: 56
3428 23:22:36.757435 [Byte1]: 56
3429 23:22:36.762562
3430 23:22:36.762649 Set Vref, RX VrefLevel [Byte0]: 57
3431 23:22:36.765256 [Byte1]: 57
3432 23:22:36.770140
3433 23:22:36.770233 Set Vref, RX VrefLevel [Byte0]: 58
3434 23:22:36.773361 [Byte1]: 58
3435 23:22:36.777673
3436 23:22:36.777772 Set Vref, RX VrefLevel [Byte0]: 59
3437 23:22:36.781034 [Byte1]: 59
3438 23:22:36.785549
3439 23:22:36.785633 Set Vref, RX VrefLevel [Byte0]: 60
3440 23:22:36.789065 [Byte1]: 60
3441 23:22:36.793594
3442 23:22:36.793677 Set Vref, RX VrefLevel [Byte0]: 61
3443 23:22:36.797057 [Byte1]: 61
3444 23:22:36.801341
3445 23:22:36.801424 Set Vref, RX VrefLevel [Byte0]: 62
3446 23:22:36.804725 [Byte1]: 62
3447 23:22:36.809243
3448 23:22:36.809327 Set Vref, RX VrefLevel [Byte0]: 63
3449 23:22:36.812814 [Byte1]: 63
3450 23:22:36.817082
3451 23:22:36.817163 Set Vref, RX VrefLevel [Byte0]: 64
3452 23:22:36.820526 [Byte1]: 64
3453 23:22:36.824811
3454 23:22:36.824897 Final RX Vref Byte 0 = 51 to rank0
3455 23:22:36.828065 Final RX Vref Byte 1 = 53 to rank0
3456 23:22:36.831587 Final RX Vref Byte 0 = 51 to rank1
3457 23:22:36.834918 Final RX Vref Byte 1 = 53 to rank1==
3458 23:22:36.838274 Dram Type= 6, Freq= 0, CH_1, rank 0
3459 23:22:36.844937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 23:22:36.845022 ==
3461 23:22:36.845107 DQS Delay:
3462 23:22:36.845171 DQS0 = 0, DQS1 = 0
3463 23:22:36.848352 DQM Delay:
3464 23:22:36.848436 DQM0 = 114, DQM1 = 113
3465 23:22:36.851743 DQ Delay:
3466 23:22:36.854645 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3467 23:22:36.858172 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3468 23:22:36.861642 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3469 23:22:36.865176 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3470 23:22:36.865265
3471 23:22:36.865331
3472 23:22:36.874601 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
3473 23:22:36.874706 CH1 RK0: MR19=303, MR18=F1FE
3474 23:22:36.881527 CH1_RK0: MR19=0x303, MR18=0xF1FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3475 23:22:36.881637
3476 23:22:36.884856 ----->DramcWriteLeveling(PI) begin...
3477 23:22:36.884980 ==
3478 23:22:36.887716 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 23:22:36.895175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 23:22:36.895295 ==
3481 23:22:36.898033 Write leveling (Byte 0): 26 => 26
3482 23:22:36.901045 Write leveling (Byte 1): 31 => 31
3483 23:22:36.901152 DramcWriteLeveling(PI) end<-----
3484 23:22:36.901263
3485 23:22:36.905065 ==
3486 23:22:36.908356 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 23:22:36.911048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 23:22:36.911156 ==
3489 23:22:36.914548 [Gating] SW mode calibration
3490 23:22:36.920986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3491 23:22:36.924258 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3492 23:22:36.931099 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 23:22:36.934220 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 23:22:36.937793 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 23:22:36.944304 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 23:22:36.947817 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 23:22:36.950940 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3498 23:22:36.957953 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
3499 23:22:36.961053 0 15 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
3500 23:22:36.964400 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 23:22:36.971457 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 23:22:36.974438 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 23:22:36.978114 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 23:22:36.984445 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 23:22:36.987560 1 0 20 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
3506 23:22:36.991271 1 0 24 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
3507 23:22:36.997798 1 0 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3508 23:22:37.000522 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 23:22:37.004211 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 23:22:37.010982 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 23:22:37.014196 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 23:22:37.017049 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 23:22:37.023604 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 23:22:37.027510 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3515 23:22:37.030457 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3516 23:22:37.037024 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 23:22:37.040578 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 23:22:37.043541 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 23:22:37.050335 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 23:22:37.053950 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 23:22:37.057052 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 23:22:37.063578 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 23:22:37.066597 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 23:22:37.069832 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 23:22:37.076438 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 23:22:37.079634 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 23:22:37.082983 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 23:22:37.089642 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 23:22:37.092850 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3530 23:22:37.096269 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3531 23:22:37.103049 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3532 23:22:37.103141 Total UI for P1: 0, mck2ui 16
3533 23:22:37.106027 best dqsien dly found for B0: ( 1, 3, 22)
3534 23:22:37.112943 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 23:22:37.116292 Total UI for P1: 0, mck2ui 16
3536 23:22:37.119225 best dqsien dly found for B1: ( 1, 3, 28)
3537 23:22:37.122408 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3538 23:22:37.126154 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3539 23:22:37.126293
3540 23:22:37.129155 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3541 23:22:37.132815 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3542 23:22:37.135646 [Gating] SW calibration Done
3543 23:22:37.135762 ==
3544 23:22:37.139254 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 23:22:37.142384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 23:22:37.145733 ==
3547 23:22:37.145819 RX Vref Scan: 0
3548 23:22:37.145885
3549 23:22:37.149093 RX Vref 0 -> 0, step: 1
3550 23:22:37.149176
3551 23:22:37.152282 RX Delay -40 -> 252, step: 8
3552 23:22:37.155376 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3553 23:22:37.158689 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3554 23:22:37.162026 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3555 23:22:37.165441 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3556 23:22:37.172097 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3557 23:22:37.175656 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3558 23:22:37.178716 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3559 23:22:37.182261 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3560 23:22:37.185184 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3561 23:22:37.191825 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3562 23:22:37.195180 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3563 23:22:37.198129 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3564 23:22:37.201325 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3565 23:22:37.208038 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3566 23:22:37.211499 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3567 23:22:37.214665 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3568 23:22:37.214749 ==
3569 23:22:37.218079 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 23:22:37.221087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 23:22:37.221171 ==
3572 23:22:37.224372 DQS Delay:
3573 23:22:37.224480 DQS0 = 0, DQS1 = 0
3574 23:22:37.228110 DQM Delay:
3575 23:22:37.228199 DQM0 = 114, DQM1 = 111
3576 23:22:37.228265 DQ Delay:
3577 23:22:37.234732 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3578 23:22:37.237994 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3579 23:22:37.241325 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3580 23:22:37.244804 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3581 23:22:37.244886
3582 23:22:37.244950
3583 23:22:37.245011 ==
3584 23:22:37.247659 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 23:22:37.250702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 23:22:37.250821 ==
3587 23:22:37.250914
3588 23:22:37.251001
3589 23:22:37.254218 TX Vref Scan disable
3590 23:22:37.257394 == TX Byte 0 ==
3591 23:22:37.260877 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3592 23:22:37.264203 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3593 23:22:37.267748 == TX Byte 1 ==
3594 23:22:37.270837 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3595 23:22:37.273678 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3596 23:22:37.273784 ==
3597 23:22:37.276907 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 23:22:37.283781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 23:22:37.283876 ==
3600 23:22:37.294365 TX Vref=22, minBit 1, minWin=25, winSum=412
3601 23:22:37.297538 TX Vref=24, minBit 15, minWin=25, winSum=422
3602 23:22:37.300904 TX Vref=26, minBit 1, minWin=26, winSum=422
3603 23:22:37.304408 TX Vref=28, minBit 10, minWin=25, winSum=423
3604 23:22:37.307686 TX Vref=30, minBit 13, minWin=25, winSum=424
3605 23:22:37.313830 TX Vref=32, minBit 14, minWin=25, winSum=426
3606 23:22:37.317033 [TxChooseVref] Worse bit 1, Min win 26, Win sum 422, Final Vref 26
3607 23:22:37.320271
3608 23:22:37.320357 Final TX Range 1 Vref 26
3609 23:22:37.320440
3610 23:22:37.320522 ==
3611 23:22:37.324262 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 23:22:37.330471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 23:22:37.330577 ==
3614 23:22:37.330678
3615 23:22:37.330776
3616 23:22:37.330873 TX Vref Scan disable
3617 23:22:37.334165 == TX Byte 0 ==
3618 23:22:37.337628 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3619 23:22:37.344027 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3620 23:22:37.344133 == TX Byte 1 ==
3621 23:22:37.347305 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3622 23:22:37.354021 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3623 23:22:37.354130
3624 23:22:37.354232 [DATLAT]
3625 23:22:37.354335 Freq=1200, CH1 RK1
3626 23:22:37.354420
3627 23:22:37.357306 DATLAT Default: 0xd
3628 23:22:37.361080 0, 0xFFFF, sum = 0
3629 23:22:37.361187 1, 0xFFFF, sum = 0
3630 23:22:37.363715 2, 0xFFFF, sum = 0
3631 23:22:37.363820 3, 0xFFFF, sum = 0
3632 23:22:37.366908 4, 0xFFFF, sum = 0
3633 23:22:37.367014 5, 0xFFFF, sum = 0
3634 23:22:37.370937 6, 0xFFFF, sum = 0
3635 23:22:37.371041 7, 0xFFFF, sum = 0
3636 23:22:37.373743 8, 0xFFFF, sum = 0
3637 23:22:37.373847 9, 0xFFFF, sum = 0
3638 23:22:37.376911 10, 0xFFFF, sum = 0
3639 23:22:37.377018 11, 0xFFFF, sum = 0
3640 23:22:37.380284 12, 0x0, sum = 1
3641 23:22:37.380390 13, 0x0, sum = 2
3642 23:22:37.383689 14, 0x0, sum = 3
3643 23:22:37.383794 15, 0x0, sum = 4
3644 23:22:37.387025 best_step = 13
3645 23:22:37.387125
3646 23:22:37.387225 ==
3647 23:22:37.390374 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 23:22:37.393290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 23:22:37.393397 ==
3650 23:22:37.396745 RX Vref Scan: 0
3651 23:22:37.396846
3652 23:22:37.396945 RX Vref 0 -> 0, step: 1
3653 23:22:37.397046
3654 23:22:37.399725 RX Delay -13 -> 252, step: 4
3655 23:22:37.406746 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3656 23:22:37.410024 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3657 23:22:37.413187 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3658 23:22:37.416716 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3659 23:22:37.419609 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3660 23:22:37.426472 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3661 23:22:37.429974 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3662 23:22:37.432944 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3663 23:22:37.436539 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3664 23:22:37.443136 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3665 23:22:37.446095 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3666 23:22:37.449291 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3667 23:22:37.452599 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3668 23:22:37.455818 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3669 23:22:37.462437 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3670 23:22:37.466083 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3671 23:22:37.466187 ==
3672 23:22:37.468842 Dram Type= 6, Freq= 0, CH_1, rank 1
3673 23:22:37.472183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3674 23:22:37.472291 ==
3675 23:22:37.475779 DQS Delay:
3676 23:22:37.475891 DQS0 = 0, DQS1 = 0
3677 23:22:37.478703 DQM Delay:
3678 23:22:37.478784 DQM0 = 115, DQM1 = 112
3679 23:22:37.478847 DQ Delay:
3680 23:22:37.482634 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =112
3681 23:22:37.488623 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3682 23:22:37.491886 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3683 23:22:37.495567 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3684 23:22:37.495652
3685 23:22:37.495716
3686 23:22:37.501776 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3687 23:22:37.505400 CH1 RK1: MR19=304, MR18=F90C
3688 23:22:37.511997 CH1_RK1: MR19=0x304, MR18=0xF90C, DQSOSC=405, MR23=63, INC=39, DEC=26
3689 23:22:37.515111 [RxdqsGatingPostProcess] freq 1200
3690 23:22:37.521504 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3691 23:22:37.525225 best DQS0 dly(2T, 0.5T) = (0, 11)
3692 23:22:37.528126 best DQS1 dly(2T, 0.5T) = (0, 11)
3693 23:22:37.528210 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3694 23:22:37.531451 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3695 23:22:37.534782 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 23:22:37.538447 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 23:22:37.541860 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 23:22:37.544788 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 23:22:37.548236 Pre-setting of DQS Precalculation
3700 23:22:37.554954 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3701 23:22:37.561095 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3702 23:22:37.567709 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3703 23:22:37.567837
3704 23:22:37.567953
3705 23:22:37.571015 [Calibration Summary] 2400 Mbps
3706 23:22:37.571141 CH 0, Rank 0
3707 23:22:37.574180 SW Impedance : PASS
3708 23:22:37.577541 DUTY Scan : NO K
3709 23:22:37.577666 ZQ Calibration : PASS
3710 23:22:37.580835 Jitter Meter : NO K
3711 23:22:37.583998 CBT Training : PASS
3712 23:22:37.584124 Write leveling : PASS
3713 23:22:37.587773 RX DQS gating : PASS
3714 23:22:37.590569 RX DQ/DQS(RDDQC) : PASS
3715 23:22:37.590693 TX DQ/DQS : PASS
3716 23:22:37.594361 RX DATLAT : PASS
3717 23:22:37.597259 RX DQ/DQS(Engine): PASS
3718 23:22:37.597360 TX OE : NO K
3719 23:22:37.600884 All Pass.
3720 23:22:37.600967
3721 23:22:37.601031 CH 0, Rank 1
3722 23:22:37.604021 SW Impedance : PASS
3723 23:22:37.604105 DUTY Scan : NO K
3724 23:22:37.607511 ZQ Calibration : PASS
3725 23:22:37.610645 Jitter Meter : NO K
3726 23:22:37.610728 CBT Training : PASS
3727 23:22:37.613851 Write leveling : PASS
3728 23:22:37.617616 RX DQS gating : PASS
3729 23:22:37.617700 RX DQ/DQS(RDDQC) : PASS
3730 23:22:37.620770 TX DQ/DQS : PASS
3731 23:22:37.623986 RX DATLAT : PASS
3732 23:22:37.624103 RX DQ/DQS(Engine): PASS
3733 23:22:37.627275 TX OE : NO K
3734 23:22:37.627390 All Pass.
3735 23:22:37.627458
3736 23:22:37.630829 CH 1, Rank 0
3737 23:22:37.630912 SW Impedance : PASS
3738 23:22:37.633750 DUTY Scan : NO K
3739 23:22:37.636953 ZQ Calibration : PASS
3740 23:22:37.637036 Jitter Meter : NO K
3741 23:22:37.640127 CBT Training : PASS
3742 23:22:37.640210 Write leveling : PASS
3743 23:22:37.643509 RX DQS gating : PASS
3744 23:22:37.647002 RX DQ/DQS(RDDQC) : PASS
3745 23:22:37.647085 TX DQ/DQS : PASS
3746 23:22:37.650376 RX DATLAT : PASS
3747 23:22:37.653427 RX DQ/DQS(Engine): PASS
3748 23:22:37.653510 TX OE : NO K
3749 23:22:37.656922 All Pass.
3750 23:22:37.657004
3751 23:22:37.657069 CH 1, Rank 1
3752 23:22:37.660050 SW Impedance : PASS
3753 23:22:37.660132 DUTY Scan : NO K
3754 23:22:37.663585 ZQ Calibration : PASS
3755 23:22:37.666429 Jitter Meter : NO K
3756 23:22:37.666512 CBT Training : PASS
3757 23:22:37.669931 Write leveling : PASS
3758 23:22:37.673006 RX DQS gating : PASS
3759 23:22:37.673088 RX DQ/DQS(RDDQC) : PASS
3760 23:22:37.676388 TX DQ/DQS : PASS
3761 23:22:37.679554 RX DATLAT : PASS
3762 23:22:37.679636 RX DQ/DQS(Engine): PASS
3763 23:22:37.682872 TX OE : NO K
3764 23:22:37.682955 All Pass.
3765 23:22:37.683020
3766 23:22:37.686624 DramC Write-DBI off
3767 23:22:37.689912 PER_BANK_REFRESH: Hybrid Mode
3768 23:22:37.689996 TX_TRACKING: ON
3769 23:22:37.699512 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3770 23:22:37.702657 [FAST_K] Save calibration result to emmc
3771 23:22:37.706122 dramc_set_vcore_voltage set vcore to 650000
3772 23:22:37.709301 Read voltage for 600, 5
3773 23:22:37.709396 Vio18 = 0
3774 23:22:37.709460 Vcore = 650000
3775 23:22:37.712645 Vdram = 0
3776 23:22:37.712727 Vddq = 0
3777 23:22:37.712822 Vmddr = 0
3778 23:22:37.719513 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3779 23:22:37.722601 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3780 23:22:37.726178 MEM_TYPE=3, freq_sel=19
3781 23:22:37.729071 sv_algorithm_assistance_LP4_1600
3782 23:22:37.732598 ============ PULL DRAM RESETB DOWN ============
3783 23:22:37.738828 ========== PULL DRAM RESETB DOWN end =========
3784 23:22:37.742391 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3785 23:22:37.745927 ===================================
3786 23:22:37.748921 LPDDR4 DRAM CONFIGURATION
3787 23:22:37.752026 ===================================
3788 23:22:37.752173 EX_ROW_EN[0] = 0x0
3789 23:22:37.755302 EX_ROW_EN[1] = 0x0
3790 23:22:37.755409 LP4Y_EN = 0x0
3791 23:22:37.758664 WORK_FSP = 0x0
3792 23:22:37.758745 WL = 0x2
3793 23:22:37.761857 RL = 0x2
3794 23:22:37.765253 BL = 0x2
3795 23:22:37.765334 RPST = 0x0
3796 23:22:37.768404 RD_PRE = 0x0
3797 23:22:37.768485 WR_PRE = 0x1
3798 23:22:37.772169 WR_PST = 0x0
3799 23:22:37.772254 DBI_WR = 0x0
3800 23:22:37.774981 DBI_RD = 0x0
3801 23:22:37.775061 OTF = 0x1
3802 23:22:37.778293 ===================================
3803 23:22:37.781712 ===================================
3804 23:22:37.785036 ANA top config
3805 23:22:37.788575 ===================================
3806 23:22:37.788661 DLL_ASYNC_EN = 0
3807 23:22:37.791480 ALL_SLAVE_EN = 1
3808 23:22:37.794663 NEW_RANK_MODE = 1
3809 23:22:37.798168 DLL_IDLE_MODE = 1
3810 23:22:37.801536 LP45_APHY_COMB_EN = 1
3811 23:22:37.801632 TX_ODT_DIS = 1
3812 23:22:37.804505 NEW_8X_MODE = 1
3813 23:22:37.807872 ===================================
3814 23:22:37.811484 ===================================
3815 23:22:37.814913 data_rate = 1200
3816 23:22:37.818068 CKR = 1
3817 23:22:37.821001 DQ_P2S_RATIO = 8
3818 23:22:37.824497 ===================================
3819 23:22:37.827628 CA_P2S_RATIO = 8
3820 23:22:37.827711 DQ_CA_OPEN = 0
3821 23:22:37.831020 DQ_SEMI_OPEN = 0
3822 23:22:37.834389 CA_SEMI_OPEN = 0
3823 23:22:37.837476 CA_FULL_RATE = 0
3824 23:22:37.840851 DQ_CKDIV4_EN = 1
3825 23:22:37.844221 CA_CKDIV4_EN = 1
3826 23:22:37.844304 CA_PREDIV_EN = 0
3827 23:22:37.847607 PH8_DLY = 0
3828 23:22:37.850490 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3829 23:22:37.853871 DQ_AAMCK_DIV = 4
3830 23:22:37.857088 CA_AAMCK_DIV = 4
3831 23:22:37.860557 CA_ADMCK_DIV = 4
3832 23:22:37.860660 DQ_TRACK_CA_EN = 0
3833 23:22:37.863788 CA_PICK = 600
3834 23:22:37.867345 CA_MCKIO = 600
3835 23:22:37.870486 MCKIO_SEMI = 0
3836 23:22:37.873633 PLL_FREQ = 2288
3837 23:22:37.877343 DQ_UI_PI_RATIO = 32
3838 23:22:37.880108 CA_UI_PI_RATIO = 0
3839 23:22:37.883718 ===================================
3840 23:22:37.887240 ===================================
3841 23:22:37.887372 memory_type:LPDDR4
3842 23:22:37.890342 GP_NUM : 10
3843 23:22:37.893288 SRAM_EN : 1
3844 23:22:37.893394 MD32_EN : 0
3845 23:22:37.897108 ===================================
3846 23:22:37.900188 [ANA_INIT] >>>>>>>>>>>>>>
3847 23:22:37.903594 <<<<<< [CONFIGURE PHASE]: ANA_TX
3848 23:22:37.906942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3849 23:22:37.909910 ===================================
3850 23:22:37.913060 data_rate = 1200,PCW = 0X5800
3851 23:22:37.916452 ===================================
3852 23:22:37.919761 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3853 23:22:37.923068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 23:22:37.930052 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3855 23:22:37.933472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3856 23:22:37.939582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3857 23:22:37.943038 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3858 23:22:37.943132 [ANA_INIT] flow start
3859 23:22:37.946301 [ANA_INIT] PLL >>>>>>>>
3860 23:22:37.949875 [ANA_INIT] PLL <<<<<<<<
3861 23:22:37.949949 [ANA_INIT] MIDPI >>>>>>>>
3862 23:22:37.952716 [ANA_INIT] MIDPI <<<<<<<<
3863 23:22:37.956111 [ANA_INIT] DLL >>>>>>>>
3864 23:22:37.956192 [ANA_INIT] flow end
3865 23:22:37.962414 ============ LP4 DIFF to SE enter ============
3866 23:22:37.965820 ============ LP4 DIFF to SE exit ============
3867 23:22:37.965922 [ANA_INIT] <<<<<<<<<<<<<
3868 23:22:37.969295 [Flow] Enable top DCM control >>>>>
3869 23:22:37.972442 [Flow] Enable top DCM control <<<<<
3870 23:22:37.975691 Enable DLL master slave shuffle
3871 23:22:37.982442 ==============================================================
3872 23:22:37.985764 Gating Mode config
3873 23:22:37.989560 ==============================================================
3874 23:22:37.992447 Config description:
3875 23:22:38.002015 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3876 23:22:38.008611 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3877 23:22:38.012500 SELPH_MODE 0: By rank 1: By Phase
3878 23:22:38.018895 ==============================================================
3879 23:22:38.022059 GAT_TRACK_EN = 1
3880 23:22:38.025002 RX_GATING_MODE = 2
3881 23:22:38.028627 RX_GATING_TRACK_MODE = 2
3882 23:22:38.031904 SELPH_MODE = 1
3883 23:22:38.035235 PICG_EARLY_EN = 1
3884 23:22:38.035340 VALID_LAT_VALUE = 1
3885 23:22:38.041534 ==============================================================
3886 23:22:38.045085 Enter into Gating configuration >>>>
3887 23:22:38.048364 Exit from Gating configuration <<<<
3888 23:22:38.051285 Enter into DVFS_PRE_config >>>>>
3889 23:22:38.061579 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3890 23:22:38.064815 Exit from DVFS_PRE_config <<<<<
3891 23:22:38.067932 Enter into PICG configuration >>>>
3892 23:22:38.071314 Exit from PICG configuration <<<<
3893 23:22:38.074596 [RX_INPUT] configuration >>>>>
3894 23:22:38.078207 [RX_INPUT] configuration <<<<<
3895 23:22:38.084496 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3896 23:22:38.088213 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3897 23:22:38.094616 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 23:22:38.101155 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 23:22:38.107381 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 23:22:38.114228 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 23:22:38.117620 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3902 23:22:38.120682 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3903 23:22:38.124254 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3904 23:22:38.130421 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3905 23:22:38.134154 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3906 23:22:38.137472 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3907 23:22:38.140452 ===================================
3908 23:22:38.143703 LPDDR4 DRAM CONFIGURATION
3909 23:22:38.147079 ===================================
3910 23:22:38.150147 EX_ROW_EN[0] = 0x0
3911 23:22:38.150227 EX_ROW_EN[1] = 0x0
3912 23:22:38.153531 LP4Y_EN = 0x0
3913 23:22:38.153633 WORK_FSP = 0x0
3914 23:22:38.157404 WL = 0x2
3915 23:22:38.157483 RL = 0x2
3916 23:22:38.160095 BL = 0x2
3917 23:22:38.160169 RPST = 0x0
3918 23:22:38.163910 RD_PRE = 0x0
3919 23:22:38.163983 WR_PRE = 0x1
3920 23:22:38.166964 WR_PST = 0x0
3921 23:22:38.167039 DBI_WR = 0x0
3922 23:22:38.170334 DBI_RD = 0x0
3923 23:22:38.170411 OTF = 0x1
3924 23:22:38.173889 ===================================
3925 23:22:38.180114 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3926 23:22:38.183198 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3927 23:22:38.186549 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3928 23:22:38.190137 ===================================
3929 23:22:38.193352 LPDDR4 DRAM CONFIGURATION
3930 23:22:38.196506 ===================================
3931 23:22:38.200008 EX_ROW_EN[0] = 0x10
3932 23:22:38.200087 EX_ROW_EN[1] = 0x0
3933 23:22:38.202906 LP4Y_EN = 0x0
3934 23:22:38.202982 WORK_FSP = 0x0
3935 23:22:38.206613 WL = 0x2
3936 23:22:38.206686 RL = 0x2
3937 23:22:38.210048 BL = 0x2
3938 23:22:38.210130 RPST = 0x0
3939 23:22:38.212892 RD_PRE = 0x0
3940 23:22:38.212981 WR_PRE = 0x1
3941 23:22:38.216321 WR_PST = 0x0
3942 23:22:38.216397 DBI_WR = 0x0
3943 23:22:38.220106 DBI_RD = 0x0
3944 23:22:38.220180 OTF = 0x1
3945 23:22:38.223098 ===================================
3946 23:22:38.229616 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3947 23:22:38.234627 nWR fixed to 30
3948 23:22:38.237540 [ModeRegInit_LP4] CH0 RK0
3949 23:22:38.237614 [ModeRegInit_LP4] CH0 RK1
3950 23:22:38.240922 [ModeRegInit_LP4] CH1 RK0
3951 23:22:38.244208 [ModeRegInit_LP4] CH1 RK1
3952 23:22:38.244292 match AC timing 17
3953 23:22:38.251067 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3954 23:22:38.254271 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3955 23:22:38.257646 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3956 23:22:38.263842 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3957 23:22:38.267076 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3958 23:22:38.267189 ==
3959 23:22:38.270437 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 23:22:38.273684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 23:22:38.277171 ==
3962 23:22:38.280364 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 23:22:38.286703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3964 23:22:38.290461 [CA 0] Center 36 (6~67) winsize 62
3965 23:22:38.293505 [CA 1] Center 36 (6~67) winsize 62
3966 23:22:38.296971 [CA 2] Center 34 (4~65) winsize 62
3967 23:22:38.299904 [CA 3] Center 34 (4~65) winsize 62
3968 23:22:38.303728 [CA 4] Center 33 (3~64) winsize 62
3969 23:22:38.306592 [CA 5] Center 33 (3~64) winsize 62
3970 23:22:38.306668
3971 23:22:38.310182 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3972 23:22:38.310271
3973 23:22:38.313016 [CATrainingPosCal] consider 1 rank data
3974 23:22:38.316893 u2DelayCellTimex100 = 270/100 ps
3975 23:22:38.319690 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3976 23:22:38.323465 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3977 23:22:38.329461 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3978 23:22:38.333041 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3979 23:22:38.335977 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3980 23:22:38.339925 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 23:22:38.340004
3982 23:22:38.343100 CA PerBit enable=1, Macro0, CA PI delay=33
3983 23:22:38.343229
3984 23:22:38.346203 [CBTSetCACLKResult] CA Dly = 33
3985 23:22:38.346302 CS Dly: 6 (0~37)
3986 23:22:38.349707 ==
3987 23:22:38.353275 Dram Type= 6, Freq= 0, CH_0, rank 1
3988 23:22:38.355954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 23:22:38.356061 ==
3990 23:22:38.359189 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3991 23:22:38.365689 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3992 23:22:38.370170 [CA 0] Center 36 (6~67) winsize 62
3993 23:22:38.373256 [CA 1] Center 36 (6~67) winsize 62
3994 23:22:38.376111 [CA 2] Center 34 (4~65) winsize 62
3995 23:22:38.379543 [CA 3] Center 34 (4~65) winsize 62
3996 23:22:38.383033 [CA 4] Center 34 (3~65) winsize 63
3997 23:22:38.385988 [CA 5] Center 33 (3~64) winsize 62
3998 23:22:38.386066
3999 23:22:38.389720 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4000 23:22:38.389796
4001 23:22:38.393283 [CATrainingPosCal] consider 2 rank data
4002 23:22:38.395966 u2DelayCellTimex100 = 270/100 ps
4003 23:22:38.399173 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4004 23:22:38.405990 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4005 23:22:38.409181 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4006 23:22:38.412528 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4007 23:22:38.415665 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 23:22:38.419286 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4009 23:22:38.419369
4010 23:22:38.422773 CA PerBit enable=1, Macro0, CA PI delay=33
4011 23:22:38.422858
4012 23:22:38.426047 [CBTSetCACLKResult] CA Dly = 33
4013 23:22:38.429383 CS Dly: 6 (0~37)
4014 23:22:38.429472
4015 23:22:38.432753 ----->DramcWriteLeveling(PI) begin...
4016 23:22:38.432843 ==
4017 23:22:38.435627 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 23:22:38.439274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 23:22:38.439400 ==
4020 23:22:38.442193 Write leveling (Byte 0): 33 => 33
4021 23:22:38.445694 Write leveling (Byte 1): 31 => 31
4022 23:22:38.449048 DramcWriteLeveling(PI) end<-----
4023 23:22:38.449133
4024 23:22:38.449204 ==
4025 23:22:38.452143 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 23:22:38.455431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 23:22:38.455505 ==
4028 23:22:38.459074 [Gating] SW mode calibration
4029 23:22:38.465540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4030 23:22:38.472017 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4031 23:22:38.475183 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 23:22:38.478529 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 23:22:38.485370 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 23:22:38.488299 0 9 12 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
4035 23:22:38.491557 0 9 16 | B1->B0 | 2f2f 2929 | 0 0 | (1 1) (0 0)
4036 23:22:38.498501 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 23:22:38.501724 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 23:22:38.504757 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 23:22:38.511493 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 23:22:38.514723 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 23:22:38.517943 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 23:22:38.524495 0 10 12 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
4043 23:22:38.527701 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4044 23:22:38.531199 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 23:22:38.537741 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 23:22:38.540686 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 23:22:38.547490 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 23:22:38.550690 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 23:22:38.554078 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 23:22:38.560910 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 23:22:38.563645 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4052 23:22:38.566996 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4053 23:22:38.573794 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 23:22:38.576846 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 23:22:38.580414 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 23:22:38.587116 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 23:22:38.589866 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 23:22:38.593236 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 23:22:38.599947 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 23:22:38.603281 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 23:22:38.606550 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 23:22:38.613188 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 23:22:38.616301 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 23:22:38.619553 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 23:22:38.626144 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 23:22:38.629667 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4067 23:22:38.632700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 23:22:38.635838 Total UI for P1: 0, mck2ui 16
4069 23:22:38.639186 best dqsien dly found for B0: ( 0, 13, 12)
4070 23:22:38.642452 Total UI for P1: 0, mck2ui 16
4071 23:22:38.645874 best dqsien dly found for B1: ( 0, 13, 14)
4072 23:22:38.649351 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4073 23:22:38.652550 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4074 23:22:38.652624
4075 23:22:38.658968 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4076 23:22:38.662484 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4077 23:22:38.665525 [Gating] SW calibration Done
4078 23:22:38.665607 ==
4079 23:22:38.668825 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 23:22:38.672240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 23:22:38.672324 ==
4082 23:22:38.672388 RX Vref Scan: 0
4083 23:22:38.675529
4084 23:22:38.675610 RX Vref 0 -> 0, step: 1
4085 23:22:38.675674
4086 23:22:38.678865 RX Delay -230 -> 252, step: 16
4087 23:22:38.682315 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4088 23:22:38.688849 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4089 23:22:38.692276 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4090 23:22:38.695126 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4091 23:22:38.698392 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4092 23:22:38.704820 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4093 23:22:38.708618 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4094 23:22:38.711623 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4095 23:22:38.715026 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4096 23:22:38.718071 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4097 23:22:38.724988 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4098 23:22:38.728157 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4099 23:22:38.731703 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4100 23:22:38.734656 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4101 23:22:38.741472 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4102 23:22:38.745022 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4103 23:22:38.745144 ==
4104 23:22:38.748146 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 23:22:38.751478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 23:22:38.751599 ==
4107 23:22:38.754703 DQS Delay:
4108 23:22:38.754824 DQS0 = 0, DQS1 = 0
4109 23:22:38.758013 DQM Delay:
4110 23:22:38.758129 DQM0 = 43, DQM1 = 34
4111 23:22:38.758237 DQ Delay:
4112 23:22:38.761156 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4113 23:22:38.764687 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4114 23:22:38.768047 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4115 23:22:38.771479 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4116 23:22:38.771557
4117 23:22:38.771620
4118 23:22:38.774192 ==
4119 23:22:38.774275 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 23:22:38.780972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 23:22:38.781056 ==
4122 23:22:38.781121
4123 23:22:38.781180
4124 23:22:38.784048 TX Vref Scan disable
4125 23:22:38.784133 == TX Byte 0 ==
4126 23:22:38.790828 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4127 23:22:38.793783 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4128 23:22:38.793867 == TX Byte 1 ==
4129 23:22:38.800477 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4130 23:22:38.803696 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4131 23:22:38.803778 ==
4132 23:22:38.807034 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 23:22:38.810440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 23:22:38.810523 ==
4135 23:22:38.810587
4136 23:22:38.810646
4137 23:22:38.813589 TX Vref Scan disable
4138 23:22:38.817097 == TX Byte 0 ==
4139 23:22:38.820432 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4140 23:22:38.823617 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4141 23:22:38.826804 == TX Byte 1 ==
4142 23:22:38.830375 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4143 23:22:38.833581 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4144 23:22:38.836962
4145 23:22:38.837039 [DATLAT]
4146 23:22:38.837102 Freq=600, CH0 RK0
4147 23:22:38.837160
4148 23:22:38.840393 DATLAT Default: 0x9
4149 23:22:38.840474 0, 0xFFFF, sum = 0
4150 23:22:38.843651 1, 0xFFFF, sum = 0
4151 23:22:38.843734 2, 0xFFFF, sum = 0
4152 23:22:38.846649 3, 0xFFFF, sum = 0
4153 23:22:38.850012 4, 0xFFFF, sum = 0
4154 23:22:38.850085 5, 0xFFFF, sum = 0
4155 23:22:38.853161 6, 0xFFFF, sum = 0
4156 23:22:38.853265 7, 0xFFFF, sum = 0
4157 23:22:38.856491 8, 0x0, sum = 1
4158 23:22:38.856576 9, 0x0, sum = 2
4159 23:22:38.856662 10, 0x0, sum = 3
4160 23:22:38.860089 11, 0x0, sum = 4
4161 23:22:38.860199 best_step = 9
4162 23:22:38.860291
4163 23:22:38.860377 ==
4164 23:22:38.863414 Dram Type= 6, Freq= 0, CH_0, rank 0
4165 23:22:38.870034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 23:22:38.870126 ==
4167 23:22:38.870192 RX Vref Scan: 1
4168 23:22:38.870254
4169 23:22:38.873306 RX Vref 0 -> 0, step: 1
4170 23:22:38.873436
4171 23:22:38.876450 RX Delay -195 -> 252, step: 8
4172 23:22:38.876574
4173 23:22:38.879882 Set Vref, RX VrefLevel [Byte0]: 53
4174 23:22:38.883172 [Byte1]: 59
4175 23:22:38.883297
4176 23:22:38.886298 Final RX Vref Byte 0 = 53 to rank0
4177 23:22:38.889515 Final RX Vref Byte 1 = 59 to rank0
4178 23:22:38.892770 Final RX Vref Byte 0 = 53 to rank1
4179 23:22:38.896515 Final RX Vref Byte 1 = 59 to rank1==
4180 23:22:38.899679 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 23:22:38.902968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 23:22:38.903077 ==
4183 23:22:38.906119 DQS Delay:
4184 23:22:38.906202 DQS0 = 0, DQS1 = 0
4185 23:22:38.909537 DQM Delay:
4186 23:22:38.909620 DQM0 = 41, DQM1 = 33
4187 23:22:38.909685 DQ Delay:
4188 23:22:38.912686 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4189 23:22:38.915904 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4190 23:22:38.919423 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =32
4191 23:22:38.922574 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4192 23:22:38.922657
4193 23:22:38.922721
4194 23:22:38.932410 [DQSOSCAuto] RK0, (LSB)MR18= 0x453c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4195 23:22:38.935809 CH0 RK0: MR19=808, MR18=453C
4196 23:22:38.942227 CH0_RK0: MR19=0x808, MR18=0x453C, DQSOSC=396, MR23=63, INC=167, DEC=111
4197 23:22:38.942336
4198 23:22:38.945714 ----->DramcWriteLeveling(PI) begin...
4199 23:22:38.945799 ==
4200 23:22:38.948925 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 23:22:38.952203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 23:22:38.952290 ==
4203 23:22:38.955630 Write leveling (Byte 0): 32 => 32
4204 23:22:38.958820 Write leveling (Byte 1): 32 => 32
4205 23:22:38.961868 DramcWriteLeveling(PI) end<-----
4206 23:22:38.961954
4207 23:22:38.962040 ==
4208 23:22:38.965411 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 23:22:38.968410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 23:22:38.968539 ==
4211 23:22:38.972161 [Gating] SW mode calibration
4212 23:22:38.978473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4213 23:22:38.985072 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4214 23:22:38.988361 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 23:22:38.994888 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 23:22:38.998168 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 23:22:39.001901 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
4218 23:22:39.008224 0 9 16 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
4219 23:22:39.011502 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 23:22:39.014914 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 23:22:39.021498 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 23:22:39.024574 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 23:22:39.027724 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 23:22:39.034521 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 23:22:39.037695 0 10 12 | B1->B0 | 2828 3737 | 0 0 | (0 0) (0 0)
4226 23:22:39.040960 0 10 16 | B1->B0 | 3a3a 4545 | 1 0 | (0 0) (0 0)
4227 23:22:39.047473 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 23:22:39.051063 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 23:22:39.054261 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 23:22:39.061088 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 23:22:39.064276 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 23:22:39.067672 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 23:22:39.074074 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4234 23:22:39.077384 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 23:22:39.080574 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 23:22:39.087303 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 23:22:39.090591 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 23:22:39.093713 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 23:22:39.100758 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 23:22:39.103830 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:22:39.107217 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:22:39.113854 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:22:39.117036 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:22:39.120288 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:22:39.126607 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:22:39.129823 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:22:39.133209 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:22:39.139883 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:22:39.143164 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4250 23:22:39.146665 Total UI for P1: 0, mck2ui 16
4251 23:22:39.149751 best dqsien dly found for B0: ( 0, 13, 10)
4252 23:22:39.153259 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 23:22:39.156106 Total UI for P1: 0, mck2ui 16
4254 23:22:39.159461 best dqsien dly found for B1: ( 0, 13, 12)
4255 23:22:39.163352 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4256 23:22:39.166162 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4257 23:22:39.166298
4258 23:22:39.172920 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4259 23:22:39.175808 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4260 23:22:39.179086 [Gating] SW calibration Done
4261 23:22:39.179211 ==
4262 23:22:39.182927 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 23:22:39.185639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 23:22:39.185762 ==
4265 23:22:39.185870 RX Vref Scan: 0
4266 23:22:39.185982
4267 23:22:39.189143 RX Vref 0 -> 0, step: 1
4268 23:22:39.189265
4269 23:22:39.192903 RX Delay -230 -> 252, step: 16
4270 23:22:39.195591 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4271 23:22:39.202544 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4272 23:22:39.205862 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4273 23:22:39.209067 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4274 23:22:39.212087 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4275 23:22:39.215919 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4276 23:22:39.221984 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4277 23:22:39.225650 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4278 23:22:39.228788 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4279 23:22:39.231938 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4280 23:22:39.238709 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4281 23:22:39.242170 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4282 23:22:39.245474 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4283 23:22:39.249032 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4284 23:22:39.255135 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4285 23:22:39.258771 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4286 23:22:39.258892 ==
4287 23:22:39.262048 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 23:22:39.265271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 23:22:39.265397 ==
4290 23:22:39.268568 DQS Delay:
4291 23:22:39.268690 DQS0 = 0, DQS1 = 0
4292 23:22:39.268804 DQM Delay:
4293 23:22:39.271941 DQM0 = 44, DQM1 = 33
4294 23:22:39.272062 DQ Delay:
4295 23:22:39.274940 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4296 23:22:39.278470 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4297 23:22:39.282008 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4298 23:22:39.285117 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4299 23:22:39.285239
4300 23:22:39.285351
4301 23:22:39.285461 ==
4302 23:22:39.288470 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 23:22:39.294471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 23:22:39.294595 ==
4305 23:22:39.294700
4306 23:22:39.294805
4307 23:22:39.297778 TX Vref Scan disable
4308 23:22:39.297899 == TX Byte 0 ==
4309 23:22:39.301653 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4310 23:22:39.307967 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4311 23:22:39.308053 == TX Byte 1 ==
4312 23:22:39.314575 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4313 23:22:39.318052 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4314 23:22:39.318135 ==
4315 23:22:39.321280 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 23:22:39.324310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 23:22:39.324405 ==
4318 23:22:39.324474
4319 23:22:39.324536
4320 23:22:39.327412 TX Vref Scan disable
4321 23:22:39.330639 == TX Byte 0 ==
4322 23:22:39.334126 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4323 23:22:39.337363 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4324 23:22:39.340516 == TX Byte 1 ==
4325 23:22:39.344066 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4326 23:22:39.346997 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4327 23:22:39.347079
4328 23:22:39.350984 [DATLAT]
4329 23:22:39.351058 Freq=600, CH0 RK1
4330 23:22:39.351126
4331 23:22:39.353775 DATLAT Default: 0x9
4332 23:22:39.353854 0, 0xFFFF, sum = 0
4333 23:22:39.356995 1, 0xFFFF, sum = 0
4334 23:22:39.357075 2, 0xFFFF, sum = 0
4335 23:22:39.360301 3, 0xFFFF, sum = 0
4336 23:22:39.360378 4, 0xFFFF, sum = 0
4337 23:22:39.363474 5, 0xFFFF, sum = 0
4338 23:22:39.367070 6, 0xFFFF, sum = 0
4339 23:22:39.367157 7, 0xFFFF, sum = 0
4340 23:22:39.367221 8, 0x0, sum = 1
4341 23:22:39.370209 9, 0x0, sum = 2
4342 23:22:39.370284 10, 0x0, sum = 3
4343 23:22:39.373403 11, 0x0, sum = 4
4344 23:22:39.373482 best_step = 9
4345 23:22:39.373546
4346 23:22:39.373620 ==
4347 23:22:39.376723 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 23:22:39.383273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 23:22:39.383355 ==
4350 23:22:39.383436 RX Vref Scan: 0
4351 23:22:39.383497
4352 23:22:39.386626 RX Vref 0 -> 0, step: 1
4353 23:22:39.386701
4354 23:22:39.390365 RX Delay -195 -> 252, step: 8
4355 23:22:39.393319 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4356 23:22:39.400014 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4357 23:22:39.403615 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4358 23:22:39.407058 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4359 23:22:39.410354 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4360 23:22:39.416758 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4361 23:22:39.419572 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4362 23:22:39.422978 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4363 23:22:39.426550 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4364 23:22:39.429608 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4365 23:22:39.436022 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4366 23:22:39.439239 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4367 23:22:39.442647 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4368 23:22:39.445947 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4369 23:22:39.452961 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4370 23:22:39.456340 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4371 23:22:39.456417 ==
4372 23:22:39.459613 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 23:22:39.462983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 23:22:39.463091 ==
4375 23:22:39.466336 DQS Delay:
4376 23:22:39.466414 DQS0 = 0, DQS1 = 0
4377 23:22:39.469109 DQM Delay:
4378 23:22:39.469185 DQM0 = 41, DQM1 = 34
4379 23:22:39.469248 DQ Delay:
4380 23:22:39.472451 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4381 23:22:39.475826 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4382 23:22:39.479062 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4383 23:22:39.482647 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40
4384 23:22:39.482745
4385 23:22:39.482807
4386 23:22:39.492472 [DQSOSCAuto] RK1, (LSB)MR18= 0x4540, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4387 23:22:39.495838 CH0 RK1: MR19=808, MR18=4540
4388 23:22:39.502242 CH0_RK1: MR19=0x808, MR18=0x4540, DQSOSC=396, MR23=63, INC=167, DEC=111
4389 23:22:39.502335 [RxdqsGatingPostProcess] freq 600
4390 23:22:39.508635 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4391 23:22:39.511892 Pre-setting of DQS Precalculation
4392 23:22:39.515640 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4393 23:22:39.518479 ==
4394 23:22:39.521902 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 23:22:39.525416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 23:22:39.525495 ==
4397 23:22:39.532359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 23:22:39.534949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4399 23:22:39.539290 [CA 0] Center 35 (5~66) winsize 62
4400 23:22:39.542300 [CA 1] Center 35 (5~66) winsize 62
4401 23:22:39.545688 [CA 2] Center 34 (4~65) winsize 62
4402 23:22:39.548918 [CA 3] Center 34 (3~65) winsize 63
4403 23:22:39.552234 [CA 4] Center 34 (4~65) winsize 62
4404 23:22:39.555589 [CA 5] Center 34 (3~65) winsize 63
4405 23:22:39.555669
4406 23:22:39.558931 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4407 23:22:39.559009
4408 23:22:39.562493 [CATrainingPosCal] consider 1 rank data
4409 23:22:39.565601 u2DelayCellTimex100 = 270/100 ps
4410 23:22:39.568536 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4411 23:22:39.575848 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4412 23:22:39.578938 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4413 23:22:39.581935 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4414 23:22:39.585285 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4415 23:22:39.588607 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4416 23:22:39.588677
4417 23:22:39.591990 CA PerBit enable=1, Macro0, CA PI delay=34
4418 23:22:39.592072
4419 23:22:39.595435 [CBTSetCACLKResult] CA Dly = 34
4420 23:22:39.598445 CS Dly: 4 (0~35)
4421 23:22:39.598526 ==
4422 23:22:39.601714 Dram Type= 6, Freq= 0, CH_1, rank 1
4423 23:22:39.604844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 23:22:39.604969 ==
4425 23:22:39.611388 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 23:22:39.614993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4427 23:22:39.619102 [CA 0] Center 35 (5~66) winsize 62
4428 23:22:39.622138 [CA 1] Center 35 (5~66) winsize 62
4429 23:22:39.625861 [CA 2] Center 34 (4~65) winsize 62
4430 23:22:39.629236 [CA 3] Center 33 (3~64) winsize 62
4431 23:22:39.632400 [CA 4] Center 34 (4~65) winsize 62
4432 23:22:39.635285 [CA 5] Center 34 (3~65) winsize 63
4433 23:22:39.635413
4434 23:22:39.638686 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4435 23:22:39.638808
4436 23:22:39.641869 [CATrainingPosCal] consider 2 rank data
4437 23:22:39.645600 u2DelayCellTimex100 = 270/100 ps
4438 23:22:39.648724 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 23:22:39.654879 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 23:22:39.658621 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4441 23:22:39.661766 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4442 23:22:39.664962 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4443 23:22:39.668983 CA5 delay=34 (3~65),Diff = 1 PI (9 cell)
4444 23:22:39.669063
4445 23:22:39.671841 CA PerBit enable=1, Macro0, CA PI delay=33
4446 23:22:39.671918
4447 23:22:39.674680 [CBTSetCACLKResult] CA Dly = 33
4448 23:22:39.678610 CS Dly: 4 (0~35)
4449 23:22:39.678684
4450 23:22:39.681575 ----->DramcWriteLeveling(PI) begin...
4451 23:22:39.681659 ==
4452 23:22:39.684942 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 23:22:39.688131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 23:22:39.688206 ==
4455 23:22:39.691663 Write leveling (Byte 0): 28 => 28
4456 23:22:39.694718 Write leveling (Byte 1): 28 => 28
4457 23:22:39.698070 DramcWriteLeveling(PI) end<-----
4458 23:22:39.698152
4459 23:22:39.698214 ==
4460 23:22:39.701507 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 23:22:39.704290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 23:22:39.704371 ==
4463 23:22:39.708099 [Gating] SW mode calibration
4464 23:22:39.714488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4465 23:22:39.721376 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4466 23:22:39.724443 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 23:22:39.730538 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 23:22:39.734094 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 23:22:39.737398 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (1 1) (0 1)
4470 23:22:39.744235 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 23:22:39.747196 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 23:22:39.750471 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 23:22:39.757009 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 23:22:39.760367 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 23:22:39.763891 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 23:22:39.770019 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 23:22:39.773957 0 10 12 | B1->B0 | 2b2b 3232 | 1 0 | (0 0) (0 0)
4478 23:22:39.776809 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 23:22:39.783492 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 23:22:39.786776 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 23:22:39.790189 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 23:22:39.796812 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 23:22:39.800249 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 23:22:39.803380 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 23:22:39.810159 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4486 23:22:39.813172 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 23:22:39.816530 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 23:22:39.823241 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 23:22:39.826138 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 23:22:39.829266 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 23:22:39.836210 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 23:22:39.839319 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 23:22:39.842981 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 23:22:39.849631 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 23:22:39.852473 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 23:22:39.855601 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 23:22:39.862274 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 23:22:39.865498 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 23:22:39.868901 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 23:22:39.875756 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 23:22:39.878639 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4502 23:22:39.882087 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4503 23:22:39.888720 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 23:22:39.888830 Total UI for P1: 0, mck2ui 16
4505 23:22:39.895153 best dqsien dly found for B0: ( 0, 13, 14)
4506 23:22:39.895259 Total UI for P1: 0, mck2ui 16
4507 23:22:39.901839 best dqsien dly found for B1: ( 0, 13, 14)
4508 23:22:39.905400 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4509 23:22:39.908437 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4510 23:22:39.908526
4511 23:22:39.911985 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4512 23:22:39.915375 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4513 23:22:39.918244 [Gating] SW calibration Done
4514 23:22:39.918368 ==
4515 23:22:39.921417 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 23:22:39.924612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 23:22:39.924709 ==
4518 23:22:39.927879 RX Vref Scan: 0
4519 23:22:39.928010
4520 23:22:39.928107 RX Vref 0 -> 0, step: 1
4521 23:22:39.931173
4522 23:22:39.931276 RX Delay -230 -> 252, step: 16
4523 23:22:39.937938 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4524 23:22:39.941530 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4525 23:22:39.944611 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4526 23:22:39.948007 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4527 23:22:39.954657 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4528 23:22:39.957889 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4529 23:22:39.961046 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4530 23:22:39.964645 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4531 23:22:39.970513 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4532 23:22:39.974285 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4533 23:22:39.977353 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4534 23:22:39.980410 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4535 23:22:39.988031 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4536 23:22:39.990596 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4537 23:22:39.993979 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4538 23:22:39.997108 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4539 23:22:39.997191 ==
4540 23:22:40.000442 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 23:22:40.006834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 23:22:40.006974 ==
4543 23:22:40.007084 DQS Delay:
4544 23:22:40.010052 DQS0 = 0, DQS1 = 0
4545 23:22:40.010176 DQM Delay:
4546 23:22:40.010290 DQM0 = 43, DQM1 = 37
4547 23:22:40.013424 DQ Delay:
4548 23:22:40.016878 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4549 23:22:40.020038 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4550 23:22:40.023444 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4551 23:22:40.026723 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4552 23:22:40.026847
4553 23:22:40.026958
4554 23:22:40.027065 ==
4555 23:22:40.030226 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 23:22:40.033522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 23:22:40.033645 ==
4558 23:22:40.033757
4559 23:22:40.033863
4560 23:22:40.036345 TX Vref Scan disable
4561 23:22:40.039840 == TX Byte 0 ==
4562 23:22:40.043048 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4563 23:22:40.046699 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4564 23:22:40.049754 == TX Byte 1 ==
4565 23:22:40.053196 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4566 23:22:40.056360 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4567 23:22:40.056468 ==
4568 23:22:40.059663 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 23:22:40.066531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 23:22:40.066619 ==
4571 23:22:40.066691
4572 23:22:40.066752
4573 23:22:40.066808 TX Vref Scan disable
4574 23:22:40.070103 == TX Byte 0 ==
4575 23:22:40.073570 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4576 23:22:40.080204 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4577 23:22:40.080290 == TX Byte 1 ==
4578 23:22:40.083504 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4579 23:22:40.090092 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4580 23:22:40.090200
4581 23:22:40.090292 [DATLAT]
4582 23:22:40.090381 Freq=600, CH1 RK0
4583 23:22:40.090470
4584 23:22:40.093350 DATLAT Default: 0x9
4585 23:22:40.093457 0, 0xFFFF, sum = 0
4586 23:22:40.096739 1, 0xFFFF, sum = 0
4587 23:22:40.100117 2, 0xFFFF, sum = 0
4588 23:22:40.100200 3, 0xFFFF, sum = 0
4589 23:22:40.103429 4, 0xFFFF, sum = 0
4590 23:22:40.103537 5, 0xFFFF, sum = 0
4591 23:22:40.106501 6, 0xFFFF, sum = 0
4592 23:22:40.106610 7, 0xFFFF, sum = 0
4593 23:22:40.110014 8, 0x0, sum = 1
4594 23:22:40.110129 9, 0x0, sum = 2
4595 23:22:40.110229 10, 0x0, sum = 3
4596 23:22:40.113557 11, 0x0, sum = 4
4597 23:22:40.113670 best_step = 9
4598 23:22:40.113764
4599 23:22:40.113859 ==
4600 23:22:40.116454 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 23:22:40.123051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 23:22:40.123162 ==
4603 23:22:40.123261 RX Vref Scan: 1
4604 23:22:40.123357
4605 23:22:40.126146 RX Vref 0 -> 0, step: 1
4606 23:22:40.126249
4607 23:22:40.129446 RX Delay -179 -> 252, step: 8
4608 23:22:40.129527
4609 23:22:40.133352 Set Vref, RX VrefLevel [Byte0]: 51
4610 23:22:40.136298 [Byte1]: 53
4611 23:22:40.136380
4612 23:22:40.139643 Final RX Vref Byte 0 = 51 to rank0
4613 23:22:40.142728 Final RX Vref Byte 1 = 53 to rank0
4614 23:22:40.146043 Final RX Vref Byte 0 = 51 to rank1
4615 23:22:40.149327 Final RX Vref Byte 1 = 53 to rank1==
4616 23:22:40.152794 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 23:22:40.156072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 23:22:40.159428 ==
4619 23:22:40.159548 DQS Delay:
4620 23:22:40.159663 DQS0 = 0, DQS1 = 0
4621 23:22:40.162765 DQM Delay:
4622 23:22:40.162888 DQM0 = 42, DQM1 = 33
4623 23:22:40.166282 DQ Delay:
4624 23:22:40.166404 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4625 23:22:40.169232 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4626 23:22:40.172832 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4627 23:22:40.176032 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4628 23:22:40.176150
4629 23:22:40.179279
4630 23:22:40.185846 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4631 23:22:40.189184 CH1 RK0: MR19=808, MR18=2C45
4632 23:22:40.195743 CH1_RK0: MR19=0x808, MR18=0x2C45, DQSOSC=396, MR23=63, INC=167, DEC=111
4633 23:22:40.195874
4634 23:22:40.198775 ----->DramcWriteLeveling(PI) begin...
4635 23:22:40.198902 ==
4636 23:22:40.201948 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 23:22:40.205567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 23:22:40.205691 ==
4639 23:22:40.209121 Write leveling (Byte 0): 32 => 32
4640 23:22:40.211844 Write leveling (Byte 1): 29 => 29
4641 23:22:40.215216 DramcWriteLeveling(PI) end<-----
4642 23:22:40.215338
4643 23:22:40.215458 ==
4644 23:22:40.218958 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 23:22:40.221697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 23:22:40.221820 ==
4647 23:22:40.224917 [Gating] SW mode calibration
4648 23:22:40.231775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4649 23:22:40.238114 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4650 23:22:40.241559 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 23:22:40.248019 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 23:22:40.251773 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 23:22:40.255172 0 9 12 | B1->B0 | 3131 2e2e | 1 1 | (1 0) (0 0)
4654 23:22:40.261007 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 23:22:40.264351 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 23:22:40.267701 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 23:22:40.274536 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 23:22:40.277476 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 23:22:40.281491 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 23:22:40.287807 0 10 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4661 23:22:40.291132 0 10 12 | B1->B0 | 2d2d 3737 | 0 0 | (0 0) (1 1)
4662 23:22:40.294323 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 23:22:40.300890 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 23:22:40.304149 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 23:22:40.307416 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 23:22:40.314284 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 23:22:40.317270 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 23:22:40.320751 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 23:22:40.326862 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4670 23:22:40.330733 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 23:22:40.333612 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 23:22:40.340026 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 23:22:40.343571 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 23:22:40.346661 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 23:22:40.353424 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 23:22:40.356605 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 23:22:40.359854 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 23:22:40.366199 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 23:22:40.369846 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 23:22:40.373247 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 23:22:40.379715 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 23:22:40.383122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 23:22:40.386446 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 23:22:40.392799 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 23:22:40.396130 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 23:22:40.399325 Total UI for P1: 0, mck2ui 16
4687 23:22:40.403024 best dqsien dly found for B0: ( 0, 13, 10)
4688 23:22:40.406172 Total UI for P1: 0, mck2ui 16
4689 23:22:40.409607 best dqsien dly found for B1: ( 0, 13, 10)
4690 23:22:40.412490 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4691 23:22:40.416088 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4692 23:22:40.416212
4693 23:22:40.419257 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4694 23:22:40.425974 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4695 23:22:40.426080 [Gating] SW calibration Done
4696 23:22:40.426185 ==
4697 23:22:40.428640 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 23:22:40.435427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 23:22:40.435546 ==
4700 23:22:40.435654 RX Vref Scan: 0
4701 23:22:40.435759
4702 23:22:40.438946 RX Vref 0 -> 0, step: 1
4703 23:22:40.439052
4704 23:22:40.442121 RX Delay -230 -> 252, step: 16
4705 23:22:40.445355 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4706 23:22:40.448817 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4707 23:22:40.455311 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4708 23:22:40.458630 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4709 23:22:40.462021 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4710 23:22:40.465635 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4711 23:22:40.468300 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4712 23:22:40.475095 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4713 23:22:40.478216 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4714 23:22:40.481483 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4715 23:22:40.484999 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4716 23:22:40.491947 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4717 23:22:40.494996 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4718 23:22:40.498182 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4719 23:22:40.501467 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4720 23:22:40.507938 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4721 23:22:40.508022 ==
4722 23:22:40.511221 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 23:22:40.515069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 23:22:40.515152 ==
4725 23:22:40.515216 DQS Delay:
4726 23:22:40.518364 DQS0 = 0, DQS1 = 0
4727 23:22:40.518492 DQM Delay:
4728 23:22:40.521504 DQM0 = 42, DQM1 = 39
4729 23:22:40.521627 DQ Delay:
4730 23:22:40.524622 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4731 23:22:40.527899 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4732 23:22:40.531309 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4733 23:22:40.534759 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4734 23:22:40.534879
4735 23:22:40.534991
4736 23:22:40.535102 ==
4737 23:22:40.537691 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 23:22:40.540766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 23:22:40.544064 ==
4740 23:22:40.544186
4741 23:22:40.544296
4742 23:22:40.544405 TX Vref Scan disable
4743 23:22:40.547311 == TX Byte 0 ==
4744 23:22:40.550644 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4745 23:22:40.557655 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4746 23:22:40.557775 == TX Byte 1 ==
4747 23:22:40.560585 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4748 23:22:40.567194 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4749 23:22:40.567318 ==
4750 23:22:40.570908 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 23:22:40.574054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 23:22:40.574184 ==
4753 23:22:40.574290
4754 23:22:40.574393
4755 23:22:40.577437 TX Vref Scan disable
4756 23:22:40.580419 == TX Byte 0 ==
4757 23:22:40.583684 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4758 23:22:40.586875 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4759 23:22:40.590295 == TX Byte 1 ==
4760 23:22:40.593742 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4761 23:22:40.597104 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4762 23:22:40.597187
4763 23:22:40.600421 [DATLAT]
4764 23:22:40.600502 Freq=600, CH1 RK1
4765 23:22:40.600566
4766 23:22:40.603414 DATLAT Default: 0x9
4767 23:22:40.603495 0, 0xFFFF, sum = 0
4768 23:22:40.606757 1, 0xFFFF, sum = 0
4769 23:22:40.606840 2, 0xFFFF, sum = 0
4770 23:22:40.609836 3, 0xFFFF, sum = 0
4771 23:22:40.609920 4, 0xFFFF, sum = 0
4772 23:22:40.613567 5, 0xFFFF, sum = 0
4773 23:22:40.613650 6, 0xFFFF, sum = 0
4774 23:22:40.616940 7, 0xFFFF, sum = 0
4775 23:22:40.617069 8, 0x0, sum = 1
4776 23:22:40.619930 9, 0x0, sum = 2
4777 23:22:40.620016 10, 0x0, sum = 3
4778 23:22:40.623279 11, 0x0, sum = 4
4779 23:22:40.623394 best_step = 9
4780 23:22:40.623461
4781 23:22:40.623521 ==
4782 23:22:40.626310 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 23:22:40.630162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 23:22:40.633456 ==
4785 23:22:40.633565 RX Vref Scan: 0
4786 23:22:40.633662
4787 23:22:40.636236 RX Vref 0 -> 0, step: 1
4788 23:22:40.636310
4789 23:22:40.639593 RX Delay -179 -> 252, step: 8
4790 23:22:40.642795 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4791 23:22:40.646384 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4792 23:22:40.652679 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4793 23:22:40.656246 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4794 23:22:40.659820 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4795 23:22:40.662501 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4796 23:22:40.669112 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4797 23:22:40.672415 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4798 23:22:40.676192 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4799 23:22:40.679198 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4800 23:22:40.685917 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4801 23:22:40.689296 iDelay=205, Bit 11, Center 32 (-123 ~ 188) 312
4802 23:22:40.692540 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4803 23:22:40.695890 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4804 23:22:40.702391 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4805 23:22:40.705560 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4806 23:22:40.705673 ==
4807 23:22:40.709153 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 23:22:40.712550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 23:22:40.712664 ==
4810 23:22:40.715590 DQS Delay:
4811 23:22:40.715706 DQS0 = 0, DQS1 = 0
4812 23:22:40.715802 DQM Delay:
4813 23:22:40.718855 DQM0 = 37, DQM1 = 35
4814 23:22:40.718987 DQ Delay:
4815 23:22:40.721855 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4816 23:22:40.725215 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4817 23:22:40.728848 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =32
4818 23:22:40.731870 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4819 23:22:40.731998
4820 23:22:40.732108
4821 23:22:40.741464 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f54, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4822 23:22:40.745124 CH1 RK1: MR19=808, MR18=2F54
4823 23:22:40.748414 CH1_RK1: MR19=0x808, MR18=0x2F54, DQSOSC=393, MR23=63, INC=169, DEC=113
4824 23:22:40.751977 [RxdqsGatingPostProcess] freq 600
4825 23:22:40.757974 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4826 23:22:40.761324 Pre-setting of DQS Precalculation
4827 23:22:40.764809 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4828 23:22:40.775014 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4829 23:22:40.781372 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4830 23:22:40.781458
4831 23:22:40.781523
4832 23:22:40.784684 [Calibration Summary] 1200 Mbps
4833 23:22:40.784767 CH 0, Rank 0
4834 23:22:40.787889 SW Impedance : PASS
4835 23:22:40.787997 DUTY Scan : NO K
4836 23:22:40.791274 ZQ Calibration : PASS
4837 23:22:40.794755 Jitter Meter : NO K
4838 23:22:40.794837 CBT Training : PASS
4839 23:22:40.797431 Write leveling : PASS
4840 23:22:40.800934 RX DQS gating : PASS
4841 23:22:40.801016 RX DQ/DQS(RDDQC) : PASS
4842 23:22:40.803934 TX DQ/DQS : PASS
4843 23:22:40.807553 RX DATLAT : PASS
4844 23:22:40.807635 RX DQ/DQS(Engine): PASS
4845 23:22:40.810981 TX OE : NO K
4846 23:22:40.811089 All Pass.
4847 23:22:40.811181
4848 23:22:40.814313 CH 0, Rank 1
4849 23:22:40.814420 SW Impedance : PASS
4850 23:22:40.817826 DUTY Scan : NO K
4851 23:22:40.820931 ZQ Calibration : PASS
4852 23:22:40.821040 Jitter Meter : NO K
4853 23:22:40.824213 CBT Training : PASS
4854 23:22:40.827064 Write leveling : PASS
4855 23:22:40.827164 RX DQS gating : PASS
4856 23:22:40.830815 RX DQ/DQS(RDDQC) : PASS
4857 23:22:40.833695 TX DQ/DQS : PASS
4858 23:22:40.833777 RX DATLAT : PASS
4859 23:22:40.836987 RX DQ/DQS(Engine): PASS
4860 23:22:40.840468 TX OE : NO K
4861 23:22:40.840593 All Pass.
4862 23:22:40.840705
4863 23:22:40.840815 CH 1, Rank 0
4864 23:22:40.843629 SW Impedance : PASS
4865 23:22:40.847056 DUTY Scan : NO K
4866 23:22:40.847177 ZQ Calibration : PASS
4867 23:22:40.850060 Jitter Meter : NO K
4868 23:22:40.853313 CBT Training : PASS
4869 23:22:40.853396 Write leveling : PASS
4870 23:22:40.856593 RX DQS gating : PASS
4871 23:22:40.860535 RX DQ/DQS(RDDQC) : PASS
4872 23:22:40.860621 TX DQ/DQS : PASS
4873 23:22:40.863182 RX DATLAT : PASS
4874 23:22:40.866844 RX DQ/DQS(Engine): PASS
4875 23:22:40.866928 TX OE : NO K
4876 23:22:40.867007 All Pass.
4877 23:22:40.867068
4878 23:22:40.869898 CH 1, Rank 1
4879 23:22:40.873542 SW Impedance : PASS
4880 23:22:40.873623 DUTY Scan : NO K
4881 23:22:40.876264 ZQ Calibration : PASS
4882 23:22:40.876346 Jitter Meter : NO K
4883 23:22:40.879882 CBT Training : PASS
4884 23:22:40.883126 Write leveling : PASS
4885 23:22:40.883235 RX DQS gating : PASS
4886 23:22:40.886346 RX DQ/DQS(RDDQC) : PASS
4887 23:22:40.889668 TX DQ/DQS : PASS
4888 23:22:40.889750 RX DATLAT : PASS
4889 23:22:40.893067 RX DQ/DQS(Engine): PASS
4890 23:22:40.896003 TX OE : NO K
4891 23:22:40.896085 All Pass.
4892 23:22:40.896149
4893 23:22:40.899518 DramC Write-DBI off
4894 23:22:40.899600 PER_BANK_REFRESH: Hybrid Mode
4895 23:22:40.902724 TX_TRACKING: ON
4896 23:22:40.912495 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4897 23:22:40.916003 [FAST_K] Save calibration result to emmc
4898 23:22:40.919317 dramc_set_vcore_voltage set vcore to 662500
4899 23:22:40.919419 Read voltage for 933, 3
4900 23:22:40.922856 Vio18 = 0
4901 23:22:40.922964 Vcore = 662500
4902 23:22:40.923057 Vdram = 0
4903 23:22:40.925585 Vddq = 0
4904 23:22:40.925673 Vmddr = 0
4905 23:22:40.932473 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4906 23:22:40.935986 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4907 23:22:40.938828 MEM_TYPE=3, freq_sel=17
4908 23:22:40.942288 sv_algorithm_assistance_LP4_1600
4909 23:22:40.946045 ============ PULL DRAM RESETB DOWN ============
4910 23:22:40.949119 ========== PULL DRAM RESETB DOWN end =========
4911 23:22:40.955861 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4912 23:22:40.959188 ===================================
4913 23:22:40.959299 LPDDR4 DRAM CONFIGURATION
4914 23:22:40.961761 ===================================
4915 23:22:40.965413 EX_ROW_EN[0] = 0x0
4916 23:22:40.968717 EX_ROW_EN[1] = 0x0
4917 23:22:40.968795 LP4Y_EN = 0x0
4918 23:22:40.971673 WORK_FSP = 0x0
4919 23:22:40.971759 WL = 0x3
4920 23:22:40.975049 RL = 0x3
4921 23:22:40.975117 BL = 0x2
4922 23:22:40.978537 RPST = 0x0
4923 23:22:40.978647 RD_PRE = 0x0
4924 23:22:40.981829 WR_PRE = 0x1
4925 23:22:40.981903 WR_PST = 0x0
4926 23:22:40.985289 DBI_WR = 0x0
4927 23:22:40.985398 DBI_RD = 0x0
4928 23:22:40.988482 OTF = 0x1
4929 23:22:40.991695 ===================================
4930 23:22:40.995028 ===================================
4931 23:22:40.995139 ANA top config
4932 23:22:40.998413 ===================================
4933 23:22:41.001616 DLL_ASYNC_EN = 0
4934 23:22:41.005123 ALL_SLAVE_EN = 1
4935 23:22:41.008044 NEW_RANK_MODE = 1
4936 23:22:41.008131 DLL_IDLE_MODE = 1
4937 23:22:41.011491 LP45_APHY_COMB_EN = 1
4938 23:22:41.014872 TX_ODT_DIS = 1
4939 23:22:41.018043 NEW_8X_MODE = 1
4940 23:22:41.021013 ===================================
4941 23:22:41.024648 ===================================
4942 23:22:41.027946 data_rate = 1866
4943 23:22:41.031052 CKR = 1
4944 23:22:41.031176 DQ_P2S_RATIO = 8
4945 23:22:41.034606 ===================================
4946 23:22:41.038064 CA_P2S_RATIO = 8
4947 23:22:41.041356 DQ_CA_OPEN = 0
4948 23:22:41.044563 DQ_SEMI_OPEN = 0
4949 23:22:41.048060 CA_SEMI_OPEN = 0
4950 23:22:41.051333 CA_FULL_RATE = 0
4951 23:22:41.051460 DQ_CKDIV4_EN = 1
4952 23:22:41.054565 CA_CKDIV4_EN = 1
4953 23:22:41.058075 CA_PREDIV_EN = 0
4954 23:22:41.061221 PH8_DLY = 0
4955 23:22:41.064096 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4956 23:22:41.067370 DQ_AAMCK_DIV = 4
4957 23:22:41.067492 CA_AAMCK_DIV = 4
4958 23:22:41.070552 CA_ADMCK_DIV = 4
4959 23:22:41.074168 DQ_TRACK_CA_EN = 0
4960 23:22:41.077589 CA_PICK = 933
4961 23:22:41.080332 CA_MCKIO = 933
4962 23:22:41.083886 MCKIO_SEMI = 0
4963 23:22:41.087252 PLL_FREQ = 3732
4964 23:22:41.087388 DQ_UI_PI_RATIO = 32
4965 23:22:41.090517 CA_UI_PI_RATIO = 0
4966 23:22:41.093912 ===================================
4967 23:22:41.096956 ===================================
4968 23:22:41.100408 memory_type:LPDDR4
4969 23:22:41.103681 GP_NUM : 10
4970 23:22:41.103807 SRAM_EN : 1
4971 23:22:41.107029 MD32_EN : 0
4972 23:22:41.109870 ===================================
4973 23:22:41.113260 [ANA_INIT] >>>>>>>>>>>>>>
4974 23:22:41.116645 <<<<<< [CONFIGURE PHASE]: ANA_TX
4975 23:22:41.119738 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4976 23:22:41.123467 ===================================
4977 23:22:41.123592 data_rate = 1866,PCW = 0X8f00
4978 23:22:41.126457 ===================================
4979 23:22:41.129884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4980 23:22:41.136109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4981 23:22:41.142992 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 23:22:41.146064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4983 23:22:41.149578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4984 23:22:41.152557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4985 23:22:41.155810 [ANA_INIT] flow start
4986 23:22:41.159369 [ANA_INIT] PLL >>>>>>>>
4987 23:22:41.159452 [ANA_INIT] PLL <<<<<<<<
4988 23:22:41.162287 [ANA_INIT] MIDPI >>>>>>>>
4989 23:22:41.165733 [ANA_INIT] MIDPI <<<<<<<<
4990 23:22:41.165845 [ANA_INIT] DLL >>>>>>>>
4991 23:22:41.169148 [ANA_INIT] flow end
4992 23:22:41.172389 ============ LP4 DIFF to SE enter ============
4993 23:22:41.179129 ============ LP4 DIFF to SE exit ============
4994 23:22:41.179241 [ANA_INIT] <<<<<<<<<<<<<
4995 23:22:41.182081 [Flow] Enable top DCM control >>>>>
4996 23:22:41.185268 [Flow] Enable top DCM control <<<<<
4997 23:22:41.188804 Enable DLL master slave shuffle
4998 23:22:41.195011 ==============================================================
4999 23:22:41.195119 Gating Mode config
5000 23:22:41.202238 ==============================================================
5001 23:22:41.205365 Config description:
5002 23:22:41.215256 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5003 23:22:41.221687 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5004 23:22:41.224681 SELPH_MODE 0: By rank 1: By Phase
5005 23:22:41.231533 ==============================================================
5006 23:22:41.234595 GAT_TRACK_EN = 1
5007 23:22:41.237720 RX_GATING_MODE = 2
5008 23:22:41.241277 RX_GATING_TRACK_MODE = 2
5009 23:22:41.241362 SELPH_MODE = 1
5010 23:22:41.244716 PICG_EARLY_EN = 1
5011 23:22:41.248248 VALID_LAT_VALUE = 1
5012 23:22:41.254799 ==============================================================
5013 23:22:41.257550 Enter into Gating configuration >>>>
5014 23:22:41.261249 Exit from Gating configuration <<<<
5015 23:22:41.264062 Enter into DVFS_PRE_config >>>>>
5016 23:22:41.274050 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5017 23:22:41.277412 Exit from DVFS_PRE_config <<<<<
5018 23:22:41.280888 Enter into PICG configuration >>>>
5019 23:22:41.284296 Exit from PICG configuration <<<<
5020 23:22:41.287430 [RX_INPUT] configuration >>>>>
5021 23:22:41.290855 [RX_INPUT] configuration <<<<<
5022 23:22:41.293948 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5023 23:22:41.300421 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5024 23:22:41.306968 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5025 23:22:41.313735 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5026 23:22:41.320007 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5027 23:22:41.326905 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5028 23:22:41.330128 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5029 23:22:41.333332 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5030 23:22:41.336472 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5031 23:22:41.343165 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5032 23:22:41.346393 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5033 23:22:41.349927 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5034 23:22:41.352737 ===================================
5035 23:22:41.356175 LPDDR4 DRAM CONFIGURATION
5036 23:22:41.359711 ===================================
5037 23:22:41.362735 EX_ROW_EN[0] = 0x0
5038 23:22:41.362850 EX_ROW_EN[1] = 0x0
5039 23:22:41.366011 LP4Y_EN = 0x0
5040 23:22:41.366120 WORK_FSP = 0x0
5041 23:22:41.369477 WL = 0x3
5042 23:22:41.369586 RL = 0x3
5043 23:22:41.372836 BL = 0x2
5044 23:22:41.372943 RPST = 0x0
5045 23:22:41.376029 RD_PRE = 0x0
5046 23:22:41.376128 WR_PRE = 0x1
5047 23:22:41.379687 WR_PST = 0x0
5048 23:22:41.379772 DBI_WR = 0x0
5049 23:22:41.382978 DBI_RD = 0x0
5050 23:22:41.383061 OTF = 0x1
5051 23:22:41.386295 ===================================
5052 23:22:41.392177 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5053 23:22:41.395751 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5054 23:22:41.399146 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 23:22:41.402324 ===================================
5056 23:22:41.405418 LPDDR4 DRAM CONFIGURATION
5057 23:22:41.408666 ===================================
5058 23:22:41.412205 EX_ROW_EN[0] = 0x10
5059 23:22:41.412288 EX_ROW_EN[1] = 0x0
5060 23:22:41.415349 LP4Y_EN = 0x0
5061 23:22:41.415440 WORK_FSP = 0x0
5062 23:22:41.418722 WL = 0x3
5063 23:22:41.418811 RL = 0x3
5064 23:22:41.422101 BL = 0x2
5065 23:22:41.422213 RPST = 0x0
5066 23:22:41.425363 RD_PRE = 0x0
5067 23:22:41.425445 WR_PRE = 0x1
5068 23:22:41.428161 WR_PST = 0x0
5069 23:22:41.428243 DBI_WR = 0x0
5070 23:22:41.431697 DBI_RD = 0x0
5071 23:22:41.435347 OTF = 0x1
5072 23:22:41.435478 ===================================
5073 23:22:41.441650 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5074 23:22:41.447091 nWR fixed to 30
5075 23:22:41.450150 [ModeRegInit_LP4] CH0 RK0
5076 23:22:41.450263 [ModeRegInit_LP4] CH0 RK1
5077 23:22:41.453097 [ModeRegInit_LP4] CH1 RK0
5078 23:22:41.456396 [ModeRegInit_LP4] CH1 RK1
5079 23:22:41.456506 match AC timing 9
5080 23:22:41.463368 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5081 23:22:41.466549 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5082 23:22:41.469794 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5083 23:22:41.476377 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5084 23:22:41.480073 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5085 23:22:41.480184 ==
5086 23:22:41.482745 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 23:22:41.486180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 23:22:41.486292 ==
5089 23:22:41.492884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5090 23:22:41.499644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5091 23:22:41.502673 [CA 0] Center 37 (7~68) winsize 62
5092 23:22:41.506202 [CA 1] Center 37 (7~68) winsize 62
5093 23:22:41.509252 [CA 2] Center 34 (4~64) winsize 61
5094 23:22:41.512660 [CA 3] Center 34 (4~65) winsize 62
5095 23:22:41.515953 [CA 4] Center 32 (2~63) winsize 62
5096 23:22:41.519456 [CA 5] Center 32 (2~63) winsize 62
5097 23:22:41.519541
5098 23:22:41.522640 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5099 23:22:41.522711
5100 23:22:41.525647 [CATrainingPosCal] consider 1 rank data
5101 23:22:41.529036 u2DelayCellTimex100 = 270/100 ps
5102 23:22:41.532473 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5103 23:22:41.535484 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5104 23:22:41.539047 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5105 23:22:41.545418 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5106 23:22:41.548956 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5107 23:22:41.552145 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5108 23:22:41.552252
5109 23:22:41.555486 CA PerBit enable=1, Macro0, CA PI delay=32
5110 23:22:41.555561
5111 23:22:41.558692 [CBTSetCACLKResult] CA Dly = 32
5112 23:22:41.558790 CS Dly: 6 (0~37)
5113 23:22:41.558879 ==
5114 23:22:41.561741 Dram Type= 6, Freq= 0, CH_0, rank 1
5115 23:22:41.568410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 23:22:41.568520 ==
5117 23:22:41.572101 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5118 23:22:41.578317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5119 23:22:41.581716 [CA 0] Center 38 (8~68) winsize 61
5120 23:22:41.585222 [CA 1] Center 37 (7~68) winsize 62
5121 23:22:41.588571 [CA 2] Center 34 (4~65) winsize 62
5122 23:22:41.592138 [CA 3] Center 34 (4~65) winsize 62
5123 23:22:41.594974 [CA 4] Center 33 (3~64) winsize 62
5124 23:22:41.598290 [CA 5] Center 32 (2~63) winsize 62
5125 23:22:41.598393
5126 23:22:41.601789 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5127 23:22:41.601905
5128 23:22:41.604960 [CATrainingPosCal] consider 2 rank data
5129 23:22:41.608245 u2DelayCellTimex100 = 270/100 ps
5130 23:22:41.611441 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5131 23:22:41.618391 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5132 23:22:41.621285 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5133 23:22:41.624572 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5134 23:22:41.627956 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5135 23:22:41.631469 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5136 23:22:41.631577
5137 23:22:41.634791 CA PerBit enable=1, Macro0, CA PI delay=32
5138 23:22:41.634880
5139 23:22:41.638420 [CBTSetCACLKResult] CA Dly = 32
5140 23:22:41.640942 CS Dly: 7 (0~39)
5141 23:22:41.641024
5142 23:22:41.644562 ----->DramcWriteLeveling(PI) begin...
5143 23:22:41.644664 ==
5144 23:22:41.647629 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 23:22:41.650784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 23:22:41.650869 ==
5147 23:22:41.654256 Write leveling (Byte 0): 29 => 29
5148 23:22:41.657810 Write leveling (Byte 1): 29 => 29
5149 23:22:41.660820 DramcWriteLeveling(PI) end<-----
5150 23:22:41.660926
5151 23:22:41.661020 ==
5152 23:22:41.664203 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 23:22:41.667771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 23:22:41.667878 ==
5155 23:22:41.670712 [Gating] SW mode calibration
5156 23:22:41.677092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5157 23:22:41.684085 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5158 23:22:41.687170 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
5159 23:22:41.693861 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 23:22:41.697167 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 23:22:41.700511 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 23:22:41.706985 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 23:22:41.710547 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 23:22:41.713618 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 23:22:41.720199 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
5166 23:22:41.723619 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5167 23:22:41.726533 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 23:22:41.733058 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 23:22:41.736355 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 23:22:41.739656 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 23:22:41.746399 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 23:22:41.749979 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 23:22:41.752914 0 15 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
5174 23:22:41.759757 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5175 23:22:41.762909 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 23:22:41.766109 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 23:22:41.772632 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 23:22:41.776169 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 23:22:41.779449 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 23:22:41.785785 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 23:22:41.789391 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5182 23:22:41.792599 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5183 23:22:41.799271 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5184 23:22:41.802525 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 23:22:41.805912 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 23:22:41.812187 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 23:22:41.815731 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 23:22:41.819048 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 23:22:41.825510 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 23:22:41.828846 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 23:22:41.832035 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 23:22:41.838908 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 23:22:41.842089 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 23:22:41.845521 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 23:22:41.852311 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 23:22:41.855199 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 23:22:41.858625 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5198 23:22:41.861763 Total UI for P1: 0, mck2ui 16
5199 23:22:41.865246 best dqsien dly found for B0: ( 1, 2, 26)
5200 23:22:41.871401 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5201 23:22:41.875110 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 23:22:41.878182 Total UI for P1: 0, mck2ui 16
5203 23:22:41.881476 best dqsien dly found for B1: ( 1, 3, 2)
5204 23:22:41.885063 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5205 23:22:41.888096 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5206 23:22:41.888180
5207 23:22:41.891624 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5208 23:22:41.894656 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5209 23:22:41.897791 [Gating] SW calibration Done
5210 23:22:41.897953 ==
5211 23:22:41.901345 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 23:22:41.904966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 23:22:41.907712 ==
5214 23:22:41.907857 RX Vref Scan: 0
5215 23:22:41.907959
5216 23:22:41.910884 RX Vref 0 -> 0, step: 1
5217 23:22:41.910995
5218 23:22:41.914197 RX Delay -80 -> 252, step: 8
5219 23:22:41.918205 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5220 23:22:41.920915 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5221 23:22:41.924444 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5222 23:22:41.927871 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5223 23:22:41.930688 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5224 23:22:41.937466 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5225 23:22:41.940902 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5226 23:22:41.944128 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5227 23:22:41.947431 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5228 23:22:41.950768 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5229 23:22:41.957237 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5230 23:22:41.960426 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5231 23:22:41.963699 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5232 23:22:41.967240 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5233 23:22:41.970406 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5234 23:22:41.976935 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5235 23:22:41.977061 ==
5236 23:22:41.980459 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 23:22:41.983338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 23:22:41.983460 ==
5239 23:22:41.983567 DQS Delay:
5240 23:22:41.986499 DQS0 = 0, DQS1 = 0
5241 23:22:41.986599 DQM Delay:
5242 23:22:41.990284 DQM0 = 100, DQM1 = 89
5243 23:22:41.990383 DQ Delay:
5244 23:22:41.993455 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5245 23:22:41.996674 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5246 23:22:41.999873 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5247 23:22:42.003497 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5248 23:22:42.003624
5249 23:22:42.003740
5250 23:22:42.003853 ==
5251 23:22:42.006408 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 23:22:42.009483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 23:22:42.013146 ==
5254 23:22:42.013262
5255 23:22:42.013361
5256 23:22:42.013456 TX Vref Scan disable
5257 23:22:42.016648 == TX Byte 0 ==
5258 23:22:42.019774 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5259 23:22:42.022866 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5260 23:22:42.026499 == TX Byte 1 ==
5261 23:22:42.029349 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5262 23:22:42.033136 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5263 23:22:42.036152 ==
5264 23:22:42.039265 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 23:22:42.042535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 23:22:42.042668 ==
5267 23:22:42.042785
5268 23:22:42.042897
5269 23:22:42.046648 TX Vref Scan disable
5270 23:22:42.046752 == TX Byte 0 ==
5271 23:22:42.052689 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5272 23:22:42.056250 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5273 23:22:42.056358 == TX Byte 1 ==
5274 23:22:42.062224 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5275 23:22:42.065669 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5276 23:22:42.065782
5277 23:22:42.065879 [DATLAT]
5278 23:22:42.068811 Freq=933, CH0 RK0
5279 23:22:42.068929
5280 23:22:42.069023 DATLAT Default: 0xd
5281 23:22:42.072177 0, 0xFFFF, sum = 0
5282 23:22:42.072280 1, 0xFFFF, sum = 0
5283 23:22:42.075630 2, 0xFFFF, sum = 0
5284 23:22:42.079175 3, 0xFFFF, sum = 0
5285 23:22:42.079313 4, 0xFFFF, sum = 0
5286 23:22:42.082405 5, 0xFFFF, sum = 0
5287 23:22:42.082541 6, 0xFFFF, sum = 0
5288 23:22:42.085842 7, 0xFFFF, sum = 0
5289 23:22:42.085976 8, 0xFFFF, sum = 0
5290 23:22:42.088513 9, 0xFFFF, sum = 0
5291 23:22:42.088642 10, 0x0, sum = 1
5292 23:22:42.091985 11, 0x0, sum = 2
5293 23:22:42.092118 12, 0x0, sum = 3
5294 23:22:42.095350 13, 0x0, sum = 4
5295 23:22:42.095488 best_step = 11
5296 23:22:42.095605
5297 23:22:42.095712 ==
5298 23:22:42.098425 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 23:22:42.102043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 23:22:42.102178 ==
5301 23:22:42.105374 RX Vref Scan: 1
5302 23:22:42.105500
5303 23:22:42.108378 RX Vref 0 -> 0, step: 1
5304 23:22:42.108505
5305 23:22:42.108618 RX Delay -61 -> 252, step: 4
5306 23:22:42.108742
5307 23:22:42.111905 Set Vref, RX VrefLevel [Byte0]: 53
5308 23:22:42.114888 [Byte1]: 59
5309 23:22:42.120083
5310 23:22:42.120206 Final RX Vref Byte 0 = 53 to rank0
5311 23:22:42.123100 Final RX Vref Byte 1 = 59 to rank0
5312 23:22:42.126360 Final RX Vref Byte 0 = 53 to rank1
5313 23:22:42.129792 Final RX Vref Byte 1 = 59 to rank1==
5314 23:22:42.133239 Dram Type= 6, Freq= 0, CH_0, rank 0
5315 23:22:42.139693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 23:22:42.139822 ==
5317 23:22:42.139945 DQS Delay:
5318 23:22:42.142800 DQS0 = 0, DQS1 = 0
5319 23:22:42.142915 DQM Delay:
5320 23:22:42.143035 DQM0 = 98, DQM1 = 88
5321 23:22:42.146293 DQ Delay:
5322 23:22:42.149515 DQ0 =100, DQ1 =98, DQ2 =92, DQ3 =94
5323 23:22:42.152906 DQ4 =100, DQ5 =90, DQ6 =106, DQ7 =106
5324 23:22:42.156436 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =84
5325 23:22:42.159976 DQ12 =96, DQ13 =94, DQ14 =96, DQ15 =94
5326 23:22:42.160086
5327 23:22:42.160178
5328 23:22:42.165727 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5329 23:22:42.169089 CH0 RK0: MR19=505, MR18=1C16
5330 23:22:42.175914 CH0_RK0: MR19=0x505, MR18=0x1C16, DQSOSC=412, MR23=63, INC=63, DEC=42
5331 23:22:42.176009
5332 23:22:42.179015 ----->DramcWriteLeveling(PI) begin...
5333 23:22:42.179119 ==
5334 23:22:42.182695 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 23:22:42.185748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 23:22:42.185853 ==
5337 23:22:42.189369 Write leveling (Byte 0): 32 => 32
5338 23:22:42.192553 Write leveling (Byte 1): 29 => 29
5339 23:22:42.195491 DramcWriteLeveling(PI) end<-----
5340 23:22:42.195569
5341 23:22:42.195636 ==
5342 23:22:42.198753 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 23:22:42.205621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 23:22:42.205724 ==
5345 23:22:42.205795 [Gating] SW mode calibration
5346 23:22:42.215838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5347 23:22:42.218546 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5348 23:22:42.225554 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5349 23:22:42.228554 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5350 23:22:42.231868 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 23:22:42.238375 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 23:22:42.241533 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 23:22:42.244914 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 23:22:42.251612 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 23:22:42.254811 0 14 28 | B1->B0 | 3434 2929 | 1 1 | (0 0) (0 0)
5356 23:22:42.257980 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
5357 23:22:42.264534 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 23:22:42.268041 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 23:22:42.270966 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 23:22:42.277937 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 23:22:42.281158 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 23:22:42.284432 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5363 23:22:42.290706 0 15 28 | B1->B0 | 2b2b 4141 | 0 0 | (0 0) (0 0)
5364 23:22:42.294359 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5365 23:22:42.297493 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 23:22:42.304209 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 23:22:42.307483 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 23:22:42.310855 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 23:22:42.316964 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 23:22:42.320284 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 23:22:42.324184 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5372 23:22:42.330347 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5373 23:22:42.333413 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 23:22:42.336778 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 23:22:42.343539 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:22:42.346911 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:22:42.349944 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:22:42.357126 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:22:42.360497 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:22:42.363614 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:22:42.370147 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:22:42.373573 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:22:42.376893 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:22:42.382916 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 23:22:42.386092 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:22:42.389773 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:22:42.396177 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5388 23:22:42.399719 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5389 23:22:42.402720 Total UI for P1: 0, mck2ui 16
5390 23:22:42.405921 best dqsien dly found for B0: ( 1, 2, 28)
5391 23:22:42.409196 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 23:22:42.412470 Total UI for P1: 0, mck2ui 16
5393 23:22:42.415763 best dqsien dly found for B1: ( 1, 3, 0)
5394 23:22:42.419395 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5395 23:22:42.422555 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5396 23:22:42.422636
5397 23:22:42.428953 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5398 23:22:42.432431 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5399 23:22:42.432540 [Gating] SW calibration Done
5400 23:22:42.435801 ==
5401 23:22:42.438974 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 23:22:42.442531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 23:22:42.442643 ==
5404 23:22:42.442737 RX Vref Scan: 0
5405 23:22:42.442833
5406 23:22:42.445915 RX Vref 0 -> 0, step: 1
5407 23:22:42.445997
5408 23:22:42.448793 RX Delay -80 -> 252, step: 8
5409 23:22:42.452096 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5410 23:22:42.455378 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5411 23:22:42.458946 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5412 23:22:42.465224 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5413 23:22:42.468547 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5414 23:22:42.471741 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5415 23:22:42.475494 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5416 23:22:42.478791 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5417 23:22:42.481837 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5418 23:22:42.488411 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5419 23:22:42.491685 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5420 23:22:42.494913 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5421 23:22:42.498385 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5422 23:22:42.501728 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5423 23:22:42.508256 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5424 23:22:42.511234 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5425 23:22:42.511344 ==
5426 23:22:42.514638 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 23:22:42.517934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 23:22:42.518036 ==
5429 23:22:42.518127 DQS Delay:
5430 23:22:42.521412 DQS0 = 0, DQS1 = 0
5431 23:22:42.521507 DQM Delay:
5432 23:22:42.524352 DQM0 = 97, DQM1 = 91
5433 23:22:42.524449 DQ Delay:
5434 23:22:42.527983 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5435 23:22:42.530765 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5436 23:22:42.534538 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =83
5437 23:22:42.537627 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5438 23:22:42.537710
5439 23:22:42.537775
5440 23:22:42.537833 ==
5441 23:22:42.540702 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 23:22:42.547415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 23:22:42.547499 ==
5444 23:22:42.547564
5445 23:22:42.547623
5446 23:22:42.547680 TX Vref Scan disable
5447 23:22:42.551276 == TX Byte 0 ==
5448 23:22:42.554550 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5449 23:22:42.560936 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5450 23:22:42.561017 == TX Byte 1 ==
5451 23:22:42.564459 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5452 23:22:42.571373 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5453 23:22:42.571475 ==
5454 23:22:42.573872 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 23:22:42.577519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 23:22:42.577617 ==
5457 23:22:42.577705
5458 23:22:42.577792
5459 23:22:42.580849 TX Vref Scan disable
5460 23:22:42.580953 == TX Byte 0 ==
5461 23:22:42.587045 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5462 23:22:42.590462 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5463 23:22:42.594259 == TX Byte 1 ==
5464 23:22:42.597416 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5465 23:22:42.600285 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5466 23:22:42.600365
5467 23:22:42.600456 [DATLAT]
5468 23:22:42.603867 Freq=933, CH0 RK1
5469 23:22:42.603968
5470 23:22:42.606745 DATLAT Default: 0xb
5471 23:22:42.606844 0, 0xFFFF, sum = 0
5472 23:22:42.610888 1, 0xFFFF, sum = 0
5473 23:22:42.610990 2, 0xFFFF, sum = 0
5474 23:22:42.613598 3, 0xFFFF, sum = 0
5475 23:22:42.613701 4, 0xFFFF, sum = 0
5476 23:22:42.616983 5, 0xFFFF, sum = 0
5477 23:22:42.617087 6, 0xFFFF, sum = 0
5478 23:22:42.619997 7, 0xFFFF, sum = 0
5479 23:22:42.620097 8, 0xFFFF, sum = 0
5480 23:22:42.623808 9, 0xFFFF, sum = 0
5481 23:22:42.623893 10, 0x0, sum = 1
5482 23:22:42.626540 11, 0x0, sum = 2
5483 23:22:42.626651 12, 0x0, sum = 3
5484 23:22:42.630375 13, 0x0, sum = 4
5485 23:22:42.630491 best_step = 11
5486 23:22:42.630605
5487 23:22:42.630701 ==
5488 23:22:42.633224 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 23:22:42.636413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 23:22:42.639976 ==
5491 23:22:42.640076 RX Vref Scan: 0
5492 23:22:42.640171
5493 23:22:42.643284 RX Vref 0 -> 0, step: 1
5494 23:22:42.643389
5495 23:22:42.646635 RX Delay -53 -> 252, step: 4
5496 23:22:42.649831 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5497 23:22:42.653185 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5498 23:22:42.656145 iDelay=195, Bit 2, Center 90 (-1 ~ 182) 184
5499 23:22:42.662897 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5500 23:22:42.665944 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5501 23:22:42.669769 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5502 23:22:42.673195 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5503 23:22:42.676107 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5504 23:22:42.682686 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5505 23:22:42.686134 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5506 23:22:42.689679 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5507 23:22:42.692397 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5508 23:22:42.695777 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5509 23:22:42.702342 iDelay=195, Bit 13, Center 96 (7 ~ 186) 180
5510 23:22:42.705716 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5511 23:22:42.709227 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5512 23:22:42.709304 ==
5513 23:22:42.712887 Dram Type= 6, Freq= 0, CH_0, rank 1
5514 23:22:42.715480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 23:22:42.715580 ==
5516 23:22:42.718796 DQS Delay:
5517 23:22:42.718892 DQS0 = 0, DQS1 = 0
5518 23:22:42.718985 DQM Delay:
5519 23:22:42.722156 DQM0 = 97, DQM1 = 88
5520 23:22:42.722227 DQ Delay:
5521 23:22:42.725707 DQ0 =96, DQ1 =98, DQ2 =90, DQ3 =94
5522 23:22:42.729070 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =106
5523 23:22:42.732021 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5524 23:22:42.735341 DQ12 =94, DQ13 =96, DQ14 =98, DQ15 =94
5525 23:22:42.735460
5526 23:22:42.735528
5527 23:22:42.745412 [DQSOSCAuto] RK1, (LSB)MR18= 0x1210, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5528 23:22:42.748761 CH0 RK1: MR19=505, MR18=1210
5529 23:22:42.755406 CH0_RK1: MR19=0x505, MR18=0x1210, DQSOSC=416, MR23=63, INC=62, DEC=41
5530 23:22:42.755555 [RxdqsGatingPostProcess] freq 933
5531 23:22:42.762127 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5532 23:22:42.765163 best DQS0 dly(2T, 0.5T) = (0, 10)
5533 23:22:42.768236 best DQS1 dly(2T, 0.5T) = (0, 11)
5534 23:22:42.771841 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5535 23:22:42.775120 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5536 23:22:42.778080 best DQS0 dly(2T, 0.5T) = (0, 10)
5537 23:22:42.781573 best DQS1 dly(2T, 0.5T) = (0, 11)
5538 23:22:42.784706 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5539 23:22:42.788277 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5540 23:22:42.791688 Pre-setting of DQS Precalculation
5541 23:22:42.794639 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5542 23:22:42.794725 ==
5543 23:22:42.797963 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 23:22:42.804482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 23:22:42.804607 ==
5546 23:22:42.808041 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 23:22:42.814939 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5548 23:22:42.817698 [CA 0] Center 36 (6~67) winsize 62
5549 23:22:42.821317 [CA 1] Center 36 (6~67) winsize 62
5550 23:22:42.824188 [CA 2] Center 34 (4~65) winsize 62
5551 23:22:42.828189 [CA 3] Center 34 (3~65) winsize 63
5552 23:22:42.831582 [CA 4] Center 34 (3~65) winsize 63
5553 23:22:42.834359 [CA 5] Center 33 (3~64) winsize 62
5554 23:22:42.834467
5555 23:22:42.837601 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5556 23:22:42.837705
5557 23:22:42.841187 [CATrainingPosCal] consider 1 rank data
5558 23:22:42.844178 u2DelayCellTimex100 = 270/100 ps
5559 23:22:42.847447 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 23:22:42.851290 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5561 23:22:42.857252 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5562 23:22:42.860819 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5563 23:22:42.864224 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5564 23:22:42.867373 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5565 23:22:42.867485
5566 23:22:42.870717 CA PerBit enable=1, Macro0, CA PI delay=33
5567 23:22:42.870825
5568 23:22:42.873725 [CBTSetCACLKResult] CA Dly = 33
5569 23:22:42.873832 CS Dly: 5 (0~36)
5570 23:22:42.876849 ==
5571 23:22:42.880556 Dram Type= 6, Freq= 0, CH_1, rank 1
5572 23:22:42.883635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 23:22:42.883729 ==
5574 23:22:42.890195 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5575 23:22:42.893320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5576 23:22:42.897115 [CA 0] Center 36 (6~67) winsize 62
5577 23:22:42.900945 [CA 1] Center 36 (6~67) winsize 62
5578 23:22:42.904130 [CA 2] Center 34 (4~65) winsize 62
5579 23:22:42.907303 [CA 3] Center 33 (3~64) winsize 62
5580 23:22:42.910407 [CA 4] Center 34 (4~64) winsize 61
5581 23:22:42.914104 [CA 5] Center 33 (3~64) winsize 62
5582 23:22:42.914206
5583 23:22:42.917261 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5584 23:22:42.917363
5585 23:22:42.920178 [CATrainingPosCal] consider 2 rank data
5586 23:22:42.923801 u2DelayCellTimex100 = 270/100 ps
5587 23:22:42.926988 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5588 23:22:42.933537 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5589 23:22:42.936999 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5590 23:22:42.940368 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5591 23:22:42.943563 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5592 23:22:42.946407 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5593 23:22:42.946482
5594 23:22:42.949806 CA PerBit enable=1, Macro0, CA PI delay=33
5595 23:22:42.949907
5596 23:22:42.953681 [CBTSetCACLKResult] CA Dly = 33
5597 23:22:42.956757 CS Dly: 6 (0~38)
5598 23:22:42.956856
5599 23:22:42.959880 ----->DramcWriteLeveling(PI) begin...
5600 23:22:42.959964 ==
5601 23:22:42.963418 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 23:22:42.966616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 23:22:42.966715 ==
5604 23:22:42.969933 Write leveling (Byte 0): 28 => 28
5605 23:22:42.972853 Write leveling (Byte 1): 28 => 28
5606 23:22:42.976209 DramcWriteLeveling(PI) end<-----
5607 23:22:42.976306
5608 23:22:42.976401 ==
5609 23:22:42.979498 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 23:22:42.983153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 23:22:42.983258 ==
5612 23:22:42.986257 [Gating] SW mode calibration
5613 23:22:42.992973 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5614 23:22:42.999091 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5615 23:22:43.002422 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 23:22:43.009135 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 23:22:43.012285 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 23:22:43.015881 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 23:22:43.022324 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 23:22:43.025712 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 23:22:43.029200 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
5622 23:22:43.032345 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (1 0)
5623 23:22:43.039102 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5624 23:22:43.042305 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 23:22:43.045722 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 23:22:43.052571 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 23:22:43.055444 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 23:22:43.059247 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 23:22:43.065557 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 23:22:43.068671 0 15 28 | B1->B0 | 3a3a 4242 | 0 0 | (1 1) (0 0)
5631 23:22:43.075001 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 23:22:43.078514 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 23:22:43.081947 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 23:22:43.087957 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 23:22:43.091293 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 23:22:43.094836 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 23:22:43.101442 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 23:22:43.105159 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5639 23:22:43.107941 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 23:22:43.114582 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 23:22:43.118015 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 23:22:43.121374 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 23:22:43.127861 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 23:22:43.130870 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 23:22:43.134444 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 23:22:43.140842 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 23:22:43.144127 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:22:43.147641 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 23:22:43.154188 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 23:22:43.157266 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 23:22:43.160493 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 23:22:43.167157 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 23:22:43.170657 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 23:22:43.173795 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 23:22:43.177285 Total UI for P1: 0, mck2ui 16
5656 23:22:43.180054 best dqsien dly found for B0: ( 1, 2, 26)
5657 23:22:43.183652 Total UI for P1: 0, mck2ui 16
5658 23:22:43.187205 best dqsien dly found for B1: ( 1, 2, 26)
5659 23:22:43.190197 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5660 23:22:43.193474 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5661 23:22:43.193578
5662 23:22:43.200133 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5663 23:22:43.203444 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5664 23:22:43.203518 [Gating] SW calibration Done
5665 23:22:43.206716 ==
5666 23:22:43.210183 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 23:22:43.213282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 23:22:43.213394 ==
5669 23:22:43.213488 RX Vref Scan: 0
5670 23:22:43.213586
5671 23:22:43.216734 RX Vref 0 -> 0, step: 1
5672 23:22:43.216831
5673 23:22:43.219958 RX Delay -80 -> 252, step: 8
5674 23:22:43.223287 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5675 23:22:43.226575 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5676 23:22:43.232842 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5677 23:22:43.236058 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5678 23:22:43.239592 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5679 23:22:43.242657 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5680 23:22:43.246137 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5681 23:22:43.249234 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5682 23:22:43.255737 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5683 23:22:43.258874 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5684 23:22:43.262203 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5685 23:22:43.265565 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5686 23:22:43.268724 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5687 23:22:43.275375 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5688 23:22:43.279082 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5689 23:22:43.282374 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5690 23:22:43.282484 ==
5691 23:22:43.285524 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 23:22:43.288852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 23:22:43.288966 ==
5694 23:22:43.292357 DQS Delay:
5695 23:22:43.292486 DQS0 = 0, DQS1 = 0
5696 23:22:43.295023 DQM Delay:
5697 23:22:43.295135 DQM0 = 100, DQM1 = 95
5698 23:22:43.295231 DQ Delay:
5699 23:22:43.298781 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5700 23:22:43.301982 DQ4 =99, DQ5 =107, DQ6 =111, DQ7 =99
5701 23:22:43.304955 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =87
5702 23:22:43.311851 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5703 23:22:43.311963
5704 23:22:43.312070
5705 23:22:43.312168 ==
5706 23:22:43.315206 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 23:22:43.318042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 23:22:43.318148 ==
5709 23:22:43.318255
5710 23:22:43.318348
5711 23:22:43.321795 TX Vref Scan disable
5712 23:22:43.321903 == TX Byte 0 ==
5713 23:22:43.327941 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5714 23:22:43.331437 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5715 23:22:43.334826 == TX Byte 1 ==
5716 23:22:43.338126 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5717 23:22:43.341212 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5718 23:22:43.341319 ==
5719 23:22:43.344525 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 23:22:43.348348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 23:22:43.348452 ==
5722 23:22:43.351277
5723 23:22:43.351385
5724 23:22:43.351449 TX Vref Scan disable
5725 23:22:43.354463 == TX Byte 0 ==
5726 23:22:43.357844 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5727 23:22:43.364181 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5728 23:22:43.364286 == TX Byte 1 ==
5729 23:22:43.367979 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5730 23:22:43.374001 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5731 23:22:43.374108
5732 23:22:43.374202 [DATLAT]
5733 23:22:43.374290 Freq=933, CH1 RK0
5734 23:22:43.374381
5735 23:22:43.377293 DATLAT Default: 0xd
5736 23:22:43.380777 0, 0xFFFF, sum = 0
5737 23:22:43.380855 1, 0xFFFF, sum = 0
5738 23:22:43.384413 2, 0xFFFF, sum = 0
5739 23:22:43.384490 3, 0xFFFF, sum = 0
5740 23:22:43.387228 4, 0xFFFF, sum = 0
5741 23:22:43.387328 5, 0xFFFF, sum = 0
5742 23:22:43.390874 6, 0xFFFF, sum = 0
5743 23:22:43.390977 7, 0xFFFF, sum = 0
5744 23:22:43.393813 8, 0xFFFF, sum = 0
5745 23:22:43.393915 9, 0xFFFF, sum = 0
5746 23:22:43.397039 10, 0x0, sum = 1
5747 23:22:43.397114 11, 0x0, sum = 2
5748 23:22:43.400522 12, 0x0, sum = 3
5749 23:22:43.400624 13, 0x0, sum = 4
5750 23:22:43.403792 best_step = 11
5751 23:22:43.403863
5752 23:22:43.403928 ==
5753 23:22:43.407501 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 23:22:43.410305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 23:22:43.410405 ==
5756 23:22:43.410469 RX Vref Scan: 1
5757 23:22:43.413941
5758 23:22:43.414044 RX Vref 0 -> 0, step: 1
5759 23:22:43.414134
5760 23:22:43.416927 RX Delay -61 -> 252, step: 4
5761 23:22:43.417013
5762 23:22:43.420384 Set Vref, RX VrefLevel [Byte0]: 51
5763 23:22:43.423217 [Byte1]: 53
5764 23:22:43.426967
5765 23:22:43.427074 Final RX Vref Byte 0 = 51 to rank0
5766 23:22:43.430297 Final RX Vref Byte 1 = 53 to rank0
5767 23:22:43.434106 Final RX Vref Byte 0 = 51 to rank1
5768 23:22:43.437293 Final RX Vref Byte 1 = 53 to rank1==
5769 23:22:43.440044 Dram Type= 6, Freq= 0, CH_1, rank 0
5770 23:22:43.446833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 23:22:43.446939 ==
5772 23:22:43.447031 DQS Delay:
5773 23:22:43.449970 DQS0 = 0, DQS1 = 0
5774 23:22:43.450072 DQM Delay:
5775 23:22:43.450166 DQM0 = 98, DQM1 = 94
5776 23:22:43.453278 DQ Delay:
5777 23:22:43.456768 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =100
5778 23:22:43.460087 DQ4 =94, DQ5 =108, DQ6 =108, DQ7 =92
5779 23:22:43.463546 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =88
5780 23:22:43.466871 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5781 23:22:43.466973
5782 23:22:43.467064
5783 23:22:43.473062 [DQSOSCAuto] RK0, (LSB)MR18= 0xb1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5784 23:22:43.476860 CH1 RK0: MR19=505, MR18=B1B
5785 23:22:43.483119 CH1_RK0: MR19=0x505, MR18=0xB1B, DQSOSC=413, MR23=63, INC=63, DEC=42
5786 23:22:43.483225
5787 23:22:43.486320 ----->DramcWriteLeveling(PI) begin...
5788 23:22:43.486422 ==
5789 23:22:43.489580 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 23:22:43.492565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 23:22:43.496526 ==
5792 23:22:43.496602 Write leveling (Byte 0): 28 => 28
5793 23:22:43.499448 Write leveling (Byte 1): 28 => 28
5794 23:22:43.502791 DramcWriteLeveling(PI) end<-----
5795 23:22:43.502892
5796 23:22:43.502985 ==
5797 23:22:43.506094 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 23:22:43.512433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 23:22:43.512543 ==
5800 23:22:43.515814 [Gating] SW mode calibration
5801 23:22:43.522224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5802 23:22:43.525518 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5803 23:22:43.532627 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 23:22:43.536021 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 23:22:43.538806 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 23:22:43.545377 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 23:22:43.548670 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 23:22:43.552183 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 23:22:43.558313 0 14 24 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 0)
5810 23:22:43.561701 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5811 23:22:43.565041 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 23:22:43.572006 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 23:22:43.575235 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 23:22:43.578047 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 23:22:43.584773 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 23:22:43.588107 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 23:22:43.591438 0 15 24 | B1->B0 | 2b2b 3838 | 0 0 | (1 1) (1 1)
5818 23:22:43.597918 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5819 23:22:43.601094 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 23:22:43.604470 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 23:22:43.611157 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 23:22:43.614366 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 23:22:43.617415 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 23:22:43.624378 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 23:22:43.627631 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5826 23:22:43.630802 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5827 23:22:43.637400 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 23:22:43.640705 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 23:22:43.643827 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 23:22:43.650543 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 23:22:43.653698 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 23:22:43.657172 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 23:22:43.663681 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 23:22:43.667264 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 23:22:43.670094 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 23:22:43.676937 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 23:22:43.680150 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 23:22:43.683396 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 23:22:43.689900 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 23:22:43.693144 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 23:22:43.696356 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5842 23:22:43.699915 Total UI for P1: 0, mck2ui 16
5843 23:22:43.703178 best dqsien dly found for B0: ( 1, 2, 22)
5844 23:22:43.709798 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 23:22:43.709903 Total UI for P1: 0, mck2ui 16
5846 23:22:43.716484 best dqsien dly found for B1: ( 1, 2, 24)
5847 23:22:43.719700 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5848 23:22:43.722961 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5849 23:22:43.723058
5850 23:22:43.726243 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5851 23:22:43.729626 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5852 23:22:43.733043 [Gating] SW calibration Done
5853 23:22:43.733146 ==
5854 23:22:43.736128 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 23:22:43.739840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 23:22:43.739942 ==
5857 23:22:43.742618 RX Vref Scan: 0
5858 23:22:43.742731
5859 23:22:43.746034 RX Vref 0 -> 0, step: 1
5860 23:22:43.746141
5861 23:22:43.746238 RX Delay -80 -> 252, step: 8
5862 23:22:43.752560 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5863 23:22:43.756091 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5864 23:22:43.759243 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5865 23:22:43.762201 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5866 23:22:43.765959 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5867 23:22:43.768795 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5868 23:22:43.775651 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5869 23:22:43.778837 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5870 23:22:43.782094 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5871 23:22:43.785526 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5872 23:22:43.788435 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5873 23:22:43.795129 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5874 23:22:43.798512 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5875 23:22:43.802565 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5876 23:22:43.805146 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5877 23:22:43.808359 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5878 23:22:43.808458 ==
5879 23:22:43.811901 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 23:22:43.818617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 23:22:43.818708 ==
5882 23:22:43.818782 DQS Delay:
5883 23:22:43.821542 DQS0 = 0, DQS1 = 0
5884 23:22:43.821641 DQM Delay:
5885 23:22:43.824969 DQM0 = 97, DQM1 = 95
5886 23:22:43.825065 DQ Delay:
5887 23:22:43.828024 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5888 23:22:43.831339 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5889 23:22:43.834604 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5890 23:22:43.837928 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5891 23:22:43.838028
5892 23:22:43.838116
5893 23:22:43.838203 ==
5894 23:22:43.841325 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 23:22:43.844567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 23:22:43.844691 ==
5897 23:22:43.844800
5898 23:22:43.848381
5899 23:22:43.848499 TX Vref Scan disable
5900 23:22:43.851338 == TX Byte 0 ==
5901 23:22:43.854387 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5902 23:22:43.857720 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5903 23:22:43.861234 == TX Byte 1 ==
5904 23:22:43.864635 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5905 23:22:43.867961 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5906 23:22:43.868034 ==
5907 23:22:43.871096 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 23:22:43.877715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 23:22:43.877815 ==
5910 23:22:43.877905
5911 23:22:43.877992
5912 23:22:43.880996 TX Vref Scan disable
5913 23:22:43.881097 == TX Byte 0 ==
5914 23:22:43.887273 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5915 23:22:43.890675 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5916 23:22:43.890777 == TX Byte 1 ==
5917 23:22:43.897264 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5918 23:22:43.900214 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5919 23:22:43.900318
5920 23:22:43.900408 [DATLAT]
5921 23:22:43.904227 Freq=933, CH1 RK1
5922 23:22:43.904330
5923 23:22:43.904419 DATLAT Default: 0xb
5924 23:22:43.907253 0, 0xFFFF, sum = 0
5925 23:22:43.907382 1, 0xFFFF, sum = 0
5926 23:22:43.910070 2, 0xFFFF, sum = 0
5927 23:22:43.910177 3, 0xFFFF, sum = 0
5928 23:22:43.913563 4, 0xFFFF, sum = 0
5929 23:22:43.913688 5, 0xFFFF, sum = 0
5930 23:22:43.916632 6, 0xFFFF, sum = 0
5931 23:22:43.919927 7, 0xFFFF, sum = 0
5932 23:22:43.920029 8, 0xFFFF, sum = 0
5933 23:22:43.923318 9, 0xFFFF, sum = 0
5934 23:22:43.923466 10, 0x0, sum = 1
5935 23:22:43.926636 11, 0x0, sum = 2
5936 23:22:43.926737 12, 0x0, sum = 3
5937 23:22:43.926860 13, 0x0, sum = 4
5938 23:22:43.929694 best_step = 11
5939 23:22:43.929808
5940 23:22:43.929932 ==
5941 23:22:43.933367 Dram Type= 6, Freq= 0, CH_1, rank 1
5942 23:22:43.936777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5943 23:22:43.936893 ==
5944 23:22:43.940099 RX Vref Scan: 0
5945 23:22:43.940241
5946 23:22:43.943195 RX Vref 0 -> 0, step: 1
5947 23:22:43.943305
5948 23:22:43.943432 RX Delay -53 -> 252, step: 4
5949 23:22:43.950588 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5950 23:22:43.954237 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5951 23:22:43.957447 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5952 23:22:43.960442 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5953 23:22:43.963931 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5954 23:22:43.970459 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5955 23:22:43.973754 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5956 23:22:43.977296 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5957 23:22:43.980423 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5958 23:22:43.984051 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5959 23:22:43.987285 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5960 23:22:43.993878 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5961 23:22:43.997497 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5962 23:22:44.000083 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5963 23:22:44.003744 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5964 23:22:44.010251 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5965 23:22:44.010335 ==
5966 23:22:44.013259 Dram Type= 6, Freq= 0, CH_1, rank 1
5967 23:22:44.016582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5968 23:22:44.016667 ==
5969 23:22:44.016752 DQS Delay:
5970 23:22:44.020052 DQS0 = 0, DQS1 = 0
5971 23:22:44.020137 DQM Delay:
5972 23:22:44.023535 DQM0 = 96, DQM1 = 93
5973 23:22:44.023618 DQ Delay:
5974 23:22:44.026678 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5975 23:22:44.030255 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
5976 23:22:44.033485 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5977 23:22:44.036599 DQ12 =100, DQ13 =102, DQ14 =100, DQ15 =102
5978 23:22:44.036683
5979 23:22:44.036768
5980 23:22:44.046567 [DQSOSCAuto] RK1, (LSB)MR18= 0xd25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5981 23:22:44.046653 CH1 RK1: MR19=505, MR18=D25
5982 23:22:44.052775 CH1_RK1: MR19=0x505, MR18=0xD25, DQSOSC=410, MR23=63, INC=64, DEC=42
5983 23:22:44.056439 [RxdqsGatingPostProcess] freq 933
5984 23:22:44.062961 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5985 23:22:44.066156 best DQS0 dly(2T, 0.5T) = (0, 10)
5986 23:22:44.069261 best DQS1 dly(2T, 0.5T) = (0, 10)
5987 23:22:44.072906 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5988 23:22:44.076210 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5989 23:22:44.079516 best DQS0 dly(2T, 0.5T) = (0, 10)
5990 23:22:44.082875 best DQS1 dly(2T, 0.5T) = (0, 10)
5991 23:22:44.085643 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5992 23:22:44.089018 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5993 23:22:44.089101 Pre-setting of DQS Precalculation
5994 23:22:44.095892 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5995 23:22:44.102119 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5996 23:22:44.108683 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5997 23:22:44.108791
5998 23:22:44.108889
5999 23:22:44.112616 [Calibration Summary] 1866 Mbps
6000 23:22:44.115287 CH 0, Rank 0
6001 23:22:44.115414 SW Impedance : PASS
6002 23:22:44.118395 DUTY Scan : NO K
6003 23:22:44.122088 ZQ Calibration : PASS
6004 23:22:44.122213 Jitter Meter : NO K
6005 23:22:44.125576 CBT Training : PASS
6006 23:22:44.128482 Write leveling : PASS
6007 23:22:44.128605 RX DQS gating : PASS
6008 23:22:44.131829 RX DQ/DQS(RDDQC) : PASS
6009 23:22:44.134902 TX DQ/DQS : PASS
6010 23:22:44.135028 RX DATLAT : PASS
6011 23:22:44.138370 RX DQ/DQS(Engine): PASS
6012 23:22:44.141505 TX OE : NO K
6013 23:22:44.141609 All Pass.
6014 23:22:44.141700
6015 23:22:44.141793 CH 0, Rank 1
6016 23:22:44.144952 SW Impedance : PASS
6017 23:22:44.148439 DUTY Scan : NO K
6018 23:22:44.148514 ZQ Calibration : PASS
6019 23:22:44.151594 Jitter Meter : NO K
6020 23:22:44.155015 CBT Training : PASS
6021 23:22:44.155088 Write leveling : PASS
6022 23:22:44.158186 RX DQS gating : PASS
6023 23:22:44.161559 RX DQ/DQS(RDDQC) : PASS
6024 23:22:44.161633 TX DQ/DQS : PASS
6025 23:22:44.164457 RX DATLAT : PASS
6026 23:22:44.168064 RX DQ/DQS(Engine): PASS
6027 23:22:44.168194 TX OE : NO K
6028 23:22:44.168312 All Pass.
6029 23:22:44.171023
6030 23:22:44.171146 CH 1, Rank 0
6031 23:22:44.174684 SW Impedance : PASS
6032 23:22:44.174805 DUTY Scan : NO K
6033 23:22:44.177570 ZQ Calibration : PASS
6034 23:22:44.181074 Jitter Meter : NO K
6035 23:22:44.181199 CBT Training : PASS
6036 23:22:44.184153 Write leveling : PASS
6037 23:22:44.184278 RX DQS gating : PASS
6038 23:22:44.187576 RX DQ/DQS(RDDQC) : PASS
6039 23:22:44.191010 TX DQ/DQS : PASS
6040 23:22:44.191133 RX DATLAT : PASS
6041 23:22:44.194331 RX DQ/DQS(Engine): PASS
6042 23:22:44.197743 TX OE : NO K
6043 23:22:44.197869 All Pass.
6044 23:22:44.197984
6045 23:22:44.198097 CH 1, Rank 1
6046 23:22:44.201181 SW Impedance : PASS
6047 23:22:44.204357 DUTY Scan : NO K
6048 23:22:44.204483 ZQ Calibration : PASS
6049 23:22:44.207841 Jitter Meter : NO K
6050 23:22:44.210783 CBT Training : PASS
6051 23:22:44.210907 Write leveling : PASS
6052 23:22:44.214139 RX DQS gating : PASS
6053 23:22:44.217088 RX DQ/DQS(RDDQC) : PASS
6054 23:22:44.217210 TX DQ/DQS : PASS
6055 23:22:44.220870 RX DATLAT : PASS
6056 23:22:44.223606 RX DQ/DQS(Engine): PASS
6057 23:22:44.223735 TX OE : NO K
6058 23:22:44.227044 All Pass.
6059 23:22:44.227167
6060 23:22:44.227282 DramC Write-DBI off
6061 23:22:44.231003 PER_BANK_REFRESH: Hybrid Mode
6062 23:22:44.231128 TX_TRACKING: ON
6063 23:22:44.240623 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6064 23:22:44.243732 [FAST_K] Save calibration result to emmc
6065 23:22:44.247027 dramc_set_vcore_voltage set vcore to 650000
6066 23:22:44.250144 Read voltage for 400, 6
6067 23:22:44.250255 Vio18 = 0
6068 23:22:44.253531 Vcore = 650000
6069 23:22:44.253634 Vdram = 0
6070 23:22:44.253742 Vddq = 0
6071 23:22:44.256944 Vmddr = 0
6072 23:22:44.259997 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6073 23:22:44.267072 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6074 23:22:44.267175 MEM_TYPE=3, freq_sel=20
6075 23:22:44.269957 sv_algorithm_assistance_LP4_800
6076 23:22:44.276642 ============ PULL DRAM RESETB DOWN ============
6077 23:22:44.279876 ========== PULL DRAM RESETB DOWN end =========
6078 23:22:44.283438 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6079 23:22:44.286687 ===================================
6080 23:22:44.289581 LPDDR4 DRAM CONFIGURATION
6081 23:22:44.293377 ===================================
6082 23:22:44.296240 EX_ROW_EN[0] = 0x0
6083 23:22:44.296365 EX_ROW_EN[1] = 0x0
6084 23:22:44.299698 LP4Y_EN = 0x0
6085 23:22:44.299817 WORK_FSP = 0x0
6086 23:22:44.302894 WL = 0x2
6087 23:22:44.303018 RL = 0x2
6088 23:22:44.306650 BL = 0x2
6089 23:22:44.306757 RPST = 0x0
6090 23:22:44.309432 RD_PRE = 0x0
6091 23:22:44.309517 WR_PRE = 0x1
6092 23:22:44.313301 WR_PST = 0x0
6093 23:22:44.313383 DBI_WR = 0x0
6094 23:22:44.316219 DBI_RD = 0x0
6095 23:22:44.316306 OTF = 0x1
6096 23:22:44.319236 ===================================
6097 23:22:44.322796 ===================================
6098 23:22:44.326434 ANA top config
6099 23:22:44.329230 ===================================
6100 23:22:44.333035 DLL_ASYNC_EN = 0
6101 23:22:44.333113 ALL_SLAVE_EN = 1
6102 23:22:44.336148 NEW_RANK_MODE = 1
6103 23:22:44.339548 DLL_IDLE_MODE = 1
6104 23:22:44.343028 LP45_APHY_COMB_EN = 1
6105 23:22:44.343133 TX_ODT_DIS = 1
6106 23:22:44.346168 NEW_8X_MODE = 1
6107 23:22:44.349201 ===================================
6108 23:22:44.352585 ===================================
6109 23:22:44.355862 data_rate = 800
6110 23:22:44.359132 CKR = 1
6111 23:22:44.362429 DQ_P2S_RATIO = 4
6112 23:22:44.365956 ===================================
6113 23:22:44.369176 CA_P2S_RATIO = 4
6114 23:22:44.369282 DQ_CA_OPEN = 0
6115 23:22:44.372500 DQ_SEMI_OPEN = 1
6116 23:22:44.375746 CA_SEMI_OPEN = 1
6117 23:22:44.379141 CA_FULL_RATE = 0
6118 23:22:44.382637 DQ_CKDIV4_EN = 0
6119 23:22:44.385461 CA_CKDIV4_EN = 1
6120 23:22:44.385565 CA_PREDIV_EN = 0
6121 23:22:44.389231 PH8_DLY = 0
6122 23:22:44.392314 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6123 23:22:44.395597 DQ_AAMCK_DIV = 0
6124 23:22:44.399024 CA_AAMCK_DIV = 0
6125 23:22:44.402110 CA_ADMCK_DIV = 4
6126 23:22:44.402214 DQ_TRACK_CA_EN = 0
6127 23:22:44.405219 CA_PICK = 800
6128 23:22:44.408590 CA_MCKIO = 400
6129 23:22:44.411993 MCKIO_SEMI = 400
6130 23:22:44.415223 PLL_FREQ = 3016
6131 23:22:44.418761 DQ_UI_PI_RATIO = 32
6132 23:22:44.421732 CA_UI_PI_RATIO = 32
6133 23:22:44.425183 ===================================
6134 23:22:44.428482 ===================================
6135 23:22:44.432190 memory_type:LPDDR4
6136 23:22:44.432297 GP_NUM : 10
6137 23:22:44.435262 SRAM_EN : 1
6138 23:22:44.435386 MD32_EN : 0
6139 23:22:44.438372 ===================================
6140 23:22:44.442149 [ANA_INIT] >>>>>>>>>>>>>>
6141 23:22:44.444723 <<<<<< [CONFIGURE PHASE]: ANA_TX
6142 23:22:44.447981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6143 23:22:44.451215 ===================================
6144 23:22:44.454732 data_rate = 800,PCW = 0X7400
6145 23:22:44.458339 ===================================
6146 23:22:44.461131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6147 23:22:44.468136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6148 23:22:44.477841 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6149 23:22:44.480780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6150 23:22:44.484254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6151 23:22:44.491066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6152 23:22:44.491177 [ANA_INIT] flow start
6153 23:22:44.494179 [ANA_INIT] PLL >>>>>>>>
6154 23:22:44.497797 [ANA_INIT] PLL <<<<<<<<
6155 23:22:44.497896 [ANA_INIT] MIDPI >>>>>>>>
6156 23:22:44.500723 [ANA_INIT] MIDPI <<<<<<<<
6157 23:22:44.504260 [ANA_INIT] DLL >>>>>>>>
6158 23:22:44.504337 [ANA_INIT] flow end
6159 23:22:44.510410 ============ LP4 DIFF to SE enter ============
6160 23:22:44.513797 ============ LP4 DIFF to SE exit ============
6161 23:22:44.513871 [ANA_INIT] <<<<<<<<<<<<<
6162 23:22:44.517263 [Flow] Enable top DCM control >>>>>
6163 23:22:44.520551 [Flow] Enable top DCM control <<<<<
6164 23:22:44.524134 Enable DLL master slave shuffle
6165 23:22:44.530852 ==============================================================
6166 23:22:44.533832 Gating Mode config
6167 23:22:44.536878 ==============================================================
6168 23:22:44.540087 Config description:
6169 23:22:44.550012 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6170 23:22:44.556436 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6171 23:22:44.560049 SELPH_MODE 0: By rank 1: By Phase
6172 23:22:44.567017 ==============================================================
6173 23:22:44.569888 GAT_TRACK_EN = 0
6174 23:22:44.573198 RX_GATING_MODE = 2
6175 23:22:44.576435 RX_GATING_TRACK_MODE = 2
6176 23:22:44.579436 SELPH_MODE = 1
6177 23:22:44.582945 PICG_EARLY_EN = 1
6178 23:22:44.583052 VALID_LAT_VALUE = 1
6179 23:22:44.589535 ==============================================================
6180 23:22:44.592581 Enter into Gating configuration >>>>
6181 23:22:44.596106 Exit from Gating configuration <<<<
6182 23:22:44.599088 Enter into DVFS_PRE_config >>>>>
6183 23:22:44.609399 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6184 23:22:44.612501 Exit from DVFS_PRE_config <<<<<
6185 23:22:44.615812 Enter into PICG configuration >>>>
6186 23:22:44.619129 Exit from PICG configuration <<<<
6187 23:22:44.622095 [RX_INPUT] configuration >>>>>
6188 23:22:44.625337 [RX_INPUT] configuration <<<<<
6189 23:22:44.632018 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6190 23:22:44.635550 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6191 23:22:44.642073 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6192 23:22:44.648464 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6193 23:22:44.655341 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6194 23:22:44.661666 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6195 23:22:44.664890 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6196 23:22:44.668445 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6197 23:22:44.671675 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6198 23:22:44.678265 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6199 23:22:44.681524 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6200 23:22:44.684757 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6201 23:22:44.688185 ===================================
6202 23:22:44.691553 LPDDR4 DRAM CONFIGURATION
6203 23:22:44.694732 ===================================
6204 23:22:44.698023 EX_ROW_EN[0] = 0x0
6205 23:22:44.698108 EX_ROW_EN[1] = 0x0
6206 23:22:44.701322 LP4Y_EN = 0x0
6207 23:22:44.701405 WORK_FSP = 0x0
6208 23:22:44.704196 WL = 0x2
6209 23:22:44.704279 RL = 0x2
6210 23:22:44.707620 BL = 0x2
6211 23:22:44.707703 RPST = 0x0
6212 23:22:44.711206 RD_PRE = 0x0
6213 23:22:44.711292 WR_PRE = 0x1
6214 23:22:44.714490 WR_PST = 0x0
6215 23:22:44.717540 DBI_WR = 0x0
6216 23:22:44.717665 DBI_RD = 0x0
6217 23:22:44.720968 OTF = 0x1
6218 23:22:44.724050 ===================================
6219 23:22:44.727601 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6220 23:22:44.730845 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6221 23:22:44.734371 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6222 23:22:44.737549 ===================================
6223 23:22:44.740593 LPDDR4 DRAM CONFIGURATION
6224 23:22:44.743895 ===================================
6225 23:22:44.747116 EX_ROW_EN[0] = 0x10
6226 23:22:44.747198 EX_ROW_EN[1] = 0x0
6227 23:22:44.750468 LP4Y_EN = 0x0
6228 23:22:44.750551 WORK_FSP = 0x0
6229 23:22:44.754417 WL = 0x2
6230 23:22:44.754543 RL = 0x2
6231 23:22:44.757153 BL = 0x2
6232 23:22:44.757277 RPST = 0x0
6233 23:22:44.760786 RD_PRE = 0x0
6234 23:22:44.760916 WR_PRE = 0x1
6235 23:22:44.763756 WR_PST = 0x0
6236 23:22:44.767131 DBI_WR = 0x0
6237 23:22:44.767255 DBI_RD = 0x0
6238 23:22:44.770492 OTF = 0x1
6239 23:22:44.773935 ===================================
6240 23:22:44.777104 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6241 23:22:44.782322 nWR fixed to 30
6242 23:22:44.785404 [ModeRegInit_LP4] CH0 RK0
6243 23:22:44.785511 [ModeRegInit_LP4] CH0 RK1
6244 23:22:44.788598 [ModeRegInit_LP4] CH1 RK0
6245 23:22:44.792081 [ModeRegInit_LP4] CH1 RK1
6246 23:22:44.792195 match AC timing 19
6247 23:22:44.798484 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6248 23:22:44.802236 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6249 23:22:44.805528 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6250 23:22:44.812220 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6251 23:22:44.815169 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6252 23:22:44.815288 ==
6253 23:22:44.818379 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 23:22:44.822215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 23:22:44.822322 ==
6256 23:22:44.828505 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6257 23:22:44.835173 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6258 23:22:44.838318 [CA 0] Center 36 (8~64) winsize 57
6259 23:22:44.841928 [CA 1] Center 36 (8~64) winsize 57
6260 23:22:44.845183 [CA 2] Center 36 (8~64) winsize 57
6261 23:22:44.848327 [CA 3] Center 36 (8~64) winsize 57
6262 23:22:44.851751 [CA 4] Center 36 (8~64) winsize 57
6263 23:22:44.851852 [CA 5] Center 36 (8~64) winsize 57
6264 23:22:44.854711
6265 23:22:44.858228 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6266 23:22:44.858346
6267 23:22:44.861448 [CATrainingPosCal] consider 1 rank data
6268 23:22:44.864731 u2DelayCellTimex100 = 270/100 ps
6269 23:22:44.867807 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 23:22:44.871016 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 23:22:44.874517 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 23:22:44.877856 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 23:22:44.881278 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 23:22:44.884663 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 23:22:44.884762
6276 23:22:44.891335 CA PerBit enable=1, Macro0, CA PI delay=36
6277 23:22:44.891436
6278 23:22:44.891501 [CBTSetCACLKResult] CA Dly = 36
6279 23:22:44.894153 CS Dly: 1 (0~32)
6280 23:22:44.894249 ==
6281 23:22:44.897589 Dram Type= 6, Freq= 0, CH_0, rank 1
6282 23:22:44.900659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 23:22:44.900763 ==
6284 23:22:44.907628 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6285 23:22:44.913931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6286 23:22:44.917398 [CA 0] Center 36 (8~64) winsize 57
6287 23:22:44.920560 [CA 1] Center 36 (8~64) winsize 57
6288 23:22:44.924046 [CA 2] Center 36 (8~64) winsize 57
6289 23:22:44.927208 [CA 3] Center 36 (8~64) winsize 57
6290 23:22:44.930347 [CA 4] Center 36 (8~64) winsize 57
6291 23:22:44.930448 [CA 5] Center 36 (8~64) winsize 57
6292 23:22:44.933704
6293 23:22:44.937081 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6294 23:22:44.937188
6295 23:22:44.940268 [CATrainingPosCal] consider 2 rank data
6296 23:22:44.943611 u2DelayCellTimex100 = 270/100 ps
6297 23:22:44.947176 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 23:22:44.950060 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 23:22:44.953964 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 23:22:44.956779 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 23:22:44.960411 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 23:22:44.963443 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 23:22:44.963559
6304 23:22:44.966814 CA PerBit enable=1, Macro0, CA PI delay=36
6305 23:22:44.969871
6306 23:22:44.969974 [CBTSetCACLKResult] CA Dly = 36
6307 23:22:44.973289 CS Dly: 1 (0~32)
6308 23:22:44.973402
6309 23:22:44.976552 ----->DramcWriteLeveling(PI) begin...
6310 23:22:44.976666 ==
6311 23:22:44.980024 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 23:22:44.983012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 23:22:44.983116 ==
6314 23:22:44.986260 Write leveling (Byte 0): 40 => 8
6315 23:22:44.989709 Write leveling (Byte 1): 40 => 8
6316 23:22:44.992775 DramcWriteLeveling(PI) end<-----
6317 23:22:44.992881
6318 23:22:44.992985 ==
6319 23:22:44.996255 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 23:22:44.999775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 23:22:45.002922 ==
6322 23:22:45.003029 [Gating] SW mode calibration
6323 23:22:45.012703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6324 23:22:45.015684 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6325 23:22:45.019217 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6326 23:22:45.025573 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6327 23:22:45.029091 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6328 23:22:45.032446 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 23:22:45.038830 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 23:22:45.042268 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 23:22:45.045773 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 23:22:45.052014 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 23:22:45.055225 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6334 23:22:45.058591 Total UI for P1: 0, mck2ui 16
6335 23:22:45.061757 best dqsien dly found for B0: ( 0, 14, 24)
6336 23:22:45.065154 Total UI for P1: 0, mck2ui 16
6337 23:22:45.068489 best dqsien dly found for B1: ( 0, 14, 24)
6338 23:22:45.071913 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6339 23:22:45.074891 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6340 23:22:45.074966
6341 23:22:45.078558 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6342 23:22:45.085020 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6343 23:22:45.085104 [Gating] SW calibration Done
6344 23:22:45.085169 ==
6345 23:22:45.088345 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 23:22:45.095103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 23:22:45.095187 ==
6348 23:22:45.095252 RX Vref Scan: 0
6349 23:22:45.095313
6350 23:22:45.098262 RX Vref 0 -> 0, step: 1
6351 23:22:45.098345
6352 23:22:45.101677 RX Delay -410 -> 252, step: 16
6353 23:22:45.105006 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6354 23:22:45.108263 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6355 23:22:45.114612 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6356 23:22:45.117538 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6357 23:22:45.121114 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6358 23:22:45.127856 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6359 23:22:45.130939 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6360 23:22:45.134358 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6361 23:22:45.137254 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6362 23:22:45.144032 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6363 23:22:45.147328 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6364 23:22:45.150763 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6365 23:22:45.154077 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6366 23:22:45.160678 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6367 23:22:45.164137 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6368 23:22:45.167122 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6369 23:22:45.167232 ==
6370 23:22:45.170729 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 23:22:45.177111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 23:22:45.177198 ==
6373 23:22:45.177263 DQS Delay:
6374 23:22:45.180448 DQS0 = 35, DQS1 = 51
6375 23:22:45.180530 DQM Delay:
6376 23:22:45.180594 DQM0 = 4, DQM1 = 11
6377 23:22:45.183573 DQ Delay:
6378 23:22:45.187174 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6379 23:22:45.187282 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6380 23:22:45.190099 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6381 23:22:45.193700 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6382 23:22:45.193777
6383 23:22:45.193839
6384 23:22:45.196751 ==
6385 23:22:45.200507 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 23:22:45.203106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 23:22:45.203194 ==
6388 23:22:45.203260
6389 23:22:45.203321
6390 23:22:45.206447 TX Vref Scan disable
6391 23:22:45.206519 == TX Byte 0 ==
6392 23:22:45.209785 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6393 23:22:45.216214 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6394 23:22:45.216317 == TX Byte 1 ==
6395 23:22:45.219508 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6396 23:22:45.226266 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6397 23:22:45.226366 ==
6398 23:22:45.229363 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 23:22:45.232832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 23:22:45.232905 ==
6401 23:22:45.232966
6402 23:22:45.233023
6403 23:22:45.235922 TX Vref Scan disable
6404 23:22:45.236034 == TX Byte 0 ==
6405 23:22:45.242515 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 23:22:45.245784 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 23:22:45.245861 == TX Byte 1 ==
6408 23:22:45.252366 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6409 23:22:45.255896 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6410 23:22:45.255998
6411 23:22:45.256090 [DATLAT]
6412 23:22:45.259706 Freq=400, CH0 RK0
6413 23:22:45.259787
6414 23:22:45.259849 DATLAT Default: 0xf
6415 23:22:45.262505 0, 0xFFFF, sum = 0
6416 23:22:45.262587 1, 0xFFFF, sum = 0
6417 23:22:45.266097 2, 0xFFFF, sum = 0
6418 23:22:45.266180 3, 0xFFFF, sum = 0
6419 23:22:45.269055 4, 0xFFFF, sum = 0
6420 23:22:45.269138 5, 0xFFFF, sum = 0
6421 23:22:45.272821 6, 0xFFFF, sum = 0
6422 23:22:45.272904 7, 0xFFFF, sum = 0
6423 23:22:45.275728 8, 0xFFFF, sum = 0
6424 23:22:45.275828 9, 0xFFFF, sum = 0
6425 23:22:45.278832 10, 0xFFFF, sum = 0
6426 23:22:45.282260 11, 0xFFFF, sum = 0
6427 23:22:45.282341 12, 0xFFFF, sum = 0
6428 23:22:45.285555 13, 0x0, sum = 1
6429 23:22:45.285640 14, 0x0, sum = 2
6430 23:22:45.288659 15, 0x0, sum = 3
6431 23:22:45.288743 16, 0x0, sum = 4
6432 23:22:45.288808 best_step = 14
6433 23:22:45.288868
6434 23:22:45.291968 ==
6435 23:22:45.295600 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 23:22:45.298877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 23:22:45.298974 ==
6438 23:22:45.299052 RX Vref Scan: 1
6439 23:22:45.299126
6440 23:22:45.302204 RX Vref 0 -> 0, step: 1
6441 23:22:45.302291
6442 23:22:45.305704 RX Delay -343 -> 252, step: 8
6443 23:22:45.305798
6444 23:22:45.308386 Set Vref, RX VrefLevel [Byte0]: 53
6445 23:22:45.311654 [Byte1]: 59
6446 23:22:45.316226
6447 23:22:45.316307 Final RX Vref Byte 0 = 53 to rank0
6448 23:22:45.318755 Final RX Vref Byte 1 = 59 to rank0
6449 23:22:45.322012 Final RX Vref Byte 0 = 53 to rank1
6450 23:22:45.325363 Final RX Vref Byte 1 = 59 to rank1==
6451 23:22:45.328572 Dram Type= 6, Freq= 0, CH_0, rank 0
6452 23:22:45.335599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 23:22:45.335702 ==
6454 23:22:45.335793 DQS Delay:
6455 23:22:45.339132 DQS0 = 40, DQS1 = 60
6456 23:22:45.339254 DQM Delay:
6457 23:22:45.339349 DQM0 = 7, DQM1 = 16
6458 23:22:45.342080 DQ Delay:
6459 23:22:45.345196 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6460 23:22:45.345285 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6461 23:22:45.348955 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6462 23:22:45.351877 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6463 23:22:45.351979
6464 23:22:45.355230
6465 23:22:45.362200 [DQSOSCAuto] RK0, (LSB)MR18= 0x978a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6466 23:22:45.365401 CH0 RK0: MR19=C0C, MR18=978A
6467 23:22:45.371899 CH0_RK0: MR19=0xC0C, MR18=0x978A, DQSOSC=390, MR23=63, INC=388, DEC=258
6468 23:22:45.371983 ==
6469 23:22:45.375252 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 23:22:45.378685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 23:22:45.378768 ==
6472 23:22:45.381935 [Gating] SW mode calibration
6473 23:22:45.388271 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6474 23:22:45.394874 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6475 23:22:45.398211 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6476 23:22:45.401708 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6477 23:22:45.407868 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6478 23:22:45.411355 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 23:22:45.414407 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 23:22:45.421307 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 23:22:45.424505 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 23:22:45.427339 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 23:22:45.434746 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6484 23:22:45.434877 Total UI for P1: 0, mck2ui 16
6485 23:22:45.441284 best dqsien dly found for B0: ( 0, 14, 24)
6486 23:22:45.441370 Total UI for P1: 0, mck2ui 16
6487 23:22:45.447348 best dqsien dly found for B1: ( 0, 14, 24)
6488 23:22:45.450812 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6489 23:22:45.454185 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6490 23:22:45.454298
6491 23:22:45.457570 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6492 23:22:45.460814 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6493 23:22:45.463805 [Gating] SW calibration Done
6494 23:22:45.463904 ==
6495 23:22:45.467379 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 23:22:45.470855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 23:22:45.470933 ==
6498 23:22:45.473714 RX Vref Scan: 0
6499 23:22:45.473815
6500 23:22:45.473904 RX Vref 0 -> 0, step: 1
6501 23:22:45.477185
6502 23:22:45.477260 RX Delay -410 -> 252, step: 16
6503 23:22:45.483932 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6504 23:22:45.487135 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6505 23:22:45.490218 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6506 23:22:45.496785 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6507 23:22:45.500382 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6508 23:22:45.503683 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6509 23:22:45.506838 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6510 23:22:45.513106 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6511 23:22:45.516327 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6512 23:22:45.519864 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6513 23:22:45.523374 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6514 23:22:45.529586 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6515 23:22:45.533085 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6516 23:22:45.536378 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6517 23:22:45.539816 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6518 23:22:45.546011 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6519 23:22:45.546105 ==
6520 23:22:45.549381 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 23:22:45.552884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 23:22:45.552968 ==
6523 23:22:45.555937 DQS Delay:
6524 23:22:45.556013 DQS0 = 35, DQS1 = 59
6525 23:22:45.556075 DQM Delay:
6526 23:22:45.559573 DQM0 = 6, DQM1 = 17
6527 23:22:45.559652 DQ Delay:
6528 23:22:45.562291 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6529 23:22:45.565719 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6530 23:22:45.569360 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6531 23:22:45.572342 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6532 23:22:45.572425
6533 23:22:45.572490
6534 23:22:45.572550 ==
6535 23:22:45.575804 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 23:22:45.578738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 23:22:45.578863 ==
6538 23:22:45.582126
6539 23:22:45.582245
6540 23:22:45.582356 TX Vref Scan disable
6541 23:22:45.585396 == TX Byte 0 ==
6542 23:22:45.589129 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6543 23:22:45.592278 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6544 23:22:45.595516 == TX Byte 1 ==
6545 23:22:45.599182 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6546 23:22:45.602403 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6547 23:22:45.602525 ==
6548 23:22:45.605204 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 23:22:45.609370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 23:22:45.612381 ==
6551 23:22:45.612518
6552 23:22:45.612632
6553 23:22:45.612764 TX Vref Scan disable
6554 23:22:45.615192 == TX Byte 0 ==
6555 23:22:45.618232 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6556 23:22:45.621791 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6557 23:22:45.625302 == TX Byte 1 ==
6558 23:22:45.628434 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6559 23:22:45.632112 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6560 23:22:45.632242
6561 23:22:45.635431 [DATLAT]
6562 23:22:45.635533 Freq=400, CH0 RK1
6563 23:22:45.635636
6564 23:22:45.638570 DATLAT Default: 0xe
6565 23:22:45.638671 0, 0xFFFF, sum = 0
6566 23:22:45.641713 1, 0xFFFF, sum = 0
6567 23:22:45.641813 2, 0xFFFF, sum = 0
6568 23:22:45.644807 3, 0xFFFF, sum = 0
6569 23:22:45.644882 4, 0xFFFF, sum = 0
6570 23:22:45.648132 5, 0xFFFF, sum = 0
6571 23:22:45.648215 6, 0xFFFF, sum = 0
6572 23:22:45.651614 7, 0xFFFF, sum = 0
6573 23:22:45.651686 8, 0xFFFF, sum = 0
6574 23:22:45.655008 9, 0xFFFF, sum = 0
6575 23:22:45.655121 10, 0xFFFF, sum = 0
6576 23:22:45.657863 11, 0xFFFF, sum = 0
6577 23:22:45.661378 12, 0xFFFF, sum = 0
6578 23:22:45.661449 13, 0x0, sum = 1
6579 23:22:45.664484 14, 0x0, sum = 2
6580 23:22:45.664561 15, 0x0, sum = 3
6581 23:22:45.664621 16, 0x0, sum = 4
6582 23:22:45.667665 best_step = 14
6583 23:22:45.667738
6584 23:22:45.667806 ==
6585 23:22:45.671209 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 23:22:45.674581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 23:22:45.674674 ==
6588 23:22:45.677998 RX Vref Scan: 0
6589 23:22:45.678130
6590 23:22:45.681295 RX Vref 0 -> 0, step: 1
6591 23:22:45.681425
6592 23:22:45.681536 RX Delay -359 -> 252, step: 8
6593 23:22:45.689999 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6594 23:22:45.693054 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6595 23:22:45.696270 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6596 23:22:45.699820 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6597 23:22:45.705853 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6598 23:22:45.709567 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6599 23:22:45.712967 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6600 23:22:45.719670 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6601 23:22:45.722784 iDelay=209, Bit 8, Center -56 (-303 ~ 192) 496
6602 23:22:45.726180 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6603 23:22:45.728929 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6604 23:22:45.735946 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6605 23:22:45.738811 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6606 23:22:45.742231 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6607 23:22:45.745875 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6608 23:22:45.752128 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6609 23:22:45.752210 ==
6610 23:22:45.755377 Dram Type= 6, Freq= 0, CH_0, rank 1
6611 23:22:45.758591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 23:22:45.758665 ==
6613 23:22:45.758730 DQS Delay:
6614 23:22:45.762587 DQS0 = 44, DQS1 = 60
6615 23:22:45.762657 DQM Delay:
6616 23:22:45.765246 DQM0 = 9, DQM1 = 15
6617 23:22:45.765331 DQ Delay:
6618 23:22:45.768757 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6619 23:22:45.771710 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6620 23:22:45.775547 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6621 23:22:45.778316 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6622 23:22:45.778386
6623 23:22:45.778445
6624 23:22:45.788164 [DQSOSCAuto] RK1, (LSB)MR18= 0x847d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6625 23:22:45.788269 CH0 RK1: MR19=C0C, MR18=847D
6626 23:22:45.794835 CH0_RK1: MR19=0xC0C, MR18=0x847D, DQSOSC=393, MR23=63, INC=382, DEC=254
6627 23:22:45.798496 [RxdqsGatingPostProcess] freq 400
6628 23:22:45.804641 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6629 23:22:45.808584 best DQS0 dly(2T, 0.5T) = (0, 10)
6630 23:22:45.811295 best DQS1 dly(2T, 0.5T) = (0, 10)
6631 23:22:45.814619 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6632 23:22:45.817866 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6633 23:22:45.820984 best DQS0 dly(2T, 0.5T) = (0, 10)
6634 23:22:45.824782 best DQS1 dly(2T, 0.5T) = (0, 10)
6635 23:22:45.828121 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6636 23:22:45.828207 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6637 23:22:45.831252 Pre-setting of DQS Precalculation
6638 23:22:45.838139 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6639 23:22:45.838221 ==
6640 23:22:45.841289 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 23:22:45.844465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 23:22:45.844540 ==
6643 23:22:45.850714 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6644 23:22:45.857411 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6645 23:22:45.860985 [CA 0] Center 36 (8~64) winsize 57
6646 23:22:45.864314 [CA 1] Center 36 (8~64) winsize 57
6647 23:22:45.867572 [CA 2] Center 36 (8~64) winsize 57
6648 23:22:45.870876 [CA 3] Center 36 (8~64) winsize 57
6649 23:22:45.871010 [CA 4] Center 36 (8~64) winsize 57
6650 23:22:45.874143 [CA 5] Center 36 (8~64) winsize 57
6651 23:22:45.874248
6652 23:22:45.880388 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6653 23:22:45.880511
6654 23:22:45.883784 [CATrainingPosCal] consider 1 rank data
6655 23:22:45.886937 u2DelayCellTimex100 = 270/100 ps
6656 23:22:45.890856 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 23:22:45.893584 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 23:22:45.896815 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 23:22:45.900243 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 23:22:45.903520 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 23:22:45.906668 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 23:22:45.906791
6663 23:22:45.910140 CA PerBit enable=1, Macro0, CA PI delay=36
6664 23:22:45.910263
6665 23:22:45.913431 [CBTSetCACLKResult] CA Dly = 36
6666 23:22:45.916977 CS Dly: 1 (0~32)
6667 23:22:45.917106 ==
6668 23:22:45.920311 Dram Type= 6, Freq= 0, CH_1, rank 1
6669 23:22:45.923231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 23:22:45.923329 ==
6671 23:22:45.930208 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6672 23:22:45.936168 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6673 23:22:45.939728 [CA 0] Center 36 (8~64) winsize 57
6674 23:22:45.942862 [CA 1] Center 36 (8~64) winsize 57
6675 23:22:45.946463 [CA 2] Center 36 (8~64) winsize 57
6676 23:22:45.946583 [CA 3] Center 36 (8~64) winsize 57
6677 23:22:45.949735 [CA 4] Center 36 (8~64) winsize 57
6678 23:22:45.952607 [CA 5] Center 36 (8~64) winsize 57
6679 23:22:45.952729
6680 23:22:45.959240 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6681 23:22:45.959370
6682 23:22:45.962609 [CATrainingPosCal] consider 2 rank data
6683 23:22:45.966338 u2DelayCellTimex100 = 270/100 ps
6684 23:22:45.969344 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 23:22:45.972474 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 23:22:45.975950 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 23:22:45.979269 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 23:22:45.982486 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 23:22:45.985528 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 23:22:45.985614
6691 23:22:45.988897 CA PerBit enable=1, Macro0, CA PI delay=36
6692 23:22:45.988979
6693 23:22:45.992426 [CBTSetCACLKResult] CA Dly = 36
6694 23:22:45.995783 CS Dly: 1 (0~32)
6695 23:22:45.995865
6696 23:22:45.998776 ----->DramcWriteLeveling(PI) begin...
6697 23:22:45.998900 ==
6698 23:22:46.002248 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 23:22:46.005946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 23:22:46.006070 ==
6701 23:22:46.008468 Write leveling (Byte 0): 40 => 8
6702 23:22:46.012059 Write leveling (Byte 1): 40 => 8
6703 23:22:46.015535 DramcWriteLeveling(PI) end<-----
6704 23:22:46.015656
6705 23:22:46.015771 ==
6706 23:22:46.018476 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 23:22:46.021679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 23:22:46.021810 ==
6709 23:22:46.025295 [Gating] SW mode calibration
6710 23:22:46.031591 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6711 23:22:46.038310 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6712 23:22:46.041474 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6713 23:22:46.048443 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6714 23:22:46.051333 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6715 23:22:46.054638 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 23:22:46.061250 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 23:22:46.064457 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 23:22:46.068083 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 23:22:46.074610 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 23:22:46.077922 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6721 23:22:46.081510 Total UI for P1: 0, mck2ui 16
6722 23:22:46.084605 best dqsien dly found for B0: ( 0, 14, 24)
6723 23:22:46.087945 Total UI for P1: 0, mck2ui 16
6724 23:22:46.091042 best dqsien dly found for B1: ( 0, 14, 24)
6725 23:22:46.094339 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6726 23:22:46.097234 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6727 23:22:46.097307
6728 23:22:46.100889 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6729 23:22:46.104281 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6730 23:22:46.107384 [Gating] SW calibration Done
6731 23:22:46.107459 ==
6732 23:22:46.110791 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 23:22:46.117313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 23:22:46.117444 ==
6735 23:22:46.117559 RX Vref Scan: 0
6736 23:22:46.117673
6737 23:22:46.120631 RX Vref 0 -> 0, step: 1
6738 23:22:46.120757
6739 23:22:46.123889 RX Delay -410 -> 252, step: 16
6740 23:22:46.126840 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6741 23:22:46.130302 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6742 23:22:46.136639 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6743 23:22:46.140061 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6744 23:22:46.143351 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6745 23:22:46.146474 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6746 23:22:46.153276 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6747 23:22:46.156740 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6748 23:22:46.160164 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6749 23:22:46.163308 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6750 23:22:46.170174 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6751 23:22:46.173427 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6752 23:22:46.176481 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6753 23:22:46.182864 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6754 23:22:46.186104 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6755 23:22:46.189476 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6756 23:22:46.189567 ==
6757 23:22:46.193104 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 23:22:46.196264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 23:22:46.199353 ==
6760 23:22:46.199433 DQS Delay:
6761 23:22:46.199495 DQS0 = 35, DQS1 = 51
6762 23:22:46.202501 DQM Delay:
6763 23:22:46.202579 DQM0 = 6, DQM1 = 13
6764 23:22:46.205782 DQ Delay:
6765 23:22:46.205859 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6766 23:22:46.208981 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6767 23:22:46.212977 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6768 23:22:46.216064 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6769 23:22:46.216165
6770 23:22:46.216264
6771 23:22:46.218822 ==
6772 23:22:46.222543 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 23:22:46.226075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 23:22:46.226170 ==
6775 23:22:46.226269
6776 23:22:46.226367
6777 23:22:46.229155 TX Vref Scan disable
6778 23:22:46.229271 == TX Byte 0 ==
6779 23:22:46.232181 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6780 23:22:46.238776 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6781 23:22:46.238902 == TX Byte 1 ==
6782 23:22:46.242614 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6783 23:22:46.248719 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6784 23:22:46.248847 ==
6785 23:22:46.251977 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 23:22:46.255266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 23:22:46.255379 ==
6788 23:22:46.255481
6789 23:22:46.255572
6790 23:22:46.258567 TX Vref Scan disable
6791 23:22:46.258662 == TX Byte 0 ==
6792 23:22:46.261825 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 23:22:46.268558 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 23:22:46.268641 == TX Byte 1 ==
6795 23:22:46.271967 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6796 23:22:46.278239 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6797 23:22:46.278322
6798 23:22:46.278388 [DATLAT]
6799 23:22:46.281671 Freq=400, CH1 RK0
6800 23:22:46.281749
6801 23:22:46.281811 DATLAT Default: 0xf
6802 23:22:46.284832 0, 0xFFFF, sum = 0
6803 23:22:46.284962 1, 0xFFFF, sum = 0
6804 23:22:46.288290 2, 0xFFFF, sum = 0
6805 23:22:46.288423 3, 0xFFFF, sum = 0
6806 23:22:46.291454 4, 0xFFFF, sum = 0
6807 23:22:46.291587 5, 0xFFFF, sum = 0
6808 23:22:46.294760 6, 0xFFFF, sum = 0
6809 23:22:46.294884 7, 0xFFFF, sum = 0
6810 23:22:46.298257 8, 0xFFFF, sum = 0
6811 23:22:46.298383 9, 0xFFFF, sum = 0
6812 23:22:46.301266 10, 0xFFFF, sum = 0
6813 23:22:46.301395 11, 0xFFFF, sum = 0
6814 23:22:46.304619 12, 0xFFFF, sum = 0
6815 23:22:46.304735 13, 0x0, sum = 1
6816 23:22:46.308072 14, 0x0, sum = 2
6817 23:22:46.308196 15, 0x0, sum = 3
6818 23:22:46.311083 16, 0x0, sum = 4
6819 23:22:46.311205 best_step = 14
6820 23:22:46.311322
6821 23:22:46.311467 ==
6822 23:22:46.314520 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 23:22:46.320948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 23:22:46.321066 ==
6825 23:22:46.321166 RX Vref Scan: 1
6826 23:22:46.321255
6827 23:22:46.324266 RX Vref 0 -> 0, step: 1
6828 23:22:46.324341
6829 23:22:46.327493 RX Delay -343 -> 252, step: 8
6830 23:22:46.327598
6831 23:22:46.330678 Set Vref, RX VrefLevel [Byte0]: 51
6832 23:22:46.334039 [Byte1]: 53
6833 23:22:46.337565
6834 23:22:46.337640 Final RX Vref Byte 0 = 51 to rank0
6835 23:22:46.340878 Final RX Vref Byte 1 = 53 to rank0
6836 23:22:46.344348 Final RX Vref Byte 0 = 51 to rank1
6837 23:22:46.348063 Final RX Vref Byte 1 = 53 to rank1==
6838 23:22:46.350947 Dram Type= 6, Freq= 0, CH_1, rank 0
6839 23:22:46.357402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 23:22:46.357523 ==
6841 23:22:46.357616 DQS Delay:
6842 23:22:46.360865 DQS0 = 44, DQS1 = 52
6843 23:22:46.360945 DQM Delay:
6844 23:22:46.361019 DQM0 = 9, DQM1 = 9
6845 23:22:46.364296 DQ Delay:
6846 23:22:46.367550 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6847 23:22:46.367630 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6848 23:22:46.370841 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6849 23:22:46.373811 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6850 23:22:46.373899
6851 23:22:46.377644
6852 23:22:46.384000 [DQSOSCAuto] RK0, (LSB)MR18= 0x648b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6853 23:22:46.386690 CH1 RK0: MR19=C0C, MR18=648B
6854 23:22:46.393419 CH1_RK0: MR19=0xC0C, MR18=0x648B, DQSOSC=392, MR23=63, INC=384, DEC=256
6855 23:22:46.393500 ==
6856 23:22:46.396925 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 23:22:46.400004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 23:22:46.400094 ==
6859 23:22:46.403167 [Gating] SW mode calibration
6860 23:22:46.409960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6861 23:22:46.416679 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6862 23:22:46.420088 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6863 23:22:46.423037 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6864 23:22:46.429656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6865 23:22:46.432906 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 23:22:46.436136 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 23:22:46.442863 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 23:22:46.445791 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 23:22:46.449173 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 23:22:46.456138 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6871 23:22:46.459481 Total UI for P1: 0, mck2ui 16
6872 23:22:46.462209 best dqsien dly found for B0: ( 0, 14, 24)
6873 23:22:46.465458 Total UI for P1: 0, mck2ui 16
6874 23:22:46.468789 best dqsien dly found for B1: ( 0, 14, 24)
6875 23:22:46.472350 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6876 23:22:46.475572 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6877 23:22:46.475657
6878 23:22:46.479048 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6879 23:22:46.481883 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6880 23:22:46.485482 [Gating] SW calibration Done
6881 23:22:46.485590 ==
6882 23:22:46.488381 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 23:22:46.491957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 23:22:46.495176 ==
6885 23:22:46.495292 RX Vref Scan: 0
6886 23:22:46.495426
6887 23:22:46.498514 RX Vref 0 -> 0, step: 1
6888 23:22:46.498588
6889 23:22:46.501488 RX Delay -410 -> 252, step: 16
6890 23:22:46.505027 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6891 23:22:46.508214 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6892 23:22:46.511509 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6893 23:22:46.518292 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6894 23:22:46.521777 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6895 23:22:46.524942 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6896 23:22:46.528400 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6897 23:22:46.534793 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6898 23:22:46.537951 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6899 23:22:46.541373 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6900 23:22:46.544712 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6901 23:22:46.551350 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6902 23:22:46.554500 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6903 23:22:46.557799 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6904 23:22:46.564148 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6905 23:22:46.567455 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6906 23:22:46.567530 ==
6907 23:22:46.570753 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 23:22:46.574046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 23:22:46.574127 ==
6910 23:22:46.577614 DQS Delay:
6911 23:22:46.577694 DQS0 = 43, DQS1 = 51
6912 23:22:46.577755 DQM Delay:
6913 23:22:46.581007 DQM0 = 9, DQM1 = 14
6914 23:22:46.581075 DQ Delay:
6915 23:22:46.584339 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6916 23:22:46.587677 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6917 23:22:46.590747 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6918 23:22:46.594003 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6919 23:22:46.594080
6920 23:22:46.594143
6921 23:22:46.594202 ==
6922 23:22:46.597530 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 23:22:46.600891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 23:22:46.604235 ==
6925 23:22:46.604373
6926 23:22:46.604471
6927 23:22:46.604563 TX Vref Scan disable
6928 23:22:46.607218 == TX Byte 0 ==
6929 23:22:46.610732 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6930 23:22:46.613828 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6931 23:22:46.616970 == TX Byte 1 ==
6932 23:22:46.620210 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6933 23:22:46.623668 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6934 23:22:46.623779 ==
6935 23:22:46.627068 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 23:22:46.633355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 23:22:46.633463 ==
6938 23:22:46.633575
6939 23:22:46.633677
6940 23:22:46.633773 TX Vref Scan disable
6941 23:22:46.636926 == TX Byte 0 ==
6942 23:22:46.640045 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6943 23:22:46.643393 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6944 23:22:46.646407 == TX Byte 1 ==
6945 23:22:46.649480 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6946 23:22:46.653209 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6947 23:22:46.653288
6948 23:22:46.656294 [DATLAT]
6949 23:22:46.656367 Freq=400, CH1 RK1
6950 23:22:46.656438
6951 23:22:46.659541 DATLAT Default: 0xe
6952 23:22:46.659613 0, 0xFFFF, sum = 0
6953 23:22:46.662995 1, 0xFFFF, sum = 0
6954 23:22:46.663095 2, 0xFFFF, sum = 0
6955 23:22:46.666410 3, 0xFFFF, sum = 0
6956 23:22:46.666494 4, 0xFFFF, sum = 0
6957 23:22:46.669366 5, 0xFFFF, sum = 0
6958 23:22:46.672667 6, 0xFFFF, sum = 0
6959 23:22:46.672739 7, 0xFFFF, sum = 0
6960 23:22:46.676063 8, 0xFFFF, sum = 0
6961 23:22:46.676135 9, 0xFFFF, sum = 0
6962 23:22:46.679394 10, 0xFFFF, sum = 0
6963 23:22:46.679467 11, 0xFFFF, sum = 0
6964 23:22:46.682715 12, 0xFFFF, sum = 0
6965 23:22:46.682784 13, 0x0, sum = 1
6966 23:22:46.686229 14, 0x0, sum = 2
6967 23:22:46.686317 15, 0x0, sum = 3
6968 23:22:46.688981 16, 0x0, sum = 4
6969 23:22:46.689054 best_step = 14
6970 23:22:46.689121
6971 23:22:46.689180 ==
6972 23:22:46.692861 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 23:22:46.695847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 23:22:46.699105 ==
6975 23:22:46.699185 RX Vref Scan: 0
6976 23:22:46.699247
6977 23:22:46.702718 RX Vref 0 -> 0, step: 1
6978 23:22:46.702787
6979 23:22:46.705827 RX Delay -343 -> 252, step: 8
6980 23:22:46.709199 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6981 23:22:46.715585 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6982 23:22:46.718927 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6983 23:22:46.721939 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6984 23:22:46.728518 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6985 23:22:46.731924 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6986 23:22:46.735597 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6987 23:22:46.738656 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6988 23:22:46.744985 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6989 23:22:46.748519 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6990 23:22:46.751571 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6991 23:22:46.754802 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6992 23:22:46.761557 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6993 23:22:46.765026 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6994 23:22:46.768059 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6995 23:22:46.774697 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6996 23:22:46.774781 ==
6997 23:22:46.778068 Dram Type= 6, Freq= 0, CH_1, rank 1
6998 23:22:46.781313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6999 23:22:46.781426 ==
7000 23:22:46.781517 DQS Delay:
7001 23:22:46.784621 DQS0 = 48, DQS1 = 52
7002 23:22:46.784702 DQM Delay:
7003 23:22:46.788015 DQM0 = 11, DQM1 = 10
7004 23:22:46.788116 DQ Delay:
7005 23:22:46.791035 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
7006 23:22:46.794443 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7007 23:22:46.797693 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7008 23:22:46.801479 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7009 23:22:46.801565
7010 23:22:46.801628
7011 23:22:46.807677 [DQSOSCAuto] RK1, (LSB)MR18= 0x6fa7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7012 23:22:46.811079 CH1 RK1: MR19=C0C, MR18=6FA7
7013 23:22:46.817421 CH1_RK1: MR19=0xC0C, MR18=0x6FA7, DQSOSC=389, MR23=63, INC=390, DEC=260
7014 23:22:46.820841 [RxdqsGatingPostProcess] freq 400
7015 23:22:46.827729 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7016 23:22:46.830672 best DQS0 dly(2T, 0.5T) = (0, 10)
7017 23:22:46.830744 best DQS1 dly(2T, 0.5T) = (0, 10)
7018 23:22:46.833913 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7019 23:22:46.837220 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7020 23:22:46.840405 best DQS0 dly(2T, 0.5T) = (0, 10)
7021 23:22:46.844156 best DQS1 dly(2T, 0.5T) = (0, 10)
7022 23:22:46.847129 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7023 23:22:46.850967 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7024 23:22:46.854045 Pre-setting of DQS Precalculation
7025 23:22:46.860385 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7026 23:22:46.866704 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7027 23:22:46.874022 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7028 23:22:46.874102
7029 23:22:46.874167
7030 23:22:46.876872 [Calibration Summary] 800 Mbps
7031 23:22:46.876946 CH 0, Rank 0
7032 23:22:46.880014 SW Impedance : PASS
7033 23:22:46.883756 DUTY Scan : NO K
7034 23:22:46.883830 ZQ Calibration : PASS
7035 23:22:46.886761 Jitter Meter : NO K
7036 23:22:46.889800 CBT Training : PASS
7037 23:22:46.889875 Write leveling : PASS
7038 23:22:46.893420 RX DQS gating : PASS
7039 23:22:46.896440 RX DQ/DQS(RDDQC) : PASS
7040 23:22:46.896518 TX DQ/DQS : PASS
7041 23:22:46.899677 RX DATLAT : PASS
7042 23:22:46.903059 RX DQ/DQS(Engine): PASS
7043 23:22:46.903160 TX OE : NO K
7044 23:22:46.906556 All Pass.
7045 23:22:46.906632
7046 23:22:46.906694 CH 0, Rank 1
7047 23:22:46.909762 SW Impedance : PASS
7048 23:22:46.909833 DUTY Scan : NO K
7049 23:22:46.913033 ZQ Calibration : PASS
7050 23:22:46.916379 Jitter Meter : NO K
7051 23:22:46.916456 CBT Training : PASS
7052 23:22:46.919783 Write leveling : NO K
7053 23:22:46.923187 RX DQS gating : PASS
7054 23:22:46.923285 RX DQ/DQS(RDDQC) : PASS
7055 23:22:46.926300 TX DQ/DQS : PASS
7056 23:22:46.929529 RX DATLAT : PASS
7057 23:22:46.929602 RX DQ/DQS(Engine): PASS
7058 23:22:46.932806 TX OE : NO K
7059 23:22:46.932878 All Pass.
7060 23:22:46.932938
7061 23:22:46.936116 CH 1, Rank 0
7062 23:22:46.936186 SW Impedance : PASS
7063 23:22:46.939658 DUTY Scan : NO K
7064 23:22:46.939735 ZQ Calibration : PASS
7065 23:22:46.942579 Jitter Meter : NO K
7066 23:22:46.946084 CBT Training : PASS
7067 23:22:46.946157 Write leveling : PASS
7068 23:22:46.949216 RX DQS gating : PASS
7069 23:22:46.952252 RX DQ/DQS(RDDQC) : PASS
7070 23:22:46.952357 TX DQ/DQS : PASS
7071 23:22:46.956242 RX DATLAT : PASS
7072 23:22:46.959049 RX DQ/DQS(Engine): PASS
7073 23:22:46.959148 TX OE : NO K
7074 23:22:46.962437 All Pass.
7075 23:22:46.962519
7076 23:22:46.962593 CH 1, Rank 1
7077 23:22:46.965619 SW Impedance : PASS
7078 23:22:46.965701 DUTY Scan : NO K
7079 23:22:46.968791 ZQ Calibration : PASS
7080 23:22:46.972265 Jitter Meter : NO K
7081 23:22:46.972341 CBT Training : PASS
7082 23:22:46.975288 Write leveling : NO K
7083 23:22:46.978998 RX DQS gating : PASS
7084 23:22:46.979074 RX DQ/DQS(RDDQC) : PASS
7085 23:22:46.982016 TX DQ/DQS : PASS
7086 23:22:46.985567 RX DATLAT : PASS
7087 23:22:46.985644 RX DQ/DQS(Engine): PASS
7088 23:22:46.988622 TX OE : NO K
7089 23:22:46.988701 All Pass.
7090 23:22:46.988766
7091 23:22:46.991654 DramC Write-DBI off
7092 23:22:46.995346 PER_BANK_REFRESH: Hybrid Mode
7093 23:22:46.995457 TX_TRACKING: ON
7094 23:22:47.005199 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7095 23:22:47.008221 [FAST_K] Save calibration result to emmc
7096 23:22:47.011658 dramc_set_vcore_voltage set vcore to 725000
7097 23:22:47.015091 Read voltage for 1600, 0
7098 23:22:47.015162 Vio18 = 0
7099 23:22:47.015231 Vcore = 725000
7100 23:22:47.018499 Vdram = 0
7101 23:22:47.018598 Vddq = 0
7102 23:22:47.018688 Vmddr = 0
7103 23:22:47.025223 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7104 23:22:47.028458 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7105 23:22:47.031387 MEM_TYPE=3, freq_sel=13
7106 23:22:47.034753 sv_algorithm_assistance_LP4_3733
7107 23:22:47.037876 ============ PULL DRAM RESETB DOWN ============
7108 23:22:47.044466 ========== PULL DRAM RESETB DOWN end =========
7109 23:22:47.047871 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7110 23:22:47.051047 ===================================
7111 23:22:47.054159 LPDDR4 DRAM CONFIGURATION
7112 23:22:47.057495 ===================================
7113 23:22:47.057584 EX_ROW_EN[0] = 0x0
7114 23:22:47.061107 EX_ROW_EN[1] = 0x0
7115 23:22:47.061176 LP4Y_EN = 0x0
7116 23:22:47.064261 WORK_FSP = 0x1
7117 23:22:47.067807 WL = 0x5
7118 23:22:47.067905 RL = 0x5
7119 23:22:47.071001 BL = 0x2
7120 23:22:47.071079 RPST = 0x0
7121 23:22:47.073944 RD_PRE = 0x0
7122 23:22:47.074016 WR_PRE = 0x1
7123 23:22:47.077458 WR_PST = 0x1
7124 23:22:47.077545 DBI_WR = 0x0
7125 23:22:47.080797 DBI_RD = 0x0
7126 23:22:47.080892 OTF = 0x1
7127 23:22:47.083764 ===================================
7128 23:22:47.087374 ===================================
7129 23:22:47.090212 ANA top config
7130 23:22:47.093566 ===================================
7131 23:22:47.093639 DLL_ASYNC_EN = 0
7132 23:22:47.096967 ALL_SLAVE_EN = 0
7133 23:22:47.100144 NEW_RANK_MODE = 1
7134 23:22:47.104060 DLL_IDLE_MODE = 1
7135 23:22:47.106988 LP45_APHY_COMB_EN = 1
7136 23:22:47.107054 TX_ODT_DIS = 0
7137 23:22:47.110336 NEW_8X_MODE = 1
7138 23:22:47.113488 ===================================
7139 23:22:47.116817 ===================================
7140 23:22:47.120252 data_rate = 3200
7141 23:22:47.123874 CKR = 1
7142 23:22:47.126389 DQ_P2S_RATIO = 8
7143 23:22:47.130317 ===================================
7144 23:22:47.133012 CA_P2S_RATIO = 8
7145 23:22:47.133088 DQ_CA_OPEN = 0
7146 23:22:47.136377 DQ_SEMI_OPEN = 0
7147 23:22:47.140133 CA_SEMI_OPEN = 0
7148 23:22:47.143197 CA_FULL_RATE = 0
7149 23:22:47.146683 DQ_CKDIV4_EN = 0
7150 23:22:47.150187 CA_CKDIV4_EN = 0
7151 23:22:47.150261 CA_PREDIV_EN = 0
7152 23:22:47.153395 PH8_DLY = 12
7153 23:22:47.156215 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7154 23:22:47.160232 DQ_AAMCK_DIV = 4
7155 23:22:47.162890 CA_AAMCK_DIV = 4
7156 23:22:47.166542 CA_ADMCK_DIV = 4
7157 23:22:47.166614 DQ_TRACK_CA_EN = 0
7158 23:22:47.169484 CA_PICK = 1600
7159 23:22:47.172859 CA_MCKIO = 1600
7160 23:22:47.175944 MCKIO_SEMI = 0
7161 23:22:47.179576 PLL_FREQ = 3068
7162 23:22:47.182667 DQ_UI_PI_RATIO = 32
7163 23:22:47.185896 CA_UI_PI_RATIO = 0
7164 23:22:47.189176 ===================================
7165 23:22:47.192681 ===================================
7166 23:22:47.192761 memory_type:LPDDR4
7167 23:22:47.196014 GP_NUM : 10
7168 23:22:47.199214 SRAM_EN : 1
7169 23:22:47.199284 MD32_EN : 0
7170 23:22:47.202469 ===================================
7171 23:22:47.206074 [ANA_INIT] >>>>>>>>>>>>>>
7172 23:22:47.209025 <<<<<< [CONFIGURE PHASE]: ANA_TX
7173 23:22:47.212192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7174 23:22:47.215749 ===================================
7175 23:22:47.219101 data_rate = 3200,PCW = 0X7600
7176 23:22:47.221887 ===================================
7177 23:22:47.225986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7178 23:22:47.231747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7179 23:22:47.234982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7180 23:22:47.241940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7181 23:22:47.245141 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7182 23:22:47.248448 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7183 23:22:47.248524 [ANA_INIT] flow start
7184 23:22:47.251724 [ANA_INIT] PLL >>>>>>>>
7185 23:22:47.255399 [ANA_INIT] PLL <<<<<<<<
7186 23:22:47.255473 [ANA_INIT] MIDPI >>>>>>>>
7187 23:22:47.258667 [ANA_INIT] MIDPI <<<<<<<<
7188 23:22:47.261978 [ANA_INIT] DLL >>>>>>>>
7189 23:22:47.264790 [ANA_INIT] DLL <<<<<<<<
7190 23:22:47.264877 [ANA_INIT] flow end
7191 23:22:47.268051 ============ LP4 DIFF to SE enter ============
7192 23:22:47.274547 ============ LP4 DIFF to SE exit ============
7193 23:22:47.274630 [ANA_INIT] <<<<<<<<<<<<<
7194 23:22:47.278005 [Flow] Enable top DCM control >>>>>
7195 23:22:47.281066 [Flow] Enable top DCM control <<<<<
7196 23:22:47.284440 Enable DLL master slave shuffle
7197 23:22:47.291084 ==============================================================
7198 23:22:47.291168 Gating Mode config
7199 23:22:47.297508 ==============================================================
7200 23:22:47.301032 Config description:
7201 23:22:47.310553 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7202 23:22:47.317179 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7203 23:22:47.320437 SELPH_MODE 0: By rank 1: By Phase
7204 23:22:47.327139 ==============================================================
7205 23:22:47.330593 GAT_TRACK_EN = 1
7206 23:22:47.334126 RX_GATING_MODE = 2
7207 23:22:47.337217 RX_GATING_TRACK_MODE = 2
7208 23:22:47.337350 SELPH_MODE = 1
7209 23:22:47.340635 PICG_EARLY_EN = 1
7210 23:22:47.343395 VALID_LAT_VALUE = 1
7211 23:22:47.350574 ==============================================================
7212 23:22:47.353711 Enter into Gating configuration >>>>
7213 23:22:47.356673 Exit from Gating configuration <<<<
7214 23:22:47.360118 Enter into DVFS_PRE_config >>>>>
7215 23:22:47.370272 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7216 23:22:47.373537 Exit from DVFS_PRE_config <<<<<
7217 23:22:47.376127 Enter into PICG configuration >>>>
7218 23:22:47.380160 Exit from PICG configuration <<<<
7219 23:22:47.382893 [RX_INPUT] configuration >>>>>
7220 23:22:47.386319 [RX_INPUT] configuration <<<<<
7221 23:22:47.392952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7222 23:22:47.396328 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7223 23:22:47.402511 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7224 23:22:47.409612 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7225 23:22:47.416340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7226 23:22:47.422326 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7227 23:22:47.426094 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7228 23:22:47.429079 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7229 23:22:47.432469 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7230 23:22:47.438818 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7231 23:22:47.442536 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7232 23:22:47.445433 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7233 23:22:47.448663 ===================================
7234 23:22:47.452145 LPDDR4 DRAM CONFIGURATION
7235 23:22:47.455235 ===================================
7236 23:22:47.458814 EX_ROW_EN[0] = 0x0
7237 23:22:47.458943 EX_ROW_EN[1] = 0x0
7238 23:22:47.462241 LP4Y_EN = 0x0
7239 23:22:47.462373 WORK_FSP = 0x1
7240 23:22:47.465553 WL = 0x5
7241 23:22:47.465690 RL = 0x5
7242 23:22:47.468878 BL = 0x2
7243 23:22:47.468999 RPST = 0x0
7244 23:22:47.471749 RD_PRE = 0x0
7245 23:22:47.471880 WR_PRE = 0x1
7246 23:22:47.475062 WR_PST = 0x1
7247 23:22:47.475178 DBI_WR = 0x0
7248 23:22:47.478453 DBI_RD = 0x0
7249 23:22:47.478587 OTF = 0x1
7250 23:22:47.481730 ===================================
7251 23:22:47.488434 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7252 23:22:47.491483 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7253 23:22:47.495056 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7254 23:22:47.498603 ===================================
7255 23:22:47.501458 LPDDR4 DRAM CONFIGURATION
7256 23:22:47.504798 ===================================
7257 23:22:47.507819 EX_ROW_EN[0] = 0x10
7258 23:22:47.507953 EX_ROW_EN[1] = 0x0
7259 23:22:47.511081 LP4Y_EN = 0x0
7260 23:22:47.511179 WORK_FSP = 0x1
7261 23:22:47.514615 WL = 0x5
7262 23:22:47.514720 RL = 0x5
7263 23:22:47.518099 BL = 0x2
7264 23:22:47.518208 RPST = 0x0
7265 23:22:47.521272 RD_PRE = 0x0
7266 23:22:47.521377 WR_PRE = 0x1
7267 23:22:47.524547 WR_PST = 0x1
7268 23:22:47.524666 DBI_WR = 0x0
7269 23:22:47.527739 DBI_RD = 0x0
7270 23:22:47.527896 OTF = 0x1
7271 23:22:47.531254 ===================================
7272 23:22:47.537528 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7273 23:22:47.537622 ==
7274 23:22:47.541376 Dram Type= 6, Freq= 0, CH_0, rank 0
7275 23:22:47.547753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7276 23:22:47.547829 ==
7277 23:22:47.547892 [Duty_Offset_Calibration]
7278 23:22:47.551135 B0:2 B1:0 CA:4
7279 23:22:47.551219
7280 23:22:47.553974 [DutyScan_Calibration_Flow] k_type=0
7281 23:22:47.563063
7282 23:22:47.563180 ==CLK 0==
7283 23:22:47.566113 Final CLK duty delay cell = -4
7284 23:22:47.569510 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7285 23:22:47.572907 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7286 23:22:47.575993 [-4] AVG Duty = 4937%(X100)
7287 23:22:47.576108
7288 23:22:47.579272 CH0 CLK Duty spec in!! Max-Min= 187%
7289 23:22:47.582671 [DutyScan_Calibration_Flow] ====Done====
7290 23:22:47.582746
7291 23:22:47.586121 [DutyScan_Calibration_Flow] k_type=1
7292 23:22:47.603617
7293 23:22:47.603713 ==DQS 0 ==
7294 23:22:47.606566 Final DQS duty delay cell = 0
7295 23:22:47.610156 [0] MAX Duty = 5249%(X100), DQS PI = 38
7296 23:22:47.613510 [0] MIN Duty = 5093%(X100), DQS PI = 4
7297 23:22:47.613622 [0] AVG Duty = 5171%(X100)
7298 23:22:47.616263
7299 23:22:47.616370 ==DQS 1 ==
7300 23:22:47.619719 Final DQS duty delay cell = 0
7301 23:22:47.623039 [0] MAX Duty = 5187%(X100), DQS PI = 2
7302 23:22:47.626418 [0] MIN Duty = 4969%(X100), DQS PI = 12
7303 23:22:47.629570 [0] AVG Duty = 5078%(X100)
7304 23:22:47.629672
7305 23:22:47.633184 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7306 23:22:47.633285
7307 23:22:47.635998 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7308 23:22:47.639574 [DutyScan_Calibration_Flow] ====Done====
7309 23:22:47.639670
7310 23:22:47.642615 [DutyScan_Calibration_Flow] k_type=3
7311 23:22:47.660306
7312 23:22:47.660393 ==DQM 0 ==
7313 23:22:47.663777 Final DQM duty delay cell = 0
7314 23:22:47.666879 [0] MAX Duty = 5124%(X100), DQS PI = 22
7315 23:22:47.670799 [0] MIN Duty = 4875%(X100), DQS PI = 54
7316 23:22:47.673925 [0] AVG Duty = 4999%(X100)
7317 23:22:47.674007
7318 23:22:47.674073 ==DQM 1 ==
7319 23:22:47.676957 Final DQM duty delay cell = 0
7320 23:22:47.680317 [0] MAX Duty = 5000%(X100), DQS PI = 2
7321 23:22:47.683822 [0] MIN Duty = 4844%(X100), DQS PI = 16
7322 23:22:47.686661 [0] AVG Duty = 4922%(X100)
7323 23:22:47.686761
7324 23:22:47.690046 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7325 23:22:47.690131
7326 23:22:47.693006 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7327 23:22:47.696378 [DutyScan_Calibration_Flow] ====Done====
7328 23:22:47.696467
7329 23:22:47.699556 [DutyScan_Calibration_Flow] k_type=2
7330 23:22:47.717332
7331 23:22:47.717444 ==DQ 0 ==
7332 23:22:47.720582 Final DQ duty delay cell = 0
7333 23:22:47.724227 [0] MAX Duty = 5156%(X100), DQS PI = 22
7334 23:22:47.727542 [0] MIN Duty = 4938%(X100), DQS PI = 12
7335 23:22:47.731048 [0] AVG Duty = 5047%(X100)
7336 23:22:47.731126
7337 23:22:47.731190 ==DQ 1 ==
7338 23:22:47.734098 Final DQ duty delay cell = 0
7339 23:22:47.737281 [0] MAX Duty = 5187%(X100), DQS PI = 2
7340 23:22:47.740697 [0] MIN Duty = 4938%(X100), DQS PI = 12
7341 23:22:47.740778 [0] AVG Duty = 5062%(X100)
7342 23:22:47.743591
7343 23:22:47.747310 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7344 23:22:47.747418
7345 23:22:47.750876 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7346 23:22:47.753462 [DutyScan_Calibration_Flow] ====Done====
7347 23:22:47.753558 ==
7348 23:22:47.756711 Dram Type= 6, Freq= 0, CH_1, rank 0
7349 23:22:47.760105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7350 23:22:47.760187 ==
7351 23:22:47.763504 [Duty_Offset_Calibration]
7352 23:22:47.763584 B0:0 B1:-1 CA:3
7353 23:22:47.763648
7354 23:22:47.766869 [DutyScan_Calibration_Flow] k_type=0
7355 23:22:47.776956
7356 23:22:47.777037 ==CLK 0==
7357 23:22:47.779915 Final CLK duty delay cell = -4
7358 23:22:47.783656 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7359 23:22:47.786695 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7360 23:22:47.790232 [-4] AVG Duty = 4922%(X100)
7361 23:22:47.790313
7362 23:22:47.793053 CH1 CLK Duty spec in!! Max-Min= 156%
7363 23:22:47.796554 [DutyScan_Calibration_Flow] ====Done====
7364 23:22:47.796635
7365 23:22:47.799896 [DutyScan_Calibration_Flow] k_type=1
7366 23:22:47.816343
7367 23:22:47.816423 ==DQS 0 ==
7368 23:22:47.819602 Final DQS duty delay cell = 0
7369 23:22:47.823031 [0] MAX Duty = 5218%(X100), DQS PI = 30
7370 23:22:47.826276 [0] MIN Duty = 4907%(X100), DQS PI = 58
7371 23:22:47.829175 [0] AVG Duty = 5062%(X100)
7372 23:22:47.829280
7373 23:22:47.829371 ==DQS 1 ==
7374 23:22:47.832390 Final DQS duty delay cell = -4
7375 23:22:47.835783 [-4] MAX Duty = 5000%(X100), DQS PI = 32
7376 23:22:47.839198 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7377 23:22:47.842359 [-4] AVG Duty = 4906%(X100)
7378 23:22:47.842465
7379 23:22:47.845670 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7380 23:22:47.845809
7381 23:22:47.848771 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7382 23:22:47.852413 [DutyScan_Calibration_Flow] ====Done====
7383 23:22:47.852494
7384 23:22:47.855856 [DutyScan_Calibration_Flow] k_type=3
7385 23:22:47.873181
7386 23:22:47.873262 ==DQM 0 ==
7387 23:22:47.876745 Final DQM duty delay cell = 0
7388 23:22:47.879693 [0] MAX Duty = 5062%(X100), DQS PI = 32
7389 23:22:47.883506 [0] MIN Duty = 4782%(X100), DQS PI = 38
7390 23:22:47.886337 [0] AVG Duty = 4922%(X100)
7391 23:22:47.886431
7392 23:22:47.886523 ==DQM 1 ==
7393 23:22:47.889771 Final DQM duty delay cell = 0
7394 23:22:47.893323 [0] MAX Duty = 4969%(X100), DQS PI = 30
7395 23:22:47.896243 [0] MIN Duty = 4813%(X100), DQS PI = 62
7396 23:22:47.899461 [0] AVG Duty = 4891%(X100)
7397 23:22:47.899566
7398 23:22:47.902914 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7399 23:22:47.903038
7400 23:22:47.906310 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7401 23:22:47.909667 [DutyScan_Calibration_Flow] ====Done====
7402 23:22:47.909817
7403 23:22:47.912483 [DutyScan_Calibration_Flow] k_type=2
7404 23:22:47.929413
7405 23:22:47.929533 ==DQ 0 ==
7406 23:22:47.932975 Final DQ duty delay cell = -4
7407 23:22:47.935794 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7408 23:22:47.939276 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7409 23:22:47.942359 [-4] AVG Duty = 4891%(X100)
7410 23:22:47.942478
7411 23:22:47.942589 ==DQ 1 ==
7412 23:22:47.945974 Final DQ duty delay cell = 0
7413 23:22:47.948896 [0] MAX Duty = 5062%(X100), DQS PI = 32
7414 23:22:47.952226 [0] MIN Duty = 4875%(X100), DQS PI = 0
7415 23:22:47.955444 [0] AVG Duty = 4968%(X100)
7416 23:22:47.955529
7417 23:22:47.958899 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7418 23:22:47.958979
7419 23:22:47.962580 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7420 23:22:47.965943 [DutyScan_Calibration_Flow] ====Done====
7421 23:22:47.968643 nWR fixed to 30
7422 23:22:47.971819 [ModeRegInit_LP4] CH0 RK0
7423 23:22:47.971939 [ModeRegInit_LP4] CH0 RK1
7424 23:22:47.975442 [ModeRegInit_LP4] CH1 RK0
7425 23:22:47.978478 [ModeRegInit_LP4] CH1 RK1
7426 23:22:47.978594 match AC timing 5
7427 23:22:47.985366 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7428 23:22:47.988558 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7429 23:22:47.991644 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7430 23:22:47.998221 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7431 23:22:48.001829 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7432 23:22:48.005020 [MiockJmeterHQA]
7433 23:22:48.005134
7434 23:22:48.008149 [DramcMiockJmeter] u1RxGatingPI = 0
7435 23:22:48.008263 0 : 4366, 4137
7436 23:22:48.008375 4 : 4363, 4137
7437 23:22:48.011381 8 : 4250, 4025
7438 23:22:48.011518 12 : 4363, 4137
7439 23:22:48.014685 16 : 4252, 4027
7440 23:22:48.014804 20 : 4253, 4026
7441 23:22:48.018200 24 : 4252, 4027
7442 23:22:48.018320 28 : 4252, 4027
7443 23:22:48.018430 32 : 4361, 4137
7444 23:22:48.021324 36 : 4252, 4027
7445 23:22:48.021443 40 : 4250, 4026
7446 23:22:48.024448 44 : 4250, 4027
7447 23:22:48.024568 48 : 4250, 4027
7448 23:22:48.028183 52 : 4250, 4027
7449 23:22:48.028303 56 : 4360, 4138
7450 23:22:48.031196 60 : 4363, 4140
7451 23:22:48.031317 64 : 4250, 4027
7452 23:22:48.034821 68 : 4249, 4027
7453 23:22:48.034942 72 : 4250, 4026
7454 23:22:48.035050 76 : 4250, 4027
7455 23:22:48.038159 80 : 4250, 4027
7456 23:22:48.038281 84 : 4361, 4137
7457 23:22:48.041173 88 : 4252, 4027
7458 23:22:48.041295 92 : 4250, 4027
7459 23:22:48.044273 96 : 4250, 2829
7460 23:22:48.044387 100 : 4250, 0
7461 23:22:48.044498 104 : 4250, 0
7462 23:22:48.047956 108 : 4253, 0
7463 23:22:48.048076 112 : 4252, 0
7464 23:22:48.051417 116 : 4252, 0
7465 23:22:48.051535 120 : 4361, 0
7466 23:22:48.051646 124 : 4250, 0
7467 23:22:48.054562 128 : 4249, 0
7468 23:22:48.054673 132 : 4361, 0
7469 23:22:48.057481 136 : 4250, 0
7470 23:22:48.057562 140 : 4250, 0
7471 23:22:48.057625 144 : 4250, 0
7472 23:22:48.061331 148 : 4250, 0
7473 23:22:48.061411 152 : 4252, 0
7474 23:22:48.061474 156 : 4250, 0
7475 23:22:48.064321 160 : 4250, 0
7476 23:22:48.064402 164 : 4250, 0
7477 23:22:48.067546 168 : 4360, 0
7478 23:22:48.067627 172 : 4250, 0
7479 23:22:48.067691 176 : 4360, 0
7480 23:22:48.071515 180 : 4249, 0
7481 23:22:48.071596 184 : 4250, 0
7482 23:22:48.074009 188 : 4250, 0
7483 23:22:48.074090 192 : 4250, 0
7484 23:22:48.074153 196 : 4250, 0
7485 23:22:48.077396 200 : 4360, 0
7486 23:22:48.077482 204 : 4250, 0
7487 23:22:48.080552 208 : 4250, 0
7488 23:22:48.080633 212 : 4250, 0
7489 23:22:48.080697 216 : 4252, 0
7490 23:22:48.084047 220 : 4250, 853
7491 23:22:48.084129 224 : 4361, 4130
7492 23:22:48.087549 228 : 4252, 4029
7493 23:22:48.087631 232 : 4250, 4027
7494 23:22:48.090226 236 : 4250, 4027
7495 23:22:48.090307 240 : 4252, 4029
7496 23:22:48.094040 244 : 4250, 4026
7497 23:22:48.094121 248 : 4250, 4027
7498 23:22:48.097592 252 : 4361, 4138
7499 23:22:48.097673 256 : 4250, 4027
7500 23:22:48.100869 260 : 4250, 4027
7501 23:22:48.100950 264 : 4361, 4137
7502 23:22:48.101015 268 : 4250, 4027
7503 23:22:48.103778 272 : 4250, 4027
7504 23:22:48.103904 276 : 4363, 4140
7505 23:22:48.106698 280 : 4250, 4026
7506 23:22:48.106818 284 : 4250, 4027
7507 23:22:48.110297 288 : 4249, 4027
7508 23:22:48.110403 292 : 4252, 4029
7509 23:22:48.113845 296 : 4250, 4026
7510 23:22:48.113947 300 : 4250, 4027
7511 23:22:48.116849 304 : 4360, 4138
7512 23:22:48.116930 308 : 4250, 4027
7513 23:22:48.119964 312 : 4250, 4026
7514 23:22:48.120045 316 : 4361, 4137
7515 23:22:48.123207 320 : 4250, 4027
7516 23:22:48.123289 324 : 4250, 4027
7517 23:22:48.126771 328 : 4363, 4140
7518 23:22:48.126853 332 : 4250, 3932
7519 23:22:48.130129 336 : 4250, 1797
7520 23:22:48.130255
7521 23:22:48.130361 MIOCK jitter meter ch=0
7522 23:22:48.130467
7523 23:22:48.133432 1T = (336-100) = 236 dly cells
7524 23:22:48.139619 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7525 23:22:48.139722 ==
7526 23:22:48.142991 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 23:22:48.146433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 23:22:48.146516 ==
7529 23:22:48.153045 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7530 23:22:48.156119 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7531 23:22:48.159464 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7532 23:22:48.165995 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7533 23:22:48.175772 [CA 0] Center 44 (14~74) winsize 61
7534 23:22:48.179162 [CA 1] Center 43 (13~74) winsize 62
7535 23:22:48.183048 [CA 2] Center 39 (10~68) winsize 59
7536 23:22:48.185660 [CA 3] Center 38 (9~68) winsize 60
7537 23:22:48.189352 [CA 4] Center 36 (7~66) winsize 60
7538 23:22:48.192619 [CA 5] Center 36 (6~66) winsize 61
7539 23:22:48.192701
7540 23:22:48.195892 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7541 23:22:48.195973
7542 23:22:48.199214 [CATrainingPosCal] consider 1 rank data
7543 23:22:48.202916 u2DelayCellTimex100 = 275/100 ps
7544 23:22:48.208700 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7545 23:22:48.212037 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7546 23:22:48.215479 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7547 23:22:48.219073 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7548 23:22:48.222243 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7549 23:22:48.225699 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7550 23:22:48.225779
7551 23:22:48.229134 CA PerBit enable=1, Macro0, CA PI delay=36
7552 23:22:48.229215
7553 23:22:48.231851 [CBTSetCACLKResult] CA Dly = 36
7554 23:22:48.235137 CS Dly: 11 (0~42)
7555 23:22:48.238597 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7556 23:22:48.241703 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7557 23:22:48.241800 ==
7558 23:22:48.245128 Dram Type= 6, Freq= 0, CH_0, rank 1
7559 23:22:48.251758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 23:22:48.251856 ==
7561 23:22:48.255324 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7562 23:22:48.261513 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7563 23:22:48.264946 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7564 23:22:48.271133 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7565 23:22:48.279771 [CA 0] Center 43 (13~74) winsize 62
7566 23:22:48.282858 [CA 1] Center 43 (13~74) winsize 62
7567 23:22:48.286026 [CA 2] Center 38 (9~68) winsize 60
7568 23:22:48.289768 [CA 3] Center 38 (9~68) winsize 60
7569 23:22:48.293147 [CA 4] Center 36 (6~67) winsize 62
7570 23:22:48.296151 [CA 5] Center 36 (6~66) winsize 61
7571 23:22:48.296236
7572 23:22:48.299299 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7573 23:22:48.299406
7574 23:22:48.305744 [CATrainingPosCal] consider 2 rank data
7575 23:22:48.305826 u2DelayCellTimex100 = 275/100 ps
7576 23:22:48.312397 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7577 23:22:48.315992 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7578 23:22:48.319034 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7579 23:22:48.322651 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7580 23:22:48.325819 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7581 23:22:48.329205 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7582 23:22:48.329287
7583 23:22:48.332407 CA PerBit enable=1, Macro0, CA PI delay=36
7584 23:22:48.332554
7585 23:22:48.335577 [CBTSetCACLKResult] CA Dly = 36
7586 23:22:48.339126 CS Dly: 11 (0~43)
7587 23:22:48.342262 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7588 23:22:48.345702 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7589 23:22:48.345809
7590 23:22:48.348644 ----->DramcWriteLeveling(PI) begin...
7591 23:22:48.351951 ==
7592 23:22:48.355278 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 23:22:48.358917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 23:22:48.359000 ==
7595 23:22:48.361611 Write leveling (Byte 0): 35 => 35
7596 23:22:48.365376 Write leveling (Byte 1): 27 => 27
7597 23:22:48.368775 DramcWriteLeveling(PI) end<-----
7598 23:22:48.368862
7599 23:22:48.368926 ==
7600 23:22:48.371973 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 23:22:48.375258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 23:22:48.375355 ==
7603 23:22:48.378210 [Gating] SW mode calibration
7604 23:22:48.384809 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7605 23:22:48.391198 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7606 23:22:48.394553 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 23:22:48.398039 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 23:22:48.404476 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7609 23:22:48.407829 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7610 23:22:48.410910 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7611 23:22:48.417640 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7612 23:22:48.421057 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7613 23:22:48.424276 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 23:22:48.431170 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7615 23:22:48.433831 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 23:22:48.437251 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7617 23:22:48.444099 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7618 23:22:48.446955 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7619 23:22:48.450743 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7620 23:22:48.457164 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7621 23:22:48.460814 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 23:22:48.463790 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 23:22:48.470464 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 23:22:48.473837 1 6 8 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
7625 23:22:48.476748 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7626 23:22:48.483346 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7627 23:22:48.486700 1 6 20 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
7628 23:22:48.490005 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 23:22:48.496691 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 23:22:48.499962 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 23:22:48.503155 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 23:22:48.510056 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7633 23:22:48.513278 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7634 23:22:48.516215 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7635 23:22:48.522864 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7636 23:22:48.526013 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7637 23:22:48.529294 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 23:22:48.536017 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 23:22:48.539214 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 23:22:48.542963 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 23:22:48.549406 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 23:22:48.552418 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 23:22:48.555492 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 23:22:48.562126 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 23:22:48.565637 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 23:22:48.569223 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 23:22:48.575262 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 23:22:48.578869 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7649 23:22:48.582133 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7650 23:22:48.585406 Total UI for P1: 0, mck2ui 16
7651 23:22:48.588499 best dqsien dly found for B0: ( 1, 9, 8)
7652 23:22:48.594943 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7653 23:22:48.598613 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7654 23:22:48.601748 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7655 23:22:48.608528 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 23:22:48.611769 Total UI for P1: 0, mck2ui 16
7657 23:22:48.614847 best dqsien dly found for B1: ( 1, 9, 22)
7658 23:22:48.618553 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7659 23:22:48.621638 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7660 23:22:48.621747
7661 23:22:48.624699 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7662 23:22:48.628417 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7663 23:22:48.631326 [Gating] SW calibration Done
7664 23:22:48.631423 ==
7665 23:22:48.634680 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 23:22:48.638033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 23:22:48.638157 ==
7668 23:22:48.641421 RX Vref Scan: 0
7669 23:22:48.641524
7670 23:22:48.644594 RX Vref 0 -> 0, step: 1
7671 23:22:48.644681
7672 23:22:48.644746 RX Delay 0 -> 252, step: 8
7673 23:22:48.651615 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7674 23:22:48.654693 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7675 23:22:48.657551 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7676 23:22:48.661069 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7677 23:22:48.664092 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7678 23:22:48.671076 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7679 23:22:48.674522 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7680 23:22:48.677407 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7681 23:22:48.680593 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7682 23:22:48.684543 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7683 23:22:48.690583 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7684 23:22:48.693764 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7685 23:22:48.697315 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7686 23:22:48.700427 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7687 23:22:48.706806 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7688 23:22:48.710430 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7689 23:22:48.710534 ==
7690 23:22:48.713723 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 23:22:48.716857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 23:22:48.716938 ==
7693 23:22:48.720267 DQS Delay:
7694 23:22:48.720347 DQS0 = 0, DQS1 = 0
7695 23:22:48.720410 DQM Delay:
7696 23:22:48.723698 DQM0 = 131, DQM1 = 126
7697 23:22:48.723779 DQ Delay:
7698 23:22:48.726928 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =123
7699 23:22:48.730058 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7700 23:22:48.733350 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7701 23:22:48.740439 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7702 23:22:48.740564
7703 23:22:48.740672
7704 23:22:48.740780 ==
7705 23:22:48.743271 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 23:22:48.746408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 23:22:48.746528 ==
7708 23:22:48.746639
7709 23:22:48.746761
7710 23:22:48.749684 TX Vref Scan disable
7711 23:22:48.749799 == TX Byte 0 ==
7712 23:22:48.756780 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7713 23:22:48.760073 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7714 23:22:48.762870 == TX Byte 1 ==
7715 23:22:48.766306 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7716 23:22:48.769815 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7717 23:22:48.769896 ==
7718 23:22:48.773121 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 23:22:48.776479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 23:22:48.779347 ==
7721 23:22:48.791326
7722 23:22:48.794688 TX Vref early break, caculate TX vref
7723 23:22:48.797739 TX Vref=16, minBit 1, minWin=22, winSum=369
7724 23:22:48.800979 TX Vref=18, minBit 8, minWin=22, winSum=382
7725 23:22:48.804442 TX Vref=20, minBit 8, minWin=23, winSum=390
7726 23:22:48.807667 TX Vref=22, minBit 0, minWin=24, winSum=399
7727 23:22:48.810945 TX Vref=24, minBit 8, minWin=24, winSum=411
7728 23:22:48.817489 TX Vref=26, minBit 4, minWin=25, winSum=417
7729 23:22:48.820712 TX Vref=28, minBit 1, minWin=25, winSum=425
7730 23:22:48.824262 TX Vref=30, minBit 4, minWin=24, winSum=416
7731 23:22:48.827983 TX Vref=32, minBit 4, minWin=24, winSum=411
7732 23:22:48.830478 TX Vref=34, minBit 1, minWin=23, winSum=399
7733 23:22:48.837693 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 28
7734 23:22:48.837777
7735 23:22:48.840780 Final TX Range 0 Vref 28
7736 23:22:48.840859
7737 23:22:48.840932 ==
7738 23:22:48.843649 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 23:22:48.847027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 23:22:48.847137 ==
7741 23:22:48.847230
7742 23:22:48.847318
7743 23:22:48.850379 TX Vref Scan disable
7744 23:22:48.856763 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7745 23:22:48.856896 == TX Byte 0 ==
7746 23:22:48.860513 u2DelayCellOfst[0]=10 cells (3 PI)
7747 23:22:48.863561 u2DelayCellOfst[1]=14 cells (4 PI)
7748 23:22:48.866642 u2DelayCellOfst[2]=10 cells (3 PI)
7749 23:22:48.870403 u2DelayCellOfst[3]=10 cells (3 PI)
7750 23:22:48.873876 u2DelayCellOfst[4]=7 cells (2 PI)
7751 23:22:48.876853 u2DelayCellOfst[5]=0 cells (0 PI)
7752 23:22:48.879920 u2DelayCellOfst[6]=14 cells (4 PI)
7753 23:22:48.883873 u2DelayCellOfst[7]=14 cells (4 PI)
7754 23:22:48.887278 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7755 23:22:48.890101 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7756 23:22:48.893316 == TX Byte 1 ==
7757 23:22:48.896408 u2DelayCellOfst[8]=0 cells (0 PI)
7758 23:22:48.900084 u2DelayCellOfst[9]=0 cells (0 PI)
7759 23:22:48.903189 u2DelayCellOfst[10]=3 cells (1 PI)
7760 23:22:48.906776 u2DelayCellOfst[11]=3 cells (1 PI)
7761 23:22:48.906854 u2DelayCellOfst[12]=10 cells (3 PI)
7762 23:22:48.909701 u2DelayCellOfst[13]=10 cells (3 PI)
7763 23:22:48.913157 u2DelayCellOfst[14]=14 cells (4 PI)
7764 23:22:48.916360 u2DelayCellOfst[15]=10 cells (3 PI)
7765 23:22:48.922971 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7766 23:22:48.925993 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7767 23:22:48.926068 DramC Write-DBI on
7768 23:22:48.930025 ==
7769 23:22:48.933071 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 23:22:48.936405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 23:22:48.936486 ==
7772 23:22:48.936552
7773 23:22:48.936635
7774 23:22:48.939475 TX Vref Scan disable
7775 23:22:48.939557 == TX Byte 0 ==
7776 23:22:48.945945 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7777 23:22:48.946055 == TX Byte 1 ==
7778 23:22:48.949231 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7779 23:22:48.952356 DramC Write-DBI off
7780 23:22:48.952440
7781 23:22:48.952506 [DATLAT]
7782 23:22:48.955660 Freq=1600, CH0 RK0
7783 23:22:48.955765
7784 23:22:48.955858 DATLAT Default: 0xf
7785 23:22:48.959128 0, 0xFFFF, sum = 0
7786 23:22:48.959239 1, 0xFFFF, sum = 0
7787 23:22:48.962308 2, 0xFFFF, sum = 0
7788 23:22:48.965719 3, 0xFFFF, sum = 0
7789 23:22:48.965800 4, 0xFFFF, sum = 0
7790 23:22:48.968823 5, 0xFFFF, sum = 0
7791 23:22:48.968897 6, 0xFFFF, sum = 0
7792 23:22:48.972177 7, 0xFFFF, sum = 0
7793 23:22:48.972253 8, 0xFFFF, sum = 0
7794 23:22:48.975651 9, 0xFFFF, sum = 0
7795 23:22:48.975761 10, 0xFFFF, sum = 0
7796 23:22:48.979030 11, 0xFFFF, sum = 0
7797 23:22:48.979140 12, 0xFFFF, sum = 0
7798 23:22:48.982158 13, 0xFFFF, sum = 0
7799 23:22:48.982264 14, 0x0, sum = 1
7800 23:22:48.985326 15, 0x0, sum = 2
7801 23:22:48.985452 16, 0x0, sum = 3
7802 23:22:48.988948 17, 0x0, sum = 4
7803 23:22:48.989063 best_step = 15
7804 23:22:48.989156
7805 23:22:48.989246 ==
7806 23:22:48.991925 Dram Type= 6, Freq= 0, CH_0, rank 0
7807 23:22:48.998532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7808 23:22:48.998634 ==
7809 23:22:48.998726 RX Vref Scan: 1
7810 23:22:48.998816
7811 23:22:49.001764 Set Vref Range= 24 -> 127
7812 23:22:49.001835
7813 23:22:49.005179 RX Vref 24 -> 127, step: 1
7814 23:22:49.005249
7815 23:22:49.005344 RX Delay 11 -> 252, step: 4
7816 23:22:49.005421
7817 23:22:49.008398 Set Vref, RX VrefLevel [Byte0]: 24
7818 23:22:49.011861 [Byte1]: 24
7819 23:22:49.016202
7820 23:22:49.016284 Set Vref, RX VrefLevel [Byte0]: 25
7821 23:22:49.019216 [Byte1]: 25
7822 23:22:49.023591
7823 23:22:49.023718 Set Vref, RX VrefLevel [Byte0]: 26
7824 23:22:49.026659 [Byte1]: 26
7825 23:22:49.031564
7826 23:22:49.031699 Set Vref, RX VrefLevel [Byte0]: 27
7827 23:22:49.034686 [Byte1]: 27
7828 23:22:49.039007
7829 23:22:49.039132 Set Vref, RX VrefLevel [Byte0]: 28
7830 23:22:49.041901 [Byte1]: 28
7831 23:22:49.046466
7832 23:22:49.046587 Set Vref, RX VrefLevel [Byte0]: 29
7833 23:22:49.049628 [Byte1]: 29
7834 23:22:49.054347
7835 23:22:49.054452 Set Vref, RX VrefLevel [Byte0]: 30
7836 23:22:49.057201 [Byte1]: 30
7837 23:22:49.061415
7838 23:22:49.061494 Set Vref, RX VrefLevel [Byte0]: 31
7839 23:22:49.064828 [Byte1]: 31
7840 23:22:49.069497
7841 23:22:49.069566 Set Vref, RX VrefLevel [Byte0]: 32
7842 23:22:49.072434 [Byte1]: 32
7843 23:22:49.077156
7844 23:22:49.077231 Set Vref, RX VrefLevel [Byte0]: 33
7845 23:22:49.080099 [Byte1]: 33
7846 23:22:49.084455
7847 23:22:49.084531 Set Vref, RX VrefLevel [Byte0]: 34
7848 23:22:49.087755 [Byte1]: 34
7849 23:22:49.092323
7850 23:22:49.092401 Set Vref, RX VrefLevel [Byte0]: 35
7851 23:22:49.095445 [Byte1]: 35
7852 23:22:49.099471
7853 23:22:49.099548 Set Vref, RX VrefLevel [Byte0]: 36
7854 23:22:49.103062 [Byte1]: 36
7855 23:22:49.107511
7856 23:22:49.107641 Set Vref, RX VrefLevel [Byte0]: 37
7857 23:22:49.110581 [Byte1]: 37
7858 23:22:49.115097
7859 23:22:49.115216 Set Vref, RX VrefLevel [Byte0]: 38
7860 23:22:49.118299 [Byte1]: 38
7861 23:22:49.122606
7862 23:22:49.122728 Set Vref, RX VrefLevel [Byte0]: 39
7863 23:22:49.125969 [Byte1]: 39
7864 23:22:49.129939
7865 23:22:49.130030 Set Vref, RX VrefLevel [Byte0]: 40
7866 23:22:49.133369 [Byte1]: 40
7867 23:22:49.137475
7868 23:22:49.137552 Set Vref, RX VrefLevel [Byte0]: 41
7869 23:22:49.140946 [Byte1]: 41
7870 23:22:49.145408
7871 23:22:49.145504 Set Vref, RX VrefLevel [Byte0]: 42
7872 23:22:49.148592 [Byte1]: 42
7873 23:22:49.153039
7874 23:22:49.153116 Set Vref, RX VrefLevel [Byte0]: 43
7875 23:22:49.156041 [Byte1]: 43
7876 23:22:49.160897
7877 23:22:49.160998 Set Vref, RX VrefLevel [Byte0]: 44
7878 23:22:49.163654 [Byte1]: 44
7879 23:22:49.168372
7880 23:22:49.168468 Set Vref, RX VrefLevel [Byte0]: 45
7881 23:22:49.171792 [Byte1]: 45
7882 23:22:49.175618
7883 23:22:49.175707 Set Vref, RX VrefLevel [Byte0]: 46
7884 23:22:49.178830 [Byte1]: 46
7885 23:22:49.183446
7886 23:22:49.183552 Set Vref, RX VrefLevel [Byte0]: 47
7887 23:22:49.186421 [Byte1]: 47
7888 23:22:49.190950
7889 23:22:49.191081 Set Vref, RX VrefLevel [Byte0]: 48
7890 23:22:49.194364 [Byte1]: 48
7891 23:22:49.198507
7892 23:22:49.198582 Set Vref, RX VrefLevel [Byte0]: 49
7893 23:22:49.202302 [Byte1]: 49
7894 23:22:49.206385
7895 23:22:49.206500 Set Vref, RX VrefLevel [Byte0]: 50
7896 23:22:49.209601 [Byte1]: 50
7897 23:22:49.214138
7898 23:22:49.214252 Set Vref, RX VrefLevel [Byte0]: 51
7899 23:22:49.217634 [Byte1]: 51
7900 23:22:49.221387
7901 23:22:49.221462 Set Vref, RX VrefLevel [Byte0]: 52
7902 23:22:49.224666 [Byte1]: 52
7903 23:22:49.229189
7904 23:22:49.229262 Set Vref, RX VrefLevel [Byte0]: 53
7905 23:22:49.232309 [Byte1]: 53
7906 23:22:49.236841
7907 23:22:49.236920 Set Vref, RX VrefLevel [Byte0]: 54
7908 23:22:49.240179 [Byte1]: 54
7909 23:22:49.244243
7910 23:22:49.244319 Set Vref, RX VrefLevel [Byte0]: 55
7911 23:22:49.247814 [Byte1]: 55
7912 23:22:49.251680
7913 23:22:49.251811 Set Vref, RX VrefLevel [Byte0]: 56
7914 23:22:49.255426 [Byte1]: 56
7915 23:22:49.259269
7916 23:22:49.259409 Set Vref, RX VrefLevel [Byte0]: 57
7917 23:22:49.262973 [Byte1]: 57
7918 23:22:49.267091
7919 23:22:49.267168 Set Vref, RX VrefLevel [Byte0]: 58
7920 23:22:49.270355 [Byte1]: 58
7921 23:22:49.274979
7922 23:22:49.275052 Set Vref, RX VrefLevel [Byte0]: 59
7923 23:22:49.278159 [Byte1]: 59
7924 23:22:49.282547
7925 23:22:49.282650 Set Vref, RX VrefLevel [Byte0]: 60
7926 23:22:49.285960 [Byte1]: 60
7927 23:22:49.289958
7928 23:22:49.290032 Set Vref, RX VrefLevel [Byte0]: 61
7929 23:22:49.293133 [Byte1]: 61
7930 23:22:49.297717
7931 23:22:49.297790 Set Vref, RX VrefLevel [Byte0]: 62
7932 23:22:49.300675 [Byte1]: 62
7933 23:22:49.305180
7934 23:22:49.305266 Set Vref, RX VrefLevel [Byte0]: 63
7935 23:22:49.308221 [Byte1]: 63
7936 23:22:49.312976
7937 23:22:49.316424 Set Vref, RX VrefLevel [Byte0]: 64
7938 23:22:49.318975 [Byte1]: 64
7939 23:22:49.319073
7940 23:22:49.322417 Set Vref, RX VrefLevel [Byte0]: 65
7941 23:22:49.325938 [Byte1]: 65
7942 23:22:49.326020
7943 23:22:49.329152 Set Vref, RX VrefLevel [Byte0]: 66
7944 23:22:49.332333 [Byte1]: 66
7945 23:22:49.335569
7946 23:22:49.335640 Set Vref, RX VrefLevel [Byte0]: 67
7947 23:22:49.338969 [Byte1]: 67
7948 23:22:49.343342
7949 23:22:49.343455 Set Vref, RX VrefLevel [Byte0]: 68
7950 23:22:49.346641 [Byte1]: 68
7951 23:22:49.350944
7952 23:22:49.351048 Set Vref, RX VrefLevel [Byte0]: 69
7953 23:22:49.353960 [Byte1]: 69
7954 23:22:49.358413
7955 23:22:49.358486 Set Vref, RX VrefLevel [Byte0]: 70
7956 23:22:49.361914 [Byte1]: 70
7957 23:22:49.366176
7958 23:22:49.366276 Set Vref, RX VrefLevel [Byte0]: 71
7959 23:22:49.369132 [Byte1]: 71
7960 23:22:49.373549
7961 23:22:49.373625 Set Vref, RX VrefLevel [Byte0]: 72
7962 23:22:49.376758 [Byte1]: 72
7963 23:22:49.381584
7964 23:22:49.381672 Set Vref, RX VrefLevel [Byte0]: 73
7965 23:22:49.384744 [Byte1]: 73
7966 23:22:49.389363
7967 23:22:49.389436 Set Vref, RX VrefLevel [Byte0]: 74
7968 23:22:49.392140 [Byte1]: 74
7969 23:22:49.396497
7970 23:22:49.396568 Set Vref, RX VrefLevel [Byte0]: 75
7971 23:22:49.399923 [Byte1]: 75
7972 23:22:49.404096
7973 23:22:49.404172 Final RX Vref Byte 0 = 57 to rank0
7974 23:22:49.407373 Final RX Vref Byte 1 = 62 to rank0
7975 23:22:49.410930 Final RX Vref Byte 0 = 57 to rank1
7976 23:22:49.414187 Final RX Vref Byte 1 = 62 to rank1==
7977 23:22:49.416981 Dram Type= 6, Freq= 0, CH_0, rank 0
7978 23:22:49.423494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 23:22:49.423584 ==
7980 23:22:49.423649 DQS Delay:
7981 23:22:49.427116 DQS0 = 0, DQS1 = 0
7982 23:22:49.427231 DQM Delay:
7983 23:22:49.430396 DQM0 = 129, DQM1 = 124
7984 23:22:49.430494 DQ Delay:
7985 23:22:49.433569 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7986 23:22:49.437060 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7987 23:22:49.440501 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
7988 23:22:49.443704 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =130
7989 23:22:49.443803
7990 23:22:49.443897
7991 23:22:49.443984
7992 23:22:49.447640 [DramC_TX_OE_Calibration] TA2
7993 23:22:49.450553 Original DQ_B0 (3 6) =30, OEN = 27
7994 23:22:49.453827 Original DQ_B1 (3 6) =30, OEN = 27
7995 23:22:49.457108 24, 0x0, End_B0=24 End_B1=24
7996 23:22:49.460247 25, 0x0, End_B0=25 End_B1=25
7997 23:22:49.460323 26, 0x0, End_B0=26 End_B1=26
7998 23:22:49.463445 27, 0x0, End_B0=27 End_B1=27
7999 23:22:49.466653 28, 0x0, End_B0=28 End_B1=28
8000 23:22:49.470024 29, 0x0, End_B0=29 End_B1=29
8001 23:22:49.470096 30, 0x0, End_B0=30 End_B1=30
8002 23:22:49.473453 31, 0x4141, End_B0=30 End_B1=30
8003 23:22:49.476813 Byte0 end_step=30 best_step=27
8004 23:22:49.480592 Byte1 end_step=30 best_step=27
8005 23:22:49.483374 Byte0 TX OE(2T, 0.5T) = (3, 3)
8006 23:22:49.486915 Byte1 TX OE(2T, 0.5T) = (3, 3)
8007 23:22:49.486997
8008 23:22:49.487062
8009 23:22:49.493129 [DQSOSCAuto] RK0, (LSB)MR18= 0x1816, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
8010 23:22:49.496539 CH0 RK0: MR19=303, MR18=1816
8011 23:22:49.503193 CH0_RK0: MR19=0x303, MR18=0x1816, DQSOSC=397, MR23=63, INC=23, DEC=15
8012 23:22:49.503301
8013 23:22:49.506671 ----->DramcWriteLeveling(PI) begin...
8014 23:22:49.506745 ==
8015 23:22:49.509658 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 23:22:49.512858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 23:22:49.512930 ==
8018 23:22:49.516420 Write leveling (Byte 0): 33 => 33
8019 23:22:49.519547 Write leveling (Byte 1): 28 => 28
8020 23:22:49.522870 DramcWriteLeveling(PI) end<-----
8021 23:22:49.522974
8022 23:22:49.523075 ==
8023 23:22:49.526313 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 23:22:49.529195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 23:22:49.532618 ==
8026 23:22:49.532714 [Gating] SW mode calibration
8027 23:22:49.542800 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8028 23:22:49.546022 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8029 23:22:49.549434 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 23:22:49.555607 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 23:22:49.559184 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8032 23:22:49.562006 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8033 23:22:49.569258 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
8034 23:22:49.571815 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8035 23:22:49.575194 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 23:22:49.582147 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 23:22:49.585001 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 23:22:49.591981 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8039 23:22:49.594744 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8040 23:22:49.598544 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 1)
8041 23:22:49.604669 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8042 23:22:49.607968 1 5 20 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8043 23:22:49.611477 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 23:22:49.618151 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 23:22:49.621319 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 23:22:49.624894 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8047 23:22:49.631331 1 6 8 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
8048 23:22:49.634328 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8049 23:22:49.638080 1 6 16 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
8050 23:22:49.644823 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8051 23:22:49.647504 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 23:22:49.650880 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 23:22:49.657405 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 23:22:49.660479 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 23:22:49.664149 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8056 23:22:49.670593 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8057 23:22:49.673960 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8058 23:22:49.677088 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8059 23:22:49.683638 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 23:22:49.686991 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 23:22:49.690485 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 23:22:49.696899 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 23:22:49.700377 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 23:22:49.703718 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 23:22:49.710429 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 23:22:49.713595 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 23:22:49.716759 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 23:22:49.723545 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 23:22:49.726902 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 23:22:49.729925 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8071 23:22:49.736802 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8072 23:22:49.736926 Total UI for P1: 0, mck2ui 16
8073 23:22:49.743184 best dqsien dly found for B0: ( 1, 9, 4)
8074 23:22:49.746290 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8075 23:22:49.749603 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8076 23:22:49.756459 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8077 23:22:49.759828 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 23:22:49.762939 Total UI for P1: 0, mck2ui 16
8079 23:22:49.766319 best dqsien dly found for B1: ( 1, 9, 18)
8080 23:22:49.769649 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8081 23:22:49.773017 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8082 23:22:49.773122
8083 23:22:49.775796 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8084 23:22:49.779198 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8085 23:22:49.782288 [Gating] SW calibration Done
8086 23:22:49.782361 ==
8087 23:22:49.785883 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 23:22:49.789152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 23:22:49.792549 ==
8090 23:22:49.792626 RX Vref Scan: 0
8091 23:22:49.792687
8092 23:22:49.795543 RX Vref 0 -> 0, step: 1
8093 23:22:49.795658
8094 23:22:49.798994 RX Delay 0 -> 252, step: 8
8095 23:22:49.802223 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8096 23:22:49.805640 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8097 23:22:49.808726 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8098 23:22:49.812043 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8099 23:22:49.818735 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8100 23:22:49.822110 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8101 23:22:49.825310 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8102 23:22:49.828526 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8103 23:22:49.831836 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8104 23:22:49.838835 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8105 23:22:49.841501 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8106 23:22:49.844889 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8107 23:22:49.848184 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8108 23:22:49.855143 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8109 23:22:49.857889 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8110 23:22:49.861464 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8111 23:22:49.861566 ==
8112 23:22:49.864637 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 23:22:49.867868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 23:22:49.867942 ==
8115 23:22:49.871342 DQS Delay:
8116 23:22:49.871432 DQS0 = 0, DQS1 = 0
8117 23:22:49.874405 DQM Delay:
8118 23:22:49.874478 DQM0 = 132, DQM1 = 124
8119 23:22:49.877960 DQ Delay:
8120 23:22:49.881582 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8121 23:22:49.884832 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8122 23:22:49.887749 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8123 23:22:49.890827 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8124 23:22:49.890914
8125 23:22:49.890975
8126 23:22:49.891033 ==
8127 23:22:49.894510 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 23:22:49.897817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 23:22:49.897899 ==
8130 23:22:49.897960
8131 23:22:49.900857
8132 23:22:49.900934 TX Vref Scan disable
8133 23:22:49.903989 == TX Byte 0 ==
8134 23:22:49.907450 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8135 23:22:49.911261 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8136 23:22:49.914328 == TX Byte 1 ==
8137 23:22:49.917507 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8138 23:22:49.920906 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8139 23:22:49.920983 ==
8140 23:22:49.924049 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 23:22:49.930366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 23:22:49.930468 ==
8143 23:22:49.943253
8144 23:22:49.946086 TX Vref early break, caculate TX vref
8145 23:22:49.949389 TX Vref=16, minBit 1, minWin=23, winSum=385
8146 23:22:49.952532 TX Vref=18, minBit 3, minWin=23, winSum=387
8147 23:22:49.955877 TX Vref=20, minBit 9, minWin=24, winSum=403
8148 23:22:49.958928 TX Vref=22, minBit 1, minWin=24, winSum=406
8149 23:22:49.962604 TX Vref=24, minBit 1, minWin=25, winSum=412
8150 23:22:49.969114 TX Vref=26, minBit 0, minWin=26, winSum=421
8151 23:22:49.972503 TX Vref=28, minBit 4, minWin=25, winSum=425
8152 23:22:49.975829 TX Vref=30, minBit 5, minWin=25, winSum=420
8153 23:22:49.978784 TX Vref=32, minBit 1, minWin=25, winSum=408
8154 23:22:49.982133 TX Vref=34, minBit 3, minWin=24, winSum=401
8155 23:22:49.988804 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 26
8156 23:22:49.988887
8157 23:22:49.992217 Final TX Range 0 Vref 26
8158 23:22:49.992289
8159 23:22:49.992358 ==
8160 23:22:49.995509 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 23:22:49.998900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 23:22:49.998971 ==
8163 23:22:49.999032
8164 23:22:49.999097
8165 23:22:50.002002 TX Vref Scan disable
8166 23:22:50.008403 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8167 23:22:50.008500 == TX Byte 0 ==
8168 23:22:50.011907 u2DelayCellOfst[0]=10 cells (3 PI)
8169 23:22:50.014999 u2DelayCellOfst[1]=14 cells (4 PI)
8170 23:22:50.019021 u2DelayCellOfst[2]=7 cells (2 PI)
8171 23:22:50.021519 u2DelayCellOfst[3]=10 cells (3 PI)
8172 23:22:50.025114 u2DelayCellOfst[4]=7 cells (2 PI)
8173 23:22:50.028329 u2DelayCellOfst[5]=0 cells (0 PI)
8174 23:22:50.031614 u2DelayCellOfst[6]=14 cells (4 PI)
8175 23:22:50.034927 u2DelayCellOfst[7]=14 cells (4 PI)
8176 23:22:50.038384 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8177 23:22:50.041909 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8178 23:22:50.044921 == TX Byte 1 ==
8179 23:22:50.048377 u2DelayCellOfst[8]=0 cells (0 PI)
8180 23:22:50.051418 u2DelayCellOfst[9]=0 cells (0 PI)
8181 23:22:50.054478 u2DelayCellOfst[10]=7 cells (2 PI)
8182 23:22:50.054597 u2DelayCellOfst[11]=3 cells (1 PI)
8183 23:22:50.058166 u2DelayCellOfst[12]=10 cells (3 PI)
8184 23:22:50.061536 u2DelayCellOfst[13]=10 cells (3 PI)
8185 23:22:50.064746 u2DelayCellOfst[14]=14 cells (4 PI)
8186 23:22:50.067827 u2DelayCellOfst[15]=10 cells (3 PI)
8187 23:22:50.074364 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8188 23:22:50.077587 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8189 23:22:50.077706 DramC Write-DBI on
8190 23:22:50.080978 ==
8191 23:22:50.081103 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 23:22:50.087863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 23:22:50.087996 ==
8194 23:22:50.088127
8195 23:22:50.088229
8196 23:22:50.091483 TX Vref Scan disable
8197 23:22:50.091599 == TX Byte 0 ==
8198 23:22:50.097563 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8199 23:22:50.097642 == TX Byte 1 ==
8200 23:22:50.101082 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8201 23:22:50.104100 DramC Write-DBI off
8202 23:22:50.104214
8203 23:22:50.104343 [DATLAT]
8204 23:22:50.107269 Freq=1600, CH0 RK1
8205 23:22:50.107408
8206 23:22:50.107528 DATLAT Default: 0xf
8207 23:22:50.110439 0, 0xFFFF, sum = 0
8208 23:22:50.110553 1, 0xFFFF, sum = 0
8209 23:22:50.113906 2, 0xFFFF, sum = 0
8210 23:22:50.114033 3, 0xFFFF, sum = 0
8211 23:22:50.117263 4, 0xFFFF, sum = 0
8212 23:22:50.120787 5, 0xFFFF, sum = 0
8213 23:22:50.120859 6, 0xFFFF, sum = 0
8214 23:22:50.124271 7, 0xFFFF, sum = 0
8215 23:22:50.124400 8, 0xFFFF, sum = 0
8216 23:22:50.127303 9, 0xFFFF, sum = 0
8217 23:22:50.127439 10, 0xFFFF, sum = 0
8218 23:22:50.130505 11, 0xFFFF, sum = 0
8219 23:22:50.130602 12, 0xFFFF, sum = 0
8220 23:22:50.133750 13, 0xFFFF, sum = 0
8221 23:22:50.133824 14, 0x0, sum = 1
8222 23:22:50.136908 15, 0x0, sum = 2
8223 23:22:50.136979 16, 0x0, sum = 3
8224 23:22:50.140316 17, 0x0, sum = 4
8225 23:22:50.140428 best_step = 15
8226 23:22:50.140530
8227 23:22:50.140615 ==
8228 23:22:50.143429 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 23:22:50.150101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 23:22:50.150237 ==
8231 23:22:50.150388 RX Vref Scan: 0
8232 23:22:50.150524
8233 23:22:50.153445 RX Vref 0 -> 0, step: 1
8234 23:22:50.153563
8235 23:22:50.156870 RX Delay 11 -> 252, step: 4
8236 23:22:50.159972 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8237 23:22:50.163323 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8238 23:22:50.166443 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8239 23:22:50.173185 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8240 23:22:50.176488 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8241 23:22:50.179745 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8242 23:22:50.183134 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8243 23:22:50.186581 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8244 23:22:50.192892 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8245 23:22:50.195974 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8246 23:22:50.199292 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8247 23:22:50.202562 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8248 23:22:50.209550 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8249 23:22:50.212554 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8250 23:22:50.215662 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8251 23:22:50.219698 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8252 23:22:50.219795 ==
8253 23:22:50.222247 Dram Type= 6, Freq= 0, CH_0, rank 1
8254 23:22:50.229002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 23:22:50.229105 ==
8256 23:22:50.229182 DQS Delay:
8257 23:22:50.229241 DQS0 = 0, DQS1 = 0
8258 23:22:50.232240 DQM Delay:
8259 23:22:50.232450 DQM0 = 128, DQM1 = 123
8260 23:22:50.235839 DQ Delay:
8261 23:22:50.239050 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8262 23:22:50.242162 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134
8263 23:22:50.245418 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8264 23:22:50.249230 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =128
8265 23:22:50.249310
8266 23:22:50.249373
8267 23:22:50.249449
8268 23:22:50.252407 [DramC_TX_OE_Calibration] TA2
8269 23:22:50.255781 Original DQ_B0 (3 6) =30, OEN = 27
8270 23:22:50.258876 Original DQ_B1 (3 6) =30, OEN = 27
8271 23:22:50.262150 24, 0x0, End_B0=24 End_B1=24
8272 23:22:50.262249 25, 0x0, End_B0=25 End_B1=25
8273 23:22:50.265420 26, 0x0, End_B0=26 End_B1=26
8274 23:22:50.268789 27, 0x0, End_B0=27 End_B1=27
8275 23:22:50.271832 28, 0x0, End_B0=28 End_B1=28
8276 23:22:50.275553 29, 0x0, End_B0=29 End_B1=29
8277 23:22:50.275634 30, 0x0, End_B0=30 End_B1=30
8278 23:22:50.278589 31, 0x4141, End_B0=30 End_B1=30
8279 23:22:50.281691 Byte0 end_step=30 best_step=27
8280 23:22:50.284937 Byte1 end_step=30 best_step=27
8281 23:22:50.288363 Byte0 TX OE(2T, 0.5T) = (3, 3)
8282 23:22:50.291493 Byte1 TX OE(2T, 0.5T) = (3, 3)
8283 23:22:50.291616
8284 23:22:50.291681
8285 23:22:50.298071 [DQSOSCAuto] RK1, (LSB)MR18= 0x1513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8286 23:22:50.301747 CH0 RK1: MR19=303, MR18=1513
8287 23:22:50.308182 CH0_RK1: MR19=0x303, MR18=0x1513, DQSOSC=399, MR23=63, INC=23, DEC=15
8288 23:22:50.311631 [RxdqsGatingPostProcess] freq 1600
8289 23:22:50.317963 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8290 23:22:50.318075 best DQS0 dly(2T, 0.5T) = (1, 1)
8291 23:22:50.321276 best DQS1 dly(2T, 0.5T) = (1, 1)
8292 23:22:50.324913 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8293 23:22:50.327609 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8294 23:22:50.331089 best DQS0 dly(2T, 0.5T) = (1, 1)
8295 23:22:50.334220 best DQS1 dly(2T, 0.5T) = (1, 1)
8296 23:22:50.338012 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8297 23:22:50.341320 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8298 23:22:50.344404 Pre-setting of DQS Precalculation
8299 23:22:50.347817 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8300 23:22:50.347928 ==
8301 23:22:50.350859 Dram Type= 6, Freq= 0, CH_1, rank 0
8302 23:22:50.357543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8303 23:22:50.357649 ==
8304 23:22:50.360540 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8305 23:22:50.367280 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8306 23:22:50.370568 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8307 23:22:50.377360 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8308 23:22:50.385301 [CA 0] Center 42 (12~72) winsize 61
8309 23:22:50.388392 [CA 1] Center 42 (13~72) winsize 60
8310 23:22:50.391789 [CA 2] Center 38 (9~68) winsize 60
8311 23:22:50.395017 [CA 3] Center 37 (8~67) winsize 60
8312 23:22:50.398892 [CA 4] Center 38 (8~68) winsize 61
8313 23:22:50.402026 [CA 5] Center 37 (8~67) winsize 60
8314 23:22:50.402125
8315 23:22:50.404896 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8316 23:22:50.404992
8317 23:22:50.408424 [CATrainingPosCal] consider 1 rank data
8318 23:22:50.411786 u2DelayCellTimex100 = 275/100 ps
8319 23:22:50.418504 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8320 23:22:50.421684 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8321 23:22:50.425192 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8322 23:22:50.428324 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8323 23:22:50.431212 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8324 23:22:50.435140 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8325 23:22:50.435243
8326 23:22:50.437877 CA PerBit enable=1, Macro0, CA PI delay=37
8327 23:22:50.437991
8328 23:22:50.441083 [CBTSetCACLKResult] CA Dly = 37
8329 23:22:50.444506 CS Dly: 8 (0~39)
8330 23:22:50.447817 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8331 23:22:50.450994 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8332 23:22:50.451091 ==
8333 23:22:50.454371 Dram Type= 6, Freq= 0, CH_1, rank 1
8334 23:22:50.460917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 23:22:50.461024 ==
8336 23:22:50.464261 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8337 23:22:50.470679 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8338 23:22:50.473901 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8339 23:22:50.480760 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8340 23:22:50.488388 [CA 0] Center 42 (12~72) winsize 61
8341 23:22:50.491320 [CA 1] Center 42 (13~72) winsize 60
8342 23:22:50.494935 [CA 2] Center 38 (9~68) winsize 60
8343 23:22:50.498128 [CA 3] Center 37 (8~66) winsize 59
8344 23:22:50.501439 [CA 4] Center 37 (7~68) winsize 62
8345 23:22:50.505187 [CA 5] Center 37 (7~67) winsize 61
8346 23:22:50.505274
8347 23:22:50.508263 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8348 23:22:50.508366
8349 23:22:50.511565 [CATrainingPosCal] consider 2 rank data
8350 23:22:50.514874 u2DelayCellTimex100 = 275/100 ps
8351 23:22:50.521500 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8352 23:22:50.524517 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8353 23:22:50.527886 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8354 23:22:50.531444 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8355 23:22:50.534207 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8356 23:22:50.537510 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8357 23:22:50.537610
8358 23:22:50.540842 CA PerBit enable=1, Macro0, CA PI delay=37
8359 23:22:50.540945
8360 23:22:50.544828 [CBTSetCACLKResult] CA Dly = 37
8361 23:22:50.547198 CS Dly: 9 (0~42)
8362 23:22:50.550815 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8363 23:22:50.554233 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8364 23:22:50.554331
8365 23:22:50.557360 ----->DramcWriteLeveling(PI) begin...
8366 23:22:50.557463 ==
8367 23:22:50.560536 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 23:22:50.566978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 23:22:50.567092 ==
8370 23:22:50.570330 Write leveling (Byte 0): 26 => 26
8371 23:22:50.573694 Write leveling (Byte 1): 26 => 26
8372 23:22:50.577281 DramcWriteLeveling(PI) end<-----
8373 23:22:50.577385
8374 23:22:50.577476 ==
8375 23:22:50.580335 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 23:22:50.583661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 23:22:50.583766 ==
8378 23:22:50.587025 [Gating] SW mode calibration
8379 23:22:50.593537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8380 23:22:50.600025 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8381 23:22:50.603268 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 23:22:50.606688 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 23:22:50.613039 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8384 23:22:50.616537 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8385 23:22:50.619993 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 23:22:50.626396 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 23:22:50.629461 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 23:22:50.633089 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 23:22:50.639663 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 23:22:50.643148 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 23:22:50.646222 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8392 23:22:50.652698 1 5 12 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 1)
8393 23:22:50.656223 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 23:22:50.659115 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 23:22:50.665739 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 23:22:50.669434 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 23:22:50.672578 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 23:22:50.679045 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 23:22:50.682369 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 23:22:50.685749 1 6 12 | B1->B0 | 2626 3e3e | 0 1 | (0 0) (0 0)
8401 23:22:50.692263 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8402 23:22:50.695495 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 23:22:50.698748 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 23:22:50.705356 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 23:22:50.708946 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 23:22:50.711860 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 23:22:50.718746 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8408 23:22:50.721981 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8409 23:22:50.725339 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8410 23:22:50.731571 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 23:22:50.735405 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 23:22:50.738136 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 23:22:50.744855 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 23:22:50.748515 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 23:22:50.751627 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 23:22:50.758069 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 23:22:50.761591 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 23:22:50.764830 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 23:22:50.771534 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 23:22:50.774858 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 23:22:50.777543 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 23:22:50.784421 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 23:22:50.787710 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8424 23:22:50.791037 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8425 23:22:50.797665 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8426 23:22:50.797750 Total UI for P1: 0, mck2ui 16
8427 23:22:50.803903 best dqsien dly found for B0: ( 1, 9, 10)
8428 23:22:50.807384 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 23:22:50.810256 Total UI for P1: 0, mck2ui 16
8430 23:22:50.814042 best dqsien dly found for B1: ( 1, 9, 14)
8431 23:22:50.817260 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8432 23:22:50.820246 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8433 23:22:50.820329
8434 23:22:50.823779 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8435 23:22:50.827158 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8436 23:22:50.830163 [Gating] SW calibration Done
8437 23:22:50.830286 ==
8438 23:22:50.833424 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 23:22:50.840209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 23:22:50.840330 ==
8441 23:22:50.840446 RX Vref Scan: 0
8442 23:22:50.840559
8443 23:22:50.843579 RX Vref 0 -> 0, step: 1
8444 23:22:50.843701
8445 23:22:50.847004 RX Delay 0 -> 252, step: 8
8446 23:22:50.850491 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8447 23:22:50.853383 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8448 23:22:50.856607 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8449 23:22:50.859882 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8450 23:22:50.866758 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8451 23:22:50.869982 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8452 23:22:50.873522 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8453 23:22:50.876762 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8454 23:22:50.879705 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8455 23:22:50.886225 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8456 23:22:50.889449 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8457 23:22:50.892731 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8458 23:22:50.896003 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8459 23:22:50.902560 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8460 23:22:50.906061 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8461 23:22:50.909387 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8462 23:22:50.909493 ==
8463 23:22:50.912713 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 23:22:50.915967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 23:22:50.919076 ==
8466 23:22:50.919157 DQS Delay:
8467 23:22:50.919221 DQS0 = 0, DQS1 = 0
8468 23:22:50.922703 DQM Delay:
8469 23:22:50.922810 DQM0 = 134, DQM1 = 129
8470 23:22:50.925977 DQ Delay:
8471 23:22:50.928922 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8472 23:22:50.932335 DQ4 =127, DQ5 =147, DQ6 =147, DQ7 =127
8473 23:22:50.935718 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =127
8474 23:22:50.938889 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8475 23:22:50.938970
8476 23:22:50.939033
8477 23:22:50.939091 ==
8478 23:22:50.942614 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 23:22:50.945176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 23:22:50.945280 ==
8481 23:22:50.948895
8482 23:22:50.949038
8483 23:22:50.949103 TX Vref Scan disable
8484 23:22:50.951973 == TX Byte 0 ==
8485 23:22:50.955404 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8486 23:22:50.959073 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8487 23:22:50.962130 == TX Byte 1 ==
8488 23:22:50.965557 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8489 23:22:50.968947 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8490 23:22:50.969082 ==
8491 23:22:50.972045 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 23:22:50.978225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 23:22:50.978315 ==
8494 23:22:50.990182
8495 23:22:50.993220 TX Vref early break, caculate TX vref
8496 23:22:50.996735 TX Vref=16, minBit 8, minWin=21, winSum=370
8497 23:22:51.000002 TX Vref=18, minBit 8, minWin=22, winSum=379
8498 23:22:51.003282 TX Vref=20, minBit 3, minWin=23, winSum=389
8499 23:22:51.006341 TX Vref=22, minBit 8, minWin=23, winSum=394
8500 23:22:51.009925 TX Vref=24, minBit 1, minWin=25, winSum=410
8501 23:22:51.016701 TX Vref=26, minBit 3, minWin=25, winSum=416
8502 23:22:51.019711 TX Vref=28, minBit 0, minWin=25, winSum=419
8503 23:22:51.023092 TX Vref=30, minBit 9, minWin=25, winSum=416
8504 23:22:51.026151 TX Vref=32, minBit 0, minWin=24, winSum=406
8505 23:22:51.029325 TX Vref=34, minBit 8, minWin=23, winSum=394
8506 23:22:51.035874 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8507 23:22:51.036006
8508 23:22:51.038961 Final TX Range 0 Vref 28
8509 23:22:51.039088
8510 23:22:51.039202 ==
8511 23:22:51.042345 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 23:22:51.046165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 23:22:51.046246 ==
8514 23:22:51.046311
8515 23:22:51.046372
8516 23:22:51.049306 TX Vref Scan disable
8517 23:22:51.055889 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8518 23:22:51.056003 == TX Byte 0 ==
8519 23:22:51.059090 u2DelayCellOfst[0]=14 cells (4 PI)
8520 23:22:51.062409 u2DelayCellOfst[1]=10 cells (3 PI)
8521 23:22:51.065822 u2DelayCellOfst[2]=0 cells (0 PI)
8522 23:22:51.069367 u2DelayCellOfst[3]=7 cells (2 PI)
8523 23:22:51.072549 u2DelayCellOfst[4]=10 cells (3 PI)
8524 23:22:51.076037 u2DelayCellOfst[5]=17 cells (5 PI)
8525 23:22:51.079244 u2DelayCellOfst[6]=17 cells (5 PI)
8526 23:22:51.082054 u2DelayCellOfst[7]=7 cells (2 PI)
8527 23:22:51.085410 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8528 23:22:51.089003 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8529 23:22:51.092437 == TX Byte 1 ==
8530 23:22:51.095708 u2DelayCellOfst[8]=0 cells (0 PI)
8531 23:22:51.099179 u2DelayCellOfst[9]=3 cells (1 PI)
8532 23:22:51.102108 u2DelayCellOfst[10]=10 cells (3 PI)
8533 23:22:51.102191 u2DelayCellOfst[11]=7 cells (2 PI)
8534 23:22:51.105915 u2DelayCellOfst[12]=14 cells (4 PI)
8535 23:22:51.108561 u2DelayCellOfst[13]=14 cells (4 PI)
8536 23:22:51.111533 u2DelayCellOfst[14]=17 cells (5 PI)
8537 23:22:51.115078 u2DelayCellOfst[15]=17 cells (5 PI)
8538 23:22:51.121973 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8539 23:22:51.125248 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8540 23:22:51.125332 DramC Write-DBI on
8541 23:22:51.128300 ==
8542 23:22:51.131324 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 23:22:51.134720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 23:22:51.134820 ==
8545 23:22:51.134909
8546 23:22:51.134995
8547 23:22:51.138164 TX Vref Scan disable
8548 23:22:51.138272 == TX Byte 0 ==
8549 23:22:51.144855 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8550 23:22:51.144937 == TX Byte 1 ==
8551 23:22:51.147878 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8552 23:22:51.151214 DramC Write-DBI off
8553 23:22:51.151327
8554 23:22:51.151415 [DATLAT]
8555 23:22:51.154350 Freq=1600, CH1 RK0
8556 23:22:51.154457
8557 23:22:51.154558 DATLAT Default: 0xf
8558 23:22:51.157974 0, 0xFFFF, sum = 0
8559 23:22:51.158057 1, 0xFFFF, sum = 0
8560 23:22:51.161714 2, 0xFFFF, sum = 0
8561 23:22:51.161822 3, 0xFFFF, sum = 0
8562 23:22:51.164460 4, 0xFFFF, sum = 0
8563 23:22:51.167784 5, 0xFFFF, sum = 0
8564 23:22:51.167874 6, 0xFFFF, sum = 0
8565 23:22:51.170994 7, 0xFFFF, sum = 0
8566 23:22:51.171077 8, 0xFFFF, sum = 0
8567 23:22:51.174163 9, 0xFFFF, sum = 0
8568 23:22:51.174287 10, 0xFFFF, sum = 0
8569 23:22:51.177807 11, 0xFFFF, sum = 0
8570 23:22:51.177917 12, 0xFFFF, sum = 0
8571 23:22:51.181160 13, 0xFFFF, sum = 0
8572 23:22:51.181243 14, 0x0, sum = 1
8573 23:22:51.184085 15, 0x0, sum = 2
8574 23:22:51.184167 16, 0x0, sum = 3
8575 23:22:51.187642 17, 0x0, sum = 4
8576 23:22:51.187724 best_step = 15
8577 23:22:51.187794
8578 23:22:51.187855 ==
8579 23:22:51.190733 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 23:22:51.197349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 23:22:51.197468 ==
8582 23:22:51.197561 RX Vref Scan: 1
8583 23:22:51.197669
8584 23:22:51.200782 Set Vref Range= 24 -> 127
8585 23:22:51.200855
8586 23:22:51.203516 RX Vref 24 -> 127, step: 1
8587 23:22:51.203586
8588 23:22:51.203646 RX Delay 11 -> 252, step: 4
8589 23:22:51.206740
8590 23:22:51.206847 Set Vref, RX VrefLevel [Byte0]: 24
8591 23:22:51.210151 [Byte1]: 24
8592 23:22:51.214724
8593 23:22:51.214833 Set Vref, RX VrefLevel [Byte0]: 25
8594 23:22:51.218059 [Byte1]: 25
8595 23:22:51.222145
8596 23:22:51.222227 Set Vref, RX VrefLevel [Byte0]: 26
8597 23:22:51.225450 [Byte1]: 26
8598 23:22:51.229859
8599 23:22:51.229940 Set Vref, RX VrefLevel [Byte0]: 27
8600 23:22:51.233023 [Byte1]: 27
8601 23:22:51.237758
8602 23:22:51.237839 Set Vref, RX VrefLevel [Byte0]: 28
8603 23:22:51.240444 [Byte1]: 28
8604 23:22:51.245044
8605 23:22:51.245126 Set Vref, RX VrefLevel [Byte0]: 29
8606 23:22:51.248150 [Byte1]: 29
8607 23:22:51.252542
8608 23:22:51.252651 Set Vref, RX VrefLevel [Byte0]: 30
8609 23:22:51.256191 [Byte1]: 30
8610 23:22:51.260428
8611 23:22:51.260510 Set Vref, RX VrefLevel [Byte0]: 31
8612 23:22:51.263311 [Byte1]: 31
8613 23:22:51.267697
8614 23:22:51.267803 Set Vref, RX VrefLevel [Byte0]: 32
8615 23:22:51.271129 [Byte1]: 32
8616 23:22:51.275285
8617 23:22:51.275405 Set Vref, RX VrefLevel [Byte0]: 33
8618 23:22:51.278450 [Byte1]: 33
8619 23:22:51.283225
8620 23:22:51.283328 Set Vref, RX VrefLevel [Byte0]: 34
8621 23:22:51.286609 [Byte1]: 34
8622 23:22:51.290343
8623 23:22:51.290434 Set Vref, RX VrefLevel [Byte0]: 35
8624 23:22:51.294202 [Byte1]: 35
8625 23:22:51.298322
8626 23:22:51.298430 Set Vref, RX VrefLevel [Byte0]: 36
8627 23:22:51.301739 [Byte1]: 36
8628 23:22:51.306123
8629 23:22:51.306205 Set Vref, RX VrefLevel [Byte0]: 37
8630 23:22:51.309593 [Byte1]: 37
8631 23:22:51.313437
8632 23:22:51.313565 Set Vref, RX VrefLevel [Byte0]: 38
8633 23:22:51.316631 [Byte1]: 38
8634 23:22:51.321331
8635 23:22:51.321451 Set Vref, RX VrefLevel [Byte0]: 39
8636 23:22:51.324460 [Byte1]: 39
8637 23:22:51.328453
8638 23:22:51.328575 Set Vref, RX VrefLevel [Byte0]: 40
8639 23:22:51.331947 [Byte1]: 40
8640 23:22:51.336418
8641 23:22:51.336499 Set Vref, RX VrefLevel [Byte0]: 41
8642 23:22:51.339472 [Byte1]: 41
8643 23:22:51.343958
8644 23:22:51.344039 Set Vref, RX VrefLevel [Byte0]: 42
8645 23:22:51.347184 [Byte1]: 42
8646 23:22:51.351645
8647 23:22:51.351732 Set Vref, RX VrefLevel [Byte0]: 43
8648 23:22:51.354616 [Byte1]: 43
8649 23:22:51.359239
8650 23:22:51.359346 Set Vref, RX VrefLevel [Byte0]: 44
8651 23:22:51.362224 [Byte1]: 44
8652 23:22:51.366836
8653 23:22:51.366939 Set Vref, RX VrefLevel [Byte0]: 45
8654 23:22:51.370004 [Byte1]: 45
8655 23:22:51.374330
8656 23:22:51.374402 Set Vref, RX VrefLevel [Byte0]: 46
8657 23:22:51.377759 [Byte1]: 46
8658 23:22:51.382109
8659 23:22:51.382191 Set Vref, RX VrefLevel [Byte0]: 47
8660 23:22:51.385577 [Byte1]: 47
8661 23:22:51.389972
8662 23:22:51.390053 Set Vref, RX VrefLevel [Byte0]: 48
8663 23:22:51.393291 [Byte1]: 48
8664 23:22:51.397471
8665 23:22:51.397553 Set Vref, RX VrefLevel [Byte0]: 49
8666 23:22:51.400669 [Byte1]: 49
8667 23:22:51.404741
8668 23:22:51.404823 Set Vref, RX VrefLevel [Byte0]: 50
8669 23:22:51.408541 [Byte1]: 50
8670 23:22:51.412343
8671 23:22:51.412424 Set Vref, RX VrefLevel [Byte0]: 51
8672 23:22:51.415872 [Byte1]: 51
8673 23:22:51.420048
8674 23:22:51.420129 Set Vref, RX VrefLevel [Byte0]: 52
8675 23:22:51.423527 [Byte1]: 52
8676 23:22:51.427915
8677 23:22:51.427996 Set Vref, RX VrefLevel [Byte0]: 53
8678 23:22:51.431063 [Byte1]: 53
8679 23:22:51.435185
8680 23:22:51.435293 Set Vref, RX VrefLevel [Byte0]: 54
8681 23:22:51.438398 [Byte1]: 54
8682 23:22:51.442767
8683 23:22:51.442854 Set Vref, RX VrefLevel [Byte0]: 55
8684 23:22:51.446000 [Byte1]: 55
8685 23:22:51.450535
8686 23:22:51.450617 Set Vref, RX VrefLevel [Byte0]: 56
8687 23:22:51.453988 [Byte1]: 56
8688 23:22:51.458633
8689 23:22:51.458728 Set Vref, RX VrefLevel [Byte0]: 57
8690 23:22:51.461381 [Byte1]: 57
8691 23:22:51.465592
8692 23:22:51.465674 Set Vref, RX VrefLevel [Byte0]: 58
8693 23:22:51.468875 [Byte1]: 58
8694 23:22:51.473595
8695 23:22:51.473676 Set Vref, RX VrefLevel [Byte0]: 59
8696 23:22:51.476554 [Byte1]: 59
8697 23:22:51.481389
8698 23:22:51.481470 Set Vref, RX VrefLevel [Byte0]: 60
8699 23:22:51.484220 [Byte1]: 60
8700 23:22:51.488441
8701 23:22:51.488565 Set Vref, RX VrefLevel [Byte0]: 61
8702 23:22:51.491959 [Byte1]: 61
8703 23:22:51.496503
8704 23:22:51.496608 Set Vref, RX VrefLevel [Byte0]: 62
8705 23:22:51.499706 [Byte1]: 62
8706 23:22:51.503795
8707 23:22:51.503876 Set Vref, RX VrefLevel [Byte0]: 63
8708 23:22:51.507180 [Byte1]: 63
8709 23:22:51.511412
8710 23:22:51.511493 Set Vref, RX VrefLevel [Byte0]: 64
8711 23:22:51.514421 [Byte1]: 64
8712 23:22:51.519148
8713 23:22:51.519259 Set Vref, RX VrefLevel [Byte0]: 65
8714 23:22:51.522203 [Byte1]: 65
8715 23:22:51.526576
8716 23:22:51.526659 Set Vref, RX VrefLevel [Byte0]: 66
8717 23:22:51.529811 [Byte1]: 66
8718 23:22:51.534371
8719 23:22:51.534453 Set Vref, RX VrefLevel [Byte0]: 67
8720 23:22:51.537654 [Byte1]: 67
8721 23:22:51.541781
8722 23:22:51.541863 Set Vref, RX VrefLevel [Byte0]: 68
8723 23:22:51.545370 [Byte1]: 68
8724 23:22:51.549450
8725 23:22:51.549532 Set Vref, RX VrefLevel [Byte0]: 69
8726 23:22:51.552784 [Byte1]: 69
8727 23:22:51.557005
8728 23:22:51.557096 Set Vref, RX VrefLevel [Byte0]: 70
8729 23:22:51.560854 [Byte1]: 70
8730 23:22:51.565016
8731 23:22:51.565090 Set Vref, RX VrefLevel [Byte0]: 71
8732 23:22:51.568611 [Byte1]: 71
8733 23:22:51.572183
8734 23:22:51.572266 Set Vref, RX VrefLevel [Byte0]: 72
8735 23:22:51.575485 [Byte1]: 72
8736 23:22:51.580370
8737 23:22:51.580461 Set Vref, RX VrefLevel [Byte0]: 73
8738 23:22:51.583024 [Byte1]: 73
8739 23:22:51.587510
8740 23:22:51.587592 Final RX Vref Byte 0 = 58 to rank0
8741 23:22:51.590729 Final RX Vref Byte 1 = 56 to rank0
8742 23:22:51.594239 Final RX Vref Byte 0 = 58 to rank1
8743 23:22:51.597304 Final RX Vref Byte 1 = 56 to rank1==
8744 23:22:51.601199 Dram Type= 6, Freq= 0, CH_1, rank 0
8745 23:22:51.607471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8746 23:22:51.607556 ==
8747 23:22:51.607619 DQS Delay:
8748 23:22:51.610659 DQS0 = 0, DQS1 = 0
8749 23:22:51.610754 DQM Delay:
8750 23:22:51.610849 DQM0 = 132, DQM1 = 128
8751 23:22:51.613827 DQ Delay:
8752 23:22:51.617073 DQ0 =140, DQ1 =128, DQ2 =118, DQ3 =130
8753 23:22:51.620690 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8754 23:22:51.623933 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =122
8755 23:22:51.627188 DQ12 =138, DQ13 =136, DQ14 =134, DQ15 =140
8756 23:22:51.627287
8757 23:22:51.627431
8758 23:22:51.627507
8759 23:22:51.630486 [DramC_TX_OE_Calibration] TA2
8760 23:22:51.634100 Original DQ_B0 (3 6) =30, OEN = 27
8761 23:22:51.636979 Original DQ_B1 (3 6) =30, OEN = 27
8762 23:22:51.640372 24, 0x0, End_B0=24 End_B1=24
8763 23:22:51.640475 25, 0x0, End_B0=25 End_B1=25
8764 23:22:51.643765 26, 0x0, End_B0=26 End_B1=26
8765 23:22:51.646735 27, 0x0, End_B0=27 End_B1=27
8766 23:22:51.650333 28, 0x0, End_B0=28 End_B1=28
8767 23:22:51.653319 29, 0x0, End_B0=29 End_B1=29
8768 23:22:51.653408 30, 0x0, End_B0=30 End_B1=30
8769 23:22:51.656857 31, 0x4141, End_B0=30 End_B1=30
8770 23:22:51.659842 Byte0 end_step=30 best_step=27
8771 23:22:51.663060 Byte1 end_step=30 best_step=27
8772 23:22:51.666599 Byte0 TX OE(2T, 0.5T) = (3, 3)
8773 23:22:51.669996 Byte1 TX OE(2T, 0.5T) = (3, 3)
8774 23:22:51.670115
8775 23:22:51.670205
8776 23:22:51.676508 [DQSOSCAuto] RK0, (LSB)MR18= 0x913, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
8777 23:22:51.679843 CH1 RK0: MR19=303, MR18=913
8778 23:22:51.686700 CH1_RK0: MR19=0x303, MR18=0x913, DQSOSC=400, MR23=63, INC=23, DEC=15
8779 23:22:51.686784
8780 23:22:51.689371 ----->DramcWriteLeveling(PI) begin...
8781 23:22:51.689470 ==
8782 23:22:51.692941 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 23:22:51.696152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 23:22:51.696267 ==
8785 23:22:51.699808 Write leveling (Byte 0): 24 => 24
8786 23:22:51.702757 Write leveling (Byte 1): 26 => 26
8787 23:22:51.705970 DramcWriteLeveling(PI) end<-----
8788 23:22:51.706052
8789 23:22:51.706116 ==
8790 23:22:51.708937 Dram Type= 6, Freq= 0, CH_1, rank 1
8791 23:22:51.712381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8792 23:22:51.715646 ==
8793 23:22:51.715783 [Gating] SW mode calibration
8794 23:22:51.725682 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8795 23:22:51.728841 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8796 23:22:51.732170 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 23:22:51.739071 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 23:22:51.742621 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8799 23:22:51.745345 1 4 12 | B1->B0 | 2827 3434 | 1 1 | (0 0) (1 1)
8800 23:22:51.752391 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 23:22:51.755188 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 23:22:51.758735 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 23:22:51.765328 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 23:22:51.768223 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 23:22:51.772121 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8806 23:22:51.778302 1 5 8 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
8807 23:22:51.781629 1 5 12 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8808 23:22:51.787883 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8809 23:22:51.791747 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 23:22:51.794763 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 23:22:51.801323 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 23:22:51.804789 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 23:22:51.807714 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 23:22:51.814641 1 6 8 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8815 23:22:51.818040 1 6 12 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
8816 23:22:51.821225 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 23:22:51.828160 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 23:22:51.830685 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 23:22:51.834630 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 23:22:51.840866 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 23:22:51.843766 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 23:22:51.847482 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8823 23:22:51.854005 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8824 23:22:51.856797 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8825 23:22:51.860385 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 23:22:51.866812 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 23:22:51.870198 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 23:22:51.873203 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 23:22:51.879917 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 23:22:51.883179 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 23:22:51.886840 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 23:22:51.893122 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 23:22:51.896321 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 23:22:51.899558 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 23:22:51.906198 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 23:22:51.910014 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 23:22:51.912723 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8838 23:22:51.919986 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8839 23:22:51.922414 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8840 23:22:51.925820 Total UI for P1: 0, mck2ui 16
8841 23:22:51.929164 best dqsien dly found for B0: ( 1, 9, 6)
8842 23:22:51.932570 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8843 23:22:51.939179 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 23:22:51.939291 Total UI for P1: 0, mck2ui 16
8845 23:22:51.945884 best dqsien dly found for B1: ( 1, 9, 14)
8846 23:22:51.948765 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8847 23:22:51.952573 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8848 23:22:51.952661
8849 23:22:51.955815 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8850 23:22:51.958859 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8851 23:22:51.962361 [Gating] SW calibration Done
8852 23:22:51.962446 ==
8853 23:22:51.965667 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 23:22:51.968478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 23:22:51.968565 ==
8856 23:22:51.971889 RX Vref Scan: 0
8857 23:22:51.971975
8858 23:22:51.972063 RX Vref 0 -> 0, step: 1
8859 23:22:51.975385
8860 23:22:51.975472 RX Delay 0 -> 252, step: 8
8861 23:22:51.981711 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8862 23:22:51.985318 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8863 23:22:51.988392 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8864 23:22:51.991787 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8865 23:22:51.995318 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8866 23:22:52.001859 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8867 23:22:52.004850 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8868 23:22:52.008105 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8869 23:22:52.011561 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8870 23:22:52.014999 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8871 23:22:52.021730 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8872 23:22:52.024483 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8873 23:22:52.027779 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8874 23:22:52.031402 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8875 23:22:52.038036 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8876 23:22:52.041241 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8877 23:22:52.041324 ==
8878 23:22:52.044740 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 23:22:52.047475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 23:22:52.047585 ==
8881 23:22:52.047679 DQS Delay:
8882 23:22:52.050933 DQS0 = 0, DQS1 = 0
8883 23:22:52.051042 DQM Delay:
8884 23:22:52.054464 DQM0 = 132, DQM1 = 130
8885 23:22:52.054547 DQ Delay:
8886 23:22:52.057404 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8887 23:22:52.060769 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8888 23:22:52.064325 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8889 23:22:52.070832 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8890 23:22:52.070915
8891 23:22:52.070981
8892 23:22:52.071040 ==
8893 23:22:52.073833 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 23:22:52.077190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 23:22:52.077273 ==
8896 23:22:52.077339
8897 23:22:52.077399
8898 23:22:52.080707 TX Vref Scan disable
8899 23:22:52.080790 == TX Byte 0 ==
8900 23:22:52.087059 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8901 23:22:52.090407 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8902 23:22:52.093786 == TX Byte 1 ==
8903 23:22:52.097022 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8904 23:22:52.100446 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8905 23:22:52.100532 ==
8906 23:22:52.103299 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 23:22:52.106684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 23:22:52.110050 ==
8909 23:22:52.121838
8910 23:22:52.125467 TX Vref early break, caculate TX vref
8911 23:22:52.128633 TX Vref=16, minBit 9, minWin=21, winSum=375
8912 23:22:52.132179 TX Vref=18, minBit 9, minWin=22, winSum=386
8913 23:22:52.135295 TX Vref=20, minBit 9, minWin=22, winSum=391
8914 23:22:52.138625 TX Vref=22, minBit 8, minWin=24, winSum=402
8915 23:22:52.141727 TX Vref=24, minBit 9, minWin=24, winSum=408
8916 23:22:52.148408 TX Vref=26, minBit 9, minWin=24, winSum=415
8917 23:22:52.151751 TX Vref=28, minBit 8, minWin=25, winSum=421
8918 23:22:52.155086 TX Vref=30, minBit 5, minWin=25, winSum=417
8919 23:22:52.158059 TX Vref=32, minBit 9, minWin=23, winSum=409
8920 23:22:52.161899 TX Vref=34, minBit 0, minWin=23, winSum=407
8921 23:22:52.167883 TX Vref=36, minBit 8, minWin=23, winSum=395
8922 23:22:52.171136 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 28
8923 23:22:52.171246
8924 23:22:52.174768 Final TX Range 0 Vref 28
8925 23:22:52.174846
8926 23:22:52.174910 ==
8927 23:22:52.177747 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 23:22:52.181577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 23:22:52.184395 ==
8930 23:22:52.184474
8931 23:22:52.184537
8932 23:22:52.184597 TX Vref Scan disable
8933 23:22:52.191102 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8934 23:22:52.191181 == TX Byte 0 ==
8935 23:22:52.194497 u2DelayCellOfst[0]=14 cells (4 PI)
8936 23:22:52.197674 u2DelayCellOfst[1]=10 cells (3 PI)
8937 23:22:52.201067 u2DelayCellOfst[2]=0 cells (0 PI)
8938 23:22:52.204740 u2DelayCellOfst[3]=7 cells (2 PI)
8939 23:22:52.207648 u2DelayCellOfst[4]=7 cells (2 PI)
8940 23:22:52.210959 u2DelayCellOfst[5]=14 cells (4 PI)
8941 23:22:52.214145 u2DelayCellOfst[6]=14 cells (4 PI)
8942 23:22:52.217638 u2DelayCellOfst[7]=7 cells (2 PI)
8943 23:22:52.220897 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8944 23:22:52.224359 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8945 23:22:52.227239 == TX Byte 1 ==
8946 23:22:52.231088 u2DelayCellOfst[8]=0 cells (0 PI)
8947 23:22:52.234392 u2DelayCellOfst[9]=0 cells (0 PI)
8948 23:22:52.237119 u2DelayCellOfst[10]=7 cells (2 PI)
8949 23:22:52.240843 u2DelayCellOfst[11]=0 cells (0 PI)
8950 23:22:52.243987 u2DelayCellOfst[12]=10 cells (3 PI)
8951 23:22:52.247303 u2DelayCellOfst[13]=10 cells (3 PI)
8952 23:22:52.247415 u2DelayCellOfst[14]=14 cells (4 PI)
8953 23:22:52.250499 u2DelayCellOfst[15]=14 cells (4 PI)
8954 23:22:52.256805 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8955 23:22:52.260592 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8956 23:22:52.263517 DramC Write-DBI on
8957 23:22:52.263601 ==
8958 23:22:52.266765 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 23:22:52.270562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 23:22:52.270646 ==
8961 23:22:52.270711
8962 23:22:52.270771
8963 23:22:52.273674 TX Vref Scan disable
8964 23:22:52.273757 == TX Byte 0 ==
8965 23:22:52.280003 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8966 23:22:52.280087 == TX Byte 1 ==
8967 23:22:52.283907 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8968 23:22:52.286584 DramC Write-DBI off
8969 23:22:52.286666
8970 23:22:52.286731 [DATLAT]
8971 23:22:52.290015 Freq=1600, CH1 RK1
8972 23:22:52.290099
8973 23:22:52.290164 DATLAT Default: 0xf
8974 23:22:52.293418 0, 0xFFFF, sum = 0
8975 23:22:52.293503 1, 0xFFFF, sum = 0
8976 23:22:52.296784 2, 0xFFFF, sum = 0
8977 23:22:52.300256 3, 0xFFFF, sum = 0
8978 23:22:52.300341 4, 0xFFFF, sum = 0
8979 23:22:52.303274 5, 0xFFFF, sum = 0
8980 23:22:52.303358 6, 0xFFFF, sum = 0
8981 23:22:52.306682 7, 0xFFFF, sum = 0
8982 23:22:52.306770 8, 0xFFFF, sum = 0
8983 23:22:52.310413 9, 0xFFFF, sum = 0
8984 23:22:52.310525 10, 0xFFFF, sum = 0
8985 23:22:52.313249 11, 0xFFFF, sum = 0
8986 23:22:52.313324 12, 0xFFFF, sum = 0
8987 23:22:52.316508 13, 0xFFFF, sum = 0
8988 23:22:52.316593 14, 0x0, sum = 1
8989 23:22:52.319617 15, 0x0, sum = 2
8990 23:22:52.319702 16, 0x0, sum = 3
8991 23:22:52.323226 17, 0x0, sum = 4
8992 23:22:52.323336 best_step = 15
8993 23:22:52.323422
8994 23:22:52.323484 ==
8995 23:22:52.325982 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 23:22:52.332806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 23:22:52.332915 ==
8998 23:22:52.333010 RX Vref Scan: 0
8999 23:22:52.333099
9000 23:22:52.335906 RX Vref 0 -> 0, step: 1
9001 23:22:52.335989
9002 23:22:52.339388 RX Delay 11 -> 252, step: 4
9003 23:22:52.342691 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9004 23:22:52.345950 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
9005 23:22:52.352404 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
9006 23:22:52.356129 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9007 23:22:52.359263 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
9008 23:22:52.362410 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9009 23:22:52.365514 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9010 23:22:52.372221 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9011 23:22:52.375486 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9012 23:22:52.378797 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9013 23:22:52.381674 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9014 23:22:52.385172 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9015 23:22:52.391797 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9016 23:22:52.394891 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9017 23:22:52.398434 iDelay=195, Bit 14, Center 132 (83 ~ 182) 100
9018 23:22:52.401592 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9019 23:22:52.401726 ==
9020 23:22:52.405245 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 23:22:52.411496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 23:22:52.411625 ==
9023 23:22:52.411742 DQS Delay:
9024 23:22:52.415630 DQS0 = 0, DQS1 = 0
9025 23:22:52.415752 DQM Delay:
9026 23:22:52.418031 DQM0 = 131, DQM1 = 127
9027 23:22:52.418156 DQ Delay:
9028 23:22:52.421506 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
9029 23:22:52.424962 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
9030 23:22:52.428135 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
9031 23:22:52.431460 DQ12 =136, DQ13 =134, DQ14 =132, DQ15 =138
9032 23:22:52.431578
9033 23:22:52.431686
9034 23:22:52.431792
9035 23:22:52.434350 [DramC_TX_OE_Calibration] TA2
9036 23:22:52.437619 Original DQ_B0 (3 6) =30, OEN = 27
9037 23:22:52.441423 Original DQ_B1 (3 6) =30, OEN = 27
9038 23:22:52.444548 24, 0x0, End_B0=24 End_B1=24
9039 23:22:52.447827 25, 0x0, End_B0=25 End_B1=25
9040 23:22:52.447958 26, 0x0, End_B0=26 End_B1=26
9041 23:22:52.451031 27, 0x0, End_B0=27 End_B1=27
9042 23:22:52.454580 28, 0x0, End_B0=28 End_B1=28
9043 23:22:52.457434 29, 0x0, End_B0=29 End_B1=29
9044 23:22:52.460736 30, 0x0, End_B0=30 End_B1=30
9045 23:22:52.460845 31, 0x4141, End_B0=30 End_B1=30
9046 23:22:52.463946 Byte0 end_step=30 best_step=27
9047 23:22:52.467285 Byte1 end_step=30 best_step=27
9048 23:22:52.471010 Byte0 TX OE(2T, 0.5T) = (3, 3)
9049 23:22:52.473841 Byte1 TX OE(2T, 0.5T) = (3, 3)
9050 23:22:52.473909
9051 23:22:52.473970
9052 23:22:52.480466 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
9053 23:22:52.483827 CH1 RK1: MR19=303, MR18=C1A
9054 23:22:52.490645 CH1_RK1: MR19=0x303, MR18=0xC1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9055 23:22:52.493982 [RxdqsGatingPostProcess] freq 1600
9056 23:22:52.500546 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9057 23:22:52.503957 best DQS0 dly(2T, 0.5T) = (1, 1)
9058 23:22:52.504030 best DQS1 dly(2T, 0.5T) = (1, 1)
9059 23:22:52.507457 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9060 23:22:52.509918 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9061 23:22:52.513211 best DQS0 dly(2T, 0.5T) = (1, 1)
9062 23:22:52.516791 best DQS1 dly(2T, 0.5T) = (1, 1)
9063 23:22:52.520170 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9064 23:22:52.523359 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9065 23:22:52.526881 Pre-setting of DQS Precalculation
9066 23:22:52.529827 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9067 23:22:52.539455 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9068 23:22:52.546218 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9069 23:22:52.546337
9070 23:22:52.546445
9071 23:22:52.549826 [Calibration Summary] 3200 Mbps
9072 23:22:52.549922 CH 0, Rank 0
9073 23:22:52.552578 SW Impedance : PASS
9074 23:22:52.555787 DUTY Scan : NO K
9075 23:22:52.555893 ZQ Calibration : PASS
9076 23:22:52.559207 Jitter Meter : NO K
9077 23:22:52.562893 CBT Training : PASS
9078 23:22:52.562976 Write leveling : PASS
9079 23:22:52.566298 RX DQS gating : PASS
9080 23:22:52.569043 RX DQ/DQS(RDDQC) : PASS
9081 23:22:52.569125 TX DQ/DQS : PASS
9082 23:22:52.572329 RX DATLAT : PASS
9083 23:22:52.572439 RX DQ/DQS(Engine): PASS
9084 23:22:52.576469 TX OE : PASS
9085 23:22:52.576553 All Pass.
9086 23:22:52.576618
9087 23:22:52.578974 CH 0, Rank 1
9088 23:22:52.579083 SW Impedance : PASS
9089 23:22:52.582328 DUTY Scan : NO K
9090 23:22:52.585665 ZQ Calibration : PASS
9091 23:22:52.585753 Jitter Meter : NO K
9092 23:22:52.588928 CBT Training : PASS
9093 23:22:52.592831 Write leveling : PASS
9094 23:22:52.592915 RX DQS gating : PASS
9095 23:22:52.596118 RX DQ/DQS(RDDQC) : PASS
9096 23:22:52.598755 TX DQ/DQS : PASS
9097 23:22:52.598839 RX DATLAT : PASS
9098 23:22:52.601925 RX DQ/DQS(Engine): PASS
9099 23:22:52.605219 TX OE : PASS
9100 23:22:52.605303 All Pass.
9101 23:22:52.605368
9102 23:22:52.605428 CH 1, Rank 0
9103 23:22:52.608551 SW Impedance : PASS
9104 23:22:52.612188 DUTY Scan : NO K
9105 23:22:52.612271 ZQ Calibration : PASS
9106 23:22:52.615828 Jitter Meter : NO K
9107 23:22:52.618572 CBT Training : PASS
9108 23:22:52.618655 Write leveling : PASS
9109 23:22:52.621711 RX DQS gating : PASS
9110 23:22:52.625401 RX DQ/DQS(RDDQC) : PASS
9111 23:22:52.625483 TX DQ/DQS : PASS
9112 23:22:52.628306 RX DATLAT : PASS
9113 23:22:52.631909 RX DQ/DQS(Engine): PASS
9114 23:22:52.631992 TX OE : PASS
9115 23:22:52.634901 All Pass.
9116 23:22:52.635009
9117 23:22:52.635102 CH 1, Rank 1
9118 23:22:52.638395 SW Impedance : PASS
9119 23:22:52.638494 DUTY Scan : NO K
9120 23:22:52.641447 ZQ Calibration : PASS
9121 23:22:52.645200 Jitter Meter : NO K
9122 23:22:52.645284 CBT Training : PASS
9123 23:22:52.648025 Write leveling : PASS
9124 23:22:52.651586 RX DQS gating : PASS
9125 23:22:52.651662 RX DQ/DQS(RDDQC) : PASS
9126 23:22:52.655031 TX DQ/DQS : PASS
9127 23:22:52.658109 RX DATLAT : PASS
9128 23:22:52.658187 RX DQ/DQS(Engine): PASS
9129 23:22:52.661541 TX OE : PASS
9130 23:22:52.661620 All Pass.
9131 23:22:52.661694
9132 23:22:52.664882 DramC Write-DBI on
9133 23:22:52.668026 PER_BANK_REFRESH: Hybrid Mode
9134 23:22:52.668099 TX_TRACKING: ON
9135 23:22:52.677985 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9136 23:22:52.684153 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9137 23:22:52.691264 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9138 23:22:52.694359 [FAST_K] Save calibration result to emmc
9139 23:22:52.697750 sync common calibartion params.
9140 23:22:52.700859 sync cbt_mode0:1, 1:1
9141 23:22:52.704195 dram_init: ddr_geometry: 2
9142 23:22:52.704288 dram_init: ddr_geometry: 2
9143 23:22:52.707742 dram_init: ddr_geometry: 2
9144 23:22:52.710461 0:dram_rank_size:100000000
9145 23:22:52.713786 1:dram_rank_size:100000000
9146 23:22:52.717477 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9147 23:22:52.720261 DFS_SHUFFLE_HW_MODE: ON
9148 23:22:52.724144 dramc_set_vcore_voltage set vcore to 725000
9149 23:22:52.726815 Read voltage for 1600, 0
9150 23:22:52.726894 Vio18 = 0
9151 23:22:52.726959 Vcore = 725000
9152 23:22:52.730459 Vdram = 0
9153 23:22:52.730533 Vddq = 0
9154 23:22:52.730603 Vmddr = 0
9155 23:22:52.733982 switch to 3200 Mbps bootup
9156 23:22:52.736804 [DramcRunTimeConfig]
9157 23:22:52.736889 PHYPLL
9158 23:22:52.736954 DPM_CONTROL_AFTERK: ON
9159 23:22:52.740088 PER_BANK_REFRESH: ON
9160 23:22:52.744041 REFRESH_OVERHEAD_REDUCTION: ON
9161 23:22:52.747301 CMD_PICG_NEW_MODE: OFF
9162 23:22:52.747408 XRTWTW_NEW_MODE: ON
9163 23:22:52.750103 XRTRTR_NEW_MODE: ON
9164 23:22:52.750174 TX_TRACKING: ON
9165 23:22:52.753161 RDSEL_TRACKING: OFF
9166 23:22:52.753232 DQS Precalculation for DVFS: ON
9167 23:22:52.756421 RX_TRACKING: OFF
9168 23:22:52.756493 HW_GATING DBG: ON
9169 23:22:52.760372 ZQCS_ENABLE_LP4: ON
9170 23:22:52.763144 RX_PICG_NEW_MODE: ON
9171 23:22:52.763274 TX_PICG_NEW_MODE: ON
9172 23:22:52.766769 ENABLE_RX_DCM_DPHY: ON
9173 23:22:52.769855 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9174 23:22:52.769955 DUMMY_READ_FOR_TRACKING: OFF
9175 23:22:52.773421 !!! SPM_CONTROL_AFTERK: OFF
9176 23:22:52.776469 !!! SPM could not control APHY
9177 23:22:52.779656 IMPEDANCE_TRACKING: ON
9178 23:22:52.779728 TEMP_SENSOR: ON
9179 23:22:52.783468 HW_SAVE_FOR_SR: OFF
9180 23:22:52.786376 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9181 23:22:52.789663 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9182 23:22:52.789799 Read ODT Tracking: ON
9183 23:22:52.793432 Refresh Rate DeBounce: ON
9184 23:22:52.795986 DFS_NO_QUEUE_FLUSH: ON
9185 23:22:52.799746 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9186 23:22:52.799866 ENABLE_DFS_RUNTIME_MRW: OFF
9187 23:22:52.802716 DDR_RESERVE_NEW_MODE: ON
9188 23:22:52.806135 MR_CBT_SWITCH_FREQ: ON
9189 23:22:52.806259 =========================
9190 23:22:52.826216 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9191 23:22:52.829752 dram_init: ddr_geometry: 2
9192 23:22:52.847650 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9193 23:22:52.851604 dram_init: dram init end (result: 0)
9194 23:22:52.857476 DRAM-K: Full calibration passed in 24441 msecs
9195 23:22:52.861021 MRC: failed to locate region type 0.
9196 23:22:52.861148 DRAM rank0 size:0x100000000,
9197 23:22:52.864313 DRAM rank1 size=0x100000000
9198 23:22:52.874384 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9199 23:22:52.880658 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9200 23:22:52.890729 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9201 23:22:52.897046 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9202 23:22:52.897175 DRAM rank0 size:0x100000000,
9203 23:22:52.900276 DRAM rank1 size=0x100000000
9204 23:22:52.900401 CBMEM:
9205 23:22:52.903490 IMD: root @ 0xfffff000 254 entries.
9206 23:22:52.906757 IMD: root @ 0xffffec00 62 entries.
9207 23:22:52.910372 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9208 23:22:52.916972 WARNING: RO_VPD is uninitialized or empty.
9209 23:22:52.919900 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9210 23:22:52.927637 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9211 23:22:52.940660 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9212 23:22:52.951776 BS: romstage times (exec / console): total (unknown) / 23967 ms
9213 23:22:52.951869
9214 23:22:52.951935
9215 23:22:52.961959 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9216 23:22:52.965366 ARM64: Exception handlers installed.
9217 23:22:52.968208 ARM64: Testing exception
9218 23:22:52.971447 ARM64: Done test exception
9219 23:22:52.971575 Enumerating buses...
9220 23:22:52.975400 Show all devs... Before device enumeration.
9221 23:22:52.978472 Root Device: enabled 1
9222 23:22:52.981694 CPU_CLUSTER: 0: enabled 1
9223 23:22:52.981821 CPU: 00: enabled 1
9224 23:22:52.984920 Compare with tree...
9225 23:22:52.985045 Root Device: enabled 1
9226 23:22:52.988056 CPU_CLUSTER: 0: enabled 1
9227 23:22:52.991299 CPU: 00: enabled 1
9228 23:22:52.991432 Root Device scanning...
9229 23:22:52.994429 scan_static_bus for Root Device
9230 23:22:52.998155 CPU_CLUSTER: 0 enabled
9231 23:22:53.001561 scan_static_bus for Root Device done
9232 23:22:53.004814 scan_bus: bus Root Device finished in 8 msecs
9233 23:22:53.004916 done
9234 23:22:53.011038 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9235 23:22:53.014777 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9236 23:22:53.020936 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9237 23:22:53.027978 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9238 23:22:53.028107 Allocating resources...
9239 23:22:53.031091 Reading resources...
9240 23:22:53.034415 Root Device read_resources bus 0 link: 0
9241 23:22:53.037329 DRAM rank0 size:0x100000000,
9242 23:22:53.037455 DRAM rank1 size=0x100000000
9243 23:22:53.044042 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9244 23:22:53.044174 CPU: 00 missing read_resources
9245 23:22:53.050815 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9246 23:22:53.053687 Root Device read_resources bus 0 link: 0 done
9247 23:22:53.057668 Done reading resources.
9248 23:22:53.060640 Show resources in subtree (Root Device)...After reading.
9249 23:22:53.063695 Root Device child on link 0 CPU_CLUSTER: 0
9250 23:22:53.067228 CPU_CLUSTER: 0 child on link 0 CPU: 00
9251 23:22:53.077392 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9252 23:22:53.077501 CPU: 00
9253 23:22:53.083721 Root Device assign_resources, bus 0 link: 0
9254 23:22:53.087199 CPU_CLUSTER: 0 missing set_resources
9255 23:22:53.090065 Root Device assign_resources, bus 0 link: 0 done
9256 23:22:53.093472 Done setting resources.
9257 23:22:53.097032 Show resources in subtree (Root Device)...After assigning values.
9258 23:22:53.100326 Root Device child on link 0 CPU_CLUSTER: 0
9259 23:22:53.106787 CPU_CLUSTER: 0 child on link 0 CPU: 00
9260 23:22:53.113507 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9261 23:22:53.116549 CPU: 00
9262 23:22:53.116632 Done allocating resources.
9263 23:22:53.122861 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9264 23:22:53.122945 Enabling resources...
9265 23:22:53.126249 done.
9266 23:22:53.129299 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9267 23:22:53.132790 Initializing devices...
9268 23:22:53.132873 Root Device init
9269 23:22:53.136118 init hardware done!
9270 23:22:53.136227 0x00000018: ctrlr->caps
9271 23:22:53.139351 52.000 MHz: ctrlr->f_max
9272 23:22:53.143225 0.400 MHz: ctrlr->f_min
9273 23:22:53.146491 0x40ff8080: ctrlr->voltages
9274 23:22:53.146576 sclk: 390625
9275 23:22:53.146641 Bus Width = 1
9276 23:22:53.149695 sclk: 390625
9277 23:22:53.149777 Bus Width = 1
9278 23:22:53.152626 Early init status = 3
9279 23:22:53.156290 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9280 23:22:53.159800 in-header: 03 fc 00 00 01 00 00 00
9281 23:22:53.162615 in-data: 00
9282 23:22:53.165997 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9283 23:22:53.170474 in-header: 03 fd 00 00 00 00 00 00
9284 23:22:53.173891 in-data:
9285 23:22:53.177666 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9286 23:22:53.180756 in-header: 03 fc 00 00 01 00 00 00
9287 23:22:53.184466 in-data: 00
9288 23:22:53.187440 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9289 23:22:53.192852 in-header: 03 fd 00 00 00 00 00 00
9290 23:22:53.195972 in-data:
9291 23:22:53.199226 [SSUSB] Setting up USB HOST controller...
9292 23:22:53.202567 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9293 23:22:53.205458 [SSUSB] phy power-on done.
9294 23:22:53.209131 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9295 23:22:53.216050 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9296 23:22:53.219264 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9297 23:22:53.225460 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9298 23:22:53.232098 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9299 23:22:53.239044 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9300 23:22:53.245102 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9301 23:22:53.251779 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9302 23:22:53.255228 SPM: binary array size = 0x9dc
9303 23:22:53.258317 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9304 23:22:53.265011 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9305 23:22:53.272039 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9306 23:22:53.278556 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9307 23:22:53.281587 configure_display: Starting display init
9308 23:22:53.316163 anx7625_power_on_init: Init interface.
9309 23:22:53.318886 anx7625_disable_pd_protocol: Disabled PD feature.
9310 23:22:53.322370 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9311 23:22:53.350175 anx7625_start_dp_work: Secure OCM version=00
9312 23:22:53.353595 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9313 23:22:53.368038 sp_tx_get_edid_block: EDID Block = 1
9314 23:22:53.470609 Extracted contents:
9315 23:22:53.474244 header: 00 ff ff ff ff ff ff 00
9316 23:22:53.477394 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9317 23:22:53.480676 version: 01 04
9318 23:22:53.483856 basic params: 95 1f 11 78 0a
9319 23:22:53.487234 chroma info: 76 90 94 55 54 90 27 21 50 54
9320 23:22:53.490514 established: 00 00 00
9321 23:22:53.497320 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9322 23:22:53.503966 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9323 23:22:53.506894 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9324 23:22:53.513636 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9325 23:22:53.520148 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9326 23:22:53.523487 extensions: 00
9327 23:22:53.523613 checksum: fb
9328 23:22:53.523734
9329 23:22:53.530332 Manufacturer: IVO Model 57d Serial Number 0
9330 23:22:53.530449 Made week 0 of 2020
9331 23:22:53.533433 EDID version: 1.4
9332 23:22:53.533536 Digital display
9333 23:22:53.537030 6 bits per primary color channel
9334 23:22:53.537147 DisplayPort interface
9335 23:22:53.540097 Maximum image size: 31 cm x 17 cm
9336 23:22:53.543087 Gamma: 220%
9337 23:22:53.543202 Check DPMS levels
9338 23:22:53.549819 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9339 23:22:53.552846 First detailed timing is preferred timing
9340 23:22:53.552951 Established timings supported:
9341 23:22:53.556104 Standard timings supported:
9342 23:22:53.559857 Detailed timings
9343 23:22:53.563062 Hex of detail: 383680a07038204018303c0035ae10000019
9344 23:22:53.569375 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9345 23:22:53.573112 0780 0798 07c8 0820 hborder 0
9346 23:22:53.576607 0438 043b 0447 0458 vborder 0
9347 23:22:53.579943 -hsync -vsync
9348 23:22:53.580019 Did detailed timing
9349 23:22:53.586182 Hex of detail: 000000000000000000000000000000000000
9350 23:22:53.589550 Manufacturer-specified data, tag 0
9351 23:22:53.593012 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9352 23:22:53.595599 ASCII string: InfoVision
9353 23:22:53.599063 Hex of detail: 000000fe00523134304e574635205248200a
9354 23:22:53.602256 ASCII string: R140NWF5 RH
9355 23:22:53.602364 Checksum
9356 23:22:53.605843 Checksum: 0xfb (valid)
9357 23:22:53.608840 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9358 23:22:53.612455 DSI data_rate: 832800000 bps
9359 23:22:53.619113 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9360 23:22:53.622102 anx7625_parse_edid: pixelclock(138800).
9361 23:22:53.625335 hactive(1920), hsync(48), hfp(24), hbp(88)
9362 23:22:53.628586 vactive(1080), vsync(12), vfp(3), vbp(17)
9363 23:22:53.631850 anx7625_dsi_config: config dsi.
9364 23:22:53.638425 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9365 23:22:53.652929 anx7625_dsi_config: success to config DSI
9366 23:22:53.656380 anx7625_dp_start: MIPI phy setup OK.
9367 23:22:53.659577 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9368 23:22:53.662517 mtk_ddp_mode_set invalid vrefresh 60
9369 23:22:53.666018 main_disp_path_setup
9370 23:22:53.666092 ovl_layer_smi_id_en
9371 23:22:53.669105 ovl_layer_smi_id_en
9372 23:22:53.669218 ccorr_config
9373 23:22:53.669309 aal_config
9374 23:22:53.672668 gamma_config
9375 23:22:53.672769 postmask_config
9376 23:22:53.675677 dither_config
9377 23:22:53.679557 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9378 23:22:53.685595 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9379 23:22:53.689137 Root Device init finished in 551 msecs
9380 23:22:53.692489 CPU_CLUSTER: 0 init
9381 23:22:53.699105 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9382 23:22:53.705914 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9383 23:22:53.706025 APU_MBOX 0x190000b0 = 0x10001
9384 23:22:53.708599 APU_MBOX 0x190001b0 = 0x10001
9385 23:22:53.712061 APU_MBOX 0x190005b0 = 0x10001
9386 23:22:53.715497 APU_MBOX 0x190006b0 = 0x10001
9387 23:22:53.722407 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9388 23:22:53.731827 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9389 23:22:53.744553 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9390 23:22:53.750972 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9391 23:22:53.762241 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9392 23:22:53.771822 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9393 23:22:53.774706 CPU_CLUSTER: 0 init finished in 81 msecs
9394 23:22:53.778423 Devices initialized
9395 23:22:53.781574 Show all devs... After init.
9396 23:22:53.781679 Root Device: enabled 1
9397 23:22:53.784772 CPU_CLUSTER: 0: enabled 1
9398 23:22:53.788076 CPU: 00: enabled 1
9399 23:22:53.791151 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9400 23:22:53.794406 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9401 23:22:53.797828 ELOG: NV offset 0x57f000 size 0x1000
9402 23:22:53.804565 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9403 23:22:53.811103 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9404 23:22:53.814404 ELOG: Event(17) added with size 13 at 2024-04-03 23:22:53 UTC
9405 23:22:53.820979 out: cmd=0x121: 03 db 21 01 00 00 00 00
9406 23:22:53.824186 in-header: 03 1f 00 00 2c 00 00 00
9407 23:22:53.837245 in-data: 40 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9408 23:22:53.840764 ELOG: Event(A1) added with size 10 at 2024-04-03 23:22:53 UTC
9409 23:22:53.847311 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9410 23:22:53.853793 ELOG: Event(A0) added with size 9 at 2024-04-03 23:22:53 UTC
9411 23:22:53.856959 elog_add_boot_reason: Logged dev mode boot
9412 23:22:53.863793 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9413 23:22:53.863879 Finalize devices...
9414 23:22:53.867001 Devices finalized
9415 23:22:53.870428 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9416 23:22:53.873593 Writing coreboot table at 0xffe64000
9417 23:22:53.880260 0. 000000000010a000-0000000000113fff: RAMSTAGE
9418 23:22:53.883664 1. 0000000040000000-00000000400fffff: RAM
9419 23:22:53.886791 2. 0000000040100000-000000004032afff: RAMSTAGE
9420 23:22:53.889833 3. 000000004032b000-00000000545fffff: RAM
9421 23:22:53.893599 4. 0000000054600000-000000005465ffff: BL31
9422 23:22:53.896329 5. 0000000054660000-00000000ffe63fff: RAM
9423 23:22:53.903196 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9424 23:22:53.906741 7. 0000000100000000-000000023fffffff: RAM
9425 23:22:53.909897 Passing 5 GPIOs to payload:
9426 23:22:53.913245 NAME | PORT | POLARITY | VALUE
9427 23:22:53.919771 EC in RW | 0x000000aa | low | undefined
9428 23:22:53.923096 EC interrupt | 0x00000005 | low | undefined
9429 23:22:53.929690 TPM interrupt | 0x000000ab | high | undefined
9430 23:22:53.932811 SD card detect | 0x00000011 | high | undefined
9431 23:22:53.936161 speaker enable | 0x00000093 | high | undefined
9432 23:22:53.939452 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9433 23:22:53.943490 in-header: 03 f9 00 00 02 00 00 00
9434 23:22:53.946250 in-data: 02 00
9435 23:22:53.950081 ADC[4]: Raw value=903325 ID=7
9436 23:22:53.953008 ADC[3]: Raw value=213546 ID=1
9437 23:22:53.953111 RAM Code: 0x71
9438 23:22:53.956234 ADC[6]: Raw value=74630 ID=0
9439 23:22:53.959700 ADC[5]: Raw value=213916 ID=1
9440 23:22:53.959777 SKU Code: 0x1
9441 23:22:53.966075 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum e963
9442 23:22:53.966208 coreboot table: 964 bytes.
9443 23:22:53.969349 IMD ROOT 0. 0xfffff000 0x00001000
9444 23:22:53.972613 IMD SMALL 1. 0xffffe000 0x00001000
9445 23:22:53.976047 RO MCACHE 2. 0xffffc000 0x00001104
9446 23:22:53.979476 CONSOLE 3. 0xfff7c000 0x00080000
9447 23:22:53.982635 FMAP 4. 0xfff7b000 0x00000452
9448 23:22:53.986061 TIME STAMP 5. 0xfff7a000 0x00000910
9449 23:22:53.989057 VBOOT WORK 6. 0xfff66000 0x00014000
9450 23:22:53.992184 RAMOOPS 7. 0xffe66000 0x00100000
9451 23:22:53.995553 COREBOOT 8. 0xffe64000 0x00002000
9452 23:22:53.998786 IMD small region:
9453 23:22:54.001881 IMD ROOT 0. 0xffffec00 0x00000400
9454 23:22:54.005567 VPD 1. 0xffffeb80 0x0000006c
9455 23:22:54.009118 MMC STATUS 2. 0xffffeb60 0x00000004
9456 23:22:54.015651 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9457 23:22:54.015770 Probing TPM: done!
9458 23:22:54.022376 Connected to device vid:did:rid of 1ae0:0028:00
9459 23:22:54.028850 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9460 23:22:54.032221 Initialized TPM device CR50 revision 0
9461 23:22:54.035543 Checking cr50 for pending updates
9462 23:22:54.041560 Reading cr50 TPM mode
9463 23:22:54.049951 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9464 23:22:54.056435 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9465 23:22:54.096615 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9466 23:22:54.099599 Checking segment from ROM address 0x40100000
9467 23:22:54.106241 Checking segment from ROM address 0x4010001c
9468 23:22:54.109637 Loading segment from ROM address 0x40100000
9469 23:22:54.109764 code (compression=0)
9470 23:22:54.119734 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9471 23:22:54.126284 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9472 23:22:54.126409 it's not compressed!
9473 23:22:54.133221 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9474 23:22:54.139411 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9475 23:22:54.157056 Loading segment from ROM address 0x4010001c
9476 23:22:54.157144 Entry Point 0x80000000
9477 23:22:54.160711 Loaded segments
9478 23:22:54.163695 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9479 23:22:54.170167 Jumping to boot code at 0x80000000(0xffe64000)
9480 23:22:54.176797 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9481 23:22:54.183585 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9482 23:22:54.191262 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9483 23:22:54.194866 Checking segment from ROM address 0x40100000
9484 23:22:54.198243 Checking segment from ROM address 0x4010001c
9485 23:22:54.204861 Loading segment from ROM address 0x40100000
9486 23:22:54.204940 code (compression=1)
9487 23:22:54.211086 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9488 23:22:54.220855 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9489 23:22:54.220964 using LZMA
9490 23:22:54.230016 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9491 23:22:54.236953 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9492 23:22:54.239680 Loading segment from ROM address 0x4010001c
9493 23:22:54.239767 Entry Point 0x54601000
9494 23:22:54.242823 Loaded segments
9495 23:22:54.246295 NOTICE: MT8192 bl31_setup
9496 23:22:54.253076 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9497 23:22:54.256988 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9498 23:22:54.259871 WARNING: region 0:
9499 23:22:54.263411 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 23:22:54.263498 WARNING: region 1:
9501 23:22:54.270153 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9502 23:22:54.273640 WARNING: region 2:
9503 23:22:54.276759 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9504 23:22:54.279672 WARNING: region 3:
9505 23:22:54.283421 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9506 23:22:54.286411 WARNING: region 4:
9507 23:22:54.293036 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9508 23:22:54.293123 WARNING: region 5:
9509 23:22:54.296530 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 23:22:54.299749 WARNING: region 6:
9511 23:22:54.302924 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 23:22:54.306751 WARNING: region 7:
9513 23:22:54.309914 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 23:22:54.316838 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9515 23:22:54.319650 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9516 23:22:54.322820 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9517 23:22:54.329469 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9518 23:22:54.332694 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9519 23:22:54.339791 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9520 23:22:54.342896 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9521 23:22:54.346413 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9522 23:22:54.352915 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9523 23:22:54.356563 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9524 23:22:54.359576 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9525 23:22:54.366135 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9526 23:22:54.369736 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9527 23:22:54.373242 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9528 23:22:54.379328 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9529 23:22:54.382882 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9530 23:22:54.389657 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9531 23:22:54.392543 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9532 23:22:54.395942 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9533 23:22:54.402704 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9534 23:22:54.406046 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9535 23:22:54.412399 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9536 23:22:54.416132 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9537 23:22:54.418894 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9538 23:22:54.425601 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9539 23:22:54.429488 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9540 23:22:54.436066 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9541 23:22:54.439465 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9542 23:22:54.442755 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9543 23:22:54.448889 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9544 23:22:54.452386 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9545 23:22:54.459003 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9546 23:22:54.462304 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9547 23:22:54.465703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9548 23:22:54.468862 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9549 23:22:54.475743 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9550 23:22:54.478899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9551 23:22:54.482463 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9552 23:22:54.485562 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9553 23:22:54.492078 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9554 23:22:54.495717 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9555 23:22:54.498774 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9556 23:22:54.502151 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9557 23:22:54.508801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9558 23:22:54.511980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9559 23:22:54.515815 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9560 23:22:54.518671 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9561 23:22:54.525509 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9562 23:22:54.528630 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9563 23:22:54.535189 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9564 23:22:54.538495 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9565 23:22:54.541869 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9566 23:22:54.548349 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9567 23:22:54.551732 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9568 23:22:54.558571 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9569 23:22:54.561672 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9570 23:22:54.568675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9571 23:22:54.571502 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9572 23:22:54.574950 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9573 23:22:54.582245 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9574 23:22:54.584714 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9575 23:22:54.591350 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9576 23:22:54.594828 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9577 23:22:54.601296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9578 23:22:54.604600 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9579 23:22:54.611204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9580 23:22:54.614558 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9581 23:22:54.621446 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9582 23:22:54.624685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9583 23:22:54.627993 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9584 23:22:54.634522 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9585 23:22:54.637766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9586 23:22:54.644507 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9587 23:22:54.647646 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9588 23:22:54.655038 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9589 23:22:54.657777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9590 23:22:54.661019 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9591 23:22:54.667639 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9592 23:22:54.671106 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9593 23:22:54.677789 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9594 23:22:54.680980 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9595 23:22:54.687555 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9596 23:22:54.691475 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9597 23:22:54.697601 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9598 23:22:54.700886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9599 23:22:54.704333 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9600 23:22:54.710773 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9601 23:22:54.714620 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9602 23:22:54.720772 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9603 23:22:54.724418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9604 23:22:54.730962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9605 23:22:54.734195 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9606 23:22:54.737394 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9607 23:22:54.744116 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9608 23:22:54.747193 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9609 23:22:54.753791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9610 23:22:54.757237 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9611 23:22:54.760880 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9612 23:22:54.767198 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9613 23:22:54.770975 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9614 23:22:54.774344 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9615 23:22:54.780536 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9616 23:22:54.783747 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9617 23:22:54.787386 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9618 23:22:54.794149 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9619 23:22:54.796864 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9620 23:22:54.803488 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9621 23:22:54.807005 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9622 23:22:54.810511 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9623 23:22:54.817075 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9624 23:22:54.820285 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9625 23:22:54.826885 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9626 23:22:54.829972 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9627 23:22:54.833555 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9628 23:22:54.840127 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9629 23:22:54.843296 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9630 23:22:54.846748 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9631 23:22:54.853824 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9632 23:22:54.856384 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9633 23:22:54.860259 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9634 23:22:54.866600 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9635 23:22:54.869738 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9636 23:22:54.873120 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9637 23:22:54.876400 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9638 23:22:54.882774 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9639 23:22:54.886154 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9640 23:22:54.893150 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9641 23:22:54.896291 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9642 23:22:54.899539 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9643 23:22:54.906269 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9644 23:22:54.909135 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9645 23:22:54.915869 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9646 23:22:54.919675 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9647 23:22:54.922764 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9648 23:22:54.929069 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9649 23:22:54.932925 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9650 23:22:54.938933 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9651 23:22:54.942838 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9652 23:22:54.945612 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9653 23:22:54.952220 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9654 23:22:54.955666 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9655 23:22:54.961976 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9656 23:22:54.965804 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9657 23:22:54.969249 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9658 23:22:54.975264 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9659 23:22:54.978759 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9660 23:22:54.985789 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9661 23:22:54.988605 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9662 23:22:54.992159 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9663 23:22:54.998640 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9664 23:22:55.001977 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9665 23:22:55.005229 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9666 23:22:55.012369 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9667 23:22:55.015243 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9668 23:22:55.021870 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9669 23:22:55.025359 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9670 23:22:55.028449 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9671 23:22:55.035256 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9672 23:22:55.038395 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9673 23:22:55.045047 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9674 23:22:55.048672 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9675 23:22:55.051865 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9676 23:22:55.058785 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9677 23:22:55.061480 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9678 23:22:55.068293 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9679 23:22:55.071326 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9680 23:22:55.074977 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9681 23:22:55.081440 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9682 23:22:55.084882 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9683 23:22:55.091131 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9684 23:22:55.094523 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9685 23:22:55.097793 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9686 23:22:55.104517 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9687 23:22:55.107841 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9688 23:22:55.114461 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9689 23:22:55.117870 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9690 23:22:55.121310 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9691 23:22:55.127808 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9692 23:22:55.131273 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9693 23:22:55.137382 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9694 23:22:55.140597 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9695 23:22:55.143743 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9696 23:22:55.150513 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9697 23:22:55.153721 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9698 23:22:55.160344 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9699 23:22:55.163688 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9700 23:22:55.167213 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9701 23:22:55.174018 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9702 23:22:55.177166 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9703 23:22:55.183832 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9704 23:22:55.186779 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9705 23:22:55.193408 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9706 23:22:55.196927 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9707 23:22:55.200261 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9708 23:22:55.206879 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9709 23:22:55.210347 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9710 23:22:55.216462 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9711 23:22:55.219961 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9712 23:22:55.226091 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9713 23:22:55.229776 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9714 23:22:55.232959 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9715 23:22:55.239345 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9716 23:22:55.243055 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9717 23:22:55.249595 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9718 23:22:55.253011 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9719 23:22:55.259423 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9720 23:22:55.262758 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9721 23:22:55.265853 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9722 23:22:55.272462 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9723 23:22:55.275577 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9724 23:22:55.282361 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9725 23:22:55.285583 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9726 23:22:55.292305 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9727 23:22:55.295619 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9728 23:22:55.298535 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9729 23:22:55.305510 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9730 23:22:55.308919 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9731 23:22:55.314908 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9732 23:22:55.318422 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9733 23:22:55.324904 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9734 23:22:55.328261 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9735 23:22:55.331491 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9736 23:22:55.338477 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9737 23:22:55.341402 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9738 23:22:55.348077 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9739 23:22:55.351798 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9740 23:22:55.358331 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9741 23:22:55.361235 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9742 23:22:55.364889 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9743 23:22:55.371315 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9744 23:22:55.374321 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9745 23:22:55.377709 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9746 23:22:55.381171 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9747 23:22:55.388011 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9748 23:22:55.391251 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9749 23:22:55.394167 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9750 23:22:55.401046 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9751 23:22:55.404457 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9752 23:22:55.407692 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9753 23:22:55.414465 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9754 23:22:55.417602 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9755 23:22:55.423813 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9756 23:22:55.427289 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9757 23:22:55.430411 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9758 23:22:55.437110 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9759 23:22:55.440509 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9760 23:22:55.443592 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9761 23:22:55.450275 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9762 23:22:55.453547 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9763 23:22:55.460296 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9764 23:22:55.463443 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9765 23:22:55.466813 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9766 23:22:55.473414 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9767 23:22:55.476681 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9768 23:22:55.480044 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9769 23:22:55.486703 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9770 23:22:55.490096 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9771 23:22:55.496832 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9772 23:22:55.499714 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9773 23:22:55.502885 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9774 23:22:55.509682 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9775 23:22:55.513049 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9776 23:22:55.519342 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9777 23:22:55.522815 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9778 23:22:55.525814 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9779 23:22:55.532677 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9780 23:22:55.535938 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9781 23:22:55.539170 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9782 23:22:55.545644 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9783 23:22:55.549076 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9784 23:22:55.552175 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9785 23:22:55.555430 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9786 23:22:55.562189 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9787 23:22:55.565583 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9788 23:22:55.568812 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9789 23:22:55.572067 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9790 23:22:55.578441 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9791 23:22:55.582283 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9792 23:22:55.585424 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9793 23:22:55.589098 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9794 23:22:55.595418 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9795 23:22:55.598520 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9796 23:22:55.601666 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9797 23:22:55.608057 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9798 23:22:55.611344 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9799 23:22:55.618286 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9800 23:22:55.621469 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9801 23:22:55.627811 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9802 23:22:55.630993 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9803 23:22:55.634366 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9804 23:22:55.640916 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9805 23:22:55.644730 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9806 23:22:55.651223 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9807 23:22:55.654596 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9808 23:22:55.660740 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9809 23:22:55.663954 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9810 23:22:55.670631 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9811 23:22:55.674208 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9812 23:22:55.677163 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9813 23:22:55.683799 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9814 23:22:55.687211 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9815 23:22:55.693576 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9816 23:22:55.696803 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9817 23:22:55.700517 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9818 23:22:55.706728 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9819 23:22:55.709771 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9820 23:22:55.716535 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9821 23:22:55.719969 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9822 23:22:55.726617 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9823 23:22:55.730071 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9824 23:22:55.733280 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9825 23:22:55.739480 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9826 23:22:55.743189 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9827 23:22:55.749320 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9828 23:22:55.752987 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9829 23:22:55.756083 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9830 23:22:55.762791 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9831 23:22:55.766076 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9832 23:22:55.772558 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9833 23:22:55.775876 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9834 23:22:55.782329 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9835 23:22:55.785544 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9836 23:22:55.789062 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9837 23:22:55.795458 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9838 23:22:55.798793 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9839 23:22:55.805051 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9840 23:22:55.808313 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9841 23:22:55.815091 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9842 23:22:55.818458 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9843 23:22:55.821795 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9844 23:22:55.827984 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9845 23:22:55.831573 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9846 23:22:55.838292 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9847 23:22:55.841316 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9848 23:22:55.848012 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9849 23:22:55.851146 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9850 23:22:55.857897 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9851 23:22:55.860925 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9852 23:22:55.864364 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9853 23:22:55.870782 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9854 23:22:55.874183 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9855 23:22:55.880407 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9856 23:22:55.884017 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9857 23:22:55.887148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9858 23:22:55.894084 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9859 23:22:55.897249 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9860 23:22:55.903811 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9861 23:22:55.907049 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9862 23:22:55.913757 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9863 23:22:55.917144 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9864 23:22:55.920500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9865 23:22:55.926505 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9866 23:22:55.930143 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9867 23:22:55.936598 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9868 23:22:55.939873 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9869 23:22:55.946459 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9870 23:22:55.949948 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9871 23:22:55.953000 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9872 23:22:55.959888 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9873 23:22:55.962663 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9874 23:22:55.969790 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9875 23:22:55.972697 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9876 23:22:55.979177 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9877 23:22:55.982717 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9878 23:22:55.989356 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9879 23:22:55.992401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9880 23:22:55.996079 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9881 23:22:56.002318 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9882 23:22:56.005563 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9883 23:22:56.011870 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9884 23:22:56.015135 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9885 23:22:56.021973 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9886 23:22:56.025218 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9887 23:22:56.031810 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9888 23:22:56.034949 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9889 23:22:56.041571 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9890 23:22:56.044901 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9891 23:22:56.048236 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9892 23:22:56.054742 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9893 23:22:56.057902 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9894 23:22:56.065089 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9895 23:22:56.068183 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9896 23:22:56.074626 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9897 23:22:56.078038 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9898 23:22:56.084381 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9899 23:22:56.087742 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9900 23:22:56.091223 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9901 23:22:56.097576 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9902 23:22:56.101063 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9903 23:22:56.107337 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9904 23:22:56.110593 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9905 23:22:56.117655 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9906 23:22:56.121021 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9907 23:22:56.124513 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9908 23:22:56.130387 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9909 23:22:56.133925 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9910 23:22:56.140632 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9911 23:22:56.143799 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9912 23:22:56.150573 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9913 23:22:56.153392 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9914 23:22:56.160447 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9915 23:22:56.163310 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9916 23:22:56.166796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9917 23:22:56.173292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9918 23:22:56.176993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9919 23:22:56.183602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9920 23:22:56.186483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9921 23:22:56.193103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9922 23:22:56.196383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9923 23:22:56.202967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9924 23:22:56.206282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9925 23:22:56.213123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9926 23:22:56.216426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9927 23:22:56.222658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9928 23:22:56.226003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9929 23:22:56.232707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9930 23:22:56.236021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9931 23:22:56.242219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9932 23:22:56.246001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9933 23:22:56.252089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9934 23:22:56.256071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9935 23:22:56.262265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9936 23:22:56.265549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9937 23:22:56.272483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9938 23:22:56.275638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9939 23:22:56.282150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9940 23:22:56.285203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9941 23:22:56.291930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9942 23:22:56.295166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9943 23:22:56.301852 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9944 23:22:56.304902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9945 23:22:56.311945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9946 23:22:56.314769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9947 23:22:56.321619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9948 23:22:56.324693 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9949 23:22:56.328249 INFO: [APUAPC] vio 0
9950 23:22:56.331368 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9951 23:22:56.338180 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9952 23:22:56.341482 INFO: [APUAPC] D0_APC_0: 0x400510
9953 23:22:56.341613 INFO: [APUAPC] D0_APC_1: 0x0
9954 23:22:56.344778 INFO: [APUAPC] D0_APC_2: 0x1540
9955 23:22:56.348125 INFO: [APUAPC] D0_APC_3: 0x0
9956 23:22:56.351064 INFO: [APUAPC] D1_APC_0: 0xffffffff
9957 23:22:56.354605 INFO: [APUAPC] D1_APC_1: 0xffffffff
9958 23:22:56.357833 INFO: [APUAPC] D1_APC_2: 0x3fffff
9959 23:22:56.360973 INFO: [APUAPC] D1_APC_3: 0x0
9960 23:22:56.364789 INFO: [APUAPC] D2_APC_0: 0xffffffff
9961 23:22:56.367995 INFO: [APUAPC] D2_APC_1: 0xffffffff
9962 23:22:56.371401 INFO: [APUAPC] D2_APC_2: 0x3fffff
9963 23:22:56.374146 INFO: [APUAPC] D2_APC_3: 0x0
9964 23:22:56.378099 INFO: [APUAPC] D3_APC_0: 0xffffffff
9965 23:22:56.380895 INFO: [APUAPC] D3_APC_1: 0xffffffff
9966 23:22:56.384167 INFO: [APUAPC] D3_APC_2: 0x3fffff
9967 23:22:56.387400 INFO: [APUAPC] D3_APC_3: 0x0
9968 23:22:56.390965 INFO: [APUAPC] D4_APC_0: 0xffffffff
9969 23:22:56.394243 INFO: [APUAPC] D4_APC_1: 0xffffffff
9970 23:22:56.397649 INFO: [APUAPC] D4_APC_2: 0x3fffff
9971 23:22:56.400688 INFO: [APUAPC] D4_APC_3: 0x0
9972 23:22:56.404338 INFO: [APUAPC] D5_APC_0: 0xffffffff
9973 23:22:56.407214 INFO: [APUAPC] D5_APC_1: 0xffffffff
9974 23:22:56.410775 INFO: [APUAPC] D5_APC_2: 0x3fffff
9975 23:22:56.413710 INFO: [APUAPC] D5_APC_3: 0x0
9976 23:22:56.417112 INFO: [APUAPC] D6_APC_0: 0xffffffff
9977 23:22:56.420208 INFO: [APUAPC] D6_APC_1: 0xffffffff
9978 23:22:56.423722 INFO: [APUAPC] D6_APC_2: 0x3fffff
9979 23:22:56.427054 INFO: [APUAPC] D6_APC_3: 0x0
9980 23:22:56.430364 INFO: [APUAPC] D7_APC_0: 0xffffffff
9981 23:22:56.434013 INFO: [APUAPC] D7_APC_1: 0xffffffff
9982 23:22:56.436943 INFO: [APUAPC] D7_APC_2: 0x3fffff
9983 23:22:56.440220 INFO: [APUAPC] D7_APC_3: 0x0
9984 23:22:56.443436 INFO: [APUAPC] D8_APC_0: 0xffffffff
9985 23:22:56.446414 INFO: [APUAPC] D8_APC_1: 0xffffffff
9986 23:22:56.450413 INFO: [APUAPC] D8_APC_2: 0x3fffff
9987 23:22:56.453651 INFO: [APUAPC] D8_APC_3: 0x0
9988 23:22:56.456859 INFO: [APUAPC] D9_APC_0: 0xffffffff
9989 23:22:56.460203 INFO: [APUAPC] D9_APC_1: 0xffffffff
9990 23:22:56.463539 INFO: [APUAPC] D9_APC_2: 0x3fffff
9991 23:22:56.466312 INFO: [APUAPC] D9_APC_3: 0x0
9992 23:22:56.470087 INFO: [APUAPC] D10_APC_0: 0xffffffff
9993 23:22:56.472930 INFO: [APUAPC] D10_APC_1: 0xffffffff
9994 23:22:56.476267 INFO: [APUAPC] D10_APC_2: 0x3fffff
9995 23:22:56.479478 INFO: [APUAPC] D10_APC_3: 0x0
9996 23:22:56.482877 INFO: [APUAPC] D11_APC_0: 0xffffffff
9997 23:22:56.485928 INFO: [APUAPC] D11_APC_1: 0xffffffff
9998 23:22:56.489356 INFO: [APUAPC] D11_APC_2: 0x3fffff
9999 23:22:56.492960 INFO: [APUAPC] D11_APC_3: 0x0
10000 23:22:56.496036 INFO: [APUAPC] D12_APC_0: 0xffffffff
10001 23:22:56.499330 INFO: [APUAPC] D12_APC_1: 0xffffffff
10002 23:22:56.502667 INFO: [APUAPC] D12_APC_2: 0x3fffff
10003 23:22:56.505831 INFO: [APUAPC] D12_APC_3: 0x0
10004 23:22:56.509284 INFO: [APUAPC] D13_APC_0: 0xffffffff
10005 23:22:56.512433 INFO: [APUAPC] D13_APC_1: 0xffffffff
10006 23:22:56.515631 INFO: [APUAPC] D13_APC_2: 0x3fffff
10007 23:22:56.519718 INFO: [APUAPC] D13_APC_3: 0x0
10008 23:22:56.522019 INFO: [APUAPC] D14_APC_0: 0xffffffff
10009 23:22:56.525389 INFO: [APUAPC] D14_APC_1: 0xffffffff
10010 23:22:56.528911 INFO: [APUAPC] D14_APC_2: 0x3fffff
10011 23:22:56.532433 INFO: [APUAPC] D14_APC_3: 0x0
10012 23:22:56.535205 INFO: [APUAPC] D15_APC_0: 0xffffffff
10013 23:22:56.539059 INFO: [APUAPC] D15_APC_1: 0xffffffff
10014 23:22:56.542044 INFO: [APUAPC] D15_APC_2: 0x3fffff
10015 23:22:56.545560 INFO: [APUAPC] D15_APC_3: 0x0
10016 23:22:56.548861 INFO: [APUAPC] APC_CON: 0x4
10017 23:22:56.552060 INFO: [NOCDAPC] D0_APC_0: 0x0
10018 23:22:56.555469 INFO: [NOCDAPC] D0_APC_1: 0x0
10019 23:22:56.558556 INFO: [NOCDAPC] D1_APC_0: 0x0
10020 23:22:56.562012 INFO: [NOCDAPC] D1_APC_1: 0xfff
10021 23:22:56.565267 INFO: [NOCDAPC] D2_APC_0: 0x0
10022 23:22:56.568605 INFO: [NOCDAPC] D2_APC_1: 0xfff
10023 23:22:56.568690 INFO: [NOCDAPC] D3_APC_0: 0x0
10024 23:22:56.571724 INFO: [NOCDAPC] D3_APC_1: 0xfff
10025 23:22:56.575359 INFO: [NOCDAPC] D4_APC_0: 0x0
10026 23:22:56.578213 INFO: [NOCDAPC] D4_APC_1: 0xfff
10027 23:22:56.581908 INFO: [NOCDAPC] D5_APC_0: 0x0
10028 23:22:56.584872 INFO: [NOCDAPC] D5_APC_1: 0xfff
10029 23:22:56.588207 INFO: [NOCDAPC] D6_APC_0: 0x0
10030 23:22:56.591607 INFO: [NOCDAPC] D6_APC_1: 0xfff
10031 23:22:56.594991 INFO: [NOCDAPC] D7_APC_0: 0x0
10032 23:22:56.597923 INFO: [NOCDAPC] D7_APC_1: 0xfff
10033 23:22:56.601356 INFO: [NOCDAPC] D8_APC_0: 0x0
10034 23:22:56.604564 INFO: [NOCDAPC] D8_APC_1: 0xfff
10035 23:22:56.604682 INFO: [NOCDAPC] D9_APC_0: 0x0
10036 23:22:56.608266 INFO: [NOCDAPC] D9_APC_1: 0xfff
10037 23:22:56.611192 INFO: [NOCDAPC] D10_APC_0: 0x0
10038 23:22:56.614595 INFO: [NOCDAPC] D10_APC_1: 0xfff
10039 23:22:56.617837 INFO: [NOCDAPC] D11_APC_0: 0x0
10040 23:22:56.621028 INFO: [NOCDAPC] D11_APC_1: 0xfff
10041 23:22:56.624408 INFO: [NOCDAPC] D12_APC_0: 0x0
10042 23:22:56.627894 INFO: [NOCDAPC] D12_APC_1: 0xfff
10043 23:22:56.631125 INFO: [NOCDAPC] D13_APC_0: 0x0
10044 23:22:56.634147 INFO: [NOCDAPC] D13_APC_1: 0xfff
10045 23:22:56.637380 INFO: [NOCDAPC] D14_APC_0: 0x0
10046 23:22:56.640954 INFO: [NOCDAPC] D14_APC_1: 0xfff
10047 23:22:56.644391 INFO: [NOCDAPC] D15_APC_0: 0x0
10048 23:22:56.647305 INFO: [NOCDAPC] D15_APC_1: 0xfff
10049 23:22:56.650679 INFO: [NOCDAPC] APC_CON: 0x4
10050 23:22:56.654332 INFO: [APUAPC] set_apusys_apc done
10051 23:22:56.657327 INFO: [DEVAPC] devapc_init done
10052 23:22:56.660833 INFO: GICv3 without legacy support detected.
10053 23:22:56.663927 INFO: ARM GICv3 driver initialized in EL3
10054 23:22:56.666947 INFO: Maximum SPI INTID supported: 639
10055 23:22:56.670384 INFO: BL31: Initializing runtime services
10056 23:22:56.676996 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10057 23:22:56.680547 INFO: SPM: enable CPC mode
10058 23:22:56.683826 INFO: mcdi ready for mcusys-off-idle and system suspend
10059 23:22:56.690501 INFO: BL31: Preparing for EL3 exit to normal world
10060 23:22:56.693969 INFO: Entry point address = 0x80000000
10061 23:22:56.697109 INFO: SPSR = 0x8
10062 23:22:56.701618
10063 23:22:56.701712
10064 23:22:56.701780
10065 23:22:56.704369 Starting depthcharge on Spherion...
10066 23:22:56.704449
10067 23:22:56.704512 Wipe memory regions:
10068 23:22:56.704572
10069 23:22:56.705367 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10070 23:22:56.705538 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10071 23:22:56.705669 Setting prompt string to ['asurada:']
10072 23:22:56.705798 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10073 23:22:56.707912 [0x00000040000000, 0x00000054600000)
10074 23:22:56.830326
10075 23:22:56.830485 [0x00000054660000, 0x00000080000000)
10076 23:22:57.090489
10077 23:22:57.090719 [0x000000821a7280, 0x000000ffe64000)
10078 23:22:57.835335
10079 23:22:57.835522 [0x00000100000000, 0x00000240000000)
10080 23:22:59.724091
10081 23:22:59.727250 Initializing XHCI USB controller at 0x11200000.
10082 23:23:00.765884
10083 23:23:00.769357 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10084 23:23:00.769474
10085 23:23:00.769552
10086 23:23:00.769613
10087 23:23:00.769901 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10089 23:23:00.870231 asurada: tftpboot 192.168.201.1 13248458/tftp-deploy-z0knm9t8/kernel/image.itb 13248458/tftp-deploy-z0knm9t8/kernel/cmdline
10090 23:23:00.870386 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 23:23:00.870487 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10092 23:23:00.875065 tftpboot 192.168.201.1 13248458/tftp-deploy-z0knm9t8/kernel/image.ittp-deploy-z0knm9t8/kernel/cmdline
10093 23:23:00.875174
10094 23:23:00.875268 Waiting for link
10095 23:23:01.035495
10096 23:23:01.035633 R8152: Initializing
10097 23:23:01.035702
10098 23:23:01.038601 Version 6 (ocp_data = 5c30)
10099 23:23:01.038711
10100 23:23:01.041877 R8152: Done initializing
10101 23:23:01.041985
10102 23:23:01.042081 Adding net device
10103 23:23:03.007159
10104 23:23:03.007320 done.
10105 23:23:03.007435
10106 23:23:03.007502 MAC: 00:24:32:30:7c:7b
10107 23:23:03.007564
10108 23:23:03.010366 Sending DHCP discover... done.
10109 23:23:03.010455
10110 23:23:03.013430 Waiting for reply... done.
10111 23:23:03.013509
10112 23:23:03.016989 Sending DHCP request... done.
10113 23:23:03.017074
10114 23:23:03.017142 Waiting for reply... done.
10115 23:23:03.017204
10116 23:23:03.020319 My ip is 192.168.201.14
10117 23:23:03.020402
10118 23:23:03.023571 The DHCP server ip is 192.168.201.1
10119 23:23:03.023655
10120 23:23:03.027019 TFTP server IP predefined by user: 192.168.201.1
10121 23:23:03.027130
10122 23:23:03.033246 Bootfile predefined by user: 13248458/tftp-deploy-z0knm9t8/kernel/image.itb
10123 23:23:03.033332
10124 23:23:03.036909 Sending tftp read request... done.
10125 23:23:03.037009
10126 23:23:03.043443 Waiting for the transfer...
10127 23:23:03.043553
10128 23:23:03.574631 00000000 ################################################################
10129 23:23:03.574823
10130 23:23:04.104680 00080000 ################################################################
10131 23:23:04.104850
10132 23:23:04.632576 00100000 ################################################################
10133 23:23:04.632710
10134 23:23:05.166100 00180000 ################################################################
10135 23:23:05.166260
10136 23:23:05.691756 00200000 ################################################################
10137 23:23:05.691951
10138 23:23:06.227728 00280000 ################################################################
10139 23:23:06.227865
10140 23:23:06.760871 00300000 ################################################################
10141 23:23:06.761031
10142 23:23:07.289392 00380000 ################################################################
10143 23:23:07.289592
10144 23:23:07.824250 00400000 ################################################################
10145 23:23:07.824384
10146 23:23:08.360750 00480000 ################################################################
10147 23:23:08.360909
10148 23:23:08.903195 00500000 ################################################################
10149 23:23:08.903389
10150 23:23:09.447847 00580000 ################################################################
10151 23:23:09.447979
10152 23:23:09.985105 00600000 ################################################################
10153 23:23:09.985298
10154 23:23:10.520893 00680000 ################################################################
10155 23:23:10.521090
10156 23:23:11.057554 00700000 ################################################################
10157 23:23:11.057715
10158 23:23:11.586956 00780000 ################################################################
10159 23:23:11.587116
10160 23:23:12.125612 00800000 ################################################################
10161 23:23:12.125791
10162 23:23:12.682205 00880000 ################################################################
10163 23:23:12.682381
10164 23:23:13.226402 00900000 ################################################################
10165 23:23:13.226610
10166 23:23:13.755065 00980000 ################################################################
10167 23:23:13.755251
10168 23:23:14.293530 00a00000 ################################################################
10169 23:23:14.293715
10170 23:23:14.840472 00a80000 ################################################################
10171 23:23:14.840716
10172 23:23:15.387305 00b00000 ################################################################
10173 23:23:15.387506
10174 23:23:15.929044 00b80000 ################################################################
10175 23:23:15.929182
10176 23:23:16.469802 00c00000 ################################################################
10177 23:23:16.470013
10178 23:23:17.018152 00c80000 ################################################################
10179 23:23:17.018328
10180 23:23:17.550260 00d00000 ################################################################
10181 23:23:17.550405
10182 23:23:18.088677 00d80000 ################################################################
10183 23:23:18.088849
10184 23:23:18.632183 00e00000 ################################################################
10185 23:23:18.632366
10186 23:23:19.182512 00e80000 ################################################################
10187 23:23:19.182665
10188 23:23:19.736600 00f00000 ################################################################
10189 23:23:19.736809
10190 23:23:20.300762 00f80000 ################################################################
10191 23:23:20.300911
10192 23:23:20.877886 01000000 ################################################################
10193 23:23:20.878043
10194 23:23:21.442427 01080000 ################################################################
10195 23:23:21.442590
10196 23:23:22.014026 01100000 ################################################################
10197 23:23:22.014173
10198 23:23:22.591751 01180000 ################################################################
10199 23:23:22.591919
10200 23:23:23.133068 01200000 ################################################################
10201 23:23:23.133283
10202 23:23:23.678177 01280000 ################################################################
10203 23:23:23.678325
10204 23:23:24.245691 01300000 ################################################################
10205 23:23:24.245841
10206 23:23:24.803926 01380000 ################################################################
10207 23:23:24.804146
10208 23:23:25.372280 01400000 ################################################################
10209 23:23:25.372494
10210 23:23:25.924537 01480000 ################################################################
10211 23:23:25.924688
10212 23:23:26.484972 01500000 ################################################################
10213 23:23:26.485125
10214 23:23:27.041276 01580000 ################################################################
10215 23:23:27.041425
10216 23:23:27.597438 01600000 ################################################################
10217 23:23:27.597588
10218 23:23:28.143890 01680000 ################################################################
10219 23:23:28.144044
10220 23:23:28.697848 01700000 ################################################################
10221 23:23:28.698023
10222 23:23:29.257133 01780000 ################################################################
10223 23:23:29.257286
10224 23:23:29.812320 01800000 ################################################################
10225 23:23:29.812471
10226 23:23:30.357952 01880000 ################################################################
10227 23:23:30.358103
10228 23:23:30.902656 01900000 ################################################################
10229 23:23:30.902832
10230 23:23:31.455398 01980000 ################################################################
10231 23:23:31.455549
10232 23:23:32.007926 01a00000 ################################################################
10233 23:23:32.008071
10234 23:23:32.560285 01a80000 ################################################################
10235 23:23:32.560418
10236 23:23:33.124249 01b00000 ################################################################
10237 23:23:33.124416
10238 23:23:33.686146 01b80000 ################################################################
10239 23:23:33.686292
10240 23:23:34.255582 01c00000 ################################################################
10241 23:23:34.255727
10242 23:23:34.824799 01c80000 ################################################################
10243 23:23:34.824945
10244 23:23:35.368546 01d00000 ################################################################
10245 23:23:35.368740
10246 23:23:35.922399 01d80000 ################################################################
10247 23:23:35.922558
10248 23:23:36.205448 01e00000 ################################# done.
10249 23:23:36.205590
10250 23:23:36.208440 The bootfile was 31722762 bytes long.
10251 23:23:36.208538
10252 23:23:36.211208 Sending tftp read request... done.
10253 23:23:36.211291
10254 23:23:36.211356 Waiting for the transfer...
10255 23:23:36.211429
10256 23:23:36.214704 00000000 # done.
10257 23:23:36.214789
10258 23:23:36.221528 Command line loaded dynamically from TFTP file: 13248458/tftp-deploy-z0knm9t8/kernel/cmdline
10259 23:23:36.221612
10260 23:23:36.244231 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248458/extract-nfsrootfs-bhvk718l,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10261 23:23:36.244325
10262 23:23:36.244392 Loading FIT.
10263 23:23:36.244453
10264 23:23:36.247434 Image ramdisk-1 has 18766225 bytes.
10265 23:23:36.247561
10266 23:23:36.250782 Image fdt-1 has 47230 bytes.
10267 23:23:36.250904
10268 23:23:36.254451 Image kernel-1 has 12907270 bytes.
10269 23:23:36.254589
10270 23:23:36.264265 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10271 23:23:36.264390
10272 23:23:36.280283 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10273 23:23:36.280416
10274 23:23:36.287038 Choosing best match conf-1 for compat google,spherion-rev2.
10275 23:23:36.290404
10276 23:23:36.295328 Connected to device vid:did:rid of 1ae0:0028:00
10277 23:23:36.301893
10278 23:23:36.305525 tpm_get_response: command 0x17b, return code 0x0
10279 23:23:36.305635
10280 23:23:36.308771 ec_init: CrosEC protocol v3 supported (256, 248)
10281 23:23:36.312528
10282 23:23:36.315975 tpm_cleanup: add release locality here.
10283 23:23:36.316054
10284 23:23:36.316120 Shutting down all USB controllers.
10285 23:23:36.319599
10286 23:23:36.319674 Removing current net device
10287 23:23:36.319736
10288 23:23:36.325874 Exiting depthcharge with code 4 at timestamp: 68884138
10289 23:23:36.325956
10290 23:23:36.328891 LZMA decompressing kernel-1 to 0x821a6718
10291 23:23:36.328966
10292 23:23:36.332337 LZMA decompressing kernel-1 to 0x40000000
10293 23:23:37.926137
10294 23:23:37.926288 jumping to kernel
10295 23:23:37.926744 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10296 23:23:37.926850 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10297 23:23:37.926927 Setting prompt string to ['Linux version [0-9]']
10298 23:23:37.926997 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10299 23:23:37.927064 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10300 23:23:38.007761
10301 23:23:38.010937 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10302 23:23:38.014387 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10303 23:23:38.014478 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10304 23:23:38.014548 Setting prompt string to []
10305 23:23:38.014622 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10306 23:23:38.014693 Using line separator: #'\n'#
10307 23:23:38.014752 No login prompt set.
10308 23:23:38.014811 Parsing kernel messages
10309 23:23:38.014882 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10310 23:23:38.015000 [login-action] Waiting for messages, (timeout 00:03:44)
10311 23:23:38.015066 Waiting using forced prompt support (timeout 00:01:52)
10312 23:23:38.034266 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10313 23:23:38.037588 [ 0.000000] random: crng init done
10314 23:23:38.044391 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10315 23:23:38.049267 [ 0.000000] efi: UEFI not found.
10316 23:23:38.053983 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10317 23:23:38.060750 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10318 23:23:38.070656 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10319 23:23:38.080158 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10320 23:23:38.086766 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10321 23:23:38.093346 [ 0.000000] printk: bootconsole [mtk8250] enabled
10322 23:23:38.099963 [ 0.000000] NUMA: No NUMA configuration found
10323 23:23:38.106500 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10324 23:23:38.110697 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10325 23:23:38.113718 [ 0.000000] Zone ranges:
10326 23:23:38.120140 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10327 23:23:38.123851 [ 0.000000] DMA32 empty
10328 23:23:38.129907 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10329 23:23:38.132963 [ 0.000000] Movable zone start for each node
10330 23:23:38.136459 [ 0.000000] Early memory node ranges
10331 23:23:38.143019 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10332 23:23:38.149706 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10333 23:23:38.156288 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10334 23:23:38.162716 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10335 23:23:38.168994 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10336 23:23:38.175966 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10337 23:23:38.232439 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10338 23:23:38.238501 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10339 23:23:38.245470 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10340 23:23:38.248882 [ 0.000000] psci: probing for conduit method from DT.
10341 23:23:38.255106 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10342 23:23:38.258515 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10343 23:23:38.265030 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10344 23:23:38.268820 [ 0.000000] psci: SMC Calling Convention v1.2
10345 23:23:38.274806 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10346 23:23:38.278601 [ 0.000000] Detected VIPT I-cache on CPU0
10347 23:23:38.284937 [ 0.000000] CPU features: detected: GIC system register CPU interface
10348 23:23:38.291316 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10349 23:23:38.298275 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10350 23:23:38.304830 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10351 23:23:38.314497 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10352 23:23:38.320975 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10353 23:23:38.324320 [ 0.000000] alternatives: applying boot alternatives
10354 23:23:38.331348 [ 0.000000] Fallback order for Node 0: 0
10355 23:23:38.337794 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10356 23:23:38.340898 [ 0.000000] Policy zone: Normal
10357 23:23:38.363786 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248458/extract-nfsrootfs-bhvk718l,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10358 23:23:38.373694 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10359 23:23:38.385249 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10360 23:23:38.395008 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10361 23:23:38.401436 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10362 23:23:38.405074 <6>[ 0.000000] software IO TLB: area num 8.
10363 23:23:38.462475 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10364 23:23:38.612342 <6>[ 0.000000] Memory: 7946240K/8385536K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 406528K reserved, 32768K cma-reserved)
10365 23:23:38.618184 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10366 23:23:38.624907 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10367 23:23:38.628349 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10368 23:23:38.634901 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10369 23:23:38.641772 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10370 23:23:38.644674 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10371 23:23:38.654622 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10372 23:23:38.660860 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10373 23:23:38.667585 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10374 23:23:38.674281 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10375 23:23:38.677859 <6>[ 0.000000] GICv3: 608 SPIs implemented
10376 23:23:38.681018 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10377 23:23:38.687621 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10378 23:23:38.690611 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10379 23:23:38.697522 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10380 23:23:38.710923 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10381 23:23:38.723909 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10382 23:23:38.730166 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10383 23:23:38.738356 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10384 23:23:38.751526 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10385 23:23:38.757701 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10386 23:23:38.764741 <6>[ 0.009180] Console: colour dummy device 80x25
10387 23:23:38.774942 <6>[ 0.013937] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10388 23:23:38.781044 <6>[ 0.024443] pid_max: default: 32768 minimum: 301
10389 23:23:38.784236 <6>[ 0.029345] LSM: Security Framework initializing
10390 23:23:38.791037 <6>[ 0.034284] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10391 23:23:38.800980 <6>[ 0.042099] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10392 23:23:38.811109 <6>[ 0.051585] cblist_init_generic: Setting adjustable number of callback queues.
10393 23:23:38.817738 <6>[ 0.059075] cblist_init_generic: Setting shift to 3 and lim to 1.
10394 23:23:38.823896 <6>[ 0.065452] cblist_init_generic: Setting adjustable number of callback queues.
10395 23:23:38.830591 <6>[ 0.072924] cblist_init_generic: Setting shift to 3 and lim to 1.
10396 23:23:38.833967 <6>[ 0.079325] rcu: Hierarchical SRCU implementation.
10397 23:23:38.840522 <6>[ 0.084372] rcu: Max phase no-delay instances is 1000.
10398 23:23:38.847058 <6>[ 0.091426] EFI services will not be available.
10399 23:23:38.850549 <6>[ 0.096386] smp: Bringing up secondary CPUs ...
10400 23:23:38.859436 <6>[ 0.101433] Detected VIPT I-cache on CPU1
10401 23:23:38.865576 <6>[ 0.101502] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10402 23:23:38.872364 <6>[ 0.101532] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10403 23:23:38.875729 <6>[ 0.101867] Detected VIPT I-cache on CPU2
10404 23:23:38.885545 <6>[ 0.101919] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10405 23:23:38.891872 <6>[ 0.101936] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10406 23:23:38.895333 <6>[ 0.102194] Detected VIPT I-cache on CPU3
10407 23:23:38.901674 <6>[ 0.102242] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10408 23:23:38.908296 <6>[ 0.102257] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10409 23:23:38.914738 <6>[ 0.102560] CPU features: detected: Spectre-v4
10410 23:23:38.918070 <6>[ 0.102566] CPU features: detected: Spectre-BHB
10411 23:23:38.921426 <6>[ 0.102571] Detected PIPT I-cache on CPU4
10412 23:23:38.931319 <6>[ 0.102628] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10413 23:23:38.937908 <6>[ 0.102645] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10414 23:23:38.941165 <6>[ 0.102936] Detected PIPT I-cache on CPU5
10415 23:23:38.947755 <6>[ 0.102998] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10416 23:23:38.954204 <6>[ 0.103014] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10417 23:23:38.958172 <6>[ 0.103295] Detected PIPT I-cache on CPU6
10418 23:23:38.967528 <6>[ 0.103360] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10419 23:23:38.974403 <6>[ 0.103376] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10420 23:23:38.977251 <6>[ 0.103673] Detected PIPT I-cache on CPU7
10421 23:23:38.983854 <6>[ 0.103738] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10422 23:23:38.990424 <6>[ 0.103754] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10423 23:23:38.997317 <6>[ 0.103803] smp: Brought up 1 node, 8 CPUs
10424 23:23:39.000389 <6>[ 0.245164] SMP: Total of 8 processors activated.
10425 23:23:39.007321 <6>[ 0.250085] CPU features: detected: 32-bit EL0 Support
10426 23:23:39.013755 <6>[ 0.255448] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10427 23:23:39.020226 <6>[ 0.264249] CPU features: detected: Common not Private translations
10428 23:23:39.026660 <6>[ 0.270725] CPU features: detected: CRC32 instructions
10429 23:23:39.033425 <6>[ 0.276077] CPU features: detected: RCpc load-acquire (LDAPR)
10430 23:23:39.039886 <6>[ 0.282074] CPU features: detected: LSE atomic instructions
10431 23:23:39.043475 <6>[ 0.287856] CPU features: detected: Privileged Access Never
10432 23:23:39.050320 <6>[ 0.293635] CPU features: detected: RAS Extension Support
10433 23:23:39.056549 <6>[ 0.299244] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10434 23:23:39.059976 <6>[ 0.306465] CPU: All CPU(s) started at EL2
10435 23:23:39.066702 <6>[ 0.310782] alternatives: applying system-wide alternatives
10436 23:23:39.077320 <6>[ 0.321605] devtmpfs: initialized
10437 23:23:39.092994 <6>[ 0.330527] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10438 23:23:39.099151 <6>[ 0.340488] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10439 23:23:39.105954 <6>[ 0.348768] pinctrl core: initialized pinctrl subsystem
10440 23:23:39.109349 <6>[ 0.355437] DMI not present or invalid.
10441 23:23:39.115439 <6>[ 0.359843] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10442 23:23:39.125495 <6>[ 0.366753] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10443 23:23:39.132262 <6>[ 0.374337] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10444 23:23:39.141828 <6>[ 0.382567] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10445 23:23:39.148743 <6>[ 0.390808] audit: initializing netlink subsys (disabled)
10446 23:23:39.155229 <5>[ 0.396505] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10447 23:23:39.161781 <6>[ 0.397213] thermal_sys: Registered thermal governor 'step_wise'
10448 23:23:39.168533 <6>[ 0.404471] thermal_sys: Registered thermal governor 'power_allocator'
10449 23:23:39.172158 <6>[ 0.410728] cpuidle: using governor menu
10450 23:23:39.178242 <6>[ 0.421688] NET: Registered PF_QIPCRTR protocol family
10451 23:23:39.185177 <6>[ 0.427181] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10452 23:23:39.191298 <6>[ 0.434280] ASID allocator initialised with 32768 entries
10453 23:23:39.195064 <6>[ 0.440848] Serial: AMBA PL011 UART driver
10454 23:23:39.204938 <4>[ 0.449655] Trying to register duplicate clock ID: 134
10455 23:23:39.259310 <6>[ 0.507249] KASLR enabled
10456 23:23:39.274032 <6>[ 0.515145] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10457 23:23:39.280348 <6>[ 0.522161] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10458 23:23:39.287193 <6>[ 0.528654] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10459 23:23:39.293786 <6>[ 0.535656] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10460 23:23:39.300340 <6>[ 0.542141] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10461 23:23:39.306812 <6>[ 0.549148] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10462 23:23:39.313627 <6>[ 0.555636] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10463 23:23:39.320048 <6>[ 0.562637] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10464 23:23:39.323602 <6>[ 0.570173] ACPI: Interpreter disabled.
10465 23:23:39.332296 <6>[ 0.576637] iommu: Default domain type: Translated
10466 23:23:39.338825 <6>[ 0.581746] iommu: DMA domain TLB invalidation policy: strict mode
10467 23:23:39.341858 <5>[ 0.588407] SCSI subsystem initialized
10468 23:23:39.348876 <6>[ 0.592550] usbcore: registered new interface driver usbfs
10469 23:23:39.355587 <6>[ 0.598280] usbcore: registered new interface driver hub
10470 23:23:39.358989 <6>[ 0.603830] usbcore: registered new device driver usb
10471 23:23:39.365176 <6>[ 0.609918] pps_core: LinuxPPS API ver. 1 registered
10472 23:23:39.375540 <6>[ 0.615112] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10473 23:23:39.378428 <6>[ 0.624454] PTP clock support registered
10474 23:23:39.381652 <6>[ 0.628698] EDAC MC: Ver: 3.0.0
10475 23:23:39.389549 <6>[ 0.633881] FPGA manager framework
10476 23:23:39.396200 <6>[ 0.637561] Advanced Linux Sound Architecture Driver Initialized.
10477 23:23:39.398938 <6>[ 0.644341] vgaarb: loaded
10478 23:23:39.405526 <6>[ 0.647519] clocksource: Switched to clocksource arch_sys_counter
10479 23:23:39.409059 <5>[ 0.653963] VFS: Disk quotas dquot_6.6.0
10480 23:23:39.415604 <6>[ 0.658148] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10481 23:23:39.418747 <6>[ 0.665336] pnp: PnP ACPI: disabled
10482 23:23:39.427663 <6>[ 0.672014] NET: Registered PF_INET protocol family
10483 23:23:39.437428 <6>[ 0.677620] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10484 23:23:39.448842 <6>[ 0.689950] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10485 23:23:39.458764 <6>[ 0.698767] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10486 23:23:39.464978 <6>[ 0.706739] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10487 23:23:39.474849 <6>[ 0.715435] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10488 23:23:39.481650 <6>[ 0.725187] TCP: Hash tables configured (established 65536 bind 65536)
10489 23:23:39.487967 <6>[ 0.732050] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10490 23:23:39.498223 <6>[ 0.739250] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10491 23:23:39.504538 <6>[ 0.746953] NET: Registered PF_UNIX/PF_LOCAL protocol family
10492 23:23:39.510968 <6>[ 0.753104] RPC: Registered named UNIX socket transport module.
10493 23:23:39.514936 <6>[ 0.759257] RPC: Registered udp transport module.
10494 23:23:39.521045 <6>[ 0.764190] RPC: Registered tcp transport module.
10495 23:23:39.527793 <6>[ 0.769122] RPC: Registered tcp NFSv4.1 backchannel transport module.
10496 23:23:39.530812 <6>[ 0.775785] PCI: CLS 0 bytes, default 64
10497 23:23:39.534444 <6>[ 0.780119] Unpacking initramfs...
10498 23:23:39.558439 <6>[ 0.799634] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10499 23:23:39.568206 <6>[ 0.808304] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10500 23:23:39.571502 <6>[ 0.817182] kvm [1]: IPA Size Limit: 40 bits
10501 23:23:39.578185 <6>[ 0.821711] kvm [1]: GICv3: no GICV resource entry
10502 23:23:39.581376 <6>[ 0.826732] kvm [1]: disabling GICv2 emulation
10503 23:23:39.588326 <6>[ 0.831421] kvm [1]: GIC system register CPU interface enabled
10504 23:23:39.591191 <6>[ 0.837593] kvm [1]: vgic interrupt IRQ18
10505 23:23:39.598067 <6>[ 0.841946] kvm [1]: VHE mode initialized successfully
10506 23:23:39.604781 <5>[ 0.848498] Initialise system trusted keyrings
10507 23:23:39.611525 <6>[ 0.853323] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10508 23:23:39.618844 <6>[ 0.863504] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10509 23:23:39.625538 <5>[ 0.869940] NFS: Registering the id_resolver key type
10510 23:23:39.628948 <5>[ 0.875239] Key type id_resolver registered
10511 23:23:39.635329 <5>[ 0.879655] Key type id_legacy registered
10512 23:23:39.642090 <6>[ 0.883935] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10513 23:23:39.648797 <6>[ 0.890858] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10514 23:23:39.655105 <6>[ 0.898573] 9p: Installing v9fs 9p2000 file system support
10515 23:23:39.691521 <5>[ 0.936095] Key type asymmetric registered
10516 23:23:39.695158 <5>[ 0.940425] Asymmetric key parser 'x509' registered
10517 23:23:39.705108 <6>[ 0.945588] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10518 23:23:39.708276 <6>[ 0.953205] io scheduler mq-deadline registered
10519 23:23:39.711857 <6>[ 0.957962] io scheduler kyber registered
10520 23:23:39.730937 <6>[ 0.975184] EINJ: ACPI disabled.
10521 23:23:39.763906 <4>[ 1.001327] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10522 23:23:39.773004 <4>[ 1.011994] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10523 23:23:39.788291 <6>[ 1.032809] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10524 23:23:39.796305 <6>[ 1.040938] printk: console [ttyS0] disabled
10525 23:23:39.824530 <6>[ 1.065572] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10526 23:23:39.831144 <6>[ 1.075049] printk: console [ttyS0] enabled
10527 23:23:39.834378 <6>[ 1.075049] printk: console [ttyS0] enabled
10528 23:23:39.840927 <6>[ 1.083946] printk: bootconsole [mtk8250] disabled
10529 23:23:39.843894 <6>[ 1.083946] printk: bootconsole [mtk8250] disabled
10530 23:23:39.850598 <6>[ 1.095351] SuperH (H)SCI(F) driver initialized
10531 23:23:39.854304 <6>[ 1.100654] msm_serial: driver initialized
10532 23:23:39.868570 <6>[ 1.109676] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10533 23:23:39.878576 <6>[ 1.118226] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10534 23:23:39.885022 <6>[ 1.126770] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10535 23:23:39.894810 <6>[ 1.135398] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10536 23:23:39.904740 <6>[ 1.144106] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10537 23:23:39.911620 <6>[ 1.152825] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10538 23:23:39.921034 <6>[ 1.161379] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10539 23:23:39.927975 <6>[ 1.170194] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10540 23:23:39.937943 <6>[ 1.178738] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10541 23:23:39.949961 <6>[ 1.194547] loop: module loaded
10542 23:23:39.956535 <6>[ 1.200566] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10543 23:23:39.979546 <4>[ 1.223864] mtk-pmic-keys: Failed to locate of_node [id: -1]
10544 23:23:39.986395 <6>[ 1.230764] megasas: 07.719.03.00-rc1
10545 23:23:39.995967 <6>[ 1.240619] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10546 23:23:40.006467 <6>[ 1.250889] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10547 23:23:40.022701 <6>[ 1.267442] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10548 23:23:40.078462 <6>[ 1.316782] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10549 23:23:40.323462 <6>[ 1.568168] Freeing initrd memory: 18324K
10550 23:23:40.335655 <6>[ 1.580012] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10551 23:23:40.346204 <6>[ 1.591004] tun: Universal TUN/TAP device driver, 1.6
10552 23:23:40.349695 <6>[ 1.597100] thunder_xcv, ver 1.0
10553 23:23:40.353365 <6>[ 1.600603] thunder_bgx, ver 1.0
10554 23:23:40.356306 <6>[ 1.604097] nicpf, ver 1.0
10555 23:23:40.366818 <6>[ 1.608146] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10556 23:23:40.370118 <6>[ 1.615623] hns3: Copyright (c) 2017 Huawei Corporation.
10557 23:23:40.373438 <6>[ 1.621213] hclge is initializing
10558 23:23:40.380132 <6>[ 1.624793] e1000: Intel(R) PRO/1000 Network Driver
10559 23:23:40.386678 <6>[ 1.629923] e1000: Copyright (c) 1999-2006 Intel Corporation.
10560 23:23:40.390047 <6>[ 1.635936] e1000e: Intel(R) PRO/1000 Network Driver
10561 23:23:40.396645 <6>[ 1.641151] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10562 23:23:40.403208 <6>[ 1.647339] igb: Intel(R) Gigabit Ethernet Network Driver
10563 23:23:40.410125 <6>[ 1.652989] igb: Copyright (c) 2007-2014 Intel Corporation.
10564 23:23:40.416874 <6>[ 1.658826] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10565 23:23:40.423080 <6>[ 1.665343] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10566 23:23:40.426463 <6>[ 1.671812] sky2: driver version 1.30
10567 23:23:40.432907 <6>[ 1.676826] VFIO - User Level meta-driver version: 0.3
10568 23:23:40.440810 <6>[ 1.685136] usbcore: registered new interface driver usb-storage
10569 23:23:40.447192 <6>[ 1.691593] usbcore: registered new device driver onboard-usb-hub
10570 23:23:40.456159 <6>[ 1.700805] mt6397-rtc mt6359-rtc: registered as rtc0
10571 23:23:40.465827 <6>[ 1.706278] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:23:40 UTC (1712186620)
10572 23:23:40.469264 <6>[ 1.715892] i2c_dev: i2c /dev entries driver
10573 23:23:40.486208 <6>[ 1.727751] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10574 23:23:40.492880 <4>[ 1.736493] cpu cpu0: supply cpu not found, using dummy regulator
10575 23:23:40.499672 <4>[ 1.742922] cpu cpu1: supply cpu not found, using dummy regulator
10576 23:23:40.506253 <4>[ 1.749324] cpu cpu2: supply cpu not found, using dummy regulator
10577 23:23:40.512914 <4>[ 1.755729] cpu cpu3: supply cpu not found, using dummy regulator
10578 23:23:40.519688 <4>[ 1.762128] cpu cpu4: supply cpu not found, using dummy regulator
10579 23:23:40.526219 <4>[ 1.768542] cpu cpu5: supply cpu not found, using dummy regulator
10580 23:23:40.533085 <4>[ 1.774940] cpu cpu6: supply cpu not found, using dummy regulator
10581 23:23:40.539547 <4>[ 1.781336] cpu cpu7: supply cpu not found, using dummy regulator
10582 23:23:40.558065 <6>[ 1.802990] cpu cpu0: EM: created perf domain
10583 23:23:40.561286 <6>[ 1.807932] cpu cpu4: EM: created perf domain
10584 23:23:40.569013 <6>[ 1.813545] sdhci: Secure Digital Host Controller Interface driver
10585 23:23:40.575817 <6>[ 1.819979] sdhci: Copyright(c) Pierre Ossman
10586 23:23:40.581945 <6>[ 1.824940] Synopsys Designware Multimedia Card Interface Driver
10587 23:23:40.588613 <6>[ 1.831589] sdhci-pltfm: SDHCI platform and OF driver helper
10588 23:23:40.592315 <6>[ 1.831628] mmc0: CQHCI version 5.10
10589 23:23:40.598680 <6>[ 1.841607] ledtrig-cpu: registered to indicate activity on CPUs
10590 23:23:40.605465 <6>[ 1.848667] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10591 23:23:40.612095 <6>[ 1.855740] usbcore: registered new interface driver usbhid
10592 23:23:40.615075 <6>[ 1.861565] usbhid: USB HID core driver
10593 23:23:40.622103 <6>[ 1.865772] spi_master spi0: will run message pump with realtime priority
10594 23:23:40.664626 <6>[ 1.902738] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10595 23:23:40.683632 <6>[ 1.917906] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10596 23:23:40.690706 <6>[ 1.933540] cros-ec-spi spi0.0: Chrome EC device registered
10597 23:23:40.693906 <6>[ 1.939609] mmc0: Command Queue Engine enabled
10598 23:23:40.701184 <6>[ 1.944342] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10599 23:23:40.710983 <6>[ 1.951215] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10600 23:23:40.713942 <6>[ 1.951655] mmcblk0: mmc0:0001 DA4128 116 GiB
10601 23:23:40.720478 <6>[ 1.961629] NET: Registered PF_PACKET protocol family
10602 23:23:40.727292 <6>[ 1.968810] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10603 23:23:40.730351 <6>[ 1.970610] 9pnet: Installing 9P2000 support
10604 23:23:40.736992 <6>[ 1.977891] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10605 23:23:40.740481 <5>[ 1.980995] Key type dns_resolver registered
10606 23:23:40.747092 <6>[ 1.986828] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10607 23:23:40.750354 <6>[ 1.991165] registered taskstats version 1
10608 23:23:40.757153 <6>[ 1.996550] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10609 23:23:40.763610 <5>[ 2.000298] Loading compiled-in X.509 certificates
10610 23:23:40.778070 <4>[ 2.016259] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 23:23:40.787956 <4>[ 2.026933] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10612 23:23:40.794896 <3>[ 2.037464] debugfs: File 'uA_load' in directory '/' already present!
10613 23:23:40.801181 <3>[ 2.044164] debugfs: File 'min_uV' in directory '/' already present!
10614 23:23:40.808079 <3>[ 2.050770] debugfs: File 'max_uV' in directory '/' already present!
10615 23:23:40.814652 <3>[ 2.057377] debugfs: File 'constraint_flags' in directory '/' already present!
10616 23:23:40.825113 <3>[ 2.066614] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10617 23:23:40.834129 <6>[ 2.078874] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10618 23:23:40.841253 <6>[ 2.085804] xhci-mtk 11200000.usb: xHCI Host Controller
10619 23:23:40.848086 <6>[ 2.091301] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10620 23:23:40.857782 <6>[ 2.099142] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10621 23:23:40.864382 <6>[ 2.108561] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10622 23:23:40.871380 <6>[ 2.114623] xhci-mtk 11200000.usb: xHCI Host Controller
10623 23:23:40.878037 <6>[ 2.120097] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10624 23:23:40.884608 <6>[ 2.127745] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10625 23:23:40.891072 <6>[ 2.135406] hub 1-0:1.0: USB hub found
10626 23:23:40.894477 <6>[ 2.139418] hub 1-0:1.0: 1 port detected
10627 23:23:40.900967 <6>[ 2.143710] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10628 23:23:40.907507 <6>[ 2.152239] hub 2-0:1.0: USB hub found
10629 23:23:40.911013 <6>[ 2.156244] hub 2-0:1.0: 1 port detected
10630 23:23:40.918913 <6>[ 2.163674] mtk-msdc 11f70000.mmc: Got CD GPIO
10631 23:23:40.929504 <6>[ 2.170740] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10632 23:23:40.936013 <6>[ 2.178767] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10633 23:23:40.945848 <4>[ 2.186668] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10634 23:23:40.955939 <6>[ 2.196193] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10635 23:23:40.962439 <6>[ 2.204270] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10636 23:23:40.969133 <6>[ 2.212411] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10637 23:23:40.979374 <6>[ 2.220346] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10638 23:23:40.985742 <6>[ 2.228227] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10639 23:23:40.995468 <6>[ 2.236057] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10640 23:23:41.005757 <6>[ 2.246514] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10641 23:23:41.012066 <6>[ 2.254870] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10642 23:23:41.022185 <6>[ 2.263245] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10643 23:23:41.028650 <6>[ 2.271585] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10644 23:23:41.038465 <6>[ 2.279938] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10645 23:23:41.048812 <6>[ 2.288276] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10646 23:23:41.055308 <6>[ 2.296624] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10647 23:23:41.064901 <6>[ 2.304962] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10648 23:23:41.071896 <6>[ 2.313310] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10649 23:23:41.081820 <6>[ 2.321648] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10650 23:23:41.088449 <6>[ 2.329995] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10651 23:23:41.098040 <6>[ 2.338333] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10652 23:23:41.104961 <6>[ 2.346670] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10653 23:23:41.114601 <6>[ 2.355009] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10654 23:23:41.121309 <6>[ 2.363346] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10655 23:23:41.127535 <6>[ 2.372100] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10656 23:23:41.135082 <6>[ 2.379305] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10657 23:23:41.141770 <6>[ 2.386080] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10658 23:23:41.148495 <6>[ 2.392851] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10659 23:23:41.158588 <6>[ 2.399787] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10660 23:23:41.164839 <6>[ 2.406641] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10661 23:23:41.175271 <6>[ 2.415771] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10662 23:23:41.184698 <6>[ 2.424891] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10663 23:23:41.194847 <6>[ 2.434186] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10664 23:23:41.205265 <6>[ 2.443693] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10665 23:23:41.211257 <6>[ 2.453253] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10666 23:23:41.221352 <6>[ 2.462374] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10667 23:23:41.230929 <6>[ 2.471839] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10668 23:23:41.240864 <6>[ 2.480957] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10669 23:23:41.250892 <6>[ 2.490252] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10670 23:23:41.260708 <6>[ 2.500413] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10671 23:23:41.270643 <6>[ 2.511893] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10672 23:23:41.277329 <6>[ 2.521566] Trying to probe devices needed for running init ...
10673 23:23:41.338384 <6>[ 2.579646] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10674 23:23:41.492739 <6>[ 2.737353] hub 1-1:1.0: USB hub found
10675 23:23:41.495841 <6>[ 2.741725] hub 1-1:1.0: 4 ports detected
10676 23:23:41.504648 <6>[ 2.749420] hub 1-1:1.0: USB hub found
10677 23:23:41.508114 <6>[ 2.753753] hub 1-1:1.0: 4 ports detected
10678 23:23:41.618880 <6>[ 2.860151] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10679 23:23:41.644758 <6>[ 2.889480] hub 2-1:1.0: USB hub found
10680 23:23:41.647757 <6>[ 2.893980] hub 2-1:1.0: 3 ports detected
10681 23:23:41.657599 <6>[ 2.902083] hub 2-1:1.0: USB hub found
10682 23:23:41.660370 <6>[ 2.906525] hub 2-1:1.0: 3 ports detected
10683 23:23:41.834276 <6>[ 3.075835] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10684 23:23:41.966392 <6>[ 3.211111] hub 1-1.4:1.0: USB hub found
10685 23:23:41.969480 <6>[ 3.215697] hub 1-1.4:1.0: 2 ports detected
10686 23:23:41.979133 <6>[ 3.223864] hub 1-1.4:1.0: USB hub found
10687 23:23:41.982158 <6>[ 3.228492] hub 1-1.4:1.0: 2 ports detected
10688 23:23:42.050594 <6>[ 3.291950] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10689 23:23:42.278430 <6>[ 3.519825] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10690 23:23:42.470395 <6>[ 3.711802] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10691 23:23:53.551336 <6>[ 14.800835] ALSA device list:
10692 23:23:53.558366 <6>[ 14.804132] No soundcards found.
10693 23:23:53.566695 <6>[ 14.812539] Freeing unused kernel memory: 8448K
10694 23:23:53.569978 <6>[ 14.817485] Run /init as init process
10695 23:23:53.579997 Loading, please wait...
10696 23:23:53.606519 Starting systemd-udevd version 252.22-1~deb12u1
10697 23:23:53.606651
10698 23:23:53.864904 <6>[ 15.107935] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10699 23:23:53.871657 <6>[ 15.109094] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10700 23:23:53.881539 <3>[ 15.114094] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 23:23:53.888264 <3>[ 15.114104] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 23:23:53.894918 <3>[ 15.114108] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 23:23:53.904805 <3>[ 15.114181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 23:23:53.911383 <3>[ 15.114185] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 23:23:53.921280 <3>[ 15.114188] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 23:23:53.927723 <3>[ 15.114193] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 23:23:53.937821 <3>[ 15.114197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 23:23:53.944220 <3>[ 15.114217] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 23:23:53.954191 <3>[ 15.114241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 23:23:53.960517 <3>[ 15.114244] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 23:23:53.970376 <3>[ 15.114246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 23:23:53.976979 <3>[ 15.114269] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 23:23:53.983623 <3>[ 15.114272] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 23:23:53.993730 <3>[ 15.114275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 23:23:54.000340 <3>[ 15.114278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 23:23:54.010138 <3>[ 15.114281] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 23:23:54.016590 <3>[ 15.114297] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 23:23:54.027160 <6>[ 15.115944] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10719 23:23:54.033683 <6>[ 15.116148] usbcore: registered new device driver r8152-cfgselector
10720 23:23:54.037093 <6>[ 15.142723] remoteproc remoteproc0: scp is available
10721 23:23:54.047379 <6>[ 15.147407] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10722 23:23:54.053533 <4>[ 15.148144] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10723 23:23:54.060172 <4>[ 15.148276] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10724 23:23:54.067020 <6>[ 15.155654] remoteproc remoteproc0: powering up scp
10725 23:23:54.070318 <6>[ 15.182600] mc: Linux media interface: v0.10
10726 23:23:54.080314 <6>[ 15.187997] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10727 23:23:54.087341 <6>[ 15.189858] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10728 23:23:54.097286 <4>[ 15.214001] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10729 23:23:54.100793 <4>[ 15.214001] Fallback method does not support PEC.
10730 23:23:54.107276 <6>[ 15.220083] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10731 23:23:54.117565 <6>[ 15.258890] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10732 23:23:54.124170 <6>[ 15.261055] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10733 23:23:54.134280 <3>[ 15.277289] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10734 23:23:54.143693 <6>[ 15.296208] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10735 23:23:54.150893 <6>[ 15.297688] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10736 23:23:54.156792 <6>[ 15.297696] pci_bus 0000:00: root bus resource [bus 00-ff]
10737 23:23:54.163680 <6>[ 15.297704] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10738 23:23:54.173583 <6>[ 15.297711] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10739 23:23:54.179893 <6>[ 15.297747] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10740 23:23:54.186528 <6>[ 15.297769] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10741 23:23:54.189733 <6>[ 15.297853] pci 0000:00:00.0: supports D1 D2
10742 23:23:54.196715 <6>[ 15.297857] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10743 23:23:54.206584 <6>[ 15.300019] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10744 23:23:54.216246 <6>[ 15.306356] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10745 23:23:54.219906 <6>[ 15.312771] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10746 23:23:54.230105 <4>[ 15.327648] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10747 23:23:54.236864 <6>[ 15.331608] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10748 23:23:54.243053 <6>[ 15.332881] videodev: Linux video capture interface: v2.00
10749 23:23:54.253143 <4>[ 15.338425] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10750 23:23:54.259541 <3>[ 15.343342] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10751 23:23:54.265948 <6>[ 15.345371] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10752 23:23:54.276251 <6>[ 15.345438] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10753 23:23:54.282340 <6>[ 15.345448] remoteproc remoteproc0: remote processor scp is now up
10754 23:23:54.288964 <6>[ 15.352038] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10755 23:23:54.292609 <6>[ 15.352727] Bluetooth: Core ver 2.22
10756 23:23:54.299142 <6>[ 15.352802] NET: Registered PF_BLUETOOTH protocol family
10757 23:23:54.305629 <6>[ 15.352806] Bluetooth: HCI device and connection manager initialized
10758 23:23:54.312407 <6>[ 15.352838] Bluetooth: HCI socket layer initialized
10759 23:23:54.315637 <6>[ 15.352847] Bluetooth: L2CAP socket layer initialized
10760 23:23:54.322377 <6>[ 15.352860] Bluetooth: SCO socket layer initialized
10761 23:23:54.328772 <6>[ 15.354464] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10762 23:23:54.338699 <6>[ 15.356884] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10763 23:23:54.345323 <6>[ 15.402412] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10764 23:23:54.352108 <6>[ 15.402570] usbcore: registered new interface driver btusb
10765 23:23:54.362084 <4>[ 15.403225] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10766 23:23:54.368522 <3>[ 15.403240] Bluetooth: hci0: Failed to load firmware file (-2)
10767 23:23:54.371798 <3>[ 15.403243] Bluetooth: hci0: Failed to set up firmware (-2)
10768 23:23:54.384847 <4>[ 15.403248] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10769 23:23:54.391562 <6>[ 15.407586] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10770 23:23:54.404673 <6>[ 15.414996] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10771 23:23:54.408241 <6>[ 15.423988] pci 0000:01:00.0: supports D1 D2
10772 23:23:54.414556 <6>[ 15.424589] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10773 23:23:54.421103 <6>[ 15.430256] usbcore: registered new interface driver uvcvideo
10774 23:23:54.428407 <6>[ 15.437577] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10775 23:23:54.431105 <6>[ 15.443771] r8152 2-1.3:1.0 eth0: v1.12.13
10776 23:23:54.437699 <6>[ 15.451657] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10777 23:23:54.444282 <6>[ 15.457346] usbcore: registered new interface driver r8152
10778 23:23:54.450872 <6>[ 15.466309] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10779 23:23:54.457570 <6>[ 15.489294] usbcore: registered new interface driver cdc_ether
10780 23:23:54.467135 <6>[ 15.494778] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10781 23:23:54.473896 <6>[ 15.494787] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10782 23:23:54.480291 <6>[ 15.518751] usbcore: registered new interface driver r8153_ecm
10783 23:23:54.487196 <6>[ 15.527180] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10784 23:23:54.494113 <6>[ 15.565469] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10785 23:23:54.503494 <6>[ 15.567481] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10786 23:23:54.507170 <6>[ 15.753661] pci 0000:00:00.0: PCI bridge to [bus 01]
10787 23:23:54.517411 <6>[ 15.758878] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10788 23:23:54.523335 <6>[ 15.767025] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10789 23:23:54.529741 <6>[ 15.773868] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10790 23:23:54.536710 <6>[ 15.780704] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10791 23:23:54.552102 <5>[ 15.795224] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10792 23:23:54.576480 <5>[ 15.819473] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10793 23:23:54.583342 <5>[ 15.826740] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10794 23:23:54.593096 <4>[ 15.835238] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10795 23:23:54.599848 <6>[ 15.844141] cfg80211: failed to load regulatory.db
10796 23:23:54.637697 <6>[ 15.880694] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10797 23:23:54.644285 <6>[ 15.888266] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10798 23:23:54.665335 <6>[ 15.911768] mt7921e 0000:01:00.0: ASIC revision: 79610010
10799 23:23:54.768843 <6>[ 16.011701] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10800 23:23:54.771845 <6>[ 16.011701]
10801 23:23:54.786100 Begin: Loading essential drivers ... done.
10802 23:23:54.789937 Begin: Running /scripts/init-premount ... done.
10803 23:23:54.796479 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10804 23:23:54.806229 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10805 23:23:54.809454 Device /sys/class/net/enx002432307c7b found
10806 23:23:54.809548 done.
10807 23:23:54.816322 Begin: Waiting up to 180 secs for any network device to become available ... done.
10808 23:23:54.852876 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10809 23:23:55.041822 <6>[ 16.284096] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10810 23:23:55.771741 <6>[ 17.018317] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10811 23:23:55.905339 <6>[ 17.151706] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10812 23:23:55.959875 IP-Config: no response after 2 secs - giving up
10813 23:23:56.020592 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10814 23:23:56.037324 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:a1 mtu 1500 DHCP
10815 23:23:56.730861 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10816 23:23:56.737351 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10817 23:23:56.744330 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10818 23:23:56.750793 host : mt8192-asurada-spherion-r0-cbg-2
10819 23:23:56.757027 domain : lava-rack
10820 23:23:56.763748 rootserver: 192.168.201.1 rootpath:
10821 23:23:56.763831 filename :
10822 23:23:56.882596 done.
10823 23:23:56.891141 Begin: Running /scripts/nfs-bottom ... done.
10824 23:23:56.910238 Begin: Running /scripts/init-bottom ... done.
10825 23:23:58.259925 <6>[ 19.506170] NET: Registered PF_INET6 protocol family
10826 23:23:58.267106 <6>[ 19.513852] Segment Routing with IPv6
10827 23:23:58.270432 <6>[ 19.517864] In-situ OAM (IOAM) with IPv6
10828 23:23:58.450823 <30>[ 19.670789] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10829 23:23:58.457500 <30>[ 19.703901] systemd[1]: Detected architecture arm64.
10830 23:23:58.465853
10831 23:23:58.469289 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10832 23:23:58.469371
10833 23:23:58.469434
10834 23:23:58.494560 <30>[ 19.741024] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10835 23:23:59.587553 <30>[ 20.830983] systemd[1]: Queued start job for default target graphical.target.
10836 23:23:59.641673 <30>[ 20.884751] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10837 23:23:59.647801 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10838 23:23:59.647892
10839 23:23:59.670280 <30>[ 20.913534] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10840 23:23:59.680532 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10841 23:23:59.680617
10842 23:23:59.698797 <30>[ 20.941584] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10843 23:23:59.708405 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10844 23:23:59.708488
10845 23:23:59.725782 <30>[ 20.969135] systemd[1]: Created slice user.slice - User and Session Slice.
10846 23:23:59.732124 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10847 23:23:59.732206
10848 23:23:59.757041 <30>[ 20.996670] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10849 23:23:59.763183 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10850 23:23:59.766580
10851 23:23:59.783998 <30>[ 21.024053] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10852 23:23:59.790252 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10853 23:23:59.790361
10854 23:23:59.818902 <30>[ 21.052358] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10855 23:23:59.828870 <30>[ 21.072486] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10856 23:23:59.836198 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10857 23:23:59.836280
10858 23:23:59.852296 <30>[ 21.095823] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10859 23:23:59.858946 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10860 23:23:59.862193
10861 23:23:59.876313 <30>[ 21.119856] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10862 23:23:59.886489 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10863 23:23:59.886597
10864 23:23:59.901458 <30>[ 21.147922] systemd[1]: Reached target paths.target - Path Units.
10865 23:23:59.907638 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10866 23:23:59.911070
10867 23:23:59.929366 <30>[ 21.172262] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10868 23:23:59.935269 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10869 23:23:59.935399
10870 23:23:59.948935 <30>[ 21.195803] systemd[1]: Reached target slices.target - Slice Units.
10871 23:23:59.958873 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10872 23:23:59.958954
10873 23:23:59.973249 <30>[ 21.220301] systemd[1]: Reached target swap.target - Swaps.
10874 23:23:59.980189 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10875 23:23:59.980270
10876 23:24:00.000518 <30>[ 21.244237] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10877 23:24:00.010556 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10878 23:24:00.010639
10879 23:24:00.028990 <30>[ 21.272274] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10880 23:24:00.039037 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10881 23:24:00.039147
10882 23:24:00.059642 <30>[ 21.303216] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10883 23:24:00.069922 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10884 23:24:00.070005
10885 23:24:00.086001 <30>[ 21.329328] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10886 23:24:00.095400 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10887 23:24:00.095496
10888 23:24:00.113216 <30>[ 21.356448] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10889 23:24:00.119782 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10890 23:24:00.119864
10891 23:24:00.137637 <30>[ 21.381387] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10892 23:24:00.147522 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10893 23:24:00.147607
10894 23:24:00.167108 <30>[ 21.410810] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10895 23:24:00.176962 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10896 23:24:00.177079
10897 23:24:00.192850 <30>[ 21.436293] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10898 23:24:00.202758 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10899 23:24:00.202901
10900 23:24:00.244161 <30>[ 21.487901] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10901 23:24:00.251179 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10902 23:24:00.251289
10903 23:24:00.273106 <30>[ 21.516564] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10904 23:24:00.279841 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10905 23:24:00.279940
10906 23:24:00.305416 <30>[ 21.548960] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10907 23:24:00.312287 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10908 23:24:00.312370
10909 23:24:00.339609 <30>[ 21.576397] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10910 23:24:00.354769 <30>[ 21.598516] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10911 23:24:00.364722 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10912 23:24:00.364806
10913 23:24:00.385905 <30>[ 21.629484] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10914 23:24:00.392332 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10915 23:24:00.392415
10916 23:24:00.418107 <30>[ 21.661876] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10917 23:24:00.424910 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10918 23:24:00.424992
10919 23:24:00.449965 <30>[ 21.693370] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10920 23:24:00.463213 Starting [0;1;39mmodprobe@drm.service<6>[ 21.705324] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10921 23:24:00.466469 [0m - Load Kernel Module drm...
10922 23:24:00.466550
10923 23:24:00.525369 <30>[ 21.768718] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10924 23:24:00.535094 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10925 23:24:00.535177
10926 23:24:00.558571 <30>[ 21.801554] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10927 23:24:00.564425 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10928 23:24:00.564509
10929 23:24:00.589994 <30>[ 21.833623] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10930 23:24:00.600056 Starting [0;1;39mmodprobe@loop.ser…e<6>[ 21.844735] fuse: init (API version 7.37)
10931 23:24:00.600189 [0m - Load Kernel Module loop...
10932 23:24:00.602952
10933 23:24:00.629505 <30>[ 21.873264] systemd[1]: Starting systemd-journald.service - Journal Service...
10934 23:24:00.636476 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10935 23:24:00.636598
10936 23:24:00.669230 <30>[ 21.912922] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10937 23:24:00.675966 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10938 23:24:00.676091
10939 23:24:00.704940 <30>[ 21.945376] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10940 23:24:00.711845 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10941 23:24:00.711974
10942 23:24:00.737042 <30>[ 21.980833] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10943 23:24:00.746982 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10944 23:24:00.747103
10945 23:24:00.770189 <30>[ 22.013245] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10946 23:24:00.783996 Starting [0;1;39msystemd-udev-trig…[<3>[ 22.025255] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 23:24:00.787321 0m - Coldplug All udev Devices...
10948 23:24:00.787467
10949 23:24:00.809029 <30>[ 22.051998] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10950 23:24:00.821860 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepag<3>[ 22.062617] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 23:24:00.825777 es.mount[0m - Huge Pages File System.
10952 23:24:00.825860
10953 23:24:00.840873 <30>[ 22.084132] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10954 23:24:00.847186 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10955 23:24:00.847315
10956 23:24:00.865073 <30>[ 22.108061] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10957 23:24:00.871538 <3>[ 22.113519] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 23:24:00.881377 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10959 23:24:00.881505
10960 23:24:00.901236 <30>[ 22.144566] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10961 23:24:00.910975 <3>[ 22.144804] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 23:24:00.917413 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10963 23:24:00.917538
10964 23:24:00.938345 <30>[ 22.181787] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10965 23:24:00.944915 <3>[ 22.183677] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 23:24:00.954859 <30>[ 22.189923] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10967 23:24:00.961449 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10968 23:24:00.961561
10969 23:24:00.974650 <3>[ 22.218542] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 23:24:00.984801 <30>[ 22.228568] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10971 23:24:00.992646 <30>[ 22.236258] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10972 23:24:01.005546 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 22.247829] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 23:24:01.008997 m_mod.s…e[0m - Load Kernel Module dm_mod.
10974 23:24:01.009079
10975 23:24:01.029763 <30>[ 22.273110] systemd[1]: modprobe@drm.service: Deactivated successfully.
10976 23:24:01.036294 <3>[ 22.278428] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 23:24:01.046075 <30>[ 22.281056] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10978 23:24:01.052916 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10979 23:24:01.052998
10980 23:24:01.067876 <3>[ 22.311400] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 23:24:01.078497 <30>[ 22.322139] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10982 23:24:01.089286 <30>[ 22.332704] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10983 23:24:01.102819 [[0;32m OK [0m] Finished [0<3>[ 22.343546] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 23:24:01.106106 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10985 23:24:01.106203
10986 23:24:01.126042 <30>[ 22.368891] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10987 23:24:01.132897 <30>[ 22.377042] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10988 23:24:01.142308 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10989 23:24:01.142391
10990 23:24:01.160940 <30>[ 22.404382] systemd[1]: Started systemd-journald.service - Journal Service.
10991 23:24:01.167348 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10992 23:24:01.167500
10993 23:24:01.186029 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10994 23:24:01.186178
10995 23:24:01.212180 <4>[ 22.449097] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10996 23:24:01.222387 <3>[ 22.464776] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10997 23:24:01.228804 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10998 23:24:01.228937
10999 23:24:01.249441 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11000 23:24:01.249529
11001 23:24:01.269706 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11002 23:24:01.269841
11003 23:24:01.289966 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11004 23:24:01.290098
11005 23:24:01.311281 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11006 23:24:01.311447
11007 23:24:01.364789 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11008 23:24:01.364886
11009 23:24:01.386883 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11010 23:24:01.387000
11011 23:24:01.410239 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11012 23:24:01.410327
11013 23:24:01.434170 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11014 23:24:01.434254
11015 23:24:01.466646 <46>[ 22.710544] systemd-journald[307]: Received client request to flush runtime journal.
11016 23:24:01.489749 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11017 23:24:01.489840
11018 23:24:01.516484 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11019 23:24:01.516587
11020 23:24:01.794337 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11021 23:24:01.794484
11022 23:24:01.813120 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11023 23:24:01.813261
11024 23:24:01.832802 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11025 23:24:01.832924
11026 23:24:02.526213 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11027 23:24:02.526364
11028 23:24:02.935556 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11029 23:24:02.935764
11030 23:24:02.953009 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11031 23:24:02.953136
11032 23:24:03.009045 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11033 23:24:03.009193
11034 23:24:03.106338 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11035 23:24:03.106513
11036 23:24:03.125093 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11037 23:24:03.125226
11038 23:24:03.144775 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11039 23:24:03.144904
11040 23:24:03.193332 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11041 23:24:03.193472
11042 23:24:03.217875 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11043 23:24:03.218007
11044 23:24:03.456919 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11045 23:24:03.457163
11046 23:24:03.527270 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11047 23:24:03.527460
11048 23:24:03.582867 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11049 23:24:03.583033
11050 23:24:03.908686 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11051 23:24:03.908929
11052 23:24:03.935692 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11053 23:24:03.935801
11054 23:24:03.984216 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11055 23:24:03.984343
11056 23:24:04.084758 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11057 23:24:04.084910
11058 23:24:04.108872 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11059 23:24:04.108964
11060 23:24:04.128929 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11061 23:24:04.129017
11062 23:24:04.149258 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11063 23:24:04.149343
11064 23:24:04.221384 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11065 23:24:04.221511
11066 23:24:04.237890 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11067 23:24:04.237975
11068 23:24:04.256527 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11069 23:24:04.256612
11070 23:24:04.274080 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11071 23:24:04.274165
11072 23:24:04.325033 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11073 23:24:04.325135
11074 23:24:04.345113 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11075 23:24:04.345196
11076 23:24:04.365887 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11077 23:24:04.365972
11078 23:24:04.384340 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11079 23:24:04.384424
11080 23:24:04.403950 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11081 23:24:04.404034
11082 23:24:04.429265 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11083 23:24:04.429353
11084 23:24:04.451704 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11085 23:24:04.451805
11086 23:24:04.468327 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11087 23:24:04.468412
11088 23:24:04.487880 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11089 23:24:04.487964
11090 23:24:04.508065 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11091 23:24:04.508153
11092 23:24:04.523926 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11093 23:24:04.524013
11094 23:24:04.553012 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11095 23:24:04.553102
11096 23:24:04.571750 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11097 23:24:04.571834
11098 23:24:04.578250 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11099 23:24:04.578350
11100 23:24:04.633628 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11101 23:24:04.633739
11102 23:24:04.666465 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11103 23:24:04.666575
11104 23:24:04.745064 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11105 23:24:04.745180
11106 23:24:04.769393 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11107 23:24:04.769524
11108 23:24:04.789495 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11109 23:24:04.789599
11110 23:24:04.982573 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11111 23:24:04.982717
11112 23:24:05.042987 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11113 23:24:05.043130
11114 23:24:05.085499 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11115 23:24:05.085682
11116 23:24:05.109452 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11117 23:24:05.109538
11118 23:24:05.129627 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11119 23:24:05.129711
11120 23:24:05.168419 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11121 23:24:05.168508
11122 23:24:05.189725 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11123 23:24:05.189810
11124 23:24:05.226743 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11125 23:24:05.226832
11126 23:24:05.245598 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11127 23:24:05.245705
11128 23:24:05.315131 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11129 23:24:05.315287
11130 23:24:05.340383 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11131 23:24:05.340486
11132 23:24:05.391878 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11133 23:24:05.391979
11134 23:24:05.428140 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11135 23:24:05.428230
11136 23:24:05.508856
11137 23:24:05.508966
11138 23:24:05.512321 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11139 23:24:05.512403
11140 23:24:05.515479 debian-bookworm-arm64 login: root (automatic login)
11141 23:24:05.515586
11142 23:24:05.515677
11143 23:24:05.835538 Linux debian-bookworm-arm64 6.1.83-cip18 #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024 aarch64
11144 23:24:05.835680
11145 23:24:05.842333 The programs included with the Debian GNU/Linux system are free software;
11146 23:24:05.848456 the exact distribution terms for each program are described in the
11147 23:24:05.851743 individual files in /usr/share/doc/*/copyright.
11148 23:24:05.851824
11149 23:24:05.858576 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11150 23:24:05.862051 permitted by applicable law.
11151 23:24:06.934205 Matched prompt #10: / #
11153 23:24:06.934519 Setting prompt string to ['/ #']
11154 23:24:06.934613 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11156 23:24:06.934807 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11157 23:24:06.934892 start: 2.2.6 expect-shell-connection (timeout 00:03:15) [common]
11158 23:24:06.934963 Setting prompt string to ['/ #']
11159 23:24:06.935024 Forcing a shell prompt, looking for ['/ #']
11161 23:24:06.985214 / #
11162 23:24:06.985327 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11163 23:24:06.985431 Waiting using forced prompt support (timeout 00:02:30)
11164 23:24:06.989721
11165 23:24:06.989990 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11166 23:24:06.990083 start: 2.2.7 export-device-env (timeout 00:03:15) [common]
11168 23:24:07.090518 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248458/extract-nfsrootfs-bhvk718l'
11169 23:24:07.095402 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248458/extract-nfsrootfs-bhvk718l'
11171 23:24:07.195900 / # export NFS_SERVER_IP='192.168.201.1'
11172 23:24:07.200619 export NFS_SERVER_IP='192.168.201.1'
11173 23:24:07.200904 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11174 23:24:07.201002 end: 2.2 depthcharge-retry (duration 00:01:45) [common]
11175 23:24:07.201091 end: 2 depthcharge-action (duration 00:01:45) [common]
11176 23:24:07.201185 start: 3 lava-test-retry (timeout 00:07:29) [common]
11177 23:24:07.201272 start: 3.1 lava-test-shell (timeout 00:07:29) [common]
11178 23:24:07.201347 Using namespace: common
11180 23:24:07.301627 / # #
11181 23:24:07.301779 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11182 23:24:07.306923 #
11183 23:24:07.307190 Using /lava-13248458
11185 23:24:07.407472 / # export SHELL=/bin/bash
11186 23:24:07.412493 export SHELL=/bin/bash
11188 23:24:07.512988 / # . /lava-13248458/environment
11189 23:24:07.518015 . /lava-13248458/environment
11191 23:24:07.624701 / # /lava-13248458/bin/lava-test-runner /lava-13248458/0
11192 23:24:07.624843 Test shell timeout: 10s (minimum of the action and connection timeout)
11193 23:24:07.629717 /lava-13248458/bin/lava-test-runner /lava-13248458/0
11194 23:24:07.898572 + export TESTRUN_ID=0_timesync-off
11195 23:24:07.901666 + TESTRUN_ID=0_timesync-off
11196 23:24:07.905282 + cd /lava-13248458/0/tests/0_timesync-off
11197 23:24:07.908201 ++ cat uuid
11198 23:24:07.913408 + UUID=13248458_1.6.2.3.1
11199 23:24:07.913531 + set +x
11200 23:24:07.920143 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13248458_1.6.2.3.1>
11201 23:24:07.920432 Received signal: <STARTRUN> 0_timesync-off 13248458_1.6.2.3.1
11202 23:24:07.920531 Starting test lava.0_timesync-off (13248458_1.6.2.3.1)
11203 23:24:07.920652 Skipping test definition patterns.
11204 23:24:07.923266 + systemctl stop systemd-timesyncd
11205 23:24:07.993080 + set +x
11206 23:24:07.996077 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13248458_1.6.2.3.1>
11207 23:24:07.996382 Received signal: <ENDRUN> 0_timesync-off 13248458_1.6.2.3.1
11208 23:24:07.996512 Ending use of test pattern.
11209 23:24:07.996620 Ending test lava.0_timesync-off (13248458_1.6.2.3.1), duration 0.08
11211 23:24:08.072904 + export TESTRUN_ID=1_kselftest-dt
11212 23:24:08.076356 + TESTRUN_ID=1_kselftest-dt
11213 23:24:08.079006 + cd /lava-13248458/0/tests/1_kselftest-dt
11214 23:24:08.082579 ++ cat uuid
11215 23:24:08.086923 + UUID=13248458_1.6.2.3.5
11216 23:24:08.087072 + set +x
11217 23:24:08.093823 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 13248458_1.6.2.3.5>
11218 23:24:08.094129 Received signal: <STARTRUN> 1_kselftest-dt 13248458_1.6.2.3.5
11219 23:24:08.094246 Starting test lava.1_kselftest-dt (13248458_1.6.2.3.5)
11220 23:24:08.094384 Skipping test definition patterns.
11221 23:24:08.096985 + cd ./automated/linux/kselftest/
11222 23:24:08.119910 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11223 23:24:08.164642 INFO: install_deps skipped
11224 23:24:08.666280 --2024-04-03 23:24:08-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11225 23:24:08.672770 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11226 23:24:08.794858 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11227 23:24:08.919272 HTTP request sent, awaiting response... 200 OK
11228 23:24:08.922863 Length: 1651420 (1.6M) [application/octet-stream]
11229 23:24:08.925826 Saving to: 'kselftest_armhf.tar.gz'
11230 23:24:08.925933
11231 23:24:08.926026
11232 23:24:09.168802 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11233 23:24:09.429494 kselftest_armhf.tar 2%[ ] 47.81K 193KB/s
11234 23:24:09.668008 kselftest_armhf.tar 9%[> ] 159.52K 314KB/s
11235 23:24:09.917980 kselftest_armhf.tar 27%[====> ] 438.09K 587KB/s
11236 23:24:10.166871 kselftest_armhf.tar 42%[=======> ] 691.21K 694KB/s
11237 23:24:10.416021 kselftest_armhf.tar 59%[==========> ] 957.05K 769KB/s
11238 23:24:10.665834 kselftest_armhf.tar 76%[==============> ] 1.21M 829KB/s
11239 23:24:10.672338 kselftest_armhf.tar 94%[=================> ] 1.49M 877KB/s
11240 23:24:10.678504 kselftest_armhf.tar 100%[===================>] 1.57M 922KB/s in 1.7s
11241 23:24:10.678586
11242 23:24:10.824945 2024-04-03 23:24:10 (922 KB/s) - 'kselftest_armhf.tar.gz' saved [1651420/1651420]
11243 23:24:10.825109
11244 23:24:15.160244 skiplist:
11245 23:24:15.163266 ========================================
11246 23:24:15.166712 ========================================
11247 23:24:15.234385 ============== Tests to run ===============
11248 23:24:15.237411 ===========End Tests to run ===============
11249 23:24:15.242919 shardfile-dt fail
11250 23:24:15.264856 ./kselftest.sh: 131: cannot open /lava-13248458/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11251 23:24:15.267870 + ../../utils/send-to-lava.sh ./output/result.txt
11252 23:24:15.336632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11253 23:24:15.336741 + set +x
11254 23:24:15.336989 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11256 23:24:15.343161 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 13248458_1.6.2.3.5>
11257 23:24:15.343386 Received signal: <ENDRUN> 1_kselftest-dt 13248458_1.6.2.3.5
11258 23:24:15.343462 Ending use of test pattern.
11259 23:24:15.343523 Ending test lava.1_kselftest-dt (13248458_1.6.2.3.5), duration 7.25
11261 23:24:15.343738 ok: lava_test_shell seems to have completed
11262 23:24:15.343827 shardfile-dt: fail
11263 23:24:15.343912 end: 3.1 lava-test-shell (duration 00:00:08) [common]
11264 23:24:15.343995 end: 3 lava-test-retry (duration 00:00:08) [common]
11265 23:24:15.344099 start: 4 finalize (timeout 00:07:21) [common]
11266 23:24:15.344189 start: 4.1 power-off (timeout 00:00:30) [common]
11267 23:24:15.344337 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11268 23:24:15.420729 >> Command sent successfully.
11269 23:24:15.424224 Returned 0 in 0 seconds
11270 23:24:15.524606 end: 4.1 power-off (duration 00:00:00) [common]
11272 23:24:15.524919 start: 4.2 read-feedback (timeout 00:07:21) [common]
11274 23:24:15.525601 Listened to connection for namespace 'common' for up to 1s
11275 23:24:16.526161 Finalising connection for namespace 'common'
11276 23:24:16.526340 Disconnecting from shell: Finalise
11277 23:24:16.526417 / #
11278 23:24:16.626765 end: 4.2 read-feedback (duration 00:00:01) [common]
11279 23:24:16.626924 end: 4 finalize (duration 00:00:01) [common]
11280 23:24:16.627037 Cleaning after the job
11281 23:24:16.627133 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/ramdisk
11282 23:24:16.629773 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/kernel
11283 23:24:16.642700 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/dtb
11284 23:24:16.642912 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/nfsrootfs
11285 23:24:16.720763 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248458/tftp-deploy-z0knm9t8/modules
11286 23:24:16.727848 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248458
11287 23:24:17.402062 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248458
11288 23:24:17.402311 Job finished correctly