Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
1 23:22:04.025734 lava-dispatcher, installed at version: 2024.01
2 23:22:04.025947 start: 0 validate
3 23:22:04.026078 Start time: 2024-04-03 23:22:04.026070+00:00 (UTC)
4 23:22:04.026201 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:22:04.026328 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:22:04.299266 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:22:04.299949 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:22:04.553446 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:22:04.553690 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:22:04.812789 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:22:04.813507 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:22:05.065762 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:22:05.066509 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:22:05.322113 validate duration: 1.30
16 23:22:05.322772 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:22:05.323082 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:22:05.323335 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:22:05.323687 Not decompressing ramdisk as can be used compressed.
20 23:22:05.323936 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:22:05.324126 saving as /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/ramdisk/initrd.cpio.gz
22 23:22:05.324331 total size: 5628169 (5 MB)
23 23:22:05.327224 progress 0 % (0 MB)
24 23:22:05.332076 progress 5 % (0 MB)
25 23:22:05.336751 progress 10 % (0 MB)
26 23:22:05.340938 progress 15 % (0 MB)
27 23:22:05.342970 progress 20 % (1 MB)
28 23:22:05.344438 progress 25 % (1 MB)
29 23:22:05.346010 progress 30 % (1 MB)
30 23:22:05.347606 progress 35 % (1 MB)
31 23:22:05.349064 progress 40 % (2 MB)
32 23:22:05.350661 progress 45 % (2 MB)
33 23:22:05.352111 progress 50 % (2 MB)
34 23:22:05.353666 progress 55 % (2 MB)
35 23:22:05.355232 progress 60 % (3 MB)
36 23:22:05.356666 progress 65 % (3 MB)
37 23:22:05.358241 progress 70 % (3 MB)
38 23:22:05.359627 progress 75 % (4 MB)
39 23:22:05.361253 progress 80 % (4 MB)
40 23:22:05.362784 progress 85 % (4 MB)
41 23:22:05.364397 progress 90 % (4 MB)
42 23:22:05.365953 progress 95 % (5 MB)
43 23:22:05.367381 progress 100 % (5 MB)
44 23:22:05.367591 5 MB downloaded in 0.04 s (124.05 MB/s)
45 23:22:05.367786 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:22:05.368037 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:22:05.368126 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:22:05.368211 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:22:05.368348 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:22:05.368418 saving as /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/kernel/Image
52 23:22:05.368482 total size: 54286848 (51 MB)
53 23:22:05.368544 No compression specified
54 23:22:05.369637 progress 0 % (0 MB)
55 23:22:05.383638 progress 5 % (2 MB)
56 23:22:05.397842 progress 10 % (5 MB)
57 23:22:05.412087 progress 15 % (7 MB)
58 23:22:05.426363 progress 20 % (10 MB)
59 23:22:05.440558 progress 25 % (12 MB)
60 23:22:05.454763 progress 30 % (15 MB)
61 23:22:05.469007 progress 35 % (18 MB)
62 23:22:05.483557 progress 40 % (20 MB)
63 23:22:05.497919 progress 45 % (23 MB)
64 23:22:05.512308 progress 50 % (25 MB)
65 23:22:05.526923 progress 55 % (28 MB)
66 23:22:05.541507 progress 60 % (31 MB)
67 23:22:05.555554 progress 65 % (33 MB)
68 23:22:05.570131 progress 70 % (36 MB)
69 23:22:05.584459 progress 75 % (38 MB)
70 23:22:05.598863 progress 80 % (41 MB)
71 23:22:05.613303 progress 85 % (44 MB)
72 23:22:05.627908 progress 90 % (46 MB)
73 23:22:05.641901 progress 95 % (49 MB)
74 23:22:05.656105 progress 100 % (51 MB)
75 23:22:05.656348 51 MB downloaded in 0.29 s (179.85 MB/s)
76 23:22:05.656504 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:22:05.656745 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:22:05.656833 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:22:05.656922 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:22:05.657062 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:22:05.657131 saving as /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/dtb/mt8192-asurada-spherion-r0.dtb
83 23:22:05.657232 total size: 47230 (0 MB)
84 23:22:05.657294 No compression specified
85 23:22:05.658445 progress 69 % (0 MB)
86 23:22:05.658752 progress 100 % (0 MB)
87 23:22:05.658939 0 MB downloaded in 0.00 s (26.43 MB/s)
88 23:22:05.659100 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:22:05.659353 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:22:05.659439 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:22:05.659539 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:22:05.659659 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:22:05.659756 saving as /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/nfsrootfs/full.rootfs.tar
95 23:22:05.659819 total size: 120894716 (115 MB)
96 23:22:05.659882 Using unxz to decompress xz
97 23:22:05.664083 progress 0 % (0 MB)
98 23:22:06.035098 progress 5 % (5 MB)
99 23:22:06.423478 progress 10 % (11 MB)
100 23:22:06.796205 progress 15 % (17 MB)
101 23:22:07.133988 progress 20 % (23 MB)
102 23:22:07.425773 progress 25 % (28 MB)
103 23:22:07.786018 progress 30 % (34 MB)
104 23:22:08.130451 progress 35 % (40 MB)
105 23:22:08.296842 progress 40 % (46 MB)
106 23:22:08.473957 progress 45 % (51 MB)
107 23:22:08.783233 progress 50 % (57 MB)
108 23:22:09.187501 progress 55 % (63 MB)
109 23:22:09.566460 progress 60 % (69 MB)
110 23:22:09.938837 progress 65 % (74 MB)
111 23:22:10.319961 progress 70 % (80 MB)
112 23:22:10.830652 progress 75 % (86 MB)
113 23:22:11.180693 progress 80 % (92 MB)
114 23:22:11.527277 progress 85 % (98 MB)
115 23:22:11.886116 progress 90 % (103 MB)
116 23:22:12.217734 progress 95 % (109 MB)
117 23:22:12.579409 progress 100 % (115 MB)
118 23:22:12.584861 115 MB downloaded in 6.93 s (16.65 MB/s)
119 23:22:12.585133 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:22:12.585407 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:22:12.585500 start: 1.5 download-retry (timeout 00:09:53) [common]
123 23:22:12.585590 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 23:22:12.585743 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:22:12.585812 saving as /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/modules/modules.tar
126 23:22:12.585875 total size: 8629908 (8 MB)
127 23:22:12.585940 Using unxz to decompress xz
128 23:22:12.590189 progress 0 % (0 MB)
129 23:22:12.609295 progress 5 % (0 MB)
130 23:22:12.634081 progress 10 % (0 MB)
131 23:22:12.657902 progress 15 % (1 MB)
132 23:22:12.682791 progress 20 % (1 MB)
133 23:22:12.708995 progress 25 % (2 MB)
134 23:22:12.736625 progress 30 % (2 MB)
135 23:22:12.762945 progress 35 % (2 MB)
136 23:22:12.790105 progress 40 % (3 MB)
137 23:22:12.815337 progress 45 % (3 MB)
138 23:22:12.841914 progress 50 % (4 MB)
139 23:22:12.867875 progress 55 % (4 MB)
140 23:22:12.897834 progress 60 % (4 MB)
141 23:22:12.924572 progress 65 % (5 MB)
142 23:22:12.949728 progress 70 % (5 MB)
143 23:22:12.974184 progress 75 % (6 MB)
144 23:22:13.001029 progress 80 % (6 MB)
145 23:22:13.028454 progress 85 % (7 MB)
146 23:22:13.058536 progress 90 % (7 MB)
147 23:22:13.090040 progress 95 % (7 MB)
148 23:22:13.118205 progress 100 % (8 MB)
149 23:22:13.123707 8 MB downloaded in 0.54 s (15.30 MB/s)
150 23:22:13.123963 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:22:13.124238 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:22:13.124334 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 23:22:13.124433 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 23:22:16.878256 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13248465/extract-nfsrootfs-am49340a
156 23:22:16.878466 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:22:16.878566 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:22:16.878740 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f
159 23:22:16.878872 makedir: /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin
160 23:22:16.878978 makedir: /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/tests
161 23:22:16.879078 makedir: /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/results
162 23:22:16.879180 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-add-keys
163 23:22:16.879328 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-add-sources
164 23:22:16.879490 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-background-process-start
165 23:22:16.879619 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-background-process-stop
166 23:22:16.879966 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-common-functions
167 23:22:16.880098 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-echo-ipv4
168 23:22:16.880227 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-install-packages
169 23:22:16.880354 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-installed-packages
170 23:22:16.880486 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-os-build
171 23:22:16.880613 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-probe-channel
172 23:22:16.880739 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-probe-ip
173 23:22:16.880865 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-target-ip
174 23:22:16.880990 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-target-mac
175 23:22:16.881114 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-target-storage
176 23:22:16.881239 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-test-case
177 23:22:16.881366 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-test-event
178 23:22:16.881491 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-test-feedback
179 23:22:16.881615 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-test-raise
180 23:22:16.881741 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-test-reference
181 23:22:16.881867 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-test-runner
182 23:22:16.881993 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-test-set
183 23:22:16.882118 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-test-shell
184 23:22:16.882246 Updating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-add-keys (debian)
185 23:22:16.882398 Updating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-add-sources (debian)
186 23:22:16.882550 Updating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-install-packages (debian)
187 23:22:16.882696 Updating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-installed-packages (debian)
188 23:22:16.882839 Updating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/bin/lava-os-build (debian)
189 23:22:16.882965 Creating /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/environment
190 23:22:16.883065 LAVA metadata
191 23:22:16.883136 - LAVA_JOB_ID=13248465
192 23:22:16.883199 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:22:16.883300 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:22:16.883366 skipped lava-vland-overlay
195 23:22:16.883440 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:22:16.883518 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:22:16.883578 skipped lava-multinode-overlay
198 23:22:16.883651 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:22:16.883766 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:22:16.883838 Loading test definitions
201 23:22:16.883926 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:22:16.883997 Using /lava-13248465 at stage 0
203 23:22:16.884281 uuid=13248465_1.6.2.3.1 testdef=None
204 23:22:16.884369 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:22:16.884452 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:22:16.884916 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:22:16.885133 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:22:16.885695 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:22:16.885921 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:22:16.886507 runner path: /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/0/tests/0_timesync-off test_uuid 13248465_1.6.2.3.1
213 23:22:16.886720 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:22:16.886947 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:22:16.887019 Using /lava-13248465 at stage 0
217 23:22:16.887114 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:22:16.887200 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/0/tests/1_kselftest-rtc'
219 23:22:24.386611 Running '/usr/bin/git checkout kernelci.org
220 23:22:24.536488 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 23:22:24.537771 uuid=13248465_1.6.2.3.5 testdef=None
222 23:22:24.538001 end: 1.6.2.3.5 git-repo-action (duration 00:00:08) [common]
224 23:22:24.538555 start: 1.6.2.3.6 test-overlay (timeout 00:09:41) [common]
225 23:22:24.539902 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:22:24.540267 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:41) [common]
228 23:22:24.541661 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:22:24.541900 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:41) [common]
231 23:22:24.543210 runner path: /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/0/tests/1_kselftest-rtc test_uuid 13248465_1.6.2.3.5
232 23:22:24.543330 BOARD='mt8192-asurada-spherion-r0'
233 23:22:24.543424 BRANCH='cip'
234 23:22:24.543527 SKIPFILE='/dev/null'
235 23:22:24.543617 SKIP_INSTALL='True'
236 23:22:24.543728 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:22:24.543799 TST_CASENAME=''
238 23:22:24.543857 TST_CMDFILES='rtc'
239 23:22:24.544002 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:22:24.544214 Creating lava-test-runner.conf files
242 23:22:24.544281 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248465/lava-overlay-91n0ac9f/lava-13248465/0 for stage 0
243 23:22:24.544376 - 0_timesync-off
244 23:22:24.544446 - 1_kselftest-rtc
245 23:22:24.544544 end: 1.6.2.3 test-definition (duration 00:00:08) [common]
246 23:22:24.544634 start: 1.6.2.4 compress-overlay (timeout 00:09:41) [common]
247 23:22:32.228808 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:22:32.228970 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 23:22:32.229070 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:22:32.229168 end: 1.6.2 lava-overlay (duration 00:00:15) [common]
251 23:22:32.229259 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 23:22:32.407678 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:22:32.408081 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
254 23:22:32.408197 extracting modules file /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248465/extract-nfsrootfs-am49340a
255 23:22:32.648238 extracting modules file /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248465/extract-overlay-ramdisk-0ul9m2y4/ramdisk
256 23:22:32.884370 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:22:32.884561 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
258 23:22:32.884689 [common] Applying overlay to NFS
259 23:22:32.884792 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248465/compress-overlay-6buv1s6j/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248465/extract-nfsrootfs-am49340a
260 23:22:33.851352 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:22:33.851581 start: 1.6.6 configure-preseed-file (timeout 00:09:31) [common]
262 23:22:33.851811 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:22:33.851941 start: 1.6.7 compress-ramdisk (timeout 00:09:31) [common]
264 23:22:33.852051 Building ramdisk /var/lib/lava/dispatcher/tmp/13248465/extract-overlay-ramdisk-0ul9m2y4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248465/extract-overlay-ramdisk-0ul9m2y4/ramdisk
265 23:22:34.201958 >> 130593 blocks
266 23:22:36.411632 rename /var/lib/lava/dispatcher/tmp/13248465/extract-overlay-ramdisk-0ul9m2y4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/ramdisk/ramdisk.cpio.gz
267 23:22:36.412157 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 23:22:36.412296 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 23:22:36.412402 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 23:22:36.412507 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/kernel/Image'
271 23:22:50.436195 Returned 0 in 14 seconds
272 23:22:50.536864 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/kernel/image.itb
273 23:22:50.913774 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:22:50.914166 output: Created: Thu Apr 4 00:22:50 2024
275 23:22:50.914246 output: Image 0 (kernel-1)
276 23:22:50.914315 output: Description:
277 23:22:50.914380 output: Created: Thu Apr 4 00:22:50 2024
278 23:22:50.914445 output: Type: Kernel Image
279 23:22:50.914510 output: Compression: lzma compressed
280 23:22:50.914569 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
281 23:22:50.914628 output: Architecture: AArch64
282 23:22:50.914684 output: OS: Linux
283 23:22:50.914741 output: Load Address: 0x00000000
284 23:22:50.914801 output: Entry Point: 0x00000000
285 23:22:50.914859 output: Hash algo: crc32
286 23:22:50.914915 output: Hash value: d7c9dcc1
287 23:22:50.914970 output: Image 1 (fdt-1)
288 23:22:50.915024 output: Description: mt8192-asurada-spherion-r0
289 23:22:50.915079 output: Created: Thu Apr 4 00:22:50 2024
290 23:22:50.915134 output: Type: Flat Device Tree
291 23:22:50.915188 output: Compression: uncompressed
292 23:22:50.915243 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 23:22:50.915297 output: Architecture: AArch64
294 23:22:50.915351 output: Hash algo: crc32
295 23:22:50.915405 output: Hash value: 4bf0d1ac
296 23:22:50.915459 output: Image 2 (ramdisk-1)
297 23:22:50.915513 output: Description: unavailable
298 23:22:50.915567 output: Created: Thu Apr 4 00:22:50 2024
299 23:22:50.915621 output: Type: RAMDisk Image
300 23:22:50.915700 output: Compression: Unknown Compression
301 23:22:50.915771 output: Data Size: 18773769 Bytes = 18333.76 KiB = 17.90 MiB
302 23:22:50.915826 output: Architecture: AArch64
303 23:22:50.915880 output: OS: Linux
304 23:22:50.915934 output: Load Address: unavailable
305 23:22:50.915988 output: Entry Point: unavailable
306 23:22:50.916041 output: Hash algo: crc32
307 23:22:50.916095 output: Hash value: 4c479bd9
308 23:22:50.916150 output: Default Configuration: 'conf-1'
309 23:22:50.916204 output: Configuration 0 (conf-1)
310 23:22:50.916257 output: Description: mt8192-asurada-spherion-r0
311 23:22:50.916311 output: Kernel: kernel-1
312 23:22:50.916365 output: Init Ramdisk: ramdisk-1
313 23:22:50.916419 output: FDT: fdt-1
314 23:22:50.916472 output: Loadables: kernel-1
315 23:22:50.916526 output:
316 23:22:50.916737 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 23:22:50.916834 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 23:22:50.916941 end: 1.6 prepare-tftp-overlay (duration 00:00:38) [common]
319 23:22:50.917043 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
320 23:22:50.917128 No LXC device requested
321 23:22:50.917208 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:22:50.917298 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
323 23:22:50.917379 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:22:50.917451 Checking files for TFTP limit of 4294967296 bytes.
325 23:22:50.917960 end: 1 tftp-deploy (duration 00:00:46) [common]
326 23:22:50.918069 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:22:50.918164 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:22:50.918297 substitutions:
329 23:22:50.918369 - {DTB}: 13248465/tftp-deploy-_sc5ov9o/dtb/mt8192-asurada-spherion-r0.dtb
330 23:22:50.918436 - {INITRD}: 13248465/tftp-deploy-_sc5ov9o/ramdisk/ramdisk.cpio.gz
331 23:22:50.918496 - {KERNEL}: 13248465/tftp-deploy-_sc5ov9o/kernel/Image
332 23:22:50.918555 - {LAVA_MAC}: None
333 23:22:50.918612 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13248465/extract-nfsrootfs-am49340a
334 23:22:50.918669 - {NFS_SERVER_IP}: 192.168.201.1
335 23:22:50.918725 - {PRESEED_CONFIG}: None
336 23:22:50.918781 - {PRESEED_LOCAL}: None
337 23:22:50.918837 - {RAMDISK}: 13248465/tftp-deploy-_sc5ov9o/ramdisk/ramdisk.cpio.gz
338 23:22:50.918893 - {ROOT_PART}: None
339 23:22:50.918951 - {ROOT}: None
340 23:22:50.919007 - {SERVER_IP}: 192.168.201.1
341 23:22:50.919063 - {TEE}: None
342 23:22:50.919118 Parsed boot commands:
343 23:22:50.919173 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:22:50.919363 Parsed boot commands: tftpboot 192.168.201.1 13248465/tftp-deploy-_sc5ov9o/kernel/image.itb 13248465/tftp-deploy-_sc5ov9o/kernel/cmdline
345 23:22:50.919453 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:22:50.919542 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:22:50.919635 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:22:50.919764 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:22:50.919841 Not connected, no need to disconnect.
350 23:22:50.919917 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:22:50.919997 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:22:50.920067 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 23:22:50.924442 Setting prompt string to ['lava-test: # ']
354 23:22:50.924817 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:22:50.924928 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:22:50.925030 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:22:50.925156 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:22:50.925466 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 23:22:56.061778 >> Command sent successfully.
360 23:22:56.064502 Returned 0 in 5 seconds
361 23:22:56.164976 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:22:56.165511 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:22:56.165692 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:22:56.165857 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:22:56.165983 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:22:56.166141 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:22:56.166671 [Enter `^Ec?' for help]
369 23:22:56.338672
370 23:22:56.338986
371 23:22:56.339199 F0: 102B 0000
372 23:22:56.339401
373 23:22:56.339588 F3: 1001 0000 [0200]
374 23:22:56.339800
375 23:22:56.342342 F3: 1001 0000
376 23:22:56.342592
377 23:22:56.342791 F7: 102D 0000
378 23:22:56.342979
379 23:22:56.345477 F1: 0000 0000
380 23:22:56.345695
381 23:22:56.345881 V0: 0000 0000 [0001]
382 23:22:56.346060
383 23:22:56.348763 00: 0007 8000
384 23:22:56.349024
385 23:22:56.349224 01: 0000 0000
386 23:22:56.349414
387 23:22:56.352165 BP: 0C00 0209 [0000]
388 23:22:56.352417
389 23:22:56.352616 G0: 1182 0000
390 23:22:56.352801
391 23:22:56.356190 EC: 0000 0021 [4000]
392 23:22:56.356446
393 23:22:56.356645 S7: 0000 0000 [0000]
394 23:22:56.356831
395 23:22:56.359002 CC: 0000 0000 [0001]
396 23:22:56.359347
397 23:22:56.359629 T0: 0000 0040 [010F]
398 23:22:56.359944
399 23:22:56.360211 Jump to BL
400 23:22:56.360471
401 23:22:56.385704
402 23:22:56.386163
403 23:22:56.386633
404 23:22:56.392799 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:22:56.396732 ARM64: Exception handlers installed.
406 23:22:56.399786 ARM64: Testing exception
407 23:22:56.403018 ARM64: Done test exception
408 23:22:56.409382 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:22:56.419458 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:22:56.426638 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:22:56.436786 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:22:56.443429 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:22:56.453414 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:22:56.463530 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:22:56.470314 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:22:56.488560 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:22:56.492146 WDT: Last reset was cold boot
418 23:22:56.495596 SPI1(PAD0) initialized at 2873684 Hz
419 23:22:56.498820 SPI5(PAD0) initialized at 992727 Hz
420 23:22:56.501712 VBOOT: Loading verstage.
421 23:22:56.508500 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:22:56.512510 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:22:56.515343 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:22:56.518837 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:22:56.526272 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:22:56.532611 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:22:56.543855 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 23:22:56.544225
429 23:22:56.544590
430 23:22:56.553486 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:22:56.558270 ARM64: Exception handlers installed.
432 23:22:56.558934 ARM64: Testing exception
433 23:22:56.561465 ARM64: Done test exception
434 23:22:56.564991 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:22:56.571325 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:22:56.585201 Probing TPM: . done!
437 23:22:56.585638 TPM ready after 0 ms
438 23:22:56.589746 Connected to device vid:did:rid of 1ae0:0028:00
439 23:22:56.600893 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 23:22:56.655022 Initialized TPM device CR50 revision 0
441 23:22:56.666231 tlcl_send_startup: Startup return code is 0
442 23:22:56.666339 TPM: setup succeeded
443 23:22:56.678327 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:22:56.686138 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:22:56.698001 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:22:56.708484 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:22:56.711948 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:22:56.718520 in-header: 03 07 00 00 08 00 00 00
449 23:22:56.721453 in-data: aa e4 47 04 13 02 00 00
450 23:22:56.724903 Chrome EC: UHEPI supported
451 23:22:56.731752 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:22:56.734945 in-header: 03 ad 00 00 08 00 00 00
453 23:22:56.738622 in-data: 00 20 20 08 00 00 00 00
454 23:22:56.738743 Phase 1
455 23:22:56.742453 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:22:56.749865 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:22:56.753737 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:22:56.757209 Recovery requested (1009000e)
459 23:22:56.767292 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:22:56.773199 tlcl_extend: response is 0
461 23:22:56.783431 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:22:56.789439 tlcl_extend: response is 0
463 23:22:56.796082 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:22:56.816400 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 23:22:56.823170 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:22:56.823286
467 23:22:56.823381
468 23:22:56.833856 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:22:56.837465 ARM64: Exception handlers installed.
470 23:22:56.837544 ARM64: Testing exception
471 23:22:56.840948 ARM64: Done test exception
472 23:22:56.862237 pmic_efuse_setting: Set efuses in 11 msecs
473 23:22:56.865486 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:22:56.871858 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:22:56.875483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:22:56.879011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:22:56.886102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:22:56.889509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:22:56.897019 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:22:56.900584 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:22:56.904481 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:22:56.908011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:22:56.915835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:22:56.919053 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:22:56.922846 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:22:56.926331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:22:56.934393 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:22:56.941746 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:22:56.945344 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:22:56.952781 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:22:56.956472 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:22:56.963581 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:22:56.967445 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:22:56.975416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:22:56.978552 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:22:56.986009 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:22:56.990113 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:22:56.997013 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:22:57.000816 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:22:57.008315 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:22:57.011788 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:22:57.014980 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:22:57.022080 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:22:57.026018 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:22:57.029610 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:22:57.036931 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:22:57.040468 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:22:57.044038 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:22:57.051456 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:22:57.054692 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:22:57.062511 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:22:57.065854 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:22:57.069511 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:22:57.073289 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:22:57.076661 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:22:57.084108 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:22:57.087721 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:22:57.091565 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:22:57.095425 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:22:57.098793 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:22:57.106228 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:22:57.109537 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:22:57.113072 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:22:57.117076 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:22:57.124249 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:22:57.131843 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:22:57.139055 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:22:57.146231 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:22:57.153479 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:22:57.160471 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:22:57.164183 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:22:57.167830 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:22:57.175015 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
534 23:22:57.178981 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:22:57.186661 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 23:22:57.190533 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:22:57.199262 [RTC]rtc_get_frequency_meter,154: input=15, output=834
538 23:22:57.208334 [RTC]rtc_get_frequency_meter,154: input=7, output=709
539 23:22:57.217931 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 23:22:57.227853 [RTC]rtc_get_frequency_meter,154: input=13, output=802
541 23:22:57.237419 [RTC]rtc_get_frequency_meter,154: input=12, output=786
542 23:22:57.246552 [RTC]rtc_get_frequency_meter,154: input=12, output=787
543 23:22:57.256236 [RTC]rtc_get_frequency_meter,154: input=13, output=802
544 23:22:57.259732 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 23:22:57.267364 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 23:22:57.270847 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:22:57.274890 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 23:22:57.278376 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:22:57.282243 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 23:22:57.286076 ADC[4]: Raw value=904509 ID=7
551 23:22:57.289134 ADC[3]: Raw value=212912 ID=1
552 23:22:57.289238 RAM Code: 0x71
553 23:22:57.292932 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:22:57.300621 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:22:57.307738 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:22:57.315125 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:22:57.318557 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:22:57.322194 in-header: 03 07 00 00 08 00 00 00
559 23:22:57.326065 in-data: aa e4 47 04 13 02 00 00
560 23:22:57.326166 Chrome EC: UHEPI supported
561 23:22:57.333470 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:22:57.336394 in-header: 03 ed 00 00 08 00 00 00
563 23:22:57.340041 in-data: 80 20 60 08 00 00 00 00
564 23:22:57.343655 MRC: failed to locate region type 0.
565 23:22:57.351563 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:22:57.351716 DRAM-K: Running full calibration
567 23:22:57.358438 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:22:57.362274 header.status = 0x0
569 23:22:57.366080 header.version = 0x6 (expected: 0x6)
570 23:22:57.366173 header.size = 0xd00 (expected: 0xd00)
571 23:22:57.370172 header.flags = 0x0
572 23:22:57.377250 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:22:57.393779 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 23:22:57.401187 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:22:57.405330 dram_init: ddr_geometry: 2
576 23:22:57.405414 [EMI] MDL number = 2
577 23:22:57.408840 [EMI] Get MDL freq = 0
578 23:22:57.408946 dram_init: ddr_type: 0
579 23:22:57.412891 is_discrete_lpddr4: 1
580 23:22:57.416582 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:22:57.416683
582 23:22:57.416771
583 23:22:57.416871 [Bian_co] ETT version 0.0.0.1
584 23:22:57.423983 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:22:57.424130
586 23:22:57.427131 dramc_set_vcore_voltage set vcore to 650000
587 23:22:57.427225 Read voltage for 800, 4
588 23:22:57.430948 Vio18 = 0
589 23:22:57.431046 Vcore = 650000
590 23:22:57.431153 Vdram = 0
591 23:22:57.431237 Vddq = 0
592 23:22:57.434632 Vmddr = 0
593 23:22:57.434752 dram_init: config_dvfs: 1
594 23:22:57.441578 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:22:57.445279 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:22:57.448645 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 23:22:57.453065 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 23:22:57.456509 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 23:22:57.460080 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 23:22:57.463894 MEM_TYPE=3, freq_sel=18
601 23:22:57.468099 sv_algorithm_assistance_LP4_1600
602 23:22:57.471492 ============ PULL DRAM RESETB DOWN ============
603 23:22:57.475064 ========== PULL DRAM RESETB DOWN end =========
604 23:22:57.478414 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:22:57.481676 ===================================
606 23:22:57.484814 LPDDR4 DRAM CONFIGURATION
607 23:22:57.487830 ===================================
608 23:22:57.491282 EX_ROW_EN[0] = 0x0
609 23:22:57.491379 EX_ROW_EN[1] = 0x0
610 23:22:57.494526 LP4Y_EN = 0x0
611 23:22:57.494623 WORK_FSP = 0x0
612 23:22:57.498243 WL = 0x2
613 23:22:57.498340 RL = 0x2
614 23:22:57.501207 BL = 0x2
615 23:22:57.501310 RPST = 0x0
616 23:22:57.504543 RD_PRE = 0x0
617 23:22:57.504647 WR_PRE = 0x1
618 23:22:57.508583 WR_PST = 0x0
619 23:22:57.508733 DBI_WR = 0x0
620 23:22:57.511524 DBI_RD = 0x0
621 23:22:57.514491 OTF = 0x1
622 23:22:57.518166 ===================================
623 23:22:57.518348 ===================================
624 23:22:57.521325 ANA top config
625 23:22:57.524458 ===================================
626 23:22:57.527749 DLL_ASYNC_EN = 0
627 23:22:57.527838 ALL_SLAVE_EN = 1
628 23:22:57.531157 NEW_RANK_MODE = 1
629 23:22:57.534432 DLL_IDLE_MODE = 1
630 23:22:57.537557 LP45_APHY_COMB_EN = 1
631 23:22:57.541101 TX_ODT_DIS = 1
632 23:22:57.541206 NEW_8X_MODE = 1
633 23:22:57.544206 ===================================
634 23:22:57.547754 ===================================
635 23:22:57.550797 data_rate = 1600
636 23:22:57.554448 CKR = 1
637 23:22:57.557858 DQ_P2S_RATIO = 8
638 23:22:57.560877 ===================================
639 23:22:57.564728 CA_P2S_RATIO = 8
640 23:22:57.567739 DQ_CA_OPEN = 0
641 23:22:57.567868 DQ_SEMI_OPEN = 0
642 23:22:57.571185 CA_SEMI_OPEN = 0
643 23:22:57.574384 CA_FULL_RATE = 0
644 23:22:57.577427 DQ_CKDIV4_EN = 1
645 23:22:57.580924 CA_CKDIV4_EN = 1
646 23:22:57.583948 CA_PREDIV_EN = 0
647 23:22:57.584112 PH8_DLY = 0
648 23:22:57.587292 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:22:57.590628 DQ_AAMCK_DIV = 4
650 23:22:57.594664 CA_AAMCK_DIV = 4
651 23:22:57.597514 CA_ADMCK_DIV = 4
652 23:22:57.600899 DQ_TRACK_CA_EN = 0
653 23:22:57.601077 CA_PICK = 800
654 23:22:57.603959 CA_MCKIO = 800
655 23:22:57.607200 MCKIO_SEMI = 0
656 23:22:57.611515 PLL_FREQ = 3068
657 23:22:57.614429 DQ_UI_PI_RATIO = 32
658 23:22:57.618215 CA_UI_PI_RATIO = 0
659 23:22:57.618396 ===================================
660 23:22:57.621943 ===================================
661 23:22:57.625508 memory_type:LPDDR4
662 23:22:57.629269 GP_NUM : 10
663 23:22:57.629409 SRAM_EN : 1
664 23:22:57.632830 MD32_EN : 0
665 23:22:57.636448 ===================================
666 23:22:57.636564 [ANA_INIT] >>>>>>>>>>>>>>
667 23:22:57.639960 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:22:57.644068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:22:57.647015 ===================================
670 23:22:57.650909 data_rate = 1600,PCW = 0X7600
671 23:22:57.653880 ===================================
672 23:22:57.657650 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:22:57.660922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:22:57.667295 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:22:57.670850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:22:57.674105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:22:57.676965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:22:57.681146 [ANA_INIT] flow start
679 23:22:57.683806 [ANA_INIT] PLL >>>>>>>>
680 23:22:57.683906 [ANA_INIT] PLL <<<<<<<<
681 23:22:57.687056 [ANA_INIT] MIDPI >>>>>>>>
682 23:22:57.690132 [ANA_INIT] MIDPI <<<<<<<<
683 23:22:57.694002 [ANA_INIT] DLL >>>>>>>>
684 23:22:57.694088 [ANA_INIT] flow end
685 23:22:57.697149 ============ LP4 DIFF to SE enter ============
686 23:22:57.703657 ============ LP4 DIFF to SE exit ============
687 23:22:57.703759 [ANA_INIT] <<<<<<<<<<<<<
688 23:22:57.707333 [Flow] Enable top DCM control >>>>>
689 23:22:57.710157 [Flow] Enable top DCM control <<<<<
690 23:22:57.713401 Enable DLL master slave shuffle
691 23:22:57.720183 ==============================================================
692 23:22:57.720299 Gating Mode config
693 23:22:57.726548 ==============================================================
694 23:22:57.730424 Config description:
695 23:22:57.740011 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:22:57.746422 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:22:57.750022 SELPH_MODE 0: By rank 1: By Phase
698 23:22:57.757129 ==============================================================
699 23:22:57.760405 GAT_TRACK_EN = 1
700 23:22:57.763419 RX_GATING_MODE = 2
701 23:22:57.763532 RX_GATING_TRACK_MODE = 2
702 23:22:57.766685 SELPH_MODE = 1
703 23:22:57.769986 PICG_EARLY_EN = 1
704 23:22:57.773640 VALID_LAT_VALUE = 1
705 23:22:57.779984 ==============================================================
706 23:22:57.782997 Enter into Gating configuration >>>>
707 23:22:57.786297 Exit from Gating configuration <<<<
708 23:22:57.789622 Enter into DVFS_PRE_config >>>>>
709 23:22:57.799590 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:22:57.802729 Exit from DVFS_PRE_config <<<<<
711 23:22:57.806455 Enter into PICG configuration >>>>
712 23:22:57.809338 Exit from PICG configuration <<<<
713 23:22:57.813147 [RX_INPUT] configuration >>>>>
714 23:22:57.816221 [RX_INPUT] configuration <<<<<
715 23:22:57.819533 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:22:57.826319 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:22:57.833581 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:22:57.836955 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:22:57.843431 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:22:57.850191 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:22:57.853380 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:22:57.856828 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:22:57.863458 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:22:57.866711 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:22:57.870650 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:22:57.876989 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:22:57.880445 ===================================
728 23:22:57.880716 LPDDR4 DRAM CONFIGURATION
729 23:22:57.883145 ===================================
730 23:22:57.886696 EX_ROW_EN[0] = 0x0
731 23:22:57.887054 EX_ROW_EN[1] = 0x0
732 23:22:57.889756 LP4Y_EN = 0x0
733 23:22:57.893747 WORK_FSP = 0x0
734 23:22:57.894138 WL = 0x2
735 23:22:57.896658 RL = 0x2
736 23:22:57.897047 BL = 0x2
737 23:22:57.899900 RPST = 0x0
738 23:22:57.900204 RD_PRE = 0x0
739 23:22:57.903563 WR_PRE = 0x1
740 23:22:57.903683 WR_PST = 0x0
741 23:22:57.906247 DBI_WR = 0x0
742 23:22:57.906350 DBI_RD = 0x0
743 23:22:57.909688 OTF = 0x1
744 23:22:57.913009 ===================================
745 23:22:57.916538 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:22:57.920101 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:22:57.926480 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:22:57.929518 ===================================
749 23:22:57.929694 LPDDR4 DRAM CONFIGURATION
750 23:22:57.933032 ===================================
751 23:22:57.936306 EX_ROW_EN[0] = 0x10
752 23:22:57.936415 EX_ROW_EN[1] = 0x0
753 23:22:57.939632 LP4Y_EN = 0x0
754 23:22:57.939782 WORK_FSP = 0x0
755 23:22:57.942568 WL = 0x2
756 23:22:57.946492 RL = 0x2
757 23:22:57.946616 BL = 0x2
758 23:22:57.949478 RPST = 0x0
759 23:22:57.949604 RD_PRE = 0x0
760 23:22:57.952449 WR_PRE = 0x1
761 23:22:57.952557 WR_PST = 0x0
762 23:22:57.956017 DBI_WR = 0x0
763 23:22:57.956178 DBI_RD = 0x0
764 23:22:57.959892 OTF = 0x1
765 23:22:57.963723 ===================================
766 23:22:57.969325 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:22:57.972789 nWR fixed to 40
768 23:22:57.972991 [ModeRegInit_LP4] CH0 RK0
769 23:22:57.976256 [ModeRegInit_LP4] CH0 RK1
770 23:22:57.979510 [ModeRegInit_LP4] CH1 RK0
771 23:22:57.979739 [ModeRegInit_LP4] CH1 RK1
772 23:22:57.982661 match AC timing 13
773 23:22:57.985815 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:22:57.989374 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:22:57.995946 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:22:57.999432 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:22:58.005927 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:22:58.006362 [EMI DOE] emi_dcm 0
779 23:22:58.012689 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:22:58.013197 ==
781 23:22:58.015921 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:22:58.018969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:22:58.019441 ==
784 23:22:58.025962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:22:58.028749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:22:58.039773 [CA 0] Center 37 (7~68) winsize 62
787 23:22:58.042781 [CA 1] Center 37 (6~68) winsize 63
788 23:22:58.046256 [CA 2] Center 34 (4~65) winsize 62
789 23:22:58.049758 [CA 3] Center 34 (4~65) winsize 62
790 23:22:58.052972 [CA 4] Center 33 (3~64) winsize 62
791 23:22:58.055963 [CA 5] Center 33 (3~64) winsize 62
792 23:22:58.056422
793 23:22:58.058908 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 23:22:58.059433
795 23:22:58.062691 [CATrainingPosCal] consider 1 rank data
796 23:22:58.065404 u2DelayCellTimex100 = 270/100 ps
797 23:22:58.069006 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 23:22:58.076002 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 23:22:58.079189 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 23:22:58.081985 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 23:22:58.086143 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 23:22:58.088557 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 23:22:58.088987
804 23:22:58.091897 CA PerBit enable=1, Macro0, CA PI delay=33
805 23:22:58.092350
806 23:22:58.095162 [CBTSetCACLKResult] CA Dly = 33
807 23:22:58.098614 CS Dly: 7 (0~38)
808 23:22:58.099119 ==
809 23:22:58.101969 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:22:58.105005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:22:58.105730 ==
812 23:22:58.111931 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:22:58.115379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:22:58.125641 [CA 0] Center 37 (6~68) winsize 63
815 23:22:58.128990 [CA 1] Center 37 (7~68) winsize 62
816 23:22:58.131892 [CA 2] Center 34 (4~65) winsize 62
817 23:22:58.135446 [CA 3] Center 34 (4~65) winsize 62
818 23:22:58.139159 [CA 4] Center 33 (3~64) winsize 62
819 23:22:58.142333 [CA 5] Center 33 (3~64) winsize 62
820 23:22:58.142913
821 23:22:58.145558 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 23:22:58.146177
823 23:22:58.148762 [CATrainingPosCal] consider 2 rank data
824 23:22:58.152037 u2DelayCellTimex100 = 270/100 ps
825 23:22:58.155404 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 23:22:58.162197 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 23:22:58.165260 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 23:22:58.168532 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 23:22:58.171758 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 23:22:58.175280 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 23:22:58.175881
832 23:22:58.178971 CA PerBit enable=1, Macro0, CA PI delay=33
833 23:22:58.179503
834 23:22:58.182378 [CBTSetCACLKResult] CA Dly = 33
835 23:22:58.185368 CS Dly: 7 (0~38)
836 23:22:58.185944
837 23:22:58.188305 ----->DramcWriteLeveling(PI) begin...
838 23:22:58.188837 ==
839 23:22:58.192206 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:22:58.195301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:22:58.196215 ==
842 23:22:58.198908 Write leveling (Byte 0): 31 => 31
843 23:22:58.202492 Write leveling (Byte 1): 31 => 31
844 23:22:58.203022 DramcWriteLeveling(PI) end<-----
845 23:22:58.206155
846 23:22:58.206960 ==
847 23:22:58.209678 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:22:58.212839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:22:58.213294 ==
850 23:22:58.216757 [Gating] SW mode calibration
851 23:22:58.223299 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:22:58.226436 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:22:58.230334 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:22:58.236612 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 23:22:58.239966 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 23:22:58.243502 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 23:22:58.250025 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:22:58.253556 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:22:58.256680 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:22:58.263496 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:22:58.266724 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:22:58.269777 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:22:58.276291 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:22:58.279531 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:22:58.283280 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:22:58.289077 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:22:58.292957 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:22:58.295634 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:22:58.302875 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:22:58.305638 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 23:22:58.309464 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
872 23:22:58.315575 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
873 23:22:58.319453 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:22:58.322322 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:22:58.329214 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:22:58.332304 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:22:58.336139 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:22:58.342344 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:22:58.345926 0 9 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
880 23:22:58.348900 0 9 12 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
881 23:22:58.356113 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:22:58.358757 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:22:58.362242 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:22:58.368985 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:22:58.372159 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:22:58.375604 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
887 23:22:58.378743 0 10 8 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (0 0)
888 23:22:58.385380 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
889 23:22:58.388468 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:22:58.395026 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:22:58.398839 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:22:58.401862 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:22:58.408124 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:22:58.411580 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
895 23:22:58.415437 0 11 8 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
896 23:22:58.418220 0 11 12 | B1->B0 | 3838 4646 | 1 0 | (1 1) (0 0)
897 23:22:58.425549 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:22:58.428668 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:22:58.431589 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:22:58.438190 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:22:58.441440 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:22:58.445044 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 23:22:58.451448 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 23:22:58.454710 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:22:58.457770 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:22:58.465077 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:22:58.467833 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:22:58.471597 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:22:58.477963 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:22:58.481246 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:22:58.484810 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:22:58.490949 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:22:58.494263 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:22:58.497748 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:22:58.504607 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:22:58.507312 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:22:58.510832 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:22:58.517257 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 23:22:58.521134 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 23:22:58.524454 Total UI for P1: 0, mck2ui 16
921 23:22:58.527607 best dqsien dly found for B0: ( 0, 14, 6)
922 23:22:58.531352 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 23:22:58.534179 Total UI for P1: 0, mck2ui 16
924 23:22:58.537256 best dqsien dly found for B1: ( 0, 14, 8)
925 23:22:58.541258 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 23:22:58.543904 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 23:22:58.543987
928 23:22:58.550678 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 23:22:58.553615 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 23:22:58.557237 [Gating] SW calibration Done
931 23:22:58.557321 ==
932 23:22:58.560434 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:22:58.563610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:22:58.563746 ==
935 23:22:58.563825 RX Vref Scan: 0
936 23:22:58.563889
937 23:22:58.567126 RX Vref 0 -> 0, step: 1
938 23:22:58.567210
939 23:22:58.570210 RX Delay -130 -> 252, step: 16
940 23:22:58.573705 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 23:22:58.577047 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 23:22:58.583892 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 23:22:58.587310 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 23:22:58.589986 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 23:22:58.593199 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 23:22:58.596930 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 23:22:58.603447 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 23:22:58.606534 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 23:22:58.610460 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 23:22:58.613207 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 23:22:58.616461 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 23:22:58.623700 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
953 23:22:58.626635 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 23:22:58.630022 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 23:22:58.633521 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 23:22:58.633598 ==
957 23:22:58.636287 Dram Type= 6, Freq= 0, CH_0, rank 0
958 23:22:58.643178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 23:22:58.643295 ==
960 23:22:58.643393 DQS Delay:
961 23:22:58.646266 DQS0 = 0, DQS1 = 0
962 23:22:58.646339 DQM Delay:
963 23:22:58.649715 DQM0 = 86, DQM1 = 73
964 23:22:58.649806 DQ Delay:
965 23:22:58.652878 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 23:22:58.656079 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
967 23:22:58.659338 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 23:22:58.663118 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
969 23:22:58.663231
970 23:22:58.663324
971 23:22:58.663435 ==
972 23:22:58.666292 Dram Type= 6, Freq= 0, CH_0, rank 0
973 23:22:58.669528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 23:22:58.669617 ==
975 23:22:58.669686
976 23:22:58.669748
977 23:22:58.672973 TX Vref Scan disable
978 23:22:58.676252 == TX Byte 0 ==
979 23:22:58.679444 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 23:22:58.682952 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 23:22:58.686061 == TX Byte 1 ==
982 23:22:58.689273 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
983 23:22:58.693081 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
984 23:22:58.693165 ==
985 23:22:58.696579 Dram Type= 6, Freq= 0, CH_0, rank 0
986 23:22:58.699257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 23:22:58.703056 ==
988 23:22:58.714094 TX Vref=22, minBit 5, minWin=27, winSum=445
989 23:22:58.717015 TX Vref=24, minBit 5, minWin=27, winSum=445
990 23:22:58.720280 TX Vref=26, minBit 5, minWin=27, winSum=445
991 23:22:58.723437 TX Vref=28, minBit 10, minWin=27, winSum=448
992 23:22:58.726996 TX Vref=30, minBit 10, minWin=27, winSum=446
993 23:22:58.733756 TX Vref=32, minBit 4, minWin=27, winSum=441
994 23:22:58.737014 [TxChooseVref] Worse bit 10, Min win 27, Win sum 448, Final Vref 28
995 23:22:58.737093
996 23:22:58.739923 Final TX Range 1 Vref 28
997 23:22:58.739998
998 23:22:58.740062 ==
999 23:22:58.743817 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:22:58.750432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:22:58.750539 ==
1002 23:22:58.750641
1003 23:22:58.750741
1004 23:22:58.750820 TX Vref Scan disable
1005 23:22:58.754144 == TX Byte 0 ==
1006 23:22:58.756832 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 23:22:58.763663 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 23:22:58.763807 == TX Byte 1 ==
1009 23:22:58.767374 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1010 23:22:58.773959 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1011 23:22:58.774043
1012 23:22:58.774123 [DATLAT]
1013 23:22:58.774186 Freq=800, CH0 RK0
1014 23:22:58.774254
1015 23:22:58.776955 DATLAT Default: 0xa
1016 23:22:58.777083 0, 0xFFFF, sum = 0
1017 23:22:58.780498 1, 0xFFFF, sum = 0
1018 23:22:58.784042 2, 0xFFFF, sum = 0
1019 23:22:58.784123 3, 0xFFFF, sum = 0
1020 23:22:58.786923 4, 0xFFFF, sum = 0
1021 23:22:58.787011 5, 0xFFFF, sum = 0
1022 23:22:58.790102 6, 0xFFFF, sum = 0
1023 23:22:58.790191 7, 0xFFFF, sum = 0
1024 23:22:58.793641 8, 0xFFFF, sum = 0
1025 23:22:58.793727 9, 0x0, sum = 1
1026 23:22:58.797007 10, 0x0, sum = 2
1027 23:22:58.797094 11, 0x0, sum = 3
1028 23:22:58.797182 12, 0x0, sum = 4
1029 23:22:58.800465 best_step = 10
1030 23:22:58.800575
1031 23:22:58.800662 ==
1032 23:22:58.803620 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 23:22:58.806723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 23:22:58.806809 ==
1035 23:22:58.810240 RX Vref Scan: 1
1036 23:22:58.810327
1037 23:22:58.813874 Set Vref Range= 32 -> 127
1038 23:22:58.813960
1039 23:22:58.814047 RX Vref 32 -> 127, step: 1
1040 23:22:58.814129
1041 23:22:58.817190 RX Delay -111 -> 252, step: 8
1042 23:22:58.817278
1043 23:22:58.820772 Set Vref, RX VrefLevel [Byte0]: 32
1044 23:22:58.823410 [Byte1]: 32
1045 23:22:58.826933
1046 23:22:58.827018 Set Vref, RX VrefLevel [Byte0]: 33
1047 23:22:58.830364 [Byte1]: 33
1048 23:22:58.834828
1049 23:22:58.834913 Set Vref, RX VrefLevel [Byte0]: 34
1050 23:22:58.837917 [Byte1]: 34
1051 23:22:58.841857
1052 23:22:58.841943 Set Vref, RX VrefLevel [Byte0]: 35
1053 23:22:58.845581 [Byte1]: 35
1054 23:22:58.849905
1055 23:22:58.849987 Set Vref, RX VrefLevel [Byte0]: 36
1056 23:22:58.853432 [Byte1]: 36
1057 23:22:58.857263
1058 23:22:58.857345 Set Vref, RX VrefLevel [Byte0]: 37
1059 23:22:58.860998 [Byte1]: 37
1060 23:22:58.864769
1061 23:22:58.868694 Set Vref, RX VrefLevel [Byte0]: 38
1062 23:22:58.868783 [Byte1]: 38
1063 23:22:58.873019
1064 23:22:58.873101 Set Vref, RX VrefLevel [Byte0]: 39
1065 23:22:58.875984 [Byte1]: 39
1066 23:22:58.880956
1067 23:22:58.881039 Set Vref, RX VrefLevel [Byte0]: 40
1068 23:22:58.883682 [Byte1]: 40
1069 23:22:58.888564
1070 23:22:58.888647 Set Vref, RX VrefLevel [Byte0]: 41
1071 23:22:58.891586 [Byte1]: 41
1072 23:22:58.895143
1073 23:22:58.899061 Set Vref, RX VrefLevel [Byte0]: 42
1074 23:22:58.899144 [Byte1]: 42
1075 23:22:58.903140
1076 23:22:58.903223 Set Vref, RX VrefLevel [Byte0]: 43
1077 23:22:58.906585 [Byte1]: 43
1078 23:22:58.911217
1079 23:22:58.911300 Set Vref, RX VrefLevel [Byte0]: 44
1080 23:22:58.914002 [Byte1]: 44
1081 23:22:58.918106
1082 23:22:58.918210 Set Vref, RX VrefLevel [Byte0]: 45
1083 23:22:58.921759 [Byte1]: 45
1084 23:22:58.925739
1085 23:22:58.925822 Set Vref, RX VrefLevel [Byte0]: 46
1086 23:22:58.929565 [Byte1]: 46
1087 23:22:58.934093
1088 23:22:58.934174 Set Vref, RX VrefLevel [Byte0]: 47
1089 23:22:58.937044 [Byte1]: 47
1090 23:22:58.941878
1091 23:22:58.941981 Set Vref, RX VrefLevel [Byte0]: 48
1092 23:22:58.947551 [Byte1]: 48
1093 23:22:58.947702
1094 23:22:58.950974 Set Vref, RX VrefLevel [Byte0]: 49
1095 23:22:58.954145 [Byte1]: 49
1096 23:22:58.954229
1097 23:22:58.957449 Set Vref, RX VrefLevel [Byte0]: 50
1098 23:22:58.961030 [Byte1]: 50
1099 23:22:58.964426
1100 23:22:58.964515 Set Vref, RX VrefLevel [Byte0]: 51
1101 23:22:58.968039 [Byte1]: 51
1102 23:22:58.971809
1103 23:22:58.971910 Set Vref, RX VrefLevel [Byte0]: 52
1104 23:22:58.975654 [Byte1]: 52
1105 23:22:58.979601
1106 23:22:58.979708 Set Vref, RX VrefLevel [Byte0]: 53
1107 23:22:58.983163 [Byte1]: 53
1108 23:22:58.987561
1109 23:22:58.987708 Set Vref, RX VrefLevel [Byte0]: 54
1110 23:22:58.990707 [Byte1]: 54
1111 23:22:58.995233
1112 23:22:58.995318 Set Vref, RX VrefLevel [Byte0]: 55
1113 23:22:58.998672 [Byte1]: 55
1114 23:22:59.002450
1115 23:22:59.002535 Set Vref, RX VrefLevel [Byte0]: 56
1116 23:22:59.006266 [Byte1]: 56
1117 23:22:59.010035
1118 23:22:59.010121 Set Vref, RX VrefLevel [Byte0]: 57
1119 23:22:59.013611 [Byte1]: 57
1120 23:22:59.018097
1121 23:22:59.018183 Set Vref, RX VrefLevel [Byte0]: 58
1122 23:22:59.021201 [Byte1]: 58
1123 23:22:59.025461
1124 23:22:59.025547 Set Vref, RX VrefLevel [Byte0]: 59
1125 23:22:59.028922 [Byte1]: 59
1126 23:22:59.033083
1127 23:22:59.033169 Set Vref, RX VrefLevel [Byte0]: 60
1128 23:22:59.036418 [Byte1]: 60
1129 23:22:59.040695
1130 23:22:59.040797 Set Vref, RX VrefLevel [Byte0]: 61
1131 23:22:59.044021 [Byte1]: 61
1132 23:22:59.048768
1133 23:22:59.048853 Set Vref, RX VrefLevel [Byte0]: 62
1134 23:22:59.051808 [Byte1]: 62
1135 23:22:59.056733
1136 23:22:59.056823 Set Vref, RX VrefLevel [Byte0]: 63
1137 23:22:59.059279 [Byte1]: 63
1138 23:22:59.063635
1139 23:22:59.063754 Set Vref, RX VrefLevel [Byte0]: 64
1140 23:22:59.066969 [Byte1]: 64
1141 23:22:59.071128
1142 23:22:59.071213 Set Vref, RX VrefLevel [Byte0]: 65
1143 23:22:59.074849 [Byte1]: 65
1144 23:22:59.079161
1145 23:22:59.079271 Set Vref, RX VrefLevel [Byte0]: 66
1146 23:22:59.082070 [Byte1]: 66
1147 23:22:59.086551
1148 23:22:59.086636 Set Vref, RX VrefLevel [Byte0]: 67
1149 23:22:59.089773 [Byte1]: 67
1150 23:22:59.094331
1151 23:22:59.094416 Set Vref, RX VrefLevel [Byte0]: 68
1152 23:22:59.097454 [Byte1]: 68
1153 23:22:59.101776
1154 23:22:59.101861 Set Vref, RX VrefLevel [Byte0]: 69
1155 23:22:59.105348 [Byte1]: 69
1156 23:22:59.109575
1157 23:22:59.109660 Set Vref, RX VrefLevel [Byte0]: 70
1158 23:22:59.113060 [Byte1]: 70
1159 23:22:59.117397
1160 23:22:59.117483 Set Vref, RX VrefLevel [Byte0]: 71
1161 23:22:59.120672 [Byte1]: 71
1162 23:22:59.125127
1163 23:22:59.125212 Set Vref, RX VrefLevel [Byte0]: 72
1164 23:22:59.127888 [Byte1]: 72
1165 23:22:59.132344
1166 23:22:59.132429 Set Vref, RX VrefLevel [Byte0]: 73
1167 23:22:59.135501 [Byte1]: 73
1168 23:22:59.140006
1169 23:22:59.140092 Set Vref, RX VrefLevel [Byte0]: 74
1170 23:22:59.143467 [Byte1]: 74
1171 23:22:59.147928
1172 23:22:59.148017 Set Vref, RX VrefLevel [Byte0]: 75
1173 23:22:59.151141 [Byte1]: 75
1174 23:22:59.155214
1175 23:22:59.155323 Set Vref, RX VrefLevel [Byte0]: 76
1176 23:22:59.158713 [Byte1]: 76
1177 23:22:59.162942
1178 23:22:59.163052 Set Vref, RX VrefLevel [Byte0]: 77
1179 23:22:59.166388 [Byte1]: 77
1180 23:22:59.170731
1181 23:22:59.170817 Set Vref, RX VrefLevel [Byte0]: 78
1182 23:22:59.174310 [Byte1]: 78
1183 23:22:59.178384
1184 23:22:59.178472 Set Vref, RX VrefLevel [Byte0]: 79
1185 23:22:59.181536 [Byte1]: 79
1186 23:22:59.186097
1187 23:22:59.186182 Set Vref, RX VrefLevel [Byte0]: 80
1188 23:22:59.189547 [Byte1]: 80
1189 23:22:59.193577
1190 23:22:59.193662 Set Vref, RX VrefLevel [Byte0]: 81
1191 23:22:59.196848 [Byte1]: 81
1192 23:22:59.201257
1193 23:22:59.201342 Set Vref, RX VrefLevel [Byte0]: 82
1194 23:22:59.204898 [Byte1]: 82
1195 23:22:59.208974
1196 23:22:59.212561 Final RX Vref Byte 0 = 67 to rank0
1197 23:22:59.212648 Final RX Vref Byte 1 = 54 to rank0
1198 23:22:59.215350 Final RX Vref Byte 0 = 67 to rank1
1199 23:22:59.218445 Final RX Vref Byte 1 = 54 to rank1==
1200 23:22:59.222323 Dram Type= 6, Freq= 0, CH_0, rank 0
1201 23:22:59.228529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 23:22:59.228613 ==
1203 23:22:59.228679 DQS Delay:
1204 23:22:59.231821 DQS0 = 0, DQS1 = 0
1205 23:22:59.231903 DQM Delay:
1206 23:22:59.231968 DQM0 = 88, DQM1 = 76
1207 23:22:59.235442 DQ Delay:
1208 23:22:59.238390 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1209 23:22:59.241863 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1210 23:22:59.245109 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1211 23:22:59.248746 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1212 23:22:59.248844
1213 23:22:59.249023
1214 23:22:59.255537 [DQSOSCAuto] RK0, (LSB)MR18= 0x4325, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1215 23:22:59.298835 CH0 RK0: MR19=606, MR18=4325
1216 23:22:59.299614 CH0_RK0: MR19=0x606, MR18=0x4325, DQSOSC=393, MR23=63, INC=95, DEC=63
1217 23:22:59.299744
1218 23:22:59.299848 ----->DramcWriteLeveling(PI) begin...
1219 23:22:59.300094 ==
1220 23:22:59.300159 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 23:22:59.300219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1222 23:22:59.300278 ==
1223 23:22:59.300334 Write leveling (Byte 0): 30 => 30
1224 23:22:59.300912 Write leveling (Byte 1): 30 => 30
1225 23:22:59.301158 DramcWriteLeveling(PI) end<-----
1226 23:22:59.301265
1227 23:22:59.301336 ==
1228 23:22:59.301391 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 23:22:59.301456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 23:22:59.301514 ==
1231 23:22:59.301614 [Gating] SW mode calibration
1232 23:22:59.304973 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1233 23:22:59.308206 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1234 23:22:59.311281 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1235 23:22:59.318052 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1236 23:22:59.321509 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1237 23:22:59.324470 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1238 23:22:59.331331 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:22:59.335068 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:22:59.338015 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:22:59.344417 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:22:59.347770 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:22:59.351276 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:22:59.357588 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:22:59.361210 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:22:59.364527 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:22:59.371494 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 23:22:59.374104 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 23:22:59.378057 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 23:22:59.384474 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 23:22:59.387411 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 23:22:59.391139 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1253 23:22:59.394144 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1254 23:22:59.400853 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 23:22:59.404386 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 23:22:59.408203 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 23:22:59.413973 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 23:22:59.417568 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 23:22:59.421071 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 23:22:59.427488 0 9 8 | B1->B0 | 2323 2b2b | 1 1 | (1 1) (1 1)
1261 23:22:59.431110 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
1262 23:22:59.433675 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 23:22:59.440273 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1264 23:22:59.444180 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1265 23:22:59.447590 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 23:22:59.454819 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 23:22:59.458236 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1268 23:22:59.461783 0 10 8 | B1->B0 | 3030 2828 | 0 0 | (0 1) (1 0)
1269 23:22:59.464727 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1270 23:22:59.472030 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 23:22:59.475515 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1272 23:22:59.478542 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1273 23:22:59.485290 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1274 23:22:59.488462 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 23:22:59.491951 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1276 23:22:59.499197 0 11 8 | B1->B0 | 2d2d 3e3e | 1 0 | (0 0) (0 0)
1277 23:22:59.502022 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1278 23:22:59.505099 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 23:22:59.508420 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 23:22:59.514929 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 23:22:59.518809 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 23:22:59.521566 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 23:22:59.528268 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 23:22:59.531319 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1285 23:22:59.537966 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 23:22:59.541652 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 23:22:59.544538 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 23:22:59.551051 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 23:22:59.554609 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 23:22:59.558027 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 23:22:59.564184 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 23:22:59.567885 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 23:22:59.570954 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 23:22:59.577402 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 23:22:59.581345 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 23:22:59.584058 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 23:22:59.590874 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 23:22:59.594222 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 23:22:59.597308 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1300 23:22:59.600769 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1301 23:22:59.604636 Total UI for P1: 0, mck2ui 16
1302 23:22:59.607513 best dqsien dly found for B0: ( 0, 14, 6)
1303 23:22:59.614195 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1304 23:22:59.617944 Total UI for P1: 0, mck2ui 16
1305 23:22:59.620832 best dqsien dly found for B1: ( 0, 14, 6)
1306 23:22:59.624482 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1307 23:22:59.627639 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1308 23:22:59.627760
1309 23:22:59.630595 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1310 23:22:59.634260 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1311 23:22:59.637496 [Gating] SW calibration Done
1312 23:22:59.637570 ==
1313 23:22:59.640475 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 23:22:59.644229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 23:22:59.644303 ==
1316 23:22:59.647889 RX Vref Scan: 0
1317 23:22:59.647961
1318 23:22:59.648022 RX Vref 0 -> 0, step: 1
1319 23:22:59.648081
1320 23:22:59.650606 RX Delay -130 -> 252, step: 16
1321 23:22:59.657485 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1322 23:22:59.660726 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1323 23:22:59.664471 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1324 23:22:59.667089 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1325 23:22:59.670681 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1326 23:22:59.676991 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1327 23:22:59.680487 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1328 23:22:59.683497 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1329 23:22:59.687111 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1330 23:22:59.690693 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1331 23:22:59.696940 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1332 23:22:59.700142 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1333 23:22:59.703504 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1334 23:22:59.707023 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1335 23:22:59.710024 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1336 23:22:59.717144 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1337 23:22:59.717230 ==
1338 23:22:59.720191 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 23:22:59.723296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 23:22:59.723394 ==
1341 23:22:59.723483 DQS Delay:
1342 23:22:59.726424 DQS0 = 0, DQS1 = 0
1343 23:22:59.726520 DQM Delay:
1344 23:22:59.730076 DQM0 = 86, DQM1 = 79
1345 23:22:59.730174 DQ Delay:
1346 23:22:59.733584 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1347 23:22:59.736926 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1348 23:22:59.739707 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1349 23:22:59.742962 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1350 23:22:59.743036
1351 23:22:59.743113
1352 23:22:59.743218 ==
1353 23:22:59.746893 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 23:22:59.750052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 23:22:59.753653 ==
1356 23:22:59.753723
1357 23:22:59.753782
1358 23:22:59.753838 TX Vref Scan disable
1359 23:22:59.756323 == TX Byte 0 ==
1360 23:22:59.759522 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1361 23:22:59.763160 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1362 23:22:59.766887 == TX Byte 1 ==
1363 23:22:59.770074 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1364 23:22:59.773169 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1365 23:22:59.773244 ==
1366 23:22:59.776242 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 23:22:59.782806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 23:22:59.782895 ==
1369 23:22:59.795389 TX Vref=22, minBit 1, minWin=27, winSum=444
1370 23:22:59.798062 TX Vref=24, minBit 9, minWin=27, winSum=448
1371 23:22:59.801423 TX Vref=26, minBit 9, minWin=27, winSum=446
1372 23:22:59.804772 TX Vref=28, minBit 8, minWin=27, winSum=446
1373 23:22:59.808176 TX Vref=30, minBit 4, minWin=27, winSum=445
1374 23:22:59.814663 TX Vref=32, minBit 9, minWin=27, winSum=446
1375 23:22:59.817817 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 24
1376 23:22:59.817925
1377 23:22:59.821497 Final TX Range 1 Vref 24
1378 23:22:59.821602
1379 23:22:59.821696 ==
1380 23:22:59.825380 Dram Type= 6, Freq= 0, CH_0, rank 1
1381 23:22:59.827998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 23:22:59.831439 ==
1383 23:22:59.831547
1384 23:22:59.831640
1385 23:22:59.831755 TX Vref Scan disable
1386 23:22:59.835068 == TX Byte 0 ==
1387 23:22:59.838111 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1388 23:22:59.844969 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1389 23:22:59.845077 == TX Byte 1 ==
1390 23:22:59.848295 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1391 23:22:59.854749 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1392 23:22:59.854870
1393 23:22:59.854962 [DATLAT]
1394 23:22:59.855050 Freq=800, CH0 RK1
1395 23:22:59.855140
1396 23:22:59.857794 DATLAT Default: 0xa
1397 23:22:59.857911 0, 0xFFFF, sum = 0
1398 23:22:59.861281 1, 0xFFFF, sum = 0
1399 23:22:59.864441 2, 0xFFFF, sum = 0
1400 23:22:59.864545 3, 0xFFFF, sum = 0
1401 23:22:59.868160 4, 0xFFFF, sum = 0
1402 23:22:59.868267 5, 0xFFFF, sum = 0
1403 23:22:59.871337 6, 0xFFFF, sum = 0
1404 23:22:59.871440 7, 0xFFFF, sum = 0
1405 23:22:59.874719 8, 0xFFFF, sum = 0
1406 23:22:59.874820 9, 0x0, sum = 1
1407 23:22:59.877980 10, 0x0, sum = 2
1408 23:22:59.878086 11, 0x0, sum = 3
1409 23:22:59.878179 12, 0x0, sum = 4
1410 23:22:59.881110 best_step = 10
1411 23:22:59.881209
1412 23:22:59.881297 ==
1413 23:22:59.884619 Dram Type= 6, Freq= 0, CH_0, rank 1
1414 23:22:59.887798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 23:22:59.887886 ==
1416 23:22:59.891363 RX Vref Scan: 0
1417 23:22:59.891463
1418 23:22:59.894471 RX Vref 0 -> 0, step: 1
1419 23:22:59.894576
1420 23:22:59.894670 RX Delay -95 -> 252, step: 8
1421 23:22:59.901207 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1422 23:22:59.904986 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1423 23:22:59.908152 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1424 23:22:59.911383 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1425 23:22:59.914462 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1426 23:22:59.921521 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1427 23:22:59.924948 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1428 23:22:59.927884 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1429 23:22:59.931577 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1430 23:22:59.934576 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1431 23:22:59.941073 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1432 23:22:59.944711 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1433 23:22:59.948135 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1434 23:22:59.951142 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1435 23:22:59.957593 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1436 23:22:59.961030 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1437 23:22:59.961109 ==
1438 23:22:59.964281 Dram Type= 6, Freq= 0, CH_0, rank 1
1439 23:22:59.967891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 23:22:59.967992 ==
1441 23:22:59.971520 DQS Delay:
1442 23:22:59.971618 DQS0 = 0, DQS1 = 0
1443 23:22:59.971744 DQM Delay:
1444 23:22:59.974809 DQM0 = 86, DQM1 = 76
1445 23:22:59.974896 DQ Delay:
1446 23:22:59.977450 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1447 23:22:59.980837 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1448 23:22:59.984288 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1449 23:22:59.987938 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1450 23:22:59.988011
1451 23:22:59.988078
1452 23:22:59.997993 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f06, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1453 23:22:59.998098 CH0 RK1: MR19=606, MR18=3F06
1454 23:23:00.004097 CH0_RK1: MR19=0x606, MR18=0x3F06, DQSOSC=393, MR23=63, INC=95, DEC=63
1455 23:23:00.007457 [RxdqsGatingPostProcess] freq 800
1456 23:23:00.014003 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1457 23:23:00.017152 Pre-setting of DQS Precalculation
1458 23:23:00.020951 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1459 23:23:00.021022 ==
1460 23:23:00.024229 Dram Type= 6, Freq= 0, CH_1, rank 0
1461 23:23:00.031101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 23:23:00.031202 ==
1463 23:23:00.033801 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1464 23:23:00.040476 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1465 23:23:00.049925 [CA 0] Center 36 (6~67) winsize 62
1466 23:23:00.053251 [CA 1] Center 36 (6~67) winsize 62
1467 23:23:00.056549 [CA 2] Center 34 (4~65) winsize 62
1468 23:23:00.059985 [CA 3] Center 34 (4~65) winsize 62
1469 23:23:00.063189 [CA 4] Center 34 (4~65) winsize 62
1470 23:23:00.066097 [CA 5] Center 34 (3~65) winsize 63
1471 23:23:00.066195
1472 23:23:00.069746 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1473 23:23:00.069848
1474 23:23:00.073071 [CATrainingPosCal] consider 1 rank data
1475 23:23:00.076547 u2DelayCellTimex100 = 270/100 ps
1476 23:23:00.079556 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1477 23:23:00.086300 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1478 23:23:00.089721 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1479 23:23:00.093131 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1480 23:23:00.096285 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1481 23:23:00.099527 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1482 23:23:00.099631
1483 23:23:00.102478 CA PerBit enable=1, Macro0, CA PI delay=34
1484 23:23:00.102579
1485 23:23:00.106579 [CBTSetCACLKResult] CA Dly = 34
1486 23:23:00.109965 CS Dly: 5 (0~36)
1487 23:23:00.110061 ==
1488 23:23:00.113106 Dram Type= 6, Freq= 0, CH_1, rank 1
1489 23:23:00.115934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1490 23:23:00.116041 ==
1491 23:23:00.120208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1492 23:23:00.126715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1493 23:23:00.136227 [CA 0] Center 36 (6~67) winsize 62
1494 23:23:00.140458 [CA 1] Center 36 (6~67) winsize 62
1495 23:23:00.143782 [CA 2] Center 34 (4~65) winsize 62
1496 23:23:00.147355 [CA 3] Center 34 (3~65) winsize 63
1497 23:23:00.150636 [CA 4] Center 34 (4~65) winsize 62
1498 23:23:00.154172 [CA 5] Center 34 (3~65) winsize 63
1499 23:23:00.154272
1500 23:23:00.157218 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1501 23:23:00.157325
1502 23:23:00.160590 [CATrainingPosCal] consider 2 rank data
1503 23:23:00.163546 u2DelayCellTimex100 = 270/100 ps
1504 23:23:00.167194 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1505 23:23:00.170547 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1506 23:23:00.173365 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1507 23:23:00.176982 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1508 23:23:00.180796 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1509 23:23:00.183605 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1510 23:23:00.187196
1511 23:23:00.190350 CA PerBit enable=1, Macro0, CA PI delay=34
1512 23:23:00.190447
1513 23:23:00.194050 [CBTSetCACLKResult] CA Dly = 34
1514 23:23:00.194149 CS Dly: 6 (0~38)
1515 23:23:00.194257
1516 23:23:00.197050 ----->DramcWriteLeveling(PI) begin...
1517 23:23:00.197149 ==
1518 23:23:00.200420 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 23:23:00.203603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1520 23:23:00.206757 ==
1521 23:23:00.206859 Write leveling (Byte 0): 28 => 28
1522 23:23:00.210342 Write leveling (Byte 1): 28 => 28
1523 23:23:00.213511 DramcWriteLeveling(PI) end<-----
1524 23:23:00.213582
1525 23:23:00.213643 ==
1526 23:23:00.217051 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 23:23:00.223611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 23:23:00.223728 ==
1529 23:23:00.227035 [Gating] SW mode calibration
1530 23:23:00.233466 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1531 23:23:00.236791 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1532 23:23:00.243287 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1533 23:23:00.246786 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1534 23:23:00.250693 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1535 23:23:00.256788 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:23:00.259729 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:23:00.263283 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:23:00.269773 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:23:00.272587 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:23:00.276240 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:23:00.282502 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:23:00.285758 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:23:00.289624 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:23:00.296192 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 23:23:00.299532 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 23:23:00.302373 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 23:23:00.309579 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 23:23:00.313126 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 23:23:00.315915 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1550 23:23:00.322617 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 23:23:00.325922 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 23:23:00.329398 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 23:23:00.332296 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 23:23:00.338913 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 23:23:00.342123 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 23:23:00.345698 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 23:23:00.352468 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1558 23:23:00.356119 0 9 8 | B1->B0 | 2e2e 3333 | 1 0 | (0 0) (0 0)
1559 23:23:00.358957 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 23:23:00.365607 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1561 23:23:00.369171 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1562 23:23:00.372423 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1563 23:23:00.378570 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 23:23:00.381930 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1565 23:23:00.385628 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1566 23:23:00.392136 0 10 8 | B1->B0 | 2e2e 2b2b | 0 0 | (0 0) (0 0)
1567 23:23:00.395522 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1568 23:23:00.398725 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 23:23:00.404926 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1570 23:23:00.408210 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 23:23:00.411544 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 23:23:00.418625 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 23:23:00.421448 0 11 4 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
1574 23:23:00.424871 0 11 8 | B1->B0 | 3939 3b3b | 0 0 | (0 0) (0 0)
1575 23:23:00.432057 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 23:23:00.434981 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 23:23:00.438532 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 23:23:00.444914 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 23:23:00.448026 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 23:23:00.451697 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 23:23:00.458520 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1582 23:23:00.461417 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1583 23:23:00.464676 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 23:23:00.471654 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 23:23:00.475005 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 23:23:00.477744 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 23:23:00.484513 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 23:23:00.488403 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 23:23:00.491496 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 23:23:00.497466 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 23:23:00.500746 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 23:23:00.504338 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 23:23:00.511176 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 23:23:00.514059 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 23:23:00.517510 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 23:23:00.524559 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 23:23:00.527917 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1598 23:23:00.530703 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1599 23:23:00.534393 Total UI for P1: 0, mck2ui 16
1600 23:23:00.537735 best dqsien dly found for B0: ( 0, 14, 4)
1601 23:23:00.540406 Total UI for P1: 0, mck2ui 16
1602 23:23:00.543886 best dqsien dly found for B1: ( 0, 14, 6)
1603 23:23:00.547615 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1604 23:23:00.550895 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1605 23:23:00.550977
1606 23:23:00.553899 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1607 23:23:00.560563 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1608 23:23:00.560647 [Gating] SW calibration Done
1609 23:23:00.563706 ==
1610 23:23:00.563807 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 23:23:00.570700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 23:23:00.570799 ==
1613 23:23:00.570867 RX Vref Scan: 0
1614 23:23:00.570929
1615 23:23:00.573923 RX Vref 0 -> 0, step: 1
1616 23:23:00.574025
1617 23:23:00.577509 RX Delay -130 -> 252, step: 16
1618 23:23:00.580181 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1619 23:23:00.583588 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1620 23:23:00.590850 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1621 23:23:00.593801 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1622 23:23:00.597550 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1623 23:23:00.600491 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1624 23:23:00.603281 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1625 23:23:00.610113 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1626 23:23:00.613221 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1627 23:23:00.616720 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1628 23:23:00.619831 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1629 23:23:00.623431 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1630 23:23:00.629726 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1631 23:23:00.633515 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1632 23:23:00.636132 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1633 23:23:00.639820 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1634 23:23:00.639894 ==
1635 23:23:00.642936 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 23:23:00.649426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 23:23:00.649502 ==
1638 23:23:00.649566 DQS Delay:
1639 23:23:00.652975 DQS0 = 0, DQS1 = 0
1640 23:23:00.653045 DQM Delay:
1641 23:23:00.653104 DQM0 = 89, DQM1 = 78
1642 23:23:00.656702 DQ Delay:
1643 23:23:00.659810 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1644 23:23:00.662636 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1645 23:23:00.666445 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1646 23:23:00.669405 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1647 23:23:00.669487
1648 23:23:00.669552
1649 23:23:00.669611 ==
1650 23:23:00.673120 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 23:23:00.676118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 23:23:00.676200 ==
1653 23:23:00.676265
1654 23:23:00.676324
1655 23:23:00.679845 TX Vref Scan disable
1656 23:23:00.682867 == TX Byte 0 ==
1657 23:23:00.685923 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1658 23:23:00.689362 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1659 23:23:00.692960 == TX Byte 1 ==
1660 23:23:00.696694 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1661 23:23:00.700586 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1662 23:23:00.700666 ==
1663 23:23:00.703215 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 23:23:00.706954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 23:23:00.707052 ==
1666 23:23:00.720618 TX Vref=22, minBit 10, minWin=26, winSum=442
1667 23:23:00.723695 TX Vref=24, minBit 9, minWin=27, winSum=446
1668 23:23:00.726996 TX Vref=26, minBit 10, minWin=27, winSum=451
1669 23:23:00.730664 TX Vref=28, minBit 10, minWin=27, winSum=450
1670 23:23:00.734103 TX Vref=30, minBit 10, minWin=27, winSum=449
1671 23:23:00.740232 TX Vref=32, minBit 8, minWin=27, winSum=446
1672 23:23:00.744161 [TxChooseVref] Worse bit 10, Min win 27, Win sum 451, Final Vref 26
1673 23:23:00.744245
1674 23:23:00.747512 Final TX Range 1 Vref 26
1675 23:23:00.747619
1676 23:23:00.747745 ==
1677 23:23:00.750451 Dram Type= 6, Freq= 0, CH_1, rank 0
1678 23:23:00.753803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1679 23:23:00.757226 ==
1680 23:23:00.757307
1681 23:23:00.757372
1682 23:23:00.757431 TX Vref Scan disable
1683 23:23:00.760732 == TX Byte 0 ==
1684 23:23:00.764069 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1685 23:23:00.767649 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1686 23:23:00.770597 == TX Byte 1 ==
1687 23:23:00.774003 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1688 23:23:00.780987 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1689 23:23:00.781093
1690 23:23:00.781190 [DATLAT]
1691 23:23:00.781283 Freq=800, CH1 RK0
1692 23:23:00.781372
1693 23:23:00.784161 DATLAT Default: 0xa
1694 23:23:00.784260 0, 0xFFFF, sum = 0
1695 23:23:00.787450 1, 0xFFFF, sum = 0
1696 23:23:00.790503 2, 0xFFFF, sum = 0
1697 23:23:00.790600 3, 0xFFFF, sum = 0
1698 23:23:00.793692 4, 0xFFFF, sum = 0
1699 23:23:00.793792 5, 0xFFFF, sum = 0
1700 23:23:00.797248 6, 0xFFFF, sum = 0
1701 23:23:00.797349 7, 0xFFFF, sum = 0
1702 23:23:00.800586 8, 0xFFFF, sum = 0
1703 23:23:00.800688 9, 0x0, sum = 1
1704 23:23:00.803979 10, 0x0, sum = 2
1705 23:23:00.804079 11, 0x0, sum = 3
1706 23:23:00.804170 12, 0x0, sum = 4
1707 23:23:00.807256 best_step = 10
1708 23:23:00.807349
1709 23:23:00.807436 ==
1710 23:23:00.810557 Dram Type= 6, Freq= 0, CH_1, rank 0
1711 23:23:00.813655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1712 23:23:00.813740 ==
1713 23:23:00.817531 RX Vref Scan: 1
1714 23:23:00.817606
1715 23:23:00.820300 Set Vref Range= 32 -> 127
1716 23:23:00.820382
1717 23:23:00.820446 RX Vref 32 -> 127, step: 1
1718 23:23:00.820507
1719 23:23:00.824051 RX Delay -95 -> 252, step: 8
1720 23:23:00.824158
1721 23:23:00.826886 Set Vref, RX VrefLevel [Byte0]: 32
1722 23:23:00.830764 [Byte1]: 32
1723 23:23:00.830847
1724 23:23:00.833777 Set Vref, RX VrefLevel [Byte0]: 33
1725 23:23:00.837451 [Byte1]: 33
1726 23:23:00.841369
1727 23:23:00.841450 Set Vref, RX VrefLevel [Byte0]: 34
1728 23:23:00.844766 [Byte1]: 34
1729 23:23:00.848878
1730 23:23:00.848959 Set Vref, RX VrefLevel [Byte0]: 35
1731 23:23:00.852468 [Byte1]: 35
1732 23:23:00.856724
1733 23:23:00.856806 Set Vref, RX VrefLevel [Byte0]: 36
1734 23:23:00.859907 [Byte1]: 36
1735 23:23:00.863891
1736 23:23:00.863973 Set Vref, RX VrefLevel [Byte0]: 37
1737 23:23:00.867395 [Byte1]: 37
1738 23:23:00.871517
1739 23:23:00.871625 Set Vref, RX VrefLevel [Byte0]: 38
1740 23:23:00.875314 [Byte1]: 38
1741 23:23:00.879131
1742 23:23:00.879228 Set Vref, RX VrefLevel [Byte0]: 39
1743 23:23:00.882503 [Byte1]: 39
1744 23:23:00.886732
1745 23:23:00.886813 Set Vref, RX VrefLevel [Byte0]: 40
1746 23:23:00.890271 [Byte1]: 40
1747 23:23:00.894389
1748 23:23:00.894471 Set Vref, RX VrefLevel [Byte0]: 41
1749 23:23:00.897654 [Byte1]: 41
1750 23:23:00.901786
1751 23:23:00.901883 Set Vref, RX VrefLevel [Byte0]: 42
1752 23:23:00.905335 [Byte1]: 42
1753 23:23:00.909511
1754 23:23:00.909592 Set Vref, RX VrefLevel [Byte0]: 43
1755 23:23:00.912811 [Byte1]: 43
1756 23:23:00.916947
1757 23:23:00.917029 Set Vref, RX VrefLevel [Byte0]: 44
1758 23:23:00.920427 [Byte1]: 44
1759 23:23:00.924700
1760 23:23:00.924783 Set Vref, RX VrefLevel [Byte0]: 45
1761 23:23:00.928262 [Byte1]: 45
1762 23:23:00.932262
1763 23:23:00.932368 Set Vref, RX VrefLevel [Byte0]: 46
1764 23:23:00.935761 [Byte1]: 46
1765 23:23:00.939771
1766 23:23:00.939852 Set Vref, RX VrefLevel [Byte0]: 47
1767 23:23:00.943065 [Byte1]: 47
1768 23:23:00.947748
1769 23:23:00.947829 Set Vref, RX VrefLevel [Byte0]: 48
1770 23:23:00.950897 [Byte1]: 48
1771 23:23:00.955096
1772 23:23:00.955211 Set Vref, RX VrefLevel [Byte0]: 49
1773 23:23:00.958416 [Byte1]: 49
1774 23:23:00.962648
1775 23:23:00.962756 Set Vref, RX VrefLevel [Byte0]: 50
1776 23:23:00.966173 [Byte1]: 50
1777 23:23:00.970427
1778 23:23:00.970534 Set Vref, RX VrefLevel [Byte0]: 51
1779 23:23:00.973981 [Byte1]: 51
1780 23:23:00.977677
1781 23:23:00.977783 Set Vref, RX VrefLevel [Byte0]: 52
1782 23:23:00.981004 [Byte1]: 52
1783 23:23:00.985462
1784 23:23:00.985568 Set Vref, RX VrefLevel [Byte0]: 53
1785 23:23:00.988570 [Byte1]: 53
1786 23:23:00.993597
1787 23:23:00.993702 Set Vref, RX VrefLevel [Byte0]: 54
1788 23:23:00.996525 [Byte1]: 54
1789 23:23:01.000444
1790 23:23:01.000550 Set Vref, RX VrefLevel [Byte0]: 55
1791 23:23:01.003857 [Byte1]: 55
1792 23:23:01.008237
1793 23:23:01.008343 Set Vref, RX VrefLevel [Byte0]: 56
1794 23:23:01.011540 [Byte1]: 56
1795 23:23:01.015969
1796 23:23:01.016076 Set Vref, RX VrefLevel [Byte0]: 57
1797 23:23:01.019374 [Byte1]: 57
1798 23:23:01.023479
1799 23:23:01.023586 Set Vref, RX VrefLevel [Byte0]: 58
1800 23:23:01.026890 [Byte1]: 58
1801 23:23:01.031011
1802 23:23:01.031117 Set Vref, RX VrefLevel [Byte0]: 59
1803 23:23:01.034738 [Byte1]: 59
1804 23:23:01.038454
1805 23:23:01.038557 Set Vref, RX VrefLevel [Byte0]: 60
1806 23:23:01.041831 [Byte1]: 60
1807 23:23:01.046730
1808 23:23:01.046852 Set Vref, RX VrefLevel [Byte0]: 61
1809 23:23:01.052623 [Byte1]: 61
1810 23:23:01.052710
1811 23:23:01.056632 Set Vref, RX VrefLevel [Byte0]: 62
1812 23:23:01.059315 [Byte1]: 62
1813 23:23:01.059417
1814 23:23:01.062384 Set Vref, RX VrefLevel [Byte0]: 63
1815 23:23:01.065781 [Byte1]: 63
1816 23:23:01.065864
1817 23:23:01.069109 Set Vref, RX VrefLevel [Byte0]: 64
1818 23:23:01.072648 [Byte1]: 64
1819 23:23:01.076984
1820 23:23:01.077066 Set Vref, RX VrefLevel [Byte0]: 65
1821 23:23:01.080200 [Byte1]: 65
1822 23:23:01.084627
1823 23:23:01.084709 Set Vref, RX VrefLevel [Byte0]: 66
1824 23:23:01.087400 [Byte1]: 66
1825 23:23:01.092059
1826 23:23:01.092184 Set Vref, RX VrefLevel [Byte0]: 67
1827 23:23:01.095527 [Byte1]: 67
1828 23:23:01.099521
1829 23:23:01.099629 Set Vref, RX VrefLevel [Byte0]: 68
1830 23:23:01.102749 [Byte1]: 68
1831 23:23:01.106751
1832 23:23:01.106861 Set Vref, RX VrefLevel [Byte0]: 69
1833 23:23:01.110373 [Byte1]: 69
1834 23:23:01.114961
1835 23:23:01.115070 Set Vref, RX VrefLevel [Byte0]: 70
1836 23:23:01.118359 [Byte1]: 70
1837 23:23:01.122245
1838 23:23:01.122347 Set Vref, RX VrefLevel [Byte0]: 71
1839 23:23:01.125470 [Byte1]: 71
1840 23:23:01.129745
1841 23:23:01.129851 Set Vref, RX VrefLevel [Byte0]: 72
1842 23:23:01.133131 [Byte1]: 72
1843 23:23:01.137331
1844 23:23:01.137436 Set Vref, RX VrefLevel [Byte0]: 73
1845 23:23:01.140647 [Byte1]: 73
1846 23:23:01.144985
1847 23:23:01.145087 Set Vref, RX VrefLevel [Byte0]: 74
1848 23:23:01.151439 [Byte1]: 74
1849 23:23:01.151543
1850 23:23:01.154743 Set Vref, RX VrefLevel [Byte0]: 75
1851 23:23:01.158367 [Byte1]: 75
1852 23:23:01.158469
1853 23:23:01.161379 Set Vref, RX VrefLevel [Byte0]: 76
1854 23:23:01.164724 [Byte1]: 76
1855 23:23:01.164810
1856 23:23:01.168170 Set Vref, RX VrefLevel [Byte0]: 77
1857 23:23:01.171102 [Byte1]: 77
1858 23:23:01.176001
1859 23:23:01.176109 Final RX Vref Byte 0 = 56 to rank0
1860 23:23:01.178859 Final RX Vref Byte 1 = 64 to rank0
1861 23:23:01.181979 Final RX Vref Byte 0 = 56 to rank1
1862 23:23:01.185030 Final RX Vref Byte 1 = 64 to rank1==
1863 23:23:01.188328 Dram Type= 6, Freq= 0, CH_1, rank 0
1864 23:23:01.195146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 23:23:01.195230 ==
1866 23:23:01.195296 DQS Delay:
1867 23:23:01.198153 DQS0 = 0, DQS1 = 0
1868 23:23:01.198234 DQM Delay:
1869 23:23:01.198299 DQM0 = 86, DQM1 = 79
1870 23:23:01.201788 DQ Delay:
1871 23:23:01.205033 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1872 23:23:01.208441 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1873 23:23:01.211607 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1874 23:23:01.215079 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1875 23:23:01.215163
1876 23:23:01.215224
1877 23:23:01.221783 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1878 23:23:01.224859 CH1 RK0: MR19=606, MR18=2C19
1879 23:23:01.231436 CH1_RK0: MR19=0x606, MR18=0x2C19, DQSOSC=398, MR23=63, INC=93, DEC=62
1880 23:23:01.231518
1881 23:23:01.234573 ----->DramcWriteLeveling(PI) begin...
1882 23:23:01.234656 ==
1883 23:23:01.238108 Dram Type= 6, Freq= 0, CH_1, rank 1
1884 23:23:01.241691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1885 23:23:01.241773 ==
1886 23:23:01.244668 Write leveling (Byte 0): 29 => 29
1887 23:23:01.248289 Write leveling (Byte 1): 29 => 29
1888 23:23:01.251072 DramcWriteLeveling(PI) end<-----
1889 23:23:01.251157
1890 23:23:01.251222 ==
1891 23:23:01.254905 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 23:23:01.258414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 23:23:01.258515 ==
1894 23:23:01.261526 [Gating] SW mode calibration
1895 23:23:01.267968 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1896 23:23:01.274787 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1897 23:23:01.277840 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1898 23:23:01.284412 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1899 23:23:01.287628 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 23:23:01.290846 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 23:23:01.297882 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 23:23:01.301322 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 23:23:01.304371 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 23:23:01.311192 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 23:23:01.314214 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 23:23:01.317593 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:23:01.324012 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 23:23:01.327252 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 23:23:01.330522 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 23:23:01.337758 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 23:23:01.340678 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 23:23:01.343968 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 23:23:01.350366 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 23:23:01.354161 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1915 23:23:01.357103 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1916 23:23:01.364160 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 23:23:01.366879 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 23:23:01.370657 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 23:23:01.376869 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 23:23:01.380080 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 23:23:01.383328 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 23:23:01.390238 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 23:23:01.393403 0 9 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
1924 23:23:01.397084 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1925 23:23:01.403362 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1926 23:23:01.406942 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1927 23:23:01.409863 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1928 23:23:01.416540 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1929 23:23:01.419446 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1930 23:23:01.423238 0 10 4 | B1->B0 | 3030 3434 | 1 0 | (1 1) (0 0)
1931 23:23:01.429735 0 10 8 | B1->B0 | 2323 2f2f | 0 0 | (1 0) (0 0)
1932 23:23:01.433128 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1933 23:23:01.436907 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1934 23:23:01.442689 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1935 23:23:01.446689 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1936 23:23:01.449363 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1937 23:23:01.456165 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1938 23:23:01.459420 0 11 4 | B1->B0 | 2d2d 2929 | 0 0 | (0 0) (0 0)
1939 23:23:01.462440 0 11 8 | B1->B0 | 4444 3838 | 0 1 | (0 0) (0 0)
1940 23:23:01.469744 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 23:23:01.472504 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1942 23:23:01.475854 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 23:23:01.479476 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 23:23:01.485852 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 23:23:01.489464 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 23:23:01.492661 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 23:23:01.499224 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1948 23:23:01.502683 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 23:23:01.505871 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 23:23:01.512481 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 23:23:01.516093 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 23:23:01.519350 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 23:23:01.526076 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 23:23:01.529040 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 23:23:01.532716 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 23:23:01.539597 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 23:23:01.542516 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 23:23:01.545848 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1959 23:23:01.552444 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1960 23:23:01.555568 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 23:23:01.559372 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1962 23:23:01.565510 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1963 23:23:01.568941 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1964 23:23:01.572375 Total UI for P1: 0, mck2ui 16
1965 23:23:01.575905 best dqsien dly found for B0: ( 0, 14, 4)
1966 23:23:01.578626 Total UI for P1: 0, mck2ui 16
1967 23:23:01.582251 best dqsien dly found for B1: ( 0, 14, 4)
1968 23:23:01.585403 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1969 23:23:01.588940 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1970 23:23:01.589039
1971 23:23:01.592449 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1972 23:23:01.595837 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1973 23:23:01.598891 [Gating] SW calibration Done
1974 23:23:01.598973 ==
1975 23:23:01.602205 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 23:23:01.605964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 23:23:01.606047 ==
1978 23:23:01.608509 RX Vref Scan: 0
1979 23:23:01.608591
1980 23:23:01.612115 RX Vref 0 -> 0, step: 1
1981 23:23:01.612197
1982 23:23:01.615848 RX Delay -130 -> 252, step: 16
1983 23:23:01.618604 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1984 23:23:01.622406 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1985 23:23:01.625190 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1986 23:23:01.628746 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1987 23:23:01.635166 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1988 23:23:01.639299 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1989 23:23:01.642019 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1990 23:23:01.645298 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1991 23:23:01.648310 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1992 23:23:01.655299 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1993 23:23:01.658236 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1994 23:23:01.661467 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1995 23:23:01.665136 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1996 23:23:01.671300 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1997 23:23:01.675215 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1998 23:23:01.677959 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1999 23:23:01.678040 ==
2000 23:23:01.681327 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 23:23:01.684717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 23:23:01.684800 ==
2003 23:23:01.687668 DQS Delay:
2004 23:23:01.687789 DQS0 = 0, DQS1 = 0
2005 23:23:01.691218 DQM Delay:
2006 23:23:01.691299 DQM0 = 86, DQM1 = 78
2007 23:23:01.691364 DQ Delay:
2008 23:23:01.694266 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
2009 23:23:01.698057 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2010 23:23:01.701110 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2011 23:23:01.704241 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2012 23:23:01.704322
2013 23:23:01.707821
2014 23:23:01.707903 ==
2015 23:23:01.710962 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 23:23:01.714502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 23:23:01.714584 ==
2018 23:23:01.714650
2019 23:23:01.714710
2020 23:23:01.717782 TX Vref Scan disable
2021 23:23:01.717864 == TX Byte 0 ==
2022 23:23:01.724327 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2023 23:23:01.727863 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2024 23:23:01.727944 == TX Byte 1 ==
2025 23:23:01.734363 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2026 23:23:01.737445 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2027 23:23:01.737528 ==
2028 23:23:01.740969 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 23:23:01.744645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 23:23:01.744722 ==
2031 23:23:01.757519 TX Vref=22, minBit 8, minWin=27, winSum=443
2032 23:23:01.761055 TX Vref=24, minBit 8, minWin=26, winSum=443
2033 23:23:01.764648 TX Vref=26, minBit 8, minWin=27, winSum=452
2034 23:23:01.767580 TX Vref=28, minBit 13, minWin=27, winSum=451
2035 23:23:01.771457 TX Vref=30, minBit 13, minWin=27, winSum=449
2036 23:23:01.777908 TX Vref=32, minBit 8, minWin=27, winSum=447
2037 23:23:01.780585 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 26
2038 23:23:01.780692
2039 23:23:01.784351 Final TX Range 1 Vref 26
2040 23:23:01.784423
2041 23:23:01.784484 ==
2042 23:23:01.787856 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 23:23:01.790582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 23:23:01.794617 ==
2045 23:23:01.794711
2046 23:23:01.794798
2047 23:23:01.794864 TX Vref Scan disable
2048 23:23:01.797908 == TX Byte 0 ==
2049 23:23:01.801536 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2050 23:23:01.807856 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2051 23:23:01.807948 == TX Byte 1 ==
2052 23:23:01.811083 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2053 23:23:01.818249 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2054 23:23:01.818357
2055 23:23:01.818450 [DATLAT]
2056 23:23:01.818544 Freq=800, CH1 RK1
2057 23:23:01.818633
2058 23:23:01.821421 DATLAT Default: 0xa
2059 23:23:01.821533 0, 0xFFFF, sum = 0
2060 23:23:01.824406 1, 0xFFFF, sum = 0
2061 23:23:01.824509 2, 0xFFFF, sum = 0
2062 23:23:01.827784 3, 0xFFFF, sum = 0
2063 23:23:01.827887 4, 0xFFFF, sum = 0
2064 23:23:01.831444 5, 0xFFFF, sum = 0
2065 23:23:01.834307 6, 0xFFFF, sum = 0
2066 23:23:01.834416 7, 0xFFFF, sum = 0
2067 23:23:01.837645 8, 0xFFFF, sum = 0
2068 23:23:01.837751 9, 0x0, sum = 1
2069 23:23:01.837844 10, 0x0, sum = 2
2070 23:23:01.841133 11, 0x0, sum = 3
2071 23:23:01.841238 12, 0x0, sum = 4
2072 23:23:01.844386 best_step = 10
2073 23:23:01.844487
2074 23:23:01.844578 ==
2075 23:23:01.847712 Dram Type= 6, Freq= 0, CH_1, rank 1
2076 23:23:01.850688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2077 23:23:01.850774 ==
2078 23:23:01.853971 RX Vref Scan: 0
2079 23:23:01.854053
2080 23:23:01.854117 RX Vref 0 -> 0, step: 1
2081 23:23:01.857806
2082 23:23:01.857887 RX Delay -95 -> 252, step: 8
2083 23:23:01.864672 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2084 23:23:01.867511 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2085 23:23:01.871456 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2086 23:23:01.874085 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2087 23:23:01.881477 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2088 23:23:01.884342 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2089 23:23:01.887564 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2090 23:23:01.890841 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2091 23:23:01.894187 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2092 23:23:01.900412 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2093 23:23:01.903882 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2094 23:23:01.907142 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2095 23:23:01.910451 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2096 23:23:01.913946 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2097 23:23:01.920281 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2098 23:23:01.924265 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2099 23:23:01.924348 ==
2100 23:23:01.926932 Dram Type= 6, Freq= 0, CH_1, rank 1
2101 23:23:01.930586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2102 23:23:01.930668 ==
2103 23:23:01.933920 DQS Delay:
2104 23:23:01.934006 DQS0 = 0, DQS1 = 0
2105 23:23:01.934093 DQM Delay:
2106 23:23:01.937111 DQM0 = 87, DQM1 = 78
2107 23:23:01.937195 DQ Delay:
2108 23:23:01.940579 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2109 23:23:01.943850 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2110 23:23:01.947251 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2111 23:23:01.950088 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2112 23:23:01.950173
2113 23:23:01.950259
2114 23:23:01.960098 [DQSOSCAuto] RK1, (LSB)MR18= 0x1911, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2115 23:23:01.963405 CH1 RK1: MR19=606, MR18=1911
2116 23:23:01.966857 CH1_RK1: MR19=0x606, MR18=0x1911, DQSOSC=403, MR23=63, INC=90, DEC=60
2117 23:23:01.970294 [RxdqsGatingPostProcess] freq 800
2118 23:23:01.977176 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2119 23:23:01.979939 Pre-setting of DQS Precalculation
2120 23:23:01.983555 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2121 23:23:01.993148 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2122 23:23:02.000114 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2123 23:23:02.000197
2124 23:23:02.000261
2125 23:23:02.003656 [Calibration Summary] 1600 Mbps
2126 23:23:02.003758 CH 0, Rank 0
2127 23:23:02.006700 SW Impedance : PASS
2128 23:23:02.006782 DUTY Scan : NO K
2129 23:23:02.010474 ZQ Calibration : PASS
2130 23:23:02.013249 Jitter Meter : NO K
2131 23:23:02.013346 CBT Training : PASS
2132 23:23:02.016408 Write leveling : PASS
2133 23:23:02.020116 RX DQS gating : PASS
2134 23:23:02.020198 RX DQ/DQS(RDDQC) : PASS
2135 23:23:02.023543 TX DQ/DQS : PASS
2136 23:23:02.026250 RX DATLAT : PASS
2137 23:23:02.026357 RX DQ/DQS(Engine): PASS
2138 23:23:02.029934 TX OE : NO K
2139 23:23:02.030017 All Pass.
2140 23:23:02.030083
2141 23:23:02.033521 CH 0, Rank 1
2142 23:23:02.033606 SW Impedance : PASS
2143 23:23:02.036404 DUTY Scan : NO K
2144 23:23:02.039619 ZQ Calibration : PASS
2145 23:23:02.039739 Jitter Meter : NO K
2146 23:23:02.043319 CBT Training : PASS
2147 23:23:02.043404 Write leveling : PASS
2148 23:23:02.046690 RX DQS gating : PASS
2149 23:23:02.049481 RX DQ/DQS(RDDQC) : PASS
2150 23:23:02.049565 TX DQ/DQS : PASS
2151 23:23:02.053332 RX DATLAT : PASS
2152 23:23:02.055967 RX DQ/DQS(Engine): PASS
2153 23:23:02.056052 TX OE : NO K
2154 23:23:02.059551 All Pass.
2155 23:23:02.059662
2156 23:23:02.059768 CH 1, Rank 0
2157 23:23:02.062784 SW Impedance : PASS
2158 23:23:02.062869 DUTY Scan : NO K
2159 23:23:02.065896 ZQ Calibration : PASS
2160 23:23:02.069334 Jitter Meter : NO K
2161 23:23:02.069419 CBT Training : PASS
2162 23:23:02.072966 Write leveling : PASS
2163 23:23:02.075844 RX DQS gating : PASS
2164 23:23:02.075926 RX DQ/DQS(RDDQC) : PASS
2165 23:23:02.079429 TX DQ/DQS : PASS
2166 23:23:02.083231 RX DATLAT : PASS
2167 23:23:02.083313 RX DQ/DQS(Engine): PASS
2168 23:23:02.085978 TX OE : NO K
2169 23:23:02.086060 All Pass.
2170 23:23:02.086125
2171 23:23:02.089365 CH 1, Rank 1
2172 23:23:02.089446 SW Impedance : PASS
2173 23:23:02.093407 DUTY Scan : NO K
2174 23:23:02.096136 ZQ Calibration : PASS
2175 23:23:02.096218 Jitter Meter : NO K
2176 23:23:02.099410 CBT Training : PASS
2177 23:23:02.102901 Write leveling : PASS
2178 23:23:02.102983 RX DQS gating : PASS
2179 23:23:02.106049 RX DQ/DQS(RDDQC) : PASS
2180 23:23:02.109210 TX DQ/DQS : PASS
2181 23:23:02.109292 RX DATLAT : PASS
2182 23:23:02.112717 RX DQ/DQS(Engine): PASS
2183 23:23:02.112799 TX OE : NO K
2184 23:23:02.115815 All Pass.
2185 23:23:02.115897
2186 23:23:02.115962 DramC Write-DBI off
2187 23:23:02.119141 PER_BANK_REFRESH: Hybrid Mode
2188 23:23:02.122438 TX_TRACKING: ON
2189 23:23:02.125583 [GetDramInforAfterCalByMRR] Vendor 6.
2190 23:23:02.129063 [GetDramInforAfterCalByMRR] Revision 606.
2191 23:23:02.132510 [GetDramInforAfterCalByMRR] Revision 2 0.
2192 23:23:02.132592 MR0 0x3b3b
2193 23:23:02.136201 MR8 0x5151
2194 23:23:02.139473 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2195 23:23:02.139555
2196 23:23:02.139621 MR0 0x3b3b
2197 23:23:02.139723 MR8 0x5151
2198 23:23:02.142696 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2199 23:23:02.142778
2200 23:23:02.152239 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2201 23:23:02.155628 [FAST_K] Save calibration result to emmc
2202 23:23:02.158622 [FAST_K] Save calibration result to emmc
2203 23:23:02.161799 dram_init: config_dvfs: 1
2204 23:23:02.165368 dramc_set_vcore_voltage set vcore to 662500
2205 23:23:02.169065 Read voltage for 1200, 2
2206 23:23:02.169148 Vio18 = 0
2207 23:23:02.172056 Vcore = 662500
2208 23:23:02.172139 Vdram = 0
2209 23:23:02.172204 Vddq = 0
2210 23:23:02.172263 Vmddr = 0
2211 23:23:02.178717 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2212 23:23:02.185123 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2213 23:23:02.185231 MEM_TYPE=3, freq_sel=15
2214 23:23:02.188225 sv_algorithm_assistance_LP4_1600
2215 23:23:02.192020 ============ PULL DRAM RESETB DOWN ============
2216 23:23:02.198277 ========== PULL DRAM RESETB DOWN end =========
2217 23:23:02.201806 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2218 23:23:02.205066 ===================================
2219 23:23:02.208941 LPDDR4 DRAM CONFIGURATION
2220 23:23:02.211373 ===================================
2221 23:23:02.211482 EX_ROW_EN[0] = 0x0
2222 23:23:02.215140 EX_ROW_EN[1] = 0x0
2223 23:23:02.215249 LP4Y_EN = 0x0
2224 23:23:02.218498 WORK_FSP = 0x0
2225 23:23:02.222100 WL = 0x4
2226 23:23:02.222224 RL = 0x4
2227 23:23:02.225085 BL = 0x2
2228 23:23:02.225166 RPST = 0x0
2229 23:23:02.228109 RD_PRE = 0x0
2230 23:23:02.228191 WR_PRE = 0x1
2231 23:23:02.231654 WR_PST = 0x0
2232 23:23:02.231759 DBI_WR = 0x0
2233 23:23:02.234801 DBI_RD = 0x0
2234 23:23:02.234882 OTF = 0x1
2235 23:23:02.237849 ===================================
2236 23:23:02.241507 ===================================
2237 23:23:02.244778 ANA top config
2238 23:23:02.248283 ===================================
2239 23:23:02.248387 DLL_ASYNC_EN = 0
2240 23:23:02.251308 ALL_SLAVE_EN = 0
2241 23:23:02.254409 NEW_RANK_MODE = 1
2242 23:23:02.257796 DLL_IDLE_MODE = 1
2243 23:23:02.261485 LP45_APHY_COMB_EN = 1
2244 23:23:02.261588 TX_ODT_DIS = 1
2245 23:23:02.264673 NEW_8X_MODE = 1
2246 23:23:02.267783 ===================================
2247 23:23:02.271109 ===================================
2248 23:23:02.274363 data_rate = 2400
2249 23:23:02.277577 CKR = 1
2250 23:23:02.281268 DQ_P2S_RATIO = 8
2251 23:23:02.284843 ===================================
2252 23:23:02.284950 CA_P2S_RATIO = 8
2253 23:23:02.287472 DQ_CA_OPEN = 0
2254 23:23:02.291143 DQ_SEMI_OPEN = 0
2255 23:23:02.294136 CA_SEMI_OPEN = 0
2256 23:23:02.297450 CA_FULL_RATE = 0
2257 23:23:02.301366 DQ_CKDIV4_EN = 0
2258 23:23:02.301470 CA_CKDIV4_EN = 0
2259 23:23:02.304754 CA_PREDIV_EN = 0
2260 23:23:02.308082 PH8_DLY = 17
2261 23:23:02.310957 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2262 23:23:02.314701 DQ_AAMCK_DIV = 4
2263 23:23:02.317791 CA_AAMCK_DIV = 4
2264 23:23:02.317873 CA_ADMCK_DIV = 4
2265 23:23:02.320880 DQ_TRACK_CA_EN = 0
2266 23:23:02.324248 CA_PICK = 1200
2267 23:23:02.327517 CA_MCKIO = 1200
2268 23:23:02.331136 MCKIO_SEMI = 0
2269 23:23:02.334045 PLL_FREQ = 2366
2270 23:23:02.337706 DQ_UI_PI_RATIO = 32
2271 23:23:02.340498 CA_UI_PI_RATIO = 0
2272 23:23:02.343888 ===================================
2273 23:23:02.347961 ===================================
2274 23:23:02.348044 memory_type:LPDDR4
2275 23:23:02.350843 GP_NUM : 10
2276 23:23:02.350925 SRAM_EN : 1
2277 23:23:02.354168 MD32_EN : 0
2278 23:23:02.357486 ===================================
2279 23:23:02.360478 [ANA_INIT] >>>>>>>>>>>>>>
2280 23:23:02.363639 <<<<<< [CONFIGURE PHASE]: ANA_TX
2281 23:23:02.367365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2282 23:23:02.370895 ===================================
2283 23:23:02.373673 data_rate = 2400,PCW = 0X5b00
2284 23:23:02.373755 ===================================
2285 23:23:02.380931 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2286 23:23:02.383580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2287 23:23:02.390138 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2288 23:23:02.394005 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2289 23:23:02.396878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2290 23:23:02.399986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2291 23:23:02.403452 [ANA_INIT] flow start
2292 23:23:02.406769 [ANA_INIT] PLL >>>>>>>>
2293 23:23:02.406851 [ANA_INIT] PLL <<<<<<<<
2294 23:23:02.410237 [ANA_INIT] MIDPI >>>>>>>>
2295 23:23:02.413347 [ANA_INIT] MIDPI <<<<<<<<
2296 23:23:02.413453 [ANA_INIT] DLL >>>>>>>>
2297 23:23:02.417067 [ANA_INIT] DLL <<<<<<<<
2298 23:23:02.419881 [ANA_INIT] flow end
2299 23:23:02.423588 ============ LP4 DIFF to SE enter ============
2300 23:23:02.426616 ============ LP4 DIFF to SE exit ============
2301 23:23:02.430401 [ANA_INIT] <<<<<<<<<<<<<
2302 23:23:02.433166 [Flow] Enable top DCM control >>>>>
2303 23:23:02.436944 [Flow] Enable top DCM control <<<<<
2304 23:23:02.439567 Enable DLL master slave shuffle
2305 23:23:02.443054 ==============================================================
2306 23:23:02.446729 Gating Mode config
2307 23:23:02.453035 ==============================================================
2308 23:23:02.453117 Config description:
2309 23:23:02.462898 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2310 23:23:02.469600 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2311 23:23:02.476158 SELPH_MODE 0: By rank 1: By Phase
2312 23:23:02.479855 ==============================================================
2313 23:23:02.482893 GAT_TRACK_EN = 1
2314 23:23:02.486561 RX_GATING_MODE = 2
2315 23:23:02.489362 RX_GATING_TRACK_MODE = 2
2316 23:23:02.492866 SELPH_MODE = 1
2317 23:23:02.496124 PICG_EARLY_EN = 1
2318 23:23:02.499968 VALID_LAT_VALUE = 1
2319 23:23:02.503000 ==============================================================
2320 23:23:02.506340 Enter into Gating configuration >>>>
2321 23:23:02.509362 Exit from Gating configuration <<<<
2322 23:23:02.512981 Enter into DVFS_PRE_config >>>>>
2323 23:23:02.526288 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2324 23:23:02.529062 Exit from DVFS_PRE_config <<<<<
2325 23:23:02.532449 Enter into PICG configuration >>>>
2326 23:23:02.536406 Exit from PICG configuration <<<<
2327 23:23:02.536489 [RX_INPUT] configuration >>>>>
2328 23:23:02.539306 [RX_INPUT] configuration <<<<<
2329 23:23:02.545955 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2330 23:23:02.549205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2331 23:23:02.555591 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2332 23:23:02.562460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2333 23:23:02.568703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2334 23:23:02.575514 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2335 23:23:02.578597 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2336 23:23:02.581684 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2337 23:23:02.589069 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2338 23:23:02.591786 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2339 23:23:02.595515 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2340 23:23:02.601614 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2341 23:23:02.605139 ===================================
2342 23:23:02.605222 LPDDR4 DRAM CONFIGURATION
2343 23:23:02.608384 ===================================
2344 23:23:02.612231 EX_ROW_EN[0] = 0x0
2345 23:23:02.612314 EX_ROW_EN[1] = 0x0
2346 23:23:02.615799 LP4Y_EN = 0x0
2347 23:23:02.615881 WORK_FSP = 0x0
2348 23:23:02.618459 WL = 0x4
2349 23:23:02.618540 RL = 0x4
2350 23:23:02.621838 BL = 0x2
2351 23:23:02.625338 RPST = 0x0
2352 23:23:02.625436 RD_PRE = 0x0
2353 23:23:02.628264 WR_PRE = 0x1
2354 23:23:02.628356 WR_PST = 0x0
2355 23:23:02.631823 DBI_WR = 0x0
2356 23:23:02.631901 DBI_RD = 0x0
2357 23:23:02.635006 OTF = 0x1
2358 23:23:02.638288 ===================================
2359 23:23:02.641464 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2360 23:23:02.645179 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2361 23:23:02.648440 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2362 23:23:02.651360 ===================================
2363 23:23:02.655053 LPDDR4 DRAM CONFIGURATION
2364 23:23:02.658476 ===================================
2365 23:23:02.661312 EX_ROW_EN[0] = 0x10
2366 23:23:02.661395 EX_ROW_EN[1] = 0x0
2367 23:23:02.664729 LP4Y_EN = 0x0
2368 23:23:02.664811 WORK_FSP = 0x0
2369 23:23:02.667803 WL = 0x4
2370 23:23:02.667884 RL = 0x4
2371 23:23:02.671166 BL = 0x2
2372 23:23:02.674433 RPST = 0x0
2373 23:23:02.674537 RD_PRE = 0x0
2374 23:23:02.677845 WR_PRE = 0x1
2375 23:23:02.677945 WR_PST = 0x0
2376 23:23:02.681347 DBI_WR = 0x0
2377 23:23:02.681428 DBI_RD = 0x0
2378 23:23:02.684330 OTF = 0x1
2379 23:23:02.687862 ===================================
2380 23:23:02.691332 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2381 23:23:02.694573 ==
2382 23:23:02.697839 Dram Type= 6, Freq= 0, CH_0, rank 0
2383 23:23:02.701309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2384 23:23:02.701409 ==
2385 23:23:02.704383 [Duty_Offset_Calibration]
2386 23:23:02.704493 B0:1 B1:-1 CA:0
2387 23:23:02.704588
2388 23:23:02.707597 [DutyScan_Calibration_Flow] k_type=0
2389 23:23:02.717661
2390 23:23:02.717774 ==CLK 0==
2391 23:23:02.720747 Final CLK duty delay cell = 0
2392 23:23:02.724340 [0] MAX Duty = 5125%(X100), DQS PI = 24
2393 23:23:02.727410 [0] MIN Duty = 4907%(X100), DQS PI = 6
2394 23:23:02.727532 [0] AVG Duty = 5016%(X100)
2395 23:23:02.730751
2396 23:23:02.734187 CH0 CLK Duty spec in!! Max-Min= 218%
2397 23:23:02.737061 [DutyScan_Calibration_Flow] ====Done====
2398 23:23:02.737143
2399 23:23:02.740516 [DutyScan_Calibration_Flow] k_type=1
2400 23:23:02.756254
2401 23:23:02.756338 ==DQS 0 ==
2402 23:23:02.759179 Final DQS duty delay cell = -4
2403 23:23:02.762436 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2404 23:23:02.766013 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2405 23:23:02.769446 [-4] AVG Duty = 4968%(X100)
2406 23:23:02.769528
2407 23:23:02.769593 ==DQS 1 ==
2408 23:23:02.772271 Final DQS duty delay cell = 0
2409 23:23:02.775773 [0] MAX Duty = 5124%(X100), DQS PI = 4
2410 23:23:02.779047 [0] MIN Duty = 5000%(X100), DQS PI = 24
2411 23:23:02.782546 [0] AVG Duty = 5062%(X100)
2412 23:23:02.782628
2413 23:23:02.785407 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2414 23:23:02.785491
2415 23:23:02.789167 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2416 23:23:02.792646 [DutyScan_Calibration_Flow] ====Done====
2417 23:23:02.792727
2418 23:23:02.795804 [DutyScan_Calibration_Flow] k_type=3
2419 23:23:02.813637
2420 23:23:02.813720 ==DQM 0 ==
2421 23:23:02.816978 Final DQM duty delay cell = 0
2422 23:23:02.819801 [0] MAX Duty = 5062%(X100), DQS PI = 18
2423 23:23:02.823142 [0] MIN Duty = 4875%(X100), DQS PI = 6
2424 23:23:02.826529 [0] AVG Duty = 4968%(X100)
2425 23:23:02.826610
2426 23:23:02.826674 ==DQM 1 ==
2427 23:23:02.830238 Final DQM duty delay cell = 4
2428 23:23:02.833031 [4] MAX Duty = 5187%(X100), DQS PI = 14
2429 23:23:02.836088 [4] MIN Duty = 5000%(X100), DQS PI = 24
2430 23:23:02.839903 [4] AVG Duty = 5093%(X100)
2431 23:23:02.839986
2432 23:23:02.842916 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2433 23:23:02.843002
2434 23:23:02.846450 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2435 23:23:02.849486 [DutyScan_Calibration_Flow] ====Done====
2436 23:23:02.849568
2437 23:23:02.853061 [DutyScan_Calibration_Flow] k_type=2
2438 23:23:02.869290
2439 23:23:02.869380 ==DQ 0 ==
2440 23:23:02.872732 Final DQ duty delay cell = -4
2441 23:23:02.875597 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2442 23:23:02.878833 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2443 23:23:02.882180 [-4] AVG Duty = 4969%(X100)
2444 23:23:02.882263
2445 23:23:02.882328 ==DQ 1 ==
2446 23:23:02.885951 Final DQ duty delay cell = 0
2447 23:23:02.888859 [0] MAX Duty = 5093%(X100), DQS PI = 2
2448 23:23:02.892194 [0] MIN Duty = 4969%(X100), DQS PI = 40
2449 23:23:02.892277 [0] AVG Duty = 5031%(X100)
2450 23:23:02.895594
2451 23:23:02.899379 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2452 23:23:02.899461
2453 23:23:02.902337 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2454 23:23:02.905789 [DutyScan_Calibration_Flow] ====Done====
2455 23:23:02.905873 ==
2456 23:23:02.909014 Dram Type= 6, Freq= 0, CH_1, rank 0
2457 23:23:02.912706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2458 23:23:02.912789 ==
2459 23:23:02.915799 [Duty_Offset_Calibration]
2460 23:23:02.915882 B0:-1 B1:1 CA:2
2461 23:23:02.915947
2462 23:23:02.918767 [DutyScan_Calibration_Flow] k_type=0
2463 23:23:02.929285
2464 23:23:02.929367 ==CLK 0==
2465 23:23:02.932982 Final CLK duty delay cell = 0
2466 23:23:02.935900 [0] MAX Duty = 5156%(X100), DQS PI = 22
2467 23:23:02.939500 [0] MIN Duty = 4969%(X100), DQS PI = 62
2468 23:23:02.942444 [0] AVG Duty = 5062%(X100)
2469 23:23:02.942526
2470 23:23:02.946069 CH1 CLK Duty spec in!! Max-Min= 187%
2471 23:23:02.949190 [DutyScan_Calibration_Flow] ====Done====
2472 23:23:02.949273
2473 23:23:02.952156 [DutyScan_Calibration_Flow] k_type=1
2474 23:23:02.968855
2475 23:23:02.968943 ==DQS 0 ==
2476 23:23:02.971714 Final DQS duty delay cell = 0
2477 23:23:02.974948 [0] MAX Duty = 5125%(X100), DQS PI = 48
2478 23:23:02.978482 [0] MIN Duty = 4875%(X100), DQS PI = 8
2479 23:23:02.982320 [0] AVG Duty = 5000%(X100)
2480 23:23:02.982485
2481 23:23:02.982577 ==DQS 1 ==
2482 23:23:02.985601 Final DQS duty delay cell = 0
2483 23:23:02.989055 [0] MAX Duty = 5062%(X100), DQS PI = 10
2484 23:23:02.992022 [0] MIN Duty = 4969%(X100), DQS PI = 56
2485 23:23:02.994998 [0] AVG Duty = 5015%(X100)
2486 23:23:02.995073
2487 23:23:02.998529 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2488 23:23:02.998599
2489 23:23:03.001811 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2490 23:23:03.004862 [DutyScan_Calibration_Flow] ====Done====
2491 23:23:03.004945
2492 23:23:03.008015 [DutyScan_Calibration_Flow] k_type=3
2493 23:23:03.024609
2494 23:23:03.024695 ==DQM 0 ==
2495 23:23:03.027545 Final DQM duty delay cell = -4
2496 23:23:03.030724 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2497 23:23:03.033870 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2498 23:23:03.037274 [-4] AVG Duty = 4953%(X100)
2499 23:23:03.037356
2500 23:23:03.037421 ==DQM 1 ==
2501 23:23:03.040618 Final DQM duty delay cell = 0
2502 23:23:03.044504 [0] MAX Duty = 5125%(X100), DQS PI = 2
2503 23:23:03.047248 [0] MIN Duty = 4969%(X100), DQS PI = 28
2504 23:23:03.050374 [0] AVG Duty = 5047%(X100)
2505 23:23:03.050448
2506 23:23:03.054252 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2507 23:23:03.054335
2508 23:23:03.057278 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2509 23:23:03.060681 [DutyScan_Calibration_Flow] ====Done====
2510 23:23:03.060764
2511 23:23:03.063837 [DutyScan_Calibration_Flow] k_type=2
2512 23:23:03.080673
2513 23:23:03.080759 ==DQ 0 ==
2514 23:23:03.084058 Final DQ duty delay cell = 0
2515 23:23:03.087634 [0] MAX Duty = 5218%(X100), DQS PI = 30
2516 23:23:03.091528 [0] MIN Duty = 4876%(X100), DQS PI = 8
2517 23:23:03.091603 [0] AVG Duty = 5047%(X100)
2518 23:23:03.091666
2519 23:23:03.094382 ==DQ 1 ==
2520 23:23:03.097765 Final DQ duty delay cell = 0
2521 23:23:03.100689 [0] MAX Duty = 5124%(X100), DQS PI = 10
2522 23:23:03.103896 [0] MIN Duty = 4969%(X100), DQS PI = 0
2523 23:23:03.103979 [0] AVG Duty = 5046%(X100)
2524 23:23:03.104045
2525 23:23:03.110689 CH1 DQ 0 Duty spec in!! Max-Min= 342%
2526 23:23:03.110867
2527 23:23:03.113993 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2528 23:23:03.117470 [DutyScan_Calibration_Flow] ====Done====
2529 23:23:03.121008 nWR fixed to 30
2530 23:23:03.121115 [ModeRegInit_LP4] CH0 RK0
2531 23:23:03.123874 [ModeRegInit_LP4] CH0 RK1
2532 23:23:03.126909 [ModeRegInit_LP4] CH1 RK0
2533 23:23:03.130295 [ModeRegInit_LP4] CH1 RK1
2534 23:23:03.130408 match AC timing 7
2535 23:23:03.133731 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2536 23:23:03.140625 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2537 23:23:03.143934 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2538 23:23:03.150285 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2539 23:23:03.153704 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2540 23:23:03.153788 ==
2541 23:23:03.156754 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 23:23:03.160741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 23:23:03.160826 ==
2544 23:23:03.167301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2545 23:23:03.173228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2546 23:23:03.180742 [CA 0] Center 39 (9~70) winsize 62
2547 23:23:03.184038 [CA 1] Center 39 (9~70) winsize 62
2548 23:23:03.187706 [CA 2] Center 35 (5~66) winsize 62
2549 23:23:03.190829 [CA 3] Center 35 (5~65) winsize 61
2550 23:23:03.193771 [CA 4] Center 33 (3~64) winsize 62
2551 23:23:03.197060 [CA 5] Center 33 (4~63) winsize 60
2552 23:23:03.197140
2553 23:23:03.200589 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2554 23:23:03.200670
2555 23:23:03.203684 [CATrainingPosCal] consider 1 rank data
2556 23:23:03.207164 u2DelayCellTimex100 = 270/100 ps
2557 23:23:03.210965 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2558 23:23:03.217086 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2559 23:23:03.220638 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2560 23:23:03.224001 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2561 23:23:03.227580 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2562 23:23:03.230323 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2563 23:23:03.230403
2564 23:23:03.234122 CA PerBit enable=1, Macro0, CA PI delay=33
2565 23:23:03.234213
2566 23:23:03.237090 [CBTSetCACLKResult] CA Dly = 33
2567 23:23:03.237169 CS Dly: 8 (0~39)
2568 23:23:03.240593 ==
2569 23:23:03.243489 Dram Type= 6, Freq= 0, CH_0, rank 1
2570 23:23:03.246842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 23:23:03.246924 ==
2572 23:23:03.251044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2573 23:23:03.257293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2574 23:23:03.266233 [CA 0] Center 39 (9~70) winsize 62
2575 23:23:03.270436 [CA 1] Center 39 (9~70) winsize 62
2576 23:23:03.273369 [CA 2] Center 35 (5~66) winsize 62
2577 23:23:03.276590 [CA 3] Center 34 (4~65) winsize 62
2578 23:23:03.279820 [CA 4] Center 33 (3~64) winsize 62
2579 23:23:03.283223 [CA 5] Center 33 (3~63) winsize 61
2580 23:23:03.283301
2581 23:23:03.286304 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2582 23:23:03.286388
2583 23:23:03.289783 [CATrainingPosCal] consider 2 rank data
2584 23:23:03.293260 u2DelayCellTimex100 = 270/100 ps
2585 23:23:03.295942 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2586 23:23:03.302945 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2587 23:23:03.305789 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2588 23:23:03.309371 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2589 23:23:03.312576 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2590 23:23:03.315910 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2591 23:23:03.316048
2592 23:23:03.319451 CA PerBit enable=1, Macro0, CA PI delay=33
2593 23:23:03.319580
2594 23:23:03.322860 [CBTSetCACLKResult] CA Dly = 33
2595 23:23:03.326023 CS Dly: 8 (0~40)
2596 23:23:03.326158
2597 23:23:03.329384 ----->DramcWriteLeveling(PI) begin...
2598 23:23:03.329522 ==
2599 23:23:03.332372 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 23:23:03.336071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 23:23:03.336192 ==
2602 23:23:03.339115 Write leveling (Byte 0): 32 => 32
2603 23:23:03.342872 Write leveling (Byte 1): 29 => 29
2604 23:23:03.345898 DramcWriteLeveling(PI) end<-----
2605 23:23:03.346011
2606 23:23:03.346104 ==
2607 23:23:03.349944 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 23:23:03.352544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 23:23:03.352652 ==
2610 23:23:03.356158 [Gating] SW mode calibration
2611 23:23:03.362292 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2612 23:23:03.369577 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2613 23:23:03.372467 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
2614 23:23:03.375642 0 15 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2615 23:23:03.382509 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2616 23:23:03.386193 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2617 23:23:03.388974 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2618 23:23:03.395895 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2619 23:23:03.399501 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2620 23:23:03.402482 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
2621 23:23:03.409228 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
2622 23:23:03.412485 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2623 23:23:03.415394 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2624 23:23:03.422506 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2625 23:23:03.425816 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2626 23:23:03.428707 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2627 23:23:03.435549 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2628 23:23:03.439113 1 0 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
2629 23:23:03.441816 1 1 0 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
2630 23:23:03.445724 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2631 23:23:03.452283 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2632 23:23:03.455738 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2633 23:23:03.461618 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2634 23:23:03.465046 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 23:23:03.468433 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2636 23:23:03.471685 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2637 23:23:03.478624 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2638 23:23:03.481948 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2639 23:23:03.485051 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 23:23:03.492092 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 23:23:03.495254 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 23:23:03.498465 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 23:23:03.504795 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 23:23:03.508622 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 23:23:03.511550 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 23:23:03.518077 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 23:23:03.521687 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 23:23:03.524818 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 23:23:03.532089 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2650 23:23:03.535050 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2651 23:23:03.538055 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2652 23:23:03.544665 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2653 23:23:03.548052 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2654 23:23:03.551157 Total UI for P1: 0, mck2ui 16
2655 23:23:03.554790 best dqsien dly found for B0: ( 1, 3, 26)
2656 23:23:03.558402 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2657 23:23:03.564510 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2658 23:23:03.564598 Total UI for P1: 0, mck2ui 16
2659 23:23:03.571186 best dqsien dly found for B1: ( 1, 4, 2)
2660 23:23:03.574969 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2661 23:23:03.577764 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2662 23:23:03.577847
2663 23:23:03.581503 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2664 23:23:03.584644 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2665 23:23:03.587971 [Gating] SW calibration Done
2666 23:23:03.588055 ==
2667 23:23:03.591422 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 23:23:03.594811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 23:23:03.594895 ==
2670 23:23:03.598035 RX Vref Scan: 0
2671 23:23:03.598119
2672 23:23:03.598185 RX Vref 0 -> 0, step: 1
2673 23:23:03.598247
2674 23:23:03.600985 RX Delay -40 -> 252, step: 8
2675 23:23:03.604266 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2676 23:23:03.611338 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2677 23:23:03.614653 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2678 23:23:03.617761 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2679 23:23:03.620677 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2680 23:23:03.624171 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2681 23:23:03.630667 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2682 23:23:03.634070 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2683 23:23:03.637547 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2684 23:23:03.640558 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2685 23:23:03.644309 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2686 23:23:03.650884 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2687 23:23:03.654240 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2688 23:23:03.657347 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2689 23:23:03.660795 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2690 23:23:03.663850 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2691 23:23:03.667392 ==
2692 23:23:03.670435 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 23:23:03.674238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 23:23:03.674322 ==
2695 23:23:03.674388 DQS Delay:
2696 23:23:03.677323 DQS0 = 0, DQS1 = 0
2697 23:23:03.677407 DQM Delay:
2698 23:23:03.680325 DQM0 = 119, DQM1 = 106
2699 23:23:03.680409 DQ Delay:
2700 23:23:03.683783 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2701 23:23:03.687074 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2702 23:23:03.690192 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2703 23:23:03.693459 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2704 23:23:03.693543
2705 23:23:03.693610
2706 23:23:03.693670 ==
2707 23:23:03.696988 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 23:23:03.703617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 23:23:03.703763 ==
2710 23:23:03.703832
2711 23:23:03.703894
2712 23:23:03.706980 TX Vref Scan disable
2713 23:23:03.707062 == TX Byte 0 ==
2714 23:23:03.710578 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2715 23:23:03.716741 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2716 23:23:03.716826 == TX Byte 1 ==
2717 23:23:03.720343 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2718 23:23:03.726350 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2719 23:23:03.726433 ==
2720 23:23:03.730076 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 23:23:03.733314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 23:23:03.733425 ==
2723 23:23:03.745548 TX Vref=22, minBit 5, minWin=24, winSum=418
2724 23:23:03.748952 TX Vref=24, minBit 1, minWin=26, winSum=428
2725 23:23:03.751936 TX Vref=26, minBit 1, minWin=26, winSum=432
2726 23:23:03.755142 TX Vref=28, minBit 5, minWin=26, winSum=434
2727 23:23:03.758587 TX Vref=30, minBit 5, minWin=26, winSum=435
2728 23:23:03.765227 TX Vref=32, minBit 1, minWin=26, winSum=429
2729 23:23:03.768414 [TxChooseVref] Worse bit 5, Min win 26, Win sum 435, Final Vref 30
2730 23:23:03.768501
2731 23:23:03.771464 Final TX Range 1 Vref 30
2732 23:23:03.771550
2733 23:23:03.771617 ==
2734 23:23:03.774989 Dram Type= 6, Freq= 0, CH_0, rank 0
2735 23:23:03.778133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2736 23:23:03.781710 ==
2737 23:23:03.781887
2738 23:23:03.781953
2739 23:23:03.782014 TX Vref Scan disable
2740 23:23:03.784900 == TX Byte 0 ==
2741 23:23:03.788228 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2742 23:23:03.794990 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2743 23:23:03.795074 == TX Byte 1 ==
2744 23:23:03.798319 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2745 23:23:03.804603 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2746 23:23:03.804701
2747 23:23:03.804822 [DATLAT]
2748 23:23:03.804899 Freq=1200, CH0 RK0
2749 23:23:03.804985
2750 23:23:03.807685 DATLAT Default: 0xd
2751 23:23:03.811123 0, 0xFFFF, sum = 0
2752 23:23:03.811207 1, 0xFFFF, sum = 0
2753 23:23:03.814509 2, 0xFFFF, sum = 0
2754 23:23:03.814608 3, 0xFFFF, sum = 0
2755 23:23:03.818142 4, 0xFFFF, sum = 0
2756 23:23:03.818241 5, 0xFFFF, sum = 0
2757 23:23:03.821166 6, 0xFFFF, sum = 0
2758 23:23:03.821250 7, 0xFFFF, sum = 0
2759 23:23:03.824992 8, 0xFFFF, sum = 0
2760 23:23:03.825078 9, 0xFFFF, sum = 0
2761 23:23:03.828317 10, 0xFFFF, sum = 0
2762 23:23:03.828401 11, 0xFFFF, sum = 0
2763 23:23:03.831018 12, 0x0, sum = 1
2764 23:23:03.831143 13, 0x0, sum = 2
2765 23:23:03.834522 14, 0x0, sum = 3
2766 23:23:03.834607 15, 0x0, sum = 4
2767 23:23:03.837900 best_step = 13
2768 23:23:03.837997
2769 23:23:03.838061 ==
2770 23:23:03.841071 Dram Type= 6, Freq= 0, CH_0, rank 0
2771 23:23:03.844745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2772 23:23:03.844829 ==
2773 23:23:03.844896 RX Vref Scan: 1
2774 23:23:03.848007
2775 23:23:03.848089 Set Vref Range= 32 -> 127
2776 23:23:03.848155
2777 23:23:03.851263 RX Vref 32 -> 127, step: 1
2778 23:23:03.851345
2779 23:23:03.854251 RX Delay -21 -> 252, step: 4
2780 23:23:03.854334
2781 23:23:03.857930 Set Vref, RX VrefLevel [Byte0]: 32
2782 23:23:03.860931 [Byte1]: 32
2783 23:23:03.861015
2784 23:23:03.864303 Set Vref, RX VrefLevel [Byte0]: 33
2785 23:23:03.867611 [Byte1]: 33
2786 23:23:03.871898
2787 23:23:03.871981 Set Vref, RX VrefLevel [Byte0]: 34
2788 23:23:03.874708 [Byte1]: 34
2789 23:23:03.879542
2790 23:23:03.879627 Set Vref, RX VrefLevel [Byte0]: 35
2791 23:23:03.882733 [Byte1]: 35
2792 23:23:03.887489
2793 23:23:03.887574 Set Vref, RX VrefLevel [Byte0]: 36
2794 23:23:03.890362 [Byte1]: 36
2795 23:23:03.895838
2796 23:23:03.895921 Set Vref, RX VrefLevel [Byte0]: 37
2797 23:23:03.898673 [Byte1]: 37
2798 23:23:03.903122
2799 23:23:03.903219 Set Vref, RX VrefLevel [Byte0]: 38
2800 23:23:03.906458 [Byte1]: 38
2801 23:23:03.911188
2802 23:23:03.911271 Set Vref, RX VrefLevel [Byte0]: 39
2803 23:23:03.914771 [Byte1]: 39
2804 23:23:03.919177
2805 23:23:03.919260 Set Vref, RX VrefLevel [Byte0]: 40
2806 23:23:03.925665 [Byte1]: 40
2807 23:23:03.925748
2808 23:23:03.928894 Set Vref, RX VrefLevel [Byte0]: 41
2809 23:23:03.932138 [Byte1]: 41
2810 23:23:03.932224
2811 23:23:03.935376 Set Vref, RX VrefLevel [Byte0]: 42
2812 23:23:03.938385 [Byte1]: 42
2813 23:23:03.942779
2814 23:23:03.942862 Set Vref, RX VrefLevel [Byte0]: 43
2815 23:23:03.946096 [Byte1]: 43
2816 23:23:03.950869
2817 23:23:03.950975 Set Vref, RX VrefLevel [Byte0]: 44
2818 23:23:03.954012 [Byte1]: 44
2819 23:23:03.958381
2820 23:23:03.958464 Set Vref, RX VrefLevel [Byte0]: 45
2821 23:23:03.961920 [Byte1]: 45
2822 23:23:03.966455
2823 23:23:03.966580 Set Vref, RX VrefLevel [Byte0]: 46
2824 23:23:03.969880 [Byte1]: 46
2825 23:23:03.974763
2826 23:23:03.974845 Set Vref, RX VrefLevel [Byte0]: 47
2827 23:23:03.978005 [Byte1]: 47
2828 23:23:03.982745
2829 23:23:03.982827 Set Vref, RX VrefLevel [Byte0]: 48
2830 23:23:03.985716 [Byte1]: 48
2831 23:23:03.990737
2832 23:23:03.990820 Set Vref, RX VrefLevel [Byte0]: 49
2833 23:23:03.993707 [Byte1]: 49
2834 23:23:03.998426
2835 23:23:03.998508 Set Vref, RX VrefLevel [Byte0]: 50
2836 23:23:04.001326 [Byte1]: 50
2837 23:23:04.006158
2838 23:23:04.006270 Set Vref, RX VrefLevel [Byte0]: 51
2839 23:23:04.009550 [Byte1]: 51
2840 23:23:04.014566
2841 23:23:04.014647 Set Vref, RX VrefLevel [Byte0]: 52
2842 23:23:04.017398 [Byte1]: 52
2843 23:23:04.022573
2844 23:23:04.022655 Set Vref, RX VrefLevel [Byte0]: 53
2845 23:23:04.025564 [Byte1]: 53
2846 23:23:04.029923
2847 23:23:04.030005 Set Vref, RX VrefLevel [Byte0]: 54
2848 23:23:04.033903 [Byte1]: 54
2849 23:23:04.037941
2850 23:23:04.038050 Set Vref, RX VrefLevel [Byte0]: 55
2851 23:23:04.041576 [Byte1]: 55
2852 23:23:04.046105
2853 23:23:04.046188 Set Vref, RX VrefLevel [Byte0]: 56
2854 23:23:04.049166 [Byte1]: 56
2855 23:23:04.053632
2856 23:23:04.056724 Set Vref, RX VrefLevel [Byte0]: 57
2857 23:23:04.060063 [Byte1]: 57
2858 23:23:04.060146
2859 23:23:04.063977 Set Vref, RX VrefLevel [Byte0]: 58
2860 23:23:04.066829 [Byte1]: 58
2861 23:23:04.066922
2862 23:23:04.070655 Set Vref, RX VrefLevel [Byte0]: 59
2863 23:23:04.073316 [Byte1]: 59
2864 23:23:04.077442
2865 23:23:04.077524 Set Vref, RX VrefLevel [Byte0]: 60
2866 23:23:04.080880 [Byte1]: 60
2867 23:23:04.085413
2868 23:23:04.085531 Set Vref, RX VrefLevel [Byte0]: 61
2869 23:23:04.088910 [Byte1]: 61
2870 23:23:04.093353
2871 23:23:04.093435 Set Vref, RX VrefLevel [Byte0]: 62
2872 23:23:04.096681 [Byte1]: 62
2873 23:23:04.101243
2874 23:23:04.101325 Set Vref, RX VrefLevel [Byte0]: 63
2875 23:23:04.105767 [Byte1]: 63
2876 23:23:04.109710
2877 23:23:04.109793 Set Vref, RX VrefLevel [Byte0]: 64
2878 23:23:04.112448 [Byte1]: 64
2879 23:23:04.117464
2880 23:23:04.117559 Set Vref, RX VrefLevel [Byte0]: 65
2881 23:23:04.120339 [Byte1]: 65
2882 23:23:04.125197
2883 23:23:04.125290 Set Vref, RX VrefLevel [Byte0]: 66
2884 23:23:04.128780 [Byte1]: 66
2885 23:23:04.132949
2886 23:23:04.133032 Set Vref, RX VrefLevel [Byte0]: 67
2887 23:23:04.136453 [Byte1]: 67
2888 23:23:04.140666
2889 23:23:04.140769 Set Vref, RX VrefLevel [Byte0]: 68
2890 23:23:04.144012 [Byte1]: 68
2891 23:23:04.148933
2892 23:23:04.149037 Set Vref, RX VrefLevel [Byte0]: 69
2893 23:23:04.152340 [Byte1]: 69
2894 23:23:04.156531
2895 23:23:04.156637 Set Vref, RX VrefLevel [Byte0]: 70
2896 23:23:04.160230 [Byte1]: 70
2897 23:23:04.164615
2898 23:23:04.164722 Set Vref, RX VrefLevel [Byte0]: 71
2899 23:23:04.168029 [Byte1]: 71
2900 23:23:04.172482
2901 23:23:04.172564 Set Vref, RX VrefLevel [Byte0]: 72
2902 23:23:04.175585 [Byte1]: 72
2903 23:23:04.180482
2904 23:23:04.180564 Set Vref, RX VrefLevel [Byte0]: 73
2905 23:23:04.183881 [Byte1]: 73
2906 23:23:04.188506
2907 23:23:04.188614 Set Vref, RX VrefLevel [Byte0]: 74
2908 23:23:04.191890 [Byte1]: 74
2909 23:23:04.196630
2910 23:23:04.196714 Set Vref, RX VrefLevel [Byte0]: 75
2911 23:23:04.199607 [Byte1]: 75
2912 23:23:04.204062
2913 23:23:04.204147 Set Vref, RX VrefLevel [Byte0]: 76
2914 23:23:04.207591 [Byte1]: 76
2915 23:23:04.212195
2916 23:23:04.212279 Set Vref, RX VrefLevel [Byte0]: 77
2917 23:23:04.215291 [Byte1]: 77
2918 23:23:04.220430
2919 23:23:04.220514 Final RX Vref Byte 0 = 61 to rank0
2920 23:23:04.223689 Final RX Vref Byte 1 = 54 to rank0
2921 23:23:04.226927 Final RX Vref Byte 0 = 61 to rank1
2922 23:23:04.230159 Final RX Vref Byte 1 = 54 to rank1==
2923 23:23:04.233157 Dram Type= 6, Freq= 0, CH_0, rank 0
2924 23:23:04.239662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 23:23:04.239757 ==
2926 23:23:04.239825 DQS Delay:
2927 23:23:04.243559 DQS0 = 0, DQS1 = 0
2928 23:23:04.243644 DQM Delay:
2929 23:23:04.243723 DQM0 = 119, DQM1 = 107
2930 23:23:04.246620 DQ Delay:
2931 23:23:04.249857 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2932 23:23:04.253473 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =126
2933 23:23:04.257004 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
2934 23:23:04.259538 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =114
2935 23:23:04.259622
2936 23:23:04.259703
2937 23:23:04.269931 [DQSOSCAuto] RK0, (LSB)MR18= 0xcf8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 405 ps
2938 23:23:04.270027 CH0 RK0: MR19=403, MR18=CF8
2939 23:23:04.276371 CH0_RK0: MR19=0x403, MR18=0xCF8, DQSOSC=405, MR23=63, INC=39, DEC=26
2940 23:23:04.276461
2941 23:23:04.279433 ----->DramcWriteLeveling(PI) begin...
2942 23:23:04.279545 ==
2943 23:23:04.282730 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 23:23:04.289844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 23:23:04.289928 ==
2946 23:23:04.292665 Write leveling (Byte 0): 32 => 32
2947 23:23:04.292748 Write leveling (Byte 1): 32 => 32
2948 23:23:04.296185 DramcWriteLeveling(PI) end<-----
2949 23:23:04.296307
2950 23:23:04.296402 ==
2951 23:23:04.299665 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 23:23:04.306749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 23:23:04.306835 ==
2954 23:23:04.309784 [Gating] SW mode calibration
2955 23:23:04.316483 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2956 23:23:04.319431 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2957 23:23:04.326108 0 15 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
2958 23:23:04.329328 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2959 23:23:04.332546 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2960 23:23:04.339745 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2961 23:23:04.342617 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2962 23:23:04.346077 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2963 23:23:04.352643 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2964 23:23:04.355783 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2965 23:23:04.359445 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2966 23:23:04.365756 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2967 23:23:04.369377 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2968 23:23:04.372229 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2969 23:23:04.378705 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2970 23:23:04.382668 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 23:23:04.385587 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 23:23:04.391919 1 0 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2973 23:23:04.395891 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2974 23:23:04.398741 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 23:23:04.402638 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 23:23:04.408820 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 23:23:04.412192 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 23:23:04.415828 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 23:23:04.421844 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 23:23:04.426005 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2981 23:23:04.428671 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2982 23:23:04.435062 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 23:23:04.438637 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 23:23:04.442584 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 23:23:04.448339 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 23:23:04.452291 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 23:23:04.454977 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 23:23:04.462028 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 23:23:04.465619 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 23:23:04.468293 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 23:23:04.475107 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 23:23:04.478618 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 23:23:04.481600 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 23:23:04.488233 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 23:23:04.491923 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 23:23:04.494576 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2997 23:23:04.501657 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2998 23:23:04.501743 Total UI for P1: 0, mck2ui 16
2999 23:23:04.508366 best dqsien dly found for B0: ( 1, 3, 28)
3000 23:23:04.511765 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3001 23:23:04.514679 Total UI for P1: 0, mck2ui 16
3002 23:23:04.518355 best dqsien dly found for B1: ( 1, 3, 30)
3003 23:23:04.521680 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3004 23:23:04.525206 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3005 23:23:04.525307
3006 23:23:04.528377 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3007 23:23:04.531445 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3008 23:23:04.534844 [Gating] SW calibration Done
3009 23:23:04.534971 ==
3010 23:23:04.538415 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 23:23:04.541625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 23:23:04.541719 ==
3013 23:23:04.544975 RX Vref Scan: 0
3014 23:23:04.545067
3015 23:23:04.548021 RX Vref 0 -> 0, step: 1
3016 23:23:04.548109
3017 23:23:04.548177 RX Delay -40 -> 252, step: 8
3018 23:23:04.554848 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3019 23:23:04.558248 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3020 23:23:04.561750 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3021 23:23:04.565151 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3022 23:23:04.568575 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3023 23:23:04.575057 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3024 23:23:04.578602 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3025 23:23:04.581245 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3026 23:23:04.584636 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3027 23:23:04.588239 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3028 23:23:04.594800 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3029 23:23:04.597684 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3030 23:23:04.601269 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3031 23:23:04.604927 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3032 23:23:04.610855 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3033 23:23:04.613918 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3034 23:23:04.614021 ==
3035 23:23:04.617614 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 23:23:04.621353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 23:23:04.621427 ==
3038 23:23:04.624118 DQS Delay:
3039 23:23:04.624191 DQS0 = 0, DQS1 = 0
3040 23:23:04.624252 DQM Delay:
3041 23:23:04.627872 DQM0 = 116, DQM1 = 108
3042 23:23:04.627943 DQ Delay:
3043 23:23:04.630799 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3044 23:23:04.633729 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3045 23:23:04.637241 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3046 23:23:04.643963 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =115
3047 23:23:04.644046
3048 23:23:04.644113
3049 23:23:04.644174 ==
3050 23:23:04.647064 Dram Type= 6, Freq= 0, CH_0, rank 1
3051 23:23:04.650165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 23:23:04.650249 ==
3053 23:23:04.650321
3054 23:23:04.650384
3055 23:23:04.653510 TX Vref Scan disable
3056 23:23:04.653665 == TX Byte 0 ==
3057 23:23:04.660865 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3058 23:23:04.663861 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3059 23:23:04.663968 == TX Byte 1 ==
3060 23:23:04.670109 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3061 23:23:04.673384 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3062 23:23:04.673460 ==
3063 23:23:04.677228 Dram Type= 6, Freq= 0, CH_0, rank 1
3064 23:23:04.680839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 23:23:04.680940 ==
3066 23:23:04.693478 TX Vref=22, minBit 5, minWin=25, winSum=420
3067 23:23:04.696949 TX Vref=24, minBit 0, minWin=26, winSum=426
3068 23:23:04.699880 TX Vref=26, minBit 2, minWin=26, winSum=431
3069 23:23:04.703137 TX Vref=28, minBit 5, minWin=26, winSum=430
3070 23:23:04.706234 TX Vref=30, minBit 12, minWin=26, winSum=430
3071 23:23:04.712780 TX Vref=32, minBit 12, minWin=26, winSum=431
3072 23:23:04.716217 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 26
3073 23:23:04.716302
3074 23:23:04.719569 Final TX Range 1 Vref 26
3075 23:23:04.719653
3076 23:23:04.719756 ==
3077 23:23:04.722847 Dram Type= 6, Freq= 0, CH_0, rank 1
3078 23:23:04.726658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 23:23:04.729215 ==
3080 23:23:04.729298
3081 23:23:04.729363
3082 23:23:04.729424 TX Vref Scan disable
3083 23:23:04.733403 == TX Byte 0 ==
3084 23:23:04.736318 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3085 23:23:04.743581 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3086 23:23:04.743705 == TX Byte 1 ==
3087 23:23:04.746159 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3088 23:23:04.753063 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3089 23:23:04.753169
3090 23:23:04.753262 [DATLAT]
3091 23:23:04.753355 Freq=1200, CH0 RK1
3092 23:23:04.756248
3093 23:23:04.756325 DATLAT Default: 0xd
3094 23:23:04.759105 0, 0xFFFF, sum = 0
3095 23:23:04.759208 1, 0xFFFF, sum = 0
3096 23:23:04.762562 2, 0xFFFF, sum = 0
3097 23:23:04.762676 3, 0xFFFF, sum = 0
3098 23:23:04.766027 4, 0xFFFF, sum = 0
3099 23:23:04.766149 5, 0xFFFF, sum = 0
3100 23:23:04.769291 6, 0xFFFF, sum = 0
3101 23:23:04.769397 7, 0xFFFF, sum = 0
3102 23:23:04.772759 8, 0xFFFF, sum = 0
3103 23:23:04.772847 9, 0xFFFF, sum = 0
3104 23:23:04.775560 10, 0xFFFF, sum = 0
3105 23:23:04.775646 11, 0xFFFF, sum = 0
3106 23:23:04.779024 12, 0x0, sum = 1
3107 23:23:04.779122 13, 0x0, sum = 2
3108 23:23:04.782970 14, 0x0, sum = 3
3109 23:23:04.783072 15, 0x0, sum = 4
3110 23:23:04.785958 best_step = 13
3111 23:23:04.786040
3112 23:23:04.786105 ==
3113 23:23:04.789066 Dram Type= 6, Freq= 0, CH_0, rank 1
3114 23:23:04.792524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 23:23:04.792608 ==
3116 23:23:04.795509 RX Vref Scan: 0
3117 23:23:04.795616
3118 23:23:04.795742 RX Vref 0 -> 0, step: 1
3119 23:23:04.795806
3120 23:23:04.798937 RX Delay -21 -> 252, step: 4
3121 23:23:04.805964 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3122 23:23:04.809138 iDelay=195, Bit 1, Center 120 (47 ~ 194) 148
3123 23:23:04.812292 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3124 23:23:04.815615 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3125 23:23:04.818958 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3126 23:23:04.825722 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3127 23:23:04.828534 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3128 23:23:04.832072 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3129 23:23:04.835297 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3130 23:23:04.838590 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3131 23:23:04.845283 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3132 23:23:04.848679 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3133 23:23:04.852011 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3134 23:23:04.854966 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3135 23:23:04.861458 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3136 23:23:04.865413 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3137 23:23:04.865519 ==
3138 23:23:04.868739 Dram Type= 6, Freq= 0, CH_0, rank 1
3139 23:23:04.872178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3140 23:23:04.872280 ==
3141 23:23:04.872374 DQS Delay:
3142 23:23:04.875371 DQS0 = 0, DQS1 = 0
3143 23:23:04.875492 DQM Delay:
3144 23:23:04.878282 DQM0 = 116, DQM1 = 108
3145 23:23:04.878386 DQ Delay:
3146 23:23:04.881553 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =112
3147 23:23:04.884823 DQ4 =116, DQ5 =112, DQ6 =124, DQ7 =124
3148 23:23:04.888369 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
3149 23:23:04.891400 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =116
3150 23:23:04.895274
3151 23:23:04.895377
3152 23:23:04.902174 [DQSOSCAuto] RK1, (LSB)MR18= 0xde8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3153 23:23:04.904418 CH0 RK1: MR19=403, MR18=DE8
3154 23:23:04.911443 CH0_RK1: MR19=0x403, MR18=0xDE8, DQSOSC=405, MR23=63, INC=39, DEC=26
3155 23:23:04.914276 [RxdqsGatingPostProcess] freq 1200
3156 23:23:04.918068 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3157 23:23:04.921475 best DQS0 dly(2T, 0.5T) = (0, 11)
3158 23:23:04.924164 best DQS1 dly(2T, 0.5T) = (0, 12)
3159 23:23:04.928256 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3160 23:23:04.931182 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3161 23:23:04.934184 best DQS0 dly(2T, 0.5T) = (0, 11)
3162 23:23:04.937665 best DQS1 dly(2T, 0.5T) = (0, 11)
3163 23:23:04.941261 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3164 23:23:04.944085 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3165 23:23:04.947845 Pre-setting of DQS Precalculation
3166 23:23:04.951171 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3167 23:23:04.951241 ==
3168 23:23:04.954186 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 23:23:04.960715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 23:23:04.960792 ==
3171 23:23:04.964145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3172 23:23:04.970654 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3173 23:23:04.979094 [CA 0] Center 37 (7~68) winsize 62
3174 23:23:04.982334 [CA 1] Center 38 (8~68) winsize 61
3175 23:23:04.986096 [CA 2] Center 34 (4~64) winsize 61
3176 23:23:04.989509 [CA 3] Center 33 (3~64) winsize 62
3177 23:23:04.992381 [CA 4] Center 34 (4~64) winsize 61
3178 23:23:04.995784 [CA 5] Center 33 (3~64) winsize 62
3179 23:23:04.995854
3180 23:23:04.998815 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3181 23:23:04.998912
3182 23:23:05.002606 [CATrainingPosCal] consider 1 rank data
3183 23:23:05.005599 u2DelayCellTimex100 = 270/100 ps
3184 23:23:05.009237 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3185 23:23:05.015886 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3186 23:23:05.019062 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3187 23:23:05.022369 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3188 23:23:05.025475 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3189 23:23:05.028680 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3190 23:23:05.028757
3191 23:23:05.032238 CA PerBit enable=1, Macro0, CA PI delay=33
3192 23:23:05.032377
3193 23:23:05.035989 [CBTSetCACLKResult] CA Dly = 33
3194 23:23:05.036060 CS Dly: 6 (0~37)
3195 23:23:05.038870 ==
3196 23:23:05.042002 Dram Type= 6, Freq= 0, CH_1, rank 1
3197 23:23:05.045426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 23:23:05.045526 ==
3199 23:23:05.048929 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3200 23:23:05.055665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3201 23:23:05.064886 [CA 0] Center 37 (7~68) winsize 62
3202 23:23:05.068157 [CA 1] Center 38 (8~68) winsize 61
3203 23:23:05.071423 [CA 2] Center 34 (4~65) winsize 62
3204 23:23:05.074877 [CA 3] Center 33 (3~64) winsize 62
3205 23:23:05.078384 [CA 4] Center 34 (4~65) winsize 62
3206 23:23:05.081120 [CA 5] Center 33 (3~64) winsize 62
3207 23:23:05.081221
3208 23:23:05.084587 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3209 23:23:05.084691
3210 23:23:05.088355 [CATrainingPosCal] consider 2 rank data
3211 23:23:05.091853 u2DelayCellTimex100 = 270/100 ps
3212 23:23:05.094835 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3213 23:23:05.098264 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3214 23:23:05.105174 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3215 23:23:05.107961 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3216 23:23:05.111151 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3217 23:23:05.114593 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3218 23:23:05.114667
3219 23:23:05.118015 CA PerBit enable=1, Macro0, CA PI delay=33
3220 23:23:05.118124
3221 23:23:05.121158 [CBTSetCACLKResult] CA Dly = 33
3222 23:23:05.124478 CS Dly: 7 (0~40)
3223 23:23:05.124583
3224 23:23:05.127677 ----->DramcWriteLeveling(PI) begin...
3225 23:23:05.127760 ==
3226 23:23:05.131381 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 23:23:05.134160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 23:23:05.134265 ==
3229 23:23:05.137603 Write leveling (Byte 0): 24 => 24
3230 23:23:05.140943 Write leveling (Byte 1): 26 => 26
3231 23:23:05.144653 DramcWriteLeveling(PI) end<-----
3232 23:23:05.144761
3233 23:23:05.144858 ==
3234 23:23:05.147759 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 23:23:05.150996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 23:23:05.151072 ==
3237 23:23:05.154125 [Gating] SW mode calibration
3238 23:23:05.160523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3239 23:23:05.167775 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3240 23:23:05.171035 0 15 0 | B1->B0 | 3030 3434 | 1 0 | (1 1) (0 0)
3241 23:23:05.174295 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3242 23:23:05.180613 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3243 23:23:05.183820 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3244 23:23:05.187420 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3245 23:23:05.194007 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3246 23:23:05.197102 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
3247 23:23:05.200424 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (1 0)
3248 23:23:05.207302 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3249 23:23:05.210656 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3250 23:23:05.214052 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3251 23:23:05.220706 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3252 23:23:05.223693 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3253 23:23:05.226967 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3254 23:23:05.233836 1 0 24 | B1->B0 | 2727 3939 | 0 0 | (0 0) (0 0)
3255 23:23:05.237104 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3256 23:23:05.240344 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3257 23:23:05.247129 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3258 23:23:05.250376 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3259 23:23:05.253374 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3260 23:23:05.260429 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3261 23:23:05.263340 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3262 23:23:05.266767 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3263 23:23:05.273512 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3264 23:23:05.276753 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 23:23:05.279713 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 23:23:05.286977 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 23:23:05.290000 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 23:23:05.293327 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 23:23:05.296763 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 23:23:05.303288 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 23:23:05.306539 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 23:23:05.310013 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 23:23:05.316539 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 23:23:05.319758 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 23:23:05.323614 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 23:23:05.329814 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 23:23:05.333131 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 23:23:05.336491 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3279 23:23:05.343266 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3280 23:23:05.346680 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3281 23:23:05.349839 Total UI for P1: 0, mck2ui 16
3282 23:23:05.353145 best dqsien dly found for B0: ( 1, 3, 26)
3283 23:23:05.356181 Total UI for P1: 0, mck2ui 16
3284 23:23:05.359430 best dqsien dly found for B1: ( 1, 3, 26)
3285 23:23:05.362622 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3286 23:23:05.365976 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3287 23:23:05.366069
3288 23:23:05.369154 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3289 23:23:05.372889 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3290 23:23:05.376419 [Gating] SW calibration Done
3291 23:23:05.376500 ==
3292 23:23:05.379080 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 23:23:05.385655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 23:23:05.385769 ==
3295 23:23:05.385862 RX Vref Scan: 0
3296 23:23:05.385939
3297 23:23:05.389584 RX Vref 0 -> 0, step: 1
3298 23:23:05.389677
3299 23:23:05.392763 RX Delay -40 -> 252, step: 8
3300 23:23:05.395708 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3301 23:23:05.399086 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3302 23:23:05.402667 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3303 23:23:05.409412 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3304 23:23:05.412340 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3305 23:23:05.415574 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3306 23:23:05.418862 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3307 23:23:05.422058 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3308 23:23:05.429186 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3309 23:23:05.432208 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3310 23:23:05.435424 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3311 23:23:05.438780 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3312 23:23:05.441804 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3313 23:23:05.448755 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3314 23:23:05.452031 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3315 23:23:05.455171 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3316 23:23:05.455291 ==
3317 23:23:05.458724 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 23:23:05.461563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 23:23:05.461669 ==
3320 23:23:05.464940 DQS Delay:
3321 23:23:05.465042 DQS0 = 0, DQS1 = 0
3322 23:23:05.468315 DQM Delay:
3323 23:23:05.468424 DQM0 = 118, DQM1 = 108
3324 23:23:05.471719 DQ Delay:
3325 23:23:05.475102 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3326 23:23:05.478242 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3327 23:23:05.481351 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3328 23:23:05.484793 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3329 23:23:05.484919
3330 23:23:05.485019
3331 23:23:05.485119 ==
3332 23:23:05.488071 Dram Type= 6, Freq= 0, CH_1, rank 0
3333 23:23:05.491593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3334 23:23:05.491716 ==
3335 23:23:05.491805
3336 23:23:05.491869
3337 23:23:05.494952 TX Vref Scan disable
3338 23:23:05.498136 == TX Byte 0 ==
3339 23:23:05.501684 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3340 23:23:05.504923 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3341 23:23:05.507980 == TX Byte 1 ==
3342 23:23:05.511858 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3343 23:23:05.514767 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3344 23:23:05.514878 ==
3345 23:23:05.518244 Dram Type= 6, Freq= 0, CH_1, rank 0
3346 23:23:05.521599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3347 23:23:05.524710 ==
3348 23:23:05.534651 TX Vref=22, minBit 10, minWin=25, winSum=416
3349 23:23:05.537700 TX Vref=24, minBit 9, minWin=25, winSum=420
3350 23:23:05.541546 TX Vref=26, minBit 11, minWin=25, winSum=428
3351 23:23:05.544526 TX Vref=28, minBit 9, minWin=26, winSum=433
3352 23:23:05.548134 TX Vref=30, minBit 9, minWin=26, winSum=433
3353 23:23:05.554111 TX Vref=32, minBit 9, minWin=25, winSum=423
3354 23:23:05.558118 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
3355 23:23:05.558233
3356 23:23:05.560667 Final TX Range 1 Vref 28
3357 23:23:05.560774
3358 23:23:05.560879 ==
3359 23:23:05.564014 Dram Type= 6, Freq= 0, CH_1, rank 0
3360 23:23:05.570966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3361 23:23:05.571054 ==
3362 23:23:05.571122
3363 23:23:05.571183
3364 23:23:05.571243 TX Vref Scan disable
3365 23:23:05.574660 == TX Byte 0 ==
3366 23:23:05.577657 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3367 23:23:05.584383 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3368 23:23:05.584467 == TX Byte 1 ==
3369 23:23:05.587796 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3370 23:23:05.594130 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3371 23:23:05.594213
3372 23:23:05.594277 [DATLAT]
3373 23:23:05.594338 Freq=1200, CH1 RK0
3374 23:23:05.594414
3375 23:23:05.597783 DATLAT Default: 0xd
3376 23:23:05.600608 0, 0xFFFF, sum = 0
3377 23:23:05.600692 1, 0xFFFF, sum = 0
3378 23:23:05.604257 2, 0xFFFF, sum = 0
3379 23:23:05.604385 3, 0xFFFF, sum = 0
3380 23:23:05.606978 4, 0xFFFF, sum = 0
3381 23:23:05.607057 5, 0xFFFF, sum = 0
3382 23:23:05.610406 6, 0xFFFF, sum = 0
3383 23:23:05.610489 7, 0xFFFF, sum = 0
3384 23:23:05.613921 8, 0xFFFF, sum = 0
3385 23:23:05.613999 9, 0xFFFF, sum = 0
3386 23:23:05.617482 10, 0xFFFF, sum = 0
3387 23:23:05.617558 11, 0xFFFF, sum = 0
3388 23:23:05.620838 12, 0x0, sum = 1
3389 23:23:05.620917 13, 0x0, sum = 2
3390 23:23:05.624164 14, 0x0, sum = 3
3391 23:23:05.624257 15, 0x0, sum = 4
3392 23:23:05.627621 best_step = 13
3393 23:23:05.627735
3394 23:23:05.627857 ==
3395 23:23:05.630785 Dram Type= 6, Freq= 0, CH_1, rank 0
3396 23:23:05.634290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3397 23:23:05.634392 ==
3398 23:23:05.637088 RX Vref Scan: 1
3399 23:23:05.637158
3400 23:23:05.637220 Set Vref Range= 32 -> 127
3401 23:23:05.637278
3402 23:23:05.640659 RX Vref 32 -> 127, step: 1
3403 23:23:05.640731
3404 23:23:05.643988 RX Delay -21 -> 252, step: 4
3405 23:23:05.644074
3406 23:23:05.647191 Set Vref, RX VrefLevel [Byte0]: 32
3407 23:23:05.650362 [Byte1]: 32
3408 23:23:05.650477
3409 23:23:05.653606 Set Vref, RX VrefLevel [Byte0]: 33
3410 23:23:05.656880 [Byte1]: 33
3411 23:23:05.661228
3412 23:23:05.661314 Set Vref, RX VrefLevel [Byte0]: 34
3413 23:23:05.663983 [Byte1]: 34
3414 23:23:05.668944
3415 23:23:05.669085 Set Vref, RX VrefLevel [Byte0]: 35
3416 23:23:05.672457 [Byte1]: 35
3417 23:23:05.676826
3418 23:23:05.676902 Set Vref, RX VrefLevel [Byte0]: 36
3419 23:23:05.680095 [Byte1]: 36
3420 23:23:05.684661
3421 23:23:05.684752 Set Vref, RX VrefLevel [Byte0]: 37
3422 23:23:05.687924 [Byte1]: 37
3423 23:23:05.692467
3424 23:23:05.692541 Set Vref, RX VrefLevel [Byte0]: 38
3425 23:23:05.696024 [Byte1]: 38
3426 23:23:05.700371
3427 23:23:05.700446 Set Vref, RX VrefLevel [Byte0]: 39
3428 23:23:05.704049 [Byte1]: 39
3429 23:23:05.708460
3430 23:23:05.708534 Set Vref, RX VrefLevel [Byte0]: 40
3431 23:23:05.712021 [Byte1]: 40
3432 23:23:05.716838
3433 23:23:05.716917 Set Vref, RX VrefLevel [Byte0]: 41
3434 23:23:05.719566 [Byte1]: 41
3435 23:23:05.724110
3436 23:23:05.724194 Set Vref, RX VrefLevel [Byte0]: 42
3437 23:23:05.727725 [Byte1]: 42
3438 23:23:05.732450
3439 23:23:05.732535 Set Vref, RX VrefLevel [Byte0]: 43
3440 23:23:05.735475 [Byte1]: 43
3441 23:23:05.740039
3442 23:23:05.740112 Set Vref, RX VrefLevel [Byte0]: 44
3443 23:23:05.743871 [Byte1]: 44
3444 23:23:05.748244
3445 23:23:05.748320 Set Vref, RX VrefLevel [Byte0]: 45
3446 23:23:05.751599 [Byte1]: 45
3447 23:23:05.755742
3448 23:23:05.755831 Set Vref, RX VrefLevel [Byte0]: 46
3449 23:23:05.759430 [Byte1]: 46
3450 23:23:05.764263
3451 23:23:05.764335 Set Vref, RX VrefLevel [Byte0]: 47
3452 23:23:05.766846 [Byte1]: 47
3453 23:23:05.772375
3454 23:23:05.772452 Set Vref, RX VrefLevel [Byte0]: 48
3455 23:23:05.774990 [Byte1]: 48
3456 23:23:05.779761
3457 23:23:05.779838 Set Vref, RX VrefLevel [Byte0]: 49
3458 23:23:05.783093 [Byte1]: 49
3459 23:23:05.787475
3460 23:23:05.787549 Set Vref, RX VrefLevel [Byte0]: 50
3461 23:23:05.790805 [Byte1]: 50
3462 23:23:05.795341
3463 23:23:05.795423 Set Vref, RX VrefLevel [Byte0]: 51
3464 23:23:05.798988 [Byte1]: 51
3465 23:23:05.803449
3466 23:23:05.803547 Set Vref, RX VrefLevel [Byte0]: 52
3467 23:23:05.806653 [Byte1]: 52
3468 23:23:05.811506
3469 23:23:05.811600 Set Vref, RX VrefLevel [Byte0]: 53
3470 23:23:05.814954 [Byte1]: 53
3471 23:23:05.819230
3472 23:23:05.819328 Set Vref, RX VrefLevel [Byte0]: 54
3473 23:23:05.822745 [Byte1]: 54
3474 23:23:05.827252
3475 23:23:05.827345 Set Vref, RX VrefLevel [Byte0]: 55
3476 23:23:05.830847 [Byte1]: 55
3477 23:23:05.834989
3478 23:23:05.838474 Set Vref, RX VrefLevel [Byte0]: 56
3479 23:23:05.841717 [Byte1]: 56
3480 23:23:05.841844
3481 23:23:05.844749 Set Vref, RX VrefLevel [Byte0]: 57
3482 23:23:05.848655 [Byte1]: 57
3483 23:23:05.848731
3484 23:23:05.851570 Set Vref, RX VrefLevel [Byte0]: 58
3485 23:23:05.854989 [Byte1]: 58
3486 23:23:05.858813
3487 23:23:05.858897 Set Vref, RX VrefLevel [Byte0]: 59
3488 23:23:05.862069 [Byte1]: 59
3489 23:23:05.867083
3490 23:23:05.867158 Set Vref, RX VrefLevel [Byte0]: 60
3491 23:23:05.869991 [Byte1]: 60
3492 23:23:05.874971
3493 23:23:05.875050 Set Vref, RX VrefLevel [Byte0]: 61
3494 23:23:05.877833 [Byte1]: 61
3495 23:23:05.883054
3496 23:23:05.883134 Set Vref, RX VrefLevel [Byte0]: 62
3497 23:23:05.886484 [Byte1]: 62
3498 23:23:05.890502
3499 23:23:05.890578 Set Vref, RX VrefLevel [Byte0]: 63
3500 23:23:05.894106 [Byte1]: 63
3501 23:23:05.898405
3502 23:23:05.898515 Set Vref, RX VrefLevel [Byte0]: 64
3503 23:23:05.902193 [Byte1]: 64
3504 23:23:05.906598
3505 23:23:05.906710 Set Vref, RX VrefLevel [Byte0]: 65
3506 23:23:05.909924 [Byte1]: 65
3507 23:23:05.914515
3508 23:23:05.914620 Final RX Vref Byte 0 = 53 to rank0
3509 23:23:05.917632 Final RX Vref Byte 1 = 60 to rank0
3510 23:23:05.920982 Final RX Vref Byte 0 = 53 to rank1
3511 23:23:05.924201 Final RX Vref Byte 1 = 60 to rank1==
3512 23:23:05.927525 Dram Type= 6, Freq= 0, CH_1, rank 0
3513 23:23:05.934351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 23:23:05.934432 ==
3515 23:23:05.934507 DQS Delay:
3516 23:23:05.937473 DQS0 = 0, DQS1 = 0
3517 23:23:05.937555 DQM Delay:
3518 23:23:05.940351 DQM0 = 116, DQM1 = 111
3519 23:23:05.940433 DQ Delay:
3520 23:23:05.943700 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =114
3521 23:23:05.947538 DQ4 =112, DQ5 =128, DQ6 =124, DQ7 =112
3522 23:23:05.950560 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =100
3523 23:23:05.953744 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =120
3524 23:23:05.953849
3525 23:23:05.953949
3526 23:23:05.963735 [DQSOSCAuto] RK0, (LSB)MR18= 0xf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3527 23:23:05.963827 CH1 RK0: MR19=403, MR18=F4
3528 23:23:05.970061 CH1_RK0: MR19=0x403, MR18=0xF4, DQSOSC=410, MR23=63, INC=39, DEC=26
3529 23:23:05.970170
3530 23:23:05.973551 ----->DramcWriteLeveling(PI) begin...
3531 23:23:05.973637 ==
3532 23:23:05.976663 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 23:23:05.983725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 23:23:05.983804 ==
3535 23:23:05.986795 Write leveling (Byte 0): 26 => 26
3536 23:23:05.986879 Write leveling (Byte 1): 29 => 29
3537 23:23:05.990508 DramcWriteLeveling(PI) end<-----
3538 23:23:05.990646
3539 23:23:05.993440 ==
3540 23:23:05.996450 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 23:23:05.999784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 23:23:05.999859 ==
3543 23:23:06.003705 [Gating] SW mode calibration
3544 23:23:06.009696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3545 23:23:06.012964 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3546 23:23:06.019637 0 15 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3547 23:23:06.023055 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3548 23:23:06.026112 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3549 23:23:06.032448 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3550 23:23:06.035856 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3551 23:23:06.039041 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3552 23:23:06.045786 0 15 24 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 0)
3553 23:23:06.049133 0 15 28 | B1->B0 | 2323 2424 | 0 1 | (1 0) (1 0)
3554 23:23:06.052210 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3555 23:23:06.059035 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3556 23:23:06.061918 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3557 23:23:06.068429 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3558 23:23:06.071966 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3559 23:23:06.075207 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3560 23:23:06.081645 1 0 24 | B1->B0 | 4141 2a2a | 1 0 | (0 0) (0 0)
3561 23:23:06.084867 1 0 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
3562 23:23:06.088526 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3563 23:23:06.094757 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 23:23:06.097891 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3565 23:23:06.101496 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3566 23:23:06.108069 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 23:23:06.111145 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 23:23:06.114768 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3569 23:23:06.121093 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3570 23:23:06.124734 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 23:23:06.127562 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 23:23:06.134281 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 23:23:06.137401 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 23:23:06.140670 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 23:23:06.147659 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 23:23:06.150523 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 23:23:06.154190 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 23:23:06.160175 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 23:23:06.163707 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 23:23:06.166700 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 23:23:06.173457 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 23:23:06.176926 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 23:23:06.180021 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 23:23:06.187090 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 23:23:06.189844 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3586 23:23:06.193304 Total UI for P1: 0, mck2ui 16
3587 23:23:06.197146 best dqsien dly found for B1: ( 1, 3, 26)
3588 23:23:06.200204 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3589 23:23:06.202881 Total UI for P1: 0, mck2ui 16
3590 23:23:06.206813 best dqsien dly found for B0: ( 1, 3, 28)
3591 23:23:06.209777 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3592 23:23:06.213008 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3593 23:23:06.213171
3594 23:23:06.219801 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3595 23:23:06.223192 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3596 23:23:06.226637 [Gating] SW calibration Done
3597 23:23:06.226720 ==
3598 23:23:06.229386 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 23:23:06.233584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 23:23:06.233667 ==
3601 23:23:06.233733 RX Vref Scan: 0
3602 23:23:06.233795
3603 23:23:06.236760 RX Vref 0 -> 0, step: 1
3604 23:23:06.236843
3605 23:23:06.239228 RX Delay -40 -> 252, step: 8
3606 23:23:06.242847 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3607 23:23:06.246207 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3608 23:23:06.252573 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3609 23:23:06.256063 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3610 23:23:06.259377 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3611 23:23:06.262679 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3612 23:23:06.265934 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3613 23:23:06.272801 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3614 23:23:06.275514 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3615 23:23:06.279087 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3616 23:23:06.282086 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3617 23:23:06.285398 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3618 23:23:06.292397 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3619 23:23:06.295471 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3620 23:23:06.298696 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3621 23:23:06.302605 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3622 23:23:06.302703 ==
3623 23:23:06.305250 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 23:23:06.312030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 23:23:06.312114 ==
3626 23:23:06.312181 DQS Delay:
3627 23:23:06.315598 DQS0 = 0, DQS1 = 0
3628 23:23:06.315707 DQM Delay:
3629 23:23:06.318866 DQM0 = 116, DQM1 = 110
3630 23:23:06.318948 DQ Delay:
3631 23:23:06.322048 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3632 23:23:06.325748 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3633 23:23:06.328717 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3634 23:23:06.332531 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3635 23:23:06.332659
3636 23:23:06.332728
3637 23:23:06.332789 ==
3638 23:23:06.335256 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 23:23:06.342898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 23:23:06.342992 ==
3641 23:23:06.343059
3642 23:23:06.343120
3643 23:23:06.343179 TX Vref Scan disable
3644 23:23:06.345572 == TX Byte 0 ==
3645 23:23:06.348315 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3646 23:23:06.352204 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3647 23:23:06.355276 == TX Byte 1 ==
3648 23:23:06.358771 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3649 23:23:06.365274 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3650 23:23:06.365372 ==
3651 23:23:06.368342 Dram Type= 6, Freq= 0, CH_1, rank 1
3652 23:23:06.371572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3653 23:23:06.371656 ==
3654 23:23:06.383064 TX Vref=22, minBit 8, minWin=25, winSum=424
3655 23:23:06.386562 TX Vref=24, minBit 8, minWin=25, winSum=425
3656 23:23:06.389446 TX Vref=26, minBit 11, minWin=25, winSum=429
3657 23:23:06.393285 TX Vref=28, minBit 8, minWin=26, winSum=429
3658 23:23:06.396135 TX Vref=30, minBit 8, minWin=26, winSum=434
3659 23:23:06.402599 TX Vref=32, minBit 11, minWin=25, winSum=431
3660 23:23:06.405836 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
3661 23:23:06.405921
3662 23:23:06.409439 Final TX Range 1 Vref 30
3663 23:23:06.409524
3664 23:23:06.409591 ==
3665 23:23:06.413109 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 23:23:06.419137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 23:23:06.419223 ==
3668 23:23:06.419293
3669 23:23:06.419355
3670 23:23:06.419415 TX Vref Scan disable
3671 23:23:06.423235 == TX Byte 0 ==
3672 23:23:06.426033 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3673 23:23:06.432541 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3674 23:23:06.432626 == TX Byte 1 ==
3675 23:23:06.435819 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3676 23:23:06.442564 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3677 23:23:06.442654
3678 23:23:06.442722 [DATLAT]
3679 23:23:06.442790 Freq=1200, CH1 RK1
3680 23:23:06.442858
3681 23:23:06.445643 DATLAT Default: 0xd
3682 23:23:06.449400 0, 0xFFFF, sum = 0
3683 23:23:06.449486 1, 0xFFFF, sum = 0
3684 23:23:06.452685 2, 0xFFFF, sum = 0
3685 23:23:06.452770 3, 0xFFFF, sum = 0
3686 23:23:06.456411 4, 0xFFFF, sum = 0
3687 23:23:06.456551 5, 0xFFFF, sum = 0
3688 23:23:06.459049 6, 0xFFFF, sum = 0
3689 23:23:06.459135 7, 0xFFFF, sum = 0
3690 23:23:06.462333 8, 0xFFFF, sum = 0
3691 23:23:06.462419 9, 0xFFFF, sum = 0
3692 23:23:06.465733 10, 0xFFFF, sum = 0
3693 23:23:06.465819 11, 0xFFFF, sum = 0
3694 23:23:06.468933 12, 0x0, sum = 1
3695 23:23:06.469020 13, 0x0, sum = 2
3696 23:23:06.472280 14, 0x0, sum = 3
3697 23:23:06.472366 15, 0x0, sum = 4
3698 23:23:06.475586 best_step = 13
3699 23:23:06.475680
3700 23:23:06.475751 ==
3701 23:23:06.478832 Dram Type= 6, Freq= 0, CH_1, rank 1
3702 23:23:06.481845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3703 23:23:06.481931 ==
3704 23:23:06.485390 RX Vref Scan: 0
3705 23:23:06.485472
3706 23:23:06.485538 RX Vref 0 -> 0, step: 1
3707 23:23:06.485599
3708 23:23:06.488649 RX Delay -21 -> 252, step: 4
3709 23:23:06.495403 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3710 23:23:06.498731 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3711 23:23:06.501650 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3712 23:23:06.505271 iDelay=199, Bit 3, Center 110 (43 ~ 178) 136
3713 23:23:06.508245 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3714 23:23:06.514945 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3715 23:23:06.518550 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3716 23:23:06.521420 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3717 23:23:06.524863 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3718 23:23:06.528325 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3719 23:23:06.535022 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3720 23:23:06.537764 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3721 23:23:06.541928 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3722 23:23:06.545215 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3723 23:23:06.550892 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3724 23:23:06.554280 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3725 23:23:06.554385 ==
3726 23:23:06.557896 Dram Type= 6, Freq= 0, CH_1, rank 1
3727 23:23:06.561188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3728 23:23:06.561290 ==
3729 23:23:06.564736 DQS Delay:
3730 23:23:06.564838 DQS0 = 0, DQS1 = 0
3731 23:23:06.564940 DQM Delay:
3732 23:23:06.567350 DQM0 = 116, DQM1 = 110
3733 23:23:06.567473 DQ Delay:
3734 23:23:06.571192 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =110
3735 23:23:06.574006 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =114
3736 23:23:06.580623 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =104
3737 23:23:06.584131 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =120
3738 23:23:06.584248
3739 23:23:06.584340
3740 23:23:06.590919 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3741 23:23:06.594214 CH1 RK1: MR19=303, MR18=F3EE
3742 23:23:06.600395 CH1_RK1: MR19=0x303, MR18=0xF3EE, DQSOSC=415, MR23=63, INC=38, DEC=25
3743 23:23:06.604044 [RxdqsGatingPostProcess] freq 1200
3744 23:23:06.610142 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3745 23:23:06.614028 best DQS0 dly(2T, 0.5T) = (0, 11)
3746 23:23:06.614111 best DQS1 dly(2T, 0.5T) = (0, 11)
3747 23:23:06.617486 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3748 23:23:06.620395 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3749 23:23:06.623919 best DQS0 dly(2T, 0.5T) = (0, 11)
3750 23:23:06.626897 best DQS1 dly(2T, 0.5T) = (0, 11)
3751 23:23:06.630181 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3752 23:23:06.633723 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3753 23:23:06.636793 Pre-setting of DQS Precalculation
3754 23:23:06.643638 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3755 23:23:06.650256 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3756 23:23:06.657036 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3757 23:23:06.657120
3758 23:23:06.657186
3759 23:23:06.660208 [Calibration Summary] 2400 Mbps
3760 23:23:06.660291 CH 0, Rank 0
3761 23:23:06.663333 SW Impedance : PASS
3762 23:23:06.666572 DUTY Scan : NO K
3763 23:23:06.666655 ZQ Calibration : PASS
3764 23:23:06.670139 Jitter Meter : NO K
3765 23:23:06.673142 CBT Training : PASS
3766 23:23:06.673274 Write leveling : PASS
3767 23:23:06.676604 RX DQS gating : PASS
3768 23:23:06.679738 RX DQ/DQS(RDDQC) : PASS
3769 23:23:06.679849 TX DQ/DQS : PASS
3770 23:23:06.682764 RX DATLAT : PASS
3771 23:23:06.686028 RX DQ/DQS(Engine): PASS
3772 23:23:06.686112 TX OE : NO K
3773 23:23:06.689725 All Pass.
3774 23:23:06.689807
3775 23:23:06.689872 CH 0, Rank 1
3776 23:23:06.692582 SW Impedance : PASS
3777 23:23:06.692664 DUTY Scan : NO K
3778 23:23:06.696205 ZQ Calibration : PASS
3779 23:23:06.699190 Jitter Meter : NO K
3780 23:23:06.699272 CBT Training : PASS
3781 23:23:06.702956 Write leveling : PASS
3782 23:23:06.703040 RX DQS gating : PASS
3783 23:23:06.706334 RX DQ/DQS(RDDQC) : PASS
3784 23:23:06.709712 TX DQ/DQS : PASS
3785 23:23:06.709796 RX DATLAT : PASS
3786 23:23:06.712290 RX DQ/DQS(Engine): PASS
3787 23:23:06.716430 TX OE : NO K
3788 23:23:06.716513 All Pass.
3789 23:23:06.716579
3790 23:23:06.716640 CH 1, Rank 0
3791 23:23:06.718905 SW Impedance : PASS
3792 23:23:06.722375 DUTY Scan : NO K
3793 23:23:06.722457 ZQ Calibration : PASS
3794 23:23:06.725709 Jitter Meter : NO K
3795 23:23:06.729336 CBT Training : PASS
3796 23:23:06.729418 Write leveling : PASS
3797 23:23:06.732864 RX DQS gating : PASS
3798 23:23:06.735286 RX DQ/DQS(RDDQC) : PASS
3799 23:23:06.735368 TX DQ/DQS : PASS
3800 23:23:06.739166 RX DATLAT : PASS
3801 23:23:06.742057 RX DQ/DQS(Engine): PASS
3802 23:23:06.742139 TX OE : NO K
3803 23:23:06.745582 All Pass.
3804 23:23:06.745663
3805 23:23:06.745728 CH 1, Rank 1
3806 23:23:06.748761 SW Impedance : PASS
3807 23:23:06.748843 DUTY Scan : NO K
3808 23:23:06.752042 ZQ Calibration : PASS
3809 23:23:06.755422 Jitter Meter : NO K
3810 23:23:06.755504 CBT Training : PASS
3811 23:23:06.758604 Write leveling : PASS
3812 23:23:06.762247 RX DQS gating : PASS
3813 23:23:06.762329 RX DQ/DQS(RDDQC) : PASS
3814 23:23:06.764933 TX DQ/DQS : PASS
3815 23:23:06.768405 RX DATLAT : PASS
3816 23:23:06.768514 RX DQ/DQS(Engine): PASS
3817 23:23:06.771974 TX OE : NO K
3818 23:23:06.772084 All Pass.
3819 23:23:06.772177
3820 23:23:06.775102 DramC Write-DBI off
3821 23:23:06.778270 PER_BANK_REFRESH: Hybrid Mode
3822 23:23:06.778374 TX_TRACKING: ON
3823 23:23:06.788834 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3824 23:23:06.791380 [FAST_K] Save calibration result to emmc
3825 23:23:06.795013 dramc_set_vcore_voltage set vcore to 650000
3826 23:23:06.797961 Read voltage for 600, 5
3827 23:23:06.798044 Vio18 = 0
3828 23:23:06.798111 Vcore = 650000
3829 23:23:06.801744 Vdram = 0
3830 23:23:06.801825 Vddq = 0
3831 23:23:06.801890 Vmddr = 0
3832 23:23:06.808275 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3833 23:23:06.811353 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3834 23:23:06.814597 MEM_TYPE=3, freq_sel=19
3835 23:23:06.817860 sv_algorithm_assistance_LP4_1600
3836 23:23:06.821518 ============ PULL DRAM RESETB DOWN ============
3837 23:23:06.824524 ========== PULL DRAM RESETB DOWN end =========
3838 23:23:06.831206 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3839 23:23:06.834632 ===================================
3840 23:23:06.837357 LPDDR4 DRAM CONFIGURATION
3841 23:23:06.841235 ===================================
3842 23:23:06.841317 EX_ROW_EN[0] = 0x0
3843 23:23:06.844313 EX_ROW_EN[1] = 0x0
3844 23:23:06.844394 LP4Y_EN = 0x0
3845 23:23:06.847505 WORK_FSP = 0x0
3846 23:23:06.847589 WL = 0x2
3847 23:23:06.850613 RL = 0x2
3848 23:23:06.850720 BL = 0x2
3849 23:23:06.854537 RPST = 0x0
3850 23:23:06.854618 RD_PRE = 0x0
3851 23:23:06.857512 WR_PRE = 0x1
3852 23:23:06.857593 WR_PST = 0x0
3853 23:23:06.861184 DBI_WR = 0x0
3854 23:23:06.864323 DBI_RD = 0x0
3855 23:23:06.864405 OTF = 0x1
3856 23:23:06.867321 ===================================
3857 23:23:06.870726 ===================================
3858 23:23:06.870849 ANA top config
3859 23:23:06.873974 ===================================
3860 23:23:06.877776 DLL_ASYNC_EN = 0
3861 23:23:06.880603 ALL_SLAVE_EN = 1
3862 23:23:06.883887 NEW_RANK_MODE = 1
3863 23:23:06.887557 DLL_IDLE_MODE = 1
3864 23:23:06.887665 LP45_APHY_COMB_EN = 1
3865 23:23:06.890657 TX_ODT_DIS = 1
3866 23:23:06.893635 NEW_8X_MODE = 1
3867 23:23:06.897047 ===================================
3868 23:23:06.900801 ===================================
3869 23:23:06.903355 data_rate = 1200
3870 23:23:06.907016 CKR = 1
3871 23:23:06.909802 DQ_P2S_RATIO = 8
3872 23:23:06.913389 ===================================
3873 23:23:06.913473 CA_P2S_RATIO = 8
3874 23:23:06.916594 DQ_CA_OPEN = 0
3875 23:23:06.919959 DQ_SEMI_OPEN = 0
3876 23:23:06.923217 CA_SEMI_OPEN = 0
3877 23:23:06.926152 CA_FULL_RATE = 0
3878 23:23:06.929615 DQ_CKDIV4_EN = 1
3879 23:23:06.929727 CA_CKDIV4_EN = 1
3880 23:23:06.932773 CA_PREDIV_EN = 0
3881 23:23:06.936285 PH8_DLY = 0
3882 23:23:06.939831 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3883 23:23:06.942611 DQ_AAMCK_DIV = 4
3884 23:23:06.946030 CA_AAMCK_DIV = 4
3885 23:23:06.949490 CA_ADMCK_DIV = 4
3886 23:23:06.949573 DQ_TRACK_CA_EN = 0
3887 23:23:06.953013 CA_PICK = 600
3888 23:23:06.955924 CA_MCKIO = 600
3889 23:23:06.959325 MCKIO_SEMI = 0
3890 23:23:06.962764 PLL_FREQ = 2288
3891 23:23:06.965550 DQ_UI_PI_RATIO = 32
3892 23:23:06.969388 CA_UI_PI_RATIO = 0
3893 23:23:06.972625 ===================================
3894 23:23:06.976251 ===================================
3895 23:23:06.976335 memory_type:LPDDR4
3896 23:23:06.979079 GP_NUM : 10
3897 23:23:06.982460 SRAM_EN : 1
3898 23:23:06.982572 MD32_EN : 0
3899 23:23:06.985465 ===================================
3900 23:23:06.988914 [ANA_INIT] >>>>>>>>>>>>>>
3901 23:23:06.992166 <<<<<< [CONFIGURE PHASE]: ANA_TX
3902 23:23:06.995366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3903 23:23:06.998826 ===================================
3904 23:23:07.001895 data_rate = 1200,PCW = 0X5800
3905 23:23:07.005085 ===================================
3906 23:23:07.008614 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3907 23:23:07.011934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3908 23:23:07.018568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3909 23:23:07.022069 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3910 23:23:07.025761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3911 23:23:07.028276 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3912 23:23:07.031678 [ANA_INIT] flow start
3913 23:23:07.034999 [ANA_INIT] PLL >>>>>>>>
3914 23:23:07.035085 [ANA_INIT] PLL <<<<<<<<
3915 23:23:07.038596 [ANA_INIT] MIDPI >>>>>>>>
3916 23:23:07.041750 [ANA_INIT] MIDPI <<<<<<<<
3917 23:23:07.045060 [ANA_INIT] DLL >>>>>>>>
3918 23:23:07.045205 [ANA_INIT] flow end
3919 23:23:07.048227 ============ LP4 DIFF to SE enter ============
3920 23:23:07.054753 ============ LP4 DIFF to SE exit ============
3921 23:23:07.054888 [ANA_INIT] <<<<<<<<<<<<<
3922 23:23:07.057973 [Flow] Enable top DCM control >>>>>
3923 23:23:07.061755 [Flow] Enable top DCM control <<<<<
3924 23:23:07.064585 Enable DLL master slave shuffle
3925 23:23:07.071578 ==============================================================
3926 23:23:07.071727 Gating Mode config
3927 23:23:07.078036 ==============================================================
3928 23:23:07.081282 Config description:
3929 23:23:07.091639 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3930 23:23:07.097856 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3931 23:23:07.101185 SELPH_MODE 0: By rank 1: By Phase
3932 23:23:07.107707 ==============================================================
3933 23:23:07.111087 GAT_TRACK_EN = 1
3934 23:23:07.114124 RX_GATING_MODE = 2
3935 23:23:07.117870 RX_GATING_TRACK_MODE = 2
3936 23:23:07.117953 SELPH_MODE = 1
3937 23:23:07.120404 PICG_EARLY_EN = 1
3938 23:23:07.124053 VALID_LAT_VALUE = 1
3939 23:23:07.130393 ==============================================================
3940 23:23:07.133963 Enter into Gating configuration >>>>
3941 23:23:07.137059 Exit from Gating configuration <<<<
3942 23:23:07.140306 Enter into DVFS_PRE_config >>>>>
3943 23:23:07.150680 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3944 23:23:07.153450 Exit from DVFS_PRE_config <<<<<
3945 23:23:07.156704 Enter into PICG configuration >>>>
3946 23:23:07.160041 Exit from PICG configuration <<<<
3947 23:23:07.163647 [RX_INPUT] configuration >>>>>
3948 23:23:07.166686 [RX_INPUT] configuration <<<<<
3949 23:23:07.173210 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3950 23:23:07.176780 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3951 23:23:07.183193 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3952 23:23:07.189990 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3953 23:23:07.196313 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3954 23:23:07.202963 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3955 23:23:07.206545 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3956 23:23:07.209604 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3957 23:23:07.212867 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3958 23:23:07.219868 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3959 23:23:07.223183 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3960 23:23:07.226292 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3961 23:23:07.229923 ===================================
3962 23:23:07.232648 LPDDR4 DRAM CONFIGURATION
3963 23:23:07.235946 ===================================
3964 23:23:07.236029 EX_ROW_EN[0] = 0x0
3965 23:23:07.239423 EX_ROW_EN[1] = 0x0
3966 23:23:07.242493 LP4Y_EN = 0x0
3967 23:23:07.242576 WORK_FSP = 0x0
3968 23:23:07.245601 WL = 0x2
3969 23:23:07.245683 RL = 0x2
3970 23:23:07.249002 BL = 0x2
3971 23:23:07.249104 RPST = 0x0
3972 23:23:07.252288 RD_PRE = 0x0
3973 23:23:07.252372 WR_PRE = 0x1
3974 23:23:07.255437 WR_PST = 0x0
3975 23:23:07.255519 DBI_WR = 0x0
3976 23:23:07.258797 DBI_RD = 0x0
3977 23:23:07.258879 OTF = 0x1
3978 23:23:07.262253 ===================================
3979 23:23:07.269071 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3980 23:23:07.271975 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3981 23:23:07.275389 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3982 23:23:07.279180 ===================================
3983 23:23:07.281920 LPDDR4 DRAM CONFIGURATION
3984 23:23:07.285415 ===================================
3985 23:23:07.288520 EX_ROW_EN[0] = 0x10
3986 23:23:07.288707 EX_ROW_EN[1] = 0x0
3987 23:23:07.291859 LP4Y_EN = 0x0
3988 23:23:07.291936 WORK_FSP = 0x0
3989 23:23:07.295483 WL = 0x2
3990 23:23:07.295580 RL = 0x2
3991 23:23:07.298292 BL = 0x2
3992 23:23:07.298391 RPST = 0x0
3993 23:23:07.302224 RD_PRE = 0x0
3994 23:23:07.302326 WR_PRE = 0x1
3995 23:23:07.305184 WR_PST = 0x0
3996 23:23:07.305255 DBI_WR = 0x0
3997 23:23:07.308459 DBI_RD = 0x0
3998 23:23:07.308531 OTF = 0x1
3999 23:23:07.312247 ===================================
4000 23:23:07.318244 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4001 23:23:07.322955 nWR fixed to 30
4002 23:23:07.326013 [ModeRegInit_LP4] CH0 RK0
4003 23:23:07.326096 [ModeRegInit_LP4] CH0 RK1
4004 23:23:07.329655 [ModeRegInit_LP4] CH1 RK0
4005 23:23:07.332704 [ModeRegInit_LP4] CH1 RK1
4006 23:23:07.332787 match AC timing 17
4007 23:23:07.339237 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4008 23:23:07.342965 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4009 23:23:07.346096 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4010 23:23:07.352807 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4011 23:23:07.355725 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4012 23:23:07.355825 ==
4013 23:23:07.359105 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 23:23:07.362204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 23:23:07.365814 ==
4016 23:23:07.368905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4017 23:23:07.375871 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4018 23:23:07.378939 [CA 0] Center 36 (6~66) winsize 61
4019 23:23:07.382243 [CA 1] Center 36 (6~67) winsize 62
4020 23:23:07.385559 [CA 2] Center 34 (4~65) winsize 62
4021 23:23:07.388548 [CA 3] Center 34 (4~65) winsize 62
4022 23:23:07.391974 [CA 4] Center 33 (3~64) winsize 62
4023 23:23:07.395531 [CA 5] Center 33 (3~64) winsize 62
4024 23:23:07.395634
4025 23:23:07.398624 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4026 23:23:07.398729
4027 23:23:07.402195 [CATrainingPosCal] consider 1 rank data
4028 23:23:07.405315 u2DelayCellTimex100 = 270/100 ps
4029 23:23:07.408545 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4030 23:23:07.411539 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4031 23:23:07.418274 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4032 23:23:07.421488 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4033 23:23:07.425453 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4034 23:23:07.428519 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4035 23:23:07.428623
4036 23:23:07.431809 CA PerBit enable=1, Macro0, CA PI delay=33
4037 23:23:07.431912
4038 23:23:07.434795 [CBTSetCACLKResult] CA Dly = 33
4039 23:23:07.434878 CS Dly: 5 (0~36)
4040 23:23:07.434960 ==
4041 23:23:07.437981 Dram Type= 6, Freq= 0, CH_0, rank 1
4042 23:23:07.445185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 23:23:07.445290 ==
4044 23:23:07.448231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4045 23:23:07.454824 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4046 23:23:07.458243 [CA 0] Center 36 (6~66) winsize 61
4047 23:23:07.461764 [CA 1] Center 36 (6~66) winsize 61
4048 23:23:07.464959 [CA 2] Center 34 (4~65) winsize 62
4049 23:23:07.468395 [CA 3] Center 34 (4~65) winsize 62
4050 23:23:07.471828 [CA 4] Center 33 (3~64) winsize 62
4051 23:23:07.474903 [CA 5] Center 33 (3~64) winsize 62
4052 23:23:07.474987
4053 23:23:07.478376 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4054 23:23:07.478497
4055 23:23:07.482003 [CATrainingPosCal] consider 2 rank data
4056 23:23:07.484589 u2DelayCellTimex100 = 270/100 ps
4057 23:23:07.488515 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4058 23:23:07.494729 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4059 23:23:07.497692 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4060 23:23:07.501034 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4061 23:23:07.504460 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4062 23:23:07.507551 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4063 23:23:07.507656
4064 23:23:07.511316 CA PerBit enable=1, Macro0, CA PI delay=33
4065 23:23:07.511415
4066 23:23:07.514080 [CBTSetCACLKResult] CA Dly = 33
4067 23:23:07.517638 CS Dly: 5 (0~36)
4068 23:23:07.517742
4069 23:23:07.521060 ----->DramcWriteLeveling(PI) begin...
4070 23:23:07.521166 ==
4071 23:23:07.524115 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 23:23:07.527211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 23:23:07.527360 ==
4074 23:23:07.530625 Write leveling (Byte 0): 33 => 33
4075 23:23:07.534227 Write leveling (Byte 1): 29 => 29
4076 23:23:07.537371 DramcWriteLeveling(PI) end<-----
4077 23:23:07.537473
4078 23:23:07.537574 ==
4079 23:23:07.540723 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 23:23:07.543802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 23:23:07.543881 ==
4082 23:23:07.546975 [Gating] SW mode calibration
4083 23:23:07.553636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4084 23:23:07.560852 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4085 23:23:07.563829 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4086 23:23:07.567289 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4087 23:23:07.573516 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4088 23:23:07.576983 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4089 23:23:07.580364 0 9 16 | B1->B0 | 3030 2626 | 0 0 | (0 1) (0 0)
4090 23:23:07.587033 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4091 23:23:07.589867 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4092 23:23:07.596385 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4093 23:23:07.599856 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4094 23:23:07.603195 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4095 23:23:07.609654 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4096 23:23:07.613328 0 10 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4097 23:23:07.616028 0 10 16 | B1->B0 | 3131 3d3d | 0 1 | (0 0) (0 0)
4098 23:23:07.623065 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4099 23:23:07.626553 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4100 23:23:07.629651 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4101 23:23:07.632866 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 23:23:07.639395 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 23:23:07.643035 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4104 23:23:07.645885 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 23:23:07.652642 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 23:23:07.655623 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 23:23:07.659011 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 23:23:07.665789 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 23:23:07.668899 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 23:23:07.672412 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 23:23:07.678911 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 23:23:07.681935 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 23:23:07.688951 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 23:23:07.691838 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 23:23:07.695176 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 23:23:07.701998 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 23:23:07.705131 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 23:23:07.708366 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 23:23:07.715312 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 23:23:07.718151 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4121 23:23:07.721909 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4122 23:23:07.728011 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4123 23:23:07.728108 Total UI for P1: 0, mck2ui 16
4124 23:23:07.734632 best dqsien dly found for B0: ( 0, 13, 14)
4125 23:23:07.734744 Total UI for P1: 0, mck2ui 16
4126 23:23:07.737765 best dqsien dly found for B1: ( 0, 13, 16)
4127 23:23:07.744473 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4128 23:23:07.748031 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4129 23:23:07.748114
4130 23:23:07.751203 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4131 23:23:07.754510 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4132 23:23:07.758238 [Gating] SW calibration Done
4133 23:23:07.758343 ==
4134 23:23:07.760914 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 23:23:07.764286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 23:23:07.764380 ==
4137 23:23:07.767848 RX Vref Scan: 0
4138 23:23:07.767956
4139 23:23:07.768057 RX Vref 0 -> 0, step: 1
4140 23:23:07.768157
4141 23:23:07.771429 RX Delay -230 -> 252, step: 16
4142 23:23:07.777433 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4143 23:23:07.781363 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4144 23:23:07.784468 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4145 23:23:07.787391 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4146 23:23:07.790866 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4147 23:23:07.797299 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4148 23:23:07.801005 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4149 23:23:07.804362 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4150 23:23:07.807565 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4151 23:23:07.813524 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4152 23:23:07.817129 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4153 23:23:07.820785 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4154 23:23:07.823821 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4155 23:23:07.830806 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4156 23:23:07.833610 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4157 23:23:07.836891 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4158 23:23:07.836976 ==
4159 23:23:07.840277 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 23:23:07.846921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 23:23:07.847008 ==
4162 23:23:07.847076 DQS Delay:
4163 23:23:07.847138 DQS0 = 0, DQS1 = 0
4164 23:23:07.849870 DQM Delay:
4165 23:23:07.849955 DQM0 = 43, DQM1 = 31
4166 23:23:07.853407 DQ Delay:
4167 23:23:07.856611 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4168 23:23:07.859623 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4169 23:23:07.862792 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4170 23:23:07.866091 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4171 23:23:07.866176
4172 23:23:07.866243
4173 23:23:07.866305 ==
4174 23:23:07.869434 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 23:23:07.872878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 23:23:07.872974 ==
4177 23:23:07.873044
4178 23:23:07.873126
4179 23:23:07.876534 TX Vref Scan disable
4180 23:23:07.879572 == TX Byte 0 ==
4181 23:23:07.882676 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4182 23:23:07.886067 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4183 23:23:07.889146 == TX Byte 1 ==
4184 23:23:07.892251 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4185 23:23:07.896134 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4186 23:23:07.896219 ==
4187 23:23:07.899508 Dram Type= 6, Freq= 0, CH_0, rank 0
4188 23:23:07.902654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 23:23:07.905683 ==
4190 23:23:07.905767
4191 23:23:07.905832
4192 23:23:07.905894 TX Vref Scan disable
4193 23:23:07.909556 == TX Byte 0 ==
4194 23:23:07.913051 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4195 23:23:07.920157 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4196 23:23:07.920241 == TX Byte 1 ==
4197 23:23:07.923381 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4198 23:23:07.929484 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4199 23:23:07.929567
4200 23:23:07.929633 [DATLAT]
4201 23:23:07.929695 Freq=600, CH0 RK0
4202 23:23:07.929755
4203 23:23:07.932985 DATLAT Default: 0x9
4204 23:23:07.933067 0, 0xFFFF, sum = 0
4205 23:23:07.936206 1, 0xFFFF, sum = 0
4206 23:23:07.939269 2, 0xFFFF, sum = 0
4207 23:23:07.939357 3, 0xFFFF, sum = 0
4208 23:23:07.942741 4, 0xFFFF, sum = 0
4209 23:23:07.942862 5, 0xFFFF, sum = 0
4210 23:23:07.945775 6, 0xFFFF, sum = 0
4211 23:23:07.945858 7, 0xFFFF, sum = 0
4212 23:23:07.949128 8, 0x0, sum = 1
4213 23:23:07.949212 9, 0x0, sum = 2
4214 23:23:07.952772 10, 0x0, sum = 3
4215 23:23:07.952856 11, 0x0, sum = 4
4216 23:23:07.952923 best_step = 9
4217 23:23:07.952984
4218 23:23:07.955819 ==
4219 23:23:07.958981 Dram Type= 6, Freq= 0, CH_0, rank 0
4220 23:23:07.962167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 23:23:07.962254 ==
4222 23:23:07.962341 RX Vref Scan: 1
4223 23:23:07.962424
4224 23:23:07.965414 RX Vref 0 -> 0, step: 1
4225 23:23:07.965499
4226 23:23:07.968753 RX Delay -179 -> 252, step: 8
4227 23:23:07.968838
4228 23:23:07.972362 Set Vref, RX VrefLevel [Byte0]: 61
4229 23:23:07.975619 [Byte1]: 54
4230 23:23:07.975742
4231 23:23:07.978610 Final RX Vref Byte 0 = 61 to rank0
4232 23:23:07.981834 Final RX Vref Byte 1 = 54 to rank0
4233 23:23:07.985310 Final RX Vref Byte 0 = 61 to rank1
4234 23:23:07.988661 Final RX Vref Byte 1 = 54 to rank1==
4235 23:23:07.992236 Dram Type= 6, Freq= 0, CH_0, rank 0
4236 23:23:07.998909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 23:23:07.998996 ==
4238 23:23:07.999083 DQS Delay:
4239 23:23:07.999164 DQS0 = 0, DQS1 = 0
4240 23:23:08.001687 DQM Delay:
4241 23:23:08.001772 DQM0 = 41, DQM1 = 33
4242 23:23:08.005387 DQ Delay:
4243 23:23:08.008437 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4244 23:23:08.011484 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4245 23:23:08.014862 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4246 23:23:08.018261 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4247 23:23:08.018347
4248 23:23:08.018434
4249 23:23:08.024885 [DQSOSCAuto] RK0, (LSB)MR18= 0x673f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4250 23:23:08.028248 CH0 RK0: MR19=808, MR18=673F
4251 23:23:08.034969 CH0_RK0: MR19=0x808, MR18=0x673F, DQSOSC=390, MR23=63, INC=172, DEC=114
4252 23:23:08.035087
4253 23:23:08.038003 ----->DramcWriteLeveling(PI) begin...
4254 23:23:08.038090 ==
4255 23:23:08.041115 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 23:23:08.044405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 23:23:08.044489 ==
4258 23:23:08.047577 Write leveling (Byte 0): 34 => 34
4259 23:23:08.051289 Write leveling (Byte 1): 30 => 30
4260 23:23:08.054368 DramcWriteLeveling(PI) end<-----
4261 23:23:08.054451
4262 23:23:08.054517 ==
4263 23:23:08.057833 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 23:23:08.060743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 23:23:08.064389 ==
4266 23:23:08.064496 [Gating] SW mode calibration
4267 23:23:08.074112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4268 23:23:08.077564 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4269 23:23:08.081386 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4270 23:23:08.087211 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4271 23:23:08.090794 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4272 23:23:08.094211 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
4273 23:23:08.100439 0 9 16 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)
4274 23:23:08.103835 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4275 23:23:08.107273 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4276 23:23:09.930586 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4277 23:23:09.930730 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4278 23:23:09.930816 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4279 23:23:09.930880 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4280 23:23:09.930942 0 10 12 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
4281 23:23:09.931006 0 10 16 | B1->B0 | 3838 4040 | 0 0 | (0 0) (0 0)
4282 23:23:09.931090 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4283 23:23:09.931170 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 23:23:09.931249 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 23:23:09.931329 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 23:23:09.931409 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 23:23:09.931487 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4288 23:23:09.931584 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4289 23:23:09.931690 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4290 23:23:09.931790 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 23:23:09.931887 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 23:23:09.931983 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 23:23:09.932061 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 23:23:09.932138 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 23:23:09.932216 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 23:23:09.932311 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 23:23:09.932407 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 23:23:09.932503 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 23:23:09.932598 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 23:23:09.932694 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 23:23:09.932789 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 23:23:09.932884 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 23:23:09.932979 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 23:23:09.933085 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 23:23:09.933193 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4306 23:23:09.933295 Total UI for P1: 0, mck2ui 16
4307 23:23:09.933376 best dqsien dly found for B0: ( 0, 13, 14)
4308 23:23:09.933474 Total UI for P1: 0, mck2ui 16
4309 23:23:09.933571 best dqsien dly found for B1: ( 0, 13, 14)
4310 23:23:09.933668 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4311 23:23:09.933765 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4312 23:23:09.933861
4313 23:23:09.933957 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4314 23:23:09.934053 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4315 23:23:09.934149 [Gating] SW calibration Done
4316 23:23:09.934244 ==
4317 23:23:09.934340 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 23:23:09.934435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 23:23:09.934531 ==
4320 23:23:09.934626 RX Vref Scan: 0
4321 23:23:09.934721
4322 23:23:09.934816 RX Vref 0 -> 0, step: 1
4323 23:23:09.934911
4324 23:23:09.935006 RX Delay -230 -> 252, step: 16
4325 23:23:09.935103 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4326 23:23:09.935199 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4327 23:23:09.935295 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4328 23:23:09.935391 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4329 23:23:09.935486 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4330 23:23:09.935580 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4331 23:23:09.935686 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4332 23:23:09.935782 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4333 23:23:09.935878 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4334 23:23:09.935972 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4335 23:23:09.936067 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4336 23:23:09.936162 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4337 23:23:09.936257 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4338 23:23:09.936352 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4339 23:23:09.936446 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4340 23:23:09.936540 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4341 23:23:09.936634 ==
4342 23:23:09.936729 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 23:23:09.936823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 23:23:09.936918 ==
4345 23:23:09.937012 DQS Delay:
4346 23:23:09.937107 DQS0 = 0, DQS1 = 0
4347 23:23:09.937201 DQM Delay:
4348 23:23:09.937296 DQM0 = 42, DQM1 = 34
4349 23:23:09.937390 DQ Delay:
4350 23:23:09.937494 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4351 23:23:09.937592 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4352 23:23:09.937688 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4353 23:23:09.937784 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4354 23:23:09.937879
4355 23:23:09.937974
4356 23:23:09.938069 ==
4357 23:23:09.938164 Dram Type= 6, Freq= 0, CH_0, rank 1
4358 23:23:09.938259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 23:23:09.938353 ==
4360 23:23:09.938460
4361 23:23:09.938553
4362 23:23:09.938647 TX Vref Scan disable
4363 23:23:09.938742 == TX Byte 0 ==
4364 23:23:09.938841 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4365 23:23:09.938936 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4366 23:23:09.939027 == TX Byte 1 ==
4367 23:23:09.939117 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4368 23:23:09.939206 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4369 23:23:09.939294 ==
4370 23:23:09.939381 Dram Type= 6, Freq= 0, CH_0, rank 1
4371 23:23:09.939469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 23:23:09.939558 ==
4373 23:23:09.939645
4374 23:23:09.939743
4375 23:23:09.939831 TX Vref Scan disable
4376 23:23:09.939917 == TX Byte 0 ==
4377 23:23:09.940005 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4378 23:23:09.940092 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4379 23:23:09.940179 == TX Byte 1 ==
4380 23:23:09.940264 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4381 23:23:09.940351 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4382 23:23:09.940437
4383 23:23:09.940522 [DATLAT]
4384 23:23:09.940607 Freq=600, CH0 RK1
4385 23:23:09.940694
4386 23:23:09.940778 DATLAT Default: 0x9
4387 23:23:09.940865 0, 0xFFFF, sum = 0
4388 23:23:09.940955 1, 0xFFFF, sum = 0
4389 23:23:09.941042 2, 0xFFFF, sum = 0
4390 23:23:09.941129 3, 0xFFFF, sum = 0
4391 23:23:09.941230 4, 0xFFFF, sum = 0
4392 23:23:09.941324 5, 0xFFFF, sum = 0
4393 23:23:09.941414 6, 0xFFFF, sum = 0
4394 23:23:09.941506 7, 0xFFFF, sum = 0
4395 23:23:09.941595 8, 0x0, sum = 1
4396 23:23:09.941682 9, 0x0, sum = 2
4397 23:23:09.941769 10, 0x0, sum = 3
4398 23:23:09.941859 11, 0x0, sum = 4
4399 23:23:09.942169 best_step = 9
4400 23:23:09.942266
4401 23:23:09.942355 ==
4402 23:23:09.942444 Dram Type= 6, Freq= 0, CH_0, rank 1
4403 23:23:09.942532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 23:23:09.942620 ==
4405 23:23:09.942708 RX Vref Scan: 0
4406 23:23:09.942795
4407 23:23:09.942883 RX Vref 0 -> 0, step: 1
4408 23:23:09.942969
4409 23:23:09.943055 RX Delay -195 -> 252, step: 8
4410 23:23:09.943140 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4411 23:23:09.943226 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4412 23:23:09.943313 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4413 23:23:09.943400 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4414 23:23:09.943486 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4415 23:23:09.943572 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4416 23:23:09.943658 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4417 23:23:09.943754 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4418 23:23:09.943842 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4419 23:23:09.943929 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4420 23:23:09.944015 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4421 23:23:09.944101 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4422 23:23:09.944187 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4423 23:23:09.944273 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4424 23:23:09.944359 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4425 23:23:09.944444 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4426 23:23:09.944528 ==
4427 23:23:09.944613 Dram Type= 6, Freq= 0, CH_0, rank 1
4428 23:23:09.944700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 23:23:09.944786 ==
4430 23:23:09.944872 DQS Delay:
4431 23:23:09.944962 DQS0 = 0, DQS1 = 0
4432 23:23:09.945044 DQM Delay:
4433 23:23:09.945125 DQM0 = 41, DQM1 = 33
4434 23:23:09.945209 DQ Delay:
4435 23:23:09.945289 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4436 23:23:09.945373 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4437 23:23:09.945461 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4438 23:23:09.945549 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4439 23:23:09.945636
4440 23:23:09.945723
4441 23:23:09.945810 [DQSOSCAuto] RK1, (LSB)MR18= 0x580d, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
4442 23:23:09.945900 CH0 RK1: MR19=808, MR18=580D
4443 23:23:09.945989 CH0_RK1: MR19=0x808, MR18=0x580D, DQSOSC=393, MR23=63, INC=169, DEC=113
4444 23:23:09.946077 [RxdqsGatingPostProcess] freq 600
4445 23:23:09.946163 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4446 23:23:09.946248 Pre-setting of DQS Precalculation
4447 23:23:09.946342 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4448 23:23:09.946440 ==
4449 23:23:09.946539 Dram Type= 6, Freq= 0, CH_1, rank 0
4450 23:23:09.946640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 23:23:09.946739 ==
4452 23:23:09.946836 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4453 23:23:09.946947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4454 23:23:09.947055 [CA 0] Center 35 (5~66) winsize 62
4455 23:23:09.947151 [CA 1] Center 35 (5~66) winsize 62
4456 23:23:09.947241 [CA 2] Center 34 (4~65) winsize 62
4457 23:23:09.947329 [CA 3] Center 33 (3~64) winsize 62
4458 23:23:09.947416 [CA 4] Center 34 (4~64) winsize 61
4459 23:23:09.947501 [CA 5] Center 33 (3~64) winsize 62
4460 23:23:09.947586
4461 23:23:09.947685 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4462 23:23:09.947774
4463 23:23:09.947860 [CATrainingPosCal] consider 1 rank data
4464 23:23:09.947949 u2DelayCellTimex100 = 270/100 ps
4465 23:23:09.948035 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4466 23:23:09.948121 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4467 23:23:09.948207 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4468 23:23:09.948292 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4469 23:23:09.948377 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4470 23:23:09.948462 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4471 23:23:09.948546
4472 23:23:09.948630 CA PerBit enable=1, Macro0, CA PI delay=33
4473 23:23:09.948714
4474 23:23:09.948799 [CBTSetCACLKResult] CA Dly = 33
4475 23:23:09.948883 CS Dly: 4 (0~35)
4476 23:23:09.948967 ==
4477 23:23:09.949052 Dram Type= 6, Freq= 0, CH_1, rank 1
4478 23:23:09.949137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 23:23:09.949221 ==
4480 23:23:09.949307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4481 23:23:09.949393 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4482 23:23:09.949479 [CA 0] Center 35 (5~66) winsize 62
4483 23:23:09.949564 [CA 1] Center 36 (6~66) winsize 61
4484 23:23:09.949649 [CA 2] Center 34 (4~65) winsize 62
4485 23:23:09.949733 [CA 3] Center 34 (3~65) winsize 63
4486 23:23:09.949818 [CA 4] Center 34 (4~65) winsize 62
4487 23:23:09.949902 [CA 5] Center 34 (3~65) winsize 63
4488 23:23:09.949986
4489 23:23:09.950070 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4490 23:23:09.950154
4491 23:23:09.950238 [CATrainingPosCal] consider 2 rank data
4492 23:23:09.950323 u2DelayCellTimex100 = 270/100 ps
4493 23:23:09.950408 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4494 23:23:09.950492 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4495 23:23:09.950577 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4496 23:23:09.950662 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4497 23:23:09.950746 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4498 23:23:09.950831 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4499 23:23:09.950915
4500 23:23:09.951000 CA PerBit enable=1, Macro0, CA PI delay=33
4501 23:23:09.951083
4502 23:23:09.951167 [CBTSetCACLKResult] CA Dly = 33
4503 23:23:09.951252 CS Dly: 4 (0~36)
4504 23:23:09.951335
4505 23:23:09.951419 ----->DramcWriteLeveling(PI) begin...
4506 23:23:09.951505 ==
4507 23:23:09.951590 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 23:23:09.951680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 23:23:09.951740 ==
4510 23:23:09.951796 Write leveling (Byte 0): 29 => 29
4511 23:23:09.951852 Write leveling (Byte 1): 29 => 29
4512 23:23:09.951907 DramcWriteLeveling(PI) end<-----
4513 23:23:09.951962
4514 23:23:09.952016 ==
4515 23:23:09.952072 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 23:23:09.952127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 23:23:09.952183 ==
4518 23:23:09.952238 [Gating] SW mode calibration
4519 23:23:09.952293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4520 23:23:09.952349 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4521 23:23:09.952404 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4522 23:23:09.952460 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4523 23:23:09.952714 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4524 23:23:09.952776 0 9 12 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 1)
4525 23:23:09.952832 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4526 23:23:09.952888 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4527 23:23:09.952943 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4528 23:23:09.952999 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4529 23:23:09.953054 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4530 23:23:09.953109 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4531 23:23:09.953164 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4532 23:23:09.953219 0 10 12 | B1->B0 | 2f2f 3737 | 0 0 | (1 1) (0 0)
4533 23:23:09.953274 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4534 23:23:09.953329 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4535 23:23:09.953384 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4536 23:23:09.953440 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 23:23:09.953495 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4538 23:23:09.953550 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4539 23:23:09.953605 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 23:23:09.953659 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4541 23:23:09.953714 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 23:23:09.953768 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 23:23:09.953822 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 23:23:09.953877 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 23:23:09.953931 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 23:23:09.953986 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 23:23:09.954041 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 23:23:09.954096 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 23:23:09.954151 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 23:23:09.954206 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 23:23:09.954260 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 23:23:09.954315 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 23:23:09.954371 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 23:23:09.954425 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 23:23:09.954481 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 23:23:09.954537 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 23:23:09.954592 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4558 23:23:09.954647 Total UI for P1: 0, mck2ui 16
4559 23:23:09.954702 best dqsien dly found for B0: ( 0, 13, 14)
4560 23:23:09.954756 Total UI for P1: 0, mck2ui 16
4561 23:23:09.954812 best dqsien dly found for B1: ( 0, 13, 14)
4562 23:23:09.954866 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4563 23:23:09.954922 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4564 23:23:09.954976
4565 23:23:09.955031 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4566 23:23:09.955087 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4567 23:23:09.955141 [Gating] SW calibration Done
4568 23:23:09.955196 ==
4569 23:23:09.955250 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 23:23:09.955305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 23:23:09.955360 ==
4572 23:23:09.955414 RX Vref Scan: 0
4573 23:23:09.955469
4574 23:23:09.955523 RX Vref 0 -> 0, step: 1
4575 23:23:09.955577
4576 23:23:09.955632 RX Delay -230 -> 252, step: 16
4577 23:23:09.955704 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4578 23:23:09.955762 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4579 23:23:09.955817 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4580 23:23:09.955872 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4581 23:23:09.955927 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4582 23:23:09.955982 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4583 23:23:09.956037 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4584 23:23:09.956092 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4585 23:23:09.956147 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4586 23:23:09.956202 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4587 23:23:09.956256 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4588 23:23:09.956312 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4589 23:23:09.956367 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4590 23:23:09.956421 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4591 23:23:09.956476 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4592 23:23:09.956531 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4593 23:23:09.956586 ==
4594 23:23:09.956641 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 23:23:09.956696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 23:23:09.956750 ==
4597 23:23:09.956805 DQS Delay:
4598 23:23:09.956860 DQS0 = 0, DQS1 = 0
4599 23:23:09.956914 DQM Delay:
4600 23:23:09.956969 DQM0 = 46, DQM1 = 36
4601 23:23:09.957024 DQ Delay:
4602 23:23:09.957079 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4603 23:23:09.957134 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4604 23:23:09.957189 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4605 23:23:09.957244 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4606 23:23:09.957298
4607 23:23:09.957352
4608 23:23:09.957407 ==
4609 23:23:09.957461 Dram Type= 6, Freq= 0, CH_1, rank 0
4610 23:23:09.957516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 23:23:09.957571 ==
4612 23:23:09.957626
4613 23:23:09.957681
4614 23:23:09.957735 TX Vref Scan disable
4615 23:23:09.957790 == TX Byte 0 ==
4616 23:23:09.957845 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4617 23:23:09.957904 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4618 23:23:09.957959 == TX Byte 1 ==
4619 23:23:09.958013 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4620 23:23:09.958068 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4621 23:23:09.958134 ==
4622 23:23:09.958189 Dram Type= 6, Freq= 0, CH_1, rank 0
4623 23:23:09.958244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 23:23:09.958309 ==
4625 23:23:09.958365
4626 23:23:09.958419
4627 23:23:09.958485 TX Vref Scan disable
4628 23:23:09.958541 == TX Byte 0 ==
4629 23:23:09.958596 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4630 23:23:09.958676 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4631 23:23:09.958761 == TX Byte 1 ==
4632 23:23:09.958836 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4633 23:23:09.958893 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4634 23:23:09.958948
4635 23:23:09.959205 [DATLAT]
4636 23:23:09.959295 Freq=600, CH1 RK0
4637 23:23:09.959382
4638 23:23:09.959468 DATLAT Default: 0x9
4639 23:23:09.959554 0, 0xFFFF, sum = 0
4640 23:23:09.959640 1, 0xFFFF, sum = 0
4641 23:23:09.959717 2, 0xFFFF, sum = 0
4642 23:23:09.959775 3, 0xFFFF, sum = 0
4643 23:23:09.959831 4, 0xFFFF, sum = 0
4644 23:23:09.959887 5, 0xFFFF, sum = 0
4645 23:23:09.959943 6, 0xFFFF, sum = 0
4646 23:23:09.959999 7, 0xFFFF, sum = 0
4647 23:23:09.960054 8, 0x0, sum = 1
4648 23:23:09.960110 9, 0x0, sum = 2
4649 23:23:09.960166 10, 0x0, sum = 3
4650 23:23:09.960222 11, 0x0, sum = 4
4651 23:23:09.960278 best_step = 9
4652 23:23:09.960332
4653 23:23:09.960386 ==
4654 23:23:09.960440 Dram Type= 6, Freq= 0, CH_1, rank 0
4655 23:23:09.960496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 23:23:09.960551 ==
4657 23:23:09.960606 RX Vref Scan: 1
4658 23:23:09.960661
4659 23:23:09.960715 RX Vref 0 -> 0, step: 1
4660 23:23:09.960770
4661 23:23:09.960824 RX Delay -195 -> 252, step: 8
4662 23:23:09.960879
4663 23:23:09.960933 Set Vref, RX VrefLevel [Byte0]: 53
4664 23:23:09.960989 [Byte1]: 60
4665 23:23:09.961043
4666 23:23:09.961098 Final RX Vref Byte 0 = 53 to rank0
4667 23:23:09.961153 Final RX Vref Byte 1 = 60 to rank0
4668 23:23:09.961208 Final RX Vref Byte 0 = 53 to rank1
4669 23:23:09.961263 Final RX Vref Byte 1 = 60 to rank1==
4670 23:23:09.961317 Dram Type= 6, Freq= 0, CH_1, rank 0
4671 23:23:09.961372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 23:23:09.961427 ==
4673 23:23:09.961481 DQS Delay:
4674 23:23:09.961536 DQS0 = 0, DQS1 = 0
4675 23:23:09.961591 DQM Delay:
4676 23:23:09.961645 DQM0 = 47, DQM1 = 37
4677 23:23:09.961700 DQ Delay:
4678 23:23:09.961755 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =40
4679 23:23:09.961810 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4680 23:23:09.961865 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4681 23:23:09.961920 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4682 23:23:09.961974
4683 23:23:09.962028
4684 23:23:09.962082 [DQSOSCAuto] RK0, (LSB)MR18= 0x482d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4685 23:23:09.962137 CH1 RK0: MR19=808, MR18=482D
4686 23:23:09.962192 CH1_RK0: MR19=0x808, MR18=0x482D, DQSOSC=396, MR23=63, INC=167, DEC=111
4687 23:23:09.962247
4688 23:23:09.962302 ----->DramcWriteLeveling(PI) begin...
4689 23:23:09.962358 ==
4690 23:23:09.962412 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 23:23:09.962467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 23:23:09.962522 ==
4693 23:23:09.962577 Write leveling (Byte 0): 29 => 29
4694 23:23:09.962632 Write leveling (Byte 1): 32 => 32
4695 23:23:09.962687 DramcWriteLeveling(PI) end<-----
4696 23:23:09.962741
4697 23:23:09.962795 ==
4698 23:23:09.962850 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 23:23:09.962905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 23:23:09.962960 ==
4701 23:23:09.963013 [Gating] SW mode calibration
4702 23:23:09.963068 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4703 23:23:09.963123 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4704 23:23:09.963178 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4705 23:23:09.963234 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4706 23:23:09.963289 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4707 23:23:09.963344 0 9 12 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 1)
4708 23:23:09.963399 0 9 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4709 23:23:09.963454 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4710 23:23:09.963509 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4711 23:23:09.963587 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4712 23:23:09.963689 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4713 23:23:09.963749 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4714 23:23:09.963805 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4715 23:23:09.963861 0 10 12 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
4716 23:23:09.963917 0 10 16 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
4717 23:23:09.963973 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4718 23:23:09.964028 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4719 23:23:09.964082 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 23:23:09.964137 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 23:23:09.964192 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 23:23:09.964247 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 23:23:09.964302 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4724 23:23:09.964357 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 23:23:09.964412 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 23:23:09.964466 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 23:23:09.964521 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 23:23:09.964576 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 23:23:09.964630 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 23:23:09.964685 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 23:23:09.964740 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 23:23:09.964794 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 23:23:09.964849 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 23:23:09.964903 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 23:23:09.964958 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 23:23:09.965013 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 23:23:09.965068 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 23:23:09.965122 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 23:23:09.965177 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4740 23:23:09.965232 Total UI for P1: 0, mck2ui 16
4741 23:23:09.965287 best dqsien dly found for B1: ( 0, 13, 10)
4742 23:23:09.965342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4743 23:23:09.965396 Total UI for P1: 0, mck2ui 16
4744 23:23:09.965451 best dqsien dly found for B0: ( 0, 13, 12)
4745 23:23:09.965507 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4746 23:23:09.965562 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4747 23:23:09.965616
4748 23:23:09.965671 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4749 23:23:09.965726 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4750 23:23:09.965781 [Gating] SW calibration Done
4751 23:23:09.965836 ==
4752 23:23:09.965890 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 23:23:09.965946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 23:23:09.966001 ==
4755 23:23:09.966056 RX Vref Scan: 0
4756 23:23:09.966110
4757 23:23:09.966165 RX Vref 0 -> 0, step: 1
4758 23:23:09.966220
4759 23:23:09.966467 RX Delay -230 -> 252, step: 16
4760 23:23:09.966532 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4761 23:23:09.966589 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4762 23:23:09.966644 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4763 23:23:09.966699 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4764 23:23:09.966754 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4765 23:23:09.966809 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4766 23:23:09.966863 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4767 23:23:09.966918 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4768 23:23:09.966973 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4769 23:23:09.967027 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4770 23:23:09.967082 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4771 23:23:09.967137 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4772 23:23:09.967191 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4773 23:23:09.967246 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4774 23:23:09.967300 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4775 23:23:09.967355 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4776 23:23:09.967410 ==
4777 23:23:09.967464 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 23:23:09.967520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 23:23:09.967575 ==
4780 23:23:09.967629 DQS Delay:
4781 23:23:09.967692 DQS0 = 0, DQS1 = 0
4782 23:23:09.967748 DQM Delay:
4783 23:23:09.967803 DQM0 = 45, DQM1 = 37
4784 23:23:09.967857 DQ Delay:
4785 23:23:09.967912 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4786 23:23:09.967966 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4787 23:23:09.968021 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4788 23:23:09.968077 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4789 23:23:09.968133
4790 23:23:09.968187
4791 23:23:09.968241 ==
4792 23:23:09.968296 Dram Type= 6, Freq= 0, CH_1, rank 1
4793 23:23:09.968351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4794 23:23:09.968405 ==
4795 23:23:09.968461
4796 23:23:09.968515
4797 23:23:09.968570 TX Vref Scan disable
4798 23:23:09.968625 == TX Byte 0 ==
4799 23:23:09.968680 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4800 23:23:09.968735 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4801 23:23:09.968791 == TX Byte 1 ==
4802 23:23:09.968845 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4803 23:23:09.968904 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4804 23:23:09.968959 ==
4805 23:23:09.969014 Dram Type= 6, Freq= 0, CH_1, rank 1
4806 23:23:09.969077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4807 23:23:09.969137 ==
4808 23:23:09.969192
4809 23:23:09.969246
4810 23:23:09.969312 TX Vref Scan disable
4811 23:23:09.969367 == TX Byte 0 ==
4812 23:23:09.969421 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4813 23:23:09.969483 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4814 23:23:09.969538 == TX Byte 1 ==
4815 23:23:09.969592 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4816 23:23:09.969652 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4817 23:23:09.969707
4818 23:23:09.969762 [DATLAT]
4819 23:23:09.969819 Freq=600, CH1 RK1
4820 23:23:09.969875
4821 23:23:09.969929 DATLAT Default: 0x9
4822 23:23:09.969997 0, 0xFFFF, sum = 0
4823 23:23:09.970092 1, 0xFFFF, sum = 0
4824 23:23:09.970190 2, 0xFFFF, sum = 0
4825 23:23:09.970293 3, 0xFFFF, sum = 0
4826 23:23:09.970392 4, 0xFFFF, sum = 0
4827 23:23:09.970487 5, 0xFFFF, sum = 0
4828 23:23:09.970596 6, 0xFFFF, sum = 0
4829 23:23:09.970687 7, 0xFFFF, sum = 0
4830 23:23:09.970774 8, 0x0, sum = 1
4831 23:23:09.970887 9, 0x0, sum = 2
4832 23:23:09.970983 10, 0x0, sum = 3
4833 23:23:09.971072 11, 0x0, sum = 4
4834 23:23:09.971160 best_step = 9
4835 23:23:09.971244
4836 23:23:09.971328 ==
4837 23:23:09.971414 Dram Type= 6, Freq= 0, CH_1, rank 1
4838 23:23:09.971499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4839 23:23:09.971587 ==
4840 23:23:09.971678 RX Vref Scan: 0
4841 23:23:09.971765
4842 23:23:09.971849 RX Vref 0 -> 0, step: 1
4843 23:23:09.971933
4844 23:23:09.972017 RX Delay -195 -> 252, step: 8
4845 23:23:09.972102 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4846 23:23:09.972187 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4847 23:23:09.972272 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4848 23:23:09.972357 iDelay=213, Bit 3, Center 36 (-115 ~ 188) 304
4849 23:23:09.972441 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4850 23:23:09.972526 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4851 23:23:09.972611 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4852 23:23:09.972695 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4853 23:23:09.972780 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4854 23:23:09.972864 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4855 23:23:09.972949 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4856 23:23:09.973034 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4857 23:23:09.973118 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4858 23:23:09.973203 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4859 23:23:09.973288 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4860 23:23:09.973373 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4861 23:23:09.973457 ==
4862 23:23:09.973541 Dram Type= 6, Freq= 0, CH_1, rank 1
4863 23:23:09.973625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4864 23:23:09.973710 ==
4865 23:23:09.973796 DQS Delay:
4866 23:23:09.973899 DQS0 = 0, DQS1 = 0
4867 23:23:09.973992 DQM Delay:
4868 23:23:09.974077 DQM0 = 44, DQM1 = 37
4869 23:23:09.974162 DQ Delay:
4870 23:23:09.974247 DQ0 =44, DQ1 =40, DQ2 =32, DQ3 =36
4871 23:23:09.974332 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =40
4872 23:23:09.974417 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4873 23:23:09.974503 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4874 23:23:09.974587
4875 23:23:09.974671
4876 23:23:09.974757 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4877 23:23:09.974843 CH1 RK1: MR19=808, MR18=2E22
4878 23:23:09.974928 CH1_RK1: MR19=0x808, MR18=0x2E22, DQSOSC=401, MR23=63, INC=163, DEC=108
4879 23:23:09.975013 [RxdqsGatingPostProcess] freq 600
4880 23:23:09.975099 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4881 23:23:09.975184 Pre-setting of DQS Precalculation
4882 23:23:09.975269 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4883 23:23:09.975356 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4884 23:23:09.975442 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4885 23:23:09.975526
4886 23:23:09.975609
4887 23:23:09.975697 [Calibration Summary] 1200 Mbps
4888 23:23:09.975756 CH 0, Rank 0
4889 23:23:09.975812 SW Impedance : PASS
4890 23:23:09.975867 DUTY Scan : NO K
4891 23:23:09.975922 ZQ Calibration : PASS
4892 23:23:09.975978 Jitter Meter : NO K
4893 23:23:09.976225 CBT Training : PASS
4894 23:23:09.976289 Write leveling : PASS
4895 23:23:09.976346 RX DQS gating : PASS
4896 23:23:09.976401 RX DQ/DQS(RDDQC) : PASS
4897 23:23:09.976457 TX DQ/DQS : PASS
4898 23:23:09.976512 RX DATLAT : PASS
4899 23:23:09.976567 RX DQ/DQS(Engine): PASS
4900 23:23:09.976622 TX OE : NO K
4901 23:23:09.976678 All Pass.
4902 23:23:09.976732
4903 23:23:09.976787 CH 0, Rank 1
4904 23:23:09.976842 SW Impedance : PASS
4905 23:23:09.976897 DUTY Scan : NO K
4906 23:23:09.976953 ZQ Calibration : PASS
4907 23:23:09.977008 Jitter Meter : NO K
4908 23:23:09.977081 CBT Training : PASS
4909 23:23:09.977139 Write leveling : PASS
4910 23:23:09.977195 RX DQS gating : PASS
4911 23:23:09.977249 RX DQ/DQS(RDDQC) : PASS
4912 23:23:09.977304 TX DQ/DQS : PASS
4913 23:23:09.977359 RX DATLAT : PASS
4914 23:23:09.977414 RX DQ/DQS(Engine): PASS
4915 23:23:09.977469 TX OE : NO K
4916 23:23:09.977524 All Pass.
4917 23:23:09.977579
4918 23:23:09.977634 CH 1, Rank 0
4919 23:23:09.977689 SW Impedance : PASS
4920 23:23:09.977744 DUTY Scan : NO K
4921 23:23:09.977799 ZQ Calibration : PASS
4922 23:23:09.977854 Jitter Meter : NO K
4923 23:23:09.977909 CBT Training : PASS
4924 23:23:09.977963 Write leveling : PASS
4925 23:23:09.978018 RX DQS gating : PASS
4926 23:23:09.978073 RX DQ/DQS(RDDQC) : PASS
4927 23:23:09.978128 TX DQ/DQS : PASS
4928 23:23:09.978183 RX DATLAT : PASS
4929 23:23:09.978237 RX DQ/DQS(Engine): PASS
4930 23:23:09.978292 TX OE : NO K
4931 23:23:09.978347 All Pass.
4932 23:23:09.978401
4933 23:23:09.978456 CH 1, Rank 1
4934 23:23:09.978510 SW Impedance : PASS
4935 23:23:09.978565 DUTY Scan : NO K
4936 23:23:09.978621 ZQ Calibration : PASS
4937 23:23:09.978675 Jitter Meter : NO K
4938 23:23:09.978730 CBT Training : PASS
4939 23:23:09.978785 Write leveling : PASS
4940 23:23:09.979200 RX DQS gating : PASS
4941 23:23:09.979284 RX DQ/DQS(RDDQC) : PASS
4942 23:23:09.981943 TX DQ/DQS : PASS
4943 23:23:09.985700 RX DATLAT : PASS
4944 23:23:09.985784 RX DQ/DQS(Engine): PASS
4945 23:23:09.989173 TX OE : NO K
4946 23:23:09.989258 All Pass.
4947 23:23:09.989324
4948 23:23:09.991873 DramC Write-DBI off
4949 23:23:09.995277 PER_BANK_REFRESH: Hybrid Mode
4950 23:23:09.995397 TX_TRACKING: ON
4951 23:23:10.005199 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4952 23:23:10.008502 [FAST_K] Save calibration result to emmc
4953 23:23:10.012045 dramc_set_vcore_voltage set vcore to 662500
4954 23:23:10.015230 Read voltage for 933, 3
4955 23:23:10.015313 Vio18 = 0
4956 23:23:10.015381 Vcore = 662500
4957 23:23:10.018285 Vdram = 0
4958 23:23:10.018369 Vddq = 0
4959 23:23:10.018434 Vmddr = 0
4960 23:23:10.024744 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4961 23:23:10.028398 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4962 23:23:10.031885 MEM_TYPE=3, freq_sel=17
4963 23:23:10.034636 sv_algorithm_assistance_LP4_1600
4964 23:23:10.038589 ============ PULL DRAM RESETB DOWN ============
4965 23:23:10.044755 ========== PULL DRAM RESETB DOWN end =========
4966 23:23:10.048341 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4967 23:23:10.051009 ===================================
4968 23:23:10.054992 LPDDR4 DRAM CONFIGURATION
4969 23:23:10.057794 ===================================
4970 23:23:10.057879 EX_ROW_EN[0] = 0x0
4971 23:23:10.061189 EX_ROW_EN[1] = 0x0
4972 23:23:10.061273 LP4Y_EN = 0x0
4973 23:23:10.064134 WORK_FSP = 0x0
4974 23:23:10.064245 WL = 0x3
4975 23:23:10.067257 RL = 0x3
4976 23:23:10.071078 BL = 0x2
4977 23:23:10.071162 RPST = 0x0
4978 23:23:10.074068 RD_PRE = 0x0
4979 23:23:10.074168 WR_PRE = 0x1
4980 23:23:10.077559 WR_PST = 0x0
4981 23:23:10.077643 DBI_WR = 0x0
4982 23:23:10.080706 DBI_RD = 0x0
4983 23:23:10.080790 OTF = 0x1
4984 23:23:10.084057 ===================================
4985 23:23:10.087304 ===================================
4986 23:23:10.090798 ANA top config
4987 23:23:10.093949 ===================================
4988 23:23:10.094032 DLL_ASYNC_EN = 0
4989 23:23:10.097100 ALL_SLAVE_EN = 1
4990 23:23:10.100703 NEW_RANK_MODE = 1
4991 23:23:10.103945 DLL_IDLE_MODE = 1
4992 23:23:10.107175 LP45_APHY_COMB_EN = 1
4993 23:23:10.107256 TX_ODT_DIS = 1
4994 23:23:10.110308 NEW_8X_MODE = 1
4995 23:23:10.114079 ===================================
4996 23:23:10.117501 ===================================
4997 23:23:10.120182 data_rate = 1866
4998 23:23:10.123549 CKR = 1
4999 23:23:10.127248 DQ_P2S_RATIO = 8
5000 23:23:10.130167 ===================================
5001 23:23:10.130257 CA_P2S_RATIO = 8
5002 23:23:10.133698 DQ_CA_OPEN = 0
5003 23:23:10.136662 DQ_SEMI_OPEN = 0
5004 23:23:10.139955 CA_SEMI_OPEN = 0
5005 23:23:10.143539 CA_FULL_RATE = 0
5006 23:23:10.146491 DQ_CKDIV4_EN = 1
5007 23:23:10.150395 CA_CKDIV4_EN = 1
5008 23:23:10.150479 CA_PREDIV_EN = 0
5009 23:23:10.153483 PH8_DLY = 0
5010 23:23:10.156511 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5011 23:23:10.159624 DQ_AAMCK_DIV = 4
5012 23:23:10.163016 CA_AAMCK_DIV = 4
5013 23:23:10.166479 CA_ADMCK_DIV = 4
5014 23:23:10.166562 DQ_TRACK_CA_EN = 0
5015 23:23:10.169542 CA_PICK = 933
5016 23:23:10.172855 CA_MCKIO = 933
5017 23:23:10.176307 MCKIO_SEMI = 0
5018 23:23:10.179630 PLL_FREQ = 3732
5019 23:23:10.182677 DQ_UI_PI_RATIO = 32
5020 23:23:10.185811 CA_UI_PI_RATIO = 0
5021 23:23:10.189559 ===================================
5022 23:23:10.192741 ===================================
5023 23:23:10.192846 memory_type:LPDDR4
5024 23:23:10.196302 GP_NUM : 10
5025 23:23:10.199148 SRAM_EN : 1
5026 23:23:10.199231 MD32_EN : 0
5027 23:23:10.202221 ===================================
5028 23:23:10.205699 [ANA_INIT] >>>>>>>>>>>>>>
5029 23:23:10.209545 <<<<<< [CONFIGURE PHASE]: ANA_TX
5030 23:23:10.212683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5031 23:23:10.215734 ===================================
5032 23:23:10.219195 data_rate = 1866,PCW = 0X8f00
5033 23:23:10.222511 ===================================
5034 23:23:10.225689 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5035 23:23:10.228837 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5036 23:23:10.235704 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5037 23:23:10.239009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5038 23:23:10.242494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5039 23:23:10.245851 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5040 23:23:10.248996 [ANA_INIT] flow start
5041 23:23:10.252102 [ANA_INIT] PLL >>>>>>>>
5042 23:23:10.252186 [ANA_INIT] PLL <<<<<<<<
5043 23:23:10.255349 [ANA_INIT] MIDPI >>>>>>>>
5044 23:23:10.258715 [ANA_INIT] MIDPI <<<<<<<<
5045 23:23:10.261888 [ANA_INIT] DLL >>>>>>>>
5046 23:23:10.261975 [ANA_INIT] flow end
5047 23:23:10.265184 ============ LP4 DIFF to SE enter ============
5048 23:23:10.272144 ============ LP4 DIFF to SE exit ============
5049 23:23:10.272232 [ANA_INIT] <<<<<<<<<<<<<
5050 23:23:10.275573 [Flow] Enable top DCM control >>>>>
5051 23:23:10.278531 [Flow] Enable top DCM control <<<<<
5052 23:23:10.281737 Enable DLL master slave shuffle
5053 23:23:10.288185 ==============================================================
5054 23:23:10.291835 Gating Mode config
5055 23:23:10.294901 ==============================================================
5056 23:23:10.298206 Config description:
5057 23:23:10.308319 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5058 23:23:10.314521 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5059 23:23:10.317872 SELPH_MODE 0: By rank 1: By Phase
5060 23:23:10.324424 ==============================================================
5061 23:23:10.327891 GAT_TRACK_EN = 1
5062 23:23:10.331513 RX_GATING_MODE = 2
5063 23:23:10.334746 RX_GATING_TRACK_MODE = 2
5064 23:23:10.334831 SELPH_MODE = 1
5065 23:23:10.338090 PICG_EARLY_EN = 1
5066 23:23:10.340930 VALID_LAT_VALUE = 1
5067 23:23:10.347841 ==============================================================
5068 23:23:10.351224 Enter into Gating configuration >>>>
5069 23:23:10.354447 Exit from Gating configuration <<<<
5070 23:23:10.357466 Enter into DVFS_PRE_config >>>>>
5071 23:23:10.367793 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5072 23:23:10.370843 Exit from DVFS_PRE_config <<<<<
5073 23:23:10.374639 Enter into PICG configuration >>>>
5074 23:23:10.377374 Exit from PICG configuration <<<<
5075 23:23:10.381092 [RX_INPUT] configuration >>>>>
5076 23:23:10.383773 [RX_INPUT] configuration <<<<<
5077 23:23:10.387176 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5078 23:23:10.394159 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5079 23:23:10.400667 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5080 23:23:10.406954 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5081 23:23:10.414211 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5082 23:23:10.420263 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5083 23:23:10.423834 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5084 23:23:10.426667 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5085 23:23:10.429874 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5086 23:23:10.436532 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5087 23:23:10.440116 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5088 23:23:10.443385 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5089 23:23:10.446425 ===================================
5090 23:23:10.449874 LPDDR4 DRAM CONFIGURATION
5091 23:23:10.452628 ===================================
5092 23:23:10.456516 EX_ROW_EN[0] = 0x0
5093 23:23:10.456602 EX_ROW_EN[1] = 0x0
5094 23:23:10.459880 LP4Y_EN = 0x0
5095 23:23:10.459966 WORK_FSP = 0x0
5096 23:23:10.462750 WL = 0x3
5097 23:23:10.462835 RL = 0x3
5098 23:23:10.466078 BL = 0x2
5099 23:23:10.466163 RPST = 0x0
5100 23:23:10.469464 RD_PRE = 0x0
5101 23:23:10.469549 WR_PRE = 0x1
5102 23:23:10.472709 WR_PST = 0x0
5103 23:23:10.472795 DBI_WR = 0x0
5104 23:23:10.476008 DBI_RD = 0x0
5105 23:23:10.476124 OTF = 0x1
5106 23:23:10.479073 ===================================
5107 23:23:10.485996 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5108 23:23:10.488922 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5109 23:23:10.492367 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5110 23:23:10.495935 ===================================
5111 23:23:10.499115 LPDDR4 DRAM CONFIGURATION
5112 23:23:10.502743 ===================================
5113 23:23:10.505356 EX_ROW_EN[0] = 0x10
5114 23:23:10.505462 EX_ROW_EN[1] = 0x0
5115 23:23:10.508853 LP4Y_EN = 0x0
5116 23:23:10.508962 WORK_FSP = 0x0
5117 23:23:10.512296 WL = 0x3
5118 23:23:10.512378 RL = 0x3
5119 23:23:10.515635 BL = 0x2
5120 23:23:10.515756 RPST = 0x0
5121 23:23:10.519142 RD_PRE = 0x0
5122 23:23:10.519224 WR_PRE = 0x1
5123 23:23:10.521886 WR_PST = 0x0
5124 23:23:10.521969 DBI_WR = 0x0
5125 23:23:10.525796 DBI_RD = 0x0
5126 23:23:10.525878 OTF = 0x1
5127 23:23:10.528466 ===================================
5128 23:23:10.535070 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5129 23:23:10.540206 nWR fixed to 30
5130 23:23:10.543381 [ModeRegInit_LP4] CH0 RK0
5131 23:23:10.543463 [ModeRegInit_LP4] CH0 RK1
5132 23:23:10.547059 [ModeRegInit_LP4] CH1 RK0
5133 23:23:10.550397 [ModeRegInit_LP4] CH1 RK1
5134 23:23:10.550480 match AC timing 9
5135 23:23:10.557011 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5136 23:23:10.560016 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5137 23:23:10.563277 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5138 23:23:10.570007 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5139 23:23:10.573084 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5140 23:23:10.573167 ==
5141 23:23:10.576231 Dram Type= 6, Freq= 0, CH_0, rank 0
5142 23:23:10.579491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 23:23:10.579594 ==
5144 23:23:10.586501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5145 23:23:10.592565 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5146 23:23:10.596003 [CA 0] Center 37 (7~68) winsize 62
5147 23:23:10.599899 [CA 1] Center 37 (7~68) winsize 62
5148 23:23:10.603511 [CA 2] Center 34 (4~65) winsize 62
5149 23:23:10.606346 [CA 3] Center 35 (5~65) winsize 61
5150 23:23:10.609398 [CA 4] Center 34 (4~64) winsize 61
5151 23:23:10.612754 [CA 5] Center 33 (4~63) winsize 60
5152 23:23:10.612837
5153 23:23:10.615761 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5154 23:23:10.615898
5155 23:23:10.619554 [CATrainingPosCal] consider 1 rank data
5156 23:23:10.622479 u2DelayCellTimex100 = 270/100 ps
5157 23:23:10.626220 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5158 23:23:10.629117 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5159 23:23:10.632261 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5160 23:23:10.639038 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5161 23:23:10.642015 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5162 23:23:10.645880 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5163 23:23:10.645977
5164 23:23:10.648956 CA PerBit enable=1, Macro0, CA PI delay=33
5165 23:23:10.649039
5166 23:23:10.652199 [CBTSetCACLKResult] CA Dly = 33
5167 23:23:10.652282 CS Dly: 7 (0~38)
5168 23:23:10.652352 ==
5169 23:23:10.655821 Dram Type= 6, Freq= 0, CH_0, rank 1
5170 23:23:10.661902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 23:23:10.662015 ==
5172 23:23:10.665325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5173 23:23:10.671915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5174 23:23:10.675039 [CA 0] Center 37 (7~68) winsize 62
5175 23:23:10.678751 [CA 1] Center 37 (7~68) winsize 62
5176 23:23:10.681840 [CA 2] Center 34 (4~65) winsize 62
5177 23:23:10.685444 [CA 3] Center 34 (4~65) winsize 62
5178 23:23:10.688247 [CA 4] Center 33 (3~64) winsize 62
5179 23:23:10.691534 [CA 5] Center 33 (3~63) winsize 61
5180 23:23:10.691620
5181 23:23:10.694920 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5182 23:23:10.695005
5183 23:23:10.698244 [CATrainingPosCal] consider 2 rank data
5184 23:23:10.701687 u2DelayCellTimex100 = 270/100 ps
5185 23:23:10.704707 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5186 23:23:10.711337 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5187 23:23:10.714891 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5188 23:23:10.717911 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5189 23:23:10.721182 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5190 23:23:10.724449 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5191 23:23:10.724534
5192 23:23:10.727847 CA PerBit enable=1, Macro0, CA PI delay=33
5193 23:23:10.727934
5194 23:23:10.731429 [CBTSetCACLKResult] CA Dly = 33
5195 23:23:10.734713 CS Dly: 7 (0~39)
5196 23:23:10.734794
5197 23:23:10.738165 ----->DramcWriteLeveling(PI) begin...
5198 23:23:10.738252 ==
5199 23:23:10.740887 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 23:23:10.744546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 23:23:10.744632 ==
5202 23:23:10.748293 Write leveling (Byte 0): 31 => 31
5203 23:23:10.751056 Write leveling (Byte 1): 28 => 28
5204 23:23:10.754513 DramcWriteLeveling(PI) end<-----
5205 23:23:10.754597
5206 23:23:10.754664 ==
5207 23:23:10.757593 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 23:23:10.761075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 23:23:10.761161 ==
5210 23:23:10.764041 [Gating] SW mode calibration
5211 23:23:10.770402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5212 23:23:10.777341 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5213 23:23:10.780364 0 14 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5214 23:23:10.787135 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5215 23:23:10.790602 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5216 23:23:10.793472 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5217 23:23:10.800199 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5218 23:23:10.803833 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5219 23:23:10.806929 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5220 23:23:10.813413 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
5221 23:23:10.816625 0 15 0 | B1->B0 | 3333 2828 | 1 0 | (0 1) (1 1)
5222 23:23:10.819816 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5223 23:23:10.826939 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5224 23:23:10.829822 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5225 23:23:10.833304 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5226 23:23:10.839862 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5227 23:23:10.842867 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5228 23:23:10.846090 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5229 23:23:10.852565 1 0 0 | B1->B0 | 3030 4545 | 0 0 | (1 1) (0 0)
5230 23:23:10.855979 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5231 23:23:10.859555 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5232 23:23:10.865684 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5233 23:23:10.869339 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 23:23:10.872372 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 23:23:10.879021 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5236 23:23:10.882030 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5237 23:23:10.885363 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5238 23:23:10.892391 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 23:23:10.895449 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 23:23:10.898751 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 23:23:10.905178 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 23:23:10.908579 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 23:23:10.911806 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 23:23:10.918427 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 23:23:10.922145 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 23:23:10.924984 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 23:23:10.931419 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 23:23:10.934781 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 23:23:10.938392 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 23:23:10.945183 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 23:23:10.947925 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 23:23:10.951083 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5253 23:23:10.958247 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5254 23:23:10.960826 Total UI for P1: 0, mck2ui 16
5255 23:23:10.964560 best dqsien dly found for B0: ( 1, 2, 28)
5256 23:23:10.967509 Total UI for P1: 0, mck2ui 16
5257 23:23:10.970650 best dqsien dly found for B1: ( 1, 2, 30)
5258 23:23:10.974252 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5259 23:23:10.977387 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5260 23:23:10.977497
5261 23:23:10.980768 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5262 23:23:10.984339 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5263 23:23:10.987437 [Gating] SW calibration Done
5264 23:23:10.987555 ==
5265 23:23:10.990752 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 23:23:10.994144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 23:23:10.994262 ==
5268 23:23:10.997021 RX Vref Scan: 0
5269 23:23:10.997118
5270 23:23:11.000859 RX Vref 0 -> 0, step: 1
5271 23:23:11.000945
5272 23:23:11.001011 RX Delay -80 -> 252, step: 8
5273 23:23:11.007294 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5274 23:23:11.010309 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5275 23:23:11.013352 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5276 23:23:11.016814 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5277 23:23:11.020508 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5278 23:23:11.023324 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5279 23:23:11.029983 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5280 23:23:11.033377 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5281 23:23:11.036509 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5282 23:23:11.040215 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5283 23:23:11.043185 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5284 23:23:11.049705 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5285 23:23:11.053201 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5286 23:23:11.056531 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5287 23:23:11.059354 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5288 23:23:11.063257 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5289 23:23:11.066603 ==
5290 23:23:11.069826 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 23:23:11.072689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 23:23:11.072792 ==
5293 23:23:11.072885 DQS Delay:
5294 23:23:11.076086 DQS0 = 0, DQS1 = 0
5295 23:23:11.076202 DQM Delay:
5296 23:23:11.079564 DQM0 = 97, DQM1 = 85
5297 23:23:11.079680 DQ Delay:
5298 23:23:11.082411 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5299 23:23:11.086245 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5300 23:23:11.089508 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5301 23:23:11.092364 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5302 23:23:11.092455
5303 23:23:11.092520
5304 23:23:11.092580 ==
5305 23:23:11.096338 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 23:23:11.099301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 23:23:11.099419 ==
5308 23:23:11.099513
5309 23:23:11.102804
5310 23:23:11.102901 TX Vref Scan disable
5311 23:23:11.106001 == TX Byte 0 ==
5312 23:23:11.109319 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5313 23:23:11.112329 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5314 23:23:11.115485 == TX Byte 1 ==
5315 23:23:11.119198 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5316 23:23:11.122549 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5317 23:23:11.122646 ==
5318 23:23:11.125600 Dram Type= 6, Freq= 0, CH_0, rank 0
5319 23:23:11.132139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 23:23:11.132215 ==
5321 23:23:11.132279
5322 23:23:11.132346
5323 23:23:11.135426 TX Vref Scan disable
5324 23:23:11.135523 == TX Byte 0 ==
5325 23:23:11.142318 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5326 23:23:11.145397 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5327 23:23:11.145472 == TX Byte 1 ==
5328 23:23:11.151648 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5329 23:23:11.155185 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5330 23:23:11.155256
5331 23:23:11.155350 [DATLAT]
5332 23:23:11.158597 Freq=933, CH0 RK0
5333 23:23:11.158673
5334 23:23:11.158734 DATLAT Default: 0xd
5335 23:23:11.162067 0, 0xFFFF, sum = 0
5336 23:23:11.162137 1, 0xFFFF, sum = 0
5337 23:23:11.165604 2, 0xFFFF, sum = 0
5338 23:23:11.165741 3, 0xFFFF, sum = 0
5339 23:23:11.168571 4, 0xFFFF, sum = 0
5340 23:23:11.168667 5, 0xFFFF, sum = 0
5341 23:23:11.171649 6, 0xFFFF, sum = 0
5342 23:23:11.175287 7, 0xFFFF, sum = 0
5343 23:23:11.175360 8, 0xFFFF, sum = 0
5344 23:23:11.178397 9, 0xFFFF, sum = 0
5345 23:23:11.178502 10, 0x0, sum = 1
5346 23:23:11.178573 11, 0x0, sum = 2
5347 23:23:11.181481 12, 0x0, sum = 3
5348 23:23:11.181551 13, 0x0, sum = 4
5349 23:23:11.185129 best_step = 11
5350 23:23:11.185203
5351 23:23:11.185272 ==
5352 23:23:11.188124 Dram Type= 6, Freq= 0, CH_0, rank 0
5353 23:23:11.191565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 23:23:11.191633 ==
5355 23:23:11.194945 RX Vref Scan: 1
5356 23:23:11.195044
5357 23:23:11.195140 RX Vref 0 -> 0, step: 1
5358 23:23:11.198226
5359 23:23:11.198297 RX Delay -61 -> 252, step: 4
5360 23:23:11.198358
5361 23:23:11.201106 Set Vref, RX VrefLevel [Byte0]: 61
5362 23:23:11.204436 [Byte1]: 54
5363 23:23:11.209048
5364 23:23:11.209116 Final RX Vref Byte 0 = 61 to rank0
5365 23:23:11.212453 Final RX Vref Byte 1 = 54 to rank0
5366 23:23:11.215708 Final RX Vref Byte 0 = 61 to rank1
5367 23:23:11.218909 Final RX Vref Byte 1 = 54 to rank1==
5368 23:23:11.222967 Dram Type= 6, Freq= 0, CH_0, rank 0
5369 23:23:11.229069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 23:23:11.229151 ==
5371 23:23:11.229217 DQS Delay:
5372 23:23:11.232493 DQS0 = 0, DQS1 = 0
5373 23:23:11.232568 DQM Delay:
5374 23:23:11.232636 DQM0 = 97, DQM1 = 85
5375 23:23:11.235306 DQ Delay:
5376 23:23:11.239380 DQ0 =94, DQ1 =96, DQ2 =94, DQ3 =94
5377 23:23:11.242639 DQ4 =98, DQ5 =88, DQ6 =108, DQ7 =104
5378 23:23:11.245521 DQ8 =80, DQ9 =74, DQ10 =86, DQ11 =80
5379 23:23:11.249107 DQ12 =90, DQ13 =88, DQ14 =96, DQ15 =92
5380 23:23:11.249181
5381 23:23:11.249244
5382 23:23:11.255214 [DQSOSCAuto] RK0, (LSB)MR18= 0x270e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 409 ps
5383 23:23:11.258732 CH0 RK0: MR19=505, MR18=270E
5384 23:23:11.265044 CH0_RK0: MR19=0x505, MR18=0x270E, DQSOSC=409, MR23=63, INC=64, DEC=43
5385 23:23:11.265143
5386 23:23:11.269006 ----->DramcWriteLeveling(PI) begin...
5387 23:23:11.269090 ==
5388 23:23:11.271992 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 23:23:11.275111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 23:23:11.275194 ==
5391 23:23:11.278686 Write leveling (Byte 0): 31 => 31
5392 23:23:11.281659 Write leveling (Byte 1): 34 => 34
5393 23:23:11.285071 DramcWriteLeveling(PI) end<-----
5394 23:23:11.285167
5395 23:23:11.285246 ==
5396 23:23:11.288174 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 23:23:11.291350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 23:23:11.294580 ==
5399 23:23:11.294662 [Gating] SW mode calibration
5400 23:23:11.304694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5401 23:23:11.308016 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5402 23:23:11.311119 0 14 0 | B1->B0 | 2929 3333 | 1 0 | (1 1) (0 0)
5403 23:23:11.318124 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5404 23:23:11.321940 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5405 23:23:11.324569 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5406 23:23:11.331357 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 23:23:11.334343 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 23:23:11.337919 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5409 23:23:11.344599 0 14 28 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (1 1)
5410 23:23:11.347994 0 15 0 | B1->B0 | 2c2c 2828 | 1 0 | (1 0) (1 0)
5411 23:23:11.350661 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5412 23:23:11.357458 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5413 23:23:11.360814 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5414 23:23:11.364220 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 23:23:11.371081 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 23:23:11.373839 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 23:23:11.377401 0 15 28 | B1->B0 | 2525 3333 | 0 1 | (0 0) (0 0)
5418 23:23:11.384039 1 0 0 | B1->B0 | 3939 3b3b | 0 1 | (0 0) (1 1)
5419 23:23:11.387469 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5420 23:23:11.390433 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5421 23:23:11.397367 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 23:23:11.400057 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 23:23:11.403622 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 23:23:11.410493 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 23:23:11.413395 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5426 23:23:11.416868 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5427 23:23:11.423235 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 23:23:11.426971 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 23:23:11.429948 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 23:23:11.436783 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 23:23:11.440019 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 23:23:11.443425 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 23:23:11.450115 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 23:23:11.453089 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 23:23:11.456316 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 23:23:11.463007 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 23:23:11.466433 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 23:23:11.469619 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 23:23:11.476196 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 23:23:11.479975 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 23:23:11.482618 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5442 23:23:11.486171 Total UI for P1: 0, mck2ui 16
5443 23:23:11.489111 best dqsien dly found for B0: ( 1, 2, 26)
5444 23:23:11.496264 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5445 23:23:11.499551 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 23:23:11.502559 Total UI for P1: 0, mck2ui 16
5447 23:23:11.505752 best dqsien dly found for B1: ( 1, 2, 30)
5448 23:23:11.509622 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5449 23:23:11.512757 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5450 23:23:11.512834
5451 23:23:11.516235 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5452 23:23:11.519004 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5453 23:23:11.522127 [Gating] SW calibration Done
5454 23:23:11.522228 ==
5455 23:23:11.525293 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 23:23:11.532729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 23:23:11.532836 ==
5458 23:23:11.532931 RX Vref Scan: 0
5459 23:23:11.533043
5460 23:23:11.535928 RX Vref 0 -> 0, step: 1
5461 23:23:11.536000
5462 23:23:11.538975 RX Delay -80 -> 252, step: 8
5463 23:23:11.542141 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5464 23:23:11.545446 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5465 23:23:11.549107 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5466 23:23:11.552235 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5467 23:23:11.558339 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5468 23:23:11.561728 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5469 23:23:11.565355 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5470 23:23:11.568218 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5471 23:23:11.571534 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5472 23:23:11.578418 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5473 23:23:11.581597 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5474 23:23:11.584740 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5475 23:23:11.588226 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5476 23:23:11.591833 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5477 23:23:11.598312 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5478 23:23:11.600998 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5479 23:23:11.601074 ==
5480 23:23:11.604124 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 23:23:11.607704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 23:23:11.607819 ==
5483 23:23:11.610676 DQS Delay:
5484 23:23:11.610750 DQS0 = 0, DQS1 = 0
5485 23:23:11.610814 DQM Delay:
5486 23:23:11.614134 DQM0 = 97, DQM1 = 89
5487 23:23:11.614208 DQ Delay:
5488 23:23:11.617932 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5489 23:23:11.620756 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5490 23:23:11.624586 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5491 23:23:11.627234 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5492 23:23:11.627308
5493 23:23:11.627373
5494 23:23:11.627434 ==
5495 23:23:11.630478 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 23:23:11.637294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 23:23:11.637379 ==
5498 23:23:11.637444
5499 23:23:11.637505
5500 23:23:11.637563 TX Vref Scan disable
5501 23:23:11.640698 == TX Byte 0 ==
5502 23:23:11.644334 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5503 23:23:11.650726 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5504 23:23:11.650804 == TX Byte 1 ==
5505 23:23:11.654219 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5506 23:23:11.660694 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5507 23:23:11.660800 ==
5508 23:23:11.664062 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 23:23:11.666873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 23:23:11.666955 ==
5511 23:23:11.667019
5512 23:23:11.667079
5513 23:23:11.670958 TX Vref Scan disable
5514 23:23:11.673952 == TX Byte 0 ==
5515 23:23:11.677239 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5516 23:23:11.680272 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5517 23:23:11.683581 == TX Byte 1 ==
5518 23:23:11.686708 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5519 23:23:11.690174 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5520 23:23:11.690259
5521 23:23:11.690324 [DATLAT]
5522 23:23:11.693212 Freq=933, CH0 RK1
5523 23:23:11.693295
5524 23:23:11.696907 DATLAT Default: 0xb
5525 23:23:11.696990 0, 0xFFFF, sum = 0
5526 23:23:11.699882 1, 0xFFFF, sum = 0
5527 23:23:11.699966 2, 0xFFFF, sum = 0
5528 23:23:11.702937 3, 0xFFFF, sum = 0
5529 23:23:11.703020 4, 0xFFFF, sum = 0
5530 23:23:11.706476 5, 0xFFFF, sum = 0
5531 23:23:11.706627 6, 0xFFFF, sum = 0
5532 23:23:11.709519 7, 0xFFFF, sum = 0
5533 23:23:11.709633 8, 0xFFFF, sum = 0
5534 23:23:11.712711 9, 0xFFFF, sum = 0
5535 23:23:11.712796 10, 0x0, sum = 1
5536 23:23:11.716373 11, 0x0, sum = 2
5537 23:23:11.716456 12, 0x0, sum = 3
5538 23:23:11.719188 13, 0x0, sum = 4
5539 23:23:11.719271 best_step = 11
5540 23:23:11.719336
5541 23:23:11.719406 ==
5542 23:23:11.722861 Dram Type= 6, Freq= 0, CH_0, rank 1
5543 23:23:11.729320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 23:23:11.729403 ==
5545 23:23:11.729510 RX Vref Scan: 0
5546 23:23:11.729571
5547 23:23:11.733171 RX Vref 0 -> 0, step: 1
5548 23:23:11.733270
5549 23:23:11.736162 RX Delay -61 -> 252, step: 4
5550 23:23:11.739230 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5551 23:23:11.742662 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5552 23:23:11.749071 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5553 23:23:11.752575 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5554 23:23:11.755545 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5555 23:23:11.759085 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5556 23:23:11.762523 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5557 23:23:11.765505 iDelay=203, Bit 7, Center 102 (7 ~ 198) 192
5558 23:23:11.772025 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5559 23:23:11.775605 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5560 23:23:11.778918 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5561 23:23:11.781859 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5562 23:23:11.788593 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5563 23:23:11.791845 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5564 23:23:11.795400 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5565 23:23:11.798944 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5566 23:23:11.799045 ==
5567 23:23:11.801863 Dram Type= 6, Freq= 0, CH_0, rank 1
5568 23:23:11.808244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 23:23:11.808346 ==
5570 23:23:11.808443 DQS Delay:
5571 23:23:11.808533 DQS0 = 0, DQS1 = 0
5572 23:23:11.811417 DQM Delay:
5573 23:23:11.811518 DQM0 = 94, DQM1 = 87
5574 23:23:11.814551 DQ Delay:
5575 23:23:11.818008 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =92
5576 23:23:11.821028 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =102
5577 23:23:11.824877 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =80
5578 23:23:11.828185 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5579 23:23:11.828285
5580 23:23:11.828387
5581 23:23:11.834707 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5582 23:23:11.838264 CH0 RK1: MR19=504, MR18=26F7
5583 23:23:11.844619 CH0_RK1: MR19=0x504, MR18=0x26F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5584 23:23:11.847808 [RxdqsGatingPostProcess] freq 933
5585 23:23:11.850988 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5586 23:23:11.854138 best DQS0 dly(2T, 0.5T) = (0, 10)
5587 23:23:11.857452 best DQS1 dly(2T, 0.5T) = (0, 10)
5588 23:23:11.861179 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5589 23:23:11.864425 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5590 23:23:11.867454 best DQS0 dly(2T, 0.5T) = (0, 10)
5591 23:23:11.870530 best DQS1 dly(2T, 0.5T) = (0, 10)
5592 23:23:11.873922 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5593 23:23:11.877426 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5594 23:23:11.880894 Pre-setting of DQS Precalculation
5595 23:23:11.883593 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5596 23:23:11.887320 ==
5597 23:23:11.890532 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 23:23:11.893794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 23:23:11.893893 ==
5600 23:23:11.900450 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5601 23:23:11.903550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5602 23:23:11.907408 [CA 0] Center 36 (6~67) winsize 62
5603 23:23:11.910951 [CA 1] Center 36 (6~67) winsize 62
5604 23:23:11.913908 [CA 2] Center 34 (4~65) winsize 62
5605 23:23:11.917721 [CA 3] Center 33 (3~64) winsize 62
5606 23:23:11.921058 [CA 4] Center 34 (4~64) winsize 61
5607 23:23:11.923969 [CA 5] Center 33 (3~64) winsize 62
5608 23:23:11.924070
5609 23:23:11.927145 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5610 23:23:11.927244
5611 23:23:11.930894 [CATrainingPosCal] consider 1 rank data
5612 23:23:11.933927 u2DelayCellTimex100 = 270/100 ps
5613 23:23:11.940185 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5614 23:23:11.943553 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5615 23:23:11.947284 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5616 23:23:11.950305 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5617 23:23:11.953528 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5618 23:23:11.956950 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5619 23:23:11.957033
5620 23:23:11.960457 CA PerBit enable=1, Macro0, CA PI delay=33
5621 23:23:11.960540
5622 23:23:11.963211 [CBTSetCACLKResult] CA Dly = 33
5623 23:23:11.966449 CS Dly: 6 (0~37)
5624 23:23:11.966532 ==
5625 23:23:11.969569 Dram Type= 6, Freq= 0, CH_1, rank 1
5626 23:23:11.973274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 23:23:11.973396 ==
5628 23:23:11.979955 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5629 23:23:11.985978 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5630 23:23:11.989362 [CA 0] Center 36 (6~67) winsize 62
5631 23:23:11.992581 [CA 1] Center 36 (6~67) winsize 62
5632 23:23:11.996388 [CA 2] Center 34 (4~65) winsize 62
5633 23:23:11.999277 [CA 3] Center 33 (3~64) winsize 62
5634 23:23:12.002496 [CA 4] Center 34 (3~65) winsize 63
5635 23:23:12.006062 [CA 5] Center 33 (3~64) winsize 62
5636 23:23:12.006161
5637 23:23:12.008944 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5638 23:23:12.009027
5639 23:23:12.012845 [CATrainingPosCal] consider 2 rank data
5640 23:23:12.015658 u2DelayCellTimex100 = 270/100 ps
5641 23:23:12.019613 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5642 23:23:12.022135 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5643 23:23:12.025944 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5644 23:23:12.029091 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5645 23:23:12.032226 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5646 23:23:12.035516 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5647 23:23:12.035622
5648 23:23:12.042304 CA PerBit enable=1, Macro0, CA PI delay=33
5649 23:23:12.042412
5650 23:23:12.042507 [CBTSetCACLKResult] CA Dly = 33
5651 23:23:12.045700 CS Dly: 7 (0~39)
5652 23:23:12.045798
5653 23:23:12.048848 ----->DramcWriteLeveling(PI) begin...
5654 23:23:12.048954 ==
5655 23:23:12.051863 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 23:23:12.055147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 23:23:12.055254 ==
5658 23:23:12.058498 Write leveling (Byte 0): 23 => 23
5659 23:23:12.061825 Write leveling (Byte 1): 29 => 29
5660 23:23:12.065579 DramcWriteLeveling(PI) end<-----
5661 23:23:12.065682
5662 23:23:12.065774 ==
5663 23:23:12.068691 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 23:23:12.075541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 23:23:12.075647 ==
5666 23:23:12.075778 [Gating] SW mode calibration
5667 23:23:12.085034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5668 23:23:12.088821 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5669 23:23:12.094642 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5670 23:23:12.097976 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5671 23:23:12.101794 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5672 23:23:12.108403 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5673 23:23:12.111415 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5674 23:23:12.114904 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5675 23:23:12.121760 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5676 23:23:12.124543 0 14 28 | B1->B0 | 2e2e 2c2c | 1 0 | (1 0) (0 0)
5677 23:23:12.128439 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5678 23:23:12.134254 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5679 23:23:12.137797 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5680 23:23:12.140992 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5681 23:23:12.148028 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5682 23:23:12.150738 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5683 23:23:12.154166 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5684 23:23:12.160738 0 15 28 | B1->B0 | 2d2d 3535 | 1 0 | (0 0) (0 0)
5685 23:23:12.164114 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5686 23:23:12.167511 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5687 23:23:12.174024 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5688 23:23:12.177473 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5689 23:23:12.180914 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 23:23:12.187271 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5691 23:23:12.190703 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5692 23:23:12.194010 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5693 23:23:12.200193 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5694 23:23:12.203694 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 23:23:12.206781 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 23:23:12.213278 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 23:23:12.217075 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 23:23:12.220106 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 23:23:12.226635 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 23:23:12.229959 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 23:23:12.233085 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 23:23:12.239577 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 23:23:12.243031 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 23:23:12.246848 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 23:23:12.253185 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 23:23:12.256089 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 23:23:12.259799 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5708 23:23:12.266423 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5709 23:23:12.266562 Total UI for P1: 0, mck2ui 16
5710 23:23:12.272662 best dqsien dly found for B0: ( 1, 2, 24)
5711 23:23:12.272765 Total UI for P1: 0, mck2ui 16
5712 23:23:12.279295 best dqsien dly found for B1: ( 1, 2, 26)
5713 23:23:12.282528 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5714 23:23:12.285731 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5715 23:23:12.285817
5716 23:23:12.288940 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5717 23:23:12.292126 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5718 23:23:12.295542 [Gating] SW calibration Done
5719 23:23:12.295628 ==
5720 23:23:12.299097 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 23:23:12.302080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 23:23:12.302166 ==
5723 23:23:12.305977 RX Vref Scan: 0
5724 23:23:12.306061
5725 23:23:12.306128 RX Vref 0 -> 0, step: 1
5726 23:23:12.306192
5727 23:23:12.309123 RX Delay -80 -> 252, step: 8
5728 23:23:12.312111 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5729 23:23:12.318930 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5730 23:23:12.322062 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5731 23:23:12.325138 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5732 23:23:12.328727 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5733 23:23:12.331979 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5734 23:23:12.335510 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5735 23:23:12.341780 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5736 23:23:12.345642 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5737 23:23:12.348742 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5738 23:23:12.352016 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5739 23:23:12.355181 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5740 23:23:12.361669 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5741 23:23:12.365335 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5742 23:23:12.368754 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5743 23:23:12.371800 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5744 23:23:12.371888 ==
5745 23:23:12.374910 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 23:23:12.381640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 23:23:12.381734 ==
5748 23:23:12.381802 DQS Delay:
5749 23:23:12.381865 DQS0 = 0, DQS1 = 0
5750 23:23:12.384707 DQM Delay:
5751 23:23:12.384795 DQM0 = 101, DQM1 = 91
5752 23:23:12.387963 DQ Delay:
5753 23:23:12.391554 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5754 23:23:12.394732 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5755 23:23:12.398129 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5756 23:23:12.401079 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5757 23:23:12.401162
5758 23:23:12.401227
5759 23:23:12.401289 ==
5760 23:23:12.404760 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 23:23:12.407864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 23:23:12.407963 ==
5763 23:23:12.408034
5764 23:23:12.408096
5765 23:23:12.411164 TX Vref Scan disable
5766 23:23:12.414291 == TX Byte 0 ==
5767 23:23:12.417642 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5768 23:23:12.421391 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5769 23:23:12.424275 == TX Byte 1 ==
5770 23:23:12.427183 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5771 23:23:12.430539 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5772 23:23:12.430622 ==
5773 23:23:12.434127 Dram Type= 6, Freq= 0, CH_1, rank 0
5774 23:23:12.440260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 23:23:12.440344 ==
5776 23:23:12.440410
5777 23:23:12.440471
5778 23:23:12.440530 TX Vref Scan disable
5779 23:23:12.444184 == TX Byte 0 ==
5780 23:23:12.447915 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5781 23:23:12.454317 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5782 23:23:12.454400 == TX Byte 1 ==
5783 23:23:12.458088 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5784 23:23:12.464127 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5785 23:23:12.464211
5786 23:23:12.464276 [DATLAT]
5787 23:23:12.464337 Freq=933, CH1 RK0
5788 23:23:12.464399
5789 23:23:12.467606 DATLAT Default: 0xd
5790 23:23:12.467718 0, 0xFFFF, sum = 0
5791 23:23:12.471139 1, 0xFFFF, sum = 0
5792 23:23:12.474590 2, 0xFFFF, sum = 0
5793 23:23:12.474701 3, 0xFFFF, sum = 0
5794 23:23:12.477828 4, 0xFFFF, sum = 0
5795 23:23:12.477913 5, 0xFFFF, sum = 0
5796 23:23:12.480657 6, 0xFFFF, sum = 0
5797 23:23:12.480742 7, 0xFFFF, sum = 0
5798 23:23:12.484145 8, 0xFFFF, sum = 0
5799 23:23:12.484229 9, 0xFFFF, sum = 0
5800 23:23:12.487198 10, 0x0, sum = 1
5801 23:23:12.487282 11, 0x0, sum = 2
5802 23:23:12.490651 12, 0x0, sum = 3
5803 23:23:12.490771 13, 0x0, sum = 4
5804 23:23:12.490887 best_step = 11
5805 23:23:12.494080
5806 23:23:12.494163 ==
5807 23:23:12.497151 Dram Type= 6, Freq= 0, CH_1, rank 0
5808 23:23:12.500498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 23:23:12.500589 ==
5810 23:23:12.500670 RX Vref Scan: 1
5811 23:23:12.500733
5812 23:23:12.503667 RX Vref 0 -> 0, step: 1
5813 23:23:12.503771
5814 23:23:12.507566 RX Delay -69 -> 252, step: 4
5815 23:23:12.507651
5816 23:23:12.510406 Set Vref, RX VrefLevel [Byte0]: 53
5817 23:23:12.513858 [Byte1]: 60
5818 23:23:12.517325
5819 23:23:12.517436 Final RX Vref Byte 0 = 53 to rank0
5820 23:23:12.520395 Final RX Vref Byte 1 = 60 to rank0
5821 23:23:12.523649 Final RX Vref Byte 0 = 53 to rank1
5822 23:23:12.526883 Final RX Vref Byte 1 = 60 to rank1==
5823 23:23:12.530372 Dram Type= 6, Freq= 0, CH_1, rank 0
5824 23:23:12.537062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 23:23:12.537161 ==
5826 23:23:12.537309 DQS Delay:
5827 23:23:12.540405 DQS0 = 0, DQS1 = 0
5828 23:23:12.540491 DQM Delay:
5829 23:23:12.540590 DQM0 = 100, DQM1 = 95
5830 23:23:12.543254 DQ Delay:
5831 23:23:12.546570 DQ0 =104, DQ1 =98, DQ2 =90, DQ3 =98
5832 23:23:12.549814 DQ4 =100, DQ5 =110, DQ6 =110, DQ7 =96
5833 23:23:12.553394 DQ8 =82, DQ9 =84, DQ10 =98, DQ11 =84
5834 23:23:12.556771 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =104
5835 23:23:12.556854
5836 23:23:12.556919
5837 23:23:12.562871 [DQSOSCAuto] RK0, (LSB)MR18= 0x1708, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 414 ps
5838 23:23:12.566308 CH1 RK0: MR19=505, MR18=1708
5839 23:23:12.573359 CH1_RK0: MR19=0x505, MR18=0x1708, DQSOSC=414, MR23=63, INC=63, DEC=42
5840 23:23:12.573443
5841 23:23:12.576280 ----->DramcWriteLeveling(PI) begin...
5842 23:23:12.576364 ==
5843 23:23:12.579924 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 23:23:12.582627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 23:23:12.586442 ==
5846 23:23:12.589297 Write leveling (Byte 0): 24 => 24
5847 23:23:12.589395 Write leveling (Byte 1): 31 => 31
5848 23:23:12.592585 DramcWriteLeveling(PI) end<-----
5849 23:23:12.592668
5850 23:23:12.596107 ==
5851 23:23:12.596184 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 23:23:12.602172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 23:23:12.602278 ==
5854 23:23:12.605701 [Gating] SW mode calibration
5855 23:23:12.612275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5856 23:23:12.615935 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5857 23:23:12.622439 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5858 23:23:12.625616 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5859 23:23:12.629126 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5860 23:23:12.635662 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5861 23:23:12.639056 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5862 23:23:12.642381 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5863 23:23:12.648786 0 14 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5864 23:23:12.652098 0 14 28 | B1->B0 | 2c2c 2c2c | 0 1 | (1 0) (1 0)
5865 23:23:12.655593 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5866 23:23:12.662488 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5867 23:23:12.665471 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5868 23:23:12.668698 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5869 23:23:12.675221 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5870 23:23:12.678564 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5871 23:23:12.681759 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5872 23:23:12.688494 0 15 28 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
5873 23:23:12.692282 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 23:23:12.694761 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5875 23:23:12.701409 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5876 23:23:12.705028 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5877 23:23:12.708384 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5878 23:23:12.714656 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 23:23:12.718632 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 23:23:12.721279 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5881 23:23:12.728526 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5882 23:23:12.731234 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 23:23:12.734814 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 23:23:12.741418 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 23:23:12.744741 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 23:23:12.747948 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 23:23:12.754488 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 23:23:12.757678 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 23:23:12.761051 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 23:23:12.767472 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 23:23:12.770766 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 23:23:12.774100 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 23:23:12.780943 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 23:23:12.784177 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 23:23:12.787708 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5896 23:23:12.794104 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5897 23:23:12.794223 Total UI for P1: 0, mck2ui 16
5898 23:23:12.800553 best dqsien dly found for B1: ( 1, 2, 24)
5899 23:23:12.803916 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5900 23:23:12.807178 Total UI for P1: 0, mck2ui 16
5901 23:23:12.810810 best dqsien dly found for B0: ( 1, 2, 28)
5902 23:23:12.813837 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5903 23:23:12.817621 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5904 23:23:12.817720
5905 23:23:12.820432 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5906 23:23:12.823873 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5907 23:23:12.827111 [Gating] SW calibration Done
5908 23:23:12.827193 ==
5909 23:23:12.830221 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 23:23:12.833614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 23:23:12.836956 ==
5912 23:23:12.837039 RX Vref Scan: 0
5913 23:23:12.837106
5914 23:23:12.840529 RX Vref 0 -> 0, step: 1
5915 23:23:12.840649
5916 23:23:12.843124 RX Delay -80 -> 252, step: 8
5917 23:23:12.846851 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5918 23:23:12.849837 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5919 23:23:12.853711 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5920 23:23:12.856723 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5921 23:23:12.859959 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5922 23:23:12.866617 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5923 23:23:12.870266 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5924 23:23:12.873084 iDelay=208, Bit 7, Center 99 (0 ~ 199) 200
5925 23:23:12.876695 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5926 23:23:12.879591 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5927 23:23:12.886315 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5928 23:23:12.889507 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5929 23:23:12.893027 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5930 23:23:12.896365 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5931 23:23:12.899791 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5932 23:23:12.902834 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5933 23:23:12.906036 ==
5934 23:23:12.906141 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 23:23:12.912928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 23:23:12.913057 ==
5937 23:23:12.913123 DQS Delay:
5938 23:23:12.916267 DQS0 = 0, DQS1 = 0
5939 23:23:12.916339 DQM Delay:
5940 23:23:12.919783 DQM0 = 100, DQM1 = 91
5941 23:23:12.919882 DQ Delay:
5942 23:23:12.922688 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5943 23:23:12.926819 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5944 23:23:12.929653 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5945 23:23:12.932331 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5946 23:23:12.932413
5947 23:23:12.932479
5948 23:23:12.932540 ==
5949 23:23:12.936118 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 23:23:12.939403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 23:23:12.939501 ==
5952 23:23:12.939594
5953 23:23:12.942863
5954 23:23:12.942945 TX Vref Scan disable
5955 23:23:12.946076 == TX Byte 0 ==
5956 23:23:12.949357 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5957 23:23:12.952290 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5958 23:23:12.955876 == TX Byte 1 ==
5959 23:23:12.959423 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5960 23:23:12.962602 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5961 23:23:12.962711 ==
5962 23:23:12.965360 Dram Type= 6, Freq= 0, CH_1, rank 1
5963 23:23:12.972573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5964 23:23:12.972659 ==
5965 23:23:12.972727
5966 23:23:12.972789
5967 23:23:12.972848 TX Vref Scan disable
5968 23:23:12.976400 == TX Byte 0 ==
5969 23:23:12.979727 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5970 23:23:12.986279 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5971 23:23:12.986363 == TX Byte 1 ==
5972 23:23:12.989749 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5973 23:23:12.996559 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5974 23:23:12.996642
5975 23:23:12.996709 [DATLAT]
5976 23:23:12.996770 Freq=933, CH1 RK1
5977 23:23:12.996831
5978 23:23:12.999500 DATLAT Default: 0xb
5979 23:23:13.003155 0, 0xFFFF, sum = 0
5980 23:23:13.003241 1, 0xFFFF, sum = 0
5981 23:23:13.006405 2, 0xFFFF, sum = 0
5982 23:23:13.006489 3, 0xFFFF, sum = 0
5983 23:23:13.009572 4, 0xFFFF, sum = 0
5984 23:23:13.009656 5, 0xFFFF, sum = 0
5985 23:23:13.012815 6, 0xFFFF, sum = 0
5986 23:23:13.012903 7, 0xFFFF, sum = 0
5987 23:23:13.016040 8, 0xFFFF, sum = 0
5988 23:23:13.016124 9, 0xFFFF, sum = 0
5989 23:23:13.019390 10, 0x0, sum = 1
5990 23:23:13.019482 11, 0x0, sum = 2
5991 23:23:13.022357 12, 0x0, sum = 3
5992 23:23:13.022480 13, 0x0, sum = 4
5993 23:23:13.025831 best_step = 11
5994 23:23:13.025928
5995 23:23:13.026017 ==
5996 23:23:13.028961 Dram Type= 6, Freq= 0, CH_1, rank 1
5997 23:23:13.032209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5998 23:23:13.032281 ==
5999 23:23:13.035650 RX Vref Scan: 0
6000 23:23:13.035764
6001 23:23:13.035834 RX Vref 0 -> 0, step: 1
6002 23:23:13.035895
6003 23:23:13.038851 RX Delay -61 -> 252, step: 4
6004 23:23:13.045429 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6005 23:23:13.048860 iDelay=207, Bit 1, Center 96 (7 ~ 186) 180
6006 23:23:13.051965 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
6007 23:23:13.055305 iDelay=207, Bit 3, Center 98 (11 ~ 186) 176
6008 23:23:13.058551 iDelay=207, Bit 4, Center 100 (7 ~ 194) 188
6009 23:23:13.065554 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
6010 23:23:13.068478 iDelay=207, Bit 6, Center 112 (19 ~ 206) 188
6011 23:23:13.071812 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6012 23:23:13.075396 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
6013 23:23:13.078241 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6014 23:23:13.081896 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
6015 23:23:13.088627 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6016 23:23:13.091796 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6017 23:23:13.095185 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
6018 23:23:13.098358 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
6019 23:23:13.104777 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6020 23:23:13.104860 ==
6021 23:23:13.109090 Dram Type= 6, Freq= 0, CH_1, rank 1
6022 23:23:13.111616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6023 23:23:13.111736 ==
6024 23:23:13.111804 DQS Delay:
6025 23:23:13.115053 DQS0 = 0, DQS1 = 0
6026 23:23:13.115151 DQM Delay:
6027 23:23:13.118031 DQM0 = 101, DQM1 = 93
6028 23:23:13.118114 DQ Delay:
6029 23:23:13.121330 DQ0 =106, DQ1 =96, DQ2 =88, DQ3 =98
6030 23:23:13.124563 DQ4 =100, DQ5 =112, DQ6 =112, DQ7 =98
6031 23:23:13.128120 DQ8 =84, DQ9 =84, DQ10 =92, DQ11 =84
6032 23:23:13.131218 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =102
6033 23:23:13.131301
6034 23:23:13.131367
6035 23:23:13.141190 [DQSOSCAuto] RK1, (LSB)MR18= 0x801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6036 23:23:13.144613 CH1 RK1: MR19=505, MR18=801
6037 23:23:13.147585 CH1_RK1: MR19=0x505, MR18=0x801, DQSOSC=419, MR23=63, INC=61, DEC=41
6038 23:23:13.151097 [RxdqsGatingPostProcess] freq 933
6039 23:23:13.157682 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6040 23:23:13.161015 best DQS0 dly(2T, 0.5T) = (0, 10)
6041 23:23:13.164039 best DQS1 dly(2T, 0.5T) = (0, 10)
6042 23:23:13.167178 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6043 23:23:13.170692 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6044 23:23:13.173848 best DQS0 dly(2T, 0.5T) = (0, 10)
6045 23:23:13.177313 best DQS1 dly(2T, 0.5T) = (0, 10)
6046 23:23:13.180596 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6047 23:23:13.183570 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6048 23:23:13.186959 Pre-setting of DQS Precalculation
6049 23:23:13.190178 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6050 23:23:13.196954 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6051 23:23:13.203319 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6052 23:23:13.207010
6053 23:23:13.207095
6054 23:23:13.207162 [Calibration Summary] 1866 Mbps
6055 23:23:13.210054 CH 0, Rank 0
6056 23:23:13.210151 SW Impedance : PASS
6057 23:23:13.213579 DUTY Scan : NO K
6058 23:23:13.216838 ZQ Calibration : PASS
6059 23:23:13.217028 Jitter Meter : NO K
6060 23:23:13.219862 CBT Training : PASS
6061 23:23:13.223372 Write leveling : PASS
6062 23:23:13.223482 RX DQS gating : PASS
6063 23:23:13.226986 RX DQ/DQS(RDDQC) : PASS
6064 23:23:13.230094 TX DQ/DQS : PASS
6065 23:23:13.230179 RX DATLAT : PASS
6066 23:23:13.233142 RX DQ/DQS(Engine): PASS
6067 23:23:13.236831 TX OE : NO K
6068 23:23:13.236946 All Pass.
6069 23:23:13.237028
6070 23:23:13.237092 CH 0, Rank 1
6071 23:23:13.240055 SW Impedance : PASS
6072 23:23:13.243494 DUTY Scan : NO K
6073 23:23:13.243607 ZQ Calibration : PASS
6074 23:23:13.246674 Jitter Meter : NO K
6075 23:23:13.249641 CBT Training : PASS
6076 23:23:13.249725 Write leveling : PASS
6077 23:23:13.253104 RX DQS gating : PASS
6078 23:23:13.256319 RX DQ/DQS(RDDQC) : PASS
6079 23:23:13.256401 TX DQ/DQS : PASS
6080 23:23:13.259451 RX DATLAT : PASS
6081 23:23:13.259561 RX DQ/DQS(Engine): PASS
6082 23:23:13.263203 TX OE : NO K
6083 23:23:13.263288 All Pass.
6084 23:23:13.263355
6085 23:23:13.266425 CH 1, Rank 0
6086 23:23:13.269604 SW Impedance : PASS
6087 23:23:13.269688 DUTY Scan : NO K
6088 23:23:13.272905 ZQ Calibration : PASS
6089 23:23:13.272987 Jitter Meter : NO K
6090 23:23:13.276213 CBT Training : PASS
6091 23:23:13.279515 Write leveling : PASS
6092 23:23:13.279627 RX DQS gating : PASS
6093 23:23:13.282813 RX DQ/DQS(RDDQC) : PASS
6094 23:23:13.285790 TX DQ/DQS : PASS
6095 23:23:13.285900 RX DATLAT : PASS
6096 23:23:13.289042 RX DQ/DQS(Engine): PASS
6097 23:23:13.292721 TX OE : NO K
6098 23:23:13.292817 All Pass.
6099 23:23:13.292885
6100 23:23:13.292946 CH 1, Rank 1
6101 23:23:13.295781 SW Impedance : PASS
6102 23:23:13.299804 DUTY Scan : NO K
6103 23:23:13.299905 ZQ Calibration : PASS
6104 23:23:13.302787 Jitter Meter : NO K
6105 23:23:13.305373 CBT Training : PASS
6106 23:23:13.305460 Write leveling : PASS
6107 23:23:13.309051 RX DQS gating : PASS
6108 23:23:13.312744 RX DQ/DQS(RDDQC) : PASS
6109 23:23:13.312827 TX DQ/DQS : PASS
6110 23:23:13.315382 RX DATLAT : PASS
6111 23:23:13.319148 RX DQ/DQS(Engine): PASS
6112 23:23:13.319231 TX OE : NO K
6113 23:23:13.321996 All Pass.
6114 23:23:13.322078
6115 23:23:13.322144 DramC Write-DBI off
6116 23:23:13.325465 PER_BANK_REFRESH: Hybrid Mode
6117 23:23:13.325549 TX_TRACKING: ON
6118 23:23:13.334996 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6119 23:23:13.338348 [FAST_K] Save calibration result to emmc
6120 23:23:13.341630 dramc_set_vcore_voltage set vcore to 650000
6121 23:23:13.344810 Read voltage for 400, 6
6122 23:23:13.344968 Vio18 = 0
6123 23:23:13.348373 Vcore = 650000
6124 23:23:13.348482 Vdram = 0
6125 23:23:13.348575 Vddq = 0
6126 23:23:13.351293 Vmddr = 0
6127 23:23:13.355032 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6128 23:23:13.361198 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6129 23:23:13.361303 MEM_TYPE=3, freq_sel=20
6130 23:23:13.364870 sv_algorithm_assistance_LP4_800
6131 23:23:13.371591 ============ PULL DRAM RESETB DOWN ============
6132 23:23:13.374654 ========== PULL DRAM RESETB DOWN end =========
6133 23:23:13.377792 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6134 23:23:13.381769 ===================================
6135 23:23:13.384426 LPDDR4 DRAM CONFIGURATION
6136 23:23:13.387883 ===================================
6137 23:23:13.391249 EX_ROW_EN[0] = 0x0
6138 23:23:13.391348 EX_ROW_EN[1] = 0x0
6139 23:23:13.394246 LP4Y_EN = 0x0
6140 23:23:13.394345 WORK_FSP = 0x0
6141 23:23:13.397337 WL = 0x2
6142 23:23:13.397445 RL = 0x2
6143 23:23:13.400809 BL = 0x2
6144 23:23:13.400924 RPST = 0x0
6145 23:23:13.404120 RD_PRE = 0x0
6146 23:23:13.404227 WR_PRE = 0x1
6147 23:23:13.407460 WR_PST = 0x0
6148 23:23:13.407573 DBI_WR = 0x0
6149 23:23:13.411089 DBI_RD = 0x0
6150 23:23:13.411202 OTF = 0x1
6151 23:23:13.414178 ===================================
6152 23:23:13.417724 ===================================
6153 23:23:13.420889 ANA top config
6154 23:23:13.424444 ===================================
6155 23:23:13.427094 DLL_ASYNC_EN = 0
6156 23:23:13.427208 ALL_SLAVE_EN = 1
6157 23:23:13.430450 NEW_RANK_MODE = 1
6158 23:23:13.433960 DLL_IDLE_MODE = 1
6159 23:23:13.437269 LP45_APHY_COMB_EN = 1
6160 23:23:13.440481 TX_ODT_DIS = 1
6161 23:23:13.440589 NEW_8X_MODE = 1
6162 23:23:13.443823 ===================================
6163 23:23:13.446666 ===================================
6164 23:23:13.450473 data_rate = 800
6165 23:23:13.453293 CKR = 1
6166 23:23:13.457079 DQ_P2S_RATIO = 4
6167 23:23:13.459920 ===================================
6168 23:23:13.463424 CA_P2S_RATIO = 4
6169 23:23:13.466709 DQ_CA_OPEN = 0
6170 23:23:13.469842 DQ_SEMI_OPEN = 1
6171 23:23:13.469952 CA_SEMI_OPEN = 1
6172 23:23:13.473597 CA_FULL_RATE = 0
6173 23:23:13.476473 DQ_CKDIV4_EN = 0
6174 23:23:13.479599 CA_CKDIV4_EN = 1
6175 23:23:13.483213 CA_PREDIV_EN = 0
6176 23:23:13.486748 PH8_DLY = 0
6177 23:23:13.486857 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6178 23:23:13.489958 DQ_AAMCK_DIV = 0
6179 23:23:13.493105 CA_AAMCK_DIV = 0
6180 23:23:13.496323 CA_ADMCK_DIV = 4
6181 23:23:13.499697 DQ_TRACK_CA_EN = 0
6182 23:23:13.502521 CA_PICK = 800
6183 23:23:13.505936 CA_MCKIO = 400
6184 23:23:13.506048 MCKIO_SEMI = 400
6185 23:23:13.509586 PLL_FREQ = 3016
6186 23:23:13.512348 DQ_UI_PI_RATIO = 32
6187 23:23:13.515845 CA_UI_PI_RATIO = 32
6188 23:23:13.519071 ===================================
6189 23:23:13.522240 ===================================
6190 23:23:13.525827 memory_type:LPDDR4
6191 23:23:13.525940 GP_NUM : 10
6192 23:23:13.529301 SRAM_EN : 1
6193 23:23:13.532817 MD32_EN : 0
6194 23:23:13.535785 ===================================
6195 23:23:13.535889 [ANA_INIT] >>>>>>>>>>>>>>
6196 23:23:13.539164 <<<<<< [CONFIGURE PHASE]: ANA_TX
6197 23:23:13.542516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6198 23:23:13.545608 ===================================
6199 23:23:13.548943 data_rate = 800,PCW = 0X7400
6200 23:23:13.552208 ===================================
6201 23:23:13.555203 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6202 23:23:13.561916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6203 23:23:13.571629 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6204 23:23:13.578501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6205 23:23:13.582057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6206 23:23:13.585176 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6207 23:23:13.585284 [ANA_INIT] flow start
6208 23:23:13.588437 [ANA_INIT] PLL >>>>>>>>
6209 23:23:13.591873 [ANA_INIT] PLL <<<<<<<<
6210 23:23:13.591983 [ANA_INIT] MIDPI >>>>>>>>
6211 23:23:13.594780 [ANA_INIT] MIDPI <<<<<<<<
6212 23:23:13.598400 [ANA_INIT] DLL >>>>>>>>
6213 23:23:13.598526 [ANA_INIT] flow end
6214 23:23:13.604733 ============ LP4 DIFF to SE enter ============
6215 23:23:13.608347 ============ LP4 DIFF to SE exit ============
6216 23:23:13.611611 [ANA_INIT] <<<<<<<<<<<<<
6217 23:23:13.614793 [Flow] Enable top DCM control >>>>>
6218 23:23:13.617758 [Flow] Enable top DCM control <<<<<
6219 23:23:13.621107 Enable DLL master slave shuffle
6220 23:23:13.624322 ==============================================================
6221 23:23:13.627865 Gating Mode config
6222 23:23:13.634250 ==============================================================
6223 23:23:13.634366 Config description:
6224 23:23:13.644484 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6225 23:23:13.651451 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6226 23:23:13.653982 SELPH_MODE 0: By rank 1: By Phase
6227 23:23:13.660686 ==============================================================
6228 23:23:13.664056 GAT_TRACK_EN = 0
6229 23:23:13.667363 RX_GATING_MODE = 2
6230 23:23:13.671075 RX_GATING_TRACK_MODE = 2
6231 23:23:13.674284 SELPH_MODE = 1
6232 23:23:13.677691 PICG_EARLY_EN = 1
6233 23:23:13.680618 VALID_LAT_VALUE = 1
6234 23:23:13.683884 ==============================================================
6235 23:23:13.687304 Enter into Gating configuration >>>>
6236 23:23:13.690762 Exit from Gating configuration <<<<
6237 23:23:13.693914 Enter into DVFS_PRE_config >>>>>
6238 23:23:13.706821 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6239 23:23:13.710141 Exit from DVFS_PRE_config <<<<<
6240 23:23:13.710244 Enter into PICG configuration >>>>
6241 23:23:13.714070 Exit from PICG configuration <<<<
6242 23:23:13.716887 [RX_INPUT] configuration >>>>>
6243 23:23:13.720126 [RX_INPUT] configuration <<<<<
6244 23:23:13.727261 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6245 23:23:13.730081 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6246 23:23:13.737025 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6247 23:23:13.743585 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6248 23:23:13.750031 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6249 23:23:13.757155 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6250 23:23:13.760038 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6251 23:23:13.763301 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6252 23:23:13.766640 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6253 23:23:13.773248 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6254 23:23:13.776439 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6255 23:23:13.779979 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6256 23:23:13.783486 ===================================
6257 23:23:13.786492 LPDDR4 DRAM CONFIGURATION
6258 23:23:13.789634 ===================================
6259 23:23:13.793295 EX_ROW_EN[0] = 0x0
6260 23:23:13.793378 EX_ROW_EN[1] = 0x0
6261 23:23:13.796381 LP4Y_EN = 0x0
6262 23:23:13.796463 WORK_FSP = 0x0
6263 23:23:13.799869 WL = 0x2
6264 23:23:13.799988 RL = 0x2
6265 23:23:13.802981 BL = 0x2
6266 23:23:13.803063 RPST = 0x0
6267 23:23:13.805949 RD_PRE = 0x0
6268 23:23:13.806058 WR_PRE = 0x1
6269 23:23:13.809899 WR_PST = 0x0
6270 23:23:13.810001 DBI_WR = 0x0
6271 23:23:13.812794 DBI_RD = 0x0
6272 23:23:13.816379 OTF = 0x1
6273 23:23:13.819279 ===================================
6274 23:23:13.822831 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6275 23:23:13.825803 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6276 23:23:13.829134 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6277 23:23:13.832592 ===================================
6278 23:23:13.835821 LPDDR4 DRAM CONFIGURATION
6279 23:23:13.838765 ===================================
6280 23:23:13.842158 EX_ROW_EN[0] = 0x10
6281 23:23:13.842266 EX_ROW_EN[1] = 0x0
6282 23:23:13.845454 LP4Y_EN = 0x0
6283 23:23:13.845536 WORK_FSP = 0x0
6284 23:23:13.848987 WL = 0x2
6285 23:23:13.849069 RL = 0x2
6286 23:23:13.852062 BL = 0x2
6287 23:23:13.852144 RPST = 0x0
6288 23:23:13.855771 RD_PRE = 0x0
6289 23:23:13.855852 WR_PRE = 0x1
6290 23:23:13.858991 WR_PST = 0x0
6291 23:23:13.862473 DBI_WR = 0x0
6292 23:23:13.862554 DBI_RD = 0x0
6293 23:23:13.865124 OTF = 0x1
6294 23:23:13.868650 ===================================
6295 23:23:13.871935 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6296 23:23:13.877328 nWR fixed to 30
6297 23:23:13.880453 [ModeRegInit_LP4] CH0 RK0
6298 23:23:13.880536 [ModeRegInit_LP4] CH0 RK1
6299 23:23:13.883664 [ModeRegInit_LP4] CH1 RK0
6300 23:23:13.887067 [ModeRegInit_LP4] CH1 RK1
6301 23:23:13.887149 match AC timing 19
6302 23:23:13.893587 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6303 23:23:13.896818 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6304 23:23:13.900275 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6305 23:23:13.906980 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6306 23:23:13.910243 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6307 23:23:13.910355 ==
6308 23:23:13.913336 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 23:23:13.916561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 23:23:13.916644 ==
6311 23:23:13.923483 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6312 23:23:13.929868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6313 23:23:13.933095 [CA 0] Center 36 (8~64) winsize 57
6314 23:23:13.936273 [CA 1] Center 36 (8~64) winsize 57
6315 23:23:13.939738 [CA 2] Center 36 (8~64) winsize 57
6316 23:23:13.943236 [CA 3] Center 36 (8~64) winsize 57
6317 23:23:13.946164 [CA 4] Center 36 (8~64) winsize 57
6318 23:23:13.949454 [CA 5] Center 36 (8~64) winsize 57
6319 23:23:13.949536
6320 23:23:13.953059 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6321 23:23:13.953141
6322 23:23:13.956474 [CATrainingPosCal] consider 1 rank data
6323 23:23:13.959520 u2DelayCellTimex100 = 270/100 ps
6324 23:23:13.962744 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 23:23:13.966046 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 23:23:13.969520 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 23:23:13.972733 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 23:23:13.976109 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 23:23:13.979169 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 23:23:13.979277
6331 23:23:13.985859 CA PerBit enable=1, Macro0, CA PI delay=36
6332 23:23:13.986085
6333 23:23:13.986270 [CBTSetCACLKResult] CA Dly = 36
6334 23:23:13.988997 CS Dly: 1 (0~32)
6335 23:23:13.989096 ==
6336 23:23:13.992772 Dram Type= 6, Freq= 0, CH_0, rank 1
6337 23:23:13.996111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 23:23:13.996193 ==
6339 23:23:14.002467 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6340 23:23:14.009820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6341 23:23:14.012443 [CA 0] Center 36 (8~64) winsize 57
6342 23:23:14.015700 [CA 1] Center 36 (8~64) winsize 57
6343 23:23:14.019414 [CA 2] Center 36 (8~64) winsize 57
6344 23:23:14.022346 [CA 3] Center 36 (8~64) winsize 57
6345 23:23:14.022447 [CA 4] Center 36 (8~64) winsize 57
6346 23:23:14.026032 [CA 5] Center 36 (8~64) winsize 57
6347 23:23:14.026140
6348 23:23:14.031915 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6349 23:23:14.031993
6350 23:23:14.035693 [CATrainingPosCal] consider 2 rank data
6351 23:23:14.038842 u2DelayCellTimex100 = 270/100 ps
6352 23:23:14.041890 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6353 23:23:14.045076 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6354 23:23:14.048573 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6355 23:23:14.051798 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6356 23:23:14.055227 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6357 23:23:14.058583 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6358 23:23:14.058660
6359 23:23:14.061293 CA PerBit enable=1, Macro0, CA PI delay=36
6360 23:23:14.064752
6361 23:23:14.064830 [CBTSetCACLKResult] CA Dly = 36
6362 23:23:14.068064 CS Dly: 1 (0~32)
6363 23:23:14.068138
6364 23:23:14.071377 ----->DramcWriteLeveling(PI) begin...
6365 23:23:14.071477 ==
6366 23:23:14.074796 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 23:23:14.077887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 23:23:14.077964 ==
6369 23:23:14.081570 Write leveling (Byte 0): 40 => 8
6370 23:23:14.084352 Write leveling (Byte 1): 32 => 0
6371 23:23:14.088025 DramcWriteLeveling(PI) end<-----
6372 23:23:14.088109
6373 23:23:14.088175 ==
6374 23:23:14.091410 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 23:23:14.094610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 23:23:14.097907 ==
6377 23:23:14.097995 [Gating] SW mode calibration
6378 23:23:14.107548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6379 23:23:14.110733 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6380 23:23:14.114999 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6381 23:23:14.120874 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6382 23:23:14.123878 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6383 23:23:14.127492 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6384 23:23:14.133946 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6385 23:23:14.137380 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6386 23:23:14.140685 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6387 23:23:14.147359 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6388 23:23:14.150799 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6389 23:23:14.154251 Total UI for P1: 0, mck2ui 16
6390 23:23:14.157047 best dqsien dly found for B0: ( 0, 14, 24)
6391 23:23:14.160273 Total UI for P1: 0, mck2ui 16
6392 23:23:14.163543 best dqsien dly found for B1: ( 0, 14, 24)
6393 23:23:14.166987 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6394 23:23:14.170017 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6395 23:23:14.170123
6396 23:23:14.173562 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6397 23:23:14.179991 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6398 23:23:14.180079 [Gating] SW calibration Done
6399 23:23:14.180146 ==
6400 23:23:14.183548 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 23:23:14.190070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 23:23:14.190174 ==
6403 23:23:14.190265 RX Vref Scan: 0
6404 23:23:14.190353
6405 23:23:14.193391 RX Vref 0 -> 0, step: 1
6406 23:23:14.193487
6407 23:23:14.196844 RX Delay -410 -> 252, step: 16
6408 23:23:14.200212 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6409 23:23:14.203623 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6410 23:23:14.210159 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6411 23:23:14.213670 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6412 23:23:14.216671 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6413 23:23:14.219958 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6414 23:23:14.226735 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6415 23:23:14.229816 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6416 23:23:14.233166 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6417 23:23:14.236187 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6418 23:23:14.243101 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6419 23:23:14.246349 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6420 23:23:14.249677 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6421 23:23:14.252867 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6422 23:23:14.259585 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6423 23:23:14.262833 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6424 23:23:14.262933 ==
6425 23:23:14.266009 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 23:23:14.269757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 23:23:14.269858 ==
6428 23:23:14.272420 DQS Delay:
6429 23:23:14.272493 DQS0 = 43, DQS1 = 59
6430 23:23:14.276027 DQM Delay:
6431 23:23:14.276130 DQM0 = 10, DQM1 = 12
6432 23:23:14.279121 DQ Delay:
6433 23:23:14.279227 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6434 23:23:14.282899 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6435 23:23:14.285834 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6436 23:23:14.289109 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6437 23:23:14.289192
6438 23:23:14.289272
6439 23:23:14.289347 ==
6440 23:23:14.292114 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 23:23:14.299115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 23:23:14.299198 ==
6443 23:23:14.299264
6444 23:23:14.299325
6445 23:23:14.299382 TX Vref Scan disable
6446 23:23:14.302408 == TX Byte 0 ==
6447 23:23:14.305612 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6448 23:23:14.309088 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6449 23:23:14.312347 == TX Byte 1 ==
6450 23:23:14.315711 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6451 23:23:14.322545 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6452 23:23:14.322632 ==
6453 23:23:14.325289 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 23:23:14.328383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 23:23:14.328465 ==
6456 23:23:14.328530
6457 23:23:14.328590
6458 23:23:14.331909 TX Vref Scan disable
6459 23:23:14.332007 == TX Byte 0 ==
6460 23:23:14.335713 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6461 23:23:14.342173 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6462 23:23:14.342255 == TX Byte 1 ==
6463 23:23:14.345095 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6464 23:23:14.351815 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6465 23:23:14.351898
6466 23:23:14.351963 [DATLAT]
6467 23:23:14.355029 Freq=400, CH0 RK0
6468 23:23:14.355144
6469 23:23:14.355222 DATLAT Default: 0xf
6470 23:23:14.358245 0, 0xFFFF, sum = 0
6471 23:23:14.358341 1, 0xFFFF, sum = 0
6472 23:23:14.361718 2, 0xFFFF, sum = 0
6473 23:23:14.361832 3, 0xFFFF, sum = 0
6474 23:23:14.364596 4, 0xFFFF, sum = 0
6475 23:23:14.364680 5, 0xFFFF, sum = 0
6476 23:23:14.368020 6, 0xFFFF, sum = 0
6477 23:23:14.368094 7, 0xFFFF, sum = 0
6478 23:23:14.371200 8, 0xFFFF, sum = 0
6479 23:23:14.371311 9, 0xFFFF, sum = 0
6480 23:23:14.374863 10, 0xFFFF, sum = 0
6481 23:23:14.374967 11, 0xFFFF, sum = 0
6482 23:23:14.378010 12, 0xFFFF, sum = 0
6483 23:23:14.378145 13, 0x0, sum = 1
6484 23:23:14.381480 14, 0x0, sum = 2
6485 23:23:14.381561 15, 0x0, sum = 3
6486 23:23:14.384767 16, 0x0, sum = 4
6487 23:23:14.384850 best_step = 14
6488 23:23:14.384916
6489 23:23:14.384976 ==
6490 23:23:14.388447 Dram Type= 6, Freq= 0, CH_0, rank 0
6491 23:23:14.394378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 23:23:14.394488 ==
6493 23:23:14.394587 RX Vref Scan: 1
6494 23:23:14.394677
6495 23:23:14.398101 RX Vref 0 -> 0, step: 1
6496 23:23:14.398205
6497 23:23:14.400959 RX Delay -359 -> 252, step: 8
6498 23:23:14.401060
6499 23:23:14.404408 Set Vref, RX VrefLevel [Byte0]: 61
6500 23:23:14.407686 [Byte1]: 54
6501 23:23:14.411282
6502 23:23:14.411379 Final RX Vref Byte 0 = 61 to rank0
6503 23:23:14.414615 Final RX Vref Byte 1 = 54 to rank0
6504 23:23:14.417896 Final RX Vref Byte 0 = 61 to rank1
6505 23:23:14.421029 Final RX Vref Byte 1 = 54 to rank1==
6506 23:23:14.424710 Dram Type= 6, Freq= 0, CH_0, rank 0
6507 23:23:14.430936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 23:23:14.431019 ==
6509 23:23:14.431084 DQS Delay:
6510 23:23:14.434133 DQS0 = 48, DQS1 = 60
6511 23:23:14.434258 DQM Delay:
6512 23:23:14.434365 DQM0 = 11, DQM1 = 12
6513 23:23:14.437294 DQ Delay:
6514 23:23:14.441241 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6515 23:23:14.444788 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6516 23:23:14.444892 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6517 23:23:14.450776 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6518 23:23:14.450861
6519 23:23:14.450933
6520 23:23:14.457467 [DQSOSCAuto] RK0, (LSB)MR18= 0xbc80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6521 23:23:14.460729 CH0 RK0: MR19=C0C, MR18=BC80
6522 23:23:14.467199 CH0_RK0: MR19=0xC0C, MR18=0xBC80, DQSOSC=386, MR23=63, INC=396, DEC=264
6523 23:23:14.467286 ==
6524 23:23:14.470481 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 23:23:14.473824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 23:23:14.473921 ==
6527 23:23:14.477018 [Gating] SW mode calibration
6528 23:23:14.483936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6529 23:23:14.490105 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6530 23:23:14.493269 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6531 23:23:14.497275 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6532 23:23:14.503951 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6533 23:23:14.506929 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6534 23:23:14.509739 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6535 23:23:14.517007 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6536 23:23:14.519889 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6537 23:23:14.523010 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6538 23:23:14.529893 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6539 23:23:14.533060 Total UI for P1: 0, mck2ui 16
6540 23:23:14.536726 best dqsien dly found for B0: ( 0, 14, 24)
6541 23:23:14.539318 Total UI for P1: 0, mck2ui 16
6542 23:23:14.543084 best dqsien dly found for B1: ( 0, 14, 24)
6543 23:23:14.546114 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6544 23:23:14.550020 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6545 23:23:14.550131
6546 23:23:14.553022 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6547 23:23:14.555812 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6548 23:23:14.559833 [Gating] SW calibration Done
6549 23:23:14.559908 ==
6550 23:23:14.562752 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 23:23:14.565858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 23:23:14.565960 ==
6553 23:23:14.569346 RX Vref Scan: 0
6554 23:23:14.569445
6555 23:23:14.572667 RX Vref 0 -> 0, step: 1
6556 23:23:14.572768
6557 23:23:14.575786 RX Delay -410 -> 252, step: 16
6558 23:23:14.578895 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6559 23:23:14.582207 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6560 23:23:14.585772 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6561 23:23:14.591941 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6562 23:23:14.595297 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6563 23:23:14.599061 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6564 23:23:14.602123 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6565 23:23:14.608863 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6566 23:23:14.611739 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6567 23:23:14.615437 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6568 23:23:14.618784 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6569 23:23:14.625339 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6570 23:23:14.628789 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6571 23:23:14.631678 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6572 23:23:14.638328 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6573 23:23:14.641736 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6574 23:23:14.641834 ==
6575 23:23:14.644686 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 23:23:14.648180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 23:23:14.648493 ==
6578 23:23:14.651309 DQS Delay:
6579 23:23:14.651398 DQS0 = 43, DQS1 = 59
6580 23:23:14.654574 DQM Delay:
6581 23:23:14.654657 DQM0 = 10, DQM1 = 16
6582 23:23:14.654754 DQ Delay:
6583 23:23:14.657679 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6584 23:23:14.660934 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6585 23:23:14.664686 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6586 23:23:14.667877 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6587 23:23:14.667965
6588 23:23:14.668050
6589 23:23:14.668133 ==
6590 23:23:14.670777 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 23:23:14.677521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 23:23:14.677622 ==
6593 23:23:14.677710
6594 23:23:14.677793
6595 23:23:14.677873 TX Vref Scan disable
6596 23:23:14.680910 == TX Byte 0 ==
6597 23:23:14.683921 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6598 23:23:14.687735 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6599 23:23:14.691063 == TX Byte 1 ==
6600 23:23:14.694232 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6601 23:23:14.697180 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6602 23:23:14.700556 ==
6603 23:23:14.700638 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 23:23:14.707361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 23:23:14.707443 ==
6606 23:23:14.707560
6607 23:23:14.707679
6608 23:23:14.710239 TX Vref Scan disable
6609 23:23:14.710333 == TX Byte 0 ==
6610 23:23:14.713801 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6611 23:23:14.719859 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6612 23:23:14.719950 == TX Byte 1 ==
6613 23:23:14.723398 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6614 23:23:14.729876 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6615 23:23:14.729963
6616 23:23:14.730066 [DATLAT]
6617 23:23:14.730155 Freq=400, CH0 RK1
6618 23:23:14.730248
6619 23:23:14.733195 DATLAT Default: 0xe
6620 23:23:14.733287 0, 0xFFFF, sum = 0
6621 23:23:14.736537 1, 0xFFFF, sum = 0
6622 23:23:14.739701 2, 0xFFFF, sum = 0
6623 23:23:14.739803 3, 0xFFFF, sum = 0
6624 23:23:14.743014 4, 0xFFFF, sum = 0
6625 23:23:14.743104 5, 0xFFFF, sum = 0
6626 23:23:14.746166 6, 0xFFFF, sum = 0
6627 23:23:14.746255 7, 0xFFFF, sum = 0
6628 23:23:14.749802 8, 0xFFFF, sum = 0
6629 23:23:14.749883 9, 0xFFFF, sum = 0
6630 23:23:14.752690 10, 0xFFFF, sum = 0
6631 23:23:14.752780 11, 0xFFFF, sum = 0
6632 23:23:14.756048 12, 0xFFFF, sum = 0
6633 23:23:14.756133 13, 0x0, sum = 1
6634 23:23:14.759316 14, 0x0, sum = 2
6635 23:23:14.759412 15, 0x0, sum = 3
6636 23:23:14.763167 16, 0x0, sum = 4
6637 23:23:14.763280 best_step = 14
6638 23:23:14.763381
6639 23:23:14.763473 ==
6640 23:23:14.766094 Dram Type= 6, Freq= 0, CH_0, rank 1
6641 23:23:14.772585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 23:23:14.772696 ==
6643 23:23:14.772791 RX Vref Scan: 0
6644 23:23:14.772885
6645 23:23:14.776094 RX Vref 0 -> 0, step: 1
6646 23:23:14.776196
6647 23:23:14.779675 RX Delay -359 -> 252, step: 8
6648 23:23:14.786296 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6649 23:23:14.788926 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6650 23:23:14.792426 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6651 23:23:14.796216 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6652 23:23:14.802142 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6653 23:23:14.805689 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6654 23:23:14.808844 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6655 23:23:14.811983 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6656 23:23:14.818641 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6657 23:23:14.821877 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6658 23:23:14.825203 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
6659 23:23:14.831662 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6660 23:23:14.835434 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6661 23:23:14.838892 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6662 23:23:14.841721 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6663 23:23:14.848339 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6664 23:23:14.848418 ==
6665 23:23:14.851758 Dram Type= 6, Freq= 0, CH_0, rank 1
6666 23:23:14.854962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 23:23:14.855034 ==
6668 23:23:14.855140 DQS Delay:
6669 23:23:14.858157 DQS0 = 44, DQS1 = 60
6670 23:23:14.858235 DQM Delay:
6671 23:23:14.861837 DQM0 = 8, DQM1 = 14
6672 23:23:14.861910 DQ Delay:
6673 23:23:14.865060 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6674 23:23:14.868484 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6675 23:23:14.871596 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6676 23:23:14.874641 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6677 23:23:14.874719
6678 23:23:14.874790
6679 23:23:14.881660 [DQSOSCAuto] RK1, (LSB)MR18= 0xae39, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6680 23:23:14.884370 CH0 RK1: MR19=C0C, MR18=AE39
6681 23:23:14.891187 CH0_RK1: MR19=0xC0C, MR18=0xAE39, DQSOSC=388, MR23=63, INC=392, DEC=261
6682 23:23:14.894812 [RxdqsGatingPostProcess] freq 400
6683 23:23:14.901321 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6684 23:23:14.904381 best DQS0 dly(2T, 0.5T) = (0, 10)
6685 23:23:14.907655 best DQS1 dly(2T, 0.5T) = (0, 10)
6686 23:23:14.910647 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6687 23:23:14.914300 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6688 23:23:14.917122 best DQS0 dly(2T, 0.5T) = (0, 10)
6689 23:23:14.917222 best DQS1 dly(2T, 0.5T) = (0, 10)
6690 23:23:14.920933 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6691 23:23:14.923721 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6692 23:23:14.927166 Pre-setting of DQS Precalculation
6693 23:23:14.934145 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6694 23:23:14.934234 ==
6695 23:23:14.937388 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 23:23:14.940108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 23:23:14.940198 ==
6698 23:23:14.947228 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6699 23:23:14.953449 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6700 23:23:14.956788 [CA 0] Center 36 (8~64) winsize 57
6701 23:23:14.960373 [CA 1] Center 36 (8~64) winsize 57
6702 23:23:14.963552 [CA 2] Center 36 (8~64) winsize 57
6703 23:23:14.966819 [CA 3] Center 36 (8~64) winsize 57
6704 23:23:14.966915 [CA 4] Center 36 (8~64) winsize 57
6705 23:23:14.970051 [CA 5] Center 36 (8~64) winsize 57
6706 23:23:14.970146
6707 23:23:14.976599 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6708 23:23:14.976689
6709 23:23:14.979829 [CATrainingPosCal] consider 1 rank data
6710 23:23:14.983334 u2DelayCellTimex100 = 270/100 ps
6711 23:23:14.986604 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 23:23:14.989563 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 23:23:14.993399 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 23:23:14.996341 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 23:23:14.999596 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 23:23:15.003085 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 23:23:15.003169
6718 23:23:15.006325 CA PerBit enable=1, Macro0, CA PI delay=36
6719 23:23:15.006414
6720 23:23:15.009818 [CBTSetCACLKResult] CA Dly = 36
6721 23:23:15.013025 CS Dly: 1 (0~32)
6722 23:23:15.013126 ==
6723 23:23:15.016466 Dram Type= 6, Freq= 0, CH_1, rank 1
6724 23:23:15.019511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 23:23:15.019651 ==
6726 23:23:15.026051 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6727 23:23:15.032799 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6728 23:23:15.035846 [CA 0] Center 36 (8~64) winsize 57
6729 23:23:15.035936 [CA 1] Center 36 (8~64) winsize 57
6730 23:23:15.039165 [CA 2] Center 36 (8~64) winsize 57
6731 23:23:15.042814 [CA 3] Center 36 (8~64) winsize 57
6732 23:23:15.045706 [CA 4] Center 36 (8~64) winsize 57
6733 23:23:15.049294 [CA 5] Center 36 (8~64) winsize 57
6734 23:23:15.049381
6735 23:23:15.052764 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6736 23:23:15.052885
6737 23:23:15.059088 [CATrainingPosCal] consider 2 rank data
6738 23:23:15.059192 u2DelayCellTimex100 = 270/100 ps
6739 23:23:15.065987 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6740 23:23:15.068651 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6741 23:23:15.072381 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6742 23:23:15.075468 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6743 23:23:15.078663 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6744 23:23:15.082458 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6745 23:23:15.082583
6746 23:23:15.085543 CA PerBit enable=1, Macro0, CA PI delay=36
6747 23:23:15.085664
6748 23:23:15.088838 [CBTSetCACLKResult] CA Dly = 36
6749 23:23:15.091782 CS Dly: 1 (0~32)
6750 23:23:15.091875
6751 23:23:15.095250 ----->DramcWriteLeveling(PI) begin...
6752 23:23:15.095352 ==
6753 23:23:15.098526 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 23:23:15.101752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 23:23:15.101873 ==
6756 23:23:15.105007 Write leveling (Byte 0): 40 => 8
6757 23:23:15.108693 Write leveling (Byte 1): 40 => 8
6758 23:23:15.111759 DramcWriteLeveling(PI) end<-----
6759 23:23:15.111844
6760 23:23:15.111946 ==
6761 23:23:15.115415 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 23:23:15.118904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 23:23:15.119013 ==
6764 23:23:15.121593 [Gating] SW mode calibration
6765 23:23:15.128242 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6766 23:23:15.134717 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6767 23:23:15.138042 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6768 23:23:15.141550 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6769 23:23:15.148162 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6770 23:23:15.151293 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6771 23:23:15.154580 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6772 23:23:15.161164 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6773 23:23:15.164777 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6774 23:23:15.167783 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6775 23:23:15.174810 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6776 23:23:15.178105 Total UI for P1: 0, mck2ui 16
6777 23:23:15.181014 best dqsien dly found for B0: ( 0, 14, 24)
6778 23:23:15.183978 Total UI for P1: 0, mck2ui 16
6779 23:23:15.187628 best dqsien dly found for B1: ( 0, 14, 24)
6780 23:23:15.190796 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6781 23:23:15.194366 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6782 23:23:15.194444
6783 23:23:15.197740 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6784 23:23:15.200476 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6785 23:23:15.203654 [Gating] SW calibration Done
6786 23:23:15.203780 ==
6787 23:23:15.207365 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 23:23:15.210666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 23:23:15.213704 ==
6790 23:23:15.213789 RX Vref Scan: 0
6791 23:23:15.213853
6792 23:23:15.217023 RX Vref 0 -> 0, step: 1
6793 23:23:15.217117
6794 23:23:15.220308 RX Delay -410 -> 252, step: 16
6795 23:23:15.223578 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6796 23:23:15.226981 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6797 23:23:15.230291 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6798 23:23:15.236581 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6799 23:23:15.240040 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6800 23:23:15.243498 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6801 23:23:15.246845 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6802 23:23:15.253053 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6803 23:23:15.256351 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6804 23:23:15.259420 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6805 23:23:15.266587 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6806 23:23:15.269629 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6807 23:23:15.272617 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6808 23:23:15.276412 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6809 23:23:15.282959 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6810 23:23:15.286330 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6811 23:23:15.286450 ==
6812 23:23:15.289822 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 23:23:15.292547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 23:23:15.292627 ==
6815 23:23:15.296354 DQS Delay:
6816 23:23:15.296434 DQS0 = 35, DQS1 = 51
6817 23:23:15.298861 DQM Delay:
6818 23:23:15.298951 DQM0 = 5, DQM1 = 15
6819 23:23:15.299026 DQ Delay:
6820 23:23:15.302174 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6821 23:23:15.305893 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6822 23:23:15.309446 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =0
6823 23:23:15.312507 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6824 23:23:15.312593
6825 23:23:15.312658
6826 23:23:15.312722 ==
6827 23:23:15.315968 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 23:23:15.322207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 23:23:15.322299 ==
6830 23:23:15.322370
6831 23:23:15.322446
6832 23:23:15.322531 TX Vref Scan disable
6833 23:23:15.325607 == TX Byte 0 ==
6834 23:23:15.329132 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6835 23:23:15.331980 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6836 23:23:15.335333 == TX Byte 1 ==
6837 23:23:15.338761 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6838 23:23:15.341946 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6839 23:23:15.342065 ==
6840 23:23:15.345472 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 23:23:15.351947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 23:23:15.352032 ==
6843 23:23:15.352108
6844 23:23:15.352177
6845 23:23:15.352236 TX Vref Scan disable
6846 23:23:15.355371 == TX Byte 0 ==
6847 23:23:15.358680 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6848 23:23:15.362324 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6849 23:23:15.365165 == TX Byte 1 ==
6850 23:23:15.368888 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6851 23:23:15.371861 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6852 23:23:15.371941
6853 23:23:15.375264 [DATLAT]
6854 23:23:15.375374 Freq=400, CH1 RK0
6855 23:23:15.375466
6856 23:23:15.378458 DATLAT Default: 0xf
6857 23:23:15.378540 0, 0xFFFF, sum = 0
6858 23:23:15.381830 1, 0xFFFF, sum = 0
6859 23:23:15.381945 2, 0xFFFF, sum = 0
6860 23:23:15.385302 3, 0xFFFF, sum = 0
6861 23:23:15.385388 4, 0xFFFF, sum = 0
6862 23:23:15.388082 5, 0xFFFF, sum = 0
6863 23:23:15.388165 6, 0xFFFF, sum = 0
6864 23:23:15.391836 7, 0xFFFF, sum = 0
6865 23:23:15.395477 8, 0xFFFF, sum = 0
6866 23:23:15.395551 9, 0xFFFF, sum = 0
6867 23:23:15.398085 10, 0xFFFF, sum = 0
6868 23:23:15.398173 11, 0xFFFF, sum = 0
6869 23:23:15.401818 12, 0xFFFF, sum = 0
6870 23:23:15.401940 13, 0x0, sum = 1
6871 23:23:15.404987 14, 0x0, sum = 2
6872 23:23:15.405135 15, 0x0, sum = 3
6873 23:23:15.408301 16, 0x0, sum = 4
6874 23:23:15.408405 best_step = 14
6875 23:23:15.408511
6876 23:23:15.408614 ==
6877 23:23:15.411740 Dram Type= 6, Freq= 0, CH_1, rank 0
6878 23:23:15.414953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 23:23:15.415048 ==
6880 23:23:15.418075 RX Vref Scan: 1
6881 23:23:15.418190
6882 23:23:15.421567 RX Vref 0 -> 0, step: 1
6883 23:23:15.421670
6884 23:23:15.421774 RX Delay -343 -> 252, step: 8
6885 23:23:15.425009
6886 23:23:15.425122 Set Vref, RX VrefLevel [Byte0]: 53
6887 23:23:15.427777 [Byte1]: 60
6888 23:23:15.433960
6889 23:23:15.434113 Final RX Vref Byte 0 = 53 to rank0
6890 23:23:15.436640 Final RX Vref Byte 1 = 60 to rank0
6891 23:23:15.440257 Final RX Vref Byte 0 = 53 to rank1
6892 23:23:15.443312 Final RX Vref Byte 1 = 60 to rank1==
6893 23:23:15.447053 Dram Type= 6, Freq= 0, CH_1, rank 0
6894 23:23:15.453267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 23:23:15.453356 ==
6896 23:23:15.453425 DQS Delay:
6897 23:23:15.456500 DQS0 = 44, DQS1 = 56
6898 23:23:15.456582 DQM Delay:
6899 23:23:15.456646 DQM0 = 8, DQM1 = 12
6900 23:23:15.460455 DQ Delay:
6901 23:23:15.463089 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6902 23:23:15.463171 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =0
6903 23:23:15.467190 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6904 23:23:15.470739 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6905 23:23:15.470837
6906 23:23:15.472866
6907 23:23:15.479660 [DQSOSCAuto] RK0, (LSB)MR18= 0x9269, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6908 23:23:15.483104 CH1 RK0: MR19=C0C, MR18=9269
6909 23:23:15.489367 CH1_RK0: MR19=0xC0C, MR18=0x9269, DQSOSC=391, MR23=63, INC=386, DEC=257
6910 23:23:15.489507 ==
6911 23:23:15.493421 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 23:23:15.496394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 23:23:15.496501 ==
6914 23:23:15.499775 [Gating] SW mode calibration
6915 23:23:15.506209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6916 23:23:15.512895 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6917 23:23:15.515842 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6918 23:23:15.519833 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6919 23:23:15.526321 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6920 23:23:15.529024 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6921 23:23:15.533146 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6922 23:23:15.539184 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6923 23:23:15.542386 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6924 23:23:15.545927 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6925 23:23:15.552341 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6926 23:23:15.552426 Total UI for P1: 0, mck2ui 16
6927 23:23:15.559167 best dqsien dly found for B0: ( 0, 14, 24)
6928 23:23:15.559252 Total UI for P1: 0, mck2ui 16
6929 23:23:15.565251 best dqsien dly found for B1: ( 0, 14, 24)
6930 23:23:15.568437 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6931 23:23:15.571785 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6932 23:23:15.571870
6933 23:23:15.575039 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6934 23:23:15.578651 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6935 23:23:15.581424 [Gating] SW calibration Done
6936 23:23:15.581512 ==
6937 23:23:15.585164 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 23:23:15.588229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 23:23:15.588338 ==
6940 23:23:15.591807 RX Vref Scan: 0
6941 23:23:15.591889
6942 23:23:15.594705 RX Vref 0 -> 0, step: 1
6943 23:23:15.594789
6944 23:23:15.594855 RX Delay -410 -> 252, step: 16
6945 23:23:15.601388 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6946 23:23:15.604650 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6947 23:23:15.608492 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6948 23:23:15.611197 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6949 23:23:15.617955 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6950 23:23:15.621614 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6951 23:23:15.624645 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6952 23:23:15.631242 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6953 23:23:15.634654 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6954 23:23:15.637750 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6955 23:23:15.641218 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6956 23:23:15.647867 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6957 23:23:15.651020 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6958 23:23:15.654363 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6959 23:23:15.657875 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6960 23:23:15.664163 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6961 23:23:15.664246 ==
6962 23:23:15.667394 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 23:23:15.670932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 23:23:15.671015 ==
6965 23:23:15.671081 DQS Delay:
6966 23:23:15.674201 DQS0 = 43, DQS1 = 51
6967 23:23:15.674283 DQM Delay:
6968 23:23:15.677246 DQM0 = 12, DQM1 = 15
6969 23:23:15.677328 DQ Delay:
6970 23:23:15.680424 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6971 23:23:15.683819 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6972 23:23:15.687564 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6973 23:23:15.690758 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6974 23:23:15.690840
6975 23:23:15.690905
6976 23:23:15.690971 ==
6977 23:23:15.693581 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 23:23:15.697478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 23:23:15.697572 ==
6980 23:23:15.697639
6981 23:23:15.700896
6982 23:23:15.700972 TX Vref Scan disable
6983 23:23:15.703580 == TX Byte 0 ==
6984 23:23:15.706912 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6985 23:23:15.710080 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6986 23:23:15.713920 == TX Byte 1 ==
6987 23:23:15.716685 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6988 23:23:15.719955 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6989 23:23:15.720077 ==
6990 23:23:15.723621 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 23:23:15.726821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 23:23:15.729837 ==
6993 23:23:15.729945
6994 23:23:15.730064
6995 23:23:15.730160 TX Vref Scan disable
6996 23:23:15.733703 == TX Byte 0 ==
6997 23:23:15.736636 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6998 23:23:15.740098 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6999 23:23:15.743543 == TX Byte 1 ==
7000 23:23:15.746559 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
7001 23:23:15.750438 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7002 23:23:15.750571
7003 23:23:15.753070 [DATLAT]
7004 23:23:15.753150 Freq=400, CH1 RK1
7005 23:23:15.753232
7006 23:23:15.756968 DATLAT Default: 0xe
7007 23:23:15.757049 0, 0xFFFF, sum = 0
7008 23:23:15.759562 1, 0xFFFF, sum = 0
7009 23:23:15.759695 2, 0xFFFF, sum = 0
7010 23:23:15.762753 3, 0xFFFF, sum = 0
7011 23:23:15.762861 4, 0xFFFF, sum = 0
7012 23:23:15.766235 5, 0xFFFF, sum = 0
7013 23:23:15.766361 6, 0xFFFF, sum = 0
7014 23:23:15.769379 7, 0xFFFF, sum = 0
7015 23:23:15.769497 8, 0xFFFF, sum = 0
7016 23:23:15.773381 9, 0xFFFF, sum = 0
7017 23:23:15.773505 10, 0xFFFF, sum = 0
7018 23:23:15.776206 11, 0xFFFF, sum = 0
7019 23:23:15.779556 12, 0xFFFF, sum = 0
7020 23:23:15.779635 13, 0x0, sum = 1
7021 23:23:15.779727 14, 0x0, sum = 2
7022 23:23:15.783083 15, 0x0, sum = 3
7023 23:23:15.783207 16, 0x0, sum = 4
7024 23:23:15.786339 best_step = 14
7025 23:23:15.786465
7026 23:23:15.786564 ==
7027 23:23:15.789238 Dram Type= 6, Freq= 0, CH_1, rank 1
7028 23:23:15.792606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7029 23:23:15.792689 ==
7030 23:23:15.795814 RX Vref Scan: 0
7031 23:23:15.795902
7032 23:23:15.795974 RX Vref 0 -> 0, step: 1
7033 23:23:15.799286
7034 23:23:15.799405 RX Delay -343 -> 252, step: 8
7035 23:23:15.807386 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7036 23:23:15.811090 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7037 23:23:15.813958 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7038 23:23:15.821137 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7039 23:23:15.824063 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7040 23:23:15.827813 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7041 23:23:15.830565 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7042 23:23:15.836919 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7043 23:23:15.840897 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7044 23:23:15.844209 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7045 23:23:15.847090 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7046 23:23:15.853622 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
7047 23:23:15.857084 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7048 23:23:15.860343 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7049 23:23:15.866712 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7050 23:23:15.869585 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7051 23:23:15.869712 ==
7052 23:23:15.873124 Dram Type= 6, Freq= 0, CH_1, rank 1
7053 23:23:15.876435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7054 23:23:15.876561 ==
7055 23:23:15.879866 DQS Delay:
7056 23:23:15.879953 DQS0 = 44, DQS1 = 56
7057 23:23:15.880018 DQM Delay:
7058 23:23:15.883257 DQM0 = 8, DQM1 = 10
7059 23:23:15.883372 DQ Delay:
7060 23:23:15.886222 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7061 23:23:15.889484 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7062 23:23:15.893086 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7063 23:23:15.896645 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7064 23:23:15.896731
7065 23:23:15.896843
7066 23:23:15.906024 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d4c, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7067 23:23:15.906144 CH1 RK1: MR19=C0C, MR18=5D4C
7068 23:23:15.912568 CH1_RK1: MR19=0xC0C, MR18=0x5D4C, DQSOSC=398, MR23=63, INC=372, DEC=248
7069 23:23:15.915831 [RxdqsGatingPostProcess] freq 400
7070 23:23:15.922565 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7071 23:23:15.925846 best DQS0 dly(2T, 0.5T) = (0, 10)
7072 23:23:15.928854 best DQS1 dly(2T, 0.5T) = (0, 10)
7073 23:23:15.932172 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7074 23:23:15.935827 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7075 23:23:15.939153 best DQS0 dly(2T, 0.5T) = (0, 10)
7076 23:23:15.942041 best DQS1 dly(2T, 0.5T) = (0, 10)
7077 23:23:15.945543 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7078 23:23:15.948835 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7079 23:23:15.951866 Pre-setting of DQS Precalculation
7080 23:23:15.955876 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7081 23:23:15.962366 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7082 23:23:15.968920 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7083 23:23:15.969001
7084 23:23:15.969095
7085 23:23:15.971765 [Calibration Summary] 800 Mbps
7086 23:23:15.975270 CH 0, Rank 0
7087 23:23:15.975370 SW Impedance : PASS
7088 23:23:15.978431 DUTY Scan : NO K
7089 23:23:15.982120 ZQ Calibration : PASS
7090 23:23:15.982222 Jitter Meter : NO K
7091 23:23:15.985362 CBT Training : PASS
7092 23:23:15.988403 Write leveling : PASS
7093 23:23:15.988479 RX DQS gating : PASS
7094 23:23:15.992156 RX DQ/DQS(RDDQC) : PASS
7095 23:23:15.995129 TX DQ/DQS : PASS
7096 23:23:15.995236 RX DATLAT : PASS
7097 23:23:15.998090 RX DQ/DQS(Engine): PASS
7098 23:23:16.001474 TX OE : NO K
7099 23:23:16.001550 All Pass.
7100 23:23:16.001614
7101 23:23:16.001690 CH 0, Rank 1
7102 23:23:16.004808 SW Impedance : PASS
7103 23:23:16.007667 DUTY Scan : NO K
7104 23:23:16.007764 ZQ Calibration : PASS
7105 23:23:16.011186 Jitter Meter : NO K
7106 23:23:16.014269 CBT Training : PASS
7107 23:23:16.014343 Write leveling : NO K
7108 23:23:16.017827 RX DQS gating : PASS
7109 23:23:16.021253 RX DQ/DQS(RDDQC) : PASS
7110 23:23:16.021327 TX DQ/DQS : PASS
7111 23:23:16.024699 RX DATLAT : PASS
7112 23:23:16.024773 RX DQ/DQS(Engine): PASS
7113 23:23:16.027386 TX OE : NO K
7114 23:23:16.027463 All Pass.
7115 23:23:16.027526
7116 23:23:16.031009 CH 1, Rank 0
7117 23:23:16.031110 SW Impedance : PASS
7118 23:23:16.034462 DUTY Scan : NO K
7119 23:23:16.037770 ZQ Calibration : PASS
7120 23:23:16.037852 Jitter Meter : NO K
7121 23:23:16.041026 CBT Training : PASS
7122 23:23:16.044691 Write leveling : PASS
7123 23:23:16.044799 RX DQS gating : PASS
7124 23:23:16.047600 RX DQ/DQS(RDDQC) : PASS
7125 23:23:16.051178 TX DQ/DQS : PASS
7126 23:23:16.051260 RX DATLAT : PASS
7127 23:23:16.054592 RX DQ/DQS(Engine): PASS
7128 23:23:16.057499 TX OE : NO K
7129 23:23:16.057621 All Pass.
7130 23:23:16.057729
7131 23:23:16.057818 CH 1, Rank 1
7132 23:23:16.061306 SW Impedance : PASS
7133 23:23:16.064217 DUTY Scan : NO K
7134 23:23:16.064299 ZQ Calibration : PASS
7135 23:23:16.067546 Jitter Meter : NO K
7136 23:23:16.070961 CBT Training : PASS
7137 23:23:16.071050 Write leveling : NO K
7138 23:23:16.073956 RX DQS gating : PASS
7139 23:23:16.077283 RX DQ/DQS(RDDQC) : PASS
7140 23:23:16.077383 TX DQ/DQS : PASS
7141 23:23:16.080546 RX DATLAT : PASS
7142 23:23:16.083588 RX DQ/DQS(Engine): PASS
7143 23:23:16.083698 TX OE : NO K
7144 23:23:16.083779 All Pass.
7145 23:23:16.087002
7146 23:23:16.087084 DramC Write-DBI off
7147 23:23:16.090225 PER_BANK_REFRESH: Hybrid Mode
7148 23:23:16.090340 TX_TRACKING: ON
7149 23:23:16.100013 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7150 23:23:16.103294 [FAST_K] Save calibration result to emmc
7151 23:23:16.106811 dramc_set_vcore_voltage set vcore to 725000
7152 23:23:16.109962 Read voltage for 1600, 0
7153 23:23:16.110058 Vio18 = 0
7154 23:23:16.113326 Vcore = 725000
7155 23:23:16.113408 Vdram = 0
7156 23:23:16.113510 Vddq = 0
7157 23:23:16.116467 Vmddr = 0
7158 23:23:16.120173 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7159 23:23:16.127129 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7160 23:23:16.127241 MEM_TYPE=3, freq_sel=13
7161 23:23:16.129726 sv_algorithm_assistance_LP4_3733
7162 23:23:16.136766 ============ PULL DRAM RESETB DOWN ============
7163 23:23:16.139873 ========== PULL DRAM RESETB DOWN end =========
7164 23:23:16.142682 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7165 23:23:16.146577 ===================================
7166 23:23:16.149931 LPDDR4 DRAM CONFIGURATION
7167 23:23:16.153054 ===================================
7168 23:23:16.156252 EX_ROW_EN[0] = 0x0
7169 23:23:16.156368 EX_ROW_EN[1] = 0x0
7170 23:23:16.159558 LP4Y_EN = 0x0
7171 23:23:16.159692 WORK_FSP = 0x1
7172 23:23:16.162651 WL = 0x5
7173 23:23:16.162724 RL = 0x5
7174 23:23:16.166241 BL = 0x2
7175 23:23:16.166321 RPST = 0x0
7176 23:23:16.169589 RD_PRE = 0x0
7177 23:23:16.169697 WR_PRE = 0x1
7178 23:23:16.172852 WR_PST = 0x1
7179 23:23:16.172926 DBI_WR = 0x0
7180 23:23:16.176011 DBI_RD = 0x0
7181 23:23:16.176085 OTF = 0x1
7182 23:23:16.179666 ===================================
7183 23:23:16.182329 ===================================
7184 23:23:16.186098 ANA top config
7185 23:23:16.189270 ===================================
7186 23:23:16.192577 DLL_ASYNC_EN = 0
7187 23:23:16.192655 ALL_SLAVE_EN = 0
7188 23:23:16.195860 NEW_RANK_MODE = 1
7189 23:23:16.199035 DLL_IDLE_MODE = 1
7190 23:23:16.202699 LP45_APHY_COMB_EN = 1
7191 23:23:16.205714 TX_ODT_DIS = 0
7192 23:23:16.205793 NEW_8X_MODE = 1
7193 23:23:16.208982 ===================================
7194 23:23:16.212397 ===================================
7195 23:23:16.215576 data_rate = 3200
7196 23:23:16.219067 CKR = 1
7197 23:23:16.222727 DQ_P2S_RATIO = 8
7198 23:23:16.225209 ===================================
7199 23:23:16.228604 CA_P2S_RATIO = 8
7200 23:23:16.231825 DQ_CA_OPEN = 0
7201 23:23:16.231909 DQ_SEMI_OPEN = 0
7202 23:23:16.235695 CA_SEMI_OPEN = 0
7203 23:23:16.238946 CA_FULL_RATE = 0
7204 23:23:16.242165 DQ_CKDIV4_EN = 0
7205 23:23:16.245235 CA_CKDIV4_EN = 0
7206 23:23:16.248914 CA_PREDIV_EN = 0
7207 23:23:16.249000 PH8_DLY = 12
7208 23:23:16.252072 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7209 23:23:16.255291 DQ_AAMCK_DIV = 4
7210 23:23:16.258572 CA_AAMCK_DIV = 4
7211 23:23:16.261770 CA_ADMCK_DIV = 4
7212 23:23:16.264714 DQ_TRACK_CA_EN = 0
7213 23:23:16.268379 CA_PICK = 1600
7214 23:23:16.268474 CA_MCKIO = 1600
7215 23:23:16.271269 MCKIO_SEMI = 0
7216 23:23:16.274902 PLL_FREQ = 3068
7217 23:23:16.278059 DQ_UI_PI_RATIO = 32
7218 23:23:16.281213 CA_UI_PI_RATIO = 0
7219 23:23:16.284454 ===================================
7220 23:23:16.288306 ===================================
7221 23:23:16.291975 memory_type:LPDDR4
7222 23:23:16.292057 GP_NUM : 10
7223 23:23:16.294613 SRAM_EN : 1
7224 23:23:16.294711 MD32_EN : 0
7225 23:23:16.297969 ===================================
7226 23:23:16.301018 [ANA_INIT] >>>>>>>>>>>>>>
7227 23:23:16.304435 <<<<<< [CONFIGURE PHASE]: ANA_TX
7228 23:23:16.307631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7229 23:23:16.311461 ===================================
7230 23:23:16.314442 data_rate = 3200,PCW = 0X7600
7231 23:23:16.317834 ===================================
7232 23:23:16.320856 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7233 23:23:16.327619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7234 23:23:16.331221 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7235 23:23:16.337291 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7236 23:23:16.340935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7237 23:23:16.343617 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7238 23:23:16.343715 [ANA_INIT] flow start
7239 23:23:16.347140 [ANA_INIT] PLL >>>>>>>>
7240 23:23:16.350575 [ANA_INIT] PLL <<<<<<<<
7241 23:23:16.353797 [ANA_INIT] MIDPI >>>>>>>>
7242 23:23:16.353876 [ANA_INIT] MIDPI <<<<<<<<
7243 23:23:16.357114 [ANA_INIT] DLL >>>>>>>>
7244 23:23:16.360165 [ANA_INIT] DLL <<<<<<<<
7245 23:23:16.360246 [ANA_INIT] flow end
7246 23:23:16.366520 ============ LP4 DIFF to SE enter ============
7247 23:23:16.369922 ============ LP4 DIFF to SE exit ============
7248 23:23:16.373357 [ANA_INIT] <<<<<<<<<<<<<
7249 23:23:16.376354 [Flow] Enable top DCM control >>>>>
7250 23:23:16.380009 [Flow] Enable top DCM control <<<<<
7251 23:23:16.380089 Enable DLL master slave shuffle
7252 23:23:16.386540 ==============================================================
7253 23:23:16.390084 Gating Mode config
7254 23:23:16.393322 ==============================================================
7255 23:23:16.396327 Config description:
7256 23:23:16.405942 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7257 23:23:16.412790 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7258 23:23:16.415939 SELPH_MODE 0: By rank 1: By Phase
7259 23:23:16.422793 ==============================================================
7260 23:23:16.425795 GAT_TRACK_EN = 1
7261 23:23:16.429395 RX_GATING_MODE = 2
7262 23:23:16.432390 RX_GATING_TRACK_MODE = 2
7263 23:23:16.435990 SELPH_MODE = 1
7264 23:23:16.439055 PICG_EARLY_EN = 1
7265 23:23:16.439137 VALID_LAT_VALUE = 1
7266 23:23:16.445962 ==============================================================
7267 23:23:16.449081 Enter into Gating configuration >>>>
7268 23:23:16.452791 Exit from Gating configuration <<<<
7269 23:23:16.455824 Enter into DVFS_PRE_config >>>>>
7270 23:23:16.465543 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7271 23:23:16.468798 Exit from DVFS_PRE_config <<<<<
7272 23:23:16.471984 Enter into PICG configuration >>>>
7273 23:23:16.475660 Exit from PICG configuration <<<<
7274 23:23:16.478406 [RX_INPUT] configuration >>>>>
7275 23:23:16.481928 [RX_INPUT] configuration <<<<<
7276 23:23:16.488745 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7277 23:23:16.491974 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7278 23:23:16.498545 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7279 23:23:16.505254 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7280 23:23:16.511825 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7281 23:23:16.518177 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7282 23:23:16.521737 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7283 23:23:16.524960 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7284 23:23:16.527891 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7285 23:23:16.534525 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7286 23:23:16.538282 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7287 23:23:16.541345 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7288 23:23:16.544571 ===================================
7289 23:23:16.547580 LPDDR4 DRAM CONFIGURATION
7290 23:23:16.551350 ===================================
7291 23:23:16.554445 EX_ROW_EN[0] = 0x0
7292 23:23:16.554526 EX_ROW_EN[1] = 0x0
7293 23:23:16.557364 LP4Y_EN = 0x0
7294 23:23:16.557448 WORK_FSP = 0x1
7295 23:23:16.561248 WL = 0x5
7296 23:23:16.561332 RL = 0x5
7297 23:23:16.564056 BL = 0x2
7298 23:23:16.564147 RPST = 0x0
7299 23:23:16.567776 RD_PRE = 0x0
7300 23:23:16.567903 WR_PRE = 0x1
7301 23:23:16.571065 WR_PST = 0x1
7302 23:23:16.571145 DBI_WR = 0x0
7303 23:23:16.573848 DBI_RD = 0x0
7304 23:23:16.577714 OTF = 0x1
7305 23:23:16.580987 ===================================
7306 23:23:16.584291 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7307 23:23:16.587290 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7308 23:23:16.590392 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7309 23:23:16.594343 ===================================
7310 23:23:16.597262 LPDDR4 DRAM CONFIGURATION
7311 23:23:16.600691 ===================================
7312 23:23:16.603905 EX_ROW_EN[0] = 0x10
7313 23:23:16.603985 EX_ROW_EN[1] = 0x0
7314 23:23:16.607054 LP4Y_EN = 0x0
7315 23:23:16.607132 WORK_FSP = 0x1
7316 23:23:16.610542 WL = 0x5
7317 23:23:16.610619 RL = 0x5
7318 23:23:16.613824 BL = 0x2
7319 23:23:16.613936 RPST = 0x0
7320 23:23:16.617163 RD_PRE = 0x0
7321 23:23:16.617247 WR_PRE = 0x1
7322 23:23:16.620152 WR_PST = 0x1
7323 23:23:16.620242 DBI_WR = 0x0
7324 23:23:16.623588 DBI_RD = 0x0
7325 23:23:16.626643 OTF = 0x1
7326 23:23:16.630325 ===================================
7327 23:23:16.633633 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7328 23:23:16.636410 ==
7329 23:23:16.636495 Dram Type= 6, Freq= 0, CH_0, rank 0
7330 23:23:16.643432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7331 23:23:16.643545 ==
7332 23:23:16.646276 [Duty_Offset_Calibration]
7333 23:23:16.646385 B0:1 B1:-1 CA:0
7334 23:23:16.646484
7335 23:23:16.649948 [DutyScan_Calibration_Flow] k_type=0
7336 23:23:16.659678
7337 23:23:16.659761 ==CLK 0==
7338 23:23:16.662914 Final CLK duty delay cell = 0
7339 23:23:16.666507 [0] MAX Duty = 5125%(X100), DQS PI = 20
7340 23:23:16.669390 [0] MIN Duty = 4907%(X100), DQS PI = 4
7341 23:23:16.669466 [0] AVG Duty = 5016%(X100)
7342 23:23:16.672863
7343 23:23:16.676226 CH0 CLK Duty spec in!! Max-Min= 218%
7344 23:23:16.679699 [DutyScan_Calibration_Flow] ====Done====
7345 23:23:16.679784
7346 23:23:16.682592 [DutyScan_Calibration_Flow] k_type=1
7347 23:23:16.699097
7348 23:23:16.699189 ==DQS 0 ==
7349 23:23:16.702394 Final DQS duty delay cell = -4
7350 23:23:16.705563 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7351 23:23:16.708415 [-4] MIN Duty = 4844%(X100), DQS PI = 54
7352 23:23:16.712065 [-4] AVG Duty = 4906%(X100)
7353 23:23:16.712150
7354 23:23:16.712217 ==DQS 1 ==
7355 23:23:16.715431 Final DQS duty delay cell = 0
7356 23:23:16.719056 [0] MAX Duty = 5156%(X100), DQS PI = 0
7357 23:23:16.722023 [0] MIN Duty = 5031%(X100), DQS PI = 20
7358 23:23:16.725282 [0] AVG Duty = 5093%(X100)
7359 23:23:16.725376
7360 23:23:16.728609 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7361 23:23:16.728697
7362 23:23:16.731573 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7363 23:23:16.735076 [DutyScan_Calibration_Flow] ====Done====
7364 23:23:16.735166
7365 23:23:16.738228 [DutyScan_Calibration_Flow] k_type=3
7366 23:23:16.756513
7367 23:23:16.756613 ==DQM 0 ==
7368 23:23:16.759572 Final DQM duty delay cell = 0
7369 23:23:16.763056 [0] MAX Duty = 5124%(X100), DQS PI = 22
7370 23:23:16.766133 [0] MIN Duty = 4907%(X100), DQS PI = 8
7371 23:23:16.769899 [0] AVG Duty = 5015%(X100)
7372 23:23:16.769991
7373 23:23:16.770065 ==DQM 1 ==
7374 23:23:16.772998 Final DQM duty delay cell = 0
7375 23:23:16.776835 [0] MAX Duty = 5000%(X100), DQS PI = 4
7376 23:23:16.779454 [0] MIN Duty = 4813%(X100), DQS PI = 20
7377 23:23:16.782674 [0] AVG Duty = 4906%(X100)
7378 23:23:16.782755
7379 23:23:16.786290 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7380 23:23:16.786380
7381 23:23:16.789377 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7382 23:23:16.792873 [DutyScan_Calibration_Flow] ====Done====
7383 23:23:16.792957
7384 23:23:16.795658 [DutyScan_Calibration_Flow] k_type=2
7385 23:23:16.812927
7386 23:23:16.813007 ==DQ 0 ==
7387 23:23:16.815522 Final DQ duty delay cell = -4
7388 23:23:16.818893 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7389 23:23:16.822373 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7390 23:23:16.825358 [-4] AVG Duty = 4953%(X100)
7391 23:23:16.825443
7392 23:23:16.825509 ==DQ 1 ==
7393 23:23:16.829201 Final DQ duty delay cell = 0
7394 23:23:16.832794 [0] MAX Duty = 5125%(X100), DQS PI = 48
7395 23:23:16.835496 [0] MIN Duty = 4969%(X100), DQS PI = 38
7396 23:23:16.839215 [0] AVG Duty = 5047%(X100)
7397 23:23:16.839316
7398 23:23:16.842292 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7399 23:23:16.842389
7400 23:23:16.845665 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7401 23:23:16.848815 [DutyScan_Calibration_Flow] ====Done====
7402 23:23:16.848897 ==
7403 23:23:16.852194 Dram Type= 6, Freq= 0, CH_1, rank 0
7404 23:23:16.855522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7405 23:23:16.855607 ==
7406 23:23:16.858423 [Duty_Offset_Calibration]
7407 23:23:16.858498 B0:-1 B1:1 CA:2
7408 23:23:16.862052
7409 23:23:16.864794 [DutyScan_Calibration_Flow] k_type=0
7410 23:23:16.873462
7411 23:23:16.873543 ==CLK 0==
7412 23:23:16.876776 Final CLK duty delay cell = 0
7413 23:23:16.879969 [0] MAX Duty = 5187%(X100), DQS PI = 20
7414 23:23:16.882927 [0] MIN Duty = 5031%(X100), DQS PI = 14
7415 23:23:16.886304 [0] AVG Duty = 5109%(X100)
7416 23:23:16.886446
7417 23:23:16.889769 CH1 CLK Duty spec in!! Max-Min= 156%
7418 23:23:16.893352 [DutyScan_Calibration_Flow] ====Done====
7419 23:23:16.893447
7420 23:23:16.896652 [DutyScan_Calibration_Flow] k_type=1
7421 23:23:16.912946
7422 23:23:16.913032 ==DQS 0 ==
7423 23:23:16.916082 Final DQS duty delay cell = 0
7424 23:23:16.919351 [0] MAX Duty = 5156%(X100), DQS PI = 22
7425 23:23:16.923301 [0] MIN Duty = 4907%(X100), DQS PI = 40
7426 23:23:16.926691 [0] AVG Duty = 5031%(X100)
7427 23:23:16.926798
7428 23:23:16.926870 ==DQS 1 ==
7429 23:23:16.929872 Final DQS duty delay cell = 0
7430 23:23:16.932892 [0] MAX Duty = 5093%(X100), DQS PI = 6
7431 23:23:16.935957 [0] MIN Duty = 4969%(X100), DQS PI = 26
7432 23:23:16.939967 [0] AVG Duty = 5031%(X100)
7433 23:23:16.940074
7434 23:23:16.943450 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7435 23:23:16.943555
7436 23:23:16.946046 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7437 23:23:16.949488 [DutyScan_Calibration_Flow] ====Done====
7438 23:23:16.949568
7439 23:23:16.952412 [DutyScan_Calibration_Flow] k_type=3
7440 23:23:16.969629
7441 23:23:16.969752 ==DQM 0 ==
7442 23:23:16.973104 Final DQM duty delay cell = 0
7443 23:23:16.977002 [0] MAX Duty = 5187%(X100), DQS PI = 0
7444 23:23:16.979908 [0] MIN Duty = 5031%(X100), DQS PI = 40
7445 23:23:16.983266 [0] AVG Duty = 5109%(X100)
7446 23:23:16.983368
7447 23:23:16.983468 ==DQM 1 ==
7448 23:23:16.986097 Final DQM duty delay cell = 0
7449 23:23:16.989711 [0] MAX Duty = 5187%(X100), DQS PI = 34
7450 23:23:16.992605 [0] MIN Duty = 4969%(X100), DQS PI = 58
7451 23:23:16.996075 [0] AVG Duty = 5078%(X100)
7452 23:23:16.996163
7453 23:23:16.999611 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7454 23:23:16.999748
7455 23:23:17.003045 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7456 23:23:17.006207 [DutyScan_Calibration_Flow] ====Done====
7457 23:23:17.006313
7458 23:23:17.009320 [DutyScan_Calibration_Flow] k_type=2
7459 23:23:17.026442
7460 23:23:17.026556 ==DQ 0 ==
7461 23:23:17.030017 Final DQ duty delay cell = 0
7462 23:23:17.033349 [0] MAX Duty = 5156%(X100), DQS PI = 0
7463 23:23:17.036528 [0] MIN Duty = 4906%(X100), DQS PI = 40
7464 23:23:17.036628 [0] AVG Duty = 5031%(X100)
7465 23:23:17.040106
7466 23:23:17.040236 ==DQ 1 ==
7467 23:23:17.042844 Final DQ duty delay cell = 0
7468 23:23:17.046488 [0] MAX Duty = 5156%(X100), DQS PI = 42
7469 23:23:17.049961 [0] MIN Duty = 4969%(X100), DQS PI = 26
7470 23:23:17.052950 [0] AVG Duty = 5062%(X100)
7471 23:23:17.053037
7472 23:23:17.056262 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7473 23:23:17.056349
7474 23:23:17.059638 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7475 23:23:17.062949 [DutyScan_Calibration_Flow] ====Done====
7476 23:23:17.065901 nWR fixed to 30
7477 23:23:17.069342 [ModeRegInit_LP4] CH0 RK0
7478 23:23:17.069429 [ModeRegInit_LP4] CH0 RK1
7479 23:23:17.072386 [ModeRegInit_LP4] CH1 RK0
7480 23:23:17.075624 [ModeRegInit_LP4] CH1 RK1
7481 23:23:17.075739 match AC timing 5
7482 23:23:17.082523 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7483 23:23:17.086075 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7484 23:23:17.089206 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7485 23:23:17.095576 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7486 23:23:17.099032 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7487 23:23:17.099115 [MiockJmeterHQA]
7488 23:23:17.102618
7489 23:23:17.102700 [DramcMiockJmeter] u1RxGatingPI = 0
7490 23:23:17.105856 0 : 4260, 4031
7491 23:23:17.105944 4 : 4258, 4029
7492 23:23:17.108719 8 : 4252, 4027
7493 23:23:17.108806 12 : 4363, 4137
7494 23:23:17.112106 16 : 4253, 4027
7495 23:23:17.112194 20 : 4253, 4026
7496 23:23:17.115242 24 : 4252, 4027
7497 23:23:17.115329 28 : 4254, 4029
7498 23:23:17.115434 32 : 4252, 4027
7499 23:23:17.118823 36 : 4363, 4138
7500 23:23:17.118910 40 : 4363, 4137
7501 23:23:17.122143 44 : 4253, 4027
7502 23:23:17.122230 48 : 4252, 4027
7503 23:23:17.125674 52 : 4253, 4026
7504 23:23:17.125760 56 : 4253, 4027
7505 23:23:17.128427 60 : 4255, 4029
7506 23:23:17.128528 64 : 4361, 4137
7507 23:23:17.128660 68 : 4250, 4027
7508 23:23:17.132000 72 : 4250, 4027
7509 23:23:17.132088 76 : 4250, 4027
7510 23:23:17.134999 80 : 4253, 4029
7511 23:23:17.135082 84 : 4250, 4027
7512 23:23:17.138675 88 : 4360, 4137
7513 23:23:17.138758 92 : 4361, 219
7514 23:23:17.138823 96 : 4250, 0
7515 23:23:17.141812 100 : 4360, 0
7516 23:23:17.141936 104 : 4363, 0
7517 23:23:17.145173 108 : 4250, 0
7518 23:23:17.145288 112 : 4250, 0
7519 23:23:17.145355 116 : 4250, 0
7520 23:23:17.148695 120 : 4250, 0
7521 23:23:17.148805 124 : 4250, 0
7522 23:23:17.151848 128 : 4250, 0
7523 23:23:17.151932 132 : 4252, 0
7524 23:23:17.151998 136 : 4250, 0
7525 23:23:17.155036 140 : 4250, 0
7526 23:23:17.155109 144 : 4363, 0
7527 23:23:17.157881 148 : 4361, 0
7528 23:23:17.157955 152 : 4360, 0
7529 23:23:17.158016 156 : 4363, 0
7530 23:23:17.161402 160 : 4250, 0
7531 23:23:17.161474 164 : 4250, 0
7532 23:23:17.164939 168 : 4250, 0
7533 23:23:17.165016 172 : 4252, 0
7534 23:23:17.165077 176 : 4250, 0
7535 23:23:17.168153 180 : 4250, 0
7536 23:23:17.168230 184 : 4252, 0
7537 23:23:17.168292 188 : 4250, 0
7538 23:23:17.171243 192 : 4361, 0
7539 23:23:17.171315 196 : 4250, 0
7540 23:23:17.174594 200 : 4361, 0
7541 23:23:17.174759 204 : 4360, 0
7542 23:23:17.174883 208 : 4250, 0
7543 23:23:17.177792 212 : 4250, 0
7544 23:23:17.177890 216 : 4250, 0
7545 23:23:17.181238 220 : 4250, 0
7546 23:23:17.181322 224 : 4250, 282
7547 23:23:17.184269 228 : 4250, 3592
7548 23:23:17.184380 232 : 4250, 4027
7549 23:23:17.184483 236 : 4252, 4030
7550 23:23:17.187563 240 : 4249, 4027
7551 23:23:17.187650 244 : 4250, 4027
7552 23:23:17.190880 248 : 4250, 4027
7553 23:23:17.190991 252 : 4360, 4138
7554 23:23:17.194525 256 : 4250, 4027
7555 23:23:17.194608 260 : 4250, 4027
7556 23:23:17.197717 264 : 4360, 4138
7557 23:23:17.197801 268 : 4250, 4027
7558 23:23:17.200857 272 : 4249, 4027
7559 23:23:17.200941 276 : 4363, 4140
7560 23:23:17.204395 280 : 4250, 4026
7561 23:23:17.204479 284 : 4250, 4027
7562 23:23:17.207387 288 : 4250, 4027
7563 23:23:17.207470 292 : 4252, 4029
7564 23:23:17.210678 296 : 4250, 4027
7565 23:23:17.210848 300 : 4250, 4027
7566 23:23:17.210919 304 : 4360, 4138
7567 23:23:17.214413 308 : 4249, 4027
7568 23:23:17.214561 312 : 4250, 4026
7569 23:23:17.217364 316 : 4360, 4138
7570 23:23:17.217443 320 : 4250, 4027
7571 23:23:17.220717 324 : 4250, 4027
7572 23:23:17.220821 328 : 4363, 4139
7573 23:23:17.224436 332 : 4250, 4027
7574 23:23:17.224515 336 : 4250, 3819
7575 23:23:17.227288 340 : 4252, 1700
7576 23:23:17.227385
7577 23:23:17.227474 MIOCK jitter meter ch=0
7578 23:23:17.230745
7579 23:23:17.230814 1T = (340-92) = 248 dly cells
7580 23:23:17.237177 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7581 23:23:17.237249 ==
7582 23:23:17.240084 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 23:23:17.243358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 23:23:17.243475 ==
7585 23:23:17.250343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7586 23:23:17.253710 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7587 23:23:17.260219 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7588 23:23:17.263383 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7589 23:23:17.277046 [CA 0] Center 43 (12~74) winsize 63
7590 23:23:17.277128 [CA 1] Center 43 (13~73) winsize 61
7591 23:23:17.280281 [CA 2] Center 38 (9~68) winsize 60
7592 23:23:17.283536 [CA 3] Center 38 (8~68) winsize 61
7593 23:23:17.286587 [CA 4] Center 36 (7~66) winsize 60
7594 23:23:17.290101 [CA 5] Center 35 (6~65) winsize 60
7595 23:23:17.290205
7596 23:23:17.293571 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7597 23:23:17.293672
7598 23:23:17.300005 [CATrainingPosCal] consider 1 rank data
7599 23:23:17.300080 u2DelayCellTimex100 = 262/100 ps
7600 23:23:17.306852 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7601 23:23:17.309627 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7602 23:23:17.313053 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7603 23:23:17.316110 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7604 23:23:17.319915 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7605 23:23:17.322824 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7606 23:23:17.322897
7607 23:23:17.326336 CA PerBit enable=1, Macro0, CA PI delay=35
7608 23:23:17.326466
7609 23:23:17.329802 [CBTSetCACLKResult] CA Dly = 35
7610 23:23:17.332825 CS Dly: 12 (0~43)
7611 23:23:17.336391 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7612 23:23:17.339836 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7613 23:23:17.342518 ==
7614 23:23:17.342608 Dram Type= 6, Freq= 0, CH_0, rank 1
7615 23:23:17.349293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 23:23:17.349385 ==
7617 23:23:17.352829 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7618 23:23:17.358857 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7619 23:23:17.362400 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7620 23:23:17.369015 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7621 23:23:17.377579 [CA 0] Center 43 (13~74) winsize 62
7622 23:23:17.380569 [CA 1] Center 44 (14~74) winsize 61
7623 23:23:17.384037 [CA 2] Center 38 (9~68) winsize 60
7624 23:23:17.387035 [CA 3] Center 38 (9~68) winsize 60
7625 23:23:17.390720 [CA 4] Center 36 (7~66) winsize 60
7626 23:23:17.393712 [CA 5] Center 36 (6~66) winsize 61
7627 23:23:17.393795
7628 23:23:17.397097 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7629 23:23:17.397204
7630 23:23:17.403848 [CATrainingPosCal] consider 2 rank data
7631 23:23:17.403958 u2DelayCellTimex100 = 262/100 ps
7632 23:23:17.410026 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7633 23:23:17.413392 CA1 delay=43 (14~73),Diff = 8 PI (29 cell)
7634 23:23:17.416952 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7635 23:23:17.420269 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7636 23:23:17.423299 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7637 23:23:17.426724 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7638 23:23:17.426825
7639 23:23:17.430418 CA PerBit enable=1, Macro0, CA PI delay=35
7640 23:23:17.430533
7641 23:23:17.433719 [CBTSetCACLKResult] CA Dly = 35
7642 23:23:17.436423 CS Dly: 12 (0~44)
7643 23:23:17.439688 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7644 23:23:17.443100 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7645 23:23:17.443199
7646 23:23:17.446737 ----->DramcWriteLeveling(PI) begin...
7647 23:23:17.446835 ==
7648 23:23:17.450034 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 23:23:17.457017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 23:23:17.457100 ==
7651 23:23:17.459884 Write leveling (Byte 0): 34 => 34
7652 23:23:17.463242 Write leveling (Byte 1): 29 => 29
7653 23:23:17.466873 DramcWriteLeveling(PI) end<-----
7654 23:23:17.466970
7655 23:23:17.467049 ==
7656 23:23:17.469536 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 23:23:17.472922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 23:23:17.473041 ==
7659 23:23:17.476231 [Gating] SW mode calibration
7660 23:23:17.482717 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7661 23:23:17.489338 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7662 23:23:17.493226 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 23:23:17.495984 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 23:23:17.502409 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 23:23:17.505732 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7666 23:23:17.509270 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7667 23:23:17.512825 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7668 23:23:17.518889 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7669 23:23:17.522497 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7670 23:23:17.525795 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7671 23:23:17.532703 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7672 23:23:17.535618 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7673 23:23:17.542210 1 5 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7674 23:23:17.545537 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7675 23:23:17.548514 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7676 23:23:17.552229 1 5 24 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
7677 23:23:17.558594 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7678 23:23:17.561970 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7679 23:23:17.565402 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7680 23:23:17.572022 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7681 23:23:17.575422 1 6 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
7682 23:23:17.578484 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7683 23:23:17.584935 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
7684 23:23:17.588503 1 6 24 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
7685 23:23:17.592260 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7686 23:23:17.598175 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7687 23:23:17.601561 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7688 23:23:17.605114 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 23:23:17.611615 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7690 23:23:17.615028 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7691 23:23:17.618487 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7692 23:23:17.624842 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7693 23:23:17.628605 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 23:23:17.631268 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 23:23:17.638337 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 23:23:17.641282 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 23:23:17.644620 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 23:23:17.651194 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 23:23:17.654446 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 23:23:17.658113 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 23:23:17.664556 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 23:23:17.667408 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 23:23:17.671035 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 23:23:17.677786 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7705 23:23:17.680838 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7706 23:23:17.684116 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7707 23:23:17.687863 Total UI for P1: 0, mck2ui 16
7708 23:23:17.690696 best dqsien dly found for B0: ( 1, 9, 10)
7709 23:23:17.697404 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7710 23:23:17.700590 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7711 23:23:17.704050 Total UI for P1: 0, mck2ui 16
7712 23:23:17.707539 best dqsien dly found for B1: ( 1, 9, 20)
7713 23:23:17.710430 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7714 23:23:17.714153 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7715 23:23:17.714255
7716 23:23:17.716821 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7717 23:23:17.723983 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7718 23:23:17.724103 [Gating] SW calibration Done
7719 23:23:17.724168 ==
7720 23:23:17.727356 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 23:23:17.733672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 23:23:17.733755 ==
7723 23:23:17.733821 RX Vref Scan: 0
7724 23:23:17.733882
7725 23:23:17.737144 RX Vref 0 -> 0, step: 1
7726 23:23:17.737226
7727 23:23:17.739970 RX Delay 0 -> 252, step: 8
7728 23:23:17.743495 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7729 23:23:17.746688 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7730 23:23:17.749988 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7731 23:23:17.757204 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7732 23:23:17.760152 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7733 23:23:17.763442 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7734 23:23:17.766395 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7735 23:23:17.770212 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7736 23:23:17.776389 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7737 23:23:17.779339 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7738 23:23:17.782794 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7739 23:23:17.786497 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7740 23:23:17.790034 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7741 23:23:17.796165 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7742 23:23:17.799083 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7743 23:23:17.802497 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7744 23:23:17.802579 ==
7745 23:23:17.806118 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 23:23:17.809727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 23:23:17.812541 ==
7748 23:23:17.812622 DQS Delay:
7749 23:23:17.812705 DQS0 = 0, DQS1 = 0
7750 23:23:17.815989 DQM Delay:
7751 23:23:17.816132 DQM0 = 135, DQM1 = 127
7752 23:23:17.819582 DQ Delay:
7753 23:23:17.822588 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7754 23:23:17.825817 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =147
7755 23:23:17.829192 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7756 23:23:17.832972 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7757 23:23:17.833054
7758 23:23:17.833137
7759 23:23:17.833212 ==
7760 23:23:17.836241 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 23:23:17.838849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 23:23:17.838945 ==
7763 23:23:17.842331
7764 23:23:17.842437
7765 23:23:17.842530 TX Vref Scan disable
7766 23:23:17.845880 == TX Byte 0 ==
7767 23:23:17.848869 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7768 23:23:17.852425 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7769 23:23:17.855814 == TX Byte 1 ==
7770 23:23:17.858585 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7771 23:23:17.862094 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7772 23:23:17.865359 ==
7773 23:23:17.865436 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 23:23:17.872331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 23:23:17.872424 ==
7776 23:23:17.884523
7777 23:23:17.887522 TX Vref early break, caculate TX vref
7778 23:23:17.890587 TX Vref=16, minBit 6, minWin=21, winSum=369
7779 23:23:17.894734 TX Vref=18, minBit 14, minWin=22, winSum=382
7780 23:23:17.897156 TX Vref=20, minBit 1, minWin=24, winSum=394
7781 23:23:17.900557 TX Vref=22, minBit 3, minWin=24, winSum=402
7782 23:23:17.904338 TX Vref=24, minBit 4, minWin=25, winSum=418
7783 23:23:17.910825 TX Vref=26, minBit 3, minWin=25, winSum=421
7784 23:23:17.913807 TX Vref=28, minBit 4, minWin=25, winSum=422
7785 23:23:17.917486 TX Vref=30, minBit 0, minWin=24, winSum=416
7786 23:23:17.920200 TX Vref=32, minBit 0, minWin=24, winSum=403
7787 23:23:17.923751 TX Vref=34, minBit 4, minWin=23, winSum=395
7788 23:23:17.930459 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 28
7789 23:23:17.930573
7790 23:23:17.934072 Final TX Range 0 Vref 28
7791 23:23:17.934155
7792 23:23:17.934220 ==
7793 23:23:17.937099 Dram Type= 6, Freq= 0, CH_0, rank 0
7794 23:23:17.940239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7795 23:23:17.940321 ==
7796 23:23:17.940390
7797 23:23:17.940473
7798 23:23:17.943483 TX Vref Scan disable
7799 23:23:17.949799 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7800 23:23:17.949881 == TX Byte 0 ==
7801 23:23:17.953927 u2DelayCellOfst[0]=18 cells (5 PI)
7802 23:23:17.956664 u2DelayCellOfst[1]=18 cells (5 PI)
7803 23:23:17.960014 u2DelayCellOfst[2]=14 cells (4 PI)
7804 23:23:17.963226 u2DelayCellOfst[3]=14 cells (4 PI)
7805 23:23:17.966753 u2DelayCellOfst[4]=11 cells (3 PI)
7806 23:23:17.969942 u2DelayCellOfst[5]=0 cells (0 PI)
7807 23:23:17.973242 u2DelayCellOfst[6]=22 cells (6 PI)
7808 23:23:17.976495 u2DelayCellOfst[7]=22 cells (6 PI)
7809 23:23:17.979915 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7810 23:23:17.983181 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7811 23:23:17.986356 == TX Byte 1 ==
7812 23:23:17.989841 u2DelayCellOfst[8]=0 cells (0 PI)
7813 23:23:17.992978 u2DelayCellOfst[9]=3 cells (1 PI)
7814 23:23:17.996518 u2DelayCellOfst[10]=7 cells (2 PI)
7815 23:23:17.999244 u2DelayCellOfst[11]=0 cells (0 PI)
7816 23:23:17.999344 u2DelayCellOfst[12]=11 cells (3 PI)
7817 23:23:18.002712 u2DelayCellOfst[13]=11 cells (3 PI)
7818 23:23:18.006241 u2DelayCellOfst[14]=14 cells (4 PI)
7819 23:23:18.009351 u2DelayCellOfst[15]=11 cells (3 PI)
7820 23:23:18.016295 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7821 23:23:18.018998 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7822 23:23:18.019071 DramC Write-DBI on
7823 23:23:18.022969 ==
7824 23:23:18.026278 Dram Type= 6, Freq= 0, CH_0, rank 0
7825 23:23:18.029825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7826 23:23:18.029917 ==
7827 23:23:18.030008
7828 23:23:18.030095
7829 23:23:18.032378 TX Vref Scan disable
7830 23:23:18.032452 == TX Byte 0 ==
7831 23:23:18.039086 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7832 23:23:18.039161 == TX Byte 1 ==
7833 23:23:18.042227 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7834 23:23:18.046038 DramC Write-DBI off
7835 23:23:18.046204
7836 23:23:18.046330 [DATLAT]
7837 23:23:18.048711 Freq=1600, CH0 RK0
7838 23:23:18.048813
7839 23:23:18.048902 DATLAT Default: 0xf
7840 23:23:18.052371 0, 0xFFFF, sum = 0
7841 23:23:18.052467 1, 0xFFFF, sum = 0
7842 23:23:18.056262 2, 0xFFFF, sum = 0
7843 23:23:18.056348 3, 0xFFFF, sum = 0
7844 23:23:18.059266 4, 0xFFFF, sum = 0
7845 23:23:18.062622 5, 0xFFFF, sum = 0
7846 23:23:18.062706 6, 0xFFFF, sum = 0
7847 23:23:18.065156 7, 0xFFFF, sum = 0
7848 23:23:18.065240 8, 0xFFFF, sum = 0
7849 23:23:18.068536 9, 0xFFFF, sum = 0
7850 23:23:18.068632 10, 0xFFFF, sum = 0
7851 23:23:18.072079 11, 0xFFFF, sum = 0
7852 23:23:18.072163 12, 0xFFFF, sum = 0
7853 23:23:18.075032 13, 0xFFFF, sum = 0
7854 23:23:18.075115 14, 0x0, sum = 1
7855 23:23:18.078685 15, 0x0, sum = 2
7856 23:23:18.078768 16, 0x0, sum = 3
7857 23:23:18.082057 17, 0x0, sum = 4
7858 23:23:18.082144 best_step = 15
7859 23:23:18.082208
7860 23:23:18.082268 ==
7861 23:23:18.085164 Dram Type= 6, Freq= 0, CH_0, rank 0
7862 23:23:18.091407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7863 23:23:18.091518 ==
7864 23:23:18.091631 RX Vref Scan: 1
7865 23:23:18.091734
7866 23:23:18.095026 Set Vref Range= 24 -> 127
7867 23:23:18.095108
7868 23:23:18.098037 RX Vref 24 -> 127, step: 1
7869 23:23:18.098119
7870 23:23:18.098183 RX Delay 19 -> 252, step: 4
7871 23:23:18.101866
7872 23:23:18.101948 Set Vref, RX VrefLevel [Byte0]: 24
7873 23:23:18.104459 [Byte1]: 24
7874 23:23:18.109755
7875 23:23:18.109837 Set Vref, RX VrefLevel [Byte0]: 25
7876 23:23:18.112074 [Byte1]: 25
7877 23:23:18.116659
7878 23:23:18.116740 Set Vref, RX VrefLevel [Byte0]: 26
7879 23:23:18.119995 [Byte1]: 26
7880 23:23:18.123846
7881 23:23:18.123928 Set Vref, RX VrefLevel [Byte0]: 27
7882 23:23:18.127125 [Byte1]: 27
7883 23:23:18.131841
7884 23:23:18.131922 Set Vref, RX VrefLevel [Byte0]: 28
7885 23:23:18.134897 [Byte1]: 28
7886 23:23:18.140075
7887 23:23:18.140183 Set Vref, RX VrefLevel [Byte0]: 29
7888 23:23:18.142872 [Byte1]: 29
7889 23:23:18.146636
7890 23:23:18.146718 Set Vref, RX VrefLevel [Byte0]: 30
7891 23:23:18.150258 [Byte1]: 30
7892 23:23:18.154283
7893 23:23:18.154366 Set Vref, RX VrefLevel [Byte0]: 31
7894 23:23:18.157549 [Byte1]: 31
7895 23:23:18.162055
7896 23:23:18.162138 Set Vref, RX VrefLevel [Byte0]: 32
7897 23:23:18.165396 [Byte1]: 32
7898 23:23:18.169638
7899 23:23:18.169721 Set Vref, RX VrefLevel [Byte0]: 33
7900 23:23:18.172949 [Byte1]: 33
7901 23:23:18.177137
7902 23:23:18.177220 Set Vref, RX VrefLevel [Byte0]: 34
7903 23:23:18.180499 [Byte1]: 34
7904 23:23:18.184760
7905 23:23:18.184842 Set Vref, RX VrefLevel [Byte0]: 35
7906 23:23:18.187952 [Byte1]: 35
7907 23:23:18.192072
7908 23:23:18.192198 Set Vref, RX VrefLevel [Byte0]: 36
7909 23:23:18.195361 [Byte1]: 36
7910 23:23:18.199783
7911 23:23:18.199934 Set Vref, RX VrefLevel [Byte0]: 37
7912 23:23:18.203364 [Byte1]: 37
7913 23:23:18.207156
7914 23:23:18.207232 Set Vref, RX VrefLevel [Byte0]: 38
7915 23:23:18.210675 [Byte1]: 38
7916 23:23:18.214845
7917 23:23:18.214927 Set Vref, RX VrefLevel [Byte0]: 39
7918 23:23:18.218501 [Byte1]: 39
7919 23:23:18.222758
7920 23:23:18.222832 Set Vref, RX VrefLevel [Byte0]: 40
7921 23:23:18.225654 [Byte1]: 40
7922 23:23:18.229849
7923 23:23:18.233435 Set Vref, RX VrefLevel [Byte0]: 41
7924 23:23:18.236512 [Byte1]: 41
7925 23:23:18.236618
7926 23:23:18.240066 Set Vref, RX VrefLevel [Byte0]: 42
7927 23:23:18.243287 [Byte1]: 42
7928 23:23:18.243371
7929 23:23:18.246551 Set Vref, RX VrefLevel [Byte0]: 43
7930 23:23:18.249659 [Byte1]: 43
7931 23:23:18.253442
7932 23:23:18.253519 Set Vref, RX VrefLevel [Byte0]: 44
7933 23:23:18.256447 [Byte1]: 44
7934 23:23:18.260564
7935 23:23:18.260650 Set Vref, RX VrefLevel [Byte0]: 45
7936 23:23:18.263689 [Byte1]: 45
7937 23:23:18.267848
7938 23:23:18.267922 Set Vref, RX VrefLevel [Byte0]: 46
7939 23:23:18.271652 [Byte1]: 46
7940 23:23:18.275176
7941 23:23:18.275258 Set Vref, RX VrefLevel [Byte0]: 47
7942 23:23:18.278671 [Byte1]: 47
7943 23:23:18.283330
7944 23:23:18.283403 Set Vref, RX VrefLevel [Byte0]: 48
7945 23:23:18.286412 [Byte1]: 48
7946 23:23:18.290643
7947 23:23:18.290724 Set Vref, RX VrefLevel [Byte0]: 49
7948 23:23:18.294081 [Byte1]: 49
7949 23:23:18.298721
7950 23:23:18.298800 Set Vref, RX VrefLevel [Byte0]: 50
7951 23:23:18.301318 [Byte1]: 50
7952 23:23:18.305679
7953 23:23:18.305760 Set Vref, RX VrefLevel [Byte0]: 51
7954 23:23:18.309271 [Byte1]: 51
7955 23:23:18.313565
7956 23:23:18.313637 Set Vref, RX VrefLevel [Byte0]: 52
7957 23:23:18.316916 [Byte1]: 52
7958 23:23:18.321224
7959 23:23:18.321313 Set Vref, RX VrefLevel [Byte0]: 53
7960 23:23:18.324268 [Byte1]: 53
7961 23:23:18.328845
7962 23:23:18.328924 Set Vref, RX VrefLevel [Byte0]: 54
7963 23:23:18.331867 [Byte1]: 54
7964 23:23:18.335755
7965 23:23:18.335831 Set Vref, RX VrefLevel [Byte0]: 55
7966 23:23:18.339489 [Byte1]: 55
7967 23:23:18.343832
7968 23:23:18.343906 Set Vref, RX VrefLevel [Byte0]: 56
7969 23:23:18.346868 [Byte1]: 56
7970 23:23:18.351495
7971 23:23:18.351574 Set Vref, RX VrefLevel [Byte0]: 57
7972 23:23:18.354526 [Byte1]: 57
7973 23:23:18.358669
7974 23:23:18.358747 Set Vref, RX VrefLevel [Byte0]: 58
7975 23:23:18.365120 [Byte1]: 58
7976 23:23:18.365205
7977 23:23:18.368490 Set Vref, RX VrefLevel [Byte0]: 59
7978 23:23:18.371812 [Byte1]: 59
7979 23:23:18.371897
7980 23:23:18.375071 Set Vref, RX VrefLevel [Byte0]: 60
7981 23:23:18.378260 [Byte1]: 60
7982 23:23:18.378417
7983 23:23:18.381688 Set Vref, RX VrefLevel [Byte0]: 61
7984 23:23:18.384844 [Byte1]: 61
7985 23:23:18.389024
7986 23:23:18.389108 Set Vref, RX VrefLevel [Byte0]: 62
7987 23:23:18.392484 [Byte1]: 62
7988 23:23:18.396910
7989 23:23:18.397007 Set Vref, RX VrefLevel [Byte0]: 63
7990 23:23:18.399894 [Byte1]: 63
7991 23:23:18.404411
7992 23:23:18.404486 Set Vref, RX VrefLevel [Byte0]: 64
7993 23:23:18.407617 [Byte1]: 64
7994 23:23:18.411994
7995 23:23:18.412111 Set Vref, RX VrefLevel [Byte0]: 65
7996 23:23:18.415150 [Byte1]: 65
7997 23:23:18.419299
7998 23:23:18.419379 Set Vref, RX VrefLevel [Byte0]: 66
7999 23:23:18.422446 [Byte1]: 66
8000 23:23:18.426868
8001 23:23:18.426948 Set Vref, RX VrefLevel [Byte0]: 67
8002 23:23:18.430172 [Byte1]: 67
8003 23:23:18.434477
8004 23:23:18.434554 Set Vref, RX VrefLevel [Byte0]: 68
8005 23:23:18.437750 [Byte1]: 68
8006 23:23:18.442302
8007 23:23:18.442378 Set Vref, RX VrefLevel [Byte0]: 69
8008 23:23:18.445425 [Byte1]: 69
8009 23:23:18.449678
8010 23:23:18.449752 Set Vref, RX VrefLevel [Byte0]: 70
8011 23:23:18.452749 [Byte1]: 70
8012 23:23:18.457618
8013 23:23:18.457692 Set Vref, RX VrefLevel [Byte0]: 71
8014 23:23:18.463774 [Byte1]: 71
8015 23:23:18.463852
8016 23:23:18.467014 Set Vref, RX VrefLevel [Byte0]: 72
8017 23:23:18.470885 [Byte1]: 72
8018 23:23:18.470962
8019 23:23:18.473425 Set Vref, RX VrefLevel [Byte0]: 73
8020 23:23:18.476859 [Byte1]: 73
8021 23:23:18.480123
8022 23:23:18.480217 Set Vref, RX VrefLevel [Byte0]: 74
8023 23:23:18.483456 [Byte1]: 74
8024 23:23:18.487565
8025 23:23:18.487677 Set Vref, RX VrefLevel [Byte0]: 75
8026 23:23:18.490533 [Byte1]: 75
8027 23:23:18.495375
8028 23:23:18.495458 Set Vref, RX VrefLevel [Byte0]: 76
8029 23:23:18.498219 [Byte1]: 76
8030 23:23:18.502346
8031 23:23:18.502423 Set Vref, RX VrefLevel [Byte0]: 77
8032 23:23:18.505769 [Byte1]: 77
8033 23:23:18.510148
8034 23:23:18.510225 Set Vref, RX VrefLevel [Byte0]: 78
8035 23:23:18.513515 [Byte1]: 78
8036 23:23:18.517754
8037 23:23:18.517828 Set Vref, RX VrefLevel [Byte0]: 79
8038 23:23:18.521084 [Byte1]: 79
8039 23:23:18.525238
8040 23:23:18.525321 Final RX Vref Byte 0 = 62 to rank0
8041 23:23:18.528331 Final RX Vref Byte 1 = 62 to rank0
8042 23:23:18.532051 Final RX Vref Byte 0 = 62 to rank1
8043 23:23:18.535099 Final RX Vref Byte 1 = 62 to rank1==
8044 23:23:18.538277 Dram Type= 6, Freq= 0, CH_0, rank 0
8045 23:23:18.545001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 23:23:18.545081 ==
8047 23:23:18.545147 DQS Delay:
8048 23:23:18.548827 DQS0 = 0, DQS1 = 0
8049 23:23:18.548907 DQM Delay:
8050 23:23:18.548970 DQM0 = 132, DQM1 = 123
8051 23:23:18.551828 DQ Delay:
8052 23:23:18.555168 DQ0 =130, DQ1 =132, DQ2 =128, DQ3 =130
8053 23:23:18.558228 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
8054 23:23:18.561669 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8055 23:23:18.564985 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
8056 23:23:18.565058
8057 23:23:18.565120
8058 23:23:18.565179
8059 23:23:18.568121 [DramC_TX_OE_Calibration] TA2
8060 23:23:18.571440 Original DQ_B0 (3 6) =30, OEN = 27
8061 23:23:18.574619 Original DQ_B1 (3 6) =30, OEN = 27
8062 23:23:18.578163 24, 0x0, End_B0=24 End_B1=24
8063 23:23:18.581014 25, 0x0, End_B0=25 End_B1=25
8064 23:23:18.581088 26, 0x0, End_B0=26 End_B1=26
8065 23:23:18.585009 27, 0x0, End_B0=27 End_B1=27
8066 23:23:18.588456 28, 0x0, End_B0=28 End_B1=28
8067 23:23:18.591058 29, 0x0, End_B0=29 End_B1=29
8068 23:23:18.591140 30, 0x0, End_B0=30 End_B1=30
8069 23:23:18.594402 31, 0x4141, End_B0=30 End_B1=30
8070 23:23:18.597447 Byte0 end_step=30 best_step=27
8071 23:23:18.601326 Byte1 end_step=30 best_step=27
8072 23:23:18.604821 Byte0 TX OE(2T, 0.5T) = (3, 3)
8073 23:23:18.607730 Byte1 TX OE(2T, 0.5T) = (3, 3)
8074 23:23:18.607811
8075 23:23:18.607876
8076 23:23:18.614679 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8077 23:23:18.617406 CH0 RK0: MR19=303, MR18=2112
8078 23:23:18.624608 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8079 23:23:18.624701
8080 23:23:18.627512 ----->DramcWriteLeveling(PI) begin...
8081 23:23:18.627612 ==
8082 23:23:18.631107 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 23:23:18.634023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 23:23:18.634098 ==
8085 23:23:18.637364 Write leveling (Byte 0): 33 => 33
8086 23:23:18.640853 Write leveling (Byte 1): 29 => 29
8087 23:23:18.643806 DramcWriteLeveling(PI) end<-----
8088 23:23:18.643882
8089 23:23:18.643951 ==
8090 23:23:18.647408 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 23:23:18.650848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 23:23:18.653986 ==
8093 23:23:18.654060 [Gating] SW mode calibration
8094 23:23:18.663801 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8095 23:23:18.667096 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8096 23:23:18.670476 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 23:23:18.677279 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 23:23:18.680193 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 23:23:18.683248 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8100 23:23:18.690515 1 4 16 | B1->B0 | 2423 3232 | 1 1 | (0 0) (1 1)
8101 23:23:18.693551 1 4 20 | B1->B0 | 2e2d 3434 | 1 1 | (0 0) (1 1)
8102 23:23:18.696395 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8103 23:23:18.703087 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8104 23:23:18.706394 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8105 23:23:18.709971 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8106 23:23:18.716181 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8107 23:23:18.719983 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8108 23:23:18.722972 1 5 16 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
8109 23:23:18.729829 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8110 23:23:18.732970 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 23:23:18.736173 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 23:23:18.743124 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 23:23:18.746607 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 23:23:18.749653 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 23:23:18.756141 1 6 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8116 23:23:18.759756 1 6 16 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8117 23:23:18.762867 1 6 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8118 23:23:18.769008 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8119 23:23:18.772379 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8120 23:23:18.775965 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 23:23:18.782379 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 23:23:18.786266 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 23:23:18.788881 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8124 23:23:18.795498 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8125 23:23:18.799068 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8126 23:23:18.802083 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 23:23:18.809284 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 23:23:18.812199 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 23:23:18.815497 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 23:23:18.821989 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 23:23:18.825507 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 23:23:18.828470 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 23:23:18.835489 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 23:23:18.838686 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 23:23:18.842207 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 23:23:18.848622 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 23:23:18.851493 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 23:23:18.855330 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 23:23:18.861826 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8140 23:23:18.865375 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8141 23:23:18.867970 Total UI for P1: 0, mck2ui 16
8142 23:23:18.871563 best dqsien dly found for B0: ( 1, 9, 12)
8143 23:23:18.874671 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8144 23:23:18.881760 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8145 23:23:18.885057 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 23:23:18.887964 Total UI for P1: 0, mck2ui 16
8147 23:23:18.891302 best dqsien dly found for B1: ( 1, 9, 20)
8148 23:23:18.894322 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8149 23:23:18.897575 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8150 23:23:18.897651
8151 23:23:18.901346 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8152 23:23:18.907523 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8153 23:23:18.907635 [Gating] SW calibration Done
8154 23:23:18.907729 ==
8155 23:23:18.910964 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 23:23:18.917477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 23:23:18.917591 ==
8158 23:23:18.917709 RX Vref Scan: 0
8159 23:23:18.917807
8160 23:23:18.921120 RX Vref 0 -> 0, step: 1
8161 23:23:18.921198
8162 23:23:18.924470 RX Delay 0 -> 252, step: 8
8163 23:23:18.927202 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8164 23:23:18.931031 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8165 23:23:18.933940 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8166 23:23:18.940647 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8167 23:23:18.944398 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8168 23:23:18.947402 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8169 23:23:18.950964 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8170 23:23:18.953850 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8171 23:23:18.960637 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8172 23:23:18.963926 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8173 23:23:18.966850 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8174 23:23:18.970041 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8175 23:23:18.973739 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8176 23:23:18.980098 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8177 23:23:18.983468 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8178 23:23:18.986659 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8179 23:23:18.986746 ==
8180 23:23:18.990256 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 23:23:18.994056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 23:23:18.996823 ==
8183 23:23:18.996908 DQS Delay:
8184 23:23:18.996974 DQS0 = 0, DQS1 = 0
8185 23:23:19.000183 DQM Delay:
8186 23:23:19.000266 DQM0 = 133, DQM1 = 127
8187 23:23:19.003192 DQ Delay:
8188 23:23:19.006873 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8189 23:23:19.009822 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8190 23:23:19.013680 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8191 23:23:19.016763 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8192 23:23:19.016907
8193 23:23:19.017022
8194 23:23:19.017124 ==
8195 23:23:19.020391 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 23:23:19.022983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 23:23:19.026706 ==
8198 23:23:19.026802
8199 23:23:19.026899
8200 23:23:19.027012 TX Vref Scan disable
8201 23:23:19.029699 == TX Byte 0 ==
8202 23:23:19.033026 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8203 23:23:19.036413 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8204 23:23:19.039960 == TX Byte 1 ==
8205 23:23:19.043266 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8206 23:23:19.046023 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8207 23:23:19.049862 ==
8208 23:23:19.049938 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 23:23:19.055791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 23:23:19.055873 ==
8211 23:23:19.067118
8212 23:23:19.070524 TX Vref early break, caculate TX vref
8213 23:23:19.074074 TX Vref=16, minBit 1, minWin=22, winSum=380
8214 23:23:19.077075 TX Vref=18, minBit 2, minWin=23, winSum=389
8215 23:23:19.080562 TX Vref=20, minBit 7, minWin=23, winSum=396
8216 23:23:19.083355 TX Vref=22, minBit 1, minWin=24, winSum=407
8217 23:23:19.087209 TX Vref=24, minBit 0, minWin=24, winSum=411
8218 23:23:19.093552 TX Vref=26, minBit 1, minWin=25, winSum=419
8219 23:23:19.096863 TX Vref=28, minBit 1, minWin=25, winSum=417
8220 23:23:19.100257 TX Vref=30, minBit 1, minWin=24, winSum=406
8221 23:23:19.103265 TX Vref=32, minBit 1, minWin=23, winSum=397
8222 23:23:19.109872 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 26
8223 23:23:19.109986
8224 23:23:19.113561 Final TX Range 0 Vref 26
8225 23:23:19.113635
8226 23:23:19.113706 ==
8227 23:23:19.116293 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 23:23:19.119587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 23:23:19.119724 ==
8230 23:23:19.119858
8231 23:23:19.119923
8232 23:23:19.123461 TX Vref Scan disable
8233 23:23:19.130098 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8234 23:23:19.130176 == TX Byte 0 ==
8235 23:23:19.133117 u2DelayCellOfst[0]=11 cells (3 PI)
8236 23:23:19.136469 u2DelayCellOfst[1]=18 cells (5 PI)
8237 23:23:19.141187 u2DelayCellOfst[2]=11 cells (3 PI)
8238 23:23:19.143176 u2DelayCellOfst[3]=14 cells (4 PI)
8239 23:23:19.146793 u2DelayCellOfst[4]=7 cells (2 PI)
8240 23:23:19.149627 u2DelayCellOfst[5]=0 cells (0 PI)
8241 23:23:19.153367 u2DelayCellOfst[6]=14 cells (4 PI)
8242 23:23:19.156357 u2DelayCellOfst[7]=18 cells (5 PI)
8243 23:23:19.159394 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8244 23:23:19.162651 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8245 23:23:19.166353 == TX Byte 1 ==
8246 23:23:19.166428 u2DelayCellOfst[8]=0 cells (0 PI)
8247 23:23:19.169390 u2DelayCellOfst[9]=3 cells (1 PI)
8248 23:23:19.172679 u2DelayCellOfst[10]=11 cells (3 PI)
8249 23:23:19.175958 u2DelayCellOfst[11]=3 cells (1 PI)
8250 23:23:19.179159 u2DelayCellOfst[12]=14 cells (4 PI)
8251 23:23:19.182998 u2DelayCellOfst[13]=14 cells (4 PI)
8252 23:23:19.185990 u2DelayCellOfst[14]=18 cells (5 PI)
8253 23:23:19.189371 u2DelayCellOfst[15]=14 cells (4 PI)
8254 23:23:19.192566 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8255 23:23:19.199379 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8256 23:23:19.199461 DramC Write-DBI on
8257 23:23:19.199527 ==
8258 23:23:19.202441 Dram Type= 6, Freq= 0, CH_0, rank 1
8259 23:23:19.209210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 23:23:19.209293 ==
8261 23:23:19.209357
8262 23:23:19.209417
8263 23:23:19.209475 TX Vref Scan disable
8264 23:23:19.213118 == TX Byte 0 ==
8265 23:23:19.216337 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8266 23:23:19.219900 == TX Byte 1 ==
8267 23:23:19.222774 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8268 23:23:19.225954 DramC Write-DBI off
8269 23:23:19.226036
8270 23:23:19.226100 [DATLAT]
8271 23:23:19.226160 Freq=1600, CH0 RK1
8272 23:23:19.226220
8273 23:23:19.229243 DATLAT Default: 0xf
8274 23:23:19.232860 0, 0xFFFF, sum = 0
8275 23:23:19.232943 1, 0xFFFF, sum = 0
8276 23:23:19.235578 2, 0xFFFF, sum = 0
8277 23:23:19.235706 3, 0xFFFF, sum = 0
8278 23:23:19.239349 4, 0xFFFF, sum = 0
8279 23:23:19.239433 5, 0xFFFF, sum = 0
8280 23:23:19.243216 6, 0xFFFF, sum = 0
8281 23:23:19.243325 7, 0xFFFF, sum = 0
8282 23:23:19.245807 8, 0xFFFF, sum = 0
8283 23:23:19.245911 9, 0xFFFF, sum = 0
8284 23:23:19.249417 10, 0xFFFF, sum = 0
8285 23:23:19.249500 11, 0xFFFF, sum = 0
8286 23:23:19.251903 12, 0xFFFF, sum = 0
8287 23:23:19.251986 13, 0xFFFF, sum = 0
8288 23:23:19.255453 14, 0x0, sum = 1
8289 23:23:19.255536 15, 0x0, sum = 2
8290 23:23:19.258514 16, 0x0, sum = 3
8291 23:23:19.258623 17, 0x0, sum = 4
8292 23:23:19.262233 best_step = 15
8293 23:23:19.262334
8294 23:23:19.262423 ==
8295 23:23:19.265328 Dram Type= 6, Freq= 0, CH_0, rank 1
8296 23:23:19.268718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 23:23:19.268842 ==
8298 23:23:19.272150 RX Vref Scan: 0
8299 23:23:19.272231
8300 23:23:19.272296 RX Vref 0 -> 0, step: 1
8301 23:23:19.272356
8302 23:23:19.275191 RX Delay 11 -> 252, step: 4
8303 23:23:19.282158 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8304 23:23:19.284720 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8305 23:23:19.288479 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8306 23:23:19.292097 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8307 23:23:19.298123 iDelay=195, Bit 4, Center 132 (83 ~ 182) 100
8308 23:23:19.301356 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8309 23:23:19.305202 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8310 23:23:19.307842 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8311 23:23:19.311549 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8312 23:23:19.317590 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8313 23:23:19.321107 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8314 23:23:19.324174 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8315 23:23:19.328183 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8316 23:23:19.334086 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8317 23:23:19.337756 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8318 23:23:19.340832 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8319 23:23:19.340914 ==
8320 23:23:19.344288 Dram Type= 6, Freq= 0, CH_0, rank 1
8321 23:23:19.347489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 23:23:19.347601 ==
8323 23:23:19.350739 DQS Delay:
8324 23:23:19.350820 DQS0 = 0, DQS1 = 0
8325 23:23:19.354065 DQM Delay:
8326 23:23:19.354146 DQM0 = 130, DQM1 = 125
8327 23:23:19.356972 DQ Delay:
8328 23:23:19.360453 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8329 23:23:19.363842 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =138
8330 23:23:19.366956 DQ8 =116, DQ9 =112, DQ10 =128, DQ11 =120
8331 23:23:19.370503 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8332 23:23:19.370585
8333 23:23:19.370649
8334 23:23:19.370709
8335 23:23:19.373548 [DramC_TX_OE_Calibration] TA2
8336 23:23:19.376768 Original DQ_B0 (3 6) =30, OEN = 27
8337 23:23:19.380317 Original DQ_B1 (3 6) =30, OEN = 27
8338 23:23:19.380403 24, 0x0, End_B0=24 End_B1=24
8339 23:23:19.383562 25, 0x0, End_B0=25 End_B1=25
8340 23:23:19.387091 26, 0x0, End_B0=26 End_B1=26
8341 23:23:19.390031 27, 0x0, End_B0=27 End_B1=27
8342 23:23:19.393255 28, 0x0, End_B0=28 End_B1=28
8343 23:23:19.393339 29, 0x0, End_B0=29 End_B1=29
8344 23:23:19.396814 30, 0x0, End_B0=30 End_B1=30
8345 23:23:19.400121 31, 0x4141, End_B0=30 End_B1=30
8346 23:23:19.403303 Byte0 end_step=30 best_step=27
8347 23:23:19.406659 Byte1 end_step=30 best_step=27
8348 23:23:19.410008 Byte0 TX OE(2T, 0.5T) = (3, 3)
8349 23:23:19.410086 Byte1 TX OE(2T, 0.5T) = (3, 3)
8350 23:23:19.413289
8351 23:23:19.413362
8352 23:23:19.419899 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8353 23:23:19.423303 CH0 RK1: MR19=303, MR18=1E01
8354 23:23:19.429640 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8355 23:23:19.433133 [RxdqsGatingPostProcess] freq 1600
8356 23:23:19.436715 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8357 23:23:19.439958 best DQS0 dly(2T, 0.5T) = (1, 1)
8358 23:23:19.442698 best DQS1 dly(2T, 0.5T) = (1, 1)
8359 23:23:19.446629 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8360 23:23:19.449542 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8361 23:23:19.452816 best DQS0 dly(2T, 0.5T) = (1, 1)
8362 23:23:19.455956 best DQS1 dly(2T, 0.5T) = (1, 1)
8363 23:23:19.459235 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8364 23:23:19.462496 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8365 23:23:19.466155 Pre-setting of DQS Precalculation
8366 23:23:19.469691 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8367 23:23:19.469857 ==
8368 23:23:19.472442 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 23:23:19.475873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 23:23:19.478934 ==
8371 23:23:19.482540 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8372 23:23:19.485728 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8373 23:23:19.492497 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8374 23:23:19.499031 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8375 23:23:19.506450 [CA 0] Center 41 (12~70) winsize 59
8376 23:23:19.509396 [CA 1] Center 41 (12~71) winsize 60
8377 23:23:19.512374 [CA 2] Center 37 (8~66) winsize 59
8378 23:23:19.516368 [CA 3] Center 36 (7~66) winsize 60
8379 23:23:19.519191 [CA 4] Center 37 (7~67) winsize 61
8380 23:23:19.522613 [CA 5] Center 36 (7~65) winsize 59
8381 23:23:19.522695
8382 23:23:19.525834 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8383 23:23:19.525916
8384 23:23:19.532728 [CATrainingPosCal] consider 1 rank data
8385 23:23:19.532809 u2DelayCellTimex100 = 262/100 ps
8386 23:23:19.538978 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8387 23:23:19.542601 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8388 23:23:19.545772 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8389 23:23:19.548723 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8390 23:23:19.552449 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8391 23:23:19.555609 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8392 23:23:19.555711
8393 23:23:19.558741 CA PerBit enable=1, Macro0, CA PI delay=36
8394 23:23:19.558822
8395 23:23:19.562056 [CBTSetCACLKResult] CA Dly = 36
8396 23:23:19.565720 CS Dly: 8 (0~39)
8397 23:23:19.568572 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8398 23:23:19.571906 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8399 23:23:19.571988 ==
8400 23:23:19.575352 Dram Type= 6, Freq= 0, CH_1, rank 1
8401 23:23:19.582043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 23:23:19.582127 ==
8403 23:23:19.585206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8404 23:23:19.591632 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8405 23:23:19.594999 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8406 23:23:19.601543 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8407 23:23:19.609403 [CA 0] Center 43 (14~72) winsize 59
8408 23:23:19.612627 [CA 1] Center 42 (13~72) winsize 60
8409 23:23:19.616112 [CA 2] Center 37 (8~67) winsize 60
8410 23:23:19.619182 [CA 3] Center 37 (8~67) winsize 60
8411 23:23:19.622437 [CA 4] Center 37 (8~67) winsize 60
8412 23:23:19.625755 [CA 5] Center 37 (8~67) winsize 60
8413 23:23:19.625856
8414 23:23:19.629087 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8415 23:23:19.629187
8416 23:23:19.632339 [CATrainingPosCal] consider 2 rank data
8417 23:23:19.636184 u2DelayCellTimex100 = 262/100 ps
8418 23:23:19.642236 CA0 delay=42 (14~70),Diff = 6 PI (22 cell)
8419 23:23:19.645336 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8420 23:23:19.648603 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8421 23:23:19.651974 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8422 23:23:19.655249 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8423 23:23:19.658731 CA5 delay=36 (8~65),Diff = 0 PI (0 cell)
8424 23:23:19.658808
8425 23:23:19.661795 CA PerBit enable=1, Macro0, CA PI delay=36
8426 23:23:19.661871
8427 23:23:19.665031 [CBTSetCACLKResult] CA Dly = 36
8428 23:23:19.668692 CS Dly: 10 (0~44)
8429 23:23:19.671876 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8430 23:23:19.675198 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8431 23:23:19.675274
8432 23:23:19.678729 ----->DramcWriteLeveling(PI) begin...
8433 23:23:19.678805 ==
8434 23:23:19.681899 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 23:23:19.688379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 23:23:19.688469 ==
8437 23:23:19.691391 Write leveling (Byte 0): 23 => 23
8438 23:23:19.695024 Write leveling (Byte 1): 26 => 26
8439 23:23:19.695127 DramcWriteLeveling(PI) end<-----
8440 23:23:19.698086
8441 23:23:19.698188 ==
8442 23:23:19.701593 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 23:23:19.704632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 23:23:19.704736 ==
8445 23:23:19.708210 [Gating] SW mode calibration
8446 23:23:19.714915 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8447 23:23:19.718485 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8448 23:23:19.724733 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 23:23:19.728580 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 23:23:19.731215 1 4 8 | B1->B0 | 2323 2525 | 1 0 | (0 0) (0 0)
8451 23:23:19.738009 1 4 12 | B1->B0 | 2929 3433 | 0 1 | (0 0) (0 0)
8452 23:23:19.741566 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 23:23:19.744474 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8454 23:23:19.751306 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8455 23:23:19.754483 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8456 23:23:19.757466 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8457 23:23:19.764655 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8458 23:23:19.767424 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8459 23:23:19.771239 1 5 12 | B1->B0 | 2f2f 2626 | 0 0 | (1 0) (1 0)
8460 23:23:19.777608 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8461 23:23:19.780921 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 23:23:19.784121 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 23:23:19.790686 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 23:23:19.793938 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 23:23:19.797568 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 23:23:19.804140 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8467 23:23:19.807253 1 6 12 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
8468 23:23:19.810371 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 23:23:19.817111 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 23:23:19.820806 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 23:23:19.823480 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 23:23:19.830350 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8473 23:23:19.833388 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8474 23:23:19.837290 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8475 23:23:19.843579 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8476 23:23:19.847096 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8477 23:23:19.850289 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 23:23:19.856681 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 23:23:19.860392 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 23:23:19.863218 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 23:23:19.869981 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 23:23:19.872922 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 23:23:19.876290 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 23:23:19.883511 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 23:23:19.886041 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 23:23:19.889187 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 23:23:19.895864 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 23:23:19.899575 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 23:23:19.902543 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 23:23:19.909072 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8491 23:23:19.912516 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8492 23:23:19.915636 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8493 23:23:19.919484 Total UI for P1: 0, mck2ui 16
8494 23:23:19.922576 best dqsien dly found for B0: ( 1, 9, 10)
8495 23:23:19.929092 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 23:23:19.932405 Total UI for P1: 0, mck2ui 16
8497 23:23:19.935549 best dqsien dly found for B1: ( 1, 9, 12)
8498 23:23:19.938852 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8499 23:23:19.942184 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8500 23:23:19.942256
8501 23:23:19.945608 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8502 23:23:19.948671 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8503 23:23:19.951971 [Gating] SW calibration Done
8504 23:23:19.952040 ==
8505 23:23:19.954948 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 23:23:19.958911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 23:23:19.958990 ==
8508 23:23:19.961663 RX Vref Scan: 0
8509 23:23:19.961739
8510 23:23:19.965264 RX Vref 0 -> 0, step: 1
8511 23:23:19.965341
8512 23:23:19.965403 RX Delay 0 -> 252, step: 8
8513 23:23:19.971903 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8514 23:23:19.974820 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8515 23:23:19.978730 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8516 23:23:19.981791 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8517 23:23:19.985292 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8518 23:23:19.991605 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8519 23:23:19.995173 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8520 23:23:19.998050 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8521 23:23:20.001390 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8522 23:23:20.004808 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8523 23:23:20.011387 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8524 23:23:20.014664 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8525 23:23:20.017607 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8526 23:23:20.021253 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8527 23:23:20.027566 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8528 23:23:20.031122 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8529 23:23:20.031202 ==
8530 23:23:20.034344 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 23:23:20.037379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 23:23:20.037462 ==
8533 23:23:20.041096 DQS Delay:
8534 23:23:20.041177 DQS0 = 0, DQS1 = 0
8535 23:23:20.041249 DQM Delay:
8536 23:23:20.044111 DQM0 = 138, DQM1 = 128
8537 23:23:20.044190 DQ Delay:
8538 23:23:20.047850 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8539 23:23:20.050769 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8540 23:23:20.057656 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8541 23:23:20.060825 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8542 23:23:20.060935
8543 23:23:20.061001
8544 23:23:20.061061 ==
8545 23:23:20.063964 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 23:23:20.067453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 23:23:20.067560 ==
8548 23:23:20.067651
8549 23:23:20.067765
8550 23:23:20.070760 TX Vref Scan disable
8551 23:23:20.073944 == TX Byte 0 ==
8552 23:23:20.076791 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8553 23:23:20.080176 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8554 23:23:20.083601 == TX Byte 1 ==
8555 23:23:20.086852 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8556 23:23:20.090353 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8557 23:23:20.090433 ==
8558 23:23:20.093325 Dram Type= 6, Freq= 0, CH_1, rank 0
8559 23:23:20.100531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8560 23:23:20.100613 ==
8561 23:23:20.112856
8562 23:23:20.115452 TX Vref early break, caculate TX vref
8563 23:23:20.119270 TX Vref=16, minBit 0, minWin=20, winSum=371
8564 23:23:20.122424 TX Vref=18, minBit 6, minWin=22, winSum=386
8565 23:23:20.125895 TX Vref=20, minBit 5, minWin=22, winSum=393
8566 23:23:20.128578 TX Vref=22, minBit 0, minWin=23, winSum=402
8567 23:23:20.132120 TX Vref=24, minBit 0, minWin=24, winSum=411
8568 23:23:20.139066 TX Vref=26, minBit 5, minWin=24, winSum=415
8569 23:23:20.141662 TX Vref=28, minBit 0, minWin=24, winSum=416
8570 23:23:20.145221 TX Vref=30, minBit 1, minWin=24, winSum=412
8571 23:23:20.148480 TX Vref=32, minBit 0, minWin=23, winSum=401
8572 23:23:20.151944 TX Vref=34, minBit 0, minWin=23, winSum=397
8573 23:23:20.158216 TX Vref=36, minBit 0, minWin=22, winSum=377
8574 23:23:20.161673 [TxChooseVref] Worse bit 0, Min win 24, Win sum 416, Final Vref 28
8575 23:23:20.161750
8576 23:23:20.164724 Final TX Range 0 Vref 28
8577 23:23:20.164798
8578 23:23:20.164869 ==
8579 23:23:20.168382 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 23:23:20.171345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 23:23:20.174636 ==
8582 23:23:20.174718
8583 23:23:20.174781
8584 23:23:20.174839 TX Vref Scan disable
8585 23:23:20.181595 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8586 23:23:20.181672 == TX Byte 0 ==
8587 23:23:20.184998 u2DelayCellOfst[0]=18 cells (5 PI)
8588 23:23:20.188513 u2DelayCellOfst[1]=11 cells (3 PI)
8589 23:23:20.191546 u2DelayCellOfst[2]=0 cells (0 PI)
8590 23:23:20.195151 u2DelayCellOfst[3]=7 cells (2 PI)
8591 23:23:20.199360 u2DelayCellOfst[4]=7 cells (2 PI)
8592 23:23:20.201822 u2DelayCellOfst[5]=18 cells (5 PI)
8593 23:23:20.204845 u2DelayCellOfst[6]=18 cells (5 PI)
8594 23:23:20.208094 u2DelayCellOfst[7]=3 cells (1 PI)
8595 23:23:20.211381 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8596 23:23:20.214783 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8597 23:23:20.217821 == TX Byte 1 ==
8598 23:23:20.221031 u2DelayCellOfst[8]=0 cells (0 PI)
8599 23:23:20.224657 u2DelayCellOfst[9]=3 cells (1 PI)
8600 23:23:20.227786 u2DelayCellOfst[10]=11 cells (3 PI)
8601 23:23:20.231274 u2DelayCellOfst[11]=3 cells (1 PI)
8602 23:23:20.234177 u2DelayCellOfst[12]=14 cells (4 PI)
8603 23:23:20.237450 u2DelayCellOfst[13]=18 cells (5 PI)
8604 23:23:20.240681 u2DelayCellOfst[14]=18 cells (5 PI)
8605 23:23:20.244094 u2DelayCellOfst[15]=22 cells (6 PI)
8606 23:23:20.247581 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8607 23:23:20.251103 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8608 23:23:20.254450 DramC Write-DBI on
8609 23:23:20.254551 ==
8610 23:23:20.257201 Dram Type= 6, Freq= 0, CH_1, rank 0
8611 23:23:20.260583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8612 23:23:20.260658 ==
8613 23:23:20.260728
8614 23:23:20.260786
8615 23:23:20.263855 TX Vref Scan disable
8616 23:23:20.263925 == TX Byte 0 ==
8617 23:23:20.270980 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8618 23:23:20.271060 == TX Byte 1 ==
8619 23:23:20.274151 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8620 23:23:20.277419 DramC Write-DBI off
8621 23:23:20.277504
8622 23:23:20.277568 [DATLAT]
8623 23:23:20.280565 Freq=1600, CH1 RK0
8624 23:23:20.280635
8625 23:23:20.280695 DATLAT Default: 0xf
8626 23:23:20.284178 0, 0xFFFF, sum = 0
8627 23:23:20.287330 1, 0xFFFF, sum = 0
8628 23:23:20.287411 2, 0xFFFF, sum = 0
8629 23:23:20.290846 3, 0xFFFF, sum = 0
8630 23:23:20.290926 4, 0xFFFF, sum = 0
8631 23:23:20.293841 5, 0xFFFF, sum = 0
8632 23:23:20.293930 6, 0xFFFF, sum = 0
8633 23:23:20.296917 7, 0xFFFF, sum = 0
8634 23:23:20.297002 8, 0xFFFF, sum = 0
8635 23:23:20.300271 9, 0xFFFF, sum = 0
8636 23:23:20.300360 10, 0xFFFF, sum = 0
8637 23:23:20.303614 11, 0xFFFF, sum = 0
8638 23:23:20.303750 12, 0xFFFF, sum = 0
8639 23:23:20.306693 13, 0xFFFF, sum = 0
8640 23:23:20.306805 14, 0x0, sum = 1
8641 23:23:20.310387 15, 0x0, sum = 2
8642 23:23:20.310469 16, 0x0, sum = 3
8643 23:23:20.313768 17, 0x0, sum = 4
8644 23:23:20.313851 best_step = 15
8645 23:23:20.313916
8646 23:23:20.313976 ==
8647 23:23:20.317150 Dram Type= 6, Freq= 0, CH_1, rank 0
8648 23:23:20.323181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8649 23:23:20.323288 ==
8650 23:23:20.323381 RX Vref Scan: 1
8651 23:23:20.323470
8652 23:23:20.326389 Set Vref Range= 24 -> 127
8653 23:23:20.326509
8654 23:23:20.330273 RX Vref 24 -> 127, step: 1
8655 23:23:20.330354
8656 23:23:20.330418 RX Delay 11 -> 252, step: 4
8657 23:23:20.332959
8658 23:23:20.333066 Set Vref, RX VrefLevel [Byte0]: 24
8659 23:23:20.336890 [Byte1]: 24
8660 23:23:20.340748
8661 23:23:20.343572 Set Vref, RX VrefLevel [Byte0]: 25
8662 23:23:20.346976 [Byte1]: 25
8663 23:23:20.347057
8664 23:23:20.350443 Set Vref, RX VrefLevel [Byte0]: 26
8665 23:23:20.353667 [Byte1]: 26
8666 23:23:20.353748
8667 23:23:20.357260 Set Vref, RX VrefLevel [Byte0]: 27
8668 23:23:20.360379 [Byte1]: 27
8669 23:23:20.363602
8670 23:23:20.363712 Set Vref, RX VrefLevel [Byte0]: 28
8671 23:23:20.367087 [Byte1]: 28
8672 23:23:20.371567
8673 23:23:20.371663 Set Vref, RX VrefLevel [Byte0]: 29
8674 23:23:20.374859 [Byte1]: 29
8675 23:23:20.379125
8676 23:23:20.379206 Set Vref, RX VrefLevel [Byte0]: 30
8677 23:23:20.381871 [Byte1]: 30
8678 23:23:20.386570
8679 23:23:20.386651 Set Vref, RX VrefLevel [Byte0]: 31
8680 23:23:20.389808 [Byte1]: 31
8681 23:23:20.394090
8682 23:23:20.394170 Set Vref, RX VrefLevel [Byte0]: 32
8683 23:23:20.397488 [Byte1]: 32
8684 23:23:20.402033
8685 23:23:20.402113 Set Vref, RX VrefLevel [Byte0]: 33
8686 23:23:20.405428 [Byte1]: 33
8687 23:23:20.409450
8688 23:23:20.409531 Set Vref, RX VrefLevel [Byte0]: 34
8689 23:23:20.412885 [Byte1]: 34
8690 23:23:20.417011
8691 23:23:20.417091 Set Vref, RX VrefLevel [Byte0]: 35
8692 23:23:20.419861 [Byte1]: 35
8693 23:23:20.424327
8694 23:23:20.424437 Set Vref, RX VrefLevel [Byte0]: 36
8695 23:23:20.427801 [Byte1]: 36
8696 23:23:20.431857
8697 23:23:20.431938 Set Vref, RX VrefLevel [Byte0]: 37
8698 23:23:20.435457 [Byte1]: 37
8699 23:23:20.439759
8700 23:23:20.439863 Set Vref, RX VrefLevel [Byte0]: 38
8701 23:23:20.443084 [Byte1]: 38
8702 23:23:20.447496
8703 23:23:20.447606 Set Vref, RX VrefLevel [Byte0]: 39
8704 23:23:20.450837 [Byte1]: 39
8705 23:23:20.455409
8706 23:23:20.455518 Set Vref, RX VrefLevel [Byte0]: 40
8707 23:23:20.458176 [Byte1]: 40
8708 23:23:20.462502
8709 23:23:20.462583 Set Vref, RX VrefLevel [Byte0]: 41
8710 23:23:20.465811 [Byte1]: 41
8711 23:23:20.469904
8712 23:23:20.469984 Set Vref, RX VrefLevel [Byte0]: 42
8713 23:23:20.473495 [Byte1]: 42
8714 23:23:20.478082
8715 23:23:20.478163 Set Vref, RX VrefLevel [Byte0]: 43
8716 23:23:20.481385 [Byte1]: 43
8717 23:23:20.485409
8718 23:23:20.485490 Set Vref, RX VrefLevel [Byte0]: 44
8719 23:23:20.488836 [Byte1]: 44
8720 23:23:20.493087
8721 23:23:20.493168 Set Vref, RX VrefLevel [Byte0]: 45
8722 23:23:20.496250 [Byte1]: 45
8723 23:23:20.500677
8724 23:23:20.500757 Set Vref, RX VrefLevel [Byte0]: 46
8725 23:23:20.504301 [Byte1]: 46
8726 23:23:20.508118
8727 23:23:20.508198 Set Vref, RX VrefLevel [Byte0]: 47
8728 23:23:20.511405 [Byte1]: 47
8729 23:23:20.515564
8730 23:23:20.515678 Set Vref, RX VrefLevel [Byte0]: 48
8731 23:23:20.519302 [Byte1]: 48
8732 23:23:20.523506
8733 23:23:20.523618 Set Vref, RX VrefLevel [Byte0]: 49
8734 23:23:20.527123 [Byte1]: 49
8735 23:23:20.531129
8736 23:23:20.531209 Set Vref, RX VrefLevel [Byte0]: 50
8737 23:23:20.534526 [Byte1]: 50
8738 23:23:20.538959
8739 23:23:20.539039 Set Vref, RX VrefLevel [Byte0]: 51
8740 23:23:20.542012 [Byte1]: 51
8741 23:23:20.546488
8742 23:23:20.546601 Set Vref, RX VrefLevel [Byte0]: 52
8743 23:23:20.549564 [Byte1]: 52
8744 23:23:20.554194
8745 23:23:20.554301 Set Vref, RX VrefLevel [Byte0]: 53
8746 23:23:20.556989 [Byte1]: 53
8747 23:23:20.561421
8748 23:23:20.561502 Set Vref, RX VrefLevel [Byte0]: 54
8749 23:23:20.564917 [Byte1]: 54
8750 23:23:20.569533
8751 23:23:20.569613 Set Vref, RX VrefLevel [Byte0]: 55
8752 23:23:20.572632 [Byte1]: 55
8753 23:23:20.576498
8754 23:23:20.576584 Set Vref, RX VrefLevel [Byte0]: 56
8755 23:23:20.579880 [Byte1]: 56
8756 23:23:20.584648
8757 23:23:20.584747 Set Vref, RX VrefLevel [Byte0]: 57
8758 23:23:20.587820 [Byte1]: 57
8759 23:23:20.592215
8760 23:23:20.592296 Set Vref, RX VrefLevel [Byte0]: 58
8761 23:23:20.595589 [Byte1]: 58
8762 23:23:20.599709
8763 23:23:20.599832 Set Vref, RX VrefLevel [Byte0]: 59
8764 23:23:20.603004 [Byte1]: 59
8765 23:23:20.607101
8766 23:23:20.607186 Set Vref, RX VrefLevel [Byte0]: 60
8767 23:23:20.610341 [Byte1]: 60
8768 23:23:20.615033
8769 23:23:20.615114 Set Vref, RX VrefLevel [Byte0]: 61
8770 23:23:20.618170 [Byte1]: 61
8771 23:23:20.622821
8772 23:23:20.622901 Set Vref, RX VrefLevel [Byte0]: 62
8773 23:23:20.626309 [Byte1]: 62
8774 23:23:20.630027
8775 23:23:20.630116 Set Vref, RX VrefLevel [Byte0]: 63
8776 23:23:20.633731 [Byte1]: 63
8777 23:23:20.638059
8778 23:23:20.638135 Set Vref, RX VrefLevel [Byte0]: 64
8779 23:23:20.641601 [Byte1]: 64
8780 23:23:20.645411
8781 23:23:20.645495 Set Vref, RX VrefLevel [Byte0]: 65
8782 23:23:20.648952 [Byte1]: 65
8783 23:23:20.652784
8784 23:23:20.652862 Set Vref, RX VrefLevel [Byte0]: 66
8785 23:23:20.656234 [Byte1]: 66
8786 23:23:20.660700
8787 23:23:20.660784 Set Vref, RX VrefLevel [Byte0]: 67
8788 23:23:20.663658 [Byte1]: 67
8789 23:23:20.668391
8790 23:23:20.668484 Set Vref, RX VrefLevel [Byte0]: 68
8791 23:23:20.671062 [Byte1]: 68
8792 23:23:20.676114
8793 23:23:20.676186 Set Vref, RX VrefLevel [Byte0]: 69
8794 23:23:20.679082 [Byte1]: 69
8795 23:23:20.683195
8796 23:23:20.683269 Set Vref, RX VrefLevel [Byte0]: 70
8797 23:23:20.686269 [Byte1]: 70
8798 23:23:20.690798
8799 23:23:20.690880 Set Vref, RX VrefLevel [Byte0]: 71
8800 23:23:20.694156 [Byte1]: 71
8801 23:23:20.698664
8802 23:23:20.698736 Set Vref, RX VrefLevel [Byte0]: 72
8803 23:23:20.702305 [Byte1]: 72
8804 23:23:20.706496
8805 23:23:20.706581 Set Vref, RX VrefLevel [Byte0]: 73
8806 23:23:20.709700 [Byte1]: 73
8807 23:23:20.713490
8808 23:23:20.713576 Set Vref, RX VrefLevel [Byte0]: 74
8809 23:23:20.716875 [Byte1]: 74
8810 23:23:20.721743
8811 23:23:20.721816 Final RX Vref Byte 0 = 55 to rank0
8812 23:23:20.724467 Final RX Vref Byte 1 = 60 to rank0
8813 23:23:20.728255 Final RX Vref Byte 0 = 55 to rank1
8814 23:23:20.731302 Final RX Vref Byte 1 = 60 to rank1==
8815 23:23:20.734456 Dram Type= 6, Freq= 0, CH_1, rank 0
8816 23:23:20.741248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 23:23:20.741330 ==
8818 23:23:20.741410 DQS Delay:
8819 23:23:20.744587 DQS0 = 0, DQS1 = 0
8820 23:23:20.744659 DQM Delay:
8821 23:23:20.744727 DQM0 = 133, DQM1 = 127
8822 23:23:20.748373 DQ Delay:
8823 23:23:20.751125 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8824 23:23:20.754440 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8825 23:23:20.757868 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8826 23:23:20.761261 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8827 23:23:20.761351
8828 23:23:20.761417
8829 23:23:20.761478
8830 23:23:20.764313 [DramC_TX_OE_Calibration] TA2
8831 23:23:20.767397 Original DQ_B0 (3 6) =30, OEN = 27
8832 23:23:20.770723 Original DQ_B1 (3 6) =30, OEN = 27
8833 23:23:20.774119 24, 0x0, End_B0=24 End_B1=24
8834 23:23:20.777936 25, 0x0, End_B0=25 End_B1=25
8835 23:23:20.778009 26, 0x0, End_B0=26 End_B1=26
8836 23:23:20.780356 27, 0x0, End_B0=27 End_B1=27
8837 23:23:20.784056 28, 0x0, End_B0=28 End_B1=28
8838 23:23:20.787865 29, 0x0, End_B0=29 End_B1=29
8839 23:23:20.787942 30, 0x0, End_B0=30 End_B1=30
8840 23:23:20.790383 31, 0x4141, End_B0=30 End_B1=30
8841 23:23:20.794052 Byte0 end_step=30 best_step=27
8842 23:23:20.797471 Byte1 end_step=30 best_step=27
8843 23:23:20.800291 Byte0 TX OE(2T, 0.5T) = (3, 3)
8844 23:23:20.803952 Byte1 TX OE(2T, 0.5T) = (3, 3)
8845 23:23:20.804028
8846 23:23:20.804091
8847 23:23:20.810217 [DQSOSCAuto] RK0, (LSB)MR18= 0x150b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8848 23:23:20.813873 CH1 RK0: MR19=303, MR18=150B
8849 23:23:20.820447 CH1_RK0: MR19=0x303, MR18=0x150B, DQSOSC=399, MR23=63, INC=23, DEC=15
8850 23:23:20.820526
8851 23:23:20.823574 ----->DramcWriteLeveling(PI) begin...
8852 23:23:20.823652 ==
8853 23:23:20.826864 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 23:23:20.830417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 23:23:20.830499 ==
8856 23:23:20.833578 Write leveling (Byte 0): 23 => 23
8857 23:23:20.837226 Write leveling (Byte 1): 27 => 27
8858 23:23:20.840383 DramcWriteLeveling(PI) end<-----
8859 23:23:20.840487
8860 23:23:20.840587 ==
8861 23:23:20.843574 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 23:23:20.847063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 23:23:20.850234 ==
8864 23:23:20.850310 [Gating] SW mode calibration
8865 23:23:20.859912 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8866 23:23:20.863159 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8867 23:23:20.866730 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8868 23:23:20.872947 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8869 23:23:20.876380 1 4 8 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
8870 23:23:20.879790 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8871 23:23:20.886335 1 4 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8872 23:23:20.889846 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8873 23:23:20.893000 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8874 23:23:20.899912 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8875 23:23:20.902920 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8876 23:23:20.906449 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8877 23:23:20.912217 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8878 23:23:20.915707 1 5 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 0)
8879 23:23:20.919264 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8880 23:23:20.925570 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8881 23:23:20.928452 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8882 23:23:20.935016 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8883 23:23:20.938727 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8884 23:23:20.942345 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8885 23:23:20.948832 1 6 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8886 23:23:20.952020 1 6 12 | B1->B0 | 4545 2424 | 0 0 | (0 0) (0 0)
8887 23:23:20.955566 1 6 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8888 23:23:20.958801 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 23:23:20.964957 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8890 23:23:20.968468 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8891 23:23:20.974920 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8892 23:23:20.978591 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8893 23:23:20.981327 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8894 23:23:20.988054 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8895 23:23:20.991347 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8896 23:23:20.994958 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 23:23:21.001266 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 23:23:21.004900 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 23:23:21.007520 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 23:23:21.014149 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 23:23:21.018011 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 23:23:21.020948 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 23:23:21.028170 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 23:23:21.031149 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 23:23:21.034486 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 23:23:21.037875 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 23:23:21.044772 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 23:23:21.047485 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 23:23:21.051083 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8910 23:23:21.057190 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8911 23:23:21.061023 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8912 23:23:21.063894 Total UI for P1: 0, mck2ui 16
8913 23:23:21.067230 best dqsien dly found for B0: ( 1, 9, 12)
8914 23:23:21.070604 Total UI for P1: 0, mck2ui 16
8915 23:23:21.073479 best dqsien dly found for B1: ( 1, 9, 10)
8916 23:23:21.076854 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8917 23:23:21.080385 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8918 23:23:21.080511
8919 23:23:21.083825 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8920 23:23:21.090594 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8921 23:23:21.090709 [Gating] SW calibration Done
8922 23:23:21.093225 ==
8923 23:23:21.096829 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 23:23:21.100504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 23:23:21.100617 ==
8926 23:23:21.100715 RX Vref Scan: 0
8927 23:23:21.100786
8928 23:23:21.103164 RX Vref 0 -> 0, step: 1
8929 23:23:21.103249
8930 23:23:21.106997 RX Delay 0 -> 252, step: 8
8931 23:23:21.109919 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8932 23:23:21.113151 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8933 23:23:21.116687 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8934 23:23:21.123000 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8935 23:23:21.126545 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8936 23:23:21.130177 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8937 23:23:21.133462 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8938 23:23:21.136809 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8939 23:23:21.142862 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8940 23:23:21.146607 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8941 23:23:21.150095 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8942 23:23:21.153232 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8943 23:23:21.159492 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8944 23:23:21.162972 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8945 23:23:21.166019 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8946 23:23:21.169522 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8947 23:23:21.169604 ==
8948 23:23:21.172291 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 23:23:21.179518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 23:23:21.179613 ==
8951 23:23:21.179726 DQS Delay:
8952 23:23:21.182675 DQS0 = 0, DQS1 = 0
8953 23:23:21.182753 DQM Delay:
8954 23:23:21.185738 DQM0 = 137, DQM1 = 130
8955 23:23:21.185841 DQ Delay:
8956 23:23:21.188918 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8957 23:23:21.192008 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8958 23:23:21.195307 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8959 23:23:21.198490 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8960 23:23:21.198566
8961 23:23:21.198638
8962 23:23:21.198697 ==
8963 23:23:21.202212 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 23:23:21.208268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 23:23:21.208350 ==
8966 23:23:21.208418
8967 23:23:21.208477
8968 23:23:21.208554 TX Vref Scan disable
8969 23:23:21.212196 == TX Byte 0 ==
8970 23:23:21.215503 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8971 23:23:21.221846 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8972 23:23:21.221990 == TX Byte 1 ==
8973 23:23:21.225129 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8974 23:23:21.231529 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8975 23:23:21.231655 ==
8976 23:23:21.235067 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 23:23:21.238136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 23:23:21.238263 ==
8979 23:23:21.251395
8980 23:23:21.254390 TX Vref early break, caculate TX vref
8981 23:23:21.257760 TX Vref=16, minBit 0, minWin=22, winSum=380
8982 23:23:21.260645 TX Vref=18, minBit 1, minWin=23, winSum=390
8983 23:23:21.264406 TX Vref=20, minBit 5, minWin=23, winSum=397
8984 23:23:21.267489 TX Vref=22, minBit 1, minWin=24, winSum=406
8985 23:23:21.270652 TX Vref=24, minBit 0, minWin=25, winSum=415
8986 23:23:21.277173 TX Vref=26, minBit 0, minWin=24, winSum=418
8987 23:23:21.280943 TX Vref=28, minBit 0, minWin=24, winSum=418
8988 23:23:21.283966 TX Vref=30, minBit 0, minWin=23, winSum=410
8989 23:23:21.287534 TX Vref=32, minBit 1, minWin=23, winSum=400
8990 23:23:21.291231 TX Vref=34, minBit 0, minWin=22, winSum=395
8991 23:23:21.297818 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 24
8992 23:23:21.297943
8993 23:23:21.300822 Final TX Range 0 Vref 24
8994 23:23:21.300926
8995 23:23:21.301027 ==
8996 23:23:21.303851 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 23:23:21.307085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 23:23:21.307190 ==
8999 23:23:21.307288
9000 23:23:21.307409
9001 23:23:21.310534 TX Vref Scan disable
9002 23:23:21.316898 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9003 23:23:21.317021 == TX Byte 0 ==
9004 23:23:21.320552 u2DelayCellOfst[0]=18 cells (5 PI)
9005 23:23:21.323580 u2DelayCellOfst[1]=11 cells (3 PI)
9006 23:23:21.327277 u2DelayCellOfst[2]=0 cells (0 PI)
9007 23:23:21.330187 u2DelayCellOfst[3]=7 cells (2 PI)
9008 23:23:21.333628 u2DelayCellOfst[4]=7 cells (2 PI)
9009 23:23:21.337444 u2DelayCellOfst[5]=18 cells (5 PI)
9010 23:23:21.340299 u2DelayCellOfst[6]=18 cells (5 PI)
9011 23:23:21.343862 u2DelayCellOfst[7]=3 cells (1 PI)
9012 23:23:21.346584 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9013 23:23:21.350441 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9014 23:23:21.353592 == TX Byte 1 ==
9015 23:23:21.356465 u2DelayCellOfst[8]=0 cells (0 PI)
9016 23:23:21.356571 u2DelayCellOfst[9]=3 cells (1 PI)
9017 23:23:21.360030 u2DelayCellOfst[10]=11 cells (3 PI)
9018 23:23:21.362874 u2DelayCellOfst[11]=7 cells (2 PI)
9019 23:23:21.366398 u2DelayCellOfst[12]=14 cells (4 PI)
9020 23:23:21.369608 u2DelayCellOfst[13]=18 cells (5 PI)
9021 23:23:21.373217 u2DelayCellOfst[14]=18 cells (5 PI)
9022 23:23:21.376727 u2DelayCellOfst[15]=18 cells (5 PI)
9023 23:23:21.380022 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9024 23:23:21.386211 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9025 23:23:21.386324 DramC Write-DBI on
9026 23:23:21.386420 ==
9027 23:23:21.389775 Dram Type= 6, Freq= 0, CH_1, rank 1
9028 23:23:21.396042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9029 23:23:21.396141 ==
9030 23:23:21.396208
9031 23:23:21.396278
9032 23:23:21.396412 TX Vref Scan disable
9033 23:23:21.400281 == TX Byte 0 ==
9034 23:23:21.403294 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9035 23:23:21.407067 == TX Byte 1 ==
9036 23:23:21.409760 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9037 23:23:21.413556 DramC Write-DBI off
9038 23:23:21.413665
9039 23:23:21.413755 [DATLAT]
9040 23:23:21.413849 Freq=1600, CH1 RK1
9041 23:23:21.413936
9042 23:23:21.416708 DATLAT Default: 0xf
9043 23:23:21.419712 0, 0xFFFF, sum = 0
9044 23:23:21.419830 1, 0xFFFF, sum = 0
9045 23:23:21.423318 2, 0xFFFF, sum = 0
9046 23:23:21.423461 3, 0xFFFF, sum = 0
9047 23:23:21.426765 4, 0xFFFF, sum = 0
9048 23:23:21.426858 5, 0xFFFF, sum = 0
9049 23:23:21.429797 6, 0xFFFF, sum = 0
9050 23:23:21.429913 7, 0xFFFF, sum = 0
9051 23:23:21.433174 8, 0xFFFF, sum = 0
9052 23:23:21.433281 9, 0xFFFF, sum = 0
9053 23:23:21.436550 10, 0xFFFF, sum = 0
9054 23:23:21.436653 11, 0xFFFF, sum = 0
9055 23:23:21.439596 12, 0xFFFF, sum = 0
9056 23:23:21.439755 13, 0xFFFF, sum = 0
9057 23:23:21.443347 14, 0x0, sum = 1
9058 23:23:21.443452 15, 0x0, sum = 2
9059 23:23:21.446160 16, 0x0, sum = 3
9060 23:23:21.446291 17, 0x0, sum = 4
9061 23:23:21.449450 best_step = 15
9062 23:23:21.449524
9063 23:23:21.449585 ==
9064 23:23:21.453178 Dram Type= 6, Freq= 0, CH_1, rank 1
9065 23:23:21.456806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9066 23:23:21.456881 ==
9067 23:23:21.459752 RX Vref Scan: 0
9068 23:23:21.459846
9069 23:23:21.459909 RX Vref 0 -> 0, step: 1
9070 23:23:21.459967
9071 23:23:21.463291 RX Delay 11 -> 252, step: 4
9072 23:23:21.469693 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9073 23:23:21.472974 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9074 23:23:21.476455 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9075 23:23:21.479565 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9076 23:23:21.482412 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9077 23:23:21.489070 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9078 23:23:21.492497 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9079 23:23:21.496196 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9080 23:23:21.499193 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9081 23:23:21.502803 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9082 23:23:21.509289 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9083 23:23:21.512157 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9084 23:23:21.515521 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9085 23:23:21.519187 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9086 23:23:21.525805 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9087 23:23:21.529093 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9088 23:23:21.529175 ==
9089 23:23:21.531852 Dram Type= 6, Freq= 0, CH_1, rank 1
9090 23:23:21.535337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9091 23:23:21.535444 ==
9092 23:23:21.538617 DQS Delay:
9093 23:23:21.538719 DQS0 = 0, DQS1 = 0
9094 23:23:21.538810 DQM Delay:
9095 23:23:21.541841 DQM0 = 134, DQM1 = 126
9096 23:23:21.541923 DQ Delay:
9097 23:23:21.545358 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9098 23:23:21.548533 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9099 23:23:21.554929 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =116
9100 23:23:21.558786 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9101 23:23:21.558868
9102 23:23:21.558933
9103 23:23:21.558993
9104 23:23:21.561377 [DramC_TX_OE_Calibration] TA2
9105 23:23:21.565015 Original DQ_B0 (3 6) =30, OEN = 27
9106 23:23:21.567930 Original DQ_B1 (3 6) =30, OEN = 27
9107 23:23:21.568012 24, 0x0, End_B0=24 End_B1=24
9108 23:23:21.571744 25, 0x0, End_B0=25 End_B1=25
9109 23:23:21.574802 26, 0x0, End_B0=26 End_B1=26
9110 23:23:21.578616 27, 0x0, End_B0=27 End_B1=27
9111 23:23:21.578707 28, 0x0, End_B0=28 End_B1=28
9112 23:23:21.581480 29, 0x0, End_B0=29 End_B1=29
9113 23:23:21.584477 30, 0x0, End_B0=30 End_B1=30
9114 23:23:21.588099 31, 0x4141, End_B0=30 End_B1=30
9115 23:23:21.591517 Byte0 end_step=30 best_step=27
9116 23:23:21.594303 Byte1 end_step=30 best_step=27
9117 23:23:21.594421 Byte0 TX OE(2T, 0.5T) = (3, 3)
9118 23:23:21.597831 Byte1 TX OE(2T, 0.5T) = (3, 3)
9119 23:23:21.597935
9120 23:23:21.598088
9121 23:23:21.608082 [DQSOSCAuto] RK1, (LSB)MR18= 0xa05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 404 ps
9122 23:23:21.611216 CH1 RK1: MR19=303, MR18=A05
9123 23:23:21.614172 CH1_RK1: MR19=0x303, MR18=0xA05, DQSOSC=404, MR23=63, INC=22, DEC=15
9124 23:23:21.617504 [RxdqsGatingPostProcess] freq 1600
9125 23:23:21.624312 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9126 23:23:21.627302 best DQS0 dly(2T, 0.5T) = (1, 1)
9127 23:23:21.630608 best DQS1 dly(2T, 0.5T) = (1, 1)
9128 23:23:21.633855 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9129 23:23:21.636750 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9130 23:23:21.640059 best DQS0 dly(2T, 0.5T) = (1, 1)
9131 23:23:21.643455 best DQS1 dly(2T, 0.5T) = (1, 1)
9132 23:23:21.647111 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9133 23:23:21.649986 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9134 23:23:21.653482 Pre-setting of DQS Precalculation
9135 23:23:21.656858 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9136 23:23:21.663804 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9137 23:23:21.670230 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9138 23:23:21.670312
9139 23:23:21.673790
9140 23:23:21.673873 [Calibration Summary] 3200 Mbps
9141 23:23:21.676353 CH 0, Rank 0
9142 23:23:21.676435 SW Impedance : PASS
9143 23:23:21.679754 DUTY Scan : NO K
9144 23:23:21.683416 ZQ Calibration : PASS
9145 23:23:21.683498 Jitter Meter : NO K
9146 23:23:21.686163 CBT Training : PASS
9147 23:23:21.689617 Write leveling : PASS
9148 23:23:21.689699 RX DQS gating : PASS
9149 23:23:21.692786 RX DQ/DQS(RDDQC) : PASS
9150 23:23:21.695900 TX DQ/DQS : PASS
9151 23:23:21.696009 RX DATLAT : PASS
9152 23:23:21.699777 RX DQ/DQS(Engine): PASS
9153 23:23:21.702808 TX OE : PASS
9154 23:23:21.702890 All Pass.
9155 23:23:21.702994
9156 23:23:21.703072 CH 0, Rank 1
9157 23:23:21.705996 SW Impedance : PASS
9158 23:23:21.709591 DUTY Scan : NO K
9159 23:23:21.709697 ZQ Calibration : PASS
9160 23:23:21.712767 Jitter Meter : NO K
9161 23:23:21.715721 CBT Training : PASS
9162 23:23:21.715825 Write leveling : PASS
9163 23:23:21.719059 RX DQS gating : PASS
9164 23:23:21.722538 RX DQ/DQS(RDDQC) : PASS
9165 23:23:21.722663 TX DQ/DQS : PASS
9166 23:23:21.725963 RX DATLAT : PASS
9167 23:23:21.729511 RX DQ/DQS(Engine): PASS
9168 23:23:21.729640 TX OE : PASS
9169 23:23:21.729768 All Pass.
9170 23:23:21.732731
9171 23:23:21.732836 CH 1, Rank 0
9172 23:23:21.735571 SW Impedance : PASS
9173 23:23:21.735703 DUTY Scan : NO K
9174 23:23:21.738799 ZQ Calibration : PASS
9175 23:23:21.742510 Jitter Meter : NO K
9176 23:23:21.742634 CBT Training : PASS
9177 23:23:21.745525 Write leveling : PASS
9178 23:23:21.745609 RX DQS gating : PASS
9179 23:23:21.749090 RX DQ/DQS(RDDQC) : PASS
9180 23:23:21.751955 TX DQ/DQS : PASS
9181 23:23:21.752064 RX DATLAT : PASS
9182 23:23:21.755359 RX DQ/DQS(Engine): PASS
9183 23:23:21.758763 TX OE : PASS
9184 23:23:21.758851 All Pass.
9185 23:23:21.758913
9186 23:23:21.758982 CH 1, Rank 1
9187 23:23:21.762125 SW Impedance : PASS
9188 23:23:21.765172 DUTY Scan : NO K
9189 23:23:21.765286 ZQ Calibration : PASS
9190 23:23:21.768531 Jitter Meter : NO K
9191 23:23:21.771873 CBT Training : PASS
9192 23:23:21.772004 Write leveling : PASS
9193 23:23:21.775276 RX DQS gating : PASS
9194 23:23:21.778224 RX DQ/DQS(RDDQC) : PASS
9195 23:23:21.778341 TX DQ/DQS : PASS
9196 23:23:21.781771 RX DATLAT : PASS
9197 23:23:21.785109 RX DQ/DQS(Engine): PASS
9198 23:23:21.785219 TX OE : PASS
9199 23:23:21.788622 All Pass.
9200 23:23:21.788747
9201 23:23:21.788844 DramC Write-DBI on
9202 23:23:21.792289 PER_BANK_REFRESH: Hybrid Mode
9203 23:23:21.792397 TX_TRACKING: ON
9204 23:23:21.801516 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9205 23:23:21.811682 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9206 23:23:21.818191 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9207 23:23:21.821167 [FAST_K] Save calibration result to emmc
9208 23:23:21.824925 sync common calibartion params.
9209 23:23:21.825009 sync cbt_mode0:1, 1:1
9210 23:23:21.827826 dram_init: ddr_geometry: 2
9211 23:23:21.831028 dram_init: ddr_geometry: 2
9212 23:23:21.834868 dram_init: ddr_geometry: 2
9213 23:23:21.834984 0:dram_rank_size:100000000
9214 23:23:21.837444 1:dram_rank_size:100000000
9215 23:23:21.844511 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9216 23:23:21.844626 DFS_SHUFFLE_HW_MODE: ON
9217 23:23:21.850915 dramc_set_vcore_voltage set vcore to 725000
9218 23:23:21.851029 Read voltage for 1600, 0
9219 23:23:21.854202 Vio18 = 0
9220 23:23:21.854316 Vcore = 725000
9221 23:23:21.854418 Vdram = 0
9222 23:23:21.854510 Vddq = 0
9223 23:23:21.857626 Vmddr = 0
9224 23:23:21.860765 switch to 3200 Mbps bootup
9225 23:23:21.860876 [DramcRunTimeConfig]
9226 23:23:21.860976 PHYPLL
9227 23:23:21.863921 DPM_CONTROL_AFTERK: ON
9228 23:23:21.867424 PER_BANK_REFRESH: ON
9229 23:23:21.867519 REFRESH_OVERHEAD_REDUCTION: ON
9230 23:23:21.870581 CMD_PICG_NEW_MODE: OFF
9231 23:23:21.874013 XRTWTW_NEW_MODE: ON
9232 23:23:21.874113 XRTRTR_NEW_MODE: ON
9233 23:23:21.877333 TX_TRACKING: ON
9234 23:23:21.877415 RDSEL_TRACKING: OFF
9235 23:23:21.880334 DQS Precalculation for DVFS: ON
9236 23:23:21.880462 RX_TRACKING: OFF
9237 23:23:21.883861 HW_GATING DBG: ON
9238 23:23:21.883965 ZQCS_ENABLE_LP4: ON
9239 23:23:21.886983 RX_PICG_NEW_MODE: ON
9240 23:23:21.890419 TX_PICG_NEW_MODE: ON
9241 23:23:21.890522 ENABLE_RX_DCM_DPHY: ON
9242 23:23:21.893752 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9243 23:23:21.897653 DUMMY_READ_FOR_TRACKING: OFF
9244 23:23:21.900152 !!! SPM_CONTROL_AFTERK: OFF
9245 23:23:21.903374 !!! SPM could not control APHY
9246 23:23:21.903462 IMPEDANCE_TRACKING: ON
9247 23:23:21.906732 TEMP_SENSOR: ON
9248 23:23:21.906842 HW_SAVE_FOR_SR: OFF
9249 23:23:21.910630 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9250 23:23:21.913278 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9251 23:23:21.917005 Read ODT Tracking: ON
9252 23:23:21.917108 Refresh Rate DeBounce: ON
9253 23:23:21.920084 DFS_NO_QUEUE_FLUSH: ON
9254 23:23:21.923236 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9255 23:23:21.926782 ENABLE_DFS_RUNTIME_MRW: OFF
9256 23:23:21.929768 DDR_RESERVE_NEW_MODE: ON
9257 23:23:21.929890 MR_CBT_SWITCH_FREQ: ON
9258 23:23:21.933534 =========================
9259 23:23:21.951614 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9260 23:23:21.954862 dram_init: ddr_geometry: 2
9261 23:23:21.973478 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9262 23:23:21.976463 dram_init: dram init end (result: 0)
9263 23:23:21.982958 DRAM-K: Full calibration passed in 24618 msecs
9264 23:23:21.986587 MRC: failed to locate region type 0.
9265 23:23:21.986699 DRAM rank0 size:0x100000000,
9266 23:23:21.989450 DRAM rank1 size=0x100000000
9267 23:23:21.999463 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9268 23:23:22.005858 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9269 23:23:22.015849 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9270 23:23:22.022272 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9271 23:23:22.022392 DRAM rank0 size:0x100000000,
9272 23:23:22.025383 DRAM rank1 size=0x100000000
9273 23:23:22.025495 CBMEM:
9274 23:23:22.029003 IMD: root @ 0xfffff000 254 entries.
9275 23:23:22.032646 IMD: root @ 0xffffec00 62 entries.
9276 23:23:22.038642 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9277 23:23:22.041868 WARNING: RO_VPD is uninitialized or empty.
9278 23:23:22.045279 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9279 23:23:22.056285 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9280 23:23:22.065960 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9281 23:23:22.077358 BS: romstage times (exec / console): total (unknown) / 24113 ms
9282 23:23:22.077439
9283 23:23:22.077533
9284 23:23:22.087700 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9285 23:23:22.090457 ARM64: Exception handlers installed.
9286 23:23:22.093949 ARM64: Testing exception
9287 23:23:22.097036 ARM64: Done test exception
9288 23:23:22.097115 Enumerating buses...
9289 23:23:22.100636 Show all devs... Before device enumeration.
9290 23:23:22.103415 Root Device: enabled 1
9291 23:23:22.106928 CPU_CLUSTER: 0: enabled 1
9292 23:23:22.107008 CPU: 00: enabled 1
9293 23:23:22.110288 Compare with tree...
9294 23:23:22.110414 Root Device: enabled 1
9295 23:23:22.113577 CPU_CLUSTER: 0: enabled 1
9296 23:23:22.116995 CPU: 00: enabled 1
9297 23:23:22.117098 Root Device scanning...
9298 23:23:22.120138 scan_static_bus for Root Device
9299 23:23:22.123540 CPU_CLUSTER: 0 enabled
9300 23:23:22.127046 scan_static_bus for Root Device done
9301 23:23:22.129809 scan_bus: bus Root Device finished in 8 msecs
9302 23:23:22.129932 done
9303 23:23:22.136382 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9304 23:23:22.140090 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9305 23:23:22.146707 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9306 23:23:22.152945 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9307 23:23:22.153064 Allocating resources...
9308 23:23:22.156231 Reading resources...
9309 23:23:22.159551 Root Device read_resources bus 0 link: 0
9310 23:23:22.162737 DRAM rank0 size:0x100000000,
9311 23:23:22.162854 DRAM rank1 size=0x100000000
9312 23:23:22.169532 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9313 23:23:22.169651 CPU: 00 missing read_resources
9314 23:23:22.176178 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9315 23:23:22.179783 Root Device read_resources bus 0 link: 0 done
9316 23:23:22.182902 Done reading resources.
9317 23:23:22.185905 Show resources in subtree (Root Device)...After reading.
9318 23:23:22.189348 Root Device child on link 0 CPU_CLUSTER: 0
9319 23:23:22.192618 CPU_CLUSTER: 0 child on link 0 CPU: 00
9320 23:23:22.202041 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9321 23:23:22.202159 CPU: 00
9322 23:23:22.208895 Root Device assign_resources, bus 0 link: 0
9323 23:23:22.212093 CPU_CLUSTER: 0 missing set_resources
9324 23:23:22.215693 Root Device assign_resources, bus 0 link: 0 done
9325 23:23:22.218777 Done setting resources.
9326 23:23:22.222176 Show resources in subtree (Root Device)...After assigning values.
9327 23:23:22.225212 Root Device child on link 0 CPU_CLUSTER: 0
9328 23:23:22.231997 CPU_CLUSTER: 0 child on link 0 CPU: 00
9329 23:23:22.238663 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9330 23:23:22.241905 CPU: 00
9331 23:23:22.242010 Done allocating resources.
9332 23:23:22.248162 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9333 23:23:22.248254 Enabling resources...
9334 23:23:22.252090 done.
9335 23:23:22.255215 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9336 23:23:22.258194 Initializing devices...
9337 23:23:22.258307 Root Device init
9338 23:23:22.261500 init hardware done!
9339 23:23:22.261604 0x00000018: ctrlr->caps
9340 23:23:22.265126 52.000 MHz: ctrlr->f_max
9341 23:23:22.268126 0.400 MHz: ctrlr->f_min
9342 23:23:22.271750 0x40ff8080: ctrlr->voltages
9343 23:23:22.271832 sclk: 390625
9344 23:23:22.271907 Bus Width = 1
9345 23:23:22.275194 sclk: 390625
9346 23:23:22.275307 Bus Width = 1
9347 23:23:22.278173 Early init status = 3
9348 23:23:22.281495 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9349 23:23:22.285847 in-header: 03 fc 00 00 01 00 00 00
9350 23:23:22.288927 in-data: 00
9351 23:23:22.292482 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9352 23:23:22.297969 in-header: 03 fd 00 00 00 00 00 00
9353 23:23:22.301392 in-data:
9354 23:23:22.304232 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9355 23:23:22.308850 in-header: 03 fc 00 00 01 00 00 00
9356 23:23:22.311878 in-data: 00
9357 23:23:22.315660 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9358 23:23:22.321039 in-header: 03 fd 00 00 00 00 00 00
9359 23:23:22.324864 in-data:
9360 23:23:22.327585 [SSUSB] Setting up USB HOST controller...
9361 23:23:22.330753 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9362 23:23:22.334254 [SSUSB] phy power-on done.
9363 23:23:22.337203 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9364 23:23:22.343946 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9365 23:23:22.348121 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9366 23:23:22.354163 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9367 23:23:22.360542 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9368 23:23:22.367105 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9369 23:23:22.373715 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9370 23:23:22.380384 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9371 23:23:22.383922 SPM: binary array size = 0x9dc
9372 23:23:22.386947 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9373 23:23:22.393766 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9374 23:23:22.400357 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9375 23:23:22.407017 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9376 23:23:22.409803 configure_display: Starting display init
9377 23:23:22.444329 anx7625_power_on_init: Init interface.
9378 23:23:22.447941 anx7625_disable_pd_protocol: Disabled PD feature.
9379 23:23:22.450597 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9380 23:23:22.478453 anx7625_start_dp_work: Secure OCM version=00
9381 23:23:22.481720 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9382 23:23:22.496698 sp_tx_get_edid_block: EDID Block = 1
9383 23:23:22.599169 Extracted contents:
9384 23:23:22.602674 header: 00 ff ff ff ff ff ff 00
9385 23:23:22.605769 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9386 23:23:22.609056 version: 01 04
9387 23:23:22.612337 basic params: 95 1f 11 78 0a
9388 23:23:22.616073 chroma info: 76 90 94 55 54 90 27 21 50 54
9389 23:23:22.618962 established: 00 00 00
9390 23:23:22.625726 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9391 23:23:22.632124 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9392 23:23:22.635266 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9393 23:23:22.641803 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9394 23:23:22.648297 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9395 23:23:22.652145 extensions: 00
9396 23:23:22.652235 checksum: fb
9397 23:23:22.652301
9398 23:23:22.658177 Manufacturer: IVO Model 57d Serial Number 0
9399 23:23:22.658288 Made week 0 of 2020
9400 23:23:22.662072 EDID version: 1.4
9401 23:23:22.662148 Digital display
9402 23:23:22.664731 6 bits per primary color channel
9403 23:23:22.668028 DisplayPort interface
9404 23:23:22.668113 Maximum image size: 31 cm x 17 cm
9405 23:23:22.671894 Gamma: 220%
9406 23:23:22.671979 Check DPMS levels
9407 23:23:22.678092 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9408 23:23:22.681345 First detailed timing is preferred timing
9409 23:23:22.684770 Established timings supported:
9410 23:23:22.684864 Standard timings supported:
9411 23:23:22.687812 Detailed timings
9412 23:23:22.691239 Hex of detail: 383680a07038204018303c0035ae10000019
9413 23:23:22.697739 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9414 23:23:22.701532 0780 0798 07c8 0820 hborder 0
9415 23:23:22.704646 0438 043b 0447 0458 vborder 0
9416 23:23:22.707679 -hsync -vsync
9417 23:23:22.707790 Did detailed timing
9418 23:23:22.714210 Hex of detail: 000000000000000000000000000000000000
9419 23:23:22.718030 Manufacturer-specified data, tag 0
9420 23:23:22.721521 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9421 23:23:22.724093 ASCII string: InfoVision
9422 23:23:22.727714 Hex of detail: 000000fe00523134304e574635205248200a
9423 23:23:22.731071 ASCII string: R140NWF5 RH
9424 23:23:22.731214 Checksum
9425 23:23:22.734491 Checksum: 0xfb (valid)
9426 23:23:22.737500 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9427 23:23:22.741010 DSI data_rate: 832800000 bps
9428 23:23:22.747405 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9429 23:23:22.750686 anx7625_parse_edid: pixelclock(138800).
9430 23:23:22.754448 hactive(1920), hsync(48), hfp(24), hbp(88)
9431 23:23:22.757803 vactive(1080), vsync(12), vfp(3), vbp(17)
9432 23:23:22.760371 anx7625_dsi_config: config dsi.
9433 23:23:22.767142 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9434 23:23:22.781176 anx7625_dsi_config: success to config DSI
9435 23:23:22.784618 anx7625_dp_start: MIPI phy setup OK.
9436 23:23:22.788335 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9437 23:23:22.791052 mtk_ddp_mode_set invalid vrefresh 60
9438 23:23:22.794647 main_disp_path_setup
9439 23:23:22.794728 ovl_layer_smi_id_en
9440 23:23:22.797805 ovl_layer_smi_id_en
9441 23:23:22.797913 ccorr_config
9442 23:23:22.798025 aal_config
9443 23:23:22.801176 gamma_config
9444 23:23:22.801289 postmask_config
9445 23:23:22.804567 dither_config
9446 23:23:22.808035 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9447 23:23:22.814443 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9448 23:23:22.817636 Root Device init finished in 555 msecs
9449 23:23:22.821122 CPU_CLUSTER: 0 init
9450 23:23:22.827435 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9451 23:23:22.834379 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9452 23:23:22.834500 APU_MBOX 0x190000b0 = 0x10001
9453 23:23:22.837852 APU_MBOX 0x190001b0 = 0x10001
9454 23:23:22.840715 APU_MBOX 0x190005b0 = 0x10001
9455 23:23:22.844386 APU_MBOX 0x190006b0 = 0x10001
9456 23:23:22.850472 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9457 23:23:22.860199 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9458 23:23:22.873011 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9459 23:23:22.879541 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9460 23:23:22.891204 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9461 23:23:22.899910 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9462 23:23:22.903601 CPU_CLUSTER: 0 init finished in 81 msecs
9463 23:23:22.906763 Devices initialized
9464 23:23:22.909847 Show all devs... After init.
9465 23:23:22.909930 Root Device: enabled 1
9466 23:23:22.913217 CPU_CLUSTER: 0: enabled 1
9467 23:23:22.916127 CPU: 00: enabled 1
9468 23:23:22.919977 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9469 23:23:22.923192 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9470 23:23:22.926300 ELOG: NV offset 0x57f000 size 0x1000
9471 23:23:22.932973 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9472 23:23:22.939594 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9473 23:23:22.943130 ELOG: Event(17) added with size 13 at 2024-04-03 23:23:23 UTC
9474 23:23:22.949839 out: cmd=0x121: 03 db 21 01 00 00 00 00
9475 23:23:22.952731 in-header: 03 a6 00 00 2c 00 00 00
9476 23:23:22.966082 in-data: b9 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9477 23:23:22.969425 ELOG: Event(A1) added with size 10 at 2024-04-03 23:23:23 UTC
9478 23:23:22.979300 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9479 23:23:22.982653 ELOG: Event(A0) added with size 9 at 2024-04-03 23:23:23 UTC
9480 23:23:22.985482 elog_add_boot_reason: Logged dev mode boot
9481 23:23:22.992268 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9482 23:23:22.992352 Finalize devices...
9483 23:23:22.995439 Devices finalized
9484 23:23:22.999123 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9485 23:23:23.002005 Writing coreboot table at 0xffe64000
9486 23:23:23.008832 0. 000000000010a000-0000000000113fff: RAMSTAGE
9487 23:23:23.012644 1. 0000000040000000-00000000400fffff: RAM
9488 23:23:23.015297 2. 0000000040100000-000000004032afff: RAMSTAGE
9489 23:23:23.018965 3. 000000004032b000-00000000545fffff: RAM
9490 23:23:23.022049 4. 0000000054600000-000000005465ffff: BL31
9491 23:23:23.028737 5. 0000000054660000-00000000ffe63fff: RAM
9492 23:23:23.031785 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9493 23:23:23.035303 7. 0000000100000000-000000023fffffff: RAM
9494 23:23:23.038337 Passing 5 GPIOs to payload:
9495 23:23:23.045180 NAME | PORT | POLARITY | VALUE
9496 23:23:23.048290 EC in RW | 0x000000aa | low | undefined
9497 23:23:23.051678 EC interrupt | 0x00000005 | low | undefined
9498 23:23:23.057849 TPM interrupt | 0x000000ab | high | undefined
9499 23:23:23.061806 SD card detect | 0x00000011 | high | undefined
9500 23:23:23.068249 speaker enable | 0x00000093 | high | undefined
9501 23:23:23.071070 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9502 23:23:23.074603 in-header: 03 f9 00 00 02 00 00 00
9503 23:23:23.074710 in-data: 02 00
9504 23:23:23.078182 ADC[4]: Raw value=900443 ID=7
9505 23:23:23.081251 ADC[3]: Raw value=213652 ID=1
9506 23:23:23.081334 RAM Code: 0x71
9507 23:23:23.084725 ADC[6]: Raw value=75036 ID=0
9508 23:23:23.087827 ADC[5]: Raw value=213282 ID=1
9509 23:23:23.087909 SKU Code: 0x1
9510 23:23:23.094392 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum dda9
9511 23:23:23.097513 coreboot table: 964 bytes.
9512 23:23:23.100836 IMD ROOT 0. 0xfffff000 0x00001000
9513 23:23:23.104280 IMD SMALL 1. 0xffffe000 0x00001000
9514 23:23:23.107521 RO MCACHE 2. 0xffffc000 0x00001104
9515 23:23:23.110963 CONSOLE 3. 0xfff7c000 0x00080000
9516 23:23:23.114497 FMAP 4. 0xfff7b000 0x00000452
9517 23:23:23.117357 TIME STAMP 5. 0xfff7a000 0x00000910
9518 23:23:23.121059 VBOOT WORK 6. 0xfff66000 0x00014000
9519 23:23:23.123966 RAMOOPS 7. 0xffe66000 0x00100000
9520 23:23:23.127409 COREBOOT 8. 0xffe64000 0x00002000
9521 23:23:23.127541 IMD small region:
9522 23:23:23.130935 IMD ROOT 0. 0xffffec00 0x00000400
9523 23:23:23.134130 VPD 1. 0xffffeb80 0x0000006c
9524 23:23:23.137098 MMC STATUS 2. 0xffffeb60 0x00000004
9525 23:23:23.143458 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9526 23:23:23.146819 Probing TPM: done!
9527 23:23:23.150038 Connected to device vid:did:rid of 1ae0:0028:00
9528 23:23:23.160044 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9529 23:23:23.163278 Initialized TPM device CR50 revision 0
9530 23:23:23.166744 Checking cr50 for pending updates
9531 23:23:23.170444 Reading cr50 TPM mode
9532 23:23:23.179397 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9533 23:23:23.185663 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9534 23:23:23.226146 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9535 23:23:23.228831 Checking segment from ROM address 0x40100000
9536 23:23:23.232772 Checking segment from ROM address 0x4010001c
9537 23:23:23.239060 Loading segment from ROM address 0x40100000
9538 23:23:23.239146 code (compression=0)
9539 23:23:23.248956 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9540 23:23:23.255321 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9541 23:23:23.255441 it's not compressed!
9542 23:23:23.262256 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9543 23:23:23.268525 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9544 23:23:23.285995 Loading segment from ROM address 0x4010001c
9545 23:23:23.286110 Entry Point 0x80000000
9546 23:23:23.289489 Loaded segments
9547 23:23:23.293048 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9548 23:23:23.299435 Jumping to boot code at 0x80000000(0xffe64000)
9549 23:23:23.305845 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9550 23:23:23.312608 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9551 23:23:23.320500 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9552 23:23:23.324019 Checking segment from ROM address 0x40100000
9553 23:23:23.327770 Checking segment from ROM address 0x4010001c
9554 23:23:23.334412 Loading segment from ROM address 0x40100000
9555 23:23:23.334520 code (compression=1)
9556 23:23:23.341043 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9557 23:23:23.350714 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9558 23:23:23.350802 using LZMA
9559 23:23:23.358847 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9560 23:23:23.365740 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9561 23:23:23.368977 Loading segment from ROM address 0x4010001c
9562 23:23:23.369082 Entry Point 0x54601000
9563 23:23:23.372530 Loaded segments
9564 23:23:23.375154 NOTICE: MT8192 bl31_setup
9565 23:23:23.382957 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9566 23:23:23.385713 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9567 23:23:23.389013 WARNING: region 0:
9568 23:23:23.392435 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9569 23:23:23.392547 WARNING: region 1:
9570 23:23:23.399110 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9571 23:23:23.402591 WARNING: region 2:
9572 23:23:23.406002 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9573 23:23:23.409041 WARNING: region 3:
9574 23:23:23.412452 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9575 23:23:23.415865 WARNING: region 4:
9576 23:23:23.422837 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9577 23:23:23.422963 WARNING: region 5:
9578 23:23:23.425455 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9579 23:23:23.429274 WARNING: region 6:
9580 23:23:23.432632 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9581 23:23:23.435998 WARNING: region 7:
9582 23:23:23.438951 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9583 23:23:23.445824 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9584 23:23:23.448715 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9585 23:23:23.452072 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9586 23:23:23.459269 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9587 23:23:23.462150 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9588 23:23:23.469192 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9589 23:23:23.472313 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9590 23:23:23.475569 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9591 23:23:23.481912 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9592 23:23:23.485591 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9593 23:23:23.488813 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9594 23:23:23.495211 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9595 23:23:23.499275 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9596 23:23:23.505168 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9597 23:23:23.508785 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9598 23:23:23.511908 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9599 23:23:23.518433 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9600 23:23:23.521793 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9601 23:23:23.528636 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9602 23:23:23.532157 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9603 23:23:23.534891 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9604 23:23:23.541739 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9605 23:23:23.544494 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9606 23:23:23.548254 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9607 23:23:23.554810 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9608 23:23:23.558199 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9609 23:23:23.564456 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9610 23:23:23.567900 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9611 23:23:23.574486 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9612 23:23:23.577744 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9613 23:23:23.581427 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9614 23:23:23.588055 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9615 23:23:23.591426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9616 23:23:23.594341 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9617 23:23:23.597476 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9618 23:23:23.603994 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9619 23:23:23.607928 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9620 23:23:23.610857 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9621 23:23:23.617536 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9622 23:23:23.620890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9623 23:23:23.624027 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9624 23:23:23.627691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9625 23:23:23.633894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9626 23:23:23.637171 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9627 23:23:23.640622 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9628 23:23:23.644020 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9629 23:23:23.650886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9630 23:23:23.654492 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9631 23:23:23.657161 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9632 23:23:23.664078 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9633 23:23:23.666959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9634 23:23:23.673863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9635 23:23:23.677409 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9636 23:23:23.680837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9637 23:23:23.687239 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9638 23:23:23.690466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9639 23:23:23.697150 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9640 23:23:23.700398 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9641 23:23:23.707321 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9642 23:23:23.710270 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9643 23:23:23.716806 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9644 23:23:23.720498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9645 23:23:23.726676 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9646 23:23:23.730400 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9647 23:23:23.733560 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9648 23:23:23.739818 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9649 23:23:23.743140 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9650 23:23:23.750168 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9651 23:23:23.753165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9652 23:23:23.759910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9653 23:23:23.763446 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9654 23:23:23.766176 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9655 23:23:23.773033 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9656 23:23:23.776461 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9657 23:23:23.782964 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9658 23:23:23.785988 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9659 23:23:23.792973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9660 23:23:23.796614 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9661 23:23:23.803215 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9662 23:23:23.806436 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9663 23:23:23.812662 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9664 23:23:23.815984 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9665 23:23:23.819306 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9666 23:23:23.826184 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9667 23:23:23.829141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9668 23:23:23.835892 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9669 23:23:23.839130 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9670 23:23:23.845621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9671 23:23:23.849258 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9672 23:23:23.852773 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9673 23:23:23.858793 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9674 23:23:23.862495 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9675 23:23:23.869626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9676 23:23:23.872505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9677 23:23:23.879003 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9678 23:23:23.882225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9679 23:23:23.885462 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9680 23:23:23.892105 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9681 23:23:23.895829 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9682 23:23:23.898794 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9683 23:23:23.902079 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9684 23:23:23.908776 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9685 23:23:23.912647 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9686 23:23:23.918559 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9687 23:23:23.922185 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9688 23:23:23.925190 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9689 23:23:23.931885 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9690 23:23:23.935485 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9691 23:23:23.941658 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9692 23:23:23.945375 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9693 23:23:23.948650 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9694 23:23:23.954926 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9695 23:23:23.958496 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9696 23:23:23.965307 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9697 23:23:23.968246 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9698 23:23:23.971879 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9699 23:23:23.978270 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9700 23:23:23.982035 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9701 23:23:23.984922 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9702 23:23:23.991448 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9703 23:23:23.994741 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9704 23:23:23.998095 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9705 23:23:24.001867 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9706 23:23:24.008066 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9707 23:23:24.011501 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9708 23:23:24.015043 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9709 23:23:24.021445 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9710 23:23:24.024717 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9711 23:23:24.031287 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9712 23:23:24.034713 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9713 23:23:24.037605 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9714 23:23:24.044440 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9715 23:23:24.047568 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9716 23:23:24.054392 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9717 23:23:24.057577 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9718 23:23:24.060855 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9719 23:23:24.067326 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9720 23:23:24.071101 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9721 23:23:24.077820 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9722 23:23:24.081281 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9723 23:23:24.083821 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9724 23:23:24.090977 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9725 23:23:24.094169 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9726 23:23:24.100908 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9727 23:23:24.103826 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9728 23:23:24.107286 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9729 23:23:24.113667 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9730 23:23:24.116824 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9731 23:23:24.123457 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9732 23:23:24.126855 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9733 23:23:24.130141 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9734 23:23:24.136920 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9735 23:23:24.140019 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9736 23:23:24.146880 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9737 23:23:24.149944 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9738 23:23:24.153544 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9739 23:23:24.160060 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9740 23:23:24.163299 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9741 23:23:24.169865 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9742 23:23:24.173436 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9743 23:23:24.176405 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9744 23:23:24.183080 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9745 23:23:24.186472 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9746 23:23:24.192912 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9747 23:23:24.196208 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9748 23:23:24.199441 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9749 23:23:24.205970 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9750 23:23:24.209756 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9751 23:23:24.216281 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9752 23:23:24.219540 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9753 23:23:24.222977 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9754 23:23:24.229146 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9755 23:23:24.232540 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9756 23:23:24.239104 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9757 23:23:24.242465 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9758 23:23:24.245691 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9759 23:23:24.252295 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9760 23:23:24.255754 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9761 23:23:24.262187 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9762 23:23:24.265489 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9763 23:23:24.268383 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9764 23:23:24.276181 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9765 23:23:24.278426 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9766 23:23:24.285343 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9767 23:23:24.288526 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9768 23:23:24.291828 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9769 23:23:24.298450 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9770 23:23:24.301535 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9771 23:23:24.308257 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9772 23:23:24.311339 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9773 23:23:24.318003 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9774 23:23:24.321704 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9775 23:23:24.324732 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9776 23:23:24.331251 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9777 23:23:24.334404 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9778 23:23:24.341154 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9779 23:23:24.344307 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9780 23:23:24.350847 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9781 23:23:24.354341 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9782 23:23:24.357323 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9783 23:23:24.364274 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9784 23:23:24.367357 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9785 23:23:24.373607 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9786 23:23:24.377641 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9787 23:23:24.383885 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9788 23:23:24.386934 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9789 23:23:24.390368 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9790 23:23:24.397137 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9791 23:23:24.400017 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9792 23:23:24.407176 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9793 23:23:24.409862 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9794 23:23:24.416768 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9795 23:23:24.420210 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9796 23:23:24.423094 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9797 23:23:24.430045 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9798 23:23:24.432931 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9799 23:23:24.439461 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9800 23:23:24.442840 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9801 23:23:24.449817 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9802 23:23:24.452784 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9803 23:23:24.456431 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9804 23:23:24.462551 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9805 23:23:24.466182 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9806 23:23:24.472645 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9807 23:23:24.476395 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9808 23:23:24.482364 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9809 23:23:24.485840 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9810 23:23:24.488897 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9811 23:23:24.495983 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9812 23:23:24.499312 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9813 23:23:24.501881 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9814 23:23:24.508699 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9815 23:23:24.511918 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9816 23:23:24.515488 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9817 23:23:24.518646 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9818 23:23:24.525128 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9819 23:23:24.528687 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9820 23:23:24.535246 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9821 23:23:24.538471 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9822 23:23:24.541869 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9823 23:23:24.548905 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9824 23:23:24.551693 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9825 23:23:24.558455 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9826 23:23:24.561381 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9827 23:23:24.564876 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9828 23:23:24.571384 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9829 23:23:24.574556 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9830 23:23:24.577659 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9831 23:23:24.584570 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9832 23:23:24.587796 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9833 23:23:24.591476 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9834 23:23:24.597845 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9835 23:23:24.600905 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9836 23:23:24.607478 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9837 23:23:24.610709 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9838 23:23:24.614584 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9839 23:23:24.621217 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9840 23:23:24.624074 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9841 23:23:24.627311 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9842 23:23:24.634009 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9843 23:23:24.637011 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9844 23:23:24.643819 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9845 23:23:24.647130 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9846 23:23:24.650646 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9847 23:23:24.657253 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9848 23:23:24.660671 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9849 23:23:24.663634 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9850 23:23:24.670328 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9851 23:23:24.673174 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9852 23:23:24.676976 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9853 23:23:24.683363 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9854 23:23:24.686477 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9855 23:23:24.690186 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9856 23:23:24.693661 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9857 23:23:24.699852 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9858 23:23:24.703140 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9859 23:23:24.706178 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9860 23:23:24.709678 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9861 23:23:24.716275 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9862 23:23:24.719431 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9863 23:23:24.722782 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9864 23:23:24.726388 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9865 23:23:24.732630 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9866 23:23:24.736138 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9867 23:23:24.742727 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9868 23:23:24.746131 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9869 23:23:24.752535 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9870 23:23:24.755663 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9871 23:23:24.762239 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9872 23:23:24.766023 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9873 23:23:24.768866 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9874 23:23:24.775558 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9875 23:23:24.779203 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9876 23:23:24.785858 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9877 23:23:24.788542 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9878 23:23:24.795468 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9879 23:23:24.798720 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9880 23:23:24.801821 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9881 23:23:24.808239 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9882 23:23:24.811950 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9883 23:23:24.818584 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9884 23:23:24.821744 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9885 23:23:24.825042 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9886 23:23:24.831637 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9887 23:23:24.835225 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9888 23:23:24.838444 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9889 23:23:24.845209 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9890 23:23:24.848509 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9891 23:23:24.854689 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9892 23:23:24.858280 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9893 23:23:24.864685 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9894 23:23:24.868012 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9895 23:23:24.874552 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9896 23:23:24.878184 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9897 23:23:24.881333 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9898 23:23:24.887957 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9899 23:23:24.891117 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9900 23:23:24.897896 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9901 23:23:24.901448 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9902 23:23:24.904258 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9903 23:23:24.910887 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9904 23:23:24.914451 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9905 23:23:24.920736 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9906 23:23:24.923827 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9907 23:23:24.927826 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9908 23:23:24.934079 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9909 23:23:24.937617 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9910 23:23:24.943971 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9911 23:23:24.947200 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9912 23:23:24.953654 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9913 23:23:24.956637 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9914 23:23:24.960250 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9915 23:23:24.966922 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9916 23:23:24.970256 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9917 23:23:24.976848 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9918 23:23:24.980302 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9919 23:23:24.986716 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9920 23:23:24.989633 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9921 23:23:24.993360 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9922 23:23:24.999901 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9923 23:23:25.003438 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9924 23:23:25.010102 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9925 23:23:25.013007 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9926 23:23:25.019372 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9927 23:23:25.023050 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9928 23:23:25.025837 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9929 23:23:25.032565 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9930 23:23:25.035709 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9931 23:23:25.042310 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9932 23:23:25.045752 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9933 23:23:25.049046 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9934 23:23:25.055596 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9935 23:23:25.059444 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9936 23:23:25.065788 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9937 23:23:25.068711 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9938 23:23:25.075449 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9939 23:23:25.078552 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9940 23:23:25.085464 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9941 23:23:25.088685 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9942 23:23:25.092223 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9943 23:23:25.098371 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9944 23:23:25.102216 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9945 23:23:25.108291 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9946 23:23:25.111370 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9947 23:23:25.118286 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9948 23:23:25.121204 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9949 23:23:25.128107 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9950 23:23:25.131537 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9951 23:23:25.134742 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9952 23:23:25.140846 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9953 23:23:25.144524 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9954 23:23:25.151201 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9955 23:23:25.154313 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9956 23:23:25.161199 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9957 23:23:25.164557 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9958 23:23:25.171111 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9959 23:23:25.174843 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9960 23:23:25.177397 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9961 23:23:25.184316 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9962 23:23:25.187656 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9963 23:23:25.194015 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9964 23:23:25.197466 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9965 23:23:25.203950 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9966 23:23:25.207143 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9967 23:23:25.213848 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9968 23:23:25.217469 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9969 23:23:25.220816 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9970 23:23:25.226755 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9971 23:23:25.230299 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9972 23:23:25.236905 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9973 23:23:25.240014 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9974 23:23:25.246677 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9975 23:23:25.250276 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9976 23:23:25.253087 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9977 23:23:25.259875 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9978 23:23:25.263178 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9979 23:23:25.269802 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9980 23:23:25.273407 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9981 23:23:25.279346 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9982 23:23:25.283367 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9983 23:23:25.289546 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9984 23:23:25.292605 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9985 23:23:25.296287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9986 23:23:25.302893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9987 23:23:25.305664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9988 23:23:25.312492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9989 23:23:25.315882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9990 23:23:25.322716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9991 23:23:25.325458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9992 23:23:25.332945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9993 23:23:25.335515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9994 23:23:25.342359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9995 23:23:25.345441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9996 23:23:25.352062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9997 23:23:25.355512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9998 23:23:25.362004 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9999 23:23:25.365638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10000 23:23:25.371868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10001 23:23:25.375302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10002 23:23:25.381832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10003 23:23:25.385155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10004 23:23:25.391700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10005 23:23:25.394803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10006 23:23:25.401152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10007 23:23:25.404791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10008 23:23:25.411732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10009 23:23:25.414416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10010 23:23:25.421262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10011 23:23:25.424656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10012 23:23:25.430937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10013 23:23:25.434425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10014 23:23:25.441205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10015 23:23:25.444233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10016 23:23:25.450496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10017 23:23:25.454134 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10018 23:23:25.457556 INFO: [APUAPC] vio 0
10019 23:23:25.460591 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10020 23:23:25.467543 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10021 23:23:25.470650 INFO: [APUAPC] D0_APC_0: 0x400510
10022 23:23:25.474069 INFO: [APUAPC] D0_APC_1: 0x0
10023 23:23:25.474156 INFO: [APUAPC] D0_APC_2: 0x1540
10024 23:23:25.477546 INFO: [APUAPC] D0_APC_3: 0x0
10025 23:23:25.480486 INFO: [APUAPC] D1_APC_0: 0xffffffff
10026 23:23:25.483910 INFO: [APUAPC] D1_APC_1: 0xffffffff
10027 23:23:25.486843 INFO: [APUAPC] D1_APC_2: 0x3fffff
10028 23:23:25.490103 INFO: [APUAPC] D1_APC_3: 0x0
10029 23:23:25.493212 INFO: [APUAPC] D2_APC_0: 0xffffffff
10030 23:23:25.497101 INFO: [APUAPC] D2_APC_1: 0xffffffff
10031 23:23:25.499959 INFO: [APUAPC] D2_APC_2: 0x3fffff
10032 23:23:25.503283 INFO: [APUAPC] D2_APC_3: 0x0
10033 23:23:25.506671 INFO: [APUAPC] D3_APC_0: 0xffffffff
10034 23:23:25.509778 INFO: [APUAPC] D3_APC_1: 0xffffffff
10035 23:23:25.513446 INFO: [APUAPC] D3_APC_2: 0x3fffff
10036 23:23:25.516771 INFO: [APUAPC] D3_APC_3: 0x0
10037 23:23:25.519513 INFO: [APUAPC] D4_APC_0: 0xffffffff
10038 23:23:25.522777 INFO: [APUAPC] D4_APC_1: 0xffffffff
10039 23:23:25.525946 INFO: [APUAPC] D4_APC_2: 0x3fffff
10040 23:23:25.529303 INFO: [APUAPC] D4_APC_3: 0x0
10041 23:23:25.532754 INFO: [APUAPC] D5_APC_0: 0xffffffff
10042 23:23:25.536074 INFO: [APUAPC] D5_APC_1: 0xffffffff
10043 23:23:25.539475 INFO: [APUAPC] D5_APC_2: 0x3fffff
10044 23:23:25.543005 INFO: [APUAPC] D5_APC_3: 0x0
10045 23:23:25.545931 INFO: [APUAPC] D6_APC_0: 0xffffffff
10046 23:23:25.549633 INFO: [APUAPC] D6_APC_1: 0xffffffff
10047 23:23:25.552463 INFO: [APUAPC] D6_APC_2: 0x3fffff
10048 23:23:25.555932 INFO: [APUAPC] D6_APC_3: 0x0
10049 23:23:25.559746 INFO: [APUAPC] D7_APC_0: 0xffffffff
10050 23:23:25.562381 INFO: [APUAPC] D7_APC_1: 0xffffffff
10051 23:23:25.565659 INFO: [APUAPC] D7_APC_2: 0x3fffff
10052 23:23:25.569263 INFO: [APUAPC] D7_APC_3: 0x0
10053 23:23:25.572361 INFO: [APUAPC] D8_APC_0: 0xffffffff
10054 23:23:25.575789 INFO: [APUAPC] D8_APC_1: 0xffffffff
10055 23:23:25.578911 INFO: [APUAPC] D8_APC_2: 0x3fffff
10056 23:23:25.582309 INFO: [APUAPC] D8_APC_3: 0x0
10057 23:23:25.585403 INFO: [APUAPC] D9_APC_0: 0xffffffff
10058 23:23:25.588636 INFO: [APUAPC] D9_APC_1: 0xffffffff
10059 23:23:25.592488 INFO: [APUAPC] D9_APC_2: 0x3fffff
10060 23:23:25.594969 INFO: [APUAPC] D9_APC_3: 0x0
10061 23:23:25.598536 INFO: [APUAPC] D10_APC_0: 0xffffffff
10062 23:23:25.601954 INFO: [APUAPC] D10_APC_1: 0xffffffff
10063 23:23:25.605361 INFO: [APUAPC] D10_APC_2: 0x3fffff
10064 23:23:25.608623 INFO: [APUAPC] D10_APC_3: 0x0
10065 23:23:25.611795 INFO: [APUAPC] D11_APC_0: 0xffffffff
10066 23:23:25.615181 INFO: [APUAPC] D11_APC_1: 0xffffffff
10067 23:23:25.618498 INFO: [APUAPC] D11_APC_2: 0x3fffff
10068 23:23:25.622002 INFO: [APUAPC] D11_APC_3: 0x0
10069 23:23:25.625212 INFO: [APUAPC] D12_APC_0: 0xffffffff
10070 23:23:25.628440 INFO: [APUAPC] D12_APC_1: 0xffffffff
10071 23:23:25.631437 INFO: [APUAPC] D12_APC_2: 0x3fffff
10072 23:23:25.634877 INFO: [APUAPC] D12_APC_3: 0x0
10073 23:23:25.638407 INFO: [APUAPC] D13_APC_0: 0xffffffff
10074 23:23:25.641303 INFO: [APUAPC] D13_APC_1: 0xffffffff
10075 23:23:25.644508 INFO: [APUAPC] D13_APC_2: 0x3fffff
10076 23:23:25.648230 INFO: [APUAPC] D13_APC_3: 0x0
10077 23:23:25.651103 INFO: [APUAPC] D14_APC_0: 0xffffffff
10078 23:23:25.654761 INFO: [APUAPC] D14_APC_1: 0xffffffff
10079 23:23:25.657958 INFO: [APUAPC] D14_APC_2: 0x3fffff
10080 23:23:25.661197 INFO: [APUAPC] D14_APC_3: 0x0
10081 23:23:25.664914 INFO: [APUAPC] D15_APC_0: 0xffffffff
10082 23:23:25.667979 INFO: [APUAPC] D15_APC_1: 0xffffffff
10083 23:23:25.671532 INFO: [APUAPC] D15_APC_2: 0x3fffff
10084 23:23:25.674501 INFO: [APUAPC] D15_APC_3: 0x0
10085 23:23:25.678004 INFO: [APUAPC] APC_CON: 0x4
10086 23:23:25.681073 INFO: [NOCDAPC] D0_APC_0: 0x0
10087 23:23:25.684397 INFO: [NOCDAPC] D0_APC_1: 0x0
10088 23:23:25.687334 INFO: [NOCDAPC] D1_APC_0: 0x0
10089 23:23:25.691260 INFO: [NOCDAPC] D1_APC_1: 0xfff
10090 23:23:25.694776 INFO: [NOCDAPC] D2_APC_0: 0x0
10091 23:23:25.697906 INFO: [NOCDAPC] D2_APC_1: 0xfff
10092 23:23:25.697995 INFO: [NOCDAPC] D3_APC_0: 0x0
10093 23:23:25.700931 INFO: [NOCDAPC] D3_APC_1: 0xfff
10094 23:23:25.704449 INFO: [NOCDAPC] D4_APC_0: 0x0
10095 23:23:25.707202 INFO: [NOCDAPC] D4_APC_1: 0xfff
10096 23:23:25.710898 INFO: [NOCDAPC] D5_APC_0: 0x0
10097 23:23:25.714150 INFO: [NOCDAPC] D5_APC_1: 0xfff
10098 23:23:25.717477 INFO: [NOCDAPC] D6_APC_0: 0x0
10099 23:23:25.721038 INFO: [NOCDAPC] D6_APC_1: 0xfff
10100 23:23:25.723568 INFO: [NOCDAPC] D7_APC_0: 0x0
10101 23:23:25.727065 INFO: [NOCDAPC] D7_APC_1: 0xfff
10102 23:23:25.730875 INFO: [NOCDAPC] D8_APC_0: 0x0
10103 23:23:25.733552 INFO: [NOCDAPC] D8_APC_1: 0xfff
10104 23:23:25.737103 INFO: [NOCDAPC] D9_APC_0: 0x0
10105 23:23:25.737177 INFO: [NOCDAPC] D9_APC_1: 0xfff
10106 23:23:25.740390 INFO: [NOCDAPC] D10_APC_0: 0x0
10107 23:23:25.743842 INFO: [NOCDAPC] D10_APC_1: 0xfff
10108 23:23:25.747084 INFO: [NOCDAPC] D11_APC_0: 0x0
10109 23:23:25.750333 INFO: [NOCDAPC] D11_APC_1: 0xfff
10110 23:23:25.753456 INFO: [NOCDAPC] D12_APC_0: 0x0
10111 23:23:25.756570 INFO: [NOCDAPC] D12_APC_1: 0xfff
10112 23:23:25.759838 INFO: [NOCDAPC] D13_APC_0: 0x0
10113 23:23:25.763077 INFO: [NOCDAPC] D13_APC_1: 0xfff
10114 23:23:25.766202 INFO: [NOCDAPC] D14_APC_0: 0x0
10115 23:23:25.769622 INFO: [NOCDAPC] D14_APC_1: 0xfff
10116 23:23:25.773203 INFO: [NOCDAPC] D15_APC_0: 0x0
10117 23:23:25.776308 INFO: [NOCDAPC] D15_APC_1: 0xfff
10118 23:23:25.779524 INFO: [NOCDAPC] APC_CON: 0x4
10119 23:23:25.782725 INFO: [APUAPC] set_apusys_apc done
10120 23:23:25.786125 INFO: [DEVAPC] devapc_init done
10121 23:23:25.789405 INFO: GICv3 without legacy support detected.
10122 23:23:25.792704 INFO: ARM GICv3 driver initialized in EL3
10123 23:23:25.795853 INFO: Maximum SPI INTID supported: 639
10124 23:23:25.799323 INFO: BL31: Initializing runtime services
10125 23:23:25.805930 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10126 23:23:25.809388 INFO: SPM: enable CPC mode
10127 23:23:25.816513 INFO: mcdi ready for mcusys-off-idle and system suspend
10128 23:23:25.819049 INFO: BL31: Preparing for EL3 exit to normal world
10129 23:23:25.822105 INFO: Entry point address = 0x80000000
10130 23:23:25.825550 INFO: SPSR = 0x8
10131 23:23:25.830392
10132 23:23:25.830477
10133 23:23:25.830564
10134 23:23:25.833925 Starting depthcharge on Spherion...
10135 23:23:25.834012
10136 23:23:25.834098 Wipe memory regions:
10137 23:23:25.834179
10138 23:23:25.834862 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10139 23:23:25.834980 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10140 23:23:25.835066 Setting prompt string to ['asurada:']
10141 23:23:25.835153 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10142 23:23:25.836936 [0x00000040000000, 0x00000054600000)
10143 23:23:25.959460
10144 23:23:25.959594 [0x00000054660000, 0x00000080000000)
10145 23:23:26.220051
10146 23:23:26.220200 [0x000000821a7280, 0x000000ffe64000)
10147 23:23:26.965112
10148 23:23:26.965271 [0x00000100000000, 0x00000240000000)
10149 23:23:28.854419
10150 23:23:28.857415 Initializing XHCI USB controller at 0x11200000.
10151 23:23:29.895596
10152 23:23:29.898879 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10153 23:23:29.898972
10154 23:23:29.899038
10155 23:23:29.899100
10156 23:23:29.899387 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10158 23:23:29.999757 asurada: tftpboot 192.168.201.1 13248465/tftp-deploy-_sc5ov9o/kernel/image.itb 13248465/tftp-deploy-_sc5ov9o/kernel/cmdline
10159 23:23:29.999912 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10160 23:23:30 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10161 23:23:30.004736 tftpboot 192.168.201.1 13248465/tftp-deploy-_sc5ov9o/kernel/image.itp-deploy-_sc5ov9o/kernel/cmdline
10162 23:23:30.004825
10163 23:23:30.004892 Waiting for link
10164 23:23:30.164996
10165 23:23:30.165148 R8152: Initializing
10166 23:23:30.165220
10167 23:23:30.168432 Version 6 (ocp_data = 5c30)
10168 23:23:30.168516
10169 23:23:30.171465 R8152: Done initializing
10170 23:23:30.171548
10171 23:23:30.171614 Adding net device
10172 23:23:32.074425
10173 23:23:32.074586 done.
10174 23:23:32.074663
10175 23:23:32.074727 MAC: 00:e0:4c:68:02:81
10176 23:23:32.074789
10177 23:23:32.078089 Sending DHCP discover... done.
10178 23:23:32.078175
10179 23:23:32.081052 Waiting for reply... done.
10180 23:23:32.081136
10181 23:23:32.084393 Sending DHCP request... done.
10182 23:23:32.084476
10183 23:23:32.088667 Waiting for reply... done.
10184 23:23:32.088772
10185 23:23:32.088925 My ip is 192.168.201.14
10186 23:23:32.089070
10187 23:23:32.091909 The DHCP server ip is 192.168.201.1
10188 23:23:32.091992
10189 23:23:32.098209 TFTP server IP predefined by user: 192.168.201.1
10190 23:23:32.098293
10191 23:23:32.105738 Bootfile predefined by user: 13248465/tftp-deploy-_sc5ov9o/kernel/image.itb
10192 23:23:32.105824
10193 23:23:32.108678 Sending tftp read request... done.
10194 23:23:32.108764
10195 23:23:32.112058 Waiting for the transfer...
10196 23:23:32.112181
10197 23:23:32.711170 00000000 ################################################################
10198 23:23:32.711326
10199 23:23:33.322385 00080000 ################################################################
10200 23:23:33.322534
10201 23:23:33.922367 00100000 ################################################################
10202 23:23:33.922539
10203 23:23:34.520553 00180000 ################################################################
10204 23:23:34.520758
10205 23:23:35.118240 00200000 ################################################################
10206 23:23:35.118426
10207 23:23:35.724840 00280000 ################################################################
10208 23:23:35.724994
10209 23:23:36.326122 00300000 ################################################################
10210 23:23:36.326276
10211 23:23:36.911355 00380000 ################################################################
10212 23:23:36.911498
10213 23:23:37.514234 00400000 ################################################################
10214 23:23:37.514388
10215 23:23:38.115327 00480000 ################################################################
10216 23:23:38.115471
10217 23:23:38.724256 00500000 ################################################################
10218 23:23:38.724415
10219 23:23:39.316111 00580000 ################################################################
10220 23:23:39.316260
10221 23:23:39.898399 00600000 ################################################################
10222 23:23:39.898603
10223 23:23:40.492771 00680000 ################################################################
10224 23:23:40.492926
10225 23:23:41.091849 00700000 ################################################################
10226 23:23:41.091994
10227 23:23:41.681169 00780000 ################################################################
10228 23:23:41.681323
10229 23:23:42.270843 00800000 ################################################################
10230 23:23:42.270997
10231 23:23:42.876241 00880000 ################################################################
10232 23:23:42.876396
10233 23:23:43.473398 00900000 ################################################################
10234 23:23:43.473554
10235 23:23:44.059563 00980000 ################################################################
10236 23:23:44.059757
10237 23:23:44.622057 00a00000 ################################################################
10238 23:23:44.622196
10239 23:23:45.207342 00a80000 ################################################################
10240 23:23:45.207503
10241 23:23:45.796170 00b00000 ################################################################
10242 23:23:45.796324
10243 23:23:46.412975 00b80000 ################################################################
10244 23:23:46.413131
10245 23:23:47.012383 00c00000 ################################################################
10246 23:23:47.012570
10247 23:23:47.595620 00c80000 ################################################################
10248 23:23:47.595821
10249 23:23:48.190270 00d00000 ################################################################
10250 23:23:48.190429
10251 23:23:48.791028 00d80000 ################################################################
10252 23:23:48.791179
10253 23:23:49.387732 00e00000 ################################################################
10254 23:23:49.387913
10255 23:23:49.991545 00e80000 ################################################################
10256 23:23:49.991716
10257 23:23:50.598413 00f00000 ################################################################
10258 23:23:50.598570
10259 23:23:51.212284 00f80000 ################################################################
10260 23:23:51.212447
10261 23:23:51.805302 01000000 ################################################################
10262 23:23:51.805453
10263 23:23:52.412993 01080000 ################################################################
10264 23:23:52.413168
10265 23:23:53.011050 01100000 ################################################################
10266 23:23:53.011191
10267 23:23:53.612876 01180000 ################################################################
10268 23:23:53.613014
10269 23:23:54.189983 01200000 ################################################################
10270 23:23:54.190136
10271 23:23:54.773343 01280000 ################################################################
10272 23:23:54.773485
10273 23:23:55.415964 01300000 ################################################################
10274 23:23:55.416129
10275 23:23:56.102909 01380000 ################################################################
10276 23:23:56.103102
10277 23:23:56.719994 01400000 ################################################################
10278 23:23:56.720150
10279 23:23:57.297770 01480000 ################################################################
10280 23:23:57.297910
10281 23:23:57.873454 01500000 ################################################################
10282 23:23:57.873604
10283 23:23:58.443312 01580000 ################################################################
10284 23:23:58.443458
10285 23:23:59.011607 01600000 ################################################################
10286 23:23:59.011800
10287 23:23:59.573648 01680000 ################################################################
10288 23:23:59.573785
10289 23:24:00.132817 01700000 ################################################################
10290 23:24:00.132981
10291 23:24:00.718526 01780000 ################################################################
10292 23:24:00.718682
10293 23:24:01.287408 01800000 ################################################################
10294 23:24:01.287585
10295 23:24:01.841376 01880000 ################################################################
10296 23:24:01.841529
10297 23:24:02.398507 01900000 ################################################################
10298 23:24:02.398729
10299 23:24:02.972488 01980000 ################################################################
10300 23:24:02.972645
10301 23:24:03.529586 01a00000 ################################################################
10302 23:24:03.529728
10303 23:24:04.086945 01a80000 ################################################################
10304 23:24:04.087082
10305 23:24:04.645113 01b00000 ################################################################
10306 23:24:04.645261
10307 23:24:05.212961 01b80000 ################################################################
10308 23:24:05.213101
10309 23:24:05.791632 01c00000 ################################################################
10310 23:24:05.791819
10311 23:24:06.362596 01c80000 ################################################################
10312 23:24:06.362771
10313 23:24:06.940771 01d00000 ################################################################
10314 23:24:06.940924
10315 23:24:07.496725 01d80000 ################################################################
10316 23:24:07.496877
10317 23:24:07.787041 01e00000 ################################## done.
10318 23:24:07.787190
10319 23:24:07.790133 The bootfile was 31730306 bytes long.
10320 23:24:07.790219
10321 23:24:07.793551 Sending tftp read request... done.
10322 23:24:07.793633
10323 23:24:07.793698 Waiting for the transfer...
10324 23:24:07.793759
10325 23:24:07.796758 00000000 # done.
10326 23:24:07.796842
10327 23:24:07.803152 Command line loaded dynamically from TFTP file: 13248465/tftp-deploy-_sc5ov9o/kernel/cmdline
10328 23:24:07.803265
10329 23:24:07.826428 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248465/extract-nfsrootfs-am49340a,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10330 23:24:07.826527
10331 23:24:07.826594 Loading FIT.
10332 23:24:07.826656
10333 23:24:07.829869 Image ramdisk-1 has 18773769 bytes.
10334 23:24:07.829952
10335 23:24:07.832972 Image fdt-1 has 47230 bytes.
10336 23:24:07.833055
10337 23:24:07.836766 Image kernel-1 has 12907270 bytes.
10338 23:24:07.836850
10339 23:24:07.845951 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10340 23:24:07.846035
10341 23:24:07.862597 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10342 23:24:07.862687
10343 23:24:07.868885 Choosing best match conf-1 for compat google,spherion-rev2.
10344 23:24:07.868969
10345 23:24:07.876545 Connected to device vid:did:rid of 1ae0:0028:00
10346 23:24:07.883244
10347 23:24:07.886734 tpm_get_response: command 0x17b, return code 0x0
10348 23:24:07.886844
10349 23:24:07.889905 ec_init: CrosEC protocol v3 supported (256, 248)
10350 23:24:07.894491
10351 23:24:07.897489 tpm_cleanup: add release locality here.
10352 23:24:07.897572
10353 23:24:07.897638 Shutting down all USB controllers.
10354 23:24:07.900758
10355 23:24:07.900840 Removing current net device
10356 23:24:07.900906
10357 23:24:07.907326 Exiting depthcharge with code 4 at timestamp: 71518010
10358 23:24:07.907435
10359 23:24:07.910418 LZMA decompressing kernel-1 to 0x821a6718
10360 23:24:07.910501
10361 23:24:07.913845 LZMA decompressing kernel-1 to 0x40000000
10362 23:24:09.507106
10363 23:24:09.507259 jumping to kernel
10364 23:24:09.507751 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10365 23:24:09.507852 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10366 23:24:09.507932 Setting prompt string to ['Linux version [0-9]']
10367 23:24:09.508003 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10368 23:24:09.508074 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10369 23:24:09.588995
10370 23:24:09.592150 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10371 23:24:09.595850 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10372 23:24:09.595943 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10373 23:24:09.596015 Setting prompt string to []
10374 23:24:09.596093 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10375 23:24:09.596167 Using line separator: #'\n'#
10376 23:24:09.596226 No login prompt set.
10377 23:24:09.596289 Parsing kernel messages
10378 23:24:09.596345 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10379 23:24:09.596449 [login-action] Waiting for messages, (timeout 00:03:41)
10380 23:24:09.596521 Waiting using forced prompt support (timeout 00:01:51)
10381 23:24:09.615357 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10382 23:24:09.618319 [ 0.000000] random: crng init done
10383 23:24:09.624947 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10384 23:24:09.628206 [ 0.000000] efi: UEFI not found.
10385 23:24:09.634669 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10386 23:24:09.644817 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10387 23:24:09.654559 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10388 23:24:09.661142 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10389 23:24:09.667586 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10390 23:24:09.674429 [ 0.000000] printk: bootconsole [mtk8250] enabled
10391 23:24:09.681107 [ 0.000000] NUMA: No NUMA configuration found
10392 23:24:09.687609 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10393 23:24:09.694154 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10394 23:24:09.694237 [ 0.000000] Zone ranges:
10395 23:24:09.700528 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10396 23:24:09.703970 [ 0.000000] DMA32 empty
10397 23:24:09.710528 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10398 23:24:09.713695 [ 0.000000] Movable zone start for each node
10399 23:24:09.717299 [ 0.000000] Early memory node ranges
10400 23:24:09.724211 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10401 23:24:09.730056 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10402 23:24:09.736905 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10403 23:24:09.743305 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10404 23:24:09.750179 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10405 23:24:09.756757 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10406 23:24:09.813590 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10407 23:24:09.819927 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10408 23:24:09.826806 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10409 23:24:09.830002 [ 0.000000] psci: probing for conduit method from DT.
10410 23:24:09.836913 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10411 23:24:09.840405 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10412 23:24:09.846401 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10413 23:24:09.849524 [ 0.000000] psci: SMC Calling Convention v1.2
10414 23:24:09.855906 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10415 23:24:09.859451 [ 0.000000] Detected VIPT I-cache on CPU0
10416 23:24:09.866005 [ 0.000000] CPU features: detected: GIC system register CPU interface
10417 23:24:09.872488 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10418 23:24:09.878951 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10419 23:24:09.886028 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10420 23:24:09.895743 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10421 23:24:09.902222 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10422 23:24:09.905435 [ 0.000000] alternatives: applying boot alternatives
10423 23:24:09.912698 [ 0.000000] Fallback order for Node 0: 0
10424 23:24:09.918971 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10425 23:24:09.922331 [ 0.000000] Policy zone: Normal
10426 23:24:09.945646 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248465/extract-nfsrootfs-am49340a,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10427 23:24:09.954823 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10428 23:24:09.965949 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10429 23:24:09.975861 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10430 23:24:09.982623 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10431 23:24:09.985742 <6>[ 0.000000] software IO TLB: area num 8.
10432 23:24:10.042381 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10433 23:24:10.192304 <6>[ 0.000000] Memory: 7946232K/8385536K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 406536K reserved, 32768K cma-reserved)
10434 23:24:10.198473 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10435 23:24:10.205039 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10436 23:24:10.208304 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10437 23:24:10.214817 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10438 23:24:10.221852 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10439 23:24:10.228296 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10440 23:24:10.234641 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10441 23:24:10.241363 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10442 23:24:10.248080 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10443 23:24:10.254722 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10444 23:24:10.257702 <6>[ 0.000000] GICv3: 608 SPIs implemented
10445 23:24:10.261180 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10446 23:24:10.267645 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10447 23:24:10.271570 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10448 23:24:10.277920 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10449 23:24:10.290916 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10450 23:24:10.304088 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10451 23:24:10.310430 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10452 23:24:10.318762 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10453 23:24:10.331939 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10454 23:24:10.338209 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10455 23:24:10.344929 <6>[ 0.009182] Console: colour dummy device 80x25
10456 23:24:10.355134 <6>[ 0.013936] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10457 23:24:10.361654 <6>[ 0.024378] pid_max: default: 32768 minimum: 301
10458 23:24:10.365179 <6>[ 0.029250] LSM: Security Framework initializing
10459 23:24:10.371742 <6>[ 0.034149] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10460 23:24:10.381291 <6>[ 0.042012] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10461 23:24:10.391090 <6>[ 0.051335] cblist_init_generic: Setting adjustable number of callback queues.
10462 23:24:10.397877 <6>[ 0.058827] cblist_init_generic: Setting shift to 3 and lim to 1.
10463 23:24:10.404363 <6>[ 0.065165] cblist_init_generic: Setting adjustable number of callback queues.
10464 23:24:10.411409 <6>[ 0.072591] cblist_init_generic: Setting shift to 3 and lim to 1.
10465 23:24:10.414222 <6>[ 0.078992] rcu: Hierarchical SRCU implementation.
10466 23:24:10.420694 <6>[ 0.084006] rcu: Max phase no-delay instances is 1000.
10467 23:24:10.427318 <6>[ 0.091030] EFI services will not be available.
10468 23:24:10.430449 <6>[ 0.095989] smp: Bringing up secondary CPUs ...
10469 23:24:10.439358 <6>[ 0.101012] Detected VIPT I-cache on CPU1
10470 23:24:10.445961 <6>[ 0.101072] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10471 23:24:10.452520 <6>[ 0.101096] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10472 23:24:10.455633 <6>[ 0.101415] Detected VIPT I-cache on CPU2
10473 23:24:10.465320 <6>[ 0.101466] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10474 23:24:10.472368 <6>[ 0.101483] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10475 23:24:10.475186 <6>[ 0.101742] Detected VIPT I-cache on CPU3
10476 23:24:10.481971 <6>[ 0.101790] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10477 23:24:10.488844 <6>[ 0.101804] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10478 23:24:10.495137 <6>[ 0.102113] CPU features: detected: Spectre-v4
10479 23:24:10.498757 <6>[ 0.102119] CPU features: detected: Spectre-BHB
10480 23:24:10.501963 <6>[ 0.102124] Detected PIPT I-cache on CPU4
10481 23:24:10.508475 <6>[ 0.102182] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10482 23:24:10.515304 <6>[ 0.102200] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10483 23:24:10.521841 <6>[ 0.102496] Detected PIPT I-cache on CPU5
10484 23:24:10.528180 <6>[ 0.102559] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10485 23:24:10.534684 <6>[ 0.102575] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10486 23:24:10.538107 <6>[ 0.102857] Detected PIPT I-cache on CPU6
10487 23:24:10.548276 <6>[ 0.102922] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10488 23:24:10.554376 <6>[ 0.102937] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10489 23:24:10.557855 <6>[ 0.103234] Detected PIPT I-cache on CPU7
10490 23:24:10.564299 <6>[ 0.103299] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10491 23:24:10.571170 <6>[ 0.103315] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10492 23:24:10.574381 <6>[ 0.103363] smp: Brought up 1 node, 8 CPUs
10493 23:24:10.580697 <6>[ 0.244580] SMP: Total of 8 processors activated.
10494 23:24:10.587236 <6>[ 0.249501] CPU features: detected: 32-bit EL0 Support
10495 23:24:10.593901 <6>[ 0.254864] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10496 23:24:10.600471 <6>[ 0.263665] CPU features: detected: Common not Private translations
10497 23:24:10.606877 <6>[ 0.270141] CPU features: detected: CRC32 instructions
10498 23:24:10.613333 <6>[ 0.275493] CPU features: detected: RCpc load-acquire (LDAPR)
10499 23:24:10.616797 <6>[ 0.281453] CPU features: detected: LSE atomic instructions
10500 23:24:10.623650 <6>[ 0.287235] CPU features: detected: Privileged Access Never
10501 23:24:10.629870 <6>[ 0.293051] CPU features: detected: RAS Extension Support
10502 23:24:10.637136 <6>[ 0.298694] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10503 23:24:10.639887 <6>[ 0.305916] CPU: All CPU(s) started at EL2
10504 23:24:10.646497 <6>[ 0.310232] alternatives: applying system-wide alternatives
10505 23:24:10.656509 <6>[ 0.321036] devtmpfs: initialized
10506 23:24:10.672543 <6>[ 0.329891] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10507 23:24:10.679397 <6>[ 0.339856] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10508 23:24:10.685774 <6>[ 0.348116] pinctrl core: initialized pinctrl subsystem
10509 23:24:10.689014 <6>[ 0.354784] DMI not present or invalid.
10510 23:24:10.695178 <6>[ 0.359196] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10511 23:24:10.705865 <6>[ 0.366090] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10512 23:24:10.712162 <6>[ 0.373678] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10513 23:24:10.721445 <6>[ 0.381905] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10514 23:24:10.728065 <6>[ 0.390152] audit: initializing netlink subsys (disabled)
10515 23:24:10.735050 <5>[ 0.395844] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10516 23:24:10.741781 <6>[ 0.396546] thermal_sys: Registered thermal governor 'step_wise'
10517 23:24:10.747899 <6>[ 0.403811] thermal_sys: Registered thermal governor 'power_allocator'
10518 23:24:10.750926 <6>[ 0.410065] cpuidle: using governor menu
10519 23:24:10.758124 <6>[ 0.421026] NET: Registered PF_QIPCRTR protocol family
10520 23:24:10.764392 <6>[ 0.426520] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10521 23:24:10.770832 <6>[ 0.433620] ASID allocator initialised with 32768 entries
10522 23:24:10.773710 <6>[ 0.440189] Serial: AMBA PL011 UART driver
10523 23:24:10.784800 <4>[ 0.449010] Trying to register duplicate clock ID: 134
10524 23:24:10.839097 <6>[ 0.506588] KASLR enabled
10525 23:24:10.853302 <6>[ 0.514328] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10526 23:24:10.859891 <6>[ 0.521342] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10527 23:24:10.866854 <6>[ 0.527835] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10528 23:24:10.873328 <6>[ 0.534838] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10529 23:24:10.880013 <6>[ 0.541327] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10530 23:24:10.886452 <6>[ 0.548332] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10531 23:24:10.892847 <6>[ 0.554817] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10532 23:24:10.899381 <6>[ 0.561818] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10533 23:24:10.902730 <6>[ 0.569343] ACPI: Interpreter disabled.
10534 23:24:10.911445 <6>[ 0.575808] iommu: Default domain type: Translated
10535 23:24:10.918351 <6>[ 0.580917] iommu: DMA domain TLB invalidation policy: strict mode
10536 23:24:10.921283 <5>[ 0.587575] SCSI subsystem initialized
10537 23:24:10.928746 <6>[ 0.591734] usbcore: registered new interface driver usbfs
10538 23:24:10.935024 <6>[ 0.597465] usbcore: registered new interface driver hub
10539 23:24:10.937818 <6>[ 0.603018] usbcore: registered new device driver usb
10540 23:24:10.945017 <6>[ 0.609120] pps_core: LinuxPPS API ver. 1 registered
10541 23:24:10.955136 <6>[ 0.614314] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10542 23:24:10.958017 <6>[ 0.623662] PTP clock support registered
10543 23:24:10.961725 <6>[ 0.627905] EDAC MC: Ver: 3.0.0
10544 23:24:10.969128 <6>[ 0.633078] FPGA manager framework
10545 23:24:10.975607 <6>[ 0.636759] Advanced Linux Sound Architecture Driver Initialized.
10546 23:24:10.978531 <6>[ 0.643539] vgaarb: loaded
10547 23:24:10.985697 <6>[ 0.646718] clocksource: Switched to clocksource arch_sys_counter
10548 23:24:10.988618 <5>[ 0.653153] VFS: Disk quotas dquot_6.6.0
10549 23:24:10.994969 <6>[ 0.657337] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10550 23:24:10.998191 <6>[ 0.664521] pnp: PnP ACPI: disabled
10551 23:24:11.007149 <6>[ 0.671115] NET: Registered PF_INET protocol family
10552 23:24:11.016976 <6>[ 0.676720] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10553 23:24:11.028198 <6>[ 0.689045] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10554 23:24:11.037978 <6>[ 0.697864] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10555 23:24:11.045183 <6>[ 0.705834] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10556 23:24:11.054269 <6>[ 0.714528] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10557 23:24:11.060954 <6>[ 0.724279] TCP: Hash tables configured (established 65536 bind 65536)
10558 23:24:11.067551 <6>[ 0.731141] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10559 23:24:11.077351 <6>[ 0.738343] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10560 23:24:11.084408 <6>[ 0.746043] NET: Registered PF_UNIX/PF_LOCAL protocol family
10561 23:24:11.091014 <6>[ 0.752194] RPC: Registered named UNIX socket transport module.
10562 23:24:11.093852 <6>[ 0.758350] RPC: Registered udp transport module.
10563 23:24:11.100475 <6>[ 0.763280] RPC: Registered tcp transport module.
10564 23:24:11.107492 <6>[ 0.768214] RPC: Registered tcp NFSv4.1 backchannel transport module.
10565 23:24:11.110051 <6>[ 0.774877] PCI: CLS 0 bytes, default 64
10566 23:24:11.113563 <6>[ 0.779214] Unpacking initramfs...
10567 23:24:11.137721 <6>[ 0.798836] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10568 23:24:11.147977 <6>[ 0.807509] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10569 23:24:11.151125 <6>[ 0.816367] kvm [1]: IPA Size Limit: 40 bits
10570 23:24:11.157603 <6>[ 0.820894] kvm [1]: GICv3: no GICV resource entry
10571 23:24:11.161262 <6>[ 0.825914] kvm [1]: disabling GICv2 emulation
10572 23:24:11.167851 <6>[ 0.830602] kvm [1]: GIC system register CPU interface enabled
10573 23:24:11.171053 <6>[ 0.836773] kvm [1]: vgic interrupt IRQ18
10574 23:24:11.177634 <6>[ 0.841122] kvm [1]: VHE mode initialized successfully
10575 23:24:11.184613 <5>[ 0.847557] Initialise system trusted keyrings
10576 23:24:11.190721 <6>[ 0.852343] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10577 23:24:11.198298 <6>[ 0.862298] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10578 23:24:11.204862 <5>[ 0.868713] NFS: Registering the id_resolver key type
10579 23:24:11.207893 <5>[ 0.874015] Key type id_resolver registered
10580 23:24:11.214658 <5>[ 0.878432] Key type id_legacy registered
10581 23:24:11.221434 <6>[ 0.882725] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10582 23:24:11.227754 <6>[ 0.889646] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10583 23:24:11.234255 <6>[ 0.897384] 9p: Installing v9fs 9p2000 file system support
10584 23:24:11.271628 <5>[ 0.935418] Key type asymmetric registered
10585 23:24:11.274634 <5>[ 0.939748] Asymmetric key parser 'x509' registered
10586 23:24:11.285053 <6>[ 0.944889] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10587 23:24:11.287829 <6>[ 0.952526] io scheduler mq-deadline registered
10588 23:24:11.290901 <6>[ 0.957289] io scheduler kyber registered
10589 23:24:11.310160 <6>[ 0.974410] EINJ: ACPI disabled.
10590 23:24:11.342922 <4>[ 1.000400] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10591 23:24:11.352312 <4>[ 1.011037] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 23:24:11.367667 <6>[ 1.031658] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10593 23:24:11.375534 <6>[ 1.039660] printk: console [ttyS0] disabled
10594 23:24:11.403569 <6>[ 1.064304] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10595 23:24:11.410180 <6>[ 1.073779] printk: console [ttyS0] enabled
10596 23:24:11.412995 <6>[ 1.073779] printk: console [ttyS0] enabled
10597 23:24:11.420138 <6>[ 1.082674] printk: bootconsole [mtk8250] disabled
10598 23:24:11.423386 <6>[ 1.082674] printk: bootconsole [mtk8250] disabled
10599 23:24:11.429730 <6>[ 1.094009] SuperH (H)SCI(F) driver initialized
10600 23:24:11.433414 <6>[ 1.099295] msm_serial: driver initialized
10601 23:24:11.447516 <6>[ 1.108260] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10602 23:24:11.457414 <6>[ 1.116810] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10603 23:24:11.463939 <6>[ 1.125352] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10604 23:24:11.473980 <6>[ 1.133981] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10605 23:24:11.484371 <6>[ 1.142693] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10606 23:24:11.490569 <6>[ 1.151414] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10607 23:24:11.500197 <6>[ 1.159955] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10608 23:24:11.506901 <6>[ 1.168762] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10609 23:24:11.516597 <6>[ 1.177306] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10610 23:24:11.529132 <6>[ 1.192845] loop: module loaded
10611 23:24:11.535122 <6>[ 1.198835] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10612 23:24:11.558030 <4>[ 1.222050] mtk-pmic-keys: Failed to locate of_node [id: -1]
10613 23:24:11.564919 <6>[ 1.229032] megasas: 07.719.03.00-rc1
10614 23:24:11.574664 <6>[ 1.238621] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10615 23:24:11.582572 <6>[ 1.246081] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10616 23:24:11.598596 <6>[ 1.262655] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10617 23:24:11.658917 <6>[ 1.316345] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10618 23:24:11.909364 <6>[ 1.573496] Freeing initrd memory: 18332K
10619 23:24:11.921104 <6>[ 1.585257] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10620 23:24:11.932148 <6>[ 1.596331] tun: Universal TUN/TAP device driver, 1.6
10621 23:24:11.935763 <6>[ 1.602409] thunder_xcv, ver 1.0
10622 23:24:11.938732 <6>[ 1.605915] thunder_bgx, ver 1.0
10623 23:24:11.942076 <6>[ 1.609410] nicpf, ver 1.0
10624 23:24:11.952555 <6>[ 1.613466] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10625 23:24:11.956147 <6>[ 1.620942] hns3: Copyright (c) 2017 Huawei Corporation.
10626 23:24:11.963036 <6>[ 1.626529] hclge is initializing
10627 23:24:11.965958 <6>[ 1.630110] e1000: Intel(R) PRO/1000 Network Driver
10628 23:24:11.972775 <6>[ 1.635239] e1000: Copyright (c) 1999-2006 Intel Corporation.
10629 23:24:11.975886 <6>[ 1.641254] e1000e: Intel(R) PRO/1000 Network Driver
10630 23:24:11.982785 <6>[ 1.646469] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10631 23:24:11.989056 <6>[ 1.652654] igb: Intel(R) Gigabit Ethernet Network Driver
10632 23:24:11.995992 <6>[ 1.658303] igb: Copyright (c) 2007-2014 Intel Corporation.
10633 23:24:12.002353 <6>[ 1.664139] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10634 23:24:12.009256 <6>[ 1.670657] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10635 23:24:12.012151 <6>[ 1.677130] sky2: driver version 1.30
10636 23:24:12.018768 <6>[ 1.682144] VFIO - User Level meta-driver version: 0.3
10637 23:24:12.026441 <6>[ 1.690421] usbcore: registered new interface driver usb-storage
10638 23:24:12.033050 <6>[ 1.696877] usbcore: registered new device driver onboard-usb-hub
10639 23:24:12.041866 <6>[ 1.706063] mt6397-rtc mt6359-rtc: registered as rtc0
10640 23:24:12.051855 <6>[ 1.711527] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:24:13 UTC (1712186653)
10641 23:24:12.055432 <6>[ 1.721103] i2c_dev: i2c /dev entries driver
10642 23:24:12.072115 <6>[ 1.732868] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10643 23:24:12.078729 <4>[ 1.741616] cpu cpu0: supply cpu not found, using dummy regulator
10644 23:24:12.085537 <4>[ 1.748055] cpu cpu1: supply cpu not found, using dummy regulator
10645 23:24:12.091662 <4>[ 1.754463] cpu cpu2: supply cpu not found, using dummy regulator
10646 23:24:12.099021 <4>[ 1.760859] cpu cpu3: supply cpu not found, using dummy regulator
10647 23:24:12.105043 <4>[ 1.767259] cpu cpu4: supply cpu not found, using dummy regulator
10648 23:24:12.112355 <4>[ 1.773656] cpu cpu5: supply cpu not found, using dummy regulator
10649 23:24:12.118195 <4>[ 1.780069] cpu cpu6: supply cpu not found, using dummy regulator
10650 23:24:12.125034 <4>[ 1.786467] cpu cpu7: supply cpu not found, using dummy regulator
10651 23:24:12.144019 <6>[ 1.808106] cpu cpu0: EM: created perf domain
10652 23:24:12.146985 <6>[ 1.813055] cpu cpu4: EM: created perf domain
10653 23:24:12.154454 <6>[ 1.818690] sdhci: Secure Digital Host Controller Interface driver
10654 23:24:12.161359 <6>[ 1.825122] sdhci: Copyright(c) Pierre Ossman
10655 23:24:12.167851 <6>[ 1.830098] Synopsys Designware Multimedia Card Interface Driver
10656 23:24:12.174465 <6>[ 1.836756] sdhci-pltfm: SDHCI platform and OF driver helper
10657 23:24:12.177785 <6>[ 1.836762] mmc0: CQHCI version 5.10
10658 23:24:12.184568 <6>[ 1.846693] ledtrig-cpu: registered to indicate activity on CPUs
10659 23:24:12.191112 <6>[ 1.853725] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10660 23:24:12.197394 <6>[ 1.860752] usbcore: registered new interface driver usbhid
10661 23:24:12.200840 <6>[ 1.866576] usbhid: USB HID core driver
10662 23:24:12.207105 <6>[ 1.870796] spi_master spi0: will run message pump with realtime priority
10663 23:24:12.253709 <6>[ 1.911218] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10664 23:24:12.273682 <6>[ 1.926982] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10665 23:24:12.277359 <6>[ 1.940790] mmc0: Command Queue Engine enabled
10666 23:24:12.283857 <6>[ 1.943800] cros-ec-spi spi0.0: Chrome EC device registered
10667 23:24:12.290892 <6>[ 1.945561] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10668 23:24:12.293607 <6>[ 1.958690] mmcblk0: mmc0:0001 DA4128 116 GiB
10669 23:24:12.306057 <6>[ 1.966175] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10670 23:24:12.312418 <6>[ 1.968452] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10671 23:24:12.318840 <6>[ 1.976767] NET: Registered PF_PACKET protocol family
10672 23:24:12.322095 <6>[ 1.982287] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10673 23:24:12.329097 <6>[ 1.986827] 9pnet: Installing 9P2000 support
10674 23:24:12.332366 <6>[ 1.992548] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10675 23:24:12.338768 <5>[ 1.996501] Key type dns_resolver registered
10676 23:24:12.345544 <6>[ 2.002231] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10677 23:24:12.349073 <6>[ 2.006702] registered taskstats version 1
10678 23:24:12.351743 <5>[ 2.017134] Loading compiled-in X.509 certificates
10679 23:24:12.380880 <4>[ 2.037841] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10680 23:24:12.391067 <4>[ 2.048546] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10681 23:24:12.397049 <3>[ 2.059073] debugfs: File 'uA_load' in directory '/' already present!
10682 23:24:12.404165 <3>[ 2.065772] debugfs: File 'min_uV' in directory '/' already present!
10683 23:24:12.410778 <3>[ 2.072380] debugfs: File 'max_uV' in directory '/' already present!
10684 23:24:12.416974 <3>[ 2.079055] debugfs: File 'constraint_flags' in directory '/' already present!
10685 23:24:12.428279 <3>[ 2.088713] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10686 23:24:12.437074 <6>[ 2.101026] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10687 23:24:12.444172 <6>[ 2.107964] xhci-mtk 11200000.usb: xHCI Host Controller
10688 23:24:12.450758 <6>[ 2.113469] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10689 23:24:12.460627 <6>[ 2.121312] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10690 23:24:12.467562 <6>[ 2.130755] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10691 23:24:12.474437 <6>[ 2.136837] xhci-mtk 11200000.usb: xHCI Host Controller
10692 23:24:12.481067 <6>[ 2.142317] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10693 23:24:12.487051 <6>[ 2.149963] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10694 23:24:12.494076 <6>[ 2.157829] hub 1-0:1.0: USB hub found
10695 23:24:12.497353 <6>[ 2.161870] hub 1-0:1.0: 1 port detected
10696 23:24:12.507086 <6>[ 2.166159] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10697 23:24:12.510626 <6>[ 2.175012] hub 2-0:1.0: USB hub found
10698 23:24:12.514073 <6>[ 2.179039] hub 2-0:1.0: 1 port detected
10699 23:24:12.523544 <6>[ 2.187280] mtk-msdc 11f70000.mmc: Got CD GPIO
10700 23:24:12.534987 <6>[ 2.195370] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10701 23:24:12.541564 <6>[ 2.203393] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10702 23:24:12.551464 <4>[ 2.211295] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10703 23:24:12.561194 <6>[ 2.220825] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10704 23:24:12.568014 <6>[ 2.228906] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10705 23:24:12.574786 <6>[ 2.237027] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10706 23:24:12.584499 <6>[ 2.244978] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10707 23:24:12.591399 <6>[ 2.252797] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10708 23:24:12.601088 <6>[ 2.260613] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10709 23:24:12.610854 <6>[ 2.271231] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10710 23:24:12.617908 <6>[ 2.279589] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10711 23:24:12.627540 <6>[ 2.287927] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10712 23:24:12.637692 <6>[ 2.296265] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10713 23:24:12.643811 <6>[ 2.304605] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10714 23:24:12.653965 <6>[ 2.312942] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10715 23:24:12.660594 <6>[ 2.321279] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10716 23:24:12.670705 <6>[ 2.329617] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10717 23:24:12.677271 <6>[ 2.337954] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10718 23:24:12.686967 <6>[ 2.346291] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10719 23:24:12.693418 <6>[ 2.354629] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10720 23:24:12.703053 <6>[ 2.362966] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10721 23:24:12.709746 <6>[ 2.371313] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10722 23:24:12.719491 <6>[ 2.379651] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10723 23:24:12.726292 <6>[ 2.387989] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10724 23:24:12.733239 <6>[ 2.396804] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10725 23:24:12.740070 <6>[ 2.404102] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10726 23:24:12.747366 <6>[ 2.411051] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10727 23:24:12.757593 <6>[ 2.417958] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10728 23:24:12.764230 <6>[ 2.425010] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10729 23:24:12.771188 <6>[ 2.431880] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10730 23:24:12.780610 <6>[ 2.441011] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10731 23:24:12.790798 <6>[ 2.450131] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10732 23:24:12.800084 <6>[ 2.459425] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10733 23:24:12.810029 <6>[ 2.468893] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10734 23:24:12.820021 <6>[ 2.478361] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10735 23:24:12.826725 <6>[ 2.487481] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10736 23:24:12.836669 <6>[ 2.496950] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10737 23:24:12.846529 <6>[ 2.506070] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10738 23:24:12.856500 <6>[ 2.515364] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10739 23:24:12.866439 <6>[ 2.525525] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10740 23:24:12.877394 <6>[ 2.537522] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10741 23:24:12.883713 <6>[ 2.547330] Trying to probe devices needed for running init ...
10742 23:24:12.918727 <6>[ 2.578852] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10743 23:24:13.072989 <6>[ 2.736637] hub 1-1:1.0: USB hub found
10744 23:24:13.076204 <6>[ 2.741179] hub 1-1:1.0: 4 ports detected
10745 23:24:13.085699 <6>[ 2.749920] hub 1-1:1.0: USB hub found
10746 23:24:13.089136 <6>[ 2.754331] hub 1-1:1.0: 4 ports detected
10747 23:24:13.199121 <6>[ 2.859329] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10748 23:24:13.225272 <6>[ 2.888905] hub 2-1:1.0: USB hub found
10749 23:24:13.228446 <6>[ 2.893436] hub 2-1:1.0: 3 ports detected
10750 23:24:13.237977 <6>[ 2.901500] hub 2-1:1.0: USB hub found
10751 23:24:13.241105 <6>[ 2.905957] hub 2-1:1.0: 3 ports detected
10752 23:24:13.414097 <6>[ 3.075020] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10753 23:24:13.546157 <6>[ 3.210235] hub 1-1.4:1.0: USB hub found
10754 23:24:13.549965 <6>[ 3.214891] hub 1-1.4:1.0: 2 ports detected
10755 23:24:13.558182 <6>[ 3.222190] hub 1-1.4:1.0: USB hub found
10756 23:24:13.561420 <6>[ 3.226727] hub 1-1.4:1.0: 2 ports detected
10757 23:24:13.630183 <6>[ 3.291126] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10758 23:24:13.858296 <6>[ 3.518999] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10759 23:24:14.050710 <6>[ 3.711011] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10760 23:24:25.163838 <6>[ 14.832069] ALSA device list:
10761 23:24:25.170261 <6>[ 14.835357] No soundcards found.
10762 23:24:25.178740 <6>[ 14.843366] Freeing unused kernel memory: 8448K
10763 23:24:25.181427 <6>[ 14.848853] Run /init as init process
10764 23:24:25.191779 Loading, please wait...
10765 23:24:25.216085 Starting systemd-udevd version 252.22-1~deb12u1
10766 23:24:25.216637
10767 23:24:25.498247 <6>[ 15.159930] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10768 23:24:25.508322 <6>[ 15.169368] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10769 23:24:25.511231 <6>[ 15.174039] remoteproc remoteproc0: scp is available
10770 23:24:25.521105 <6>[ 15.177048] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10771 23:24:25.527525 <6>[ 15.182439] remoteproc remoteproc0: powering up scp
10772 23:24:25.534693 <6>[ 15.193237] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10773 23:24:25.544443 <6>[ 15.196473] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10774 23:24:25.547407 <6>[ 15.196514] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10775 23:24:25.559056 <3>[ 15.220501] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 23:24:25.565760 <3>[ 15.228670] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10777 23:24:25.575213 <3>[ 15.236851] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10778 23:24:25.586645 <4>[ 15.248685] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10779 23:24:25.593034 <3>[ 15.256156] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10780 23:24:25.603779 <3>[ 15.264332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10781 23:24:25.610141 <4>[ 15.270568] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10782 23:24:25.616370 <3>[ 15.272490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 23:24:25.622649 <6>[ 15.286210] mc: Linux media interface: v0.10
10784 23:24:25.629216 <3>[ 15.287887] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10785 23:24:25.639724 <3>[ 15.287896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 23:24:25.646175 <3>[ 15.296315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10787 23:24:25.652615 <6>[ 15.302512] usbcore: registered new device driver r8152-cfgselector
10788 23:24:25.662485 <6>[ 15.308116] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10789 23:24:25.668847 <3>[ 15.308803] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 23:24:25.676034 <6>[ 15.323914] videodev: Linux video capture interface: v2.00
10791 23:24:25.683162 <6>[ 15.330421] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10792 23:24:25.685931 <6>[ 15.330426] pci_bus 0000:00: root bus resource [bus 00-ff]
10793 23:24:25.695627 <6>[ 15.330431] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10794 23:24:25.706353 <6>[ 15.330433] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10795 23:24:25.709061 <6>[ 15.330462] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10796 23:24:25.719001 <6>[ 15.330476] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10797 23:24:25.722072 <6>[ 15.330539] pci 0000:00:00.0: supports D1 D2
10798 23:24:25.728959 <6>[ 15.330541] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10799 23:24:25.736440 <3>[ 15.331356] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10800 23:24:25.746478 <6>[ 15.331834] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10801 23:24:25.752919 <6>[ 15.331927] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10802 23:24:25.759791 <6>[ 15.331952] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10803 23:24:25.766174 <6>[ 15.331968] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10804 23:24:25.775820 <6>[ 15.331983] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10805 23:24:25.779079 <6>[ 15.332099] pci 0000:01:00.0: supports D1 D2
10806 23:24:25.785300 <6>[ 15.332100] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10807 23:24:25.795735 <4>[ 15.332922] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10808 23:24:25.798846 <4>[ 15.332922] Fallback method does not support PEC.
10809 23:24:25.805358 <6>[ 15.343022] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10810 23:24:25.815528 <6>[ 15.343391] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10811 23:24:25.825256 <6>[ 15.344178] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10812 23:24:25.835771 <6>[ 15.344785] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10813 23:24:25.841870 <6>[ 15.344792] remoteproc remoteproc0: remote processor scp is now up
10814 23:24:25.848384 <6>[ 15.344804] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10815 23:24:25.855085 <3>[ 15.344850] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10816 23:24:25.865033 <6>[ 15.351913] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10817 23:24:25.871644 <6>[ 15.352871] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10818 23:24:25.880986 <6>[ 15.353922] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10819 23:24:25.888314 <3>[ 15.357477] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10820 23:24:25.897791 <6>[ 15.364585] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10821 23:24:25.904775 <3>[ 15.374467] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10822 23:24:25.914956 <3>[ 15.374471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 23:24:25.920741 <6>[ 15.380822] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10824 23:24:25.930547 <3>[ 15.382156] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10825 23:24:25.937649 <6>[ 15.386003] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10826 23:24:25.947404 <3>[ 15.388196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10827 23:24:25.954174 <3>[ 15.388199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10828 23:24:25.964034 <3>[ 15.388228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10829 23:24:25.970298 <6>[ 15.399579] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10830 23:24:25.980198 <6>[ 15.399664] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10831 23:24:25.986800 <3>[ 15.404519] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10832 23:24:25.993196 <6>[ 15.409775] Bluetooth: Core ver 2.22
10833 23:24:26.000087 <6>[ 15.416199] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10834 23:24:26.010152 <4>[ 15.422175] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10835 23:24:26.016917 <4>[ 15.422185] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10836 23:24:26.023204 <6>[ 15.422507] NET: Registered PF_BLUETOOTH protocol family
10837 23:24:26.026719 <6>[ 15.429849] pci 0000:00:00.0: PCI bridge to [bus 01]
10838 23:24:26.036187 <6>[ 15.429857] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10839 23:24:26.043375 <6>[ 15.430146] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10840 23:24:26.050276 <6>[ 15.437459] Bluetooth: HCI device and connection manager initialized
10841 23:24:26.056506 <6>[ 15.445585] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10842 23:24:26.062843 <6>[ 15.446007] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10843 23:24:26.072616 <6>[ 15.447358] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10844 23:24:26.079079 <6>[ 15.447486] usbcore: registered new interface driver uvcvideo
10845 23:24:26.085945 <6>[ 15.449362] Bluetooth: HCI socket layer initialized
10846 23:24:26.092365 <6>[ 15.456512] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10847 23:24:26.095611 <6>[ 15.466991] r8152 2-1.3:1.0 eth0: v1.12.13
10848 23:24:26.102216 <6>[ 15.467031] usbcore: registered new interface driver r8152
10849 23:24:26.105521 <6>[ 15.469916] Bluetooth: L2CAP socket layer initialized
10850 23:24:26.112400 <6>[ 15.469939] Bluetooth: SCO socket layer initialized
10851 23:24:26.118919 <6>[ 15.470842] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10852 23:24:26.125374 <6>[ 15.487328] usbcore: registered new interface driver cdc_ether
10853 23:24:26.131985 <5>[ 15.499807] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10854 23:24:26.139009 <6>[ 15.511321] usbcore: registered new interface driver r8153_ecm
10855 23:24:26.145216 <5>[ 15.530666] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10856 23:24:26.151572 <6>[ 15.535212] usbcore: registered new interface driver btusb
10857 23:24:26.161996 <4>[ 15.542969] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10858 23:24:26.168387 <5>[ 15.543041] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10859 23:24:26.178592 <4>[ 15.543135] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10860 23:24:26.184607 <6>[ 15.543146] cfg80211: failed to load regulatory.db
10861 23:24:26.187759 <6>[ 15.546543] r8152 2-1.3:1.0 enx00e04c680281: renamed from eth0
10862 23:24:26.194905 <3>[ 15.859984] Bluetooth: hci0: Failed to load firmware file (-2)
10863 23:24:26.201192 <3>[ 15.866152] Bluetooth: hci0: Failed to set up firmware (-2)
10864 23:24:26.211251 <4>[ 15.871979] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10865 23:24:26.252990 <6>[ 15.914965] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10866 23:24:26.259825 <6>[ 15.922662] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10867 23:24:26.284005 <6>[ 15.949557] mt7921e 0000:01:00.0: ASIC revision: 79610010
10868 23:24:26.389394 <6>[ 16.051004] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10869 23:24:26.392172 <6>[ 16.051004]
10870 23:24:26.401691 Begin: Loading essential drivers ... done.
10871 23:24:26.404030 Begin: Running /scripts/init-premount ... done.
10872 23:24:26.411421 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10873 23:24:26.420942 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10874 23:24:26.424239 Device /sys/class/net/enx00e04c680281 found
10875 23:24:26.424709 done.
10876 23:24:26.441693 Begin: Waiting up to 180 secs for any network device to become available ... done.
10877 23:24:26.488726 IP-Config: enx00e04c680281 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10878 23:24:26.655572 <6>[ 16.317750] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10879 23:24:27.359494 <6>[ 17.024766] r8152 2-1.3:1.0 enx00e04c680281: carrier on
10880 23:24:27.521731 <6>[ 17.186959] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10881 23:24:27.546295 IP-Config: no response after 2 secs - giving up
10882 23:24:27.584761 IP-Config: enx00e04c680281 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10883 23:24:27.609855 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:47 mtu 1500 DHCP
10884 23:24:28.302096 IP-Config: enx00e04c680281 complete (dhcp from 192.168.201.1):
10885 23:24:28.308340 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10886 23:24:28.318607 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10887 23:24:28.325183 host : mt8192-asurada-spherion-r0-cbg-9
10888 23:24:28.331702 domain : lava-rack
10889 23:24:28.334985 rootserver: 192.168.201.1 rootpath:
10890 23:24:28.335451 filename :
10891 23:24:28.462852 done.
10892 23:24:28.470597 Begin: Running /scripts/nfs-bottom ... done.
10893 23:24:28.482500 Begin: Running /scripts/init-bottom ... done.
10894 23:24:29.867549 <6>[ 19.533532] NET: Registered PF_INET6 protocol family
10895 23:24:29.875239 <6>[ 19.541217] Segment Routing with IPv6
10896 23:24:29.878385 <6>[ 19.545209] In-situ OAM (IOAM) with IPv6
10897 23:24:30.075444 <30>[ 19.714999] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10898 23:24:30.082148 <30>[ 19.748118] systemd[1]: Detected architecture arm64.
10899 23:24:30.091678
10900 23:24:30.094970 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10901 23:24:30.095118
10902 23:24:30.095213
10903 23:24:30.122725 <30>[ 19.788766] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10904 23:24:31.334682 <30>[ 20.996952] systemd[1]: Queued start job for default target graphical.target.
10905 23:24:31.373282 <30>[ 21.035973] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10906 23:24:31.379933 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10907 23:24:31.380195
10908 23:24:31.402054 <30>[ 21.064815] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10909 23:24:31.412233 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10910 23:24:31.412803
10911 23:24:31.430641 <30>[ 21.092723] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10912 23:24:31.440030 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10913 23:24:31.440803
10914 23:24:31.457628 <30>[ 21.120338] systemd[1]: Created slice user.slice - User and Session Slice.
10915 23:24:31.464838 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10916 23:24:31.465428
10917 23:24:31.487667 <30>[ 21.147322] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10918 23:24:31.494072 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10919 23:24:31.497350
10920 23:24:31.515343 <30>[ 21.175241] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10921 23:24:31.522346 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10922 23:24:31.522934
10923 23:24:31.550755 <30>[ 21.203667] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10924 23:24:31.561352 <30>[ 21.223587] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10925 23:24:31.567527 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10926 23:24:31.568108
10927 23:24:31.584815 <30>[ 21.247413] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10928 23:24:31.594719 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10929 23:24:31.595155
10930 23:24:31.612717 <30>[ 21.275538] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10931 23:24:31.622905 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10932 23:24:31.623341
10933 23:24:31.637054 <30>[ 21.303122] systemd[1]: Reached target paths.target - Path Units.
10934 23:24:31.643730 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10935 23:24:31.646848
10936 23:24:31.664969 <30>[ 21.327555] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10937 23:24:31.671563 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10938 23:24:31.672099
10939 23:24:31.684901 <30>[ 21.351004] systemd[1]: Reached target slices.target - Slice Units.
10940 23:24:31.694927 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10941 23:24:31.695365
10942 23:24:31.709786 <30>[ 21.375512] systemd[1]: Reached target swap.target - Swaps.
10943 23:24:31.716347 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10944 23:24:31.716807
10945 23:24:31.736682 <30>[ 21.399524] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10946 23:24:31.746397 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10947 23:24:31.746853
10948 23:24:31.765519 <30>[ 21.427970] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10949 23:24:31.775357 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10950 23:24:31.775944
10951 23:24:31.796476 <30>[ 21.459184] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10952 23:24:31.806584 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10953 23:24:31.807020
10954 23:24:31.825974 <30>[ 21.488677] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10955 23:24:31.835727 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10956 23:24:31.836225
10957 23:24:31.853065 <30>[ 21.515832] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10958 23:24:31.859849 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10959 23:24:31.860380
10960 23:24:31.877722 <30>[ 21.540702] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10961 23:24:31.887624 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10962 23:24:31.887751
10963 23:24:31.907618 <30>[ 21.570228] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10964 23:24:31.917604 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10965 23:24:31.918037
10966 23:24:31.932691 <30>[ 21.595474] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10967 23:24:31.942833 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10968 23:24:31.943364
10969 23:24:32.000588 <30>[ 21.663199] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10970 23:24:32.007066 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10971 23:24:32.007535
10972 23:24:32.028548 <30>[ 21.691384] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10973 23:24:32.035394 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10974 23:24:32.035864
10975 23:24:32.061442 <30>[ 21.724163] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10976 23:24:32.068184 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10977 23:24:32.068617
10978 23:24:32.095786 <30>[ 21.751354] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10979 23:24:32.136960 <30>[ 21.799863] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10980 23:24:32.147591 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10981 23:24:32.148323
10982 23:24:32.169747 <30>[ 21.832698] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10983 23:24:32.176713 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10984 23:24:32.177144
10985 23:24:32.200136 <30>[ 21.863188] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10986 23:24:32.207345 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10987 23:24:32.207811
10988 23:24:32.246520 <6>[ 21.909254] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10989 23:24:32.277516 <30>[ 21.940120] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10990 23:24:32.283720 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10991 23:24:32.284173
10992 23:24:32.314405 <30>[ 21.977039] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10993 23:24:32.324408 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10994 23:24:32.324840
10995 23:24:32.365049 <30>[ 22.027751] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10996 23:24:32.371977 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10997 23:24:32.372438
10998 23:24:32.398820 <30>[ 22.061238] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10999 23:24:32.408238 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 22.074277] fuse: init (API version 7.37)
11000 23:24:32.408717 el Module loop...
11001 23:24:32.409059
11002 23:24:32.437844 <30>[ 22.100766] systemd[1]: Starting systemd-journald.service - Journal Service...
11003 23:24:32.444561 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
11004 23:24:32.444656
11005 23:24:32.476660 <30>[ 22.139730] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
11006 23:24:32.483036 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
11007 23:24:32.483125
11008 23:24:32.514377 <30>[ 22.174132] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
11009 23:24:32.520808 Starting [0;1;39msystemd-network-g… units from Kernel command line...
11010 23:24:32.520894
11011 23:24:32.544748 <30>[ 22.207872] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
11012 23:24:32.554344 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
11013 23:24:32.554431
11014 23:24:32.579795 <30>[ 22.242103] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
11015 23:24:32.592771 Starting [0;1;39msyste<3>[ 22.253210] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11016 23:24:32.596747 md-udev-trig…[0m - Coldplug All udev Devices...
11017 23:24:32.597176
11018 23:24:32.622672 <3>[ 22.285421] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11019 23:24:32.629398 <30>[ 22.288456] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
11020 23:24:32.639484 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
11021 23:24:32.639963
11022 23:24:32.656867 <30>[ 22.319269] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
11023 23:24:32.663439 <3>[ 22.320485] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 23:24:32.673303 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
11025 23:24:32.673729
11026 23:24:32.693163 <30>[ 22.355451] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
11027 23:24:32.702898 [[0;32m OK [0m] Mounted [0;<3>[ 22.366089] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11028 23:24:32.709078 1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11029 23:24:32.709186
11030 23:24:32.733247 <30>[ 22.396003] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
11031 23:24:32.742801 <3>[ 22.396518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11032 23:24:32.749236 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11033 23:24:32.752623
11034 23:24:32.769514 <30>[ 22.432523] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11035 23:24:32.776233 <3>[ 22.436388] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11036 23:24:32.786856 <30>[ 22.440536] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11037 23:24:32.793533 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11038 23:24:32.794054
11039 23:24:32.807381 <3>[ 22.470274] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11040 23:24:32.818184 <30>[ 22.481230] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11041 23:24:32.824559 <30>[ 22.489292] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11042 23:24:32.842441 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m <3>[ 22.502474] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11043 23:24:32.843048 - Load Kernel Module dm_mod.
11044 23:24:32.843571
11045 23:24:32.866692 <30>[ 22.528776] systemd[1]: modprobe@drm.service: Deactivated successfully.
11046 23:24:32.873150 <30>[ 22.537007] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11047 23:24:32.882469 <3>[ 22.538357] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11048 23:24:32.889442 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11049 23:24:32.890063
11050 23:24:32.912931 <30>[ 22.575788] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11051 23:24:32.919850 <3>[ 22.576301] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11052 23:24:32.929156 <30>[ 22.584983] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11053 23:24:32.939489 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11054 23:24:32.940022
11055 23:24:32.957683 <30>[ 22.620328] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11056 23:24:32.964188 <30>[ 22.627850] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11057 23:24:32.974638 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11058 23:24:32.975059
11059 23:24:32.993562 <30>[ 22.655735] systemd[1]: Started systemd-journald.service - Journal Service.
11060 23:24:32.999321 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11061 23:24:32.999777
11062 23:24:33.018234 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11063 23:24:33.018658
11064 23:24:33.051203 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Ker<4>[ 22.706557] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11065 23:24:33.060825 <3>[ 22.722855] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11066 23:24:33.061253 nel Modules.
11067 23:24:33.061587
11068 23:24:33.079942 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11069 23:24:33.080369
11070 23:24:33.098723 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11071 23:24:33.099157
11072 23:24:33.117833 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11073 23:24:33.118343
11074 23:24:33.138951 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11075 23:24:33.139382
11076 23:24:33.189219 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11077 23:24:33.189663
11078 23:24:33.210653 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11079 23:24:33.210754
11080 23:24:33.233755 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11081 23:24:33.234230
11082 23:24:33.258713 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11083 23:24:33.259151
11084 23:24:33.285558 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11085 23:24:33.286024
11086 23:24:33.316041 Starting [0;1;39msystemd-sysusers.…r<46>[ 22.978340] systemd-journald[310]: Received client request to flush runtime journal.
11087 23:24:33.319126 vice[0m - Create System Users...
11088 23:24:33.319569
11089 23:24:33.351789 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11090 23:24:33.352387
11091 23:24:33.369319 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11092 23:24:33.369782
11093 23:24:33.393815 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11094 23:24:33.394308
11095 23:24:33.413653 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11096 23:24:33.414104
11097 23:24:34.095631 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11098 23:24:34.095802
11099 23:24:34.145280 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11100 23:24:34.145423
11101 23:24:34.727207 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11102 23:24:34.727357
11103 23:24:34.806405 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11104 23:24:34.807065
11105 23:24:34.824789 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11106 23:24:34.825365
11107 23:24:34.844197 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11108 23:24:34.844773
11109 23:24:34.896717 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11110 23:24:34.897306
11111 23:24:34.918085 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11112 23:24:34.918685
11113 23:24:35.197877 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11114 23:24:35.198380
11115 23:24:35.270958 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11116 23:24:35.271457
11117 23:24:35.307450 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11118 23:24:35.307958
11119 23:24:35.632365 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11120 23:24:35.632518
11121 23:24:35.675406 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11122 23:24:35.675565
11123 23:24:35.728337 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11124 23:24:35.728445
11125 23:24:35.814480 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11126 23:24:35.814619
11127 23:24:35.848592 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11128 23:24:35.848745
11129 23:24:35.868587 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11130 23:24:35.868849
11131 23:24:35.889232 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11132 23:24:35.889673
11133 23:24:35.910886 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11134 23:24:35.911444
11135 23:24:35.930875 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11136 23:24:35.931350
11137 23:24:35.993136 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11138 23:24:35.993656
11139 23:24:36.018572 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11140 23:24:36.019006
11141 23:24:36.040719 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11142 23:24:36.041151
11143 23:24:36.080969 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11144 23:24:36.081471
11145 23:24:36.190255 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11146 23:24:36.190870
11147 23:24:36.211096 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11148 23:24:36.211527
11149 23:24:36.228207 [[0;32m OK [0m] Started [0;<46>[ 25.893951] systemd-journald[310]: Time jumped backwards, rotating.
11150 23:24:36.234825 1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11151 23:24:36.235263
11152 23:24:36.264604 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11153 23:24:36.265034
11154 23:24:36.997964 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11155 23:24:36.998119
11156 23:24:37.329823 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11157 23:24:37.329976
11158 23:24:37.347221 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11159 23:24:37.347310
11160 23:24:37.701321 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11161 23:24:37.701485
11162 23:24:37.724058 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11163 23:24:37.724346
11164 23:24:37.739437 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11165 23:24:37.739795
11166 23:24:37.758425 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11167 23:24:37.759006
11168 23:24:37.776304 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11169 23:24:37.776867
11170 23:24:37.792226 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11171 23:24:37.792743
11172 23:24:37.845787 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11173 23:24:37.846345
11174 23:24:37.881780 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11175 23:24:37.882229
11176 23:24:37.936468 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11177 23:24:37.936927
11178 23:24:37.965569 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11179 23:24:37.966011
11180 23:24:38.178441 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11181 23:24:38.179138
11182 23:24:38.244718 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11183 23:24:38.245237
11184 23:24:38.289693 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11185 23:24:38.290194
11186 23:24:38.303238 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11187 23:24:38.303865
11188 23:24:38.321073 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11189 23:24:38.321528
11190 23:24:38.361734 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11191 23:24:38.362241
11192 23:24:38.390049 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11193 23:24:38.390484
11194 23:24:38.425170 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11195 23:24:38.425720
11196 23:24:38.445143 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11197 23:24:38.445731
11198 23:24:38.515501 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11199 23:24:38.516070
11200 23:24:38.540600 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11201 23:24:38.540725
11202 23:24:38.622101 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11203 23:24:38.622686
11204 23:24:38.643364 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11205 23:24:38.643849
11206 23:24:38.726502
11207 23:24:38.726663
11208 23:24:38.730035 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11209 23:24:38.730127
11210 23:24:38.733302 debian-bookworm-arm64 login: root (automatic login)
11211 23:24:38.733411
11212 23:24:38.733505
11213 23:24:39.084722 Linux debian-bookworm-arm64 6.1.83-cip18 #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024 aarch64
11214 23:24:39.085255
11215 23:24:39.091982 The programs included with the Debian GNU/Linux system are free software;
11216 23:24:39.098152 the exact distribution terms for each program are described in the
11217 23:24:39.101659 individual files in /usr/share/doc/*/copyright.
11218 23:24:39.102086
11219 23:24:39.108219 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11220 23:24:39.111063 permitted by applicable law.
11221 23:24:40.275380 Matched prompt #10: / #
11223 23:24:40.275768 Setting prompt string to ['/ #']
11224 23:24:40.275871 end: 2.2.5.1 login-action (duration 00:00:31) [common]
11226 23:24:40.276086 end: 2.2.5 auto-login-action (duration 00:00:31) [common]
11227 23:24:40.276198 start: 2.2.6 expect-shell-connection (timeout 00:03:11) [common]
11228 23:24:40.276281 Setting prompt string to ['/ #']
11229 23:24:40.276349 Forcing a shell prompt, looking for ['/ #']
11231 23:24:40.326648 / #
11232 23:24:40.327152 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11233 23:24:40.327525 Waiting using forced prompt support (timeout 00:02:30)
11234 23:24:40.333605
11235 23:24:40.334498 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11236 23:24:40.334997 start: 2.2.7 export-device-env (timeout 00:03:11) [common]
11238 23:24:40.436229 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248465/extract-nfsrootfs-am49340a'
11239 23:24:40.442465 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248465/extract-nfsrootfs-am49340a'
11241 23:24:40.544263 / # export NFS_SERVER_IP='192.168.201.1'
11242 23:24:40.550837 export NFS_SERVER_IP='192.168.201.1'
11243 23:24:40.551903 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11244 23:24:40.552509 end: 2.2 depthcharge-retry (duration 00:01:50) [common]
11245 23:24:40.553040 end: 2 depthcharge-action (duration 00:01:50) [common]
11246 23:24:40.553556 start: 3 lava-test-retry (timeout 00:07:25) [common]
11247 23:24:40.554037 start: 3.1 lava-test-shell (timeout 00:07:25) [common]
11248 23:24:40.554466 Using namespace: common
11250 23:24:40.655608 / # #
11251 23:24:40.656333 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11252 23:24:40.662773 #
11253 23:24:40.663541 Using /lava-13248465
11255 23:24:40.764805 / # export SHELL=/bin/bash
11256 23:24:40.770655 export SHELL=/bin/bash
11258 23:24:40.872036 / # . /lava-13248465/environment
11259 23:24:40.878564 . /lava-13248465/environment
11261 23:24:40.986233 / # /lava-13248465/bin/lava-test-runner /lava-13248465/0
11262 23:24:40.986376 Test shell timeout: 10s (minimum of the action and connection timeout)
11263 23:24:40.991452 /lava-13248465/bin/lava-test-runner /lava-13248465/0
11264 23:24:41.315721 + export TESTRUN_ID=0_timesync-off
11265 23:24:41.318135 + TESTRUN_ID=0_timesync-off
11266 23:24:41.321839 + cd /lava-13248465/0/tests/0_timesync-off
11267 23:24:41.324786 ++ cat uuid
11268 23:24:41.334320 + UUID=13248465_1.6.2.3.1
11269 23:24:41.334746 + set +x
11270 23:24:41.341838 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13248465_1.6.2.3.1>
11271 23:24:41.342630 Received signal: <STARTRUN> 0_timesync-off 13248465_1.6.2.3.1
11272 23:24:41.343020 Starting test lava.0_timesync-off (13248465_1.6.2.3.1)
11273 23:24:41.343442 Skipping test definition patterns.
11274 23:24:41.344270 + systemctl stop systemd-timesyncd
11275 23:24:41.418548 + set +x
11276 23:24:41.421299 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13248465_1.6.2.3.1>
11277 23:24:41.422046 Received signal: <ENDRUN> 0_timesync-off 13248465_1.6.2.3.1
11278 23:24:41.422459 Ending use of test pattern.
11279 23:24:41.422787 Ending test lava.0_timesync-off (13248465_1.6.2.3.1), duration 0.08
11281 23:24:41.521079 + export TESTRUN_ID=1_kselftest-rtc
11282 23:24:41.523972 + TESTRUN_ID=1_kselftest-rtc
11283 23:24:41.527123 + cd /lava-13248465/0/tests/1_kselftest-rtc
11284 23:24:41.530410 ++ cat uuid
11285 23:24:41.541949 + UUID=13248465_1.6.2.3.5
11286 23:24:41.542380 + set +x
11287 23:24:41.548379 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 13248465_1.6.2.3.5>
11288 23:24:41.549342 Received signal: <STARTRUN> 1_kselftest-rtc 13248465_1.6.2.3.5
11289 23:24:41.549932 Starting test lava.1_kselftest-rtc (13248465_1.6.2.3.5)
11290 23:24:41.550633 Skipping test definition patterns.
11291 23:24:41.551806 + cd ./automated/linux/kselftest/
11292 23:24:41.577565 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11293 23:24:41.634708 INFO: install_deps skipped
11294 23:24:42.160255 --2024-04-03 23:24:42-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11295 23:24:42.166307 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11296 23:24:42.297991 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11297 23:24:42.426731 HTTP request sent, awaiting response... 200 OK
11298 23:24:42.430029 Length: 1651420 (1.6M) [application/octet-stream]
11299 23:24:42.433294 Saving to: 'kselftest_armhf.tar.gz'
11300 23:24:42.433679
11301 23:24:42.434003
11302 23:24:42.686046 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11303 23:24:42.943961 kselftest_armhf.tar 2%[ ] 47.81K 185KB/s
11304 23:24:43.249243 kselftest_armhf.tar 13%[=> ] 217.50K 421KB/s
11305 23:24:43.381666 kselftest_armhf.tar 49%[========> ] 804.33K 978KB/s
11306 23:24:43.388085 kselftest_armhf.tar 100%[===================>] 1.57M 1.65MB/s in 1.0s
11307 23:24:43.388554
11308 23:24:43.536316 2024-04-03 23:24:43 (1.65 MB/s) - 'kselftest_armhf.tar.gz' saved [1651420/1651420]
11309 23:24:43.536839
11310 23:24:49.274829 skiplist:
11311 23:24:49.278288 ========================================
11312 23:24:49.280967 ========================================
11313 23:24:49.337413 rtc:rtctest
11314 23:24:49.360282 ============== Tests to run ===============
11315 23:24:49.360380 rtc:rtctest
11316 23:24:49.366706 ===========End Tests to run ===============
11317 23:24:49.369919 shardfile-rtc pass
11318 23:24:49.494779 <12>[ 39.162895] kselftest: Running tests in rtc
11319 23:24:49.505650 TAP version 13
11320 23:24:49.523320 1..1
11321 23:24:49.562136 # selftests: rtc: rtctest
11322 23:24:50.066463 # TAP version 13
11323 23:24:50.067026 # 1..8
11324 23:24:50.070134 # # Starting 8 tests from 2 test cases.
11325 23:24:50.072569 # # RUN rtc.date_read ...
11326 23:24:50.079279 # # rtctest.c:49:date_read:Current RTC date/time is 03/04/2024 23:24:49.
11327 23:24:50.082427 # # OK rtc.date_read
11328 23:24:50.085940 # ok 1 rtc.date_read
11329 23:24:50.089434 # # RUN rtc.date_read_loop ...
11330 23:24:50.098911 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11331 23:24:56.487262 <6>[ 46.158989] vpu: disabling
11332 23:24:56.489988 <6>[ 46.162093] vproc2: disabling
11333 23:24:56.493954 <6>[ 46.165429] vproc1: disabling
11334 23:24:56.500335 <6>[ 46.169213] vaud18: disabling
11335 23:24:56.503774 <6>[ 46.173552] vsram_others: disabling
11336 23:24:56.507036 <6>[ 46.177782] va09: disabling
11337 23:24:56.510317 <6>[ 46.181166] vsram_md: disabling
11338 23:24:56.513631 <6>[ 46.184969] Vgpu: disabling
11339 23:25:20.017454 # # rtctest.c:115:date_read_loop:Performed 2629 RTC time reads.
11340 23:25:20.020793 # # OK rtc.date_read_loop
11341 23:25:20.024119 # ok 2 rtc.date_read_loop
11342 23:25:20.027048 # # RUN rtc.uie_read ...
11343 23:25:22.997403 # # OK rtc.uie_read
11344 23:25:23.000677 # ok 3 rtc.uie_read
11345 23:25:23.003847 # # RUN rtc.uie_select ...
11346 23:25:25.996929 # # OK rtc.uie_select
11347 23:25:26.000485 # ok 4 rtc.uie_select
11348 23:25:26.003732 # # RUN rtc.alarm_alm_set ...
11349 23:25:26.010121 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 23:25:29.
11350 23:25:26.013725 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11351 23:25:26.020039 # # alarm_alm_set: Test terminated by assertion
11352 23:25:26.023138 # # FAIL rtc.alarm_alm_set
11353 23:25:26.026673 # not ok 5 rtc.alarm_alm_set
11354 23:25:26.029724 # # RUN rtc.alarm_wkalm_set ...
11355 23:25:26.036759 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 03/04/2024 23:25:29.
11356 23:25:28.999375 # # OK rtc.alarm_wkalm_set
11357 23:25:29.000098 # ok 6 rtc.alarm_wkalm_set
11358 23:25:29.006444 # # RUN rtc.alarm_alm_set_minute ...
11359 23:25:29.009053 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 23:26:00.
11360 23:25:29.016039 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11361 23:25:29.022232 # # alarm_alm_set_minute: Test terminated by assertion
11362 23:25:29.025784 # # FAIL rtc.alarm_alm_set_minute
11363 23:25:29.029199 # not ok 7 rtc.alarm_alm_set_minute
11364 23:25:29.032735 # # RUN rtc.alarm_wkalm_set_minute ...
11365 23:25:29.039312 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 03/04/2024 23:26:00.
11366 23:25:59.995968 # # OK rtc.alarm_wkalm_set_minute
11367 23:25:59.999199 # ok 8 rtc.alarm_wkalm_set_minute
11368 23:26:00.002723 # # FAILED: 6 / 8 tests passed.
11369 23:26:00.005684 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11370 23:26:00.009155 not ok 1 selftests: rtc: rtctest # exit=1
11371 23:26:01.590348 rtc_rtctest_rtc_date_read pass
11372 23:26:01.594032 rtc_rtctest_rtc_date_read_loop pass
11373 23:26:01.597223 rtc_rtctest_rtc_uie_read pass
11374 23:26:01.600842 rtc_rtctest_rtc_uie_select pass
11375 23:26:01.603948 rtc_rtctest_rtc_alarm_alm_set fail
11376 23:26:01.607133 rtc_rtctest_rtc_alarm_wkalm_set pass
11377 23:26:01.610251 rtc_rtctest_rtc_alarm_alm_set_minute fail
11378 23:26:01.614323 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11379 23:26:01.617076 rtc_rtctest fail
11380 23:26:01.668866 + ../../utils/send-to-lava.sh ./output/result.txt
11381 23:26:01.762400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11382 23:26:01.763415 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11384 23:26:01.833848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11385 23:26:01.834773 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11387 23:26:01.906824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11388 23:26:01.907740 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11390 23:26:01.972628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11391 23:26:01.973418 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11393 23:26:02.040505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11394 23:26:02.041356 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11396 23:26:02.111621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11397 23:26:02.112545 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11399 23:26:02.179961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11400 23:26:02.180912 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11402 23:26:02.242601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11403 23:26:02.242874 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11405 23:26:02.300714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11406 23:26:02.300998 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11408 23:26:02.357986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11409 23:26:02.358104 + set +x
11410 23:26:02.358383 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11412 23:26:02.364752 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 13248465_1.6.2.3.5>
11413 23:26:02.365573 Received signal: <ENDRUN> 1_kselftest-rtc 13248465_1.6.2.3.5
11414 23:26:02.366080 Ending use of test pattern.
11415 23:26:02.366540 Ending test lava.1_kselftest-rtc (13248465_1.6.2.3.5), duration 80.82
11417 23:26:02.368461 ok: lava_test_shell seems to have completed
11418 23:26:02.369608 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11419 23:26:02.370195 end: 3.1 lava-test-shell (duration 00:01:22) [common]
11420 23:26:02.370771 end: 3 lava-test-retry (duration 00:01:22) [common]
11421 23:26:02.371433 start: 4 finalize (timeout 00:06:03) [common]
11422 23:26:02.372160 start: 4.1 power-off (timeout 00:00:30) [common]
11423 23:26:02.372995 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11424 23:26:02.452801 >> Command sent successfully.
11425 23:26:02.456711 Returned 0 in 0 seconds
11426 23:26:02.557506 end: 4.1 power-off (duration 00:00:00) [common]
11428 23:26:02.559015 start: 4.2 read-feedback (timeout 00:06:03) [common]
11430 23:26:02.561183 Listened to connection for namespace 'common' for up to 1s
11431 23:26:03.559978 Finalising connection for namespace 'common'
11432 23:26:03.560681 Disconnecting from shell: Finalise
11433 23:26:03.561101 / #
11434 23:26:03.662082 end: 4.2 read-feedback (duration 00:00:01) [common]
11435 23:26:03.662755 end: 4 finalize (duration 00:00:01) [common]
11436 23:26:03.663450 Cleaning after the job
11437 23:26:03.664026 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/ramdisk
11438 23:26:03.677286 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/kernel
11439 23:26:03.712910 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/dtb
11440 23:26:03.713207 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/nfsrootfs
11441 23:26:03.798557 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248465/tftp-deploy-_sc5ov9o/modules
11442 23:26:03.805739 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248465
11443 23:26:04.442846 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248465
11444 23:26:04.443033 Job finished correctly