Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
1 23:23:12.081619 lava-dispatcher, installed at version: 2024.01
2 23:23:12.081842 start: 0 validate
3 23:23:12.081984 Start time: 2024-04-03 23:23:12.081976+00:00 (UTC)
4 23:23:12.082119 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:23:12.082256 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:23:12.336707 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:23:12.336869 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:23:12.586610 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:23:12.586769 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:23:12.836993 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:23:12.837168 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:23:13.102376 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:23:13.102597 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:23:13.362598 validate duration: 1.28
16 23:23:13.362857 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:23:13.362956 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:23:13.363042 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:23:13.363171 Not decompressing ramdisk as can be used compressed.
20 23:23:13.363258 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:23:13.363322 saving as /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/ramdisk/initrd.cpio.gz
22 23:23:13.363391 total size: 5628169 (5 MB)
23 23:23:13.364533 progress 0 % (0 MB)
24 23:23:13.366269 progress 5 % (0 MB)
25 23:23:13.367965 progress 10 % (0 MB)
26 23:23:13.369414 progress 15 % (0 MB)
27 23:23:13.371386 progress 20 % (1 MB)
28 23:23:13.372983 progress 25 % (1 MB)
29 23:23:13.374720 progress 30 % (1 MB)
30 23:23:13.376307 progress 35 % (1 MB)
31 23:23:13.377716 progress 40 % (2 MB)
32 23:23:13.379360 progress 45 % (2 MB)
33 23:23:13.380781 progress 50 % (2 MB)
34 23:23:13.382352 progress 55 % (2 MB)
35 23:23:13.383973 progress 60 % (3 MB)
36 23:23:13.385388 progress 65 % (3 MB)
37 23:23:13.387074 progress 70 % (3 MB)
38 23:23:13.388484 progress 75 % (4 MB)
39 23:23:13.390055 progress 80 % (4 MB)
40 23:23:13.391517 progress 85 % (4 MB)
41 23:23:13.393237 progress 90 % (4 MB)
42 23:23:13.395121 progress 95 % (5 MB)
43 23:23:13.396608 progress 100 % (5 MB)
44 23:23:13.396825 5 MB downloaded in 0.03 s (160.55 MB/s)
45 23:23:13.396988 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:23:13.397233 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:23:13.397323 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:23:13.397409 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:23:13.397568 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:23:13.397652 saving as /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/kernel/Image
52 23:23:13.397716 total size: 54286848 (51 MB)
53 23:23:13.397778 No compression specified
54 23:23:13.399010 progress 0 % (0 MB)
55 23:23:13.413162 progress 5 % (2 MB)
56 23:23:13.427842 progress 10 % (5 MB)
57 23:23:13.442435 progress 15 % (7 MB)
58 23:23:13.456878 progress 20 % (10 MB)
59 23:23:13.472017 progress 25 % (12 MB)
60 23:23:13.486577 progress 30 % (15 MB)
61 23:23:13.500895 progress 35 % (18 MB)
62 23:23:13.515473 progress 40 % (20 MB)
63 23:23:13.529824 progress 45 % (23 MB)
64 23:23:13.544554 progress 50 % (25 MB)
65 23:23:13.559324 progress 55 % (28 MB)
66 23:23:13.573598 progress 60 % (31 MB)
67 23:23:13.588761 progress 65 % (33 MB)
68 23:23:13.603661 progress 70 % (36 MB)
69 23:23:13.618098 progress 75 % (38 MB)
70 23:23:13.632758 progress 80 % (41 MB)
71 23:23:13.648274 progress 85 % (44 MB)
72 23:23:13.663695 progress 90 % (46 MB)
73 23:23:13.679138 progress 95 % (49 MB)
74 23:23:13.694626 progress 100 % (51 MB)
75 23:23:13.694934 51 MB downloaded in 0.30 s (174.19 MB/s)
76 23:23:13.695149 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:23:13.695540 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:23:13.695669 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:23:13.695801 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:23:13.695989 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:23:13.696091 saving as /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/dtb/mt8192-asurada-spherion-r0.dtb
83 23:23:13.696192 total size: 47230 (0 MB)
84 23:23:13.696294 No compression specified
85 23:23:13.697986 progress 69 % (0 MB)
86 23:23:13.698312 progress 100 % (0 MB)
87 23:23:13.698562 0 MB downloaded in 0.00 s (19.03 MB/s)
88 23:23:13.698745 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:23:13.699124 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:23:13.699269 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:23:13.699409 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:23:13.699573 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:23:13.699669 saving as /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/nfsrootfs/full.rootfs.tar
95 23:23:13.699759 total size: 120894716 (115 MB)
96 23:23:13.699854 Using unxz to decompress xz
97 23:23:13.704933 progress 0 % (0 MB)
98 23:23:14.070166 progress 5 % (5 MB)
99 23:23:14.449875 progress 10 % (11 MB)
100 23:23:14.811249 progress 15 % (17 MB)
101 23:23:15.150548 progress 20 % (23 MB)
102 23:23:15.450271 progress 25 % (28 MB)
103 23:23:15.820467 progress 30 % (34 MB)
104 23:23:16.177042 progress 35 % (40 MB)
105 23:23:16.346121 progress 40 % (46 MB)
106 23:23:16.535400 progress 45 % (51 MB)
107 23:23:16.890419 progress 50 % (57 MB)
108 23:23:17.319251 progress 55 % (63 MB)
109 23:23:17.715839 progress 60 % (69 MB)
110 23:23:18.098959 progress 65 % (74 MB)
111 23:23:18.491413 progress 70 % (80 MB)
112 23:23:18.900236 progress 75 % (86 MB)
113 23:23:19.287523 progress 80 % (92 MB)
114 23:23:19.672144 progress 85 % (98 MB)
115 23:23:20.074618 progress 90 % (103 MB)
116 23:23:20.444086 progress 95 % (109 MB)
117 23:23:20.839492 progress 100 % (115 MB)
118 23:23:20.845640 115 MB downloaded in 7.15 s (16.13 MB/s)
119 23:23:20.845942 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:23:20.846254 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:23:20.846379 start: 1.5 download-retry (timeout 00:09:53) [common]
123 23:23:20.846513 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 23:23:20.846672 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:23:20.846743 saving as /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/modules/modules.tar
126 23:23:20.846805 total size: 8629908 (8 MB)
127 23:23:20.846870 Using unxz to decompress xz
128 23:23:20.851181 progress 0 % (0 MB)
129 23:23:20.871740 progress 5 % (0 MB)
130 23:23:20.897991 progress 10 % (0 MB)
131 23:23:20.922973 progress 15 % (1 MB)
132 23:23:20.947027 progress 20 % (1 MB)
133 23:23:20.972895 progress 25 % (2 MB)
134 23:23:20.999493 progress 30 % (2 MB)
135 23:23:21.024456 progress 35 % (2 MB)
136 23:23:21.050852 progress 40 % (3 MB)
137 23:23:21.075385 progress 45 % (3 MB)
138 23:23:21.101275 progress 50 % (4 MB)
139 23:23:21.126723 progress 55 % (4 MB)
140 23:23:21.155583 progress 60 % (4 MB)
141 23:23:21.182062 progress 65 % (5 MB)
142 23:23:21.208078 progress 70 % (5 MB)
143 23:23:21.233251 progress 75 % (6 MB)
144 23:23:21.259112 progress 80 % (6 MB)
145 23:23:21.285974 progress 85 % (7 MB)
146 23:23:21.315132 progress 90 % (7 MB)
147 23:23:21.345763 progress 95 % (7 MB)
148 23:23:21.372944 progress 100 % (8 MB)
149 23:23:21.378423 8 MB downloaded in 0.53 s (15.48 MB/s)
150 23:23:21.378695 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:23:21.378976 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:23:21.379072 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 23:23:21.379170 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 23:23:25.148520 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13248467/extract-nfsrootfs-gyhcfl92
156 23:23:25.148737 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:23:25.148836 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:23:25.149020 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3
159 23:23:25.149186 makedir: /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin
160 23:23:25.149299 makedir: /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/tests
161 23:23:25.149400 makedir: /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/results
162 23:23:25.149505 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-add-keys
163 23:23:25.149658 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-add-sources
164 23:23:25.149790 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-background-process-start
165 23:23:25.149920 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-background-process-stop
166 23:23:25.150051 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-common-functions
167 23:23:25.150180 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-echo-ipv4
168 23:23:25.150309 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-install-packages
169 23:23:25.150484 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-installed-packages
170 23:23:25.150613 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-os-build
171 23:23:25.150741 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-probe-channel
172 23:23:25.150869 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-probe-ip
173 23:23:25.150996 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-target-ip
174 23:23:25.151124 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-target-mac
175 23:23:25.151250 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-target-storage
176 23:23:25.151380 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-test-case
177 23:23:25.151511 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-test-event
178 23:23:25.151639 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-test-feedback
179 23:23:25.151766 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-test-raise
180 23:23:25.151893 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-test-reference
181 23:23:25.152022 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-test-runner
182 23:23:25.152153 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-test-set
183 23:23:25.152281 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-test-shell
184 23:23:25.152410 Updating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-add-keys (debian)
185 23:23:25.152567 Updating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-add-sources (debian)
186 23:23:25.152723 Updating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-install-packages (debian)
187 23:23:25.152929 Updating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-installed-packages (debian)
188 23:23:25.153120 Updating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/bin/lava-os-build (debian)
189 23:23:25.153261 Creating /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/environment
190 23:23:25.153362 LAVA metadata
191 23:23:25.153434 - LAVA_JOB_ID=13248467
192 23:23:25.153497 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:23:25.153612 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:23:25.153681 skipped lava-vland-overlay
195 23:23:25.153757 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:23:25.153838 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:23:25.153899 skipped lava-multinode-overlay
198 23:23:25.153970 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:23:25.154047 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:23:25.154123 Loading test definitions
201 23:23:25.154212 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:23:25.154282 Using /lava-13248467 at stage 0
203 23:23:25.154871 uuid=13248467_1.6.2.3.1 testdef=None
204 23:23:25.154962 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:23:25.155047 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:23:25.155511 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:23:25.155739 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:23:25.156344 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:23:25.156575 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:23:25.157235 runner path: /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/0/tests/0_timesync-off test_uuid 13248467_1.6.2.3.1
213 23:23:25.157399 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:23:25.157623 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:23:25.157695 Using /lava-13248467 at stage 0
217 23:23:25.157793 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:23:25.157881 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/0/tests/1_kselftest-tpm2'
219 23:23:29.809511 Running '/usr/bin/git checkout kernelci.org
220 23:23:29.960455 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 23:23:29.961221 uuid=13248467_1.6.2.3.5 testdef=None
222 23:23:29.961388 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 23:23:29.961676 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 23:23:29.962432 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:23:29.962663 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 23:23:29.963752 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:23:29.963991 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 23:23:29.964932 runner path: /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/0/tests/1_kselftest-tpm2 test_uuid 13248467_1.6.2.3.5
232 23:23:29.965024 BOARD='mt8192-asurada-spherion-r0'
233 23:23:29.965089 BRANCH='cip'
234 23:23:29.965149 SKIPFILE='/dev/null'
235 23:23:29.965207 SKIP_INSTALL='True'
236 23:23:29.965263 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:23:29.965322 TST_CASENAME=''
238 23:23:29.965377 TST_CMDFILES='tpm2'
239 23:23:29.965524 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:23:29.965735 Creating lava-test-runner.conf files
242 23:23:29.965798 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248467/lava-overlay-j1a42ru3/lava-13248467/0 for stage 0
243 23:23:29.965892 - 0_timesync-off
244 23:23:29.965964 - 1_kselftest-tpm2
245 23:23:29.966066 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 23:23:29.966153 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 23:23:37.739530 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:23:37.739694 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 23:23:37.739788 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:23:37.739892 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 23:23:37.739985 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 23:23:37.919237 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:23:37.919651 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 23:23:37.919771 extracting modules file /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248467/extract-nfsrootfs-gyhcfl92
255 23:23:38.164197 extracting modules file /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248467/extract-overlay-ramdisk-bpiuikp_/ramdisk
256 23:23:38.403466 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:23:38.403649 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 23:23:38.403746 [common] Applying overlay to NFS
259 23:23:38.403820 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248467/compress-overlay-fo3_nv6j/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248467/extract-nfsrootfs-gyhcfl92
260 23:23:39.370220 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:23:39.370400 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 23:23:39.370505 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:23:39.370598 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 23:23:39.370681 Building ramdisk /var/lib/lava/dispatcher/tmp/13248467/extract-overlay-ramdisk-bpiuikp_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248467/extract-overlay-ramdisk-bpiuikp_/ramdisk
265 23:23:39.765073 >> 130593 blocks
266 23:23:41.944784 rename /var/lib/lava/dispatcher/tmp/13248467/extract-overlay-ramdisk-bpiuikp_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/ramdisk/ramdisk.cpio.gz
267 23:23:41.945260 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 23:23:41.945412 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 23:23:41.945524 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 23:23:41.945642 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/kernel/Image'
271 23:23:55.730287 Returned 0 in 13 seconds
272 23:23:55.830990 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/kernel/image.itb
273 23:23:56.208110 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:23:56.208501 output: Created: Thu Apr 4 00:23:56 2024
275 23:23:56.208581 output: Image 0 (kernel-1)
276 23:23:56.208649 output: Description:
277 23:23:56.208715 output: Created: Thu Apr 4 00:23:56 2024
278 23:23:56.208775 output: Type: Kernel Image
279 23:23:56.208836 output: Compression: lzma compressed
280 23:23:56.208894 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
281 23:23:56.208954 output: Architecture: AArch64
282 23:23:56.209009 output: OS: Linux
283 23:23:56.209065 output: Load Address: 0x00000000
284 23:23:56.209121 output: Entry Point: 0x00000000
285 23:23:56.209178 output: Hash algo: crc32
286 23:23:56.209236 output: Hash value: d7c9dcc1
287 23:23:56.209294 output: Image 1 (fdt-1)
288 23:23:56.209350 output: Description: mt8192-asurada-spherion-r0
289 23:23:56.209403 output: Created: Thu Apr 4 00:23:56 2024
290 23:23:56.209457 output: Type: Flat Device Tree
291 23:23:56.209510 output: Compression: uncompressed
292 23:23:56.209563 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 23:23:56.209617 output: Architecture: AArch64
294 23:23:56.209670 output: Hash algo: crc32
295 23:23:56.209729 output: Hash value: 4bf0d1ac
296 23:23:56.209788 output: Image 2 (ramdisk-1)
297 23:23:56.209842 output: Description: unavailable
298 23:23:56.209894 output: Created: Thu Apr 4 00:23:56 2024
299 23:23:56.209947 output: Type: RAMDisk Image
300 23:23:56.210000 output: Compression: Unknown Compression
301 23:23:56.210053 output: Data Size: 18771126 Bytes = 18331.18 KiB = 17.90 MiB
302 23:23:56.210106 output: Architecture: AArch64
303 23:23:56.210158 output: OS: Linux
304 23:23:56.210211 output: Load Address: unavailable
305 23:23:56.210263 output: Entry Point: unavailable
306 23:23:56.210316 output: Hash algo: crc32
307 23:23:56.210368 output: Hash value: 2c98aee0
308 23:23:56.210472 output: Default Configuration: 'conf-1'
309 23:23:56.210527 output: Configuration 0 (conf-1)
310 23:23:56.210581 output: Description: mt8192-asurada-spherion-r0
311 23:23:56.210634 output: Kernel: kernel-1
312 23:23:56.210687 output: Init Ramdisk: ramdisk-1
313 23:23:56.210740 output: FDT: fdt-1
314 23:23:56.210793 output: Loadables: kernel-1
315 23:23:56.210846 output:
316 23:23:56.211050 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 23:23:56.211150 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 23:23:56.211251 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 23:23:56.211343 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 23:23:56.211426 No LXC device requested
321 23:23:56.211505 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:23:56.211594 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 23:23:56.211672 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:23:56.211745 Checking files for TFTP limit of 4294967296 bytes.
325 23:23:56.212260 end: 1 tftp-deploy (duration 00:00:43) [common]
326 23:23:56.212374 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:23:56.212469 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:23:56.212603 substitutions:
329 23:23:56.212671 - {DTB}: 13248467/tftp-deploy-q9kurlc5/dtb/mt8192-asurada-spherion-r0.dtb
330 23:23:56.212736 - {INITRD}: 13248467/tftp-deploy-q9kurlc5/ramdisk/ramdisk.cpio.gz
331 23:23:56.212796 - {KERNEL}: 13248467/tftp-deploy-q9kurlc5/kernel/Image
332 23:23:56.212854 - {LAVA_MAC}: None
333 23:23:56.212911 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13248467/extract-nfsrootfs-gyhcfl92
334 23:23:56.212968 - {NFS_SERVER_IP}: 192.168.201.1
335 23:23:56.213026 - {PRESEED_CONFIG}: None
336 23:23:56.213082 - {PRESEED_LOCAL}: None
337 23:23:56.213138 - {RAMDISK}: 13248467/tftp-deploy-q9kurlc5/ramdisk/ramdisk.cpio.gz
338 23:23:56.213193 - {ROOT_PART}: None
339 23:23:56.213248 - {ROOT}: None
340 23:23:56.213303 - {SERVER_IP}: 192.168.201.1
341 23:23:56.213357 - {TEE}: None
342 23:23:56.213410 Parsed boot commands:
343 23:23:56.213464 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:23:56.213652 Parsed boot commands: tftpboot 192.168.201.1 13248467/tftp-deploy-q9kurlc5/kernel/image.itb 13248467/tftp-deploy-q9kurlc5/kernel/cmdline
345 23:23:56.213740 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:23:56.213822 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:23:56.213912 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:23:56.214001 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:23:56.214072 Not connected, no need to disconnect.
350 23:23:56.214145 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:23:56.214228 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:23:56.214297 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 23:23:56.218548 Setting prompt string to ['lava-test: # ']
354 23:23:56.218939 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:23:56.219075 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:23:56.219195 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:23:56.219311 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:23:56.219533 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 23:24:01.353181 >> Command sent successfully.
360 23:24:01.355635 Returned 0 in 5 seconds
361 23:24:01.456046 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:24:01.456377 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:24:01.456477 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:24:01.456566 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:24:01.456635 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:24:01.456704 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:24:01.456986 [Enter `^Ec?' for help]
369 23:24:01.632666
370 23:24:01.632813
371 23:24:01.632886 F0: 102B 0000
372 23:24:01.632949
373 23:24:01.633014 F3: 1001 0000 [0200]
374 23:24:01.635704
375 23:24:01.635816 F3: 1001 0000
376 23:24:01.635911
377 23:24:01.636001 F7: 102D 0000
378 23:24:01.636092
379 23:24:01.639012 F1: 0000 0000
380 23:24:01.639096
381 23:24:01.639162 V0: 0000 0000 [0001]
382 23:24:01.639228
383 23:24:01.642351 00: 0007 8000
384 23:24:01.642491
385 23:24:01.642558 01: 0000 0000
386 23:24:01.642622
387 23:24:01.645857 BP: 0C00 0209 [0000]
388 23:24:01.645940
389 23:24:01.646006 G0: 1182 0000
390 23:24:01.646067
391 23:24:01.649792 EC: 0000 0021 [4000]
392 23:24:01.649875
393 23:24:01.649941 S7: 0000 0000 [0000]
394 23:24:01.650005
395 23:24:01.653443 CC: 0000 0000 [0001]
396 23:24:01.653526
397 23:24:01.653591 T0: 0000 0040 [010F]
398 23:24:01.653653
399 23:24:01.653712 Jump to BL
400 23:24:01.653771
401 23:24:01.679843
402 23:24:01.679931
403 23:24:01.679997
404 23:24:01.686633 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:24:01.690044 ARM64: Exception handlers installed.
406 23:24:01.693164 ARM64: Testing exception
407 23:24:01.696805 ARM64: Done test exception
408 23:24:01.703813 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:24:01.713830 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:24:01.720598 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:24:01.730774 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:24:01.737269 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:24:01.743753 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:24:01.756460 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:24:01.763388 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:24:01.782412 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:24:01.785312 WDT: Last reset was cold boot
418 23:24:01.788659 SPI1(PAD0) initialized at 2873684 Hz
419 23:24:01.792252 SPI5(PAD0) initialized at 992727 Hz
420 23:24:01.795546 VBOOT: Loading verstage.
421 23:24:01.802072 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:24:01.806015 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:24:01.809007 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:24:01.812459 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:24:01.819786 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:24:01.826042 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:24:01.836992 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 23:24:01.837102
429 23:24:01.837185
430 23:24:01.847124 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:24:01.850431 ARM64: Exception handlers installed.
432 23:24:01.853670 ARM64: Testing exception
433 23:24:01.853768 ARM64: Done test exception
434 23:24:01.860633 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:24:01.863843 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:24:01.879304 Probing TPM: . done!
437 23:24:01.879460 TPM ready after 0 ms
438 23:24:01.886636 Connected to device vid:did:rid of 1ae0:0028:00
439 23:24:01.893186 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 23:24:01.950199 Initialized TPM device CR50 revision 0
441 23:24:01.962150 tlcl_send_startup: Startup return code is 0
442 23:24:01.962243 TPM: setup succeeded
443 23:24:01.973515 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:24:01.982522 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:24:01.995024 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:24:02.004656 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:24:02.008132 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:24:02.013393 in-header: 03 07 00 00 08 00 00 00
449 23:24:02.016791 in-data: aa e4 47 04 13 02 00 00
450 23:24:02.020767 Chrome EC: UHEPI supported
451 23:24:02.027763 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:24:02.031802 in-header: 03 ad 00 00 08 00 00 00
453 23:24:02.031885 in-data: 00 20 20 08 00 00 00 00
454 23:24:02.035103 Phase 1
455 23:24:02.038939 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:24:02.045751 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:24:02.049938 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:24:02.053748 Recovery requested (1009000e)
459 23:24:02.061614 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:24:02.066789 tlcl_extend: response is 0
461 23:24:02.076516 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:24:02.082332 tlcl_extend: response is 0
463 23:24:02.088859 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:24:02.108752 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 23:24:02.115436 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:24:02.115546
467 23:24:02.115639
468 23:24:02.126362 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:24:02.129805 ARM64: Exception handlers installed.
470 23:24:02.129887 ARM64: Testing exception
471 23:24:02.133235 ARM64: Done test exception
472 23:24:02.154253 pmic_efuse_setting: Set efuses in 11 msecs
473 23:24:02.157755 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:24:02.164700 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:24:02.168015 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:24:02.175158 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:24:02.178521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:24:02.182312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:24:02.186219 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:24:02.193051 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:24:02.197449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:24:02.200467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:24:02.208449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:24:02.212258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:24:02.215968 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:24:02.219209 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:24:02.226720 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:24:02.230491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:24:02.238044 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:24:02.245528 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:24:02.248811 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:24:02.256345 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:24:02.260234 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:24:02.267353 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:24:02.271080 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:24:02.278330 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:24:02.281889 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:24:02.289298 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:24:02.293117 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:24:02.297313 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:24:02.304317 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:24:02.307855 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:24:02.311285 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:24:02.319161 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:24:02.322323 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:24:02.330257 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:24:02.333501 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:24:02.337358 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:24:02.344503 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:24:02.348019 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:24:02.351946 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:24:02.356064 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:24:02.362931 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:24:02.366507 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:24:02.370802 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:24:02.373848 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:24:02.381233 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:24:02.384808 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:24:02.388750 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:24:02.392294 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:24:02.396249 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:24:02.399598 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:24:02.403154 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:24:02.410716 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:24:02.418266 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:24:02.425774 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:24:02.429895 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:24:02.436850 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:24:02.447967 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:24:02.451401 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:24:02.455291 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:24:02.458613 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:24:02.467266 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2a
534 23:24:02.471359 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:24:02.480026 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 23:24:02.482423 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:24:02.491366 [RTC]rtc_get_frequency_meter,154: input=15, output=790
538 23:24:02.501131 [RTC]rtc_get_frequency_meter,154: input=23, output=979
539 23:24:02.510723 [RTC]rtc_get_frequency_meter,154: input=19, output=883
540 23:24:02.519864 [RTC]rtc_get_frequency_meter,154: input=17, output=838
541 23:24:02.529690 [RTC]rtc_get_frequency_meter,154: input=16, output=813
542 23:24:02.540140 [RTC]rtc_get_frequency_meter,154: input=15, output=789
543 23:24:02.549406 [RTC]rtc_get_frequency_meter,154: input=16, output=813
544 23:24:02.552814 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 23:24:02.557813 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 23:24:02.560069 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:24:02.567952 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 23:24:02.571278 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:24:02.575519 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 23:24:02.578669 ADC[4]: Raw value=901328 ID=7
551 23:24:02.578751 ADC[3]: Raw value=213336 ID=1
552 23:24:02.582550 RAM Code: 0x71
553 23:24:02.586176 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:24:02.593183 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:24:02.599997 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:24:02.607854 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:24:02.611032 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:24:02.615252 in-header: 03 07 00 00 08 00 00 00
559 23:24:02.615334 in-data: aa e4 47 04 13 02 00 00
560 23:24:02.618383 Chrome EC: UHEPI supported
561 23:24:02.626376 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:24:02.630053 in-header: 03 ed 00 00 08 00 00 00
563 23:24:02.633337 in-data: 80 20 60 08 00 00 00 00
564 23:24:02.637735 MRC: failed to locate region type 0.
565 23:24:02.641013 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:24:02.644749 DRAM-K: Running full calibration
567 23:24:02.652335 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:24:02.652418 header.status = 0x0
569 23:24:02.656255 header.version = 0x6 (expected: 0x6)
570 23:24:02.659605 header.size = 0xd00 (expected: 0xd00)
571 23:24:02.663514 header.flags = 0x0
572 23:24:02.666935 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:24:02.686022 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 23:24:02.693760 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:24:02.697252 dram_init: ddr_geometry: 2
576 23:24:02.697353 [EMI] MDL number = 2
577 23:24:02.700844 [EMI] Get MDL freq = 0
578 23:24:02.700926 dram_init: ddr_type: 0
579 23:24:02.704532 is_discrete_lpddr4: 1
580 23:24:02.708872 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:24:02.708954
582 23:24:02.709018
583 23:24:02.709078 [Bian_co] ETT version 0.0.0.1
584 23:24:02.715935 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:24:02.716021
586 23:24:02.719568 dramc_set_vcore_voltage set vcore to 650000
587 23:24:02.719651 Read voltage for 800, 4
588 23:24:02.723193 Vio18 = 0
589 23:24:02.723277 Vcore = 650000
590 23:24:02.723348 Vdram = 0
591 23:24:02.723407 Vddq = 0
592 23:24:02.726801 Vmddr = 0
593 23:24:02.726881 dram_init: config_dvfs: 1
594 23:24:02.734560 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:24:02.737892 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:24:02.740872 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 23:24:02.744289 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 23:24:02.748106 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 23:24:02.754379 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 23:24:02.754472 MEM_TYPE=3, freq_sel=18
601 23:24:02.757772 sv_algorithm_assistance_LP4_1600
602 23:24:02.761249 ============ PULL DRAM RESETB DOWN ============
603 23:24:02.768064 ========== PULL DRAM RESETB DOWN end =========
604 23:24:02.771627 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:24:02.775137 ===================================
606 23:24:02.778516 LPDDR4 DRAM CONFIGURATION
607 23:24:02.781928 ===================================
608 23:24:02.782010 EX_ROW_EN[0] = 0x0
609 23:24:02.785031 EX_ROW_EN[1] = 0x0
610 23:24:02.785112 LP4Y_EN = 0x0
611 23:24:02.788230 WORK_FSP = 0x0
612 23:24:02.788338 WL = 0x2
613 23:24:02.791304 RL = 0x2
614 23:24:02.791412 BL = 0x2
615 23:24:02.794851 RPST = 0x0
616 23:24:02.798603 RD_PRE = 0x0
617 23:24:02.798684 WR_PRE = 0x1
618 23:24:02.801507 WR_PST = 0x0
619 23:24:02.801589 DBI_WR = 0x0
620 23:24:02.804651 DBI_RD = 0x0
621 23:24:02.804750 OTF = 0x1
622 23:24:02.808267 ===================================
623 23:24:02.811588 ===================================
624 23:24:02.811670 ANA top config
625 23:24:02.815404 ===================================
626 23:24:02.818229 DLL_ASYNC_EN = 0
627 23:24:02.821922 ALL_SLAVE_EN = 1
628 23:24:02.825402 NEW_RANK_MODE = 1
629 23:24:02.828588 DLL_IDLE_MODE = 1
630 23:24:02.828669 LP45_APHY_COMB_EN = 1
631 23:24:02.831812 TX_ODT_DIS = 1
632 23:24:02.835230 NEW_8X_MODE = 1
633 23:24:02.838326 ===================================
634 23:24:02.841966 ===================================
635 23:24:02.845626 data_rate = 1600
636 23:24:02.845708 CKR = 1
637 23:24:02.848673 DQ_P2S_RATIO = 8
638 23:24:02.851987 ===================================
639 23:24:02.855711 CA_P2S_RATIO = 8
640 23:24:02.859052 DQ_CA_OPEN = 0
641 23:24:02.862354 DQ_SEMI_OPEN = 0
642 23:24:02.865811 CA_SEMI_OPEN = 0
643 23:24:02.865892 CA_FULL_RATE = 0
644 23:24:02.869300 DQ_CKDIV4_EN = 1
645 23:24:02.872088 CA_CKDIV4_EN = 1
646 23:24:02.875825 CA_PREDIV_EN = 0
647 23:24:02.879044 PH8_DLY = 0
648 23:24:02.879125 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:24:02.882628 DQ_AAMCK_DIV = 4
650 23:24:02.885487 CA_AAMCK_DIV = 4
651 23:24:02.889094 CA_ADMCK_DIV = 4
652 23:24:02.892839 DQ_TRACK_CA_EN = 0
653 23:24:02.896270 CA_PICK = 800
654 23:24:02.896355 CA_MCKIO = 800
655 23:24:02.899039 MCKIO_SEMI = 0
656 23:24:02.902421 PLL_FREQ = 3068
657 23:24:02.906099 DQ_UI_PI_RATIO = 32
658 23:24:02.909570 CA_UI_PI_RATIO = 0
659 23:24:02.913659 ===================================
660 23:24:02.913742 ===================================
661 23:24:02.917624 memory_type:LPDDR4
662 23:24:02.921328 GP_NUM : 10
663 23:24:02.921421 SRAM_EN : 1
664 23:24:02.924732 MD32_EN : 0
665 23:24:02.928519 ===================================
666 23:24:02.928600 [ANA_INIT] >>>>>>>>>>>>>>
667 23:24:02.932458 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:24:02.936066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:24:02.939981 ===================================
670 23:24:02.943659 data_rate = 1600,PCW = 0X7600
671 23:24:02.946482 ===================================
672 23:24:02.950644 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:24:02.953211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:24:02.960134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:24:02.963493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:24:02.967176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:24:02.970283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:24:02.973520 [ANA_INIT] flow start
679 23:24:02.976648 [ANA_INIT] PLL >>>>>>>>
680 23:24:02.976729 [ANA_INIT] PLL <<<<<<<<
681 23:24:02.980000 [ANA_INIT] MIDPI >>>>>>>>
682 23:24:02.983535 [ANA_INIT] MIDPI <<<<<<<<
683 23:24:02.983617 [ANA_INIT] DLL >>>>>>>>
684 23:24:02.986451 [ANA_INIT] flow end
685 23:24:02.990050 ============ LP4 DIFF to SE enter ============
686 23:24:02.993280 ============ LP4 DIFF to SE exit ============
687 23:24:02.996769 [ANA_INIT] <<<<<<<<<<<<<
688 23:24:02.999745 [Flow] Enable top DCM control >>>>>
689 23:24:03.003283 [Flow] Enable top DCM control <<<<<
690 23:24:03.006702 Enable DLL master slave shuffle
691 23:24:03.013615 ==============================================================
692 23:24:03.013695 Gating Mode config
693 23:24:03.020151 ==============================================================
694 23:24:03.020236 Config description:
695 23:24:03.029999 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:24:03.036633 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:24:03.043364 SELPH_MODE 0: By rank 1: By Phase
698 23:24:03.046965 ==============================================================
699 23:24:03.050025 GAT_TRACK_EN = 1
700 23:24:03.053864 RX_GATING_MODE = 2
701 23:24:03.057001 RX_GATING_TRACK_MODE = 2
702 23:24:03.060518 SELPH_MODE = 1
703 23:24:03.063479 PICG_EARLY_EN = 1
704 23:24:03.067036 VALID_LAT_VALUE = 1
705 23:24:03.070316 ==============================================================
706 23:24:03.074117 Enter into Gating configuration >>>>
707 23:24:03.077243 Exit from Gating configuration <<<<
708 23:24:03.080132 Enter into DVFS_PRE_config >>>>>
709 23:24:03.094045 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:24:03.094136 Exit from DVFS_PRE_config <<<<<
711 23:24:03.097060 Enter into PICG configuration >>>>
712 23:24:03.100222 Exit from PICG configuration <<<<
713 23:24:03.104286 [RX_INPUT] configuration >>>>>
714 23:24:03.107202 [RX_INPUT] configuration <<<<<
715 23:24:03.113936 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:24:03.117529 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:24:03.124713 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:24:03.131518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:24:03.137955 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:24:03.141727 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:24:03.144924 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:24:03.152195 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:24:03.155434 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:24:03.158314 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:24:03.161937 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:24:03.168397 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:24:03.172072 ===================================
728 23:24:03.172187 LPDDR4 DRAM CONFIGURATION
729 23:24:03.175328 ===================================
730 23:24:03.178873 EX_ROW_EN[0] = 0x0
731 23:24:03.181674 EX_ROW_EN[1] = 0x0
732 23:24:03.181781 LP4Y_EN = 0x0
733 23:24:03.185564 WORK_FSP = 0x0
734 23:24:03.185675 WL = 0x2
735 23:24:03.188969 RL = 0x2
736 23:24:03.189105 BL = 0x2
737 23:24:03.191784 RPST = 0x0
738 23:24:03.191914 RD_PRE = 0x0
739 23:24:03.195838 WR_PRE = 0x1
740 23:24:03.195944 WR_PST = 0x0
741 23:24:03.198806 DBI_WR = 0x0
742 23:24:03.198878 DBI_RD = 0x0
743 23:24:03.202180 OTF = 0x1
744 23:24:03.205514 ===================================
745 23:24:03.208968 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:24:03.212316 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:24:03.215424 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:24:03.218837 ===================================
749 23:24:03.222313 LPDDR4 DRAM CONFIGURATION
750 23:24:03.225888 ===================================
751 23:24:03.228753 EX_ROW_EN[0] = 0x10
752 23:24:03.228864 EX_ROW_EN[1] = 0x0
753 23:24:03.232429 LP4Y_EN = 0x0
754 23:24:03.232541 WORK_FSP = 0x0
755 23:24:03.235625 WL = 0x2
756 23:24:03.235737 RL = 0x2
757 23:24:03.238897 BL = 0x2
758 23:24:03.239018 RPST = 0x0
759 23:24:03.242447 RD_PRE = 0x0
760 23:24:03.242534 WR_PRE = 0x1
761 23:24:03.245679 WR_PST = 0x0
762 23:24:03.245762 DBI_WR = 0x0
763 23:24:03.248947 DBI_RD = 0x0
764 23:24:03.249052 OTF = 0x1
765 23:24:03.252511 ===================================
766 23:24:03.259279 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:24:03.264144 nWR fixed to 40
768 23:24:03.267261 [ModeRegInit_LP4] CH0 RK0
769 23:24:03.267342 [ModeRegInit_LP4] CH0 RK1
770 23:24:03.270745 [ModeRegInit_LP4] CH1 RK0
771 23:24:03.274029 [ModeRegInit_LP4] CH1 RK1
772 23:24:03.274137 match AC timing 13
773 23:24:03.281051 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:24:03.284308 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:24:03.287463 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:24:03.294070 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:24:03.297998 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:24:03.298080 [EMI DOE] emi_dcm 0
779 23:24:03.304756 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:24:03.304838 ==
781 23:24:03.307605 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:24:03.310949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:24:03.311032 ==
784 23:24:03.317535 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:24:03.321033 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:24:03.331185 [CA 0] Center 37 (7~68) winsize 62
787 23:24:03.334771 [CA 1] Center 37 (6~68) winsize 63
788 23:24:03.338678 [CA 2] Center 35 (5~66) winsize 62
789 23:24:03.341502 [CA 3] Center 34 (4~65) winsize 62
790 23:24:03.344984 [CA 4] Center 34 (3~65) winsize 63
791 23:24:03.348280 [CA 5] Center 34 (4~64) winsize 61
792 23:24:03.348361
793 23:24:03.351829 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 23:24:03.351921
795 23:24:03.354883 [CATrainingPosCal] consider 1 rank data
796 23:24:03.358248 u2DelayCellTimex100 = 270/100 ps
797 23:24:03.361474 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
798 23:24:03.365005 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
799 23:24:03.368208 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
800 23:24:03.374768 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
801 23:24:03.378821 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
802 23:24:03.381657 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
803 23:24:03.381739
804 23:24:03.385109 CA PerBit enable=1, Macro0, CA PI delay=34
805 23:24:03.385192
806 23:24:03.388316 [CBTSetCACLKResult] CA Dly = 34
807 23:24:03.388398 CS Dly: 5 (0~36)
808 23:24:03.388463 ==
809 23:24:03.391672 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:24:03.398985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:24:03.399067 ==
812 23:24:03.401777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:24:03.408870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:24:03.417817 [CA 0] Center 37 (6~68) winsize 63
815 23:24:03.421630 [CA 1] Center 37 (7~68) winsize 62
816 23:24:03.424221 [CA 2] Center 35 (4~66) winsize 63
817 23:24:03.427598 [CA 3] Center 35 (4~66) winsize 63
818 23:24:03.430985 [CA 4] Center 34 (3~65) winsize 63
819 23:24:03.434641 [CA 5] Center 34 (4~64) winsize 61
820 23:24:03.434723
821 23:24:03.437976 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 23:24:03.438057
823 23:24:03.441306 [CATrainingPosCal] consider 2 rank data
824 23:24:03.444317 u2DelayCellTimex100 = 270/100 ps
825 23:24:03.447781 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
826 23:24:03.451434 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
827 23:24:03.454564 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
828 23:24:03.461433 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
829 23:24:03.464500 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
830 23:24:03.468202 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
831 23:24:03.468291
832 23:24:03.471329 CA PerBit enable=1, Macro0, CA PI delay=34
833 23:24:03.471411
834 23:24:03.474727 [CBTSetCACLKResult] CA Dly = 34
835 23:24:03.474809 CS Dly: 6 (0~38)
836 23:24:03.474875
837 23:24:03.478144 ----->DramcWriteLeveling(PI) begin...
838 23:24:03.478272 ==
839 23:24:03.481287 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:24:03.488499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:24:03.488583 ==
842 23:24:03.488654 Write leveling (Byte 0): 28 => 28
843 23:24:03.492822 Write leveling (Byte 1): 28 => 28
844 23:24:03.496000 DramcWriteLeveling(PI) end<-----
845 23:24:03.496104
846 23:24:03.496188 ==
847 23:24:03.499962 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:24:03.503797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:24:03.503879 ==
850 23:24:03.507323 [Gating] SW mode calibration
851 23:24:03.514237 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:24:03.517395 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:24:03.524463 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:24:03.527693 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 23:24:03.531115 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 23:24:03.537780 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:24:03.540828 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:24:03.544200 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:24:03.551105 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:24:03.554118 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:24:03.557491 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:24:03.564432 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:24:03.567749 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:24:03.571507 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:24:03.574360 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:24:03.581325 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:24:03.584770 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:24:03.588276 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:24:03.594435 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:24:03.597607 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 23:24:03.601505 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 23:24:03.607935 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
873 23:24:03.611288 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:24:03.614770 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:24:03.621640 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:24:03.624721 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:24:03.628148 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:24:03.634743 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:24:03.638411 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 23:24:03.641860 0 9 12 | B1->B0 | 2626 2e2e | 1 0 | (0 0) (0 0)
881 23:24:03.645019 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:24:03.651726 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:24:03.655022 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:24:03.658253 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:24:03.665321 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:24:03.668436 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 23:24:03.671801 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 1)
888 23:24:03.679047 0 10 12 | B1->B0 | 3030 2626 | 0 0 | (1 1) (0 0)
889 23:24:03.681850 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:24:03.685458 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:24:03.688796 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:24:03.695122 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:24:03.698727 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:24:03.701962 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 23:24:03.708472 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
896 23:24:03.711934 0 11 12 | B1->B0 | 3a3a 3e3e | 0 0 | (0 0) (1 1)
897 23:24:03.715449 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:24:03.722276 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:24:03.725535 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:24:03.728994 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:24:03.735581 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:24:03.739137 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 23:24:03.742527 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 23:24:03.748941 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:24:03.752455 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:24:03.755588 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:24:03.759523 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:24:03.765801 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:24:03.769012 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:24:03.772756 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:24:03.779147 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:24:03.782839 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:24:03.785805 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:24:03.793001 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:24:03.795958 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:24:03.799875 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:24:03.805990 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:24:03.809714 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 23:24:03.812555 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 23:24:03.816470 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 23:24:03.819921 Total UI for P1: 0, mck2ui 16
922 23:24:03.822913 best dqsien dly found for B0: ( 0, 14, 8)
923 23:24:03.826145 Total UI for P1: 0, mck2ui 16
924 23:24:03.829720 best dqsien dly found for B1: ( 0, 14, 10)
925 23:24:03.833044 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 23:24:03.836014 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 23:24:03.839937
928 23:24:03.842870 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 23:24:03.846295 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 23:24:03.849720 [Gating] SW calibration Done
931 23:24:03.849791 ==
932 23:24:03.853080 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:24:03.856108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:24:03.856179 ==
935 23:24:03.856241 RX Vref Scan: 0
936 23:24:03.856303
937 23:24:03.859609 RX Vref 0 -> 0, step: 1
938 23:24:03.859691
939 23:24:03.863162 RX Delay -130 -> 252, step: 16
940 23:24:03.866589 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 23:24:03.870249 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 23:24:03.876429 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 23:24:03.879964 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 23:24:03.883353 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 23:24:03.886757 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 23:24:03.890065 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 23:24:03.893477 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 23:24:03.900539 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 23:24:03.903528 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 23:24:03.906901 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 23:24:03.910373 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 23:24:03.913601 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 23:24:03.920357 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
954 23:24:03.923917 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 23:24:03.927161 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 23:24:03.927245 ==
957 23:24:03.930568 Dram Type= 6, Freq= 0, CH_0, rank 0
958 23:24:03.933727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 23:24:03.933809 ==
960 23:24:03.937098 DQS Delay:
961 23:24:03.937179 DQS0 = 0, DQS1 = 0
962 23:24:03.937244 DQM Delay:
963 23:24:03.940475 DQM0 = 87, DQM1 = 77
964 23:24:03.940556 DQ Delay:
965 23:24:03.943850 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 23:24:03.947151 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
967 23:24:03.950679 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
968 23:24:03.953958 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
969 23:24:03.954040
970 23:24:03.954105
971 23:24:03.954164 ==
972 23:24:03.957403 Dram Type= 6, Freq= 0, CH_0, rank 0
973 23:24:03.964123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 23:24:03.964231 ==
975 23:24:03.964323
976 23:24:03.964410
977 23:24:03.964496 TX Vref Scan disable
978 23:24:03.967946 == TX Byte 0 ==
979 23:24:03.970771 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 23:24:03.974421 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 23:24:03.977715 == TX Byte 1 ==
982 23:24:03.981792 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
983 23:24:03.984193 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
984 23:24:03.988035 ==
985 23:24:03.990890 Dram Type= 6, Freq= 0, CH_0, rank 0
986 23:24:03.994516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 23:24:03.994597 ==
988 23:24:04.006561 TX Vref=22, minBit 7, minWin=26, winSum=438
989 23:24:04.010003 TX Vref=24, minBit 0, minWin=27, winSum=443
990 23:24:04.013570 TX Vref=26, minBit 5, minWin=27, winSum=445
991 23:24:04.016802 TX Vref=28, minBit 12, minWin=27, winSum=450
992 23:24:04.020516 TX Vref=30, minBit 1, minWin=28, winSum=450
993 23:24:04.023359 TX Vref=32, minBit 2, minWin=28, winSum=451
994 23:24:04.030851 [TxChooseVref] Worse bit 2, Min win 28, Win sum 451, Final Vref 32
995 23:24:04.030933
996 23:24:04.033897 Final TX Range 1 Vref 32
997 23:24:04.033978
998 23:24:04.034043 ==
999 23:24:04.036867 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:24:04.040303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:24:04.040385 ==
1002 23:24:04.040450
1003 23:24:04.040509
1004 23:24:04.043600 TX Vref Scan disable
1005 23:24:04.047105 == TX Byte 0 ==
1006 23:24:04.050867 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 23:24:04.053857 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 23:24:04.057467 == TX Byte 1 ==
1009 23:24:04.060307 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 23:24:04.063863 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 23:24:04.063945
1012 23:24:04.067049 [DATLAT]
1013 23:24:04.067129 Freq=800, CH0 RK0
1014 23:24:04.067193
1015 23:24:04.070140 DATLAT Default: 0xa
1016 23:24:04.070246 0, 0xFFFF, sum = 0
1017 23:24:04.073964 1, 0xFFFF, sum = 0
1018 23:24:04.074056 2, 0xFFFF, sum = 0
1019 23:24:04.077218 3, 0xFFFF, sum = 0
1020 23:24:04.077300 4, 0xFFFF, sum = 0
1021 23:24:04.080629 5, 0xFFFF, sum = 0
1022 23:24:04.080739 6, 0xFFFF, sum = 0
1023 23:24:04.084274 7, 0xFFFF, sum = 0
1024 23:24:04.084356 8, 0xFFFF, sum = 0
1025 23:24:04.086917 9, 0x0, sum = 1
1026 23:24:04.087034 10, 0x0, sum = 2
1027 23:24:04.090827 11, 0x0, sum = 3
1028 23:24:04.090908 12, 0x0, sum = 4
1029 23:24:04.093711 best_step = 10
1030 23:24:04.093800
1031 23:24:04.093893 ==
1032 23:24:04.097157 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 23:24:04.100253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 23:24:04.100333 ==
1035 23:24:04.103925 RX Vref Scan: 1
1036 23:24:04.104004
1037 23:24:04.104066 Set Vref Range= 32 -> 127
1038 23:24:04.104124
1039 23:24:04.107269 RX Vref 32 -> 127, step: 1
1040 23:24:04.107349
1041 23:24:04.110601 RX Delay -95 -> 252, step: 8
1042 23:24:04.110682
1043 23:24:04.114117 Set Vref, RX VrefLevel [Byte0]: 32
1044 23:24:04.117556 [Byte1]: 32
1045 23:24:04.117636
1046 23:24:04.121002 Set Vref, RX VrefLevel [Byte0]: 33
1047 23:24:04.124456 [Byte1]: 33
1048 23:24:04.124536
1049 23:24:04.128101 Set Vref, RX VrefLevel [Byte0]: 34
1050 23:24:04.131722 [Byte1]: 34
1051 23:24:04.134984
1052 23:24:04.135063 Set Vref, RX VrefLevel [Byte0]: 35
1053 23:24:04.137884 [Byte1]: 35
1054 23:24:04.142205
1055 23:24:04.142284 Set Vref, RX VrefLevel [Byte0]: 36
1056 23:24:04.145627 [Byte1]: 36
1057 23:24:04.149985
1058 23:24:04.150064 Set Vref, RX VrefLevel [Byte0]: 37
1059 23:24:04.153547 [Byte1]: 37
1060 23:24:04.158018
1061 23:24:04.158102 Set Vref, RX VrefLevel [Byte0]: 38
1062 23:24:04.161590 [Byte1]: 38
1063 23:24:04.165538
1064 23:24:04.165608 Set Vref, RX VrefLevel [Byte0]: 39
1065 23:24:04.169144 [Byte1]: 39
1066 23:24:04.173800
1067 23:24:04.173873 Set Vref, RX VrefLevel [Byte0]: 40
1068 23:24:04.176777 [Byte1]: 40
1069 23:24:04.180792
1070 23:24:04.180879 Set Vref, RX VrefLevel [Byte0]: 41
1071 23:24:04.183917 [Byte1]: 41
1072 23:24:04.188098
1073 23:24:04.188174 Set Vref, RX VrefLevel [Byte0]: 42
1074 23:24:04.191417 [Byte1]: 42
1075 23:24:04.195166
1076 23:24:04.195249 Set Vref, RX VrefLevel [Byte0]: 43
1077 23:24:04.198604 [Byte1]: 43
1078 23:24:04.202980
1079 23:24:04.203057 Set Vref, RX VrefLevel [Byte0]: 44
1080 23:24:04.206339 [Byte1]: 44
1081 23:24:04.210966
1082 23:24:04.211080 Set Vref, RX VrefLevel [Byte0]: 45
1083 23:24:04.213812 [Byte1]: 45
1084 23:24:04.218199
1085 23:24:04.218278 Set Vref, RX VrefLevel [Byte0]: 46
1086 23:24:04.221494 [Byte1]: 46
1087 23:24:04.225933
1088 23:24:04.226008 Set Vref, RX VrefLevel [Byte0]: 47
1089 23:24:04.229340 [Byte1]: 47
1090 23:24:04.233386
1091 23:24:04.233464 Set Vref, RX VrefLevel [Byte0]: 48
1092 23:24:04.237142 [Byte1]: 48
1093 23:24:04.241199
1094 23:24:04.241281 Set Vref, RX VrefLevel [Byte0]: 49
1095 23:24:04.244498 [Byte1]: 49
1096 23:24:04.248307
1097 23:24:04.248386 Set Vref, RX VrefLevel [Byte0]: 50
1098 23:24:04.251912 [Byte1]: 50
1099 23:24:04.256314
1100 23:24:04.256395 Set Vref, RX VrefLevel [Byte0]: 51
1101 23:24:04.259326 [Byte1]: 51
1102 23:24:04.263782
1103 23:24:04.263862 Set Vref, RX VrefLevel [Byte0]: 52
1104 23:24:04.267280 [Byte1]: 52
1105 23:24:04.271188
1106 23:24:04.271269 Set Vref, RX VrefLevel [Byte0]: 53
1107 23:24:04.277793 [Byte1]: 53
1108 23:24:04.277874
1109 23:24:04.281157 Set Vref, RX VrefLevel [Byte0]: 54
1110 23:24:04.284312 [Byte1]: 54
1111 23:24:04.284393
1112 23:24:04.287871 Set Vref, RX VrefLevel [Byte0]: 55
1113 23:24:04.291343 [Byte1]: 55
1114 23:24:04.291425
1115 23:24:04.294695 Set Vref, RX VrefLevel [Byte0]: 56
1116 23:24:04.297814 [Byte1]: 56
1117 23:24:04.302596
1118 23:24:04.302677 Set Vref, RX VrefLevel [Byte0]: 57
1119 23:24:04.305053 [Byte1]: 57
1120 23:24:04.309314
1121 23:24:04.309394 Set Vref, RX VrefLevel [Byte0]: 58
1122 23:24:04.312411 [Byte1]: 58
1123 23:24:04.316733
1124 23:24:04.316815 Set Vref, RX VrefLevel [Byte0]: 59
1125 23:24:04.320147 [Byte1]: 59
1126 23:24:04.324412
1127 23:24:04.324493 Set Vref, RX VrefLevel [Byte0]: 60
1128 23:24:04.327941 [Byte1]: 60
1129 23:24:04.332393
1130 23:24:04.332473 Set Vref, RX VrefLevel [Byte0]: 61
1131 23:24:04.335108 [Byte1]: 61
1132 23:24:04.339632
1133 23:24:04.339713 Set Vref, RX VrefLevel [Byte0]: 62
1134 23:24:04.342992 [Byte1]: 62
1135 23:24:04.347401
1136 23:24:04.347530 Set Vref, RX VrefLevel [Byte0]: 63
1137 23:24:04.351051 [Byte1]: 63
1138 23:24:04.354717
1139 23:24:04.354820 Set Vref, RX VrefLevel [Byte0]: 64
1140 23:24:04.358156 [Byte1]: 64
1141 23:24:04.362287
1142 23:24:04.362394 Set Vref, RX VrefLevel [Byte0]: 65
1143 23:24:04.365782 [Byte1]: 65
1144 23:24:04.369929
1145 23:24:04.370002 Set Vref, RX VrefLevel [Byte0]: 66
1146 23:24:04.373417 [Byte1]: 66
1147 23:24:04.377825
1148 23:24:04.377899 Set Vref, RX VrefLevel [Byte0]: 67
1149 23:24:04.380846 [Byte1]: 67
1150 23:24:04.385302
1151 23:24:04.385415 Set Vref, RX VrefLevel [Byte0]: 68
1152 23:24:04.388666 [Byte1]: 68
1153 23:24:04.392603
1154 23:24:04.392714 Set Vref, RX VrefLevel [Byte0]: 69
1155 23:24:04.395957 [Byte1]: 69
1156 23:24:04.400493
1157 23:24:04.400583 Set Vref, RX VrefLevel [Byte0]: 70
1158 23:24:04.403975 [Byte1]: 70
1159 23:24:04.408095
1160 23:24:04.408192 Set Vref, RX VrefLevel [Byte0]: 71
1161 23:24:04.411373 [Byte1]: 71
1162 23:24:04.416061
1163 23:24:04.416142 Set Vref, RX VrefLevel [Byte0]: 72
1164 23:24:04.418987 [Byte1]: 72
1165 23:24:04.423294
1166 23:24:04.423380 Set Vref, RX VrefLevel [Byte0]: 73
1167 23:24:04.426704 [Byte1]: 73
1168 23:24:04.430675
1169 23:24:04.430758 Set Vref, RX VrefLevel [Byte0]: 74
1170 23:24:04.433816 [Byte1]: 74
1171 23:24:04.438227
1172 23:24:04.438306 Set Vref, RX VrefLevel [Byte0]: 75
1173 23:24:04.441555 [Byte1]: 75
1174 23:24:04.446135
1175 23:24:04.446240 Set Vref, RX VrefLevel [Byte0]: 76
1176 23:24:04.449528 [Byte1]: 76
1177 23:24:04.453255
1178 23:24:04.453338 Set Vref, RX VrefLevel [Byte0]: 77
1179 23:24:04.457244 [Byte1]: 77
1180 23:24:04.461426
1181 23:24:04.461507 Final RX Vref Byte 0 = 62 to rank0
1182 23:24:04.464165 Final RX Vref Byte 1 = 57 to rank0
1183 23:24:04.468206 Final RX Vref Byte 0 = 62 to rank1
1184 23:24:04.471155 Final RX Vref Byte 1 = 57 to rank1==
1185 23:24:04.474557 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 23:24:04.477946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 23:24:04.481198 ==
1188 23:24:04.481278 DQS Delay:
1189 23:24:04.481342 DQS0 = 0, DQS1 = 0
1190 23:24:04.484566 DQM Delay:
1191 23:24:04.484638 DQM0 = 87, DQM1 = 80
1192 23:24:04.487840 DQ Delay:
1193 23:24:04.487913 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1194 23:24:04.491266 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1195 23:24:04.494548 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1196 23:24:04.498320 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1197 23:24:04.498411
1198 23:24:04.501854
1199 23:24:04.508476 [DQSOSCAuto] RK0, (LSB)MR18= 0x230a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
1200 23:24:04.511813 CH0 RK0: MR19=606, MR18=230A
1201 23:24:04.518314 CH0_RK0: MR19=0x606, MR18=0x230A, DQSOSC=401, MR23=63, INC=91, DEC=61
1202 23:24:04.518402
1203 23:24:04.521927 ----->DramcWriteLeveling(PI) begin...
1204 23:24:04.522011 ==
1205 23:24:04.525279 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 23:24:04.528198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 23:24:04.528282 ==
1208 23:24:04.531737 Write leveling (Byte 0): 30 => 30
1209 23:24:04.535124 Write leveling (Byte 1): 30 => 30
1210 23:24:04.538224 DramcWriteLeveling(PI) end<-----
1211 23:24:04.538336
1212 23:24:04.538437 ==
1213 23:24:04.541850 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 23:24:04.545038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 23:24:04.545148 ==
1216 23:24:04.548449 [Gating] SW mode calibration
1217 23:24:04.555156 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 23:24:04.558348 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 23:24:04.565198 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1220 23:24:04.609045 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1221 23:24:04.609709 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1222 23:24:04.609794 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:24:04.610045 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:24:04.610113 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:24:04.610174 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:24:04.610878 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:24:04.610960 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:24:04.611212 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:24:04.611347 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:24:04.615035 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:24:04.618504 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:24:04.622094 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:24:04.624942 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:24:04.631839 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:24:04.635439 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1236 23:24:04.638807 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1237 23:24:04.645297 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1238 23:24:04.648861 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:24:04.652311 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:24:04.655513 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:24:04.662062 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:24:04.665527 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:24:04.668797 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:24:04.675823 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:24:04.678908 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1246 23:24:04.681967 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1247 23:24:04.688872 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 23:24:04.692573 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 23:24:04.695373 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 23:24:04.702068 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 23:24:04.705598 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 23:24:04.709208 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1253 23:24:04.715794 0 10 8 | B1->B0 | 3131 2525 | 0 0 | (0 0) (0 0)
1254 23:24:04.718960 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1255 23:24:04.722562 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 23:24:04.725808 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 23:24:04.732184 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 23:24:04.736040 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 23:24:04.740028 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 23:24:04.747170 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1261 23:24:04.750231 0 11 8 | B1->B0 | 2727 3e3e | 0 0 | (0 0) (0 0)
1262 23:24:04.753499 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1263 23:24:04.756913 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 23:24:04.764077 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 23:24:04.767595 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 23:24:04.771178 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 23:24:04.774266 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 23:24:04.781060 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 23:24:04.784638 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1270 23:24:04.787897 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:24:04.794292 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:24:04.797824 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:24:04.801693 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:24:04.804399 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:24:04.811124 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:24:04.814618 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:24:04.817824 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:24:04.825175 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:24:04.828163 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:24:04.831510 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:24:04.838360 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:24:04.842206 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:24:04.844909 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:24:04.851568 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1285 23:24:04.855732 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 23:24:04.858320 Total UI for P1: 0, mck2ui 16
1287 23:24:04.861896 best dqsien dly found for B0: ( 0, 14, 4)
1288 23:24:04.865259 Total UI for P1: 0, mck2ui 16
1289 23:24:04.868353 best dqsien dly found for B1: ( 0, 14, 6)
1290 23:24:04.872118 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1291 23:24:04.875013 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1292 23:24:04.875096
1293 23:24:04.878435 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1294 23:24:04.882045 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1295 23:24:04.885149 [Gating] SW calibration Done
1296 23:24:04.885232 ==
1297 23:24:04.888721 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 23:24:04.892097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 23:24:04.892180 ==
1300 23:24:04.895403 RX Vref Scan: 0
1301 23:24:04.895485
1302 23:24:04.895550 RX Vref 0 -> 0, step: 1
1303 23:24:04.895610
1304 23:24:04.898532 RX Delay -130 -> 252, step: 16
1305 23:24:04.902014 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1306 23:24:04.908831 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1307 23:24:04.911681 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1308 23:24:04.915346 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1309 23:24:04.918686 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1310 23:24:04.922298 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1311 23:24:04.928559 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1312 23:24:04.931824 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1313 23:24:04.935799 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1314 23:24:04.938848 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1315 23:24:04.942168 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1316 23:24:04.948958 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1317 23:24:04.952603 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1318 23:24:04.955627 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1319 23:24:04.958969 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1320 23:24:04.962311 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1321 23:24:04.965726 ==
1322 23:24:04.965807 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 23:24:04.972095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 23:24:04.972176 ==
1325 23:24:04.972241 DQS Delay:
1326 23:24:04.976027 DQS0 = 0, DQS1 = 0
1327 23:24:04.976107 DQM Delay:
1328 23:24:04.979426 DQM0 = 86, DQM1 = 75
1329 23:24:04.979510 DQ Delay:
1330 23:24:04.982013 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1331 23:24:04.985705 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1332 23:24:04.988726 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1333 23:24:04.991996 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1334 23:24:04.992103
1335 23:24:04.992193
1336 23:24:04.992278 ==
1337 23:24:04.995770 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 23:24:04.999001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 23:24:04.999097 ==
1340 23:24:04.999188
1341 23:24:04.999246
1342 23:24:05.002036 TX Vref Scan disable
1343 23:24:05.005662 == TX Byte 0 ==
1344 23:24:05.008878 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1345 23:24:05.012609 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1346 23:24:05.015393 == TX Byte 1 ==
1347 23:24:05.018761 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1348 23:24:05.022151 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1349 23:24:05.022224 ==
1350 23:24:05.025511 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 23:24:05.029096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 23:24:05.029231 ==
1353 23:24:05.043171 TX Vref=22, minBit 2, minWin=27, winSum=444
1354 23:24:05.046575 TX Vref=24, minBit 9, minWin=27, winSum=448
1355 23:24:05.050002 TX Vref=26, minBit 3, minWin=27, winSum=447
1356 23:24:05.053438 TX Vref=28, minBit 9, minWin=27, winSum=452
1357 23:24:05.056797 TX Vref=30, minBit 0, minWin=28, winSum=455
1358 23:24:05.060054 TX Vref=32, minBit 0, minWin=28, winSum=453
1359 23:24:05.066662 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1360 23:24:05.066748
1361 23:24:05.070097 Final TX Range 1 Vref 30
1362 23:24:05.070177
1363 23:24:05.070240 ==
1364 23:24:05.073337 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 23:24:05.076716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 23:24:05.076796 ==
1367 23:24:05.076858
1368 23:24:05.076916
1369 23:24:05.080203 TX Vref Scan disable
1370 23:24:05.083095 == TX Byte 0 ==
1371 23:24:05.087121 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1372 23:24:05.090186 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1373 23:24:05.093385 == TX Byte 1 ==
1374 23:24:05.096635 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1375 23:24:05.100105 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1376 23:24:05.100186
1377 23:24:05.103214 [DATLAT]
1378 23:24:05.103331 Freq=800, CH0 RK1
1379 23:24:05.103395
1380 23:24:05.106721 DATLAT Default: 0xa
1381 23:24:05.106827 0, 0xFFFF, sum = 0
1382 23:24:05.110274 1, 0xFFFF, sum = 0
1383 23:24:05.110382 2, 0xFFFF, sum = 0
1384 23:24:05.113740 3, 0xFFFF, sum = 0
1385 23:24:05.113815 4, 0xFFFF, sum = 0
1386 23:24:05.117001 5, 0xFFFF, sum = 0
1387 23:24:05.117109 6, 0xFFFF, sum = 0
1388 23:24:05.120029 7, 0xFFFF, sum = 0
1389 23:24:05.120104 8, 0xFFFF, sum = 0
1390 23:24:05.123591 9, 0x0, sum = 1
1391 23:24:05.123691 10, 0x0, sum = 2
1392 23:24:05.127202 11, 0x0, sum = 3
1393 23:24:05.127276 12, 0x0, sum = 4
1394 23:24:05.130539 best_step = 10
1395 23:24:05.130614
1396 23:24:05.130674 ==
1397 23:24:05.134086 Dram Type= 6, Freq= 0, CH_0, rank 1
1398 23:24:05.137397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 23:24:05.137501 ==
1400 23:24:05.137589 RX Vref Scan: 0
1401 23:24:05.140808
1402 23:24:05.140888 RX Vref 0 -> 0, step: 1
1403 23:24:05.140975
1404 23:24:05.144234 RX Delay -95 -> 252, step: 8
1405 23:24:05.147329 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1406 23:24:05.153728 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1407 23:24:05.157340 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1408 23:24:05.160616 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1409 23:24:05.164218 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1410 23:24:05.167198 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1411 23:24:05.174033 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1412 23:24:05.177364 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1413 23:24:05.180726 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1414 23:24:05.183999 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1415 23:24:05.187544 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1416 23:24:05.190821 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1417 23:24:05.197419 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1418 23:24:05.201216 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1419 23:24:05.204039 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1420 23:24:05.207838 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1421 23:24:05.207917 ==
1422 23:24:05.210827 Dram Type= 6, Freq= 0, CH_0, rank 1
1423 23:24:05.217389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 23:24:05.217468 ==
1425 23:24:05.217530 DQS Delay:
1426 23:24:05.220791 DQS0 = 0, DQS1 = 0
1427 23:24:05.220895 DQM Delay:
1428 23:24:05.220986 DQM0 = 87, DQM1 = 78
1429 23:24:05.224486 DQ Delay:
1430 23:24:05.227643 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1431 23:24:05.231312 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1432 23:24:05.234366 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1433 23:24:05.237945 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1434 23:24:05.238028
1435 23:24:05.238090
1436 23:24:05.244471 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1437 23:24:05.247755 CH0 RK1: MR19=606, MR18=2F19
1438 23:24:05.254343 CH0_RK1: MR19=0x606, MR18=0x2F19, DQSOSC=397, MR23=63, INC=93, DEC=62
1439 23:24:05.257582 [RxdqsGatingPostProcess] freq 800
1440 23:24:05.261245 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1441 23:24:05.264729 Pre-setting of DQS Precalculation
1442 23:24:05.271141 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1443 23:24:05.271244 ==
1444 23:24:05.274349 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 23:24:05.277822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 23:24:05.277897 ==
1447 23:24:05.284572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1448 23:24:05.287992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1449 23:24:05.297705 [CA 0] Center 36 (6~67) winsize 62
1450 23:24:05.301232 [CA 1] Center 36 (6~66) winsize 61
1451 23:24:05.304680 [CA 2] Center 34 (4~64) winsize 61
1452 23:24:05.308237 [CA 3] Center 33 (3~64) winsize 62
1453 23:24:05.311095 [CA 4] Center 34 (4~65) winsize 62
1454 23:24:05.314664 [CA 5] Center 33 (3~64) winsize 62
1455 23:24:05.314738
1456 23:24:05.317887 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1457 23:24:05.317958
1458 23:24:05.321406 [CATrainingPosCal] consider 1 rank data
1459 23:24:05.324332 u2DelayCellTimex100 = 270/100 ps
1460 23:24:05.328063 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1461 23:24:05.331163 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1462 23:24:05.334817 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1463 23:24:05.341354 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 23:24:05.344891 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1465 23:24:05.347999 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1466 23:24:05.348141
1467 23:24:05.351476 CA PerBit enable=1, Macro0, CA PI delay=33
1468 23:24:05.351551
1469 23:24:05.354681 [CBTSetCACLKResult] CA Dly = 33
1470 23:24:05.354786 CS Dly: 4 (0~35)
1471 23:24:05.354877 ==
1472 23:24:05.358261 Dram Type= 6, Freq= 0, CH_1, rank 1
1473 23:24:05.364912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 23:24:05.364991 ==
1475 23:24:05.368071 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1476 23:24:05.374770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1477 23:24:05.383898 [CA 0] Center 36 (6~67) winsize 62
1478 23:24:05.387357 [CA 1] Center 36 (6~66) winsize 61
1479 23:24:05.390633 [CA 2] Center 34 (4~65) winsize 62
1480 23:24:05.394216 [CA 3] Center 33 (3~64) winsize 62
1481 23:24:05.397447 [CA 4] Center 34 (4~65) winsize 62
1482 23:24:05.400729 [CA 5] Center 33 (3~64) winsize 62
1483 23:24:05.400828
1484 23:24:05.404311 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1485 23:24:05.404409
1486 23:24:05.408303 [CATrainingPosCal] consider 2 rank data
1487 23:24:05.411807 u2DelayCellTimex100 = 270/100 ps
1488 23:24:05.415888 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1489 23:24:05.419607 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1490 23:24:05.423050 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1491 23:24:05.426959 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1492 23:24:05.431163 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1493 23:24:05.434345 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1494 23:24:05.434457
1495 23:24:05.437983 CA PerBit enable=1, Macro0, CA PI delay=33
1496 23:24:05.438087
1497 23:24:05.441417 [CBTSetCACLKResult] CA Dly = 33
1498 23:24:05.441492 CS Dly: 5 (0~37)
1499 23:24:05.441553
1500 23:24:05.445021 ----->DramcWriteLeveling(PI) begin...
1501 23:24:05.445099 ==
1502 23:24:05.448655 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 23:24:05.451756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 23:24:05.454797 ==
1505 23:24:05.454869 Write leveling (Byte 0): 27 => 27
1506 23:24:05.458174 Write leveling (Byte 1): 31 => 31
1507 23:24:05.461420 DramcWriteLeveling(PI) end<-----
1508 23:24:05.461522
1509 23:24:05.461613 ==
1510 23:24:05.464853 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 23:24:05.471509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1512 23:24:05.471597 ==
1513 23:24:05.471663 [Gating] SW mode calibration
1514 23:24:05.481822 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1515 23:24:05.484916 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1516 23:24:05.488404 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1517 23:24:05.494961 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 23:24:05.498504 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1519 23:24:05.501965 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:24:05.508445 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:24:05.511917 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:24:05.515370 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:24:05.521620 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:24:05.525109 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:24:05.528406 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:24:05.531842 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:24:05.539226 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:24:05.542110 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:24:05.545556 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:24:05.552120 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:24:05.555702 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:24:05.558863 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:24:05.565816 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:24:05.568843 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1535 23:24:05.572307 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:24:05.578970 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:24:05.582169 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:24:05.585405 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:24:05.592020 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:24:05.595481 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:24:05.599404 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:24:05.602185 0 9 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1543 23:24:05.609014 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1544 23:24:05.612509 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 23:24:05.615948 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 23:24:05.622332 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 23:24:05.625869 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 23:24:05.629047 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 23:24:05.635870 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1550 23:24:05.639398 0 10 8 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 0)
1551 23:24:05.642592 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 23:24:05.649460 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 23:24:05.652416 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 23:24:05.655652 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 23:24:05.662548 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 23:24:05.665815 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 23:24:05.669341 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 23:24:05.672724 0 11 8 | B1->B0 | 3030 2828 | 0 1 | (0 0) (0 0)
1559 23:24:05.679671 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 23:24:05.682741 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 23:24:05.686125 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 23:24:05.692730 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 23:24:05.696196 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 23:24:05.699382 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 23:24:05.706342 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 23:24:05.709778 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1567 23:24:05.713129 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:24:05.719469 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 23:24:05.722816 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:24:05.726893 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:24:05.729547 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:24:05.736743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:24:05.739779 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:24:05.743559 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:24:05.749754 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:24:05.753358 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:24:05.756659 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:24:05.763238 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:24:05.766531 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 23:24:05.770164 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:24:05.776886 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1582 23:24:05.779844 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1583 23:24:05.783324 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 23:24:05.786577 Total UI for P1: 0, mck2ui 16
1585 23:24:05.789830 best dqsien dly found for B0: ( 0, 14, 6)
1586 23:24:05.793742 Total UI for P1: 0, mck2ui 16
1587 23:24:05.796895 best dqsien dly found for B1: ( 0, 14, 6)
1588 23:24:05.799980 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1589 23:24:05.803568 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1590 23:24:05.803666
1591 23:24:05.806673 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1592 23:24:05.810018 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1593 23:24:05.813748 [Gating] SW calibration Done
1594 23:24:05.813823 ==
1595 23:24:05.816983 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 23:24:05.820016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 23:24:05.823366 ==
1598 23:24:05.823461 RX Vref Scan: 0
1599 23:24:05.823552
1600 23:24:05.826985 RX Vref 0 -> 0, step: 1
1601 23:24:05.827078
1602 23:24:05.830366 RX Delay -130 -> 252, step: 16
1603 23:24:05.833734 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1604 23:24:05.837181 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1605 23:24:05.840135 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1606 23:24:05.843976 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1607 23:24:05.850231 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1608 23:24:05.853812 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1609 23:24:05.857442 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1610 23:24:05.860442 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1611 23:24:05.863756 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1612 23:24:05.867217 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1613 23:24:05.873880 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1614 23:24:05.877219 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1615 23:24:05.880793 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1616 23:24:05.884352 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1617 23:24:05.887083 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1618 23:24:05.893776 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1619 23:24:05.893853 ==
1620 23:24:05.897310 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 23:24:05.900690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 23:24:05.900762 ==
1623 23:24:05.900822 DQS Delay:
1624 23:24:05.903784 DQS0 = 0, DQS1 = 0
1625 23:24:05.903858 DQM Delay:
1626 23:24:05.907176 DQM0 = 82, DQM1 = 76
1627 23:24:05.907245 DQ Delay:
1628 23:24:05.910981 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1629 23:24:05.914295 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =77
1630 23:24:05.917335 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1631 23:24:05.920719 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1632 23:24:05.920788
1633 23:24:05.920848
1634 23:24:05.920904 ==
1635 23:24:05.924585 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 23:24:05.927859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 23:24:05.927956 ==
1638 23:24:05.928046
1639 23:24:05.928131
1640 23:24:05.930850 TX Vref Scan disable
1641 23:24:05.934281 == TX Byte 0 ==
1642 23:24:05.937767 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1643 23:24:05.940901 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1644 23:24:05.944322 == TX Byte 1 ==
1645 23:24:05.947810 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1646 23:24:05.950932 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1647 23:24:05.951002 ==
1648 23:24:05.954506 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 23:24:05.960940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 23:24:05.961042 ==
1651 23:24:05.972744 TX Vref=22, minBit 11, minWin=26, winSum=437
1652 23:24:05.976355 TX Vref=24, minBit 8, minWin=27, winSum=447
1653 23:24:05.979601 TX Vref=26, minBit 0, minWin=27, winSum=448
1654 23:24:05.982855 TX Vref=28, minBit 11, minWin=27, winSum=451
1655 23:24:05.986750 TX Vref=30, minBit 0, minWin=28, winSum=454
1656 23:24:05.989969 TX Vref=32, minBit 1, minWin=28, winSum=455
1657 23:24:05.996530 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 32
1658 23:24:05.996613
1659 23:24:05.999913 Final TX Range 1 Vref 32
1660 23:24:05.999994
1661 23:24:06.000058 ==
1662 23:24:06.003534 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 23:24:06.006637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 23:24:06.006719 ==
1665 23:24:06.006783
1666 23:24:06.006843
1667 23:24:06.010176 TX Vref Scan disable
1668 23:24:06.013249 == TX Byte 0 ==
1669 23:24:06.016492 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1670 23:24:06.020181 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1671 23:24:06.023886 == TX Byte 1 ==
1672 23:24:06.026760 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1673 23:24:06.029945 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1674 23:24:06.030019
1675 23:24:06.033075 [DATLAT]
1676 23:24:06.033147 Freq=800, CH1 RK0
1677 23:24:06.033207
1678 23:24:06.037073 DATLAT Default: 0xa
1679 23:24:06.037168 0, 0xFFFF, sum = 0
1680 23:24:06.040026 1, 0xFFFF, sum = 0
1681 23:24:06.040115 2, 0xFFFF, sum = 0
1682 23:24:06.043299 3, 0xFFFF, sum = 0
1683 23:24:06.043371 4, 0xFFFF, sum = 0
1684 23:24:06.046597 5, 0xFFFF, sum = 0
1685 23:24:06.046683 6, 0xFFFF, sum = 0
1686 23:24:06.050069 7, 0xFFFF, sum = 0
1687 23:24:06.050166 8, 0xFFFF, sum = 0
1688 23:24:06.053517 9, 0x0, sum = 1
1689 23:24:06.053589 10, 0x0, sum = 2
1690 23:24:06.056970 11, 0x0, sum = 3
1691 23:24:06.057076 12, 0x0, sum = 4
1692 23:24:06.060567 best_step = 10
1693 23:24:06.060662
1694 23:24:06.060748 ==
1695 23:24:06.063454 Dram Type= 6, Freq= 0, CH_1, rank 0
1696 23:24:06.066750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1697 23:24:06.066829 ==
1698 23:24:06.066888 RX Vref Scan: 1
1699 23:24:06.070505
1700 23:24:06.070584 Set Vref Range= 32 -> 127
1701 23:24:06.070646
1702 23:24:06.073616 RX Vref 32 -> 127, step: 1
1703 23:24:06.073709
1704 23:24:06.077283 RX Delay -95 -> 252, step: 8
1705 23:24:06.077384
1706 23:24:06.080316 Set Vref, RX VrefLevel [Byte0]: 32
1707 23:24:06.083660 [Byte1]: 32
1708 23:24:06.083763
1709 23:24:06.086827 Set Vref, RX VrefLevel [Byte0]: 33
1710 23:24:06.090129 [Byte1]: 33
1711 23:24:06.090225
1712 23:24:06.093557 Set Vref, RX VrefLevel [Byte0]: 34
1713 23:24:06.096972 [Byte1]: 34
1714 23:24:06.100606
1715 23:24:06.100681 Set Vref, RX VrefLevel [Byte0]: 35
1716 23:24:06.107308 [Byte1]: 35
1717 23:24:06.107383
1718 23:24:06.110524 Set Vref, RX VrefLevel [Byte0]: 36
1719 23:24:06.114184 [Byte1]: 36
1720 23:24:06.114266
1721 23:24:06.117531 Set Vref, RX VrefLevel [Byte0]: 37
1722 23:24:06.121082 [Byte1]: 37
1723 23:24:06.121179
1724 23:24:06.124470 Set Vref, RX VrefLevel [Byte0]: 38
1725 23:24:06.127375 [Byte1]: 38
1726 23:24:06.131029
1727 23:24:06.131108 Set Vref, RX VrefLevel [Byte0]: 39
1728 23:24:06.134362 [Byte1]: 39
1729 23:24:06.139156
1730 23:24:06.139240 Set Vref, RX VrefLevel [Byte0]: 40
1731 23:24:06.142347 [Byte1]: 40
1732 23:24:06.146196
1733 23:24:06.146277 Set Vref, RX VrefLevel [Byte0]: 41
1734 23:24:06.150047 [Byte1]: 41
1735 23:24:06.153795
1736 23:24:06.153871 Set Vref, RX VrefLevel [Byte0]: 42
1737 23:24:06.157547 [Byte1]: 42
1738 23:24:06.161673
1739 23:24:06.161745 Set Vref, RX VrefLevel [Byte0]: 43
1740 23:24:06.164899 [Byte1]: 43
1741 23:24:06.168915
1742 23:24:06.168992 Set Vref, RX VrefLevel [Byte0]: 44
1743 23:24:06.172199 [Byte1]: 44
1744 23:24:06.176913
1745 23:24:06.176990 Set Vref, RX VrefLevel [Byte0]: 45
1746 23:24:06.180029 [Byte1]: 45
1747 23:24:06.184690
1748 23:24:06.184805 Set Vref, RX VrefLevel [Byte0]: 46
1749 23:24:06.187535 [Byte1]: 46
1750 23:24:06.191923
1751 23:24:06.192001 Set Vref, RX VrefLevel [Byte0]: 47
1752 23:24:06.198708 [Byte1]: 47
1753 23:24:06.198785
1754 23:24:06.202074 Set Vref, RX VrefLevel [Byte0]: 48
1755 23:24:06.205326 [Byte1]: 48
1756 23:24:06.205416
1757 23:24:06.209274 Set Vref, RX VrefLevel [Byte0]: 49
1758 23:24:06.212052 [Byte1]: 49
1759 23:24:06.212142
1760 23:24:06.215579 Set Vref, RX VrefLevel [Byte0]: 50
1761 23:24:06.218391 [Byte1]: 50
1762 23:24:06.222406
1763 23:24:06.222510 Set Vref, RX VrefLevel [Byte0]: 51
1764 23:24:06.225867 [Byte1]: 51
1765 23:24:06.229954
1766 23:24:06.230027 Set Vref, RX VrefLevel [Byte0]: 52
1767 23:24:06.233559 [Byte1]: 52
1768 23:24:06.237704
1769 23:24:06.237776 Set Vref, RX VrefLevel [Byte0]: 53
1770 23:24:06.240804 [Byte1]: 53
1771 23:24:06.245207
1772 23:24:06.245289 Set Vref, RX VrefLevel [Byte0]: 54
1773 23:24:06.248335 [Byte1]: 54
1774 23:24:06.252659
1775 23:24:06.252735 Set Vref, RX VrefLevel [Byte0]: 55
1776 23:24:06.255949 [Byte1]: 55
1777 23:24:06.262682
1778 23:24:06.262779 Set Vref, RX VrefLevel [Byte0]: 56
1779 23:24:06.263742 [Byte1]: 56
1780 23:24:06.267928
1781 23:24:06.268008 Set Vref, RX VrefLevel [Byte0]: 57
1782 23:24:06.271282 [Byte1]: 57
1783 23:24:06.275801
1784 23:24:06.275877 Set Vref, RX VrefLevel [Byte0]: 58
1785 23:24:06.278855 [Byte1]: 58
1786 23:24:06.283944
1787 23:24:06.284025 Set Vref, RX VrefLevel [Byte0]: 59
1788 23:24:06.286629 [Byte1]: 59
1789 23:24:06.290917
1790 23:24:06.290995 Set Vref, RX VrefLevel [Byte0]: 60
1791 23:24:06.294104 [Byte1]: 60
1792 23:24:06.298238
1793 23:24:06.298320 Set Vref, RX VrefLevel [Byte0]: 61
1794 23:24:06.301944 [Byte1]: 61
1795 23:24:06.305834
1796 23:24:06.305912 Set Vref, RX VrefLevel [Byte0]: 62
1797 23:24:06.309156 [Byte1]: 62
1798 23:24:06.313885
1799 23:24:06.313959 Set Vref, RX VrefLevel [Byte0]: 63
1800 23:24:06.316854 [Byte1]: 63
1801 23:24:06.321350
1802 23:24:06.321425 Set Vref, RX VrefLevel [Byte0]: 64
1803 23:24:06.324223 [Byte1]: 64
1804 23:24:06.328792
1805 23:24:06.328870 Set Vref, RX VrefLevel [Byte0]: 65
1806 23:24:06.331853 [Byte1]: 65
1807 23:24:06.336229
1808 23:24:06.336321 Set Vref, RX VrefLevel [Byte0]: 66
1809 23:24:06.339815 [Byte1]: 66
1810 23:24:06.343836
1811 23:24:06.343908 Set Vref, RX VrefLevel [Byte0]: 67
1812 23:24:06.347276 [Byte1]: 67
1813 23:24:06.351405
1814 23:24:06.351484 Set Vref, RX VrefLevel [Byte0]: 68
1815 23:24:06.354724 [Byte1]: 68
1816 23:24:06.359201
1817 23:24:06.359278 Set Vref, RX VrefLevel [Byte0]: 69
1818 23:24:06.362638 [Byte1]: 69
1819 23:24:06.366832
1820 23:24:06.366910 Set Vref, RX VrefLevel [Byte0]: 70
1821 23:24:06.369969 [Byte1]: 70
1822 23:24:06.374281
1823 23:24:06.374410 Set Vref, RX VrefLevel [Byte0]: 71
1824 23:24:06.377753 [Byte1]: 71
1825 23:24:06.382163
1826 23:24:06.382264 Set Vref, RX VrefLevel [Byte0]: 72
1827 23:24:06.384982 [Byte1]: 72
1828 23:24:06.389676
1829 23:24:06.389756 Set Vref, RX VrefLevel [Byte0]: 73
1830 23:24:06.392740 [Byte1]: 73
1831 23:24:06.397118
1832 23:24:06.397199 Set Vref, RX VrefLevel [Byte0]: 74
1833 23:24:06.400204 [Byte1]: 74
1834 23:24:06.404576
1835 23:24:06.404652 Set Vref, RX VrefLevel [Byte0]: 75
1836 23:24:06.408059 [Byte1]: 75
1837 23:24:06.412780
1838 23:24:06.412853 Set Vref, RX VrefLevel [Byte0]: 76
1839 23:24:06.415727 [Byte1]: 76
1840 23:24:06.419892
1841 23:24:06.419970 Set Vref, RX VrefLevel [Byte0]: 77
1842 23:24:06.423182 [Byte1]: 77
1843 23:24:06.427465
1844 23:24:06.427546 Set Vref, RX VrefLevel [Byte0]: 78
1845 23:24:06.431041 [Byte1]: 78
1846 23:24:06.435213
1847 23:24:06.435294 Set Vref, RX VrefLevel [Byte0]: 79
1848 23:24:06.438651 [Byte1]: 79
1849 23:24:06.442712
1850 23:24:06.442793 Set Vref, RX VrefLevel [Byte0]: 80
1851 23:24:06.445973 [Byte1]: 80
1852 23:24:06.450096
1853 23:24:06.450179 Final RX Vref Byte 0 = 60 to rank0
1854 23:24:06.453868 Final RX Vref Byte 1 = 58 to rank0
1855 23:24:06.457229 Final RX Vref Byte 0 = 60 to rank1
1856 23:24:06.460143 Final RX Vref Byte 1 = 58 to rank1==
1857 23:24:06.463667 Dram Type= 6, Freq= 0, CH_1, rank 0
1858 23:24:06.467385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 23:24:06.470281 ==
1860 23:24:06.470363 DQS Delay:
1861 23:24:06.470471 DQS0 = 0, DQS1 = 0
1862 23:24:06.474255 DQM Delay:
1863 23:24:06.474338 DQM0 = 83, DQM1 = 75
1864 23:24:06.476995 DQ Delay:
1865 23:24:06.477107 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1866 23:24:06.480991 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =76
1867 23:24:06.483851 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
1868 23:24:06.487204 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1869 23:24:06.487331
1870 23:24:06.490346
1871 23:24:06.497171 [DQSOSCAuto] RK0, (LSB)MR18= 0x28fd, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1872 23:24:06.500696 CH1 RK0: MR19=605, MR18=28FD
1873 23:24:06.507677 CH1_RK0: MR19=0x605, MR18=0x28FD, DQSOSC=399, MR23=63, INC=92, DEC=61
1874 23:24:06.507760
1875 23:24:06.511076 ----->DramcWriteLeveling(PI) begin...
1876 23:24:06.511185 ==
1877 23:24:06.513970 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 23:24:06.517378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 23:24:06.517460 ==
1880 23:24:06.520891 Write leveling (Byte 0): 28 => 28
1881 23:24:06.524074 Write leveling (Byte 1): 28 => 28
1882 23:24:06.527760 DramcWriteLeveling(PI) end<-----
1883 23:24:06.527841
1884 23:24:06.527904 ==
1885 23:24:06.530773 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 23:24:06.534230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 23:24:06.534327 ==
1888 23:24:06.537492 [Gating] SW mode calibration
1889 23:24:06.544312 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1890 23:24:06.550875 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1891 23:24:06.554085 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1892 23:24:06.557615 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1893 23:24:06.560953 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:24:06.567574 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:24:06.570952 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:24:06.574169 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:24:06.581210 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:24:06.584138 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 23:24:06.587628 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 23:24:06.594890 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 23:24:06.597724 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 23:24:06.600982 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 23:24:06.607887 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 23:24:06.611271 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 23:24:06.614631 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 23:24:06.617909 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:24:06.624974 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1908 23:24:06.627862 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1909 23:24:06.631715 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 23:24:06.638442 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 23:24:06.641728 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 23:24:06.645008 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 23:24:06.651587 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 23:24:06.655193 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 23:24:06.658145 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 23:24:06.664719 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 23:24:06.668248 0 9 8 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
1918 23:24:06.671742 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 23:24:06.675156 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 23:24:06.681807 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 23:24:06.684919 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 23:24:06.688415 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1923 23:24:06.695228 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1924 23:24:06.698713 0 10 4 | B1->B0 | 3030 2a2a | 1 1 | (1 1) (1 0)
1925 23:24:06.701940 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
1926 23:24:06.708521 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 23:24:06.711834 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 23:24:06.715289 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 23:24:06.721820 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 23:24:06.725281 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1931 23:24:06.728757 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1932 23:24:06.732193 0 11 4 | B1->B0 | 2929 3636 | 0 0 | (0 0) (0 0)
1933 23:24:06.738935 0 11 8 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
1934 23:24:06.742025 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 23:24:06.745446 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 23:24:06.752379 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 23:24:06.755993 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 23:24:06.758700 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 23:24:06.765667 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 23:24:06.769436 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1941 23:24:06.772164 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1942 23:24:06.779071 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 23:24:06.782317 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 23:24:06.785633 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 23:24:06.792122 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 23:24:06.795689 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 23:24:06.798911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 23:24:06.802898 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 23:24:06.809964 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 23:24:06.812666 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 23:24:06.815831 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 23:24:06.822760 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 23:24:06.825815 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 23:24:06.829580 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 23:24:06.836311 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 23:24:06.839455 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1957 23:24:06.843006 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1958 23:24:06.846372 Total UI for P1: 0, mck2ui 16
1959 23:24:06.849246 best dqsien dly found for B0: ( 0, 14, 4)
1960 23:24:06.852861 Total UI for P1: 0, mck2ui 16
1961 23:24:06.855978 best dqsien dly found for B1: ( 0, 14, 4)
1962 23:24:06.859692 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1963 23:24:06.863222 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1964 23:24:06.863303
1965 23:24:06.866530 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1966 23:24:06.869480 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1967 23:24:06.873059 [Gating] SW calibration Done
1968 23:24:06.873141 ==
1969 23:24:06.875970 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 23:24:06.882905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 23:24:06.883005 ==
1972 23:24:06.883072 RX Vref Scan: 0
1973 23:24:06.883153
1974 23:24:06.886471 RX Vref 0 -> 0, step: 1
1975 23:24:06.886561
1976 23:24:06.889377 RX Delay -130 -> 252, step: 16
1977 23:24:06.892811 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1978 23:24:06.896215 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1979 23:24:06.899494 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1980 23:24:06.902818 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1981 23:24:06.909434 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1982 23:24:06.912861 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1983 23:24:06.916765 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1984 23:24:06.919632 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1985 23:24:06.923195 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1986 23:24:06.929692 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1987 23:24:06.933250 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1988 23:24:06.936539 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1989 23:24:06.939854 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1990 23:24:06.943272 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1991 23:24:06.950118 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1992 23:24:06.953906 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1993 23:24:06.953987 ==
1994 23:24:06.956463 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 23:24:06.960446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 23:24:06.960526 ==
1997 23:24:06.960590 DQS Delay:
1998 23:24:06.963176 DQS0 = 0, DQS1 = 0
1999 23:24:06.963257 DQM Delay:
2000 23:24:06.966915 DQM0 = 82, DQM1 = 76
2001 23:24:06.967013 DQ Delay:
2002 23:24:06.970554 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
2003 23:24:06.973892 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
2004 23:24:06.976910 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
2005 23:24:06.980289 DQ12 =85, DQ13 =93, DQ14 =85, DQ15 =85
2006 23:24:06.980369
2007 23:24:06.980433
2008 23:24:06.980493 ==
2009 23:24:06.983673 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 23:24:06.986973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 23:24:06.987055 ==
2012 23:24:06.990107
2013 23:24:06.990187
2014 23:24:06.990251 TX Vref Scan disable
2015 23:24:06.993761 == TX Byte 0 ==
2016 23:24:06.997185 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2017 23:24:07.000637 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2018 23:24:07.003915 == TX Byte 1 ==
2019 23:24:07.007357 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2020 23:24:07.010557 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2021 23:24:07.010639 ==
2022 23:24:07.013635 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 23:24:07.020239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 23:24:07.020321 ==
2025 23:24:07.031738 TX Vref=22, minBit 1, minWin=27, winSum=442
2026 23:24:07.035126 TX Vref=24, minBit 1, minWin=27, winSum=445
2027 23:24:07.038892 TX Vref=26, minBit 1, minWin=27, winSum=446
2028 23:24:07.041932 TX Vref=28, minBit 13, minWin=27, winSum=448
2029 23:24:07.045471 TX Vref=30, minBit 0, minWin=28, winSum=451
2030 23:24:07.048598 TX Vref=32, minBit 0, minWin=28, winSum=453
2031 23:24:07.055136 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
2032 23:24:07.055218
2033 23:24:07.058517 Final TX Range 1 Vref 32
2034 23:24:07.058599
2035 23:24:07.058663 ==
2036 23:24:07.062325 Dram Type= 6, Freq= 0, CH_1, rank 1
2037 23:24:07.065505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2038 23:24:07.065593 ==
2039 23:24:07.065724
2040 23:24:07.065817
2041 23:24:07.068667 TX Vref Scan disable
2042 23:24:07.072498 == TX Byte 0 ==
2043 23:24:07.075509 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2044 23:24:07.078828 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2045 23:24:07.082313 == TX Byte 1 ==
2046 23:24:07.085406 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2047 23:24:07.089094 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2048 23:24:07.089176
2049 23:24:07.092329 [DATLAT]
2050 23:24:07.092410 Freq=800, CH1 RK1
2051 23:24:07.092475
2052 23:24:07.095352 DATLAT Default: 0xa
2053 23:24:07.095433 0, 0xFFFF, sum = 0
2054 23:24:07.099401 1, 0xFFFF, sum = 0
2055 23:24:07.099483 2, 0xFFFF, sum = 0
2056 23:24:07.102113 3, 0xFFFF, sum = 0
2057 23:24:07.102196 4, 0xFFFF, sum = 0
2058 23:24:07.105269 5, 0xFFFF, sum = 0
2059 23:24:07.105377 6, 0xFFFF, sum = 0
2060 23:24:07.109209 7, 0xFFFF, sum = 0
2061 23:24:07.109292 8, 0xFFFF, sum = 0
2062 23:24:07.112614 9, 0x0, sum = 1
2063 23:24:07.112696 10, 0x0, sum = 2
2064 23:24:07.115539 11, 0x0, sum = 3
2065 23:24:07.115622 12, 0x0, sum = 4
2066 23:24:07.118765 best_step = 10
2067 23:24:07.118846
2068 23:24:07.118910 ==
2069 23:24:07.122364 Dram Type= 6, Freq= 0, CH_1, rank 1
2070 23:24:07.125915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2071 23:24:07.125997 ==
2072 23:24:07.129053 RX Vref Scan: 0
2073 23:24:07.129148
2074 23:24:07.129213 RX Vref 0 -> 0, step: 1
2075 23:24:07.129273
2076 23:24:07.132368 RX Delay -111 -> 252, step: 8
2077 23:24:07.138905 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2078 23:24:07.142177 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2079 23:24:07.146203 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2080 23:24:07.149234 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2081 23:24:07.152268 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2082 23:24:07.155839 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2083 23:24:07.162821 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2084 23:24:07.165718 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2085 23:24:07.169016 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2086 23:24:07.172696 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2087 23:24:07.176010 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2088 23:24:07.182935 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2089 23:24:07.186122 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2090 23:24:07.188974 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2091 23:24:07.192508 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2092 23:24:07.199308 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2093 23:24:07.199390 ==
2094 23:24:07.202260 Dram Type= 6, Freq= 0, CH_1, rank 1
2095 23:24:07.206145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2096 23:24:07.206255 ==
2097 23:24:07.206351 DQS Delay:
2098 23:24:07.209198 DQS0 = 0, DQS1 = 0
2099 23:24:07.209279 DQM Delay:
2100 23:24:07.212293 DQM0 = 80, DQM1 = 75
2101 23:24:07.212375 DQ Delay:
2102 23:24:07.215946 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2103 23:24:07.219154 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2104 23:24:07.222882 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2105 23:24:07.225690 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2106 23:24:07.225798
2107 23:24:07.225886
2108 23:24:07.232410 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
2109 23:24:07.235978 CH1 RK1: MR19=606, MR18=1C27
2110 23:24:07.242729 CH1_RK1: MR19=0x606, MR18=0x1C27, DQSOSC=400, MR23=63, INC=92, DEC=61
2111 23:24:07.246186 [RxdqsGatingPostProcess] freq 800
2112 23:24:07.249493 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2113 23:24:07.252781 Pre-setting of DQS Precalculation
2114 23:24:07.259278 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2115 23:24:07.265978 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2116 23:24:07.272789 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2117 23:24:07.272871
2118 23:24:07.272935
2119 23:24:07.275988 [Calibration Summary] 1600 Mbps
2120 23:24:07.276070 CH 0, Rank 0
2121 23:24:07.279839 SW Impedance : PASS
2122 23:24:07.283075 DUTY Scan : NO K
2123 23:24:07.283156 ZQ Calibration : PASS
2124 23:24:07.286170 Jitter Meter : NO K
2125 23:24:07.289500 CBT Training : PASS
2126 23:24:07.289582 Write leveling : PASS
2127 23:24:07.293116 RX DQS gating : PASS
2128 23:24:07.296215 RX DQ/DQS(RDDQC) : PASS
2129 23:24:07.296296 TX DQ/DQS : PASS
2130 23:24:07.299740 RX DATLAT : PASS
2131 23:24:07.299821 RX DQ/DQS(Engine): PASS
2132 23:24:07.303021 TX OE : NO K
2133 23:24:07.303103 All Pass.
2134 23:24:07.303168
2135 23:24:07.306582 CH 0, Rank 1
2136 23:24:07.306662 SW Impedance : PASS
2137 23:24:07.309740 DUTY Scan : NO K
2138 23:24:07.313539 ZQ Calibration : PASS
2139 23:24:07.313619 Jitter Meter : NO K
2140 23:24:07.316540 CBT Training : PASS
2141 23:24:07.320057 Write leveling : PASS
2142 23:24:07.320137 RX DQS gating : PASS
2143 23:24:07.323071 RX DQ/DQS(RDDQC) : PASS
2144 23:24:07.326548 TX DQ/DQS : PASS
2145 23:24:07.326629 RX DATLAT : PASS
2146 23:24:07.329789 RX DQ/DQS(Engine): PASS
2147 23:24:07.329870 TX OE : NO K
2148 23:24:07.333272 All Pass.
2149 23:24:07.333353
2150 23:24:07.333417 CH 1, Rank 0
2151 23:24:07.336655 SW Impedance : PASS
2152 23:24:07.336737 DUTY Scan : NO K
2153 23:24:07.339834 ZQ Calibration : PASS
2154 23:24:07.343608 Jitter Meter : NO K
2155 23:24:07.343690 CBT Training : PASS
2156 23:24:07.346593 Write leveling : PASS
2157 23:24:07.350088 RX DQS gating : PASS
2158 23:24:07.350170 RX DQ/DQS(RDDQC) : PASS
2159 23:24:07.353360 TX DQ/DQS : PASS
2160 23:24:07.356413 RX DATLAT : PASS
2161 23:24:07.356497 RX DQ/DQS(Engine): PASS
2162 23:24:07.359754 TX OE : NO K
2163 23:24:07.359835 All Pass.
2164 23:24:07.359899
2165 23:24:07.363190 CH 1, Rank 1
2166 23:24:07.363270 SW Impedance : PASS
2167 23:24:07.366474 DUTY Scan : NO K
2168 23:24:07.369837 ZQ Calibration : PASS
2169 23:24:07.369921 Jitter Meter : NO K
2170 23:24:07.373471 CBT Training : PASS
2171 23:24:07.373556 Write leveling : PASS
2172 23:24:07.377107 RX DQS gating : PASS
2173 23:24:07.380532 RX DQ/DQS(RDDQC) : PASS
2174 23:24:07.380616 TX DQ/DQS : PASS
2175 23:24:07.383467 RX DATLAT : PASS
2176 23:24:07.386970 RX DQ/DQS(Engine): PASS
2177 23:24:07.387053 TX OE : NO K
2178 23:24:07.390381 All Pass.
2179 23:24:07.390506
2180 23:24:07.390591 DramC Write-DBI off
2181 23:24:07.393540 PER_BANK_REFRESH: Hybrid Mode
2182 23:24:07.393625 TX_TRACKING: ON
2183 23:24:07.396853 [GetDramInforAfterCalByMRR] Vendor 6.
2184 23:24:07.403453 [GetDramInforAfterCalByMRR] Revision 606.
2185 23:24:07.406704 [GetDramInforAfterCalByMRR] Revision 2 0.
2186 23:24:07.406789 MR0 0x3b3b
2187 23:24:07.406875 MR8 0x5151
2188 23:24:07.410195 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2189 23:24:07.410279
2190 23:24:07.413709 MR0 0x3b3b
2191 23:24:07.413794 MR8 0x5151
2192 23:24:07.416957 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2193 23:24:07.417046
2194 23:24:07.426982 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2195 23:24:07.430307 [FAST_K] Save calibration result to emmc
2196 23:24:07.433698 [FAST_K] Save calibration result to emmc
2197 23:24:07.437140 dram_init: config_dvfs: 1
2198 23:24:07.440724 dramc_set_vcore_voltage set vcore to 662500
2199 23:24:07.443545 Read voltage for 1200, 2
2200 23:24:07.443629 Vio18 = 0
2201 23:24:07.443715 Vcore = 662500
2202 23:24:07.443796 Vdram = 0
2203 23:24:07.447105 Vddq = 0
2204 23:24:07.447189 Vmddr = 0
2205 23:24:07.453888 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2206 23:24:07.457237 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2207 23:24:07.460444 MEM_TYPE=3, freq_sel=15
2208 23:24:07.463924 sv_algorithm_assistance_LP4_1600
2209 23:24:07.466870 ============ PULL DRAM RESETB DOWN ============
2210 23:24:07.470324 ========== PULL DRAM RESETB DOWN end =========
2211 23:24:07.477766 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2212 23:24:07.480531 ===================================
2213 23:24:07.480616 LPDDR4 DRAM CONFIGURATION
2214 23:24:07.484066 ===================================
2215 23:24:07.487711 EX_ROW_EN[0] = 0x0
2216 23:24:07.487796 EX_ROW_EN[1] = 0x0
2217 23:24:07.490343 LP4Y_EN = 0x0
2218 23:24:07.490467 WORK_FSP = 0x0
2219 23:24:07.493867 WL = 0x4
2220 23:24:07.497080 RL = 0x4
2221 23:24:07.497164 BL = 0x2
2222 23:24:07.500312 RPST = 0x0
2223 23:24:07.500397 RD_PRE = 0x0
2224 23:24:07.503945 WR_PRE = 0x1
2225 23:24:07.504029 WR_PST = 0x0
2226 23:24:07.507264 DBI_WR = 0x0
2227 23:24:07.507348 DBI_RD = 0x0
2228 23:24:07.510964 OTF = 0x1
2229 23:24:07.514119 ===================================
2230 23:24:07.517459 ===================================
2231 23:24:07.517544 ANA top config
2232 23:24:07.520704 ===================================
2233 23:24:07.524249 DLL_ASYNC_EN = 0
2234 23:24:07.527350 ALL_SLAVE_EN = 0
2235 23:24:07.527435 NEW_RANK_MODE = 1
2236 23:24:07.530720 DLL_IDLE_MODE = 1
2237 23:24:07.534035 LP45_APHY_COMB_EN = 1
2238 23:24:07.537381 TX_ODT_DIS = 1
2239 23:24:07.537466 NEW_8X_MODE = 1
2240 23:24:07.540579 ===================================
2241 23:24:07.543739 ===================================
2242 23:24:07.547069 data_rate = 2400
2243 23:24:07.550733 CKR = 1
2244 23:24:07.554034 DQ_P2S_RATIO = 8
2245 23:24:07.557485 ===================================
2246 23:24:07.560712 CA_P2S_RATIO = 8
2247 23:24:07.563940 DQ_CA_OPEN = 0
2248 23:24:07.564025 DQ_SEMI_OPEN = 0
2249 23:24:07.567503 CA_SEMI_OPEN = 0
2250 23:24:07.571217 CA_FULL_RATE = 0
2251 23:24:07.574366 DQ_CKDIV4_EN = 0
2252 23:24:07.577766 CA_CKDIV4_EN = 0
2253 23:24:07.577851 CA_PREDIV_EN = 0
2254 23:24:07.581278 PH8_DLY = 17
2255 23:24:07.584521 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2256 23:24:07.587496 DQ_AAMCK_DIV = 4
2257 23:24:07.591028 CA_AAMCK_DIV = 4
2258 23:24:07.594531 CA_ADMCK_DIV = 4
2259 23:24:07.594616 DQ_TRACK_CA_EN = 0
2260 23:24:07.597762 CA_PICK = 1200
2261 23:24:07.601007 CA_MCKIO = 1200
2262 23:24:07.604411 MCKIO_SEMI = 0
2263 23:24:07.607922 PLL_FREQ = 2366
2264 23:24:07.611010 DQ_UI_PI_RATIO = 32
2265 23:24:07.614383 CA_UI_PI_RATIO = 0
2266 23:24:07.618148 ===================================
2267 23:24:07.620968 ===================================
2268 23:24:07.621096 memory_type:LPDDR4
2269 23:24:07.624229 GP_NUM : 10
2270 23:24:07.628012 SRAM_EN : 1
2271 23:24:07.628085 MD32_EN : 0
2272 23:24:07.631197 ===================================
2273 23:24:07.634818 [ANA_INIT] >>>>>>>>>>>>>>
2274 23:24:07.637784 <<<<<< [CONFIGURE PHASE]: ANA_TX
2275 23:24:07.641156 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2276 23:24:07.644980 ===================================
2277 23:24:07.645085 data_rate = 2400,PCW = 0X5b00
2278 23:24:07.648094 ===================================
2279 23:24:07.651346 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2280 23:24:07.657959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2281 23:24:07.664746 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2282 23:24:07.668392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2283 23:24:07.671558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2284 23:24:07.674618 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2285 23:24:07.678036 [ANA_INIT] flow start
2286 23:24:07.678108 [ANA_INIT] PLL >>>>>>>>
2287 23:24:07.681394 [ANA_INIT] PLL <<<<<<<<
2288 23:24:07.684884 [ANA_INIT] MIDPI >>>>>>>>
2289 23:24:07.688304 [ANA_INIT] MIDPI <<<<<<<<
2290 23:24:07.688383 [ANA_INIT] DLL >>>>>>>>
2291 23:24:07.691731 [ANA_INIT] DLL <<<<<<<<
2292 23:24:07.694711 [ANA_INIT] flow end
2293 23:24:07.698430 ============ LP4 DIFF to SE enter ============
2294 23:24:07.701372 ============ LP4 DIFF to SE exit ============
2295 23:24:07.704905 [ANA_INIT] <<<<<<<<<<<<<
2296 23:24:07.707969 [Flow] Enable top DCM control >>>>>
2297 23:24:07.711752 [Flow] Enable top DCM control <<<<<
2298 23:24:07.711833 Enable DLL master slave shuffle
2299 23:24:07.718064 ==============================================================
2300 23:24:07.722070 Gating Mode config
2301 23:24:07.724936 ==============================================================
2302 23:24:07.728592 Config description:
2303 23:24:07.738858 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2304 23:24:07.745443 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2305 23:24:07.748737 SELPH_MODE 0: By rank 1: By Phase
2306 23:24:07.755181 ==============================================================
2307 23:24:07.758454 GAT_TRACK_EN = 1
2308 23:24:07.761847 RX_GATING_MODE = 2
2309 23:24:07.765338 RX_GATING_TRACK_MODE = 2
2310 23:24:07.765423 SELPH_MODE = 1
2311 23:24:07.768610 PICG_EARLY_EN = 1
2312 23:24:07.772046 VALID_LAT_VALUE = 1
2313 23:24:07.779330 ==============================================================
2314 23:24:07.781994 Enter into Gating configuration >>>>
2315 23:24:07.785496 Exit from Gating configuration <<<<
2316 23:24:07.788700 Enter into DVFS_PRE_config >>>>>
2317 23:24:07.798604 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2318 23:24:07.802026 Exit from DVFS_PRE_config <<<<<
2319 23:24:07.805547 Enter into PICG configuration >>>>
2320 23:24:07.809199 Exit from PICG configuration <<<<
2321 23:24:07.812477 [RX_INPUT] configuration >>>>>
2322 23:24:07.815834 [RX_INPUT] configuration <<<<<
2323 23:24:07.818960 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2324 23:24:07.825508 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2325 23:24:07.829177 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2326 23:24:07.835684 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2327 23:24:07.842337 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2328 23:24:07.849100 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2329 23:24:07.852654 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2330 23:24:07.856205 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2331 23:24:07.862662 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2332 23:24:07.865857 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2333 23:24:07.869152 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2334 23:24:07.872660 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2335 23:24:07.876166 ===================================
2336 23:24:07.879887 LPDDR4 DRAM CONFIGURATION
2337 23:24:07.882537 ===================================
2338 23:24:07.885983 EX_ROW_EN[0] = 0x0
2339 23:24:07.886064 EX_ROW_EN[1] = 0x0
2340 23:24:07.889232 LP4Y_EN = 0x0
2341 23:24:07.889344 WORK_FSP = 0x0
2342 23:24:07.893147 WL = 0x4
2343 23:24:07.893229 RL = 0x4
2344 23:24:07.896128 BL = 0x2
2345 23:24:07.896209 RPST = 0x0
2346 23:24:07.899415 RD_PRE = 0x0
2347 23:24:07.899496 WR_PRE = 0x1
2348 23:24:07.902855 WR_PST = 0x0
2349 23:24:07.902935 DBI_WR = 0x0
2350 23:24:07.906254 DBI_RD = 0x0
2351 23:24:07.906361 OTF = 0x1
2352 23:24:07.909735 ===================================
2353 23:24:07.916124 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2354 23:24:07.919763 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2355 23:24:07.923091 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2356 23:24:07.926511 ===================================
2357 23:24:07.929754 LPDDR4 DRAM CONFIGURATION
2358 23:24:07.933361 ===================================
2359 23:24:07.933441 EX_ROW_EN[0] = 0x10
2360 23:24:07.936135 EX_ROW_EN[1] = 0x0
2361 23:24:07.939609 LP4Y_EN = 0x0
2362 23:24:07.939698 WORK_FSP = 0x0
2363 23:24:07.943097 WL = 0x4
2364 23:24:07.943178 RL = 0x4
2365 23:24:07.946596 BL = 0x2
2366 23:24:07.946677 RPST = 0x0
2367 23:24:07.949965 RD_PRE = 0x0
2368 23:24:07.950045 WR_PRE = 0x1
2369 23:24:07.953080 WR_PST = 0x0
2370 23:24:07.953160 DBI_WR = 0x0
2371 23:24:07.956815 DBI_RD = 0x0
2372 23:24:07.956895 OTF = 0x1
2373 23:24:07.959864 ===================================
2374 23:24:07.966911 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2375 23:24:07.966994 ==
2376 23:24:07.969971 Dram Type= 6, Freq= 0, CH_0, rank 0
2377 23:24:07.973281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2378 23:24:07.973355 ==
2379 23:24:07.976856 [Duty_Offset_Calibration]
2380 23:24:07.980357 B0:2 B1:-1 CA:1
2381 23:24:07.980437
2382 23:24:07.983763 [DutyScan_Calibration_Flow] k_type=0
2383 23:24:07.990562
2384 23:24:07.990642 ==CLK 0==
2385 23:24:07.993842 Final CLK duty delay cell = -4
2386 23:24:07.997605 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2387 23:24:08.000691 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2388 23:24:08.004231 [-4] AVG Duty = 4953%(X100)
2389 23:24:08.004310
2390 23:24:08.007520 CH0 CLK Duty spec in!! Max-Min= 156%
2391 23:24:08.010649 [DutyScan_Calibration_Flow] ====Done====
2392 23:24:08.010722
2393 23:24:08.014123 [DutyScan_Calibration_Flow] k_type=1
2394 23:24:08.028821
2395 23:24:08.028901 ==DQS 0 ==
2396 23:24:08.032194 Final DQS duty delay cell = -4
2397 23:24:08.035329 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2398 23:24:08.038707 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2399 23:24:08.042184 [-4] AVG Duty = 4938%(X100)
2400 23:24:08.042264
2401 23:24:08.042327 ==DQS 1 ==
2402 23:24:08.045262 Final DQS duty delay cell = -4
2403 23:24:08.048701 [-4] MAX Duty = 5093%(X100), DQS PI = 16
2404 23:24:08.051800 [-4] MIN Duty = 5000%(X100), DQS PI = 10
2405 23:24:08.055183 [-4] AVG Duty = 5046%(X100)
2406 23:24:08.055263
2407 23:24:08.058825 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2408 23:24:08.058905
2409 23:24:08.062071 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2410 23:24:08.065124 [DutyScan_Calibration_Flow] ====Done====
2411 23:24:08.065209
2412 23:24:08.068500 [DutyScan_Calibration_Flow] k_type=3
2413 23:24:08.086196
2414 23:24:08.086305 ==DQM 0 ==
2415 23:24:08.089136 Final DQM duty delay cell = 0
2416 23:24:08.092446 [0] MAX Duty = 5031%(X100), DQS PI = 54
2417 23:24:08.095631 [0] MIN Duty = 4907%(X100), DQS PI = 2
2418 23:24:08.095716 [0] AVG Duty = 4969%(X100)
2419 23:24:08.099181
2420 23:24:08.099330 ==DQM 1 ==
2421 23:24:08.102287 Final DQM duty delay cell = 0
2422 23:24:08.105984 [0] MAX Duty = 5156%(X100), DQS PI = 62
2423 23:24:08.109362 [0] MIN Duty = 4969%(X100), DQS PI = 10
2424 23:24:08.109445 [0] AVG Duty = 5062%(X100)
2425 23:24:08.112739
2426 23:24:08.116161 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2427 23:24:08.116237
2428 23:24:08.119096 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2429 23:24:08.122292 [DutyScan_Calibration_Flow] ====Done====
2430 23:24:08.122388
2431 23:24:08.125967 [DutyScan_Calibration_Flow] k_type=2
2432 23:24:08.141399
2433 23:24:08.141480 ==DQ 0 ==
2434 23:24:08.144928 Final DQ duty delay cell = -4
2435 23:24:08.148256 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2436 23:24:08.151745 [-4] MIN Duty = 4876%(X100), DQS PI = 10
2437 23:24:08.155009 [-4] AVG Duty = 4969%(X100)
2438 23:24:08.155089
2439 23:24:08.155151 ==DQ 1 ==
2440 23:24:08.158566 Final DQ duty delay cell = 0
2441 23:24:08.162049 [0] MAX Duty = 5031%(X100), DQS PI = 18
2442 23:24:08.165308 [0] MIN Duty = 4907%(X100), DQS PI = 46
2443 23:24:08.165387 [0] AVG Duty = 4969%(X100)
2444 23:24:08.165450
2445 23:24:08.168403 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2446 23:24:08.171843
2447 23:24:08.175227 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2448 23:24:08.178711 [DutyScan_Calibration_Flow] ====Done====
2449 23:24:08.178790 ==
2450 23:24:08.181716 Dram Type= 6, Freq= 0, CH_1, rank 0
2451 23:24:08.185065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2452 23:24:08.185171 ==
2453 23:24:08.188732 [Duty_Offset_Calibration]
2454 23:24:08.188811 B0:1 B1:1 CA:2
2455 23:24:08.188873
2456 23:24:08.191986 [DutyScan_Calibration_Flow] k_type=0
2457 23:24:08.201654
2458 23:24:08.201734 ==CLK 0==
2459 23:24:08.205051 Final CLK duty delay cell = 0
2460 23:24:08.208481 [0] MAX Duty = 5156%(X100), DQS PI = 24
2461 23:24:08.211876 [0] MIN Duty = 4938%(X100), DQS PI = 48
2462 23:24:08.211955 [0] AVG Duty = 5047%(X100)
2463 23:24:08.214978
2464 23:24:08.218572 CH1 CLK Duty spec in!! Max-Min= 218%
2465 23:24:08.221613 [DutyScan_Calibration_Flow] ====Done====
2466 23:24:08.221692
2467 23:24:08.224872 [DutyScan_Calibration_Flow] k_type=1
2468 23:24:08.241333
2469 23:24:08.241412 ==DQS 0 ==
2470 23:24:08.244512 Final DQS duty delay cell = 0
2471 23:24:08.247762 [0] MAX Duty = 5062%(X100), DQS PI = 18
2472 23:24:08.251166 [0] MIN Duty = 4813%(X100), DQS PI = 50
2473 23:24:08.254575 [0] AVG Duty = 4937%(X100)
2474 23:24:08.254655
2475 23:24:08.254718 ==DQS 1 ==
2476 23:24:08.257604 Final DQS duty delay cell = 0
2477 23:24:08.261087 [0] MAX Duty = 5062%(X100), DQS PI = 36
2478 23:24:08.264340 [0] MIN Duty = 4907%(X100), DQS PI = 8
2479 23:24:08.267972 [0] AVG Duty = 4984%(X100)
2480 23:24:08.268052
2481 23:24:08.271189 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2482 23:24:08.271273
2483 23:24:08.274474 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2484 23:24:08.278079 [DutyScan_Calibration_Flow] ====Done====
2485 23:24:08.278159
2486 23:24:08.281225 [DutyScan_Calibration_Flow] k_type=3
2487 23:24:08.297914
2488 23:24:08.297994 ==DQM 0 ==
2489 23:24:08.301013 Final DQM duty delay cell = 0
2490 23:24:08.304336 [0] MAX Duty = 5093%(X100), DQS PI = 18
2491 23:24:08.307731 [0] MIN Duty = 4844%(X100), DQS PI = 50
2492 23:24:08.307811 [0] AVG Duty = 4968%(X100)
2493 23:24:08.311720
2494 23:24:08.311799 ==DQM 1 ==
2495 23:24:08.314865 Final DQM duty delay cell = 0
2496 23:24:08.317664 [0] MAX Duty = 5156%(X100), DQS PI = 62
2497 23:24:08.321193 [0] MIN Duty = 4938%(X100), DQS PI = 22
2498 23:24:08.324513 [0] AVG Duty = 5047%(X100)
2499 23:24:08.324594
2500 23:24:08.328137 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2501 23:24:08.328218
2502 23:24:08.331284 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2503 23:24:08.334119 [DutyScan_Calibration_Flow] ====Done====
2504 23:24:08.334231
2505 23:24:08.337516 [DutyScan_Calibration_Flow] k_type=2
2506 23:24:08.354138
2507 23:24:08.354244 ==DQ 0 ==
2508 23:24:08.357581 Final DQ duty delay cell = 0
2509 23:24:08.360777 [0] MAX Duty = 5093%(X100), DQS PI = 18
2510 23:24:08.364375 [0] MIN Duty = 4907%(X100), DQS PI = 50
2511 23:24:08.364456 [0] AVG Duty = 5000%(X100)
2512 23:24:08.367850
2513 23:24:08.367930 ==DQ 1 ==
2514 23:24:08.370858 Final DQ duty delay cell = 0
2515 23:24:08.374095 [0] MAX Duty = 5124%(X100), DQS PI = 56
2516 23:24:08.377627 [0] MIN Duty = 5031%(X100), DQS PI = 2
2517 23:24:08.377714 [0] AVG Duty = 5077%(X100)
2518 23:24:08.377785
2519 23:24:08.380807 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2520 23:24:08.380918
2521 23:24:08.384166 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2522 23:24:08.391073 [DutyScan_Calibration_Flow] ====Done====
2523 23:24:08.394140 nWR fixed to 30
2524 23:24:08.394221 [ModeRegInit_LP4] CH0 RK0
2525 23:24:08.397547 [ModeRegInit_LP4] CH0 RK1
2526 23:24:08.400934 [ModeRegInit_LP4] CH1 RK0
2527 23:24:08.401015 [ModeRegInit_LP4] CH1 RK1
2528 23:24:08.404190 match AC timing 7
2529 23:24:08.408250 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2530 23:24:08.411226 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2531 23:24:08.417852 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2532 23:24:08.421356 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2533 23:24:08.424679 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2534 23:24:08.428262 ==
2535 23:24:08.431252 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 23:24:08.434903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2537 23:24:08.434986 ==
2538 23:24:08.438312 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2539 23:24:08.444716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2540 23:24:08.453891 [CA 0] Center 40 (10~71) winsize 62
2541 23:24:08.457180 [CA 1] Center 39 (9~70) winsize 62
2542 23:24:08.460968 [CA 2] Center 36 (6~67) winsize 62
2543 23:24:08.464278 [CA 3] Center 36 (5~67) winsize 63
2544 23:24:08.467702 [CA 4] Center 35 (5~65) winsize 61
2545 23:24:08.470866 [CA 5] Center 34 (4~64) winsize 61
2546 23:24:08.470946
2547 23:24:08.474348 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2548 23:24:08.474475
2549 23:24:08.477830 [CATrainingPosCal] consider 1 rank data
2550 23:24:08.480742 u2DelayCellTimex100 = 270/100 ps
2551 23:24:08.484442 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2552 23:24:08.487409 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2553 23:24:08.494180 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2554 23:24:08.497415 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2555 23:24:08.501318 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2556 23:24:08.504516 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2557 23:24:08.504656
2558 23:24:08.508140 CA PerBit enable=1, Macro0, CA PI delay=34
2559 23:24:08.508246
2560 23:24:08.510744 [CBTSetCACLKResult] CA Dly = 34
2561 23:24:08.510843 CS Dly: 7 (0~38)
2562 23:24:08.510930 ==
2563 23:24:08.514523 Dram Type= 6, Freq= 0, CH_0, rank 1
2564 23:24:08.521003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 23:24:08.521114 ==
2566 23:24:08.524358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2567 23:24:08.531181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2568 23:24:08.540120 [CA 0] Center 39 (9~70) winsize 62
2569 23:24:08.543414 [CA 1] Center 39 (9~70) winsize 62
2570 23:24:08.547234 [CA 2] Center 36 (6~67) winsize 62
2571 23:24:08.549874 [CA 3] Center 36 (5~67) winsize 63
2572 23:24:08.553288 [CA 4] Center 34 (4~65) winsize 62
2573 23:24:08.557306 [CA 5] Center 34 (4~64) winsize 61
2574 23:24:08.557410
2575 23:24:08.560131 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2576 23:24:08.560207
2577 23:24:08.563451 [CATrainingPosCal] consider 2 rank data
2578 23:24:08.566912 u2DelayCellTimex100 = 270/100 ps
2579 23:24:08.570310 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2580 23:24:08.573508 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2581 23:24:08.579983 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2582 23:24:08.583569 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2583 23:24:08.586962 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2584 23:24:08.590227 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2585 23:24:08.590327
2586 23:24:08.593544 CA PerBit enable=1, Macro0, CA PI delay=34
2587 23:24:08.593614
2588 23:24:08.597211 [CBTSetCACLKResult] CA Dly = 34
2589 23:24:08.597291 CS Dly: 8 (0~41)
2590 23:24:08.597354
2591 23:24:08.600590 ----->DramcWriteLeveling(PI) begin...
2592 23:24:08.600672 ==
2593 23:24:08.603810 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 23:24:08.610256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 23:24:08.610363 ==
2596 23:24:08.613693 Write leveling (Byte 0): 30 => 30
2597 23:24:08.616946 Write leveling (Byte 1): 27 => 27
2598 23:24:08.617027 DramcWriteLeveling(PI) end<-----
2599 23:24:08.617091
2600 23:24:08.620424 ==
2601 23:24:08.623975 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 23:24:08.627293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 23:24:08.627374 ==
2604 23:24:08.630293 [Gating] SW mode calibration
2605 23:24:08.637291 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2606 23:24:08.640593 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2607 23:24:08.647367 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 23:24:08.650706 0 15 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2609 23:24:08.654012 0 15 8 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
2610 23:24:08.660478 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 23:24:08.664392 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 23:24:08.667404 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2613 23:24:08.670668 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2614 23:24:08.677773 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2615 23:24:08.680989 1 0 0 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
2616 23:24:08.684310 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
2617 23:24:08.690345 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 23:24:08.693965 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 23:24:08.697497 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 23:24:08.704097 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2621 23:24:08.707496 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2622 23:24:08.710887 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2623 23:24:08.717661 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2624 23:24:08.720957 1 1 4 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
2625 23:24:08.724264 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 23:24:08.731203 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 23:24:08.734131 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 23:24:08.738077 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 23:24:08.741209 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 23:24:08.747502 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 23:24:08.751045 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2632 23:24:08.754660 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2633 23:24:08.760954 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 23:24:08.764540 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 23:24:08.767803 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 23:24:08.774357 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 23:24:08.777654 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 23:24:08.781614 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 23:24:08.787615 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 23:24:08.791221 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 23:24:08.794501 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 23:24:08.800905 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 23:24:08.804473 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 23:24:08.807564 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 23:24:08.814916 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 23:24:08.818096 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 23:24:08.820936 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2648 23:24:08.824513 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2649 23:24:08.827698 Total UI for P1: 0, mck2ui 16
2650 23:24:08.831172 best dqsien dly found for B0: ( 1, 4, 0)
2651 23:24:08.837898 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2652 23:24:08.840962 Total UI for P1: 0, mck2ui 16
2653 23:24:08.844783 best dqsien dly found for B1: ( 1, 4, 4)
2654 23:24:08.848371 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2655 23:24:08.851292 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2656 23:24:08.851373
2657 23:24:08.854669 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2658 23:24:08.858034 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2659 23:24:08.861391 [Gating] SW calibration Done
2660 23:24:08.861471 ==
2661 23:24:08.864709 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 23:24:08.868344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 23:24:08.868424 ==
2664 23:24:08.871317 RX Vref Scan: 0
2665 23:24:08.871397
2666 23:24:08.871460 RX Vref 0 -> 0, step: 1
2667 23:24:08.871554
2668 23:24:08.874901 RX Delay -40 -> 252, step: 8
2669 23:24:08.877986 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2670 23:24:08.884622 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2671 23:24:08.888189 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2672 23:24:08.891570 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2673 23:24:08.894897 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2674 23:24:08.897975 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2675 23:24:08.901813 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2676 23:24:08.908414 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2677 23:24:08.911786 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2678 23:24:08.914849 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2679 23:24:08.918011 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2680 23:24:08.921669 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2681 23:24:08.928645 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2682 23:24:08.931761 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2683 23:24:08.935301 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2684 23:24:08.938809 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2685 23:24:08.938890 ==
2686 23:24:08.941853 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 23:24:08.944884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 23:24:08.948280 ==
2689 23:24:08.948361 DQS Delay:
2690 23:24:08.948424 DQS0 = 0, DQS1 = 0
2691 23:24:08.951808 DQM Delay:
2692 23:24:08.951888 DQM0 = 116, DQM1 = 107
2693 23:24:08.955313 DQ Delay:
2694 23:24:08.958310 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2695 23:24:08.961670 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2696 23:24:08.965508 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2697 23:24:08.968438 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2698 23:24:08.968512
2699 23:24:08.968573
2700 23:24:08.968630 ==
2701 23:24:08.971837 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 23:24:08.975292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 23:24:08.975373 ==
2704 23:24:08.975437
2705 23:24:08.975495
2706 23:24:08.978762 TX Vref Scan disable
2707 23:24:08.982280 == TX Byte 0 ==
2708 23:24:08.985122 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2709 23:24:08.988598 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2710 23:24:08.991794 == TX Byte 1 ==
2711 23:24:08.995370 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2712 23:24:08.998536 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2713 23:24:08.998617 ==
2714 23:24:09.002535 Dram Type= 6, Freq= 0, CH_0, rank 0
2715 23:24:09.005313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2716 23:24:09.008766 ==
2717 23:24:09.018685 TX Vref=22, minBit 1, minWin=24, winSum=419
2718 23:24:09.022146 TX Vref=24, minBit 1, minWin=25, winSum=424
2719 23:24:09.025544 TX Vref=26, minBit 5, minWin=25, winSum=425
2720 23:24:09.029072 TX Vref=28, minBit 1, minWin=25, winSum=433
2721 23:24:09.032559 TX Vref=30, minBit 0, minWin=26, winSum=436
2722 23:24:09.035501 TX Vref=32, minBit 0, minWin=26, winSum=428
2723 23:24:09.042573 [TxChooseVref] Worse bit 0, Min win 26, Win sum 436, Final Vref 30
2724 23:24:09.042661
2725 23:24:09.045724 Final TX Range 1 Vref 30
2726 23:24:09.045806
2727 23:24:09.045869 ==
2728 23:24:09.049167 Dram Type= 6, Freq= 0, CH_0, rank 0
2729 23:24:09.052490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2730 23:24:09.052571 ==
2731 23:24:09.052635
2732 23:24:09.052695
2733 23:24:09.055641 TX Vref Scan disable
2734 23:24:09.059502 == TX Byte 0 ==
2735 23:24:09.062335 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2736 23:24:09.065585 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2737 23:24:09.069054 == TX Byte 1 ==
2738 23:24:09.072345 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2739 23:24:09.075909 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2740 23:24:09.075990
2741 23:24:09.079251 [DATLAT]
2742 23:24:09.079331 Freq=1200, CH0 RK0
2743 23:24:09.079394
2744 23:24:09.082252 DATLAT Default: 0xd
2745 23:24:09.082357 0, 0xFFFF, sum = 0
2746 23:24:09.085594 1, 0xFFFF, sum = 0
2747 23:24:09.085675 2, 0xFFFF, sum = 0
2748 23:24:09.088998 3, 0xFFFF, sum = 0
2749 23:24:09.089099 4, 0xFFFF, sum = 0
2750 23:24:09.092350 5, 0xFFFF, sum = 0
2751 23:24:09.092432 6, 0xFFFF, sum = 0
2752 23:24:09.096272 7, 0xFFFF, sum = 0
2753 23:24:09.096354 8, 0xFFFF, sum = 0
2754 23:24:09.099138 9, 0xFFFF, sum = 0
2755 23:24:09.099219 10, 0xFFFF, sum = 0
2756 23:24:09.102285 11, 0xFFFF, sum = 0
2757 23:24:09.102393 12, 0x0, sum = 1
2758 23:24:09.105620 13, 0x0, sum = 2
2759 23:24:09.105702 14, 0x0, sum = 3
2760 23:24:09.109053 15, 0x0, sum = 4
2761 23:24:09.109135 best_step = 13
2762 23:24:09.109199
2763 23:24:09.109257 ==
2764 23:24:09.112505 Dram Type= 6, Freq= 0, CH_0, rank 0
2765 23:24:09.119327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2766 23:24:09.119432 ==
2767 23:24:09.119497 RX Vref Scan: 1
2768 23:24:09.119613
2769 23:24:09.122641 Set Vref Range= 32 -> 127
2770 23:24:09.122778
2771 23:24:09.125773 RX Vref 32 -> 127, step: 1
2772 23:24:09.125861
2773 23:24:09.129043 RX Delay -21 -> 252, step: 4
2774 23:24:09.129124
2775 23:24:09.132203 Set Vref, RX VrefLevel [Byte0]: 32
2776 23:24:09.132286 [Byte1]: 32
2777 23:24:09.137244
2778 23:24:09.137330 Set Vref, RX VrefLevel [Byte0]: 33
2779 23:24:09.140280 [Byte1]: 33
2780 23:24:09.144790
2781 23:24:09.144891 Set Vref, RX VrefLevel [Byte0]: 34
2782 23:24:09.148242 [Byte1]: 34
2783 23:24:09.152953
2784 23:24:09.153063 Set Vref, RX VrefLevel [Byte0]: 35
2785 23:24:09.156113 [Byte1]: 35
2786 23:24:09.160862
2787 23:24:09.160944 Set Vref, RX VrefLevel [Byte0]: 36
2788 23:24:09.164130 [Byte1]: 36
2789 23:24:09.169053
2790 23:24:09.169141 Set Vref, RX VrefLevel [Byte0]: 37
2791 23:24:09.172400 [Byte1]: 37
2792 23:24:09.176940
2793 23:24:09.177028 Set Vref, RX VrefLevel [Byte0]: 38
2794 23:24:09.180354 [Byte1]: 38
2795 23:24:09.184911
2796 23:24:09.184985 Set Vref, RX VrefLevel [Byte0]: 39
2797 23:24:09.187716 [Byte1]: 39
2798 23:24:09.193043
2799 23:24:09.193138 Set Vref, RX VrefLevel [Byte0]: 40
2800 23:24:09.196183 [Byte1]: 40
2801 23:24:09.200402
2802 23:24:09.200486 Set Vref, RX VrefLevel [Byte0]: 41
2803 23:24:09.204166 [Byte1]: 41
2804 23:24:09.208676
2805 23:24:09.208755 Set Vref, RX VrefLevel [Byte0]: 42
2806 23:24:09.211856 [Byte1]: 42
2807 23:24:09.216867
2808 23:24:09.216947 Set Vref, RX VrefLevel [Byte0]: 43
2809 23:24:09.219502 [Byte1]: 43
2810 23:24:09.224686
2811 23:24:09.224769 Set Vref, RX VrefLevel [Byte0]: 44
2812 23:24:09.227747 [Byte1]: 44
2813 23:24:09.232255
2814 23:24:09.232335 Set Vref, RX VrefLevel [Byte0]: 45
2815 23:24:09.235690 [Byte1]: 45
2816 23:24:09.240087
2817 23:24:09.240167 Set Vref, RX VrefLevel [Byte0]: 46
2818 23:24:09.243488 [Byte1]: 46
2819 23:24:09.247855
2820 23:24:09.251213 Set Vref, RX VrefLevel [Byte0]: 47
2821 23:24:09.251299 [Byte1]: 47
2822 23:24:09.256047
2823 23:24:09.256127 Set Vref, RX VrefLevel [Byte0]: 48
2824 23:24:09.259217 [Byte1]: 48
2825 23:24:09.263715
2826 23:24:09.263795 Set Vref, RX VrefLevel [Byte0]: 49
2827 23:24:09.267323 [Byte1]: 49
2828 23:24:09.271745
2829 23:24:09.271824 Set Vref, RX VrefLevel [Byte0]: 50
2830 23:24:09.275289 [Byte1]: 50
2831 23:24:09.279712
2832 23:24:09.279792 Set Vref, RX VrefLevel [Byte0]: 51
2833 23:24:09.283228 [Byte1]: 51
2834 23:24:09.287484
2835 23:24:09.287576 Set Vref, RX VrefLevel [Byte0]: 52
2836 23:24:09.290704 [Byte1]: 52
2837 23:24:09.295325
2838 23:24:09.295405 Set Vref, RX VrefLevel [Byte0]: 53
2839 23:24:09.299251 [Byte1]: 53
2840 23:24:09.303418
2841 23:24:09.303498 Set Vref, RX VrefLevel [Byte0]: 54
2842 23:24:09.307400 [Byte1]: 54
2843 23:24:09.311379
2844 23:24:09.311459 Set Vref, RX VrefLevel [Byte0]: 55
2845 23:24:09.314787 [Byte1]: 55
2846 23:24:09.319595
2847 23:24:09.319675 Set Vref, RX VrefLevel [Byte0]: 56
2848 23:24:09.323010 [Byte1]: 56
2849 23:24:09.327677
2850 23:24:09.327757 Set Vref, RX VrefLevel [Byte0]: 57
2851 23:24:09.330498 [Byte1]: 57
2852 23:24:09.335020
2853 23:24:09.335100 Set Vref, RX VrefLevel [Byte0]: 58
2854 23:24:09.338921 [Byte1]: 58
2855 23:24:09.343371
2856 23:24:09.343476 Set Vref, RX VrefLevel [Byte0]: 59
2857 23:24:09.346885 [Byte1]: 59
2858 23:24:09.351462
2859 23:24:09.351558 Set Vref, RX VrefLevel [Byte0]: 60
2860 23:24:09.354731 [Byte1]: 60
2861 23:24:09.359157
2862 23:24:09.359241 Set Vref, RX VrefLevel [Byte0]: 61
2863 23:24:09.362550 [Byte1]: 61
2864 23:24:09.366982
2865 23:24:09.367092 Set Vref, RX VrefLevel [Byte0]: 62
2866 23:24:09.370505 [Byte1]: 62
2867 23:24:09.375217
2868 23:24:09.375298 Set Vref, RX VrefLevel [Byte0]: 63
2869 23:24:09.378054 [Byte1]: 63
2870 23:24:09.383033
2871 23:24:09.383114 Set Vref, RX VrefLevel [Byte0]: 64
2872 23:24:09.386170 [Byte1]: 64
2873 23:24:09.390751
2874 23:24:09.390857 Set Vref, RX VrefLevel [Byte0]: 65
2875 23:24:09.393874 [Byte1]: 65
2876 23:24:09.398712
2877 23:24:09.398817 Set Vref, RX VrefLevel [Byte0]: 66
2878 23:24:09.401754 [Byte1]: 66
2879 23:24:09.406964
2880 23:24:09.407051 Set Vref, RX VrefLevel [Byte0]: 67
2881 23:24:09.410138 [Byte1]: 67
2882 23:24:09.414700
2883 23:24:09.414780 Set Vref, RX VrefLevel [Byte0]: 68
2884 23:24:09.418197 [Byte1]: 68
2885 23:24:09.422443
2886 23:24:09.422523 Final RX Vref Byte 0 = 54 to rank0
2887 23:24:09.425842 Final RX Vref Byte 1 = 51 to rank0
2888 23:24:09.429268 Final RX Vref Byte 0 = 54 to rank1
2889 23:24:09.432451 Final RX Vref Byte 1 = 51 to rank1==
2890 23:24:09.435762 Dram Type= 6, Freq= 0, CH_0, rank 0
2891 23:24:09.439300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 23:24:09.442712 ==
2893 23:24:09.442817 DQS Delay:
2894 23:24:09.442887 DQS0 = 0, DQS1 = 0
2895 23:24:09.446082 DQM Delay:
2896 23:24:09.446162 DQM0 = 114, DQM1 = 104
2897 23:24:09.449621 DQ Delay:
2898 23:24:09.452563 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2899 23:24:09.456405 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2900 23:24:09.459234 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2901 23:24:09.462882 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2902 23:24:09.462964
2903 23:24:09.463037
2904 23:24:09.469877 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbea, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
2905 23:24:09.473099 CH0 RK0: MR19=303, MR18=FBEA
2906 23:24:09.479501 CH0_RK0: MR19=0x303, MR18=0xFBEA, DQSOSC=412, MR23=63, INC=38, DEC=25
2907 23:24:09.479581
2908 23:24:09.483187 ----->DramcWriteLeveling(PI) begin...
2909 23:24:09.483281 ==
2910 23:24:09.486535 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 23:24:09.489406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 23:24:09.489481 ==
2913 23:24:09.492702 Write leveling (Byte 0): 33 => 33
2914 23:24:09.496089 Write leveling (Byte 1): 28 => 28
2915 23:24:09.499987 DramcWriteLeveling(PI) end<-----
2916 23:24:09.500094
2917 23:24:09.500164 ==
2918 23:24:09.502705 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 23:24:09.506224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 23:24:09.506334 ==
2921 23:24:09.510056 [Gating] SW mode calibration
2922 23:24:09.517016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2923 23:24:09.522831 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2924 23:24:09.526213 0 15 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
2925 23:24:09.533225 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2926 23:24:09.536182 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 23:24:09.539510 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 23:24:09.546371 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 23:24:09.549732 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 23:24:09.552775 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 23:24:09.556195 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
2932 23:24:09.562941 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2933 23:24:09.566260 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2934 23:24:09.569543 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 23:24:09.576431 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 23:24:09.579694 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 23:24:09.583048 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 23:24:09.590041 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2939 23:24:09.593184 1 0 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (1 1)
2940 23:24:09.596687 1 1 0 | B1->B0 | 3434 4343 | 1 0 | (0 0) (0 0)
2941 23:24:09.603730 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 23:24:09.606478 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 23:24:09.610063 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 23:24:09.616450 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 23:24:09.620030 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 23:24:09.623529 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2947 23:24:09.626491 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2948 23:24:09.633232 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2949 23:24:09.636769 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2950 23:24:09.640224 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 23:24:09.647069 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 23:24:09.650516 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 23:24:09.653365 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 23:24:09.660077 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 23:24:09.663480 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 23:24:09.666505 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 23:24:09.673120 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 23:24:09.676533 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 23:24:09.680197 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 23:24:09.686583 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 23:24:09.690144 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 23:24:09.693393 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 23:24:09.700129 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2964 23:24:09.703661 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2965 23:24:09.706805 Total UI for P1: 0, mck2ui 16
2966 23:24:09.710184 best dqsien dly found for B0: ( 1, 3, 28)
2967 23:24:09.713384 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 23:24:09.716967 Total UI for P1: 0, mck2ui 16
2969 23:24:09.720188 best dqsien dly found for B1: ( 1, 4, 0)
2970 23:24:09.723760 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2971 23:24:09.726784 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2972 23:24:09.726864
2973 23:24:09.730226 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2974 23:24:09.733476 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2975 23:24:09.737041 [Gating] SW calibration Done
2976 23:24:09.737122 ==
2977 23:24:09.740653 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 23:24:09.744020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 23:24:09.746892 ==
2980 23:24:09.746972 RX Vref Scan: 0
2981 23:24:09.747037
2982 23:24:09.750498 RX Vref 0 -> 0, step: 1
2983 23:24:09.750578
2984 23:24:09.750641 RX Delay -40 -> 252, step: 8
2985 23:24:09.757656 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2986 23:24:09.760436 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2987 23:24:09.763976 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2988 23:24:09.767586 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2989 23:24:09.770761 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2990 23:24:09.777223 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2991 23:24:09.780499 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2992 23:24:09.784213 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2993 23:24:09.787404 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2994 23:24:09.790519 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2995 23:24:09.794116 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2996 23:24:09.800617 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2997 23:24:09.803821 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2998 23:24:09.807304 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2999 23:24:09.810632 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3000 23:24:09.814521 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3001 23:24:09.817348 ==
3002 23:24:09.821092 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 23:24:09.824191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 23:24:09.824303 ==
3005 23:24:09.824394 DQS Delay:
3006 23:24:09.827707 DQS0 = 0, DQS1 = 0
3007 23:24:09.827786 DQM Delay:
3008 23:24:09.831199 DQM0 = 115, DQM1 = 105
3009 23:24:09.831279 DQ Delay:
3010 23:24:09.834378 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3011 23:24:09.837683 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
3012 23:24:09.841086 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3013 23:24:09.844489 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
3014 23:24:09.844595
3015 23:24:09.844717
3016 23:24:09.844804 ==
3017 23:24:09.847902 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 23:24:09.854536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 23:24:09.854619 ==
3020 23:24:09.854683
3021 23:24:09.854751
3022 23:24:09.854812 TX Vref Scan disable
3023 23:24:09.858003 == TX Byte 0 ==
3024 23:24:09.861412 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3025 23:24:09.864586 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3026 23:24:09.867881 == TX Byte 1 ==
3027 23:24:09.870926 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3028 23:24:09.874331 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3029 23:24:09.877769 ==
3030 23:24:09.877880 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 23:24:09.884706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 23:24:09.884783 ==
3033 23:24:09.895703 TX Vref=22, minBit 1, minWin=25, winSum=417
3034 23:24:09.899173 TX Vref=24, minBit 1, minWin=25, winSum=428
3035 23:24:09.902376 TX Vref=26, minBit 2, minWin=26, winSum=434
3036 23:24:09.906374 TX Vref=28, minBit 3, minWin=26, winSum=435
3037 23:24:09.909323 TX Vref=30, minBit 2, minWin=26, winSum=436
3038 23:24:09.912902 TX Vref=32, minBit 0, minWin=27, winSum=436
3039 23:24:09.919276 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 32
3040 23:24:09.919359
3041 23:24:09.922752 Final TX Range 1 Vref 32
3042 23:24:09.922833
3043 23:24:09.922896 ==
3044 23:24:09.926289 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 23:24:09.929752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 23:24:09.929833 ==
3047 23:24:09.929895
3048 23:24:09.929953
3049 23:24:09.933221 TX Vref Scan disable
3050 23:24:09.936145 == TX Byte 0 ==
3051 23:24:09.939547 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3052 23:24:09.942639 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3053 23:24:09.945995 == TX Byte 1 ==
3054 23:24:09.949724 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3055 23:24:09.952649 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3056 23:24:09.952730
3057 23:24:09.956651 [DATLAT]
3058 23:24:09.956731 Freq=1200, CH0 RK1
3059 23:24:09.956795
3060 23:24:09.959430 DATLAT Default: 0xd
3061 23:24:09.959518 0, 0xFFFF, sum = 0
3062 23:24:09.963186 1, 0xFFFF, sum = 0
3063 23:24:09.963267 2, 0xFFFF, sum = 0
3064 23:24:09.966199 3, 0xFFFF, sum = 0
3065 23:24:09.966281 4, 0xFFFF, sum = 0
3066 23:24:09.969830 5, 0xFFFF, sum = 0
3067 23:24:09.969911 6, 0xFFFF, sum = 0
3068 23:24:09.972825 7, 0xFFFF, sum = 0
3069 23:24:09.972906 8, 0xFFFF, sum = 0
3070 23:24:09.976250 9, 0xFFFF, sum = 0
3071 23:24:09.976331 10, 0xFFFF, sum = 0
3072 23:24:09.979600 11, 0xFFFF, sum = 0
3073 23:24:09.979682 12, 0x0, sum = 1
3074 23:24:09.983215 13, 0x0, sum = 2
3075 23:24:09.983297 14, 0x0, sum = 3
3076 23:24:09.986925 15, 0x0, sum = 4
3077 23:24:09.987006 best_step = 13
3078 23:24:09.987069
3079 23:24:09.987127 ==
3080 23:24:09.989595 Dram Type= 6, Freq= 0, CH_0, rank 1
3081 23:24:09.996508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 23:24:09.996589 ==
3083 23:24:09.996651 RX Vref Scan: 0
3084 23:24:09.996710
3085 23:24:09.999934 RX Vref 0 -> 0, step: 1
3086 23:24:10.000050
3087 23:24:10.003655 RX Delay -21 -> 252, step: 4
3088 23:24:10.006804 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3089 23:24:10.009960 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3090 23:24:10.013408 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3091 23:24:10.020060 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3092 23:24:10.023134 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3093 23:24:10.026699 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3094 23:24:10.029955 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3095 23:24:10.033213 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3096 23:24:10.039903 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3097 23:24:10.043289 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3098 23:24:10.046869 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3099 23:24:10.050160 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3100 23:24:10.053686 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3101 23:24:10.059938 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3102 23:24:10.063339 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3103 23:24:10.067036 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3104 23:24:10.067131 ==
3105 23:24:10.070098 Dram Type= 6, Freq= 0, CH_0, rank 1
3106 23:24:10.073709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 23:24:10.073791 ==
3108 23:24:10.076643 DQS Delay:
3109 23:24:10.076754 DQS0 = 0, DQS1 = 0
3110 23:24:10.076819 DQM Delay:
3111 23:24:10.080258 DQM0 = 113, DQM1 = 104
3112 23:24:10.080338 DQ Delay:
3113 23:24:10.084018 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3114 23:24:10.087316 DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =122
3115 23:24:10.090671 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3116 23:24:10.097482 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3117 23:24:10.097562
3118 23:24:10.097625
3119 23:24:10.103580 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3120 23:24:10.107076 CH0 RK1: MR19=403, MR18=4F6
3121 23:24:10.113664 CH0_RK1: MR19=0x403, MR18=0x4F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3122 23:24:10.113785 [RxdqsGatingPostProcess] freq 1200
3123 23:24:10.120272 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3124 23:24:10.123817 best DQS0 dly(2T, 0.5T) = (0, 12)
3125 23:24:10.127297 best DQS1 dly(2T, 0.5T) = (0, 12)
3126 23:24:10.130525 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3127 23:24:10.133916 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3128 23:24:10.137227 best DQS0 dly(2T, 0.5T) = (0, 11)
3129 23:24:10.140903 best DQS1 dly(2T, 0.5T) = (0, 12)
3130 23:24:10.144042 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3131 23:24:10.147418 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3132 23:24:10.150471 Pre-setting of DQS Precalculation
3133 23:24:10.153846 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3134 23:24:10.153926 ==
3135 23:24:10.157366 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 23:24:10.160765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 23:24:10.160845 ==
3138 23:24:10.167097 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3139 23:24:10.173948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3140 23:24:10.181273 [CA 0] Center 38 (8~68) winsize 61
3141 23:24:10.185391 [CA 1] Center 38 (8~68) winsize 61
3142 23:24:10.188454 [CA 2] Center 35 (5~65) winsize 61
3143 23:24:10.192261 [CA 3] Center 34 (4~65) winsize 62
3144 23:24:10.195191 [CA 4] Center 35 (5~65) winsize 61
3145 23:24:10.198294 [CA 5] Center 33 (4~63) winsize 60
3146 23:24:10.198373
3147 23:24:10.201523 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3148 23:24:10.201603
3149 23:24:10.204929 [CATrainingPosCal] consider 1 rank data
3150 23:24:10.208484 u2DelayCellTimex100 = 270/100 ps
3151 23:24:10.211951 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3152 23:24:10.215392 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3153 23:24:10.218572 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3154 23:24:10.224979 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3155 23:24:10.228275 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3156 23:24:10.231673 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3157 23:24:10.231768
3158 23:24:10.235285 CA PerBit enable=1, Macro0, CA PI delay=33
3159 23:24:10.235365
3160 23:24:10.238692 [CBTSetCACLKResult] CA Dly = 33
3161 23:24:10.238772 CS Dly: 6 (0~37)
3162 23:24:10.238835 ==
3163 23:24:10.241604 Dram Type= 6, Freq= 0, CH_1, rank 1
3164 23:24:10.248920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 23:24:10.249021 ==
3166 23:24:10.251708 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3167 23:24:10.258474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3168 23:24:10.267000 [CA 0] Center 38 (8~68) winsize 61
3169 23:24:10.270380 [CA 1] Center 38 (8~68) winsize 61
3170 23:24:10.273355 [CA 2] Center 34 (4~65) winsize 62
3171 23:24:10.276676 [CA 3] Center 34 (4~65) winsize 62
3172 23:24:10.280422 [CA 4] Center 34 (4~65) winsize 62
3173 23:24:10.283554 [CA 5] Center 33 (3~63) winsize 61
3174 23:24:10.283635
3175 23:24:10.286740 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3176 23:24:10.286820
3177 23:24:10.290147 [CATrainingPosCal] consider 2 rank data
3178 23:24:10.293684 u2DelayCellTimex100 = 270/100 ps
3179 23:24:10.296937 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3180 23:24:10.300332 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3181 23:24:10.306979 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3182 23:24:10.310279 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3183 23:24:10.313585 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3184 23:24:10.316703 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3185 23:24:10.316809
3186 23:24:10.320598 CA PerBit enable=1, Macro0, CA PI delay=33
3187 23:24:10.320672
3188 23:24:10.323935 [CBTSetCACLKResult] CA Dly = 33
3189 23:24:10.324007 CS Dly: 7 (0~40)
3190 23:24:10.324067
3191 23:24:10.327149 ----->DramcWriteLeveling(PI) begin...
3192 23:24:10.330664 ==
3193 23:24:10.330744 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 23:24:10.337063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 23:24:10.337148 ==
3196 23:24:10.340291 Write leveling (Byte 0): 26 => 26
3197 23:24:10.343603 Write leveling (Byte 1): 27 => 27
3198 23:24:10.343690 DramcWriteLeveling(PI) end<-----
3199 23:24:10.346857
3200 23:24:10.346943 ==
3201 23:24:10.350475 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 23:24:10.353886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 23:24:10.353963 ==
3204 23:24:10.357270 [Gating] SW mode calibration
3205 23:24:10.363763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3206 23:24:10.367254 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3207 23:24:10.374047 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3208 23:24:10.376894 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 23:24:10.380685 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 23:24:10.387161 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 23:24:10.390863 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 23:24:10.393839 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 23:24:10.400671 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 23:24:10.403998 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3215 23:24:10.407427 1 0 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 1)
3216 23:24:10.414060 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 23:24:10.417378 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 23:24:10.420702 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 23:24:10.424073 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 23:24:10.430791 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 23:24:10.434260 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 23:24:10.437679 1 0 28 | B1->B0 | 3131 2b2b | 1 0 | (0 0) (1 1)
3223 23:24:10.444131 1 1 0 | B1->B0 | 4545 3434 | 0 1 | (0 0) (1 1)
3224 23:24:10.447533 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 23:24:10.451219 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 23:24:10.457655 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 23:24:10.460880 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 23:24:10.464398 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 23:24:10.471187 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 23:24:10.474242 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3231 23:24:10.477893 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3232 23:24:10.484262 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 23:24:10.487894 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 23:24:10.490936 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 23:24:10.494631 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 23:24:10.501067 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 23:24:10.504439 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 23:24:10.507762 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 23:24:10.514336 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 23:24:10.517972 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 23:24:10.521075 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 23:24:10.527680 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 23:24:10.531080 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 23:24:10.534791 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 23:24:10.541554 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 23:24:10.544567 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3247 23:24:10.547860 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3248 23:24:10.551302 Total UI for P1: 0, mck2ui 16
3249 23:24:10.554508 best dqsien dly found for B0: ( 1, 3, 28)
3250 23:24:10.557848 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3251 23:24:10.561451 Total UI for P1: 0, mck2ui 16
3252 23:24:10.564814 best dqsien dly found for B1: ( 1, 4, 0)
3253 23:24:10.567812 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3254 23:24:10.571081 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3255 23:24:10.574527
3256 23:24:10.577970 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3257 23:24:10.581140 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3258 23:24:10.584305 [Gating] SW calibration Done
3259 23:24:10.584382 ==
3260 23:24:10.587715 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 23:24:10.591270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 23:24:10.591344 ==
3263 23:24:10.591409 RX Vref Scan: 0
3264 23:24:10.591467
3265 23:24:10.594677 RX Vref 0 -> 0, step: 1
3266 23:24:10.594748
3267 23:24:10.598046 RX Delay -40 -> 252, step: 8
3268 23:24:10.601317 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3269 23:24:10.604453 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3270 23:24:10.611284 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3271 23:24:10.614714 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3272 23:24:10.618108 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3273 23:24:10.621684 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3274 23:24:10.625372 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3275 23:24:10.628338 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3276 23:24:10.635146 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3277 23:24:10.638476 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3278 23:24:10.641839 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3279 23:24:10.645599 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3280 23:24:10.648856 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3281 23:24:10.655247 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3282 23:24:10.658353 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3283 23:24:10.661928 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3284 23:24:10.662012 ==
3285 23:24:10.664786 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 23:24:10.668567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 23:24:10.668675 ==
3288 23:24:10.672062 DQS Delay:
3289 23:24:10.672137 DQS0 = 0, DQS1 = 0
3290 23:24:10.674971 DQM Delay:
3291 23:24:10.675044 DQM0 = 116, DQM1 = 109
3292 23:24:10.675104 DQ Delay:
3293 23:24:10.678511 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3294 23:24:10.681823 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3295 23:24:10.688323 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3296 23:24:10.691707 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3297 23:24:10.691788
3298 23:24:10.691854
3299 23:24:10.691912 ==
3300 23:24:10.695047 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 23:24:10.698551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3302 23:24:10.698627 ==
3303 23:24:10.698688
3304 23:24:10.698752
3305 23:24:10.701932 TX Vref Scan disable
3306 23:24:10.702007 == TX Byte 0 ==
3307 23:24:10.708575 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3308 23:24:10.711689 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3309 23:24:10.711767 == TX Byte 1 ==
3310 23:24:10.718391 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3311 23:24:10.722200 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3312 23:24:10.722295 ==
3313 23:24:10.725238 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 23:24:10.728432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 23:24:10.728510 ==
3316 23:24:10.741090 TX Vref=22, minBit 3, minWin=24, winSum=407
3317 23:24:10.744667 TX Vref=24, minBit 9, minWin=25, winSum=416
3318 23:24:10.748274 TX Vref=26, minBit 0, minWin=26, winSum=421
3319 23:24:10.751124 TX Vref=28, minBit 0, minWin=26, winSum=426
3320 23:24:10.754880 TX Vref=30, minBit 1, minWin=26, winSum=426
3321 23:24:10.758040 TX Vref=32, minBit 11, minWin=25, winSum=427
3322 23:24:10.764856 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
3323 23:24:10.764931
3324 23:24:10.768193 Final TX Range 1 Vref 28
3325 23:24:10.768270
3326 23:24:10.768341 ==
3327 23:24:10.771804 Dram Type= 6, Freq= 0, CH_1, rank 0
3328 23:24:10.774672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3329 23:24:10.774746 ==
3330 23:24:10.774837
3331 23:24:10.774910
3332 23:24:10.778035 TX Vref Scan disable
3333 23:24:10.781511 == TX Byte 0 ==
3334 23:24:10.784753 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3335 23:24:10.788370 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3336 23:24:10.791713 == TX Byte 1 ==
3337 23:24:10.795563 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3338 23:24:10.798286 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3339 23:24:10.798384
3340 23:24:10.801731 [DATLAT]
3341 23:24:10.801807 Freq=1200, CH1 RK0
3342 23:24:10.801872
3343 23:24:10.805129 DATLAT Default: 0xd
3344 23:24:10.805198 0, 0xFFFF, sum = 0
3345 23:24:10.808686 1, 0xFFFF, sum = 0
3346 23:24:10.808761 2, 0xFFFF, sum = 0
3347 23:24:10.811819 3, 0xFFFF, sum = 0
3348 23:24:10.811919 4, 0xFFFF, sum = 0
3349 23:24:10.815216 5, 0xFFFF, sum = 0
3350 23:24:10.815367 6, 0xFFFF, sum = 0
3351 23:24:10.818519 7, 0xFFFF, sum = 0
3352 23:24:10.818617 8, 0xFFFF, sum = 0
3353 23:24:10.822112 9, 0xFFFF, sum = 0
3354 23:24:10.822182 10, 0xFFFF, sum = 0
3355 23:24:10.825464 11, 0xFFFF, sum = 0
3356 23:24:10.825535 12, 0x0, sum = 1
3357 23:24:10.828555 13, 0x0, sum = 2
3358 23:24:10.828633 14, 0x0, sum = 3
3359 23:24:10.832076 15, 0x0, sum = 4
3360 23:24:10.832149 best_step = 13
3361 23:24:10.832216
3362 23:24:10.832277 ==
3363 23:24:10.835239 Dram Type= 6, Freq= 0, CH_1, rank 0
3364 23:24:10.838788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3365 23:24:10.841960 ==
3366 23:24:10.842067 RX Vref Scan: 1
3367 23:24:10.842155
3368 23:24:10.845209 Set Vref Range= 32 -> 127
3369 23:24:10.845284
3370 23:24:10.845348 RX Vref 32 -> 127, step: 1
3371 23:24:10.848698
3372 23:24:10.848772 RX Delay -21 -> 252, step: 4
3373 23:24:10.848832
3374 23:24:10.851792 Set Vref, RX VrefLevel [Byte0]: 32
3375 23:24:10.855558 [Byte1]: 32
3376 23:24:10.859393
3377 23:24:10.859470 Set Vref, RX VrefLevel [Byte0]: 33
3378 23:24:10.862736 [Byte1]: 33
3379 23:24:10.867235
3380 23:24:10.867313 Set Vref, RX VrefLevel [Byte0]: 34
3381 23:24:10.870711 [Byte1]: 34
3382 23:24:10.875145
3383 23:24:10.875219 Set Vref, RX VrefLevel [Byte0]: 35
3384 23:24:10.878747 [Byte1]: 35
3385 23:24:10.883122
3386 23:24:10.883210 Set Vref, RX VrefLevel [Byte0]: 36
3387 23:24:10.886523 [Byte1]: 36
3388 23:24:10.891444
3389 23:24:10.891523 Set Vref, RX VrefLevel [Byte0]: 37
3390 23:24:10.894712 [Byte1]: 37
3391 23:24:10.899222
3392 23:24:10.899297 Set Vref, RX VrefLevel [Byte0]: 38
3393 23:24:10.902937 [Byte1]: 38
3394 23:24:10.907022
3395 23:24:10.907095 Set Vref, RX VrefLevel [Byte0]: 39
3396 23:24:10.910271 [Byte1]: 39
3397 23:24:10.914592
3398 23:24:10.914669 Set Vref, RX VrefLevel [Byte0]: 40
3399 23:24:10.918581 [Byte1]: 40
3400 23:24:10.922652
3401 23:24:10.922731 Set Vref, RX VrefLevel [Byte0]: 41
3402 23:24:10.926125 [Byte1]: 41
3403 23:24:10.930586
3404 23:24:10.930666 Set Vref, RX VrefLevel [Byte0]: 42
3405 23:24:10.933753 [Byte1]: 42
3406 23:24:10.939045
3407 23:24:10.939124 Set Vref, RX VrefLevel [Byte0]: 43
3408 23:24:10.942362 [Byte1]: 43
3409 23:24:10.946713
3410 23:24:10.946821 Set Vref, RX VrefLevel [Byte0]: 44
3411 23:24:10.949678 [Byte1]: 44
3412 23:24:10.954516
3413 23:24:10.954626 Set Vref, RX VrefLevel [Byte0]: 45
3414 23:24:10.957541 [Byte1]: 45
3415 23:24:10.962235
3416 23:24:10.962340 Set Vref, RX VrefLevel [Byte0]: 46
3417 23:24:10.965538 [Byte1]: 46
3418 23:24:10.970791
3419 23:24:10.970885 Set Vref, RX VrefLevel [Byte0]: 47
3420 23:24:10.973774 [Byte1]: 47
3421 23:24:10.978303
3422 23:24:10.978419 Set Vref, RX VrefLevel [Byte0]: 48
3423 23:24:10.981452 [Byte1]: 48
3424 23:24:10.986232
3425 23:24:10.986334 Set Vref, RX VrefLevel [Byte0]: 49
3426 23:24:10.989762 [Byte1]: 49
3427 23:24:10.993964
3428 23:24:10.994037 Set Vref, RX VrefLevel [Byte0]: 50
3429 23:24:10.997195 [Byte1]: 50
3430 23:24:11.002204
3431 23:24:11.002284 Set Vref, RX VrefLevel [Byte0]: 51
3432 23:24:11.005319 [Byte1]: 51
3433 23:24:11.010193
3434 23:24:11.010266 Set Vref, RX VrefLevel [Byte0]: 52
3435 23:24:11.013449 [Byte1]: 52
3436 23:24:11.018130
3437 23:24:11.018206 Set Vref, RX VrefLevel [Byte0]: 53
3438 23:24:11.021156 [Byte1]: 53
3439 23:24:11.025957
3440 23:24:11.026040 Set Vref, RX VrefLevel [Byte0]: 54
3441 23:24:11.028872 [Byte1]: 54
3442 23:24:11.033446
3443 23:24:11.033531 Set Vref, RX VrefLevel [Byte0]: 55
3444 23:24:11.036954 [Byte1]: 55
3445 23:24:11.041870
3446 23:24:11.041950 Set Vref, RX VrefLevel [Byte0]: 56
3447 23:24:11.044871 [Byte1]: 56
3448 23:24:11.049489
3449 23:24:11.049568 Set Vref, RX VrefLevel [Byte0]: 57
3450 23:24:11.052890 [Byte1]: 57
3451 23:24:11.057579
3452 23:24:11.057658 Set Vref, RX VrefLevel [Byte0]: 58
3453 23:24:11.060790 [Byte1]: 58
3454 23:24:11.065703
3455 23:24:11.065786 Set Vref, RX VrefLevel [Byte0]: 59
3456 23:24:11.071900 [Byte1]: 59
3457 23:24:11.071979
3458 23:24:11.075276 Set Vref, RX VrefLevel [Byte0]: 60
3459 23:24:11.078571 [Byte1]: 60
3460 23:24:11.078651
3461 23:24:11.082199 Set Vref, RX VrefLevel [Byte0]: 61
3462 23:24:11.085545 [Byte1]: 61
3463 23:24:11.089392
3464 23:24:11.089500 Set Vref, RX VrefLevel [Byte0]: 62
3465 23:24:11.092939 [Byte1]: 62
3466 23:24:11.096879
3467 23:24:11.096957 Set Vref, RX VrefLevel [Byte0]: 63
3468 23:24:11.100182 [Byte1]: 63
3469 23:24:11.105037
3470 23:24:11.105142 Set Vref, RX VrefLevel [Byte0]: 64
3471 23:24:11.108114 [Byte1]: 64
3472 23:24:11.112981
3473 23:24:11.113060 Set Vref, RX VrefLevel [Byte0]: 65
3474 23:24:11.116713 [Byte1]: 65
3475 23:24:11.120759
3476 23:24:11.120847 Set Vref, RX VrefLevel [Byte0]: 66
3477 23:24:11.123921 [Byte1]: 66
3478 23:24:11.129003
3479 23:24:11.129110 Set Vref, RX VrefLevel [Byte0]: 67
3480 23:24:11.132554 [Byte1]: 67
3481 23:24:11.136698
3482 23:24:11.136778 Set Vref, RX VrefLevel [Byte0]: 68
3483 23:24:11.139930 [Byte1]: 68
3484 23:24:11.144655
3485 23:24:11.144735 Set Vref, RX VrefLevel [Byte0]: 69
3486 23:24:11.147782 [Byte1]: 69
3487 23:24:11.152821
3488 23:24:11.152905 Set Vref, RX VrefLevel [Byte0]: 70
3489 23:24:11.156487 [Byte1]: 70
3490 23:24:11.160626
3491 23:24:11.160746 Set Vref, RX VrefLevel [Byte0]: 71
3492 23:24:11.164158 [Byte1]: 71
3493 23:24:11.168109
3494 23:24:11.168187 Set Vref, RX VrefLevel [Byte0]: 72
3495 23:24:11.171626 [Byte1]: 72
3496 23:24:11.176397
3497 23:24:11.176477 Final RX Vref Byte 0 = 56 to rank0
3498 23:24:11.179832 Final RX Vref Byte 1 = 54 to rank0
3499 23:24:11.182731 Final RX Vref Byte 0 = 56 to rank1
3500 23:24:11.186848 Final RX Vref Byte 1 = 54 to rank1==
3501 23:24:11.189400 Dram Type= 6, Freq= 0, CH_1, rank 0
3502 23:24:11.196328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 23:24:11.196410 ==
3504 23:24:11.196473 DQS Delay:
3505 23:24:11.196533 DQS0 = 0, DQS1 = 0
3506 23:24:11.199922 DQM Delay:
3507 23:24:11.200008 DQM0 = 115, DQM1 = 109
3508 23:24:11.202760 DQ Delay:
3509 23:24:11.206380 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3510 23:24:11.209643 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =112
3511 23:24:11.213088 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =106
3512 23:24:11.216621 DQ12 =118, DQ13 =114, DQ14 =116, DQ15 =114
3513 23:24:11.216701
3514 23:24:11.216764
3515 23:24:11.223002 [DQSOSCAuto] RK0, (LSB)MR18= 0xfde2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3516 23:24:11.226366 CH1 RK0: MR19=303, MR18=FDE2
3517 23:24:11.233341 CH1_RK0: MR19=0x303, MR18=0xFDE2, DQSOSC=411, MR23=63, INC=38, DEC=25
3518 23:24:11.233422
3519 23:24:11.237120 ----->DramcWriteLeveling(PI) begin...
3520 23:24:11.237200 ==
3521 23:24:11.239798 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 23:24:11.243452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 23:24:11.243532 ==
3524 23:24:11.246558 Write leveling (Byte 0): 26 => 26
3525 23:24:11.250160 Write leveling (Byte 1): 28 => 28
3526 23:24:11.253117 DramcWriteLeveling(PI) end<-----
3527 23:24:11.253266
3528 23:24:11.253365 ==
3529 23:24:11.256737 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 23:24:11.260143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 23:24:11.263219 ==
3532 23:24:11.263300 [Gating] SW mode calibration
3533 23:24:11.273330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3534 23:24:11.276767 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3535 23:24:11.280002 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3536 23:24:11.286783 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3537 23:24:11.290087 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3538 23:24:11.293487 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3539 23:24:11.300393 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3540 23:24:11.303117 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3541 23:24:11.306765 0 15 24 | B1->B0 | 3333 2929 | 1 1 | (1 1) (1 0)
3542 23:24:11.313194 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3543 23:24:11.316636 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3544 23:24:11.320168 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3545 23:24:11.326540 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3546 23:24:11.329988 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3547 23:24:11.333474 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 23:24:11.336468 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 23:24:11.343189 1 0 24 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
3550 23:24:11.346882 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3551 23:24:11.350101 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 23:24:11.356900 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 23:24:11.360187 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 23:24:11.363644 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 23:24:11.369768 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 23:24:11.373349 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3557 23:24:11.376537 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3558 23:24:11.382981 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3559 23:24:11.386267 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 23:24:11.389971 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 23:24:11.397014 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 23:24:11.400326 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 23:24:11.403556 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 23:24:11.409755 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 23:24:11.413162 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 23:24:11.416850 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 23:24:11.423283 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 23:24:11.426701 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 23:24:11.430311 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 23:24:11.433101 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 23:24:11.439938 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 23:24:11.443084 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3573 23:24:11.446674 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3574 23:24:11.453631 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3575 23:24:11.456483 Total UI for P1: 0, mck2ui 16
3576 23:24:11.459792 best dqsien dly found for B0: ( 1, 3, 22)
3577 23:24:11.463367 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3578 23:24:11.466363 Total UI for P1: 0, mck2ui 16
3579 23:24:11.469781 best dqsien dly found for B1: ( 1, 3, 28)
3580 23:24:11.473170 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3581 23:24:11.476423 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3582 23:24:11.476496
3583 23:24:11.479658 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3584 23:24:11.483527 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3585 23:24:11.486417 [Gating] SW calibration Done
3586 23:24:11.486507 ==
3587 23:24:11.489741 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 23:24:11.493287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 23:24:11.496624 ==
3590 23:24:11.496704 RX Vref Scan: 0
3591 23:24:11.496766
3592 23:24:11.499722 RX Vref 0 -> 0, step: 1
3593 23:24:11.499801
3594 23:24:11.503282 RX Delay -40 -> 252, step: 8
3595 23:24:11.506656 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3596 23:24:11.510266 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3597 23:24:11.512933 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3598 23:24:11.516545 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3599 23:24:11.523232 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3600 23:24:11.526469 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3601 23:24:11.529721 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3602 23:24:11.533178 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3603 23:24:11.536710 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3604 23:24:11.539917 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3605 23:24:11.546725 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3606 23:24:11.549658 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3607 23:24:11.553126 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3608 23:24:11.556612 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3609 23:24:11.563274 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3610 23:24:11.566302 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3611 23:24:11.566437 ==
3612 23:24:11.569868 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 23:24:11.573561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 23:24:11.573668 ==
3615 23:24:11.573762 DQS Delay:
3616 23:24:11.577133 DQS0 = 0, DQS1 = 0
3617 23:24:11.577235 DQM Delay:
3618 23:24:11.579786 DQM0 = 114, DQM1 = 111
3619 23:24:11.579856 DQ Delay:
3620 23:24:11.583328 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3621 23:24:11.587188 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =107
3622 23:24:11.589774 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3623 23:24:11.593303 DQ12 =119, DQ13 =123, DQ14 =119, DQ15 =119
3624 23:24:11.593401
3625 23:24:11.596783
3626 23:24:11.596859 ==
3627 23:24:11.600148 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 23:24:11.603313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 23:24:11.603418 ==
3630 23:24:11.603481
3631 23:24:11.603601
3632 23:24:11.606521 TX Vref Scan disable
3633 23:24:11.606592 == TX Byte 0 ==
3634 23:24:11.613130 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3635 23:24:11.616721 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3636 23:24:11.616797 == TX Byte 1 ==
3637 23:24:11.623326 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3638 23:24:11.626718 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3639 23:24:11.626797 ==
3640 23:24:11.629624 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 23:24:11.633056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 23:24:11.633133 ==
3643 23:24:11.644991 TX Vref=22, minBit 1, minWin=25, winSum=416
3644 23:24:11.648398 TX Vref=24, minBit 1, minWin=25, winSum=420
3645 23:24:11.651957 TX Vref=26, minBit 1, minWin=25, winSum=424
3646 23:24:11.655233 TX Vref=28, minBit 0, minWin=26, winSum=432
3647 23:24:11.658284 TX Vref=30, minBit 4, minWin=26, winSum=434
3648 23:24:11.665087 TX Vref=32, minBit 0, minWin=26, winSum=436
3649 23:24:11.668421 [TxChooseVref] Worse bit 0, Min win 26, Win sum 436, Final Vref 32
3650 23:24:11.668496
3651 23:24:11.672254 Final TX Range 1 Vref 32
3652 23:24:11.672331
3653 23:24:11.672403 ==
3654 23:24:11.675003 Dram Type= 6, Freq= 0, CH_1, rank 1
3655 23:24:11.678455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3656 23:24:11.678552 ==
3657 23:24:11.681701
3658 23:24:11.681774
3659 23:24:11.681844 TX Vref Scan disable
3660 23:24:11.685016 == TX Byte 0 ==
3661 23:24:11.688243 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3662 23:24:11.691657 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3663 23:24:11.695146 == TX Byte 1 ==
3664 23:24:11.698546 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3665 23:24:11.702278 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3666 23:24:11.702379
3667 23:24:11.705158 [DATLAT]
3668 23:24:11.705262 Freq=1200, CH1 RK1
3669 23:24:11.705350
3670 23:24:11.708428 DATLAT Default: 0xd
3671 23:24:11.708498 0, 0xFFFF, sum = 0
3672 23:24:11.711612 1, 0xFFFF, sum = 0
3673 23:24:11.711709 2, 0xFFFF, sum = 0
3674 23:24:11.715152 3, 0xFFFF, sum = 0
3675 23:24:11.715224 4, 0xFFFF, sum = 0
3676 23:24:11.718728 5, 0xFFFF, sum = 0
3677 23:24:11.718829 6, 0xFFFF, sum = 0
3678 23:24:11.721896 7, 0xFFFF, sum = 0
3679 23:24:11.725322 8, 0xFFFF, sum = 0
3680 23:24:11.725428 9, 0xFFFF, sum = 0
3681 23:24:11.728320 10, 0xFFFF, sum = 0
3682 23:24:11.728409 11, 0xFFFF, sum = 0
3683 23:24:11.731803 12, 0x0, sum = 1
3684 23:24:11.731872 13, 0x0, sum = 2
3685 23:24:11.735520 14, 0x0, sum = 3
3686 23:24:11.735600 15, 0x0, sum = 4
3687 23:24:11.735668 best_step = 13
3688 23:24:11.735728
3689 23:24:11.738632 ==
3690 23:24:11.741847 Dram Type= 6, Freq= 0, CH_1, rank 1
3691 23:24:11.745214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3692 23:24:11.745286 ==
3693 23:24:11.745357 RX Vref Scan: 0
3694 23:24:11.745456
3695 23:24:11.748239 RX Vref 0 -> 0, step: 1
3696 23:24:11.748321
3697 23:24:11.751804 RX Delay -21 -> 252, step: 4
3698 23:24:11.755021 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3699 23:24:11.761743 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3700 23:24:11.765176 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3701 23:24:11.768468 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3702 23:24:11.771937 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3703 23:24:11.774799 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3704 23:24:11.778289 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3705 23:24:11.785006 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3706 23:24:11.788278 iDelay=191, Bit 8, Center 100 (35 ~ 166) 132
3707 23:24:11.791454 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3708 23:24:11.794996 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3709 23:24:11.798244 iDelay=191, Bit 11, Center 104 (39 ~ 170) 132
3710 23:24:11.805031 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3711 23:24:11.808474 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3712 23:24:11.811830 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3713 23:24:11.814673 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3714 23:24:11.814752 ==
3715 23:24:11.818073 Dram Type= 6, Freq= 0, CH_1, rank 1
3716 23:24:11.824827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3717 23:24:11.824910 ==
3718 23:24:11.824986 DQS Delay:
3719 23:24:11.828348 DQS0 = 0, DQS1 = 0
3720 23:24:11.828462 DQM Delay:
3721 23:24:11.831600 DQM0 = 113, DQM1 = 110
3722 23:24:11.831669 DQ Delay:
3723 23:24:11.834933 DQ0 =112, DQ1 =110, DQ2 =106, DQ3 =112
3724 23:24:11.838511 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =110
3725 23:24:11.841295 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =104
3726 23:24:11.844823 DQ12 =116, DQ13 =118, DQ14 =118, DQ15 =120
3727 23:24:11.844894
3728 23:24:11.844961
3729 23:24:11.854607 [DQSOSCAuto] RK1, (LSB)MR18= 0xf900, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 412 ps
3730 23:24:11.854706 CH1 RK1: MR19=304, MR18=F900
3731 23:24:11.861698 CH1_RK1: MR19=0x304, MR18=0xF900, DQSOSC=410, MR23=63, INC=39, DEC=26
3732 23:24:11.865072 [RxdqsGatingPostProcess] freq 1200
3733 23:24:11.871511 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3734 23:24:11.874863 best DQS0 dly(2T, 0.5T) = (0, 11)
3735 23:24:11.878067 best DQS1 dly(2T, 0.5T) = (0, 12)
3736 23:24:11.881729 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3737 23:24:11.884880 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3738 23:24:11.884955 best DQS0 dly(2T, 0.5T) = (0, 11)
3739 23:24:11.887944 best DQS1 dly(2T, 0.5T) = (0, 11)
3740 23:24:11.891332 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3741 23:24:11.894689 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3742 23:24:11.898333 Pre-setting of DQS Precalculation
3743 23:24:11.905002 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3744 23:24:11.911456 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3745 23:24:11.918060 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3746 23:24:11.918154
3747 23:24:11.918216
3748 23:24:11.921646 [Calibration Summary] 2400 Mbps
3749 23:24:11.921757 CH 0, Rank 0
3750 23:24:11.925062 SW Impedance : PASS
3751 23:24:11.928389 DUTY Scan : NO K
3752 23:24:11.928460 ZQ Calibration : PASS
3753 23:24:11.931695 Jitter Meter : NO K
3754 23:24:11.934743 CBT Training : PASS
3755 23:24:11.934818 Write leveling : PASS
3756 23:24:11.937942 RX DQS gating : PASS
3757 23:24:11.941421 RX DQ/DQS(RDDQC) : PASS
3758 23:24:11.941525 TX DQ/DQS : PASS
3759 23:24:11.945002 RX DATLAT : PASS
3760 23:24:11.947849 RX DQ/DQS(Engine): PASS
3761 23:24:11.947924 TX OE : NO K
3762 23:24:11.947984 All Pass.
3763 23:24:11.951195
3764 23:24:11.951271 CH 0, Rank 1
3765 23:24:11.954646 SW Impedance : PASS
3766 23:24:11.954719 DUTY Scan : NO K
3767 23:24:11.957962 ZQ Calibration : PASS
3768 23:24:11.961361 Jitter Meter : NO K
3769 23:24:11.961437 CBT Training : PASS
3770 23:24:11.964696 Write leveling : PASS
3771 23:24:11.964772 RX DQS gating : PASS
3772 23:24:11.967596 RX DQ/DQS(RDDQC) : PASS
3773 23:24:11.971615 TX DQ/DQS : PASS
3774 23:24:11.971691 RX DATLAT : PASS
3775 23:24:11.974938 RX DQ/DQS(Engine): PASS
3776 23:24:11.977698 TX OE : NO K
3777 23:24:11.977769 All Pass.
3778 23:24:11.977828
3779 23:24:11.977892 CH 1, Rank 0
3780 23:24:11.981450 SW Impedance : PASS
3781 23:24:11.984809 DUTY Scan : NO K
3782 23:24:11.984892 ZQ Calibration : PASS
3783 23:24:11.987710 Jitter Meter : NO K
3784 23:24:11.990894 CBT Training : PASS
3785 23:24:11.990970 Write leveling : PASS
3786 23:24:11.994624 RX DQS gating : PASS
3787 23:24:11.997812 RX DQ/DQS(RDDQC) : PASS
3788 23:24:11.997912 TX DQ/DQS : PASS
3789 23:24:12.001105 RX DATLAT : PASS
3790 23:24:12.004597 RX DQ/DQS(Engine): PASS
3791 23:24:12.004676 TX OE : NO K
3792 23:24:12.004737 All Pass.
3793 23:24:12.007675
3794 23:24:12.007744 CH 1, Rank 1
3795 23:24:12.010623 SW Impedance : PASS
3796 23:24:12.010727 DUTY Scan : NO K
3797 23:24:12.014721 ZQ Calibration : PASS
3798 23:24:12.017416 Jitter Meter : NO K
3799 23:24:12.017487 CBT Training : PASS
3800 23:24:12.020772 Write leveling : PASS
3801 23:24:12.020845 RX DQS gating : PASS
3802 23:24:12.024311 RX DQ/DQS(RDDQC) : PASS
3803 23:24:12.027560 TX DQ/DQS : PASS
3804 23:24:12.027634 RX DATLAT : PASS
3805 23:24:12.031035 RX DQ/DQS(Engine): PASS
3806 23:24:12.034437 TX OE : NO K
3807 23:24:12.034566 All Pass.
3808 23:24:12.034660
3809 23:24:12.037390 DramC Write-DBI off
3810 23:24:12.037487 PER_BANK_REFRESH: Hybrid Mode
3811 23:24:12.040813 TX_TRACKING: ON
3812 23:24:12.047769 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3813 23:24:12.054369 [FAST_K] Save calibration result to emmc
3814 23:24:12.057338 dramc_set_vcore_voltage set vcore to 650000
3815 23:24:12.057437 Read voltage for 600, 5
3816 23:24:12.060845 Vio18 = 0
3817 23:24:12.060948 Vcore = 650000
3818 23:24:12.061035 Vdram = 0
3819 23:24:12.064034 Vddq = 0
3820 23:24:12.064104 Vmddr = 0
3821 23:24:12.067411 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3822 23:24:12.073885 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3823 23:24:12.077258 MEM_TYPE=3, freq_sel=19
3824 23:24:12.081243 sv_algorithm_assistance_LP4_1600
3825 23:24:12.084439 ============ PULL DRAM RESETB DOWN ============
3826 23:24:12.087388 ========== PULL DRAM RESETB DOWN end =========
3827 23:24:12.094293 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3828 23:24:12.097165 ===================================
3829 23:24:12.097238 LPDDR4 DRAM CONFIGURATION
3830 23:24:12.100931 ===================================
3831 23:24:12.103962 EX_ROW_EN[0] = 0x0
3832 23:24:12.104043 EX_ROW_EN[1] = 0x0
3833 23:24:12.107389 LP4Y_EN = 0x0
3834 23:24:12.107466 WORK_FSP = 0x0
3835 23:24:12.110613 WL = 0x2
3836 23:24:12.110687 RL = 0x2
3837 23:24:12.113867 BL = 0x2
3838 23:24:12.113938 RPST = 0x0
3839 23:24:12.117650 RD_PRE = 0x0
3840 23:24:12.117722 WR_PRE = 0x1
3841 23:24:12.120640 WR_PST = 0x0
3842 23:24:12.123945 DBI_WR = 0x0
3843 23:24:12.124015 DBI_RD = 0x0
3844 23:24:12.127540 OTF = 0x1
3845 23:24:12.130746 ===================================
3846 23:24:12.134309 ===================================
3847 23:24:12.134383 ANA top config
3848 23:24:12.138135 ===================================
3849 23:24:12.141101 DLL_ASYNC_EN = 0
3850 23:24:12.141182 ALL_SLAVE_EN = 1
3851 23:24:12.144396 NEW_RANK_MODE = 1
3852 23:24:12.147674 DLL_IDLE_MODE = 1
3853 23:24:12.151201 LP45_APHY_COMB_EN = 1
3854 23:24:12.154332 TX_ODT_DIS = 1
3855 23:24:12.154427 NEW_8X_MODE = 1
3856 23:24:12.157778 ===================================
3857 23:24:12.161042 ===================================
3858 23:24:12.164253 data_rate = 1200
3859 23:24:12.167507 CKR = 1
3860 23:24:12.171112 DQ_P2S_RATIO = 8
3861 23:24:12.174602 ===================================
3862 23:24:12.177369 CA_P2S_RATIO = 8
3863 23:24:12.177436 DQ_CA_OPEN = 0
3864 23:24:12.181251 DQ_SEMI_OPEN = 0
3865 23:24:12.184410 CA_SEMI_OPEN = 0
3866 23:24:12.188019 CA_FULL_RATE = 0
3867 23:24:12.191587 DQ_CKDIV4_EN = 1
3868 23:24:12.194263 CA_CKDIV4_EN = 1
3869 23:24:12.194333 CA_PREDIV_EN = 0
3870 23:24:12.197649 PH8_DLY = 0
3871 23:24:12.201022 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3872 23:24:12.204609 DQ_AAMCK_DIV = 4
3873 23:24:12.208080 CA_AAMCK_DIV = 4
3874 23:24:12.210823 CA_ADMCK_DIV = 4
3875 23:24:12.210899 DQ_TRACK_CA_EN = 0
3876 23:24:12.214641 CA_PICK = 600
3877 23:24:12.217596 CA_MCKIO = 600
3878 23:24:12.221043 MCKIO_SEMI = 0
3879 23:24:12.224393 PLL_FREQ = 2288
3880 23:24:12.227704 DQ_UI_PI_RATIO = 32
3881 23:24:12.230978 CA_UI_PI_RATIO = 0
3882 23:24:12.234227 ===================================
3883 23:24:12.234354 ===================================
3884 23:24:12.237528 memory_type:LPDDR4
3885 23:24:12.241131 GP_NUM : 10
3886 23:24:12.241205 SRAM_EN : 1
3887 23:24:12.244047 MD32_EN : 0
3888 23:24:12.247561 ===================================
3889 23:24:12.251065 [ANA_INIT] >>>>>>>>>>>>>>
3890 23:24:12.254552 <<<<<< [CONFIGURE PHASE]: ANA_TX
3891 23:24:12.257846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3892 23:24:12.261020 ===================================
3893 23:24:12.261099 data_rate = 1200,PCW = 0X5800
3894 23:24:12.264037 ===================================
3895 23:24:12.267992 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3896 23:24:12.274260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3897 23:24:12.281086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3898 23:24:12.284377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3899 23:24:12.287759 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3900 23:24:12.291433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3901 23:24:12.294297 [ANA_INIT] flow start
3902 23:24:12.297824 [ANA_INIT] PLL >>>>>>>>
3903 23:24:12.297894 [ANA_INIT] PLL <<<<<<<<
3904 23:24:12.301234 [ANA_INIT] MIDPI >>>>>>>>
3905 23:24:12.304700 [ANA_INIT] MIDPI <<<<<<<<
3906 23:24:12.304779 [ANA_INIT] DLL >>>>>>>>
3907 23:24:12.307890 [ANA_INIT] flow end
3908 23:24:12.310949 ============ LP4 DIFF to SE enter ============
3909 23:24:12.314559 ============ LP4 DIFF to SE exit ============
3910 23:24:12.317534 [ANA_INIT] <<<<<<<<<<<<<
3911 23:24:12.321013 [Flow] Enable top DCM control >>>>>
3912 23:24:12.324261 [Flow] Enable top DCM control <<<<<
3913 23:24:12.327602 Enable DLL master slave shuffle
3914 23:24:12.334275 ==============================================================
3915 23:24:12.334359 Gating Mode config
3916 23:24:12.341137 ==============================================================
3917 23:24:12.341214 Config description:
3918 23:24:12.351093 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3919 23:24:12.357949 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3920 23:24:12.364191 SELPH_MODE 0: By rank 1: By Phase
3921 23:24:12.367527 ==============================================================
3922 23:24:12.371153 GAT_TRACK_EN = 1
3923 23:24:12.373985 RX_GATING_MODE = 2
3924 23:24:12.377697 RX_GATING_TRACK_MODE = 2
3925 23:24:12.381083 SELPH_MODE = 1
3926 23:24:12.384016 PICG_EARLY_EN = 1
3927 23:24:12.387967 VALID_LAT_VALUE = 1
3928 23:24:12.391099 ==============================================================
3929 23:24:12.394527 Enter into Gating configuration >>>>
3930 23:24:12.397323 Exit from Gating configuration <<<<
3931 23:24:12.400868 Enter into DVFS_PRE_config >>>>>
3932 23:24:12.414521 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3933 23:24:12.417732 Exit from DVFS_PRE_config <<<<<
3934 23:24:12.420700 Enter into PICG configuration >>>>
3935 23:24:12.420774 Exit from PICG configuration <<<<
3936 23:24:12.424622 [RX_INPUT] configuration >>>>>
3937 23:24:12.427554 [RX_INPUT] configuration <<<<<
3938 23:24:12.434085 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3939 23:24:12.437764 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3940 23:24:12.444516 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3941 23:24:12.451018 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3942 23:24:12.457249 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3943 23:24:12.464267 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3944 23:24:12.467661 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3945 23:24:12.470701 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3946 23:24:12.474290 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3947 23:24:12.481303 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3948 23:24:12.484605 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3949 23:24:12.487568 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3950 23:24:12.491055 ===================================
3951 23:24:12.494191 LPDDR4 DRAM CONFIGURATION
3952 23:24:12.497614 ===================================
3953 23:24:12.497696 EX_ROW_EN[0] = 0x0
3954 23:24:12.500743 EX_ROW_EN[1] = 0x0
3955 23:24:12.504284 LP4Y_EN = 0x0
3956 23:24:12.504365 WORK_FSP = 0x0
3957 23:24:12.507751 WL = 0x2
3958 23:24:12.507832 RL = 0x2
3959 23:24:12.511044 BL = 0x2
3960 23:24:12.511125 RPST = 0x0
3961 23:24:12.514422 RD_PRE = 0x0
3962 23:24:12.514519 WR_PRE = 0x1
3963 23:24:12.517477 WR_PST = 0x0
3964 23:24:12.517561 DBI_WR = 0x0
3965 23:24:12.520761 DBI_RD = 0x0
3966 23:24:12.520856 OTF = 0x1
3967 23:24:12.524171 ===================================
3968 23:24:12.527820 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3969 23:24:12.534094 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3970 23:24:12.537660 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3971 23:24:12.540987 ===================================
3972 23:24:12.544612 LPDDR4 DRAM CONFIGURATION
3973 23:24:12.547725 ===================================
3974 23:24:12.547837 EX_ROW_EN[0] = 0x10
3975 23:24:12.551115 EX_ROW_EN[1] = 0x0
3976 23:24:12.551197 LP4Y_EN = 0x0
3977 23:24:12.554377 WORK_FSP = 0x0
3978 23:24:12.554480 WL = 0x2
3979 23:24:12.557728 RL = 0x2
3980 23:24:12.557809 BL = 0x2
3981 23:24:12.561019 RPST = 0x0
3982 23:24:12.561115 RD_PRE = 0x0
3983 23:24:12.564297 WR_PRE = 0x1
3984 23:24:12.568097 WR_PST = 0x0
3985 23:24:12.568178 DBI_WR = 0x0
3986 23:24:12.571070 DBI_RD = 0x0
3987 23:24:12.571156 OTF = 0x1
3988 23:24:12.574387 ===================================
3989 23:24:12.581209 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3990 23:24:12.584874 nWR fixed to 30
3991 23:24:12.587931 [ModeRegInit_LP4] CH0 RK0
3992 23:24:12.588013 [ModeRegInit_LP4] CH0 RK1
3993 23:24:12.591358 [ModeRegInit_LP4] CH1 RK0
3994 23:24:12.594737 [ModeRegInit_LP4] CH1 RK1
3995 23:24:12.594818 match AC timing 17
3996 23:24:12.601469 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3997 23:24:12.604950 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3998 23:24:12.608292 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3999 23:24:12.615145 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4000 23:24:12.618537 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4001 23:24:12.618619 ==
4002 23:24:12.621325 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 23:24:12.624700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 23:24:12.624781 ==
4005 23:24:12.631421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4006 23:24:12.638012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4007 23:24:12.641651 [CA 0] Center 36 (6~66) winsize 61
4008 23:24:12.644896 [CA 1] Center 36 (6~66) winsize 61
4009 23:24:12.647917 [CA 2] Center 34 (4~65) winsize 62
4010 23:24:12.651775 [CA 3] Center 34 (4~65) winsize 62
4011 23:24:12.654604 [CA 4] Center 34 (3~65) winsize 63
4012 23:24:12.658309 [CA 5] Center 33 (3~64) winsize 62
4013 23:24:12.658390
4014 23:24:12.661436 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4015 23:24:12.661518
4016 23:24:12.665109 [CATrainingPosCal] consider 1 rank data
4017 23:24:12.668488 u2DelayCellTimex100 = 270/100 ps
4018 23:24:12.671331 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4019 23:24:12.674776 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4020 23:24:12.678007 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4021 23:24:12.681384 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4022 23:24:12.684643 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4023 23:24:12.688455 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4024 23:24:12.688532
4025 23:24:12.694817 CA PerBit enable=1, Macro0, CA PI delay=33
4026 23:24:12.694898
4027 23:24:12.694964 [CBTSetCACLKResult] CA Dly = 33
4028 23:24:12.698161 CS Dly: 4 (0~35)
4029 23:24:12.698261 ==
4030 23:24:12.701471 Dram Type= 6, Freq= 0, CH_0, rank 1
4031 23:24:12.704935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 23:24:12.705015 ==
4033 23:24:12.711612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4034 23:24:12.718039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4035 23:24:12.721351 [CA 0] Center 36 (6~66) winsize 61
4036 23:24:12.724668 [CA 1] Center 36 (6~66) winsize 61
4037 23:24:12.728273 [CA 2] Center 34 (4~65) winsize 62
4038 23:24:12.731381 [CA 3] Center 34 (4~65) winsize 62
4039 23:24:12.734698 [CA 4] Center 33 (3~64) winsize 62
4040 23:24:12.738518 [CA 5] Center 33 (3~64) winsize 62
4041 23:24:12.738592
4042 23:24:12.741674 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4043 23:24:12.741748
4044 23:24:12.745187 [CATrainingPosCal] consider 2 rank data
4045 23:24:12.748016 u2DelayCellTimex100 = 270/100 ps
4046 23:24:12.752300 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4047 23:24:12.755189 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4048 23:24:12.758720 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4049 23:24:12.761469 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4050 23:24:12.764705 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4051 23:24:12.768470 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4052 23:24:12.768548
4053 23:24:12.774739 CA PerBit enable=1, Macro0, CA PI delay=33
4054 23:24:12.774824
4055 23:24:12.774887 [CBTSetCACLKResult] CA Dly = 33
4056 23:24:12.779028 CS Dly: 4 (0~36)
4057 23:24:12.779101
4058 23:24:12.781724 ----->DramcWriteLeveling(PI) begin...
4059 23:24:12.781792 ==
4060 23:24:12.784732 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 23:24:12.788323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 23:24:12.788399 ==
4063 23:24:12.791758 Write leveling (Byte 0): 32 => 32
4064 23:24:12.794971 Write leveling (Byte 1): 32 => 32
4065 23:24:12.798524 DramcWriteLeveling(PI) end<-----
4066 23:24:12.798594
4067 23:24:12.798660 ==
4068 23:24:12.801739 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 23:24:12.805380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 23:24:12.805451 ==
4071 23:24:12.808376 [Gating] SW mode calibration
4072 23:24:12.815285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4073 23:24:12.821718 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4074 23:24:12.825449 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4075 23:24:12.832232 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4076 23:24:12.835256 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4077 23:24:12.838365 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4078 23:24:12.842127 0 9 16 | B1->B0 | 3232 2b2b | 1 0 | (1 0) (1 1)
4079 23:24:12.848543 0 9 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4080 23:24:12.851927 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4081 23:24:12.854876 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4082 23:24:12.861551 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4083 23:24:12.865305 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 23:24:12.868267 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 23:24:12.874907 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4086 23:24:12.878598 0 10 16 | B1->B0 | 2d2d 3939 | 0 0 | (0 0) (0 0)
4087 23:24:12.881785 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 23:24:12.888740 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 23:24:12.891564 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 23:24:12.895596 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 23:24:12.901744 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 23:24:12.905375 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 23:24:12.908755 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 23:24:12.914905 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4095 23:24:12.918201 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 23:24:12.921798 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 23:24:12.928799 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 23:24:12.931687 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 23:24:12.934925 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 23:24:12.938215 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 23:24:12.945472 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 23:24:12.948793 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 23:24:12.951681 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 23:24:12.958620 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 23:24:12.961953 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 23:24:12.965371 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 23:24:12.971869 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 23:24:12.975362 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 23:24:12.978457 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 23:24:12.985197 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4111 23:24:12.988690 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4112 23:24:12.992011 Total UI for P1: 0, mck2ui 16
4113 23:24:12.995448 best dqsien dly found for B0: ( 0, 13, 16)
4114 23:24:12.998277 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4115 23:24:13.001870 Total UI for P1: 0, mck2ui 16
4116 23:24:13.005361 best dqsien dly found for B1: ( 0, 13, 20)
4117 23:24:13.008840 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4118 23:24:13.011773 best DQS1 dly(MCK, UI, PI) = (0, 13, 20)
4119 23:24:13.011853
4120 23:24:13.018929 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4121 23:24:13.021703 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 20)
4122 23:24:13.021779 [Gating] SW calibration Done
4123 23:24:13.025222 ==
4124 23:24:13.025308 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 23:24:13.031817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 23:24:13.031893 ==
4127 23:24:13.031954 RX Vref Scan: 0
4128 23:24:13.032013
4129 23:24:13.035191 RX Vref 0 -> 0, step: 1
4130 23:24:13.035271
4131 23:24:13.038683 RX Delay -230 -> 252, step: 16
4132 23:24:13.041722 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4133 23:24:13.045061 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4134 23:24:13.051753 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4135 23:24:13.055203 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4136 23:24:13.058433 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4137 23:24:13.062824 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4138 23:24:13.065210 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4139 23:24:13.072221 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4140 23:24:13.075507 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4141 23:24:13.078783 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4142 23:24:13.081696 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4143 23:24:13.088792 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4144 23:24:13.092023 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4145 23:24:13.095246 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4146 23:24:13.098800 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4147 23:24:13.102052 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4148 23:24:13.105687 ==
4149 23:24:13.109092 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 23:24:13.111996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 23:24:13.112079 ==
4152 23:24:13.112143 DQS Delay:
4153 23:24:13.115328 DQS0 = 0, DQS1 = 0
4154 23:24:13.115408 DQM Delay:
4155 23:24:13.118715 DQM0 = 42, DQM1 = 31
4156 23:24:13.118795 DQ Delay:
4157 23:24:13.122151 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4158 23:24:13.125568 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4159 23:24:13.128725 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4160 23:24:13.131836 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4161 23:24:13.131918
4162 23:24:13.131982
4163 23:24:13.132041 ==
4164 23:24:13.135044 Dram Type= 6, Freq= 0, CH_0, rank 0
4165 23:24:13.138565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 23:24:13.138685 ==
4167 23:24:13.138749
4168 23:24:13.138809
4169 23:24:13.141789 TX Vref Scan disable
4170 23:24:13.145134 == TX Byte 0 ==
4171 23:24:13.148732 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4172 23:24:13.151771 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4173 23:24:13.155482 == TX Byte 1 ==
4174 23:24:13.159110 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4175 23:24:13.161857 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4176 23:24:13.161938 ==
4177 23:24:13.165188 Dram Type= 6, Freq= 0, CH_0, rank 0
4178 23:24:13.168565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 23:24:13.172006 ==
4180 23:24:13.172114
4181 23:24:13.172210
4182 23:24:13.172297 TX Vref Scan disable
4183 23:24:13.175635 == TX Byte 0 ==
4184 23:24:13.178939 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4185 23:24:13.185464 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4186 23:24:13.185545 == TX Byte 1 ==
4187 23:24:13.189246 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4188 23:24:13.195781 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4189 23:24:13.195894
4190 23:24:13.195984 [DATLAT]
4191 23:24:13.196069 Freq=600, CH0 RK0
4192 23:24:13.196151
4193 23:24:13.198846 DATLAT Default: 0x9
4194 23:24:13.198927 0, 0xFFFF, sum = 0
4195 23:24:13.202225 1, 0xFFFF, sum = 0
4196 23:24:13.202306 2, 0xFFFF, sum = 0
4197 23:24:13.206101 3, 0xFFFF, sum = 0
4198 23:24:13.206184 4, 0xFFFF, sum = 0
4199 23:24:13.209240 5, 0xFFFF, sum = 0
4200 23:24:13.212430 6, 0xFFFF, sum = 0
4201 23:24:13.212513 7, 0xFFFF, sum = 0
4202 23:24:13.212578 8, 0x0, sum = 1
4203 23:24:13.215812 9, 0x0, sum = 2
4204 23:24:13.215893 10, 0x0, sum = 3
4205 23:24:13.219236 11, 0x0, sum = 4
4206 23:24:13.219317 best_step = 9
4207 23:24:13.219381
4208 23:24:13.219442 ==
4209 23:24:13.222516 Dram Type= 6, Freq= 0, CH_0, rank 0
4210 23:24:13.228961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 23:24:13.229043 ==
4212 23:24:13.229108 RX Vref Scan: 1
4213 23:24:13.229167
4214 23:24:13.232500 RX Vref 0 -> 0, step: 1
4215 23:24:13.232580
4216 23:24:13.235640 RX Delay -195 -> 252, step: 8
4217 23:24:13.235720
4218 23:24:13.239284 Set Vref, RX VrefLevel [Byte0]: 54
4219 23:24:13.242510 [Byte1]: 51
4220 23:24:13.242591
4221 23:24:13.245884 Final RX Vref Byte 0 = 54 to rank0
4222 23:24:13.249144 Final RX Vref Byte 1 = 51 to rank0
4223 23:24:13.252158 Final RX Vref Byte 0 = 54 to rank1
4224 23:24:13.255445 Final RX Vref Byte 1 = 51 to rank1==
4225 23:24:13.258840 Dram Type= 6, Freq= 0, CH_0, rank 0
4226 23:24:13.262655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 23:24:13.262736 ==
4228 23:24:13.265436 DQS Delay:
4229 23:24:13.265516 DQS0 = 0, DQS1 = 0
4230 23:24:13.265596 DQM Delay:
4231 23:24:13.268861 DQM0 = 42, DQM1 = 33
4232 23:24:13.268941 DQ Delay:
4233 23:24:13.272272 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4234 23:24:13.275542 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4235 23:24:13.278789 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4236 23:24:13.282280 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4237 23:24:13.282360
4238 23:24:13.282478
4239 23:24:13.291956 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f1e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4240 23:24:13.295295 CH0 RK0: MR19=808, MR18=3F1E
4241 23:24:13.298520 CH0_RK0: MR19=0x808, MR18=0x3F1E, DQSOSC=397, MR23=63, INC=166, DEC=110
4242 23:24:13.298601
4243 23:24:13.301840 ----->DramcWriteLeveling(PI) begin...
4244 23:24:13.305299 ==
4245 23:24:13.309181 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 23:24:13.312123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 23:24:13.312205 ==
4248 23:24:13.315827 Write leveling (Byte 0): 31 => 31
4249 23:24:13.319249 Write leveling (Byte 1): 31 => 31
4250 23:24:13.322822 DramcWriteLeveling(PI) end<-----
4251 23:24:13.322932
4252 23:24:13.323023 ==
4253 23:24:13.325293 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 23:24:13.329074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 23:24:13.329173 ==
4256 23:24:13.332181 [Gating] SW mode calibration
4257 23:24:13.338962 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4258 23:24:13.341915 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4259 23:24:13.348737 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4260 23:24:13.351977 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4261 23:24:13.355439 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4262 23:24:13.362233 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
4263 23:24:13.365389 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
4264 23:24:13.368661 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4265 23:24:13.375674 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 23:24:13.378739 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 23:24:13.381818 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 23:24:13.389169 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 23:24:13.392150 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 23:24:13.395246 0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
4271 23:24:13.402026 0 10 16 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
4272 23:24:13.405266 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 23:24:13.408516 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 23:24:13.415602 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 23:24:13.418963 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 23:24:13.422035 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 23:24:13.428428 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 23:24:13.431986 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4279 23:24:13.435623 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4280 23:24:13.441964 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4281 23:24:13.445068 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 23:24:13.448902 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 23:24:13.452396 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 23:24:13.458629 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 23:24:13.461849 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 23:24:13.465416 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 23:24:13.471788 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 23:24:13.475336 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 23:24:13.478450 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 23:24:13.485244 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 23:24:13.488557 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 23:24:13.491896 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 23:24:13.498695 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 23:24:13.502005 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4295 23:24:13.505055 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4296 23:24:13.508764 Total UI for P1: 0, mck2ui 16
4297 23:24:13.511808 best dqsien dly found for B0: ( 0, 13, 12)
4298 23:24:13.518402 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 23:24:13.518484 Total UI for P1: 0, mck2ui 16
4300 23:24:13.521703 best dqsien dly found for B1: ( 0, 13, 16)
4301 23:24:13.528730 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4302 23:24:13.531844 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4303 23:24:13.531918
4304 23:24:13.535196 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4305 23:24:13.538671 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4306 23:24:13.541917 [Gating] SW calibration Done
4307 23:24:13.541998 ==
4308 23:24:13.545996 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 23:24:13.548630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 23:24:13.548712 ==
4311 23:24:13.551744 RX Vref Scan: 0
4312 23:24:13.551844
4313 23:24:13.551923 RX Vref 0 -> 0, step: 1
4314 23:24:13.551982
4315 23:24:13.555026 RX Delay -230 -> 252, step: 16
4316 23:24:13.558548 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4317 23:24:13.565352 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4318 23:24:13.568656 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4319 23:24:13.571827 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4320 23:24:13.575484 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4321 23:24:13.581915 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4322 23:24:13.585211 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4323 23:24:13.588309 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4324 23:24:13.592090 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4325 23:24:13.595159 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4326 23:24:13.601946 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4327 23:24:13.605481 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4328 23:24:13.608928 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4329 23:24:13.611566 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4330 23:24:13.618906 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4331 23:24:13.622510 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4332 23:24:13.622600 ==
4333 23:24:13.625343 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 23:24:13.629024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 23:24:13.629138 ==
4336 23:24:13.629215 DQS Delay:
4337 23:24:13.632052 DQS0 = 0, DQS1 = 0
4338 23:24:13.632139 DQM Delay:
4339 23:24:13.635502 DQM0 = 41, DQM1 = 33
4340 23:24:13.635580 DQ Delay:
4341 23:24:13.639016 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4342 23:24:13.641999 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4343 23:24:13.645887 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4344 23:24:13.648601 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4345 23:24:13.648683
4346 23:24:13.648748
4347 23:24:13.648807 ==
4348 23:24:13.652139 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 23:24:13.655759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 23:24:13.658628 ==
4351 23:24:13.658746
4352 23:24:13.658852
4353 23:24:13.658939 TX Vref Scan disable
4354 23:24:13.662077 == TX Byte 0 ==
4355 23:24:13.665338 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4356 23:24:13.668724 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4357 23:24:13.671739 == TX Byte 1 ==
4358 23:24:13.675205 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4359 23:24:13.678347 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4360 23:24:13.681886 ==
4361 23:24:13.685258 Dram Type= 6, Freq= 0, CH_0, rank 1
4362 23:24:13.688305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 23:24:13.688415 ==
4364 23:24:13.688517
4365 23:24:13.688604
4366 23:24:13.692123 TX Vref Scan disable
4367 23:24:13.692223 == TX Byte 0 ==
4368 23:24:13.698321 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4369 23:24:13.701809 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4370 23:24:13.701903 == TX Byte 1 ==
4371 23:24:13.708376 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4372 23:24:13.711662 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4373 23:24:13.711768
4374 23:24:13.711847 [DATLAT]
4375 23:24:13.715114 Freq=600, CH0 RK1
4376 23:24:13.715201
4377 23:24:13.715264 DATLAT Default: 0x9
4378 23:24:13.718160 0, 0xFFFF, sum = 0
4379 23:24:13.718261 1, 0xFFFF, sum = 0
4380 23:24:13.721649 2, 0xFFFF, sum = 0
4381 23:24:13.724956 3, 0xFFFF, sum = 0
4382 23:24:13.725039 4, 0xFFFF, sum = 0
4383 23:24:13.728427 5, 0xFFFF, sum = 0
4384 23:24:13.728510 6, 0xFFFF, sum = 0
4385 23:24:13.731854 7, 0xFFFF, sum = 0
4386 23:24:13.731937 8, 0x0, sum = 1
4387 23:24:13.732004 9, 0x0, sum = 2
4388 23:24:13.735187 10, 0x0, sum = 3
4389 23:24:13.735269 11, 0x0, sum = 4
4390 23:24:13.738658 best_step = 9
4391 23:24:13.738740
4392 23:24:13.738804 ==
4393 23:24:13.741597 Dram Type= 6, Freq= 0, CH_0, rank 1
4394 23:24:13.745286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 23:24:13.745368 ==
4396 23:24:13.748785 RX Vref Scan: 0
4397 23:24:13.748866
4398 23:24:13.748931 RX Vref 0 -> 0, step: 1
4399 23:24:13.748991
4400 23:24:13.751880 RX Delay -195 -> 252, step: 8
4401 23:24:13.758915 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4402 23:24:13.762277 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4403 23:24:13.765805 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4404 23:24:13.768798 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4405 23:24:13.775664 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4406 23:24:13.779212 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4407 23:24:13.782391 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4408 23:24:13.785517 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4409 23:24:13.789168 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4410 23:24:13.795718 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4411 23:24:13.798883 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4412 23:24:13.802861 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4413 23:24:13.805656 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4414 23:24:13.812329 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4415 23:24:13.815692 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4416 23:24:13.819106 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4417 23:24:13.819193 ==
4418 23:24:13.822621 Dram Type= 6, Freq= 0, CH_0, rank 1
4419 23:24:13.825468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 23:24:13.825549 ==
4421 23:24:13.828908 DQS Delay:
4422 23:24:13.828988 DQS0 = 0, DQS1 = 0
4423 23:24:13.832391 DQM Delay:
4424 23:24:13.832470 DQM0 = 40, DQM1 = 32
4425 23:24:13.832533 DQ Delay:
4426 23:24:13.836211 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4427 23:24:13.839038 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4428 23:24:13.842613 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =20
4429 23:24:13.845897 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4430 23:24:13.845977
4431 23:24:13.846040
4432 23:24:13.855739 [DQSOSCAuto] RK1, (LSB)MR18= 0x4628, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4433 23:24:13.859212 CH0 RK1: MR19=808, MR18=4628
4434 23:24:13.865620 CH0_RK1: MR19=0x808, MR18=0x4628, DQSOSC=396, MR23=63, INC=167, DEC=111
4435 23:24:13.865705 [RxdqsGatingPostProcess] freq 600
4436 23:24:13.872320 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4437 23:24:13.876120 Pre-setting of DQS Precalculation
4438 23:24:13.878972 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4439 23:24:13.882193 ==
4440 23:24:13.882273 Dram Type= 6, Freq= 0, CH_1, rank 0
4441 23:24:13.888798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 23:24:13.888881 ==
4443 23:24:13.892078 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4444 23:24:13.898722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4445 23:24:13.902393 [CA 0] Center 35 (5~66) winsize 62
4446 23:24:13.905746 [CA 1] Center 35 (5~66) winsize 62
4447 23:24:13.909425 [CA 2] Center 34 (3~65) winsize 63
4448 23:24:13.912662 [CA 3] Center 33 (3~64) winsize 62
4449 23:24:13.915859 [CA 4] Center 34 (3~65) winsize 63
4450 23:24:13.919120 [CA 5] Center 33 (2~64) winsize 63
4451 23:24:13.919229
4452 23:24:13.923108 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4453 23:24:13.923188
4454 23:24:13.925816 [CATrainingPosCal] consider 1 rank data
4455 23:24:13.929223 u2DelayCellTimex100 = 270/100 ps
4456 23:24:13.932578 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4457 23:24:13.936082 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4458 23:24:13.942734 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4459 23:24:13.945727 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4460 23:24:13.949406 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4461 23:24:13.952816 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4462 23:24:13.952897
4463 23:24:13.956397 CA PerBit enable=1, Macro0, CA PI delay=33
4464 23:24:13.956477
4465 23:24:13.959571 [CBTSetCACLKResult] CA Dly = 33
4466 23:24:13.959652 CS Dly: 4 (0~35)
4467 23:24:13.959715 ==
4468 23:24:13.963083 Dram Type= 6, Freq= 0, CH_1, rank 1
4469 23:24:13.969049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 23:24:13.969156 ==
4471 23:24:13.972446 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4472 23:24:13.979705 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4473 23:24:13.982531 [CA 0] Center 35 (5~66) winsize 62
4474 23:24:13.986232 [CA 1] Center 35 (5~66) winsize 62
4475 23:24:13.989536 [CA 2] Center 34 (4~65) winsize 62
4476 23:24:13.992817 [CA 3] Center 34 (3~65) winsize 63
4477 23:24:13.996128 [CA 4] Center 34 (3~65) winsize 63
4478 23:24:13.999376 [CA 5] Center 33 (3~64) winsize 62
4479 23:24:13.999456
4480 23:24:14.002895 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4481 23:24:14.002980
4482 23:24:14.006305 [CATrainingPosCal] consider 2 rank data
4483 23:24:14.010240 u2DelayCellTimex100 = 270/100 ps
4484 23:24:14.012861 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4485 23:24:14.016485 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4486 23:24:14.022923 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4487 23:24:14.025828 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4488 23:24:14.029437 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4489 23:24:14.032952 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4490 23:24:14.033036
4491 23:24:14.035723 CA PerBit enable=1, Macro0, CA PI delay=33
4492 23:24:14.035837
4493 23:24:14.039167 [CBTSetCACLKResult] CA Dly = 33
4494 23:24:14.039250 CS Dly: 5 (0~37)
4495 23:24:14.039335
4496 23:24:14.042845 ----->DramcWriteLeveling(PI) begin...
4497 23:24:14.045657 ==
4498 23:24:14.048984 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 23:24:14.052399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 23:24:14.052483 ==
4501 23:24:14.055824 Write leveling (Byte 0): 30 => 30
4502 23:24:14.059246 Write leveling (Byte 1): 32 => 32
4503 23:24:14.062733 DramcWriteLeveling(PI) end<-----
4504 23:24:14.062816
4505 23:24:14.062900 ==
4506 23:24:14.066142 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 23:24:14.069423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 23:24:14.069508 ==
4509 23:24:14.072695 [Gating] SW mode calibration
4510 23:24:14.079681 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4511 23:24:14.082359 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4512 23:24:14.089687 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4513 23:24:14.092401 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4514 23:24:14.095982 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4515 23:24:14.102780 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4516 23:24:14.105831 0 9 16 | B1->B0 | 2b2b 2727 | 0 0 | (0 0) (0 0)
4517 23:24:14.109267 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4518 23:24:14.116075 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 23:24:14.119410 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 23:24:14.122460 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 23:24:14.129076 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 23:24:14.132856 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4523 23:24:14.136058 0 10 12 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 0)
4524 23:24:14.142814 0 10 16 | B1->B0 | 4242 4444 | 0 0 | (0 0) (0 0)
4525 23:24:14.145756 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 23:24:14.149462 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 23:24:14.156062 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 23:24:14.159357 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 23:24:14.162718 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 23:24:14.165944 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 23:24:14.172598 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 23:24:14.175756 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4533 23:24:14.179216 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 23:24:14.186104 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 23:24:14.188983 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 23:24:14.192390 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 23:24:14.199212 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 23:24:14.202506 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 23:24:14.205980 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 23:24:14.212712 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 23:24:14.216144 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 23:24:14.219716 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 23:24:14.226064 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 23:24:14.229395 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 23:24:14.232835 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 23:24:14.239713 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 23:24:14.242654 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4548 23:24:14.246089 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4549 23:24:14.249470 Total UI for P1: 0, mck2ui 16
4550 23:24:14.252403 best dqsien dly found for B0: ( 0, 13, 12)
4551 23:24:14.256136 Total UI for P1: 0, mck2ui 16
4552 23:24:14.259084 best dqsien dly found for B1: ( 0, 13, 14)
4553 23:24:14.262909 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4554 23:24:14.265829 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4555 23:24:14.265958
4556 23:24:14.269290 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4557 23:24:14.275899 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4558 23:24:14.276011 [Gating] SW calibration Done
4559 23:24:14.276096 ==
4560 23:24:14.279332 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 23:24:14.285932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 23:24:14.286045 ==
4563 23:24:14.286138 RX Vref Scan: 0
4564 23:24:14.286228
4565 23:24:14.289331 RX Vref 0 -> 0, step: 1
4566 23:24:14.289411
4567 23:24:14.292875 RX Delay -230 -> 252, step: 16
4568 23:24:14.295923 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4569 23:24:14.299469 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4570 23:24:14.302640 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4571 23:24:14.309378 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4572 23:24:14.312684 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4573 23:24:14.316002 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4574 23:24:14.319183 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4575 23:24:14.326043 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4576 23:24:14.329415 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4577 23:24:14.333075 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4578 23:24:14.336098 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4579 23:24:14.339856 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4580 23:24:14.346514 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4581 23:24:14.349244 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4582 23:24:14.352843 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4583 23:24:14.356617 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4584 23:24:14.356698 ==
4585 23:24:14.359490 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 23:24:14.366244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 23:24:14.366352 ==
4588 23:24:14.366473 DQS Delay:
4589 23:24:14.369470 DQS0 = 0, DQS1 = 0
4590 23:24:14.369551 DQM Delay:
4591 23:24:14.369614 DQM0 = 44, DQM1 = 35
4592 23:24:14.372878 DQ Delay:
4593 23:24:14.376416 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4594 23:24:14.379399 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4595 23:24:14.383139 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4596 23:24:14.386389 DQ12 =49, DQ13 =41, DQ14 =33, DQ15 =41
4597 23:24:14.386508
4598 23:24:14.386572
4599 23:24:14.386631 ==
4600 23:24:14.390093 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 23:24:14.392982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 23:24:14.393089 ==
4603 23:24:14.393186
4604 23:24:14.393251
4605 23:24:14.396281 TX Vref Scan disable
4606 23:24:14.396362 == TX Byte 0 ==
4607 23:24:14.402679 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4608 23:24:14.406184 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4609 23:24:14.406264 == TX Byte 1 ==
4610 23:24:14.412847 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4611 23:24:14.416001 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4612 23:24:14.416082 ==
4613 23:24:14.419853 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 23:24:14.422656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 23:24:14.422737 ==
4616 23:24:14.422802
4617 23:24:14.425989
4618 23:24:14.426069 TX Vref Scan disable
4619 23:24:14.429826 == TX Byte 0 ==
4620 23:24:14.433008 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4621 23:24:14.436606 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4622 23:24:14.439579 == TX Byte 1 ==
4623 23:24:14.443134 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4624 23:24:14.446255 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4625 23:24:14.449971
4626 23:24:14.450050 [DATLAT]
4627 23:24:14.450113 Freq=600, CH1 RK0
4628 23:24:14.450174
4629 23:24:14.453238 DATLAT Default: 0x9
4630 23:24:14.453318 0, 0xFFFF, sum = 0
4631 23:24:14.456895 1, 0xFFFF, sum = 0
4632 23:24:14.456977 2, 0xFFFF, sum = 0
4633 23:24:14.459566 3, 0xFFFF, sum = 0
4634 23:24:14.459648 4, 0xFFFF, sum = 0
4635 23:24:14.462996 5, 0xFFFF, sum = 0
4636 23:24:14.463078 6, 0xFFFF, sum = 0
4637 23:24:14.466378 7, 0xFFFF, sum = 0
4638 23:24:14.466497 8, 0x0, sum = 1
4639 23:24:14.469732 9, 0x0, sum = 2
4640 23:24:14.469814 10, 0x0, sum = 3
4641 23:24:14.473046 11, 0x0, sum = 4
4642 23:24:14.473128 best_step = 9
4643 23:24:14.473192
4644 23:24:14.473251 ==
4645 23:24:14.476243 Dram Type= 6, Freq= 0, CH_1, rank 0
4646 23:24:14.482917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 23:24:14.483001 ==
4648 23:24:14.483085 RX Vref Scan: 1
4649 23:24:14.483165
4650 23:24:14.486443 RX Vref 0 -> 0, step: 1
4651 23:24:14.486542
4652 23:24:14.489264 RX Delay -179 -> 252, step: 8
4653 23:24:14.489350
4654 23:24:14.492716 Set Vref, RX VrefLevel [Byte0]: 56
4655 23:24:14.495913 [Byte1]: 54
4656 23:24:14.495996
4657 23:24:14.499861 Final RX Vref Byte 0 = 56 to rank0
4658 23:24:14.502665 Final RX Vref Byte 1 = 54 to rank0
4659 23:24:14.505993 Final RX Vref Byte 0 = 56 to rank1
4660 23:24:14.509867 Final RX Vref Byte 1 = 54 to rank1==
4661 23:24:14.512672 Dram Type= 6, Freq= 0, CH_1, rank 0
4662 23:24:14.516005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 23:24:14.516089 ==
4664 23:24:14.519710 DQS Delay:
4665 23:24:14.519794 DQS0 = 0, DQS1 = 0
4666 23:24:14.519879 DQM Delay:
4667 23:24:14.522915 DQM0 = 41, DQM1 = 33
4668 23:24:14.522999 DQ Delay:
4669 23:24:14.526034 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4670 23:24:14.529529 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4671 23:24:14.532894 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4672 23:24:14.536025 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4673 23:24:14.536109
4674 23:24:14.536193
4675 23:24:14.546574 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d03, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4676 23:24:14.546659 CH1 RK0: MR19=808, MR18=3D03
4677 23:24:14.552993 CH1_RK0: MR19=0x808, MR18=0x3D03, DQSOSC=398, MR23=63, INC=165, DEC=110
4678 23:24:14.553077
4679 23:24:14.555988 ----->DramcWriteLeveling(PI) begin...
4680 23:24:14.556074 ==
4681 23:24:14.559513 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 23:24:14.566073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 23:24:14.566157 ==
4684 23:24:14.569481 Write leveling (Byte 0): 29 => 29
4685 23:24:14.572757 Write leveling (Byte 1): 31 => 31
4686 23:24:14.572838 DramcWriteLeveling(PI) end<-----
4687 23:24:14.572906
4688 23:24:14.576341 ==
4689 23:24:14.579542 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 23:24:14.583212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 23:24:14.583294 ==
4692 23:24:14.586550 [Gating] SW mode calibration
4693 23:24:14.593200 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4694 23:24:14.596209 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4695 23:24:14.603074 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4696 23:24:14.606387 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4697 23:24:14.609583 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4698 23:24:14.616689 0 9 12 | B1->B0 | 3332 2c2c | 1 1 | (1 1) (1 0)
4699 23:24:14.619667 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4700 23:24:14.622761 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4701 23:24:14.629575 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4702 23:24:14.633102 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 23:24:14.636396 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4704 23:24:14.642805 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4705 23:24:14.646270 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4706 23:24:14.649773 0 10 12 | B1->B0 | 3232 3d3d | 0 1 | (1 1) (0 0)
4707 23:24:14.656377 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4708 23:24:14.659772 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 23:24:14.663237 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 23:24:14.666462 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 23:24:14.673080 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 23:24:14.676541 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 23:24:14.679750 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 23:24:14.685990 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4715 23:24:14.689468 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4716 23:24:14.693008 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 23:24:14.699594 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 23:24:14.702886 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 23:24:14.706310 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 23:24:14.713397 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 23:24:14.716160 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 23:24:14.719628 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 23:24:14.726329 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 23:24:14.729748 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 23:24:14.732768 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 23:24:14.739343 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 23:24:14.742658 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 23:24:14.745922 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 23:24:14.752826 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 23:24:14.756084 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4731 23:24:14.759624 Total UI for P1: 0, mck2ui 16
4732 23:24:14.762849 best dqsien dly found for B0: ( 0, 13, 10)
4733 23:24:14.766197 Total UI for P1: 0, mck2ui 16
4734 23:24:14.769346 best dqsien dly found for B1: ( 0, 13, 10)
4735 23:24:14.772882 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4736 23:24:14.776149 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4737 23:24:14.776227
4738 23:24:14.779536 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4739 23:24:14.782742 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4740 23:24:14.785957 [Gating] SW calibration Done
4741 23:24:14.786036 ==
4742 23:24:14.789255 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 23:24:14.793250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 23:24:14.793335 ==
4745 23:24:14.796146 RX Vref Scan: 0
4746 23:24:14.796223
4747 23:24:14.799544 RX Vref 0 -> 0, step: 1
4748 23:24:14.799625
4749 23:24:14.799703 RX Delay -230 -> 252, step: 16
4750 23:24:14.806272 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4751 23:24:14.809278 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4752 23:24:14.812726 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4753 23:24:14.815966 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4754 23:24:14.823375 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4755 23:24:14.826263 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4756 23:24:14.829659 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4757 23:24:14.833015 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4758 23:24:14.836183 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4759 23:24:14.842651 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4760 23:24:14.846134 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4761 23:24:14.849390 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4762 23:24:14.852638 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4763 23:24:14.859471 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4764 23:24:14.862975 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4765 23:24:14.866484 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4766 23:24:14.866559 ==
4767 23:24:14.869608 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 23:24:14.872634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 23:24:14.872735 ==
4770 23:24:14.876102 DQS Delay:
4771 23:24:14.876179 DQS0 = 0, DQS1 = 0
4772 23:24:14.879272 DQM Delay:
4773 23:24:14.879343 DQM0 = 40, DQM1 = 36
4774 23:24:14.883208 DQ Delay:
4775 23:24:14.883288 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4776 23:24:14.885814 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4777 23:24:14.889663 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4778 23:24:14.892694 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4779 23:24:14.892792
4780 23:24:14.892891
4781 23:24:14.895933 ==
4782 23:24:14.899405 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 23:24:14.902947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 23:24:14.903022 ==
4785 23:24:14.903085
4786 23:24:14.903157
4787 23:24:14.905913 TX Vref Scan disable
4788 23:24:14.905991 == TX Byte 0 ==
4789 23:24:14.912431 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4790 23:24:14.915600 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4791 23:24:14.915672 == TX Byte 1 ==
4792 23:24:14.922631 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4793 23:24:14.925918 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4794 23:24:14.926016 ==
4795 23:24:14.929329 Dram Type= 6, Freq= 0, CH_1, rank 1
4796 23:24:14.932544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4797 23:24:14.932617 ==
4798 23:24:14.932679
4799 23:24:14.932756
4800 23:24:14.936089 TX Vref Scan disable
4801 23:24:14.939225 == TX Byte 0 ==
4802 23:24:14.942671 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4803 23:24:14.946081 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4804 23:24:14.949331 == TX Byte 1 ==
4805 23:24:14.953087 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4806 23:24:14.956141 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4807 23:24:14.956223
4808 23:24:14.959480 [DATLAT]
4809 23:24:14.959626 Freq=600, CH1 RK1
4810 23:24:14.959714
4811 23:24:14.962655 DATLAT Default: 0x9
4812 23:24:14.962752 0, 0xFFFF, sum = 0
4813 23:24:14.966110 1, 0xFFFF, sum = 0
4814 23:24:14.966184 2, 0xFFFF, sum = 0
4815 23:24:14.969600 3, 0xFFFF, sum = 0
4816 23:24:14.969685 4, 0xFFFF, sum = 0
4817 23:24:14.972649 5, 0xFFFF, sum = 0
4818 23:24:14.972739 6, 0xFFFF, sum = 0
4819 23:24:14.976168 7, 0xFFFF, sum = 0
4820 23:24:14.976257 8, 0x0, sum = 1
4821 23:24:14.979456 9, 0x0, sum = 2
4822 23:24:14.979579 10, 0x0, sum = 3
4823 23:24:14.982850 11, 0x0, sum = 4
4824 23:24:14.982923 best_step = 9
4825 23:24:14.982994
4826 23:24:14.983066 ==
4827 23:24:14.986111 Dram Type= 6, Freq= 0, CH_1, rank 1
4828 23:24:14.989577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4829 23:24:14.989652 ==
4830 23:24:14.992679 RX Vref Scan: 0
4831 23:24:14.992757
4832 23:24:14.996215 RX Vref 0 -> 0, step: 1
4833 23:24:14.996289
4834 23:24:14.996368 RX Delay -195 -> 252, step: 8
4835 23:24:15.004055 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4836 23:24:15.007376 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4837 23:24:15.010900 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4838 23:24:15.014365 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4839 23:24:15.020515 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4840 23:24:15.024181 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4841 23:24:15.027517 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4842 23:24:15.031308 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4843 23:24:15.033939 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4844 23:24:15.040808 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4845 23:24:15.044535 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4846 23:24:15.048175 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4847 23:24:15.051069 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4848 23:24:15.057953 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4849 23:24:15.060781 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4850 23:24:15.064342 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4851 23:24:15.064425 ==
4852 23:24:15.067856 Dram Type= 6, Freq= 0, CH_1, rank 1
4853 23:24:15.071254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4854 23:24:15.071336 ==
4855 23:24:15.075237 DQS Delay:
4856 23:24:15.075318 DQS0 = 0, DQS1 = 0
4857 23:24:15.075381 DQM Delay:
4858 23:24:15.077769 DQM0 = 38, DQM1 = 33
4859 23:24:15.077849 DQ Delay:
4860 23:24:15.081356 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4861 23:24:15.084775 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =32
4862 23:24:15.088164 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4863 23:24:15.091577 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4864 23:24:15.091682
4865 23:24:15.091764
4866 23:24:15.101176 [DQSOSCAuto] RK1, (LSB)MR18= 0x3241, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4867 23:24:15.104489 CH1 RK1: MR19=808, MR18=3241
4868 23:24:15.107829 CH1_RK1: MR19=0x808, MR18=0x3241, DQSOSC=397, MR23=63, INC=166, DEC=110
4869 23:24:15.111461 [RxdqsGatingPostProcess] freq 600
4870 23:24:15.117934 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4871 23:24:15.121353 Pre-setting of DQS Precalculation
4872 23:24:15.124536 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4873 23:24:15.131431 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4874 23:24:15.141332 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4875 23:24:15.141414
4876 23:24:15.141478
4877 23:24:15.144431 [Calibration Summary] 1200 Mbps
4878 23:24:15.144517 CH 0, Rank 0
4879 23:24:15.147867 SW Impedance : PASS
4880 23:24:15.147948 DUTY Scan : NO K
4881 23:24:15.151586 ZQ Calibration : PASS
4882 23:24:15.154278 Jitter Meter : NO K
4883 23:24:15.154358 CBT Training : PASS
4884 23:24:15.158038 Write leveling : PASS
4885 23:24:15.161109 RX DQS gating : PASS
4886 23:24:15.161190 RX DQ/DQS(RDDQC) : PASS
4887 23:24:15.164069 TX DQ/DQS : PASS
4888 23:24:15.164150 RX DATLAT : PASS
4889 23:24:15.168047 RX DQ/DQS(Engine): PASS
4890 23:24:15.171056 TX OE : NO K
4891 23:24:15.171177 All Pass.
4892 23:24:15.171266
4893 23:24:15.171344 CH 0, Rank 1
4894 23:24:15.174766 SW Impedance : PASS
4895 23:24:15.177527 DUTY Scan : NO K
4896 23:24:15.177617 ZQ Calibration : PASS
4897 23:24:15.180937 Jitter Meter : NO K
4898 23:24:15.184720 CBT Training : PASS
4899 23:24:15.184793 Write leveling : PASS
4900 23:24:15.188023 RX DQS gating : PASS
4901 23:24:15.191167 RX DQ/DQS(RDDQC) : PASS
4902 23:24:15.191255 TX DQ/DQS : PASS
4903 23:24:15.194516 RX DATLAT : PASS
4904 23:24:15.197971 RX DQ/DQS(Engine): PASS
4905 23:24:15.198087 TX OE : NO K
4906 23:24:15.198178 All Pass.
4907 23:24:15.198266
4908 23:24:15.200793 CH 1, Rank 0
4909 23:24:15.204453 SW Impedance : PASS
4910 23:24:15.204525 DUTY Scan : NO K
4911 23:24:15.207419 ZQ Calibration : PASS
4912 23:24:15.207491 Jitter Meter : NO K
4913 23:24:15.210845 CBT Training : PASS
4914 23:24:15.214254 Write leveling : PASS
4915 23:24:15.214352 RX DQS gating : PASS
4916 23:24:15.217574 RX DQ/DQS(RDDQC) : PASS
4917 23:24:15.220658 TX DQ/DQS : PASS
4918 23:24:15.220758 RX DATLAT : PASS
4919 23:24:15.224098 RX DQ/DQS(Engine): PASS
4920 23:24:15.227846 TX OE : NO K
4921 23:24:15.227923 All Pass.
4922 23:24:15.228002
4923 23:24:15.228073 CH 1, Rank 1
4924 23:24:15.230820 SW Impedance : PASS
4925 23:24:15.234392 DUTY Scan : NO K
4926 23:24:15.234506 ZQ Calibration : PASS
4927 23:24:15.237649 Jitter Meter : NO K
4928 23:24:15.240944 CBT Training : PASS
4929 23:24:15.241067 Write leveling : PASS
4930 23:24:15.243876 RX DQS gating : PASS
4931 23:24:15.247350 RX DQ/DQS(RDDQC) : PASS
4932 23:24:15.247462 TX DQ/DQS : PASS
4933 23:24:15.250557 RX DATLAT : PASS
4934 23:24:15.253961 RX DQ/DQS(Engine): PASS
4935 23:24:15.254069 TX OE : NO K
4936 23:24:15.254178 All Pass.
4937 23:24:15.254292
4938 23:24:15.257420 DramC Write-DBI off
4939 23:24:15.260735 PER_BANK_REFRESH: Hybrid Mode
4940 23:24:15.260866 TX_TRACKING: ON
4941 23:24:15.270824 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4942 23:24:15.274074 [FAST_K] Save calibration result to emmc
4943 23:24:15.277432 dramc_set_vcore_voltage set vcore to 662500
4944 23:24:15.280556 Read voltage for 933, 3
4945 23:24:15.280629 Vio18 = 0
4946 23:24:15.284094 Vcore = 662500
4947 23:24:15.284189 Vdram = 0
4948 23:24:15.284276 Vddq = 0
4949 23:24:15.284337 Vmddr = 0
4950 23:24:15.290777 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4951 23:24:15.294145 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4952 23:24:15.297358 MEM_TYPE=3, freq_sel=17
4953 23:24:15.300696 sv_algorithm_assistance_LP4_1600
4954 23:24:15.304178 ============ PULL DRAM RESETB DOWN ============
4955 23:24:15.311007 ========== PULL DRAM RESETB DOWN end =========
4956 23:24:15.313760 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4957 23:24:15.317211 ===================================
4958 23:24:15.320822 LPDDR4 DRAM CONFIGURATION
4959 23:24:15.323940 ===================================
4960 23:24:15.324015 EX_ROW_EN[0] = 0x0
4961 23:24:15.327269 EX_ROW_EN[1] = 0x0
4962 23:24:15.327350 LP4Y_EN = 0x0
4963 23:24:15.330573 WORK_FSP = 0x0
4964 23:24:15.330648 WL = 0x3
4965 23:24:15.334230 RL = 0x3
4966 23:24:15.334328 BL = 0x2
4967 23:24:15.337057 RPST = 0x0
4968 23:24:15.337149 RD_PRE = 0x0
4969 23:24:15.340603 WR_PRE = 0x1
4970 23:24:15.340675 WR_PST = 0x0
4971 23:24:15.343846 DBI_WR = 0x0
4972 23:24:15.343943 DBI_RD = 0x0
4973 23:24:15.347032 OTF = 0x1
4974 23:24:15.350588 ===================================
4975 23:24:15.353862 ===================================
4976 23:24:15.353937 ANA top config
4977 23:24:15.357404 ===================================
4978 23:24:15.360472 DLL_ASYNC_EN = 0
4979 23:24:15.363963 ALL_SLAVE_EN = 1
4980 23:24:15.367098 NEW_RANK_MODE = 1
4981 23:24:15.367175 DLL_IDLE_MODE = 1
4982 23:24:15.370636 LP45_APHY_COMB_EN = 1
4983 23:24:15.374024 TX_ODT_DIS = 1
4984 23:24:15.377634 NEW_8X_MODE = 1
4985 23:24:15.380667 ===================================
4986 23:24:15.384079 ===================================
4987 23:24:15.387261 data_rate = 1866
4988 23:24:15.387394 CKR = 1
4989 23:24:15.390727 DQ_P2S_RATIO = 8
4990 23:24:15.393912 ===================================
4991 23:24:15.397524 CA_P2S_RATIO = 8
4992 23:24:15.400422 DQ_CA_OPEN = 0
4993 23:24:15.404003 DQ_SEMI_OPEN = 0
4994 23:24:15.407185 CA_SEMI_OPEN = 0
4995 23:24:15.407268 CA_FULL_RATE = 0
4996 23:24:15.410435 DQ_CKDIV4_EN = 1
4997 23:24:15.413854 CA_CKDIV4_EN = 1
4998 23:24:15.417451 CA_PREDIV_EN = 0
4999 23:24:15.420900 PH8_DLY = 0
5000 23:24:15.423748 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5001 23:24:15.423828 DQ_AAMCK_DIV = 4
5002 23:24:15.427133 CA_AAMCK_DIV = 4
5003 23:24:15.430573 CA_ADMCK_DIV = 4
5004 23:24:15.433729 DQ_TRACK_CA_EN = 0
5005 23:24:15.437079 CA_PICK = 933
5006 23:24:15.440362 CA_MCKIO = 933
5007 23:24:15.440455 MCKIO_SEMI = 0
5008 23:24:15.443740 PLL_FREQ = 3732
5009 23:24:15.447693 DQ_UI_PI_RATIO = 32
5010 23:24:15.450951 CA_UI_PI_RATIO = 0
5011 23:24:15.454211 ===================================
5012 23:24:15.457413 ===================================
5013 23:24:15.460967 memory_type:LPDDR4
5014 23:24:15.461049 GP_NUM : 10
5015 23:24:15.463816 SRAM_EN : 1
5016 23:24:15.467701 MD32_EN : 0
5017 23:24:15.470672 ===================================
5018 23:24:15.470745 [ANA_INIT] >>>>>>>>>>>>>>
5019 23:24:15.474429 <<<<<< [CONFIGURE PHASE]: ANA_TX
5020 23:24:15.477112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5021 23:24:15.480700 ===================================
5022 23:24:15.483932 data_rate = 1866,PCW = 0X8f00
5023 23:24:15.487182 ===================================
5024 23:24:15.490557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5025 23:24:15.497676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5026 23:24:15.500494 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5027 23:24:15.507457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5028 23:24:15.510727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5029 23:24:15.513789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5030 23:24:15.513873 [ANA_INIT] flow start
5031 23:24:15.517311 [ANA_INIT] PLL >>>>>>>>
5032 23:24:15.520336 [ANA_INIT] PLL <<<<<<<<
5033 23:24:15.520413 [ANA_INIT] MIDPI >>>>>>>>
5034 23:24:15.524433 [ANA_INIT] MIDPI <<<<<<<<
5035 23:24:15.527302 [ANA_INIT] DLL >>>>>>>>
5036 23:24:15.527381 [ANA_INIT] flow end
5037 23:24:15.533957 ============ LP4 DIFF to SE enter ============
5038 23:24:15.537429 ============ LP4 DIFF to SE exit ============
5039 23:24:15.540795 [ANA_INIT] <<<<<<<<<<<<<
5040 23:24:15.543799 [Flow] Enable top DCM control >>>>>
5041 23:24:15.547423 [Flow] Enable top DCM control <<<<<
5042 23:24:15.547500 Enable DLL master slave shuffle
5043 23:24:15.554232 ==============================================================
5044 23:24:15.557621 Gating Mode config
5045 23:24:15.560476 ==============================================================
5046 23:24:15.563883 Config description:
5047 23:24:15.574078 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5048 23:24:15.580802 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5049 23:24:15.584032 SELPH_MODE 0: By rank 1: By Phase
5050 23:24:15.591043 ==============================================================
5051 23:24:15.593939 GAT_TRACK_EN = 1
5052 23:24:15.597076 RX_GATING_MODE = 2
5053 23:24:15.600402 RX_GATING_TRACK_MODE = 2
5054 23:24:15.600483 SELPH_MODE = 1
5055 23:24:15.603678 PICG_EARLY_EN = 1
5056 23:24:15.607276 VALID_LAT_VALUE = 1
5057 23:24:15.614020 ==============================================================
5058 23:24:15.617583 Enter into Gating configuration >>>>
5059 23:24:15.620822 Exit from Gating configuration <<<<
5060 23:24:15.623990 Enter into DVFS_PRE_config >>>>>
5061 23:24:15.633882 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5062 23:24:15.637564 Exit from DVFS_PRE_config <<<<<
5063 23:24:15.640820 Enter into PICG configuration >>>>
5064 23:24:15.643848 Exit from PICG configuration <<<<
5065 23:24:15.647015 [RX_INPUT] configuration >>>>>
5066 23:24:15.650296 [RX_INPUT] configuration <<<<<
5067 23:24:15.653741 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5068 23:24:15.660961 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5069 23:24:15.667261 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5070 23:24:15.670834 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5071 23:24:15.677280 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5072 23:24:15.684496 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5073 23:24:15.687225 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5074 23:24:15.693970 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5075 23:24:15.697377 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5076 23:24:15.700827 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5077 23:24:15.704078 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5078 23:24:15.711726 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5079 23:24:15.714172 ===================================
5080 23:24:15.714250 LPDDR4 DRAM CONFIGURATION
5081 23:24:15.717092 ===================================
5082 23:24:15.720854 EX_ROW_EN[0] = 0x0
5083 23:24:15.723777 EX_ROW_EN[1] = 0x0
5084 23:24:15.723863 LP4Y_EN = 0x0
5085 23:24:15.727313 WORK_FSP = 0x0
5086 23:24:15.727396 WL = 0x3
5087 23:24:15.730911 RL = 0x3
5088 23:24:15.730984 BL = 0x2
5089 23:24:15.734018 RPST = 0x0
5090 23:24:15.734099 RD_PRE = 0x0
5091 23:24:15.737399 WR_PRE = 0x1
5092 23:24:15.737485 WR_PST = 0x0
5093 23:24:15.740625 DBI_WR = 0x0
5094 23:24:15.740733 DBI_RD = 0x0
5095 23:24:15.743917 OTF = 0x1
5096 23:24:15.747149 ===================================
5097 23:24:15.750499 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5098 23:24:15.753793 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5099 23:24:15.760504 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5100 23:24:15.763901 ===================================
5101 23:24:15.763990 LPDDR4 DRAM CONFIGURATION
5102 23:24:15.767382 ===================================
5103 23:24:15.770744 EX_ROW_EN[0] = 0x10
5104 23:24:15.770817 EX_ROW_EN[1] = 0x0
5105 23:24:15.774052 LP4Y_EN = 0x0
5106 23:24:15.774123 WORK_FSP = 0x0
5107 23:24:15.777097 WL = 0x3
5108 23:24:15.777210 RL = 0x3
5109 23:24:15.780476 BL = 0x2
5110 23:24:15.783869 RPST = 0x0
5111 23:24:15.783995 RD_PRE = 0x0
5112 23:24:15.787641 WR_PRE = 0x1
5113 23:24:15.787729 WR_PST = 0x0
5114 23:24:15.790415 DBI_WR = 0x0
5115 23:24:15.790544 DBI_RD = 0x0
5116 23:24:15.793723 OTF = 0x1
5117 23:24:15.797412 ===================================
5118 23:24:15.800443 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5119 23:24:15.805881 nWR fixed to 30
5120 23:24:15.809543 [ModeRegInit_LP4] CH0 RK0
5121 23:24:15.809642 [ModeRegInit_LP4] CH0 RK1
5122 23:24:15.812904 [ModeRegInit_LP4] CH1 RK0
5123 23:24:15.816076 [ModeRegInit_LP4] CH1 RK1
5124 23:24:15.816156 match AC timing 9
5125 23:24:15.822270 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5126 23:24:15.825617 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5127 23:24:15.829572 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5128 23:24:15.836017 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5129 23:24:15.839349 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5130 23:24:15.839431 ==
5131 23:24:15.842835 Dram Type= 6, Freq= 0, CH_0, rank 0
5132 23:24:15.846182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5133 23:24:15.846267 ==
5134 23:24:15.852475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5135 23:24:15.859227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5136 23:24:15.862613 [CA 0] Center 38 (8~69) winsize 62
5137 23:24:15.865798 [CA 1] Center 38 (7~69) winsize 63
5138 23:24:15.869179 [CA 2] Center 35 (5~66) winsize 62
5139 23:24:15.872470 [CA 3] Center 34 (4~65) winsize 62
5140 23:24:15.876131 [CA 4] Center 34 (4~65) winsize 62
5141 23:24:15.879597 [CA 5] Center 34 (4~64) winsize 61
5142 23:24:15.879679
5143 23:24:15.883027 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5144 23:24:15.883124
5145 23:24:15.886125 [CATrainingPosCal] consider 1 rank data
5146 23:24:15.889733 u2DelayCellTimex100 = 270/100 ps
5147 23:24:15.892842 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5148 23:24:15.896124 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5149 23:24:15.899204 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5150 23:24:15.902871 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5151 23:24:15.906003 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5152 23:24:15.908944 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5153 23:24:15.909051
5154 23:24:15.915671 CA PerBit enable=1, Macro0, CA PI delay=34
5155 23:24:15.915753
5156 23:24:15.915817 [CBTSetCACLKResult] CA Dly = 34
5157 23:24:15.919180 CS Dly: 6 (0~37)
5158 23:24:15.919262 ==
5159 23:24:15.922414 Dram Type= 6, Freq= 0, CH_0, rank 1
5160 23:24:15.926122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 23:24:15.926240 ==
5162 23:24:15.933259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5163 23:24:15.939304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5164 23:24:15.942766 [CA 0] Center 38 (7~69) winsize 63
5165 23:24:15.946138 [CA 1] Center 38 (7~69) winsize 63
5166 23:24:15.949107 [CA 2] Center 35 (5~66) winsize 62
5167 23:24:15.952678 [CA 3] Center 35 (4~66) winsize 63
5168 23:24:15.955724 [CA 4] Center 34 (3~65) winsize 63
5169 23:24:15.959354 [CA 5] Center 33 (3~64) winsize 62
5170 23:24:15.959432
5171 23:24:15.962743 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5172 23:24:15.962836
5173 23:24:15.966067 [CATrainingPosCal] consider 2 rank data
5174 23:24:15.969310 u2DelayCellTimex100 = 270/100 ps
5175 23:24:15.972473 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5176 23:24:15.976011 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5177 23:24:15.979206 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5178 23:24:15.983033 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5179 23:24:15.986210 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5180 23:24:15.989244 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5181 23:24:15.989323
5182 23:24:15.996155 CA PerBit enable=1, Macro0, CA PI delay=34
5183 23:24:15.996253
5184 23:24:15.996316 [CBTSetCACLKResult] CA Dly = 34
5185 23:24:15.999594 CS Dly: 7 (0~39)
5186 23:24:15.999709
5187 23:24:16.002880 ----->DramcWriteLeveling(PI) begin...
5188 23:24:16.002967 ==
5189 23:24:16.005876 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 23:24:16.009998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 23:24:16.010110 ==
5192 23:24:16.012489 Write leveling (Byte 0): 32 => 32
5193 23:24:16.016289 Write leveling (Byte 1): 26 => 26
5194 23:24:16.019370 DramcWriteLeveling(PI) end<-----
5195 23:24:16.019444
5196 23:24:16.019515 ==
5197 23:24:16.022634 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 23:24:16.026073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 23:24:16.029311 ==
5200 23:24:16.029404 [Gating] SW mode calibration
5201 23:24:16.035794 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5202 23:24:16.042605 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5203 23:24:16.046027 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5204 23:24:16.052741 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5205 23:24:16.055814 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5206 23:24:16.059115 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5207 23:24:16.065976 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5208 23:24:16.069392 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 23:24:16.072571 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 23:24:16.079180 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
5211 23:24:16.082359 0 15 0 | B1->B0 | 3333 2e2e | 0 1 | (0 1) (1 0)
5212 23:24:16.085945 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5213 23:24:16.089423 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5214 23:24:16.096141 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5215 23:24:16.099343 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5216 23:24:16.102860 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 23:24:16.109079 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 23:24:16.112395 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5219 23:24:16.115847 1 0 0 | B1->B0 | 3232 3b3b | 1 0 | (1 1) (0 0)
5220 23:24:16.122333 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5221 23:24:16.126011 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 23:24:16.129274 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 23:24:16.136649 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 23:24:16.139329 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 23:24:16.143101 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 23:24:16.149365 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 23:24:16.152767 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5228 23:24:16.155766 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5229 23:24:16.162504 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 23:24:16.166273 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 23:24:16.169508 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 23:24:16.176135 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 23:24:16.179147 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 23:24:16.182413 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 23:24:16.185991 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 23:24:16.192517 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 23:24:16.195789 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 23:24:16.199463 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 23:24:16.206213 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 23:24:16.209031 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 23:24:16.212414 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 23:24:16.219434 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5243 23:24:16.222644 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5244 23:24:16.226339 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5245 23:24:16.229025 Total UI for P1: 0, mck2ui 16
5246 23:24:16.232874 best dqsien dly found for B0: ( 1, 2, 30)
5247 23:24:16.235624 Total UI for P1: 0, mck2ui 16
5248 23:24:16.239148 best dqsien dly found for B1: ( 1, 3, 0)
5249 23:24:16.242689 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5250 23:24:16.245763 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5251 23:24:16.245841
5252 23:24:16.252300 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5253 23:24:16.256028 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5254 23:24:16.256134 [Gating] SW calibration Done
5255 23:24:16.259715 ==
5256 23:24:16.259796 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 23:24:16.265996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 23:24:16.266078 ==
5259 23:24:16.266190 RX Vref Scan: 0
5260 23:24:16.266281
5261 23:24:16.269475 RX Vref 0 -> 0, step: 1
5262 23:24:16.269587
5263 23:24:16.272884 RX Delay -80 -> 252, step: 8
5264 23:24:16.275735 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5265 23:24:16.279358 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5266 23:24:16.282349 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5267 23:24:16.285635 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5268 23:24:16.292641 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5269 23:24:16.296312 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5270 23:24:16.299111 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5271 23:24:16.302653 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5272 23:24:16.306564 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5273 23:24:16.312654 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5274 23:24:16.315978 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5275 23:24:16.319269 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5276 23:24:16.322809 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5277 23:24:16.325929 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5278 23:24:16.328874 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5279 23:24:16.335695 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5280 23:24:16.335776 ==
5281 23:24:16.338860 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 23:24:16.342358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 23:24:16.342477 ==
5284 23:24:16.342541 DQS Delay:
5285 23:24:16.346243 DQS0 = 0, DQS1 = 0
5286 23:24:16.346323 DQM Delay:
5287 23:24:16.349046 DQM0 = 98, DQM1 = 87
5288 23:24:16.349126 DQ Delay:
5289 23:24:16.352762 DQ0 =99, DQ1 =103, DQ2 =91, DQ3 =91
5290 23:24:16.356213 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =103
5291 23:24:16.360461 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =79
5292 23:24:16.362848 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5293 23:24:16.362943
5294 23:24:16.363037
5295 23:24:16.363111 ==
5296 23:24:16.365962 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 23:24:16.369713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 23:24:16.369844 ==
5299 23:24:16.369932
5300 23:24:16.373011
5301 23:24:16.373107 TX Vref Scan disable
5302 23:24:16.375667 == TX Byte 0 ==
5303 23:24:16.379107 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5304 23:24:16.382306 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5305 23:24:16.385674 == TX Byte 1 ==
5306 23:24:16.389274 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5307 23:24:16.392496 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5308 23:24:16.392578 ==
5309 23:24:16.396094 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 23:24:16.402706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 23:24:16.402788 ==
5312 23:24:16.402852
5313 23:24:16.402911
5314 23:24:16.403003 TX Vref Scan disable
5315 23:24:16.406557 == TX Byte 0 ==
5316 23:24:16.410185 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5317 23:24:16.413586 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5318 23:24:16.417470 == TX Byte 1 ==
5319 23:24:16.420526 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5320 23:24:16.423399 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5321 23:24:16.426805
5322 23:24:16.426901 [DATLAT]
5323 23:24:16.427007 Freq=933, CH0 RK0
5324 23:24:16.427090
5325 23:24:16.430050 DATLAT Default: 0xd
5326 23:24:16.430146 0, 0xFFFF, sum = 0
5327 23:24:16.433917 1, 0xFFFF, sum = 0
5328 23:24:16.434001 2, 0xFFFF, sum = 0
5329 23:24:16.436556 3, 0xFFFF, sum = 0
5330 23:24:16.436632 4, 0xFFFF, sum = 0
5331 23:24:16.440072 5, 0xFFFF, sum = 0
5332 23:24:16.443320 6, 0xFFFF, sum = 0
5333 23:24:16.443399 7, 0xFFFF, sum = 0
5334 23:24:16.446932 8, 0xFFFF, sum = 0
5335 23:24:16.447006 9, 0xFFFF, sum = 0
5336 23:24:16.450082 10, 0x0, sum = 1
5337 23:24:16.450166 11, 0x0, sum = 2
5338 23:24:16.450229 12, 0x0, sum = 3
5339 23:24:16.453375 13, 0x0, sum = 4
5340 23:24:16.453449 best_step = 11
5341 23:24:16.453520
5342 23:24:16.453577 ==
5343 23:24:16.456849 Dram Type= 6, Freq= 0, CH_0, rank 0
5344 23:24:16.463754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 23:24:16.463856 ==
5346 23:24:16.463957 RX Vref Scan: 1
5347 23:24:16.464080
5348 23:24:16.466687 RX Vref 0 -> 0, step: 1
5349 23:24:16.466760
5350 23:24:16.470278 RX Delay -69 -> 252, step: 4
5351 23:24:16.470360
5352 23:24:16.473327 Set Vref, RX VrefLevel [Byte0]: 54
5353 23:24:16.476844 [Byte1]: 51
5354 23:24:16.476950
5355 23:24:16.480055 Final RX Vref Byte 0 = 54 to rank0
5356 23:24:16.483811 Final RX Vref Byte 1 = 51 to rank0
5357 23:24:16.486828 Final RX Vref Byte 0 = 54 to rank1
5358 23:24:16.490362 Final RX Vref Byte 1 = 51 to rank1==
5359 23:24:16.493870 Dram Type= 6, Freq= 0, CH_0, rank 0
5360 23:24:16.497299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 23:24:16.497377 ==
5362 23:24:16.499897 DQS Delay:
5363 23:24:16.499975 DQS0 = 0, DQS1 = 0
5364 23:24:16.503215 DQM Delay:
5365 23:24:16.503290 DQM0 = 97, DQM1 = 87
5366 23:24:16.503350 DQ Delay:
5367 23:24:16.506638 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5368 23:24:16.510599 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =104
5369 23:24:16.513457 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =80
5370 23:24:16.516738 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =96
5371 23:24:16.516813
5372 23:24:16.516873
5373 23:24:16.526837 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5374 23:24:16.530351 CH0 RK0: MR19=504, MR18=14FF
5375 23:24:16.533640 CH0_RK0: MR19=0x504, MR18=0x14FF, DQSOSC=415, MR23=63, INC=62, DEC=41
5376 23:24:16.533712
5377 23:24:16.536666 ----->DramcWriteLeveling(PI) begin...
5378 23:24:16.540110 ==
5379 23:24:16.543458 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 23:24:16.547121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 23:24:16.547208 ==
5382 23:24:16.550292 Write leveling (Byte 0): 31 => 31
5383 23:24:16.553817 Write leveling (Byte 1): 30 => 30
5384 23:24:16.556865 DramcWriteLeveling(PI) end<-----
5385 23:24:16.556947
5386 23:24:16.557011 ==
5387 23:24:16.560151 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 23:24:16.563883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 23:24:16.563993 ==
5390 23:24:16.566634 [Gating] SW mode calibration
5391 23:24:16.573796 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5392 23:24:16.576882 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5393 23:24:16.583876 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5394 23:24:16.586963 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5395 23:24:16.590172 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5396 23:24:16.597281 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5397 23:24:16.600594 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 23:24:16.603717 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 23:24:16.610604 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5400 23:24:16.613927 0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
5401 23:24:16.617517 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5402 23:24:16.624152 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 23:24:16.627144 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 23:24:16.630827 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5405 23:24:16.636737 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 23:24:16.640352 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 23:24:16.643650 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 23:24:16.650102 0 15 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5409 23:24:16.653545 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5410 23:24:16.657138 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 23:24:16.663152 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 23:24:16.666621 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 23:24:16.670349 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 23:24:16.677039 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 23:24:16.680370 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5416 23:24:16.683914 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5417 23:24:16.690287 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5418 23:24:16.693139 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 23:24:16.696766 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 23:24:16.703038 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 23:24:16.706530 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 23:24:16.709992 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 23:24:16.713390 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 23:24:16.720097 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 23:24:16.723332 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 23:24:16.726698 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 23:24:16.733510 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 23:24:16.736506 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 23:24:16.740987 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 23:24:16.746331 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 23:24:16.749726 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 23:24:16.753123 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5433 23:24:16.756633 Total UI for P1: 0, mck2ui 16
5434 23:24:16.759929 best dqsien dly found for B0: ( 1, 2, 26)
5435 23:24:16.766327 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5436 23:24:16.769522 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5437 23:24:16.773306 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 23:24:16.776363 Total UI for P1: 0, mck2ui 16
5439 23:24:16.779723 best dqsien dly found for B1: ( 1, 3, 0)
5440 23:24:16.782959 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5441 23:24:16.786446 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5442 23:24:16.786528
5443 23:24:16.792762 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5444 23:24:16.796154 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5445 23:24:16.796291 [Gating] SW calibration Done
5446 23:24:16.799535 ==
5447 23:24:16.799694 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 23:24:16.806036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 23:24:16.806124 ==
5450 23:24:16.806190 RX Vref Scan: 0
5451 23:24:16.806255
5452 23:24:16.809254 RX Vref 0 -> 0, step: 1
5453 23:24:16.809333
5454 23:24:16.812580 RX Delay -80 -> 252, step: 8
5455 23:24:16.816387 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5456 23:24:16.819420 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5457 23:24:16.822875 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5458 23:24:16.825943 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5459 23:24:16.832736 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5460 23:24:16.836068 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5461 23:24:16.839458 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5462 23:24:16.842893 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5463 23:24:16.846506 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5464 23:24:16.849545 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5465 23:24:16.856374 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5466 23:24:16.860126 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5467 23:24:16.862919 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5468 23:24:16.866349 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5469 23:24:16.870003 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5470 23:24:16.873283 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5471 23:24:16.876135 ==
5472 23:24:16.879664 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 23:24:16.883179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 23:24:16.883262 ==
5475 23:24:16.883358 DQS Delay:
5476 23:24:16.886229 DQS0 = 0, DQS1 = 0
5477 23:24:16.886311 DQM Delay:
5478 23:24:16.889490 DQM0 = 96, DQM1 = 87
5479 23:24:16.889575 DQ Delay:
5480 23:24:16.893192 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5481 23:24:16.896130 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5482 23:24:16.899786 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =75
5483 23:24:16.903389 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5484 23:24:16.903471
5485 23:24:16.903535
5486 23:24:16.903594 ==
5487 23:24:16.906155 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 23:24:16.909583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 23:24:16.909665 ==
5490 23:24:16.909729
5491 23:24:16.909814
5492 23:24:16.912905 TX Vref Scan disable
5493 23:24:16.916014 == TX Byte 0 ==
5494 23:24:16.919470 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5495 23:24:16.922867 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5496 23:24:16.926248 == TX Byte 1 ==
5497 23:24:16.929302 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5498 23:24:16.932671 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5499 23:24:16.932753 ==
5500 23:24:16.936672 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 23:24:16.939388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 23:24:16.943025 ==
5503 23:24:16.943106
5504 23:24:16.943171
5505 23:24:16.943231 TX Vref Scan disable
5506 23:24:16.946531 == TX Byte 0 ==
5507 23:24:16.950306 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5508 23:24:16.956460 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5509 23:24:16.956542 == TX Byte 1 ==
5510 23:24:16.959815 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5511 23:24:16.966207 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5512 23:24:16.966319
5513 23:24:16.966456 [DATLAT]
5514 23:24:16.966533 Freq=933, CH0 RK1
5515 23:24:16.966593
5516 23:24:16.970146 DATLAT Default: 0xb
5517 23:24:16.970227 0, 0xFFFF, sum = 0
5518 23:24:16.972942 1, 0xFFFF, sum = 0
5519 23:24:16.973028 2, 0xFFFF, sum = 0
5520 23:24:16.976504 3, 0xFFFF, sum = 0
5521 23:24:16.976651 4, 0xFFFF, sum = 0
5522 23:24:16.979956 5, 0xFFFF, sum = 0
5523 23:24:16.983251 6, 0xFFFF, sum = 0
5524 23:24:16.983338 7, 0xFFFF, sum = 0
5525 23:24:16.986651 8, 0xFFFF, sum = 0
5526 23:24:16.986734 9, 0xFFFF, sum = 0
5527 23:24:16.989494 10, 0x0, sum = 1
5528 23:24:16.989583 11, 0x0, sum = 2
5529 23:24:16.989650 12, 0x0, sum = 3
5530 23:24:16.993210 13, 0x0, sum = 4
5531 23:24:16.993319 best_step = 11
5532 23:24:16.993409
5533 23:24:16.993495 ==
5534 23:24:16.996266 Dram Type= 6, Freq= 0, CH_0, rank 1
5535 23:24:17.003223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 23:24:17.003307 ==
5537 23:24:17.003372 RX Vref Scan: 0
5538 23:24:17.003432
5539 23:24:17.006263 RX Vref 0 -> 0, step: 1
5540 23:24:17.006370
5541 23:24:17.009841 RX Delay -61 -> 252, step: 4
5542 23:24:17.013264 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5543 23:24:17.016102 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5544 23:24:17.023157 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5545 23:24:17.026536 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5546 23:24:17.029681 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5547 23:24:17.033371 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5548 23:24:17.036585 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5549 23:24:17.039573 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5550 23:24:17.046347 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5551 23:24:17.049552 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5552 23:24:17.053286 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5553 23:24:17.056411 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5554 23:24:17.059775 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5555 23:24:17.063197 iDelay=199, Bit 13, Center 90 (3 ~ 178) 176
5556 23:24:17.070296 iDelay=199, Bit 14, Center 94 (7 ~ 182) 176
5557 23:24:17.073381 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5558 23:24:17.073463 ==
5559 23:24:17.076443 Dram Type= 6, Freq= 0, CH_0, rank 1
5560 23:24:17.079950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 23:24:17.080070 ==
5562 23:24:17.083730 DQS Delay:
5563 23:24:17.083822 DQS0 = 0, DQS1 = 0
5564 23:24:17.083893 DQM Delay:
5565 23:24:17.086623 DQM0 = 95, DQM1 = 86
5566 23:24:17.086738 DQ Delay:
5567 23:24:17.090037 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5568 23:24:17.093405 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =104
5569 23:24:17.097057 DQ8 =82, DQ9 =80, DQ10 =88, DQ11 =78
5570 23:24:17.100018 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5571 23:24:17.100123
5572 23:24:17.100271
5573 23:24:17.110068 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5574 23:24:17.110242 CH0 RK1: MR19=505, MR18=1B0A
5575 23:24:17.116690 CH0_RK1: MR19=0x505, MR18=0x1B0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5576 23:24:17.120147 [RxdqsGatingPostProcess] freq 933
5577 23:24:17.126728 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5578 23:24:17.130285 best DQS0 dly(2T, 0.5T) = (0, 10)
5579 23:24:17.133408 best DQS1 dly(2T, 0.5T) = (0, 11)
5580 23:24:17.136573 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5581 23:24:17.140193 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5582 23:24:17.140276 best DQS0 dly(2T, 0.5T) = (0, 10)
5583 23:24:17.143431 best DQS1 dly(2T, 0.5T) = (0, 11)
5584 23:24:17.146764 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5585 23:24:17.150155 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5586 23:24:17.153758 Pre-setting of DQS Precalculation
5587 23:24:17.159769 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5588 23:24:17.159886 ==
5589 23:24:17.163270 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 23:24:17.166585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 23:24:17.166664 ==
5592 23:24:17.172958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5593 23:24:17.180040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5594 23:24:17.182972 [CA 0] Center 36 (6~67) winsize 62
5595 23:24:17.186626 [CA 1] Center 36 (6~67) winsize 62
5596 23:24:17.189739 [CA 2] Center 34 (4~64) winsize 61
5597 23:24:17.193168 [CA 3] Center 33 (3~64) winsize 62
5598 23:24:17.196560 [CA 4] Center 34 (4~65) winsize 62
5599 23:24:17.199985 [CA 5] Center 33 (3~63) winsize 61
5600 23:24:17.200092
5601 23:24:17.203086 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5602 23:24:17.203168
5603 23:24:17.206308 [CATrainingPosCal] consider 1 rank data
5604 23:24:17.209899 u2DelayCellTimex100 = 270/100 ps
5605 23:24:17.212846 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5606 23:24:17.216015 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5607 23:24:17.219483 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5608 23:24:17.222750 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5609 23:24:17.226212 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5610 23:24:17.229816 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5611 23:24:17.229936
5612 23:24:17.233078 CA PerBit enable=1, Macro0, CA PI delay=33
5613 23:24:17.233188
5614 23:24:17.236786 [CBTSetCACLKResult] CA Dly = 33
5615 23:24:17.239588 CS Dly: 4 (0~35)
5616 23:24:17.239691 ==
5617 23:24:17.243334 Dram Type= 6, Freq= 0, CH_1, rank 1
5618 23:24:17.246638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 23:24:17.246721 ==
5620 23:24:17.252926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5621 23:24:17.259802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5622 23:24:17.263319 [CA 0] Center 36 (6~67) winsize 62
5623 23:24:17.266103 [CA 1] Center 36 (6~67) winsize 62
5624 23:24:17.269609 [CA 2] Center 33 (3~64) winsize 62
5625 23:24:17.273224 [CA 3] Center 33 (3~64) winsize 62
5626 23:24:17.276947 [CA 4] Center 33 (3~64) winsize 62
5627 23:24:17.279395 [CA 5] Center 33 (2~64) winsize 63
5628 23:24:17.279477
5629 23:24:17.283337 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5630 23:24:17.283418
5631 23:24:17.286646 [CATrainingPosCal] consider 2 rank data
5632 23:24:17.289919 u2DelayCellTimex100 = 270/100 ps
5633 23:24:17.293152 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5634 23:24:17.296757 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5635 23:24:17.299759 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5636 23:24:17.303147 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5637 23:24:17.306292 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5638 23:24:17.309703 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5639 23:24:17.309785
5640 23:24:17.313326 CA PerBit enable=1, Macro0, CA PI delay=33
5641 23:24:17.313408
5642 23:24:17.316682 [CBTSetCACLKResult] CA Dly = 33
5643 23:24:17.319721 CS Dly: 5 (0~37)
5644 23:24:17.319802
5645 23:24:17.323205 ----->DramcWriteLeveling(PI) begin...
5646 23:24:17.323287 ==
5647 23:24:17.326294 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 23:24:17.330295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 23:24:17.330378 ==
5650 23:24:17.333720 Write leveling (Byte 0): 27 => 27
5651 23:24:17.336461 Write leveling (Byte 1): 27 => 27
5652 23:24:17.340139 DramcWriteLeveling(PI) end<-----
5653 23:24:17.340220
5654 23:24:17.340284 ==
5655 23:24:17.343793 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 23:24:17.346659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 23:24:17.346768 ==
5658 23:24:17.349838 [Gating] SW mode calibration
5659 23:24:17.356693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5660 23:24:17.363417 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5661 23:24:17.366948 0 14 0 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
5662 23:24:17.370120 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5663 23:24:17.376923 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 23:24:17.379682 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 23:24:17.383244 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 23:24:17.389939 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5667 23:24:17.393366 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5668 23:24:17.396807 0 14 28 | B1->B0 | 3131 3434 | 0 1 | (1 0) (1 0)
5669 23:24:17.403188 0 15 0 | B1->B0 | 2626 2b2b | 0 1 | (0 0) (1 0)
5670 23:24:17.406872 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5671 23:24:17.410202 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 23:24:17.416639 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 23:24:17.419960 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 23:24:17.423475 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5675 23:24:17.430137 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5676 23:24:17.433191 0 15 28 | B1->B0 | 2d2d 2c2c | 0 0 | (1 1) (0 0)
5677 23:24:17.437097 1 0 0 | B1->B0 | 4343 4444 | 0 0 | (0 0) (0 0)
5678 23:24:17.443501 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 23:24:17.446632 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 23:24:17.450295 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 23:24:17.453097 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 23:24:17.460257 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 23:24:17.463527 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 23:24:17.466604 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5685 23:24:17.473215 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5686 23:24:17.476821 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 23:24:17.479659 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 23:24:17.486458 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 23:24:17.489884 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 23:24:17.493312 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 23:24:17.500519 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 23:24:17.503110 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 23:24:17.506468 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 23:24:17.513543 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 23:24:17.516446 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 23:24:17.520076 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 23:24:17.526914 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 23:24:17.530070 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 23:24:17.533388 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 23:24:17.537087 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5701 23:24:17.543533 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5702 23:24:17.546935 Total UI for P1: 0, mck2ui 16
5703 23:24:17.550288 best dqsien dly found for B0: ( 1, 2, 28)
5704 23:24:17.553245 Total UI for P1: 0, mck2ui 16
5705 23:24:17.556918 best dqsien dly found for B1: ( 1, 2, 28)
5706 23:24:17.560062 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5707 23:24:17.563647 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5708 23:24:17.563729
5709 23:24:17.566682 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5710 23:24:17.570045 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5711 23:24:17.573258 [Gating] SW calibration Done
5712 23:24:17.573340 ==
5713 23:24:17.576855 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 23:24:17.580509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 23:24:17.580591 ==
5716 23:24:17.583540 RX Vref Scan: 0
5717 23:24:17.583626
5718 23:24:17.583690 RX Vref 0 -> 0, step: 1
5719 23:24:17.583751
5720 23:24:17.586867 RX Delay -80 -> 252, step: 8
5721 23:24:17.590054 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5722 23:24:17.597213 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5723 23:24:17.600147 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5724 23:24:17.603226 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5725 23:24:17.606608 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5726 23:24:17.610070 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5727 23:24:17.613370 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5728 23:24:17.620870 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5729 23:24:17.623522 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5730 23:24:17.626661 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5731 23:24:17.629941 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5732 23:24:17.633742 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5733 23:24:17.639921 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5734 23:24:17.643541 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5735 23:24:17.646982 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5736 23:24:17.650290 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5737 23:24:17.650387 ==
5738 23:24:17.653301 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 23:24:17.656626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 23:24:17.656723 ==
5741 23:24:17.659889 DQS Delay:
5742 23:24:17.659964 DQS0 = 0, DQS1 = 0
5743 23:24:17.663075 DQM Delay:
5744 23:24:17.663147 DQM0 = 95, DQM1 = 89
5745 23:24:17.663208 DQ Delay:
5746 23:24:17.666673 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =95
5747 23:24:17.670203 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5748 23:24:17.673494 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =87
5749 23:24:17.676646 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5750 23:24:17.676721
5751 23:24:17.679877
5752 23:24:17.679954 ==
5753 23:24:17.683172 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 23:24:17.686300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 23:24:17.686454 ==
5756 23:24:17.686555
5757 23:24:17.686644
5758 23:24:17.690008 TX Vref Scan disable
5759 23:24:17.690106 == TX Byte 0 ==
5760 23:24:17.696631 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5761 23:24:17.699968 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5762 23:24:17.700046 == TX Byte 1 ==
5763 23:24:17.706610 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5764 23:24:17.709581 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5765 23:24:17.709687 ==
5766 23:24:17.712902 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 23:24:17.716680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 23:24:17.716781 ==
5769 23:24:17.716870
5770 23:24:17.716958
5771 23:24:17.719585 TX Vref Scan disable
5772 23:24:17.723024 == TX Byte 0 ==
5773 23:24:17.726471 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5774 23:24:17.730036 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5775 23:24:17.732988 == TX Byte 1 ==
5776 23:24:17.736522 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5777 23:24:17.739607 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5778 23:24:17.739680
5779 23:24:17.743330 [DATLAT]
5780 23:24:17.743407 Freq=933, CH1 RK0
5781 23:24:17.743470
5782 23:24:17.746599 DATLAT Default: 0xd
5783 23:24:17.746702 0, 0xFFFF, sum = 0
5784 23:24:17.750207 1, 0xFFFF, sum = 0
5785 23:24:17.750305 2, 0xFFFF, sum = 0
5786 23:24:17.752932 3, 0xFFFF, sum = 0
5787 23:24:17.753035 4, 0xFFFF, sum = 0
5788 23:24:17.756505 5, 0xFFFF, sum = 0
5789 23:24:17.756577 6, 0xFFFF, sum = 0
5790 23:24:17.759739 7, 0xFFFF, sum = 0
5791 23:24:17.759830 8, 0xFFFF, sum = 0
5792 23:24:17.763202 9, 0xFFFF, sum = 0
5793 23:24:17.763300 10, 0x0, sum = 1
5794 23:24:17.766323 11, 0x0, sum = 2
5795 23:24:17.766453 12, 0x0, sum = 3
5796 23:24:17.769927 13, 0x0, sum = 4
5797 23:24:17.770026 best_step = 11
5798 23:24:17.770125
5799 23:24:17.770213 ==
5800 23:24:17.773096 Dram Type= 6, Freq= 0, CH_1, rank 0
5801 23:24:17.776745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 23:24:17.776822 ==
5803 23:24:17.780363 RX Vref Scan: 1
5804 23:24:17.780453
5805 23:24:17.783627 RX Vref 0 -> 0, step: 1
5806 23:24:17.783698
5807 23:24:17.783759 RX Delay -61 -> 252, step: 4
5808 23:24:17.783828
5809 23:24:17.786295 Set Vref, RX VrefLevel [Byte0]: 56
5810 23:24:17.789780 [Byte1]: 54
5811 23:24:17.794975
5812 23:24:17.795058 Final RX Vref Byte 0 = 56 to rank0
5813 23:24:17.798032 Final RX Vref Byte 1 = 54 to rank0
5814 23:24:17.801370 Final RX Vref Byte 0 = 56 to rank1
5815 23:24:17.804525 Final RX Vref Byte 1 = 54 to rank1==
5816 23:24:17.808385 Dram Type= 6, Freq= 0, CH_1, rank 0
5817 23:24:17.815046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 23:24:17.815149 ==
5819 23:24:17.815251 DQS Delay:
5820 23:24:17.815340 DQS0 = 0, DQS1 = 0
5821 23:24:17.817982 DQM Delay:
5822 23:24:17.818077 DQM0 = 98, DQM1 = 90
5823 23:24:17.821322 DQ Delay:
5824 23:24:17.824940 DQ0 =100, DQ1 =90, DQ2 =88, DQ3 =98
5825 23:24:17.828110 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =94
5826 23:24:17.832167 DQ8 =82, DQ9 =82, DQ10 =90, DQ11 =86
5827 23:24:17.834932 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =94
5828 23:24:17.835037
5829 23:24:17.835126
5830 23:24:17.841562 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ef, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5831 23:24:17.844804 CH1 RK0: MR19=504, MR18=13EF
5832 23:24:17.851156 CH1_RK0: MR19=0x504, MR18=0x13EF, DQSOSC=415, MR23=63, INC=62, DEC=41
5833 23:24:17.851238
5834 23:24:17.854653 ----->DramcWriteLeveling(PI) begin...
5835 23:24:17.854730 ==
5836 23:24:17.857813 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 23:24:17.861179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 23:24:17.861277 ==
5839 23:24:17.864669 Write leveling (Byte 0): 26 => 26
5840 23:24:17.868207 Write leveling (Byte 1): 28 => 28
5841 23:24:17.871458 DramcWriteLeveling(PI) end<-----
5842 23:24:17.871555
5843 23:24:17.871654 ==
5844 23:24:17.874604 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 23:24:17.877905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 23:24:17.878013 ==
5847 23:24:17.881222 [Gating] SW mode calibration
5848 23:24:17.888355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5849 23:24:17.895217 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5850 23:24:17.898485 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5851 23:24:17.901351 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5852 23:24:17.908118 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5853 23:24:17.911460 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 23:24:17.914671 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 23:24:17.921527 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5856 23:24:17.924661 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
5857 23:24:17.928037 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
5858 23:24:17.934613 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5859 23:24:17.938291 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5860 23:24:17.941058 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5861 23:24:17.947792 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 23:24:17.951608 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 23:24:17.954805 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 23:24:17.961364 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5865 23:24:17.964675 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5866 23:24:17.968191 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 23:24:17.974470 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 23:24:17.977996 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 23:24:17.981502 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 23:24:17.987978 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 23:24:17.991047 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 23:24:17.994465 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5873 23:24:17.997824 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 23:24:18.004336 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 23:24:18.007937 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 23:24:18.011366 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 23:24:18.018136 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 23:24:18.021275 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 23:24:18.024548 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 23:24:18.031187 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 23:24:18.034749 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 23:24:18.038097 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 23:24:18.044323 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 23:24:18.048110 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 23:24:18.050863 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 23:24:18.057897 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 23:24:18.061051 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5888 23:24:18.064181 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 23:24:18.071045 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5890 23:24:18.071128 Total UI for P1: 0, mck2ui 16
5891 23:24:18.077791 best dqsien dly found for B0: ( 1, 2, 26)
5892 23:24:18.081230 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5893 23:24:18.084805 Total UI for P1: 0, mck2ui 16
5894 23:24:18.088119 best dqsien dly found for B1: ( 1, 2, 28)
5895 23:24:18.090894 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5896 23:24:18.094129 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5897 23:24:18.094233
5898 23:24:18.097893 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5899 23:24:18.101345 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5900 23:24:18.104714 [Gating] SW calibration Done
5901 23:24:18.104823 ==
5902 23:24:18.107870 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 23:24:18.111650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 23:24:18.111731 ==
5905 23:24:18.114231 RX Vref Scan: 0
5906 23:24:18.114316
5907 23:24:18.117965 RX Vref 0 -> 0, step: 1
5908 23:24:18.118045
5909 23:24:18.118109 RX Delay -80 -> 252, step: 8
5910 23:24:18.124303 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5911 23:24:18.128000 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5912 23:24:18.130902 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5913 23:24:18.134453 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5914 23:24:18.137846 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5915 23:24:18.141074 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5916 23:24:18.148070 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5917 23:24:18.151227 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5918 23:24:18.154232 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5919 23:24:18.157584 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5920 23:24:18.160761 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5921 23:24:18.164254 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5922 23:24:18.171670 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5923 23:24:18.174161 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5924 23:24:18.177342 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5925 23:24:18.180816 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5926 23:24:18.180923 ==
5927 23:24:18.184106 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 23:24:18.187673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 23:24:18.191008 ==
5930 23:24:18.191129 DQS Delay:
5931 23:24:18.191196 DQS0 = 0, DQS1 = 0
5932 23:24:18.194738 DQM Delay:
5933 23:24:18.194819 DQM0 = 94, DQM1 = 90
5934 23:24:18.197466 DQ Delay:
5935 23:24:18.197546 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =95
5936 23:24:18.200725 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5937 23:24:18.204466 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5938 23:24:18.207721 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5939 23:24:18.207803
5940 23:24:18.210808
5941 23:24:18.210888 ==
5942 23:24:18.214251 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 23:24:18.218126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 23:24:18.218209 ==
5945 23:24:18.218273
5946 23:24:18.218336
5947 23:24:18.220871 TX Vref Scan disable
5948 23:24:18.220952 == TX Byte 0 ==
5949 23:24:18.227575 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5950 23:24:18.231159 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5951 23:24:18.231258 == TX Byte 1 ==
5952 23:24:18.237644 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5953 23:24:18.240955 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5954 23:24:18.241044 ==
5955 23:24:18.244488 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 23:24:18.247389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 23:24:18.247466 ==
5958 23:24:18.247533
5959 23:24:18.247599
5960 23:24:18.250939 TX Vref Scan disable
5961 23:24:18.254591 == TX Byte 0 ==
5962 23:24:18.257922 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5963 23:24:18.261743 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5964 23:24:18.264199 == TX Byte 1 ==
5965 23:24:18.267834 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5966 23:24:18.271278 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5967 23:24:18.271357
5968 23:24:18.271469 [DATLAT]
5969 23:24:18.274446 Freq=933, CH1 RK1
5970 23:24:18.274523
5971 23:24:18.277752 DATLAT Default: 0xb
5972 23:24:18.277841 0, 0xFFFF, sum = 0
5973 23:24:18.281614 1, 0xFFFF, sum = 0
5974 23:24:18.281702 2, 0xFFFF, sum = 0
5975 23:24:18.284338 3, 0xFFFF, sum = 0
5976 23:24:18.284412 4, 0xFFFF, sum = 0
5977 23:24:18.287756 5, 0xFFFF, sum = 0
5978 23:24:18.287841 6, 0xFFFF, sum = 0
5979 23:24:18.291275 7, 0xFFFF, sum = 0
5980 23:24:18.291350 8, 0xFFFF, sum = 0
5981 23:24:18.294643 9, 0xFFFF, sum = 0
5982 23:24:18.294736 10, 0x0, sum = 1
5983 23:24:18.298059 11, 0x0, sum = 2
5984 23:24:18.298166 12, 0x0, sum = 3
5985 23:24:18.301498 13, 0x0, sum = 4
5986 23:24:18.301574 best_step = 11
5987 23:24:18.301636
5988 23:24:18.301701 ==
5989 23:24:18.304599 Dram Type= 6, Freq= 0, CH_1, rank 1
5990 23:24:18.307960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5991 23:24:18.308035 ==
5992 23:24:18.311687 RX Vref Scan: 0
5993 23:24:18.311762
5994 23:24:18.314687 RX Vref 0 -> 0, step: 1
5995 23:24:18.314756
5996 23:24:18.314816 RX Delay -61 -> 252, step: 4
5997 23:24:18.322354 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5998 23:24:18.325563 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5999 23:24:18.328899 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
6000 23:24:18.332190 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
6001 23:24:18.335506 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
6002 23:24:18.338680 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
6003 23:24:18.345608 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
6004 23:24:18.348764 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
6005 23:24:18.352450 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
6006 23:24:18.355421 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
6007 23:24:18.358946 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
6008 23:24:18.366140 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
6009 23:24:18.369164 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
6010 23:24:18.372105 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
6011 23:24:18.375841 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
6012 23:24:18.378974 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
6013 23:24:18.379047 ==
6014 23:24:18.382276 Dram Type= 6, Freq= 0, CH_1, rank 1
6015 23:24:18.389082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6016 23:24:18.389161 ==
6017 23:24:18.389231 DQS Delay:
6018 23:24:18.392300 DQS0 = 0, DQS1 = 0
6019 23:24:18.392372 DQM Delay:
6020 23:24:18.392441 DQM0 = 95, DQM1 = 91
6021 23:24:18.395669 DQ Delay:
6022 23:24:18.398949 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
6023 23:24:18.402326 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =90
6024 23:24:18.405712 DQ8 =80, DQ9 =78, DQ10 =94, DQ11 =84
6025 23:24:18.409115 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
6026 23:24:18.409187
6027 23:24:18.409254
6028 23:24:18.416044 [DQSOSCAuto] RK1, (LSB)MR18= 0xe18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
6029 23:24:18.419220 CH1 RK1: MR19=505, MR18=E18
6030 23:24:18.425623 CH1_RK1: MR19=0x505, MR18=0xE18, DQSOSC=414, MR23=63, INC=63, DEC=42
6031 23:24:18.428893 [RxdqsGatingPostProcess] freq 933
6032 23:24:18.432407 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6033 23:24:18.435706 best DQS0 dly(2T, 0.5T) = (0, 10)
6034 23:24:18.439035 best DQS1 dly(2T, 0.5T) = (0, 10)
6035 23:24:18.442514 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6036 23:24:18.445871 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6037 23:24:18.449238 best DQS0 dly(2T, 0.5T) = (0, 10)
6038 23:24:18.452828 best DQS1 dly(2T, 0.5T) = (0, 10)
6039 23:24:18.455670 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6040 23:24:18.459428 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6041 23:24:18.462756 Pre-setting of DQS Precalculation
6042 23:24:18.465728 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6043 23:24:18.472899 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6044 23:24:18.482582 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6045 23:24:18.482666
6046 23:24:18.482730
6047 23:24:18.485758 [Calibration Summary] 1866 Mbps
6048 23:24:18.485835 CH 0, Rank 0
6049 23:24:18.489304 SW Impedance : PASS
6050 23:24:18.489383 DUTY Scan : NO K
6051 23:24:18.492572 ZQ Calibration : PASS
6052 23:24:18.495784 Jitter Meter : NO K
6053 23:24:18.495867 CBT Training : PASS
6054 23:24:18.499424 Write leveling : PASS
6055 23:24:18.499494 RX DQS gating : PASS
6056 23:24:18.502646 RX DQ/DQS(RDDQC) : PASS
6057 23:24:18.506174 TX DQ/DQS : PASS
6058 23:24:18.506247 RX DATLAT : PASS
6059 23:24:18.508916 RX DQ/DQS(Engine): PASS
6060 23:24:18.512550 TX OE : NO K
6061 23:24:18.512624 All Pass.
6062 23:24:18.512684
6063 23:24:18.512749 CH 0, Rank 1
6064 23:24:18.515781 SW Impedance : PASS
6065 23:24:18.519227 DUTY Scan : NO K
6066 23:24:18.519301 ZQ Calibration : PASS
6067 23:24:18.522869 Jitter Meter : NO K
6068 23:24:18.526037 CBT Training : PASS
6069 23:24:18.526110 Write leveling : PASS
6070 23:24:18.529133 RX DQS gating : PASS
6071 23:24:18.532274 RX DQ/DQS(RDDQC) : PASS
6072 23:24:18.532347 TX DQ/DQS : PASS
6073 23:24:18.536138 RX DATLAT : PASS
6074 23:24:18.536212 RX DQ/DQS(Engine): PASS
6075 23:24:18.538986 TX OE : NO K
6076 23:24:18.539065 All Pass.
6077 23:24:18.539126
6078 23:24:18.542365 CH 1, Rank 0
6079 23:24:18.542489 SW Impedance : PASS
6080 23:24:18.545637 DUTY Scan : NO K
6081 23:24:18.549317 ZQ Calibration : PASS
6082 23:24:18.549391 Jitter Meter : NO K
6083 23:24:18.552591 CBT Training : PASS
6084 23:24:18.555985 Write leveling : PASS
6085 23:24:18.556056 RX DQS gating : PASS
6086 23:24:18.559057 RX DQ/DQS(RDDQC) : PASS
6087 23:24:18.562692 TX DQ/DQS : PASS
6088 23:24:18.562771 RX DATLAT : PASS
6089 23:24:18.566264 RX DQ/DQS(Engine): PASS
6090 23:24:18.569138 TX OE : NO K
6091 23:24:18.569209 All Pass.
6092 23:24:18.569270
6093 23:24:18.569327 CH 1, Rank 1
6094 23:24:18.573023 SW Impedance : PASS
6095 23:24:18.575698 DUTY Scan : NO K
6096 23:24:18.575772 ZQ Calibration : PASS
6097 23:24:18.579656 Jitter Meter : NO K
6098 23:24:18.579728 CBT Training : PASS
6099 23:24:18.582628 Write leveling : PASS
6100 23:24:18.585975 RX DQS gating : PASS
6101 23:24:18.586044 RX DQ/DQS(RDDQC) : PASS
6102 23:24:18.589496 TX DQ/DQS : PASS
6103 23:24:18.592757 RX DATLAT : PASS
6104 23:24:18.592834 RX DQ/DQS(Engine): PASS
6105 23:24:18.595845 TX OE : NO K
6106 23:24:18.595915 All Pass.
6107 23:24:18.595975
6108 23:24:18.599678 DramC Write-DBI off
6109 23:24:18.602591 PER_BANK_REFRESH: Hybrid Mode
6110 23:24:18.602668 TX_TRACKING: ON
6111 23:24:18.612481 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6112 23:24:18.615986 [FAST_K] Save calibration result to emmc
6113 23:24:18.619536 dramc_set_vcore_voltage set vcore to 650000
6114 23:24:18.622417 Read voltage for 400, 6
6115 23:24:18.622487 Vio18 = 0
6116 23:24:18.622552 Vcore = 650000
6117 23:24:18.625773 Vdram = 0
6118 23:24:18.625841 Vddq = 0
6119 23:24:18.625902 Vmddr = 0
6120 23:24:18.632608 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6121 23:24:18.635852 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6122 23:24:18.639272 MEM_TYPE=3, freq_sel=20
6123 23:24:18.643024 sv_algorithm_assistance_LP4_800
6124 23:24:18.646131 ============ PULL DRAM RESETB DOWN ============
6125 23:24:18.649502 ========== PULL DRAM RESETB DOWN end =========
6126 23:24:18.656375 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6127 23:24:18.659398 ===================================
6128 23:24:18.659480 LPDDR4 DRAM CONFIGURATION
6129 23:24:18.663087 ===================================
6130 23:24:18.666110 EX_ROW_EN[0] = 0x0
6131 23:24:18.669525 EX_ROW_EN[1] = 0x0
6132 23:24:18.669609 LP4Y_EN = 0x0
6133 23:24:18.672831 WORK_FSP = 0x0
6134 23:24:18.672912 WL = 0x2
6135 23:24:18.676158 RL = 0x2
6136 23:24:18.676239 BL = 0x2
6137 23:24:18.679454 RPST = 0x0
6138 23:24:18.679534 RD_PRE = 0x0
6139 23:24:18.682775 WR_PRE = 0x1
6140 23:24:18.682861 WR_PST = 0x0
6141 23:24:18.686079 DBI_WR = 0x0
6142 23:24:18.686159 DBI_RD = 0x0
6143 23:24:18.689953 OTF = 0x1
6144 23:24:18.692559 ===================================
6145 23:24:18.696402 ===================================
6146 23:24:18.696513 ANA top config
6147 23:24:18.699430 ===================================
6148 23:24:18.702415 DLL_ASYNC_EN = 0
6149 23:24:18.706022 ALL_SLAVE_EN = 1
6150 23:24:18.709413 NEW_RANK_MODE = 1
6151 23:24:18.709495 DLL_IDLE_MODE = 1
6152 23:24:18.712598 LP45_APHY_COMB_EN = 1
6153 23:24:18.716168 TX_ODT_DIS = 1
6154 23:24:18.719110 NEW_8X_MODE = 1
6155 23:24:18.723108 ===================================
6156 23:24:18.726042 ===================================
6157 23:24:18.726115 data_rate = 800
6158 23:24:18.729461 CKR = 1
6159 23:24:18.732649 DQ_P2S_RATIO = 4
6160 23:24:18.736151 ===================================
6161 23:24:18.739470 CA_P2S_RATIO = 4
6162 23:24:18.742388 DQ_CA_OPEN = 0
6163 23:24:18.746175 DQ_SEMI_OPEN = 1
6164 23:24:18.746250 CA_SEMI_OPEN = 1
6165 23:24:18.749223 CA_FULL_RATE = 0
6166 23:24:18.752473 DQ_CKDIV4_EN = 0
6167 23:24:18.755994 CA_CKDIV4_EN = 1
6168 23:24:18.759465 CA_PREDIV_EN = 0
6169 23:24:18.762708 PH8_DLY = 0
6170 23:24:18.762781 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6171 23:24:18.765635 DQ_AAMCK_DIV = 0
6172 23:24:18.769543 CA_AAMCK_DIV = 0
6173 23:24:18.772342 CA_ADMCK_DIV = 4
6174 23:24:18.776173 DQ_TRACK_CA_EN = 0
6175 23:24:18.779268 CA_PICK = 800
6176 23:24:18.779347 CA_MCKIO = 400
6177 23:24:18.782306 MCKIO_SEMI = 400
6178 23:24:18.785927 PLL_FREQ = 3016
6179 23:24:18.789209 DQ_UI_PI_RATIO = 32
6180 23:24:18.792612 CA_UI_PI_RATIO = 32
6181 23:24:18.795862 ===================================
6182 23:24:18.799102 ===================================
6183 23:24:18.802464 memory_type:LPDDR4
6184 23:24:18.802545 GP_NUM : 10
6185 23:24:18.805910 SRAM_EN : 1
6186 23:24:18.809352 MD32_EN : 0
6187 23:24:18.812463 ===================================
6188 23:24:18.812544 [ANA_INIT] >>>>>>>>>>>>>>
6189 23:24:18.815765 <<<<<< [CONFIGURE PHASE]: ANA_TX
6190 23:24:18.819158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6191 23:24:18.822475 ===================================
6192 23:24:18.825543 data_rate = 800,PCW = 0X7400
6193 23:24:18.828911 ===================================
6194 23:24:18.832572 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6195 23:24:18.839294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6196 23:24:18.848867 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6197 23:24:18.852746 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6198 23:24:18.855620 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6199 23:24:18.858855 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6200 23:24:18.862453 [ANA_INIT] flow start
6201 23:24:18.865673 [ANA_INIT] PLL >>>>>>>>
6202 23:24:18.865748 [ANA_INIT] PLL <<<<<<<<
6203 23:24:18.868787 [ANA_INIT] MIDPI >>>>>>>>
6204 23:24:18.872396 [ANA_INIT] MIDPI <<<<<<<<
6205 23:24:18.875684 [ANA_INIT] DLL >>>>>>>>
6206 23:24:18.875757 [ANA_INIT] flow end
6207 23:24:18.878968 ============ LP4 DIFF to SE enter ============
6208 23:24:18.885396 ============ LP4 DIFF to SE exit ============
6209 23:24:18.885473 [ANA_INIT] <<<<<<<<<<<<<
6210 23:24:18.889170 [Flow] Enable top DCM control >>>>>
6211 23:24:18.892130 [Flow] Enable top DCM control <<<<<
6212 23:24:18.895964 Enable DLL master slave shuffle
6213 23:24:18.902301 ==============================================================
6214 23:24:18.902447 Gating Mode config
6215 23:24:18.909058 ==============================================================
6216 23:24:18.912421 Config description:
6217 23:24:18.919200 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6218 23:24:18.925667 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6219 23:24:18.932805 SELPH_MODE 0: By rank 1: By Phase
6220 23:24:18.938887 ==============================================================
6221 23:24:18.938970 GAT_TRACK_EN = 0
6222 23:24:18.942236 RX_GATING_MODE = 2
6223 23:24:18.945668 RX_GATING_TRACK_MODE = 2
6224 23:24:18.949193 SELPH_MODE = 1
6225 23:24:18.952543 PICG_EARLY_EN = 1
6226 23:24:18.955715 VALID_LAT_VALUE = 1
6227 23:24:18.962581 ==============================================================
6228 23:24:18.965647 Enter into Gating configuration >>>>
6229 23:24:18.969093 Exit from Gating configuration <<<<
6230 23:24:18.972273 Enter into DVFS_PRE_config >>>>>
6231 23:24:18.982386 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6232 23:24:18.985839 Exit from DVFS_PRE_config <<<<<
6233 23:24:18.989196 Enter into PICG configuration >>>>
6234 23:24:18.992141 Exit from PICG configuration <<<<
6235 23:24:18.995571 [RX_INPUT] configuration >>>>>
6236 23:24:18.995651 [RX_INPUT] configuration <<<<<
6237 23:24:19.002272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6238 23:24:19.009001 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6239 23:24:19.012082 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6240 23:24:19.019085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6241 23:24:19.026181 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6242 23:24:19.032623 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6243 23:24:19.035471 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6244 23:24:19.039184 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6245 23:24:19.045586 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6246 23:24:19.048993 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6247 23:24:19.051929 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6248 23:24:19.058801 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6249 23:24:19.058882 ===================================
6250 23:24:19.062155 LPDDR4 DRAM CONFIGURATION
6251 23:24:19.065173 ===================================
6252 23:24:19.068917 EX_ROW_EN[0] = 0x0
6253 23:24:19.069026 EX_ROW_EN[1] = 0x0
6254 23:24:19.072586 LP4Y_EN = 0x0
6255 23:24:19.072668 WORK_FSP = 0x0
6256 23:24:19.075376 WL = 0x2
6257 23:24:19.075458 RL = 0x2
6258 23:24:19.078774 BL = 0x2
6259 23:24:19.078855 RPST = 0x0
6260 23:24:19.082299 RD_PRE = 0x0
6261 23:24:19.085608 WR_PRE = 0x1
6262 23:24:19.085689 WR_PST = 0x0
6263 23:24:19.088905 DBI_WR = 0x0
6264 23:24:19.089011 DBI_RD = 0x0
6265 23:24:19.092301 OTF = 0x1
6266 23:24:19.095803 ===================================
6267 23:24:19.098743 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6268 23:24:19.102111 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6269 23:24:19.105552 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6270 23:24:19.108836 ===================================
6271 23:24:19.112381 LPDDR4 DRAM CONFIGURATION
6272 23:24:19.115678 ===================================
6273 23:24:19.118988 EX_ROW_EN[0] = 0x10
6274 23:24:19.119069 EX_ROW_EN[1] = 0x0
6275 23:24:19.122029 LP4Y_EN = 0x0
6276 23:24:19.122110 WORK_FSP = 0x0
6277 23:24:19.125319 WL = 0x2
6278 23:24:19.125438 RL = 0x2
6279 23:24:19.128785 BL = 0x2
6280 23:24:19.128866 RPST = 0x0
6281 23:24:19.131805 RD_PRE = 0x0
6282 23:24:19.131886 WR_PRE = 0x1
6283 23:24:19.135339 WR_PST = 0x0
6284 23:24:19.135420 DBI_WR = 0x0
6285 23:24:19.138591 DBI_RD = 0x0
6286 23:24:19.138671 OTF = 0x1
6287 23:24:19.141870 ===================================
6288 23:24:19.149122 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6289 23:24:19.153661 nWR fixed to 30
6290 23:24:19.156893 [ModeRegInit_LP4] CH0 RK0
6291 23:24:19.157000 [ModeRegInit_LP4] CH0 RK1
6292 23:24:19.160408 [ModeRegInit_LP4] CH1 RK0
6293 23:24:19.163775 [ModeRegInit_LP4] CH1 RK1
6294 23:24:19.163857 match AC timing 19
6295 23:24:19.170549 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6296 23:24:19.173371 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6297 23:24:19.177176 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6298 23:24:19.183835 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6299 23:24:19.186748 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6300 23:24:19.186831 ==
6301 23:24:19.190125 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 23:24:19.193292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 23:24:19.193374 ==
6304 23:24:19.200323 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6305 23:24:19.207127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6306 23:24:19.210333 [CA 0] Center 36 (8~64) winsize 57
6307 23:24:19.213238 [CA 1] Center 36 (8~64) winsize 57
6308 23:24:19.216806 [CA 2] Center 36 (8~64) winsize 57
6309 23:24:19.216888 [CA 3] Center 36 (8~64) winsize 57
6310 23:24:19.220222 [CA 4] Center 36 (8~64) winsize 57
6311 23:24:19.223471 [CA 5] Center 36 (8~64) winsize 57
6312 23:24:19.223570
6313 23:24:19.226934 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6314 23:24:19.230127
6315 23:24:19.233468 [CATrainingPosCal] consider 1 rank data
6316 23:24:19.233549 u2DelayCellTimex100 = 270/100 ps
6317 23:24:19.240358 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 23:24:19.243618 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 23:24:19.246744 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 23:24:19.250056 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 23:24:19.253710 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 23:24:19.257162 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 23:24:19.257243
6324 23:24:19.260040 CA PerBit enable=1, Macro0, CA PI delay=36
6325 23:24:19.260121
6326 23:24:19.263412 [CBTSetCACLKResult] CA Dly = 36
6327 23:24:19.266755 CS Dly: 1 (0~32)
6328 23:24:19.266837 ==
6329 23:24:19.270299 Dram Type= 6, Freq= 0, CH_0, rank 1
6330 23:24:19.273714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 23:24:19.273800 ==
6332 23:24:19.280072 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6333 23:24:19.283460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6334 23:24:19.286879 [CA 0] Center 36 (8~64) winsize 57
6335 23:24:19.290199 [CA 1] Center 36 (8~64) winsize 57
6336 23:24:19.293435 [CA 2] Center 36 (8~64) winsize 57
6337 23:24:19.296872 [CA 3] Center 36 (8~64) winsize 57
6338 23:24:19.299928 [CA 4] Center 36 (8~64) winsize 57
6339 23:24:19.303456 [CA 5] Center 36 (8~64) winsize 57
6340 23:24:19.303538
6341 23:24:19.306859 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6342 23:24:19.306940
6343 23:24:19.310099 [CATrainingPosCal] consider 2 rank data
6344 23:24:19.313808 u2DelayCellTimex100 = 270/100 ps
6345 23:24:19.316616 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 23:24:19.320436 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 23:24:19.323744 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 23:24:19.327231 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 23:24:19.330214 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 23:24:19.336658 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 23:24:19.336739
6352 23:24:19.340124 CA PerBit enable=1, Macro0, CA PI delay=36
6353 23:24:19.340256
6354 23:24:19.343615 [CBTSetCACLKResult] CA Dly = 36
6355 23:24:19.343696 CS Dly: 1 (0~32)
6356 23:24:19.343760
6357 23:24:19.346570 ----->DramcWriteLeveling(PI) begin...
6358 23:24:19.346653 ==
6359 23:24:19.350247 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 23:24:19.356841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 23:24:19.356924 ==
6362 23:24:19.356988 Write leveling (Byte 0): 40 => 8
6363 23:24:19.360362 Write leveling (Byte 1): 32 => 0
6364 23:24:19.363364 DramcWriteLeveling(PI) end<-----
6365 23:24:19.363444
6366 23:24:19.363507 ==
6367 23:24:19.366977 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 23:24:19.373765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 23:24:19.373857 ==
6370 23:24:19.376551 [Gating] SW mode calibration
6371 23:24:19.383387 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6372 23:24:19.386720 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6373 23:24:19.393304 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6374 23:24:19.396855 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6375 23:24:19.400044 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6376 23:24:19.403278 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6377 23:24:19.410328 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6378 23:24:19.413165 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6379 23:24:19.416950 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 23:24:19.423515 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6381 23:24:19.426741 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6382 23:24:19.429931 Total UI for P1: 0, mck2ui 16
6383 23:24:19.433434 best dqsien dly found for B0: ( 0, 14, 24)
6384 23:24:19.436844 Total UI for P1: 0, mck2ui 16
6385 23:24:19.439998 best dqsien dly found for B1: ( 0, 14, 24)
6386 23:24:19.443485 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6387 23:24:19.446993 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6388 23:24:19.447069
6389 23:24:19.450246 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6390 23:24:19.453156 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6391 23:24:19.456777 [Gating] SW calibration Done
6392 23:24:19.456851 ==
6393 23:24:19.460148 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 23:24:19.466778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 23:24:19.466855 ==
6396 23:24:19.466918 RX Vref Scan: 0
6397 23:24:19.466981
6398 23:24:19.470362 RX Vref 0 -> 0, step: 1
6399 23:24:19.470482
6400 23:24:19.473677 RX Delay -410 -> 252, step: 16
6401 23:24:19.476761 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6402 23:24:19.479787 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6403 23:24:19.483323 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6404 23:24:19.489906 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6405 23:24:19.493329 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6406 23:24:19.496607 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6407 23:24:19.499654 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6408 23:24:19.506880 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6409 23:24:19.509760 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6410 23:24:19.513610 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6411 23:24:19.517024 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6412 23:24:19.523093 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6413 23:24:19.526288 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6414 23:24:19.529980 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6415 23:24:19.536313 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6416 23:24:19.540114 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6417 23:24:19.540192 ==
6418 23:24:19.543288 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 23:24:19.546555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 23:24:19.546639 ==
6421 23:24:19.550049 DQS Delay:
6422 23:24:19.550129 DQS0 = 35, DQS1 = 51
6423 23:24:19.550193 DQM Delay:
6424 23:24:19.553205 DQM0 = 7, DQM1 = 10
6425 23:24:19.553286 DQ Delay:
6426 23:24:19.556449 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6427 23:24:19.559732 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6428 23:24:19.563298 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6429 23:24:19.566811 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6430 23:24:19.566895
6431 23:24:19.566963
6432 23:24:19.567023 ==
6433 23:24:19.570249 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 23:24:19.572967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 23:24:19.573039 ==
6436 23:24:19.573101
6437 23:24:19.573166
6438 23:24:19.576436 TX Vref Scan disable
6439 23:24:19.580006 == TX Byte 0 ==
6440 23:24:19.583847 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6441 23:24:19.586270 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6442 23:24:19.590266 == TX Byte 1 ==
6443 23:24:19.593848 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6444 23:24:19.596542 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6445 23:24:19.596623 ==
6446 23:24:19.599815 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 23:24:19.603212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 23:24:19.603294 ==
6449 23:24:19.603357
6450 23:24:19.606841
6451 23:24:19.606947 TX Vref Scan disable
6452 23:24:19.610203 == TX Byte 0 ==
6453 23:24:19.613587 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6454 23:24:19.616365 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6455 23:24:19.619731 == TX Byte 1 ==
6456 23:24:19.622998 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6457 23:24:19.626567 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6458 23:24:19.626649
6459 23:24:19.626712 [DATLAT]
6460 23:24:19.629913 Freq=400, CH0 RK0
6461 23:24:19.629994
6462 23:24:19.632944 DATLAT Default: 0xf
6463 23:24:19.633024 0, 0xFFFF, sum = 0
6464 23:24:19.636359 1, 0xFFFF, sum = 0
6465 23:24:19.636441 2, 0xFFFF, sum = 0
6466 23:24:19.639827 3, 0xFFFF, sum = 0
6467 23:24:19.639909 4, 0xFFFF, sum = 0
6468 23:24:19.643137 5, 0xFFFF, sum = 0
6469 23:24:19.643219 6, 0xFFFF, sum = 0
6470 23:24:19.646962 7, 0xFFFF, sum = 0
6471 23:24:19.647045 8, 0xFFFF, sum = 0
6472 23:24:19.650059 9, 0xFFFF, sum = 0
6473 23:24:19.650140 10, 0xFFFF, sum = 0
6474 23:24:19.653556 11, 0xFFFF, sum = 0
6475 23:24:19.653637 12, 0xFFFF, sum = 0
6476 23:24:19.656557 13, 0x0, sum = 1
6477 23:24:19.656639 14, 0x0, sum = 2
6478 23:24:19.660155 15, 0x0, sum = 3
6479 23:24:19.660237 16, 0x0, sum = 4
6480 23:24:19.663291 best_step = 14
6481 23:24:19.663372
6482 23:24:19.663435 ==
6483 23:24:19.666744 Dram Type= 6, Freq= 0, CH_0, rank 0
6484 23:24:19.669747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 23:24:19.669829 ==
6486 23:24:19.669893 RX Vref Scan: 1
6487 23:24:19.673297
6488 23:24:19.673378 RX Vref 0 -> 0, step: 1
6489 23:24:19.673441
6490 23:24:19.676490 RX Delay -343 -> 252, step: 8
6491 23:24:19.676571
6492 23:24:19.680279 Set Vref, RX VrefLevel [Byte0]: 54
6493 23:24:19.683327 [Byte1]: 51
6494 23:24:19.687626
6495 23:24:19.687706 Final RX Vref Byte 0 = 54 to rank0
6496 23:24:19.690640 Final RX Vref Byte 1 = 51 to rank0
6497 23:24:19.693858 Final RX Vref Byte 0 = 54 to rank1
6498 23:24:19.697422 Final RX Vref Byte 1 = 51 to rank1==
6499 23:24:19.700910 Dram Type= 6, Freq= 0, CH_0, rank 0
6500 23:24:19.707344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 23:24:19.707425 ==
6502 23:24:19.707489 DQS Delay:
6503 23:24:19.710631 DQS0 = 44, DQS1 = 60
6504 23:24:19.710711 DQM Delay:
6505 23:24:19.710774 DQM0 = 11, DQM1 = 14
6506 23:24:19.713724 DQ Delay:
6507 23:24:19.717231 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6508 23:24:19.717312 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6509 23:24:19.720647 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6510 23:24:19.723919 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6511 23:24:19.724026
6512 23:24:19.724114
6513 23:24:19.734150 [DQSOSCAuto] RK0, (LSB)MR18= 0x8352, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6514 23:24:19.737451 CH0 RK0: MR19=C0C, MR18=8352
6515 23:24:19.744086 CH0_RK0: MR19=0xC0C, MR18=0x8352, DQSOSC=393, MR23=63, INC=382, DEC=254
6516 23:24:19.744189 ==
6517 23:24:19.747509 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 23:24:19.750651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 23:24:19.750732 ==
6520 23:24:19.753752 [Gating] SW mode calibration
6521 23:24:19.760629 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6522 23:24:19.763870 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6523 23:24:19.770545 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6524 23:24:19.773835 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6525 23:24:19.776761 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6526 23:24:19.783639 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6527 23:24:19.786947 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6528 23:24:19.790105 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6529 23:24:19.797163 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 23:24:19.800048 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 23:24:19.803832 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6532 23:24:19.806735 Total UI for P1: 0, mck2ui 16
6533 23:24:19.810663 best dqsien dly found for B0: ( 0, 14, 24)
6534 23:24:19.813574 Total UI for P1: 0, mck2ui 16
6535 23:24:19.816769 best dqsien dly found for B1: ( 0, 14, 24)
6536 23:24:19.820300 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6537 23:24:19.823706 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6538 23:24:19.827026
6539 23:24:19.830335 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6540 23:24:19.833809 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6541 23:24:19.837059 [Gating] SW calibration Done
6542 23:24:19.837139 ==
6543 23:24:19.840192 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 23:24:19.843552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 23:24:19.843634 ==
6546 23:24:19.843698 RX Vref Scan: 0
6547 23:24:19.843757
6548 23:24:19.846847 RX Vref 0 -> 0, step: 1
6549 23:24:19.846927
6550 23:24:19.850444 RX Delay -410 -> 252, step: 16
6551 23:24:19.853952 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6552 23:24:19.860256 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6553 23:24:19.863722 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6554 23:24:19.867291 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6555 23:24:19.870232 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6556 23:24:19.873496 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6557 23:24:19.880586 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6558 23:24:19.883761 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6559 23:24:19.887037 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6560 23:24:19.890421 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6561 23:24:19.896856 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6562 23:24:19.900695 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6563 23:24:19.903777 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6564 23:24:19.910542 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6565 23:24:19.913535 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6566 23:24:19.917162 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6567 23:24:19.917242 ==
6568 23:24:19.920312 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 23:24:19.923920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 23:24:19.923993 ==
6571 23:24:19.926842 DQS Delay:
6572 23:24:19.926912 DQS0 = 43, DQS1 = 51
6573 23:24:19.930348 DQM Delay:
6574 23:24:19.930453 DQM0 = 11, DQM1 = 10
6575 23:24:19.934237 DQ Delay:
6576 23:24:19.934338 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6577 23:24:19.936943 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6578 23:24:19.940954 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6579 23:24:19.943856 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6580 23:24:19.943931
6581 23:24:19.943998
6582 23:24:19.944056 ==
6583 23:24:19.946797 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 23:24:19.953599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 23:24:19.953682 ==
6586 23:24:19.953745
6587 23:24:19.953804
6588 23:24:19.953860 TX Vref Scan disable
6589 23:24:19.956913 == TX Byte 0 ==
6590 23:24:19.960316 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6591 23:24:19.963758 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6592 23:24:19.967182 == TX Byte 1 ==
6593 23:24:19.970200 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6594 23:24:19.974032 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6595 23:24:19.974117 ==
6596 23:24:19.977236 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 23:24:19.983503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 23:24:19.983581 ==
6599 23:24:19.983648
6600 23:24:19.983713
6601 23:24:19.983773 TX Vref Scan disable
6602 23:24:19.986863 == TX Byte 0 ==
6603 23:24:19.990569 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6604 23:24:19.993684 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6605 23:24:19.996977 == TX Byte 1 ==
6606 23:24:20.000181 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6607 23:24:20.003334 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6608 23:24:20.003430
6609 23:24:20.006874 [DATLAT]
6610 23:24:20.006948 Freq=400, CH0 RK1
6611 23:24:20.007011
6612 23:24:20.010216 DATLAT Default: 0xe
6613 23:24:20.010317 0, 0xFFFF, sum = 0
6614 23:24:20.013648 1, 0xFFFF, sum = 0
6615 23:24:20.013721 2, 0xFFFF, sum = 0
6616 23:24:20.017191 3, 0xFFFF, sum = 0
6617 23:24:20.017263 4, 0xFFFF, sum = 0
6618 23:24:20.020292 5, 0xFFFF, sum = 0
6619 23:24:20.020369 6, 0xFFFF, sum = 0
6620 23:24:20.023687 7, 0xFFFF, sum = 0
6621 23:24:20.023765 8, 0xFFFF, sum = 0
6622 23:24:20.026787 9, 0xFFFF, sum = 0
6623 23:24:20.026861 10, 0xFFFF, sum = 0
6624 23:24:20.030080 11, 0xFFFF, sum = 0
6625 23:24:20.030150 12, 0xFFFF, sum = 0
6626 23:24:20.033770 13, 0x0, sum = 1
6627 23:24:20.033848 14, 0x0, sum = 2
6628 23:24:20.037355 15, 0x0, sum = 3
6629 23:24:20.037428 16, 0x0, sum = 4
6630 23:24:20.040637 best_step = 14
6631 23:24:20.040717
6632 23:24:20.040777 ==
6633 23:24:20.043608 Dram Type= 6, Freq= 0, CH_0, rank 1
6634 23:24:20.047004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 23:24:20.047079 ==
6636 23:24:20.050650 RX Vref Scan: 0
6637 23:24:20.050722
6638 23:24:20.050783 RX Vref 0 -> 0, step: 1
6639 23:24:20.050851
6640 23:24:20.053482 RX Delay -343 -> 252, step: 8
6641 23:24:20.061389 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6642 23:24:20.064901 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6643 23:24:20.068378 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6644 23:24:20.074878 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6645 23:24:20.078111 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6646 23:24:20.081221 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6647 23:24:20.084491 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6648 23:24:20.088149 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6649 23:24:20.094639 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6650 23:24:20.097927 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6651 23:24:20.101353 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6652 23:24:20.104693 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6653 23:24:20.111103 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6654 23:24:20.114675 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6655 23:24:20.117841 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6656 23:24:20.124481 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6657 23:24:20.124560 ==
6658 23:24:20.127910 Dram Type= 6, Freq= 0, CH_0, rank 1
6659 23:24:20.131528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 23:24:20.131603 ==
6661 23:24:20.131665 DQS Delay:
6662 23:24:20.134588 DQS0 = 48, DQS1 = 60
6663 23:24:20.134653 DQM Delay:
6664 23:24:20.138089 DQM0 = 13, DQM1 = 13
6665 23:24:20.138169 DQ Delay:
6666 23:24:20.141417 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6667 23:24:20.144813 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6668 23:24:20.147970 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6669 23:24:20.151272 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6670 23:24:20.151357
6671 23:24:20.151422
6672 23:24:20.157861 [DQSOSCAuto] RK1, (LSB)MR18= 0x9164, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6673 23:24:20.161380 CH0 RK1: MR19=C0C, MR18=9164
6674 23:24:20.168220 CH0_RK1: MR19=0xC0C, MR18=0x9164, DQSOSC=391, MR23=63, INC=386, DEC=257
6675 23:24:20.171602 [RxdqsGatingPostProcess] freq 400
6676 23:24:20.178268 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6677 23:24:20.178371 best DQS0 dly(2T, 0.5T) = (0, 10)
6678 23:24:20.181694 best DQS1 dly(2T, 0.5T) = (0, 10)
6679 23:24:20.184427 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6680 23:24:20.187827 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6681 23:24:20.191382 best DQS0 dly(2T, 0.5T) = (0, 10)
6682 23:24:20.194990 best DQS1 dly(2T, 0.5T) = (0, 10)
6683 23:24:20.198023 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6684 23:24:20.201321 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6685 23:24:20.205076 Pre-setting of DQS Precalculation
6686 23:24:20.207822 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6687 23:24:20.211155 ==
6688 23:24:20.214546 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 23:24:20.218082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 23:24:20.218154 ==
6691 23:24:20.221335 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6692 23:24:20.228110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6693 23:24:20.231593 [CA 0] Center 36 (8~64) winsize 57
6694 23:24:20.234881 [CA 1] Center 36 (8~64) winsize 57
6695 23:24:20.237904 [CA 2] Center 36 (8~64) winsize 57
6696 23:24:20.241424 [CA 3] Center 36 (8~64) winsize 57
6697 23:24:20.244818 [CA 4] Center 36 (8~64) winsize 57
6698 23:24:20.248951 [CA 5] Center 36 (8~64) winsize 57
6699 23:24:20.249057
6700 23:24:20.251583 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6701 23:24:20.251664
6702 23:24:20.254841 [CATrainingPosCal] consider 1 rank data
6703 23:24:20.258577 u2DelayCellTimex100 = 270/100 ps
6704 23:24:20.261326 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 23:24:20.265358 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 23:24:20.268347 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 23:24:20.271619 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 23:24:20.275150 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 23:24:20.278301 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 23:24:20.278382
6711 23:24:20.285363 CA PerBit enable=1, Macro0, CA PI delay=36
6712 23:24:20.285443
6713 23:24:20.288387 [CBTSetCACLKResult] CA Dly = 36
6714 23:24:20.288544 CS Dly: 1 (0~32)
6715 23:24:20.288608 ==
6716 23:24:20.291710 Dram Type= 6, Freq= 0, CH_1, rank 1
6717 23:24:20.295252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 23:24:20.295334 ==
6719 23:24:20.301740 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6720 23:24:20.308153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6721 23:24:20.311645 [CA 0] Center 36 (8~64) winsize 57
6722 23:24:20.315025 [CA 1] Center 36 (8~64) winsize 57
6723 23:24:20.318526 [CA 2] Center 36 (8~64) winsize 57
6724 23:24:20.321399 [CA 3] Center 36 (8~64) winsize 57
6725 23:24:20.321479 [CA 4] Center 36 (8~64) winsize 57
6726 23:24:20.324820 [CA 5] Center 36 (8~64) winsize 57
6727 23:24:20.324901
6728 23:24:20.331421 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6729 23:24:20.331502
6730 23:24:20.335270 [CATrainingPosCal] consider 2 rank data
6731 23:24:20.338356 u2DelayCellTimex100 = 270/100 ps
6732 23:24:20.341681 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 23:24:20.345016 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 23:24:20.348476 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 23:24:20.351440 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 23:24:20.354768 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 23:24:20.358146 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 23:24:20.358227
6739 23:24:20.362188 CA PerBit enable=1, Macro0, CA PI delay=36
6740 23:24:20.362269
6741 23:24:20.364946 [CBTSetCACLKResult] CA Dly = 36
6742 23:24:20.368436 CS Dly: 1 (0~32)
6743 23:24:20.368516
6744 23:24:20.371893 ----->DramcWriteLeveling(PI) begin...
6745 23:24:20.371978 ==
6746 23:24:20.375224 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 23:24:20.379189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 23:24:20.379271 ==
6749 23:24:20.381542 Write leveling (Byte 0): 40 => 8
6750 23:24:20.384957 Write leveling (Byte 1): 40 => 8
6751 23:24:20.388542 DramcWriteLeveling(PI) end<-----
6752 23:24:20.388622
6753 23:24:20.388685 ==
6754 23:24:20.391936 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 23:24:20.394903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 23:24:20.394984 ==
6757 23:24:20.398469 [Gating] SW mode calibration
6758 23:24:20.404864 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6759 23:24:20.411481 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6760 23:24:20.415380 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6761 23:24:20.418357 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6762 23:24:20.425020 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6763 23:24:20.428585 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6764 23:24:20.431798 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6765 23:24:20.438445 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6766 23:24:20.441885 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 23:24:20.444946 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6768 23:24:20.451701 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6769 23:24:20.451783 Total UI for P1: 0, mck2ui 16
6770 23:24:20.455090 best dqsien dly found for B0: ( 0, 14, 24)
6771 23:24:20.457937 Total UI for P1: 0, mck2ui 16
6772 23:24:20.461684 best dqsien dly found for B1: ( 0, 14, 24)
6773 23:24:20.468392 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6774 23:24:20.471798 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6775 23:24:20.471879
6776 23:24:20.475032 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6777 23:24:20.477983 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6778 23:24:20.481272 [Gating] SW calibration Done
6779 23:24:20.481353 ==
6780 23:24:20.484596 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 23:24:20.487960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 23:24:20.488043 ==
6783 23:24:20.491419 RX Vref Scan: 0
6784 23:24:20.491500
6785 23:24:20.491565 RX Vref 0 -> 0, step: 1
6786 23:24:20.491625
6787 23:24:20.494747 RX Delay -410 -> 252, step: 16
6788 23:24:20.497900 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6789 23:24:20.504774 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6790 23:24:20.508148 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6791 23:24:20.511381 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6792 23:24:20.514699 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6793 23:24:20.521501 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6794 23:24:20.524913 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6795 23:24:20.527884 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6796 23:24:20.531463 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6797 23:24:20.538047 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6798 23:24:20.541297 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6799 23:24:20.544619 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6800 23:24:20.547955 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6801 23:24:20.554511 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6802 23:24:20.558019 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6803 23:24:20.561323 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6804 23:24:20.561403 ==
6805 23:24:20.564932 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 23:24:20.571780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 23:24:20.571861 ==
6808 23:24:20.571924 DQS Delay:
6809 23:24:20.574554 DQS0 = 51, DQS1 = 59
6810 23:24:20.574634 DQM Delay:
6811 23:24:20.574697 DQM0 = 19, DQM1 = 16
6812 23:24:20.578108 DQ Delay:
6813 23:24:20.581315 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6814 23:24:20.584654 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6815 23:24:20.584734 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6816 23:24:20.587897 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6817 23:24:20.591492
6818 23:24:20.591573
6819 23:24:20.591635 ==
6820 23:24:20.594582 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 23:24:20.597994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 23:24:20.598099 ==
6823 23:24:20.598190
6824 23:24:20.598251
6825 23:24:20.601697 TX Vref Scan disable
6826 23:24:20.601777 == TX Byte 0 ==
6827 23:24:20.604805 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6828 23:24:20.611332 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6829 23:24:20.611412 == TX Byte 1 ==
6830 23:24:20.614590 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6831 23:24:20.621749 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6832 23:24:20.621859 ==
6833 23:24:20.624733 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 23:24:20.628023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 23:24:20.628104 ==
6836 23:24:20.628167
6837 23:24:20.628225
6838 23:24:20.631636 TX Vref Scan disable
6839 23:24:20.631715 == TX Byte 0 ==
6840 23:24:20.635232 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6841 23:24:20.641349 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6842 23:24:20.641429 == TX Byte 1 ==
6843 23:24:20.644588 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6844 23:24:20.651627 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6845 23:24:20.651711
6846 23:24:20.651774 [DATLAT]
6847 23:24:20.651833 Freq=400, CH1 RK0
6848 23:24:20.651891
6849 23:24:20.655036 DATLAT Default: 0xf
6850 23:24:20.657934 0, 0xFFFF, sum = 0
6851 23:24:20.658016 1, 0xFFFF, sum = 0
6852 23:24:20.661353 2, 0xFFFF, sum = 0
6853 23:24:20.661433 3, 0xFFFF, sum = 0
6854 23:24:20.664627 4, 0xFFFF, sum = 0
6855 23:24:20.664707 5, 0xFFFF, sum = 0
6856 23:24:20.668247 6, 0xFFFF, sum = 0
6857 23:24:20.668329 7, 0xFFFF, sum = 0
6858 23:24:20.671240 8, 0xFFFF, sum = 0
6859 23:24:20.671320 9, 0xFFFF, sum = 0
6860 23:24:20.675204 10, 0xFFFF, sum = 0
6861 23:24:20.675285 11, 0xFFFF, sum = 0
6862 23:24:20.678096 12, 0xFFFF, sum = 0
6863 23:24:20.678176 13, 0x0, sum = 1
6864 23:24:20.681404 14, 0x0, sum = 2
6865 23:24:20.681485 15, 0x0, sum = 3
6866 23:24:20.684736 16, 0x0, sum = 4
6867 23:24:20.684817 best_step = 14
6868 23:24:20.684880
6869 23:24:20.684938 ==
6870 23:24:20.688268 Dram Type= 6, Freq= 0, CH_1, rank 0
6871 23:24:20.691663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 23:24:20.694797 ==
6873 23:24:20.694876 RX Vref Scan: 1
6874 23:24:20.694938
6875 23:24:20.698000 RX Vref 0 -> 0, step: 1
6876 23:24:20.698105
6877 23:24:20.701532 RX Delay -359 -> 252, step: 8
6878 23:24:20.701626
6879 23:24:20.704986 Set Vref, RX VrefLevel [Byte0]: 56
6880 23:24:20.705080 [Byte1]: 54
6881 23:24:20.710563
6882 23:24:20.710643 Final RX Vref Byte 0 = 56 to rank0
6883 23:24:20.713964 Final RX Vref Byte 1 = 54 to rank0
6884 23:24:20.718016 Final RX Vref Byte 0 = 56 to rank1
6885 23:24:20.720509 Final RX Vref Byte 1 = 54 to rank1==
6886 23:24:20.723856 Dram Type= 6, Freq= 0, CH_1, rank 0
6887 23:24:20.730294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 23:24:20.730451 ==
6889 23:24:20.730535 DQS Delay:
6890 23:24:20.733535 DQS0 = 48, DQS1 = 60
6891 23:24:20.733613 DQM Delay:
6892 23:24:20.733712 DQM0 = 12, DQM1 = 13
6893 23:24:20.736885 DQ Delay:
6894 23:24:20.740462 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6895 23:24:20.740542 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6896 23:24:20.743836 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =12
6897 23:24:20.747229 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6898 23:24:20.747309
6899 23:24:20.750372
6900 23:24:20.757005 [DQSOSCAuto] RK0, (LSB)MR18= 0x8129, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6901 23:24:20.760625 CH1 RK0: MR19=C0C, MR18=8129
6902 23:24:20.767261 CH1_RK0: MR19=0xC0C, MR18=0x8129, DQSOSC=393, MR23=63, INC=382, DEC=254
6903 23:24:20.767366 ==
6904 23:24:20.770374 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 23:24:20.773443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 23:24:20.773523 ==
6907 23:24:20.776834 [Gating] SW mode calibration
6908 23:24:20.783774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6909 23:24:20.791101 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6910 23:24:20.793595 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6911 23:24:20.796846 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6912 23:24:20.800347 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6913 23:24:20.806887 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6914 23:24:20.810607 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6915 23:24:20.813510 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6916 23:24:20.820264 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 23:24:20.823936 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6918 23:24:20.827460 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6919 23:24:20.830482 Total UI for P1: 0, mck2ui 16
6920 23:24:20.834810 best dqsien dly found for B0: ( 0, 14, 24)
6921 23:24:20.837080 Total UI for P1: 0, mck2ui 16
6922 23:24:20.841524 best dqsien dly found for B1: ( 0, 14, 24)
6923 23:24:20.844172 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6924 23:24:20.847032 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6925 23:24:20.847113
6926 23:24:20.853571 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6927 23:24:20.857416 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6928 23:24:20.857497 [Gating] SW calibration Done
6929 23:24:20.860198 ==
6930 23:24:20.863995 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 23:24:20.867201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 23:24:20.867282 ==
6933 23:24:20.867346 RX Vref Scan: 0
6934 23:24:20.867406
6935 23:24:20.870593 RX Vref 0 -> 0, step: 1
6936 23:24:20.870673
6937 23:24:20.874074 RX Delay -410 -> 252, step: 16
6938 23:24:20.877864 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6939 23:24:20.880837 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6940 23:24:20.886896 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6941 23:24:20.890335 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6942 23:24:20.893927 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6943 23:24:20.897274 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6944 23:24:20.903958 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6945 23:24:20.907531 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6946 23:24:20.910603 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6947 23:24:20.913899 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6948 23:24:20.920356 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6949 23:24:20.923951 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6950 23:24:20.927242 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6951 23:24:20.930726 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6952 23:24:20.937054 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6953 23:24:20.940298 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6954 23:24:20.940378 ==
6955 23:24:20.943773 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 23:24:20.946901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 23:24:20.946982 ==
6958 23:24:20.950904 DQS Delay:
6959 23:24:20.950984 DQS0 = 43, DQS1 = 59
6960 23:24:20.953747 DQM Delay:
6961 23:24:20.953828 DQM0 = 10, DQM1 = 20
6962 23:24:20.953892 DQ Delay:
6963 23:24:20.957272 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6964 23:24:20.960540 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6965 23:24:20.963810 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6966 23:24:20.967879 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6967 23:24:20.967960
6968 23:24:20.968023
6969 23:24:20.968082 ==
6970 23:24:20.970496 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 23:24:20.977272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 23:24:20.977353 ==
6973 23:24:20.977417
6974 23:24:20.977476
6975 23:24:20.977531 TX Vref Scan disable
6976 23:24:20.980507 == TX Byte 0 ==
6977 23:24:20.983611 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6978 23:24:20.986931 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6979 23:24:20.990517 == TX Byte 1 ==
6980 23:24:20.993913 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6981 23:24:20.997370 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6982 23:24:20.997470 ==
6983 23:24:21.000699 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 23:24:21.004002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 23:24:21.007587 ==
6986 23:24:21.007668
6987 23:24:21.007731
6988 23:24:21.007791 TX Vref Scan disable
6989 23:24:21.010989 == TX Byte 0 ==
6990 23:24:21.014006 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6991 23:24:21.017309 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6992 23:24:21.020595 == TX Byte 1 ==
6993 23:24:21.023715 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6994 23:24:21.026907 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6995 23:24:21.026988
6996 23:24:21.030559 [DATLAT]
6997 23:24:21.030639 Freq=400, CH1 RK1
6998 23:24:21.030703
6999 23:24:21.033972 DATLAT Default: 0xe
7000 23:24:21.034052 0, 0xFFFF, sum = 0
7001 23:24:21.037051 1, 0xFFFF, sum = 0
7002 23:24:21.037133 2, 0xFFFF, sum = 0
7003 23:24:21.040506 3, 0xFFFF, sum = 0
7004 23:24:21.040588 4, 0xFFFF, sum = 0
7005 23:24:21.044020 5, 0xFFFF, sum = 0
7006 23:24:21.044101 6, 0xFFFF, sum = 0
7007 23:24:21.047021 7, 0xFFFF, sum = 0
7008 23:24:21.047103 8, 0xFFFF, sum = 0
7009 23:24:21.050327 9, 0xFFFF, sum = 0
7010 23:24:21.050418 10, 0xFFFF, sum = 0
7011 23:24:21.053722 11, 0xFFFF, sum = 0
7012 23:24:21.053804 12, 0xFFFF, sum = 0
7013 23:24:21.057169 13, 0x0, sum = 1
7014 23:24:21.057251 14, 0x0, sum = 2
7015 23:24:21.060635 15, 0x0, sum = 3
7016 23:24:21.060716 16, 0x0, sum = 4
7017 23:24:21.063417 best_step = 14
7018 23:24:21.063498
7019 23:24:21.063561 ==
7020 23:24:21.066974 Dram Type= 6, Freq= 0, CH_1, rank 1
7021 23:24:21.070115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7022 23:24:21.070196 ==
7023 23:24:21.073702 RX Vref Scan: 0
7024 23:24:21.073783
7025 23:24:21.073847 RX Vref 0 -> 0, step: 1
7026 23:24:21.073906
7027 23:24:21.076650 RX Delay -359 -> 252, step: 8
7028 23:24:21.084933 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7029 23:24:21.088087 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7030 23:24:21.091702 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
7031 23:24:21.095078 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7032 23:24:21.101352 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
7033 23:24:21.105019 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7034 23:24:21.108105 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7035 23:24:21.111348 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7036 23:24:21.118102 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
7037 23:24:21.121778 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7038 23:24:21.124807 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7039 23:24:21.128634 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7040 23:24:21.135046 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
7041 23:24:21.138538 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7042 23:24:21.141582 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7043 23:24:21.144816 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7044 23:24:21.148263 ==
7045 23:24:21.151937 Dram Type= 6, Freq= 0, CH_1, rank 1
7046 23:24:21.154973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7047 23:24:21.155054 ==
7048 23:24:21.155117 DQS Delay:
7049 23:24:21.158335 DQS0 = 48, DQS1 = 60
7050 23:24:21.158436 DQM Delay:
7051 23:24:21.161398 DQM0 = 9, DQM1 = 13
7052 23:24:21.161478 DQ Delay:
7053 23:24:21.165511 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
7054 23:24:21.168600 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
7055 23:24:21.171905 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
7056 23:24:21.174757 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
7057 23:24:21.174838
7058 23:24:21.174902
7059 23:24:21.181684 [DQSOSCAuto] RK1, (LSB)MR18= 0x778e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
7060 23:24:21.184829 CH1 RK1: MR19=C0C, MR18=778E
7061 23:24:21.191506 CH1_RK1: MR19=0xC0C, MR18=0x778E, DQSOSC=392, MR23=63, INC=384, DEC=256
7062 23:24:21.195242 [RxdqsGatingPostProcess] freq 400
7063 23:24:21.198609 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7064 23:24:21.201387 best DQS0 dly(2T, 0.5T) = (0, 10)
7065 23:24:21.205275 best DQS1 dly(2T, 0.5T) = (0, 10)
7066 23:24:21.208462 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7067 23:24:21.211658 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7068 23:24:21.215113 best DQS0 dly(2T, 0.5T) = (0, 10)
7069 23:24:21.218276 best DQS1 dly(2T, 0.5T) = (0, 10)
7070 23:24:21.221893 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7071 23:24:21.224584 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7072 23:24:21.228125 Pre-setting of DQS Precalculation
7073 23:24:21.231446 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7074 23:24:21.241626 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7075 23:24:21.248639 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7076 23:24:21.248722
7077 23:24:21.248785
7078 23:24:21.251581 [Calibration Summary] 800 Mbps
7079 23:24:21.251662 CH 0, Rank 0
7080 23:24:21.255020 SW Impedance : PASS
7081 23:24:21.255101 DUTY Scan : NO K
7082 23:24:21.258642 ZQ Calibration : PASS
7083 23:24:21.262151 Jitter Meter : NO K
7084 23:24:21.262232 CBT Training : PASS
7085 23:24:21.264947 Write leveling : PASS
7086 23:24:21.265027 RX DQS gating : PASS
7087 23:24:21.268676 RX DQ/DQS(RDDQC) : PASS
7088 23:24:21.271757 TX DQ/DQS : PASS
7089 23:24:21.271838 RX DATLAT : PASS
7090 23:24:21.274935 RX DQ/DQS(Engine): PASS
7091 23:24:21.278849 TX OE : NO K
7092 23:24:21.278930 All Pass.
7093 23:24:21.278994
7094 23:24:21.279053 CH 0, Rank 1
7095 23:24:21.281682 SW Impedance : PASS
7096 23:24:21.285265 DUTY Scan : NO K
7097 23:24:21.285346 ZQ Calibration : PASS
7098 23:24:21.288548 Jitter Meter : NO K
7099 23:24:21.291752 CBT Training : PASS
7100 23:24:21.291833 Write leveling : NO K
7101 23:24:21.295017 RX DQS gating : PASS
7102 23:24:21.295098 RX DQ/DQS(RDDQC) : PASS
7103 23:24:21.298827 TX DQ/DQS : PASS
7104 23:24:21.301646 RX DATLAT : PASS
7105 23:24:21.301741 RX DQ/DQS(Engine): PASS
7106 23:24:21.305430 TX OE : NO K
7107 23:24:21.305510 All Pass.
7108 23:24:21.305574
7109 23:24:21.308626 CH 1, Rank 0
7110 23:24:21.308707 SW Impedance : PASS
7111 23:24:21.312162 DUTY Scan : NO K
7112 23:24:21.315408 ZQ Calibration : PASS
7113 23:24:21.315489 Jitter Meter : NO K
7114 23:24:21.318937 CBT Training : PASS
7115 23:24:21.322238 Write leveling : PASS
7116 23:24:21.322318 RX DQS gating : PASS
7117 23:24:21.325419 RX DQ/DQS(RDDQC) : PASS
7118 23:24:21.328248 TX DQ/DQS : PASS
7119 23:24:21.328329 RX DATLAT : PASS
7120 23:24:21.332181 RX DQ/DQS(Engine): PASS
7121 23:24:21.334959 TX OE : NO K
7122 23:24:21.335041 All Pass.
7123 23:24:21.335105
7124 23:24:21.335163 CH 1, Rank 1
7125 23:24:21.338497 SW Impedance : PASS
7126 23:24:21.341685 DUTY Scan : NO K
7127 23:24:21.341766 ZQ Calibration : PASS
7128 23:24:21.345436 Jitter Meter : NO K
7129 23:24:21.345517 CBT Training : PASS
7130 23:24:21.348380 Write leveling : NO K
7131 23:24:21.351585 RX DQS gating : PASS
7132 23:24:21.351753 RX DQ/DQS(RDDQC) : PASS
7133 23:24:21.355001 TX DQ/DQS : PASS
7134 23:24:21.358516 RX DATLAT : PASS
7135 23:24:21.358597 RX DQ/DQS(Engine): PASS
7136 23:24:21.361932 TX OE : NO K
7137 23:24:21.362017 All Pass.
7138 23:24:21.362082
7139 23:24:21.365219 DramC Write-DBI off
7140 23:24:21.368200 PER_BANK_REFRESH: Hybrid Mode
7141 23:24:21.368282 TX_TRACKING: ON
7142 23:24:21.378116 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7143 23:24:21.381533 [FAST_K] Save calibration result to emmc
7144 23:24:21.385115 dramc_set_vcore_voltage set vcore to 725000
7145 23:24:21.388704 Read voltage for 1600, 0
7146 23:24:21.388784 Vio18 = 0
7147 23:24:21.388848 Vcore = 725000
7148 23:24:21.391530 Vdram = 0
7149 23:24:21.391611 Vddq = 0
7150 23:24:21.391674 Vmddr = 0
7151 23:24:21.398143 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7152 23:24:21.401867 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7153 23:24:21.404962 MEM_TYPE=3, freq_sel=13
7154 23:24:21.408102 sv_algorithm_assistance_LP4_3733
7155 23:24:21.411844 ============ PULL DRAM RESETB DOWN ============
7156 23:24:21.414649 ========== PULL DRAM RESETB DOWN end =========
7157 23:24:21.421599 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7158 23:24:21.424808 ===================================
7159 23:24:21.428100 LPDDR4 DRAM CONFIGURATION
7160 23:24:21.431402 ===================================
7161 23:24:21.431481 EX_ROW_EN[0] = 0x0
7162 23:24:21.434887 EX_ROW_EN[1] = 0x0
7163 23:24:21.434963 LP4Y_EN = 0x0
7164 23:24:21.438486 WORK_FSP = 0x1
7165 23:24:21.438557 WL = 0x5
7166 23:24:21.441537 RL = 0x5
7167 23:24:21.441606 BL = 0x2
7168 23:24:21.445234 RPST = 0x0
7169 23:24:21.445303 RD_PRE = 0x0
7170 23:24:21.448316 WR_PRE = 0x1
7171 23:24:21.448386 WR_PST = 0x1
7172 23:24:21.451847 DBI_WR = 0x0
7173 23:24:21.451918 DBI_RD = 0x0
7174 23:24:21.454674 OTF = 0x1
7175 23:24:21.458190 ===================================
7176 23:24:21.461404 ===================================
7177 23:24:21.461485 ANA top config
7178 23:24:21.464684 ===================================
7179 23:24:21.468169 DLL_ASYNC_EN = 0
7180 23:24:21.471554 ALL_SLAVE_EN = 0
7181 23:24:21.475150 NEW_RANK_MODE = 1
7182 23:24:21.475231 DLL_IDLE_MODE = 1
7183 23:24:21.478501 LP45_APHY_COMB_EN = 1
7184 23:24:21.481566 TX_ODT_DIS = 0
7185 23:24:21.484962 NEW_8X_MODE = 1
7186 23:24:21.488492 ===================================
7187 23:24:21.491823 ===================================
7188 23:24:21.494681 data_rate = 3200
7189 23:24:21.494762 CKR = 1
7190 23:24:21.498523 DQ_P2S_RATIO = 8
7191 23:24:21.501511 ===================================
7192 23:24:21.504783 CA_P2S_RATIO = 8
7193 23:24:21.508160 DQ_CA_OPEN = 0
7194 23:24:21.511540 DQ_SEMI_OPEN = 0
7195 23:24:21.515252 CA_SEMI_OPEN = 0
7196 23:24:21.515333 CA_FULL_RATE = 0
7197 23:24:21.518598 DQ_CKDIV4_EN = 0
7198 23:24:21.521706 CA_CKDIV4_EN = 0
7199 23:24:21.525380 CA_PREDIV_EN = 0
7200 23:24:21.528316 PH8_DLY = 12
7201 23:24:21.528397 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7202 23:24:21.531531 DQ_AAMCK_DIV = 4
7203 23:24:21.535063 CA_AAMCK_DIV = 4
7204 23:24:21.538764 CA_ADMCK_DIV = 4
7205 23:24:21.541738 DQ_TRACK_CA_EN = 0
7206 23:24:21.544862 CA_PICK = 1600
7207 23:24:21.548411 CA_MCKIO = 1600
7208 23:24:21.548494 MCKIO_SEMI = 0
7209 23:24:21.551884 PLL_FREQ = 3068
7210 23:24:21.555316 DQ_UI_PI_RATIO = 32
7211 23:24:21.558209 CA_UI_PI_RATIO = 0
7212 23:24:21.561653 ===================================
7213 23:24:21.564930 ===================================
7214 23:24:21.568544 memory_type:LPDDR4
7215 23:24:21.568629 GP_NUM : 10
7216 23:24:21.571729 SRAM_EN : 1
7217 23:24:21.575036 MD32_EN : 0
7218 23:24:21.575160 ===================================
7219 23:24:21.578221 [ANA_INIT] >>>>>>>>>>>>>>
7220 23:24:21.582036 <<<<<< [CONFIGURE PHASE]: ANA_TX
7221 23:24:21.585483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7222 23:24:21.589001 ===================================
7223 23:24:21.591638 data_rate = 3200,PCW = 0X7600
7224 23:24:21.594941 ===================================
7225 23:24:21.598837 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7226 23:24:21.604902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7227 23:24:21.608292 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7228 23:24:21.615219 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7229 23:24:21.618625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7230 23:24:21.621867 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7231 23:24:21.621950 [ANA_INIT] flow start
7232 23:24:21.625287 [ANA_INIT] PLL >>>>>>>>
7233 23:24:21.629002 [ANA_INIT] PLL <<<<<<<<
7234 23:24:21.629083 [ANA_INIT] MIDPI >>>>>>>>
7235 23:24:21.632227 [ANA_INIT] MIDPI <<<<<<<<
7236 23:24:21.635181 [ANA_INIT] DLL >>>>>>>>
7237 23:24:21.635286 [ANA_INIT] DLL <<<<<<<<
7238 23:24:21.638255 [ANA_INIT] flow end
7239 23:24:21.641625 ============ LP4 DIFF to SE enter ============
7240 23:24:21.645008 ============ LP4 DIFF to SE exit ============
7241 23:24:21.648436 [ANA_INIT] <<<<<<<<<<<<<
7242 23:24:21.652391 [Flow] Enable top DCM control >>>>>
7243 23:24:21.654900 [Flow] Enable top DCM control <<<<<
7244 23:24:21.658381 Enable DLL master slave shuffle
7245 23:24:21.664847 ==============================================================
7246 23:24:21.664927 Gating Mode config
7247 23:24:21.671949 ==============================================================
7248 23:24:21.672029 Config description:
7249 23:24:21.681987 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7250 23:24:21.688564 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7251 23:24:21.695427 SELPH_MODE 0: By rank 1: By Phase
7252 23:24:21.698360 ==============================================================
7253 23:24:21.701970 GAT_TRACK_EN = 1
7254 23:24:21.705386 RX_GATING_MODE = 2
7255 23:24:21.708701 RX_GATING_TRACK_MODE = 2
7256 23:24:21.712307 SELPH_MODE = 1
7257 23:24:21.715205 PICG_EARLY_EN = 1
7258 23:24:21.718538 VALID_LAT_VALUE = 1
7259 23:24:21.722084 ==============================================================
7260 23:24:21.725576 Enter into Gating configuration >>>>
7261 23:24:21.728666 Exit from Gating configuration <<<<
7262 23:24:21.732223 Enter into DVFS_PRE_config >>>>>
7263 23:24:21.745095 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7264 23:24:21.748682 Exit from DVFS_PRE_config <<<<<
7265 23:24:21.751574 Enter into PICG configuration >>>>
7266 23:24:21.755180 Exit from PICG configuration <<<<
7267 23:24:21.755260 [RX_INPUT] configuration >>>>>
7268 23:24:21.758750 [RX_INPUT] configuration <<<<<
7269 23:24:21.765388 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7270 23:24:21.768788 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7271 23:24:21.775147 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7272 23:24:21.781604 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7273 23:24:21.788419 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7274 23:24:21.795116 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7275 23:24:21.798483 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7276 23:24:21.802159 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7277 23:24:21.804785 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7278 23:24:21.811691 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7279 23:24:21.815276 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7280 23:24:21.818715 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7281 23:24:21.821733 ===================================
7282 23:24:21.825299 LPDDR4 DRAM CONFIGURATION
7283 23:24:21.828595 ===================================
7284 23:24:21.831821 EX_ROW_EN[0] = 0x0
7285 23:24:21.831905 EX_ROW_EN[1] = 0x0
7286 23:24:21.835615 LP4Y_EN = 0x0
7287 23:24:21.835726 WORK_FSP = 0x1
7288 23:24:21.838297 WL = 0x5
7289 23:24:21.838442 RL = 0x5
7290 23:24:21.841654 BL = 0x2
7291 23:24:21.841735 RPST = 0x0
7292 23:24:21.845519 RD_PRE = 0x0
7293 23:24:21.845599 WR_PRE = 0x1
7294 23:24:21.848589 WR_PST = 0x1
7295 23:24:21.848669 DBI_WR = 0x0
7296 23:24:21.851734 DBI_RD = 0x0
7297 23:24:21.851813 OTF = 0x1
7298 23:24:21.855266 ===================================
7299 23:24:21.858533 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7300 23:24:21.865625 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7301 23:24:21.868921 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7302 23:24:21.871795 ===================================
7303 23:24:21.875263 LPDDR4 DRAM CONFIGURATION
7304 23:24:21.878625 ===================================
7305 23:24:21.878705 EX_ROW_EN[0] = 0x10
7306 23:24:21.882200 EX_ROW_EN[1] = 0x0
7307 23:24:21.882280 LP4Y_EN = 0x0
7308 23:24:21.885407 WORK_FSP = 0x1
7309 23:24:21.885486 WL = 0x5
7310 23:24:21.888731 RL = 0x5
7311 23:24:21.892493 BL = 0x2
7312 23:24:21.892573 RPST = 0x0
7313 23:24:21.895400 RD_PRE = 0x0
7314 23:24:21.895479 WR_PRE = 0x1
7315 23:24:21.898776 WR_PST = 0x1
7316 23:24:21.898881 DBI_WR = 0x0
7317 23:24:21.902038 DBI_RD = 0x0
7318 23:24:21.902148 OTF = 0x1
7319 23:24:21.905419 ===================================
7320 23:24:21.912233 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7321 23:24:21.912314 ==
7322 23:24:21.916435 Dram Type= 6, Freq= 0, CH_0, rank 0
7323 23:24:21.918977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7324 23:24:21.919098 ==
7325 23:24:21.922432 [Duty_Offset_Calibration]
7326 23:24:21.925606 B0:2 B1:-1 CA:1
7327 23:24:21.925685
7328 23:24:21.928576 [DutyScan_Calibration_Flow] k_type=0
7329 23:24:21.936538
7330 23:24:21.936618 ==CLK 0==
7331 23:24:21.939980 Final CLK duty delay cell = -4
7332 23:24:21.942804 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7333 23:24:21.946577 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7334 23:24:21.949880 [-4] AVG Duty = 4937%(X100)
7335 23:24:21.949959
7336 23:24:21.952701 CH0 CLK Duty spec in!! Max-Min= 187%
7337 23:24:21.956990 [DutyScan_Calibration_Flow] ====Done====
7338 23:24:21.957069
7339 23:24:21.959547 [DutyScan_Calibration_Flow] k_type=1
7340 23:24:21.976354
7341 23:24:21.976434 ==DQS 0 ==
7342 23:24:21.979168 Final DQS duty delay cell = 0
7343 23:24:21.982338 [0] MAX Duty = 5125%(X100), DQS PI = 20
7344 23:24:21.985854 [0] MIN Duty = 5000%(X100), DQS PI = 14
7345 23:24:21.989067 [0] AVG Duty = 5062%(X100)
7346 23:24:21.989146
7347 23:24:21.989209 ==DQS 1 ==
7348 23:24:21.992471 Final DQS duty delay cell = -4
7349 23:24:21.995666 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7350 23:24:21.998964 [-4] MIN Duty = 5031%(X100), DQS PI = 6
7351 23:24:22.002431 [-4] AVG Duty = 5062%(X100)
7352 23:24:22.002550
7353 23:24:22.005846 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7354 23:24:22.005950
7355 23:24:22.009391 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7356 23:24:22.012499 [DutyScan_Calibration_Flow] ====Done====
7357 23:24:22.012579
7358 23:24:22.015884 [DutyScan_Calibration_Flow] k_type=3
7359 23:24:22.032918
7360 23:24:22.033006 ==DQM 0 ==
7361 23:24:22.036963 Final DQM duty delay cell = 0
7362 23:24:22.039925 [0] MAX Duty = 5000%(X100), DQS PI = 20
7363 23:24:22.042881 [0] MIN Duty = 4875%(X100), DQS PI = 6
7364 23:24:22.042989 [0] AVG Duty = 4937%(X100)
7365 23:24:22.046704
7366 23:24:22.046837 ==DQM 1 ==
7367 23:24:22.049788 Final DQM duty delay cell = 0
7368 23:24:22.053199 [0] MAX Duty = 5218%(X100), DQS PI = 58
7369 23:24:22.056510 [0] MIN Duty = 4969%(X100), DQS PI = 18
7370 23:24:22.056590 [0] AVG Duty = 5093%(X100)
7371 23:24:22.060003
7372 23:24:22.062807 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7373 23:24:22.062886
7374 23:24:22.066422 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7375 23:24:22.069536 [DutyScan_Calibration_Flow] ====Done====
7376 23:24:22.069615
7377 23:24:22.072758 [DutyScan_Calibration_Flow] k_type=2
7378 23:24:22.089694
7379 23:24:22.089781 ==DQ 0 ==
7380 23:24:22.092560 Final DQ duty delay cell = -4
7381 23:24:22.096089 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7382 23:24:22.099146 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7383 23:24:22.102366 [-4] AVG Duty = 4937%(X100)
7384 23:24:22.102494
7385 23:24:22.102556 ==DQ 1 ==
7386 23:24:22.106253 Final DQ duty delay cell = 0
7387 23:24:22.109954 [0] MAX Duty = 5000%(X100), DQS PI = 12
7388 23:24:22.112421 [0] MIN Duty = 4907%(X100), DQS PI = 24
7389 23:24:22.116319 [0] AVG Duty = 4953%(X100)
7390 23:24:22.116394
7391 23:24:22.119939 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7392 23:24:22.120014
7393 23:24:22.123010 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7394 23:24:22.126265 [DutyScan_Calibration_Flow] ====Done====
7395 23:24:22.126344 ==
7396 23:24:22.129250 Dram Type= 6, Freq= 0, CH_1, rank 0
7397 23:24:22.132585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7398 23:24:22.132666 ==
7399 23:24:22.136326 [Duty_Offset_Calibration]
7400 23:24:22.136406 B0:1 B1:1 CA:2
7401 23:24:22.136469
7402 23:24:22.139235 [DutyScan_Calibration_Flow] k_type=0
7403 23:24:22.149727
7404 23:24:22.149806 ==CLK 0==
7405 23:24:22.153047 Final CLK duty delay cell = 0
7406 23:24:22.156242 [0] MAX Duty = 5156%(X100), DQS PI = 24
7407 23:24:22.160115 [0] MIN Duty = 4938%(X100), DQS PI = 48
7408 23:24:22.160195 [0] AVG Duty = 5047%(X100)
7409 23:24:22.163131
7410 23:24:22.163211 CH1 CLK Duty spec in!! Max-Min= 218%
7411 23:24:22.170023 [DutyScan_Calibration_Flow] ====Done====
7412 23:24:22.170102
7413 23:24:22.172929 [DutyScan_Calibration_Flow] k_type=1
7414 23:24:22.189536
7415 23:24:22.189619 ==DQS 0 ==
7416 23:24:22.192803 Final DQS duty delay cell = 0
7417 23:24:22.196340 [0] MAX Duty = 5031%(X100), DQS PI = 20
7418 23:24:22.199778 [0] MIN Duty = 4813%(X100), DQS PI = 50
7419 23:24:22.203335 [0] AVG Duty = 4922%(X100)
7420 23:24:22.203417
7421 23:24:22.203481 ==DQS 1 ==
7422 23:24:22.206075 Final DQS duty delay cell = 0
7423 23:24:22.209405 [0] MAX Duty = 5031%(X100), DQS PI = 36
7424 23:24:22.213194 [0] MIN Duty = 4938%(X100), DQS PI = 12
7425 23:24:22.216275 [0] AVG Duty = 4984%(X100)
7426 23:24:22.216356
7427 23:24:22.219508 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7428 23:24:22.219589
7429 23:24:22.223228 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7430 23:24:22.226115 [DutyScan_Calibration_Flow] ====Done====
7431 23:24:22.226195
7432 23:24:22.229663 [DutyScan_Calibration_Flow] k_type=3
7433 23:24:22.246415
7434 23:24:22.246510 ==DQM 0 ==
7435 23:24:22.249863 Final DQM duty delay cell = 0
7436 23:24:22.253534 [0] MAX Duty = 5156%(X100), DQS PI = 20
7437 23:24:22.256452 [0] MIN Duty = 4844%(X100), DQS PI = 50
7438 23:24:22.259666 [0] AVG Duty = 5000%(X100)
7439 23:24:22.259747
7440 23:24:22.259811 ==DQM 1 ==
7441 23:24:22.262879 Final DQM duty delay cell = 0
7442 23:24:22.266561 [0] MAX Duty = 5156%(X100), DQS PI = 60
7443 23:24:22.270082 [0] MIN Duty = 4907%(X100), DQS PI = 20
7444 23:24:22.270163 [0] AVG Duty = 5031%(X100)
7445 23:24:22.273367
7446 23:24:22.276265 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7447 23:24:22.276371
7448 23:24:22.279690 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7449 23:24:22.283404 [DutyScan_Calibration_Flow] ====Done====
7450 23:24:22.283485
7451 23:24:22.286637 [DutyScan_Calibration_Flow] k_type=2
7452 23:24:22.303616
7453 23:24:22.303699 ==DQ 0 ==
7454 23:24:22.306806 Final DQ duty delay cell = 0
7455 23:24:22.310340 [0] MAX Duty = 5125%(X100), DQS PI = 20
7456 23:24:22.313637 [0] MIN Duty = 4907%(X100), DQS PI = 52
7457 23:24:22.313717 [0] AVG Duty = 5016%(X100)
7458 23:24:22.316598
7459 23:24:22.316693 ==DQ 1 ==
7460 23:24:22.320349 Final DQ duty delay cell = 0
7461 23:24:22.323782 [0] MAX Duty = 5093%(X100), DQS PI = 6
7462 23:24:22.326745 [0] MIN Duty = 5031%(X100), DQS PI = 0
7463 23:24:22.326826 [0] AVG Duty = 5062%(X100)
7464 23:24:22.326888
7465 23:24:22.330356 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7466 23:24:22.330471
7467 23:24:22.333731 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7468 23:24:22.339949 [DutyScan_Calibration_Flow] ====Done====
7469 23:24:22.343455 nWR fixed to 30
7470 23:24:22.343536 [ModeRegInit_LP4] CH0 RK0
7471 23:24:22.346721 [ModeRegInit_LP4] CH0 RK1
7472 23:24:22.350226 [ModeRegInit_LP4] CH1 RK0
7473 23:24:22.350331 [ModeRegInit_LP4] CH1 RK1
7474 23:24:22.353617 match AC timing 5
7475 23:24:22.356913 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7476 23:24:22.360299 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7477 23:24:22.366719 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7478 23:24:22.370159 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7479 23:24:22.377050 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7480 23:24:22.377130 [MiockJmeterHQA]
7481 23:24:22.377194
7482 23:24:22.380268 [DramcMiockJmeter] u1RxGatingPI = 0
7483 23:24:22.383796 0 : 4253, 4026
7484 23:24:22.383877 4 : 4253, 4026
7485 23:24:22.383972 8 : 4252, 4027
7486 23:24:22.386694 12 : 4252, 4027
7487 23:24:22.386774 16 : 4363, 4138
7488 23:24:22.390329 20 : 4253, 4026
7489 23:24:22.390468 24 : 4252, 4027
7490 23:24:22.393282 28 : 4252, 4027
7491 23:24:22.393363 32 : 4255, 4029
7492 23:24:22.393442 36 : 4363, 4138
7493 23:24:22.397179 40 : 4253, 4026
7494 23:24:22.397259 44 : 4252, 4027
7495 23:24:22.399936 48 : 4250, 4027
7496 23:24:22.400017 52 : 4255, 4029
7497 23:24:22.403893 56 : 4250, 4027
7498 23:24:22.403974 60 : 4360, 4137
7499 23:24:22.404039 64 : 4361, 4137
7500 23:24:22.406615 68 : 4250, 4027
7501 23:24:22.406748 72 : 4250, 4026
7502 23:24:22.409902 76 : 4250, 4027
7503 23:24:22.409983 80 : 4250, 4027
7504 23:24:22.413277 84 : 4253, 4029
7505 23:24:22.413359 88 : 4361, 4138
7506 23:24:22.417165 92 : 4250, 4026
7507 23:24:22.417246 96 : 4250, 3349
7508 23:24:22.417326 100 : 4249, 0
7509 23:24:22.419886 104 : 4250, 0
7510 23:24:22.419972 108 : 4250, 0
7511 23:24:22.423977 112 : 4252, 0
7512 23:24:22.424058 116 : 4250, 0
7513 23:24:22.424122 120 : 4252, 0
7514 23:24:22.426694 124 : 4253, 0
7515 23:24:22.426775 128 : 4250, 0
7516 23:24:22.426839 132 : 4252, 0
7517 23:24:22.430117 136 : 4363, 0
7518 23:24:22.430198 140 : 4361, 0
7519 23:24:22.433232 144 : 4250, 0
7520 23:24:22.433316 148 : 4255, 0
7521 23:24:22.433381 152 : 4253, 0
7522 23:24:22.436694 156 : 4249, 0
7523 23:24:22.436781 160 : 4252, 0
7524 23:24:22.440051 164 : 4250, 0
7525 23:24:22.440132 168 : 4250, 0
7526 23:24:22.440196 172 : 4253, 0
7527 23:24:22.443731 176 : 4250, 0
7528 23:24:22.443813 180 : 4250, 0
7529 23:24:22.446993 184 : 4252, 0
7530 23:24:22.447100 188 : 4363, 0
7531 23:24:22.447193 192 : 4361, 0
7532 23:24:22.450251 196 : 4363, 0
7533 23:24:22.450332 200 : 4255, 0
7534 23:24:22.450426 204 : 4253, 0
7535 23:24:22.453698 208 : 4249, 0
7536 23:24:22.453779 212 : 4252, 71
7537 23:24:22.457167 216 : 4250, 3618
7538 23:24:22.457247 220 : 4361, 4137
7539 23:24:22.460388 224 : 4250, 4026
7540 23:24:22.460469 228 : 4361, 4137
7541 23:24:22.463361 232 : 4361, 4138
7542 23:24:22.463446 236 : 4249, 4027
7543 23:24:22.463510 240 : 4250, 4026
7544 23:24:22.467094 244 : 4363, 4140
7545 23:24:22.467175 248 : 4250, 4027
7546 23:24:22.470365 252 : 4250, 4027
7547 23:24:22.470490 256 : 4250, 4026
7548 23:24:22.473832 260 : 4253, 4029
7549 23:24:22.473912 264 : 4250, 4027
7550 23:24:22.477110 268 : 4250, 4027
7551 23:24:22.477191 272 : 4360, 4137
7552 23:24:22.480480 276 : 4250, 4026
7553 23:24:22.480561 280 : 4250, 4027
7554 23:24:22.483628 284 : 4360, 4138
7555 23:24:22.483713 288 : 4250, 4027
7556 23:24:22.487060 292 : 4250, 4026
7557 23:24:22.487141 296 : 4363, 4140
7558 23:24:22.487206 300 : 4250, 4027
7559 23:24:22.490722 304 : 4250, 4027
7560 23:24:22.490803 308 : 4250, 4026
7561 23:24:22.493703 312 : 4253, 4029
7562 23:24:22.493784 316 : 4250, 4027
7563 23:24:22.497048 320 : 4250, 4027
7564 23:24:22.497129 324 : 4360, 4137
7565 23:24:22.500163 328 : 4250, 4026
7566 23:24:22.500244 332 : 4250, 3037
7567 23:24:22.503586 336 : 4360, 129
7568 23:24:22.503667
7569 23:24:22.503730 MIOCK jitter meter ch=0
7570 23:24:22.503789
7571 23:24:22.506921 1T = (336-100) = 236 dly cells
7572 23:24:22.513666 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7573 23:24:22.513746 ==
7574 23:24:22.517224 Dram Type= 6, Freq= 0, CH_0, rank 0
7575 23:24:22.520256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 23:24:22.520337 ==
7577 23:24:22.526764 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7578 23:24:22.530125 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7579 23:24:22.533939 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7580 23:24:22.540433 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7581 23:24:22.549960 [CA 0] Center 44 (14~75) winsize 62
7582 23:24:22.553494 [CA 1] Center 44 (13~75) winsize 63
7583 23:24:22.556586 [CA 2] Center 40 (11~69) winsize 59
7584 23:24:22.559828 [CA 3] Center 39 (10~69) winsize 60
7585 23:24:22.563465 [CA 4] Center 38 (8~68) winsize 61
7586 23:24:22.566644 [CA 5] Center 37 (7~67) winsize 61
7587 23:24:22.566724
7588 23:24:22.570158 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7589 23:24:22.570263
7590 23:24:22.573440 [CATrainingPosCal] consider 1 rank data
7591 23:24:22.576656 u2DelayCellTimex100 = 275/100 ps
7592 23:24:22.579970 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7593 23:24:22.586922 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7594 23:24:22.590029 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7595 23:24:22.593204 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7596 23:24:22.597025 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7597 23:24:22.599929 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7598 23:24:22.600041
7599 23:24:22.603376 CA PerBit enable=1, Macro0, CA PI delay=37
7600 23:24:22.603456
7601 23:24:22.606775 [CBTSetCACLKResult] CA Dly = 37
7602 23:24:22.610260 CS Dly: 11 (0~42)
7603 23:24:22.613637 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7604 23:24:22.616895 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7605 23:24:22.616975 ==
7606 23:24:22.620462 Dram Type= 6, Freq= 0, CH_0, rank 1
7607 23:24:22.623873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 23:24:22.623961 ==
7609 23:24:22.630174 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7610 23:24:22.633683 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7611 23:24:22.640410 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7612 23:24:22.643390 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7613 23:24:22.654161 [CA 0] Center 43 (13~74) winsize 62
7614 23:24:22.657436 [CA 1] Center 43 (13~74) winsize 62
7615 23:24:22.660429 [CA 2] Center 39 (10~69) winsize 60
7616 23:24:22.663711 [CA 3] Center 38 (9~68) winsize 60
7617 23:24:22.666808 [CA 4] Center 37 (7~67) winsize 61
7618 23:24:22.670311 [CA 5] Center 36 (6~67) winsize 62
7619 23:24:22.670455
7620 23:24:22.673675 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7621 23:24:22.673756
7622 23:24:22.677010 [CATrainingPosCal] consider 2 rank data
7623 23:24:22.680477 u2DelayCellTimex100 = 275/100 ps
7624 23:24:22.683741 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7625 23:24:22.690435 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7626 23:24:22.693760 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7627 23:24:22.696804 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7628 23:24:22.700219 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7629 23:24:22.703630 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7630 23:24:22.703704
7631 23:24:22.706828 CA PerBit enable=1, Macro0, CA PI delay=37
7632 23:24:22.706947
7633 23:24:22.710334 [CBTSetCACLKResult] CA Dly = 37
7634 23:24:22.713786 CS Dly: 12 (0~44)
7635 23:24:22.717075 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7636 23:24:22.720607 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7637 23:24:22.720688
7638 23:24:22.723890 ----->DramcWriteLeveling(PI) begin...
7639 23:24:22.723971 ==
7640 23:24:22.727216 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 23:24:22.733816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 23:24:22.733897 ==
7643 23:24:22.736741 Write leveling (Byte 0): 33 => 33
7644 23:24:22.736846 Write leveling (Byte 1): 26 => 26
7645 23:24:22.740683 DramcWriteLeveling(PI) end<-----
7646 23:24:22.740766
7647 23:24:22.740830 ==
7648 23:24:22.744248 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 23:24:22.750389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 23:24:22.750511 ==
7651 23:24:22.753736 [Gating] SW mode calibration
7652 23:24:22.760495 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7653 23:24:22.763412 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7654 23:24:22.770217 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 23:24:22.773765 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 23:24:22.777497 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 23:24:22.780351 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 23:24:22.787993 1 4 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7659 23:24:22.790370 1 4 20 | B1->B0 | 2323 3333 | 1 1 | (1 1) (1 1)
7660 23:24:22.793989 1 4 24 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
7661 23:24:22.800733 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7662 23:24:22.804139 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7663 23:24:22.807313 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7664 23:24:22.813645 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7665 23:24:22.817648 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7666 23:24:22.820294 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
7667 23:24:22.827144 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7668 23:24:22.830710 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7669 23:24:22.834064 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 23:24:22.840945 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 23:24:22.843676 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 23:24:22.847111 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 23:24:22.853991 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 23:24:22.857319 1 6 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7675 23:24:22.860708 1 6 20 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7676 23:24:22.863927 1 6 24 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
7677 23:24:22.870252 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 23:24:22.873916 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 23:24:22.876956 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 23:24:22.883555 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 23:24:22.886963 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7682 23:24:22.890332 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7683 23:24:22.897508 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7684 23:24:22.900284 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7685 23:24:22.903915 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 23:24:22.910678 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 23:24:22.914155 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 23:24:22.917392 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 23:24:22.923800 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 23:24:22.927603 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 23:24:22.930922 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 23:24:22.937056 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 23:24:22.940747 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 23:24:22.943997 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 23:24:22.950661 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 23:24:22.954141 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 23:24:22.957475 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 23:24:22.960837 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7699 23:24:22.967192 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7700 23:24:22.970562 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7701 23:24:22.973935 Total UI for P1: 0, mck2ui 16
7702 23:24:22.978097 best dqsien dly found for B0: ( 1, 9, 18)
7703 23:24:22.980579 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7704 23:24:22.983951 Total UI for P1: 0, mck2ui 16
7705 23:24:22.987341 best dqsien dly found for B1: ( 1, 9, 22)
7706 23:24:22.990588 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7707 23:24:22.993903 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7708 23:24:22.993980
7709 23:24:23.000864 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7710 23:24:23.003899 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7711 23:24:23.007403 [Gating] SW calibration Done
7712 23:24:23.007509 ==
7713 23:24:23.010642 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 23:24:23.014106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 23:24:23.014188 ==
7716 23:24:23.014252 RX Vref Scan: 0
7717 23:24:23.014311
7718 23:24:23.017058 RX Vref 0 -> 0, step: 1
7719 23:24:23.017140
7720 23:24:23.020604 RX Delay 0 -> 252, step: 8
7721 23:24:23.023957 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7722 23:24:23.027128 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7723 23:24:23.030604 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7724 23:24:23.037272 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7725 23:24:23.040680 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7726 23:24:23.044271 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7727 23:24:23.047524 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7728 23:24:23.050780 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7729 23:24:23.057299 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7730 23:24:23.060747 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7731 23:24:23.064131 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7732 23:24:23.067546 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7733 23:24:23.071094 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7734 23:24:23.077854 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7735 23:24:23.080679 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7736 23:24:23.083913 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7737 23:24:23.083993 ==
7738 23:24:23.087241 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 23:24:23.090719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 23:24:23.090800 ==
7741 23:24:23.093943 DQS Delay:
7742 23:24:23.094023 DQS0 = 0, DQS1 = 0
7743 23:24:23.097198 DQM Delay:
7744 23:24:23.097277 DQM0 = 131, DQM1 = 123
7745 23:24:23.100592 DQ Delay:
7746 23:24:23.104382 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
7747 23:24:23.107689 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7748 23:24:23.111119 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7749 23:24:23.114362 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7750 23:24:23.114475
7751 23:24:23.114540
7752 23:24:23.114598 ==
7753 23:24:23.117760 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 23:24:23.121005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 23:24:23.121123 ==
7756 23:24:23.121189
7757 23:24:23.121247
7758 23:24:23.124377 TX Vref Scan disable
7759 23:24:23.127821 == TX Byte 0 ==
7760 23:24:23.130653 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7761 23:24:23.134013 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7762 23:24:23.137526 == TX Byte 1 ==
7763 23:24:23.140869 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7764 23:24:23.144425 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7765 23:24:23.144505 ==
7766 23:24:23.147370 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 23:24:23.150910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 23:24:23.151021 ==
7769 23:24:23.167269
7770 23:24:23.170848 TX Vref early break, caculate TX vref
7771 23:24:23.174024 TX Vref=16, minBit 4, minWin=20, winSum=349
7772 23:24:23.176982 TX Vref=18, minBit 0, minWin=22, winSum=366
7773 23:24:23.180415 TX Vref=20, minBit 0, minWin=22, winSum=374
7774 23:24:23.183974 TX Vref=22, minBit 0, minWin=23, winSum=387
7775 23:24:23.187271 TX Vref=24, minBit 0, minWin=23, winSum=397
7776 23:24:23.193915 TX Vref=26, minBit 3, minWin=24, winSum=405
7777 23:24:23.197418 TX Vref=28, minBit 4, minWin=24, winSum=411
7778 23:24:23.200487 TX Vref=30, minBit 7, minWin=24, winSum=412
7779 23:24:23.204119 TX Vref=32, minBit 4, minWin=24, winSum=408
7780 23:24:23.207181 TX Vref=34, minBit 0, minWin=24, winSum=394
7781 23:24:23.210829 TX Vref=36, minBit 0, minWin=23, winSum=385
7782 23:24:23.217464 [TxChooseVref] Worse bit 7, Min win 24, Win sum 412, Final Vref 30
7783 23:24:23.217561
7784 23:24:23.220812 Final TX Range 0 Vref 30
7785 23:24:23.220918
7786 23:24:23.221050 ==
7787 23:24:23.224235 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 23:24:23.227178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 23:24:23.227258 ==
7790 23:24:23.227322
7791 23:24:23.227381
7792 23:24:23.231133 TX Vref Scan disable
7793 23:24:23.237215 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7794 23:24:23.237319 == TX Byte 0 ==
7795 23:24:23.240846 u2DelayCellOfst[0]=14 cells (4 PI)
7796 23:24:23.243688 u2DelayCellOfst[1]=17 cells (5 PI)
7797 23:24:23.247230 u2DelayCellOfst[2]=10 cells (3 PI)
7798 23:24:23.250519 u2DelayCellOfst[3]=10 cells (3 PI)
7799 23:24:23.253720 u2DelayCellOfst[4]=10 cells (3 PI)
7800 23:24:23.257116 u2DelayCellOfst[5]=0 cells (0 PI)
7801 23:24:23.260764 u2DelayCellOfst[6]=17 cells (5 PI)
7802 23:24:23.263910 u2DelayCellOfst[7]=17 cells (5 PI)
7803 23:24:23.267157 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7804 23:24:23.270803 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7805 23:24:23.273634 == TX Byte 1 ==
7806 23:24:23.277128 u2DelayCellOfst[8]=0 cells (0 PI)
7807 23:24:23.277211 u2DelayCellOfst[9]=0 cells (0 PI)
7808 23:24:23.280847 u2DelayCellOfst[10]=7 cells (2 PI)
7809 23:24:23.283826 u2DelayCellOfst[11]=0 cells (0 PI)
7810 23:24:23.286944 u2DelayCellOfst[12]=14 cells (4 PI)
7811 23:24:23.290334 u2DelayCellOfst[13]=10 cells (3 PI)
7812 23:24:23.293762 u2DelayCellOfst[14]=17 cells (5 PI)
7813 23:24:23.296965 u2DelayCellOfst[15]=10 cells (3 PI)
7814 23:24:23.300383 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7815 23:24:23.307025 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7816 23:24:23.307133 DramC Write-DBI on
7817 23:24:23.307224 ==
7818 23:24:23.310180 Dram Type= 6, Freq= 0, CH_0, rank 0
7819 23:24:23.313717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7820 23:24:23.317132 ==
7821 23:24:23.317213
7822 23:24:23.317276
7823 23:24:23.317335 TX Vref Scan disable
7824 23:24:23.320412 == TX Byte 0 ==
7825 23:24:23.323811 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7826 23:24:23.327113 == TX Byte 1 ==
7827 23:24:23.330533 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7828 23:24:23.334030 DramC Write-DBI off
7829 23:24:23.334109
7830 23:24:23.334172 [DATLAT]
7831 23:24:23.334230 Freq=1600, CH0 RK0
7832 23:24:23.334288
7833 23:24:23.336811 DATLAT Default: 0xf
7834 23:24:23.336912 0, 0xFFFF, sum = 0
7835 23:24:23.340442 1, 0xFFFF, sum = 0
7836 23:24:23.343681 2, 0xFFFF, sum = 0
7837 23:24:23.343762 3, 0xFFFF, sum = 0
7838 23:24:23.347172 4, 0xFFFF, sum = 0
7839 23:24:23.347253 5, 0xFFFF, sum = 0
7840 23:24:23.350662 6, 0xFFFF, sum = 0
7841 23:24:23.350744 7, 0xFFFF, sum = 0
7842 23:24:23.353933 8, 0xFFFF, sum = 0
7843 23:24:23.354014 9, 0xFFFF, sum = 0
7844 23:24:23.357403 10, 0xFFFF, sum = 0
7845 23:24:23.357484 11, 0xFFFF, sum = 0
7846 23:24:23.360769 12, 0xFFFF, sum = 0
7847 23:24:23.360850 13, 0xFFFF, sum = 0
7848 23:24:23.364351 14, 0x0, sum = 1
7849 23:24:23.364432 15, 0x0, sum = 2
7850 23:24:23.367076 16, 0x0, sum = 3
7851 23:24:23.367158 17, 0x0, sum = 4
7852 23:24:23.370427 best_step = 15
7853 23:24:23.370554
7854 23:24:23.370618 ==
7855 23:24:23.373695 Dram Type= 6, Freq= 0, CH_0, rank 0
7856 23:24:23.376969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7857 23:24:23.377049 ==
7858 23:24:23.377112 RX Vref Scan: 1
7859 23:24:23.380658
7860 23:24:23.380766 Set Vref Range= 24 -> 127
7861 23:24:23.380829
7862 23:24:23.383630 RX Vref 24 -> 127, step: 1
7863 23:24:23.383725
7864 23:24:23.387578 RX Delay 11 -> 252, step: 4
7865 23:24:23.387658
7866 23:24:23.390650 Set Vref, RX VrefLevel [Byte0]: 24
7867 23:24:23.393967 [Byte1]: 24
7868 23:24:23.394048
7869 23:24:23.397043 Set Vref, RX VrefLevel [Byte0]: 25
7870 23:24:23.400287 [Byte1]: 25
7871 23:24:23.400397
7872 23:24:23.403780 Set Vref, RX VrefLevel [Byte0]: 26
7873 23:24:23.407062 [Byte1]: 26
7874 23:24:23.411123
7875 23:24:23.411208 Set Vref, RX VrefLevel [Byte0]: 27
7876 23:24:23.414168 [Byte1]: 27
7877 23:24:23.418725
7878 23:24:23.418805 Set Vref, RX VrefLevel [Byte0]: 28
7879 23:24:23.422064 [Byte1]: 28
7880 23:24:23.426623
7881 23:24:23.426703 Set Vref, RX VrefLevel [Byte0]: 29
7882 23:24:23.429373 [Byte1]: 29
7883 23:24:23.433943
7884 23:24:23.434049 Set Vref, RX VrefLevel [Byte0]: 30
7885 23:24:23.436953 [Byte1]: 30
7886 23:24:23.441515
7887 23:24:23.441594 Set Vref, RX VrefLevel [Byte0]: 31
7888 23:24:23.444612 [Byte1]: 31
7889 23:24:23.449070
7890 23:24:23.449148 Set Vref, RX VrefLevel [Byte0]: 32
7891 23:24:23.452410 [Byte1]: 32
7892 23:24:23.456499
7893 23:24:23.456578 Set Vref, RX VrefLevel [Byte0]: 33
7894 23:24:23.459913 [Byte1]: 33
7895 23:24:23.464446
7896 23:24:23.464525 Set Vref, RX VrefLevel [Byte0]: 34
7897 23:24:23.467647 [Byte1]: 34
7898 23:24:23.471837
7899 23:24:23.471916 Set Vref, RX VrefLevel [Byte0]: 35
7900 23:24:23.474968 [Byte1]: 35
7901 23:24:23.479501
7902 23:24:23.479581 Set Vref, RX VrefLevel [Byte0]: 36
7903 23:24:23.482954 [Byte1]: 36
7904 23:24:23.487088
7905 23:24:23.487167 Set Vref, RX VrefLevel [Byte0]: 37
7906 23:24:23.490675 [Byte1]: 37
7907 23:24:23.494548
7908 23:24:23.494627 Set Vref, RX VrefLevel [Byte0]: 38
7909 23:24:23.497800 [Byte1]: 38
7910 23:24:23.502449
7911 23:24:23.502529 Set Vref, RX VrefLevel [Byte0]: 39
7912 23:24:23.505778 [Byte1]: 39
7913 23:24:23.509709
7914 23:24:23.509788 Set Vref, RX VrefLevel [Byte0]: 40
7915 23:24:23.513771 [Byte1]: 40
7916 23:24:23.517534
7917 23:24:23.517628 Set Vref, RX VrefLevel [Byte0]: 41
7918 23:24:23.520903 [Byte1]: 41
7919 23:24:23.525293
7920 23:24:23.525372 Set Vref, RX VrefLevel [Byte0]: 42
7921 23:24:23.528609 [Byte1]: 42
7922 23:24:23.532662
7923 23:24:23.532741 Set Vref, RX VrefLevel [Byte0]: 43
7924 23:24:23.536026 [Byte1]: 43
7925 23:24:23.540540
7926 23:24:23.540620 Set Vref, RX VrefLevel [Byte0]: 44
7927 23:24:23.543912 [Byte1]: 44
7928 23:24:23.547739
7929 23:24:23.547818 Set Vref, RX VrefLevel [Byte0]: 45
7930 23:24:23.551140 [Byte1]: 45
7931 23:24:23.555829
7932 23:24:23.555908 Set Vref, RX VrefLevel [Byte0]: 46
7933 23:24:23.559482 [Byte1]: 46
7934 23:24:23.562878
7935 23:24:23.562958 Set Vref, RX VrefLevel [Byte0]: 47
7936 23:24:23.567172 [Byte1]: 47
7937 23:24:23.570991
7938 23:24:23.571096 Set Vref, RX VrefLevel [Byte0]: 48
7939 23:24:23.574046 [Byte1]: 48
7940 23:24:23.578910
7941 23:24:23.578989 Set Vref, RX VrefLevel [Byte0]: 49
7942 23:24:23.581965 [Byte1]: 49
7943 23:24:23.585823
7944 23:24:23.585903 Set Vref, RX VrefLevel [Byte0]: 50
7945 23:24:23.589246 [Byte1]: 50
7946 23:24:23.593756
7947 23:24:23.593835 Set Vref, RX VrefLevel [Byte0]: 51
7948 23:24:23.597080 [Byte1]: 51
7949 23:24:23.601075
7950 23:24:23.601155 Set Vref, RX VrefLevel [Byte0]: 52
7951 23:24:23.604635 [Byte1]: 52
7952 23:24:23.608943
7953 23:24:23.609023 Set Vref, RX VrefLevel [Byte0]: 53
7954 23:24:23.612089 [Byte1]: 53
7955 23:24:23.616366
7956 23:24:23.616445 Set Vref, RX VrefLevel [Byte0]: 54
7957 23:24:23.619780 [Byte1]: 54
7958 23:24:23.624452
7959 23:24:23.624531 Set Vref, RX VrefLevel [Byte0]: 55
7960 23:24:23.627516 [Byte1]: 55
7961 23:24:23.631835
7962 23:24:23.631925 Set Vref, RX VrefLevel [Byte0]: 56
7963 23:24:23.634965 [Byte1]: 56
7964 23:24:23.639237
7965 23:24:23.639316 Set Vref, RX VrefLevel [Byte0]: 57
7966 23:24:23.642689 [Byte1]: 57
7967 23:24:23.647113
7968 23:24:23.647192 Set Vref, RX VrefLevel [Byte0]: 58
7969 23:24:23.650057 [Byte1]: 58
7970 23:24:23.654748
7971 23:24:23.654828 Set Vref, RX VrefLevel [Byte0]: 59
7972 23:24:23.657812 [Byte1]: 59
7973 23:24:23.662025
7974 23:24:23.662104 Set Vref, RX VrefLevel [Byte0]: 60
7975 23:24:23.665987 [Byte1]: 60
7976 23:24:23.669747
7977 23:24:23.669826 Set Vref, RX VrefLevel [Byte0]: 61
7978 23:24:23.673055 [Byte1]: 61
7979 23:24:23.677662
7980 23:24:23.677742 Set Vref, RX VrefLevel [Byte0]: 62
7981 23:24:23.680826 [Byte1]: 62
7982 23:24:23.685307
7983 23:24:23.685386 Set Vref, RX VrefLevel [Byte0]: 63
7984 23:24:23.688252 [Byte1]: 63
7985 23:24:23.692759
7986 23:24:23.692840 Set Vref, RX VrefLevel [Byte0]: 64
7987 23:24:23.695700 [Byte1]: 64
7988 23:24:23.700037
7989 23:24:23.700116 Set Vref, RX VrefLevel [Byte0]: 65
7990 23:24:23.703506 [Byte1]: 65
7991 23:24:23.707853
7992 23:24:23.707933 Set Vref, RX VrefLevel [Byte0]: 66
7993 23:24:23.711296 [Byte1]: 66
7994 23:24:23.715275
7995 23:24:23.715354 Set Vref, RX VrefLevel [Byte0]: 67
7996 23:24:23.718628 [Byte1]: 67
7997 23:24:23.723387
7998 23:24:23.723467 Set Vref, RX VrefLevel [Byte0]: 68
7999 23:24:23.726212 [Byte1]: 68
8000 23:24:23.730673
8001 23:24:23.730753 Set Vref, RX VrefLevel [Byte0]: 69
8002 23:24:23.733907 [Byte1]: 69
8003 23:24:23.738155
8004 23:24:23.738264 Set Vref, RX VrefLevel [Byte0]: 70
8005 23:24:23.741540 [Byte1]: 70
8006 23:24:23.745680
8007 23:24:23.745759 Set Vref, RX VrefLevel [Byte0]: 71
8008 23:24:23.749087 [Byte1]: 71
8009 23:24:23.753607
8010 23:24:23.753686 Set Vref, RX VrefLevel [Byte0]: 72
8011 23:24:23.757337 [Byte1]: 72
8012 23:24:23.761087
8013 23:24:23.761166 Set Vref, RX VrefLevel [Byte0]: 73
8014 23:24:23.764715 [Byte1]: 73
8015 23:24:23.768790
8016 23:24:23.768871 Set Vref, RX VrefLevel [Byte0]: 74
8017 23:24:23.771899 [Byte1]: 74
8018 23:24:23.776075
8019 23:24:23.776152 Set Vref, RX VrefLevel [Byte0]: 75
8020 23:24:23.780160 [Byte1]: 75
8021 23:24:23.783991
8022 23:24:23.784072 Set Vref, RX VrefLevel [Byte0]: 76
8023 23:24:23.787236 [Byte1]: 76
8024 23:24:23.791677
8025 23:24:23.791758 Final RX Vref Byte 0 = 63 to rank0
8026 23:24:23.794840 Final RX Vref Byte 1 = 62 to rank0
8027 23:24:23.798081 Final RX Vref Byte 0 = 63 to rank1
8028 23:24:23.801315 Final RX Vref Byte 1 = 62 to rank1==
8029 23:24:23.804992 Dram Type= 6, Freq= 0, CH_0, rank 0
8030 23:24:23.811658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 23:24:23.811744 ==
8032 23:24:23.811808 DQS Delay:
8033 23:24:23.811868 DQS0 = 0, DQS1 = 0
8034 23:24:23.814749 DQM Delay:
8035 23:24:23.814829 DQM0 = 130, DQM1 = 121
8036 23:24:23.818669 DQ Delay:
8037 23:24:23.821768 DQ0 =132, DQ1 =132, DQ2 =126, DQ3 =126
8038 23:24:23.825410 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8039 23:24:23.828108 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
8040 23:24:23.831867 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8041 23:24:23.831942
8042 23:24:23.832003
8043 23:24:23.832060
8044 23:24:23.834529 [DramC_TX_OE_Calibration] TA2
8045 23:24:23.837905 Original DQ_B0 (3 6) =30, OEN = 27
8046 23:24:23.841209 Original DQ_B1 (3 6) =30, OEN = 27
8047 23:24:23.844831 24, 0x0, End_B0=24 End_B1=24
8048 23:24:23.844912 25, 0x0, End_B0=25 End_B1=25
8049 23:24:23.848050 26, 0x0, End_B0=26 End_B1=26
8050 23:24:23.851812 27, 0x0, End_B0=27 End_B1=27
8051 23:24:23.854838 28, 0x0, End_B0=28 End_B1=28
8052 23:24:23.854924 29, 0x0, End_B0=29 End_B1=29
8053 23:24:23.858209 30, 0x0, End_B0=30 End_B1=30
8054 23:24:23.861473 31, 0x4141, End_B0=30 End_B1=30
8055 23:24:23.864687 Byte0 end_step=30 best_step=27
8056 23:24:23.868751 Byte1 end_step=30 best_step=27
8057 23:24:23.871474 Byte0 TX OE(2T, 0.5T) = (3, 3)
8058 23:24:23.871554 Byte1 TX OE(2T, 0.5T) = (3, 3)
8059 23:24:23.871617
8060 23:24:23.874687
8061 23:24:23.881551 [DQSOSCAuto] RK0, (LSB)MR18= 0x1105, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
8062 23:24:23.884551 CH0 RK0: MR19=303, MR18=1105
8063 23:24:23.891806 CH0_RK0: MR19=0x303, MR18=0x1105, DQSOSC=401, MR23=63, INC=22, DEC=15
8064 23:24:23.891889
8065 23:24:23.894933 ----->DramcWriteLeveling(PI) begin...
8066 23:24:23.895015 ==
8067 23:24:23.897981 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 23:24:23.901484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 23:24:23.901566 ==
8070 23:24:23.904754 Write leveling (Byte 0): 34 => 34
8071 23:24:23.908696 Write leveling (Byte 1): 27 => 27
8072 23:24:23.911373 DramcWriteLeveling(PI) end<-----
8073 23:24:23.911468
8074 23:24:23.911561 ==
8075 23:24:23.914700 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 23:24:23.918168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 23:24:23.918250 ==
8078 23:24:23.921661 [Gating] SW mode calibration
8079 23:24:23.928279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8080 23:24:23.934706 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8081 23:24:23.937923 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 23:24:23.941498 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 23:24:23.948327 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8084 23:24:23.951196 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8085 23:24:23.954586 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8086 23:24:23.961480 1 4 20 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8087 23:24:23.964719 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8088 23:24:23.968322 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8089 23:24:23.974861 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8090 23:24:23.978031 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8091 23:24:23.981388 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
8092 23:24:23.988434 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8093 23:24:23.991506 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8094 23:24:23.994481 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8095 23:24:23.997836 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 23:24:24.004601 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 23:24:24.007902 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 23:24:24.011408 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 23:24:24.018231 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8100 23:24:24.020985 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8101 23:24:24.024750 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8102 23:24:24.031734 1 6 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8103 23:24:24.034767 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 23:24:24.037719 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 23:24:24.044916 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 23:24:24.048181 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 23:24:24.051586 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8108 23:24:24.058115 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8109 23:24:24.061107 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8110 23:24:24.064569 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8111 23:24:24.071399 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8112 23:24:24.074901 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 23:24:24.077773 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 23:24:24.084415 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 23:24:24.087635 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 23:24:24.091325 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 23:24:24.095156 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 23:24:24.101465 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 23:24:24.104784 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 23:24:24.108057 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 23:24:24.114542 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 23:24:24.118031 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 23:24:24.121607 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8124 23:24:24.128575 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8125 23:24:24.128657 Total UI for P1: 0, mck2ui 16
8126 23:24:24.134647 best dqsien dly found for B0: ( 1, 9, 8)
8127 23:24:24.138159 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8128 23:24:24.141439 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8129 23:24:24.147966 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8130 23:24:24.148048 Total UI for P1: 0, mck2ui 16
8131 23:24:24.154956 best dqsien dly found for B1: ( 1, 9, 18)
8132 23:24:24.157881 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8133 23:24:24.161285 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8134 23:24:24.161364
8135 23:24:24.165042 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8136 23:24:24.168008 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8137 23:24:24.171435 [Gating] SW calibration Done
8138 23:24:24.171515 ==
8139 23:24:24.175351 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 23:24:24.178087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 23:24:24.178168 ==
8142 23:24:24.181775 RX Vref Scan: 0
8143 23:24:24.181855
8144 23:24:24.181917 RX Vref 0 -> 0, step: 1
8145 23:24:24.181975
8146 23:24:24.184832 RX Delay 0 -> 252, step: 8
8147 23:24:24.188050 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8148 23:24:24.191367 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8149 23:24:24.197991 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8150 23:24:24.201603 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8151 23:24:24.205051 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8152 23:24:24.208486 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8153 23:24:24.211848 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8154 23:24:24.218150 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8155 23:24:24.221697 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8156 23:24:24.225478 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8157 23:24:24.228828 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8158 23:24:24.231564 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8159 23:24:24.238194 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8160 23:24:24.241529 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8161 23:24:24.244995 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8162 23:24:24.248331 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8163 23:24:24.248401 ==
8164 23:24:24.251743 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 23:24:24.254850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 23:24:24.258458 ==
8167 23:24:24.258532 DQS Delay:
8168 23:24:24.258597 DQS0 = 0, DQS1 = 0
8169 23:24:24.261578 DQM Delay:
8170 23:24:24.261647 DQM0 = 131, DQM1 = 123
8171 23:24:24.264975 DQ Delay:
8172 23:24:24.268323 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
8173 23:24:24.271683 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8174 23:24:24.275113 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =115
8175 23:24:24.278349 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8176 23:24:24.278456
8177 23:24:24.278526
8178 23:24:24.278624 ==
8179 23:24:24.281811 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 23:24:24.285143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 23:24:24.285211 ==
8182 23:24:24.285270
8183 23:24:24.285329
8184 23:24:24.288644 TX Vref Scan disable
8185 23:24:24.291768 == TX Byte 0 ==
8186 23:24:24.295032 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8187 23:24:24.298394 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8188 23:24:24.302185 == TX Byte 1 ==
8189 23:24:24.305411 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8190 23:24:24.308710 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8191 23:24:24.308784 ==
8192 23:24:24.312021 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 23:24:24.315325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 23:24:24.318532 ==
8195 23:24:24.331680
8196 23:24:24.334755 TX Vref early break, caculate TX vref
8197 23:24:24.338578 TX Vref=16, minBit 4, minWin=22, winSum=366
8198 23:24:24.342069 TX Vref=18, minBit 0, minWin=23, winSum=380
8199 23:24:24.345268 TX Vref=20, minBit 0, minWin=23, winSum=387
8200 23:24:24.348203 TX Vref=22, minBit 0, minWin=23, winSum=393
8201 23:24:24.351718 TX Vref=24, minBit 12, minWin=24, winSum=405
8202 23:24:24.359010 TX Vref=26, minBit 2, minWin=25, winSum=417
8203 23:24:24.361551 TX Vref=28, minBit 0, minWin=25, winSum=418
8204 23:24:24.365127 TX Vref=30, minBit 0, minWin=25, winSum=414
8205 23:24:24.368412 TX Vref=32, minBit 0, minWin=25, winSum=407
8206 23:24:24.371809 TX Vref=34, minBit 0, minWin=24, winSum=400
8207 23:24:24.375197 TX Vref=36, minBit 4, minWin=23, winSum=393
8208 23:24:24.381669 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8209 23:24:24.381748
8210 23:24:24.385272 Final TX Range 0 Vref 28
8211 23:24:24.385344
8212 23:24:24.385407 ==
8213 23:24:24.387967 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 23:24:24.391285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 23:24:24.391359 ==
8216 23:24:24.391421
8217 23:24:24.394766
8218 23:24:24.394833 TX Vref Scan disable
8219 23:24:24.401619 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8220 23:24:24.401704 == TX Byte 0 ==
8221 23:24:24.404638 u2DelayCellOfst[0]=10 cells (3 PI)
8222 23:24:24.407971 u2DelayCellOfst[1]=14 cells (4 PI)
8223 23:24:24.411250 u2DelayCellOfst[2]=7 cells (2 PI)
8224 23:24:24.414829 u2DelayCellOfst[3]=7 cells (2 PI)
8225 23:24:24.417874 u2DelayCellOfst[4]=7 cells (2 PI)
8226 23:24:24.421353 u2DelayCellOfst[5]=0 cells (0 PI)
8227 23:24:24.424880 u2DelayCellOfst[6]=14 cells (4 PI)
8228 23:24:24.427994 u2DelayCellOfst[7]=14 cells (4 PI)
8229 23:24:24.431109 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8230 23:24:24.434656 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8231 23:24:24.437670 == TX Byte 1 ==
8232 23:24:24.440986 u2DelayCellOfst[8]=0 cells (0 PI)
8233 23:24:24.445187 u2DelayCellOfst[9]=0 cells (0 PI)
8234 23:24:24.445270 u2DelayCellOfst[10]=7 cells (2 PI)
8235 23:24:24.447595 u2DelayCellOfst[11]=0 cells (0 PI)
8236 23:24:24.451117 u2DelayCellOfst[12]=14 cells (4 PI)
8237 23:24:24.454741 u2DelayCellOfst[13]=10 cells (3 PI)
8238 23:24:24.458049 u2DelayCellOfst[14]=14 cells (4 PI)
8239 23:24:24.461104 u2DelayCellOfst[15]=10 cells (3 PI)
8240 23:24:24.467833 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8241 23:24:24.471073 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8242 23:24:24.471162 DramC Write-DBI on
8243 23:24:24.471226 ==
8244 23:24:24.474587 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 23:24:24.481571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 23:24:24.481652 ==
8247 23:24:24.481715
8248 23:24:24.481775
8249 23:24:24.481832 TX Vref Scan disable
8250 23:24:24.484904 == TX Byte 0 ==
8251 23:24:24.488720 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8252 23:24:24.491697 == TX Byte 1 ==
8253 23:24:24.495017 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8254 23:24:24.498575 DramC Write-DBI off
8255 23:24:24.498654
8256 23:24:24.498716 [DATLAT]
8257 23:24:24.498774 Freq=1600, CH0 RK1
8258 23:24:24.498832
8259 23:24:24.501614 DATLAT Default: 0xf
8260 23:24:24.501694 0, 0xFFFF, sum = 0
8261 23:24:24.504908 1, 0xFFFF, sum = 0
8262 23:24:24.505027 2, 0xFFFF, sum = 0
8263 23:24:24.508330 3, 0xFFFF, sum = 0
8264 23:24:24.511906 4, 0xFFFF, sum = 0
8265 23:24:24.511987 5, 0xFFFF, sum = 0
8266 23:24:24.515240 6, 0xFFFF, sum = 0
8267 23:24:24.515348 7, 0xFFFF, sum = 0
8268 23:24:24.518559 8, 0xFFFF, sum = 0
8269 23:24:24.518641 9, 0xFFFF, sum = 0
8270 23:24:24.521617 10, 0xFFFF, sum = 0
8271 23:24:24.521697 11, 0xFFFF, sum = 0
8272 23:24:24.525338 12, 0xFFFF, sum = 0
8273 23:24:24.525430 13, 0xFFFF, sum = 0
8274 23:24:24.528764 14, 0x0, sum = 1
8275 23:24:24.528850 15, 0x0, sum = 2
8276 23:24:24.532298 16, 0x0, sum = 3
8277 23:24:24.532394 17, 0x0, sum = 4
8278 23:24:24.535244 best_step = 15
8279 23:24:24.535324
8280 23:24:24.535396 ==
8281 23:24:24.538675 Dram Type= 6, Freq= 0, CH_0, rank 1
8282 23:24:24.541986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 23:24:24.542066 ==
8284 23:24:24.542129 RX Vref Scan: 0
8285 23:24:24.542188
8286 23:24:24.544901 RX Vref 0 -> 0, step: 1
8287 23:24:24.544981
8288 23:24:24.548615 RX Delay 11 -> 252, step: 4
8289 23:24:24.552159 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8290 23:24:24.558310 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8291 23:24:24.561698 iDelay=191, Bit 2, Center 126 (71 ~ 182) 112
8292 23:24:24.565310 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8293 23:24:24.568731 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8294 23:24:24.572013 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8295 23:24:24.575104 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8296 23:24:24.581779 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8297 23:24:24.585249 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8298 23:24:24.588718 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8299 23:24:24.591687 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8300 23:24:24.595470 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8301 23:24:24.602040 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8302 23:24:24.605277 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8303 23:24:24.608585 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8304 23:24:24.611814 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8305 23:24:24.611894 ==
8306 23:24:24.615214 Dram Type= 6, Freq= 0, CH_0, rank 1
8307 23:24:24.621906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 23:24:24.621987 ==
8309 23:24:24.622050 DQS Delay:
8310 23:24:24.622148 DQS0 = 0, DQS1 = 0
8311 23:24:24.625316 DQM Delay:
8312 23:24:24.625397 DQM0 = 128, DQM1 = 122
8313 23:24:24.628594 DQ Delay:
8314 23:24:24.631762 DQ0 =126, DQ1 =130, DQ2 =126, DQ3 =126
8315 23:24:24.635209 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8316 23:24:24.638577 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8317 23:24:24.642279 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8318 23:24:24.642406
8319 23:24:24.642486
8320 23:24:24.642545
8321 23:24:24.645601 [DramC_TX_OE_Calibration] TA2
8322 23:24:24.648561 Original DQ_B0 (3 6) =30, OEN = 27
8323 23:24:24.652014 Original DQ_B1 (3 6) =30, OEN = 27
8324 23:24:24.655496 24, 0x0, End_B0=24 End_B1=24
8325 23:24:24.655577 25, 0x0, End_B0=25 End_B1=25
8326 23:24:24.658882 26, 0x0, End_B0=26 End_B1=26
8327 23:24:24.662372 27, 0x0, End_B0=27 End_B1=27
8328 23:24:24.665525 28, 0x0, End_B0=28 End_B1=28
8329 23:24:24.665623 29, 0x0, End_B0=29 End_B1=29
8330 23:24:24.668668 30, 0x0, End_B0=30 End_B1=30
8331 23:24:24.672082 31, 0x4141, End_B0=30 End_B1=30
8332 23:24:24.675236 Byte0 end_step=30 best_step=27
8333 23:24:24.678822 Byte1 end_step=30 best_step=27
8334 23:24:24.682117 Byte0 TX OE(2T, 0.5T) = (3, 3)
8335 23:24:24.682197 Byte1 TX OE(2T, 0.5T) = (3, 3)
8336 23:24:24.682260
8337 23:24:24.685327
8338 23:24:24.692088 [DQSOSCAuto] RK1, (LSB)MR18= 0x150b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8339 23:24:24.695212 CH0 RK1: MR19=303, MR18=150B
8340 23:24:24.702239 CH0_RK1: MR19=0x303, MR18=0x150B, DQSOSC=399, MR23=63, INC=23, DEC=15
8341 23:24:24.702321 [RxdqsGatingPostProcess] freq 1600
8342 23:24:24.708797 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8343 23:24:24.712106 best DQS0 dly(2T, 0.5T) = (1, 1)
8344 23:24:24.715736 best DQS1 dly(2T, 0.5T) = (1, 1)
8345 23:24:24.718837 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8346 23:24:24.722197 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8347 23:24:24.725726 best DQS0 dly(2T, 0.5T) = (1, 1)
8348 23:24:24.729194 best DQS1 dly(2T, 0.5T) = (1, 1)
8349 23:24:24.732750 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8350 23:24:24.732830 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8351 23:24:24.735846 Pre-setting of DQS Precalculation
8352 23:24:24.742315 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8353 23:24:24.742406 ==
8354 23:24:24.745327 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 23:24:24.748943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 23:24:24.749025 ==
8357 23:24:24.755717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8358 23:24:24.759014 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8359 23:24:24.762076 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8360 23:24:24.769083 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8361 23:24:24.778241 [CA 0] Center 42 (14~71) winsize 58
8362 23:24:24.781805 [CA 1] Center 42 (13~71) winsize 59
8363 23:24:24.784552 [CA 2] Center 37 (9~66) winsize 58
8364 23:24:24.788095 [CA 3] Center 36 (7~66) winsize 60
8365 23:24:24.791472 [CA 4] Center 37 (8~66) winsize 59
8366 23:24:24.794814 [CA 5] Center 36 (7~65) winsize 59
8367 23:24:24.794903
8368 23:24:24.798171 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8369 23:24:24.798259
8370 23:24:24.801533 [CATrainingPosCal] consider 1 rank data
8371 23:24:24.804996 u2DelayCellTimex100 = 275/100 ps
8372 23:24:24.808528 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8373 23:24:24.815219 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8374 23:24:24.818184 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8375 23:24:24.821502 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8376 23:24:24.824973 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8377 23:24:24.828625 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8378 23:24:24.828705
8379 23:24:24.831296 CA PerBit enable=1, Macro0, CA PI delay=36
8380 23:24:24.831375
8381 23:24:24.834681 [CBTSetCACLKResult] CA Dly = 36
8382 23:24:24.834760 CS Dly: 9 (0~40)
8383 23:24:24.841454 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8384 23:24:24.844697 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8385 23:24:24.844776 ==
8386 23:24:24.848461 Dram Type= 6, Freq= 0, CH_1, rank 1
8387 23:24:24.851560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 23:24:24.851641 ==
8389 23:24:24.858170 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8390 23:24:24.861785 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8391 23:24:24.867949 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8392 23:24:24.871687 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8393 23:24:24.881014 [CA 0] Center 43 (14~72) winsize 59
8394 23:24:24.884920 [CA 1] Center 43 (14~72) winsize 59
8395 23:24:24.887798 [CA 2] Center 38 (9~67) winsize 59
8396 23:24:24.891844 [CA 3] Center 37 (8~66) winsize 59
8397 23:24:24.894376 [CA 4] Center 37 (8~67) winsize 60
8398 23:24:24.897915 [CA 5] Center 36 (7~66) winsize 60
8399 23:24:24.897999
8400 23:24:24.901506 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8401 23:24:24.901585
8402 23:24:24.904580 [CATrainingPosCal] consider 2 rank data
8403 23:24:24.907845 u2DelayCellTimex100 = 275/100 ps
8404 23:24:24.911369 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8405 23:24:24.917831 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8406 23:24:24.921256 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8407 23:24:24.924473 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8408 23:24:24.928178 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8409 23:24:24.931507 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8410 23:24:24.931587
8411 23:24:24.934620 CA PerBit enable=1, Macro0, CA PI delay=36
8412 23:24:24.934699
8413 23:24:24.938489 [CBTSetCACLKResult] CA Dly = 36
8414 23:24:24.938568 CS Dly: 11 (0~44)
8415 23:24:24.944521 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8416 23:24:24.948086 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8417 23:24:24.948166
8418 23:24:24.951449 ----->DramcWriteLeveling(PI) begin...
8419 23:24:24.951544 ==
8420 23:24:24.954535 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 23:24:24.958092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 23:24:24.958172 ==
8423 23:24:24.961630 Write leveling (Byte 0): 24 => 24
8424 23:24:24.965078 Write leveling (Byte 1): 30 => 30
8425 23:24:24.968096 DramcWriteLeveling(PI) end<-----
8426 23:24:24.968175
8427 23:24:24.968253 ==
8428 23:24:24.971324 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 23:24:24.978090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 23:24:24.978176 ==
8431 23:24:24.978240 [Gating] SW mode calibration
8432 23:24:24.987726 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8433 23:24:24.991291 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8434 23:24:24.994729 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 23:24:25.001508 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 23:24:25.004705 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 23:24:25.008102 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 23:24:25.014684 1 4 16 | B1->B0 | 2d2d 2625 | 1 1 | (1 1) (0 0)
8439 23:24:25.018142 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8440 23:24:25.021419 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 23:24:25.027952 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 23:24:25.031349 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 23:24:25.034844 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 23:24:25.041258 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8445 23:24:25.045033 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8446 23:24:25.048208 1 5 16 | B1->B0 | 2929 3131 | 1 0 | (1 0) (0 1)
8447 23:24:25.054632 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 23:24:25.058065 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 23:24:25.061214 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 23:24:25.068128 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 23:24:25.071560 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 23:24:25.074587 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 23:24:25.077750 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8454 23:24:25.084734 1 6 16 | B1->B0 | 3434 2e2e | 1 0 | (0 0) (0 0)
8455 23:24:25.088076 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 23:24:25.091314 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 23:24:25.098148 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 23:24:25.101687 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 23:24:25.104476 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 23:24:25.111612 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 23:24:25.114634 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 23:24:25.118318 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8463 23:24:25.124388 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 23:24:25.128043 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8465 23:24:25.131459 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 23:24:25.138341 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 23:24:25.141453 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 23:24:25.144580 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 23:24:25.151704 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 23:24:25.155055 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 23:24:25.157900 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 23:24:25.161401 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 23:24:25.167838 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 23:24:25.171459 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 23:24:25.174801 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 23:24:25.181525 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 23:24:25.184715 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8478 23:24:25.187896 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8479 23:24:25.194551 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8480 23:24:25.197982 Total UI for P1: 0, mck2ui 16
8481 23:24:25.201553 best dqsien dly found for B0: ( 1, 9, 16)
8482 23:24:25.201634 Total UI for P1: 0, mck2ui 16
8483 23:24:25.208508 best dqsien dly found for B1: ( 1, 9, 14)
8484 23:24:25.211978 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8485 23:24:25.214553 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8486 23:24:25.214634
8487 23:24:25.218270 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8488 23:24:25.221513 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8489 23:24:25.224838 [Gating] SW calibration Done
8490 23:24:25.224918 ==
8491 23:24:25.228245 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 23:24:25.231537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 23:24:25.231643 ==
8494 23:24:25.234890 RX Vref Scan: 0
8495 23:24:25.234970
8496 23:24:25.235033 RX Vref 0 -> 0, step: 1
8497 23:24:25.235092
8498 23:24:25.238089 RX Delay 0 -> 252, step: 8
8499 23:24:25.241568 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8500 23:24:25.248395 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8501 23:24:25.251184 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8502 23:24:25.254642 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8503 23:24:25.258139 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8504 23:24:25.261602 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8505 23:24:25.268198 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8506 23:24:25.271313 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8507 23:24:25.275404 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8508 23:24:25.278084 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8509 23:24:25.281450 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8510 23:24:25.288123 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8511 23:24:25.291148 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8512 23:24:25.295207 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8513 23:24:25.298134 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8514 23:24:25.301344 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8515 23:24:25.301425 ==
8516 23:24:25.304876 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 23:24:25.311927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 23:24:25.312009 ==
8519 23:24:25.312073 DQS Delay:
8520 23:24:25.314764 DQS0 = 0, DQS1 = 0
8521 23:24:25.314846 DQM Delay:
8522 23:24:25.314910 DQM0 = 135, DQM1 = 126
8523 23:24:25.318314 DQ Delay:
8524 23:24:25.321530 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8525 23:24:25.324961 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8526 23:24:25.328295 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8527 23:24:25.331436 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131
8528 23:24:25.331518
8529 23:24:25.331581
8530 23:24:25.331641 ==
8531 23:24:25.334376 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 23:24:25.341217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 23:24:25.341298 ==
8534 23:24:25.341360
8535 23:24:25.341417
8536 23:24:25.341473 TX Vref Scan disable
8537 23:24:25.344415 == TX Byte 0 ==
8538 23:24:25.347912 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8539 23:24:25.351402 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8540 23:24:25.354585 == TX Byte 1 ==
8541 23:24:25.357962 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8542 23:24:25.364472 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8543 23:24:25.364553 ==
8544 23:24:25.368134 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 23:24:25.370930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 23:24:25.371011 ==
8547 23:24:25.384870
8548 23:24:25.388361 TX Vref early break, caculate TX vref
8549 23:24:25.391464 TX Vref=16, minBit 8, minWin=21, winSum=361
8550 23:24:25.395252 TX Vref=18, minBit 8, minWin=21, winSum=372
8551 23:24:25.398497 TX Vref=20, minBit 8, minWin=22, winSum=382
8552 23:24:25.401684 TX Vref=22, minBit 8, minWin=23, winSum=393
8553 23:24:25.405159 TX Vref=24, minBit 5, minWin=24, winSum=402
8554 23:24:25.412151 TX Vref=26, minBit 11, minWin=24, winSum=415
8555 23:24:25.415319 TX Vref=28, minBit 8, minWin=25, winSum=420
8556 23:24:25.418190 TX Vref=30, minBit 15, minWin=24, winSum=416
8557 23:24:25.421778 TX Vref=32, minBit 8, minWin=24, winSum=408
8558 23:24:25.425483 TX Vref=34, minBit 0, minWin=24, winSum=399
8559 23:24:25.428679 TX Vref=36, minBit 3, minWin=23, winSum=385
8560 23:24:25.434814 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 28
8561 23:24:25.434899
8562 23:24:25.438710 Final TX Range 0 Vref 28
8563 23:24:25.438792
8564 23:24:25.438856 ==
8565 23:24:25.441443 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 23:24:25.445133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 23:24:25.445215 ==
8568 23:24:25.445309
8569 23:24:25.445369
8570 23:24:25.448512 TX Vref Scan disable
8571 23:24:25.455098 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8572 23:24:25.455181 == TX Byte 0 ==
8573 23:24:25.458626 u2DelayCellOfst[0]=17 cells (5 PI)
8574 23:24:25.461569 u2DelayCellOfst[1]=10 cells (3 PI)
8575 23:24:25.464940 u2DelayCellOfst[2]=0 cells (0 PI)
8576 23:24:25.468450 u2DelayCellOfst[3]=7 cells (2 PI)
8577 23:24:25.471991 u2DelayCellOfst[4]=7 cells (2 PI)
8578 23:24:25.475124 u2DelayCellOfst[5]=17 cells (5 PI)
8579 23:24:25.478651 u2DelayCellOfst[6]=17 cells (5 PI)
8580 23:24:25.482205 u2DelayCellOfst[7]=7 cells (2 PI)
8581 23:24:25.485384 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8582 23:24:25.488713 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8583 23:24:25.491845 == TX Byte 1 ==
8584 23:24:25.491926 u2DelayCellOfst[8]=0 cells (0 PI)
8585 23:24:25.495434 u2DelayCellOfst[9]=3 cells (1 PI)
8586 23:24:25.498737 u2DelayCellOfst[10]=7 cells (2 PI)
8587 23:24:25.501539 u2DelayCellOfst[11]=3 cells (1 PI)
8588 23:24:25.505340 u2DelayCellOfst[12]=10 cells (3 PI)
8589 23:24:25.508664 u2DelayCellOfst[13]=14 cells (4 PI)
8590 23:24:25.511756 u2DelayCellOfst[14]=14 cells (4 PI)
8591 23:24:25.515098 u2DelayCellOfst[15]=14 cells (4 PI)
8592 23:24:25.518319 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8593 23:24:25.524864 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8594 23:24:25.524945 DramC Write-DBI on
8595 23:24:25.525009 ==
8596 23:24:25.528808 Dram Type= 6, Freq= 0, CH_1, rank 0
8597 23:24:25.532266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8598 23:24:25.532348 ==
8599 23:24:25.535037
8600 23:24:25.535117
8601 23:24:25.535180 TX Vref Scan disable
8602 23:24:25.538476 == TX Byte 0 ==
8603 23:24:25.541831 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8604 23:24:25.545174 == TX Byte 1 ==
8605 23:24:25.548748 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8606 23:24:25.548834 DramC Write-DBI off
8607 23:24:25.548897
8608 23:24:25.551582 [DATLAT]
8609 23:24:25.551662 Freq=1600, CH1 RK0
8610 23:24:25.551726
8611 23:24:25.554957 DATLAT Default: 0xf
8612 23:24:25.555037 0, 0xFFFF, sum = 0
8613 23:24:25.558363 1, 0xFFFF, sum = 0
8614 23:24:25.558489 2, 0xFFFF, sum = 0
8615 23:24:25.561876 3, 0xFFFF, sum = 0
8616 23:24:25.561958 4, 0xFFFF, sum = 0
8617 23:24:25.565275 5, 0xFFFF, sum = 0
8618 23:24:25.565356 6, 0xFFFF, sum = 0
8619 23:24:25.568656 7, 0xFFFF, sum = 0
8620 23:24:25.568737 8, 0xFFFF, sum = 0
8621 23:24:25.571886 9, 0xFFFF, sum = 0
8622 23:24:25.575551 10, 0xFFFF, sum = 0
8623 23:24:25.575633 11, 0xFFFF, sum = 0
8624 23:24:25.578492 12, 0xFFFF, sum = 0
8625 23:24:25.578615 13, 0xFFFF, sum = 0
8626 23:24:25.582086 14, 0x0, sum = 1
8627 23:24:25.582168 15, 0x0, sum = 2
8628 23:24:25.585428 16, 0x0, sum = 3
8629 23:24:25.585509 17, 0x0, sum = 4
8630 23:24:25.585573 best_step = 15
8631 23:24:25.585633
8632 23:24:25.588548 ==
8633 23:24:25.592032 Dram Type= 6, Freq= 0, CH_1, rank 0
8634 23:24:25.595219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8635 23:24:25.595299 ==
8636 23:24:25.595363 RX Vref Scan: 1
8637 23:24:25.595423
8638 23:24:25.598871 Set Vref Range= 24 -> 127
8639 23:24:25.598951
8640 23:24:25.601889 RX Vref 24 -> 127, step: 1
8641 23:24:25.601970
8642 23:24:25.605489 RX Delay 19 -> 252, step: 4
8643 23:24:25.605569
8644 23:24:25.608996 Set Vref, RX VrefLevel [Byte0]: 24
8645 23:24:25.611721 [Byte1]: 24
8646 23:24:25.611802
8647 23:24:25.615176 Set Vref, RX VrefLevel [Byte0]: 25
8648 23:24:25.619101 [Byte1]: 25
8649 23:24:25.619181
8650 23:24:25.622303 Set Vref, RX VrefLevel [Byte0]: 26
8651 23:24:25.625462 [Byte1]: 26
8652 23:24:25.628982
8653 23:24:25.629062 Set Vref, RX VrefLevel [Byte0]: 27
8654 23:24:25.632375 [Byte1]: 27
8655 23:24:25.636145
8656 23:24:25.636225 Set Vref, RX VrefLevel [Byte0]: 28
8657 23:24:25.639368 [Byte1]: 28
8658 23:24:25.643608
8659 23:24:25.643688 Set Vref, RX VrefLevel [Byte0]: 29
8660 23:24:25.646776 [Byte1]: 29
8661 23:24:25.651798
8662 23:24:25.651878 Set Vref, RX VrefLevel [Byte0]: 30
8663 23:24:25.654581 [Byte1]: 30
8664 23:24:25.658607
8665 23:24:25.658688 Set Vref, RX VrefLevel [Byte0]: 31
8666 23:24:25.662168 [Byte1]: 31
8667 23:24:25.666563
8668 23:24:25.666643 Set Vref, RX VrefLevel [Byte0]: 32
8669 23:24:25.670026 [Byte1]: 32
8670 23:24:25.673919
8671 23:24:25.674000 Set Vref, RX VrefLevel [Byte0]: 33
8672 23:24:25.677485 [Byte1]: 33
8673 23:24:25.681703
8674 23:24:25.681783 Set Vref, RX VrefLevel [Byte0]: 34
8675 23:24:25.684623 [Byte1]: 34
8676 23:24:25.689205
8677 23:24:25.689285 Set Vref, RX VrefLevel [Byte0]: 35
8678 23:24:25.692714 [Byte1]: 35
8679 23:24:25.696966
8680 23:24:25.697050 Set Vref, RX VrefLevel [Byte0]: 36
8681 23:24:25.700146 [Byte1]: 36
8682 23:24:25.704385
8683 23:24:25.704465 Set Vref, RX VrefLevel [Byte0]: 37
8684 23:24:25.708071 [Byte1]: 37
8685 23:24:25.711607
8686 23:24:25.711690 Set Vref, RX VrefLevel [Byte0]: 38
8687 23:24:25.715336 [Byte1]: 38
8688 23:24:25.719312
8689 23:24:25.719392 Set Vref, RX VrefLevel [Byte0]: 39
8690 23:24:25.722715 [Byte1]: 39
8691 23:24:25.726903
8692 23:24:25.726982 Set Vref, RX VrefLevel [Byte0]: 40
8693 23:24:25.730195 [Byte1]: 40
8694 23:24:25.734577
8695 23:24:25.734657 Set Vref, RX VrefLevel [Byte0]: 41
8696 23:24:25.737597 [Byte1]: 41
8697 23:24:25.742140
8698 23:24:25.742220 Set Vref, RX VrefLevel [Byte0]: 42
8699 23:24:25.745403 [Byte1]: 42
8700 23:24:25.750159
8701 23:24:25.750240 Set Vref, RX VrefLevel [Byte0]: 43
8702 23:24:25.753958 [Byte1]: 43
8703 23:24:25.757102
8704 23:24:25.757181 Set Vref, RX VrefLevel [Byte0]: 44
8705 23:24:25.760963 [Byte1]: 44
8706 23:24:25.765040
8707 23:24:25.765119 Set Vref, RX VrefLevel [Byte0]: 45
8708 23:24:25.767908 [Byte1]: 45
8709 23:24:25.772213
8710 23:24:25.772293 Set Vref, RX VrefLevel [Byte0]: 46
8711 23:24:25.775808 [Byte1]: 46
8712 23:24:25.780248
8713 23:24:25.780328 Set Vref, RX VrefLevel [Byte0]: 47
8714 23:24:25.783225 [Byte1]: 47
8715 23:24:25.787291
8716 23:24:25.787371 Set Vref, RX VrefLevel [Byte0]: 48
8717 23:24:25.791084 [Byte1]: 48
8718 23:24:25.795062
8719 23:24:25.795142 Set Vref, RX VrefLevel [Byte0]: 49
8720 23:24:25.798686 [Byte1]: 49
8721 23:24:25.802574
8722 23:24:25.802654 Set Vref, RX VrefLevel [Byte0]: 50
8723 23:24:25.805855 [Byte1]: 50
8724 23:24:25.810183
8725 23:24:25.810289 Set Vref, RX VrefLevel [Byte0]: 51
8726 23:24:25.813419 [Byte1]: 51
8727 23:24:25.818009
8728 23:24:25.818089 Set Vref, RX VrefLevel [Byte0]: 52
8729 23:24:25.820857 [Byte1]: 52
8730 23:24:25.825347
8731 23:24:25.825427 Set Vref, RX VrefLevel [Byte0]: 53
8732 23:24:25.828592 [Byte1]: 53
8733 23:24:25.833120
8734 23:24:25.833208 Set Vref, RX VrefLevel [Byte0]: 54
8735 23:24:25.836129 [Byte1]: 54
8736 23:24:25.840415
8737 23:24:25.840495 Set Vref, RX VrefLevel [Byte0]: 55
8738 23:24:25.844087 [Byte1]: 55
8739 23:24:25.847896
8740 23:24:25.847975 Set Vref, RX VrefLevel [Byte0]: 56
8741 23:24:25.851157 [Byte1]: 56
8742 23:24:25.855789
8743 23:24:25.855868 Set Vref, RX VrefLevel [Byte0]: 57
8744 23:24:25.859923 [Byte1]: 57
8745 23:24:25.863341
8746 23:24:25.863421 Set Vref, RX VrefLevel [Byte0]: 58
8747 23:24:25.866336 [Byte1]: 58
8748 23:24:25.870829
8749 23:24:25.870912 Set Vref, RX VrefLevel [Byte0]: 59
8750 23:24:25.874262 [Byte1]: 59
8751 23:24:25.878393
8752 23:24:25.878480 Set Vref, RX VrefLevel [Byte0]: 60
8753 23:24:25.882058 [Byte1]: 60
8754 23:24:25.885973
8755 23:24:25.886053 Set Vref, RX VrefLevel [Byte0]: 61
8756 23:24:25.889122 [Byte1]: 61
8757 23:24:25.893680
8758 23:24:25.893760 Set Vref, RX VrefLevel [Byte0]: 62
8759 23:24:25.896745 [Byte1]: 62
8760 23:24:25.901024
8761 23:24:25.901112 Set Vref, RX VrefLevel [Byte0]: 63
8762 23:24:25.904348 [Byte1]: 63
8763 23:24:25.908661
8764 23:24:25.908741 Set Vref, RX VrefLevel [Byte0]: 64
8765 23:24:25.911869 [Byte1]: 64
8766 23:24:25.916486
8767 23:24:25.916565 Set Vref, RX VrefLevel [Byte0]: 65
8768 23:24:25.919675 [Byte1]: 65
8769 23:24:25.923840
8770 23:24:25.923920 Set Vref, RX VrefLevel [Byte0]: 66
8771 23:24:25.927285 [Byte1]: 66
8772 23:24:25.931304
8773 23:24:25.931384 Set Vref, RX VrefLevel [Byte0]: 67
8774 23:24:25.934902 [Byte1]: 67
8775 23:24:25.938805
8776 23:24:25.938884 Set Vref, RX VrefLevel [Byte0]: 68
8777 23:24:25.942292 [Byte1]: 68
8778 23:24:25.946736
8779 23:24:25.946816 Set Vref, RX VrefLevel [Byte0]: 69
8780 23:24:25.949529 [Byte1]: 69
8781 23:24:25.953929
8782 23:24:25.954009 Set Vref, RX VrefLevel [Byte0]: 70
8783 23:24:25.957306 [Byte1]: 70
8784 23:24:25.962047
8785 23:24:25.962127 Set Vref, RX VrefLevel [Byte0]: 71
8786 23:24:25.965110 [Byte1]: 71
8787 23:24:25.969925
8788 23:24:25.970004 Set Vref, RX VrefLevel [Byte0]: 72
8789 23:24:25.972811 [Byte1]: 72
8790 23:24:25.976770
8791 23:24:25.976850 Set Vref, RX VrefLevel [Byte0]: 73
8792 23:24:25.980496 [Byte1]: 73
8793 23:24:25.984318
8794 23:24:25.984398 Set Vref, RX VrefLevel [Byte0]: 74
8795 23:24:25.987650 [Byte1]: 74
8796 23:24:25.991936
8797 23:24:25.992016 Set Vref, RX VrefLevel [Byte0]: 75
8798 23:24:25.995408 [Byte1]: 75
8799 23:24:25.999500
8800 23:24:25.999579 Set Vref, RX VrefLevel [Byte0]: 76
8801 23:24:26.002680 [Byte1]: 76
8802 23:24:26.007384
8803 23:24:26.007464 Final RX Vref Byte 0 = 61 to rank0
8804 23:24:26.010606 Final RX Vref Byte 1 = 55 to rank0
8805 23:24:26.013979 Final RX Vref Byte 0 = 61 to rank1
8806 23:24:26.017376 Final RX Vref Byte 1 = 55 to rank1==
8807 23:24:26.020565 Dram Type= 6, Freq= 0, CH_1, rank 0
8808 23:24:26.027146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 23:24:26.027230 ==
8810 23:24:26.027293 DQS Delay:
8811 23:24:26.027352 DQS0 = 0, DQS1 = 0
8812 23:24:26.030742 DQM Delay:
8813 23:24:26.030821 DQM0 = 131, DQM1 = 124
8814 23:24:26.034256 DQ Delay:
8815 23:24:26.037036 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8816 23:24:26.040573 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8817 23:24:26.043743 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8818 23:24:26.047306 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8819 23:24:26.047386
8820 23:24:26.047448
8821 23:24:26.047507
8822 23:24:26.050687 [DramC_TX_OE_Calibration] TA2
8823 23:24:26.054155 Original DQ_B0 (3 6) =30, OEN = 27
8824 23:24:26.057302 Original DQ_B1 (3 6) =30, OEN = 27
8825 23:24:26.060652 24, 0x0, End_B0=24 End_B1=24
8826 23:24:26.060733 25, 0x0, End_B0=25 End_B1=25
8827 23:24:26.063922 26, 0x0, End_B0=26 End_B1=26
8828 23:24:26.067023 27, 0x0, End_B0=27 End_B1=27
8829 23:24:26.070634 28, 0x0, End_B0=28 End_B1=28
8830 23:24:26.070715 29, 0x0, End_B0=29 End_B1=29
8831 23:24:26.074021 30, 0x0, End_B0=30 End_B1=30
8832 23:24:26.077199 31, 0x4141, End_B0=30 End_B1=30
8833 23:24:26.080482 Byte0 end_step=30 best_step=27
8834 23:24:26.083688 Byte1 end_step=30 best_step=27
8835 23:24:26.087124 Byte0 TX OE(2T, 0.5T) = (3, 3)
8836 23:24:26.087204 Byte1 TX OE(2T, 0.5T) = (3, 3)
8837 23:24:26.087276
8838 23:24:26.090515
8839 23:24:26.097010 [DQSOSCAuto] RK0, (LSB)MR18= 0x14fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
8840 23:24:26.100793 CH1 RK0: MR19=302, MR18=14FE
8841 23:24:26.107396 CH1_RK0: MR19=0x302, MR18=0x14FE, DQSOSC=399, MR23=63, INC=23, DEC=15
8842 23:24:26.107477
8843 23:24:26.110908 ----->DramcWriteLeveling(PI) begin...
8844 23:24:26.110995 ==
8845 23:24:26.113784 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 23:24:26.117321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 23:24:26.117401 ==
8848 23:24:26.120871 Write leveling (Byte 0): 25 => 25
8849 23:24:26.123732 Write leveling (Byte 1): 25 => 25
8850 23:24:26.127019 DramcWriteLeveling(PI) end<-----
8851 23:24:26.127104
8852 23:24:26.127167 ==
8853 23:24:26.130347 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 23:24:26.133500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 23:24:26.133606 ==
8856 23:24:26.136928 [Gating] SW mode calibration
8857 23:24:26.143925 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8858 23:24:26.150271 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8859 23:24:26.153605 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 23:24:26.157563 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 23:24:26.163805 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 23:24:26.167166 1 4 12 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
8863 23:24:26.170429 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8864 23:24:26.176940 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8865 23:24:26.180532 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8866 23:24:26.183701 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8867 23:24:26.190357 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8868 23:24:26.193882 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8869 23:24:26.196988 1 5 8 | B1->B0 | 3434 2a2a | 1 1 | (1 0) (1 0)
8870 23:24:26.200700 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
8871 23:24:26.207402 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8872 23:24:26.210894 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8873 23:24:26.214173 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8874 23:24:26.220609 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8875 23:24:26.223990 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8876 23:24:26.227207 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 23:24:26.234108 1 6 8 | B1->B0 | 2424 3e3e | 0 0 | (0 0) (0 0)
8878 23:24:26.237452 1 6 12 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8879 23:24:26.240810 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8880 23:24:26.247358 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8881 23:24:26.250578 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8882 23:24:26.253829 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8883 23:24:26.260976 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8884 23:24:26.263818 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 23:24:26.267232 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8886 23:24:26.270661 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8887 23:24:26.278180 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8888 23:24:26.280390 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8889 23:24:26.283835 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 23:24:26.290580 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 23:24:26.294203 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 23:24:26.297619 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 23:24:26.303975 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 23:24:26.307377 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 23:24:26.310513 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 23:24:26.317531 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 23:24:26.320200 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 23:24:26.323667 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 23:24:26.330779 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 23:24:26.334094 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8901 23:24:26.337145 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8902 23:24:26.344475 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8903 23:24:26.347684 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8904 23:24:26.350722 Total UI for P1: 0, mck2ui 16
8905 23:24:26.354112 best dqsien dly found for B0: ( 1, 9, 8)
8906 23:24:26.357581 Total UI for P1: 0, mck2ui 16
8907 23:24:26.360571 best dqsien dly found for B1: ( 1, 9, 12)
8908 23:24:26.364333 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8909 23:24:26.367446 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8910 23:24:26.367526
8911 23:24:26.370588 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8912 23:24:26.374030 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8913 23:24:26.376950 [Gating] SW calibration Done
8914 23:24:26.377030 ==
8915 23:24:26.380403 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 23:24:26.383634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 23:24:26.383714 ==
8918 23:24:26.387394 RX Vref Scan: 0
8919 23:24:26.387491
8920 23:24:26.390539 RX Vref 0 -> 0, step: 1
8921 23:24:26.390620
8922 23:24:26.390683 RX Delay 0 -> 252, step: 8
8923 23:24:26.397118 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8924 23:24:26.400466 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8925 23:24:26.403698 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8926 23:24:26.406921 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8927 23:24:26.410473 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8928 23:24:26.417044 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8929 23:24:26.420433 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8930 23:24:26.424270 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8931 23:24:26.427025 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8932 23:24:26.430512 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8933 23:24:26.437361 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8934 23:24:26.440825 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8935 23:24:26.443789 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8936 23:24:26.446959 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8937 23:24:26.450247 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8938 23:24:26.456864 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8939 23:24:26.456945 ==
8940 23:24:26.460433 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 23:24:26.464183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 23:24:26.464263 ==
8943 23:24:26.464326 DQS Delay:
8944 23:24:26.467427 DQS0 = 0, DQS1 = 0
8945 23:24:26.467507 DQM Delay:
8946 23:24:26.470530 DQM0 = 133, DQM1 = 128
8947 23:24:26.470609 DQ Delay:
8948 23:24:26.473563 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8949 23:24:26.476919 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8950 23:24:26.480410 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8951 23:24:26.483662 DQ12 =135, DQ13 =143, DQ14 =135, DQ15 =135
8952 23:24:26.483743
8953 23:24:26.483807
8954 23:24:26.487237 ==
8955 23:24:26.487311 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 23:24:26.493564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 23:24:26.493639 ==
8958 23:24:26.493700
8959 23:24:26.493758
8960 23:24:26.497444 TX Vref Scan disable
8961 23:24:26.497525 == TX Byte 0 ==
8962 23:24:26.500747 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8963 23:24:26.507045 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8964 23:24:26.507126 == TX Byte 1 ==
8965 23:24:26.510839 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8966 23:24:26.517217 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8967 23:24:26.517297 ==
8968 23:24:26.520349 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 23:24:26.523864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 23:24:26.523945 ==
8971 23:24:26.537204
8972 23:24:26.540992 TX Vref early break, caculate TX vref
8973 23:24:26.544364 TX Vref=16, minBit 5, minWin=23, winSum=386
8974 23:24:26.547906 TX Vref=18, minBit 0, minWin=24, winSum=395
8975 23:24:26.550645 TX Vref=20, minBit 1, minWin=24, winSum=401
8976 23:24:26.553952 TX Vref=22, minBit 9, minWin=24, winSum=408
8977 23:24:26.557331 TX Vref=24, minBit 5, minWin=25, winSum=417
8978 23:24:26.563832 TX Vref=26, minBit 0, minWin=26, winSum=427
8979 23:24:26.567207 TX Vref=28, minBit 5, minWin=25, winSum=428
8980 23:24:26.570592 TX Vref=30, minBit 0, minWin=25, winSum=425
8981 23:24:26.574329 TX Vref=32, minBit 0, minWin=25, winSum=421
8982 23:24:26.577823 TX Vref=34, minBit 0, minWin=25, winSum=411
8983 23:24:26.580907 TX Vref=36, minBit 0, minWin=24, winSum=401
8984 23:24:26.587188 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
8985 23:24:26.587269
8986 23:24:26.590668 Final TX Range 0 Vref 26
8987 23:24:26.590749
8988 23:24:26.590813 ==
8989 23:24:26.593957 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 23:24:26.597498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 23:24:26.597583 ==
8992 23:24:26.597648
8993 23:24:26.597706
8994 23:24:26.601106 TX Vref Scan disable
8995 23:24:26.607272 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8996 23:24:26.607353 == TX Byte 0 ==
8997 23:24:26.610757 u2DelayCellOfst[0]=14 cells (4 PI)
8998 23:24:26.614084 u2DelayCellOfst[1]=10 cells (3 PI)
8999 23:24:26.617554 u2DelayCellOfst[2]=0 cells (0 PI)
9000 23:24:26.620797 u2DelayCellOfst[3]=7 cells (2 PI)
9001 23:24:26.624318 u2DelayCellOfst[4]=7 cells (2 PI)
9002 23:24:26.627559 u2DelayCellOfst[5]=17 cells (5 PI)
9003 23:24:26.630650 u2DelayCellOfst[6]=17 cells (5 PI)
9004 23:24:26.633967 u2DelayCellOfst[7]=7 cells (2 PI)
9005 23:24:26.637673 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9006 23:24:26.640591 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9007 23:24:26.644138 == TX Byte 1 ==
9008 23:24:26.644219 u2DelayCellOfst[8]=0 cells (0 PI)
9009 23:24:26.647250 u2DelayCellOfst[9]=7 cells (2 PI)
9010 23:24:26.650826 u2DelayCellOfst[10]=14 cells (4 PI)
9011 23:24:26.653725 u2DelayCellOfst[11]=7 cells (2 PI)
9012 23:24:26.657068 u2DelayCellOfst[12]=17 cells (5 PI)
9013 23:24:26.660436 u2DelayCellOfst[13]=17 cells (5 PI)
9014 23:24:26.664116 u2DelayCellOfst[14]=17 cells (5 PI)
9015 23:24:26.667414 u2DelayCellOfst[15]=17 cells (5 PI)
9016 23:24:26.670835 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
9017 23:24:26.677025 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
9018 23:24:26.677106 DramC Write-DBI on
9019 23:24:26.677169 ==
9020 23:24:26.680970 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 23:24:26.684193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 23:24:26.684273 ==
9023 23:24:26.687627
9024 23:24:26.687707
9025 23:24:26.687770 TX Vref Scan disable
9026 23:24:26.690681 == TX Byte 0 ==
9027 23:24:26.693824 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9028 23:24:26.697298 == TX Byte 1 ==
9029 23:24:26.700673 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9030 23:24:26.700754 DramC Write-DBI off
9031 23:24:26.700818
9032 23:24:26.704208 [DATLAT]
9033 23:24:26.704288 Freq=1600, CH1 RK1
9034 23:24:26.704352
9035 23:24:26.707569 DATLAT Default: 0xf
9036 23:24:26.707649 0, 0xFFFF, sum = 0
9037 23:24:26.710762 1, 0xFFFF, sum = 0
9038 23:24:26.710844 2, 0xFFFF, sum = 0
9039 23:24:26.714174 3, 0xFFFF, sum = 0
9040 23:24:26.714255 4, 0xFFFF, sum = 0
9041 23:24:26.717827 5, 0xFFFF, sum = 0
9042 23:24:26.717909 6, 0xFFFF, sum = 0
9043 23:24:26.720565 7, 0xFFFF, sum = 0
9044 23:24:26.723946 8, 0xFFFF, sum = 0
9045 23:24:26.724028 9, 0xFFFF, sum = 0
9046 23:24:26.727389 10, 0xFFFF, sum = 0
9047 23:24:26.727470 11, 0xFFFF, sum = 0
9048 23:24:26.730592 12, 0xFFFF, sum = 0
9049 23:24:26.730673 13, 0xFFFF, sum = 0
9050 23:24:26.734563 14, 0x0, sum = 1
9051 23:24:26.734645 15, 0x0, sum = 2
9052 23:24:26.737547 16, 0x0, sum = 3
9053 23:24:26.737628 17, 0x0, sum = 4
9054 23:24:26.737694 best_step = 15
9055 23:24:26.741013
9056 23:24:26.741092 ==
9057 23:24:26.744056 Dram Type= 6, Freq= 0, CH_1, rank 1
9058 23:24:26.747516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9059 23:24:26.747597 ==
9060 23:24:26.747661 RX Vref Scan: 0
9061 23:24:26.747721
9062 23:24:26.750623 RX Vref 0 -> 0, step: 1
9063 23:24:26.750703
9064 23:24:26.754196 RX Delay 11 -> 252, step: 4
9065 23:24:26.756912 iDelay=191, Bit 0, Center 130 (79 ~ 182) 104
9066 23:24:26.763649 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
9067 23:24:26.767374 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
9068 23:24:26.770621 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
9069 23:24:26.773951 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
9070 23:24:26.777206 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9071 23:24:26.780576 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9072 23:24:26.787082 iDelay=191, Bit 7, Center 124 (71 ~ 178) 108
9073 23:24:26.790073 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
9074 23:24:26.793475 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
9075 23:24:26.797188 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
9076 23:24:26.803776 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
9077 23:24:26.806894 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9078 23:24:26.810204 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
9079 23:24:26.814121 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
9080 23:24:26.817276 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
9081 23:24:26.817357 ==
9082 23:24:26.820362 Dram Type= 6, Freq= 0, CH_1, rank 1
9083 23:24:26.826971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9084 23:24:26.827053 ==
9085 23:24:26.827117 DQS Delay:
9086 23:24:26.829979 DQS0 = 0, DQS1 = 0
9087 23:24:26.830058 DQM Delay:
9088 23:24:26.833933 DQM0 = 129, DQM1 = 126
9089 23:24:26.834013 DQ Delay:
9090 23:24:26.836766 DQ0 =130, DQ1 =126, DQ2 =118, DQ3 =126
9091 23:24:26.840112 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =124
9092 23:24:26.843316 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =116
9093 23:24:26.846977 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9094 23:24:26.847073
9095 23:24:26.847136
9096 23:24:26.847195
9097 23:24:26.850633 [DramC_TX_OE_Calibration] TA2
9098 23:24:26.853673 Original DQ_B0 (3 6) =30, OEN = 27
9099 23:24:26.856549 Original DQ_B1 (3 6) =30, OEN = 27
9100 23:24:26.860001 24, 0x0, End_B0=24 End_B1=24
9101 23:24:26.860083 25, 0x0, End_B0=25 End_B1=25
9102 23:24:26.863763 26, 0x0, End_B0=26 End_B1=26
9103 23:24:26.867030 27, 0x0, End_B0=27 End_B1=27
9104 23:24:26.870052 28, 0x0, End_B0=28 End_B1=28
9105 23:24:26.873329 29, 0x0, End_B0=29 End_B1=29
9106 23:24:26.873411 30, 0x0, End_B0=30 End_B1=30
9107 23:24:26.877215 31, 0x4141, End_B0=30 End_B1=30
9108 23:24:26.880409 Byte0 end_step=30 best_step=27
9109 23:24:26.883282 Byte1 end_step=30 best_step=27
9110 23:24:26.886920 Byte0 TX OE(2T, 0.5T) = (3, 3)
9111 23:24:26.890262 Byte1 TX OE(2T, 0.5T) = (3, 3)
9112 23:24:26.890344
9113 23:24:26.890418
9114 23:24:26.897130 [DQSOSCAuto] RK1, (LSB)MR18= 0xc11, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
9115 23:24:26.900191 CH1 RK1: MR19=303, MR18=C11
9116 23:24:26.906767 CH1_RK1: MR19=0x303, MR18=0xC11, DQSOSC=401, MR23=63, INC=22, DEC=15
9117 23:24:26.910222 [RxdqsGatingPostProcess] freq 1600
9118 23:24:26.913542 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9119 23:24:26.916556 best DQS0 dly(2T, 0.5T) = (1, 1)
9120 23:24:26.920040 best DQS1 dly(2T, 0.5T) = (1, 1)
9121 23:24:26.923663 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9122 23:24:26.926807 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9123 23:24:26.930295 best DQS0 dly(2T, 0.5T) = (1, 1)
9124 23:24:26.933967 best DQS1 dly(2T, 0.5T) = (1, 1)
9125 23:24:26.936706 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9126 23:24:26.940084 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9127 23:24:26.943415 Pre-setting of DQS Precalculation
9128 23:24:26.946864 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9129 23:24:26.953810 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9130 23:24:26.960031 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9131 23:24:26.960112
9132 23:24:26.960175
9133 23:24:26.963373 [Calibration Summary] 3200 Mbps
9134 23:24:26.967126 CH 0, Rank 0
9135 23:24:26.967206 SW Impedance : PASS
9136 23:24:26.970008 DUTY Scan : NO K
9137 23:24:26.973777 ZQ Calibration : PASS
9138 23:24:26.973857 Jitter Meter : NO K
9139 23:24:26.976746 CBT Training : PASS
9140 23:24:26.980215 Write leveling : PASS
9141 23:24:26.980308 RX DQS gating : PASS
9142 23:24:26.983367 RX DQ/DQS(RDDQC) : PASS
9143 23:24:26.986940 TX DQ/DQS : PASS
9144 23:24:26.987022 RX DATLAT : PASS
9145 23:24:26.990072 RX DQ/DQS(Engine): PASS
9146 23:24:26.990152 TX OE : PASS
9147 23:24:26.993465 All Pass.
9148 23:24:26.993546
9149 23:24:26.993609 CH 0, Rank 1
9150 23:24:26.996894 SW Impedance : PASS
9151 23:24:26.996974 DUTY Scan : NO K
9152 23:24:26.999981 ZQ Calibration : PASS
9153 23:24:27.003543 Jitter Meter : NO K
9154 23:24:27.003624 CBT Training : PASS
9155 23:24:27.006666 Write leveling : PASS
9156 23:24:27.009999 RX DQS gating : PASS
9157 23:24:27.010080 RX DQ/DQS(RDDQC) : PASS
9158 23:24:27.013721 TX DQ/DQS : PASS
9159 23:24:27.016893 RX DATLAT : PASS
9160 23:24:27.016973 RX DQ/DQS(Engine): PASS
9161 23:24:27.020431 TX OE : PASS
9162 23:24:27.020512 All Pass.
9163 23:24:27.020576
9164 23:24:27.023660 CH 1, Rank 0
9165 23:24:27.023740 SW Impedance : PASS
9166 23:24:27.026832 DUTY Scan : NO K
9167 23:24:27.030333 ZQ Calibration : PASS
9168 23:24:27.030455 Jitter Meter : NO K
9169 23:24:27.033300 CBT Training : PASS
9170 23:24:27.033380 Write leveling : PASS
9171 23:24:27.037001 RX DQS gating : PASS
9172 23:24:27.040026 RX DQ/DQS(RDDQC) : PASS
9173 23:24:27.040106 TX DQ/DQS : PASS
9174 23:24:27.043389 RX DATLAT : PASS
9175 23:24:27.046708 RX DQ/DQS(Engine): PASS
9176 23:24:27.046788 TX OE : PASS
9177 23:24:27.050199 All Pass.
9178 23:24:27.050280
9179 23:24:27.050343 CH 1, Rank 1
9180 23:24:27.053752 SW Impedance : PASS
9181 23:24:27.053832 DUTY Scan : NO K
9182 23:24:27.057103 ZQ Calibration : PASS
9183 23:24:27.060327 Jitter Meter : NO K
9184 23:24:27.060407 CBT Training : PASS
9185 23:24:27.063747 Write leveling : PASS
9186 23:24:27.066845 RX DQS gating : PASS
9187 23:24:27.066925 RX DQ/DQS(RDDQC) : PASS
9188 23:24:27.070454 TX DQ/DQS : PASS
9189 23:24:27.070535 RX DATLAT : PASS
9190 23:24:27.073971 RX DQ/DQS(Engine): PASS
9191 23:24:27.077460 TX OE : PASS
9192 23:24:27.077541 All Pass.
9193 23:24:27.077605
9194 23:24:27.080664 DramC Write-DBI on
9195 23:24:27.080756 PER_BANK_REFRESH: Hybrid Mode
9196 23:24:27.083921 TX_TRACKING: ON
9197 23:24:27.093488 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9198 23:24:27.100632 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9199 23:24:27.107528 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9200 23:24:27.110544 [FAST_K] Save calibration result to emmc
9201 23:24:27.113579 sync common calibartion params.
9202 23:24:27.117100 sync cbt_mode0:1, 1:1
9203 23:24:27.117181 dram_init: ddr_geometry: 2
9204 23:24:27.120201 dram_init: ddr_geometry: 2
9205 23:24:27.123631 dram_init: ddr_geometry: 2
9206 23:24:27.127055 0:dram_rank_size:100000000
9207 23:24:27.127137 1:dram_rank_size:100000000
9208 23:24:27.133660 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9209 23:24:27.137048 DFS_SHUFFLE_HW_MODE: ON
9210 23:24:27.140588 dramc_set_vcore_voltage set vcore to 725000
9211 23:24:27.140669 Read voltage for 1600, 0
9212 23:24:27.143373 Vio18 = 0
9213 23:24:27.143454 Vcore = 725000
9214 23:24:27.143517 Vdram = 0
9215 23:24:27.147488 Vddq = 0
9216 23:24:27.147569 Vmddr = 0
9217 23:24:27.150289 switch to 3200 Mbps bootup
9218 23:24:27.150370 [DramcRunTimeConfig]
9219 23:24:27.150476 PHYPLL
9220 23:24:27.153699 DPM_CONTROL_AFTERK: ON
9221 23:24:27.157046 PER_BANK_REFRESH: ON
9222 23:24:27.157126 REFRESH_OVERHEAD_REDUCTION: ON
9223 23:24:27.160386 CMD_PICG_NEW_MODE: OFF
9224 23:24:27.163391 XRTWTW_NEW_MODE: ON
9225 23:24:27.163471 XRTRTR_NEW_MODE: ON
9226 23:24:27.166665 TX_TRACKING: ON
9227 23:24:27.166746 RDSEL_TRACKING: OFF
9228 23:24:27.170119 DQS Precalculation for DVFS: ON
9229 23:24:27.173425 RX_TRACKING: OFF
9230 23:24:27.173506 HW_GATING DBG: ON
9231 23:24:27.177064 ZQCS_ENABLE_LP4: ON
9232 23:24:27.177145 RX_PICG_NEW_MODE: ON
9233 23:24:27.180290 TX_PICG_NEW_MODE: ON
9234 23:24:27.180371 ENABLE_RX_DCM_DPHY: ON
9235 23:24:27.183609 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9236 23:24:27.186547 DUMMY_READ_FOR_TRACKING: OFF
9237 23:24:27.190247 !!! SPM_CONTROL_AFTERK: OFF
9238 23:24:27.193403 !!! SPM could not control APHY
9239 23:24:27.193485 IMPEDANCE_TRACKING: ON
9240 23:24:27.197050 TEMP_SENSOR: ON
9241 23:24:27.197131 HW_SAVE_FOR_SR: OFF
9242 23:24:27.199966 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9243 23:24:27.203455 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9244 23:24:27.206727 Read ODT Tracking: ON
9245 23:24:27.210358 Refresh Rate DeBounce: ON
9246 23:24:27.210489 DFS_NO_QUEUE_FLUSH: ON
9247 23:24:27.213528 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9248 23:24:27.216803 ENABLE_DFS_RUNTIME_MRW: OFF
9249 23:24:27.216883 DDR_RESERVE_NEW_MODE: ON
9250 23:24:27.220380 MR_CBT_SWITCH_FREQ: ON
9251 23:24:27.223640 =========================
9252 23:24:27.242017 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9253 23:24:27.245473 dram_init: ddr_geometry: 2
9254 23:24:27.263189 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9255 23:24:27.266700 dram_init: dram init end (result: 0)
9256 23:24:27.272999 DRAM-K: Full calibration passed in 24616 msecs
9257 23:24:27.276390 MRC: failed to locate region type 0.
9258 23:24:27.276465 DRAM rank0 size:0x100000000,
9259 23:24:27.279737 DRAM rank1 size=0x100000000
9260 23:24:27.290111 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9261 23:24:27.296295 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9262 23:24:27.302902 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9263 23:24:27.309560 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9264 23:24:27.312617 DRAM rank0 size:0x100000000,
9265 23:24:27.316801 DRAM rank1 size=0x100000000
9266 23:24:27.316882 CBMEM:
9267 23:24:27.319513 IMD: root @ 0xfffff000 254 entries.
9268 23:24:27.323274 IMD: root @ 0xffffec00 62 entries.
9269 23:24:27.325895 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9270 23:24:27.329532 WARNING: RO_VPD is uninitialized or empty.
9271 23:24:27.336193 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9272 23:24:27.343145 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9273 23:24:27.356145 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9274 23:24:27.367435 BS: romstage times (exec / console): total (unknown) / 24115 ms
9275 23:24:27.367517
9276 23:24:27.367581
9277 23:24:27.377374 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9278 23:24:27.380923 ARM64: Exception handlers installed.
9279 23:24:27.384069 ARM64: Testing exception
9280 23:24:27.387531 ARM64: Done test exception
9281 23:24:27.387612 Enumerating buses...
9282 23:24:27.390594 Show all devs... Before device enumeration.
9283 23:24:27.393954 Root Device: enabled 1
9284 23:24:27.397199 CPU_CLUSTER: 0: enabled 1
9285 23:24:27.397279 CPU: 00: enabled 1
9286 23:24:27.400743 Compare with tree...
9287 23:24:27.400823 Root Device: enabled 1
9288 23:24:27.404242 CPU_CLUSTER: 0: enabled 1
9289 23:24:27.407150 CPU: 00: enabled 1
9290 23:24:27.407231 Root Device scanning...
9291 23:24:27.410976 scan_static_bus for Root Device
9292 23:24:27.413747 CPU_CLUSTER: 0 enabled
9293 23:24:27.417513 scan_static_bus for Root Device done
9294 23:24:27.420982 scan_bus: bus Root Device finished in 8 msecs
9295 23:24:27.421063 done
9296 23:24:27.427336 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9297 23:24:27.430337 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9298 23:24:27.437211 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9299 23:24:27.440418 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9300 23:24:27.443762 Allocating resources...
9301 23:24:27.447087 Reading resources...
9302 23:24:27.450391 Root Device read_resources bus 0 link: 0
9303 23:24:27.450494 DRAM rank0 size:0x100000000,
9304 23:24:27.453911 DRAM rank1 size=0x100000000
9305 23:24:27.457332 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9306 23:24:27.460658 CPU: 00 missing read_resources
9307 23:24:27.463803 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9308 23:24:27.470436 Root Device read_resources bus 0 link: 0 done
9309 23:24:27.470531 Done reading resources.
9310 23:24:27.477426 Show resources in subtree (Root Device)...After reading.
9311 23:24:27.480442 Root Device child on link 0 CPU_CLUSTER: 0
9312 23:24:27.483935 CPU_CLUSTER: 0 child on link 0 CPU: 00
9313 23:24:27.493928 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9314 23:24:27.494010 CPU: 00
9315 23:24:27.497563 Root Device assign_resources, bus 0 link: 0
9316 23:24:27.500431 CPU_CLUSTER: 0 missing set_resources
9317 23:24:27.503991 Root Device assign_resources, bus 0 link: 0 done
9318 23:24:27.507251 Done setting resources.
9319 23:24:27.513611 Show resources in subtree (Root Device)...After assigning values.
9320 23:24:27.517795 Root Device child on link 0 CPU_CLUSTER: 0
9321 23:24:27.520441 CPU_CLUSTER: 0 child on link 0 CPU: 00
9322 23:24:27.530829 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9323 23:24:27.530911 CPU: 00
9324 23:24:27.533794 Done allocating resources.
9325 23:24:27.537137 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9326 23:24:27.540451 Enabling resources...
9327 23:24:27.540531 done.
9328 23:24:27.543860 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9329 23:24:27.547633 Initializing devices...
9330 23:24:27.551385 Root Device init
9331 23:24:27.551465 init hardware done!
9332 23:24:27.554888 0x00000018: ctrlr->caps
9333 23:24:27.554970 52.000 MHz: ctrlr->f_max
9334 23:24:27.557514 0.400 MHz: ctrlr->f_min
9335 23:24:27.560548 0x40ff8080: ctrlr->voltages
9336 23:24:27.560630 sclk: 390625
9337 23:24:27.564414 Bus Width = 1
9338 23:24:27.564495 sclk: 390625
9339 23:24:27.564559 Bus Width = 1
9340 23:24:27.567140 Early init status = 3
9341 23:24:27.570769 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9342 23:24:27.575809 in-header: 03 fc 00 00 01 00 00 00
9343 23:24:27.579051 in-data: 00
9344 23:24:27.582580 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9345 23:24:27.588041 in-header: 03 fd 00 00 00 00 00 00
9346 23:24:27.591839 in-data:
9347 23:24:27.594793 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9348 23:24:27.598976 in-header: 03 fc 00 00 01 00 00 00
9349 23:24:27.602299 in-data: 00
9350 23:24:27.605720 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9351 23:24:27.611080 in-header: 03 fd 00 00 00 00 00 00
9352 23:24:27.614338 in-data:
9353 23:24:27.618382 [SSUSB] Setting up USB HOST controller...
9354 23:24:27.621205 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9355 23:24:27.624702 [SSUSB] phy power-on done.
9356 23:24:27.627924 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9357 23:24:27.634391 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9358 23:24:27.637778 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9359 23:24:27.644559 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9360 23:24:27.651185 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9361 23:24:27.657934 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9362 23:24:27.664862 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9363 23:24:27.670945 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9364 23:24:27.671031 SPM: binary array size = 0x9dc
9365 23:24:27.677928 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9366 23:24:27.684522 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9367 23:24:27.691060 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9368 23:24:27.694332 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9369 23:24:27.697759 configure_display: Starting display init
9370 23:24:27.734393 anx7625_power_on_init: Init interface.
9371 23:24:27.737583 anx7625_disable_pd_protocol: Disabled PD feature.
9372 23:24:27.741243 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9373 23:24:27.769168 anx7625_start_dp_work: Secure OCM version=00
9374 23:24:27.772231 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9375 23:24:27.787356 sp_tx_get_edid_block: EDID Block = 1
9376 23:24:27.889508 Extracted contents:
9377 23:24:27.892969 header: 00 ff ff ff ff ff ff 00
9378 23:24:27.896458 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9379 23:24:27.899551 version: 01 04
9380 23:24:27.902751 basic params: 95 1f 11 78 0a
9381 23:24:27.906121 chroma info: 76 90 94 55 54 90 27 21 50 54
9382 23:24:27.909483 established: 00 00 00
9383 23:24:27.916213 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9384 23:24:27.919074 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9385 23:24:27.925952 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9386 23:24:27.932481 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9387 23:24:27.939552 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9388 23:24:27.943034 extensions: 00
9389 23:24:27.943140 checksum: fb
9390 23:24:27.943232
9391 23:24:27.946035 Manufacturer: IVO Model 57d Serial Number 0
9392 23:24:27.949296 Made week 0 of 2020
9393 23:24:27.949403 EDID version: 1.4
9394 23:24:27.952596 Digital display
9395 23:24:27.955750 6 bits per primary color channel
9396 23:24:27.955857 DisplayPort interface
9397 23:24:27.959251 Maximum image size: 31 cm x 17 cm
9398 23:24:27.962587 Gamma: 220%
9399 23:24:27.962666 Check DPMS levels
9400 23:24:27.966125 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9401 23:24:27.969131 First detailed timing is preferred timing
9402 23:24:27.972724 Established timings supported:
9403 23:24:27.976220 Standard timings supported:
9404 23:24:27.976295 Detailed timings
9405 23:24:27.982531 Hex of detail: 383680a07038204018303c0035ae10000019
9406 23:24:27.986021 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9407 23:24:27.992685 0780 0798 07c8 0820 hborder 0
9408 23:24:27.995920 0438 043b 0447 0458 vborder 0
9409 23:24:27.995993 -hsync -vsync
9410 23:24:27.999016 Did detailed timing
9411 23:24:28.002882 Hex of detail: 000000000000000000000000000000000000
9412 23:24:28.005777 Manufacturer-specified data, tag 0
9413 23:24:28.012536 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9414 23:24:28.012636 ASCII string: InfoVision
9415 23:24:28.019496 Hex of detail: 000000fe00523134304e574635205248200a
9416 23:24:28.022287 ASCII string: R140NWF5 RH
9417 23:24:28.022383 Checksum
9418 23:24:28.022491 Checksum: 0xfb (valid)
9419 23:24:28.029194 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9420 23:24:28.032387 DSI data_rate: 832800000 bps
9421 23:24:28.036127 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9422 23:24:28.039415 anx7625_parse_edid: pixelclock(138800).
9423 23:24:28.045833 hactive(1920), hsync(48), hfp(24), hbp(88)
9424 23:24:28.049252 vactive(1080), vsync(12), vfp(3), vbp(17)
9425 23:24:28.052770 anx7625_dsi_config: config dsi.
9426 23:24:28.059055 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9427 23:24:28.071345 anx7625_dsi_config: success to config DSI
9428 23:24:28.075360 anx7625_dp_start: MIPI phy setup OK.
9429 23:24:28.078265 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9430 23:24:28.081419 mtk_ddp_mode_set invalid vrefresh 60
9431 23:24:28.085099 main_disp_path_setup
9432 23:24:28.085196 ovl_layer_smi_id_en
9433 23:24:28.087922 ovl_layer_smi_id_en
9434 23:24:28.088002 ccorr_config
9435 23:24:28.088065 aal_config
9436 23:24:28.091536 gamma_config
9437 23:24:28.091617 postmask_config
9438 23:24:28.095324 dither_config
9439 23:24:28.098168 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9440 23:24:28.104662 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9441 23:24:28.108127 Root Device init finished in 555 msecs
9442 23:24:28.108334 CPU_CLUSTER: 0 init
9443 23:24:28.118284 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9444 23:24:28.121805 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9445 23:24:28.125080 APU_MBOX 0x190000b0 = 0x10001
9446 23:24:28.128673 APU_MBOX 0x190001b0 = 0x10001
9447 23:24:28.131549 APU_MBOX 0x190005b0 = 0x10001
9448 23:24:28.134948 APU_MBOX 0x190006b0 = 0x10001
9449 23:24:28.138431 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9450 23:24:28.150221 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9451 23:24:28.163059 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9452 23:24:28.169894 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9453 23:24:28.181500 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9454 23:24:28.190519 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9455 23:24:28.193612 CPU_CLUSTER: 0 init finished in 81 msecs
9456 23:24:28.196853 Devices initialized
9457 23:24:28.200307 Show all devs... After init.
9458 23:24:28.200386 Root Device: enabled 1
9459 23:24:28.203988 CPU_CLUSTER: 0: enabled 1
9460 23:24:28.206862 CPU: 00: enabled 1
9461 23:24:28.210247 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9462 23:24:28.213607 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9463 23:24:28.217039 ELOG: NV offset 0x57f000 size 0x1000
9464 23:24:28.223923 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9465 23:24:28.229960 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9466 23:24:28.233710 ELOG: Event(17) added with size 13 at 2024-04-03 23:24:28 UTC
9467 23:24:28.237244 out: cmd=0x121: 03 db 21 01 00 00 00 00
9468 23:24:28.241222 in-header: 03 ad 00 00 2c 00 00 00
9469 23:24:28.254581 in-data: b2 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9470 23:24:28.261548 ELOG: Event(A1) added with size 10 at 2024-04-03 23:24:28 UTC
9471 23:24:28.267829 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9472 23:24:28.274657 ELOG: Event(A0) added with size 9 at 2024-04-03 23:24:28 UTC
9473 23:24:28.278154 elog_add_boot_reason: Logged dev mode boot
9474 23:24:28.281083 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9475 23:24:28.284639 Finalize devices...
9476 23:24:28.284716 Devices finalized
9477 23:24:28.291188 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9478 23:24:28.295003 Writing coreboot table at 0xffe64000
9479 23:24:28.297863 0. 000000000010a000-0000000000113fff: RAMSTAGE
9480 23:24:28.301599 1. 0000000040000000-00000000400fffff: RAM
9481 23:24:28.306072 2. 0000000040100000-000000004032afff: RAMSTAGE
9482 23:24:28.311324 3. 000000004032b000-00000000545fffff: RAM
9483 23:24:28.314660 4. 0000000054600000-000000005465ffff: BL31
9484 23:24:28.318339 5. 0000000054660000-00000000ffe63fff: RAM
9485 23:24:28.321050 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9486 23:24:28.328063 7. 0000000100000000-000000023fffffff: RAM
9487 23:24:28.328171 Passing 5 GPIOs to payload:
9488 23:24:28.335055 NAME | PORT | POLARITY | VALUE
9489 23:24:28.338622 EC in RW | 0x000000aa | low | undefined
9490 23:24:28.341511 EC interrupt | 0x00000005 | low | undefined
9491 23:24:28.347898 TPM interrupt | 0x000000ab | high | undefined
9492 23:24:28.351279 SD card detect | 0x00000011 | high | undefined
9493 23:24:28.358391 speaker enable | 0x00000093 | high | undefined
9494 23:24:28.361618 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9495 23:24:28.364782 in-header: 03 f9 00 00 02 00 00 00
9496 23:24:28.364852 in-data: 02 00
9497 23:24:28.368322 ADC[4]: Raw value=899852 ID=7
9498 23:24:28.371733 ADC[3]: Raw value=213336 ID=1
9499 23:24:28.371810 RAM Code: 0x71
9500 23:24:28.375001 ADC[6]: Raw value=74926 ID=0
9501 23:24:28.378509 ADC[5]: Raw value=211860 ID=1
9502 23:24:28.378586 SKU Code: 0x1
9503 23:24:28.384869 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a82b
9504 23:24:28.387941 coreboot table: 964 bytes.
9505 23:24:28.391654 IMD ROOT 0. 0xfffff000 0x00001000
9506 23:24:28.394932 IMD SMALL 1. 0xffffe000 0x00001000
9507 23:24:28.399312 RO MCACHE 2. 0xffffc000 0x00001104
9508 23:24:28.402012 CONSOLE 3. 0xfff7c000 0x00080000
9509 23:24:28.404789 FMAP 4. 0xfff7b000 0x00000452
9510 23:24:28.404872 TIME STAMP 5. 0xfff7a000 0x00000910
9511 23:24:28.408187 VBOOT WORK 6. 0xfff66000 0x00014000
9512 23:24:28.411531 RAMOOPS 7. 0xffe66000 0x00100000
9513 23:24:28.414716 COREBOOT 8. 0xffe64000 0x00002000
9514 23:24:28.418216 IMD small region:
9515 23:24:28.421237 IMD ROOT 0. 0xffffec00 0x00000400
9516 23:24:28.424851 VPD 1. 0xffffeb80 0x0000006c
9517 23:24:28.428120 MMC STATUS 2. 0xffffeb60 0x00000004
9518 23:24:28.434677 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9519 23:24:28.434793 Probing TPM: done!
9520 23:24:28.441665 Connected to device vid:did:rid of 1ae0:0028:00
9521 23:24:28.448036 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9522 23:24:28.451231 Initialized TPM device CR50 revision 0
9523 23:24:28.455254 Checking cr50 for pending updates
9524 23:24:28.460449 Reading cr50 TPM mode
9525 23:24:28.469814 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9526 23:24:28.475855 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9527 23:24:28.516307 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9528 23:24:28.519728 Checking segment from ROM address 0x40100000
9529 23:24:28.522815 Checking segment from ROM address 0x4010001c
9530 23:24:28.529363 Loading segment from ROM address 0x40100000
9531 23:24:28.529447 code (compression=0)
9532 23:24:28.536649 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9533 23:24:28.546125 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9534 23:24:28.546209 it's not compressed!
9535 23:24:28.552998 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9536 23:24:28.556437 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9537 23:24:28.576564 Loading segment from ROM address 0x4010001c
9538 23:24:28.576675 Entry Point 0x80000000
9539 23:24:28.579574 Loaded segments
9540 23:24:28.583080 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9541 23:24:28.589800 Jumping to boot code at 0x80000000(0xffe64000)
9542 23:24:28.596262 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9543 23:24:28.603141 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9544 23:24:28.610826 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9545 23:24:28.614299 Checking segment from ROM address 0x40100000
9546 23:24:28.617713 Checking segment from ROM address 0x4010001c
9547 23:24:28.624630 Loading segment from ROM address 0x40100000
9548 23:24:28.624713 code (compression=1)
9549 23:24:28.630822 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9550 23:24:28.640924 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9551 23:24:28.641039 using LZMA
9552 23:24:28.649186 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9553 23:24:28.656245 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9554 23:24:28.659388 Loading segment from ROM address 0x4010001c
9555 23:24:28.659469 Entry Point 0x54601000
9556 23:24:28.662974 Loaded segments
9557 23:24:28.666148 NOTICE: MT8192 bl31_setup
9558 23:24:28.673458 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9559 23:24:28.676504 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9560 23:24:28.679947 WARNING: region 0:
9561 23:24:28.682772 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9562 23:24:28.682860 WARNING: region 1:
9563 23:24:28.689447 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9564 23:24:28.689530 WARNING: region 2:
9565 23:24:28.696243 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9566 23:24:28.699961 WARNING: region 3:
9567 23:24:28.702981 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9568 23:24:28.706829 WARNING: region 4:
9569 23:24:28.709995 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9570 23:24:28.712955 WARNING: region 5:
9571 23:24:28.716335 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9572 23:24:28.720091 WARNING: region 6:
9573 23:24:28.723646 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9574 23:24:28.723729 WARNING: region 7:
9575 23:24:28.729774 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9576 23:24:28.736612 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9577 23:24:28.739794 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9578 23:24:28.743174 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9579 23:24:28.746628 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9580 23:24:28.753118 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9581 23:24:28.756756 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9582 23:24:28.763240 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9583 23:24:28.766719 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9584 23:24:28.770142 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9585 23:24:28.776917 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9586 23:24:28.779943 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9587 23:24:28.783601 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9588 23:24:28.789994 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9589 23:24:28.793636 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9590 23:24:28.800004 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9591 23:24:28.803594 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9592 23:24:28.807154 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9593 23:24:28.813781 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9594 23:24:28.817136 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9595 23:24:28.820402 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9596 23:24:28.826811 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9597 23:24:28.830534 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9598 23:24:28.833822 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9599 23:24:28.840731 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9600 23:24:28.844121 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9601 23:24:28.850364 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9602 23:24:28.853903 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9603 23:24:28.857109 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9604 23:24:28.864256 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9605 23:24:28.867112 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9606 23:24:28.874071 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9607 23:24:28.877420 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9608 23:24:28.880698 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9609 23:24:28.884346 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9610 23:24:28.890577 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9611 23:24:28.894099 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9612 23:24:28.897558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9613 23:24:28.900980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9614 23:24:28.907559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9615 23:24:28.910976 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9616 23:24:28.914515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9617 23:24:28.917290 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9618 23:24:28.924402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9619 23:24:28.927335 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9620 23:24:28.931167 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9621 23:24:28.934422 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9622 23:24:28.941490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9623 23:24:28.944223 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9624 23:24:28.947872 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9625 23:24:28.955224 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9626 23:24:28.958440 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9627 23:24:28.961491 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9628 23:24:28.967837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9629 23:24:28.971485 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9630 23:24:28.977835 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9631 23:24:28.981328 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9632 23:24:28.988237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9633 23:24:28.991534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9634 23:24:28.994749 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9635 23:24:29.001621 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9636 23:24:29.005007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9637 23:24:29.012231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9638 23:24:29.014770 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9639 23:24:29.021466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9640 23:24:29.025158 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9641 23:24:29.028413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9642 23:24:29.035222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9643 23:24:29.038221 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9644 23:24:29.045195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9645 23:24:29.048631 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9646 23:24:29.051985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9647 23:24:29.058747 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9648 23:24:29.061572 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9649 23:24:29.069413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9650 23:24:29.071802 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9651 23:24:29.078837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9652 23:24:29.082296 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9653 23:24:29.085710 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9654 23:24:29.092020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9655 23:24:29.095335 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9656 23:24:29.102218 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9657 23:24:29.105754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9658 23:24:29.112003 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9659 23:24:29.115316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9660 23:24:29.118801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9661 23:24:29.125644 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9662 23:24:29.128917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9663 23:24:29.136027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9664 23:24:29.139828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9665 23:24:29.142768 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9666 23:24:29.149230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9667 23:24:29.152592 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9668 23:24:29.159950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9669 23:24:29.162673 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9670 23:24:29.169548 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9671 23:24:29.173045 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9672 23:24:29.176507 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9673 23:24:29.179334 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9674 23:24:29.185949 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9675 23:24:29.189602 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9676 23:24:29.192556 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9677 23:24:29.199317 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9678 23:24:29.202854 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9679 23:24:29.206537 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9680 23:24:29.212642 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9681 23:24:29.216215 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9682 23:24:29.222829 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9683 23:24:29.226366 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9684 23:24:29.229534 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9685 23:24:29.236148 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9686 23:24:29.239690 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9687 23:24:29.246203 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9688 23:24:29.250018 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9689 23:24:29.253045 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9690 23:24:29.259839 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9691 23:24:29.263034 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9692 23:24:29.266332 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9693 23:24:29.273258 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9694 23:24:29.276529 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9695 23:24:29.279585 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9696 23:24:29.283340 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9697 23:24:29.289780 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9698 23:24:29.293384 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9699 23:24:29.296544 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9700 23:24:29.303413 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9701 23:24:29.306675 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9702 23:24:29.310064 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9703 23:24:29.316877 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9704 23:24:29.319792 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9705 23:24:29.323350 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9706 23:24:29.330033 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9707 23:24:29.333306 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9708 23:24:29.339932 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9709 23:24:29.343426 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9710 23:24:29.347547 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9711 23:24:29.353809 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9712 23:24:29.356904 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9713 23:24:29.360214 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9714 23:24:29.366952 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9715 23:24:29.370407 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9716 23:24:29.377257 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9717 23:24:29.380634 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9718 23:24:29.383477 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9719 23:24:29.390660 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9720 23:24:29.394195 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9721 23:24:29.400231 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9722 23:24:29.403362 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9723 23:24:29.406786 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9724 23:24:29.413899 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9725 23:24:29.417225 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9726 23:24:29.420502 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9727 23:24:29.427185 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9728 23:24:29.430630 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9729 23:24:29.437024 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9730 23:24:29.440394 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9731 23:24:29.443855 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9732 23:24:29.450556 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9733 23:24:29.454435 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9734 23:24:29.457582 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9735 23:24:29.463970 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9736 23:24:29.466937 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9737 23:24:29.473854 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9738 23:24:29.477101 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9739 23:24:29.480368 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9740 23:24:29.487110 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9741 23:24:29.490431 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9742 23:24:29.493873 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9743 23:24:29.500311 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9744 23:24:29.504178 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9745 23:24:29.510593 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9746 23:24:29.514030 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9747 23:24:29.517347 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9748 23:24:29.523795 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9749 23:24:29.527306 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9750 23:24:29.534053 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9751 23:24:29.537385 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9752 23:24:29.540749 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9753 23:24:29.547116 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9754 23:24:29.550727 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9755 23:24:29.554022 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9756 23:24:29.560560 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9757 23:24:29.564108 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9758 23:24:29.570864 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9759 23:24:29.573954 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9760 23:24:29.577303 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9761 23:24:29.584113 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9762 23:24:29.587283 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9763 23:24:29.593909 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9764 23:24:29.597456 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9765 23:24:29.600809 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9766 23:24:29.607047 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9767 23:24:29.610517 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9768 23:24:29.617156 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9769 23:24:29.620641 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9770 23:24:29.624206 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9771 23:24:29.631229 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9772 23:24:29.633786 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9773 23:24:29.640868 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9774 23:24:29.644414 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9775 23:24:29.650556 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9776 23:24:29.654559 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9777 23:24:29.657147 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9778 23:24:29.664258 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9779 23:24:29.667866 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9780 23:24:29.674634 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9781 23:24:29.677354 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9782 23:24:29.680756 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9783 23:24:29.687635 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9784 23:24:29.690730 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9785 23:24:29.697298 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9786 23:24:29.700534 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9787 23:24:29.704032 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9788 23:24:29.710612 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9789 23:24:29.714564 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9790 23:24:29.720712 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9791 23:24:29.724103 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9792 23:24:29.727406 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9793 23:24:29.734182 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9794 23:24:29.737385 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9795 23:24:29.743980 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9796 23:24:29.747897 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9797 23:24:29.751045 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9798 23:24:29.757424 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9799 23:24:29.761031 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9800 23:24:29.767636 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9801 23:24:29.770900 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9802 23:24:29.777737 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9803 23:24:29.781358 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9804 23:24:29.784132 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9805 23:24:29.787509 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9806 23:24:29.794189 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9807 23:24:29.797199 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9808 23:24:29.801426 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9809 23:24:29.804210 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9810 23:24:29.810725 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9811 23:24:29.814215 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9812 23:24:29.821220 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9813 23:24:29.824207 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9814 23:24:29.827622 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9815 23:24:29.834301 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9816 23:24:29.837202 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9817 23:24:29.840696 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9818 23:24:29.847810 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9819 23:24:29.850981 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9820 23:24:29.854057 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9821 23:24:29.860879 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9822 23:24:29.864009 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9823 23:24:29.870724 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9824 23:24:29.874095 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9825 23:24:29.877495 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9826 23:24:29.884160 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9827 23:24:29.887421 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9828 23:24:29.890781 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9829 23:24:29.897427 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9830 23:24:29.900948 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9831 23:24:29.904401 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9832 23:24:29.910741 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9833 23:24:29.914086 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9834 23:24:29.917553 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9835 23:24:29.923877 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9836 23:24:29.927381 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9837 23:24:29.934077 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9838 23:24:29.937374 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9839 23:24:29.940888 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9840 23:24:29.947216 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9841 23:24:29.950584 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9842 23:24:29.954238 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9843 23:24:29.960713 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9844 23:24:29.963810 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9845 23:24:29.967402 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9846 23:24:29.970522 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9847 23:24:29.977520 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9848 23:24:29.980734 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9849 23:24:29.984081 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9850 23:24:29.987151 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9851 23:24:29.994273 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9852 23:24:29.997348 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9853 23:24:30.000874 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9854 23:24:30.003737 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9855 23:24:30.010811 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9856 23:24:30.013950 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9857 23:24:30.017460 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9858 23:24:30.024423 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9859 23:24:30.027640 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9860 23:24:30.031054 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9861 23:24:30.037751 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9862 23:24:30.040734 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9863 23:24:30.047750 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9864 23:24:30.050619 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9865 23:24:30.054215 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9866 23:24:30.061333 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9867 23:24:30.064537 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9868 23:24:30.071223 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9869 23:24:30.074112 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9870 23:24:30.077626 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9871 23:24:30.084518 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9872 23:24:30.087404 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9873 23:24:30.094114 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9874 23:24:30.097549 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9875 23:24:30.101352 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9876 23:24:30.107574 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9877 23:24:30.111127 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9878 23:24:30.117472 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9879 23:24:30.120809 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9880 23:24:30.127311 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9881 23:24:30.131077 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9882 23:24:30.134063 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9883 23:24:30.140916 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9884 23:24:30.144166 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9885 23:24:30.151027 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9886 23:24:30.154343 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9887 23:24:30.157649 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9888 23:24:30.163938 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9889 23:24:30.167578 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9890 23:24:30.170694 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9891 23:24:30.177275 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9892 23:24:30.180828 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9893 23:24:30.187483 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9894 23:24:30.190655 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9895 23:24:30.197191 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9896 23:24:30.200909 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9897 23:24:30.204046 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9898 23:24:30.210504 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9899 23:24:30.213769 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9900 23:24:30.220357 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9901 23:24:30.224046 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9902 23:24:30.227522 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9903 23:24:30.233789 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9904 23:24:30.237515 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9905 23:24:30.243902 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9906 23:24:30.247138 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9907 23:24:30.251150 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9908 23:24:30.257006 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9909 23:24:30.260320 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9910 23:24:30.267533 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9911 23:24:30.270650 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9912 23:24:30.274073 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9913 23:24:30.280765 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9914 23:24:30.284115 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9915 23:24:30.290683 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9916 23:24:30.293855 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9917 23:24:30.297032 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9918 23:24:30.304160 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9919 23:24:30.307128 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9920 23:24:30.314316 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9921 23:24:30.317250 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9922 23:24:30.320917 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9923 23:24:30.327125 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9924 23:24:30.330253 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9925 23:24:30.337208 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9926 23:24:30.340579 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9927 23:24:30.346958 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9928 23:24:30.350912 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9929 23:24:30.353600 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9930 23:24:30.360134 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9931 23:24:30.363785 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9932 23:24:30.370516 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9933 23:24:30.373714 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9934 23:24:30.380365 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9935 23:24:30.383788 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9936 23:24:30.387019 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9937 23:24:30.393621 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9938 23:24:30.397324 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9939 23:24:30.403770 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9940 23:24:30.406946 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9941 23:24:30.410653 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9942 23:24:30.417301 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9943 23:24:30.420175 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9944 23:24:30.426992 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9945 23:24:30.430221 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9946 23:24:30.436869 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9947 23:24:30.440338 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9948 23:24:30.443629 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9949 23:24:30.450674 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9950 23:24:30.453524 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9951 23:24:30.460566 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9952 23:24:30.463882 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9953 23:24:30.470379 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9954 23:24:30.473883 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9955 23:24:30.477072 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9956 23:24:30.484162 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9957 23:24:30.487071 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9958 23:24:30.493510 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9959 23:24:30.496977 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9960 23:24:30.503863 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9961 23:24:30.507187 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9962 23:24:30.510624 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9963 23:24:30.517218 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9964 23:24:30.520441 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9965 23:24:30.527191 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9966 23:24:30.530530 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9967 23:24:30.537508 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9968 23:24:30.540899 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9969 23:24:30.544309 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9970 23:24:30.550986 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9971 23:24:30.553802 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9972 23:24:30.560761 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9973 23:24:30.563948 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9974 23:24:30.571109 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9975 23:24:30.574144 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9976 23:24:30.577068 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9977 23:24:30.583701 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9978 23:24:30.587139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9979 23:24:30.590614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9980 23:24:30.597372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9981 23:24:30.600609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9982 23:24:30.607383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9983 23:24:30.610530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9984 23:24:30.617300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9985 23:24:30.620531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9986 23:24:30.627427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9987 23:24:30.630729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9988 23:24:30.637599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9989 23:24:30.640846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9990 23:24:30.647758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9991 23:24:30.650534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9992 23:24:30.657577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9993 23:24:30.660942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9994 23:24:30.664239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9995 23:24:30.671327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9996 23:24:30.674120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9997 23:24:30.680770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9998 23:24:30.684368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9999 23:24:30.690760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10000 23:24:30.693895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10001 23:24:30.701391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10002 23:24:30.704090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10003 23:24:30.710932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10004 23:24:30.714422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10005 23:24:30.720323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10006 23:24:30.724307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10007 23:24:30.731008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10008 23:24:30.733854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10009 23:24:30.740872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10010 23:24:30.743981 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10011 23:24:30.747482 INFO: [APUAPC] vio 0
10012 23:24:30.750764 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10013 23:24:30.757777 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10014 23:24:30.760836 INFO: [APUAPC] D0_APC_0: 0x400510
10015 23:24:30.764230 INFO: [APUAPC] D0_APC_1: 0x0
10016 23:24:30.764304 INFO: [APUAPC] D0_APC_2: 0x1540
10017 23:24:30.767452 INFO: [APUAPC] D0_APC_3: 0x0
10018 23:24:30.770913 INFO: [APUAPC] D1_APC_0: 0xffffffff
10019 23:24:30.774199 INFO: [APUAPC] D1_APC_1: 0xffffffff
10020 23:24:30.777049 INFO: [APUAPC] D1_APC_2: 0x3fffff
10021 23:24:30.780559 INFO: [APUAPC] D1_APC_3: 0x0
10022 23:24:30.783973 INFO: [APUAPC] D2_APC_0: 0xffffffff
10023 23:24:30.787105 INFO: [APUAPC] D2_APC_1: 0xffffffff
10024 23:24:30.790715 INFO: [APUAPC] D2_APC_2: 0x3fffff
10025 23:24:30.794056 INFO: [APUAPC] D2_APC_3: 0x0
10026 23:24:30.797265 INFO: [APUAPC] D3_APC_0: 0xffffffff
10027 23:24:30.800486 INFO: [APUAPC] D3_APC_1: 0xffffffff
10028 23:24:30.803997 INFO: [APUAPC] D3_APC_2: 0x3fffff
10029 23:24:30.807470 INFO: [APUAPC] D3_APC_3: 0x0
10030 23:24:30.811091 INFO: [APUAPC] D4_APC_0: 0xffffffff
10031 23:24:30.814190 INFO: [APUAPC] D4_APC_1: 0xffffffff
10032 23:24:30.817028 INFO: [APUAPC] D4_APC_2: 0x3fffff
10033 23:24:30.820551 INFO: [APUAPC] D4_APC_3: 0x0
10034 23:24:30.823895 INFO: [APUAPC] D5_APC_0: 0xffffffff
10035 23:24:30.827604 INFO: [APUAPC] D5_APC_1: 0xffffffff
10036 23:24:30.830943 INFO: [APUAPC] D5_APC_2: 0x3fffff
10037 23:24:30.834297 INFO: [APUAPC] D5_APC_3: 0x0
10038 23:24:30.837215 INFO: [APUAPC] D6_APC_0: 0xffffffff
10039 23:24:30.840692 INFO: [APUAPC] D6_APC_1: 0xffffffff
10040 23:24:30.844352 INFO: [APUAPC] D6_APC_2: 0x3fffff
10041 23:24:30.847625 INFO: [APUAPC] D6_APC_3: 0x0
10042 23:24:30.850931 INFO: [APUAPC] D7_APC_0: 0xffffffff
10043 23:24:30.854002 INFO: [APUAPC] D7_APC_1: 0xffffffff
10044 23:24:30.857393 INFO: [APUAPC] D7_APC_2: 0x3fffff
10045 23:24:30.860735 INFO: [APUAPC] D7_APC_3: 0x0
10046 23:24:30.864230 INFO: [APUAPC] D8_APC_0: 0xffffffff
10047 23:24:30.867634 INFO: [APUAPC] D8_APC_1: 0xffffffff
10048 23:24:30.871009 INFO: [APUAPC] D8_APC_2: 0x3fffff
10049 23:24:30.873952 INFO: [APUAPC] D8_APC_3: 0x0
10050 23:24:30.877377 INFO: [APUAPC] D9_APC_0: 0xffffffff
10051 23:24:30.880594 INFO: [APUAPC] D9_APC_1: 0xffffffff
10052 23:24:30.884015 INFO: [APUAPC] D9_APC_2: 0x3fffff
10053 23:24:30.884111 INFO: [APUAPC] D9_APC_3: 0x0
10054 23:24:30.890604 INFO: [APUAPC] D10_APC_0: 0xffffffff
10055 23:24:30.894081 INFO: [APUAPC] D10_APC_1: 0xffffffff
10056 23:24:30.897724 INFO: [APUAPC] D10_APC_2: 0x3fffff
10057 23:24:30.897838 INFO: [APUAPC] D10_APC_3: 0x0
10058 23:24:30.904122 INFO: [APUAPC] D11_APC_0: 0xffffffff
10059 23:24:30.907903 INFO: [APUAPC] D11_APC_1: 0xffffffff
10060 23:24:30.910664 INFO: [APUAPC] D11_APC_2: 0x3fffff
10061 23:24:30.913847 INFO: [APUAPC] D11_APC_3: 0x0
10062 23:24:30.917361 INFO: [APUAPC] D12_APC_0: 0xffffffff
10063 23:24:30.920657 INFO: [APUAPC] D12_APC_1: 0xffffffff
10064 23:24:30.923850 INFO: [APUAPC] D12_APC_2: 0x3fffff
10065 23:24:30.927233 INFO: [APUAPC] D12_APC_3: 0x0
10066 23:24:30.930635 INFO: [APUAPC] D13_APC_0: 0xffffffff
10067 23:24:30.933710 INFO: [APUAPC] D13_APC_1: 0xffffffff
10068 23:24:30.937234 INFO: [APUAPC] D13_APC_2: 0x3fffff
10069 23:24:30.940697 INFO: [APUAPC] D13_APC_3: 0x0
10070 23:24:30.943866 INFO: [APUAPC] D14_APC_0: 0xffffffff
10071 23:24:30.947279 INFO: [APUAPC] D14_APC_1: 0xffffffff
10072 23:24:30.950809 INFO: [APUAPC] D14_APC_2: 0x3fffff
10073 23:24:30.953815 INFO: [APUAPC] D14_APC_3: 0x0
10074 23:24:30.956842 INFO: [APUAPC] D15_APC_0: 0xffffffff
10075 23:24:30.960684 INFO: [APUAPC] D15_APC_1: 0xffffffff
10076 23:24:30.963835 INFO: [APUAPC] D15_APC_2: 0x3fffff
10077 23:24:30.967302 INFO: [APUAPC] D15_APC_3: 0x0
10078 23:24:30.967383 INFO: [APUAPC] APC_CON: 0x4
10079 23:24:30.970268 INFO: [NOCDAPC] D0_APC_0: 0x0
10080 23:24:30.974294 INFO: [NOCDAPC] D0_APC_1: 0x0
10081 23:24:30.976911 INFO: [NOCDAPC] D1_APC_0: 0x0
10082 23:24:30.980568 INFO: [NOCDAPC] D1_APC_1: 0xfff
10083 23:24:30.983894 INFO: [NOCDAPC] D2_APC_0: 0x0
10084 23:24:30.987337 INFO: [NOCDAPC] D2_APC_1: 0xfff
10085 23:24:30.990348 INFO: [NOCDAPC] D3_APC_0: 0x0
10086 23:24:30.994223 INFO: [NOCDAPC] D3_APC_1: 0xfff
10087 23:24:30.994298 INFO: [NOCDAPC] D4_APC_0: 0x0
10088 23:24:30.997301 INFO: [NOCDAPC] D4_APC_1: 0xfff
10089 23:24:31.000729 INFO: [NOCDAPC] D5_APC_0: 0x0
10090 23:24:31.004209 INFO: [NOCDAPC] D5_APC_1: 0xfff
10091 23:24:31.007237 INFO: [NOCDAPC] D6_APC_0: 0x0
10092 23:24:31.010588 INFO: [NOCDAPC] D6_APC_1: 0xfff
10093 23:24:31.013855 INFO: [NOCDAPC] D7_APC_0: 0x0
10094 23:24:31.017636 INFO: [NOCDAPC] D7_APC_1: 0xfff
10095 23:24:31.020315 INFO: [NOCDAPC] D8_APC_0: 0x0
10096 23:24:31.023853 INFO: [NOCDAPC] D8_APC_1: 0xfff
10097 23:24:31.023950 INFO: [NOCDAPC] D9_APC_0: 0x0
10098 23:24:31.027560 INFO: [NOCDAPC] D9_APC_1: 0xfff
10099 23:24:31.030374 INFO: [NOCDAPC] D10_APC_0: 0x0
10100 23:24:31.033846 INFO: [NOCDAPC] D10_APC_1: 0xfff
10101 23:24:31.037443 INFO: [NOCDAPC] D11_APC_0: 0x0
10102 23:24:31.040648 INFO: [NOCDAPC] D11_APC_1: 0xfff
10103 23:24:31.043922 INFO: [NOCDAPC] D12_APC_0: 0x0
10104 23:24:31.047550 INFO: [NOCDAPC] D12_APC_1: 0xfff
10105 23:24:31.050387 INFO: [NOCDAPC] D13_APC_0: 0x0
10106 23:24:31.053602 INFO: [NOCDAPC] D13_APC_1: 0xfff
10107 23:24:31.057317 INFO: [NOCDAPC] D14_APC_0: 0x0
10108 23:24:31.060630 INFO: [NOCDAPC] D14_APC_1: 0xfff
10109 23:24:31.063655 INFO: [NOCDAPC] D15_APC_0: 0x0
10110 23:24:31.067021 INFO: [NOCDAPC] D15_APC_1: 0xfff
10111 23:24:31.067102 INFO: [NOCDAPC] APC_CON: 0x4
10112 23:24:31.070604 INFO: [APUAPC] set_apusys_apc done
10113 23:24:31.073556 INFO: [DEVAPC] devapc_init done
10114 23:24:31.080479 INFO: GICv3 without legacy support detected.
10115 23:24:31.084073 INFO: ARM GICv3 driver initialized in EL3
10116 23:24:31.087799 INFO: Maximum SPI INTID supported: 639
10117 23:24:31.090359 INFO: BL31: Initializing runtime services
10118 23:24:31.097242 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10119 23:24:31.100626 INFO: SPM: enable CPC mode
10120 23:24:31.103928 INFO: mcdi ready for mcusys-off-idle and system suspend
10121 23:24:31.111159 INFO: BL31: Preparing for EL3 exit to normal world
10122 23:24:31.114216 INFO: Entry point address = 0x80000000
10123 23:24:31.114297 INFO: SPSR = 0x8
10124 23:24:31.120688
10125 23:24:31.120769
10126 23:24:31.120871
10127 23:24:31.124060 Starting depthcharge on Spherion...
10128 23:24:31.124157
10129 23:24:31.124249 Wipe memory regions:
10130 23:24:31.124341
10131 23:24:31.125075 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10132 23:24:31.125172 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10133 23:24:31.125255 Setting prompt string to ['asurada:']
10134 23:24:31.125338 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10135 23:24:31.127287 [0x00000040000000, 0x00000054600000)
10136 23:24:31.249942
10137 23:24:31.250081 [0x00000054660000, 0x00000080000000)
10138 23:24:31.510460
10139 23:24:31.510613 [0x000000821a7280, 0x000000ffe64000)
10140 23:24:32.255073
10141 23:24:32.255221 [0x00000100000000, 0x00000240000000)
10142 23:24:34.145322
10143 23:24:34.149113 Initializing XHCI USB controller at 0x11200000.
10144 23:24:35.186457
10145 23:24:35.189811 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10146 23:24:35.190231
10147 23:24:35.190602
10148 23:24:35.190913
10149 23:24:35.191672 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10151 23:24:35.292743 asurada: tftpboot 192.168.201.1 13248467/tftp-deploy-q9kurlc5/kernel/image.itb 13248467/tftp-deploy-q9kurlc5/kernel/cmdline
10152 23:24:35.293287 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10153 23:24:35.293797 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10154 23:24:35.298338 tftpboot 192.168.201.1 13248467/tftp-deploy-q9kurlc5/kernel/image.itp-deploy-q9kurlc5/kernel/cmdline
10155 23:24:35.298825
10156 23:24:35.299156 Waiting for link
10157 23:24:35.458451
10158 23:24:35.458802 R8152: Initializing
10159 23:24:35.459044
10160 23:24:35.461779 Version 6 (ocp_data = 5c30)
10161 23:24:35.462078
10162 23:24:35.465089 R8152: Done initializing
10163 23:24:35.465384
10164 23:24:35.465618 Adding net device
10165 23:24:37.333254
10166 23:24:37.333392 done.
10167 23:24:37.333458
10168 23:24:37.333518 MAC: 00:24:32:30:78:52
10169 23:24:37.333577
10170 23:24:37.336841 Sending DHCP discover... done.
10171 23:24:37.336915
10172 23:24:37.340047 Waiting for reply... done.
10173 23:24:37.340153
10174 23:24:37.343017 Sending DHCP request... done.
10175 23:24:37.343098
10176 23:24:37.346548 Waiting for reply... done.
10177 23:24:37.346628
10178 23:24:37.346693 My ip is 192.168.201.14
10179 23:24:37.346753
10180 23:24:37.349770 The DHCP server ip is 192.168.201.1
10181 23:24:37.349851
10182 23:24:37.356685 TFTP server IP predefined by user: 192.168.201.1
10183 23:24:37.356766
10184 23:24:37.363521 Bootfile predefined by user: 13248467/tftp-deploy-q9kurlc5/kernel/image.itb
10185 23:24:37.363603
10186 23:24:37.363666 Sending tftp read request... done.
10187 23:24:37.363726
10188 23:24:37.369905 Waiting for the transfer...
10189 23:24:37.369988
10190 23:24:37.915950 00000000 ################################################################
10191 23:24:37.916092
10192 23:24:38.473999 00080000 ################################################################
10193 23:24:38.474142
10194 23:24:39.032951 00100000 ################################################################
10195 23:24:39.033100
10196 23:24:39.589952 00180000 ################################################################
10197 23:24:39.590101
10198 23:24:40.154371 00200000 ################################################################
10199 23:24:40.154560
10200 23:24:40.708403 00280000 ################################################################
10201 23:24:40.708541
10202 23:24:41.263619 00300000 ################################################################
10203 23:24:41.263784
10204 23:24:41.852019 00380000 ################################################################
10205 23:24:41.852545
10206 23:24:42.559669 00400000 ################################################################
10207 23:24:42.560194
10208 23:24:43.272115 00480000 ################################################################
10209 23:24:43.272666
10210 23:24:43.987159 00500000 ################################################################
10211 23:24:43.987661
10212 23:24:44.691419 00580000 ################################################################
10213 23:24:44.691939
10214 23:24:45.362620 00600000 ################################################################
10215 23:24:45.362761
10216 23:24:46.051937 00680000 ################################################################
10217 23:24:46.052490
10218 23:24:46.784666 00700000 ################################################################
10219 23:24:46.785192
10220 23:24:47.504794 00780000 ################################################################
10221 23:24:47.505370
10222 23:24:48.229243 00800000 ################################################################
10223 23:24:48.229757
10224 23:24:48.939425 00880000 ################################################################
10225 23:24:48.939913
10226 23:24:49.662196 00900000 ################################################################
10227 23:24:49.662818
10228 23:24:50.382319 00980000 ################################################################
10229 23:24:50.382934
10230 23:24:51.028558 00a00000 ################################################################
10231 23:24:51.028708
10232 23:24:51.587417 00a80000 ################################################################
10233 23:24:51.587600
10234 23:24:52.130759 00b00000 ################################################################
10235 23:24:52.130910
10236 23:24:52.680322 00b80000 ################################################################
10237 23:24:52.680478
10238 23:24:53.257534 00c00000 ################################################################
10239 23:24:53.257688
10240 23:24:53.884515 00c80000 ################################################################
10241 23:24:53.885025
10242 23:24:54.607955 00d00000 ################################################################
10243 23:24:54.608525
10244 23:24:55.332852 00d80000 ################################################################
10245 23:24:55.333378
10246 23:24:56.043934 00e00000 ################################################################
10247 23:24:56.044447
10248 23:24:56.774727 00e80000 ################################################################
10249 23:24:56.775273
10250 23:24:57.486209 00f00000 ################################################################
10251 23:24:57.486797
10252 23:24:58.219274 00f80000 ################################################################
10253 23:24:58.219799
10254 23:24:58.897479 01000000 ################################################################
10255 23:24:58.898136
10256 23:24:59.570666 01080000 ################################################################
10257 23:24:59.570825
10258 23:25:00.190382 01100000 ################################################################
10259 23:25:00.190527
10260 23:25:00.886899 01180000 ################################################################
10261 23:25:00.887427
10262 23:25:01.589923 01200000 ################################################################
10263 23:25:01.590510
10264 23:25:02.261990 01280000 ################################################################
10265 23:25:02.262492
10266 23:25:02.937940 01300000 ################################################################
10267 23:25:02.938078
10268 23:25:03.520418 01380000 ################################################################
10269 23:25:03.520562
10270 23:25:04.073381 01400000 ################################################################
10271 23:25:04.073519
10272 23:25:04.617116 01480000 ################################################################
10273 23:25:04.617252
10274 23:25:05.181643 01500000 ################################################################
10275 23:25:05.182195
10276 23:25:05.801742 01580000 ################################################################
10277 23:25:05.801882
10278 23:25:06.485183 01600000 ################################################################
10279 23:25:06.485810
10280 23:25:07.120990 01680000 ################################################################
10281 23:25:07.121632
10282 23:25:07.790222 01700000 ################################################################
10283 23:25:07.790363
10284 23:25:08.469941 01780000 ################################################################
10285 23:25:08.470560
10286 23:25:09.148076 01800000 ################################################################
10287 23:25:09.148589
10288 23:25:09.836877 01880000 ################################################################
10289 23:25:09.837462
10290 23:25:10.531937 01900000 ################################################################
10291 23:25:10.532437
10292 23:25:11.214051 01980000 ################################################################
10293 23:25:11.214203
10294 23:25:11.881646 01a00000 ################################################################
10295 23:25:11.882142
10296 23:25:12.591211 01a80000 ################################################################
10297 23:25:12.591719
10298 23:25:13.170181 01b00000 ################################################################
10299 23:25:13.170322
10300 23:25:13.757446 01b80000 ################################################################
10301 23:25:13.757647
10302 23:25:14.382321 01c00000 ################################################################
10303 23:25:14.382508
10304 23:25:15.023718 01c80000 ################################################################
10305 23:25:15.024230
10306 23:25:15.687945 01d00000 ################################################################
10307 23:25:15.688482
10308 23:25:16.244489 01d80000 ################################################################
10309 23:25:16.244642
10310 23:25:16.552693 01e00000 ################################## done.
10311 23:25:16.552848
10312 23:25:16.556077 The bootfile was 31727662 bytes long.
10313 23:25:16.556173
10314 23:25:16.559473 Sending tftp read request... done.
10315 23:25:16.559573
10316 23:25:16.559673 Waiting for the transfer...
10317 23:25:16.559766
10318 23:25:16.562520 00000000 # done.
10319 23:25:16.562620
10320 23:25:16.569681 Command line loaded dynamically from TFTP file: 13248467/tftp-deploy-q9kurlc5/kernel/cmdline
10321 23:25:16.569796
10322 23:25:16.592854 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248467/extract-nfsrootfs-gyhcfl92,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10323 23:25:16.593059
10324 23:25:16.593196 Loading FIT.
10325 23:25:16.593322
10326 23:25:16.596222 Image ramdisk-1 has 18771126 bytes.
10327 23:25:16.596418
10328 23:25:16.599134 Image fdt-1 has 47230 bytes.
10329 23:25:16.599370
10330 23:25:16.602568 Image kernel-1 has 12907270 bytes.
10331 23:25:16.602803
10332 23:25:16.612990 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10333 23:25:16.613466
10334 23:25:16.629470 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10335 23:25:16.629910
10336 23:25:16.636173 Choosing best match conf-1 for compat google,spherion-rev2.
10337 23:25:16.636698
10338 23:25:16.639707 Connected to device vid:did:rid of 1ae0:0028:00
10339 23:25:16.651026
10340 23:25:16.654300 tpm_get_response: command 0x17b, return code 0x0
10341 23:25:16.654381
10342 23:25:16.657697 ec_init: CrosEC protocol v3 supported (256, 248)
10343 23:25:16.662523
10344 23:25:16.666010 tpm_cleanup: add release locality here.
10345 23:25:16.666087
10346 23:25:16.666156 Shutting down all USB controllers.
10347 23:25:16.669141
10348 23:25:16.669213 Removing current net device
10349 23:25:16.669274
10350 23:25:16.676008 Exiting depthcharge with code 4 at timestamp: 74993226
10351 23:25:16.676085
10352 23:25:16.679513 LZMA decompressing kernel-1 to 0x821a6718
10353 23:25:16.679586
10354 23:25:16.682551 LZMA decompressing kernel-1 to 0x40000000
10355 23:25:18.275916
10356 23:25:18.276554 jumping to kernel
10357 23:25:18.278251 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10358 23:25:18.278847 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10359 23:25:18.279268 Setting prompt string to ['Linux version [0-9]']
10360 23:25:18.279624 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10361 23:25:18.280007 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10362 23:25:18.357958
10363 23:25:18.361263 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10364 23:25:18.365619 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10365 23:25:18.366092 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10366 23:25:18.366488 Setting prompt string to []
10367 23:25:18.366874 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10368 23:25:18.367230 Using line separator: #'\n'#
10369 23:25:18.367591 No login prompt set.
10370 23:25:18.367964 Parsing kernel messages
10371 23:25:18.368252 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10372 23:25:18.368762 [login-action] Waiting for messages, (timeout 00:03:38)
10373 23:25:18.369083 Waiting using forced prompt support (timeout 00:01:49)
10374 23:25:18.384983 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10375 23:25:18.388384 [ 0.000000] random: crng init done
10376 23:25:18.395268 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10377 23:25:18.395736 [ 0.000000] efi: UEFI not found.
10378 23:25:18.404506 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10379 23:25:18.411423 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10380 23:25:18.421095 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10381 23:25:18.431630 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10382 23:25:18.438026 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10383 23:25:18.441445 [ 0.000000] printk: bootconsole [mtk8250] enabled
10384 23:25:18.450119 [ 0.000000] NUMA: No NUMA configuration found
10385 23:25:18.456409 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10386 23:25:18.463583 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10387 23:25:18.464020 [ 0.000000] Zone ranges:
10388 23:25:18.469465 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10389 23:25:18.472953 [ 0.000000] DMA32 empty
10390 23:25:18.480014 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10391 23:25:18.482964 [ 0.000000] Movable zone start for each node
10392 23:25:18.486166 [ 0.000000] Early memory node ranges
10393 23:25:18.492912 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10394 23:25:18.499984 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10395 23:25:18.506478 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10396 23:25:18.513140 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10397 23:25:18.519483 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10398 23:25:18.526365 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10399 23:25:18.582990 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10400 23:25:18.589275 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10401 23:25:18.595890 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10402 23:25:18.599628 [ 0.000000] psci: probing for conduit method from DT.
10403 23:25:18.605633 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10404 23:25:18.609266 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10405 23:25:18.615855 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10406 23:25:18.619452 [ 0.000000] psci: SMC Calling Convention v1.2
10407 23:25:18.625607 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10408 23:25:18.629222 [ 0.000000] Detected VIPT I-cache on CPU0
10409 23:25:18.636079 [ 0.000000] CPU features: detected: GIC system register CPU interface
10410 23:25:18.642651 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10411 23:25:18.648677 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10412 23:25:18.656069 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10413 23:25:18.662265 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10414 23:25:18.669013 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10415 23:25:18.675927 [ 0.000000] alternatives: applying boot alternatives
10416 23:25:18.679524 [ 0.000000] Fallback order for Node 0: 0
10417 23:25:18.685887 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10418 23:25:18.689314 [ 0.000000] Policy zone: Normal
10419 23:25:18.712646 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248467/extract-nfsrootfs-gyhcfl92,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10420 23:25:18.726528 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10421 23:25:18.736078 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10422 23:25:18.745716 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10423 23:25:18.752465 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10424 23:25:18.755903 <6>[ 0.000000] software IO TLB: area num 8.
10425 23:25:18.813996 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10426 23:25:18.962663 <6>[ 0.000000] Memory: 7946240K/8385536K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 406528K reserved, 32768K cma-reserved)
10427 23:25:18.969504 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10428 23:25:18.976723 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10429 23:25:18.979588 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10430 23:25:18.986027 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10431 23:25:18.992597 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10432 23:25:18.995817 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10433 23:25:19.006568 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10434 23:25:19.012784 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10435 23:25:19.015935 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10436 23:25:19.023540 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10437 23:25:19.026896 <6>[ 0.000000] GICv3: 608 SPIs implemented
10438 23:25:19.034234 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10439 23:25:19.037009 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10440 23:25:19.040418 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10441 23:25:19.050241 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10442 23:25:19.060621 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10443 23:25:19.073630 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10444 23:25:19.080319 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10445 23:25:19.089135 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10446 23:25:19.102740 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10447 23:25:19.108718 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10448 23:25:19.115545 <6>[ 0.009179] Console: colour dummy device 80x25
10449 23:25:19.125802 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10450 23:25:19.129060 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10451 23:25:19.135550 <6>[ 0.029219] LSM: Security Framework initializing
10452 23:25:19.142122 <6>[ 0.034158] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10453 23:25:19.152410 <6>[ 0.041973] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10454 23:25:19.158904 <6>[ 0.051402] cblist_init_generic: Setting adjustable number of callback queues.
10455 23:25:19.165855 <6>[ 0.058847] cblist_init_generic: Setting shift to 3 and lim to 1.
10456 23:25:19.172317 <6>[ 0.065185] cblist_init_generic: Setting adjustable number of callback queues.
10457 23:25:19.178922 <6>[ 0.072612] cblist_init_generic: Setting shift to 3 and lim to 1.
10458 23:25:19.185684 <6>[ 0.079053] rcu: Hierarchical SRCU implementation.
10459 23:25:19.192010 <6>[ 0.084068] rcu: Max phase no-delay instances is 1000.
10460 23:25:19.198766 <6>[ 0.091080] EFI services will not be available.
10461 23:25:19.202133 <6>[ 0.096066] smp: Bringing up secondary CPUs ...
10462 23:25:19.209766 <6>[ 0.101119] Detected VIPT I-cache on CPU1
10463 23:25:19.216385 <6>[ 0.101190] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10464 23:25:19.223321 <6>[ 0.101222] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10465 23:25:19.226612 <6>[ 0.101559] Detected VIPT I-cache on CPU2
10466 23:25:19.232991 <6>[ 0.101610] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10467 23:25:19.239750 <6>[ 0.101628] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10468 23:25:19.246757 <6>[ 0.101889] Detected VIPT I-cache on CPU3
10469 23:25:19.252894 <6>[ 0.101937] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10470 23:25:19.259622 <6>[ 0.101952] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10471 23:25:19.262923 <6>[ 0.102258] CPU features: detected: Spectre-v4
10472 23:25:19.269222 <6>[ 0.102265] CPU features: detected: Spectre-BHB
10473 23:25:19.272875 <6>[ 0.102271] Detected PIPT I-cache on CPU4
10474 23:25:19.279486 <6>[ 0.102330] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10475 23:25:19.285873 <6>[ 0.102347] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10476 23:25:19.292922 <6>[ 0.102642] Detected PIPT I-cache on CPU5
10477 23:25:19.298975 <6>[ 0.102706] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10478 23:25:19.305748 <6>[ 0.102722] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10479 23:25:19.309186 <6>[ 0.103005] Detected PIPT I-cache on CPU6
10480 23:25:19.315797 <6>[ 0.103071] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10481 23:25:19.322778 <6>[ 0.103087] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10482 23:25:19.329001 <6>[ 0.103384] Detected PIPT I-cache on CPU7
10483 23:25:19.335730 <6>[ 0.103450] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10484 23:25:19.342290 <6>[ 0.103466] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10485 23:25:19.345868 <6>[ 0.103514] smp: Brought up 1 node, 8 CPUs
10486 23:25:19.352247 <6>[ 0.244897] SMP: Total of 8 processors activated.
10487 23:25:19.355594 <6>[ 0.249819] CPU features: detected: 32-bit EL0 Support
10488 23:25:19.365651 <6>[ 0.255182] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10489 23:25:19.371997 <6>[ 0.264037] CPU features: detected: Common not Private translations
10490 23:25:19.378728 <6>[ 0.270514] CPU features: detected: CRC32 instructions
10491 23:25:19.382236 <6>[ 0.275865] CPU features: detected: RCpc load-acquire (LDAPR)
10492 23:25:19.388989 <6>[ 0.281825] CPU features: detected: LSE atomic instructions
10493 23:25:19.395181 <6>[ 0.287642] CPU features: detected: Privileged Access Never
10494 23:25:19.402085 <6>[ 0.293422] CPU features: detected: RAS Extension Support
10495 23:25:19.408646 <6>[ 0.299066] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10496 23:25:19.412032 <6>[ 0.306286] CPU: All CPU(s) started at EL2
10497 23:25:19.418533 <6>[ 0.310629] alternatives: applying system-wide alternatives
10498 23:25:19.427622 <6>[ 0.321451] devtmpfs: initialized
10499 23:25:19.440036 <6>[ 0.330310] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10500 23:25:19.449804 <6>[ 0.340266] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10501 23:25:19.456359 <6>[ 0.348319] pinctrl core: initialized pinctrl subsystem
10502 23:25:19.459815 <6>[ 0.354986] DMI not present or invalid.
10503 23:25:19.466664 <6>[ 0.359398] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10504 23:25:19.476515 <6>[ 0.366290] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10505 23:25:19.482908 <6>[ 0.373874] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10506 23:25:19.493085 <6>[ 0.382097] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10507 23:25:19.496504 <6>[ 0.390339] audit: initializing netlink subsys (disabled)
10508 23:25:19.506524 <5>[ 0.396033] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10509 23:25:19.513247 <6>[ 0.396735] thermal_sys: Registered thermal governor 'step_wise'
10510 23:25:19.519692 <6>[ 0.403999] thermal_sys: Registered thermal governor 'power_allocator'
10511 23:25:19.523287 <6>[ 0.410252] cpuidle: using governor menu
10512 23:25:19.526303 <6>[ 0.421213] NET: Registered PF_QIPCRTR protocol family
10513 23:25:19.536504 <6>[ 0.426713] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10514 23:25:19.539556 <6>[ 0.433819] ASID allocator initialised with 32768 entries
10515 23:25:19.546332 <6>[ 0.440381] Serial: AMBA PL011 UART driver
10516 23:25:19.555325 <4>[ 0.449205] Trying to register duplicate clock ID: 134
10517 23:25:19.609661 <6>[ 0.506800] KASLR enabled
10518 23:25:19.624138 <6>[ 0.514556] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10519 23:25:19.630854 <6>[ 0.521568] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10520 23:25:19.637452 <6>[ 0.528057] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10521 23:25:19.643930 <6>[ 0.535061] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10522 23:25:19.650825 <6>[ 0.541545] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10523 23:25:19.657730 <6>[ 0.548546] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10524 23:25:19.664134 <6>[ 0.555032] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10525 23:25:19.670777 <6>[ 0.562034] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10526 23:25:19.673553 <6>[ 0.569554] ACPI: Interpreter disabled.
10527 23:25:19.682570 <6>[ 0.576016] iommu: Default domain type: Translated
10528 23:25:19.689067 <6>[ 0.581127] iommu: DMA domain TLB invalidation policy: strict mode
10529 23:25:19.692646 <5>[ 0.587789] SCSI subsystem initialized
10530 23:25:19.698989 <6>[ 0.591955] usbcore: registered new interface driver usbfs
10531 23:25:19.705838 <6>[ 0.597688] usbcore: registered new interface driver hub
10532 23:25:19.709467 <6>[ 0.603239] usbcore: registered new device driver usb
10533 23:25:19.716009 <6>[ 0.609339] pps_core: LinuxPPS API ver. 1 registered
10534 23:25:19.725787 <6>[ 0.614530] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10535 23:25:19.728998 <6>[ 0.623877] PTP clock support registered
10536 23:25:19.732723 <6>[ 0.628121] EDAC MC: Ver: 3.0.0
10537 23:25:19.739646 <6>[ 0.633288] FPGA manager framework
10538 23:25:19.746371 <6>[ 0.636969] Advanced Linux Sound Architecture Driver Initialized.
10539 23:25:19.749352 <6>[ 0.643752] vgaarb: loaded
10540 23:25:19.756261 <6>[ 0.646931] clocksource: Switched to clocksource arch_sys_counter
10541 23:25:19.759697 <5>[ 0.653375] VFS: Disk quotas dquot_6.6.0
10542 23:25:19.766022 <6>[ 0.657563] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10543 23:25:19.768988 <6>[ 0.664750] pnp: PnP ACPI: disabled
10544 23:25:19.777729 <6>[ 0.671429] NET: Registered PF_INET protocol family
10545 23:25:19.787783 <6>[ 0.677037] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10546 23:25:19.798839 <6>[ 0.689352] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10547 23:25:19.808739 <6>[ 0.698167] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10548 23:25:19.815251 <6>[ 0.706133] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10549 23:25:19.825016 <6>[ 0.714836] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10550 23:25:19.831947 <6>[ 0.724594] TCP: Hash tables configured (established 65536 bind 65536)
10551 23:25:19.838328 <6>[ 0.731458] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10552 23:25:19.848622 <6>[ 0.738658] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10553 23:25:19.854926 <6>[ 0.746366] NET: Registered PF_UNIX/PF_LOCAL protocol family
10554 23:25:19.858103 <6>[ 0.752514] RPC: Registered named UNIX socket transport module.
10555 23:25:19.865479 <6>[ 0.758665] RPC: Registered udp transport module.
10556 23:25:19.867983 <6>[ 0.763597] RPC: Registered tcp transport module.
10557 23:25:19.874922 <6>[ 0.768528] RPC: Registered tcp NFSv4.1 backchannel transport module.
10558 23:25:19.881539 <6>[ 0.775195] PCI: CLS 0 bytes, default 64
10559 23:25:19.884826 <6>[ 0.779529] Unpacking initramfs...
10560 23:25:19.900974 <6>[ 0.791491] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10561 23:25:19.911697 <6>[ 0.800164] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10562 23:25:19.914810 <6>[ 0.809020] kvm [1]: IPA Size Limit: 40 bits
10563 23:25:19.921580 <6>[ 0.813546] kvm [1]: GICv3: no GICV resource entry
10564 23:25:19.925072 <6>[ 0.818564] kvm [1]: disabling GICv2 emulation
10565 23:25:19.931150 <6>[ 0.823253] kvm [1]: GIC system register CPU interface enabled
10566 23:25:19.934605 <6>[ 0.829423] kvm [1]: vgic interrupt IRQ18
10567 23:25:19.941224 <6>[ 0.833778] kvm [1]: VHE mode initialized successfully
10568 23:25:19.947847 <5>[ 0.840224] Initialise system trusted keyrings
10569 23:25:19.954222 <6>[ 0.845031] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10570 23:25:19.961082 <6>[ 0.855086] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10571 23:25:19.967923 <5>[ 0.861477] NFS: Registering the id_resolver key type
10572 23:25:19.971235 <5>[ 0.866775] Key type id_resolver registered
10573 23:25:19.977794 <5>[ 0.871190] Key type id_legacy registered
10574 23:25:19.984437 <6>[ 0.875465] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10575 23:25:19.991074 <6>[ 0.882386] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10576 23:25:19.997496 <6>[ 0.890094] 9p: Installing v9fs 9p2000 file system support
10577 23:25:20.035552 <5>[ 0.928725] Key type asymmetric registered
10578 23:25:20.038235 <5>[ 0.933056] Asymmetric key parser 'x509' registered
10579 23:25:20.048603 <6>[ 0.938212] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10580 23:25:20.051409 <6>[ 0.945827] io scheduler mq-deadline registered
10581 23:25:20.054612 <6>[ 0.950601] io scheduler kyber registered
10582 23:25:20.074116 <6>[ 0.967937] EINJ: ACPI disabled.
10583 23:25:20.106350 <4>[ 0.993798] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10584 23:25:20.116154 <4>[ 1.004453] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 23:25:20.131011 <6>[ 1.025245] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10586 23:25:20.139328 <6>[ 1.033343] printk: console [ttyS0] disabled
10587 23:25:20.167044 <6>[ 1.057968] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10588 23:25:20.173502 <6>[ 1.067444] printk: console [ttyS0] enabled
10589 23:25:20.176936 <6>[ 1.067444] printk: console [ttyS0] enabled
10590 23:25:20.183734 <6>[ 1.076343] printk: bootconsole [mtk8250] disabled
10591 23:25:20.187529 <6>[ 1.076343] printk: bootconsole [mtk8250] disabled
10592 23:25:20.193752 <6>[ 1.087654] SuperH (H)SCI(F) driver initialized
10593 23:25:20.197092 <6>[ 1.092919] msm_serial: driver initialized
10594 23:25:20.211209 <6>[ 1.101904] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10595 23:25:20.221594 <6>[ 1.110452] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10596 23:25:20.228233 <6>[ 1.118997] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10597 23:25:20.237747 <6>[ 1.127626] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10598 23:25:20.244659 <6>[ 1.136331] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10599 23:25:20.254508 <6>[ 1.145053] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10600 23:25:20.264444 <6>[ 1.153595] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10601 23:25:20.271297 <6>[ 1.162388] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10602 23:25:20.281463 <6>[ 1.170934] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10603 23:25:20.292807 <6>[ 1.186672] loop: module loaded
10604 23:25:20.299701 <6>[ 1.192679] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10605 23:25:20.321942 <4>[ 1.216054] mtk-pmic-keys: Failed to locate of_node [id: -1]
10606 23:25:20.328692 <6>[ 1.222964] megasas: 07.719.03.00-rc1
10607 23:25:20.339075 <6>[ 1.232794] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10608 23:25:20.348460 <6>[ 1.242311] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10609 23:25:20.365178 <6>[ 1.259124] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10610 23:25:20.422183 <6>[ 1.309274] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10611 23:25:20.681834 <6>[ 1.576083] Freeing initrd memory: 18328K
10612 23:25:20.693478 <6>[ 1.587652] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10613 23:25:20.704941 <6>[ 1.598610] tun: Universal TUN/TAP device driver, 1.6
10614 23:25:20.707917 <6>[ 1.604683] thunder_xcv, ver 1.0
10615 23:25:20.711635 <6>[ 1.608191] thunder_bgx, ver 1.0
10616 23:25:20.715035 <6>[ 1.611687] nicpf, ver 1.0
10617 23:25:20.725481 <6>[ 1.615723] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10618 23:25:20.728958 <6>[ 1.623199] hns3: Copyright (c) 2017 Huawei Corporation.
10619 23:25:20.732365 <6>[ 1.628787] hclge is initializing
10620 23:25:20.738986 <6>[ 1.632363] e1000: Intel(R) PRO/1000 Network Driver
10621 23:25:20.745388 <6>[ 1.637493] e1000: Copyright (c) 1999-2006 Intel Corporation.
10622 23:25:20.748706 <6>[ 1.643509] e1000e: Intel(R) PRO/1000 Network Driver
10623 23:25:20.755345 <6>[ 1.648725] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10624 23:25:20.761936 <6>[ 1.654911] igb: Intel(R) Gigabit Ethernet Network Driver
10625 23:25:20.768736 <6>[ 1.660561] igb: Copyright (c) 2007-2014 Intel Corporation.
10626 23:25:20.775210 <6>[ 1.666398] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10627 23:25:20.778963 <6>[ 1.672916] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10628 23:25:20.785360 <6>[ 1.679400] sky2: driver version 1.30
10629 23:25:20.792586 <6>[ 1.684419] VFIO - User Level meta-driver version: 0.3
10630 23:25:20.799026 <6>[ 1.692692] usbcore: registered new interface driver usb-storage
10631 23:25:20.805597 <6>[ 1.699147] usbcore: registered new device driver onboard-usb-hub
10632 23:25:20.814169 <6>[ 1.708354] mt6397-rtc mt6359-rtc: registered as rtc0
10633 23:25:20.824644 <6>[ 1.713827] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:25:20 UTC (1712186720)
10634 23:25:20.828193 <6>[ 1.723428] i2c_dev: i2c /dev entries driver
10635 23:25:20.844760 <6>[ 1.735143] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10636 23:25:20.851070 <4>[ 1.743887] cpu cpu0: supply cpu not found, using dummy regulator
10637 23:25:20.857920 <4>[ 1.750307] cpu cpu1: supply cpu not found, using dummy regulator
10638 23:25:20.864550 <4>[ 1.756728] cpu cpu2: supply cpu not found, using dummy regulator
10639 23:25:20.871392 <4>[ 1.763141] cpu cpu3: supply cpu not found, using dummy regulator
10640 23:25:20.878130 <4>[ 1.769538] cpu cpu4: supply cpu not found, using dummy regulator
10641 23:25:20.884414 <4>[ 1.775935] cpu cpu5: supply cpu not found, using dummy regulator
10642 23:25:20.891135 <4>[ 1.782328] cpu cpu6: supply cpu not found, using dummy regulator
10643 23:25:20.894663 <4>[ 1.788742] cpu cpu7: supply cpu not found, using dummy regulator
10644 23:25:20.916024 <6>[ 1.809375] cpu cpu0: EM: created perf domain
10645 23:25:20.918987 <6>[ 1.814289] cpu cpu4: EM: created perf domain
10646 23:25:20.925992 <6>[ 1.819873] sdhci: Secure Digital Host Controller Interface driver
10647 23:25:20.932858 <6>[ 1.826305] sdhci: Copyright(c) Pierre Ossman
10648 23:25:20.939325 <6>[ 1.831259] Synopsys Designware Multimedia Card Interface Driver
10649 23:25:20.946126 <6>[ 1.837894] sdhci-pltfm: SDHCI platform and OF driver helper
10650 23:25:20.949457 <6>[ 1.837941] mmc0: CQHCI version 5.10
10651 23:25:20.955827 <6>[ 1.848162] ledtrig-cpu: registered to indicate activity on CPUs
10652 23:25:20.962649 <6>[ 1.855129] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10653 23:25:20.969019 <6>[ 1.862178] usbcore: registered new interface driver usbhid
10654 23:25:20.972737 <6>[ 1.868003] usbhid: USB HID core driver
10655 23:25:20.978889 <6>[ 1.872218] spi_master spi0: will run message pump with realtime priority
10656 23:25:21.020897 <6>[ 1.907842] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10657 23:25:21.039599 <6>[ 1.922737] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10658 23:25:21.046389 <6>[ 1.937722] cros-ec-spi spi0.0: Chrome EC device registered
10659 23:25:21.049582 <6>[ 1.943720] mmc0: Command Queue Engine enabled
10660 23:25:21.056695 <6>[ 1.948467] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10661 23:25:21.062846 <6>[ 1.955999] mmcblk0: mmc0:0001 DA4128 116 GiB
10662 23:25:21.071239 <6>[ 1.964881] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10663 23:25:21.077976 <6>[ 1.972201] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10664 23:25:21.088365 <6>[ 1.976318] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10665 23:25:21.091829 <6>[ 1.978125] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10666 23:25:21.098308 <6>[ 1.988010] NET: Registered PF_PACKET protocol family
10667 23:25:21.105857 <6>[ 1.992642] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10668 23:25:21.108360 <6>[ 1.997349] 9pnet: Installing 9P2000 support
10669 23:25:21.114951 <5>[ 2.008356] Key type dns_resolver registered
10670 23:25:21.118236 <6>[ 2.013333] registered taskstats version 1
10671 23:25:21.125282 <5>[ 2.017719] Loading compiled-in X.509 certificates
10672 23:25:21.152904 <4>[ 2.040164] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10673 23:25:21.162776 <4>[ 2.050936] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10674 23:25:21.169630 <3>[ 2.061474] debugfs: File 'uA_load' in directory '/' already present!
10675 23:25:21.176378 <3>[ 2.068229] debugfs: File 'min_uV' in directory '/' already present!
10676 23:25:21.183095 <3>[ 2.074847] debugfs: File 'max_uV' in directory '/' already present!
10677 23:25:21.189314 <3>[ 2.081459] debugfs: File 'constraint_flags' in directory '/' already present!
10678 23:25:21.200718 <3>[ 2.091170] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10679 23:25:21.210983 <6>[ 2.104425] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10680 23:25:21.217072 <6>[ 2.111188] xhci-mtk 11200000.usb: xHCI Host Controller
10681 23:25:21.223775 <6>[ 2.116697] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10682 23:25:21.233697 <6>[ 2.124547] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10683 23:25:21.240960 <6>[ 2.133960] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10684 23:25:21.247143 <6>[ 2.140024] xhci-mtk 11200000.usb: xHCI Host Controller
10685 23:25:21.254391 <6>[ 2.145499] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10686 23:25:21.260277 <6>[ 2.153144] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10687 23:25:21.267024 <6>[ 2.161014] hub 1-0:1.0: USB hub found
10688 23:25:21.270570 <6>[ 2.165032] hub 1-0:1.0: 1 port detected
10689 23:25:21.277077 <6>[ 2.169308] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10690 23:25:21.284101 <6>[ 2.178048] hub 2-0:1.0: USB hub found
10691 23:25:21.287942 <6>[ 2.182067] hub 2-0:1.0: 1 port detected
10692 23:25:21.296200 <6>[ 2.190017] mtk-msdc 11f70000.mmc: Got CD GPIO
10693 23:25:21.307796 <6>[ 2.197864] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10694 23:25:21.314796 <6>[ 2.205889] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10695 23:25:21.324163 <4>[ 2.213779] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10696 23:25:21.331024 <6>[ 2.223311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10697 23:25:21.341120 <6>[ 2.231388] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10698 23:25:21.347708 <6>[ 2.239399] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10699 23:25:21.357790 <6>[ 2.247324] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10700 23:25:21.364609 <6>[ 2.255141] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10701 23:25:21.374538 <6>[ 2.262959] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10702 23:25:21.381469 <6>[ 2.273168] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10703 23:25:21.390966 <6>[ 2.281532] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10704 23:25:21.398329 <6>[ 2.289876] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10705 23:25:21.407841 <6>[ 2.298214] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10706 23:25:21.414585 <6>[ 2.306552] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10707 23:25:21.424203 <6>[ 2.314892] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10708 23:25:21.434733 <6>[ 2.323230] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10709 23:25:21.440799 <6>[ 2.331567] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10710 23:25:21.450682 <6>[ 2.339904] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10711 23:25:21.457657 <6>[ 2.348241] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10712 23:25:21.467715 <6>[ 2.356578] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10713 23:25:21.473922 <6>[ 2.364915] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10714 23:25:21.484065 <6>[ 2.373252] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10715 23:25:21.490628 <6>[ 2.381590] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10716 23:25:21.501014 <6>[ 2.389927] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10717 23:25:21.507316 <6>[ 2.398704] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10718 23:25:21.514151 <6>[ 2.405934] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10719 23:25:21.520420 <6>[ 2.412797] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10720 23:25:21.527563 <6>[ 2.419632] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10721 23:25:21.533720 <6>[ 2.426631] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10722 23:25:21.543978 <6>[ 2.433513] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10723 23:25:21.553404 <6>[ 2.442645] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10724 23:25:21.563298 <6>[ 2.451768] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10725 23:25:21.569986 <6>[ 2.461060] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10726 23:25:21.579951 <6>[ 2.470528] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10727 23:25:21.589917 <6>[ 2.479995] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10728 23:25:21.599705 <6>[ 2.489115] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10729 23:25:21.610129 <6>[ 2.498580] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10730 23:25:21.616891 <6>[ 2.507706] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10731 23:25:21.629878 <6>[ 2.517001] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10732 23:25:21.639380 <6>[ 2.527161] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10733 23:25:21.649335 <6>[ 2.539227] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10734 23:25:21.656226 <6>[ 2.548894] Trying to probe devices needed for running init ...
10735 23:25:21.676867 <6>[ 2.567302] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10736 23:25:21.705300 <6>[ 2.599035] hub 2-1:1.0: USB hub found
10737 23:25:21.708156 <6>[ 2.603506] hub 2-1:1.0: 3 ports detected
10738 23:25:21.717289 <6>[ 2.610700] hub 2-1:1.0: USB hub found
10739 23:25:21.720387 <6>[ 2.615134] hub 2-1:1.0: 3 ports detected
10740 23:25:21.828732 <6>[ 2.719220] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10741 23:25:21.983088 <6>[ 2.876705] hub 1-1:1.0: USB hub found
10742 23:25:21.985960 <6>[ 2.881167] hub 1-1:1.0: 4 ports detected
10743 23:25:21.995675 <6>[ 2.889472] hub 1-1:1.0: USB hub found
10744 23:25:21.998725 <6>[ 2.893959] hub 1-1:1.0: 4 ports detected
10745 23:25:22.069026 <6>[ 2.959432] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10746 23:25:22.320678 <6>[ 3.211258] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10747 23:25:22.453373 <6>[ 3.347210] hub 1-1.4:1.0: USB hub found
10748 23:25:22.456654 <6>[ 3.351892] hub 1-1.4:1.0: 2 ports detected
10749 23:25:22.467341 <6>[ 3.360809] hub 1-1.4:1.0: USB hub found
10750 23:25:22.470064 <6>[ 3.365422] hub 1-1.4:1.0: 2 ports detected
10751 23:25:22.768183 <6>[ 3.659206] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10752 23:25:22.960273 <6>[ 3.851229] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10753 23:25:33.933443 <6>[ 14.832344] ALSA device list:
10754 23:25:33.939544 <6>[ 14.835638] No soundcards found.
10755 23:25:33.947715 <6>[ 14.843705] Freeing unused kernel memory: 8448K
10756 23:25:33.951294 <6>[ 14.849341] Run /init as init process
10757 23:25:33.961413 Loading, please wait...
10758 23:25:33.986165 Starting systemd-udevd version 252.22-1~deb12u1
10759 23:25:33.986532
10760 23:25:34.260597 <3>[ 15.153090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 23:25:34.267483 <3>[ 15.161644] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 23:25:34.279214 <3>[ 15.171097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10763 23:25:34.288697 <3>[ 15.179914] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 23:25:34.295545 <3>[ 15.188241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 23:25:34.302341 <6>[ 15.189396] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10766 23:25:34.312032 <3>[ 15.197015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 23:25:34.318755 <6>[ 15.204123] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10768 23:25:34.328995 <3>[ 15.212185] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10769 23:25:34.335682 <6>[ 15.220810] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10770 23:25:34.345944 <6>[ 15.223057] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10771 23:25:34.352202 <3>[ 15.228842] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 23:25:34.362703 <3>[ 15.235774] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10773 23:25:34.365218 <6>[ 15.235847] remoteproc remoteproc0: scp is available
10774 23:25:34.372013 <6>[ 15.235968] remoteproc remoteproc0: powering up scp
10775 23:25:34.378615 <6>[ 15.235974] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10776 23:25:34.385427 <6>[ 15.236002] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10777 23:25:34.392426 <4>[ 15.241572] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10778 23:25:34.401918 <3>[ 15.256859] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 23:25:34.408450 <4>[ 15.263841] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10780 23:25:34.415352 <3>[ 15.266417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 23:25:34.421535 <6>[ 15.271879] mc: Linux media interface: v0.10
10782 23:25:34.428382 <3>[ 15.279896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 23:25:34.438370 <3>[ 15.281993] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 23:25:34.445337 <6>[ 15.282162] usbcore: registered new device driver r8152-cfgselector
10785 23:25:34.451789 <6>[ 15.286045] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10786 23:25:34.458770 <3>[ 15.293051] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 23:25:34.465823 <6>[ 15.309590] videodev: Linux video capture interface: v2.00
10788 23:25:34.472605 <3>[ 15.316705] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 23:25:34.482294 <4>[ 15.329372] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10790 23:25:34.485574 <4>[ 15.329372] Fallback method does not support PEC.
10791 23:25:34.495833 <3>[ 15.337491] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 23:25:34.502660 <6>[ 15.357622] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10793 23:25:34.508894 <6>[ 15.357633] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10794 23:25:34.515202 <6>[ 15.357643] remoteproc remoteproc0: remote processor scp is now up
10795 23:25:34.525252 <3>[ 15.359588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 23:25:34.531846 <3>[ 15.359642] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 23:25:34.538901 <6>[ 15.360350] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10798 23:25:34.546527 <6>[ 15.360355] pci_bus 0000:00: root bus resource [bus 00-ff]
10799 23:25:34.552898 <6>[ 15.360359] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10800 23:25:34.562541 <6>[ 15.360361] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10801 23:25:34.569689 <6>[ 15.360387] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10802 23:25:34.576148 <6>[ 15.360400] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10803 23:25:34.579510 <6>[ 15.360464] pci 0000:00:00.0: supports D1 D2
10804 23:25:34.585862 <6>[ 15.360466] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10805 23:25:34.596212 <6>[ 15.361372] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10806 23:25:34.603141 <6>[ 15.361450] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10807 23:25:34.609321 <6>[ 15.361475] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10808 23:25:34.615920 <6>[ 15.361491] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10809 23:25:34.626324 <6>[ 15.361506] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10810 23:25:34.629805 <6>[ 15.361612] pci 0000:01:00.0: supports D1 D2
10811 23:25:34.635974 <6>[ 15.361613] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10812 23:25:34.646188 <3>[ 15.369877] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10813 23:25:34.652260 <6>[ 15.375263] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10814 23:25:34.662285 <6>[ 15.378044] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10815 23:25:34.672222 <6>[ 15.379421] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10816 23:25:34.678902 <6>[ 15.379930] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10817 23:25:34.689279 <6>[ 15.387687] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10818 23:25:34.695876 <6>[ 15.389125] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10819 23:25:34.706109 <6>[ 15.391051] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10820 23:25:34.712251 <6>[ 15.395296] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10821 23:25:34.715483 <6>[ 15.425862] Bluetooth: Core ver 2.22
10822 23:25:34.725430 <4>[ 15.426940] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10823 23:25:34.735221 <4>[ 15.426950] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10824 23:25:34.742244 <6>[ 15.433386] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10825 23:25:34.748494 <6>[ 15.440319] NET: Registered PF_BLUETOOTH protocol family
10826 23:25:34.755263 <6>[ 15.445999] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10827 23:25:34.762227 <6>[ 15.446548] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10828 23:25:34.775138 <6>[ 15.447626] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10829 23:25:34.781913 <6>[ 15.447711] usbcore: registered new interface driver uvcvideo
10830 23:25:34.789078 <6>[ 15.453112] Bluetooth: HCI device and connection manager initialized
10831 23:25:34.794808 <6>[ 15.463023] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10832 23:25:34.805366 <3>[ 15.469275] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10833 23:25:34.808894 <6>[ 15.469285] Bluetooth: HCI socket layer initialized
10834 23:25:34.815097 <6>[ 15.469288] Bluetooth: L2CAP socket layer initialized
10835 23:25:34.818508 <6>[ 15.469296] Bluetooth: SCO socket layer initialized
10836 23:25:34.828253 <6>[ 15.476749] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10837 23:25:34.832100 <6>[ 15.479019] r8152 2-1.3:1.0 eth0: v1.12.13
10838 23:25:34.838344 <6>[ 15.479085] usbcore: registered new interface driver r8152
10839 23:25:34.845001 <6>[ 15.489128] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10840 23:25:34.848491 <6>[ 15.496386] pci 0000:00:00.0: PCI bridge to [bus 01]
10841 23:25:34.855398 <6>[ 15.503132] usbcore: registered new interface driver cdc_ether
10842 23:25:34.864964 <6>[ 15.510106] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10843 23:25:34.871359 <6>[ 15.510309] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10844 23:25:34.875002 <6>[ 15.525379] usbcore: registered new interface driver r8153_ecm
10845 23:25:34.881792 <6>[ 15.525621] usbcore: registered new interface driver btusb
10846 23:25:34.891394 <4>[ 15.526627] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10847 23:25:34.897841 <3>[ 15.526638] Bluetooth: hci0: Failed to load firmware file (-2)
10848 23:25:34.904453 <3>[ 15.526642] Bluetooth: hci0: Failed to set up firmware (-2)
10849 23:25:34.914467 <4>[ 15.526647] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10850 23:25:34.921680 <6>[ 15.530137] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10851 23:25:34.928202 <6>[ 15.549141] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10852 23:25:34.930762 <6>[ 15.552771] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10853 23:25:34.977359 <5>[ 15.869219] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10854 23:25:35.003711 <5>[ 15.895789] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10855 23:25:35.010449 <5>[ 15.903225] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10856 23:25:35.020538 <4>[ 15.911767] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10857 23:25:35.023723 <6>[ 15.920698] cfg80211: failed to load regulatory.db
10858 23:25:35.087904 <6>[ 15.979911] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10859 23:25:35.094323 <6>[ 15.987457] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10860 23:25:35.118882 <6>[ 16.014409] mt7921e 0000:01:00.0: ASIC revision: 79610010
10861 23:25:35.225061 <6>[ 16.117124] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10862 23:25:35.228441 <6>[ 16.117124]
10863 23:25:35.252801 Begin: Loading essential drivers ... done.
10864 23:25:35.256031 Begin: Running /scripts/init-premount ... done.
10865 23:25:35.262951 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10866 23:25:35.272954 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10867 23:25:35.275763 Device /sys/class/net/enx002432307852 found
10868 23:25:35.276185 done.
10869 23:25:35.287430 Begin: Waiting up to 180 secs for any network device to become available ... done.
10870 23:25:35.338785 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10871 23:25:35.494150 <6>[ 16.385966] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10872 23:25:36.228033 <6>[ 17.123788] r8152 2-1.3:1.0 enx002432307852: carrier on
10873 23:25:36.347383 <6>[ 17.243224] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10874 23:25:46.327383 IP-Config: no response after 2 secs - giving up
10875 23:25:46.362659 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:3d mtu 1500 DHCP
10876 23:25:47.057931 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10877 23:25:47.060694 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10878 23:25:47.067541 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10879 23:25:47.074271 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10880 23:25:47.081259 host : mt8192-asurada-spherion-r0-cbg-3
10881 23:25:47.087566 domain : lava-rack
10882 23:25:47.090672 rootserver: 192.168.201.1 rootpath:
10883 23:25:47.093897 filename :
10884 23:25:47.233612 done.
10885 23:25:47.242956 Begin: Running /scripts/nfs-bottom ... done.
10886 23:25:47.255495 Begin: Running /scripts/init-bottom ... done.
10887 23:25:48.651777 <6>[ 29.548573] NET: Registered PF_INET6 protocol family
10888 23:25:48.659187 <6>[ 29.556343] Segment Routing with IPv6
10889 23:25:48.662366 <6>[ 29.560298] In-situ OAM (IOAM) with IPv6
10890 23:25:48.851799 <30>[ 29.722211] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10891 23:25:48.858567 <30>[ 29.755843] systemd[1]: Detected architecture arm64.
10892 23:25:48.869800
10893 23:25:48.872800 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10894 23:25:48.873219
10895 23:25:48.873548
10896 23:25:48.900890 <30>[ 29.797947] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10897 23:25:50.161729 <30>[ 31.055655] systemd[1]: Queued start job for default target graphical.target.
10898 23:25:50.198835 <30>[ 31.092781] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10899 23:25:50.205683 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10900 23:25:50.206164
10901 23:25:50.227519 <30>[ 31.121277] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10902 23:25:50.237433 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10903 23:25:50.237983
10904 23:25:50.255290 <30>[ 31.149243] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10905 23:25:50.265329 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10906 23:25:50.265866
10907 23:25:50.284118 <30>[ 31.177533] systemd[1]: Created slice user.slice - User and Session Slice.
10908 23:25:50.290590 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10909 23:25:50.291136
10910 23:25:50.313726 <30>[ 31.204158] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10911 23:25:50.320625 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10912 23:25:50.321164
10913 23:25:50.345379 <30>[ 31.236147] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10914 23:25:50.352403 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10915 23:25:50.352939
10916 23:25:50.380077 <30>[ 31.263452] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10917 23:25:50.389390 <30>[ 31.283296] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10918 23:25:50.396183 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10919 23:25:50.396640
10920 23:25:50.413709 <30>[ 31.307684] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10921 23:25:50.420158 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10922 23:25:50.423945
10923 23:25:50.441158 <30>[ 31.335440] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10924 23:25:50.451540 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10925 23:25:50.451969
10926 23:25:50.466204 <30>[ 31.363820] systemd[1]: Reached target paths.target - Path Units.
10927 23:25:50.473372 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10928 23:25:50.476619
10929 23:25:50.493488 <30>[ 31.387731] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10930 23:25:50.500109 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10931 23:25:50.500832
10932 23:25:50.513989 <30>[ 31.411228] systemd[1]: Reached target slices.target - Slice Units.
10933 23:25:50.523809 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10934 23:25:50.524363
10935 23:25:50.538608 <30>[ 31.435762] systemd[1]: Reached target swap.target - Swaps.
10936 23:25:50.545503 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10937 23:25:50.546031
10938 23:25:50.565834 <30>[ 31.459778] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10939 23:25:50.575660 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10940 23:25:50.576167
10941 23:25:50.594766 <30>[ 31.488255] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10942 23:25:50.604573 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10943 23:25:50.605120
10944 23:25:50.625401 <30>[ 31.519228] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10945 23:25:50.634943 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10946 23:25:50.635368
10947 23:25:50.655191 <30>[ 31.549087] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10948 23:25:50.665299 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10949 23:25:50.665864
10950 23:25:50.682387 <30>[ 31.575980] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10951 23:25:50.688498 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10952 23:25:50.689166
10953 23:25:50.707060 <30>[ 31.601290] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10954 23:25:50.717736 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10955 23:25:50.718271
10956 23:25:50.737387 <30>[ 31.631144] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10957 23:25:50.746792 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10958 23:25:50.747346
10959 23:25:50.761735 <30>[ 31.655796] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10960 23:25:50.771892 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10961 23:25:50.772397
10962 23:25:50.821732 <30>[ 31.715700] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10963 23:25:50.828400 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10964 23:25:50.828971
10965 23:25:50.848022 <30>[ 31.741845] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10966 23:25:50.854263 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10967 23:25:50.854883
10968 23:25:50.876820 <30>[ 31.771117] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10969 23:25:50.883236 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10970 23:25:50.883320
10971 23:25:50.907999 <30>[ 31.795452] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10972 23:25:50.921769 <30>[ 31.815203] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10973 23:25:50.930637 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10974 23:25:50.930812
10975 23:25:50.954800 <30>[ 31.848223] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10976 23:25:50.960899 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10977 23:25:50.961319
10978 23:25:50.987336 <30>[ 31.881070] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10979 23:25:50.993583 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10980 23:25:50.994008
10981 23:25:51.020603 <30>[ 31.913852] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10982 23:25:51.026377 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10983 23:25:51.026836
10984 23:25:51.036469 <6>[ 31.930726] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10985 23:25:51.052320 <30>[ 31.946499] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10986 23:25:51.062521 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10987 23:25:51.062947
10988 23:25:51.110277 <30>[ 32.004084] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10989 23:25:51.117355 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10990 23:25:51.117781
10991 23:25:51.143682 <30>[ 32.037878] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10992 23:25:51.150829 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10993 23:25:51.151256
10994 23:25:51.154004 <6>[ 32.053363] fuse: init (API version 7.37)
10995 23:25:51.180181 <30>[ 32.073744] systemd[1]: Starting systemd-journald.service - Journal Service...
10996 23:25:51.186573 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10997 23:25:51.187098
10998 23:25:51.223136 <30>[ 32.117005] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10999 23:25:51.229744 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
11000 23:25:51.230199
11001 23:25:51.255632 <30>[ 32.146207] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
11002 23:25:51.262210 Starting [0;1;39msystemd-network-g… units from Kernel command line...
11003 23:25:51.262672
11004 23:25:51.285989 <30>[ 32.180170] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
11005 23:25:51.296188 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
11006 23:25:51.296628
11007 23:25:51.319714 <30>[ 32.213627] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
11008 23:25:51.326123 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
11009 23:25:51.326582
11010 23:25:51.349608 <3>[ 32.243335] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 23:25:51.355843 <30>[ 32.246264] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
11012 23:25:51.365671 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
11013 23:25:51.366094
11014 23:25:51.382274 <30>[ 32.275709] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
11015 23:25:51.388547 <3>[ 32.279292] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11016 23:25:51.398552 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
11017 23:25:51.398994
11018 23:25:51.417785 <30>[ 32.311479] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
11019 23:25:51.428455 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-<3>[ 32.322313] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11020 23:25:51.435204 debug.m…nt[0m - Kernel Debug File System.
11021 23:25:51.435624
11022 23:25:51.454519 <30>[ 32.347840] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
11023 23:25:51.464688 <3>[ 32.352019] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 23:25:51.471250 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11025 23:25:51.471674
11026 23:25:51.490760 <30>[ 32.384013] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11027 23:25:51.497078 <3>[ 32.386645] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11028 23:25:51.507391 <30>[ 32.392013] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11029 23:25:51.514113 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11030 23:25:51.514569
11031 23:25:51.526336 <3>[ 32.420327] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11032 23:25:51.537069 <30>[ 32.430735] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11033 23:25:51.543414 <30>[ 32.439467] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11034 23:25:51.560989 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m <3>[ 32.452938] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11035 23:25:51.561424 - Load Kernel Module dm_mod.
11036 23:25:51.561762
11037 23:25:51.579302 <30>[ 32.476219] systemd[1]: modprobe@drm.service: Deactivated successfully.
11038 23:25:51.590285 <30>[ 32.483950] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11039 23:25:51.596949 <3>[ 32.485516] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11040 23:25:51.606903 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11041 23:25:51.607328
11042 23:25:51.627513 <30>[ 32.521213] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11043 23:25:51.634141 <3>[ 32.523076] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11044 23:25:51.644298 <30>[ 32.529608] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11045 23:25:51.654740 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11046 23:25:51.655298
11047 23:25:51.667862 <3>[ 32.561681] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11048 23:25:51.679291 <30>[ 32.572657] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11049 23:25:51.685964 <30>[ 32.580641] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11050 23:25:51.695518 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11051 23:25:51.696036
11052 23:25:51.714497 <30>[ 32.608248] systemd[1]: modprobe@loop.service: Deactivated successfully.
11053 23:25:51.721118 <30>[ 32.616137] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11054 23:25:51.730981 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11055 23:25:51.731422
11056 23:25:51.750144 <30>[ 32.644167] systemd[1]: Started systemd-journald.service - Journal Service.
11057 23:25:51.757701 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11058 23:25:51.758137
11059 23:25:51.770874 <4>[ 32.658872] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11060 23:25:51.781425 <3>[ 32.674926] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11061 23:25:51.787647 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11062 23:25:51.788193
11063 23:25:51.807840 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11064 23:25:51.808363
11065 23:25:51.831348 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11066 23:25:51.831872
11067 23:25:51.850881 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11068 23:25:51.851402
11069 23:25:51.872848 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11070 23:25:51.873389
11071 23:25:51.913998 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11072 23:25:51.914553
11073 23:25:51.934157 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11074 23:25:51.934642
11075 23:25:51.962466 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11076 23:25:51.962915
11077 23:25:51.990809 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11078 23:25:51.991276
11079 23:25:52.034702 <46>[ 32.929049] systemd-journald[314]: Received client request to flush runtime journal.
11080 23:25:52.054457 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11081 23:25:52.054906
11082 23:25:52.080547 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11083 23:25:52.080991
11084 23:25:52.369701 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11085 23:25:52.369846
11086 23:25:52.390124 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11087 23:25:52.390211
11088 23:25:52.410194 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11089 23:25:52.410283
11090 23:25:53.189526 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11091 23:25:53.189746
11092 23:25:53.492408 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11093 23:25:53.492916
11094 23:25:53.514568 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11095 23:25:53.515234
11096 23:25:53.577848 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11097 23:25:53.578367
11098 23:25:53.695841 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11099 23:25:53.696362
11100 23:25:53.713830 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11101 23:25:53.714447
11102 23:25:53.733324 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11103 23:25:53.733752
11104 23:25:53.777868 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11105 23:25:53.778387
11106 23:25:53.804796 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11107 23:25:53.805224
11108 23:25:54.101775 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11109 23:25:54.102440
11110 23:25:54.152082 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11111 23:25:54.152538
11112 23:25:54.201216 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11113 23:25:54.201649
11114 23:25:54.561276 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11115 23:25:54.561786
11116 23:25:54.606382 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11117 23:25:54.606864
11118 23:25:54.672813 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11119 23:25:54.672919
11120 23:25:54.706205 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11121 23:25:54.706317
11122 23:25:54.745901 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11123 23:25:54.745991
11124 23:25:54.801501 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11125 23:25:54.801781
11126 23:25:54.822325 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11127 23:25:54.822815
11128 23:25:54.847454 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11129 23:25:54.847896
11130 23:25:54.871003 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11131 23:25:54.871431
11132 23:25:54.919133 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11133 23:25:54.919723
11134 23:25:54.979143 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11135 23:25:54.979849
11136 23:25:55.008763 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11137 23:25:55.009198
11138 23:25:55.039385 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11139 23:25:55.039822
11140 23:25:55.061915 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11141 23:25:55.062347
11142 23:25:55.085780 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11143 23:25:55.086206
11144 23:25:55.105270 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11145 23:25:55.105703
11146 23:25:55.120825 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11147 23:25:55.121250
11148 23:25:55.146923 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11149 23:25:55.147361
11150 23:25:55.168343 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11151 23:25:55.168775
11152 23:25:55.185297 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11153 23:25:55.185839
11154 23:25:55.204671 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11155 23:25:55.205255
11156 23:25:55.224935 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11157 23:25:55.225499
11158 23:25:55.240558 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11159 23:25:55.241087
11160 23:25:55.259566 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11161 23:25:55.260013
11162 23:25:55.276780 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11163 23:25:55.277368
11164 23:25:55.293736 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11165 23:25:55.294316
11166 23:25:55.345304 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11167 23:25:55.345926
11168 23:25:55.397787 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11169 23:25:55.398236
11170 23:25:55.495565 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11171 23:25:55.495716
11172 23:25:55.520157 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11173 23:25:55.520245
11174 23:25:55.707573 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11175 23:25:55.707709
11176 23:25:55.745773 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11177 23:25:55.745871
11178 23:25:55.787870 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11179 23:25:55.787980
11180 23:25:55.807044 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11181 23:25:55.807203
11182 23:25:55.823564 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11183 23:25:55.823907
11184 23:25:55.859968 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11185 23:25:55.860533
11186 23:25:55.883799 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11187 23:25:55.884360
11188 23:25:55.933457 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11189 23:25:55.934032
11190 23:25:55.952090 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11191 23:25:55.952647
11192 23:25:56.003171 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11193 23:25:56.003686
11194 23:25:56.026654 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11195 23:25:56.027099
11196 23:25:56.094840 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11197 23:25:56.095354
11198 23:25:56.156805 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11199 23:25:56.157324
11200 23:25:56.237086
11201 23:25:56.237607
11202 23:25:56.240138 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11203 23:25:56.240570
11204 23:25:56.243633 debian-bookworm-arm64 login: root (automatic login)
11205 23:25:56.244073
11206 23:25:56.244406
11207 23:25:56.599653 Linux debian-bookworm-arm64 6.1.83-cip18 #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024 aarch64
11208 23:25:56.600191
11209 23:25:56.606056 The programs included with the Debian GNU/Linux system are free software;
11210 23:25:56.613087 the exact distribution terms for each program are described in the
11211 23:25:56.616474 individual files in /usr/share/doc/*/copyright.
11212 23:25:56.616993
11213 23:25:56.623289 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11214 23:25:56.626249 permitted by applicable law.
11215 23:25:57.814622 Matched prompt #10: / #
11217 23:25:57.814906 Setting prompt string to ['/ #']
11218 23:25:57.815000 end: 2.2.5.1 login-action (duration 00:00:39) [common]
11220 23:25:57.815198 end: 2.2.5 auto-login-action (duration 00:00:40) [common]
11221 23:25:57.815286 start: 2.2.6 expect-shell-connection (timeout 00:02:58) [common]
11222 23:25:57.815359 Setting prompt string to ['/ #']
11223 23:25:57.815420 Forcing a shell prompt, looking for ['/ #']
11225 23:25:57.865646 / #
11226 23:25:57.865761 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11227 23:25:57.865846 Waiting using forced prompt support (timeout 00:02:30)
11228 23:25:57.870592
11229 23:25:57.870868 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11230 23:25:57.870978 start: 2.2.7 export-device-env (timeout 00:02:58) [common]
11232 23:25:57.971376 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248467/extract-nfsrootfs-gyhcfl92'
11233 23:25:57.976692 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248467/extract-nfsrootfs-gyhcfl92'
11235 23:25:58.077460 / # export NFS_SERVER_IP='192.168.201.1'
11236 23:25:58.084619 export NFS_SERVER_IP='192.168.201.1'
11237 23:25:58.085585 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11238 23:25:58.086185 end: 2.2 depthcharge-retry (duration 00:02:02) [common]
11239 23:25:58.086863 end: 2 depthcharge-action (duration 00:02:02) [common]
11240 23:25:58.087478 start: 3 lava-test-retry (timeout 00:07:15) [common]
11241 23:25:58.088067 start: 3.1 lava-test-shell (timeout 00:07:15) [common]
11242 23:25:58.088554 Using namespace: common
11244 23:25:58.189807 / # #
11245 23:25:58.190002 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11246 23:25:58.195641 #
11247 23:25:58.196544 Using /lava-13248467
11249 23:25:58.297881 / # export SHELL=/bin/bash
11250 23:25:58.304436 export SHELL=/bin/bash
11252 23:25:58.406062 / # . /lava-13248467/environment
11253 23:25:58.412593 . /lava-13248467/environment
11255 23:25:58.521590 / # /lava-13248467/bin/lava-test-runner /lava-13248467/0
11256 23:25:58.522175 Test shell timeout: 10s (minimum of the action and connection timeout)
11257 23:25:58.527508 /lava-13248467/bin/lava-test-runner /lava-13248467/0
11258 23:25:58.847591 + export TESTRUN_ID=0_timesync-off
11259 23:25:58.851184 + TESTRUN_ID=0_timesync-off
11260 23:25:58.853967 + cd /lava-13248467/0/tests/0_timesync-off
11261 23:25:58.857664 ++ cat uuid
11262 23:25:58.865345 + UUID=13248467_1.6.2.3.1
11263 23:25:58.865789 + set +x
11264 23:25:58.872076 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13248467_1.6.2.3.1>
11265 23:25:58.872803 Received signal: <STARTRUN> 0_timesync-off 13248467_1.6.2.3.1
11266 23:25:58.873219 Starting test lava.0_timesync-off (13248467_1.6.2.3.1)
11267 23:25:58.873769 Skipping test definition patterns.
11268 23:25:58.875372 + systemctl stop systemd-timesyncd
11269 23:25:58.945679 + set +x
11270 23:25:58.949534 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13248467_1.6.2.3.1>
11271 23:25:58.950252 Received signal: <ENDRUN> 0_timesync-off 13248467_1.6.2.3.1
11272 23:25:58.950739 Ending use of test pattern.
11273 23:25:58.951090 Ending test lava.0_timesync-off (13248467_1.6.2.3.1), duration 0.08
11275 23:25:59.055261 + export TESTRUN_ID=1_kselftest-tpm2
11276 23:25:59.058636 + TESTRUN_ID=1_kselftest-tpm2
11277 23:25:59.065750 + cd /lava-13248467/0/tests/1_kselftest-tpm2
11278 23:25:59.066197 ++ cat uuid
11279 23:25:59.074706 + UUID=13248467_1.6.2.3.5
11280 23:25:59.075124 + set +x
11281 23:25:59.080976 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 13248467_1.6.2.3.5>
11282 23:25:59.081652 Received signal: <STARTRUN> 1_kselftest-tpm2 13248467_1.6.2.3.5
11283 23:25:59.082075 Starting test lava.1_kselftest-tpm2 (13248467_1.6.2.3.5)
11284 23:25:59.082513 Skipping test definition patterns.
11285 23:25:59.084336 + cd ./automated/linux/kselftest/
11286 23:25:59.107404 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11287 23:25:59.171019 INFO: install_deps skipped
11288 23:25:59.706323 --2024-04-03 23:25:59-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11289 23:25:59.713141 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11290 23:25:59.842285 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11291 23:25:59.971408 HTTP request sent, awaiting response... 200 OK
11292 23:25:59.974306 Length: 1651420 (1.6M) [application/octet-stream]
11293 23:25:59.977506 Saving to: 'kselftest_armhf.tar.gz'
11294 23:25:59.977987
11295 23:25:59.978517
11296 23:26:00.228250 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11297 23:26:00.486719 kselftest_armhf.tar 2%[ ] 47.81K 182KB/s
11298 23:26:00.791108 kselftest_armhf.tar 13%[=> ] 219.84K 418KB/s
11299 23:26:00.921246 kselftest_armhf.tar 50%[=========> ] 808.57K 966KB/s
11300 23:26:00.928215 kselftest_armhf.tar 100%[===================>] 1.57M 1.62MB/s in 1.0s
11301 23:26:00.928301
11302 23:26:01.073381 2024-04-03 23:26:00 (1.62 MB/s) - 'kselftest_armhf.tar.gz' saved [1651420/1651420]
11303 23:26:01.073531
11304 23:26:05.042763 <6>[ 45.944488] vpu: disabling
11305 23:26:05.045529 <6>[ 45.947563] vproc2: disabling
11306 23:26:05.048120 <6>[ 45.951126] vproc1: disabling
11307 23:26:05.052889 <6>[ 45.955707] vaud18: disabling
11308 23:26:05.059830 <6>[ 45.959228] vsram_others: disabling
11309 23:26:05.063444 <6>[ 45.963139] va09: disabling
11310 23:26:05.066330 <6>[ 45.966266] vsram_md: disabling
11311 23:26:05.071029 <6>[ 45.969787] Vgpu: disabling
11312 23:26:06.429002 skiplist:
11313 23:26:06.432346 ========================================
11314 23:26:06.436023 ========================================
11315 23:26:06.492171 tpm2:test_smoke.sh
11316 23:26:06.495319 tpm2:test_space.sh
11317 23:26:06.515229 ============== Tests to run ===============
11318 23:26:06.518757 tpm2:test_smoke.sh
11319 23:26:06.519284 tpm2:test_space.sh
11320 23:26:06.521750 ===========End Tests to run ===============
11321 23:26:06.526973 shardfile-tpm2 pass
11322 23:26:06.662467 <12>[ 47.561490] kselftest: Running tests in tpm2
11323 23:26:06.673828 TAP version 13
11324 23:26:06.691411 1..2
11325 23:26:06.731033 # selftests: tpm2: test_smoke.sh
11326 23:26:08.649672 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11327 23:26:08.655976 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11328 23:26:08.662848 # Exception ignored in: <function Client.__del__ at 0xffff8668ccc0>
11329 23:26:08.665880 # Traceback (most recent call last):
11330 23:26:08.676168 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11331 23:26:08.676275 # if self.tpm:
11332 23:26:08.679333 # ^^^^^^^^
11333 23:26:08.683465 # AttributeError: 'Client' object has no attribute 'tpm'
11334 23:26:08.689240 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11335 23:26:08.695937 # Exception ignored in: <function Client.__del__ at 0xffff8668ccc0>
11336 23:26:08.699511 # Traceback (most recent call last):
11337 23:26:08.709458 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11338 23:26:08.709555 # if self.tpm:
11339 23:26:08.712978 # ^^^^^^^^
11340 23:26:08.715910 # AttributeError: 'Client' object has no attribute 'tpm'
11341 23:26:08.722541 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11342 23:26:08.729559 # Exception ignored in: <function Client.__del__ at 0xffff8668ccc0>
11343 23:26:08.732636 # Traceback (most recent call last):
11344 23:26:08.742698 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11345 23:26:08.746340 # if self.tpm:
11346 23:26:08.746459 # ^^^^^^^^
11347 23:26:08.752683 # AttributeError: 'Client' object has no attribute 'tpm'
11348 23:26:08.759596 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11349 23:26:08.766714 # Exception ignored in: <function Client.__del__ at 0xffff8668ccc0>
11350 23:26:08.770212 # Traceback (most recent call last):
11351 23:26:08.779991 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11352 23:26:08.780075 # if self.tpm:
11353 23:26:08.782975 # ^^^^^^^^
11354 23:26:08.786301 # AttributeError: 'Client' object has no attribute 'tpm'
11355 23:26:08.793110 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11356 23:26:08.799428 # Exception ignored in: <function Client.__del__ at 0xffff8668ccc0>
11357 23:26:08.803215 # Traceback (most recent call last):
11358 23:26:08.812846 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11359 23:26:08.812951 # if self.tpm:
11360 23:26:08.816249 # ^^^^^^^^
11361 23:26:08.820028 # AttributeError: 'Client' object has no attribute 'tpm'
11362 23:26:08.826434 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11363 23:26:08.833283 # Exception ignored in: <function Client.__del__ at 0xffff8668ccc0>
11364 23:26:08.836742 # Traceback (most recent call last):
11365 23:26:08.846531 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11366 23:26:08.849974 # if self.tpm:
11367 23:26:08.850096 # ^^^^^^^^
11368 23:26:08.856890 # AttributeError: 'Client' object has no attribute 'tpm'
11369 23:26:08.863469 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11370 23:26:08.870160 # Exception ignored in: <function Client.__del__ at 0xffff8668ccc0>
11371 23:26:08.873139 # Traceback (most recent call last):
11372 23:26:08.883992 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11373 23:26:08.884382 # if self.tpm:
11374 23:26:08.887347 # ^^^^^^^^
11375 23:26:08.890575 # AttributeError: 'Client' object has no attribute 'tpm'
11376 23:26:08.900699 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11377 23:26:08.907078 # Exception ignored in: <function Client.__del__ at 0xffff8668ccc0>
11378 23:26:08.910478 # Traceback (most recent call last):
11379 23:26:08.916918 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11380 23:26:08.920405 # if self.tpm:
11381 23:26:08.920821 # ^^^^^^^^
11382 23:26:08.927383 # AttributeError: 'Client' object has no attribute 'tpm'
11383 23:26:08.927838 #
11384 23:26:08.934126 # ======================================================================
11385 23:26:08.940687 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11386 23:26:08.947148 # ----------------------------------------------------------------------
11387 23:26:08.950275 # Traceback (most recent call last):
11388 23:26:08.960586 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11389 23:26:08.966790 # self.root_key = self.client.create_root_key()
11390 23:26:08.970704 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11391 23:26:08.980362 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11392 23:26:08.987860 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11393 23:26:08.992889 # ^^^^^^^^^^^^^^^^^^
11394 23:26:08.999615 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11395 23:26:09.003367 # raise ProtocolError(cc, rc)
11396 23:26:09.009405 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11397 23:26:09.009827 #
11398 23:26:09.016638 # ======================================================================
11399 23:26:09.023145 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11400 23:26:09.030603 # ----------------------------------------------------------------------
11401 23:26:09.032825 # Traceback (most recent call last):
11402 23:26:09.043028 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11403 23:26:09.046506 # self.client = tpm2.Client()
11404 23:26:09.049770 # ^^^^^^^^^^^^^
11405 23:26:09.059650 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11406 23:26:09.066059 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11407 23:26:09.069724 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11408 23:26:09.076876 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11409 23:26:09.077492 #
11410 23:26:09.083542 # ======================================================================
11411 23:26:09.086357 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11412 23:26:09.093272 # ----------------------------------------------------------------------
11413 23:26:09.096432 # Traceback (most recent call last):
11414 23:26:09.105942 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11415 23:26:09.109300 # self.client = tpm2.Client()
11416 23:26:09.112760 # ^^^^^^^^^^^^^
11417 23:26:09.123051 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11418 23:26:09.129473 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11419 23:26:09.133206 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11420 23:26:09.139586 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11421 23:26:09.140024 #
11422 23:26:09.145867 # ======================================================================
11423 23:26:09.153057 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11424 23:26:09.159996 # ----------------------------------------------------------------------
11425 23:26:09.162572 # Traceback (most recent call last):
11426 23:26:09.173373 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11427 23:26:09.176232 # self.client = tpm2.Client()
11428 23:26:09.176669 # ^^^^^^^^^^^^^
11429 23:26:09.186313 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11430 23:26:09.192613 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11431 23:26:09.196300 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11432 23:26:09.202713 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11433 23:26:09.203231 #
11434 23:26:09.209979 # ======================================================================
11435 23:26:09.216466 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11436 23:26:09.222990 # ----------------------------------------------------------------------
11437 23:26:09.226393 # Traceback (most recent call last):
11438 23:26:09.236430 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11439 23:26:09.239618 # self.client = tpm2.Client()
11440 23:26:09.243089 # ^^^^^^^^^^^^^
11441 23:26:09.253340 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11442 23:26:09.259429 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11443 23:26:09.263074 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11444 23:26:09.270175 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11445 23:26:09.270727 #
11446 23:26:09.277005 # ======================================================================
11447 23:26:09.279557 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11448 23:26:09.286383 # ----------------------------------------------------------------------
11449 23:26:09.289810 # Traceback (most recent call last):
11450 23:26:09.299655 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11451 23:26:09.303196 # self.client = tpm2.Client()
11452 23:26:09.306639 # ^^^^^^^^^^^^^
11453 23:26:09.316390 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11454 23:26:09.323023 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11455 23:26:09.326239 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11456 23:26:09.333004 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11457 23:26:09.333442 #
11458 23:26:09.340217 # ======================================================================
11459 23:26:09.343079 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11460 23:26:09.350514 # ----------------------------------------------------------------------
11461 23:26:09.353158 # Traceback (most recent call last):
11462 23:26:09.363436 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11463 23:26:09.367128 # self.client = tpm2.Client()
11464 23:26:09.370566 # ^^^^^^^^^^^^^
11465 23:26:09.381410 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11466 23:26:09.385351 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11467 23:26:09.392193 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11468 23:26:09.395609 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11469 23:26:09.396049 #
11470 23:26:09.405205 # ======================================================================
11471 23:26:09.409243 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11472 23:26:09.416161 # ----------------------------------------------------------------------
11473 23:26:09.420624 # Traceback (most recent call last):
11474 23:26:09.431544 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11475 23:26:09.432054 # self.client = tpm2.Client()
11476 23:26:09.437526 # ^^^^^^^^^^^^^
11477 23:26:09.447738 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11478 23:26:09.450753 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11479 23:26:09.453959 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11480 23:26:09.461240 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11481 23:26:09.461759 #
11482 23:26:09.467622 # ======================================================================
11483 23:26:09.474808 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11484 23:26:09.480803 # ----------------------------------------------------------------------
11485 23:26:09.484604 # Traceback (most recent call last):
11486 23:26:09.494388 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11487 23:26:09.497798 # self.client = tpm2.Client()
11488 23:26:09.501196 # ^^^^^^^^^^^^^
11489 23:26:09.510975 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11490 23:26:09.517883 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11491 23:26:09.520878 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11492 23:26:09.527518 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11493 23:26:09.527941 #
11494 23:26:09.534191 # ----------------------------------------------------------------------
11495 23:26:09.534640 # Ran 9 tests in 0.052s
11496 23:26:09.535010 #
11497 23:26:09.537699 # FAILED (errors=9)
11498 23:26:09.541066 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11499 23:26:09.548524 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11500 23:26:09.551980 #
11501 23:26:09.554889 # ----------------------------------------------------------------------
11502 23:26:09.558314 # Ran 2 tests in 0.027s
11503 23:26:09.558885 #
11504 23:26:09.559339 # OK
11505 23:26:09.561316 ok 1 selftests: tpm2: test_smoke.sh
11506 23:26:09.564627 # selftests: tpm2: test_space.sh
11507 23:26:09.571532 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11508 23:26:09.578480 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11509 23:26:09.585423 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11510 23:26:09.591433 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11511 23:26:09.591872 #
11512 23:26:09.598482 # ======================================================================
11513 23:26:09.604920 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11514 23:26:09.611669 # ----------------------------------------------------------------------
11515 23:26:09.612134 # Traceback (most recent call last):
11516 23:26:09.625521 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11517 23:26:09.628795 # root1 = space1.create_root_key()
11518 23:26:09.631597 # ^^^^^^^^^^^^^^^^^^^^^^^^
11519 23:26:09.641596 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11520 23:26:09.648491 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11521 23:26:09.651590 # ^^^^^^^^^^^^^^^^^^
11522 23:26:09.661838 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11523 23:26:09.665534 # raise ProtocolError(cc, rc)
11524 23:26:09.671610 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11525 23:26:09.672083 #
11526 23:26:09.678967 # ======================================================================
11527 23:26:09.685016 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11528 23:26:09.689476 # ----------------------------------------------------------------------
11529 23:26:09.691971 # Traceback (most recent call last):
11530 23:26:09.705708 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11531 23:26:09.708996 # space1.create_root_key()
11532 23:26:09.719530 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11533 23:26:09.722044 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11534 23:26:09.729040 # ^^^^^^^^^^^^^^^^^^
11535 23:26:09.739014 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11536 23:26:09.741860 # raise ProtocolError(cc, rc)
11537 23:26:09.745671 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11538 23:26:09.748586 #
11539 23:26:09.755102 # ======================================================================
11540 23:26:09.759438 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11541 23:26:09.765407 # ----------------------------------------------------------------------
11542 23:26:09.768806 # Traceback (most recent call last):
11543 23:26:09.778727 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11544 23:26:09.781918 # root1 = space1.create_root_key()
11545 23:26:09.788679 # ^^^^^^^^^^^^^^^^^^^^^^^^
11546 23:26:09.798901 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11547 23:26:09.801786 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11548 23:26:09.808684 # ^^^^^^^^^^^^^^^^^^
11549 23:26:09.818320 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11550 23:26:09.821567 # raise ProtocolError(cc, rc)
11551 23:26:09.825456 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11552 23:26:09.829061 #
11553 23:26:09.831636 # ======================================================================
11554 23:26:09.838584 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11555 23:26:09.845222 # ----------------------------------------------------------------------
11556 23:26:09.848785 # Traceback (most recent call last):
11557 23:26:09.861787 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11558 23:26:09.865180 # root1 = space1.create_root_key()
11559 23:26:09.868804 # ^^^^^^^^^^^^^^^^^^^^^^^^
11560 23:26:09.879351 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11561 23:26:09.885654 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11562 23:26:09.888480 # ^^^^^^^^^^^^^^^^^^
11563 23:26:09.898775 # File "/lava-13248467/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11564 23:26:09.902589 # raise ProtocolError(cc, rc)
11565 23:26:09.908509 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11566 23:26:09.908944 #
11567 23:26:09.915784 # ----------------------------------------------------------------------
11568 23:26:09.916222 # Ran 4 tests in 0.079s
11569 23:26:09.916664 #
11570 23:26:09.918934 # FAILED (errors=4)
11571 23:26:09.923013 not ok 2 selftests: tpm2: test_space.sh # exit=1
11572 23:26:10.418217 tpm2_test_smoke_sh pass
11573 23:26:10.421697 tpm2_test_space_sh fail
11574 23:26:10.492590 + ../../utils/send-to-lava.sh ./output/result.txt
11575 23:26:10.598757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11576 23:26:10.599711 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11578 23:26:10.674717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11579 23:26:10.675479 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11581 23:26:10.743536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11582 23:26:10.744222 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11584 23:26:10.746806 + set +x
11585 23:26:10.749966 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 13248467_1.6.2.3.5>
11586 23:26:10.750681 Received signal: <ENDRUN> 1_kselftest-tpm2 13248467_1.6.2.3.5
11587 23:26:10.751050 Ending use of test pattern.
11588 23:26:10.751364 Ending test lava.1_kselftest-tpm2 (13248467_1.6.2.3.5), duration 11.67
11590 23:26:10.753032 <LAVA_TEST_RUNNER EXIT>
11591 23:26:10.753702 ok: lava_test_shell seems to have completed
11592 23:26:10.754269 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11593 23:26:10.754740 end: 3.1 lava-test-shell (duration 00:00:13) [common]
11594 23:26:10.755165 end: 3 lava-test-retry (duration 00:00:13) [common]
11595 23:26:10.755591 start: 4 finalize (timeout 00:07:03) [common]
11596 23:26:10.756036 start: 4.1 power-off (timeout 00:00:30) [common]
11597 23:26:10.756762 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11598 23:26:10.882507 >> Command sent successfully.
11599 23:26:10.893370 Returned 0 in 0 seconds
11600 23:26:10.994667 end: 4.1 power-off (duration 00:00:00) [common]
11602 23:26:10.995999 start: 4.2 read-feedback (timeout 00:07:02) [common]
11603 23:26:10.997176 Listened to connection for namespace 'common' for up to 1s
11604 23:26:11.997324 Finalising connection for namespace 'common'
11605 23:26:11.998057 Disconnecting from shell: Finalise
11606 23:26:11.998565 / #
11607 23:26:12.099581 end: 4.2 read-feedback (duration 00:00:01) [common]
11608 23:26:12.100291 end: 4 finalize (duration 00:00:01) [common]
11609 23:26:12.100925 Cleaning after the job
11610 23:26:12.101436 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/ramdisk
11611 23:26:12.114881 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/kernel
11612 23:26:12.149380 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/dtb
11613 23:26:12.149652 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/nfsrootfs
11614 23:26:12.233362 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248467/tftp-deploy-q9kurlc5/modules
11615 23:26:12.240654 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248467
11616 23:26:12.876585 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248467
11617 23:26:12.876770 Job finished correctly