Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
1 23:18:49.563455 lava-dispatcher, installed at version: 2024.01
2 23:18:49.563708 start: 0 validate
3 23:18:49.563879 Start time: 2024-04-03 23:18:49.563858+00:00 (UTC)
4 23:18:49.564012 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:18:49.564182 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:18:49.831880 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:18:49.832061 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:18:50.088969 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:18:50.089136 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:19:08.930876 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:19:08.931042 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:19:09.434282 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:19:09.434447 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:19:09.692369 validate duration: 20.13
16 23:19:09.692634 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:19:09.692765 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:19:09.692853 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:19:09.692971 Not decompressing ramdisk as can be used compressed.
20 23:19:09.693053 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 23:19:09.693117 saving as /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/ramdisk/initrd.cpio.gz
22 23:19:09.693180 total size: 5628151 (5 MB)
23 23:19:13.010485 progress 0 % (0 MB)
24 23:19:13.012185 progress 5 % (0 MB)
25 23:19:13.013801 progress 10 % (0 MB)
26 23:19:13.015197 progress 15 % (0 MB)
27 23:19:13.016796 progress 20 % (1 MB)
28 23:19:13.018225 progress 25 % (1 MB)
29 23:19:13.019802 progress 30 % (1 MB)
30 23:19:13.021412 progress 35 % (1 MB)
31 23:19:13.022817 progress 40 % (2 MB)
32 23:19:13.024378 progress 45 % (2 MB)
33 23:19:13.025815 progress 50 % (2 MB)
34 23:19:13.027377 progress 55 % (2 MB)
35 23:19:13.028972 progress 60 % (3 MB)
36 23:19:13.030401 progress 65 % (3 MB)
37 23:19:13.031962 progress 70 % (3 MB)
38 23:19:13.033491 progress 75 % (4 MB)
39 23:19:13.035067 progress 80 % (4 MB)
40 23:19:13.036563 progress 85 % (4 MB)
41 23:19:13.038197 progress 90 % (4 MB)
42 23:19:13.039801 progress 95 % (5 MB)
43 23:19:13.041267 progress 100 % (5 MB)
44 23:19:13.041510 5 MB downloaded in 3.35 s (1.60 MB/s)
45 23:19:13.041703 end: 1.1.1 http-download (duration 00:00:03) [common]
47 23:19:13.042004 end: 1.1 download-retry (duration 00:00:03) [common]
48 23:19:13.042096 start: 1.2 download-retry (timeout 00:09:57) [common]
49 23:19:13.042218 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 23:19:13.042403 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:19:13.042475 saving as /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/kernel/Image
52 23:19:13.042573 total size: 54286848 (51 MB)
53 23:19:13.042688 No compression specified
54 23:19:13.043792 progress 0 % (0 MB)
55 23:19:13.057530 progress 5 % (2 MB)
56 23:19:13.071646 progress 10 % (5 MB)
57 23:19:13.086533 progress 15 % (7 MB)
58 23:19:13.101965 progress 20 % (10 MB)
59 23:19:13.115813 progress 25 % (12 MB)
60 23:19:13.129528 progress 30 % (15 MB)
61 23:19:13.143542 progress 35 % (18 MB)
62 23:19:13.157377 progress 40 % (20 MB)
63 23:19:13.171166 progress 45 % (23 MB)
64 23:19:13.185142 progress 50 % (25 MB)
65 23:19:13.199118 progress 55 % (28 MB)
66 23:19:13.213116 progress 60 % (31 MB)
67 23:19:13.226838 progress 65 % (33 MB)
68 23:19:13.240809 progress 70 % (36 MB)
69 23:19:13.254851 progress 75 % (38 MB)
70 23:19:13.268740 progress 80 % (41 MB)
71 23:19:13.282639 progress 85 % (44 MB)
72 23:19:13.296543 progress 90 % (46 MB)
73 23:19:13.310301 progress 95 % (49 MB)
74 23:19:13.324042 progress 100 % (51 MB)
75 23:19:13.324278 51 MB downloaded in 0.28 s (183.78 MB/s)
76 23:19:13.324442 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:19:13.324698 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:19:13.324791 start: 1.3 download-retry (timeout 00:09:56) [common]
80 23:19:13.324884 start: 1.3.1 http-download (timeout 00:09:56) [common]
81 23:19:13.325024 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:19:13.325098 saving as /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/dtb/mt8192-asurada-spherion-r0.dtb
83 23:19:13.325164 total size: 47230 (0 MB)
84 23:19:13.325230 No compression specified
85 23:19:13.326330 progress 69 % (0 MB)
86 23:19:13.326613 progress 100 % (0 MB)
87 23:19:13.326774 0 MB downloaded in 0.00 s (28.01 MB/s)
88 23:19:13.326905 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:19:13.327137 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:19:13.327230 start: 1.4 download-retry (timeout 00:09:56) [common]
92 23:19:13.327318 start: 1.4.1 http-download (timeout 00:09:56) [common]
93 23:19:13.327434 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 23:19:13.327504 saving as /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/nfsrootfs/full.rootfs.tar
95 23:19:13.327568 total size: 69067788 (65 MB)
96 23:19:13.327634 Using unxz to decompress xz
97 23:19:13.331179 progress 0 % (0 MB)
98 23:19:13.534975 progress 5 % (3 MB)
99 23:19:13.753150 progress 10 % (6 MB)
100 23:19:13.967948 progress 15 % (9 MB)
101 23:19:14.136752 progress 20 % (13 MB)
102 23:19:14.317183 progress 25 % (16 MB)
103 23:19:14.525620 progress 30 % (19 MB)
104 23:19:14.645491 progress 35 % (23 MB)
105 23:19:14.743388 progress 40 % (26 MB)
106 23:19:14.949399 progress 45 % (29 MB)
107 23:19:15.170051 progress 50 % (32 MB)
108 23:19:15.385788 progress 55 % (36 MB)
109 23:19:15.618508 progress 60 % (39 MB)
110 23:19:15.805396 progress 65 % (42 MB)
111 23:19:15.997755 progress 70 % (46 MB)
112 23:19:16.189203 progress 75 % (49 MB)
113 23:19:16.404269 progress 80 % (52 MB)
114 23:19:16.587211 progress 85 % (56 MB)
115 23:19:16.777041 progress 90 % (59 MB)
116 23:19:16.981501 progress 95 % (62 MB)
117 23:19:17.190378 progress 100 % (65 MB)
118 23:19:17.196862 65 MB downloaded in 3.87 s (17.02 MB/s)
119 23:19:17.197121 end: 1.4.1 http-download (duration 00:00:04) [common]
121 23:19:17.197479 end: 1.4 download-retry (duration 00:00:04) [common]
122 23:19:17.197586 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:19:17.197709 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:19:17.197871 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:19:17.197944 saving as /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/modules/modules.tar
126 23:19:17.198007 total size: 8629908 (8 MB)
127 23:19:17.198076 Using unxz to decompress xz
128 23:19:17.201947 progress 0 % (0 MB)
129 23:19:17.220978 progress 5 % (0 MB)
130 23:19:17.245582 progress 10 % (0 MB)
131 23:19:17.269330 progress 15 % (1 MB)
132 23:19:17.292420 progress 20 % (1 MB)
133 23:19:17.317924 progress 25 % (2 MB)
134 23:19:17.343564 progress 30 % (2 MB)
135 23:19:17.367428 progress 35 % (2 MB)
136 23:19:17.392253 progress 40 % (3 MB)
137 23:19:17.415627 progress 45 % (3 MB)
138 23:19:17.440673 progress 50 % (4 MB)
139 23:19:17.465324 progress 55 % (4 MB)
140 23:19:17.492920 progress 60 % (4 MB)
141 23:19:17.517619 progress 65 % (5 MB)
142 23:19:17.542295 progress 70 % (5 MB)
143 23:19:17.566859 progress 75 % (6 MB)
144 23:19:17.591763 progress 80 % (6 MB)
145 23:19:17.617107 progress 85 % (7 MB)
146 23:19:17.645195 progress 90 % (7 MB)
147 23:19:17.673969 progress 95 % (7 MB)
148 23:19:17.700130 progress 100 % (8 MB)
149 23:19:17.705545 8 MB downloaded in 0.51 s (16.22 MB/s)
150 23:19:17.705797 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:19:17.706070 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:19:17.706172 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 23:19:17.706269 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 23:19:19.135917 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13248443/extract-nfsrootfs-6x_hms3y
156 23:19:19.136115 end: 1.6.1 extract-nfsrootfs (duration 00:00:01) [common]
157 23:19:19.136216 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 23:19:19.136373 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew
159 23:19:19.136502 makedir: /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin
160 23:19:19.136602 makedir: /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/tests
161 23:19:19.136705 makedir: /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/results
162 23:19:19.136804 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-add-keys
163 23:19:19.136940 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-add-sources
164 23:19:19.137065 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-background-process-start
165 23:19:19.137187 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-background-process-stop
166 23:19:19.137307 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-common-functions
167 23:19:19.137425 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-echo-ipv4
168 23:19:19.137544 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-install-packages
169 23:19:19.137662 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-installed-packages
170 23:19:19.137780 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-os-build
171 23:19:19.137897 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-probe-channel
172 23:19:19.138019 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-probe-ip
173 23:19:19.138137 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-target-ip
174 23:19:19.138254 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-target-mac
175 23:19:19.138372 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-target-storage
176 23:19:19.138491 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-test-case
177 23:19:19.138611 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-test-event
178 23:19:19.138727 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-test-feedback
179 23:19:19.138845 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-test-raise
180 23:19:19.138963 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-test-reference
181 23:19:19.139079 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-test-runner
182 23:19:19.139196 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-test-set
183 23:19:19.139312 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-test-shell
184 23:19:19.139430 Updating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-install-packages (oe)
185 23:19:19.139579 Updating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/bin/lava-installed-packages (oe)
186 23:19:19.139703 Creating /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/environment
187 23:19:19.139801 LAVA metadata
188 23:19:19.139872 - LAVA_JOB_ID=13248443
189 23:19:19.139935 - LAVA_DISPATCHER_IP=192.168.201.1
190 23:19:19.140032 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 23:19:19.140099 skipped lava-vland-overlay
192 23:19:19.140172 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 23:19:19.140253 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 23:19:19.140313 skipped lava-multinode-overlay
195 23:19:19.140385 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 23:19:19.140462 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 23:19:19.140533 Loading test definitions
198 23:19:19.140620 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 23:19:19.140764 Using /lava-13248443 at stage 0
200 23:19:19.141120 uuid=13248443_1.6.2.3.1 testdef=None
201 23:19:19.141209 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 23:19:19.141294 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 23:19:19.141768 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 23:19:19.142021 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 23:19:19.142620 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 23:19:19.142848 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 23:19:19.143430 runner path: /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/0/tests/0_lc-compliance test_uuid 13248443_1.6.2.3.1
210 23:19:19.143583 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 23:19:19.143788 Creating lava-test-runner.conf files
213 23:19:19.143851 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248443/lava-overlay-ikrak_ew/lava-13248443/0 for stage 0
214 23:19:19.143937 - 0_lc-compliance
215 23:19:19.144032 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 23:19:19.144115 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 23:19:19.149745 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 23:19:19.149847 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 23:19:19.149931 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 23:19:19.150016 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 23:19:19.150100 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 23:19:19.309355 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 23:19:19.309699 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
224 23:19:19.309807 extracting modules file /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248443/extract-nfsrootfs-6x_hms3y
225 23:19:19.510728 extracting modules file /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248443/extract-overlay-ramdisk-vc5h2qt7/ramdisk
226 23:19:19.717051 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 23:19:19.717214 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
228 23:19:19.717311 [common] Applying overlay to NFS
229 23:19:19.717384 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248443/compress-overlay-uygnwqcf/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248443/extract-nfsrootfs-6x_hms3y
230 23:19:19.723571 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 23:19:19.723688 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
232 23:19:19.723783 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 23:19:19.723875 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
234 23:19:19.723958 Building ramdisk /var/lib/lava/dispatcher/tmp/13248443/extract-overlay-ramdisk-vc5h2qt7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248443/extract-overlay-ramdisk-vc5h2qt7/ramdisk
235 23:19:20.012643 >> 130593 blocks
236 23:19:22.021211 rename /var/lib/lava/dispatcher/tmp/13248443/extract-overlay-ramdisk-vc5h2qt7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/ramdisk/ramdisk.cpio.gz
237 23:19:22.021637 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 23:19:22.021758 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
239 23:19:22.021863 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
240 23:19:22.021973 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/kernel/Image'
241 23:19:35.237666 Returned 0 in 13 seconds
242 23:19:35.338268 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/kernel/image.itb
243 23:19:35.684208 output: FIT description: Kernel Image image with one or more FDT blobs
244 23:19:35.684558 output: Created: Thu Apr 4 00:19:35 2024
245 23:19:35.684637 output: Image 0 (kernel-1)
246 23:19:35.684744 output: Description:
247 23:19:35.684806 output: Created: Thu Apr 4 00:19:35 2024
248 23:19:35.684871 output: Type: Kernel Image
249 23:19:35.684934 output: Compression: lzma compressed
250 23:19:35.684995 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
251 23:19:35.685059 output: Architecture: AArch64
252 23:19:35.685124 output: OS: Linux
253 23:19:35.685184 output: Load Address: 0x00000000
254 23:19:35.685242 output: Entry Point: 0x00000000
255 23:19:35.685297 output: Hash algo: crc32
256 23:19:35.685356 output: Hash value: d7c9dcc1
257 23:19:35.685412 output: Image 1 (fdt-1)
258 23:19:35.685470 output: Description: mt8192-asurada-spherion-r0
259 23:19:35.685527 output: Created: Thu Apr 4 00:19:35 2024
260 23:19:35.685583 output: Type: Flat Device Tree
261 23:19:35.685638 output: Compression: uncompressed
262 23:19:35.685694 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
263 23:19:35.685750 output: Architecture: AArch64
264 23:19:35.685805 output: Hash algo: crc32
265 23:19:35.685860 output: Hash value: 4bf0d1ac
266 23:19:35.685915 output: Image 2 (ramdisk-1)
267 23:19:35.685969 output: Description: unavailable
268 23:19:35.686024 output: Created: Thu Apr 4 00:19:35 2024
269 23:19:35.686078 output: Type: RAMDisk Image
270 23:19:35.686133 output: Compression: Unknown Compression
271 23:19:35.686187 output: Data Size: 18776442 Bytes = 18336.37 KiB = 17.91 MiB
272 23:19:35.686242 output: Architecture: AArch64
273 23:19:35.686297 output: OS: Linux
274 23:19:35.686351 output: Load Address: unavailable
275 23:19:35.686405 output: Entry Point: unavailable
276 23:19:35.686460 output: Hash algo: crc32
277 23:19:35.686514 output: Hash value: 4d4648c4
278 23:19:35.686568 output: Default Configuration: 'conf-1'
279 23:19:35.686623 output: Configuration 0 (conf-1)
280 23:19:35.686677 output: Description: mt8192-asurada-spherion-r0
281 23:19:35.686731 output: Kernel: kernel-1
282 23:19:35.686786 output: Init Ramdisk: ramdisk-1
283 23:19:35.686840 output: FDT: fdt-1
284 23:19:35.686895 output: Loadables: kernel-1
285 23:19:35.686948 output:
286 23:19:35.687138 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 23:19:35.687243 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 23:19:35.687349 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 23:19:35.687445 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
290 23:19:35.687528 No LXC device requested
291 23:19:35.687608 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 23:19:35.687695 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
293 23:19:35.687775 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 23:19:35.687844 Checking files for TFTP limit of 4294967296 bytes.
295 23:19:35.688316 end: 1 tftp-deploy (duration 00:00:26) [common]
296 23:19:35.688419 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 23:19:35.688516 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 23:19:35.688650 substitutions:
299 23:19:35.688755 - {DTB}: 13248443/tftp-deploy-j1vc58mq/dtb/mt8192-asurada-spherion-r0.dtb
300 23:19:35.688823 - {INITRD}: 13248443/tftp-deploy-j1vc58mq/ramdisk/ramdisk.cpio.gz
301 23:19:35.688886 - {KERNEL}: 13248443/tftp-deploy-j1vc58mq/kernel/Image
302 23:19:35.688947 - {LAVA_MAC}: None
303 23:19:35.689007 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13248443/extract-nfsrootfs-6x_hms3y
304 23:19:35.689066 - {NFS_SERVER_IP}: 192.168.201.1
305 23:19:35.689124 - {PRESEED_CONFIG}: None
306 23:19:35.689180 - {PRESEED_LOCAL}: None
307 23:19:35.689237 - {RAMDISK}: 13248443/tftp-deploy-j1vc58mq/ramdisk/ramdisk.cpio.gz
308 23:19:35.689294 - {ROOT_PART}: None
309 23:19:35.689351 - {ROOT}: None
310 23:19:35.689407 - {SERVER_IP}: 192.168.201.1
311 23:19:35.689463 - {TEE}: None
312 23:19:35.689521 Parsed boot commands:
313 23:19:35.689577 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 23:19:35.689750 Parsed boot commands: tftpboot 192.168.201.1 13248443/tftp-deploy-j1vc58mq/kernel/image.itb 13248443/tftp-deploy-j1vc58mq/kernel/cmdline
315 23:19:35.689840 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 23:19:35.689927 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 23:19:35.690019 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 23:19:35.690110 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 23:19:35.690183 Not connected, no need to disconnect.
320 23:19:35.690258 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 23:19:35.690341 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 23:19:35.690412 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
323 23:19:35.693771 Setting prompt string to ['lava-test: # ']
324 23:19:35.694109 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 23:19:35.694220 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 23:19:35.694315 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 23:19:35.694437 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 23:19:35.694639 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
329 23:19:40.828556 >> Command sent successfully.
330 23:19:40.830892 Returned 0 in 5 seconds
331 23:19:40.931281 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 23:19:40.931613 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 23:19:40.931718 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 23:19:40.931807 Setting prompt string to 'Starting depthcharge on Spherion...'
336 23:19:40.931882 Changing prompt to 'Starting depthcharge on Spherion...'
337 23:19:40.931952 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 23:19:40.932215 [Enter `^Ec?' for help]
339 23:19:41.107806
340 23:19:41.107948
341 23:19:41.108021 F0: 102B 0000
342 23:19:41.108088
343 23:19:41.108152 F3: 1001 0000 [0200]
344 23:19:41.111159
345 23:19:41.111245 F3: 1001 0000
346 23:19:41.111314
347 23:19:41.111378 F7: 102D 0000
348 23:19:41.111439
349 23:19:41.114358 F1: 0000 0000
350 23:19:41.114444
351 23:19:41.114512 V0: 0000 0000 [0001]
352 23:19:41.114576
353 23:19:41.117829 00: 0007 8000
354 23:19:41.117947
355 23:19:41.118036 01: 0000 0000
356 23:19:41.118103
357 23:19:41.121219 BP: 0C00 0209 [0000]
358 23:19:41.121303
359 23:19:41.121371 G0: 1182 0000
360 23:19:41.121434
361 23:19:41.124987 EC: 0000 0021 [4000]
362 23:19:41.125071
363 23:19:41.125139 S7: 0000 0000 [0000]
364 23:19:41.125202
365 23:19:41.128353 CC: 0000 0000 [0001]
366 23:19:41.128438
367 23:19:41.128506 T0: 0000 0040 [010F]
368 23:19:41.128571
369 23:19:41.128632 Jump to BL
370 23:19:41.128726
371 23:19:41.155115
372 23:19:41.155203
373 23:19:41.155271
374 23:19:41.161994 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 23:19:41.166268 ARM64: Exception handlers installed.
376 23:19:41.169640 ARM64: Testing exception
377 23:19:41.172750 ARM64: Done test exception
378 23:19:41.179653 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 23:19:41.190041 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 23:19:41.196701 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 23:19:41.206516 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 23:19:41.213596 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 23:19:41.219942 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 23:19:41.231056 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 23:19:41.237968 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 23:19:41.257378 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 23:19:41.260772 WDT: Last reset was cold boot
388 23:19:41.264080 SPI1(PAD0) initialized at 2873684 Hz
389 23:19:41.267454 SPI5(PAD0) initialized at 992727 Hz
390 23:19:41.271393 VBOOT: Loading verstage.
391 23:19:41.277536 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 23:19:41.280886 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 23:19:41.284256 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 23:19:41.287527 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 23:19:41.294831 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 23:19:41.301640 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 23:19:41.312792 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
398 23:19:41.312878
399 23:19:41.312947
400 23:19:41.322605 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 23:19:41.325729 ARM64: Exception handlers installed.
402 23:19:41.329475 ARM64: Testing exception
403 23:19:41.329561 ARM64: Done test exception
404 23:19:41.335729 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 23:19:41.339261 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 23:19:41.353410 Probing TPM: . done!
407 23:19:41.353496 TPM ready after 0 ms
408 23:19:41.360416 Connected to device vid:did:rid of 1ae0:0028:00
409 23:19:41.367570 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 23:19:41.424178 Initialized TPM device CR50 revision 0
411 23:19:41.436346 tlcl_send_startup: Startup return code is 0
412 23:19:41.436438 TPM: setup succeeded
413 23:19:41.447813 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 23:19:41.456707 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 23:19:41.466889 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 23:19:41.476187 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 23:19:41.479329 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 23:19:41.485970 in-header: 03 07 00 00 08 00 00 00
419 23:19:41.489737 in-data: aa e4 47 04 13 02 00 00
420 23:19:41.493316 Chrome EC: UHEPI supported
421 23:19:41.500473 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 23:19:41.504283 in-header: 03 ad 00 00 08 00 00 00
423 23:19:41.507554 in-data: 00 20 20 08 00 00 00 00
424 23:19:41.507640 Phase 1
425 23:19:41.511315 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 23:19:41.519101 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 23:19:41.522693 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 23:19:41.526843 Recovery requested (1009000e)
429 23:19:41.535496 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 23:19:41.541338 tlcl_extend: response is 0
431 23:19:41.550249 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 23:19:41.555892 tlcl_extend: response is 0
433 23:19:41.562869 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 23:19:41.583423 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 23:19:41.590037 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 23:19:41.590123
437 23:19:41.590214
438 23:19:41.600175 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 23:19:41.603507 ARM64: Exception handlers installed.
440 23:19:41.603587 ARM64: Testing exception
441 23:19:41.606918 ARM64: Done test exception
442 23:19:41.628682 pmic_efuse_setting: Set efuses in 11 msecs
443 23:19:41.632050 pmwrap_interface_init: Select PMIF_VLD_RDY
444 23:19:41.638927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 23:19:41.642379 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 23:19:41.645591 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 23:19:41.652233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 23:19:41.655942 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 23:19:41.663558 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 23:19:41.667126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 23:19:41.670875 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 23:19:41.674759 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 23:19:41.682306 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 23:19:41.685670 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 23:19:41.689048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 23:19:41.692448 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 23:19:41.700173 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 23:19:41.706461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 23:19:41.713758 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 23:19:41.717692 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 23:19:41.725384 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 23:19:41.728859 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 23:19:41.736016 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 23:19:41.739156 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 23:19:41.746445 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 23:19:41.749747 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 23:19:41.756529 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 23:19:41.763104 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 23:19:41.766752 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 23:19:41.773261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 23:19:41.776585 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 23:19:41.783193 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 23:19:41.786547 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 23:19:41.792863 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 23:19:41.796303 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 23:19:41.803119 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 23:19:41.806321 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 23:19:41.813124 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 23:19:41.816449 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 23:19:41.823250 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 23:19:41.826288 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 23:19:41.833509 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 23:19:41.837372 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 23:19:41.840654 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 23:19:41.844322 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 23:19:41.850959 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 23:19:41.854358 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 23:19:41.857636 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 23:19:41.864211 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 23:19:41.867457 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 23:19:41.870633 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 23:19:41.874441 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 23:19:41.880777 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 23:19:41.883814 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 23:19:41.890544 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 23:19:41.900983 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 23:19:41.904106 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 23:19:41.910770 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 23:19:41.920807 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 23:19:41.924376 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 23:19:41.930661 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 23:19:41.934297 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 23:19:41.941329 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x10
504 23:19:41.947964 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 23:19:41.951246 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 23:19:41.954512 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 23:19:41.965806 [RTC]rtc_get_frequency_meter,154: input=15, output=771
508 23:19:41.975139 [RTC]rtc_get_frequency_meter,154: input=23, output=958
509 23:19:41.984359 [RTC]rtc_get_frequency_meter,154: input=19, output=865
510 23:19:41.994283 [RTC]rtc_get_frequency_meter,154: input=17, output=818
511 23:19:42.003752 [RTC]rtc_get_frequency_meter,154: input=16, output=794
512 23:19:42.006751 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
513 23:19:42.013933 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
514 23:19:42.017012 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
515 23:19:42.020356 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
516 23:19:42.023573 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
517 23:19:42.026963 ADC[4]: Raw value=903245 ID=7
518 23:19:42.030145 ADC[3]: Raw value=213179 ID=1
519 23:19:42.030225 RAM Code: 0x71
520 23:19:42.036952 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
521 23:19:42.040394 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
522 23:19:42.050317 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
523 23:19:42.056874 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
524 23:19:42.060046 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
525 23:19:42.063376 in-header: 03 07 00 00 08 00 00 00
526 23:19:42.066896 in-data: aa e4 47 04 13 02 00 00
527 23:19:42.070123 Chrome EC: UHEPI supported
528 23:19:42.076696 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
529 23:19:42.080077 in-header: 03 ed 00 00 08 00 00 00
530 23:19:42.083157 in-data: 80 20 60 08 00 00 00 00
531 23:19:42.086499 MRC: failed to locate region type 0.
532 23:19:42.093294 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
533 23:19:42.096547 DRAM-K: Running full calibration
534 23:19:42.103200 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
535 23:19:42.103281 header.status = 0x0
536 23:19:42.106717 header.version = 0x6 (expected: 0x6)
537 23:19:42.109854 header.size = 0xd00 (expected: 0xd00)
538 23:19:42.113560 header.flags = 0x0
539 23:19:42.119602 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
540 23:19:42.136362 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
541 23:19:42.143861 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
542 23:19:42.147662 dram_init: ddr_geometry: 2
543 23:19:42.147742 [EMI] MDL number = 2
544 23:19:42.151740 [EMI] Get MDL freq = 0
545 23:19:42.151821 dram_init: ddr_type: 0
546 23:19:42.154974 is_discrete_lpddr4: 1
547 23:19:42.159123 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
548 23:19:42.159202
549 23:19:42.159272
550 23:19:42.162795 [Bian_co] ETT version 0.0.0.1
551 23:19:42.166386 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
552 23:19:42.166464
553 23:19:42.169995 dramc_set_vcore_voltage set vcore to 650000
554 23:19:42.170077 Read voltage for 800, 4
555 23:19:42.173582 Vio18 = 0
556 23:19:42.173663 Vcore = 650000
557 23:19:42.173731 Vdram = 0
558 23:19:42.177358 Vddq = 0
559 23:19:42.177438 Vmddr = 0
560 23:19:42.177503 dram_init: config_dvfs: 1
561 23:19:42.184572 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
562 23:19:42.188583 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
563 23:19:42.192652 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
564 23:19:42.195993 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
565 23:19:42.199390 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
566 23:19:42.206012 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
567 23:19:42.206094 MEM_TYPE=3, freq_sel=18
568 23:19:42.209333 sv_algorithm_assistance_LP4_1600
569 23:19:42.213003 ============ PULL DRAM RESETB DOWN ============
570 23:19:42.219340 ========== PULL DRAM RESETB DOWN end =========
571 23:19:42.222931 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
572 23:19:42.226297 ===================================
573 23:19:42.229254 LPDDR4 DRAM CONFIGURATION
574 23:19:42.232806 ===================================
575 23:19:42.232884 EX_ROW_EN[0] = 0x0
576 23:19:42.236289 EX_ROW_EN[1] = 0x0
577 23:19:42.236361 LP4Y_EN = 0x0
578 23:19:42.239571 WORK_FSP = 0x0
579 23:19:42.239649 WL = 0x2
580 23:19:42.242713 RL = 0x2
581 23:19:42.242786 BL = 0x2
582 23:19:42.246239 RPST = 0x0
583 23:19:42.246312 RD_PRE = 0x0
584 23:19:42.249289 WR_PRE = 0x1
585 23:19:42.249362 WR_PST = 0x0
586 23:19:42.252755 DBI_WR = 0x0
587 23:19:42.256206 DBI_RD = 0x0
588 23:19:42.256287 OTF = 0x1
589 23:19:42.260280 ===================================
590 23:19:42.263987 ===================================
591 23:19:42.264070 ANA top config
592 23:19:42.267206 ===================================
593 23:19:42.271200 DLL_ASYNC_EN = 0
594 23:19:42.271280 ALL_SLAVE_EN = 1
595 23:19:42.274776 NEW_RANK_MODE = 1
596 23:19:42.278829 DLL_IDLE_MODE = 1
597 23:19:42.282118 LP45_APHY_COMB_EN = 1
598 23:19:42.282204 TX_ODT_DIS = 1
599 23:19:42.285249 NEW_8X_MODE = 1
600 23:19:42.288814 ===================================
601 23:19:42.291886 ===================================
602 23:19:42.295737 data_rate = 1600
603 23:19:42.298767 CKR = 1
604 23:19:42.298852 DQ_P2S_RATIO = 8
605 23:19:42.302448 ===================================
606 23:19:42.305584 CA_P2S_RATIO = 8
607 23:19:42.309241 DQ_CA_OPEN = 0
608 23:19:42.312397 DQ_SEMI_OPEN = 0
609 23:19:42.315726 CA_SEMI_OPEN = 0
610 23:19:42.318551 CA_FULL_RATE = 0
611 23:19:42.318635 DQ_CKDIV4_EN = 1
612 23:19:42.321969 CA_CKDIV4_EN = 1
613 23:19:42.325369 CA_PREDIV_EN = 0
614 23:19:42.328624 PH8_DLY = 0
615 23:19:42.332268 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
616 23:19:42.335784 DQ_AAMCK_DIV = 4
617 23:19:42.335870 CA_AAMCK_DIV = 4
618 23:19:42.338952 CA_ADMCK_DIV = 4
619 23:19:42.342319 DQ_TRACK_CA_EN = 0
620 23:19:42.345602 CA_PICK = 800
621 23:19:42.349075 CA_MCKIO = 800
622 23:19:42.352613 MCKIO_SEMI = 0
623 23:19:42.352721 PLL_FREQ = 3068
624 23:19:42.355938 DQ_UI_PI_RATIO = 32
625 23:19:42.359319 CA_UI_PI_RATIO = 0
626 23:19:42.362525 ===================================
627 23:19:42.365840 ===================================
628 23:19:42.369012 memory_type:LPDDR4
629 23:19:42.369098 GP_NUM : 10
630 23:19:42.372797 SRAM_EN : 1
631 23:19:42.375700 MD32_EN : 0
632 23:19:42.379253 ===================================
633 23:19:42.379337 [ANA_INIT] >>>>>>>>>>>>>>
634 23:19:42.383316 <<<<<< [CONFIGURE PHASE]: ANA_TX
635 23:19:42.386467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
636 23:19:42.390374 ===================================
637 23:19:42.393803 data_rate = 1600,PCW = 0X7600
638 23:19:42.397553 ===================================
639 23:19:42.401414 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
640 23:19:42.405309 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
641 23:19:42.408975 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
642 23:19:42.416556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
643 23:19:42.419740 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
644 23:19:42.423169 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
645 23:19:42.423256 [ANA_INIT] flow start
646 23:19:42.426489 [ANA_INIT] PLL >>>>>>>>
647 23:19:42.429764 [ANA_INIT] PLL <<<<<<<<
648 23:19:42.429850 [ANA_INIT] MIDPI >>>>>>>>
649 23:19:42.433033 [ANA_INIT] MIDPI <<<<<<<<
650 23:19:42.436629 [ANA_INIT] DLL >>>>>>>>
651 23:19:42.436725 [ANA_INIT] flow end
652 23:19:42.443183 ============ LP4 DIFF to SE enter ============
653 23:19:42.446509 ============ LP4 DIFF to SE exit ============
654 23:19:42.446595 [ANA_INIT] <<<<<<<<<<<<<
655 23:19:42.449641 [Flow] Enable top DCM control >>>>>
656 23:19:42.453309 [Flow] Enable top DCM control <<<<<
657 23:19:42.456606 Enable DLL master slave shuffle
658 23:19:42.462880 ==============================================================
659 23:19:42.466262 Gating Mode config
660 23:19:42.469955 ==============================================================
661 23:19:42.473323 Config description:
662 23:19:42.483058 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
663 23:19:42.489732 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
664 23:19:42.493048 SELPH_MODE 0: By rank 1: By Phase
665 23:19:42.499910 ==============================================================
666 23:19:42.503087 GAT_TRACK_EN = 1
667 23:19:42.506451 RX_GATING_MODE = 2
668 23:19:42.506537 RX_GATING_TRACK_MODE = 2
669 23:19:42.509654 SELPH_MODE = 1
670 23:19:42.513395 PICG_EARLY_EN = 1
671 23:19:42.516399 VALID_LAT_VALUE = 1
672 23:19:42.523432 ==============================================================
673 23:19:42.526573 Enter into Gating configuration >>>>
674 23:19:42.530088 Exit from Gating configuration <<<<
675 23:19:42.533380 Enter into DVFS_PRE_config >>>>>
676 23:19:42.543673 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
677 23:19:42.546795 Exit from DVFS_PRE_config <<<<<
678 23:19:42.550053 Enter into PICG configuration >>>>
679 23:19:42.554087 Exit from PICG configuration <<<<
680 23:19:42.556729 [RX_INPUT] configuration >>>>>
681 23:19:42.556815 [RX_INPUT] configuration <<<<<
682 23:19:42.563737 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
683 23:19:42.570242 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
684 23:19:42.573775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
685 23:19:42.580490 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
686 23:19:42.587112 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
687 23:19:42.593725 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
688 23:19:42.597114 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
689 23:19:42.600432 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
690 23:19:42.607287 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
691 23:19:42.610784 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
692 23:19:42.614183 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
693 23:19:42.617568 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 23:19:42.620860 ===================================
695 23:19:42.623990 LPDDR4 DRAM CONFIGURATION
696 23:19:42.627600 ===================================
697 23:19:42.631090 EX_ROW_EN[0] = 0x0
698 23:19:42.631175 EX_ROW_EN[1] = 0x0
699 23:19:42.634079 LP4Y_EN = 0x0
700 23:19:42.634165 WORK_FSP = 0x0
701 23:19:42.637379 WL = 0x2
702 23:19:42.637465 RL = 0x2
703 23:19:42.641174 BL = 0x2
704 23:19:42.641259 RPST = 0x0
705 23:19:42.644298 RD_PRE = 0x0
706 23:19:42.644383 WR_PRE = 0x1
707 23:19:42.647687 WR_PST = 0x0
708 23:19:42.647773 DBI_WR = 0x0
709 23:19:42.651271 DBI_RD = 0x0
710 23:19:42.651357 OTF = 0x1
711 23:19:42.654754 ===================================
712 23:19:42.657888 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
713 23:19:42.664529 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
714 23:19:42.667809 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
715 23:19:42.671330 ===================================
716 23:19:42.674689 LPDDR4 DRAM CONFIGURATION
717 23:19:42.677914 ===================================
718 23:19:42.678001 EX_ROW_EN[0] = 0x10
719 23:19:42.681189 EX_ROW_EN[1] = 0x0
720 23:19:42.681274 LP4Y_EN = 0x0
721 23:19:42.684561 WORK_FSP = 0x0
722 23:19:42.684653 WL = 0x2
723 23:19:42.688076 RL = 0x2
724 23:19:42.688161 BL = 0x2
725 23:19:42.691278 RPST = 0x0
726 23:19:42.694733 RD_PRE = 0x0
727 23:19:42.694819 WR_PRE = 0x1
728 23:19:42.698369 WR_PST = 0x0
729 23:19:42.698455 DBI_WR = 0x0
730 23:19:42.701392 DBI_RD = 0x0
731 23:19:42.701478 OTF = 0x1
732 23:19:42.704939 ===================================
733 23:19:42.711318 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
734 23:19:42.715443 nWR fixed to 40
735 23:19:42.715530 [ModeRegInit_LP4] CH0 RK0
736 23:19:42.719239 [ModeRegInit_LP4] CH0 RK1
737 23:19:42.722602 [ModeRegInit_LP4] CH1 RK0
738 23:19:42.722689 [ModeRegInit_LP4] CH1 RK1
739 23:19:42.726413 match AC timing 13
740 23:19:42.730100 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
741 23:19:42.733658 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
742 23:19:42.737683 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
743 23:19:42.744781 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
744 23:19:42.748840 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
745 23:19:42.748926 [EMI DOE] emi_dcm 0
746 23:19:42.752901 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
747 23:19:42.752987 ==
748 23:19:42.756303 Dram Type= 6, Freq= 0, CH_0, rank 0
749 23:19:42.763988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 23:19:42.764105 ==
751 23:19:42.767212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 23:19:42.774420 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 23:19:42.783053 [CA 0] Center 38 (7~69) winsize 63
754 23:19:42.786849 [CA 1] Center 38 (7~69) winsize 63
755 23:19:42.790193 [CA 2] Center 35 (5~66) winsize 62
756 23:19:42.794278 [CA 3] Center 35 (4~66) winsize 63
757 23:19:42.797849 [CA 4] Center 34 (4~65) winsize 62
758 23:19:42.801810 [CA 5] Center 34 (3~65) winsize 63
759 23:19:42.801893
760 23:19:42.805007 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 23:19:42.805081
762 23:19:42.809063 [CATrainingPosCal] consider 1 rank data
763 23:19:42.809156 u2DelayCellTimex100 = 270/100 ps
764 23:19:42.812480 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
765 23:19:42.816426 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
766 23:19:42.819909 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
767 23:19:42.823806 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
768 23:19:42.827231 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
769 23:19:42.830937 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
770 23:19:42.831044
771 23:19:42.834633 CA PerBit enable=1, Macro0, CA PI delay=34
772 23:19:42.834731
773 23:19:42.838429 [CBTSetCACLKResult] CA Dly = 34
774 23:19:42.842291 CS Dly: 6 (0~37)
775 23:19:42.842391 ==
776 23:19:42.845698 Dram Type= 6, Freq= 0, CH_0, rank 1
777 23:19:42.849397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
778 23:19:42.849478 ==
779 23:19:42.853177 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
780 23:19:42.860202 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
781 23:19:42.869410 [CA 0] Center 38 (7~69) winsize 63
782 23:19:42.873394 [CA 1] Center 38 (7~69) winsize 63
783 23:19:42.877156 [CA 2] Center 36 (6~66) winsize 61
784 23:19:42.881154 [CA 3] Center 36 (6~66) winsize 61
785 23:19:42.881242 [CA 4] Center 35 (4~66) winsize 63
786 23:19:42.884824 [CA 5] Center 34 (4~65) winsize 62
787 23:19:42.884910
788 23:19:42.888693 [CmdBusTrainingLP45] Vref(ca) range 1: 32
789 23:19:42.888777
790 23:19:42.892122 [CATrainingPosCal] consider 2 rank data
791 23:19:42.896016 u2DelayCellTimex100 = 270/100 ps
792 23:19:42.899943 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
793 23:19:42.903439 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
794 23:19:42.907295 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
795 23:19:42.910581 CA3 delay=36 (6~66),Diff = 2 PI (14 cell)
796 23:19:42.914375 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
797 23:19:42.917887 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
798 23:19:42.917974
799 23:19:42.921624 CA PerBit enable=1, Macro0, CA PI delay=34
800 23:19:42.921710
801 23:19:42.925244 [CBTSetCACLKResult] CA Dly = 34
802 23:19:42.925331 CS Dly: 6 (0~38)
803 23:19:42.929140
804 23:19:42.929225 ----->DramcWriteLeveling(PI) begin...
805 23:19:42.932908 ==
806 23:19:42.932993 Dram Type= 6, Freq= 0, CH_0, rank 0
807 23:19:42.936768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 23:19:42.940069 ==
809 23:19:42.940155 Write leveling (Byte 0): 30 => 30
810 23:19:42.943775 Write leveling (Byte 1): 31 => 31
811 23:19:42.947677 DramcWriteLeveling(PI) end<-----
812 23:19:42.947763
813 23:19:42.947832 ==
814 23:19:42.951030 Dram Type= 6, Freq= 0, CH_0, rank 0
815 23:19:42.955468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
816 23:19:42.955555 ==
817 23:19:42.958656 [Gating] SW mode calibration
818 23:19:42.966412 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
819 23:19:42.969949 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
820 23:19:42.973557 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
821 23:19:42.980833 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
822 23:19:42.984877 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:19:42.988340 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:19:42.991863 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:19:42.995638 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:19:43.003002 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:19:43.006646 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:19:43.010420 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 23:19:43.014082 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 23:19:43.017944 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 23:19:43.021748 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 23:19:43.028418 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 23:19:43.031888 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 23:19:43.035360 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 23:19:43.041760 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 23:19:43.044836 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
837 23:19:43.048439 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
838 23:19:43.054982 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
839 23:19:43.058431 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 23:19:43.061649 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 23:19:43.068257 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 23:19:43.071857 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 23:19:43.075599 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 23:19:43.081891 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 23:19:43.085096 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
846 23:19:43.088324 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
847 23:19:43.091861 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
848 23:19:43.098722 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 23:19:43.101804 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 23:19:43.105150 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 23:19:43.111993 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 23:19:43.115343 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 23:19:43.118713 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
854 23:19:43.125440 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
855 23:19:43.128900 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:19:43.131638 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:19:43.138677 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:19:43.141840 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:19:43.145526 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:19:43.151891 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:19:43.154963 0 11 4 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
862 23:19:43.158269 0 11 8 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
863 23:19:43.164895 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
864 23:19:43.168557 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 23:19:43.171739 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 23:19:43.178357 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 23:19:43.181559 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 23:19:43.184846 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
869 23:19:43.191478 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
870 23:19:43.195228 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
871 23:19:43.198032 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
872 23:19:43.205215 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 23:19:43.208170 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 23:19:43.211787 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 23:19:43.214785 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 23:19:43.221618 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 23:19:43.225001 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 23:19:43.228437 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 23:19:43.234947 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 23:19:43.238404 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 23:19:43.241791 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 23:19:43.248094 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 23:19:43.251508 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 23:19:43.255194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 23:19:43.261806 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
886 23:19:43.265209 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
887 23:19:43.268302 Total UI for P1: 0, mck2ui 16
888 23:19:43.271409 best dqsien dly found for B0: ( 0, 14, 4)
889 23:19:43.274914 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 23:19:43.278281 Total UI for P1: 0, mck2ui 16
891 23:19:43.281447 best dqsien dly found for B1: ( 0, 14, 8)
892 23:19:43.284820 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
893 23:19:43.288169 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
894 23:19:43.288254
895 23:19:43.291695 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
896 23:19:43.298243 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
897 23:19:43.298328 [Gating] SW calibration Done
898 23:19:43.298397 ==
899 23:19:43.301539 Dram Type= 6, Freq= 0, CH_0, rank 0
900 23:19:43.308543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 23:19:43.308674 ==
902 23:19:43.308758 RX Vref Scan: 0
903 23:19:43.308822
904 23:19:43.311728 RX Vref 0 -> 0, step: 1
905 23:19:43.311812
906 23:19:43.315387 RX Delay -130 -> 252, step: 16
907 23:19:43.318163 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
908 23:19:43.321541 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
909 23:19:43.325007 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
910 23:19:43.331788 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
911 23:19:43.334955 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
912 23:19:43.338017 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
913 23:19:43.341544 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
914 23:19:43.344861 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
915 23:19:43.351427 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
916 23:19:43.354818 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
917 23:19:43.358126 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
918 23:19:43.361456 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
919 23:19:43.364832 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
920 23:19:43.371503 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
921 23:19:43.374979 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
922 23:19:43.377973 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
923 23:19:43.378058 ==
924 23:19:43.381342 Dram Type= 6, Freq= 0, CH_0, rank 0
925 23:19:43.384905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 23:19:43.384998 ==
927 23:19:43.388136 DQS Delay:
928 23:19:43.388225 DQS0 = 0, DQS1 = 0
929 23:19:43.391558 DQM Delay:
930 23:19:43.391662 DQM0 = 93, DQM1 = 81
931 23:19:43.391748 DQ Delay:
932 23:19:43.395123 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
933 23:19:43.398031 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
934 23:19:43.401546 DQ8 =77, DQ9 =61, DQ10 =85, DQ11 =77
935 23:19:43.405401 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
936 23:19:43.405482
937 23:19:43.405548
938 23:19:43.408029 ==
939 23:19:43.408108 Dram Type= 6, Freq= 0, CH_0, rank 0
940 23:19:43.415098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 23:19:43.415201 ==
942 23:19:43.415272
943 23:19:43.415334
944 23:19:43.418211 TX Vref Scan disable
945 23:19:43.418311 == TX Byte 0 ==
946 23:19:43.421665 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
947 23:19:43.428363 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
948 23:19:43.428467 == TX Byte 1 ==
949 23:19:43.431858 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
950 23:19:43.438395 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
951 23:19:43.438477 ==
952 23:19:43.441862 Dram Type= 6, Freq= 0, CH_0, rank 0
953 23:19:43.445115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 23:19:43.445193 ==
955 23:19:43.457665 TX Vref=22, minBit 5, minWin=27, winSum=437
956 23:19:43.461074 TX Vref=24, minBit 6, minWin=27, winSum=444
957 23:19:43.464571 TX Vref=26, minBit 8, minWin=27, winSum=446
958 23:19:43.467865 TX Vref=28, minBit 8, minWin=27, winSum=453
959 23:19:43.471263 TX Vref=30, minBit 8, minWin=27, winSum=457
960 23:19:43.478123 TX Vref=32, minBit 10, minWin=27, winSum=454
961 23:19:43.481219 [TxChooseVref] Worse bit 8, Min win 27, Win sum 457, Final Vref 30
962 23:19:43.481320
963 23:19:43.484259 Final TX Range 1 Vref 30
964 23:19:43.484365
965 23:19:43.484459 ==
966 23:19:43.488087 Dram Type= 6, Freq= 0, CH_0, rank 0
967 23:19:43.491107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 23:19:43.491209 ==
969 23:19:43.491301
970 23:19:43.491393
971 23:19:43.494781 TX Vref Scan disable
972 23:19:43.498132 == TX Byte 0 ==
973 23:19:43.501087 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
974 23:19:43.504537 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
975 23:19:43.507763 == TX Byte 1 ==
976 23:19:43.511479 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
977 23:19:43.514753 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
978 23:19:43.514832
979 23:19:43.517774 [DATLAT]
980 23:19:43.517847 Freq=800, CH0 RK0
981 23:19:43.517911
982 23:19:43.521421 DATLAT Default: 0xa
983 23:19:43.521497 0, 0xFFFF, sum = 0
984 23:19:43.524740 1, 0xFFFF, sum = 0
985 23:19:43.524847 2, 0xFFFF, sum = 0
986 23:19:43.527995 3, 0xFFFF, sum = 0
987 23:19:43.528072 4, 0xFFFF, sum = 0
988 23:19:43.531259 5, 0xFFFF, sum = 0
989 23:19:43.531337 6, 0xFFFF, sum = 0
990 23:19:43.534582 7, 0xFFFF, sum = 0
991 23:19:43.534660 8, 0xFFFF, sum = 0
992 23:19:43.538138 9, 0x0, sum = 1
993 23:19:43.538244 10, 0x0, sum = 2
994 23:19:43.541267 11, 0x0, sum = 3
995 23:19:43.541342 12, 0x0, sum = 4
996 23:19:43.544810 best_step = 10
997 23:19:43.544911
998 23:19:43.545003 ==
999 23:19:43.548240 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:19:43.551656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:19:43.551733 ==
1002 23:19:43.554748 RX Vref Scan: 1
1003 23:19:43.554824
1004 23:19:43.554891 Set Vref Range= 32 -> 127
1005 23:19:43.554953
1006 23:19:43.558000 RX Vref 32 -> 127, step: 1
1007 23:19:43.558072
1008 23:19:43.561400 RX Delay -95 -> 252, step: 8
1009 23:19:43.561474
1010 23:19:43.564651 Set Vref, RX VrefLevel [Byte0]: 32
1011 23:19:43.568023 [Byte1]: 32
1012 23:19:43.568112
1013 23:19:43.571357 Set Vref, RX VrefLevel [Byte0]: 33
1014 23:19:43.574793 [Byte1]: 33
1015 23:19:43.578110
1016 23:19:43.578185 Set Vref, RX VrefLevel [Byte0]: 34
1017 23:19:43.581044 [Byte1]: 34
1018 23:19:43.585546
1019 23:19:43.585627 Set Vref, RX VrefLevel [Byte0]: 35
1020 23:19:43.588814 [Byte1]: 35
1021 23:19:43.593245
1022 23:19:43.593349 Set Vref, RX VrefLevel [Byte0]: 36
1023 23:19:43.596562 [Byte1]: 36
1024 23:19:43.600883
1025 23:19:43.600964 Set Vref, RX VrefLevel [Byte0]: 37
1026 23:19:43.604149 [Byte1]: 37
1027 23:19:43.609259
1028 23:19:43.609339 Set Vref, RX VrefLevel [Byte0]: 38
1029 23:19:43.612934 [Byte1]: 38
1030 23:19:43.616065
1031 23:19:43.616170 Set Vref, RX VrefLevel [Byte0]: 39
1032 23:19:43.619335 [Byte1]: 39
1033 23:19:43.623435
1034 23:19:43.623512 Set Vref, RX VrefLevel [Byte0]: 40
1035 23:19:43.626778 [Byte1]: 40
1036 23:19:43.631727
1037 23:19:43.631807 Set Vref, RX VrefLevel [Byte0]: 41
1038 23:19:43.634990 [Byte1]: 41
1039 23:19:43.638843
1040 23:19:43.638927 Set Vref, RX VrefLevel [Byte0]: 42
1041 23:19:43.642567 [Byte1]: 42
1042 23:19:43.646941
1043 23:19:43.647048 Set Vref, RX VrefLevel [Byte0]: 43
1044 23:19:43.650159 [Byte1]: 43
1045 23:19:43.654047
1046 23:19:43.654153 Set Vref, RX VrefLevel [Byte0]: 44
1047 23:19:43.657411 [Byte1]: 44
1048 23:19:43.661964
1049 23:19:43.662077 Set Vref, RX VrefLevel [Byte0]: 45
1050 23:19:43.665525 [Byte1]: 45
1051 23:19:43.669104
1052 23:19:43.669184 Set Vref, RX VrefLevel [Byte0]: 46
1053 23:19:43.672760 [Byte1]: 46
1054 23:19:43.676889
1055 23:19:43.676972 Set Vref, RX VrefLevel [Byte0]: 47
1056 23:19:43.679827 [Byte1]: 47
1057 23:19:43.684292
1058 23:19:43.684375 Set Vref, RX VrefLevel [Byte0]: 48
1059 23:19:43.687960 [Byte1]: 48
1060 23:19:43.691920
1061 23:19:43.692003 Set Vref, RX VrefLevel [Byte0]: 49
1062 23:19:43.695086 [Byte1]: 49
1063 23:19:43.699545
1064 23:19:43.699628 Set Vref, RX VrefLevel [Byte0]: 50
1065 23:19:43.703241 [Byte1]: 50
1066 23:19:43.706990
1067 23:19:43.707073 Set Vref, RX VrefLevel [Byte0]: 51
1068 23:19:43.710710 [Byte1]: 51
1069 23:19:43.714700
1070 23:19:43.714782 Set Vref, RX VrefLevel [Byte0]: 52
1071 23:19:43.717843 [Byte1]: 52
1072 23:19:43.722082
1073 23:19:43.722164 Set Vref, RX VrefLevel [Byte0]: 53
1074 23:19:43.725507 [Byte1]: 53
1075 23:19:43.730225
1076 23:19:43.730308 Set Vref, RX VrefLevel [Byte0]: 54
1077 23:19:43.733540 [Byte1]: 54
1078 23:19:43.737358
1079 23:19:43.737441 Set Vref, RX VrefLevel [Byte0]: 55
1080 23:19:43.740718 [Byte1]: 55
1081 23:19:43.745158
1082 23:19:43.745242 Set Vref, RX VrefLevel [Byte0]: 56
1083 23:19:43.748513 [Byte1]: 56
1084 23:19:43.752804
1085 23:19:43.752887 Set Vref, RX VrefLevel [Byte0]: 57
1086 23:19:43.755856 [Byte1]: 57
1087 23:19:43.760111
1088 23:19:43.760193 Set Vref, RX VrefLevel [Byte0]: 58
1089 23:19:43.763435 [Byte1]: 58
1090 23:19:43.768219
1091 23:19:43.768301 Set Vref, RX VrefLevel [Byte0]: 59
1092 23:19:43.771163 [Byte1]: 59
1093 23:19:43.775510
1094 23:19:43.775593 Set Vref, RX VrefLevel [Byte0]: 60
1095 23:19:43.778674 [Byte1]: 60
1096 23:19:43.783190
1097 23:19:43.783272 Set Vref, RX VrefLevel [Byte0]: 61
1098 23:19:43.786579 [Byte1]: 61
1099 23:19:43.790530
1100 23:19:43.790613 Set Vref, RX VrefLevel [Byte0]: 62
1101 23:19:43.793953 [Byte1]: 62
1102 23:19:43.798374
1103 23:19:43.798482 Set Vref, RX VrefLevel [Byte0]: 63
1104 23:19:43.801321 [Byte1]: 63
1105 23:19:43.805925
1106 23:19:43.806008 Set Vref, RX VrefLevel [Byte0]: 64
1107 23:19:43.808990 [Byte1]: 64
1108 23:19:43.813661
1109 23:19:43.813745 Set Vref, RX VrefLevel [Byte0]: 65
1110 23:19:43.816822 [Byte1]: 65
1111 23:19:43.820973
1112 23:19:43.821056 Set Vref, RX VrefLevel [Byte0]: 66
1113 23:19:43.824300 [Byte1]: 66
1114 23:19:43.828598
1115 23:19:43.828702 Set Vref, RX VrefLevel [Byte0]: 67
1116 23:19:43.832249 [Byte1]: 67
1117 23:19:43.836520
1118 23:19:43.836620 Set Vref, RX VrefLevel [Byte0]: 68
1119 23:19:43.839828 [Byte1]: 68
1120 23:19:43.844104
1121 23:19:43.844187 Set Vref, RX VrefLevel [Byte0]: 69
1122 23:19:43.847014 [Byte1]: 69
1123 23:19:43.851435
1124 23:19:43.851536 Set Vref, RX VrefLevel [Byte0]: 70
1125 23:19:43.855177 [Byte1]: 70
1126 23:19:43.858998
1127 23:19:43.859081 Set Vref, RX VrefLevel [Byte0]: 71
1128 23:19:43.862242 [Byte1]: 71
1129 23:19:43.866505
1130 23:19:43.866590 Set Vref, RX VrefLevel [Byte0]: 72
1131 23:19:43.870174 [Byte1]: 72
1132 23:19:43.874492
1133 23:19:43.874600 Set Vref, RX VrefLevel [Byte0]: 73
1134 23:19:43.877583 [Byte1]: 73
1135 23:19:43.882000
1136 23:19:43.882083 Set Vref, RX VrefLevel [Byte0]: 74
1137 23:19:43.885288 [Byte1]: 74
1138 23:19:43.889443
1139 23:19:43.889528 Set Vref, RX VrefLevel [Byte0]: 75
1140 23:19:43.892850 [Byte1]: 75
1141 23:19:43.896906
1142 23:19:43.896989 Set Vref, RX VrefLevel [Byte0]: 76
1143 23:19:43.900573 [Byte1]: 76
1144 23:19:43.904549
1145 23:19:43.904632 Final RX Vref Byte 0 = 63 to rank0
1146 23:19:43.908061 Final RX Vref Byte 1 = 63 to rank0
1147 23:19:43.911186 Final RX Vref Byte 0 = 63 to rank1
1148 23:19:43.914773 Final RX Vref Byte 1 = 63 to rank1==
1149 23:19:43.918106 Dram Type= 6, Freq= 0, CH_0, rank 0
1150 23:19:43.924431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 23:19:43.924517 ==
1152 23:19:43.924586 DQS Delay:
1153 23:19:43.924670 DQS0 = 0, DQS1 = 0
1154 23:19:43.927898 DQM Delay:
1155 23:19:43.927981 DQM0 = 93, DQM1 = 82
1156 23:19:43.931645 DQ Delay:
1157 23:19:43.934934 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1158 23:19:43.938237 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1159 23:19:43.941273 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1160 23:19:43.944569 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1161 23:19:43.944675
1162 23:19:43.944743
1163 23:19:43.951337 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1164 23:19:43.954684 CH0 RK0: MR19=606, MR18=3D38
1165 23:19:43.961597 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1166 23:19:43.961682
1167 23:19:43.964775 ----->DramcWriteLeveling(PI) begin...
1168 23:19:43.964860 ==
1169 23:19:43.968171 Dram Type= 6, Freq= 0, CH_0, rank 1
1170 23:19:43.971574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1171 23:19:43.971680 ==
1172 23:19:43.974905 Write leveling (Byte 0): 31 => 31
1173 23:19:43.977919 Write leveling (Byte 1): 28 => 28
1174 23:19:43.981533 DramcWriteLeveling(PI) end<-----
1175 23:19:43.981617
1176 23:19:43.981722 ==
1177 23:19:43.984933 Dram Type= 6, Freq= 0, CH_0, rank 1
1178 23:19:43.987954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1179 23:19:43.988038 ==
1180 23:19:43.991234 [Gating] SW mode calibration
1181 23:19:43.998029 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1182 23:19:44.004571 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1183 23:19:44.008298 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1184 23:19:44.011481 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1185 23:19:44.018403 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1186 23:19:44.021337 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:19:44.025095 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:19:44.031839 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:19:44.034977 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:19:44.073625 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:19:44.073755 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 23:19:44.074014 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:19:44.074082 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 23:19:44.074144 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 23:19:44.074203 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 23:19:44.074447 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:19:44.075242 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 23:19:44.075326 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 23:19:44.077396 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 23:19:44.084504 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1201 23:19:44.087707 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 23:19:44.090609 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 23:19:44.097706 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 23:19:44.100869 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 23:19:44.104189 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 23:19:44.110836 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 23:19:44.114379 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 23:19:44.117734 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 23:19:44.120627 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
1210 23:19:44.127468 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1211 23:19:44.130857 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1212 23:19:44.134181 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1213 23:19:44.140705 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1214 23:19:44.144312 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1215 23:19:44.147328 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1216 23:19:44.154047 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1217 23:19:44.157471 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
1218 23:19:44.160750 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 23:19:44.167544 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:19:44.171135 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:19:44.174350 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:19:44.180897 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:19:44.184146 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:19:44.187999 0 11 4 | B1->B0 | 2727 3737 | 1 1 | (0 0) (0 0)
1225 23:19:44.194441 0 11 8 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
1226 23:19:44.197697 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1227 23:19:44.201202 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 23:19:44.204143 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 23:19:44.211226 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 23:19:44.215126 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 23:19:44.218621 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 23:19:44.222347 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1233 23:19:44.229733 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 23:19:44.232818 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 23:19:44.236328 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 23:19:44.240089 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 23:19:44.247163 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 23:19:44.250392 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 23:19:44.253657 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 23:19:44.257078 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 23:19:44.263821 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 23:19:44.267302 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 23:19:44.270314 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 23:19:44.277158 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 23:19:44.280926 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 23:19:44.284053 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 23:19:44.290621 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 23:19:44.293944 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1249 23:19:44.297619 Total UI for P1: 0, mck2ui 16
1250 23:19:44.300554 best dqsien dly found for B1: ( 0, 14, 2)
1251 23:19:44.303936 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1252 23:19:44.310536 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 23:19:44.310622 Total UI for P1: 0, mck2ui 16
1254 23:19:44.313818 best dqsien dly found for B0: ( 0, 14, 6)
1255 23:19:44.320570 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1256 23:19:44.324020 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1257 23:19:44.324106
1258 23:19:44.327224 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1259 23:19:44.330623 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1260 23:19:44.333620 [Gating] SW calibration Done
1261 23:19:44.333706 ==
1262 23:19:44.336792 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 23:19:44.340097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 23:19:44.340186 ==
1265 23:19:44.343836 RX Vref Scan: 0
1266 23:19:44.343931
1267 23:19:44.344018 RX Vref 0 -> 0, step: 1
1268 23:19:44.344099
1269 23:19:44.346964 RX Delay -130 -> 252, step: 16
1270 23:19:44.350833 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1271 23:19:44.354099 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1272 23:19:44.360598 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1273 23:19:44.364181 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1274 23:19:44.367244 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1275 23:19:44.370917 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1276 23:19:44.374068 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1277 23:19:44.380833 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1278 23:19:44.384094 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1279 23:19:44.387231 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1280 23:19:44.390627 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1281 23:19:44.394056 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1282 23:19:44.400778 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1283 23:19:44.403962 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1284 23:19:44.407333 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1285 23:19:44.410664 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1286 23:19:44.410750 ==
1287 23:19:44.413966 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 23:19:44.420609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 23:19:44.420739 ==
1290 23:19:44.420825 DQS Delay:
1291 23:19:44.424088 DQS0 = 0, DQS1 = 0
1292 23:19:44.424215 DQM Delay:
1293 23:19:44.424299 DQM0 = 91, DQM1 = 81
1294 23:19:44.427196 DQ Delay:
1295 23:19:44.430573 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1296 23:19:44.433837 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1297 23:19:44.437264 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =85
1298 23:19:44.440713 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1299 23:19:44.440798
1300 23:19:44.440883
1301 23:19:44.440963 ==
1302 23:19:44.443670 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 23:19:44.447169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 23:19:44.447256 ==
1305 23:19:44.447340
1306 23:19:44.447421
1307 23:19:44.450854 TX Vref Scan disable
1308 23:19:44.450939 == TX Byte 0 ==
1309 23:19:44.457601 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1310 23:19:44.460549 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1311 23:19:44.460636 == TX Byte 1 ==
1312 23:19:44.467262 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1313 23:19:44.470412 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1314 23:19:44.470513 ==
1315 23:19:44.473791 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 23:19:44.477088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 23:19:44.477172 ==
1318 23:19:44.491679 TX Vref=22, minBit 8, minWin=27, winSum=447
1319 23:19:44.494775 TX Vref=24, minBit 1, minWin=27, winSum=449
1320 23:19:44.498112 TX Vref=26, minBit 8, minWin=27, winSum=453
1321 23:19:44.501692 TX Vref=28, minBit 8, minWin=28, winSum=458
1322 23:19:44.505126 TX Vref=30, minBit 8, minWin=28, winSum=459
1323 23:19:44.508535 TX Vref=32, minBit 8, minWin=28, winSum=460
1324 23:19:44.515160 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 32
1325 23:19:44.515248
1326 23:19:44.518239 Final TX Range 1 Vref 32
1327 23:19:44.518323
1328 23:19:44.518389 ==
1329 23:19:44.521870 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 23:19:44.525215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 23:19:44.525303 ==
1332 23:19:44.525368
1333 23:19:44.525429
1334 23:19:44.528142 TX Vref Scan disable
1335 23:19:44.531662 == TX Byte 0 ==
1336 23:19:44.534951 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1337 23:19:44.538230 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1338 23:19:44.541513 == TX Byte 1 ==
1339 23:19:44.545317 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1340 23:19:44.548113 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1341 23:19:44.548194
1342 23:19:44.551582 [DATLAT]
1343 23:19:44.551666 Freq=800, CH0 RK1
1344 23:19:44.551732
1345 23:19:44.555126 DATLAT Default: 0xa
1346 23:19:44.555208 0, 0xFFFF, sum = 0
1347 23:19:44.558309 1, 0xFFFF, sum = 0
1348 23:19:44.558392 2, 0xFFFF, sum = 0
1349 23:19:44.561924 3, 0xFFFF, sum = 0
1350 23:19:44.562007 4, 0xFFFF, sum = 0
1351 23:19:44.564815 5, 0xFFFF, sum = 0
1352 23:19:44.564898 6, 0xFFFF, sum = 0
1353 23:19:44.568293 7, 0xFFFF, sum = 0
1354 23:19:44.571713 8, 0xFFFF, sum = 0
1355 23:19:44.571795 9, 0x0, sum = 1
1356 23:19:44.571861 10, 0x0, sum = 2
1357 23:19:44.574771 11, 0x0, sum = 3
1358 23:19:44.574854 12, 0x0, sum = 4
1359 23:19:44.578090 best_step = 10
1360 23:19:44.578170
1361 23:19:44.578234 ==
1362 23:19:44.581592 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 23:19:44.584739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 23:19:44.584858 ==
1365 23:19:44.588041 RX Vref Scan: 0
1366 23:19:44.588122
1367 23:19:44.588185 RX Vref 0 -> 0, step: 1
1368 23:19:44.588246
1369 23:19:44.591553 RX Delay -95 -> 252, step: 8
1370 23:19:44.598324 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1371 23:19:44.601208 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1372 23:19:44.604546 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1373 23:19:44.607832 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1374 23:19:44.611280 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1375 23:19:44.618185 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1376 23:19:44.621423 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1377 23:19:44.624392 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1378 23:19:44.627868 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1379 23:19:44.631147 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1380 23:19:44.637843 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1381 23:19:44.641381 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1382 23:19:44.644791 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1383 23:19:44.648238 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1384 23:19:44.651365 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1385 23:19:44.658036 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1386 23:19:44.658120 ==
1387 23:19:44.661500 Dram Type= 6, Freq= 0, CH_0, rank 1
1388 23:19:44.664825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 23:19:44.664910 ==
1390 23:19:44.664977 DQS Delay:
1391 23:19:44.667855 DQS0 = 0, DQS1 = 0
1392 23:19:44.667967 DQM Delay:
1393 23:19:44.671066 DQM0 = 91, DQM1 = 81
1394 23:19:44.671165 DQ Delay:
1395 23:19:44.674595 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =84
1396 23:19:44.677856 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1397 23:19:44.681460 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1398 23:19:44.684729 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1399 23:19:44.684807
1400 23:19:44.684871
1401 23:19:44.694608 [DQSOSCAuto] RK1, (LSB)MR18= 0x451f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1402 23:19:44.694711 CH0 RK1: MR19=606, MR18=451F
1403 23:19:44.701504 CH0_RK1: MR19=0x606, MR18=0x451F, DQSOSC=392, MR23=63, INC=96, DEC=64
1404 23:19:44.704785 [RxdqsGatingPostProcess] freq 800
1405 23:19:44.711197 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1406 23:19:44.714743 Pre-setting of DQS Precalculation
1407 23:19:44.718077 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1408 23:19:44.718150 ==
1409 23:19:44.721584 Dram Type= 6, Freq= 0, CH_1, rank 0
1410 23:19:44.724764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 23:19:44.728037 ==
1412 23:19:44.731272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 23:19:44.737949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 23:19:44.746457 [CA 0] Center 36 (6~67) winsize 62
1415 23:19:44.749877 [CA 1] Center 36 (6~67) winsize 62
1416 23:19:44.753377 [CA 2] Center 34 (4~65) winsize 62
1417 23:19:44.756959 [CA 3] Center 34 (4~65) winsize 62
1418 23:19:44.760338 [CA 4] Center 34 (4~65) winsize 62
1419 23:19:44.763642 [CA 5] Center 34 (3~65) winsize 63
1420 23:19:44.763725
1421 23:19:44.766668 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1422 23:19:44.766752
1423 23:19:44.770109 [CATrainingPosCal] consider 1 rank data
1424 23:19:44.773386 u2DelayCellTimex100 = 270/100 ps
1425 23:19:44.776588 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 23:19:44.779822 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 23:19:44.786544 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 23:19:44.789818 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 23:19:44.793242 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 23:19:44.797140 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1431 23:19:44.797223
1432 23:19:44.800088 CA PerBit enable=1, Macro0, CA PI delay=34
1433 23:19:44.800196
1434 23:19:44.803760 [CBTSetCACLKResult] CA Dly = 34
1435 23:19:44.803869 CS Dly: 5 (0~36)
1436 23:19:44.806806 ==
1437 23:19:44.806890 Dram Type= 6, Freq= 0, CH_1, rank 1
1438 23:19:44.813068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 23:19:44.813152 ==
1440 23:19:44.816511 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1441 23:19:44.823237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1442 23:19:44.833092 [CA 0] Center 36 (6~67) winsize 62
1443 23:19:44.835866 [CA 1] Center 37 (6~68) winsize 63
1444 23:19:44.839694 [CA 2] Center 35 (5~66) winsize 62
1445 23:19:44.842485 [CA 3] Center 34 (4~65) winsize 62
1446 23:19:44.845962 [CA 4] Center 34 (4~65) winsize 62
1447 23:19:44.849717 [CA 5] Center 34 (4~65) winsize 62
1448 23:19:44.849800
1449 23:19:44.852610 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1450 23:19:44.852709
1451 23:19:44.856274 [CATrainingPosCal] consider 2 rank data
1452 23:19:44.859483 u2DelayCellTimex100 = 270/100 ps
1453 23:19:44.862745 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1454 23:19:44.866253 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1455 23:19:44.872597 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1456 23:19:44.875911 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1457 23:19:44.879995 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1458 23:19:44.883666 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 23:19:44.883775
1460 23:19:44.887439 CA PerBit enable=1, Macro0, CA PI delay=34
1461 23:19:44.887569
1462 23:19:44.890766 [CBTSetCACLKResult] CA Dly = 34
1463 23:19:44.890875 CS Dly: 6 (0~38)
1464 23:19:44.890970
1465 23:19:44.895068 ----->DramcWriteLeveling(PI) begin...
1466 23:19:44.895180 ==
1467 23:19:44.898166 Dram Type= 6, Freq= 0, CH_1, rank 0
1468 23:19:44.902003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 23:19:44.902113 ==
1470 23:19:44.905913 Write leveling (Byte 0): 27 => 27
1471 23:19:44.909515 Write leveling (Byte 1): 27 => 27
1472 23:19:44.913394 DramcWriteLeveling(PI) end<-----
1473 23:19:44.913478
1474 23:19:44.913545 ==
1475 23:19:44.916460 Dram Type= 6, Freq= 0, CH_1, rank 0
1476 23:19:44.919227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 23:19:44.919311 ==
1478 23:19:44.922903 [Gating] SW mode calibration
1479 23:19:44.929329 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1480 23:19:44.932699 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1481 23:19:44.939669 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1482 23:19:44.942882 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1483 23:19:44.946315 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1484 23:19:44.953175 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:19:44.956627 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:19:44.959957 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:19:44.966762 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:19:44.969712 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:19:44.972932 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 23:19:44.979829 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:19:44.982938 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 23:19:44.986350 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 23:19:44.989899 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 23:19:44.996321 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 23:19:44.999669 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:19:45.003244 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 23:19:45.009504 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1498 23:19:45.012873 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1499 23:19:45.016199 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 23:19:45.022929 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 23:19:45.026465 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 23:19:45.029481 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 23:19:45.036170 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 23:19:45.039610 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 23:19:45.042955 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 23:19:45.049802 0 9 4 | B1->B0 | 2323 2928 | 1 1 | (1 1) (0 0)
1507 23:19:45.052682 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1508 23:19:45.055978 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1509 23:19:45.063068 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1510 23:19:45.066324 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 23:19:45.069817 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1512 23:19:45.076107 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1513 23:19:45.079899 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 23:19:45.082816 0 10 4 | B1->B0 | 3030 2d2d | 1 0 | (0 0) (0 0)
1515 23:19:45.089704 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1516 23:19:45.092903 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 23:19:45.096158 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:19:45.099571 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:19:45.106500 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:19:45.109741 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:19:45.112994 0 11 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1522 23:19:45.119680 0 11 4 | B1->B0 | 3030 3939 | 1 0 | (0 0) (0 0)
1523 23:19:45.122870 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1524 23:19:45.126556 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 23:19:45.133216 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 23:19:45.136577 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 23:19:45.139704 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 23:19:45.146855 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 23:19:45.149691 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 23:19:45.153152 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1531 23:19:45.159590 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1532 23:19:45.162957 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 23:19:45.166749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 23:19:45.172922 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 23:19:45.176289 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 23:19:45.180012 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 23:19:45.183071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 23:19:45.189659 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 23:19:45.193089 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 23:19:45.196288 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 23:19:45.203367 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 23:19:45.206756 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 23:19:45.210074 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 23:19:45.216381 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 23:19:45.220042 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1546 23:19:45.223411 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1547 23:19:45.229790 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 23:19:45.229875 Total UI for P1: 0, mck2ui 16
1549 23:19:45.236315 best dqsien dly found for B0: ( 0, 14, 2)
1550 23:19:45.236400 Total UI for P1: 0, mck2ui 16
1551 23:19:45.242919 best dqsien dly found for B1: ( 0, 14, 4)
1552 23:19:45.246298 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1553 23:19:45.249929 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1554 23:19:45.250013
1555 23:19:45.253400 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1556 23:19:45.256174 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1557 23:19:45.259628 [Gating] SW calibration Done
1558 23:19:45.259711 ==
1559 23:19:45.262985 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 23:19:45.266602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 23:19:45.266685 ==
1562 23:19:45.269578 RX Vref Scan: 0
1563 23:19:45.269661
1564 23:19:45.269727 RX Vref 0 -> 0, step: 1
1565 23:19:45.269790
1566 23:19:45.272953 RX Delay -130 -> 252, step: 16
1567 23:19:45.276192 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1568 23:19:45.283186 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1569 23:19:45.286422 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1570 23:19:45.289752 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1571 23:19:45.293158 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1572 23:19:45.296570 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1573 23:19:45.300136 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1574 23:19:45.306679 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1575 23:19:45.309760 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1576 23:19:45.313245 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1577 23:19:45.316564 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1578 23:19:45.319888 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1579 23:19:45.326736 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1580 23:19:45.329748 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1581 23:19:45.333315 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1582 23:19:45.336435 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1583 23:19:45.336521 ==
1584 23:19:45.339707 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 23:19:45.346504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 23:19:45.346595 ==
1587 23:19:45.346664 DQS Delay:
1588 23:19:45.349838 DQS0 = 0, DQS1 = 0
1589 23:19:45.349923 DQM Delay:
1590 23:19:45.349990 DQM0 = 91, DQM1 = 83
1591 23:19:45.353027 DQ Delay:
1592 23:19:45.356553 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1593 23:19:45.359916 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =93
1594 23:19:45.363244 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1595 23:19:45.366552 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1596 23:19:45.366638
1597 23:19:45.366705
1598 23:19:45.366767 ==
1599 23:19:45.370030 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 23:19:45.373035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 23:19:45.373143 ==
1602 23:19:45.373243
1603 23:19:45.373306
1604 23:19:45.376741 TX Vref Scan disable
1605 23:19:45.376825 == TX Byte 0 ==
1606 23:19:45.382913 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1607 23:19:45.386727 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1608 23:19:45.386816 == TX Byte 1 ==
1609 23:19:45.393193 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1610 23:19:45.396567 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1611 23:19:45.396709 ==
1612 23:19:45.399892 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 23:19:45.403154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 23:19:45.403241 ==
1615 23:19:45.417465 TX Vref=22, minBit 10, minWin=27, winSum=449
1616 23:19:45.420828 TX Vref=24, minBit 10, minWin=27, winSum=452
1617 23:19:45.424132 TX Vref=26, minBit 15, minWin=27, winSum=457
1618 23:19:45.427104 TX Vref=28, minBit 9, minWin=28, winSum=460
1619 23:19:45.430367 TX Vref=30, minBit 9, minWin=28, winSum=461
1620 23:19:45.437227 TX Vref=32, minBit 9, minWin=27, winSum=457
1621 23:19:45.441010 [TxChooseVref] Worse bit 9, Min win 28, Win sum 461, Final Vref 30
1622 23:19:45.441095
1623 23:19:45.444110 Final TX Range 1 Vref 30
1624 23:19:45.444248
1625 23:19:45.444362 ==
1626 23:19:45.447085 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 23:19:45.450785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 23:19:45.450896 ==
1629 23:19:45.450991
1630 23:19:45.453852
1631 23:19:45.453936 TX Vref Scan disable
1632 23:19:45.457330 == TX Byte 0 ==
1633 23:19:45.460591 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1634 23:19:45.464167 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1635 23:19:45.467566 == TX Byte 1 ==
1636 23:19:45.471217 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1637 23:19:45.474447 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1638 23:19:45.474533
1639 23:19:45.477674 [DATLAT]
1640 23:19:45.477772 Freq=800, CH1 RK0
1641 23:19:45.477840
1642 23:19:45.481324 DATLAT Default: 0xa
1643 23:19:45.481427 0, 0xFFFF, sum = 0
1644 23:19:45.484535 1, 0xFFFF, sum = 0
1645 23:19:45.484622 2, 0xFFFF, sum = 0
1646 23:19:45.487874 3, 0xFFFF, sum = 0
1647 23:19:45.487963 4, 0xFFFF, sum = 0
1648 23:19:45.491029 5, 0xFFFF, sum = 0
1649 23:19:45.491116 6, 0xFFFF, sum = 0
1650 23:19:45.494264 7, 0xFFFF, sum = 0
1651 23:19:45.494385 8, 0xFFFF, sum = 0
1652 23:19:45.497899 9, 0x0, sum = 1
1653 23:19:45.498019 10, 0x0, sum = 2
1654 23:19:45.501164 11, 0x0, sum = 3
1655 23:19:45.501250 12, 0x0, sum = 4
1656 23:19:45.504225 best_step = 10
1657 23:19:45.504324
1658 23:19:45.504406 ==
1659 23:19:45.507528 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 23:19:45.510942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 23:19:45.511064 ==
1662 23:19:45.514463 RX Vref Scan: 1
1663 23:19:45.514548
1664 23:19:45.514616 Set Vref Range= 32 -> 127
1665 23:19:45.514694
1666 23:19:45.517729 RX Vref 32 -> 127, step: 1
1667 23:19:45.517813
1668 23:19:45.521036 RX Delay -95 -> 252, step: 8
1669 23:19:45.521120
1670 23:19:45.524392 Set Vref, RX VrefLevel [Byte0]: 32
1671 23:19:45.527779 [Byte1]: 32
1672 23:19:45.527864
1673 23:19:45.531224 Set Vref, RX VrefLevel [Byte0]: 33
1674 23:19:45.534538 [Byte1]: 33
1675 23:19:45.534623
1676 23:19:45.537919 Set Vref, RX VrefLevel [Byte0]: 34
1677 23:19:45.541313 [Byte1]: 34
1678 23:19:45.545140
1679 23:19:45.545224 Set Vref, RX VrefLevel [Byte0]: 35
1680 23:19:45.548411 [Byte1]: 35
1681 23:19:45.552524
1682 23:19:45.552656 Set Vref, RX VrefLevel [Byte0]: 36
1683 23:19:45.556334 [Byte1]: 36
1684 23:19:45.560394
1685 23:19:45.560533 Set Vref, RX VrefLevel [Byte0]: 37
1686 23:19:45.563792 [Byte1]: 37
1687 23:19:45.567854
1688 23:19:45.567955 Set Vref, RX VrefLevel [Byte0]: 38
1689 23:19:45.571534 [Byte1]: 38
1690 23:19:45.575446
1691 23:19:45.575531 Set Vref, RX VrefLevel [Byte0]: 39
1692 23:19:45.578811 [Byte1]: 39
1693 23:19:45.583060
1694 23:19:45.583143 Set Vref, RX VrefLevel [Byte0]: 40
1695 23:19:45.586233 [Byte1]: 40
1696 23:19:45.590712
1697 23:19:45.590824 Set Vref, RX VrefLevel [Byte0]: 41
1698 23:19:45.593997 [Byte1]: 41
1699 23:19:45.598123
1700 23:19:45.598239 Set Vref, RX VrefLevel [Byte0]: 42
1701 23:19:45.601818 [Byte1]: 42
1702 23:19:45.606237
1703 23:19:45.606349 Set Vref, RX VrefLevel [Byte0]: 43
1704 23:19:45.609446 [Byte1]: 43
1705 23:19:45.613599
1706 23:19:45.613705 Set Vref, RX VrefLevel [Byte0]: 44
1707 23:19:45.617044 [Byte1]: 44
1708 23:19:45.621225
1709 23:19:45.621340 Set Vref, RX VrefLevel [Byte0]: 45
1710 23:19:45.624745 [Byte1]: 45
1711 23:19:45.628877
1712 23:19:45.628963 Set Vref, RX VrefLevel [Byte0]: 46
1713 23:19:45.631888 [Byte1]: 46
1714 23:19:45.636250
1715 23:19:45.636358 Set Vref, RX VrefLevel [Byte0]: 47
1716 23:19:45.639576 [Byte1]: 47
1717 23:19:45.644302
1718 23:19:45.644400 Set Vref, RX VrefLevel [Byte0]: 48
1719 23:19:45.647203 [Byte1]: 48
1720 23:19:45.651368
1721 23:19:45.651452 Set Vref, RX VrefLevel [Byte0]: 49
1722 23:19:45.654723 [Byte1]: 49
1723 23:19:45.659164
1724 23:19:45.659263 Set Vref, RX VrefLevel [Byte0]: 50
1725 23:19:45.662254 [Byte1]: 50
1726 23:19:45.666588
1727 23:19:45.666687 Set Vref, RX VrefLevel [Byte0]: 51
1728 23:19:45.670005 [Byte1]: 51
1729 23:19:45.674545
1730 23:19:45.674652 Set Vref, RX VrefLevel [Byte0]: 52
1731 23:19:45.677560 [Byte1]: 52
1732 23:19:45.681882
1733 23:19:45.681966 Set Vref, RX VrefLevel [Byte0]: 53
1734 23:19:45.685264 [Byte1]: 53
1735 23:19:45.689398
1736 23:19:45.689549 Set Vref, RX VrefLevel [Byte0]: 54
1737 23:19:45.692903 [Byte1]: 54
1738 23:19:45.697055
1739 23:19:45.697139 Set Vref, RX VrefLevel [Byte0]: 55
1740 23:19:45.700273 [Byte1]: 55
1741 23:19:45.704559
1742 23:19:45.704643 Set Vref, RX VrefLevel [Byte0]: 56
1743 23:19:45.707848 [Byte1]: 56
1744 23:19:45.712227
1745 23:19:45.712311 Set Vref, RX VrefLevel [Byte0]: 57
1746 23:19:45.715698 [Byte1]: 57
1747 23:19:45.719890
1748 23:19:45.719973 Set Vref, RX VrefLevel [Byte0]: 58
1749 23:19:45.723213 [Byte1]: 58
1750 23:19:45.727408
1751 23:19:45.727492 Set Vref, RX VrefLevel [Byte0]: 59
1752 23:19:45.731243 [Byte1]: 59
1753 23:19:45.735005
1754 23:19:45.735100 Set Vref, RX VrefLevel [Byte0]: 60
1755 23:19:45.738388 [Byte1]: 60
1756 23:19:45.742881
1757 23:19:45.742964 Set Vref, RX VrefLevel [Byte0]: 61
1758 23:19:45.746059 [Byte1]: 61
1759 23:19:45.750521
1760 23:19:45.750603 Set Vref, RX VrefLevel [Byte0]: 62
1761 23:19:45.753366 [Byte1]: 62
1762 23:19:45.758088
1763 23:19:45.758171 Set Vref, RX VrefLevel [Byte0]: 63
1764 23:19:45.761242 [Byte1]: 63
1765 23:19:45.765495
1766 23:19:45.765579 Set Vref, RX VrefLevel [Byte0]: 64
1767 23:19:45.768996 [Byte1]: 64
1768 23:19:45.773004
1769 23:19:45.773090 Set Vref, RX VrefLevel [Byte0]: 65
1770 23:19:45.776084 [Byte1]: 65
1771 23:19:45.780911
1772 23:19:45.781027 Set Vref, RX VrefLevel [Byte0]: 66
1773 23:19:45.783874 [Byte1]: 66
1774 23:19:45.788410
1775 23:19:45.788495 Set Vref, RX VrefLevel [Byte0]: 67
1776 23:19:45.794870 [Byte1]: 67
1777 23:19:45.794954
1778 23:19:45.797955 Set Vref, RX VrefLevel [Byte0]: 68
1779 23:19:45.801329 [Byte1]: 68
1780 23:19:45.801412
1781 23:19:45.804954 Set Vref, RX VrefLevel [Byte0]: 69
1782 23:19:45.807984 [Byte1]: 69
1783 23:19:45.808068
1784 23:19:45.811587 Set Vref, RX VrefLevel [Byte0]: 70
1785 23:19:45.814811 [Byte1]: 70
1786 23:19:45.818675
1787 23:19:45.818757 Set Vref, RX VrefLevel [Byte0]: 71
1788 23:19:45.821917 [Byte1]: 71
1789 23:19:45.826168
1790 23:19:45.826255 Set Vref, RX VrefLevel [Byte0]: 72
1791 23:19:45.829452 [Byte1]: 72
1792 23:19:45.833661
1793 23:19:45.833774 Set Vref, RX VrefLevel [Byte0]: 73
1794 23:19:45.837440 [Byte1]: 73
1795 23:19:45.841816
1796 23:19:45.841924 Set Vref, RX VrefLevel [Byte0]: 74
1797 23:19:45.845028 [Byte1]: 74
1798 23:19:45.849379
1799 23:19:45.849469 Set Vref, RX VrefLevel [Byte0]: 75
1800 23:19:45.852315 [Byte1]: 75
1801 23:19:45.856789
1802 23:19:45.856895 Set Vref, RX VrefLevel [Byte0]: 76
1803 23:19:45.859950 [Byte1]: 76
1804 23:19:45.864328
1805 23:19:45.864442 Set Vref, RX VrefLevel [Byte0]: 77
1806 23:19:45.867523 [Byte1]: 77
1807 23:19:45.871892
1808 23:19:45.871978 Set Vref, RX VrefLevel [Byte0]: 78
1809 23:19:45.875059 [Byte1]: 78
1810 23:19:45.879497
1811 23:19:45.879580 Set Vref, RX VrefLevel [Byte0]: 79
1812 23:19:45.883215 [Byte1]: 79
1813 23:19:45.887192
1814 23:19:45.887276 Set Vref, RX VrefLevel [Byte0]: 80
1815 23:19:45.890306 [Byte1]: 80
1816 23:19:45.894672
1817 23:19:45.894779 Final RX Vref Byte 0 = 51 to rank0
1818 23:19:45.898071 Final RX Vref Byte 1 = 64 to rank0
1819 23:19:45.901552 Final RX Vref Byte 0 = 51 to rank1
1820 23:19:45.904640 Final RX Vref Byte 1 = 64 to rank1==
1821 23:19:45.907887 Dram Type= 6, Freq= 0, CH_1, rank 0
1822 23:19:45.915262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1823 23:19:45.915362 ==
1824 23:19:45.915467 DQS Delay:
1825 23:19:45.915566 DQS0 = 0, DQS1 = 0
1826 23:19:45.917893 DQM Delay:
1827 23:19:45.917991 DQM0 = 92, DQM1 = 83
1828 23:19:45.921819 DQ Delay:
1829 23:19:45.921917 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1830 23:19:45.925059 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1831 23:19:45.928205 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1832 23:19:45.935061 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1833 23:19:45.935146
1834 23:19:45.935213
1835 23:19:45.941430 [DQSOSCAuto] RK0, (LSB)MR18= 0x314e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1836 23:19:45.944864 CH1 RK0: MR19=606, MR18=314E
1837 23:19:45.951920 CH1_RK0: MR19=0x606, MR18=0x314E, DQSOSC=390, MR23=63, INC=97, DEC=64
1838 23:19:45.952005
1839 23:19:45.955312 ----->DramcWriteLeveling(PI) begin...
1840 23:19:45.955398 ==
1841 23:19:45.958381 Dram Type= 6, Freq= 0, CH_1, rank 1
1842 23:19:45.961898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1843 23:19:45.961983 ==
1844 23:19:45.965240 Write leveling (Byte 0): 28 => 28
1845 23:19:45.968601 Write leveling (Byte 1): 29 => 29
1846 23:19:45.971891 DramcWriteLeveling(PI) end<-----
1847 23:19:45.971975
1848 23:19:45.972041 ==
1849 23:19:45.975405 Dram Type= 6, Freq= 0, CH_1, rank 1
1850 23:19:45.978400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 23:19:45.978485 ==
1852 23:19:45.981813 [Gating] SW mode calibration
1853 23:19:45.988662 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1854 23:19:45.995231 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1855 23:19:45.998641 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1856 23:19:46.001919 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1857 23:19:46.008461 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1858 23:19:46.011860 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 23:19:46.015383 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 23:19:46.018485 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 23:19:46.025336 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 23:19:46.028700 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 23:19:46.032037 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:19:46.038721 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:19:46.041912 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:19:46.045407 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:19:46.052080 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:19:46.055349 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:19:46.058764 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:19:46.065636 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:19:46.069056 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:19:46.071907 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1873 23:19:46.079005 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1874 23:19:46.081952 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:19:46.085351 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:19:46.091777 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:19:46.095510 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:19:46.098582 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:19:46.105231 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:19:46.108899 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:19:46.112349 0 9 8 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
1882 23:19:46.115663 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 23:19:46.122075 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 23:19:46.125149 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 23:19:46.128439 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 23:19:46.135397 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 23:19:46.138669 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 23:19:46.141999 0 10 4 | B1->B0 | 3030 3030 | 0 0 | (1 1) (0 1)
1889 23:19:46.148596 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
1890 23:19:46.151989 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:19:46.155265 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:19:46.161944 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 23:19:46.165219 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:19:46.168796 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:19:46.175587 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:19:46.178773 0 11 4 | B1->B0 | 3535 3434 | 1 0 | (0 0) (0 0)
1897 23:19:46.182177 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1898 23:19:46.188840 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 23:19:46.192334 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 23:19:46.195800 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 23:19:46.198754 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 23:19:46.205400 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 23:19:46.208576 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 23:19:46.212162 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1905 23:19:46.218845 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 23:19:46.222196 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 23:19:46.225213 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 23:19:46.232263 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 23:19:46.235520 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 23:19:46.238825 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 23:19:46.245280 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 23:19:46.248663 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 23:19:46.252205 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 23:19:46.259084 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 23:19:46.261962 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 23:19:46.265275 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 23:19:46.272182 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:19:46.275532 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:19:46.278910 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:19:46.282207 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1921 23:19:46.288795 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 23:19:46.292159 Total UI for P1: 0, mck2ui 16
1923 23:19:46.295728 best dqsien dly found for B0: ( 0, 14, 6)
1924 23:19:46.299157 Total UI for P1: 0, mck2ui 16
1925 23:19:46.302177 best dqsien dly found for B1: ( 0, 14, 4)
1926 23:19:46.305497 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1927 23:19:46.309257 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1928 23:19:46.309341
1929 23:19:46.312591 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1930 23:19:46.315825 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1931 23:19:46.319162 [Gating] SW calibration Done
1932 23:19:46.319247 ==
1933 23:19:46.322530 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 23:19:46.325924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 23:19:46.326009 ==
1936 23:19:46.329097 RX Vref Scan: 0
1937 23:19:46.329181
1938 23:19:46.329247 RX Vref 0 -> 0, step: 1
1939 23:19:46.329308
1940 23:19:46.332390 RX Delay -130 -> 252, step: 16
1941 23:19:46.335596 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1942 23:19:46.342429 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1943 23:19:46.345983 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1944 23:19:46.349001 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1945 23:19:46.352313 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1946 23:19:46.356171 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1947 23:19:46.362286 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1948 23:19:46.365758 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1949 23:19:46.369209 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1950 23:19:46.372512 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1951 23:19:46.375795 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1952 23:19:46.382700 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1953 23:19:46.386013 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1954 23:19:46.389185 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1955 23:19:46.392685 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1956 23:19:46.395894 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1957 23:19:46.395978 ==
1958 23:19:46.399144 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 23:19:46.405904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 23:19:46.405989 ==
1961 23:19:46.406055 DQS Delay:
1962 23:19:46.409353 DQS0 = 0, DQS1 = 0
1963 23:19:46.409437 DQM Delay:
1964 23:19:46.409507 DQM0 = 89, DQM1 = 83
1965 23:19:46.412594 DQ Delay:
1966 23:19:46.416192 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1967 23:19:46.419518 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1968 23:19:46.422849 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1969 23:19:46.426205 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1970 23:19:46.426288
1971 23:19:46.426355
1972 23:19:46.426416 ==
1973 23:19:46.429283 Dram Type= 6, Freq= 0, CH_1, rank 1
1974 23:19:46.432607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1975 23:19:46.432699 ==
1976 23:19:46.432767
1977 23:19:46.432828
1978 23:19:46.436299 TX Vref Scan disable
1979 23:19:46.436382 == TX Byte 0 ==
1980 23:19:46.442898 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1981 23:19:46.446174 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1982 23:19:46.446258 == TX Byte 1 ==
1983 23:19:46.452604 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1984 23:19:46.456069 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1985 23:19:46.456153 ==
1986 23:19:46.459360 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 23:19:46.462643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 23:19:46.462728 ==
1989 23:19:46.476594 TX Vref=22, minBit 13, minWin=27, winSum=450
1990 23:19:46.479867 TX Vref=24, minBit 13, minWin=27, winSum=453
1991 23:19:46.483273 TX Vref=26, minBit 8, minWin=28, winSum=458
1992 23:19:46.486200 TX Vref=28, minBit 8, minWin=28, winSum=457
1993 23:19:46.489554 TX Vref=30, minBit 8, minWin=28, winSum=459
1994 23:19:46.496402 TX Vref=32, minBit 8, minWin=28, winSum=457
1995 23:19:46.499658 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1996 23:19:46.499743
1997 23:19:46.503282 Final TX Range 1 Vref 30
1998 23:19:46.503366
1999 23:19:46.503433 ==
2000 23:19:46.506201 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 23:19:46.509577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 23:19:46.509662 ==
2003 23:19:46.512944
2004 23:19:46.513029
2005 23:19:46.513096 TX Vref Scan disable
2006 23:19:46.516316 == TX Byte 0 ==
2007 23:19:46.519772 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2008 23:19:46.523214 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2009 23:19:46.526248 == TX Byte 1 ==
2010 23:19:46.529634 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2011 23:19:46.533407 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2012 23:19:46.536789
2013 23:19:46.536873 [DATLAT]
2014 23:19:46.536940 Freq=800, CH1 RK1
2015 23:19:46.537005
2016 23:19:46.539924 DATLAT Default: 0xa
2017 23:19:46.540008 0, 0xFFFF, sum = 0
2018 23:19:46.543180 1, 0xFFFF, sum = 0
2019 23:19:46.543266 2, 0xFFFF, sum = 0
2020 23:19:46.546706 3, 0xFFFF, sum = 0
2021 23:19:46.546791 4, 0xFFFF, sum = 0
2022 23:19:46.549738 5, 0xFFFF, sum = 0
2023 23:19:46.549824 6, 0xFFFF, sum = 0
2024 23:19:46.553129 7, 0xFFFF, sum = 0
2025 23:19:46.556550 8, 0xFFFF, sum = 0
2026 23:19:46.556636 9, 0x0, sum = 1
2027 23:19:46.556745 10, 0x0, sum = 2
2028 23:19:46.560254 11, 0x0, sum = 3
2029 23:19:46.560339 12, 0x0, sum = 4
2030 23:19:46.563180 best_step = 10
2031 23:19:46.563264
2032 23:19:46.563331 ==
2033 23:19:46.566656 Dram Type= 6, Freq= 0, CH_1, rank 1
2034 23:19:46.569800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2035 23:19:46.569885 ==
2036 23:19:46.573202 RX Vref Scan: 0
2037 23:19:46.573286
2038 23:19:46.573353 RX Vref 0 -> 0, step: 1
2039 23:19:46.573418
2040 23:19:46.576595 RX Delay -79 -> 252, step: 8
2041 23:19:46.583305 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2042 23:19:46.586726 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2043 23:19:46.590285 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2044 23:19:46.593488 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2045 23:19:46.596613 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2046 23:19:46.600283 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2047 23:19:46.606922 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2048 23:19:46.610178 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2049 23:19:46.613545 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2050 23:19:46.616621 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2051 23:19:46.619981 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2052 23:19:46.626660 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2053 23:19:46.630115 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2054 23:19:46.633534 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2055 23:19:46.636654 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2056 23:19:46.639969 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2057 23:19:46.643240 ==
2058 23:19:46.647066 Dram Type= 6, Freq= 0, CH_1, rank 1
2059 23:19:46.650518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2060 23:19:46.650603 ==
2061 23:19:46.650671 DQS Delay:
2062 23:19:46.653373 DQS0 = 0, DQS1 = 0
2063 23:19:46.653457 DQM Delay:
2064 23:19:46.656599 DQM0 = 90, DQM1 = 83
2065 23:19:46.656735 DQ Delay:
2066 23:19:46.660176 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2067 23:19:46.663874 DQ4 =92, DQ5 =104, DQ6 =96, DQ7 =88
2068 23:19:46.666746 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2069 23:19:46.670369 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2070 23:19:46.670453
2071 23:19:46.670519
2072 23:19:46.676673 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
2073 23:19:46.680075 CH1 RK1: MR19=606, MR18=3B0F
2074 23:19:46.686949 CH1_RK1: MR19=0x606, MR18=0x3B0F, DQSOSC=394, MR23=63, INC=95, DEC=63
2075 23:19:46.690014 [RxdqsGatingPostProcess] freq 800
2076 23:19:46.693511 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2077 23:19:46.696654 Pre-setting of DQS Precalculation
2078 23:19:46.703282 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2079 23:19:46.710090 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2080 23:19:46.717226 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2081 23:19:46.717309
2082 23:19:46.717375
2083 23:19:46.719844 [Calibration Summary] 1600 Mbps
2084 23:19:46.723298 CH 0, Rank 0
2085 23:19:46.723381 SW Impedance : PASS
2086 23:19:46.726615 DUTY Scan : NO K
2087 23:19:46.726698 ZQ Calibration : PASS
2088 23:19:46.729977 Jitter Meter : NO K
2089 23:19:46.733395 CBT Training : PASS
2090 23:19:46.733478 Write leveling : PASS
2091 23:19:46.736611 RX DQS gating : PASS
2092 23:19:46.739894 RX DQ/DQS(RDDQC) : PASS
2093 23:19:46.739976 TX DQ/DQS : PASS
2094 23:19:46.743171 RX DATLAT : PASS
2095 23:19:46.746707 RX DQ/DQS(Engine): PASS
2096 23:19:46.746790 TX OE : NO K
2097 23:19:46.750447 All Pass.
2098 23:19:46.750529
2099 23:19:46.750595 CH 0, Rank 1
2100 23:19:46.753534 SW Impedance : PASS
2101 23:19:46.753616 DUTY Scan : NO K
2102 23:19:46.756597 ZQ Calibration : PASS
2103 23:19:46.760016 Jitter Meter : NO K
2104 23:19:46.760099 CBT Training : PASS
2105 23:19:46.763334 Write leveling : PASS
2106 23:19:46.763450 RX DQS gating : PASS
2107 23:19:46.766719 RX DQ/DQS(RDDQC) : PASS
2108 23:19:46.770417 TX DQ/DQS : PASS
2109 23:19:46.770500 RX DATLAT : PASS
2110 23:19:46.773532 RX DQ/DQS(Engine): PASS
2111 23:19:46.776913 TX OE : NO K
2112 23:19:46.777019 All Pass.
2113 23:19:46.777090
2114 23:19:46.777151 CH 1, Rank 0
2115 23:19:46.780157 SW Impedance : PASS
2116 23:19:46.783456 DUTY Scan : NO K
2117 23:19:46.783538 ZQ Calibration : PASS
2118 23:19:46.786795 Jitter Meter : NO K
2119 23:19:46.789929 CBT Training : PASS
2120 23:19:46.790012 Write leveling : PASS
2121 23:19:46.793277 RX DQS gating : PASS
2122 23:19:46.796676 RX DQ/DQS(RDDQC) : PASS
2123 23:19:46.796773 TX DQ/DQS : PASS
2124 23:19:46.800145 RX DATLAT : PASS
2125 23:19:46.803359 RX DQ/DQS(Engine): PASS
2126 23:19:46.803443 TX OE : NO K
2127 23:19:46.803510 All Pass.
2128 23:19:46.803575
2129 23:19:46.807162 CH 1, Rank 1
2130 23:19:46.807246 SW Impedance : PASS
2131 23:19:46.810174 DUTY Scan : NO K
2132 23:19:46.813425 ZQ Calibration : PASS
2133 23:19:46.813508 Jitter Meter : NO K
2134 23:19:46.816815 CBT Training : PASS
2135 23:19:46.820225 Write leveling : PASS
2136 23:19:46.820308 RX DQS gating : PASS
2137 23:19:46.824101 RX DQ/DQS(RDDQC) : PASS
2138 23:19:46.826933 TX DQ/DQS : PASS
2139 23:19:46.827016 RX DATLAT : PASS
2140 23:19:46.830507 RX DQ/DQS(Engine): PASS
2141 23:19:46.833716 TX OE : NO K
2142 23:19:46.833800 All Pass.
2143 23:19:46.833867
2144 23:19:46.833929 DramC Write-DBI off
2145 23:19:46.837045 PER_BANK_REFRESH: Hybrid Mode
2146 23:19:46.840576 TX_TRACKING: ON
2147 23:19:46.843793 [GetDramInforAfterCalByMRR] Vendor 6.
2148 23:19:46.847151 [GetDramInforAfterCalByMRR] Revision 606.
2149 23:19:46.850954 [GetDramInforAfterCalByMRR] Revision 2 0.
2150 23:19:46.851037 MR0 0x3b3b
2151 23:19:46.851103 MR8 0x5151
2152 23:19:46.857209 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2153 23:19:46.857292
2154 23:19:46.857358 MR0 0x3b3b
2155 23:19:46.857419 MR8 0x5151
2156 23:19:46.860485 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2157 23:19:46.860568
2158 23:19:46.870497 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2159 23:19:46.873968 [FAST_K] Save calibration result to emmc
2160 23:19:46.877232 [FAST_K] Save calibration result to emmc
2161 23:19:46.880595 dram_init: config_dvfs: 1
2162 23:19:46.883683 dramc_set_vcore_voltage set vcore to 662500
2163 23:19:46.887314 Read voltage for 1200, 2
2164 23:19:46.887424 Vio18 = 0
2165 23:19:46.887523 Vcore = 662500
2166 23:19:46.890539 Vdram = 0
2167 23:19:46.890623 Vddq = 0
2168 23:19:46.890690 Vmddr = 0
2169 23:19:46.897154 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2170 23:19:46.900572 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2171 23:19:46.904163 MEM_TYPE=3, freq_sel=15
2172 23:19:46.907491 sv_algorithm_assistance_LP4_1600
2173 23:19:46.910896 ============ PULL DRAM RESETB DOWN ============
2174 23:19:46.914059 ========== PULL DRAM RESETB DOWN end =========
2175 23:19:46.920620 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2176 23:19:46.924068 ===================================
2177 23:19:46.927516 LPDDR4 DRAM CONFIGURATION
2178 23:19:46.931028 ===================================
2179 23:19:46.931111 EX_ROW_EN[0] = 0x0
2180 23:19:46.934392 EX_ROW_EN[1] = 0x0
2181 23:19:46.934475 LP4Y_EN = 0x0
2182 23:19:46.937512 WORK_FSP = 0x0
2183 23:19:46.937596 WL = 0x4
2184 23:19:46.940608 RL = 0x4
2185 23:19:46.940737 BL = 0x2
2186 23:19:46.944246 RPST = 0x0
2187 23:19:46.944328 RD_PRE = 0x0
2188 23:19:46.947604 WR_PRE = 0x1
2189 23:19:46.947686 WR_PST = 0x0
2190 23:19:46.950968 DBI_WR = 0x0
2191 23:19:46.951051 DBI_RD = 0x0
2192 23:19:46.954230 OTF = 0x1
2193 23:19:46.957585 ===================================
2194 23:19:46.960633 ===================================
2195 23:19:46.960722 ANA top config
2196 23:19:46.964020 ===================================
2197 23:19:46.967414 DLL_ASYNC_EN = 0
2198 23:19:46.970891 ALL_SLAVE_EN = 0
2199 23:19:46.974098 NEW_RANK_MODE = 1
2200 23:19:46.974182 DLL_IDLE_MODE = 1
2201 23:19:46.977389 LP45_APHY_COMB_EN = 1
2202 23:19:46.980748 TX_ODT_DIS = 1
2203 23:19:46.984256 NEW_8X_MODE = 1
2204 23:19:46.987310 ===================================
2205 23:19:46.990717 ===================================
2206 23:19:46.990800 data_rate = 2400
2207 23:19:46.994111 CKR = 1
2208 23:19:46.997389 DQ_P2S_RATIO = 8
2209 23:19:47.001237 ===================================
2210 23:19:47.004074 CA_P2S_RATIO = 8
2211 23:19:47.007429 DQ_CA_OPEN = 0
2212 23:19:47.010851 DQ_SEMI_OPEN = 0
2213 23:19:47.010934 CA_SEMI_OPEN = 0
2214 23:19:47.014311 CA_FULL_RATE = 0
2215 23:19:47.017757 DQ_CKDIV4_EN = 0
2216 23:19:47.021357 CA_CKDIV4_EN = 0
2217 23:19:47.024816 CA_PREDIV_EN = 0
2218 23:19:47.027572 PH8_DLY = 17
2219 23:19:47.027654 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2220 23:19:47.030998 DQ_AAMCK_DIV = 4
2221 23:19:47.034380 CA_AAMCK_DIV = 4
2222 23:19:47.037572 CA_ADMCK_DIV = 4
2223 23:19:47.041040 DQ_TRACK_CA_EN = 0
2224 23:19:47.044439 CA_PICK = 1200
2225 23:19:47.044548 CA_MCKIO = 1200
2226 23:19:47.047790 MCKIO_SEMI = 0
2227 23:19:47.050947 PLL_FREQ = 2366
2228 23:19:47.054369 DQ_UI_PI_RATIO = 32
2229 23:19:47.058090 CA_UI_PI_RATIO = 0
2230 23:19:47.060870 ===================================
2231 23:19:47.064503 ===================================
2232 23:19:47.067711 memory_type:LPDDR4
2233 23:19:47.067794 GP_NUM : 10
2234 23:19:47.071242 SRAM_EN : 1
2235 23:19:47.071325 MD32_EN : 0
2236 23:19:47.074473 ===================================
2237 23:19:47.077692 [ANA_INIT] >>>>>>>>>>>>>>
2238 23:19:47.081177 <<<<<< [CONFIGURE PHASE]: ANA_TX
2239 23:19:47.084686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2240 23:19:47.087619 ===================================
2241 23:19:47.090848 data_rate = 2400,PCW = 0X5b00
2242 23:19:47.094324 ===================================
2243 23:19:47.097760 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2244 23:19:47.104341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2245 23:19:47.107870 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2246 23:19:47.114515 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2247 23:19:47.117789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2248 23:19:47.120850 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2249 23:19:47.120934 [ANA_INIT] flow start
2250 23:19:47.124303 [ANA_INIT] PLL >>>>>>>>
2251 23:19:47.127705 [ANA_INIT] PLL <<<<<<<<
2252 23:19:47.127789 [ANA_INIT] MIDPI >>>>>>>>
2253 23:19:47.131002 [ANA_INIT] MIDPI <<<<<<<<
2254 23:19:47.134305 [ANA_INIT] DLL >>>>>>>>
2255 23:19:47.134413 [ANA_INIT] DLL <<<<<<<<
2256 23:19:47.137811 [ANA_INIT] flow end
2257 23:19:47.140761 ============ LP4 DIFF to SE enter ============
2258 23:19:47.144116 ============ LP4 DIFF to SE exit ============
2259 23:19:47.147800 [ANA_INIT] <<<<<<<<<<<<<
2260 23:19:47.150862 [Flow] Enable top DCM control >>>>>
2261 23:19:47.154152 [Flow] Enable top DCM control <<<<<
2262 23:19:47.158012 Enable DLL master slave shuffle
2263 23:19:47.164191 ==============================================================
2264 23:19:47.164275 Gating Mode config
2265 23:19:47.171147 ==============================================================
2266 23:19:47.171231 Config description:
2267 23:19:47.181169 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2268 23:19:47.187647 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2269 23:19:47.194328 SELPH_MODE 0: By rank 1: By Phase
2270 23:19:47.197466 ==============================================================
2271 23:19:47.201168 GAT_TRACK_EN = 1
2272 23:19:47.204166 RX_GATING_MODE = 2
2273 23:19:47.207509 RX_GATING_TRACK_MODE = 2
2274 23:19:47.210996 SELPH_MODE = 1
2275 23:19:47.214443 PICG_EARLY_EN = 1
2276 23:19:47.217785 VALID_LAT_VALUE = 1
2277 23:19:47.220960 ==============================================================
2278 23:19:47.224682 Enter into Gating configuration >>>>
2279 23:19:47.227559 Exit from Gating configuration <<<<
2280 23:19:47.231043 Enter into DVFS_PRE_config >>>>>
2281 23:19:47.244605 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2282 23:19:47.247500 Exit from DVFS_PRE_config <<<<<
2283 23:19:47.250860 Enter into PICG configuration >>>>
2284 23:19:47.254189 Exit from PICG configuration <<<<
2285 23:19:47.254273 [RX_INPUT] configuration >>>>>
2286 23:19:47.257844 [RX_INPUT] configuration <<<<<
2287 23:19:47.264130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2288 23:19:47.267629 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2289 23:19:47.274494 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2290 23:19:47.280663 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2291 23:19:47.287903 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2292 23:19:47.294520 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2293 23:19:47.297801 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2294 23:19:47.301026 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2295 23:19:47.304558 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2296 23:19:47.311252 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2297 23:19:47.314426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2298 23:19:47.317612 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2299 23:19:47.320845 ===================================
2300 23:19:47.324377 LPDDR4 DRAM CONFIGURATION
2301 23:19:47.327608 ===================================
2302 23:19:47.331027 EX_ROW_EN[0] = 0x0
2303 23:19:47.331110 EX_ROW_EN[1] = 0x0
2304 23:19:47.334315 LP4Y_EN = 0x0
2305 23:19:47.334398 WORK_FSP = 0x0
2306 23:19:47.337816 WL = 0x4
2307 23:19:47.337899 RL = 0x4
2308 23:19:47.340997 BL = 0x2
2309 23:19:47.341079 RPST = 0x0
2310 23:19:47.344124 RD_PRE = 0x0
2311 23:19:47.344207 WR_PRE = 0x1
2312 23:19:47.347811 WR_PST = 0x0
2313 23:19:47.347894 DBI_WR = 0x0
2314 23:19:47.351263 DBI_RD = 0x0
2315 23:19:47.351346 OTF = 0x1
2316 23:19:47.354305 ===================================
2317 23:19:47.357754 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2318 23:19:47.364483 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2319 23:19:47.367765 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2320 23:19:47.371170 ===================================
2321 23:19:47.374448 LPDDR4 DRAM CONFIGURATION
2322 23:19:47.377795 ===================================
2323 23:19:47.377878 EX_ROW_EN[0] = 0x10
2324 23:19:47.381096 EX_ROW_EN[1] = 0x0
2325 23:19:47.381179 LP4Y_EN = 0x0
2326 23:19:47.384357 WORK_FSP = 0x0
2327 23:19:47.387668 WL = 0x4
2328 23:19:47.387752 RL = 0x4
2329 23:19:47.391070 BL = 0x2
2330 23:19:47.391152 RPST = 0x0
2331 23:19:47.394296 RD_PRE = 0x0
2332 23:19:47.394377 WR_PRE = 0x1
2333 23:19:47.397759 WR_PST = 0x0
2334 23:19:47.397840 DBI_WR = 0x0
2335 23:19:47.401011 DBI_RD = 0x0
2336 23:19:47.401092 OTF = 0x1
2337 23:19:47.404624 ===================================
2338 23:19:47.411119 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2339 23:19:47.411200 ==
2340 23:19:47.414317 Dram Type= 6, Freq= 0, CH_0, rank 0
2341 23:19:47.417674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2342 23:19:47.417756 ==
2343 23:19:47.421346 [Duty_Offset_Calibration]
2344 23:19:47.424450 B0:2 B1:0 CA:1
2345 23:19:47.424540
2346 23:19:47.427517 [DutyScan_Calibration_Flow] k_type=0
2347 23:19:47.434926
2348 23:19:47.435007 ==CLK 0==
2349 23:19:47.438070 Final CLK duty delay cell = -4
2350 23:19:47.441539 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2351 23:19:47.444898 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2352 23:19:47.448441 [-4] AVG Duty = 4953%(X100)
2353 23:19:47.448522
2354 23:19:47.451308 CH0 CLK Duty spec in!! Max-Min= 156%
2355 23:19:47.455158 [DutyScan_Calibration_Flow] ====Done====
2356 23:19:47.455241
2357 23:19:47.457921 [DutyScan_Calibration_Flow] k_type=1
2358 23:19:47.473575
2359 23:19:47.473658 ==DQS 0 ==
2360 23:19:47.476837 Final DQS duty delay cell = 0
2361 23:19:47.480172 [0] MAX Duty = 5187%(X100), DQS PI = 30
2362 23:19:47.483811 [0] MIN Duty = 4938%(X100), DQS PI = 0
2363 23:19:47.483893 [0] AVG Duty = 5062%(X100)
2364 23:19:47.487212
2365 23:19:47.487292 ==DQS 1 ==
2366 23:19:47.490121 Final DQS duty delay cell = -4
2367 23:19:47.493527 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2368 23:19:47.497246 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2369 23:19:47.500189 [-4] AVG Duty = 5015%(X100)
2370 23:19:47.500271
2371 23:19:47.503604 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2372 23:19:47.503685
2373 23:19:47.506880 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2374 23:19:47.510553 [DutyScan_Calibration_Flow] ====Done====
2375 23:19:47.510636
2376 23:19:47.513638 [DutyScan_Calibration_Flow] k_type=3
2377 23:19:47.530289
2378 23:19:47.530383 ==DQM 0 ==
2379 23:19:47.533791 Final DQM duty delay cell = 0
2380 23:19:47.537440 [0] MAX Duty = 5062%(X100), DQS PI = 24
2381 23:19:47.540748 [0] MIN Duty = 4813%(X100), DQS PI = 0
2382 23:19:47.540831 [0] AVG Duty = 4937%(X100)
2383 23:19:47.540896
2384 23:19:47.543612 ==DQM 1 ==
2385 23:19:47.547463 Final DQM duty delay cell = 0
2386 23:19:47.550899 [0] MAX Duty = 5187%(X100), DQS PI = 48
2387 23:19:47.553690 [0] MIN Duty = 5000%(X100), DQS PI = 22
2388 23:19:47.553773 [0] AVG Duty = 5093%(X100)
2389 23:19:47.556860
2390 23:19:47.560277 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2391 23:19:47.560361
2392 23:19:47.563825 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2393 23:19:47.566985 [DutyScan_Calibration_Flow] ====Done====
2394 23:19:47.567069
2395 23:19:47.570348 [DutyScan_Calibration_Flow] k_type=2
2396 23:19:47.586822
2397 23:19:47.586913 ==DQ 0 ==
2398 23:19:47.590163 Final DQ duty delay cell = -4
2399 23:19:47.593707 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2400 23:19:47.597272 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2401 23:19:47.600391 [-4] AVG Duty = 4953%(X100)
2402 23:19:47.600477
2403 23:19:47.600544 ==DQ 1 ==
2404 23:19:47.603290 Final DQ duty delay cell = 4
2405 23:19:47.607178 [4] MAX Duty = 5093%(X100), DQS PI = 4
2406 23:19:47.610343 [4] MIN Duty = 5031%(X100), DQS PI = 2
2407 23:19:47.610428 [4] AVG Duty = 5062%(X100)
2408 23:19:47.610495
2409 23:19:47.613615 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2410 23:19:47.616893
2411 23:19:47.616978 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2412 23:19:47.623594 [DutyScan_Calibration_Flow] ====Done====
2413 23:19:47.623679 ==
2414 23:19:47.626951 Dram Type= 6, Freq= 0, CH_1, rank 0
2415 23:19:47.630542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2416 23:19:47.630627 ==
2417 23:19:47.633741 [Duty_Offset_Calibration]
2418 23:19:47.633825 B0:0 B1:-1 CA:2
2419 23:19:47.633893
2420 23:19:47.636783 [DutyScan_Calibration_Flow] k_type=0
2421 23:19:47.646971
2422 23:19:47.647060 ==CLK 0==
2423 23:19:47.650249 Final CLK duty delay cell = 0
2424 23:19:47.653608 [0] MAX Duty = 5124%(X100), DQS PI = 4
2425 23:19:47.657421 [0] MIN Duty = 4938%(X100), DQS PI = 12
2426 23:19:47.657511 [0] AVG Duty = 5031%(X100)
2427 23:19:47.660329
2428 23:19:47.660413 CH1 CLK Duty spec in!! Max-Min= 186%
2429 23:19:47.666986 [DutyScan_Calibration_Flow] ====Done====
2430 23:19:47.667072
2431 23:19:47.670288 [DutyScan_Calibration_Flow] k_type=1
2432 23:19:47.686294
2433 23:19:47.686384 ==DQS 0 ==
2434 23:19:47.689428 Final DQS duty delay cell = 0
2435 23:19:47.693375 [0] MAX Duty = 5093%(X100), DQS PI = 56
2436 23:19:47.696170 [0] MIN Duty = 4969%(X100), DQS PI = 46
2437 23:19:47.696255 [0] AVG Duty = 5031%(X100)
2438 23:19:47.699541
2439 23:19:47.699625 ==DQS 1 ==
2440 23:19:47.703176 Final DQS duty delay cell = 0
2441 23:19:47.706325 [0] MAX Duty = 5156%(X100), DQS PI = 28
2442 23:19:47.709715 [0] MIN Duty = 4813%(X100), DQS PI = 4
2443 23:19:47.709799 [0] AVG Duty = 4984%(X100)
2444 23:19:47.713170
2445 23:19:47.716394 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2446 23:19:47.716477
2447 23:19:47.719865 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2448 23:19:47.723199 [DutyScan_Calibration_Flow] ====Done====
2449 23:19:47.723285
2450 23:19:47.726225 [DutyScan_Calibration_Flow] k_type=3
2451 23:19:47.743539
2452 23:19:47.743639 ==DQM 0 ==
2453 23:19:47.747000 Final DQM duty delay cell = 4
2454 23:19:47.750399 [4] MAX Duty = 5124%(X100), DQS PI = 22
2455 23:19:47.753852 [4] MIN Duty = 4969%(X100), DQS PI = 0
2456 23:19:47.753938 [4] AVG Duty = 5046%(X100)
2457 23:19:47.756673
2458 23:19:47.756757 ==DQM 1 ==
2459 23:19:47.760224 Final DQM duty delay cell = 0
2460 23:19:47.763429 [0] MAX Duty = 5249%(X100), DQS PI = 28
2461 23:19:47.766795 [0] MIN Duty = 4875%(X100), DQS PI = 4
2462 23:19:47.766879 [0] AVG Duty = 5062%(X100)
2463 23:19:47.770194
2464 23:19:47.773932 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2465 23:19:47.774016
2466 23:19:47.777223 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2467 23:19:47.780306 [DutyScan_Calibration_Flow] ====Done====
2468 23:19:47.780390
2469 23:19:47.783752 [DutyScan_Calibration_Flow] k_type=2
2470 23:19:47.800013
2471 23:19:47.800107 ==DQ 0 ==
2472 23:19:47.803420 Final DQ duty delay cell = 0
2473 23:19:47.806663 [0] MAX Duty = 5062%(X100), DQS PI = 24
2474 23:19:47.809955 [0] MIN Duty = 4938%(X100), DQS PI = 0
2475 23:19:47.810040 [0] AVG Duty = 5000%(X100)
2476 23:19:47.810107
2477 23:19:47.813434 ==DQ 1 ==
2478 23:19:47.816595 Final DQ duty delay cell = 0
2479 23:19:47.820265 [0] MAX Duty = 5031%(X100), DQS PI = 32
2480 23:19:47.823399 [0] MIN Duty = 4813%(X100), DQS PI = 2
2481 23:19:47.823482 [0] AVG Duty = 4922%(X100)
2482 23:19:47.823549
2483 23:19:47.826689 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2484 23:19:47.826773
2485 23:19:47.830111 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2486 23:19:47.836614 [DutyScan_Calibration_Flow] ====Done====
2487 23:19:47.839997 nWR fixed to 30
2488 23:19:47.840081 [ModeRegInit_LP4] CH0 RK0
2489 23:19:47.843677 [ModeRegInit_LP4] CH0 RK1
2490 23:19:47.846869 [ModeRegInit_LP4] CH1 RK0
2491 23:19:47.846954 [ModeRegInit_LP4] CH1 RK1
2492 23:19:47.850130 match AC timing 7
2493 23:19:47.853707 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2494 23:19:47.857086 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2495 23:19:47.863449 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2496 23:19:47.866698 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2497 23:19:47.873529 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2498 23:19:47.873613 ==
2499 23:19:47.877117 Dram Type= 6, Freq= 0, CH_0, rank 0
2500 23:19:47.880177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2501 23:19:47.880261 ==
2502 23:19:47.886612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2503 23:19:47.890119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2504 23:19:47.900082 [CA 0] Center 38 (7~69) winsize 63
2505 23:19:47.903204 [CA 1] Center 38 (8~69) winsize 62
2506 23:19:47.906426 [CA 2] Center 35 (5~66) winsize 62
2507 23:19:47.910002 [CA 3] Center 35 (4~66) winsize 63
2508 23:19:47.913411 [CA 4] Center 34 (4~65) winsize 62
2509 23:19:47.916480 [CA 5] Center 33 (3~63) winsize 61
2510 23:19:47.916563
2511 23:19:47.919908 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2512 23:19:47.919991
2513 23:19:47.923454 [CATrainingPosCal] consider 1 rank data
2514 23:19:47.926425 u2DelayCellTimex100 = 270/100 ps
2515 23:19:47.929780 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2516 23:19:47.933192 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2517 23:19:47.939838 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2518 23:19:47.943506 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2519 23:19:47.946798 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2520 23:19:47.950135 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2521 23:19:47.950218
2522 23:19:47.953254 CA PerBit enable=1, Macro0, CA PI delay=33
2523 23:19:47.953338
2524 23:19:47.956636 [CBTSetCACLKResult] CA Dly = 33
2525 23:19:47.956756 CS Dly: 6 (0~37)
2526 23:19:47.956824 ==
2527 23:19:47.959994 Dram Type= 6, Freq= 0, CH_0, rank 1
2528 23:19:47.966674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 23:19:47.966759 ==
2530 23:19:47.970298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2531 23:19:47.976622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2532 23:19:47.985645 [CA 0] Center 39 (8~70) winsize 63
2533 23:19:47.989213 [CA 1] Center 38 (8~69) winsize 62
2534 23:19:47.992140 [CA 2] Center 35 (5~66) winsize 62
2535 23:19:47.995722 [CA 3] Center 35 (5~66) winsize 62
2536 23:19:47.998944 [CA 4] Center 34 (4~65) winsize 62
2537 23:19:48.002206 [CA 5] Center 34 (4~64) winsize 61
2538 23:19:48.002290
2539 23:19:48.005740 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2540 23:19:48.005824
2541 23:19:48.009201 [CATrainingPosCal] consider 2 rank data
2542 23:19:48.012412 u2DelayCellTimex100 = 270/100 ps
2543 23:19:48.015784 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2544 23:19:48.019023 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2545 23:19:48.022826 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2546 23:19:48.029184 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2547 23:19:48.032630 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2548 23:19:48.036007 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2549 23:19:48.036097
2550 23:19:48.039379 CA PerBit enable=1, Macro0, CA PI delay=33
2551 23:19:48.039469
2552 23:19:48.042305 [CBTSetCACLKResult] CA Dly = 33
2553 23:19:48.042388 CS Dly: 7 (0~39)
2554 23:19:48.042455
2555 23:19:48.045807 ----->DramcWriteLeveling(PI) begin...
2556 23:19:48.045891 ==
2557 23:19:48.049548 Dram Type= 6, Freq= 0, CH_0, rank 0
2558 23:19:48.055662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2559 23:19:48.055746 ==
2560 23:19:48.059396 Write leveling (Byte 0): 33 => 33
2561 23:19:48.062817 Write leveling (Byte 1): 30 => 30
2562 23:19:48.062900 DramcWriteLeveling(PI) end<-----
2563 23:19:48.062966
2564 23:19:48.065991 ==
2565 23:19:48.069097 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 23:19:48.072398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 23:19:48.072488 ==
2568 23:19:48.075833 [Gating] SW mode calibration
2569 23:19:48.082628 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2570 23:19:48.085857 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2571 23:19:48.092613 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2572 23:19:48.095702 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2573 23:19:48.099338 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2574 23:19:48.105919 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 23:19:48.109295 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2576 23:19:48.112431 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 23:19:48.119468 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2578 23:19:48.122695 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2579 23:19:48.126107 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2580 23:19:48.129333 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 23:19:48.136171 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 23:19:48.139575 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 23:19:48.142817 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 23:19:48.149545 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 23:19:48.152590 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2586 23:19:48.155956 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2587 23:19:48.163015 1 1 0 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2588 23:19:48.166062 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 23:19:48.169667 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 23:19:48.176236 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 23:19:48.180315 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 23:19:48.183236 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 23:19:48.189485 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2594 23:19:48.192752 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2595 23:19:48.196286 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2596 23:19:48.202779 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 23:19:48.206383 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 23:19:48.209863 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 23:19:48.213123 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 23:19:48.219638 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 23:19:48.222958 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 23:19:48.226152 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 23:19:48.233208 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 23:19:48.236471 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 23:19:48.239529 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 23:19:48.246432 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 23:19:48.249371 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 23:19:48.253086 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 23:19:48.259403 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2610 23:19:48.263091 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2611 23:19:48.266116 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2612 23:19:48.269680 Total UI for P1: 0, mck2ui 16
2613 23:19:48.272858 best dqsien dly found for B0: ( 1, 3, 26)
2614 23:19:48.279962 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 23:19:48.280045 Total UI for P1: 0, mck2ui 16
2616 23:19:48.283184 best dqsien dly found for B1: ( 1, 3, 30)
2617 23:19:48.289681 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2618 23:19:48.292972 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2619 23:19:48.293055
2620 23:19:48.296244 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2621 23:19:48.299518 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2622 23:19:48.302861 [Gating] SW calibration Done
2623 23:19:48.302943 ==
2624 23:19:48.306226 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 23:19:48.309695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 23:19:48.309779 ==
2627 23:19:48.313121 RX Vref Scan: 0
2628 23:19:48.313203
2629 23:19:48.313268 RX Vref 0 -> 0, step: 1
2630 23:19:48.313329
2631 23:19:48.316528 RX Delay -40 -> 252, step: 8
2632 23:19:48.319658 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2633 23:19:48.322990 iDelay=208, Bit 1, Center 127 (56 ~ 199) 144
2634 23:19:48.329631 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2635 23:19:48.332982 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2636 23:19:48.336448 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2637 23:19:48.339790 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2638 23:19:48.343178 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2639 23:19:48.349672 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2640 23:19:48.353117 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2641 23:19:48.356600 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2642 23:19:48.359570 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2643 23:19:48.363168 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2644 23:19:48.369811 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2645 23:19:48.373133 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2646 23:19:48.376457 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2647 23:19:48.379773 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2648 23:19:48.379856 ==
2649 23:19:48.382963 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 23:19:48.386355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 23:19:48.389851 ==
2652 23:19:48.389943 DQS Delay:
2653 23:19:48.390041 DQS0 = 0, DQS1 = 0
2654 23:19:48.393916 DQM Delay:
2655 23:19:48.393999 DQM0 = 123, DQM1 = 110
2656 23:19:48.396747 DQ Delay:
2657 23:19:48.399812 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2658 23:19:48.403024 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2659 23:19:48.406394 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2660 23:19:48.409538 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2661 23:19:48.409620
2662 23:19:48.409697
2663 23:19:48.409764 ==
2664 23:19:48.413237 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 23:19:48.416384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 23:19:48.416468 ==
2667 23:19:48.416533
2668 23:19:48.419972
2669 23:19:48.420054 TX Vref Scan disable
2670 23:19:48.423245 == TX Byte 0 ==
2671 23:19:48.426387 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2672 23:19:48.429863 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2673 23:19:48.433154 == TX Byte 1 ==
2674 23:19:48.436578 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2675 23:19:48.439730 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2676 23:19:48.439813 ==
2677 23:19:48.443160 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 23:19:48.449929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 23:19:48.450011 ==
2680 23:19:48.460086 TX Vref=22, minBit 0, minWin=24, winSum=408
2681 23:19:48.463858 TX Vref=24, minBit 0, minWin=25, winSum=413
2682 23:19:48.466870 TX Vref=26, minBit 4, minWin=25, winSum=419
2683 23:19:48.470292 TX Vref=28, minBit 0, minWin=26, winSum=426
2684 23:19:48.473652 TX Vref=30, minBit 5, minWin=25, winSum=430
2685 23:19:48.476870 TX Vref=32, minBit 1, minWin=25, winSum=421
2686 23:19:48.483508 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
2687 23:19:48.483591
2688 23:19:48.486927 Final TX Range 1 Vref 28
2689 23:19:48.487011
2690 23:19:48.487080 ==
2691 23:19:48.490002 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 23:19:48.493792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 23:19:48.493876 ==
2694 23:19:48.493942
2695 23:19:48.494018
2696 23:19:48.496627 TX Vref Scan disable
2697 23:19:48.500248 == TX Byte 0 ==
2698 23:19:48.503466 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2699 23:19:48.507124 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2700 23:19:48.510317 == TX Byte 1 ==
2701 23:19:48.513784 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2702 23:19:48.516852 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2703 23:19:48.516937
2704 23:19:48.520564 [DATLAT]
2705 23:19:48.520707 Freq=1200, CH0 RK0
2706 23:19:48.520775
2707 23:19:48.523811 DATLAT Default: 0xd
2708 23:19:48.523894 0, 0xFFFF, sum = 0
2709 23:19:48.527007 1, 0xFFFF, sum = 0
2710 23:19:48.527090 2, 0xFFFF, sum = 0
2711 23:19:48.530123 3, 0xFFFF, sum = 0
2712 23:19:48.530206 4, 0xFFFF, sum = 0
2713 23:19:48.533654 5, 0xFFFF, sum = 0
2714 23:19:48.533738 6, 0xFFFF, sum = 0
2715 23:19:48.536862 7, 0xFFFF, sum = 0
2716 23:19:48.536946 8, 0xFFFF, sum = 0
2717 23:19:48.540530 9, 0xFFFF, sum = 0
2718 23:19:48.543894 10, 0xFFFF, sum = 0
2719 23:19:48.543978 11, 0xFFFF, sum = 0
2720 23:19:48.546702 12, 0x0, sum = 1
2721 23:19:48.546786 13, 0x0, sum = 2
2722 23:19:48.546853 14, 0x0, sum = 3
2723 23:19:48.550343 15, 0x0, sum = 4
2724 23:19:48.550426 best_step = 13
2725 23:19:48.550492
2726 23:19:48.550552 ==
2727 23:19:48.553616 Dram Type= 6, Freq= 0, CH_0, rank 0
2728 23:19:48.560499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2729 23:19:48.560608 ==
2730 23:19:48.560725 RX Vref Scan: 1
2731 23:19:48.560788
2732 23:19:48.563460 Set Vref Range= 32 -> 127
2733 23:19:48.563542
2734 23:19:48.566929 RX Vref 32 -> 127, step: 1
2735 23:19:48.567011
2736 23:19:48.570112 RX Delay -13 -> 252, step: 4
2737 23:19:48.570195
2738 23:19:48.573376 Set Vref, RX VrefLevel [Byte0]: 32
2739 23:19:48.576868 [Byte1]: 32
2740 23:19:48.576951
2741 23:19:48.580184 Set Vref, RX VrefLevel [Byte0]: 33
2742 23:19:48.583521 [Byte1]: 33
2743 23:19:48.583603
2744 23:19:48.586861 Set Vref, RX VrefLevel [Byte0]: 34
2745 23:19:48.589925 [Byte1]: 34
2746 23:19:48.594030
2747 23:19:48.594114 Set Vref, RX VrefLevel [Byte0]: 35
2748 23:19:48.597488 [Byte1]: 35
2749 23:19:48.602009
2750 23:19:48.602091 Set Vref, RX VrefLevel [Byte0]: 36
2751 23:19:48.605258 [Byte1]: 36
2752 23:19:48.610192
2753 23:19:48.610274 Set Vref, RX VrefLevel [Byte0]: 37
2754 23:19:48.613130 [Byte1]: 37
2755 23:19:48.617751
2756 23:19:48.617836 Set Vref, RX VrefLevel [Byte0]: 38
2757 23:19:48.621266 [Byte1]: 38
2758 23:19:48.625738
2759 23:19:48.625830 Set Vref, RX VrefLevel [Byte0]: 39
2760 23:19:48.629120 [Byte1]: 39
2761 23:19:48.633748
2762 23:19:48.633845 Set Vref, RX VrefLevel [Byte0]: 40
2763 23:19:48.637213 [Byte1]: 40
2764 23:19:48.641774
2765 23:19:48.641869 Set Vref, RX VrefLevel [Byte0]: 41
2766 23:19:48.644558 [Byte1]: 41
2767 23:19:48.649438
2768 23:19:48.649532 Set Vref, RX VrefLevel [Byte0]: 42
2769 23:19:48.652546 [Byte1]: 42
2770 23:19:48.657307
2771 23:19:48.657401 Set Vref, RX VrefLevel [Byte0]: 43
2772 23:19:48.660730 [Byte1]: 43
2773 23:19:48.665158
2774 23:19:48.665253 Set Vref, RX VrefLevel [Byte0]: 44
2775 23:19:48.668470 [Byte1]: 44
2776 23:19:48.673268
2777 23:19:48.673357 Set Vref, RX VrefLevel [Byte0]: 45
2778 23:19:48.676424 [Byte1]: 45
2779 23:19:48.680764
2780 23:19:48.680850 Set Vref, RX VrefLevel [Byte0]: 46
2781 23:19:48.684075 [Byte1]: 46
2782 23:19:48.688913
2783 23:19:48.689000 Set Vref, RX VrefLevel [Byte0]: 47
2784 23:19:48.691891 [Byte1]: 47
2785 23:19:48.696974
2786 23:19:48.697064 Set Vref, RX VrefLevel [Byte0]: 48
2787 23:19:48.700058 [Byte1]: 48
2788 23:19:48.704464
2789 23:19:48.704550 Set Vref, RX VrefLevel [Byte0]: 49
2790 23:19:48.708031 [Byte1]: 49
2791 23:19:48.712347
2792 23:19:48.712434 Set Vref, RX VrefLevel [Byte0]: 50
2793 23:19:48.715731 [Byte1]: 50
2794 23:19:48.720335
2795 23:19:48.720421 Set Vref, RX VrefLevel [Byte0]: 51
2796 23:19:48.723709 [Byte1]: 51
2797 23:19:48.728319
2798 23:19:48.728408 Set Vref, RX VrefLevel [Byte0]: 52
2799 23:19:48.731516 [Byte1]: 52
2800 23:19:48.736435
2801 23:19:48.736522 Set Vref, RX VrefLevel [Byte0]: 53
2802 23:19:48.739448 [Byte1]: 53
2803 23:19:48.744012
2804 23:19:48.744095 Set Vref, RX VrefLevel [Byte0]: 54
2805 23:19:48.747209 [Byte1]: 54
2806 23:19:48.752006
2807 23:19:48.752089 Set Vref, RX VrefLevel [Byte0]: 55
2808 23:19:48.755208 [Byte1]: 55
2809 23:19:48.759849
2810 23:19:48.759933 Set Vref, RX VrefLevel [Byte0]: 56
2811 23:19:48.763120 [Byte1]: 56
2812 23:19:48.768021
2813 23:19:48.768104 Set Vref, RX VrefLevel [Byte0]: 57
2814 23:19:48.771147 [Byte1]: 57
2815 23:19:48.775427
2816 23:19:48.775509 Set Vref, RX VrefLevel [Byte0]: 58
2817 23:19:48.778753 [Byte1]: 58
2818 23:19:48.783600
2819 23:19:48.783683 Set Vref, RX VrefLevel [Byte0]: 59
2820 23:19:48.786755 [Byte1]: 59
2821 23:19:48.791205
2822 23:19:48.791290 Set Vref, RX VrefLevel [Byte0]: 60
2823 23:19:48.794756 [Byte1]: 60
2824 23:19:48.799444
2825 23:19:48.799555 Set Vref, RX VrefLevel [Byte0]: 61
2826 23:19:48.802759 [Byte1]: 61
2827 23:19:48.807191
2828 23:19:48.807276 Set Vref, RX VrefLevel [Byte0]: 62
2829 23:19:48.810359 [Byte1]: 62
2830 23:19:48.815008
2831 23:19:48.815091 Set Vref, RX VrefLevel [Byte0]: 63
2832 23:19:48.818354 [Byte1]: 63
2833 23:19:48.822803
2834 23:19:48.822927 Set Vref, RX VrefLevel [Byte0]: 64
2835 23:19:48.826408 [Byte1]: 64
2836 23:19:48.831128
2837 23:19:48.831219 Set Vref, RX VrefLevel [Byte0]: 65
2838 23:19:48.834212 [Byte1]: 65
2839 23:19:48.838853
2840 23:19:48.838942 Set Vref, RX VrefLevel [Byte0]: 66
2841 23:19:48.842284 [Byte1]: 66
2842 23:19:48.846623
2843 23:19:48.846705 Set Vref, RX VrefLevel [Byte0]: 67
2844 23:19:48.849836 [Byte1]: 67
2845 23:19:48.854440
2846 23:19:48.854523 Set Vref, RX VrefLevel [Byte0]: 68
2847 23:19:48.857613 [Byte1]: 68
2848 23:19:48.862294
2849 23:19:48.862405 Set Vref, RX VrefLevel [Byte0]: 69
2850 23:19:48.865763 [Byte1]: 69
2851 23:19:48.870683
2852 23:19:48.870766 Set Vref, RX VrefLevel [Byte0]: 70
2853 23:19:48.873784 [Byte1]: 70
2854 23:19:48.878091
2855 23:19:48.878179 Set Vref, RX VrefLevel [Byte0]: 71
2856 23:19:48.881360 [Byte1]: 71
2857 23:19:48.886377
2858 23:19:48.886461 Final RX Vref Byte 0 = 59 to rank0
2859 23:19:48.889658 Final RX Vref Byte 1 = 49 to rank0
2860 23:19:48.892803 Final RX Vref Byte 0 = 59 to rank1
2861 23:19:48.896229 Final RX Vref Byte 1 = 49 to rank1==
2862 23:19:48.899471 Dram Type= 6, Freq= 0, CH_0, rank 0
2863 23:19:48.906068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2864 23:19:48.906155 ==
2865 23:19:48.906222 DQS Delay:
2866 23:19:48.906283 DQS0 = 0, DQS1 = 0
2867 23:19:48.909258 DQM Delay:
2868 23:19:48.909342 DQM0 = 122, DQM1 = 109
2869 23:19:48.912626 DQ Delay:
2870 23:19:48.916092 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2871 23:19:48.919448 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2872 23:19:48.922748 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2873 23:19:48.926163 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2874 23:19:48.926251
2875 23:19:48.926318
2876 23:19:48.932735 [DQSOSCAuto] RK0, (LSB)MR18= 0xa06, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2877 23:19:48.936089 CH0 RK0: MR19=404, MR18=A06
2878 23:19:48.942662 CH0_RK0: MR19=0x404, MR18=0xA06, DQSOSC=406, MR23=63, INC=39, DEC=26
2879 23:19:48.942749
2880 23:19:48.945990 ----->DramcWriteLeveling(PI) begin...
2881 23:19:48.946073 ==
2882 23:19:48.949303 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 23:19:48.952753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 23:19:48.952838 ==
2885 23:19:48.956429 Write leveling (Byte 0): 35 => 35
2886 23:19:48.959533 Write leveling (Byte 1): 28 => 28
2887 23:19:48.963164 DramcWriteLeveling(PI) end<-----
2888 23:19:48.963247
2889 23:19:48.963313 ==
2890 23:19:48.966698 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 23:19:48.969613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 23:19:48.972829 ==
2893 23:19:48.972913 [Gating] SW mode calibration
2894 23:19:48.979575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2895 23:19:48.986165 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2896 23:19:48.989741 0 15 0 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
2897 23:19:48.996652 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 23:19:48.999602 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 23:19:49.002888 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 23:19:49.009748 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 23:19:49.013155 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 23:19:49.016581 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2903 23:19:49.023251 0 15 28 | B1->B0 | 3131 2b2b | 0 0 | (0 1) (0 1)
2904 23:19:49.026610 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 23:19:49.029663 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 23:19:49.033206 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 23:19:49.039666 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 23:19:49.043393 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 23:19:49.046524 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 23:19:49.053404 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2911 23:19:49.056531 1 0 28 | B1->B0 | 3939 3f3f | 0 1 | (0 0) (0 0)
2912 23:19:49.059823 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 23:19:49.066954 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 23:19:49.070028 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 23:19:49.073538 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 23:19:49.080289 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 23:19:49.083318 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 23:19:49.086541 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 23:19:49.093634 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2920 23:19:49.096477 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2921 23:19:49.099939 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 23:19:49.106677 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 23:19:49.110138 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 23:19:49.113352 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 23:19:49.116679 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 23:19:49.123356 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 23:19:49.127237 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 23:19:49.130115 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 23:19:49.136668 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 23:19:49.140351 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:19:49.143460 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:19:49.149914 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 23:19:49.153720 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 23:19:49.156981 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2935 23:19:49.163602 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2936 23:19:49.166423 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 23:19:49.170279 Total UI for P1: 0, mck2ui 16
2938 23:19:49.173400 best dqsien dly found for B0: ( 1, 3, 26)
2939 23:19:49.176953 Total UI for P1: 0, mck2ui 16
2940 23:19:49.180088 best dqsien dly found for B1: ( 1, 3, 30)
2941 23:19:49.183412 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2942 23:19:49.186898 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2943 23:19:49.186984
2944 23:19:49.190217 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2945 23:19:49.193459 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2946 23:19:49.196831 [Gating] SW calibration Done
2947 23:19:49.196916 ==
2948 23:19:49.200121 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 23:19:49.203571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 23:19:49.203657 ==
2951 23:19:49.206963 RX Vref Scan: 0
2952 23:19:49.207054
2953 23:19:49.209976 RX Vref 0 -> 0, step: 1
2954 23:19:49.210065
2955 23:19:49.210133 RX Delay -40 -> 252, step: 8
2956 23:19:49.216964 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2957 23:19:49.219885 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2958 23:19:49.223830 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2959 23:19:49.226964 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2960 23:19:49.229950 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2961 23:19:49.236827 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2962 23:19:49.240147 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2963 23:19:49.243543 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2964 23:19:49.247302 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2965 23:19:49.250400 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2966 23:19:49.253822 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2967 23:19:49.260330 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2968 23:19:49.263487 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2969 23:19:49.267073 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2970 23:19:49.270224 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2971 23:19:49.276823 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2972 23:19:49.276910 ==
2973 23:19:49.280157 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 23:19:49.283633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 23:19:49.283719 ==
2976 23:19:49.283787 DQS Delay:
2977 23:19:49.286572 DQS0 = 0, DQS1 = 0
2978 23:19:49.286657 DQM Delay:
2979 23:19:49.290033 DQM0 = 120, DQM1 = 108
2980 23:19:49.290117 DQ Delay:
2981 23:19:49.293276 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2982 23:19:49.296675 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2983 23:19:49.300535 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2984 23:19:49.303841 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2985 23:19:49.303945
2986 23:19:49.304015
2987 23:19:49.304078 ==
2988 23:19:49.306709 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 23:19:49.313835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 23:19:49.313935 ==
2991 23:19:49.314005
2992 23:19:49.314068
2993 23:19:49.314128 TX Vref Scan disable
2994 23:19:49.317312 == TX Byte 0 ==
2995 23:19:49.320327 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2996 23:19:49.323948 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2997 23:19:49.327245 == TX Byte 1 ==
2998 23:19:49.330498 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2999 23:19:49.333899 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3000 23:19:49.337190 ==
3001 23:19:49.340312 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 23:19:49.343573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 23:19:49.343659 ==
3004 23:19:49.355899 TX Vref=22, minBit 0, minWin=24, winSum=408
3005 23:19:49.358854 TX Vref=24, minBit 1, minWin=25, winSum=413
3006 23:19:49.362260 TX Vref=26, minBit 2, minWin=25, winSum=420
3007 23:19:49.365887 TX Vref=28, minBit 1, minWin=25, winSum=424
3008 23:19:49.369030 TX Vref=30, minBit 5, minWin=25, winSum=425
3009 23:19:49.372291 TX Vref=32, minBit 3, minWin=25, winSum=422
3010 23:19:49.379132 [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 30
3011 23:19:49.379217
3012 23:19:49.382218 Final TX Range 1 Vref 30
3013 23:19:49.382329
3014 23:19:49.382423 ==
3015 23:19:49.385851 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 23:19:49.388899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 23:19:49.388984 ==
3018 23:19:49.389051
3019 23:19:49.391983
3020 23:19:49.392067 TX Vref Scan disable
3021 23:19:49.395538 == TX Byte 0 ==
3022 23:19:49.399051 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3023 23:19:49.402417 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3024 23:19:49.405714 == TX Byte 1 ==
3025 23:19:49.408986 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3026 23:19:49.412384 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3027 23:19:49.412604
3028 23:19:49.415672 [DATLAT]
3029 23:19:49.415860 Freq=1200, CH0 RK1
3030 23:19:49.415971
3031 23:19:49.419164 DATLAT Default: 0xd
3032 23:19:49.419361 0, 0xFFFF, sum = 0
3033 23:19:49.422573 1, 0xFFFF, sum = 0
3034 23:19:49.422756 2, 0xFFFF, sum = 0
3035 23:19:49.426112 3, 0xFFFF, sum = 0
3036 23:19:49.426347 4, 0xFFFF, sum = 0
3037 23:19:49.429216 5, 0xFFFF, sum = 0
3038 23:19:49.429453 6, 0xFFFF, sum = 0
3039 23:19:49.432514 7, 0xFFFF, sum = 0
3040 23:19:49.432745 8, 0xFFFF, sum = 0
3041 23:19:49.435741 9, 0xFFFF, sum = 0
3042 23:19:49.439372 10, 0xFFFF, sum = 0
3043 23:19:49.439582 11, 0xFFFF, sum = 0
3044 23:19:49.442549 12, 0x0, sum = 1
3045 23:19:49.442882 13, 0x0, sum = 2
3046 23:19:49.443095 14, 0x0, sum = 3
3047 23:19:49.445699 15, 0x0, sum = 4
3048 23:19:49.445951 best_step = 13
3049 23:19:49.446202
3050 23:19:49.449150 ==
3051 23:19:49.449491 Dram Type= 6, Freq= 0, CH_0, rank 1
3052 23:19:49.455790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 23:19:49.456236 ==
3054 23:19:49.456535 RX Vref Scan: 0
3055 23:19:49.456874
3056 23:19:49.459544 RX Vref 0 -> 0, step: 1
3057 23:19:49.459962
3058 23:19:49.462490 RX Delay -21 -> 252, step: 4
3059 23:19:49.466099 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3060 23:19:49.469777 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3061 23:19:49.476139 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3062 23:19:49.479433 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3063 23:19:49.482977 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3064 23:19:49.486040 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3065 23:19:49.489971 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3066 23:19:49.496584 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3067 23:19:49.499940 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3068 23:19:49.503069 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3069 23:19:49.506562 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3070 23:19:49.509797 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3071 23:19:49.513333 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3072 23:19:49.519771 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3073 23:19:49.523100 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3074 23:19:49.526679 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3075 23:19:49.527221 ==
3076 23:19:49.529776 Dram Type= 6, Freq= 0, CH_0, rank 1
3077 23:19:49.533147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 23:19:49.536302 ==
3079 23:19:49.536804 DQS Delay:
3080 23:19:49.537243 DQS0 = 0, DQS1 = 0
3081 23:19:49.539699 DQM Delay:
3082 23:19:49.540138 DQM0 = 119, DQM1 = 108
3083 23:19:49.542974 DQ Delay:
3084 23:19:49.546451 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3085 23:19:49.549608 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =124
3086 23:19:49.553238 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3087 23:19:49.555986 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3088 23:19:49.556421
3089 23:19:49.556811
3090 23:19:49.562831 [DQSOSCAuto] RK1, (LSB)MR18= 0xff6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3091 23:19:49.566045 CH0 RK1: MR19=403, MR18=FF6
3092 23:19:49.572917 CH0_RK1: MR19=0x403, MR18=0xFF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3093 23:19:49.575828 [RxdqsGatingPostProcess] freq 1200
3094 23:19:49.582735 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3095 23:19:49.582927 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 23:19:49.585870 best DQS1 dly(2T, 0.5T) = (0, 11)
3097 23:19:49.589373 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 23:19:49.593122 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3099 23:19:49.596481 best DQS0 dly(2T, 0.5T) = (0, 11)
3100 23:19:49.599687 best DQS1 dly(2T, 0.5T) = (0, 11)
3101 23:19:49.603314 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3102 23:19:49.606556 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3103 23:19:49.609949 Pre-setting of DQS Precalculation
3104 23:19:49.613083 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3105 23:19:49.613530 ==
3106 23:19:49.616552 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 23:19:49.623191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 23:19:49.623724 ==
3109 23:19:49.626824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3110 23:19:49.633125 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3111 23:19:49.642130 [CA 0] Center 38 (8~68) winsize 61
3112 23:19:49.645181 [CA 1] Center 37 (7~68) winsize 62
3113 23:19:49.648550 [CA 2] Center 35 (5~65) winsize 61
3114 23:19:49.652305 [CA 3] Center 34 (4~64) winsize 61
3115 23:19:49.655572 [CA 4] Center 34 (4~64) winsize 61
3116 23:19:49.658891 [CA 5] Center 33 (3~64) winsize 62
3117 23:19:49.659454
3118 23:19:49.662065 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3119 23:19:49.662687
3120 23:19:49.665181 [CATrainingPosCal] consider 1 rank data
3121 23:19:49.668706 u2DelayCellTimex100 = 270/100 ps
3122 23:19:49.672131 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3123 23:19:49.675242 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3124 23:19:49.681631 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3125 23:19:49.685186 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 23:19:49.688181 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3127 23:19:49.691819 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3128 23:19:49.692322
3129 23:19:49.695085 CA PerBit enable=1, Macro0, CA PI delay=33
3130 23:19:49.695579
3131 23:19:49.698826 [CBTSetCACLKResult] CA Dly = 33
3132 23:19:49.699363 CS Dly: 5 (0~36)
3133 23:19:49.702357 ==
3134 23:19:49.702911 Dram Type= 6, Freq= 0, CH_1, rank 1
3135 23:19:49.708619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 23:19:49.709089 ==
3137 23:19:49.712015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3138 23:19:49.718337 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3139 23:19:49.727982 [CA 0] Center 38 (8~68) winsize 61
3140 23:19:49.731045 [CA 1] Center 38 (8~68) winsize 61
3141 23:19:49.734614 [CA 2] Center 35 (5~66) winsize 62
3142 23:19:49.737924 [CA 3] Center 34 (4~65) winsize 62
3143 23:19:49.741243 [CA 4] Center 34 (5~64) winsize 60
3144 23:19:49.744859 [CA 5] Center 34 (4~64) winsize 61
3145 23:19:49.745281
3146 23:19:49.747665 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3147 23:19:49.748136
3148 23:19:49.750977 [CATrainingPosCal] consider 2 rank data
3149 23:19:49.754496 u2DelayCellTimex100 = 270/100 ps
3150 23:19:49.757602 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3151 23:19:49.761260 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3152 23:19:49.767854 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3153 23:19:49.771131 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3154 23:19:49.774226 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3155 23:19:49.777449 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3156 23:19:49.777874
3157 23:19:49.780817 CA PerBit enable=1, Macro0, CA PI delay=34
3158 23:19:49.781313
3159 23:19:49.784295 [CBTSetCACLKResult] CA Dly = 34
3160 23:19:49.784879 CS Dly: 6 (0~39)
3161 23:19:49.785269
3162 23:19:49.787532 ----->DramcWriteLeveling(PI) begin...
3163 23:19:49.790904 ==
3164 23:19:49.791326 Dram Type= 6, Freq= 0, CH_1, rank 0
3165 23:19:49.797850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 23:19:49.798318 ==
3167 23:19:49.800919 Write leveling (Byte 0): 24 => 24
3168 23:19:49.804425 Write leveling (Byte 1): 26 => 26
3169 23:19:49.804886 DramcWriteLeveling(PI) end<-----
3170 23:19:49.807464
3171 23:19:49.807889 ==
3172 23:19:49.811240 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 23:19:49.814687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 23:19:49.815230 ==
3175 23:19:49.817776 [Gating] SW mode calibration
3176 23:19:49.824775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3177 23:19:49.827861 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3178 23:19:49.834799 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 23:19:49.837665 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 23:19:49.841102 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 23:19:49.847619 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 23:19:49.851200 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 23:19:49.854552 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3184 23:19:49.861285 0 15 24 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (1 0)
3185 23:19:49.864745 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 23:19:49.868068 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 23:19:49.874726 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 23:19:49.878171 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 23:19:49.881524 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 23:19:49.884905 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 23:19:49.891020 1 0 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3192 23:19:49.894452 1 0 24 | B1->B0 | 3535 4343 | 0 0 | (1 1) (0 0)
3193 23:19:49.898259 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 23:19:49.904532 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 23:19:49.907857 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 23:19:49.911448 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 23:19:49.918376 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 23:19:49.921362 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 23:19:49.924907 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 23:19:49.931478 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3201 23:19:49.934765 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3202 23:19:49.938095 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 23:19:49.944713 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 23:19:49.948891 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 23:19:49.951588 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 23:19:49.958725 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 23:19:49.961575 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 23:19:49.965121 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 23:19:49.968264 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 23:19:49.974795 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 23:19:49.978419 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 23:19:49.981354 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:19:49.988229 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:19:49.991268 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:19:49.995145 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:19:50.001505 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3217 23:19:50.004824 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3218 23:19:50.008177 Total UI for P1: 0, mck2ui 16
3219 23:19:50.012055 best dqsien dly found for B0: ( 1, 3, 24)
3220 23:19:50.015463 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 23:19:50.018337 Total UI for P1: 0, mck2ui 16
3222 23:19:50.021777 best dqsien dly found for B1: ( 1, 3, 26)
3223 23:19:50.024963 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3224 23:19:50.028557 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3225 23:19:50.029236
3226 23:19:50.031823 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3227 23:19:50.038564 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3228 23:19:50.038959 [Gating] SW calibration Done
3229 23:19:50.039274 ==
3230 23:19:50.041931 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 23:19:50.048018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 23:19:50.048417 ==
3233 23:19:50.048785 RX Vref Scan: 0
3234 23:19:50.049211
3235 23:19:50.051675 RX Vref 0 -> 0, step: 1
3236 23:19:50.052182
3237 23:19:50.054870 RX Delay -40 -> 252, step: 8
3238 23:19:50.058565 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3239 23:19:50.061675 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3240 23:19:50.065168 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3241 23:19:50.071719 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3242 23:19:50.074888 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3243 23:19:50.078030 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3244 23:19:50.081297 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3245 23:19:50.084744 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3246 23:19:50.091258 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3247 23:19:50.094872 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3248 23:19:50.098303 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3249 23:19:50.101619 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3250 23:19:50.104494 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3251 23:19:50.111342 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3252 23:19:50.114965 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3253 23:19:50.117712 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3254 23:19:50.118198 ==
3255 23:19:50.121463 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 23:19:50.124503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 23:19:50.124970 ==
3258 23:19:50.128278 DQS Delay:
3259 23:19:50.128739 DQS0 = 0, DQS1 = 0
3260 23:19:50.131309 DQM Delay:
3261 23:19:50.131776 DQM0 = 121, DQM1 = 113
3262 23:19:50.132127 DQ Delay:
3263 23:19:50.138021 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3264 23:19:50.141532 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3265 23:19:50.144922 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
3266 23:19:50.148350 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3267 23:19:50.148808
3268 23:19:50.149168
3269 23:19:50.149538 ==
3270 23:19:50.151465 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 23:19:50.154861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 23:19:50.155390 ==
3273 23:19:50.155730
3274 23:19:50.156047
3275 23:19:50.158334 TX Vref Scan disable
3276 23:19:50.161524 == TX Byte 0 ==
3277 23:19:50.165061 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3278 23:19:50.168553 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3279 23:19:50.171590 == TX Byte 1 ==
3280 23:19:50.175048 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3281 23:19:50.178267 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3282 23:19:50.178692 ==
3283 23:19:50.181557 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 23:19:50.184560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 23:19:50.187953 ==
3286 23:19:50.198036 TX Vref=22, minBit 1, minWin=24, winSum=407
3287 23:19:50.200937 TX Vref=24, minBit 9, minWin=24, winSum=411
3288 23:19:50.204478 TX Vref=26, minBit 9, minWin=25, winSum=419
3289 23:19:50.207693 TX Vref=28, minBit 9, minWin=25, winSum=422
3290 23:19:50.211088 TX Vref=30, minBit 1, minWin=26, winSum=424
3291 23:19:50.217799 TX Vref=32, minBit 9, minWin=25, winSum=423
3292 23:19:50.221308 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 30
3293 23:19:50.221746
3294 23:19:50.224213 Final TX Range 1 Vref 30
3295 23:19:50.224638
3296 23:19:50.225026 ==
3297 23:19:50.228633 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 23:19:50.230750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 23:19:50.231178 ==
3300 23:19:50.231513
3301 23:19:50.234400
3302 23:19:50.234837 TX Vref Scan disable
3303 23:19:50.237700 == TX Byte 0 ==
3304 23:19:50.241380 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3305 23:19:50.244418 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3306 23:19:50.247852 == TX Byte 1 ==
3307 23:19:50.251051 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3308 23:19:50.254738 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3309 23:19:50.255170
3310 23:19:50.258268 [DATLAT]
3311 23:19:50.258800 Freq=1200, CH1 RK0
3312 23:19:50.259148
3313 23:19:50.261045 DATLAT Default: 0xd
3314 23:19:50.261476 0, 0xFFFF, sum = 0
3315 23:19:50.264220 1, 0xFFFF, sum = 0
3316 23:19:50.264682 2, 0xFFFF, sum = 0
3317 23:19:50.267799 3, 0xFFFF, sum = 0
3318 23:19:50.268341 4, 0xFFFF, sum = 0
3319 23:19:50.271383 5, 0xFFFF, sum = 0
3320 23:19:50.271928 6, 0xFFFF, sum = 0
3321 23:19:50.274477 7, 0xFFFF, sum = 0
3322 23:19:50.277757 8, 0xFFFF, sum = 0
3323 23:19:50.278193 9, 0xFFFF, sum = 0
3324 23:19:50.281207 10, 0xFFFF, sum = 0
3325 23:19:50.281643 11, 0xFFFF, sum = 0
3326 23:19:50.284030 12, 0x0, sum = 1
3327 23:19:50.284428 13, 0x0, sum = 2
3328 23:19:50.284780 14, 0x0, sum = 3
3329 23:19:50.287764 15, 0x0, sum = 4
3330 23:19:50.288155 best_step = 13
3331 23:19:50.288467
3332 23:19:50.291039 ==
3333 23:19:50.291433 Dram Type= 6, Freq= 0, CH_1, rank 0
3334 23:19:50.297783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3335 23:19:50.298185 ==
3336 23:19:50.298489 RX Vref Scan: 1
3337 23:19:50.298773
3338 23:19:50.301029 Set Vref Range= 32 -> 127
3339 23:19:50.301404
3340 23:19:50.304187 RX Vref 32 -> 127, step: 1
3341 23:19:50.304567
3342 23:19:50.307522 RX Delay -5 -> 252, step: 4
3343 23:19:50.307899
3344 23:19:50.311101 Set Vref, RX VrefLevel [Byte0]: 32
3345 23:19:50.314932 [Byte1]: 32
3346 23:19:50.315431
3347 23:19:50.317899 Set Vref, RX VrefLevel [Byte0]: 33
3348 23:19:50.321416 [Byte1]: 33
3349 23:19:50.321830
3350 23:19:50.324503 Set Vref, RX VrefLevel [Byte0]: 34
3351 23:19:50.327836 [Byte1]: 34
3352 23:19:50.331448
3353 23:19:50.331825 Set Vref, RX VrefLevel [Byte0]: 35
3354 23:19:50.334831 [Byte1]: 35
3355 23:19:50.339469
3356 23:19:50.339846 Set Vref, RX VrefLevel [Byte0]: 36
3357 23:19:50.342592 [Byte1]: 36
3358 23:19:50.347664
3359 23:19:50.348158 Set Vref, RX VrefLevel [Byte0]: 37
3360 23:19:50.350509 [Byte1]: 37
3361 23:19:50.355236
3362 23:19:50.355709 Set Vref, RX VrefLevel [Byte0]: 38
3363 23:19:50.358445 [Byte1]: 38
3364 23:19:50.363216
3365 23:19:50.363634 Set Vref, RX VrefLevel [Byte0]: 39
3366 23:19:50.366545 [Byte1]: 39
3367 23:19:50.371481
3368 23:19:50.371994 Set Vref, RX VrefLevel [Byte0]: 40
3369 23:19:50.374478 [Byte1]: 40
3370 23:19:50.378544
3371 23:19:50.379049 Set Vref, RX VrefLevel [Byte0]: 41
3372 23:19:50.384907 [Byte1]: 41
3373 23:19:50.385322
3374 23:19:50.388517 Set Vref, RX VrefLevel [Byte0]: 42
3375 23:19:50.391700 [Byte1]: 42
3376 23:19:50.392117
3377 23:19:50.395134 Set Vref, RX VrefLevel [Byte0]: 43
3378 23:19:50.398240 [Byte1]: 43
3379 23:19:50.402138
3380 23:19:50.402551 Set Vref, RX VrefLevel [Byte0]: 44
3381 23:19:50.405587 [Byte1]: 44
3382 23:19:50.410150
3383 23:19:50.410663 Set Vref, RX VrefLevel [Byte0]: 45
3384 23:19:50.413426 [Byte1]: 45
3385 23:19:50.418159
3386 23:19:50.418669 Set Vref, RX VrefLevel [Byte0]: 46
3387 23:19:50.421590 [Byte1]: 46
3388 23:19:50.426040
3389 23:19:50.426551 Set Vref, RX VrefLevel [Byte0]: 47
3390 23:19:50.429041 [Byte1]: 47
3391 23:19:50.433727
3392 23:19:50.434139 Set Vref, RX VrefLevel [Byte0]: 48
3393 23:19:50.436954 [Byte1]: 48
3394 23:19:50.441383
3395 23:19:50.441793 Set Vref, RX VrefLevel [Byte0]: 49
3396 23:19:50.444496 [Byte1]: 49
3397 23:19:50.449451
3398 23:19:50.449888 Set Vref, RX VrefLevel [Byte0]: 50
3399 23:19:50.452289 [Byte1]: 50
3400 23:19:50.457294
3401 23:19:50.457715 Set Vref, RX VrefLevel [Byte0]: 51
3402 23:19:50.460483 [Byte1]: 51
3403 23:19:50.465096
3404 23:19:50.465617 Set Vref, RX VrefLevel [Byte0]: 52
3405 23:19:50.468461 [Byte1]: 52
3406 23:19:50.473305
3407 23:19:50.473858 Set Vref, RX VrefLevel [Byte0]: 53
3408 23:19:50.476564 [Byte1]: 53
3409 23:19:50.480718
3410 23:19:50.481141 Set Vref, RX VrefLevel [Byte0]: 54
3411 23:19:50.484013 [Byte1]: 54
3412 23:19:50.488829
3413 23:19:50.489251 Set Vref, RX VrefLevel [Byte0]: 55
3414 23:19:50.492342 [Byte1]: 55
3415 23:19:50.496291
3416 23:19:50.496863 Set Vref, RX VrefLevel [Byte0]: 56
3417 23:19:50.500104 [Byte1]: 56
3418 23:19:50.504577
3419 23:19:50.505145 Set Vref, RX VrefLevel [Byte0]: 57
3420 23:19:50.507872 [Byte1]: 57
3421 23:19:50.512266
3422 23:19:50.512715 Set Vref, RX VrefLevel [Byte0]: 58
3423 23:19:50.515724 [Byte1]: 58
3424 23:19:50.519933
3425 23:19:50.520440 Set Vref, RX VrefLevel [Byte0]: 59
3426 23:19:50.523282 [Byte1]: 59
3427 23:19:50.528050
3428 23:19:50.528541 Set Vref, RX VrefLevel [Byte0]: 60
3429 23:19:50.530914 [Byte1]: 60
3430 23:19:50.536126
3431 23:19:50.536690 Set Vref, RX VrefLevel [Byte0]: 61
3432 23:19:50.539176 [Byte1]: 61
3433 23:19:50.543657
3434 23:19:50.544205 Set Vref, RX VrefLevel [Byte0]: 62
3435 23:19:50.546653 [Byte1]: 62
3436 23:19:50.551683
3437 23:19:50.552105 Set Vref, RX VrefLevel [Byte0]: 63
3438 23:19:50.554489 [Byte1]: 63
3439 23:19:50.559070
3440 23:19:50.559493 Set Vref, RX VrefLevel [Byte0]: 64
3441 23:19:50.562447 [Byte1]: 64
3442 23:19:50.567314
3443 23:19:50.567759 Set Vref, RX VrefLevel [Byte0]: 65
3444 23:19:50.570597 [Byte1]: 65
3445 23:19:50.575125
3446 23:19:50.575550 Set Vref, RX VrefLevel [Byte0]: 66
3447 23:19:50.578545 [Byte1]: 66
3448 23:19:50.582646
3449 23:19:50.583069 Set Vref, RX VrefLevel [Byte0]: 67
3450 23:19:50.586149 [Byte1]: 67
3451 23:19:50.590710
3452 23:19:50.591129 Final RX Vref Byte 0 = 52 to rank0
3453 23:19:50.594021 Final RX Vref Byte 1 = 52 to rank0
3454 23:19:50.597169 Final RX Vref Byte 0 = 52 to rank1
3455 23:19:50.601020 Final RX Vref Byte 1 = 52 to rank1==
3456 23:19:50.603899 Dram Type= 6, Freq= 0, CH_1, rank 0
3457 23:19:50.610473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 23:19:50.610972 ==
3459 23:19:50.611319 DQS Delay:
3460 23:19:50.611636 DQS0 = 0, DQS1 = 0
3461 23:19:50.613996 DQM Delay:
3462 23:19:50.614528 DQM0 = 120, DQM1 = 112
3463 23:19:50.617419 DQ Delay:
3464 23:19:50.620847 DQ0 =122, DQ1 =114, DQ2 =112, DQ3 =120
3465 23:19:50.624412 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3466 23:19:50.627607 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3467 23:19:50.630867 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =120
3468 23:19:50.631294
3469 23:19:50.631634
3470 23:19:50.637270 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3471 23:19:51.771822 CH1 RK0: MR19=404, MR18=13
3472 23:19:51.772939 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3473 23:19:51.773514
3474 23:19:51.774050 ----->DramcWriteLeveling(PI) begin...
3475 23:19:51.774557 ==
3476 23:19:51.775137 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 23:19:51.775649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 23:19:51.776175 ==
3479 23:19:51.776690 Write leveling (Byte 0): 27 => 27
3480 23:19:51.777141 Write leveling (Byte 1): 28 => 28
3481 23:19:51.777298 DramcWriteLeveling(PI) end<-----
3482 23:19:51.777437
3483 23:19:51.777570 ==
3484 23:19:51.777702 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 23:19:51.777807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 23:19:51.777909 ==
3487 23:19:51.778019 [Gating] SW mode calibration
3488 23:19:51.778130 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3489 23:19:51.778234 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3490 23:19:51.778396 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 23:19:51.778529 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 23:19:51.778662 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 23:19:51.778794 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 23:19:51.778900 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 23:19:51.779004 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3496 23:19:51.779109 0 15 24 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 0)
3497 23:19:51.779221 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3498 23:19:51.779322 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 23:19:51.779432 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 23:19:51.779533 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 23:19:51.779642 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 23:19:51.779773 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 23:19:51.779881 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3504 23:19:51.779983 1 0 24 | B1->B0 | 3d3d 2a2a | 0 0 | (1 1) (0 0)
3505 23:19:51.780091 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 23:19:51.780192 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 23:19:51.780298 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 23:19:51.780400 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 23:19:51.780505 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 23:19:51.780612 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 23:19:51.780735 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 23:19:51.780858 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3513 23:19:51.780974 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3514 23:19:51.781082 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 23:19:51.781181 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 23:19:51.781281 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 23:19:51.781371 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 23:19:51.781459 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 23:19:51.781577 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 23:19:51.781663 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 23:19:51.781748 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 23:19:51.781833 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 23:19:51.781918 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 23:19:51.782003 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 23:19:51.782088 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 23:19:51.782172 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 23:19:51.782273 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 23:19:51.782359 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3529 23:19:51.782445 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 23:19:51.782531 Total UI for P1: 0, mck2ui 16
3531 23:19:51.782618 best dqsien dly found for B0: ( 1, 3, 24)
3532 23:19:51.782703 Total UI for P1: 0, mck2ui 16
3533 23:19:51.782790 best dqsien dly found for B1: ( 1, 3, 24)
3534 23:19:51.782876 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3535 23:19:51.782976 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3536 23:19:51.783059
3537 23:19:51.783158 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3538 23:19:51.783245 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3539 23:19:51.783330 [Gating] SW calibration Done
3540 23:19:51.783415 ==
3541 23:19:51.783501 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 23:19:51.783587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 23:19:51.783673 ==
3544 23:19:51.783758 RX Vref Scan: 0
3545 23:19:51.783843
3546 23:19:51.783960 RX Vref 0 -> 0, step: 1
3547 23:19:51.784077
3548 23:19:51.784195 RX Delay -40 -> 252, step: 8
3549 23:19:51.784281 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3550 23:19:51.784368 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3551 23:19:51.784456 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3552 23:19:51.784543 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3553 23:19:51.784628 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3554 23:19:51.784724 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3555 23:19:51.784841 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3556 23:19:51.784927 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3557 23:19:51.785013 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3558 23:19:51.785099 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3559 23:19:51.785185 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3560 23:19:51.785271 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3561 23:19:51.785357 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3562 23:19:51.785443 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3563 23:19:51.785528 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3564 23:19:51.785614 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3565 23:19:51.785698 ==
3566 23:19:51.785784 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 23:19:51.785869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 23:19:51.785955 ==
3569 23:19:51.786039 DQS Delay:
3570 23:19:51.786124 DQS0 = 0, DQS1 = 0
3571 23:19:51.786209 DQM Delay:
3572 23:19:51.786295 DQM0 = 120, DQM1 = 113
3573 23:19:51.786380 DQ Delay:
3574 23:19:51.786465 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3575 23:19:51.786761 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3576 23:19:51.786852 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3577 23:19:51.786940 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3578 23:19:51.787026
3579 23:19:51.787111
3580 23:19:51.787195 ==
3581 23:19:51.787281 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 23:19:51.787367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 23:19:51.787453 ==
3584 23:19:51.787537
3585 23:19:51.787622
3586 23:19:51.787707 TX Vref Scan disable
3587 23:19:51.787792 == TX Byte 0 ==
3588 23:19:51.787878 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3589 23:19:51.787963 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3590 23:19:51.788048 == TX Byte 1 ==
3591 23:19:51.788134 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3592 23:19:51.788220 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3593 23:19:51.788305 ==
3594 23:19:51.788391 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 23:19:51.788477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 23:19:51.788563 ==
3597 23:19:51.788656 TX Vref=22, minBit 1, minWin=25, winSum=419
3598 23:19:51.788745 TX Vref=24, minBit 1, minWin=25, winSum=423
3599 23:19:51.788831 TX Vref=26, minBit 3, minWin=25, winSum=426
3600 23:19:51.788917 TX Vref=28, minBit 7, minWin=26, winSum=433
3601 23:19:51.789003 TX Vref=30, minBit 9, minWin=26, winSum=430
3602 23:19:51.789089 TX Vref=32, minBit 10, minWin=25, winSum=424
3603 23:19:51.789176 [TxChooseVref] Worse bit 7, Min win 26, Win sum 433, Final Vref 28
3604 23:19:51.789261
3605 23:19:51.789346 Final TX Range 1 Vref 28
3606 23:19:51.789432
3607 23:19:51.789516 ==
3608 23:19:51.789602 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 23:19:51.789688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 23:19:51.789773 ==
3611 23:19:51.789857
3612 23:19:51.789941
3613 23:19:51.790026 TX Vref Scan disable
3614 23:19:51.790111 == TX Byte 0 ==
3615 23:19:51.790197 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3616 23:19:51.790283 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3617 23:19:51.790369 == TX Byte 1 ==
3618 23:19:51.790454 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3619 23:19:51.790540 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3620 23:19:51.790625
3621 23:19:51.790709 [DATLAT]
3622 23:19:51.790799 Freq=1200, CH1 RK1
3623 23:19:51.790898
3624 23:19:51.790993 DATLAT Default: 0xd
3625 23:19:51.791096 0, 0xFFFF, sum = 0
3626 23:19:51.791201 1, 0xFFFF, sum = 0
3627 23:19:51.791307 2, 0xFFFF, sum = 0
3628 23:19:51.791421 3, 0xFFFF, sum = 0
3629 23:19:51.791528 4, 0xFFFF, sum = 0
3630 23:19:51.791636 5, 0xFFFF, sum = 0
3631 23:19:51.791743 6, 0xFFFF, sum = 0
3632 23:19:51.791848 7, 0xFFFF, sum = 0
3633 23:19:51.791953 8, 0xFFFF, sum = 0
3634 23:19:51.792063 9, 0xFFFF, sum = 0
3635 23:19:51.792165 10, 0xFFFF, sum = 0
3636 23:19:51.792273 11, 0xFFFF, sum = 0
3637 23:19:51.792375 12, 0x0, sum = 1
3638 23:19:51.792482 13, 0x0, sum = 2
3639 23:19:51.792584 14, 0x0, sum = 3
3640 23:19:51.792694 15, 0x0, sum = 4
3641 23:19:51.792803 best_step = 13
3642 23:19:51.792906
3643 23:19:51.793011 ==
3644 23:19:51.793113 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 23:19:51.793220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 23:19:51.793322 ==
3647 23:19:51.793429 RX Vref Scan: 0
3648 23:19:51.793530
3649 23:19:51.793636 RX Vref 0 -> 0, step: 1
3650 23:19:51.793738
3651 23:19:51.793845 RX Delay -13 -> 252, step: 4
3652 23:19:51.793946 iDelay=195, Bit 0, Center 124 (67 ~ 182) 116
3653 23:19:51.794049 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3654 23:19:51.794157 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3655 23:19:51.794259 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3656 23:19:51.794366 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3657 23:19:51.794466 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3658 23:19:51.794573 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3659 23:19:51.794674 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3660 23:19:51.794780 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3661 23:19:51.794881 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3662 23:19:51.794974 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3663 23:19:51.795071 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3664 23:19:51.795175 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3665 23:19:51.795279 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3666 23:19:51.795387 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3667 23:19:51.795488 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3668 23:19:51.795593 ==
3669 23:19:51.795693 Dram Type= 6, Freq= 0, CH_1, rank 1
3670 23:19:51.795794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3671 23:19:51.795901 ==
3672 23:19:51.796003 DQS Delay:
3673 23:19:51.796106 DQS0 = 0, DQS1 = 0
3674 23:19:51.796209 DQM Delay:
3675 23:19:51.796315 DQM0 = 119, DQM1 = 113
3676 23:19:51.796418 DQ Delay:
3677 23:19:51.796516 DQ0 =124, DQ1 =114, DQ2 =108, DQ3 =118
3678 23:19:51.796617 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3679 23:19:51.796735 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3680 23:19:51.796836 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3681 23:19:51.796931
3682 23:19:51.797033
3683 23:19:51.797134 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3684 23:19:51.797239 CH1 RK1: MR19=403, MR18=BF0
3685 23:19:51.797336 CH1_RK1: MR19=0x403, MR18=0xBF0, DQSOSC=405, MR23=63, INC=39, DEC=26
3686 23:19:51.797448 [RxdqsGatingPostProcess] freq 1200
3687 23:19:51.797558 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3688 23:19:51.797661 best DQS0 dly(2T, 0.5T) = (0, 11)
3689 23:19:51.797776 best DQS1 dly(2T, 0.5T) = (0, 11)
3690 23:19:51.797884 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3691 23:19:51.797991 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3692 23:19:51.798100 best DQS0 dly(2T, 0.5T) = (0, 11)
3693 23:19:51.798205 best DQS1 dly(2T, 0.5T) = (0, 11)
3694 23:19:51.798312 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3695 23:19:51.798422 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3696 23:19:51.798532 Pre-setting of DQS Precalculation
3697 23:19:51.798642 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3698 23:19:51.798752 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3699 23:19:51.798860 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3700 23:19:51.798969
3701 23:19:51.799086
3702 23:19:51.799203 [Calibration Summary] 2400 Mbps
3703 23:19:51.799267 CH 0, Rank 0
3704 23:19:51.799327 SW Impedance : PASS
3705 23:19:51.799386 DUTY Scan : NO K
3706 23:19:51.799444 ZQ Calibration : PASS
3707 23:19:51.799499 Jitter Meter : NO K
3708 23:19:51.799556 CBT Training : PASS
3709 23:19:51.799612 Write leveling : PASS
3710 23:19:51.799668 RX DQS gating : PASS
3711 23:19:51.799724 RX DQ/DQS(RDDQC) : PASS
3712 23:19:51.799779 TX DQ/DQS : PASS
3713 23:19:51.799835 RX DATLAT : PASS
3714 23:19:51.799892 RX DQ/DQS(Engine): PASS
3715 23:19:51.800151 TX OE : NO K
3716 23:19:51.800219 All Pass.
3717 23:19:51.800277
3718 23:19:51.800334 CH 0, Rank 1
3719 23:19:51.800390 SW Impedance : PASS
3720 23:19:51.800447 DUTY Scan : NO K
3721 23:19:51.800503 ZQ Calibration : PASS
3722 23:19:51.800559 Jitter Meter : NO K
3723 23:19:51.800615 CBT Training : PASS
3724 23:19:51.800682 Write leveling : PASS
3725 23:19:51.800739 RX DQS gating : PASS
3726 23:19:51.800796 RX DQ/DQS(RDDQC) : PASS
3727 23:19:51.800851 TX DQ/DQS : PASS
3728 23:19:51.800907 RX DATLAT : PASS
3729 23:19:51.800963 RX DQ/DQS(Engine): PASS
3730 23:19:51.801018 TX OE : NO K
3731 23:19:51.801074 All Pass.
3732 23:19:51.801130
3733 23:19:51.801185 CH 1, Rank 0
3734 23:19:51.801241 SW Impedance : PASS
3735 23:19:51.801295 DUTY Scan : NO K
3736 23:19:51.801350 ZQ Calibration : PASS
3737 23:19:51.801405 Jitter Meter : NO K
3738 23:19:51.801460 CBT Training : PASS
3739 23:19:51.801514 Write leveling : PASS
3740 23:19:51.801568 RX DQS gating : PASS
3741 23:19:51.801622 RX DQ/DQS(RDDQC) : PASS
3742 23:19:51.801678 TX DQ/DQS : PASS
3743 23:19:51.801732 RX DATLAT : PASS
3744 23:19:51.801787 RX DQ/DQS(Engine): PASS
3745 23:19:51.801842 TX OE : NO K
3746 23:19:51.801898 All Pass.
3747 23:19:51.801966
3748 23:19:51.802020 CH 1, Rank 1
3749 23:19:51.802073 SW Impedance : PASS
3750 23:19:51.802128 DUTY Scan : NO K
3751 23:19:51.802181 ZQ Calibration : PASS
3752 23:19:51.802235 Jitter Meter : NO K
3753 23:19:51.802289 CBT Training : PASS
3754 23:19:51.802343 Write leveling : PASS
3755 23:19:51.802397 RX DQS gating : PASS
3756 23:19:51.802451 RX DQ/DQS(RDDQC) : PASS
3757 23:19:51.802505 TX DQ/DQS : PASS
3758 23:19:51.802559 RX DATLAT : PASS
3759 23:19:51.802614 RX DQ/DQS(Engine): PASS
3760 23:19:51.802668 TX OE : NO K
3761 23:19:51.802722 All Pass.
3762 23:19:51.802776
3763 23:19:51.802829 DramC Write-DBI off
3764 23:19:51.802884 PER_BANK_REFRESH: Hybrid Mode
3765 23:19:51.802939 TX_TRACKING: ON
3766 23:19:51.802993 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3767 23:19:51.803049 [FAST_K] Save calibration result to emmc
3768 23:19:51.803103 dramc_set_vcore_voltage set vcore to 650000
3769 23:19:51.803157 Read voltage for 600, 5
3770 23:19:51.803211 Vio18 = 0
3771 23:19:51.803265 Vcore = 650000
3772 23:19:51.803319 Vdram = 0
3773 23:19:51.803372 Vddq = 0
3774 23:19:51.803427 Vmddr = 0
3775 23:19:51.803481 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3776 23:19:51.803553 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3777 23:19:51.803609 MEM_TYPE=3, freq_sel=19
3778 23:19:51.803665 sv_algorithm_assistance_LP4_1600
3779 23:19:51.803724 ============ PULL DRAM RESETB DOWN ============
3780 23:19:51.803807 ========== PULL DRAM RESETB DOWN end =========
3781 23:19:51.803864 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3782 23:19:51.803919 ===================================
3783 23:19:51.803974 LPDDR4 DRAM CONFIGURATION
3784 23:19:51.804030 ===================================
3785 23:19:51.804085 EX_ROW_EN[0] = 0x0
3786 23:19:51.804140 EX_ROW_EN[1] = 0x0
3787 23:19:51.804195 LP4Y_EN = 0x0
3788 23:19:51.804251 WORK_FSP = 0x0
3789 23:19:51.804306 WL = 0x2
3790 23:19:51.804361 RL = 0x2
3791 23:19:51.804417 BL = 0x2
3792 23:19:51.804472 RPST = 0x0
3793 23:19:51.804527 RD_PRE = 0x0
3794 23:19:51.804582 WR_PRE = 0x1
3795 23:19:51.804638 WR_PST = 0x0
3796 23:19:51.804719 DBI_WR = 0x0
3797 23:19:51.804773 DBI_RD = 0x0
3798 23:19:51.804827 OTF = 0x1
3799 23:19:51.804881 ===================================
3800 23:19:51.804934 ===================================
3801 23:19:51.804988 ANA top config
3802 23:19:51.805042 ===================================
3803 23:19:51.805096 DLL_ASYNC_EN = 0
3804 23:19:51.805150 ALL_SLAVE_EN = 1
3805 23:19:51.805204 NEW_RANK_MODE = 1
3806 23:19:51.805281 DLL_IDLE_MODE = 1
3807 23:19:51.805382 LP45_APHY_COMB_EN = 1
3808 23:19:51.805464 TX_ODT_DIS = 1
3809 23:19:51.805520 NEW_8X_MODE = 1
3810 23:19:51.805575 ===================================
3811 23:19:51.805630 ===================================
3812 23:19:51.805684 data_rate = 1200
3813 23:19:51.805738 CKR = 1
3814 23:19:51.805793 DQ_P2S_RATIO = 8
3815 23:19:51.805847 ===================================
3816 23:19:51.805901 CA_P2S_RATIO = 8
3817 23:19:51.805956 DQ_CA_OPEN = 0
3818 23:19:51.806010 DQ_SEMI_OPEN = 0
3819 23:19:51.806064 CA_SEMI_OPEN = 0
3820 23:19:51.806118 CA_FULL_RATE = 0
3821 23:19:51.806172 DQ_CKDIV4_EN = 1
3822 23:19:51.806226 CA_CKDIV4_EN = 1
3823 23:19:51.806280 CA_PREDIV_EN = 0
3824 23:19:51.806333 PH8_DLY = 0
3825 23:19:51.806387 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3826 23:19:51.806441 DQ_AAMCK_DIV = 4
3827 23:19:51.806494 CA_AAMCK_DIV = 4
3828 23:19:51.806548 CA_ADMCK_DIV = 4
3829 23:19:51.806602 DQ_TRACK_CA_EN = 0
3830 23:19:51.806656 CA_PICK = 600
3831 23:19:51.806710 CA_MCKIO = 600
3832 23:19:51.806764 MCKIO_SEMI = 0
3833 23:19:51.806817 PLL_FREQ = 2288
3834 23:19:51.806871 DQ_UI_PI_RATIO = 32
3835 23:19:51.806925 CA_UI_PI_RATIO = 0
3836 23:19:51.806979 ===================================
3837 23:19:51.807032 ===================================
3838 23:19:51.807086 memory_type:LPDDR4
3839 23:19:51.807140 GP_NUM : 10
3840 23:19:51.807194 SRAM_EN : 1
3841 23:19:51.807248 MD32_EN : 0
3842 23:19:51.807301 ===================================
3843 23:19:51.807356 [ANA_INIT] >>>>>>>>>>>>>>
3844 23:19:51.807410 <<<<<< [CONFIGURE PHASE]: ANA_TX
3845 23:19:51.807465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3846 23:19:51.807519 ===================================
3847 23:19:51.807574 data_rate = 1200,PCW = 0X5800
3848 23:19:51.807628 ===================================
3849 23:19:51.807712 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3850 23:19:51.807766 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3851 23:19:51.807821 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3852 23:19:51.807875 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3853 23:19:51.807929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3854 23:19:51.807983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3855 23:19:51.808037 [ANA_INIT] flow start
3856 23:19:51.808091 [ANA_INIT] PLL >>>>>>>>
3857 23:19:51.808144 [ANA_INIT] PLL <<<<<<<<
3858 23:19:51.808391 [ANA_INIT] MIDPI >>>>>>>>
3859 23:19:51.808451 [ANA_INIT] MIDPI <<<<<<<<
3860 23:19:51.808506 [ANA_INIT] DLL >>>>>>>>
3861 23:19:51.808560 [ANA_INIT] flow end
3862 23:19:51.808613 ============ LP4 DIFF to SE enter ============
3863 23:19:51.808713 ============ LP4 DIFF to SE exit ============
3864 23:19:51.808782 [ANA_INIT] <<<<<<<<<<<<<
3865 23:19:51.808835 [Flow] Enable top DCM control >>>>>
3866 23:19:51.808888 [Flow] Enable top DCM control <<<<<
3867 23:19:51.808941 Enable DLL master slave shuffle
3868 23:19:51.808994 ==============================================================
3869 23:19:51.809063 Gating Mode config
3870 23:19:51.809129 ==============================================================
3871 23:19:51.809183 Config description:
3872 23:19:51.809236 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3873 23:19:51.809290 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3874 23:19:51.809344 SELPH_MODE 0: By rank 1: By Phase
3875 23:19:51.809414 ==============================================================
3876 23:19:51.809481 GAT_TRACK_EN = 1
3877 23:19:51.809534 RX_GATING_MODE = 2
3878 23:19:51.809587 RX_GATING_TRACK_MODE = 2
3879 23:19:51.809640 SELPH_MODE = 1
3880 23:19:51.809692 PICG_EARLY_EN = 1
3881 23:19:51.809746 VALID_LAT_VALUE = 1
3882 23:19:51.809827 ==============================================================
3883 23:19:51.809881 Enter into Gating configuration >>>>
3884 23:19:51.809947 Exit from Gating configuration <<<<
3885 23:19:51.812041 Enter into DVFS_PRE_config >>>>>
3886 23:19:51.821763 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3887 23:19:51.825302 Exit from DVFS_PRE_config <<<<<
3888 23:19:51.828801 Enter into PICG configuration >>>>
3889 23:19:51.832140 Exit from PICG configuration <<<<
3890 23:19:51.835241 [RX_INPUT] configuration >>>>>
3891 23:19:51.838584 [RX_INPUT] configuration <<<<<
3892 23:19:51.841941 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3893 23:19:51.848668 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3894 23:19:51.855306 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3895 23:19:51.862351 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3896 23:19:51.865159 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3897 23:19:51.871946 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3898 23:19:51.875170 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3899 23:19:51.882259 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3900 23:19:51.884882 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3901 23:19:51.888590 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3902 23:19:51.891580 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3903 23:19:51.898215 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3904 23:19:51.901533 ===================================
3905 23:19:51.905092 LPDDR4 DRAM CONFIGURATION
3906 23:19:51.908319 ===================================
3907 23:19:51.908431 EX_ROW_EN[0] = 0x0
3908 23:19:51.911780 EX_ROW_EN[1] = 0x0
3909 23:19:51.911884 LP4Y_EN = 0x0
3910 23:19:51.915174 WORK_FSP = 0x0
3911 23:19:51.915285 WL = 0x2
3912 23:19:51.918300 RL = 0x2
3913 23:19:51.918387 BL = 0x2
3914 23:19:51.921892 RPST = 0x0
3915 23:19:51.921969 RD_PRE = 0x0
3916 23:19:51.924898 WR_PRE = 0x1
3917 23:19:51.924983 WR_PST = 0x0
3918 23:19:51.928227 DBI_WR = 0x0
3919 23:19:51.928333 DBI_RD = 0x0
3920 23:19:51.931556 OTF = 0x1
3921 23:19:51.934805 ===================================
3922 23:19:51.938079 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3923 23:19:51.941567 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3924 23:19:51.948235 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3925 23:19:51.951557 ===================================
3926 23:19:51.951665 LPDDR4 DRAM CONFIGURATION
3927 23:19:51.954850 ===================================
3928 23:19:51.958096 EX_ROW_EN[0] = 0x10
3929 23:19:51.961360 EX_ROW_EN[1] = 0x0
3930 23:19:51.961458 LP4Y_EN = 0x0
3931 23:19:51.964621 WORK_FSP = 0x0
3932 23:19:51.964751 WL = 0x2
3933 23:19:51.968121 RL = 0x2
3934 23:19:51.968223 BL = 0x2
3935 23:19:51.971601 RPST = 0x0
3936 23:19:51.971701 RD_PRE = 0x0
3937 23:19:51.974806 WR_PRE = 0x1
3938 23:19:51.974892 WR_PST = 0x0
3939 23:19:51.978303 DBI_WR = 0x0
3940 23:19:51.978387 DBI_RD = 0x0
3941 23:19:51.981330 OTF = 0x1
3942 23:19:51.984859 ===================================
3943 23:19:51.991308 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3944 23:19:51.994899 nWR fixed to 30
3945 23:19:51.994985 [ModeRegInit_LP4] CH0 RK0
3946 23:19:51.997967 [ModeRegInit_LP4] CH0 RK1
3947 23:19:52.001437 [ModeRegInit_LP4] CH1 RK0
3948 23:19:52.004662 [ModeRegInit_LP4] CH1 RK1
3949 23:19:52.004759 match AC timing 17
3950 23:19:52.011568 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3951 23:19:52.014828 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3952 23:19:52.017843 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3953 23:19:52.024521 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3954 23:19:52.028048 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3955 23:19:52.028131 ==
3956 23:19:52.031380 Dram Type= 6, Freq= 0, CH_0, rank 0
3957 23:19:52.034850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 23:19:52.034934 ==
3959 23:19:52.041328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3960 23:19:52.047703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3961 23:19:52.051361 [CA 0] Center 36 (6~67) winsize 62
3962 23:19:52.054503 [CA 1] Center 36 (6~67) winsize 62
3963 23:19:52.057767 [CA 2] Center 34 (4~65) winsize 62
3964 23:19:52.060845 [CA 3] Center 34 (3~65) winsize 63
3965 23:19:52.064320 [CA 4] Center 34 (3~65) winsize 63
3966 23:19:52.067610 [CA 5] Center 33 (2~64) winsize 63
3967 23:19:52.067711
3968 23:19:52.071147 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3969 23:19:52.071233
3970 23:19:52.074455 [CATrainingPosCal] consider 1 rank data
3971 23:19:52.077631 u2DelayCellTimex100 = 270/100 ps
3972 23:19:52.080977 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3973 23:19:52.084201 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3974 23:19:52.087344 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3975 23:19:52.090891 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3976 23:19:52.094251 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3977 23:19:52.097543 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3978 23:19:52.097632
3979 23:19:52.104308 CA PerBit enable=1, Macro0, CA PI delay=33
3980 23:19:52.104439
3981 23:19:52.104546 [CBTSetCACLKResult] CA Dly = 33
3982 23:19:52.107560 CS Dly: 4 (0~35)
3983 23:19:52.107647 ==
3984 23:19:52.111272 Dram Type= 6, Freq= 0, CH_0, rank 1
3985 23:19:52.114390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 23:19:52.114479 ==
3987 23:19:52.121072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3988 23:19:52.127769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3989 23:19:52.130582 [CA 0] Center 36 (6~67) winsize 62
3990 23:19:52.134054 [CA 1] Center 36 (6~67) winsize 62
3991 23:19:52.137286 [CA 2] Center 35 (4~66) winsize 63
3992 23:19:52.140625 [CA 3] Center 35 (4~66) winsize 63
3993 23:19:52.144200 [CA 4] Center 34 (3~65) winsize 63
3994 23:19:52.147246 [CA 5] Center 33 (3~64) winsize 62
3995 23:19:52.147334
3996 23:19:52.150649 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3997 23:19:52.150735
3998 23:19:52.154224 [CATrainingPosCal] consider 2 rank data
3999 23:19:52.157395 u2DelayCellTimex100 = 270/100 ps
4000 23:19:52.160781 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4001 23:19:52.164143 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4002 23:19:52.167372 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4003 23:19:52.170759 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4004 23:19:52.174121 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4005 23:19:52.177337 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4006 23:19:52.177442
4007 23:19:52.184295 CA PerBit enable=1, Macro0, CA PI delay=33
4008 23:19:52.184424
4009 23:19:52.187323 [CBTSetCACLKResult] CA Dly = 33
4010 23:19:52.187416 CS Dly: 4 (0~36)
4011 23:19:52.187485
4012 23:19:52.190646 ----->DramcWriteLeveling(PI) begin...
4013 23:19:52.190734 ==
4014 23:19:52.194044 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 23:19:52.197205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 23:19:52.197291 ==
4017 23:19:52.200860 Write leveling (Byte 0): 33 => 33
4018 23:19:52.204061 Write leveling (Byte 1): 30 => 30
4019 23:19:52.207258 DramcWriteLeveling(PI) end<-----
4020 23:19:52.207339
4021 23:19:52.207405 ==
4022 23:19:52.210593 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 23:19:52.217339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 23:19:52.217417 ==
4025 23:19:52.217486 [Gating] SW mode calibration
4026 23:19:52.227131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4027 23:19:52.230568 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4028 23:19:52.234017 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4029 23:19:52.240914 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 23:19:52.244198 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 23:19:52.247530 0 9 12 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 0)
4032 23:19:52.253894 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
4033 23:19:52.257165 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 23:19:52.260535 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 23:19:52.267159 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 23:19:52.270967 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 23:19:52.274008 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 23:19:52.280430 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4039 23:19:52.283617 0 10 12 | B1->B0 | 2525 4141 | 0 0 | (0 0) (0 0)
4040 23:19:52.287572 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
4041 23:19:52.293900 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 23:19:52.297381 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 23:19:52.300132 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 23:19:52.307011 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 23:19:52.310307 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 23:19:52.313686 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 23:19:52.320502 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 23:19:52.323578 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4049 23:19:52.327069 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 23:19:52.333404 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 23:19:52.336907 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 23:19:52.340415 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 23:19:52.343540 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 23:19:52.350455 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 23:19:52.353590 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 23:19:52.356851 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 23:19:52.363618 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 23:19:52.366728 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 23:19:52.370500 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 23:19:52.376856 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 23:19:52.380156 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 23:19:52.383292 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 23:19:52.390007 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4064 23:19:52.393467 Total UI for P1: 0, mck2ui 16
4065 23:19:52.396591 best dqsien dly found for B0: ( 0, 13, 10)
4066 23:19:52.400013 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4067 23:19:52.403326 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 23:19:52.406672 Total UI for P1: 0, mck2ui 16
4069 23:19:52.410154 best dqsien dly found for B1: ( 0, 13, 16)
4070 23:19:52.413295 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4071 23:19:52.416446 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4072 23:19:52.416557
4073 23:19:52.423427 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4074 23:19:52.426676 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4075 23:19:52.429734 [Gating] SW calibration Done
4076 23:19:52.429819 ==
4077 23:19:52.433319 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 23:19:52.436762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 23:19:52.436851 ==
4080 23:19:52.436920 RX Vref Scan: 0
4081 23:19:52.436982
4082 23:19:52.439873 RX Vref 0 -> 0, step: 1
4083 23:19:52.439957
4084 23:19:52.443537 RX Delay -230 -> 252, step: 16
4085 23:19:52.446445 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4086 23:19:52.449756 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4087 23:19:52.456326 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4088 23:19:52.459527 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4089 23:19:52.462995 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4090 23:19:52.466486 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4091 23:19:52.473198 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4092 23:19:52.476153 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4093 23:19:52.479380 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4094 23:19:52.482717 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4095 23:19:52.489380 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4096 23:19:52.492635 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4097 23:19:52.496138 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4098 23:19:52.499438 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4099 23:19:52.506138 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4100 23:19:52.509480 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4101 23:19:52.509564 ==
4102 23:19:52.512842 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 23:19:52.516187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 23:19:52.516272 ==
4105 23:19:52.519328 DQS Delay:
4106 23:19:52.519412 DQS0 = 0, DQS1 = 0
4107 23:19:52.519480 DQM Delay:
4108 23:19:52.522706 DQM0 = 50, DQM1 = 39
4109 23:19:52.522790 DQ Delay:
4110 23:19:52.526099 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4111 23:19:52.529169 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4112 23:19:52.532606 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4113 23:19:52.535655 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4114 23:19:52.535740
4115 23:19:52.535807
4116 23:19:52.535869 ==
4117 23:19:52.539180 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 23:19:52.545727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 23:19:52.545813 ==
4120 23:19:52.545880
4121 23:19:52.545941
4122 23:19:52.546000 TX Vref Scan disable
4123 23:19:52.549052 == TX Byte 0 ==
4124 23:19:52.552443 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4125 23:19:52.559347 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4126 23:19:52.559431 == TX Byte 1 ==
4127 23:19:52.562407 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4128 23:19:52.569075 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4129 23:19:52.569159 ==
4130 23:19:52.572470 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 23:19:52.575712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 23:19:52.575796 ==
4133 23:19:52.575864
4134 23:19:52.575926
4135 23:19:52.579122 TX Vref Scan disable
4136 23:19:52.582573 == TX Byte 0 ==
4137 23:19:52.585679 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4138 23:19:52.589135 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4139 23:19:52.592407 == TX Byte 1 ==
4140 23:19:52.595612 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4141 23:19:52.598983 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4142 23:19:52.599065
4143 23:19:52.599130 [DATLAT]
4144 23:19:52.602304 Freq=600, CH0 RK0
4145 23:19:52.602387
4146 23:19:52.602453 DATLAT Default: 0x9
4147 23:19:52.605568 0, 0xFFFF, sum = 0
4148 23:19:52.605652 1, 0xFFFF, sum = 0
4149 23:19:52.608932 2, 0xFFFF, sum = 0
4150 23:19:52.612469 3, 0xFFFF, sum = 0
4151 23:19:52.612565 4, 0xFFFF, sum = 0
4152 23:19:52.615826 5, 0xFFFF, sum = 0
4153 23:19:52.615908 6, 0xFFFF, sum = 0
4154 23:19:52.619283 7, 0xFFFF, sum = 0
4155 23:19:52.619366 8, 0x0, sum = 1
4156 23:19:52.619434 9, 0x0, sum = 2
4157 23:19:52.622376 10, 0x0, sum = 3
4158 23:19:52.622458 11, 0x0, sum = 4
4159 23:19:52.625762 best_step = 9
4160 23:19:52.625844
4161 23:19:52.625909 ==
4162 23:19:52.628708 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 23:19:52.632144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 23:19:52.632227 ==
4165 23:19:52.635728 RX Vref Scan: 1
4166 23:19:52.635812
4167 23:19:52.635891 RX Vref 0 -> 0, step: 1
4168 23:19:52.635952
4169 23:19:52.638947 RX Delay -179 -> 252, step: 8
4170 23:19:52.639029
4171 23:19:52.642161 Set Vref, RX VrefLevel [Byte0]: 59
4172 23:19:52.645522 [Byte1]: 49
4173 23:19:52.649830
4174 23:19:52.649912 Final RX Vref Byte 0 = 59 to rank0
4175 23:19:52.653054 Final RX Vref Byte 1 = 49 to rank0
4176 23:19:52.656321 Final RX Vref Byte 0 = 59 to rank1
4177 23:19:52.660110 Final RX Vref Byte 1 = 49 to rank1==
4178 23:19:52.663016 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 23:19:52.666421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 23:19:52.669927 ==
4181 23:19:52.670009 DQS Delay:
4182 23:19:52.670074 DQS0 = 0, DQS1 = 0
4183 23:19:52.672941 DQM Delay:
4184 23:19:52.673022 DQM0 = 49, DQM1 = 39
4185 23:19:52.676603 DQ Delay:
4186 23:19:52.679959 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4187 23:19:52.680041 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4188 23:19:52.683153 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4189 23:19:52.686507 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =44
4190 23:19:52.689403
4191 23:19:52.689483
4192 23:19:52.696287 [DQSOSCAuto] RK0, (LSB)MR18= 0x5952, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4193 23:19:52.699589 CH0 RK0: MR19=808, MR18=5952
4194 23:19:52.706289 CH0_RK0: MR19=0x808, MR18=0x5952, DQSOSC=393, MR23=63, INC=169, DEC=113
4195 23:19:52.706378
4196 23:19:52.709936 ----->DramcWriteLeveling(PI) begin...
4197 23:19:52.710023 ==
4198 23:19:52.712622 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 23:19:52.716105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 23:19:52.716188 ==
4201 23:19:52.719436 Write leveling (Byte 0): 33 => 33
4202 23:19:52.722808 Write leveling (Byte 1): 31 => 31
4203 23:19:52.725975 DramcWriteLeveling(PI) end<-----
4204 23:19:52.726057
4205 23:19:52.726123 ==
4206 23:19:52.729265 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 23:19:52.732917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 23:19:52.732999 ==
4209 23:19:52.735901 [Gating] SW mode calibration
4210 23:19:52.742887 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4211 23:19:52.749470 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4212 23:19:52.752548 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4213 23:19:52.756235 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4214 23:19:52.762256 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 23:19:52.765799 0 9 12 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
4216 23:19:52.769003 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4217 23:19:52.776052 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 23:19:52.778959 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 23:19:52.782662 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 23:19:52.788973 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 23:19:52.792594 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 23:19:52.795598 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 23:19:52.802163 0 10 12 | B1->B0 | 2e2e 3232 | 1 1 | (0 0) (1 1)
4224 23:19:52.805711 0 10 16 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
4225 23:19:52.808844 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 23:19:52.815380 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 23:19:52.818751 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 23:19:52.822146 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 23:19:52.828967 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 23:19:52.831829 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4231 23:19:52.835163 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4232 23:19:52.841818 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 23:19:52.845048 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 23:19:52.848625 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 23:19:52.855254 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 23:19:52.858334 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 23:19:52.861733 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 23:19:52.868212 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 23:19:52.871540 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 23:19:52.875141 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:19:52.881531 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:19:52.884993 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:19:52.888400 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:19:52.894534 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:19:52.897882 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:19:52.901082 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:19:52.907594 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4248 23:19:52.910922 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4249 23:19:52.914828 Total UI for P1: 0, mck2ui 16
4250 23:19:52.917773 best dqsien dly found for B0: ( 0, 13, 14)
4251 23:19:52.921199 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 23:19:52.924420 Total UI for P1: 0, mck2ui 16
4253 23:19:52.927823 best dqsien dly found for B1: ( 0, 13, 14)
4254 23:19:52.931151 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4255 23:19:52.934318 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4256 23:19:52.937746
4257 23:19:52.941086 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4258 23:19:52.944427 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4259 23:19:52.948157 [Gating] SW calibration Done
4260 23:19:52.948240 ==
4261 23:19:52.951069 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 23:19:52.954122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 23:19:52.954207 ==
4264 23:19:52.954274 RX Vref Scan: 0
4265 23:19:52.954335
4266 23:19:52.957782 RX Vref 0 -> 0, step: 1
4267 23:19:52.957866
4268 23:19:52.960719 RX Delay -230 -> 252, step: 16
4269 23:19:52.964465 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4270 23:19:52.970660 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4271 23:19:52.974288 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4272 23:19:52.977672 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4273 23:19:52.981081 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4274 23:19:52.983895 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4275 23:19:52.990546 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4276 23:19:52.993801 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4277 23:19:52.997180 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4278 23:19:53.000545 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4279 23:19:53.007150 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4280 23:19:53.010688 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4281 23:19:53.013928 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4282 23:19:53.017232 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4283 23:19:53.023750 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4284 23:19:53.026646 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4285 23:19:53.026728 ==
4286 23:19:53.029966 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 23:19:53.033182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 23:19:53.033265 ==
4289 23:19:53.036640 DQS Delay:
4290 23:19:53.036775 DQS0 = 0, DQS1 = 0
4291 23:19:53.036841 DQM Delay:
4292 23:19:53.039901 DQM0 = 48, DQM1 = 42
4293 23:19:53.039982 DQ Delay:
4294 23:19:53.043263 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41
4295 23:19:53.046954 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4296 23:19:53.049991 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4297 23:19:53.053530 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4298 23:19:53.053612
4299 23:19:53.053678
4300 23:19:53.053739 ==
4301 23:19:53.056362 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 23:19:53.063446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 23:19:53.063528 ==
4304 23:19:53.063593
4305 23:19:53.063653
4306 23:19:53.063710 TX Vref Scan disable
4307 23:19:53.066896 == TX Byte 0 ==
4308 23:19:53.070435 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4309 23:19:53.073701 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4310 23:19:53.076875 == TX Byte 1 ==
4311 23:19:53.080290 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4312 23:19:53.084005 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4313 23:19:53.086904 ==
4314 23:19:53.090297 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 23:19:53.093758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 23:19:53.093841 ==
4317 23:19:53.093908
4318 23:19:53.093970
4319 23:19:53.097125 TX Vref Scan disable
4320 23:19:53.100174 == TX Byte 0 ==
4321 23:19:53.103664 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4322 23:19:53.106997 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4323 23:19:53.110377 == TX Byte 1 ==
4324 23:19:53.113221 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4325 23:19:53.116772 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4326 23:19:53.116855
4327 23:19:53.116921 [DATLAT]
4328 23:19:53.120092 Freq=600, CH0 RK1
4329 23:19:53.120175
4330 23:19:53.120239 DATLAT Default: 0x9
4331 23:19:53.123472 0, 0xFFFF, sum = 0
4332 23:19:53.126708 1, 0xFFFF, sum = 0
4333 23:19:53.126790 2, 0xFFFF, sum = 0
4334 23:19:53.130142 3, 0xFFFF, sum = 0
4335 23:19:53.130223 4, 0xFFFF, sum = 0
4336 23:19:53.133131 5, 0xFFFF, sum = 0
4337 23:19:53.133216 6, 0xFFFF, sum = 0
4338 23:19:53.136877 7, 0xFFFF, sum = 0
4339 23:19:53.136959 8, 0x0, sum = 1
4340 23:19:53.139763 9, 0x0, sum = 2
4341 23:19:53.139844 10, 0x0, sum = 3
4342 23:19:53.139909 11, 0x0, sum = 4
4343 23:19:53.143113 best_step = 9
4344 23:19:53.143193
4345 23:19:53.143304 ==
4346 23:19:53.146751 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 23:19:53.150130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 23:19:53.150210 ==
4349 23:19:53.153238 RX Vref Scan: 0
4350 23:19:53.153317
4351 23:19:53.153381 RX Vref 0 -> 0, step: 1
4352 23:19:53.156571
4353 23:19:53.156671 RX Delay -179 -> 252, step: 8
4354 23:19:53.164149 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4355 23:19:53.167568 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4356 23:19:53.170633 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4357 23:19:53.174119 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4358 23:19:53.177483 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4359 23:19:53.184153 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4360 23:19:53.187201 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4361 23:19:53.190832 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4362 23:19:53.193834 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4363 23:19:53.200356 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4364 23:19:53.204143 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4365 23:19:53.207433 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4366 23:19:53.210631 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4367 23:19:53.213825 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4368 23:19:53.220580 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4369 23:19:53.223987 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4370 23:19:53.224067 ==
4371 23:19:53.227266 Dram Type= 6, Freq= 0, CH_0, rank 1
4372 23:19:53.230328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 23:19:53.230408 ==
4374 23:19:53.233836 DQS Delay:
4375 23:19:53.233916 DQS0 = 0, DQS1 = 0
4376 23:19:53.233979 DQM Delay:
4377 23:19:53.237149 DQM0 = 48, DQM1 = 39
4378 23:19:53.237229 DQ Delay:
4379 23:19:53.240103 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4380 23:19:53.243650 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4381 23:19:53.246912 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4382 23:19:53.250260 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4383 23:19:53.250340
4384 23:19:53.250437
4385 23:19:53.260297 [DQSOSCAuto] RK1, (LSB)MR18= 0x622f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4386 23:19:53.263793 CH0 RK1: MR19=808, MR18=622F
4387 23:19:53.266853 CH0_RK1: MR19=0x808, MR18=0x622F, DQSOSC=391, MR23=63, INC=171, DEC=114
4388 23:19:53.270236 [RxdqsGatingPostProcess] freq 600
4389 23:19:53.276705 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4390 23:19:53.279951 Pre-setting of DQS Precalculation
4391 23:19:53.283447 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4392 23:19:53.283528 ==
4393 23:19:53.286865 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 23:19:53.293752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 23:19:53.293834 ==
4396 23:19:53.296696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4397 23:19:53.303431 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4398 23:19:53.306751 [CA 0] Center 35 (5~66) winsize 62
4399 23:19:53.310114 [CA 1] Center 35 (5~66) winsize 62
4400 23:19:53.313344 [CA 2] Center 34 (4~65) winsize 62
4401 23:19:53.316587 [CA 3] Center 33 (3~64) winsize 62
4402 23:19:53.320519 [CA 4] Center 34 (3~65) winsize 63
4403 23:19:53.323361 [CA 5] Center 33 (3~64) winsize 62
4404 23:19:53.323441
4405 23:19:53.326938 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4406 23:19:53.327019
4407 23:19:53.330692 [CATrainingPosCal] consider 1 rank data
4408 23:19:53.333624 u2DelayCellTimex100 = 270/100 ps
4409 23:19:53.337157 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4410 23:19:53.340502 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4411 23:19:53.346700 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4412 23:19:53.350220 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4413 23:19:53.353391 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4414 23:19:53.356664 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4415 23:19:53.356745
4416 23:19:53.360096 CA PerBit enable=1, Macro0, CA PI delay=33
4417 23:19:53.360177
4418 23:19:53.363554 [CBTSetCACLKResult] CA Dly = 33
4419 23:19:53.363635 CS Dly: 3 (0~34)
4420 23:19:53.363699 ==
4421 23:19:53.366866 Dram Type= 6, Freq= 0, CH_1, rank 1
4422 23:19:53.373164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 23:19:53.373246 ==
4424 23:19:53.376635 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4425 23:19:53.383093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4426 23:19:53.386916 [CA 0] Center 35 (5~66) winsize 62
4427 23:19:53.390104 [CA 1] Center 35 (5~66) winsize 62
4428 23:19:53.393562 [CA 2] Center 34 (4~65) winsize 62
4429 23:19:53.396584 [CA 3] Center 34 (4~65) winsize 62
4430 23:19:53.400014 [CA 4] Center 34 (4~65) winsize 62
4431 23:19:53.403468 [CA 5] Center 33 (3~64) winsize 62
4432 23:19:53.403549
4433 23:19:53.406817 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4434 23:19:53.406899
4435 23:19:53.410257 [CATrainingPosCal] consider 2 rank data
4436 23:19:53.413133 u2DelayCellTimex100 = 270/100 ps
4437 23:19:53.416593 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4438 23:19:53.423286 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 23:19:53.426922 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4440 23:19:53.430256 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4441 23:19:53.433227 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 23:19:53.436428 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4443 23:19:53.436509
4444 23:19:53.439722 CA PerBit enable=1, Macro0, CA PI delay=33
4445 23:19:53.439803
4446 23:19:53.443160 [CBTSetCACLKResult] CA Dly = 33
4447 23:19:53.443240 CS Dly: 4 (0~36)
4448 23:19:53.446561
4449 23:19:53.449790 ----->DramcWriteLeveling(PI) begin...
4450 23:19:53.449872 ==
4451 23:19:53.453187 Dram Type= 6, Freq= 0, CH_1, rank 0
4452 23:19:53.456734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 23:19:53.456817 ==
4454 23:19:53.459518 Write leveling (Byte 0): 30 => 30
4455 23:19:53.462931 Write leveling (Byte 1): 30 => 30
4456 23:19:53.466270 DramcWriteLeveling(PI) end<-----
4457 23:19:53.466351
4458 23:19:53.466415 ==
4459 23:19:53.469736 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 23:19:53.473122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 23:19:53.473204 ==
4462 23:19:53.476431 [Gating] SW mode calibration
4463 23:19:53.483134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4464 23:19:53.489849 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4465 23:19:53.493120 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4466 23:19:53.496312 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 23:19:53.502828 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4468 23:19:53.506228 0 9 12 | B1->B0 | 2929 2d2d | 0 0 | (1 1) (1 1)
4469 23:19:53.509980 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 23:19:53.512879 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 23:19:53.519785 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 23:19:53.523035 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 23:19:53.526430 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 23:19:53.532624 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 23:19:53.536275 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4476 23:19:53.539435 0 10 12 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
4477 23:19:53.546564 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 23:19:53.549366 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 23:19:53.552889 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 23:19:53.559211 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 23:19:53.562703 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 23:19:53.566154 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 23:19:53.572893 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4484 23:19:53.576144 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4485 23:19:53.579479 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 23:19:53.586076 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 23:19:53.589384 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 23:19:53.592633 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 23:19:53.599057 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 23:19:53.602377 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 23:19:53.605682 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 23:19:53.612176 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 23:19:53.615660 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 23:19:53.619044 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 23:19:53.625972 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 23:19:53.629269 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 23:19:53.632239 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 23:19:53.638895 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 23:19:53.642243 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 23:19:53.645435 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 23:19:53.648825 Total UI for P1: 0, mck2ui 16
4502 23:19:53.652270 best dqsien dly found for B0: ( 0, 13, 10)
4503 23:19:53.655781 Total UI for P1: 0, mck2ui 16
4504 23:19:53.659177 best dqsien dly found for B1: ( 0, 13, 10)
4505 23:19:53.662357 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4506 23:19:53.665500 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4507 23:19:53.665581
4508 23:19:53.672179 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4509 23:19:53.675561 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4510 23:19:53.675642 [Gating] SW calibration Done
4511 23:19:53.678988 ==
4512 23:19:53.679068 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 23:19:53.685516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 23:19:53.685597 ==
4515 23:19:53.685662 RX Vref Scan: 0
4516 23:19:53.685721
4517 23:19:53.688738 RX Vref 0 -> 0, step: 1
4518 23:19:53.688819
4519 23:19:53.692074 RX Delay -230 -> 252, step: 16
4520 23:19:53.695372 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4521 23:19:53.698642 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4522 23:19:53.705207 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4523 23:19:53.708817 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4524 23:19:53.712107 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4525 23:19:53.715644 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4526 23:19:53.718530 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4527 23:19:53.725360 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4528 23:19:53.728557 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4529 23:19:53.731763 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4530 23:19:53.735052 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4531 23:19:53.742112 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4532 23:19:53.745268 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4533 23:19:53.748827 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4534 23:19:53.752090 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4535 23:19:53.755481 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4536 23:19:53.759011 ==
4537 23:19:53.761939 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 23:19:53.765232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 23:19:53.765313 ==
4540 23:19:53.765377 DQS Delay:
4541 23:19:53.768561 DQS0 = 0, DQS1 = 0
4542 23:19:53.768663 DQM Delay:
4543 23:19:53.771877 DQM0 = 53, DQM1 = 45
4544 23:19:53.771958 DQ Delay:
4545 23:19:53.774996 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4546 23:19:53.778401 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4547 23:19:53.781867 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4548 23:19:53.785301 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =49
4549 23:19:53.785382
4550 23:19:53.785445
4551 23:19:53.785503 ==
4552 23:19:53.788445 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 23:19:53.791709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 23:19:53.791791 ==
4555 23:19:53.791855
4556 23:19:53.791914
4557 23:19:53.795178 TX Vref Scan disable
4558 23:19:53.798109 == TX Byte 0 ==
4559 23:19:53.801692 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4560 23:19:53.805065 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4561 23:19:53.808480 == TX Byte 1 ==
4562 23:19:53.811997 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4563 23:19:53.814938 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4564 23:19:53.815063 ==
4565 23:19:53.817916 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 23:19:53.824612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 23:19:53.824756 ==
4568 23:19:53.824821
4569 23:19:53.824881
4570 23:19:53.824938 TX Vref Scan disable
4571 23:19:53.829126 == TX Byte 0 ==
4572 23:19:53.832425 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4573 23:19:53.838910 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4574 23:19:53.839050 == TX Byte 1 ==
4575 23:19:53.842125 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4576 23:19:53.848899 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4577 23:19:53.848982
4578 23:19:53.849120 [DATLAT]
4579 23:19:53.849243 Freq=600, CH1 RK0
4580 23:19:53.849317
4581 23:19:53.852269 DATLAT Default: 0x9
4582 23:19:53.852349 0, 0xFFFF, sum = 0
4583 23:19:53.855878 1, 0xFFFF, sum = 0
4584 23:19:53.855960 2, 0xFFFF, sum = 0
4585 23:19:53.859457 3, 0xFFFF, sum = 0
4586 23:19:53.862286 4, 0xFFFF, sum = 0
4587 23:19:53.862369 5, 0xFFFF, sum = 0
4588 23:19:53.865820 6, 0xFFFF, sum = 0
4589 23:19:53.865901 7, 0xFFFF, sum = 0
4590 23:19:53.868761 8, 0x0, sum = 1
4591 23:19:53.868843 9, 0x0, sum = 2
4592 23:19:53.868909 10, 0x0, sum = 3
4593 23:19:53.872171 11, 0x0, sum = 4
4594 23:19:53.872253 best_step = 9
4595 23:19:53.872317
4596 23:19:53.872378 ==
4597 23:19:53.875619 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 23:19:53.881974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 23:19:53.882055 ==
4600 23:19:53.882118 RX Vref Scan: 1
4601 23:19:53.882177
4602 23:19:53.885534 RX Vref 0 -> 0, step: 1
4603 23:19:53.885615
4604 23:19:53.888610 RX Delay -163 -> 252, step: 8
4605 23:19:53.888721
4606 23:19:53.892145 Set Vref, RX VrefLevel [Byte0]: 52
4607 23:19:53.895516 [Byte1]: 52
4608 23:19:53.895597
4609 23:19:53.899016 Final RX Vref Byte 0 = 52 to rank0
4610 23:19:53.902263 Final RX Vref Byte 1 = 52 to rank0
4611 23:19:53.905407 Final RX Vref Byte 0 = 52 to rank1
4612 23:19:53.908643 Final RX Vref Byte 1 = 52 to rank1==
4613 23:19:53.912256 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 23:19:53.915537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 23:19:53.915619 ==
4616 23:19:53.918461 DQS Delay:
4617 23:19:53.918541 DQS0 = 0, DQS1 = 0
4618 23:19:53.918605 DQM Delay:
4619 23:19:53.922330 DQM0 = 47, DQM1 = 41
4620 23:19:53.922410 DQ Delay:
4621 23:19:53.925143 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4622 23:19:53.928828 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4623 23:19:53.931866 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4624 23:19:53.935153 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4625 23:19:53.935263
4626 23:19:53.935369
4627 23:19:53.945192 [DQSOSCAuto] RK0, (LSB)MR18= 0x466e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4628 23:19:53.948410 CH1 RK0: MR19=808, MR18=466E
4629 23:19:53.951841 CH1_RK0: MR19=0x808, MR18=0x466E, DQSOSC=389, MR23=63, INC=173, DEC=115
4630 23:19:53.955257
4631 23:19:53.958487 ----->DramcWriteLeveling(PI) begin...
4632 23:19:53.958568 ==
4633 23:19:53.962091 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 23:19:53.965388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 23:19:53.965470 ==
4636 23:19:53.968810 Write leveling (Byte 0): 29 => 29
4637 23:19:53.971739 Write leveling (Byte 1): 29 => 29
4638 23:19:53.975365 DramcWriteLeveling(PI) end<-----
4639 23:19:53.975445
4640 23:19:53.975509 ==
4641 23:19:53.978687 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 23:19:53.981767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 23:19:53.981849 ==
4644 23:19:53.985123 [Gating] SW mode calibration
4645 23:19:53.991797 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4646 23:19:53.998553 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4647 23:19:54.001840 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4648 23:19:54.004925 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4649 23:19:54.011659 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4650 23:19:54.014884 0 9 12 | B1->B0 | 2c2c 2f2f | 0 0 | (1 1) (0 0)
4651 23:19:54.018234 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4652 23:19:54.024917 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 23:19:54.028114 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 23:19:54.031314 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 23:19:54.038300 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 23:19:54.041169 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 23:19:54.044693 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 23:19:54.048027 0 10 12 | B1->B0 | 3c3c 3434 | 0 0 | (0 0) (0 0)
4659 23:19:54.054688 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 23:19:54.058276 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 23:19:54.061405 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 23:19:54.068250 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 23:19:54.071141 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 23:19:54.074854 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 23:19:54.081457 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 23:19:54.084830 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4667 23:19:54.088100 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 23:19:54.094540 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 23:19:54.097787 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 23:19:54.101162 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 23:19:54.107850 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 23:19:54.111130 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 23:19:54.114523 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 23:19:54.121103 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 23:19:54.124341 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 23:19:54.128387 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 23:19:54.134696 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 23:19:54.137585 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 23:19:54.141332 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 23:19:54.148896 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 23:19:54.151186 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4682 23:19:54.154583 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4683 23:19:54.157594 Total UI for P1: 0, mck2ui 16
4684 23:19:54.161016 best dqsien dly found for B1: ( 0, 13, 8)
4685 23:19:54.164454 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 23:19:54.167635 Total UI for P1: 0, mck2ui 16
4687 23:19:54.171000 best dqsien dly found for B0: ( 0, 13, 10)
4688 23:19:54.177672 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4689 23:19:54.181096 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4690 23:19:54.181178
4691 23:19:54.184291 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4692 23:19:54.187625 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4693 23:19:54.191009 [Gating] SW calibration Done
4694 23:19:54.191091 ==
4695 23:19:54.194051 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 23:19:54.197440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 23:19:54.197523 ==
4698 23:19:54.200668 RX Vref Scan: 0
4699 23:19:54.200750
4700 23:19:54.200815 RX Vref 0 -> 0, step: 1
4701 23:19:54.200874
4702 23:19:54.204162 RX Delay -230 -> 252, step: 16
4703 23:19:54.207496 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4704 23:19:54.213719 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4705 23:19:54.217440 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4706 23:19:54.220922 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4707 23:19:54.223681 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4708 23:19:54.227321 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4709 23:19:54.233757 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4710 23:19:54.237419 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4711 23:19:54.240805 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4712 23:19:54.244158 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4713 23:19:54.250344 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4714 23:19:54.254062 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4715 23:19:54.257108 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4716 23:19:54.260401 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4717 23:19:54.267112 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4718 23:19:54.270389 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4719 23:19:54.270470 ==
4720 23:19:54.273613 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 23:19:54.277158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 23:19:54.277240 ==
4723 23:19:54.277304 DQS Delay:
4724 23:19:54.280593 DQS0 = 0, DQS1 = 0
4725 23:19:54.280717 DQM Delay:
4726 23:19:54.283869 DQM0 = 52, DQM1 = 46
4727 23:19:54.283949 DQ Delay:
4728 23:19:54.286984 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4729 23:19:54.290449 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4730 23:19:54.293854 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4731 23:19:54.297224 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4732 23:19:54.297304
4733 23:19:54.297368
4734 23:19:54.297427 ==
4735 23:19:54.300569 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 23:19:54.303784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 23:19:54.307158 ==
4738 23:19:54.307238
4739 23:19:54.307301
4740 23:19:54.307360 TX Vref Scan disable
4741 23:19:54.310498 == TX Byte 0 ==
4742 23:19:54.313954 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4743 23:19:54.317100 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4744 23:19:54.320521 == TX Byte 1 ==
4745 23:19:54.323638 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4746 23:19:54.327023 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4747 23:19:54.330411 ==
4748 23:19:54.333899 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 23:19:54.336978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 23:19:54.337059 ==
4751 23:19:54.337158
4752 23:19:54.337219
4753 23:19:54.340162 TX Vref Scan disable
4754 23:19:54.340242 == TX Byte 0 ==
4755 23:19:54.346854 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4756 23:19:54.350209 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4757 23:19:54.350290 == TX Byte 1 ==
4758 23:19:54.356798 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4759 23:19:54.360141 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4760 23:19:54.360222
4761 23:19:54.360285 [DATLAT]
4762 23:19:54.363527 Freq=600, CH1 RK1
4763 23:19:54.363607
4764 23:19:54.363672 DATLAT Default: 0x9
4765 23:19:54.366694 0, 0xFFFF, sum = 0
4766 23:19:54.366776 1, 0xFFFF, sum = 0
4767 23:19:54.370294 2, 0xFFFF, sum = 0
4768 23:19:54.373298 3, 0xFFFF, sum = 0
4769 23:19:54.373379 4, 0xFFFF, sum = 0
4770 23:19:54.376885 5, 0xFFFF, sum = 0
4771 23:19:54.376967 6, 0xFFFF, sum = 0
4772 23:19:54.380171 7, 0xFFFF, sum = 0
4773 23:19:54.380252 8, 0x0, sum = 1
4774 23:19:54.380318 9, 0x0, sum = 2
4775 23:19:54.383559 10, 0x0, sum = 3
4776 23:19:54.383641 11, 0x0, sum = 4
4777 23:19:54.387144 best_step = 9
4778 23:19:54.387249
4779 23:19:54.387344 ==
4780 23:19:54.390371 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 23:19:54.393601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 23:19:54.393683 ==
4783 23:19:54.397098 RX Vref Scan: 0
4784 23:19:54.397178
4785 23:19:54.397242 RX Vref 0 -> 0, step: 1
4786 23:19:54.397302
4787 23:19:54.400230 RX Delay -163 -> 252, step: 8
4788 23:19:54.407405 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4789 23:19:54.410308 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4790 23:19:54.413796 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4791 23:19:54.417124 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4792 23:19:54.420519 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4793 23:19:54.427191 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4794 23:19:54.430236 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4795 23:19:54.433764 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4796 23:19:54.437360 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4797 23:19:54.443602 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4798 23:19:54.447016 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4799 23:19:54.450393 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4800 23:19:54.453931 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4801 23:19:54.456886 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4802 23:19:54.463646 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4803 23:19:54.466850 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4804 23:19:54.466930 ==
4805 23:19:54.470082 Dram Type= 6, Freq= 0, CH_1, rank 1
4806 23:19:54.473417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4807 23:19:54.473498 ==
4808 23:19:54.476941 DQS Delay:
4809 23:19:54.477021 DQS0 = 0, DQS1 = 0
4810 23:19:54.477085 DQM Delay:
4811 23:19:54.480315 DQM0 = 48, DQM1 = 43
4812 23:19:54.480396 DQ Delay:
4813 23:19:54.483718 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4814 23:19:54.486670 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4815 23:19:54.490220 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4816 23:19:54.493659 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =52
4817 23:19:54.493740
4818 23:19:54.493805
4819 23:19:54.503422 [DQSOSCAuto] RK1, (LSB)MR18= 0x551c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4820 23:19:54.503505 CH1 RK1: MR19=808, MR18=551C
4821 23:19:54.510416 CH1_RK1: MR19=0x808, MR18=0x551C, DQSOSC=393, MR23=63, INC=169, DEC=113
4822 23:19:54.513295 [RxdqsGatingPostProcess] freq 600
4823 23:19:54.520062 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4824 23:19:54.523229 Pre-setting of DQS Precalculation
4825 23:19:54.526715 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4826 23:19:54.536299 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4827 23:19:54.543258 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4828 23:19:54.543341
4829 23:19:54.543404
4830 23:19:54.546511 [Calibration Summary] 1200 Mbps
4831 23:19:54.546593 CH 0, Rank 0
4832 23:19:54.549584 SW Impedance : PASS
4833 23:19:54.549666 DUTY Scan : NO K
4834 23:19:54.553030 ZQ Calibration : PASS
4835 23:19:54.556089 Jitter Meter : NO K
4836 23:19:54.556171 CBT Training : PASS
4837 23:19:54.559734 Write leveling : PASS
4838 23:19:54.562812 RX DQS gating : PASS
4839 23:19:54.562894 RX DQ/DQS(RDDQC) : PASS
4840 23:19:54.566319 TX DQ/DQS : PASS
4841 23:19:54.569642 RX DATLAT : PASS
4842 23:19:54.569723 RX DQ/DQS(Engine): PASS
4843 23:19:54.573046 TX OE : NO K
4844 23:19:54.573128 All Pass.
4845 23:19:54.573192
4846 23:19:54.576286 CH 0, Rank 1
4847 23:19:54.576367 SW Impedance : PASS
4848 23:19:54.579604 DUTY Scan : NO K
4849 23:19:54.579710 ZQ Calibration : PASS
4850 23:19:54.582645 Jitter Meter : NO K
4851 23:19:54.586370 CBT Training : PASS
4852 23:19:54.586451 Write leveling : PASS
4853 23:19:54.589356 RX DQS gating : PASS
4854 23:19:54.592835 RX DQ/DQS(RDDQC) : PASS
4855 23:19:54.592915 TX DQ/DQS : PASS
4856 23:19:54.596163 RX DATLAT : PASS
4857 23:19:54.599552 RX DQ/DQS(Engine): PASS
4858 23:19:54.599632 TX OE : NO K
4859 23:19:54.602914 All Pass.
4860 23:19:54.602994
4861 23:19:54.603058 CH 1, Rank 0
4862 23:19:54.605885 SW Impedance : PASS
4863 23:19:54.605966 DUTY Scan : NO K
4864 23:19:54.609290 ZQ Calibration : PASS
4865 23:19:54.612610 Jitter Meter : NO K
4866 23:19:54.612753 CBT Training : PASS
4867 23:19:54.615877 Write leveling : PASS
4868 23:19:54.619217 RX DQS gating : PASS
4869 23:19:54.619297 RX DQ/DQS(RDDQC) : PASS
4870 23:19:54.622717 TX DQ/DQS : PASS
4871 23:19:54.622797 RX DATLAT : PASS
4872 23:19:54.626066 RX DQ/DQS(Engine): PASS
4873 23:19:54.629429 TX OE : NO K
4874 23:19:54.629554 All Pass.
4875 23:19:54.629648
4876 23:19:54.629708 CH 1, Rank 1
4877 23:19:54.632794 SW Impedance : PASS
4878 23:19:54.635844 DUTY Scan : NO K
4879 23:19:54.635924 ZQ Calibration : PASS
4880 23:19:54.639275 Jitter Meter : NO K
4881 23:19:54.642622 CBT Training : PASS
4882 23:19:54.642702 Write leveling : PASS
4883 23:19:54.646117 RX DQS gating : PASS
4884 23:19:54.648983 RX DQ/DQS(RDDQC) : PASS
4885 23:19:54.649064 TX DQ/DQS : PASS
4886 23:19:54.652578 RX DATLAT : PASS
4887 23:19:54.655930 RX DQ/DQS(Engine): PASS
4888 23:19:54.656010 TX OE : NO K
4889 23:19:54.659529 All Pass.
4890 23:19:54.659609
4891 23:19:54.659673 DramC Write-DBI off
4892 23:19:54.662397 PER_BANK_REFRESH: Hybrid Mode
4893 23:19:54.662478 TX_TRACKING: ON
4894 23:19:54.672440 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4895 23:19:54.675740 [FAST_K] Save calibration result to emmc
4896 23:19:54.678976 dramc_set_vcore_voltage set vcore to 662500
4897 23:19:54.682428 Read voltage for 933, 3
4898 23:19:54.682510 Vio18 = 0
4899 23:19:54.685491 Vcore = 662500
4900 23:19:54.685572 Vdram = 0
4901 23:19:54.685638 Vddq = 0
4902 23:19:54.688980 Vmddr = 0
4903 23:19:54.692182 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4904 23:19:54.699146 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4905 23:19:54.699229 MEM_TYPE=3, freq_sel=17
4906 23:19:54.702348 sv_algorithm_assistance_LP4_1600
4907 23:19:54.705686 ============ PULL DRAM RESETB DOWN ============
4908 23:19:54.712294 ========== PULL DRAM RESETB DOWN end =========
4909 23:19:54.716009 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4910 23:19:54.719023 ===================================
4911 23:19:54.722123 LPDDR4 DRAM CONFIGURATION
4912 23:19:54.725970 ===================================
4913 23:19:54.726052 EX_ROW_EN[0] = 0x0
4914 23:19:54.728882 EX_ROW_EN[1] = 0x0
4915 23:19:54.728963 LP4Y_EN = 0x0
4916 23:19:54.732641 WORK_FSP = 0x0
4917 23:19:54.732758 WL = 0x3
4918 23:19:54.736270 RL = 0x3
4919 23:19:54.736351 BL = 0x2
4920 23:19:54.739213 RPST = 0x0
4921 23:19:54.742616 RD_PRE = 0x0
4922 23:19:54.742697 WR_PRE = 0x1
4923 23:19:54.745877 WR_PST = 0x0
4924 23:19:54.745959 DBI_WR = 0x0
4925 23:19:54.749268 DBI_RD = 0x0
4926 23:19:54.749350 OTF = 0x1
4927 23:19:54.752411 ===================================
4928 23:19:54.755524 ===================================
4929 23:19:54.758959 ANA top config
4930 23:19:54.759041 ===================================
4931 23:19:54.762450 DLL_ASYNC_EN = 0
4932 23:19:54.765423 ALL_SLAVE_EN = 1
4933 23:19:54.768660 NEW_RANK_MODE = 1
4934 23:19:54.772141 DLL_IDLE_MODE = 1
4935 23:19:54.772223 LP45_APHY_COMB_EN = 1
4936 23:19:54.775574 TX_ODT_DIS = 1
4937 23:19:54.778825 NEW_8X_MODE = 1
4938 23:19:54.782351 ===================================
4939 23:19:54.785587 ===================================
4940 23:19:54.788801 data_rate = 1866
4941 23:19:54.792134 CKR = 1
4942 23:19:54.795904 DQ_P2S_RATIO = 8
4943 23:19:54.795985 ===================================
4944 23:19:54.798690 CA_P2S_RATIO = 8
4945 23:19:54.802136 DQ_CA_OPEN = 0
4946 23:19:54.805364 DQ_SEMI_OPEN = 0
4947 23:19:54.808910 CA_SEMI_OPEN = 0
4948 23:19:54.812176 CA_FULL_RATE = 0
4949 23:19:54.812274 DQ_CKDIV4_EN = 1
4950 23:19:54.815818 CA_CKDIV4_EN = 1
4951 23:19:54.818752 CA_PREDIV_EN = 0
4952 23:19:54.821924 PH8_DLY = 0
4953 23:19:54.825573 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4954 23:19:54.828439 DQ_AAMCK_DIV = 4
4955 23:19:54.828524 CA_AAMCK_DIV = 4
4956 23:19:54.832003 CA_ADMCK_DIV = 4
4957 23:19:54.835314 DQ_TRACK_CA_EN = 0
4958 23:19:54.838720 CA_PICK = 933
4959 23:19:54.841859 CA_MCKIO = 933
4960 23:19:54.845328 MCKIO_SEMI = 0
4961 23:19:54.848752 PLL_FREQ = 3732
4962 23:19:54.848837 DQ_UI_PI_RATIO = 32
4963 23:19:54.852254 CA_UI_PI_RATIO = 0
4964 23:19:54.855331 ===================================
4965 23:19:54.858462 ===================================
4966 23:19:54.862164 memory_type:LPDDR4
4967 23:19:54.865359 GP_NUM : 10
4968 23:19:54.865443 SRAM_EN : 1
4969 23:19:54.868754 MD32_EN : 0
4970 23:19:54.872169 ===================================
4971 23:19:54.875054 [ANA_INIT] >>>>>>>>>>>>>>
4972 23:19:54.875136 <<<<<< [CONFIGURE PHASE]: ANA_TX
4973 23:19:54.878364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4974 23:19:54.881758 ===================================
4975 23:19:54.885449 data_rate = 1866,PCW = 0X8f00
4976 23:19:54.888376 ===================================
4977 23:19:54.891745 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4978 23:19:54.898275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4979 23:19:54.905139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4980 23:19:54.908144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4981 23:19:54.911940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4982 23:19:54.914758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4983 23:19:54.918144 [ANA_INIT] flow start
4984 23:19:54.918229 [ANA_INIT] PLL >>>>>>>>
4985 23:19:54.921628 [ANA_INIT] PLL <<<<<<<<
4986 23:19:54.924917 [ANA_INIT] MIDPI >>>>>>>>
4987 23:19:54.928176 [ANA_INIT] MIDPI <<<<<<<<
4988 23:19:54.928260 [ANA_INIT] DLL >>>>>>>>
4989 23:19:54.931480 [ANA_INIT] flow end
4990 23:19:54.934980 ============ LP4 DIFF to SE enter ============
4991 23:19:54.938228 ============ LP4 DIFF to SE exit ============
4992 23:19:54.941675 [ANA_INIT] <<<<<<<<<<<<<
4993 23:19:54.945197 [Flow] Enable top DCM control >>>>>
4994 23:19:54.948407 [Flow] Enable top DCM control <<<<<
4995 23:19:54.951660 Enable DLL master slave shuffle
4996 23:19:54.955057 ==============================================================
4997 23:19:54.958497 Gating Mode config
4998 23:19:54.965152 ==============================================================
4999 23:19:54.965243 Config description:
5000 23:19:54.974867 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5001 23:19:54.981545 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5002 23:19:54.988466 SELPH_MODE 0: By rank 1: By Phase
5003 23:19:54.991803 ==============================================================
5004 23:19:54.994803 GAT_TRACK_EN = 1
5005 23:19:54.998152 RX_GATING_MODE = 2
5006 23:19:55.001501 RX_GATING_TRACK_MODE = 2
5007 23:19:55.004677 SELPH_MODE = 1
5008 23:19:55.007958 PICG_EARLY_EN = 1
5009 23:19:55.011377 VALID_LAT_VALUE = 1
5010 23:19:55.014651 ==============================================================
5011 23:19:55.018066 Enter into Gating configuration >>>>
5012 23:19:55.021193 Exit from Gating configuration <<<<
5013 23:19:55.024679 Enter into DVFS_PRE_config >>>>>
5014 23:19:55.037890 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5015 23:19:55.041353 Exit from DVFS_PRE_config <<<<<
5016 23:19:55.041449 Enter into PICG configuration >>>>
5017 23:19:55.044806 Exit from PICG configuration <<<<
5018 23:19:55.047704 [RX_INPUT] configuration >>>>>
5019 23:19:55.050920 [RX_INPUT] configuration <<<<<
5020 23:19:55.057990 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5021 23:19:55.060936 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5022 23:19:55.067845 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5023 23:19:55.074516 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5024 23:19:55.081181 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5025 23:19:55.087730 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5026 23:19:55.091088 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5027 23:19:55.094507 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5028 23:19:55.097755 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5029 23:19:55.103966 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5030 23:19:55.107322 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5031 23:19:55.110903 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5032 23:19:55.113843 ===================================
5033 23:19:55.117325 LPDDR4 DRAM CONFIGURATION
5034 23:19:55.120567 ===================================
5035 23:19:55.124275 EX_ROW_EN[0] = 0x0
5036 23:19:55.124361 EX_ROW_EN[1] = 0x0
5037 23:19:55.127314 LP4Y_EN = 0x0
5038 23:19:55.127397 WORK_FSP = 0x0
5039 23:19:55.130647 WL = 0x3
5040 23:19:55.130747 RL = 0x3
5041 23:19:55.133883 BL = 0x2
5042 23:19:55.133966 RPST = 0x0
5043 23:19:55.137274 RD_PRE = 0x0
5044 23:19:55.137358 WR_PRE = 0x1
5045 23:19:55.140580 WR_PST = 0x0
5046 23:19:55.140699 DBI_WR = 0x0
5047 23:19:55.144110 DBI_RD = 0x0
5048 23:19:55.144194 OTF = 0x1
5049 23:19:55.147047 ===================================
5050 23:19:55.153660 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5051 23:19:55.157365 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5052 23:19:55.160349 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5053 23:19:55.163699 ===================================
5054 23:19:55.166891 LPDDR4 DRAM CONFIGURATION
5055 23:19:55.170174 ===================================
5056 23:19:55.174057 EX_ROW_EN[0] = 0x10
5057 23:19:55.174142 EX_ROW_EN[1] = 0x0
5058 23:19:55.176857 LP4Y_EN = 0x0
5059 23:19:55.176941 WORK_FSP = 0x0
5060 23:19:55.180345 WL = 0x3
5061 23:19:55.180432 RL = 0x3
5062 23:19:55.183830 BL = 0x2
5063 23:19:55.183916 RPST = 0x0
5064 23:19:55.186708 RD_PRE = 0x0
5065 23:19:55.186794 WR_PRE = 0x1
5066 23:19:55.190175 WR_PST = 0x0
5067 23:19:55.190261 DBI_WR = 0x0
5068 23:19:55.193583 DBI_RD = 0x0
5069 23:19:55.193669 OTF = 0x1
5070 23:19:55.196859 ===================================
5071 23:19:55.203505 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5072 23:19:55.208136 nWR fixed to 30
5073 23:19:55.211377 [ModeRegInit_LP4] CH0 RK0
5074 23:19:55.211474 [ModeRegInit_LP4] CH0 RK1
5075 23:19:55.214631 [ModeRegInit_LP4] CH1 RK0
5076 23:19:55.218330 [ModeRegInit_LP4] CH1 RK1
5077 23:19:55.218426 match AC timing 9
5078 23:19:55.224764 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5079 23:19:55.228297 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5080 23:19:55.231541 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5081 23:19:55.238373 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5082 23:19:55.241407 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5083 23:19:55.241501 ==
5084 23:19:55.244612 Dram Type= 6, Freq= 0, CH_0, rank 0
5085 23:19:55.248086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5086 23:19:55.248177 ==
5087 23:19:55.254631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5088 23:19:55.261596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5089 23:19:55.264764 [CA 0] Center 38 (7~69) winsize 63
5090 23:19:55.268055 [CA 1] Center 38 (8~69) winsize 62
5091 23:19:55.271350 [CA 2] Center 35 (5~66) winsize 62
5092 23:19:55.274912 [CA 3] Center 35 (4~66) winsize 63
5093 23:19:55.277993 [CA 4] Center 35 (5~65) winsize 61
5094 23:19:55.281151 [CA 5] Center 33 (3~64) winsize 62
5095 23:19:55.281238
5096 23:19:55.284627 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5097 23:19:55.284748
5098 23:19:55.287940 [CATrainingPosCal] consider 1 rank data
5099 23:19:55.291374 u2DelayCellTimex100 = 270/100 ps
5100 23:19:55.294799 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5101 23:19:55.298131 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5102 23:19:55.301381 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5103 23:19:55.304945 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5104 23:19:55.308186 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5105 23:19:55.311218 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5106 23:19:55.314954
5107 23:19:55.318323 CA PerBit enable=1, Macro0, CA PI delay=33
5108 23:19:55.318411
5109 23:19:55.321543 [CBTSetCACLKResult] CA Dly = 33
5110 23:19:55.321631 CS Dly: 6 (0~37)
5111 23:19:55.321699 ==
5112 23:19:55.324857 Dram Type= 6, Freq= 0, CH_0, rank 1
5113 23:19:55.328186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 23:19:55.328272 ==
5115 23:19:55.334414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5116 23:19:55.341115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5117 23:19:55.344466 [CA 0] Center 38 (7~69) winsize 63
5118 23:19:55.347703 [CA 1] Center 38 (8~69) winsize 62
5119 23:19:55.350978 [CA 2] Center 36 (6~66) winsize 61
5120 23:19:55.354335 [CA 3] Center 35 (5~66) winsize 62
5121 23:19:55.357871 [CA 4] Center 34 (4~65) winsize 62
5122 23:19:55.361216 [CA 5] Center 34 (4~64) winsize 61
5123 23:19:55.361308
5124 23:19:55.364356 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5125 23:19:55.364444
5126 23:19:55.367730 [CATrainingPosCal] consider 2 rank data
5127 23:19:55.370926 u2DelayCellTimex100 = 270/100 ps
5128 23:19:55.374361 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5129 23:19:55.377815 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5130 23:19:55.381235 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5131 23:19:55.384365 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5132 23:19:55.391074 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5133 23:19:55.394489 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5134 23:19:55.394578
5135 23:19:55.397676 CA PerBit enable=1, Macro0, CA PI delay=34
5136 23:19:55.397761
5137 23:19:55.400606 [CBTSetCACLKResult] CA Dly = 34
5138 23:19:55.400742 CS Dly: 7 (0~39)
5139 23:19:55.400811
5140 23:19:55.404237 ----->DramcWriteLeveling(PI) begin...
5141 23:19:55.404323 ==
5142 23:19:55.407521 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 23:19:55.413875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 23:19:55.413979 ==
5145 23:19:55.417260 Write leveling (Byte 0): 35 => 35
5146 23:19:55.417346 Write leveling (Byte 1): 28 => 28
5147 23:19:55.420581 DramcWriteLeveling(PI) end<-----
5148 23:19:55.420705
5149 23:19:55.424076 ==
5150 23:19:55.427223 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 23:19:55.430559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 23:19:55.430646 ==
5153 23:19:55.433864 [Gating] SW mode calibration
5154 23:19:55.440433 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5155 23:19:55.444040 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5156 23:19:55.450644 0 14 0 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
5157 23:19:55.454078 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 23:19:55.456951 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 23:19:55.464045 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 23:19:55.466948 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 23:19:55.470332 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 23:19:55.477179 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5163 23:19:55.480480 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (1 0)
5164 23:19:55.483738 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5165 23:19:55.490575 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 23:19:55.493372 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 23:19:55.496896 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 23:19:55.503486 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 23:19:55.507146 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 23:19:55.510528 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5171 23:19:55.516850 0 15 28 | B1->B0 | 2c2c 4343 | 0 0 | (0 0) (0 0)
5172 23:19:55.520034 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 23:19:55.523372 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 23:19:55.529953 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 23:19:55.533297 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 23:19:55.536599 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 23:19:55.540163 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 23:19:55.546803 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5179 23:19:55.550178 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5180 23:19:55.553846 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 23:19:55.560204 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 23:19:55.563534 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 23:19:55.566843 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 23:19:55.573292 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 23:19:55.576685 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 23:19:55.580265 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 23:19:55.587008 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 23:19:55.589860 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 23:19:55.593455 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 23:19:55.600273 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 23:19:55.603391 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 23:19:55.606903 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 23:19:55.613311 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 23:19:55.616386 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5195 23:19:55.619834 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5196 23:19:55.626210 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 23:19:55.626311 Total UI for P1: 0, mck2ui 16
5198 23:19:55.633389 best dqsien dly found for B0: ( 1, 2, 26)
5199 23:19:55.633488 Total UI for P1: 0, mck2ui 16
5200 23:19:55.640118 best dqsien dly found for B1: ( 1, 2, 28)
5201 23:19:55.642864 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5202 23:19:55.646409 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5203 23:19:55.646498
5204 23:19:55.649717 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5205 23:19:55.653051 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5206 23:19:55.656414 [Gating] SW calibration Done
5207 23:19:55.656501 ==
5208 23:19:55.659717 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 23:19:55.662884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 23:19:55.662973 ==
5211 23:19:55.666122 RX Vref Scan: 0
5212 23:19:55.666207
5213 23:19:55.666273 RX Vref 0 -> 0, step: 1
5214 23:19:55.666337
5215 23:19:55.669960 RX Delay -80 -> 252, step: 8
5216 23:19:55.673132 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5217 23:19:55.679793 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5218 23:19:55.682864 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5219 23:19:55.686336 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5220 23:19:55.689728 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5221 23:19:55.692781 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5222 23:19:55.696259 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5223 23:19:55.702968 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5224 23:19:55.706330 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5225 23:19:55.709442 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5226 23:19:55.713003 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5227 23:19:55.716343 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5228 23:19:55.719532 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5229 23:19:55.726127 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5230 23:19:55.729496 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5231 23:19:55.732863 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5232 23:19:55.732951 ==
5233 23:19:55.736325 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 23:19:55.739274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 23:19:55.739375 ==
5236 23:19:55.743144 DQS Delay:
5237 23:19:55.743230 DQS0 = 0, DQS1 = 0
5238 23:19:55.745928 DQM Delay:
5239 23:19:55.746011 DQM0 = 106, DQM1 = 91
5240 23:19:55.746076 DQ Delay:
5241 23:19:55.749405 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5242 23:19:55.752583 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5243 23:19:55.755913 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =87
5244 23:19:55.759731 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5245 23:19:55.759821
5246 23:19:55.763138
5247 23:19:55.763222 ==
5248 23:19:55.765942 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 23:19:55.769410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 23:19:55.769497 ==
5251 23:19:55.769566
5252 23:19:55.769626
5253 23:19:55.772766 TX Vref Scan disable
5254 23:19:55.772851 == TX Byte 0 ==
5255 23:19:55.779891 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5256 23:19:55.782817 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5257 23:19:55.782908 == TX Byte 1 ==
5258 23:19:55.789510 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5259 23:19:55.792677 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5260 23:19:55.792786 ==
5261 23:19:55.795860 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 23:19:55.799301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 23:19:55.799389 ==
5264 23:19:55.799456
5265 23:19:55.799517
5266 23:19:55.802689 TX Vref Scan disable
5267 23:19:55.805862 == TX Byte 0 ==
5268 23:19:55.809143 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5269 23:19:55.812879 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5270 23:19:55.815684 == TX Byte 1 ==
5271 23:19:55.819345 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5272 23:19:55.822640 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5273 23:19:55.822728
5274 23:19:55.825512 [DATLAT]
5275 23:19:55.825596 Freq=933, CH0 RK0
5276 23:19:55.825664
5277 23:19:55.829040 DATLAT Default: 0xd
5278 23:19:55.829124 0, 0xFFFF, sum = 0
5279 23:19:55.832354 1, 0xFFFF, sum = 0
5280 23:19:55.832439 2, 0xFFFF, sum = 0
5281 23:19:55.835612 3, 0xFFFF, sum = 0
5282 23:19:55.835698 4, 0xFFFF, sum = 0
5283 23:19:55.839026 5, 0xFFFF, sum = 0
5284 23:19:55.839113 6, 0xFFFF, sum = 0
5285 23:19:55.842285 7, 0xFFFF, sum = 0
5286 23:19:55.842373 8, 0xFFFF, sum = 0
5287 23:19:55.845708 9, 0xFFFF, sum = 0
5288 23:19:55.845795 10, 0x0, sum = 1
5289 23:19:55.849173 11, 0x0, sum = 2
5290 23:19:55.849263 12, 0x0, sum = 3
5291 23:19:55.852426 13, 0x0, sum = 4
5292 23:19:55.852512 best_step = 11
5293 23:19:55.852579
5294 23:19:55.852642 ==
5295 23:19:55.855830 Dram Type= 6, Freq= 0, CH_0, rank 0
5296 23:19:55.862383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 23:19:55.862478 ==
5298 23:19:55.862547 RX Vref Scan: 1
5299 23:19:55.862608
5300 23:19:55.865894 RX Vref 0 -> 0, step: 1
5301 23:19:55.865979
5302 23:19:55.869253 RX Delay -53 -> 252, step: 4
5303 23:19:55.869336
5304 23:19:55.872321 Set Vref, RX VrefLevel [Byte0]: 59
5305 23:19:55.875517 [Byte1]: 49
5306 23:19:55.875606
5307 23:19:55.879204 Final RX Vref Byte 0 = 59 to rank0
5308 23:19:55.882571 Final RX Vref Byte 1 = 49 to rank0
5309 23:19:55.885752 Final RX Vref Byte 0 = 59 to rank1
5310 23:19:55.889150 Final RX Vref Byte 1 = 49 to rank1==
5311 23:19:55.892282 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 23:19:55.895485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 23:19:55.895573 ==
5314 23:19:55.899141 DQS Delay:
5315 23:19:55.899227 DQS0 = 0, DQS1 = 0
5316 23:19:55.899295 DQM Delay:
5317 23:19:55.902152 DQM0 = 107, DQM1 = 91
5318 23:19:55.902237 DQ Delay:
5319 23:19:55.905665 DQ0 =108, DQ1 =106, DQ2 =102, DQ3 =106
5320 23:19:55.908688 DQ4 =108, DQ5 =98, DQ6 =120, DQ7 =114
5321 23:19:55.912240 DQ8 =86, DQ9 =76, DQ10 =92, DQ11 =90
5322 23:19:55.915459 DQ12 =94, DQ13 =94, DQ14 =104, DQ15 =98
5323 23:19:55.915552
5324 23:19:55.915620
5325 23:19:55.925605 [DQSOSCAuto] RK0, (LSB)MR18= 0x211d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5326 23:19:55.928855 CH0 RK0: MR19=505, MR18=211D
5327 23:19:55.935177 CH0_RK0: MR19=0x505, MR18=0x211D, DQSOSC=411, MR23=63, INC=64, DEC=42
5328 23:19:55.935280
5329 23:19:55.938569 ----->DramcWriteLeveling(PI) begin...
5330 23:19:55.938660 ==
5331 23:19:55.942136 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 23:19:55.945398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 23:19:55.945493 ==
5334 23:19:55.948764 Write leveling (Byte 0): 33 => 33
5335 23:19:55.952158 Write leveling (Byte 1): 28 => 28
5336 23:19:55.955432 DramcWriteLeveling(PI) end<-----
5337 23:19:55.955520
5338 23:19:55.955585 ==
5339 23:19:55.958950 Dram Type= 6, Freq= 0, CH_0, rank 1
5340 23:19:55.961875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 23:19:55.961972 ==
5342 23:19:55.965150 [Gating] SW mode calibration
5343 23:19:55.971615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5344 23:19:55.978473 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5345 23:19:55.981931 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 23:19:55.985290 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 23:19:55.991683 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 23:19:55.994607 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 23:19:55.998058 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 23:19:56.005012 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 23:19:56.007871 0 14 24 | B1->B0 | 3333 3232 | 0 0 | (0 1) (1 0)
5352 23:19:56.011635 0 14 28 | B1->B0 | 2b2b 2626 | 0 0 | (0 1) (0 0)
5353 23:19:56.018386 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 23:19:56.021402 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 23:19:56.024594 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 23:19:56.031122 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 23:19:56.034429 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 23:19:56.037840 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 23:19:56.044888 0 15 24 | B1->B0 | 2525 2b2b | 0 0 | (1 1) (0 0)
5360 23:19:56.047784 0 15 28 | B1->B0 | 3434 4141 | 1 1 | (0 0) (0 0)
5361 23:19:56.051118 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 23:19:56.057838 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 23:19:56.061132 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 23:19:56.064417 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 23:19:56.070812 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 23:19:56.074114 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 23:19:56.077710 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 23:19:56.084367 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5369 23:19:56.087588 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 23:19:56.090999 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 23:19:56.097825 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 23:19:56.100665 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 23:19:56.104441 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 23:19:56.110943 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 23:19:56.113940 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:19:56.117662 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:19:56.124218 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:19:56.127038 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:19:56.130994 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:19:56.137644 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:19:56.140748 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:19:56.143644 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:19:56.150479 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:19:56.153654 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5385 23:19:56.157217 Total UI for P1: 0, mck2ui 16
5386 23:19:56.160341 best dqsien dly found for B1: ( 1, 2, 26)
5387 23:19:56.163755 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 23:19:56.167143 Total UI for P1: 0, mck2ui 16
5389 23:19:56.170210 best dqsien dly found for B0: ( 1, 2, 28)
5390 23:19:56.173381 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5391 23:19:56.176936 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5392 23:19:56.177030
5393 23:19:56.180219 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5394 23:19:56.186919 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5395 23:19:56.187026 [Gating] SW calibration Done
5396 23:19:56.187097 ==
5397 23:19:56.190062 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 23:19:56.196955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 23:19:56.197057 ==
5400 23:19:56.197128 RX Vref Scan: 0
5401 23:19:56.197190
5402 23:19:56.200212 RX Vref 0 -> 0, step: 1
5403 23:19:56.200296
5404 23:19:56.203347 RX Delay -80 -> 252, step: 8
5405 23:19:56.207026 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5406 23:19:56.210051 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5407 23:19:56.213286 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5408 23:19:56.216599 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5409 23:19:56.223663 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5410 23:19:56.226681 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5411 23:19:56.230095 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5412 23:19:56.233571 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5413 23:19:56.236697 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5414 23:19:56.240158 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5415 23:19:56.246715 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5416 23:19:56.250237 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5417 23:19:56.253534 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5418 23:19:56.256793 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5419 23:19:56.260063 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5420 23:19:56.263411 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5421 23:19:56.266860 ==
5422 23:19:56.266952 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 23:19:56.273529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 23:19:56.273629 ==
5425 23:19:56.273698 DQS Delay:
5426 23:19:56.276626 DQS0 = 0, DQS1 = 0
5427 23:19:56.276750 DQM Delay:
5428 23:19:56.280167 DQM0 = 104, DQM1 = 90
5429 23:19:56.280254 DQ Delay:
5430 23:19:56.283322 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5431 23:19:56.286581 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5432 23:19:56.290348 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5433 23:19:56.293801 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5434 23:19:56.293892
5435 23:19:56.293960
5436 23:19:56.294021 ==
5437 23:19:56.297022 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 23:19:56.300427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 23:19:56.300515 ==
5440 23:19:56.300582
5441 23:19:56.300649
5442 23:19:56.303698 TX Vref Scan disable
5443 23:19:56.306803 == TX Byte 0 ==
5444 23:19:56.310492 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5445 23:19:56.313295 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5446 23:19:56.316701 == TX Byte 1 ==
5447 23:19:56.320221 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5448 23:19:56.323381 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5449 23:19:56.323473 ==
5450 23:19:56.326900 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 23:19:56.333347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 23:19:56.333466 ==
5453 23:19:56.333536
5454 23:19:56.333598
5455 23:19:56.333657 TX Vref Scan disable
5456 23:19:56.337082 == TX Byte 0 ==
5457 23:19:56.340813 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5458 23:19:56.347362 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5459 23:19:56.347470 == TX Byte 1 ==
5460 23:19:56.350922 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5461 23:19:56.357407 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5462 23:19:56.357513
5463 23:19:56.357582 [DATLAT]
5464 23:19:56.357644 Freq=933, CH0 RK1
5465 23:19:56.357705
5466 23:19:56.360512 DATLAT Default: 0xb
5467 23:19:56.360598 0, 0xFFFF, sum = 0
5468 23:19:56.363931 1, 0xFFFF, sum = 0
5469 23:19:56.364018 2, 0xFFFF, sum = 0
5470 23:19:56.367203 3, 0xFFFF, sum = 0
5471 23:19:56.367291 4, 0xFFFF, sum = 0
5472 23:19:56.370707 5, 0xFFFF, sum = 0
5473 23:19:56.374172 6, 0xFFFF, sum = 0
5474 23:19:56.374263 7, 0xFFFF, sum = 0
5475 23:19:56.377463 8, 0xFFFF, sum = 0
5476 23:19:56.377551 9, 0xFFFF, sum = 0
5477 23:19:56.380728 10, 0x0, sum = 1
5478 23:19:56.380815 11, 0x0, sum = 2
5479 23:19:56.380883 12, 0x0, sum = 3
5480 23:19:56.383935 13, 0x0, sum = 4
5481 23:19:56.384021 best_step = 11
5482 23:19:56.384088
5483 23:19:56.387104 ==
5484 23:19:56.387191 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 23:19:56.393762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 23:19:56.393864 ==
5487 23:19:56.393933 RX Vref Scan: 0
5488 23:19:56.393994
5489 23:19:56.397156 RX Vref 0 -> 0, step: 1
5490 23:19:56.397242
5491 23:19:56.400262 RX Delay -53 -> 252, step: 4
5492 23:19:56.403624 iDelay=203, Bit 0, Center 102 (15 ~ 190) 176
5493 23:19:56.410211 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5494 23:19:56.413656 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5495 23:19:56.416960 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5496 23:19:56.420275 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5497 23:19:56.423869 iDelay=203, Bit 5, Center 98 (11 ~ 186) 176
5498 23:19:56.427432 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5499 23:19:56.433964 iDelay=203, Bit 7, Center 110 (23 ~ 198) 176
5500 23:19:56.437385 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5501 23:19:56.440854 iDelay=203, Bit 9, Center 78 (-5 ~ 162) 168
5502 23:19:56.443722 iDelay=203, Bit 10, Center 92 (7 ~ 178) 172
5503 23:19:56.447428 iDelay=203, Bit 11, Center 90 (7 ~ 174) 168
5504 23:19:56.453940 iDelay=203, Bit 12, Center 98 (15 ~ 182) 168
5505 23:19:56.457103 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5506 23:19:56.460630 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5507 23:19:56.463640 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5508 23:19:56.463731 ==
5509 23:19:56.466851 Dram Type= 6, Freq= 0, CH_0, rank 1
5510 23:19:56.470420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 23:19:56.473767 ==
5512 23:19:56.473859 DQS Delay:
5513 23:19:56.473926 DQS0 = 0, DQS1 = 0
5514 23:19:56.477086 DQM Delay:
5515 23:19:56.477171 DQM0 = 104, DQM1 = 91
5516 23:19:56.480387 DQ Delay:
5517 23:19:56.483730 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5518 23:19:56.486807 DQ4 =104, DQ5 =98, DQ6 =114, DQ7 =110
5519 23:19:56.489938 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =90
5520 23:19:56.493425 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5521 23:19:56.493517
5522 23:19:56.493586
5523 23:19:56.499960 [DQSOSCAuto] RK1, (LSB)MR18= 0x2606, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
5524 23:19:56.503422 CH0 RK1: MR19=505, MR18=2606
5525 23:19:56.509727 CH0_RK1: MR19=0x505, MR18=0x2606, DQSOSC=409, MR23=63, INC=64, DEC=43
5526 23:19:56.513112 [RxdqsGatingPostProcess] freq 933
5527 23:19:56.520101 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5528 23:19:56.520215 best DQS0 dly(2T, 0.5T) = (0, 10)
5529 23:19:56.523369 best DQS1 dly(2T, 0.5T) = (0, 10)
5530 23:19:56.526272 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5531 23:19:56.529711 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5532 23:19:56.533139 best DQS0 dly(2T, 0.5T) = (0, 10)
5533 23:19:56.536294 best DQS1 dly(2T, 0.5T) = (0, 10)
5534 23:19:56.539556 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5535 23:19:56.542996 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5536 23:19:56.546239 Pre-setting of DQS Precalculation
5537 23:19:56.552852 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5538 23:19:56.552962 ==
5539 23:19:56.556274 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 23:19:56.559657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 23:19:56.559751 ==
5542 23:19:56.566117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5543 23:19:56.569161 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5544 23:19:56.573567 [CA 0] Center 37 (7~68) winsize 62
5545 23:19:56.576483 [CA 1] Center 37 (7~68) winsize 62
5546 23:19:56.580202 [CA 2] Center 35 (5~66) winsize 62
5547 23:19:56.583224 [CA 3] Center 35 (5~65) winsize 61
5548 23:19:56.586483 [CA 4] Center 35 (5~66) winsize 62
5549 23:19:56.589797 [CA 5] Center 34 (5~64) winsize 60
5550 23:19:56.589892
5551 23:19:56.593131 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5552 23:19:56.593221
5553 23:19:56.596796 [CATrainingPosCal] consider 1 rank data
5554 23:19:56.600240 u2DelayCellTimex100 = 270/100 ps
5555 23:19:56.603415 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5556 23:19:56.606499 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5557 23:19:56.613533 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5558 23:19:56.616384 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5559 23:19:56.620223 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5560 23:19:56.623461 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5561 23:19:56.623559
5562 23:19:56.626412 CA PerBit enable=1, Macro0, CA PI delay=34
5563 23:19:56.626500
5564 23:19:56.629754 [CBTSetCACLKResult] CA Dly = 34
5565 23:19:56.629845 CS Dly: 7 (0~38)
5566 23:19:56.633291 ==
5567 23:19:56.636414 Dram Type= 6, Freq= 0, CH_1, rank 1
5568 23:19:56.639542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 23:19:56.639637 ==
5570 23:19:56.643187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5571 23:19:56.649791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5572 23:19:56.653421 [CA 0] Center 38 (8~69) winsize 62
5573 23:19:56.656852 [CA 1] Center 38 (7~69) winsize 63
5574 23:19:56.659961 [CA 2] Center 35 (5~66) winsize 62
5575 23:19:56.663130 [CA 3] Center 35 (5~65) winsize 61
5576 23:19:56.666789 [CA 4] Center 35 (5~65) winsize 61
5577 23:19:56.669841 [CA 5] Center 35 (5~65) winsize 61
5578 23:19:56.669942
5579 23:19:56.673362 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5580 23:19:56.673456
5581 23:19:56.676263 [CATrainingPosCal] consider 2 rank data
5582 23:19:56.679781 u2DelayCellTimex100 = 270/100 ps
5583 23:19:56.683137 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5584 23:19:56.689622 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5585 23:19:56.692968 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5586 23:19:56.696135 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5587 23:19:56.699971 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5588 23:19:56.702740 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5589 23:19:56.702832
5590 23:19:56.706477 CA PerBit enable=1, Macro0, CA PI delay=34
5591 23:19:56.706568
5592 23:19:56.709553 [CBTSetCACLKResult] CA Dly = 34
5593 23:19:56.712966 CS Dly: 7 (0~39)
5594 23:19:56.713073
5595 23:19:56.716234 ----->DramcWriteLeveling(PI) begin...
5596 23:19:56.716322 ==
5597 23:19:56.719295 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 23:19:56.722943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 23:19:56.723036 ==
5600 23:19:56.726209 Write leveling (Byte 0): 24 => 24
5601 23:19:56.729592 Write leveling (Byte 1): 31 => 31
5602 23:19:56.732629 DramcWriteLeveling(PI) end<-----
5603 23:19:56.732757
5604 23:19:56.732826 ==
5605 23:19:56.736021 Dram Type= 6, Freq= 0, CH_1, rank 0
5606 23:19:56.739638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 23:19:56.739735 ==
5608 23:19:56.742880 [Gating] SW mode calibration
5609 23:19:56.749329 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5610 23:19:56.756245 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5611 23:19:56.759121 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 23:19:56.762907 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 23:19:56.769103 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 23:19:56.772808 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 23:19:56.775894 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 23:19:56.782838 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5617 23:19:56.786137 0 14 24 | B1->B0 | 3131 3030 | 1 1 | (1 1) (1 0)
5618 23:19:56.789222 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5619 23:19:56.795758 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 23:19:56.799277 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 23:19:56.802260 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 23:19:56.809339 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 23:19:56.812707 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 23:19:56.815688 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 23:19:56.819063 0 15 24 | B1->B0 | 2828 3030 | 0 0 | (0 0) (1 1)
5626 23:19:56.825580 0 15 28 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5627 23:19:56.829220 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 23:19:56.832414 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 23:19:56.839223 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 23:19:56.842533 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 23:19:56.845770 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 23:19:56.852072 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 23:19:56.855455 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5634 23:19:56.858705 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 23:19:56.865476 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 23:19:56.868977 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 23:19:56.872193 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 23:19:56.879165 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 23:19:56.882276 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 23:19:56.885514 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 23:19:56.892430 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 23:19:56.895449 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 23:19:56.898686 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 23:19:56.905418 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 23:19:56.908927 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 23:19:56.912199 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 23:19:56.919195 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:19:56.922067 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5649 23:19:56.925377 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5650 23:19:56.931812 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5651 23:19:56.931924 Total UI for P1: 0, mck2ui 16
5652 23:19:56.938779 best dqsien dly found for B0: ( 1, 2, 22)
5653 23:19:56.942082 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 23:19:56.945412 Total UI for P1: 0, mck2ui 16
5655 23:19:56.948537 best dqsien dly found for B1: ( 1, 2, 28)
5656 23:19:56.952136 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5657 23:19:56.955252 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5658 23:19:56.955346
5659 23:19:56.958676 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5660 23:19:56.961972 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5661 23:19:56.965399 [Gating] SW calibration Done
5662 23:19:56.965495 ==
5663 23:19:56.968935 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 23:19:56.972108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 23:19:56.972199 ==
5666 23:19:56.975492 RX Vref Scan: 0
5667 23:19:56.975581
5668 23:19:56.979006 RX Vref 0 -> 0, step: 1
5669 23:19:56.979093
5670 23:19:56.979160 RX Delay -80 -> 252, step: 8
5671 23:19:56.985374 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5672 23:19:56.988366 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5673 23:19:56.992095 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5674 23:19:56.995014 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5675 23:19:56.998587 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5676 23:19:57.001986 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5677 23:19:57.008446 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5678 23:19:57.011833 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5679 23:19:57.015046 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5680 23:19:57.018191 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5681 23:19:57.022148 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5682 23:19:57.025108 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5683 23:19:57.031566 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5684 23:19:57.034780 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5685 23:19:57.038099 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5686 23:19:57.041776 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5687 23:19:57.041868 ==
5688 23:19:57.045209 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 23:19:57.048024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 23:19:57.051507 ==
5691 23:19:57.051597 DQS Delay:
5692 23:19:57.051664 DQS0 = 0, DQS1 = 0
5693 23:19:57.055142 DQM Delay:
5694 23:19:57.055229 DQM0 = 101, DQM1 = 95
5695 23:19:57.058535 DQ Delay:
5696 23:19:57.061679 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5697 23:19:57.064930 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5698 23:19:57.065021 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5699 23:19:57.071674 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5700 23:19:57.071774
5701 23:19:57.071843
5702 23:19:57.071904 ==
5703 23:19:57.074767 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 23:19:57.078112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 23:19:57.078203 ==
5706 23:19:57.078271
5707 23:19:57.078333
5708 23:19:57.081265 TX Vref Scan disable
5709 23:19:57.081351 == TX Byte 0 ==
5710 23:19:57.088308 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5711 23:19:57.091412 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5712 23:19:57.091509 == TX Byte 1 ==
5713 23:19:57.098058 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5714 23:19:57.101189 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5715 23:19:57.101285 ==
5716 23:19:57.104963 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 23:19:57.107868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 23:19:57.107961 ==
5719 23:19:57.108027
5720 23:19:57.111155
5721 23:19:57.111241 TX Vref Scan disable
5722 23:19:57.114401 == TX Byte 0 ==
5723 23:19:57.117964 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5724 23:19:57.121278 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5725 23:19:57.124510 == TX Byte 1 ==
5726 23:19:57.128155 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5727 23:19:57.134371 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5728 23:19:57.134479
5729 23:19:57.134548 [DATLAT]
5730 23:19:57.134609 Freq=933, CH1 RK0
5731 23:19:57.134670
5732 23:19:57.137618 DATLAT Default: 0xd
5733 23:19:57.137705 0, 0xFFFF, sum = 0
5734 23:19:57.140914 1, 0xFFFF, sum = 0
5735 23:19:57.141001 2, 0xFFFF, sum = 0
5736 23:19:57.144279 3, 0xFFFF, sum = 0
5737 23:19:57.147761 4, 0xFFFF, sum = 0
5738 23:19:57.147851 5, 0xFFFF, sum = 0
5739 23:19:57.150588 6, 0xFFFF, sum = 0
5740 23:19:57.150675 7, 0xFFFF, sum = 0
5741 23:19:57.154406 8, 0xFFFF, sum = 0
5742 23:19:57.154496 9, 0xFFFF, sum = 0
5743 23:19:57.157360 10, 0x0, sum = 1
5744 23:19:57.157446 11, 0x0, sum = 2
5745 23:19:57.161032 12, 0x0, sum = 3
5746 23:19:57.161120 13, 0x0, sum = 4
5747 23:19:57.161187 best_step = 11
5748 23:19:57.164332
5749 23:19:57.164417 ==
5750 23:19:57.167467 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 23:19:57.170848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 23:19:57.170937 ==
5753 23:19:57.171004 RX Vref Scan: 1
5754 23:19:57.171068
5755 23:19:57.174278 RX Vref 0 -> 0, step: 1
5756 23:19:57.174362
5757 23:19:57.177409 RX Delay -53 -> 252, step: 4
5758 23:19:57.177494
5759 23:19:57.180962 Set Vref, RX VrefLevel [Byte0]: 52
5760 23:19:57.184416 [Byte1]: 52
5761 23:19:57.184530
5762 23:19:57.187467 Final RX Vref Byte 0 = 52 to rank0
5763 23:19:57.190858 Final RX Vref Byte 1 = 52 to rank0
5764 23:19:57.194413 Final RX Vref Byte 0 = 52 to rank1
5765 23:19:57.197674 Final RX Vref Byte 1 = 52 to rank1==
5766 23:19:57.200664 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 23:19:57.204102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 23:19:57.207502 ==
5769 23:19:57.207592 DQS Delay:
5770 23:19:57.207659 DQS0 = 0, DQS1 = 0
5771 23:19:57.210974 DQM Delay:
5772 23:19:57.211063 DQM0 = 104, DQM1 = 97
5773 23:19:57.214182 DQ Delay:
5774 23:19:57.217229 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5775 23:19:57.220639 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =102
5776 23:19:57.224190 DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =92
5777 23:19:57.227214 DQ12 =108, DQ13 =100, DQ14 =104, DQ15 =102
5778 23:19:57.227298
5779 23:19:57.227362
5780 23:19:57.234118 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5781 23:19:57.237503 CH1 RK0: MR19=505, MR18=1D35
5782 23:19:57.243912 CH1_RK0: MR19=0x505, MR18=0x1D35, DQSOSC=405, MR23=63, INC=66, DEC=44
5783 23:19:57.244017
5784 23:19:57.247114 ----->DramcWriteLeveling(PI) begin...
5785 23:19:57.247193 ==
5786 23:19:57.250346 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 23:19:57.253899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 23:19:57.253984 ==
5789 23:19:57.257079 Write leveling (Byte 0): 29 => 29
5790 23:19:57.260897 Write leveling (Byte 1): 29 => 29
5791 23:19:57.263956 DramcWriteLeveling(PI) end<-----
5792 23:19:57.264032
5793 23:19:57.264092 ==
5794 23:19:57.267260 Dram Type= 6, Freq= 0, CH_1, rank 1
5795 23:19:57.270423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 23:19:57.273830 ==
5797 23:19:57.273910 [Gating] SW mode calibration
5798 23:19:57.280420 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5799 23:19:57.286829 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5800 23:19:57.290270 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 23:19:57.296924 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 23:19:57.300419 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 23:19:57.303931 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 23:19:57.310412 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 23:19:57.313423 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 23:19:57.316819 0 14 24 | B1->B0 | 2f2f 3434 | 1 0 | (1 1) (0 1)
5807 23:19:57.323412 0 14 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 0)
5808 23:19:57.326844 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5809 23:19:57.330228 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 23:19:57.337198 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 23:19:57.340104 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 23:19:57.343502 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 23:19:57.350403 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 23:19:57.353229 0 15 24 | B1->B0 | 2e2e 2929 | 1 0 | (0 0) (0 0)
5815 23:19:57.356652 0 15 28 | B1->B0 | 4242 3636 | 0 1 | (0 0) (0 0)
5816 23:19:57.363402 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 23:19:57.366663 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 23:19:57.370157 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 23:19:57.373628 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 23:19:57.379860 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 23:19:57.383158 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 23:19:57.386745 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 23:19:57.393194 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5824 23:19:57.396393 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 23:19:57.399718 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 23:19:57.406713 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 23:19:57.409663 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 23:19:57.413103 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 23:19:57.419626 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 23:19:57.423143 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 23:19:57.426333 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 23:19:57.432904 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 23:19:57.436165 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 23:19:57.439671 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 23:19:57.446296 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 23:19:57.449588 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 23:19:57.452925 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 23:19:57.459690 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 23:19:57.463005 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 23:19:57.466384 Total UI for P1: 0, mck2ui 16
5841 23:19:57.469753 best dqsien dly found for B0: ( 1, 2, 26)
5842 23:19:57.472899 Total UI for P1: 0, mck2ui 16
5843 23:19:57.476429 best dqsien dly found for B1: ( 1, 2, 26)
5844 23:19:57.479737 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5845 23:19:57.482671 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5846 23:19:57.482760
5847 23:19:57.486334 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5848 23:19:57.489491 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5849 23:19:57.492594 [Gating] SW calibration Done
5850 23:19:57.492731 ==
5851 23:19:57.496107 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 23:19:57.499613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 23:19:57.502816 ==
5854 23:19:57.502904 RX Vref Scan: 0
5855 23:19:57.502970
5856 23:19:57.505893 RX Vref 0 -> 0, step: 1
5857 23:19:57.505977
5858 23:19:57.509179 RX Delay -80 -> 252, step: 8
5859 23:19:57.512597 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5860 23:19:57.516071 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5861 23:19:57.519064 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5862 23:19:57.522974 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5863 23:19:57.526137 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5864 23:19:57.532628 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5865 23:19:57.536039 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5866 23:19:57.539612 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5867 23:19:57.542656 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5868 23:19:57.546154 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5869 23:19:57.552384 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5870 23:19:57.556112 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5871 23:19:57.559214 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5872 23:19:57.562712 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5873 23:19:57.565972 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5874 23:19:57.569250 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5875 23:19:57.572573 ==
5876 23:19:57.575708 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 23:19:57.579151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 23:19:57.579234 ==
5879 23:19:57.579298 DQS Delay:
5880 23:19:57.582386 DQS0 = 0, DQS1 = 0
5881 23:19:57.582460 DQM Delay:
5882 23:19:57.585837 DQM0 = 103, DQM1 = 96
5883 23:19:57.585921 DQ Delay:
5884 23:19:57.589291 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5885 23:19:57.592416 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5886 23:19:57.595444 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5887 23:19:57.599176 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5888 23:19:57.599259
5889 23:19:57.599325
5890 23:19:57.599384 ==
5891 23:19:57.602493 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 23:19:57.605711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 23:19:57.609147 ==
5894 23:19:57.609229
5895 23:19:57.609291
5896 23:19:57.609350 TX Vref Scan disable
5897 23:19:57.612593 == TX Byte 0 ==
5898 23:19:57.615770 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5899 23:19:57.618952 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5900 23:19:57.622306 == TX Byte 1 ==
5901 23:19:57.625671 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5902 23:19:57.628953 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5903 23:19:57.629033 ==
5904 23:19:57.632577 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 23:19:57.639309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 23:19:57.639408 ==
5907 23:19:57.639476
5908 23:19:57.639536
5909 23:19:57.639595 TX Vref Scan disable
5910 23:19:57.643350 == TX Byte 0 ==
5911 23:19:57.646504 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5912 23:19:57.653553 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5913 23:19:57.653682 == TX Byte 1 ==
5914 23:19:57.656394 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5915 23:19:57.663236 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5916 23:19:57.663366
5917 23:19:57.663461 [DATLAT]
5918 23:19:57.663557 Freq=933, CH1 RK1
5919 23:19:57.663645
5920 23:19:57.666366 DATLAT Default: 0xb
5921 23:19:57.666467 0, 0xFFFF, sum = 0
5922 23:19:57.669727 1, 0xFFFF, sum = 0
5923 23:19:57.669804 2, 0xFFFF, sum = 0
5924 23:19:57.673311 3, 0xFFFF, sum = 0
5925 23:19:57.676459 4, 0xFFFF, sum = 0
5926 23:19:57.676567 5, 0xFFFF, sum = 0
5927 23:19:57.679925 6, 0xFFFF, sum = 0
5928 23:19:57.680002 7, 0xFFFF, sum = 0
5929 23:19:57.683336 8, 0xFFFF, sum = 0
5930 23:19:57.683442 9, 0xFFFF, sum = 0
5931 23:19:57.686437 10, 0x0, sum = 1
5932 23:19:57.686516 11, 0x0, sum = 2
5933 23:19:57.686581 12, 0x0, sum = 3
5934 23:19:57.689734 13, 0x0, sum = 4
5935 23:19:57.689835 best_step = 11
5936 23:19:57.689928
5937 23:19:57.693133 ==
5938 23:19:57.693209 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 23:19:57.700091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 23:19:57.700209 ==
5941 23:19:57.700303 RX Vref Scan: 0
5942 23:19:57.700395
5943 23:19:57.703265 RX Vref 0 -> 0, step: 1
5944 23:19:57.703344
5945 23:19:57.706781 RX Delay -45 -> 252, step: 4
5946 23:19:57.710086 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5947 23:19:57.716502 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5948 23:19:57.719977 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5949 23:19:57.723196 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5950 23:19:57.726657 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5951 23:19:57.729776 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5952 23:19:57.733212 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5953 23:19:57.740210 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5954 23:19:57.743053 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5955 23:19:57.746523 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5956 23:19:57.749730 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5957 23:19:57.753156 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5958 23:19:57.759701 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5959 23:19:57.763217 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5960 23:19:57.766360 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5961 23:19:57.769838 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5962 23:19:57.769925 ==
5963 23:19:57.773078 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 23:19:57.779745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 23:19:57.779867 ==
5966 23:19:57.779962 DQS Delay:
5967 23:19:57.782940 DQS0 = 0, DQS1 = 0
5968 23:19:57.783040 DQM Delay:
5969 23:19:57.783133 DQM0 = 105, DQM1 = 96
5970 23:19:57.786366 DQ Delay:
5971 23:19:57.789883 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =104
5972 23:19:57.792942 DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =102
5973 23:19:57.796355 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =92
5974 23:19:57.799665 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =106
5975 23:19:57.799769
5976 23:19:57.799860
5977 23:19:57.806586 [DQSOSCAuto] RK1, (LSB)MR18= 0x22fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5978 23:19:57.809453 CH1 RK1: MR19=504, MR18=22FE
5979 23:19:57.816037 CH1_RK1: MR19=0x504, MR18=0x22FE, DQSOSC=411, MR23=63, INC=64, DEC=42
5980 23:19:57.819702 [RxdqsGatingPostProcess] freq 933
5981 23:19:57.826245 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5982 23:19:57.829467 best DQS0 dly(2T, 0.5T) = (0, 10)
5983 23:19:57.829564 best DQS1 dly(2T, 0.5T) = (0, 10)
5984 23:19:57.833193 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5985 23:19:57.836128 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5986 23:19:57.839876 best DQS0 dly(2T, 0.5T) = (0, 10)
5987 23:19:57.842865 best DQS1 dly(2T, 0.5T) = (0, 10)
5988 23:19:57.846283 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5989 23:19:57.849762 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5990 23:19:57.853150 Pre-setting of DQS Precalculation
5991 23:19:57.859482 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5992 23:19:57.866151 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5993 23:19:57.872884 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5994 23:19:57.872993
5995 23:19:57.873069
5996 23:19:57.876071 [Calibration Summary] 1866 Mbps
5997 23:19:57.876151 CH 0, Rank 0
5998 23:19:57.879573 SW Impedance : PASS
5999 23:19:57.882804 DUTY Scan : NO K
6000 23:19:57.882907 ZQ Calibration : PASS
6001 23:19:57.886210 Jitter Meter : NO K
6002 23:19:57.886286 CBT Training : PASS
6003 23:19:57.889422 Write leveling : PASS
6004 23:19:57.892911 RX DQS gating : PASS
6005 23:19:57.893001 RX DQ/DQS(RDDQC) : PASS
6006 23:19:57.895861 TX DQ/DQS : PASS
6007 23:19:57.899564 RX DATLAT : PASS
6008 23:19:57.899670 RX DQ/DQS(Engine): PASS
6009 23:19:57.902487 TX OE : NO K
6010 23:19:57.902563 All Pass.
6011 23:19:57.902626
6012 23:19:57.906012 CH 0, Rank 1
6013 23:19:57.906086 SW Impedance : PASS
6014 23:19:57.909593 DUTY Scan : NO K
6015 23:19:57.913049 ZQ Calibration : PASS
6016 23:19:57.913153 Jitter Meter : NO K
6017 23:19:57.916310 CBT Training : PASS
6018 23:19:57.919344 Write leveling : PASS
6019 23:19:57.919448 RX DQS gating : PASS
6020 23:19:57.923024 RX DQ/DQS(RDDQC) : PASS
6021 23:19:57.926325 TX DQ/DQS : PASS
6022 23:19:57.926434 RX DATLAT : PASS
6023 23:19:57.929224 RX DQ/DQS(Engine): PASS
6024 23:19:57.929299 TX OE : NO K
6025 23:19:57.932756 All Pass.
6026 23:19:57.932835
6027 23:19:57.932899 CH 1, Rank 0
6028 23:19:57.936110 SW Impedance : PASS
6029 23:19:57.936210 DUTY Scan : NO K
6030 23:19:57.939297 ZQ Calibration : PASS
6031 23:19:57.942675 Jitter Meter : NO K
6032 23:19:57.942779 CBT Training : PASS
6033 23:19:57.945943 Write leveling : PASS
6034 23:19:57.949136 RX DQS gating : PASS
6035 23:19:57.949220 RX DQ/DQS(RDDQC) : PASS
6036 23:19:57.952526 TX DQ/DQS : PASS
6037 23:19:57.956183 RX DATLAT : PASS
6038 23:19:57.956261 RX DQ/DQS(Engine): PASS
6039 23:19:57.959358 TX OE : NO K
6040 23:19:57.959434 All Pass.
6041 23:19:57.959501
6042 23:19:57.962726 CH 1, Rank 1
6043 23:19:57.962825 SW Impedance : PASS
6044 23:19:57.965729 DUTY Scan : NO K
6045 23:19:57.969005 ZQ Calibration : PASS
6046 23:19:57.969082 Jitter Meter : NO K
6047 23:19:57.972462 CBT Training : PASS
6048 23:19:57.975715 Write leveling : PASS
6049 23:19:57.975818 RX DQS gating : PASS
6050 23:19:57.979488 RX DQ/DQS(RDDQC) : PASS
6051 23:19:57.979571 TX DQ/DQS : PASS
6052 23:19:57.982747 RX DATLAT : PASS
6053 23:19:57.985747 RX DQ/DQS(Engine): PASS
6054 23:19:57.985831 TX OE : NO K
6055 23:19:57.989130 All Pass.
6056 23:19:57.989211
6057 23:19:57.989274 DramC Write-DBI off
6058 23:19:57.992524 PER_BANK_REFRESH: Hybrid Mode
6059 23:19:57.995718 TX_TRACKING: ON
6060 23:19:58.002140 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6061 23:19:58.005887 [FAST_K] Save calibration result to emmc
6062 23:19:58.012131 dramc_set_vcore_voltage set vcore to 650000
6063 23:19:58.012249 Read voltage for 400, 6
6064 23:19:58.012346 Vio18 = 0
6065 23:19:58.015343 Vcore = 650000
6066 23:19:58.015454 Vdram = 0
6067 23:19:58.015554 Vddq = 0
6068 23:19:58.018773 Vmddr = 0
6069 23:19:58.022263 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6070 23:19:58.028895 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6071 23:19:58.032224 MEM_TYPE=3, freq_sel=20
6072 23:19:58.032336 sv_algorithm_assistance_LP4_800
6073 23:19:58.038762 ============ PULL DRAM RESETB DOWN ============
6074 23:19:58.042272 ========== PULL DRAM RESETB DOWN end =========
6075 23:19:58.045360 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6076 23:19:58.048733 ===================================
6077 23:19:58.052104 LPDDR4 DRAM CONFIGURATION
6078 23:19:58.055405 ===================================
6079 23:19:58.059048 EX_ROW_EN[0] = 0x0
6080 23:19:58.059158 EX_ROW_EN[1] = 0x0
6081 23:19:58.062195 LP4Y_EN = 0x0
6082 23:19:58.062300 WORK_FSP = 0x0
6083 23:19:58.065074 WL = 0x2
6084 23:19:58.065178 RL = 0x2
6085 23:19:58.068331 BL = 0x2
6086 23:19:58.068432 RPST = 0x0
6087 23:19:58.071737 RD_PRE = 0x0
6088 23:19:58.071812 WR_PRE = 0x1
6089 23:19:58.075160 WR_PST = 0x0
6090 23:19:58.075264 DBI_WR = 0x0
6091 23:19:58.078551 DBI_RD = 0x0
6092 23:19:58.078654 OTF = 0x1
6093 23:19:58.081748 ===================================
6094 23:19:58.085174 ===================================
6095 23:19:58.088765 ANA top config
6096 23:19:58.092093 ===================================
6097 23:19:58.095208 DLL_ASYNC_EN = 0
6098 23:19:58.095289 ALL_SLAVE_EN = 1
6099 23:19:58.098438 NEW_RANK_MODE = 1
6100 23:19:58.102211 DLL_IDLE_MODE = 1
6101 23:19:58.105170 LP45_APHY_COMB_EN = 1
6102 23:19:58.105249 TX_ODT_DIS = 1
6103 23:19:58.108507 NEW_8X_MODE = 1
6104 23:19:58.111887 ===================================
6105 23:19:58.115239 ===================================
6106 23:19:58.118305 data_rate = 800
6107 23:19:58.121661 CKR = 1
6108 23:19:58.125117 DQ_P2S_RATIO = 4
6109 23:19:58.128540 ===================================
6110 23:19:58.131789 CA_P2S_RATIO = 4
6111 23:19:58.131871 DQ_CA_OPEN = 0
6112 23:19:58.135057 DQ_SEMI_OPEN = 1
6113 23:19:58.138181 CA_SEMI_OPEN = 1
6114 23:19:58.141711 CA_FULL_RATE = 0
6115 23:19:58.145045 DQ_CKDIV4_EN = 0
6116 23:19:58.148487 CA_CKDIV4_EN = 1
6117 23:19:58.148573 CA_PREDIV_EN = 0
6118 23:19:58.151649 PH8_DLY = 0
6119 23:19:58.154794 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6120 23:19:58.158100 DQ_AAMCK_DIV = 0
6121 23:19:58.161476 CA_AAMCK_DIV = 0
6122 23:19:58.164905 CA_ADMCK_DIV = 4
6123 23:19:58.164988 DQ_TRACK_CA_EN = 0
6124 23:19:58.168226 CA_PICK = 800
6125 23:19:58.171638 CA_MCKIO = 400
6126 23:19:58.174976 MCKIO_SEMI = 400
6127 23:19:58.178033 PLL_FREQ = 3016
6128 23:19:58.181244 DQ_UI_PI_RATIO = 32
6129 23:19:58.184588 CA_UI_PI_RATIO = 32
6130 23:19:58.188148 ===================================
6131 23:19:58.191423 ===================================
6132 23:19:58.191502 memory_type:LPDDR4
6133 23:19:58.194833 GP_NUM : 10
6134 23:19:58.198267 SRAM_EN : 1
6135 23:19:58.198347 MD32_EN : 0
6136 23:19:58.201504 ===================================
6137 23:19:58.204556 [ANA_INIT] >>>>>>>>>>>>>>
6138 23:19:58.208346 <<<<<< [CONFIGURE PHASE]: ANA_TX
6139 23:19:58.211232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6140 23:19:58.214615 ===================================
6141 23:19:58.218002 data_rate = 800,PCW = 0X7400
6142 23:19:58.221247 ===================================
6143 23:19:58.224450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6144 23:19:58.227889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6145 23:19:58.240960 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6146 23:19:58.244241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6147 23:19:58.247675 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6148 23:19:58.251298 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6149 23:19:58.254490 [ANA_INIT] flow start
6150 23:19:58.257724 [ANA_INIT] PLL >>>>>>>>
6151 23:19:58.257808 [ANA_INIT] PLL <<<<<<<<
6152 23:19:58.261341 [ANA_INIT] MIDPI >>>>>>>>
6153 23:19:58.264389 [ANA_INIT] MIDPI <<<<<<<<
6154 23:19:58.264468 [ANA_INIT] DLL >>>>>>>>
6155 23:19:58.267987 [ANA_INIT] flow end
6156 23:19:58.271520 ============ LP4 DIFF to SE enter ============
6157 23:19:58.274405 ============ LP4 DIFF to SE exit ============
6158 23:19:58.277489 [ANA_INIT] <<<<<<<<<<<<<
6159 23:19:58.280775 [Flow] Enable top DCM control >>>>>
6160 23:19:58.284022 [Flow] Enable top DCM control <<<<<
6161 23:19:58.287526 Enable DLL master slave shuffle
6162 23:19:58.294130 ==============================================================
6163 23:19:58.294238 Gating Mode config
6164 23:19:58.300612 ==============================================================
6165 23:19:58.300760 Config description:
6166 23:19:58.310623 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6167 23:19:58.317616 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6168 23:19:58.324238 SELPH_MODE 0: By rank 1: By Phase
6169 23:19:58.327583 ==============================================================
6170 23:19:58.330701 GAT_TRACK_EN = 0
6171 23:19:58.334074 RX_GATING_MODE = 2
6172 23:19:58.337308 RX_GATING_TRACK_MODE = 2
6173 23:19:58.340568 SELPH_MODE = 1
6174 23:19:58.343991 PICG_EARLY_EN = 1
6175 23:19:58.347561 VALID_LAT_VALUE = 1
6176 23:19:58.354124 ==============================================================
6177 23:19:58.357526 Enter into Gating configuration >>>>
6178 23:19:58.360766 Exit from Gating configuration <<<<
6179 23:19:58.360884 Enter into DVFS_PRE_config >>>>>
6180 23:19:58.373954 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6181 23:19:58.377328 Exit from DVFS_PRE_config <<<<<
6182 23:19:58.380251 Enter into PICG configuration >>>>
6183 23:19:58.384056 Exit from PICG configuration <<<<
6184 23:19:58.384155 [RX_INPUT] configuration >>>>>
6185 23:19:58.387303 [RX_INPUT] configuration <<<<<
6186 23:19:58.393741 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6187 23:19:58.397188 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6188 23:19:58.403943 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6189 23:19:58.410428 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6190 23:19:58.417240 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6191 23:19:58.423463 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6192 23:19:58.426864 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6193 23:19:58.430303 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6194 23:19:58.436858 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6195 23:19:58.440443 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6196 23:19:58.443674 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6197 23:19:58.447023 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6198 23:19:58.450429 ===================================
6199 23:19:58.453600 LPDDR4 DRAM CONFIGURATION
6200 23:19:58.457002 ===================================
6201 23:19:58.460186 EX_ROW_EN[0] = 0x0
6202 23:19:58.460276 EX_ROW_EN[1] = 0x0
6203 23:19:58.463661 LP4Y_EN = 0x0
6204 23:19:58.463749 WORK_FSP = 0x0
6205 23:19:58.466997 WL = 0x2
6206 23:19:58.467084 RL = 0x2
6207 23:19:58.470148 BL = 0x2
6208 23:19:58.470236 RPST = 0x0
6209 23:19:58.473494 RD_PRE = 0x0
6210 23:19:58.473580 WR_PRE = 0x1
6211 23:19:58.476950 WR_PST = 0x0
6212 23:19:58.479939 DBI_WR = 0x0
6213 23:19:58.480027 DBI_RD = 0x0
6214 23:19:58.483583 OTF = 0x1
6215 23:19:58.487042 ===================================
6216 23:19:58.490353 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6217 23:19:58.493442 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6218 23:19:58.496696 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6219 23:19:58.500079 ===================================
6220 23:19:58.503376 LPDDR4 DRAM CONFIGURATION
6221 23:19:58.507006 ===================================
6222 23:19:58.510619 EX_ROW_EN[0] = 0x10
6223 23:19:58.510712 EX_ROW_EN[1] = 0x0
6224 23:19:58.513860 LP4Y_EN = 0x0
6225 23:19:58.513974 WORK_FSP = 0x0
6226 23:19:58.516660 WL = 0x2
6227 23:19:58.516764 RL = 0x2
6228 23:19:58.520348 BL = 0x2
6229 23:19:58.520436 RPST = 0x0
6230 23:19:58.523391 RD_PRE = 0x0
6231 23:19:58.523476 WR_PRE = 0x1
6232 23:19:58.526789 WR_PST = 0x0
6233 23:19:58.526876 DBI_WR = 0x0
6234 23:19:58.530251 DBI_RD = 0x0
6235 23:19:58.530368 OTF = 0x1
6236 23:19:58.533357 ===================================
6237 23:19:58.540181 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6238 23:19:58.545028 nWR fixed to 30
6239 23:19:58.548148 [ModeRegInit_LP4] CH0 RK0
6240 23:19:58.548264 [ModeRegInit_LP4] CH0 RK1
6241 23:19:58.551340 [ModeRegInit_LP4] CH1 RK0
6242 23:19:58.554912 [ModeRegInit_LP4] CH1 RK1
6243 23:19:58.555002 match AC timing 19
6244 23:19:58.561383 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6245 23:19:58.564563 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6246 23:19:58.568387 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6247 23:19:58.574598 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6248 23:19:58.578009 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6249 23:19:58.578110 ==
6250 23:19:58.581423 Dram Type= 6, Freq= 0, CH_0, rank 0
6251 23:19:58.584469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6252 23:19:58.584581 ==
6253 23:19:58.591150 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6254 23:19:58.597994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6255 23:19:58.600869 [CA 0] Center 36 (8~64) winsize 57
6256 23:19:58.604519 [CA 1] Center 36 (8~64) winsize 57
6257 23:19:58.608092 [CA 2] Center 36 (8~64) winsize 57
6258 23:19:58.611371 [CA 3] Center 36 (8~64) winsize 57
6259 23:19:58.611463 [CA 4] Center 36 (8~64) winsize 57
6260 23:19:58.614240 [CA 5] Center 36 (8~64) winsize 57
6261 23:19:58.614324
6262 23:19:58.620848 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6263 23:19:58.620961
6264 23:19:58.624122 [CATrainingPosCal] consider 1 rank data
6265 23:19:58.627499 u2DelayCellTimex100 = 270/100 ps
6266 23:19:58.630844 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 23:19:58.634303 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 23:19:58.637657 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 23:19:58.641042 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 23:19:58.644357 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 23:19:58.647684 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 23:19:58.647775
6273 23:19:58.650951 CA PerBit enable=1, Macro0, CA PI delay=36
6274 23:19:58.651039
6275 23:19:58.654319 [CBTSetCACLKResult] CA Dly = 36
6276 23:19:58.657527 CS Dly: 1 (0~32)
6277 23:19:58.657615 ==
6278 23:19:58.661031 Dram Type= 6, Freq= 0, CH_0, rank 1
6279 23:19:58.663924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 23:19:58.664013 ==
6281 23:19:58.670627 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6282 23:19:58.677135 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6283 23:19:58.677245 [CA 0] Center 36 (8~64) winsize 57
6284 23:19:58.680808 [CA 1] Center 36 (8~64) winsize 57
6285 23:19:58.684053 [CA 2] Center 36 (8~64) winsize 57
6286 23:19:58.687341 [CA 3] Center 36 (8~64) winsize 57
6287 23:19:58.690857 [CA 4] Center 36 (8~64) winsize 57
6288 23:19:58.693818 [CA 5] Center 36 (8~64) winsize 57
6289 23:19:58.693908
6290 23:19:58.697266 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6291 23:19:58.697353
6292 23:19:58.700552 [CATrainingPosCal] consider 2 rank data
6293 23:19:58.704088 u2DelayCellTimex100 = 270/100 ps
6294 23:19:58.707155 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 23:19:58.714070 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 23:19:58.717079 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 23:19:58.720420 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 23:19:58.724305 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 23:19:58.727153 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 23:19:58.727245
6301 23:19:58.730497 CA PerBit enable=1, Macro0, CA PI delay=36
6302 23:19:58.730585
6303 23:19:58.733794 [CBTSetCACLKResult] CA Dly = 36
6304 23:19:58.733882 CS Dly: 1 (0~32)
6305 23:19:58.737082
6306 23:19:58.740397 ----->DramcWriteLeveling(PI) begin...
6307 23:19:58.740491 ==
6308 23:19:58.743689 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 23:19:58.746802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 23:19:58.746893 ==
6311 23:19:58.751093 Write leveling (Byte 0): 40 => 8
6312 23:19:58.753815 Write leveling (Byte 1): 32 => 0
6313 23:19:58.756889 DramcWriteLeveling(PI) end<-----
6314 23:19:58.756981
6315 23:19:58.757081 ==
6316 23:19:58.760346 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 23:19:58.763586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 23:19:58.763675 ==
6319 23:19:58.767311 [Gating] SW mode calibration
6320 23:19:58.773921 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6321 23:19:58.777194 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6322 23:19:58.783577 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6323 23:19:58.786907 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6324 23:19:58.790415 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 23:19:58.797093 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6326 23:19:58.800547 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 23:19:58.803706 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 23:19:58.810218 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 23:19:58.813813 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 23:19:58.817063 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6331 23:19:58.820499 Total UI for P1: 0, mck2ui 16
6332 23:19:58.823879 best dqsien dly found for B0: ( 0, 14, 24)
6333 23:19:58.826724 Total UI for P1: 0, mck2ui 16
6334 23:19:58.830388 best dqsien dly found for B1: ( 0, 14, 24)
6335 23:19:58.833761 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6336 23:19:58.837117 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6337 23:19:58.837208
6338 23:19:58.843501 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6339 23:19:58.846792 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6340 23:19:58.850207 [Gating] SW calibration Done
6341 23:19:58.850297 ==
6342 23:19:58.853575 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 23:19:58.856568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 23:19:58.856713 ==
6345 23:19:58.856781 RX Vref Scan: 0
6346 23:19:58.856843
6347 23:19:58.860127 RX Vref 0 -> 0, step: 1
6348 23:19:58.860210
6349 23:19:58.863111 RX Delay -410 -> 252, step: 16
6350 23:19:58.866598 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6351 23:19:58.873205 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6352 23:19:58.876582 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6353 23:19:58.879864 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6354 23:19:58.883219 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6355 23:19:58.889884 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6356 23:19:58.893149 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6357 23:19:58.896584 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6358 23:19:58.899951 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6359 23:19:58.903316 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6360 23:19:58.909797 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6361 23:19:58.913297 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6362 23:19:58.916398 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6363 23:19:58.923308 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6364 23:19:58.926245 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6365 23:19:58.929940 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6366 23:19:58.930033 ==
6367 23:19:58.933106 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 23:19:58.936489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 23:19:58.939470 ==
6370 23:19:58.939556 DQS Delay:
6371 23:19:58.939620 DQS0 = 27, DQS1 = 43
6372 23:19:58.943116 DQM Delay:
6373 23:19:58.943200 DQM0 = 14, DQM1 = 12
6374 23:19:58.946477 DQ Delay:
6375 23:19:58.946563 DQ0 =8, DQ1 =24, DQ2 =8, DQ3 =8
6376 23:19:58.949605 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6377 23:19:58.953060 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6378 23:19:58.956545 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6379 23:19:58.956653
6380 23:19:58.956732
6381 23:19:58.959669 ==
6382 23:19:58.959753 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 23:19:58.966346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 23:19:58.966449 ==
6385 23:19:58.966516
6386 23:19:58.966577
6387 23:19:58.969619 TX Vref Scan disable
6388 23:19:58.969703 == TX Byte 0 ==
6389 23:19:58.973062 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6390 23:19:58.979844 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6391 23:19:58.979945 == TX Byte 1 ==
6392 23:19:58.982572 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6393 23:19:58.989567 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6394 23:19:58.989679 ==
6395 23:19:58.992771 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 23:19:58.996158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 23:19:58.996247 ==
6398 23:19:58.996315
6399 23:19:58.996375
6400 23:19:58.999708 TX Vref Scan disable
6401 23:19:58.999795 == TX Byte 0 ==
6402 23:19:59.002945 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 23:19:59.009207 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 23:19:59.009309 == TX Byte 1 ==
6405 23:19:59.013107 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6406 23:19:59.019446 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6407 23:19:59.019559
6408 23:19:59.019630 [DATLAT]
6409 23:19:59.019692 Freq=400, CH0 RK0
6410 23:19:59.019750
6411 23:19:59.022549 DATLAT Default: 0xf
6412 23:19:59.025981 0, 0xFFFF, sum = 0
6413 23:19:59.026067 1, 0xFFFF, sum = 0
6414 23:19:59.029220 2, 0xFFFF, sum = 0
6415 23:19:59.029307 3, 0xFFFF, sum = 0
6416 23:19:59.032441 4, 0xFFFF, sum = 0
6417 23:19:59.032530 5, 0xFFFF, sum = 0
6418 23:19:59.035733 6, 0xFFFF, sum = 0
6419 23:19:59.035822 7, 0xFFFF, sum = 0
6420 23:19:59.039540 8, 0xFFFF, sum = 0
6421 23:19:59.039632 9, 0xFFFF, sum = 0
6422 23:19:59.042362 10, 0xFFFF, sum = 0
6423 23:19:59.042449 11, 0xFFFF, sum = 0
6424 23:19:59.045703 12, 0xFFFF, sum = 0
6425 23:19:59.045791 13, 0x0, sum = 1
6426 23:19:59.048986 14, 0x0, sum = 2
6427 23:19:59.049074 15, 0x0, sum = 3
6428 23:19:59.052602 16, 0x0, sum = 4
6429 23:19:59.052727 best_step = 14
6430 23:19:59.052795
6431 23:19:59.052856 ==
6432 23:19:59.055828 Dram Type= 6, Freq= 0, CH_0, rank 0
6433 23:19:59.062724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 23:19:59.062832 ==
6435 23:19:59.062902 RX Vref Scan: 1
6436 23:19:59.062967
6437 23:19:59.066008 RX Vref 0 -> 0, step: 1
6438 23:19:59.066096
6439 23:19:59.068914 RX Delay -327 -> 252, step: 8
6440 23:19:59.069006
6441 23:19:59.072454 Set Vref, RX VrefLevel [Byte0]: 59
6442 23:19:59.075399 [Byte1]: 49
6443 23:19:59.075478
6444 23:19:59.078741 Final RX Vref Byte 0 = 59 to rank0
6445 23:19:59.082420 Final RX Vref Byte 1 = 49 to rank0
6446 23:19:59.085470 Final RX Vref Byte 0 = 59 to rank1
6447 23:19:59.088794 Final RX Vref Byte 1 = 49 to rank1==
6448 23:19:59.092092 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 23:19:59.095398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 23:19:59.095488 ==
6451 23:19:59.098693 DQS Delay:
6452 23:19:59.098780 DQS0 = 28, DQS1 = 48
6453 23:19:59.102198 DQM Delay:
6454 23:19:59.102282 DQM0 = 11, DQM1 = 15
6455 23:19:59.105527 DQ Delay:
6456 23:19:59.105612 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6457 23:19:59.108762 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =20
6458 23:19:59.112113 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6459 23:19:59.115412 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6460 23:19:59.115500
6461 23:19:59.115567
6462 23:19:59.125600 [DQSOSCAuto] RK0, (LSB)MR18= 0xb2a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6463 23:19:59.129013 CH0 RK0: MR19=C0C, MR18=B2A9
6464 23:19:59.132442 CH0_RK0: MR19=0xC0C, MR18=0xB2A9, DQSOSC=387, MR23=63, INC=394, DEC=262
6465 23:19:59.135500 ==
6466 23:19:59.138800 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 23:19:59.141881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 23:19:59.141973 ==
6469 23:19:59.145244 [Gating] SW mode calibration
6470 23:19:59.152080 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6471 23:19:59.155296 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6472 23:19:59.162065 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6473 23:19:59.165448 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6474 23:19:59.168640 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 23:19:59.175304 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6476 23:19:59.178870 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 23:19:59.182021 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 23:19:59.188641 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 23:19:59.191712 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 23:19:59.195028 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6481 23:19:59.198328 Total UI for P1: 0, mck2ui 16
6482 23:19:59.202156 best dqsien dly found for B0: ( 0, 14, 24)
6483 23:19:59.205441 Total UI for P1: 0, mck2ui 16
6484 23:19:59.208379 best dqsien dly found for B1: ( 0, 14, 24)
6485 23:19:59.211984 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6486 23:19:59.214911 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6487 23:19:59.215000
6488 23:19:59.221714 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6489 23:19:59.225154 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6490 23:19:59.225250 [Gating] SW calibration Done
6491 23:19:59.228294 ==
6492 23:19:59.228382 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 23:19:59.234873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 23:19:59.234972 ==
6495 23:19:59.235042 RX Vref Scan: 0
6496 23:19:59.235105
6497 23:19:59.238290 RX Vref 0 -> 0, step: 1
6498 23:19:59.238376
6499 23:19:59.242014 RX Delay -410 -> 252, step: 16
6500 23:19:59.245173 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6501 23:19:59.248529 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6502 23:19:59.255220 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6503 23:19:59.258251 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6504 23:19:59.261640 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6505 23:19:59.264943 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6506 23:19:59.271705 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6507 23:19:59.274938 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6508 23:19:59.278075 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6509 23:19:59.281720 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6510 23:19:59.288384 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6511 23:19:59.291678 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6512 23:19:59.294849 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6513 23:19:59.298092 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6514 23:19:59.305112 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6515 23:19:59.308380 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6516 23:19:59.308482 ==
6517 23:19:59.311622 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 23:19:59.314736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 23:19:59.314828 ==
6520 23:19:59.318363 DQS Delay:
6521 23:19:59.318456 DQS0 = 27, DQS1 = 43
6522 23:19:59.321458 DQM Delay:
6523 23:19:59.321545 DQM0 = 9, DQM1 = 14
6524 23:19:59.321612 DQ Delay:
6525 23:19:59.324964 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6526 23:19:59.328367 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6527 23:19:59.331460 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6528 23:19:59.334728 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6529 23:19:59.334821
6530 23:19:59.334889
6531 23:19:59.334950 ==
6532 23:19:59.338156 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 23:19:59.344465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 23:19:59.344589 ==
6535 23:19:59.344728
6536 23:19:59.344795
6537 23:19:59.344856 TX Vref Scan disable
6538 23:19:59.348065 == TX Byte 0 ==
6539 23:19:59.351465 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6540 23:19:59.355008 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6541 23:19:59.358308 == TX Byte 1 ==
6542 23:19:59.361180 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6543 23:19:59.364575 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6544 23:19:59.364731 ==
6545 23:19:59.367983 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 23:19:59.374619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 23:19:59.374724 ==
6548 23:19:59.374795
6549 23:19:59.374858
6550 23:19:59.374918 TX Vref Scan disable
6551 23:19:59.377563 == TX Byte 0 ==
6552 23:19:59.381288 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6553 23:19:59.384419 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6554 23:19:59.387716 == TX Byte 1 ==
6555 23:19:59.391049 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6556 23:19:59.394510 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6557 23:19:59.394604
6558 23:19:59.397612 [DATLAT]
6559 23:19:59.397698 Freq=400, CH0 RK1
6560 23:19:59.397766
6561 23:19:59.401155 DATLAT Default: 0xe
6562 23:19:59.401241 0, 0xFFFF, sum = 0
6563 23:19:59.404255 1, 0xFFFF, sum = 0
6564 23:19:59.404344 2, 0xFFFF, sum = 0
6565 23:19:59.407601 3, 0xFFFF, sum = 0
6566 23:19:59.407690 4, 0xFFFF, sum = 0
6567 23:19:59.410791 5, 0xFFFF, sum = 0
6568 23:19:59.410880 6, 0xFFFF, sum = 0
6569 23:19:59.414262 7, 0xFFFF, sum = 0
6570 23:19:59.414348 8, 0xFFFF, sum = 0
6571 23:19:59.417704 9, 0xFFFF, sum = 0
6572 23:19:59.417856 10, 0xFFFF, sum = 0
6573 23:19:59.421080 11, 0xFFFF, sum = 0
6574 23:19:59.424355 12, 0xFFFF, sum = 0
6575 23:19:59.424471 13, 0x0, sum = 1
6576 23:19:59.424572 14, 0x0, sum = 2
6577 23:19:59.427817 15, 0x0, sum = 3
6578 23:19:59.427931 16, 0x0, sum = 4
6579 23:19:59.430657 best_step = 14
6580 23:19:59.430768
6581 23:19:59.430865 ==
6582 23:19:59.434122 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 23:19:59.438011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 23:19:59.438129 ==
6585 23:19:59.440885 RX Vref Scan: 0
6586 23:19:59.440996
6587 23:19:59.441093 RX Vref 0 -> 0, step: 1
6588 23:19:59.441187
6589 23:19:59.444398 RX Delay -327 -> 252, step: 8
6590 23:19:59.452778 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6591 23:19:59.455810 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6592 23:19:59.458778 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6593 23:19:59.462672 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6594 23:19:59.469336 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6595 23:19:59.472455 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6596 23:19:59.475528 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6597 23:19:59.478839 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6598 23:19:59.485785 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6599 23:19:59.489090 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6600 23:19:59.492115 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6601 23:19:59.495712 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6602 23:19:59.502349 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6603 23:19:59.505668 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6604 23:19:59.509004 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6605 23:19:59.515659 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6606 23:19:59.515794 ==
6607 23:19:59.518701 Dram Type= 6, Freq= 0, CH_0, rank 1
6608 23:19:59.522462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 23:19:59.522584 ==
6610 23:19:59.522683 DQS Delay:
6611 23:19:59.525762 DQS0 = 28, DQS1 = 40
6612 23:19:59.525874 DQM Delay:
6613 23:19:59.528583 DQM0 = 11, DQM1 = 12
6614 23:19:59.528731 DQ Delay:
6615 23:19:59.532238 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6616 23:19:59.535360 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6617 23:19:59.538641 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6618 23:19:59.542013 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6619 23:19:59.542130
6620 23:19:59.542227
6621 23:19:59.548576 [DQSOSCAuto] RK1, (LSB)MR18= 0xb368, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6622 23:19:59.551722 CH0 RK1: MR19=C0C, MR18=B368
6623 23:19:59.558492 CH0_RK1: MR19=0xC0C, MR18=0xB368, DQSOSC=387, MR23=63, INC=394, DEC=262
6624 23:19:59.561721 [RxdqsGatingPostProcess] freq 400
6625 23:19:59.568114 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6626 23:19:59.571507 best DQS0 dly(2T, 0.5T) = (0, 10)
6627 23:19:59.571631 best DQS1 dly(2T, 0.5T) = (0, 10)
6628 23:19:59.574889 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6629 23:19:59.578557 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6630 23:19:59.581418 best DQS0 dly(2T, 0.5T) = (0, 10)
6631 23:19:59.584834 best DQS1 dly(2T, 0.5T) = (0, 10)
6632 23:19:59.588321 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6633 23:19:59.591696 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6634 23:19:59.595080 Pre-setting of DQS Precalculation
6635 23:19:59.601552 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6636 23:19:59.601691 ==
6637 23:19:59.604907 Dram Type= 6, Freq= 0, CH_1, rank 0
6638 23:19:59.607851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 23:19:59.607965 ==
6640 23:19:59.614906 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6641 23:19:59.618376 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6642 23:19:59.621817 [CA 0] Center 36 (8~64) winsize 57
6643 23:19:59.625118 [CA 1] Center 36 (8~64) winsize 57
6644 23:19:59.628479 [CA 2] Center 36 (8~64) winsize 57
6645 23:19:59.631372 [CA 3] Center 36 (8~64) winsize 57
6646 23:19:59.634589 [CA 4] Center 36 (8~64) winsize 57
6647 23:19:59.638462 [CA 5] Center 36 (8~64) winsize 57
6648 23:19:59.638578
6649 23:19:59.641162 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6650 23:19:59.641273
6651 23:19:59.644874 [CATrainingPosCal] consider 1 rank data
6652 23:19:59.647826 u2DelayCellTimex100 = 270/100 ps
6653 23:19:59.651206 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 23:19:59.654690 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 23:19:59.657991 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 23:19:59.664545 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 23:19:59.668058 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 23:19:59.671230 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 23:19:59.671347
6660 23:19:59.674612 CA PerBit enable=1, Macro0, CA PI delay=36
6661 23:19:59.674722
6662 23:19:59.678008 [CBTSetCACLKResult] CA Dly = 36
6663 23:19:59.678122 CS Dly: 1 (0~32)
6664 23:19:59.678248 ==
6665 23:19:59.680997 Dram Type= 6, Freq= 0, CH_1, rank 1
6666 23:19:59.687666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 23:19:59.687832 ==
6668 23:19:59.691056 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6669 23:19:59.697840 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6670 23:19:59.701373 [CA 0] Center 36 (8~64) winsize 57
6671 23:19:59.704768 [CA 1] Center 36 (8~64) winsize 57
6672 23:19:59.707500 [CA 2] Center 36 (8~64) winsize 57
6673 23:19:59.711291 [CA 3] Center 36 (8~64) winsize 57
6674 23:19:59.714360 [CA 4] Center 36 (8~64) winsize 57
6675 23:19:59.717565 [CA 5] Center 36 (8~64) winsize 57
6676 23:19:59.717684
6677 23:19:59.720858 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6678 23:19:59.720979
6679 23:19:59.724387 [CATrainingPosCal] consider 2 rank data
6680 23:19:59.727619 u2DelayCellTimex100 = 270/100 ps
6681 23:19:59.730749 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 23:19:59.734167 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 23:19:59.737570 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 23:19:59.740840 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 23:19:59.744346 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 23:19:59.747694 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 23:19:59.750944
6688 23:19:59.754206 CA PerBit enable=1, Macro0, CA PI delay=36
6689 23:19:59.754322
6690 23:19:59.757739 [CBTSetCACLKResult] CA Dly = 36
6691 23:19:59.757851 CS Dly: 1 (0~32)
6692 23:19:59.757948
6693 23:19:59.760687 ----->DramcWriteLeveling(PI) begin...
6694 23:19:59.760799 ==
6695 23:19:59.763990 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 23:19:59.767521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 23:19:59.770964 ==
6698 23:19:59.771078 Write leveling (Byte 0): 40 => 8
6699 23:19:59.774261 Write leveling (Byte 1): 40 => 8
6700 23:19:59.777309 DramcWriteLeveling(PI) end<-----
6701 23:19:59.777421
6702 23:19:59.777518 ==
6703 23:19:59.780565 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 23:19:59.784220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 23:19:59.787582 ==
6706 23:19:59.787696 [Gating] SW mode calibration
6707 23:19:59.797548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6708 23:19:59.800566 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6709 23:19:59.804149 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6710 23:19:59.810971 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6711 23:19:59.813992 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 23:19:59.817254 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6713 23:19:59.823968 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 23:19:59.827317 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 23:19:59.830936 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 23:19:59.837047 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 23:19:59.840435 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6718 23:19:59.844271 Total UI for P1: 0, mck2ui 16
6719 23:19:59.847188 best dqsien dly found for B0: ( 0, 14, 24)
6720 23:19:59.850537 Total UI for P1: 0, mck2ui 16
6721 23:19:59.854070 best dqsien dly found for B1: ( 0, 14, 24)
6722 23:19:59.857438 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6723 23:19:59.860812 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6724 23:19:59.860929
6725 23:19:59.864223 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6726 23:19:59.867179 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6727 23:19:59.870766 [Gating] SW calibration Done
6728 23:19:59.870884 ==
6729 23:19:59.874172 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 23:19:59.877180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 23:19:59.880862 ==
6732 23:19:59.880981 RX Vref Scan: 0
6733 23:19:59.881078
6734 23:19:59.884234 RX Vref 0 -> 0, step: 1
6735 23:19:59.884343
6736 23:19:59.887138 RX Delay -410 -> 252, step: 16
6737 23:19:59.890770 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6738 23:19:59.893740 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6739 23:19:59.897374 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6740 23:19:59.903923 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6741 23:19:59.906907 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6742 23:19:59.910586 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6743 23:19:59.913670 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6744 23:19:59.920147 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6745 23:19:59.923803 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6746 23:19:59.927132 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6747 23:19:59.930095 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6748 23:19:59.936602 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6749 23:19:59.940233 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6750 23:19:59.943527 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6751 23:19:59.950254 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6752 23:19:59.953567 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6753 23:19:59.953696 ==
6754 23:19:59.956605 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 23:19:59.960010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 23:19:59.960128 ==
6757 23:19:59.963290 DQS Delay:
6758 23:19:59.963404 DQS0 = 27, DQS1 = 43
6759 23:19:59.963503 DQM Delay:
6760 23:19:59.966617 DQM0 = 8, DQM1 = 19
6761 23:19:59.966727 DQ Delay:
6762 23:19:59.970245 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6763 23:19:59.973620 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6764 23:19:59.976847 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6765 23:19:59.979830 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6766 23:19:59.979944
6767 23:19:59.980040
6768 23:19:59.980133 ==
6769 23:19:59.983147 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 23:19:59.986374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 23:19:59.986489 ==
6772 23:19:59.989684
6773 23:19:59.989796
6774 23:19:59.989892 TX Vref Scan disable
6775 23:19:59.993184 == TX Byte 0 ==
6776 23:19:59.996505 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6777 23:19:59.999906 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6778 23:20:00.003023 == TX Byte 1 ==
6779 23:20:00.006528 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6780 23:20:00.009728 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6781 23:20:00.009847 ==
6782 23:20:00.013174 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 23:20:00.016539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 23:20:00.019745 ==
6785 23:20:00.019869
6786 23:20:00.019967
6787 23:20:00.020062 TX Vref Scan disable
6788 23:20:00.023119 == TX Byte 0 ==
6789 23:20:00.026344 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 23:20:00.029967 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 23:20:00.033110 == TX Byte 1 ==
6792 23:20:00.036371 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 23:20:00.039929 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 23:20:00.040049
6795 23:20:00.040147 [DATLAT]
6796 23:20:00.042944 Freq=400, CH1 RK0
6797 23:20:00.043058
6798 23:20:00.046406 DATLAT Default: 0xf
6799 23:20:00.046520 0, 0xFFFF, sum = 0
6800 23:20:00.049712 1, 0xFFFF, sum = 0
6801 23:20:00.049826 2, 0xFFFF, sum = 0
6802 23:20:00.053365 3, 0xFFFF, sum = 0
6803 23:20:00.053480 4, 0xFFFF, sum = 0
6804 23:20:00.056576 5, 0xFFFF, sum = 0
6805 23:20:00.056727 6, 0xFFFF, sum = 0
6806 23:20:00.059679 7, 0xFFFF, sum = 0
6807 23:20:00.059791 8, 0xFFFF, sum = 0
6808 23:20:00.062921 9, 0xFFFF, sum = 0
6809 23:20:00.063034 10, 0xFFFF, sum = 0
6810 23:20:00.066211 11, 0xFFFF, sum = 0
6811 23:20:00.066323 12, 0xFFFF, sum = 0
6812 23:20:00.069716 13, 0x0, sum = 1
6813 23:20:00.069829 14, 0x0, sum = 2
6814 23:20:00.072974 15, 0x0, sum = 3
6815 23:20:00.073086 16, 0x0, sum = 4
6816 23:20:00.076168 best_step = 14
6817 23:20:00.076277
6818 23:20:00.076375 ==
6819 23:20:00.079451 Dram Type= 6, Freq= 0, CH_1, rank 0
6820 23:20:00.082913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 23:20:00.083027 ==
6822 23:20:00.086205 RX Vref Scan: 1
6823 23:20:00.086315
6824 23:20:00.086413 RX Vref 0 -> 0, step: 1
6825 23:20:00.086506
6826 23:20:00.089784 RX Delay -327 -> 252, step: 8
6827 23:20:00.089895
6828 23:20:00.093388 Set Vref, RX VrefLevel [Byte0]: 52
6829 23:20:00.096180 [Byte1]: 52
6830 23:20:00.100614
6831 23:20:00.100769 Final RX Vref Byte 0 = 52 to rank0
6832 23:20:00.104163 Final RX Vref Byte 1 = 52 to rank0
6833 23:20:00.107351 Final RX Vref Byte 0 = 52 to rank1
6834 23:20:00.110692 Final RX Vref Byte 1 = 52 to rank1==
6835 23:20:00.113575 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 23:20:00.120420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 23:20:00.120575 ==
6838 23:20:00.120717 DQS Delay:
6839 23:20:00.124069 DQS0 = 32, DQS1 = 40
6840 23:20:00.124182 DQM Delay:
6841 23:20:00.124279 DQM0 = 11, DQM1 = 12
6842 23:20:00.126957 DQ Delay:
6843 23:20:00.130521 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6844 23:20:00.130638 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6845 23:20:00.133905 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6846 23:20:00.137267 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6847 23:20:00.137385
6848 23:20:00.137483
6849 23:20:00.146894 [DQSOSCAuto] RK0, (LSB)MR18= 0x99d4, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6850 23:20:00.150616 CH1 RK0: MR19=C0C, MR18=99D4
6851 23:20:00.157137 CH1_RK0: MR19=0xC0C, MR18=0x99D4, DQSOSC=383, MR23=63, INC=402, DEC=268
6852 23:20:00.157281 ==
6853 23:20:00.160133 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 23:20:00.163522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 23:20:00.163639 ==
6856 23:20:00.166757 [Gating] SW mode calibration
6857 23:20:00.173904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6858 23:20:00.177163 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6859 23:20:00.183617 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6860 23:20:00.187105 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6861 23:20:00.190342 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 23:20:00.197099 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6863 23:20:00.200402 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 23:20:00.203725 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 23:20:00.210107 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 23:20:00.213643 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 23:20:00.216885 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6868 23:20:00.220131 Total UI for P1: 0, mck2ui 16
6869 23:20:00.223360 best dqsien dly found for B0: ( 0, 14, 24)
6870 23:20:00.226962 Total UI for P1: 0, mck2ui 16
6871 23:20:00.229978 best dqsien dly found for B1: ( 0, 14, 24)
6872 23:20:00.233479 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6873 23:20:00.236938 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6874 23:20:00.237058
6875 23:20:00.243568 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6876 23:20:00.246982 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6877 23:20:00.250326 [Gating] SW calibration Done
6878 23:20:00.250450 ==
6879 23:20:00.253485 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 23:20:00.257094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 23:20:00.257216 ==
6882 23:20:00.257316 RX Vref Scan: 0
6883 23:20:00.257410
6884 23:20:00.260190 RX Vref 0 -> 0, step: 1
6885 23:20:00.260299
6886 23:20:00.263605 RX Delay -410 -> 252, step: 16
6887 23:20:00.267056 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6888 23:20:00.273527 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6889 23:20:00.276900 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6890 23:20:00.280230 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6891 23:20:00.283725 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6892 23:20:00.289967 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6893 23:20:00.293357 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6894 23:20:00.296780 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6895 23:20:00.300352 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6896 23:20:00.303522 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6897 23:20:00.310153 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6898 23:20:00.313071 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6899 23:20:00.316610 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6900 23:20:00.323192 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6901 23:20:00.326815 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6902 23:20:00.329716 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6903 23:20:00.329834 ==
6904 23:20:00.333505 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 23:20:00.336383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 23:20:00.340187 ==
6907 23:20:00.340307 DQS Delay:
6908 23:20:00.340408 DQS0 = 35, DQS1 = 35
6909 23:20:00.343396 DQM Delay:
6910 23:20:00.343508 DQM0 = 16, DQM1 = 13
6911 23:20:00.346594 DQ Delay:
6912 23:20:00.346708 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6913 23:20:00.350081 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6914 23:20:00.353035 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6915 23:20:00.356537 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6916 23:20:00.356679
6917 23:20:00.359646
6918 23:20:00.359757 ==
6919 23:20:00.363088 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 23:20:00.366188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 23:20:00.366303 ==
6922 23:20:00.366399
6923 23:20:00.366491
6924 23:20:00.369757 TX Vref Scan disable
6925 23:20:00.369868 == TX Byte 0 ==
6926 23:20:00.373075 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6927 23:20:00.379572 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6928 23:20:00.379714 == TX Byte 1 ==
6929 23:20:00.383048 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6930 23:20:00.389596 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6931 23:20:00.389741 ==
6932 23:20:00.393017 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 23:20:00.395897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 23:20:00.396013 ==
6935 23:20:00.396110
6936 23:20:00.396203
6937 23:20:00.399556 TX Vref Scan disable
6938 23:20:00.399667 == TX Byte 0 ==
6939 23:20:00.402528 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6940 23:20:00.409191 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6941 23:20:00.409321 == TX Byte 1 ==
6942 23:20:00.412608 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6943 23:20:00.419025 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6944 23:20:00.419150
6945 23:20:00.419250 [DATLAT]
6946 23:20:00.419364 Freq=400, CH1 RK1
6947 23:20:00.422338
6948 23:20:00.422448 DATLAT Default: 0xe
6949 23:20:00.425649 0, 0xFFFF, sum = 0
6950 23:20:00.425764 1, 0xFFFF, sum = 0
6951 23:20:00.428951 2, 0xFFFF, sum = 0
6952 23:20:00.429065 3, 0xFFFF, sum = 0
6953 23:20:00.432366 4, 0xFFFF, sum = 0
6954 23:20:00.432481 5, 0xFFFF, sum = 0
6955 23:20:00.435616 6, 0xFFFF, sum = 0
6956 23:20:00.435729 7, 0xFFFF, sum = 0
6957 23:20:00.438767 8, 0xFFFF, sum = 0
6958 23:20:00.438880 9, 0xFFFF, sum = 0
6959 23:20:00.442529 10, 0xFFFF, sum = 0
6960 23:20:00.442642 11, 0xFFFF, sum = 0
6961 23:20:00.445553 12, 0xFFFF, sum = 0
6962 23:20:00.445669 13, 0x0, sum = 1
6963 23:20:00.448890 14, 0x0, sum = 2
6964 23:20:00.449007 15, 0x0, sum = 3
6965 23:20:00.451947 16, 0x0, sum = 4
6966 23:20:00.452062 best_step = 14
6967 23:20:00.452159
6968 23:20:00.452254 ==
6969 23:20:00.455564 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 23:20:00.462116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 23:20:00.462258 ==
6972 23:20:00.462357 RX Vref Scan: 0
6973 23:20:00.462451
6974 23:20:00.465298 RX Vref 0 -> 0, step: 1
6975 23:20:00.465410
6976 23:20:00.468650 RX Delay -311 -> 252, step: 8
6977 23:20:00.475157 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6978 23:20:00.478369 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6979 23:20:00.481927 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6980 23:20:00.484804 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6981 23:20:00.491714 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6982 23:20:00.494728 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6983 23:20:00.498109 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6984 23:20:00.501529 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6985 23:20:00.508393 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6986 23:20:00.511807 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6987 23:20:00.514775 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6988 23:20:00.518111 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6989 23:20:00.524521 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6990 23:20:00.528058 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6991 23:20:00.531339 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6992 23:20:00.538273 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6993 23:20:00.538418 ==
6994 23:20:00.541371 Dram Type= 6, Freq= 0, CH_1, rank 1
6995 23:20:00.544896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6996 23:20:00.545017 ==
6997 23:20:00.545116 DQS Delay:
6998 23:20:00.548307 DQS0 = 32, DQS1 = 36
6999 23:20:00.548418 DQM Delay:
7000 23:20:00.551152 DQM0 = 13, DQM1 = 11
7001 23:20:00.551265 DQ Delay:
7002 23:20:00.554627 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =16
7003 23:20:00.557927 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
7004 23:20:00.561150 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7005 23:20:00.564530 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7006 23:20:00.564675
7007 23:20:00.564788
7008 23:20:00.571302 [DQSOSCAuto] RK1, (LSB)MR18= 0xa750, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
7009 23:20:00.574653 CH1 RK1: MR19=C0C, MR18=A750
7010 23:20:00.581116 CH1_RK1: MR19=0xC0C, MR18=0xA750, DQSOSC=389, MR23=63, INC=390, DEC=260
7011 23:20:00.584414 [RxdqsGatingPostProcess] freq 400
7012 23:20:00.591139 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7013 23:20:00.594529 best DQS0 dly(2T, 0.5T) = (0, 10)
7014 23:20:00.594657 best DQS1 dly(2T, 0.5T) = (0, 10)
7015 23:20:00.597641 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7016 23:20:00.600940 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7017 23:20:00.604403 best DQS0 dly(2T, 0.5T) = (0, 10)
7018 23:20:00.607774 best DQS1 dly(2T, 0.5T) = (0, 10)
7019 23:20:00.611190 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7020 23:20:00.614423 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7021 23:20:00.617936 Pre-setting of DQS Precalculation
7022 23:20:00.624106 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7023 23:20:00.630837 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7024 23:20:00.637477 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7025 23:20:00.637630
7026 23:20:00.637737
7027 23:20:00.640842 [Calibration Summary] 800 Mbps
7028 23:20:00.640955 CH 0, Rank 0
7029 23:20:00.644114 SW Impedance : PASS
7030 23:20:00.647421 DUTY Scan : NO K
7031 23:20:00.647538 ZQ Calibration : PASS
7032 23:20:00.650812 Jitter Meter : NO K
7033 23:20:00.650926 CBT Training : PASS
7034 23:20:00.654129 Write leveling : PASS
7035 23:20:00.657310 RX DQS gating : PASS
7036 23:20:00.657437 RX DQ/DQS(RDDQC) : PASS
7037 23:20:00.660638 TX DQ/DQS : PASS
7038 23:20:00.663953 RX DATLAT : PASS
7039 23:20:00.664067 RX DQ/DQS(Engine): PASS
7040 23:20:00.667532 TX OE : NO K
7041 23:20:00.667646 All Pass.
7042 23:20:00.667745
7043 23:20:00.670809 CH 0, Rank 1
7044 23:20:00.670921 SW Impedance : PASS
7045 23:20:00.674345 DUTY Scan : NO K
7046 23:20:00.677210 ZQ Calibration : PASS
7047 23:20:00.677322 Jitter Meter : NO K
7048 23:20:00.680499 CBT Training : PASS
7049 23:20:00.684037 Write leveling : NO K
7050 23:20:00.684152 RX DQS gating : PASS
7051 23:20:00.687656 RX DQ/DQS(RDDQC) : PASS
7052 23:20:00.690803 TX DQ/DQS : PASS
7053 23:20:00.690918 RX DATLAT : PASS
7054 23:20:00.694332 RX DQ/DQS(Engine): PASS
7055 23:20:00.694443 TX OE : NO K
7056 23:20:00.697274 All Pass.
7057 23:20:00.697385
7058 23:20:00.697482 CH 1, Rank 0
7059 23:20:00.700498 SW Impedance : PASS
7060 23:20:00.700606 DUTY Scan : NO K
7061 23:20:00.704201 ZQ Calibration : PASS
7062 23:20:00.707684 Jitter Meter : NO K
7063 23:20:00.707801 CBT Training : PASS
7064 23:20:00.710683 Write leveling : PASS
7065 23:20:00.713844 RX DQS gating : PASS
7066 23:20:00.713956 RX DQ/DQS(RDDQC) : PASS
7067 23:20:00.717170 TX DQ/DQS : PASS
7068 23:20:00.720523 RX DATLAT : PASS
7069 23:20:00.720656 RX DQ/DQS(Engine): PASS
7070 23:20:00.724128 TX OE : NO K
7071 23:20:00.724241 All Pass.
7072 23:20:00.724339
7073 23:20:00.727428 CH 1, Rank 1
7074 23:20:00.727538 SW Impedance : PASS
7075 23:20:00.730337 DUTY Scan : NO K
7076 23:20:00.733855 ZQ Calibration : PASS
7077 23:20:00.733968 Jitter Meter : NO K
7078 23:20:00.737288 CBT Training : PASS
7079 23:20:00.740714 Write leveling : NO K
7080 23:20:00.740827 RX DQS gating : PASS
7081 23:20:00.743767 RX DQ/DQS(RDDQC) : PASS
7082 23:20:00.746883 TX DQ/DQS : PASS
7083 23:20:00.747009 RX DATLAT : PASS
7084 23:20:00.750332 RX DQ/DQS(Engine): PASS
7085 23:20:00.750445 TX OE : NO K
7086 23:20:00.753574 All Pass.
7087 23:20:00.753685
7088 23:20:00.753782 DramC Write-DBI off
7089 23:20:00.757003 PER_BANK_REFRESH: Hybrid Mode
7090 23:20:00.760255 TX_TRACKING: ON
7091 23:20:00.766895 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7092 23:20:00.770197 [FAST_K] Save calibration result to emmc
7093 23:20:00.777153 dramc_set_vcore_voltage set vcore to 725000
7094 23:20:00.777300 Read voltage for 1600, 0
7095 23:20:00.780208 Vio18 = 0
7096 23:20:00.780323 Vcore = 725000
7097 23:20:00.780420 Vdram = 0
7098 23:20:00.780520 Vddq = 0
7099 23:20:00.783655 Vmddr = 0
7100 23:20:00.786966 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7101 23:20:00.793614 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7102 23:20:00.793759 MEM_TYPE=3, freq_sel=13
7103 23:20:00.797215 sv_algorithm_assistance_LP4_3733
7104 23:20:00.803452 ============ PULL DRAM RESETB DOWN ============
7105 23:20:00.807123 ========== PULL DRAM RESETB DOWN end =========
7106 23:20:00.810055 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7107 23:20:00.813479 ===================================
7108 23:20:00.816813 LPDDR4 DRAM CONFIGURATION
7109 23:20:00.820061 ===================================
7110 23:20:00.823519 EX_ROW_EN[0] = 0x0
7111 23:20:00.823648 EX_ROW_EN[1] = 0x0
7112 23:20:00.826732 LP4Y_EN = 0x0
7113 23:20:00.826844 WORK_FSP = 0x1
7114 23:20:00.830170 WL = 0x5
7115 23:20:00.830284 RL = 0x5
7116 23:20:00.833466 BL = 0x2
7117 23:20:00.833578 RPST = 0x0
7118 23:20:00.836671 RD_PRE = 0x0
7119 23:20:00.836799 WR_PRE = 0x1
7120 23:20:00.840103 WR_PST = 0x1
7121 23:20:00.840214 DBI_WR = 0x0
7122 23:20:00.843473 DBI_RD = 0x0
7123 23:20:00.843581 OTF = 0x1
7124 23:20:00.846881 ===================================
7125 23:20:00.849901 ===================================
7126 23:20:00.853302 ANA top config
7127 23:20:00.856598 ===================================
7128 23:20:00.859911 DLL_ASYNC_EN = 0
7129 23:20:00.860027 ALL_SLAVE_EN = 0
7130 23:20:00.863385 NEW_RANK_MODE = 1
7131 23:20:00.867622 DLL_IDLE_MODE = 1
7132 23:20:00.870092 LP45_APHY_COMB_EN = 1
7133 23:20:00.870208 TX_ODT_DIS = 0
7134 23:20:00.873500 NEW_8X_MODE = 1
7135 23:20:00.876497 ===================================
7136 23:20:00.880154 ===================================
7137 23:20:00.883815 data_rate = 3200
7138 23:20:00.886531 CKR = 1
7139 23:20:00.889856 DQ_P2S_RATIO = 8
7140 23:20:00.893267 ===================================
7141 23:20:00.896924 CA_P2S_RATIO = 8
7142 23:20:00.897027 DQ_CA_OPEN = 0
7143 23:20:00.900114 DQ_SEMI_OPEN = 0
7144 23:20:00.903446 CA_SEMI_OPEN = 0
7145 23:20:00.906664 CA_FULL_RATE = 0
7146 23:20:00.909902 DQ_CKDIV4_EN = 0
7147 23:20:00.913235 CA_CKDIV4_EN = 0
7148 23:20:00.913374 CA_PREDIV_EN = 0
7149 23:20:00.916633 PH8_DLY = 12
7150 23:20:00.920021 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7151 23:20:00.923105 DQ_AAMCK_DIV = 4
7152 23:20:00.926655 CA_AAMCK_DIV = 4
7153 23:20:00.929762 CA_ADMCK_DIV = 4
7154 23:20:00.929879 DQ_TRACK_CA_EN = 0
7155 23:20:00.933410 CA_PICK = 1600
7156 23:20:00.936591 CA_MCKIO = 1600
7157 23:20:00.940158 MCKIO_SEMI = 0
7158 23:20:00.943537 PLL_FREQ = 3068
7159 23:20:00.946767 DQ_UI_PI_RATIO = 32
7160 23:20:00.950254 CA_UI_PI_RATIO = 0
7161 23:20:00.953043 ===================================
7162 23:20:00.956593 ===================================
7163 23:20:00.956706 memory_type:LPDDR4
7164 23:20:00.959673 GP_NUM : 10
7165 23:20:00.963409 SRAM_EN : 1
7166 23:20:00.963515 MD32_EN : 0
7167 23:20:00.966628 ===================================
7168 23:20:00.969987 [ANA_INIT] >>>>>>>>>>>>>>
7169 23:20:00.973402 <<<<<< [CONFIGURE PHASE]: ANA_TX
7170 23:20:00.976570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7171 23:20:00.979774 ===================================
7172 23:20:00.983141 data_rate = 3200,PCW = 0X7600
7173 23:20:00.986315 ===================================
7174 23:20:00.989731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7175 23:20:00.993223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7176 23:20:00.999881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7177 23:20:01.003100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7178 23:20:01.006661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7179 23:20:01.009785 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7180 23:20:01.013146 [ANA_INIT] flow start
7181 23:20:01.016292 [ANA_INIT] PLL >>>>>>>>
7182 23:20:01.016403 [ANA_INIT] PLL <<<<<<<<
7183 23:20:01.019888 [ANA_INIT] MIDPI >>>>>>>>
7184 23:20:01.023131 [ANA_INIT] MIDPI <<<<<<<<
7185 23:20:01.023243 [ANA_INIT] DLL >>>>>>>>
7186 23:20:01.026493 [ANA_INIT] DLL <<<<<<<<
7187 23:20:01.029845 [ANA_INIT] flow end
7188 23:20:01.033265 ============ LP4 DIFF to SE enter ============
7189 23:20:01.036190 ============ LP4 DIFF to SE exit ============
7190 23:20:01.039720 [ANA_INIT] <<<<<<<<<<<<<
7191 23:20:01.043216 [Flow] Enable top DCM control >>>>>
7192 23:20:01.046545 [Flow] Enable top DCM control <<<<<
7193 23:20:01.049611 Enable DLL master slave shuffle
7194 23:20:01.052879 ==============================================================
7195 23:20:01.056114 Gating Mode config
7196 23:20:01.062815 ==============================================================
7197 23:20:01.062953 Config description:
7198 23:20:01.072664 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7199 23:20:01.079576 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7200 23:20:01.085895 SELPH_MODE 0: By rank 1: By Phase
7201 23:20:01.089242 ==============================================================
7202 23:20:01.092621 GAT_TRACK_EN = 1
7203 23:20:01.095943 RX_GATING_MODE = 2
7204 23:20:01.099429 RX_GATING_TRACK_MODE = 2
7205 23:20:01.102715 SELPH_MODE = 1
7206 23:20:01.106129 PICG_EARLY_EN = 1
7207 23:20:01.109298 VALID_LAT_VALUE = 1
7208 23:20:01.112554 ==============================================================
7209 23:20:01.115963 Enter into Gating configuration >>>>
7210 23:20:01.119011 Exit from Gating configuration <<<<
7211 23:20:01.122646 Enter into DVFS_PRE_config >>>>>
7212 23:20:01.135792 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7213 23:20:01.139447 Exit from DVFS_PRE_config <<<<<
7214 23:20:01.139571 Enter into PICG configuration >>>>
7215 23:20:01.142609 Exit from PICG configuration <<<<
7216 23:20:01.145848 [RX_INPUT] configuration >>>>>
7217 23:20:01.149119 [RX_INPUT] configuration <<<<<
7218 23:20:01.155862 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7219 23:20:01.159337 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7220 23:20:01.166138 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7221 23:20:01.172398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7222 23:20:01.179069 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7223 23:20:01.186237 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7224 23:20:01.188987 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7225 23:20:01.192164 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7226 23:20:01.195672 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7227 23:20:01.202432 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7228 23:20:01.205471 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7229 23:20:01.209120 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7230 23:20:01.212023 ===================================
7231 23:20:01.215654 LPDDR4 DRAM CONFIGURATION
7232 23:20:01.218756 ===================================
7233 23:20:01.222194 EX_ROW_EN[0] = 0x0
7234 23:20:01.222322 EX_ROW_EN[1] = 0x0
7235 23:20:01.225404 LP4Y_EN = 0x0
7236 23:20:01.225508 WORK_FSP = 0x1
7237 23:20:01.228886 WL = 0x5
7238 23:20:01.228994 RL = 0x5
7239 23:20:01.232053 BL = 0x2
7240 23:20:01.232130 RPST = 0x0
7241 23:20:01.235511 RD_PRE = 0x0
7242 23:20:01.235613 WR_PRE = 0x1
7243 23:20:01.238650 WR_PST = 0x1
7244 23:20:01.238726 DBI_WR = 0x0
7245 23:20:01.242186 DBI_RD = 0x0
7246 23:20:01.242287 OTF = 0x1
7247 23:20:01.245613 ===================================
7248 23:20:01.248838 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7249 23:20:01.255524 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7250 23:20:01.258550 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7251 23:20:01.261912 ===================================
7252 23:20:01.265400 LPDDR4 DRAM CONFIGURATION
7253 23:20:01.268768 ===================================
7254 23:20:01.268856 EX_ROW_EN[0] = 0x10
7255 23:20:01.272226 EX_ROW_EN[1] = 0x0
7256 23:20:01.275338 LP4Y_EN = 0x0
7257 23:20:01.275447 WORK_FSP = 0x1
7258 23:20:01.278655 WL = 0x5
7259 23:20:01.278775 RL = 0x5
7260 23:20:01.282427 BL = 0x2
7261 23:20:01.282535 RPST = 0x0
7262 23:20:01.285245 RD_PRE = 0x0
7263 23:20:01.285332 WR_PRE = 0x1
7264 23:20:01.288563 WR_PST = 0x1
7265 23:20:01.288709 DBI_WR = 0x0
7266 23:20:01.292090 DBI_RD = 0x0
7267 23:20:01.292209 OTF = 0x1
7268 23:20:01.295186 ===================================
7269 23:20:01.302051 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7270 23:20:01.302205 ==
7271 23:20:01.305154 Dram Type= 6, Freq= 0, CH_0, rank 0
7272 23:20:01.308303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7273 23:20:01.311867 ==
7274 23:20:01.311955 [Duty_Offset_Calibration]
7275 23:20:01.315159 B0:2 B1:0 CA:1
7276 23:20:01.315265
7277 23:20:01.318479 [DutyScan_Calibration_Flow] k_type=0
7278 23:20:01.326650
7279 23:20:01.326808 ==CLK 0==
7280 23:20:01.329659 Final CLK duty delay cell = -4
7281 23:20:01.333222 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7282 23:20:01.336048 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7283 23:20:01.339446 [-4] AVG Duty = 4922%(X100)
7284 23:20:01.339552
7285 23:20:01.342799 CH0 CLK Duty spec in!! Max-Min= 156%
7286 23:20:01.346118 [DutyScan_Calibration_Flow] ====Done====
7287 23:20:01.346198
7288 23:20:01.349310 [DutyScan_Calibration_Flow] k_type=1
7289 23:20:01.365690
7290 23:20:01.365841 ==DQS 0 ==
7291 23:20:01.369073 Final DQS duty delay cell = 0
7292 23:20:01.372407 [0] MAX Duty = 5249%(X100), DQS PI = 34
7293 23:20:01.375571 [0] MIN Duty = 4969%(X100), DQS PI = 0
7294 23:20:01.378806 [0] AVG Duty = 5109%(X100)
7295 23:20:01.378888
7296 23:20:01.378953 ==DQS 1 ==
7297 23:20:01.382221 Final DQS duty delay cell = -4
7298 23:20:01.385453 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7299 23:20:01.389003 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7300 23:20:01.392318 [-4] AVG Duty = 4984%(X100)
7301 23:20:01.392425
7302 23:20:01.395650 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7303 23:20:01.395753
7304 23:20:01.398726 CH0 DQS 1 Duty spec in!! Max-Min= 219%
7305 23:20:01.402121 [DutyScan_Calibration_Flow] ====Done====
7306 23:20:01.402226
7307 23:20:01.405274 [DutyScan_Calibration_Flow] k_type=3
7308 23:20:01.423474
7309 23:20:01.423666 ==DQM 0 ==
7310 23:20:01.426431 Final DQM duty delay cell = 0
7311 23:20:01.429965 [0] MAX Duty = 5124%(X100), DQS PI = 26
7312 23:20:01.433139 [0] MIN Duty = 4813%(X100), DQS PI = 52
7313 23:20:01.436434 [0] AVG Duty = 4968%(X100)
7314 23:20:01.436551
7315 23:20:01.436669 ==DQM 1 ==
7316 23:20:01.439841 Final DQM duty delay cell = 0
7317 23:20:01.443165 [0] MAX Duty = 5249%(X100), DQS PI = 30
7318 23:20:01.446528 [0] MIN Duty = 5000%(X100), DQS PI = 20
7319 23:20:01.449894 [0] AVG Duty = 5124%(X100)
7320 23:20:01.449975
7321 23:20:01.453452 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7322 23:20:01.453531
7323 23:20:01.456595 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7324 23:20:01.460240 [DutyScan_Calibration_Flow] ====Done====
7325 23:20:01.460319
7326 23:20:01.463034 [DutyScan_Calibration_Flow] k_type=2
7327 23:20:01.480182
7328 23:20:01.480362 ==DQ 0 ==
7329 23:20:01.483738 Final DQ duty delay cell = 0
7330 23:20:01.487018 [0] MAX Duty = 5124%(X100), DQS PI = 34
7331 23:20:01.490339 [0] MIN Duty = 5000%(X100), DQS PI = 0
7332 23:20:01.490431 [0] AVG Duty = 5062%(X100)
7333 23:20:01.493630
7334 23:20:01.493732 ==DQ 1 ==
7335 23:20:01.496993 Final DQ duty delay cell = 0
7336 23:20:01.500262 [0] MAX Duty = 4969%(X100), DQS PI = 28
7337 23:20:01.503349 [0] MIN Duty = 4875%(X100), DQS PI = 12
7338 23:20:01.503457 [0] AVG Duty = 4922%(X100)
7339 23:20:01.506725
7340 23:20:01.509986 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7341 23:20:01.510073
7342 23:20:01.513372 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7343 23:20:01.516705 [DutyScan_Calibration_Flow] ====Done====
7344 23:20:01.516814 ==
7345 23:20:01.520034 Dram Type= 6, Freq= 0, CH_1, rank 0
7346 23:20:01.523423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7347 23:20:01.523536 ==
7348 23:20:01.526743 [Duty_Offset_Calibration]
7349 23:20:01.526853 B0:0 B1:-1 CA:2
7350 23:20:01.526946
7351 23:20:01.530010 [DutyScan_Calibration_Flow] k_type=0
7352 23:20:01.540720
7353 23:20:01.540861 ==CLK 0==
7354 23:20:01.543774 Final CLK duty delay cell = 0
7355 23:20:01.547441 [0] MAX Duty = 5156%(X100), DQS PI = 42
7356 23:20:01.550334 [0] MIN Duty = 4906%(X100), DQS PI = 12
7357 23:20:01.550447 [0] AVG Duty = 5031%(X100)
7358 23:20:01.553534
7359 23:20:01.557102 CH1 CLK Duty spec in!! Max-Min= 250%
7360 23:20:01.560427 [DutyScan_Calibration_Flow] ====Done====
7361 23:20:01.560538
7362 23:20:01.563753 [DutyScan_Calibration_Flow] k_type=1
7363 23:20:01.580373
7364 23:20:01.580553 ==DQS 0 ==
7365 23:20:01.583471 Final DQS duty delay cell = 0
7366 23:20:01.586758 [0] MAX Duty = 5062%(X100), DQS PI = 8
7367 23:20:01.590046 [0] MIN Duty = 5000%(X100), DQS PI = 0
7368 23:20:01.590156 [0] AVG Duty = 5031%(X100)
7369 23:20:01.593874
7370 23:20:01.593980 ==DQS 1 ==
7371 23:20:01.597108 Final DQS duty delay cell = 0
7372 23:20:01.600251 [0] MAX Duty = 5187%(X100), DQS PI = 28
7373 23:20:01.603507 [0] MIN Duty = 4844%(X100), DQS PI = 0
7374 23:20:01.607088 [0] AVG Duty = 5015%(X100)
7375 23:20:01.607201
7376 23:20:01.609866 CH1 DQS 0 Duty spec in!! Max-Min= 62%
7377 23:20:01.609969
7378 23:20:01.613687 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7379 23:20:01.616416 [DutyScan_Calibration_Flow] ====Done====
7380 23:20:01.616534
7381 23:20:01.619802 [DutyScan_Calibration_Flow] k_type=3
7382 23:20:01.637830
7383 23:20:01.638014 ==DQM 0 ==
7384 23:20:01.640815 Final DQM duty delay cell = 4
7385 23:20:01.644526 [4] MAX Duty = 5156%(X100), DQS PI = 24
7386 23:20:01.647554 [4] MIN Duty = 4969%(X100), DQS PI = 2
7387 23:20:01.650995 [4] AVG Duty = 5062%(X100)
7388 23:20:01.651085
7389 23:20:01.651151 ==DQM 1 ==
7390 23:20:01.654111 Final DQM duty delay cell = 0
7391 23:20:01.657538 [0] MAX Duty = 5312%(X100), DQS PI = 26
7392 23:20:01.660836 [0] MIN Duty = 4907%(X100), DQS PI = 2
7393 23:20:01.660919 [0] AVG Duty = 5109%(X100)
7394 23:20:01.664268
7395 23:20:01.667278 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7396 23:20:01.667381
7397 23:20:01.670771 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7398 23:20:01.674083 [DutyScan_Calibration_Flow] ====Done====
7399 23:20:01.674161
7400 23:20:01.677466 [DutyScan_Calibration_Flow] k_type=2
7401 23:20:01.694627
7402 23:20:01.694729 ==DQ 0 ==
7403 23:20:01.697907 Final DQ duty delay cell = 0
7404 23:20:01.701073 [0] MAX Duty = 5093%(X100), DQS PI = 22
7405 23:20:01.704421 [0] MIN Duty = 4938%(X100), DQS PI = 0
7406 23:20:01.704530 [0] AVG Duty = 5015%(X100)
7407 23:20:01.704623
7408 23:20:01.707746 ==DQ 1 ==
7409 23:20:01.711191 Final DQ duty delay cell = 0
7410 23:20:01.714499 [0] MAX Duty = 5094%(X100), DQS PI = 34
7411 23:20:01.717698 [0] MIN Duty = 4813%(X100), DQS PI = 2
7412 23:20:01.717801 [0] AVG Duty = 4953%(X100)
7413 23:20:01.717891
7414 23:20:01.721069 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7415 23:20:01.721173
7416 23:20:01.724802 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7417 23:20:01.731316 [DutyScan_Calibration_Flow] ====Done====
7418 23:20:01.734635 nWR fixed to 30
7419 23:20:01.734718 [ModeRegInit_LP4] CH0 RK0
7420 23:20:01.737662 [ModeRegInit_LP4] CH0 RK1
7421 23:20:01.741273 [ModeRegInit_LP4] CH1 RK0
7422 23:20:01.741356 [ModeRegInit_LP4] CH1 RK1
7423 23:20:01.744484 match AC timing 5
7424 23:20:01.747948 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7425 23:20:01.751002 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7426 23:20:01.757584 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7427 23:20:01.761384 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7428 23:20:01.767671 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7429 23:20:01.767755 [MiockJmeterHQA]
7430 23:20:01.767821
7431 23:20:01.771176 [DramcMiockJmeter] u1RxGatingPI = 0
7432 23:20:01.774501 0 : 4263, 4032
7433 23:20:01.774586 4 : 4253, 4027
7434 23:20:01.774655 8 : 4253, 4026
7435 23:20:01.777937 12 : 4252, 4027
7436 23:20:01.778026 16 : 4253, 4027
7437 23:20:01.781216 20 : 4363, 4138
7438 23:20:01.781302 24 : 4253, 4026
7439 23:20:01.784169 28 : 4363, 4138
7440 23:20:01.784255 32 : 4252, 4026
7441 23:20:01.784331 36 : 4252, 4027
7442 23:20:01.787480 40 : 4253, 4027
7443 23:20:01.787565 44 : 4253, 4026
7444 23:20:01.790861 48 : 4363, 4138
7445 23:20:01.790946 52 : 4250, 4027
7446 23:20:01.794240 56 : 4363, 4137
7447 23:20:01.794325 60 : 4250, 4027
7448 23:20:01.797678 64 : 4252, 4029
7449 23:20:01.797763 68 : 4250, 4027
7450 23:20:01.797831 72 : 4250, 4026
7451 23:20:01.800841 76 : 4250, 4026
7452 23:20:01.800926 80 : 4360, 4138
7453 23:20:01.804172 84 : 4250, 4027
7454 23:20:01.804258 88 : 4250, 3542
7455 23:20:01.807578 92 : 4253, 0
7456 23:20:01.807663 96 : 4360, 0
7457 23:20:01.807731 100 : 4250, 0
7458 23:20:01.810633 104 : 4250, 0
7459 23:20:01.810718 108 : 4361, 0
7460 23:20:01.813940 112 : 4360, 0
7461 23:20:01.814024 116 : 4248, 0
7462 23:20:01.814097 120 : 4361, 0
7463 23:20:01.817361 124 : 4360, 0
7464 23:20:01.817446 128 : 4361, 0
7465 23:20:01.817514 132 : 4250, 0
7466 23:20:01.820868 136 : 4250, 0
7467 23:20:01.820980 140 : 4250, 0
7468 23:20:01.824414 144 : 4250, 0
7469 23:20:01.824527 148 : 4250, 0
7470 23:20:01.824631 152 : 4250, 0
7471 23:20:01.827840 156 : 4252, 0
7472 23:20:01.827934 160 : 4250, 0
7473 23:20:01.830733 164 : 4360, 0
7474 23:20:01.830845 168 : 4250, 0
7475 23:20:01.830943 172 : 4250, 0
7476 23:20:01.833929 176 : 4360, 0
7477 23:20:01.834014 180 : 4361, 0
7478 23:20:01.837481 184 : 4250, 0
7479 23:20:01.837566 188 : 4250, 0
7480 23:20:01.837634 192 : 4249, 0
7481 23:20:01.840873 196 : 4250, 0
7482 23:20:01.840958 200 : 4250, 7
7483 23:20:01.844028 204 : 4249, 2730
7484 23:20:01.844140 208 : 4253, 4029
7485 23:20:01.844238 212 : 4363, 4138
7486 23:20:01.847439 216 : 4250, 4027
7487 23:20:01.847551 220 : 4250, 4027
7488 23:20:01.850730 224 : 4360, 4138
7489 23:20:01.850815 228 : 4361, 4137
7490 23:20:01.854083 232 : 4248, 4024
7491 23:20:01.854195 236 : 4361, 4137
7492 23:20:01.857078 240 : 4360, 4138
7493 23:20:01.857169 244 : 4250, 4027
7494 23:20:01.860431 248 : 4250, 4026
7495 23:20:01.860545 252 : 4250, 4026
7496 23:20:01.863894 256 : 4250, 4027
7497 23:20:01.864005 260 : 4253, 4027
7498 23:20:01.867096 264 : 4250, 4026
7499 23:20:01.867175 268 : 4250, 4026
7500 23:20:01.867241 272 : 4250, 4027
7501 23:20:01.870306 276 : 4360, 4138
7502 23:20:01.870380 280 : 4360, 4138
7503 23:20:01.873663 284 : 4250, 4026
7504 23:20:01.873739 288 : 4361, 4137
7505 23:20:01.877179 292 : 4360, 4138
7506 23:20:01.877268 296 : 4250, 4027
7507 23:20:01.880526 300 : 4249, 4027
7508 23:20:01.880633 304 : 4250, 4026
7509 23:20:01.884040 308 : 4250, 4027
7510 23:20:01.884151 312 : 4250, 3841
7511 23:20:01.887349 316 : 4252, 2068
7512 23:20:01.887458
7513 23:20:01.887552 MIOCK jitter meter ch=0
7514 23:20:01.887645
7515 23:20:01.890503 1T = (316-92) = 224 dly cells
7516 23:20:01.897134 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7517 23:20:01.897248 ==
7518 23:20:01.900445 Dram Type= 6, Freq= 0, CH_0, rank 0
7519 23:20:01.904023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7520 23:20:01.904139 ==
7521 23:20:01.910675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7522 23:20:01.913672 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7523 23:20:01.916990 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7524 23:20:01.923597 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7525 23:20:01.933354 [CA 0] Center 42 (12~73) winsize 62
7526 23:20:01.936806 [CA 1] Center 42 (12~72) winsize 61
7527 23:20:01.939961 [CA 2] Center 37 (7~67) winsize 61
7528 23:20:01.943446 [CA 3] Center 37 (7~67) winsize 61
7529 23:20:01.946632 [CA 4] Center 36 (6~66) winsize 61
7530 23:20:01.949796 [CA 5] Center 35 (5~65) winsize 61
7531 23:20:01.949901
7532 23:20:01.953142 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7533 23:20:01.953249
7534 23:20:01.956330 [CATrainingPosCal] consider 1 rank data
7535 23:20:01.959710 u2DelayCellTimex100 = 290/100 ps
7536 23:20:01.962836 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7537 23:20:01.969712 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7538 23:20:01.973313 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7539 23:20:01.976278 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7540 23:20:01.979776 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7541 23:20:01.982789 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7542 23:20:01.982905
7543 23:20:01.986099 CA PerBit enable=1, Macro0, CA PI delay=35
7544 23:20:01.986204
7545 23:20:01.989570 [CBTSetCACLKResult] CA Dly = 35
7546 23:20:01.992788 CS Dly: 9 (0~40)
7547 23:20:01.996134 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7548 23:20:01.999401 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7549 23:20:01.999516 ==
7550 23:20:02.003035 Dram Type= 6, Freq= 0, CH_0, rank 1
7551 23:20:02.006176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 23:20:02.009375 ==
7553 23:20:02.013027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7554 23:20:02.016073 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7555 23:20:02.022786 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7556 23:20:02.026047 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7557 23:20:02.036485 [CA 0] Center 43 (13~74) winsize 62
7558 23:20:02.039904 [CA 1] Center 43 (13~73) winsize 61
7559 23:20:02.043220 [CA 2] Center 38 (9~68) winsize 60
7560 23:20:02.046596 [CA 3] Center 38 (9~68) winsize 60
7561 23:20:02.050046 [CA 4] Center 37 (7~67) winsize 61
7562 23:20:02.053494 [CA 5] Center 36 (6~66) winsize 61
7563 23:20:02.053577
7564 23:20:02.056265 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7565 23:20:02.056348
7566 23:20:02.059603 [CATrainingPosCal] consider 2 rank data
7567 23:20:02.063054 u2DelayCellTimex100 = 290/100 ps
7568 23:20:02.066087 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7569 23:20:02.073065 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7570 23:20:02.076323 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7571 23:20:02.079668 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7572 23:20:02.082873 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7573 23:20:02.086287 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7574 23:20:02.086371
7575 23:20:02.089783 CA PerBit enable=1, Macro0, CA PI delay=35
7576 23:20:02.089866
7577 23:20:02.093121 [CBTSetCACLKResult] CA Dly = 35
7578 23:20:02.096501 CS Dly: 10 (0~43)
7579 23:20:02.099718 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7580 23:20:02.103117 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7581 23:20:02.103200
7582 23:20:02.106167 ----->DramcWriteLeveling(PI) begin...
7583 23:20:02.106251 ==
7584 23:20:02.109397 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 23:20:02.116536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 23:20:02.116651 ==
7587 23:20:02.119440 Write leveling (Byte 0): 39 => 39
7588 23:20:02.119523 Write leveling (Byte 1): 31 => 31
7589 23:20:02.122667 DramcWriteLeveling(PI) end<-----
7590 23:20:02.122780
7591 23:20:02.122909 ==
7592 23:20:02.126005 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 23:20:02.132886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 23:20:02.132971 ==
7595 23:20:02.136291 [Gating] SW mode calibration
7596 23:20:02.142702 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7597 23:20:02.146211 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7598 23:20:02.152541 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 23:20:02.155917 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 23:20:02.159471 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
7601 23:20:02.165913 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7602 23:20:02.169441 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7603 23:20:02.172947 1 4 20 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
7604 23:20:02.179437 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 23:20:02.182771 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 23:20:02.185838 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 23:20:02.189070 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 23:20:02.196251 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
7609 23:20:02.199258 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7610 23:20:02.202681 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7611 23:20:02.209156 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7612 23:20:02.212736 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 23:20:02.216067 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 23:20:02.222640 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 23:20:02.225810 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7616 23:20:02.229318 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7617 23:20:02.235596 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7618 23:20:02.239368 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7619 23:20:02.242708 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7620 23:20:02.249364 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 23:20:02.252732 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 23:20:02.256000 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 23:20:02.262373 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 23:20:02.265916 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7625 23:20:02.269642 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7626 23:20:02.275745 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7627 23:20:02.279220 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7628 23:20:02.282950 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 23:20:02.289306 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 23:20:02.292931 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 23:20:02.295689 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 23:20:02.299414 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 23:20:02.305584 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 23:20:02.309179 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 23:20:02.312379 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 23:20:02.319031 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 23:20:02.322381 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 23:20:02.325921 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 23:20:02.332626 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 23:20:02.335614 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 23:20:02.339072 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7642 23:20:02.345645 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7643 23:20:02.349294 Total UI for P1: 0, mck2ui 16
7644 23:20:02.352418 best dqsien dly found for B0: ( 1, 9, 12)
7645 23:20:02.355467 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7646 23:20:02.359158 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 23:20:02.362445 Total UI for P1: 0, mck2ui 16
7648 23:20:02.365708 best dqsien dly found for B1: ( 1, 9, 18)
7649 23:20:02.368930 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7650 23:20:02.372028 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7651 23:20:02.372112
7652 23:20:02.378928 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7653 23:20:02.382424 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7654 23:20:02.385375 [Gating] SW calibration Done
7655 23:20:02.385459 ==
7656 23:20:02.389232 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 23:20:02.391870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 23:20:02.391958 ==
7659 23:20:02.392056 RX Vref Scan: 0
7660 23:20:02.392147
7661 23:20:02.395707 RX Vref 0 -> 0, step: 1
7662 23:20:02.395791
7663 23:20:02.398591 RX Delay 0 -> 252, step: 8
7664 23:20:02.402367 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7665 23:20:02.405669 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7666 23:20:02.409002 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7667 23:20:02.415554 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7668 23:20:02.418831 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7669 23:20:02.422035 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7670 23:20:02.425685 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7671 23:20:02.428718 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7672 23:20:02.435475 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7673 23:20:02.438901 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7674 23:20:02.442183 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7675 23:20:02.445500 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7676 23:20:02.448606 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7677 23:20:02.455649 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7678 23:20:02.458515 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7679 23:20:02.461992 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7680 23:20:02.462078 ==
7681 23:20:02.465320 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 23:20:02.468794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 23:20:02.468899 ==
7684 23:20:02.471862 DQS Delay:
7685 23:20:02.471946 DQS0 = 0, DQS1 = 0
7686 23:20:02.475461 DQM Delay:
7687 23:20:02.475576 DQM0 = 137, DQM1 = 127
7688 23:20:02.475673 DQ Delay:
7689 23:20:02.481952 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7690 23:20:02.485492 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7691 23:20:02.488388 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7692 23:20:02.491665 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7693 23:20:02.491752
7694 23:20:02.491818
7695 23:20:02.491879 ==
7696 23:20:02.495042 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 23:20:02.498702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 23:20:02.498792 ==
7699 23:20:02.498858
7700 23:20:02.498917
7701 23:20:02.501950 TX Vref Scan disable
7702 23:20:02.505282 == TX Byte 0 ==
7703 23:20:02.508465 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7704 23:20:02.512028 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7705 23:20:02.515322 == TX Byte 1 ==
7706 23:20:02.518689 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7707 23:20:02.521527 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7708 23:20:02.521610 ==
7709 23:20:02.525024 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 23:20:02.528591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 23:20:02.531542 ==
7712 23:20:02.543560
7713 23:20:02.546734 TX Vref early break, caculate TX vref
7714 23:20:02.550085 TX Vref=16, minBit 4, minWin=22, winSum=374
7715 23:20:02.553314 TX Vref=18, minBit 8, minWin=23, winSum=387
7716 23:20:02.556827 TX Vref=20, minBit 4, minWin=24, winSum=397
7717 23:20:02.560008 TX Vref=22, minBit 4, minWin=24, winSum=405
7718 23:20:02.563306 TX Vref=24, minBit 4, minWin=24, winSum=416
7719 23:20:02.569885 TX Vref=26, minBit 2, minWin=25, winSum=424
7720 23:20:02.573312 TX Vref=28, minBit 2, minWin=25, winSum=427
7721 23:20:02.576553 TX Vref=30, minBit 0, minWin=26, winSum=423
7722 23:20:02.580009 TX Vref=32, minBit 2, minWin=25, winSum=416
7723 23:20:02.583612 TX Vref=34, minBit 3, minWin=24, winSum=403
7724 23:20:02.589982 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
7725 23:20:02.590111
7726 23:20:02.593236 Final TX Range 0 Vref 30
7727 23:20:02.593329
7728 23:20:02.593398 ==
7729 23:20:02.596605 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 23:20:02.600291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 23:20:02.600395 ==
7732 23:20:02.600467
7733 23:20:02.600529
7734 23:20:02.603253 TX Vref Scan disable
7735 23:20:02.609996 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7736 23:20:02.610128 == TX Byte 0 ==
7737 23:20:02.613264 u2DelayCellOfst[0]=10 cells (3 PI)
7738 23:20:02.616524 u2DelayCellOfst[1]=16 cells (5 PI)
7739 23:20:02.619731 u2DelayCellOfst[2]=10 cells (3 PI)
7740 23:20:02.623063 u2DelayCellOfst[3]=10 cells (3 PI)
7741 23:20:02.626594 u2DelayCellOfst[4]=3 cells (1 PI)
7742 23:20:02.629761 u2DelayCellOfst[5]=0 cells (0 PI)
7743 23:20:02.633115 u2DelayCellOfst[6]=16 cells (5 PI)
7744 23:20:02.636366 u2DelayCellOfst[7]=13 cells (4 PI)
7745 23:20:02.639678 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7746 23:20:02.643089 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7747 23:20:02.646486 == TX Byte 1 ==
7748 23:20:02.646570 u2DelayCellOfst[8]=0 cells (0 PI)
7749 23:20:02.649985 u2DelayCellOfst[9]=0 cells (0 PI)
7750 23:20:02.653215 u2DelayCellOfst[10]=6 cells (2 PI)
7751 23:20:02.656365 u2DelayCellOfst[11]=3 cells (1 PI)
7752 23:20:02.659833 u2DelayCellOfst[12]=13 cells (4 PI)
7753 23:20:02.663106 u2DelayCellOfst[13]=10 cells (3 PI)
7754 23:20:02.666149 u2DelayCellOfst[14]=16 cells (5 PI)
7755 23:20:02.669402 u2DelayCellOfst[15]=13 cells (4 PI)
7756 23:20:02.673044 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7757 23:20:02.679767 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7758 23:20:02.679858 DramC Write-DBI on
7759 23:20:02.679927 ==
7760 23:20:02.682800 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 23:20:02.686218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 23:20:02.689832 ==
7763 23:20:02.689916
7764 23:20:02.689981
7765 23:20:02.690041 TX Vref Scan disable
7766 23:20:02.693072 == TX Byte 0 ==
7767 23:20:02.696558 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7768 23:20:02.699584 == TX Byte 1 ==
7769 23:20:02.703153 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7770 23:20:02.706407 DramC Write-DBI off
7771 23:20:02.706510
7772 23:20:02.706578 [DATLAT]
7773 23:20:02.706641 Freq=1600, CH0 RK0
7774 23:20:02.706701
7775 23:20:02.709465 DATLAT Default: 0xf
7776 23:20:02.712750 0, 0xFFFF, sum = 0
7777 23:20:02.712838 1, 0xFFFF, sum = 0
7778 23:20:02.716407 2, 0xFFFF, sum = 0
7779 23:20:02.716491 3, 0xFFFF, sum = 0
7780 23:20:02.719757 4, 0xFFFF, sum = 0
7781 23:20:02.719852 5, 0xFFFF, sum = 0
7782 23:20:02.723060 6, 0xFFFF, sum = 0
7783 23:20:02.723144 7, 0xFFFF, sum = 0
7784 23:20:02.726167 8, 0xFFFF, sum = 0
7785 23:20:02.726253 9, 0xFFFF, sum = 0
7786 23:20:02.729372 10, 0xFFFF, sum = 0
7787 23:20:02.729456 11, 0xFFFF, sum = 0
7788 23:20:02.733085 12, 0xFFFF, sum = 0
7789 23:20:02.733170 13, 0xFFFF, sum = 0
7790 23:20:02.736356 14, 0x0, sum = 1
7791 23:20:02.736468 15, 0x0, sum = 2
7792 23:20:02.739610 16, 0x0, sum = 3
7793 23:20:02.739694 17, 0x0, sum = 4
7794 23:20:02.742847 best_step = 15
7795 23:20:02.742930
7796 23:20:02.743006 ==
7797 23:20:02.746226 Dram Type= 6, Freq= 0, CH_0, rank 0
7798 23:20:02.749255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7799 23:20:02.749345 ==
7800 23:20:02.752615 RX Vref Scan: 1
7801 23:20:02.752714
7802 23:20:02.752781 Set Vref Range= 24 -> 127
7803 23:20:02.752842
7804 23:20:02.756074 RX Vref 24 -> 127, step: 1
7805 23:20:02.756156
7806 23:20:02.759627 RX Delay 19 -> 252, step: 4
7807 23:20:02.759725
7808 23:20:02.762991 Set Vref, RX VrefLevel [Byte0]: 24
7809 23:20:02.766285 [Byte1]: 24
7810 23:20:02.766370
7811 23:20:02.769595 Set Vref, RX VrefLevel [Byte0]: 25
7812 23:20:02.773169 [Byte1]: 25
7813 23:20:02.773252
7814 23:20:02.776217 Set Vref, RX VrefLevel [Byte0]: 26
7815 23:20:02.779645 [Byte1]: 26
7816 23:20:02.783241
7817 23:20:02.783325 Set Vref, RX VrefLevel [Byte0]: 27
7818 23:20:02.786810 [Byte1]: 27
7819 23:20:02.791043
7820 23:20:02.791126 Set Vref, RX VrefLevel [Byte0]: 28
7821 23:20:02.794467 [Byte1]: 28
7822 23:20:02.798289
7823 23:20:02.798372 Set Vref, RX VrefLevel [Byte0]: 29
7824 23:20:02.801958 [Byte1]: 29
7825 23:20:02.806247
7826 23:20:02.806336 Set Vref, RX VrefLevel [Byte0]: 30
7827 23:20:02.809238 [Byte1]: 30
7828 23:20:02.813645
7829 23:20:02.813758 Set Vref, RX VrefLevel [Byte0]: 31
7830 23:20:02.817119 [Byte1]: 31
7831 23:20:02.821032
7832 23:20:02.821116 Set Vref, RX VrefLevel [Byte0]: 32
7833 23:20:02.824454 [Byte1]: 32
7834 23:20:02.828859
7835 23:20:02.828945 Set Vref, RX VrefLevel [Byte0]: 33
7836 23:20:02.832096 [Byte1]: 33
7837 23:20:02.836163
7838 23:20:02.836245 Set Vref, RX VrefLevel [Byte0]: 34
7839 23:20:02.839479 [Byte1]: 34
7840 23:20:02.843663
7841 23:20:02.843747 Set Vref, RX VrefLevel [Byte0]: 35
7842 23:20:02.847185 [Byte1]: 35
7843 23:20:02.851221
7844 23:20:02.851306 Set Vref, RX VrefLevel [Byte0]: 36
7845 23:20:02.854706 [Byte1]: 36
7846 23:20:02.859051
7847 23:20:02.859136 Set Vref, RX VrefLevel [Byte0]: 37
7848 23:20:02.862422 [Byte1]: 37
7849 23:20:02.866481
7850 23:20:02.866589 Set Vref, RX VrefLevel [Byte0]: 38
7851 23:20:02.869786 [Byte1]: 38
7852 23:20:02.874090
7853 23:20:02.874175 Set Vref, RX VrefLevel [Byte0]: 39
7854 23:20:02.877444 [Byte1]: 39
7855 23:20:02.881767
7856 23:20:02.881888 Set Vref, RX VrefLevel [Byte0]: 40
7857 23:20:02.885246 [Byte1]: 40
7858 23:20:02.889487
7859 23:20:02.889572 Set Vref, RX VrefLevel [Byte0]: 41
7860 23:20:02.892464 [Byte1]: 41
7861 23:20:02.896973
7862 23:20:02.897060 Set Vref, RX VrefLevel [Byte0]: 42
7863 23:20:02.900083 [Byte1]: 42
7864 23:20:02.904420
7865 23:20:02.904509 Set Vref, RX VrefLevel [Byte0]: 43
7866 23:20:02.907955 [Byte1]: 43
7867 23:20:02.911887
7868 23:20:02.911975 Set Vref, RX VrefLevel [Byte0]: 44
7869 23:20:02.915269 [Byte1]: 44
7870 23:20:02.919567
7871 23:20:02.919652 Set Vref, RX VrefLevel [Byte0]: 45
7872 23:20:02.922867 [Byte1]: 45
7873 23:20:02.927169
7874 23:20:02.927262 Set Vref, RX VrefLevel [Byte0]: 46
7875 23:20:02.930630 [Byte1]: 46
7876 23:20:02.934835
7877 23:20:02.934922 Set Vref, RX VrefLevel [Byte0]: 47
7878 23:20:02.938070 [Byte1]: 47
7879 23:20:02.942433
7880 23:20:02.942517 Set Vref, RX VrefLevel [Byte0]: 48
7881 23:20:02.945882 [Byte1]: 48
7882 23:20:02.950065
7883 23:20:02.950150 Set Vref, RX VrefLevel [Byte0]: 49
7884 23:20:02.953082 [Byte1]: 49
7885 23:20:02.957459
7886 23:20:02.957544 Set Vref, RX VrefLevel [Byte0]: 50
7887 23:20:02.960602 [Byte1]: 50
7888 23:20:02.965117
7889 23:20:02.965203 Set Vref, RX VrefLevel [Byte0]: 51
7890 23:20:02.968187 [Byte1]: 51
7891 23:20:02.972802
7892 23:20:02.972886 Set Vref, RX VrefLevel [Byte0]: 52
7893 23:20:02.976199 [Byte1]: 52
7894 23:20:02.980357
7895 23:20:02.980442 Set Vref, RX VrefLevel [Byte0]: 53
7896 23:20:02.983904 [Byte1]: 53
7897 23:20:02.987640
7898 23:20:02.987722 Set Vref, RX VrefLevel [Byte0]: 54
7899 23:20:02.991555 [Byte1]: 54
7900 23:20:02.995318
7901 23:20:02.995401 Set Vref, RX VrefLevel [Byte0]: 55
7902 23:20:02.998716 [Byte1]: 55
7903 23:20:03.003124
7904 23:20:03.003209 Set Vref, RX VrefLevel [Byte0]: 56
7905 23:20:03.006392 [Byte1]: 56
7906 23:20:03.010650
7907 23:20:03.010733 Set Vref, RX VrefLevel [Byte0]: 57
7908 23:20:03.014023 [Byte1]: 57
7909 23:20:03.017940
7910 23:20:03.018024 Set Vref, RX VrefLevel [Byte0]: 58
7911 23:20:03.021544 [Byte1]: 58
7912 23:20:03.025610
7913 23:20:03.025696 Set Vref, RX VrefLevel [Byte0]: 59
7914 23:20:03.028950 [Byte1]: 59
7915 23:20:03.033391
7916 23:20:03.033475 Set Vref, RX VrefLevel [Byte0]: 60
7917 23:20:03.036445 [Byte1]: 60
7918 23:20:03.040557
7919 23:20:03.040688 Set Vref, RX VrefLevel [Byte0]: 61
7920 23:20:03.044142 [Byte1]: 61
7921 23:20:03.048355
7922 23:20:03.048440 Set Vref, RX VrefLevel [Byte0]: 62
7923 23:20:03.051475 [Byte1]: 62
7924 23:20:03.055805
7925 23:20:03.055890 Set Vref, RX VrefLevel [Byte0]: 63
7926 23:20:03.062405 [Byte1]: 63
7927 23:20:03.062491
7928 23:20:03.065991 Set Vref, RX VrefLevel [Byte0]: 64
7929 23:20:03.069216 [Byte1]: 64
7930 23:20:03.069300
7931 23:20:03.072257 Set Vref, RX VrefLevel [Byte0]: 65
7932 23:20:03.075855 [Byte1]: 65
7933 23:20:03.075938
7934 23:20:03.079128 Set Vref, RX VrefLevel [Byte0]: 66
7935 23:20:03.082397 [Byte1]: 66
7936 23:20:03.086321
7937 23:20:03.086405 Set Vref, RX VrefLevel [Byte0]: 67
7938 23:20:03.089767 [Byte1]: 67
7939 23:20:03.093860
7940 23:20:03.093944 Set Vref, RX VrefLevel [Byte0]: 68
7941 23:20:03.097172 [Byte1]: 68
7942 23:20:03.101329
7943 23:20:03.101413 Set Vref, RX VrefLevel [Byte0]: 69
7944 23:20:03.104752 [Byte1]: 69
7945 23:20:03.109075
7946 23:20:03.109161 Set Vref, RX VrefLevel [Byte0]: 70
7947 23:20:03.112509 [Byte1]: 70
7948 23:20:03.116540
7949 23:20:03.116627 Set Vref, RX VrefLevel [Byte0]: 71
7950 23:20:03.120311 [Byte1]: 71
7951 23:20:03.123945
7952 23:20:03.124032 Set Vref, RX VrefLevel [Byte0]: 72
7953 23:20:03.127533 [Byte1]: 72
7954 23:20:03.131552
7955 23:20:03.131643 Set Vref, RX VrefLevel [Byte0]: 73
7956 23:20:03.135248 [Byte1]: 73
7957 23:20:03.139409
7958 23:20:03.139494 Set Vref, RX VrefLevel [Byte0]: 74
7959 23:20:03.142568 [Byte1]: 74
7960 23:20:03.146799
7961 23:20:03.146886 Set Vref, RX VrefLevel [Byte0]: 75
7962 23:20:03.150285 [Byte1]: 75
7963 23:20:03.154660
7964 23:20:03.154748 Set Vref, RX VrefLevel [Byte0]: 76
7965 23:20:03.157893 [Byte1]: 76
7966 23:20:03.162201
7967 23:20:03.162286 Set Vref, RX VrefLevel [Byte0]: 77
7968 23:20:03.164999 [Byte1]: 77
7969 23:20:03.169337
7970 23:20:03.169423 Set Vref, RX VrefLevel [Byte0]: 78
7971 23:20:03.172982 [Byte1]: 78
7972 23:20:03.177201
7973 23:20:03.177287 Set Vref, RX VrefLevel [Byte0]: 79
7974 23:20:03.180407 [Byte1]: 79
7975 23:20:03.184898
7976 23:20:03.184984 Set Vref, RX VrefLevel [Byte0]: 80
7977 23:20:03.188210 [Byte1]: 80
7978 23:20:03.192246
7979 23:20:03.192332 Set Vref, RX VrefLevel [Byte0]: 81
7980 23:20:03.195534 [Byte1]: 81
7981 23:20:03.199989
7982 23:20:03.200074 Final RX Vref Byte 0 = 59 to rank0
7983 23:20:03.203297 Final RX Vref Byte 1 = 61 to rank0
7984 23:20:03.206567 Final RX Vref Byte 0 = 59 to rank1
7985 23:20:03.209507 Final RX Vref Byte 1 = 61 to rank1==
7986 23:20:03.212949 Dram Type= 6, Freq= 0, CH_0, rank 0
7987 23:20:03.219474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 23:20:03.219596 ==
7989 23:20:03.219701 DQS Delay:
7990 23:20:03.222928 DQS0 = 0, DQS1 = 0
7991 23:20:03.223036 DQM Delay:
7992 23:20:03.223138 DQM0 = 136, DQM1 = 125
7993 23:20:03.226628 DQ Delay:
7994 23:20:03.229717 DQ0 =136, DQ1 =140, DQ2 =132, DQ3 =132
7995 23:20:03.232832 DQ4 =140, DQ5 =124, DQ6 =142, DQ7 =144
7996 23:20:03.236262 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
7997 23:20:03.239410 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =132
7998 23:20:03.239490
7999 23:20:03.239555
8000 23:20:03.239613
8001 23:20:03.243033 [DramC_TX_OE_Calibration] TA2
8002 23:20:03.246158 Original DQ_B0 (3 6) =30, OEN = 27
8003 23:20:03.249317 Original DQ_B1 (3 6) =30, OEN = 27
8004 23:20:03.252917 24, 0x0, End_B0=24 End_B1=24
8005 23:20:03.253007 25, 0x0, End_B0=25 End_B1=25
8006 23:20:03.256044 26, 0x0, End_B0=26 End_B1=26
8007 23:20:03.259618 27, 0x0, End_B0=27 End_B1=27
8008 23:20:03.262803 28, 0x0, End_B0=28 End_B1=28
8009 23:20:03.266306 29, 0x0, End_B0=29 End_B1=29
8010 23:20:03.266392 30, 0x0, End_B0=30 End_B1=30
8011 23:20:03.269574 31, 0x4141, End_B0=30 End_B1=30
8012 23:20:03.272495 Byte0 end_step=30 best_step=27
8013 23:20:03.276290 Byte1 end_step=30 best_step=27
8014 23:20:03.279223 Byte0 TX OE(2T, 0.5T) = (3, 3)
8015 23:20:03.282739 Byte1 TX OE(2T, 0.5T) = (3, 3)
8016 23:20:03.282826
8017 23:20:03.282894
8018 23:20:03.289452 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8019 23:20:03.292982 CH0 RK0: MR19=303, MR18=1E1C
8020 23:20:03.299538 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
8021 23:20:03.299651
8022 23:20:03.302947 ----->DramcWriteLeveling(PI) begin...
8023 23:20:03.303032 ==
8024 23:20:03.306424 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 23:20:03.309640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 23:20:03.309726 ==
8027 23:20:03.312890 Write leveling (Byte 0): 38 => 38
8028 23:20:03.316366 Write leveling (Byte 1): 29 => 29
8029 23:20:03.319337 DramcWriteLeveling(PI) end<-----
8030 23:20:03.319422
8031 23:20:03.319488 ==
8032 23:20:03.322780 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 23:20:03.326210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 23:20:03.326298 ==
8035 23:20:03.329274 [Gating] SW mode calibration
8036 23:20:03.335792 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8037 23:20:03.342549 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8038 23:20:03.346028 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 23:20:03.349136 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 23:20:03.355736 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 23:20:03.359279 1 4 12 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
8042 23:20:03.362598 1 4 16 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
8043 23:20:03.369101 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 23:20:03.372611 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 23:20:03.375993 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 23:20:03.382483 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 23:20:03.385668 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 23:20:03.389028 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 23:20:03.395566 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
8050 23:20:03.399245 1 5 16 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
8051 23:20:03.402118 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8052 23:20:03.409067 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 23:20:03.412218 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 23:20:03.415621 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 23:20:03.422414 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 23:20:03.425347 1 6 8 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
8057 23:20:03.428937 1 6 12 | B1->B0 | 3030 4444 | 1 0 | (0 0) (0 0)
8058 23:20:03.435468 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8059 23:20:03.438747 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 23:20:03.441833 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 23:20:03.448546 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 23:20:03.452135 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 23:20:03.455140 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 23:20:03.462089 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 23:20:03.465371 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8066 23:20:03.468502 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8067 23:20:03.475378 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 23:20:03.478297 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 23:20:03.481928 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 23:20:03.488304 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 23:20:03.491601 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 23:20:03.495047 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 23:20:03.501442 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 23:20:03.504801 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 23:20:03.508108 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 23:20:03.514710 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 23:20:03.518161 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 23:20:03.521115 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 23:20:03.527968 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 23:20:03.531324 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8081 23:20:03.534827 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8082 23:20:03.541155 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8083 23:20:03.541246 Total UI for P1: 0, mck2ui 16
8084 23:20:03.544490 best dqsien dly found for B0: ( 1, 9, 10)
8085 23:20:03.551325 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8086 23:20:03.554354 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 23:20:03.557679 Total UI for P1: 0, mck2ui 16
8088 23:20:03.561037 best dqsien dly found for B1: ( 1, 9, 16)
8089 23:20:03.564813 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8090 23:20:03.567858 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8091 23:20:03.567933
8092 23:20:03.571391 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8093 23:20:03.577912 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8094 23:20:03.577990 [Gating] SW calibration Done
8095 23:20:03.578054 ==
8096 23:20:03.581068 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 23:20:03.587530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 23:20:03.587616 ==
8099 23:20:03.587683 RX Vref Scan: 0
8100 23:20:03.587746
8101 23:20:03.591052 RX Vref 0 -> 0, step: 1
8102 23:20:03.591147
8103 23:20:03.594266 RX Delay 0 -> 252, step: 8
8104 23:20:03.597619 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8105 23:20:03.601148 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8106 23:20:03.604058 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8107 23:20:03.611309 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8108 23:20:03.614146 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8109 23:20:03.617763 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8110 23:20:03.620934 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8111 23:20:03.624206 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8112 23:20:03.627483 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8113 23:20:03.634354 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8114 23:20:03.637727 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8115 23:20:03.640944 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8116 23:20:03.644592 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8117 23:20:03.647470 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8118 23:20:03.654234 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8119 23:20:03.657432 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8120 23:20:03.657516 ==
8121 23:20:03.661211 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 23:20:03.664208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 23:20:03.664292 ==
8124 23:20:03.667380 DQS Delay:
8125 23:20:03.667488 DQS0 = 0, DQS1 = 0
8126 23:20:03.670761 DQM Delay:
8127 23:20:03.670845 DQM0 = 136, DQM1 = 125
8128 23:20:03.670912 DQ Delay:
8129 23:20:03.674181 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8130 23:20:03.680630 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8131 23:20:03.684452 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8132 23:20:03.687247 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8133 23:20:03.687331
8134 23:20:03.687398
8135 23:20:03.687460 ==
8136 23:20:03.690578 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 23:20:03.693781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 23:20:03.693866 ==
8139 23:20:03.693944
8140 23:20:03.694007
8141 23:20:03.697339 TX Vref Scan disable
8142 23:20:03.700441 == TX Byte 0 ==
8143 23:20:03.704031 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8144 23:20:03.707112 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8145 23:20:03.710568 == TX Byte 1 ==
8146 23:20:03.713817 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8147 23:20:03.717173 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8148 23:20:03.717257 ==
8149 23:20:03.720849 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 23:20:03.726902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 23:20:03.726989 ==
8152 23:20:03.740476
8153 23:20:03.743810 TX Vref early break, caculate TX vref
8154 23:20:03.747235 TX Vref=16, minBit 3, minWin=23, winSum=389
8155 23:20:03.750462 TX Vref=18, minBit 1, minWin=24, winSum=397
8156 23:20:03.753628 TX Vref=20, minBit 8, minWin=24, winSum=407
8157 23:20:03.757341 TX Vref=22, minBit 0, minWin=25, winSum=415
8158 23:20:03.760360 TX Vref=24, minBit 0, minWin=25, winSum=422
8159 23:20:03.767301 TX Vref=26, minBit 0, minWin=26, winSum=431
8160 23:20:03.770221 TX Vref=28, minBit 0, minWin=26, winSum=431
8161 23:20:03.773530 TX Vref=30, minBit 0, minWin=26, winSum=427
8162 23:20:03.777125 TX Vref=32, minBit 0, minWin=25, winSum=421
8163 23:20:03.780178 TX Vref=34, minBit 4, minWin=24, winSum=410
8164 23:20:03.783378 TX Vref=36, minBit 2, minWin=24, winSum=403
8165 23:20:03.790082 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 26
8166 23:20:03.790176
8167 23:20:03.793410 Final TX Range 0 Vref 26
8168 23:20:03.793496
8169 23:20:03.793563 ==
8170 23:20:03.796798 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 23:20:03.799923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 23:20:03.800010 ==
8173 23:20:03.800077
8174 23:20:03.803240
8175 23:20:03.803325 TX Vref Scan disable
8176 23:20:03.810028 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8177 23:20:03.810115 == TX Byte 0 ==
8178 23:20:03.813358 u2DelayCellOfst[0]=13 cells (4 PI)
8179 23:20:03.816584 u2DelayCellOfst[1]=20 cells (6 PI)
8180 23:20:03.820051 u2DelayCellOfst[2]=13 cells (4 PI)
8181 23:20:03.823452 u2DelayCellOfst[3]=13 cells (4 PI)
8182 23:20:03.826803 u2DelayCellOfst[4]=10 cells (3 PI)
8183 23:20:03.829737 u2DelayCellOfst[5]=0 cells (0 PI)
8184 23:20:03.833552 u2DelayCellOfst[6]=20 cells (6 PI)
8185 23:20:03.836911 u2DelayCellOfst[7]=20 cells (6 PI)
8186 23:20:03.840103 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8187 23:20:03.843075 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8188 23:20:03.846780 == TX Byte 1 ==
8189 23:20:03.850053 u2DelayCellOfst[8]=0 cells (0 PI)
8190 23:20:03.853340 u2DelayCellOfst[9]=3 cells (1 PI)
8191 23:20:03.856785 u2DelayCellOfst[10]=6 cells (2 PI)
8192 23:20:03.856871 u2DelayCellOfst[11]=3 cells (1 PI)
8193 23:20:03.859894 u2DelayCellOfst[12]=13 cells (4 PI)
8194 23:20:03.863148 u2DelayCellOfst[13]=13 cells (4 PI)
8195 23:20:03.866358 u2DelayCellOfst[14]=16 cells (5 PI)
8196 23:20:03.869746 u2DelayCellOfst[15]=10 cells (3 PI)
8197 23:20:03.876549 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8198 23:20:03.879730 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8199 23:20:03.879817 DramC Write-DBI on
8200 23:20:03.879886 ==
8201 23:20:03.883205 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 23:20:03.889737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 23:20:03.889827 ==
8204 23:20:03.889896
8205 23:20:03.889959
8206 23:20:03.892800 TX Vref Scan disable
8207 23:20:03.892885 == TX Byte 0 ==
8208 23:20:03.899731 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8209 23:20:03.899818 == TX Byte 1 ==
8210 23:20:03.902865 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8211 23:20:03.905951 DramC Write-DBI off
8212 23:20:03.906036
8213 23:20:03.906103 [DATLAT]
8214 23:20:03.909480 Freq=1600, CH0 RK1
8215 23:20:03.909565
8216 23:20:03.909632 DATLAT Default: 0xf
8217 23:20:03.912934 0, 0xFFFF, sum = 0
8218 23:20:03.913021 1, 0xFFFF, sum = 0
8219 23:20:03.916224 2, 0xFFFF, sum = 0
8220 23:20:03.916308 3, 0xFFFF, sum = 0
8221 23:20:03.919585 4, 0xFFFF, sum = 0
8222 23:20:03.919671 5, 0xFFFF, sum = 0
8223 23:20:03.923136 6, 0xFFFF, sum = 0
8224 23:20:03.923221 7, 0xFFFF, sum = 0
8225 23:20:03.925883 8, 0xFFFF, sum = 0
8226 23:20:03.926006 9, 0xFFFF, sum = 0
8227 23:20:03.929428 10, 0xFFFF, sum = 0
8228 23:20:03.932676 11, 0xFFFF, sum = 0
8229 23:20:03.932776 12, 0xFFFF, sum = 0
8230 23:20:03.936188 13, 0xFFFF, sum = 0
8231 23:20:03.936273 14, 0x0, sum = 1
8232 23:20:03.939522 15, 0x0, sum = 2
8233 23:20:03.939607 16, 0x0, sum = 3
8234 23:20:03.939675 17, 0x0, sum = 4
8235 23:20:03.942930 best_step = 15
8236 23:20:03.943015
8237 23:20:03.943091 ==
8238 23:20:03.946337 Dram Type= 6, Freq= 0, CH_0, rank 1
8239 23:20:03.949395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8240 23:20:03.949488 ==
8241 23:20:03.952631 RX Vref Scan: 0
8242 23:20:03.952782
8243 23:20:03.952883 RX Vref 0 -> 0, step: 1
8244 23:20:03.956027
8245 23:20:03.956139 RX Delay 11 -> 252, step: 4
8246 23:20:03.962979 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8247 23:20:03.966394 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8248 23:20:03.969342 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8249 23:20:03.972741 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8250 23:20:03.976046 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8251 23:20:03.983154 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8252 23:20:03.986176 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8253 23:20:03.989365 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8254 23:20:03.992930 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8255 23:20:03.996033 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8256 23:20:04.003046 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8257 23:20:04.006199 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8258 23:20:04.009464 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8259 23:20:04.012593 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8260 23:20:04.016281 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8261 23:20:04.023054 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8262 23:20:04.023168 ==
8263 23:20:04.025921 Dram Type= 6, Freq= 0, CH_0, rank 1
8264 23:20:04.029226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 23:20:04.029310 ==
8266 23:20:04.029381 DQS Delay:
8267 23:20:04.032583 DQS0 = 0, DQS1 = 0
8268 23:20:04.032717 DQM Delay:
8269 23:20:04.036107 DQM0 = 133, DQM1 = 123
8270 23:20:04.036205 DQ Delay:
8271 23:20:04.039460 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8272 23:20:04.042798 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8273 23:20:04.045804 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8274 23:20:04.049202 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8275 23:20:04.049282
8276 23:20:04.053002
8277 23:20:04.053075
8278 23:20:04.053138 [DramC_TX_OE_Calibration] TA2
8279 23:20:04.055990 Original DQ_B0 (3 6) =30, OEN = 27
8280 23:20:04.059457 Original DQ_B1 (3 6) =30, OEN = 27
8281 23:20:04.062713 24, 0x0, End_B0=24 End_B1=24
8282 23:20:04.066436 25, 0x0, End_B0=25 End_B1=25
8283 23:20:04.069151 26, 0x0, End_B0=26 End_B1=26
8284 23:20:04.069229 27, 0x0, End_B0=27 End_B1=27
8285 23:20:04.072556 28, 0x0, End_B0=28 End_B1=28
8286 23:20:04.075990 29, 0x0, End_B0=29 End_B1=29
8287 23:20:04.079439 30, 0x0, End_B0=30 End_B1=30
8288 23:20:04.082501 31, 0x4141, End_B0=30 End_B1=30
8289 23:20:04.082578 Byte0 end_step=30 best_step=27
8290 23:20:04.085975 Byte1 end_step=30 best_step=27
8291 23:20:04.088863 Byte0 TX OE(2T, 0.5T) = (3, 3)
8292 23:20:04.092562 Byte1 TX OE(2T, 0.5T) = (3, 3)
8293 23:20:04.092701
8294 23:20:04.092767
8295 23:20:04.102216 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
8296 23:20:04.102328 CH0 RK1: MR19=303, MR18=1E0B
8297 23:20:04.108857 CH0_RK1: MR19=0x303, MR18=0x1E0B, DQSOSC=394, MR23=63, INC=23, DEC=15
8298 23:20:04.112528 [RxdqsGatingPostProcess] freq 1600
8299 23:20:04.118920 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8300 23:20:04.122551 best DQS0 dly(2T, 0.5T) = (1, 1)
8301 23:20:04.125602 best DQS1 dly(2T, 0.5T) = (1, 1)
8302 23:20:04.128855 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8303 23:20:04.128944 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8304 23:20:04.132239 best DQS0 dly(2T, 0.5T) = (1, 1)
8305 23:20:04.135732 best DQS1 dly(2T, 0.5T) = (1, 1)
8306 23:20:04.138706 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8307 23:20:04.141941 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8308 23:20:04.145522 Pre-setting of DQS Precalculation
8309 23:20:04.151888 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8310 23:20:04.151987 ==
8311 23:20:04.155206 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 23:20:04.158598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 23:20:04.158686 ==
8314 23:20:04.165060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8315 23:20:04.168392 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8316 23:20:04.172128 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8317 23:20:04.178229 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8318 23:20:04.187147 [CA 0] Center 40 (11~70) winsize 60
8319 23:20:04.190167 [CA 1] Center 41 (11~71) winsize 61
8320 23:20:04.193790 [CA 2] Center 36 (7~66) winsize 60
8321 23:20:04.196768 [CA 3] Center 36 (6~66) winsize 61
8322 23:20:04.200545 [CA 4] Center 36 (6~67) winsize 62
8323 23:20:04.203362 [CA 5] Center 35 (6~65) winsize 60
8324 23:20:04.203439
8325 23:20:04.206656 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8326 23:20:04.206741
8327 23:20:04.210129 [CATrainingPosCal] consider 1 rank data
8328 23:20:04.213436 u2DelayCellTimex100 = 290/100 ps
8329 23:20:04.216610 CA0 delay=40 (11~70),Diff = 5 PI (16 cell)
8330 23:20:04.223403 CA1 delay=41 (11~71),Diff = 6 PI (20 cell)
8331 23:20:04.226584 CA2 delay=36 (7~66),Diff = 1 PI (3 cell)
8332 23:20:04.229993 CA3 delay=36 (6~66),Diff = 1 PI (3 cell)
8333 23:20:04.233432 CA4 delay=36 (6~67),Diff = 1 PI (3 cell)
8334 23:20:04.236914 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
8335 23:20:04.236996
8336 23:20:04.240144 CA PerBit enable=1, Macro0, CA PI delay=35
8337 23:20:04.240225
8338 23:20:04.243487 [CBTSetCACLKResult] CA Dly = 35
8339 23:20:04.246757 CS Dly: 8 (0~39)
8340 23:20:04.249944 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8341 23:20:04.253509 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8342 23:20:04.253593 ==
8343 23:20:04.256822 Dram Type= 6, Freq= 0, CH_1, rank 1
8344 23:20:04.260153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 23:20:04.260241 ==
8346 23:20:04.266544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8347 23:20:04.269975 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8348 23:20:04.276597 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8349 23:20:04.280068 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8350 23:20:04.290066 [CA 0] Center 42 (12~72) winsize 61
8351 23:20:04.293723 [CA 1] Center 42 (12~72) winsize 61
8352 23:20:04.296987 [CA 2] Center 37 (8~67) winsize 60
8353 23:20:04.300112 [CA 3] Center 37 (8~66) winsize 59
8354 23:20:04.303215 [CA 4] Center 37 (8~67) winsize 60
8355 23:20:04.306596 [CA 5] Center 36 (7~66) winsize 60
8356 23:20:04.306680
8357 23:20:04.309993 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8358 23:20:04.310124
8359 23:20:04.316260 [CATrainingPosCal] consider 2 rank data
8360 23:20:04.316348 u2DelayCellTimex100 = 290/100 ps
8361 23:20:04.323516 CA0 delay=41 (12~70),Diff = 5 PI (16 cell)
8362 23:20:04.326295 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8363 23:20:04.329666 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8364 23:20:04.333168 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8365 23:20:04.336427 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8366 23:20:04.339939 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8367 23:20:04.340020
8368 23:20:04.342712 CA PerBit enable=1, Macro0, CA PI delay=36
8369 23:20:04.342793
8370 23:20:04.346264 [CBTSetCACLKResult] CA Dly = 36
8371 23:20:04.349404 CS Dly: 9 (0~42)
8372 23:20:04.352916 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8373 23:20:04.356185 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8374 23:20:04.356268
8375 23:20:04.359870 ----->DramcWriteLeveling(PI) begin...
8376 23:20:04.359954 ==
8377 23:20:04.362680 Dram Type= 6, Freq= 0, CH_1, rank 0
8378 23:20:04.369440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8379 23:20:04.369525 ==
8380 23:20:04.372639 Write leveling (Byte 0): 24 => 24
8381 23:20:04.372764 Write leveling (Byte 1): 29 => 29
8382 23:20:04.376050 DramcWriteLeveling(PI) end<-----
8383 23:20:04.376131
8384 23:20:04.376195 ==
8385 23:20:04.379591 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 23:20:04.386107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 23:20:04.386192 ==
8388 23:20:04.389159 [Gating] SW mode calibration
8389 23:20:04.396135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8390 23:20:04.399214 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8391 23:20:04.406186 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 23:20:04.409115 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 23:20:04.412841 1 4 8 | B1->B0 | 2322 2b2b | 1 1 | (0 0) (1 1)
8394 23:20:04.419126 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 23:20:04.422568 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 23:20:04.425762 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 23:20:04.432593 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 23:20:04.436071 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 23:20:04.439588 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 23:20:04.442993 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8401 23:20:04.449553 1 5 8 | B1->B0 | 2b2b 2727 | 1 0 | (1 0) (1 0)
8402 23:20:04.452633 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8403 23:20:04.455959 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 23:20:04.462741 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 23:20:04.465937 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 23:20:04.469224 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 23:20:04.476088 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 23:20:04.479448 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 23:20:04.482718 1 6 8 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
8410 23:20:04.489051 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 23:20:04.492564 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 23:20:04.495776 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 23:20:04.502671 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 23:20:04.505829 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 23:20:04.509064 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 23:20:04.515758 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 23:20:04.519335 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8418 23:20:04.522475 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8419 23:20:04.528953 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 23:20:04.532084 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 23:20:04.535455 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 23:20:04.542254 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 23:20:04.545790 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 23:20:04.549202 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 23:20:04.555309 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 23:20:04.558730 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 23:20:04.561949 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 23:20:04.568701 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 23:20:04.572039 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 23:20:04.575453 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 23:20:04.581906 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 23:20:04.585692 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8433 23:20:04.588884 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8434 23:20:04.592281 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8435 23:20:04.595265 Total UI for P1: 0, mck2ui 16
8436 23:20:04.598910 best dqsien dly found for B0: ( 1, 9, 6)
8437 23:20:04.605495 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 23:20:04.608870 Total UI for P1: 0, mck2ui 16
8439 23:20:04.612207 best dqsien dly found for B1: ( 1, 9, 10)
8440 23:20:04.615057 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8441 23:20:04.618764 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8442 23:20:04.618852
8443 23:20:04.622004 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8444 23:20:04.625385 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8445 23:20:04.628446 [Gating] SW calibration Done
8446 23:20:04.628564 ==
8447 23:20:04.631827 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 23:20:04.635237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 23:20:04.635325 ==
8450 23:20:04.638681 RX Vref Scan: 0
8451 23:20:04.638766
8452 23:20:04.638832 RX Vref 0 -> 0, step: 1
8453 23:20:04.642099
8454 23:20:04.642183 RX Delay 0 -> 252, step: 8
8455 23:20:04.645383 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8456 23:20:04.651921 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8457 23:20:04.655607 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8458 23:20:04.658898 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8459 23:20:04.661891 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8460 23:20:04.665305 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8461 23:20:04.671957 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8462 23:20:04.675393 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8463 23:20:04.678724 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8464 23:20:04.682089 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8465 23:20:04.685087 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8466 23:20:04.688925 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8467 23:20:04.695072 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8468 23:20:04.698421 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8469 23:20:04.701888 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8470 23:20:04.705290 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8471 23:20:04.705379 ==
8472 23:20:04.708623 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 23:20:04.715231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 23:20:04.715328 ==
8475 23:20:04.715397 DQS Delay:
8476 23:20:04.718509 DQS0 = 0, DQS1 = 0
8477 23:20:04.718594 DQM Delay:
8478 23:20:04.721692 DQM0 = 138, DQM1 = 131
8479 23:20:04.721777 DQ Delay:
8480 23:20:04.724978 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8481 23:20:04.728687 DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =135
8482 23:20:04.731696 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8483 23:20:04.735193 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8484 23:20:04.735282
8485 23:20:04.735348
8486 23:20:04.735408 ==
8487 23:20:04.738477 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 23:20:04.744864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 23:20:04.744962 ==
8490 23:20:04.745030
8491 23:20:04.745090
8492 23:20:04.745147 TX Vref Scan disable
8493 23:20:04.748485 == TX Byte 0 ==
8494 23:20:04.751591 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8495 23:20:04.758448 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8496 23:20:04.758546 == TX Byte 1 ==
8497 23:20:04.761773 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8498 23:20:04.768512 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8499 23:20:04.768607 ==
8500 23:20:04.771976 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 23:20:04.774790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 23:20:04.774876 ==
8503 23:20:04.787180
8504 23:20:04.790677 TX Vref early break, caculate TX vref
8505 23:20:04.794148 TX Vref=16, minBit 10, minWin=21, winSum=365
8506 23:20:04.797577 TX Vref=18, minBit 10, minWin=22, winSum=378
8507 23:20:04.800558 TX Vref=20, minBit 10, minWin=22, winSum=388
8508 23:20:04.803764 TX Vref=22, minBit 15, minWin=22, winSum=396
8509 23:20:04.810588 TX Vref=24, minBit 10, minWin=23, winSum=400
8510 23:20:04.813820 TX Vref=26, minBit 14, minWin=24, winSum=414
8511 23:20:04.817375 TX Vref=28, minBit 14, minWin=24, winSum=417
8512 23:20:04.820762 TX Vref=30, minBit 9, minWin=23, winSum=409
8513 23:20:04.823995 TX Vref=32, minBit 8, minWin=23, winSum=400
8514 23:20:04.826967 TX Vref=34, minBit 8, minWin=23, winSum=391
8515 23:20:04.833844 [TxChooseVref] Worse bit 14, Min win 24, Win sum 417, Final Vref 28
8516 23:20:04.833952
8517 23:20:04.837179 Final TX Range 0 Vref 28
8518 23:20:04.837266
8519 23:20:04.837332 ==
8520 23:20:04.840641 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 23:20:04.843884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 23:20:04.843971 ==
8523 23:20:04.844036
8524 23:20:04.844100
8525 23:20:04.847381 TX Vref Scan disable
8526 23:20:04.853573 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8527 23:20:04.853669 == TX Byte 0 ==
8528 23:20:04.856998 u2DelayCellOfst[0]=16 cells (5 PI)
8529 23:20:04.860456 u2DelayCellOfst[1]=6 cells (2 PI)
8530 23:20:04.863721 u2DelayCellOfst[2]=0 cells (0 PI)
8531 23:20:04.867255 u2DelayCellOfst[3]=3 cells (1 PI)
8532 23:20:04.870606 u2DelayCellOfst[4]=6 cells (2 PI)
8533 23:20:04.873934 u2DelayCellOfst[5]=16 cells (5 PI)
8534 23:20:04.877352 u2DelayCellOfst[6]=16 cells (5 PI)
8535 23:20:04.880605 u2DelayCellOfst[7]=3 cells (1 PI)
8536 23:20:04.883827 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8537 23:20:04.887314 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8538 23:20:04.890382 == TX Byte 1 ==
8539 23:20:04.890466 u2DelayCellOfst[8]=0 cells (0 PI)
8540 23:20:04.894214 u2DelayCellOfst[9]=6 cells (2 PI)
8541 23:20:04.897125 u2DelayCellOfst[10]=13 cells (4 PI)
8542 23:20:04.900509 u2DelayCellOfst[11]=6 cells (2 PI)
8543 23:20:04.903830 u2DelayCellOfst[12]=16 cells (5 PI)
8544 23:20:04.907320 u2DelayCellOfst[13]=20 cells (6 PI)
8545 23:20:04.910515 u2DelayCellOfst[14]=20 cells (6 PI)
8546 23:20:04.913965 u2DelayCellOfst[15]=16 cells (5 PI)
8547 23:20:04.917162 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8548 23:20:04.923909 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8549 23:20:04.923998 DramC Write-DBI on
8550 23:20:04.924064 ==
8551 23:20:04.927090 Dram Type= 6, Freq= 0, CH_1, rank 0
8552 23:20:04.930407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8553 23:20:04.933711 ==
8554 23:20:04.933795
8555 23:20:04.933860
8556 23:20:04.933921 TX Vref Scan disable
8557 23:20:04.937349 == TX Byte 0 ==
8558 23:20:04.940482 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8559 23:20:04.943671 == TX Byte 1 ==
8560 23:20:04.947167 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8561 23:20:04.947252 DramC Write-DBI off
8562 23:20:04.950281
8563 23:20:04.950365 [DATLAT]
8564 23:20:04.950432 Freq=1600, CH1 RK0
8565 23:20:04.950494
8566 23:20:04.954048 DATLAT Default: 0xf
8567 23:20:04.954132 0, 0xFFFF, sum = 0
8568 23:20:04.957058 1, 0xFFFF, sum = 0
8569 23:20:04.957144 2, 0xFFFF, sum = 0
8570 23:20:04.960444 3, 0xFFFF, sum = 0
8571 23:20:04.963948 4, 0xFFFF, sum = 0
8572 23:20:04.964036 5, 0xFFFF, sum = 0
8573 23:20:04.967401 6, 0xFFFF, sum = 0
8574 23:20:04.967496 7, 0xFFFF, sum = 0
8575 23:20:04.970538 8, 0xFFFF, sum = 0
8576 23:20:04.970616 9, 0xFFFF, sum = 0
8577 23:20:04.973778 10, 0xFFFF, sum = 0
8578 23:20:04.973853 11, 0xFFFF, sum = 0
8579 23:20:04.976964 12, 0xFFFF, sum = 0
8580 23:20:04.977036 13, 0xFFFF, sum = 0
8581 23:20:04.980303 14, 0x0, sum = 1
8582 23:20:04.980381 15, 0x0, sum = 2
8583 23:20:04.983705 16, 0x0, sum = 3
8584 23:20:04.983795 17, 0x0, sum = 4
8585 23:20:04.987100 best_step = 15
8586 23:20:04.987176
8587 23:20:04.987239 ==
8588 23:20:04.990596 Dram Type= 6, Freq= 0, CH_1, rank 0
8589 23:20:04.993504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8590 23:20:04.993584 ==
8591 23:20:04.993647 RX Vref Scan: 1
8592 23:20:04.997212
8593 23:20:04.997284 Set Vref Range= 24 -> 127
8594 23:20:04.997346
8595 23:20:05.000596 RX Vref 24 -> 127, step: 1
8596 23:20:05.000679
8597 23:20:05.003496 RX Delay 19 -> 252, step: 4
8598 23:20:05.003567
8599 23:20:05.006740 Set Vref, RX VrefLevel [Byte0]: 24
8600 23:20:05.010162 [Byte1]: 24
8601 23:20:05.010241
8602 23:20:05.013463 Set Vref, RX VrefLevel [Byte0]: 25
8603 23:20:05.016933 [Byte1]: 25
8604 23:20:05.017006
8605 23:20:05.020187 Set Vref, RX VrefLevel [Byte0]: 26
8606 23:20:05.023757 [Byte1]: 26
8607 23:20:05.027419
8608 23:20:05.027493 Set Vref, RX VrefLevel [Byte0]: 27
8609 23:20:05.030651 [Byte1]: 27
8610 23:20:05.035188
8611 23:20:05.035266 Set Vref, RX VrefLevel [Byte0]: 28
8612 23:20:05.038549 [Byte1]: 28
8613 23:20:05.042568
8614 23:20:05.042645 Set Vref, RX VrefLevel [Byte0]: 29
8615 23:20:05.045922 [Byte1]: 29
8616 23:20:05.050228
8617 23:20:05.050308 Set Vref, RX VrefLevel [Byte0]: 30
8618 23:20:05.053287 [Byte1]: 30
8619 23:20:05.057746
8620 23:20:05.057823 Set Vref, RX VrefLevel [Byte0]: 31
8621 23:20:05.061118 [Byte1]: 31
8622 23:20:05.065366
8623 23:20:05.065444 Set Vref, RX VrefLevel [Byte0]: 32
8624 23:20:05.068912 [Byte1]: 32
8625 23:20:05.073102
8626 23:20:05.073194 Set Vref, RX VrefLevel [Byte0]: 33
8627 23:20:05.076026 [Byte1]: 33
8628 23:20:05.080428
8629 23:20:05.080512 Set Vref, RX VrefLevel [Byte0]: 34
8630 23:20:05.083966 [Byte1]: 34
8631 23:20:05.088277
8632 23:20:05.088358 Set Vref, RX VrefLevel [Byte0]: 35
8633 23:20:05.091435 [Byte1]: 35
8634 23:20:05.095348
8635 23:20:05.095458 Set Vref, RX VrefLevel [Byte0]: 36
8636 23:20:05.099115 [Byte1]: 36
8637 23:20:05.103190
8638 23:20:05.103270 Set Vref, RX VrefLevel [Byte0]: 37
8639 23:20:05.106803 [Byte1]: 37
8640 23:20:05.110906
8641 23:20:05.110983 Set Vref, RX VrefLevel [Byte0]: 38
8642 23:20:05.114167 [Byte1]: 38
8643 23:20:05.118101
8644 23:20:05.118175 Set Vref, RX VrefLevel [Byte0]: 39
8645 23:20:05.121512 [Byte1]: 39
8646 23:20:05.126023
8647 23:20:05.126129 Set Vref, RX VrefLevel [Byte0]: 40
8648 23:20:05.129236 [Byte1]: 40
8649 23:20:05.133528
8650 23:20:05.133617 Set Vref, RX VrefLevel [Byte0]: 41
8651 23:20:05.136870 [Byte1]: 41
8652 23:20:05.141212
8653 23:20:05.141300 Set Vref, RX VrefLevel [Byte0]: 42
8654 23:20:05.144055 [Byte1]: 42
8655 23:20:05.148393
8656 23:20:05.148514 Set Vref, RX VrefLevel [Byte0]: 43
8657 23:20:05.152081 [Byte1]: 43
8658 23:20:05.156122
8659 23:20:05.156207 Set Vref, RX VrefLevel [Byte0]: 44
8660 23:20:05.159489 [Byte1]: 44
8661 23:20:05.163524
8662 23:20:05.163637 Set Vref, RX VrefLevel [Byte0]: 45
8663 23:20:05.167070 [Byte1]: 45
8664 23:20:05.171384
8665 23:20:05.171491 Set Vref, RX VrefLevel [Byte0]: 46
8666 23:20:05.174481 [Byte1]: 46
8667 23:20:05.178976
8668 23:20:05.179093 Set Vref, RX VrefLevel [Byte0]: 47
8669 23:20:05.182158 [Byte1]: 47
8670 23:20:05.186219
8671 23:20:05.186301 Set Vref, RX VrefLevel [Byte0]: 48
8672 23:20:05.189848 [Byte1]: 48
8673 23:20:05.194304
8674 23:20:05.194409 Set Vref, RX VrefLevel [Byte0]: 49
8675 23:20:05.197085 [Byte1]: 49
8676 23:20:05.201569
8677 23:20:05.201657 Set Vref, RX VrefLevel [Byte0]: 50
8678 23:20:05.205040 [Byte1]: 50
8679 23:20:05.209231
8680 23:20:05.209310 Set Vref, RX VrefLevel [Byte0]: 51
8681 23:20:05.212612 [Byte1]: 51
8682 23:20:05.216566
8683 23:20:05.216701 Set Vref, RX VrefLevel [Byte0]: 52
8684 23:20:05.220020 [Byte1]: 52
8685 23:20:05.224374
8686 23:20:05.224477 Set Vref, RX VrefLevel [Byte0]: 53
8687 23:20:05.227867 [Byte1]: 53
8688 23:20:05.232033
8689 23:20:05.232145 Set Vref, RX VrefLevel [Byte0]: 54
8690 23:20:05.235224 [Byte1]: 54
8691 23:20:05.239354
8692 23:20:05.239460 Set Vref, RX VrefLevel [Byte0]: 55
8693 23:20:05.242703 [Byte1]: 55
8694 23:20:05.247067
8695 23:20:05.247174 Set Vref, RX VrefLevel [Byte0]: 56
8696 23:20:05.250382 [Byte1]: 56
8697 23:20:05.254565
8698 23:20:05.254669 Set Vref, RX VrefLevel [Byte0]: 57
8699 23:20:05.257810 [Byte1]: 57
8700 23:20:05.262231
8701 23:20:05.262335 Set Vref, RX VrefLevel [Byte0]: 58
8702 23:20:05.265585 [Byte1]: 58
8703 23:20:05.269663
8704 23:20:05.269745 Set Vref, RX VrefLevel [Byte0]: 59
8705 23:20:05.272899 [Byte1]: 59
8706 23:20:05.277183
8707 23:20:05.277289 Set Vref, RX VrefLevel [Byte0]: 60
8708 23:20:05.280848 [Byte1]: 60
8709 23:20:05.284710
8710 23:20:05.284791 Set Vref, RX VrefLevel [Byte0]: 61
8711 23:20:05.288266 [Byte1]: 61
8712 23:20:05.292398
8713 23:20:05.292500 Set Vref, RX VrefLevel [Byte0]: 62
8714 23:20:05.295995 [Byte1]: 62
8715 23:20:05.299864
8716 23:20:05.299942 Set Vref, RX VrefLevel [Byte0]: 63
8717 23:20:05.303282 [Byte1]: 63
8718 23:20:05.307437
8719 23:20:05.307514 Set Vref, RX VrefLevel [Byte0]: 64
8720 23:20:05.311008 [Byte1]: 64
8721 23:20:05.315123
8722 23:20:05.315203 Set Vref, RX VrefLevel [Byte0]: 65
8723 23:20:05.318542 [Byte1]: 65
8724 23:20:05.322967
8725 23:20:05.323045 Set Vref, RX VrefLevel [Byte0]: 66
8726 23:20:05.326457 [Byte1]: 66
8727 23:20:05.330345
8728 23:20:05.330424 Set Vref, RX VrefLevel [Byte0]: 67
8729 23:20:05.333746 [Byte1]: 67
8730 23:20:05.337783
8731 23:20:05.337861 Set Vref, RX VrefLevel [Byte0]: 68
8732 23:20:05.341079 [Byte1]: 68
8733 23:20:05.345278
8734 23:20:05.345356 Set Vref, RX VrefLevel [Byte0]: 69
8735 23:20:05.348761 [Byte1]: 69
8736 23:20:05.353018
8737 23:20:05.353095 Set Vref, RX VrefLevel [Byte0]: 70
8738 23:20:05.356291 [Byte1]: 70
8739 23:20:05.360846
8740 23:20:05.360924 Set Vref, RX VrefLevel [Byte0]: 71
8741 23:20:05.363998 [Byte1]: 71
8742 23:20:05.368385
8743 23:20:05.368489 Set Vref, RX VrefLevel [Byte0]: 72
8744 23:20:05.371456 [Byte1]: 72
8745 23:20:05.375677
8746 23:20:05.375755 Final RX Vref Byte 0 = 53 to rank0
8747 23:20:05.379167 Final RX Vref Byte 1 = 63 to rank0
8748 23:20:05.382379 Final RX Vref Byte 0 = 53 to rank1
8749 23:20:05.385663 Final RX Vref Byte 1 = 63 to rank1==
8750 23:20:05.389152 Dram Type= 6, Freq= 0, CH_1, rank 0
8751 23:20:05.395792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8752 23:20:05.395878 ==
8753 23:20:05.395968 DQS Delay:
8754 23:20:05.396049 DQS0 = 0, DQS1 = 0
8755 23:20:05.398959 DQM Delay:
8756 23:20:05.399061 DQM0 = 133, DQM1 = 128
8757 23:20:05.402616 DQ Delay:
8758 23:20:05.405697 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8759 23:20:05.409144 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8760 23:20:05.412541 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8761 23:20:05.415546 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =134
8762 23:20:05.415650
8763 23:20:05.415750
8764 23:20:05.415853
8765 23:20:05.419198 [DramC_TX_OE_Calibration] TA2
8766 23:20:05.422082 Original DQ_B0 (3 6) =30, OEN = 27
8767 23:20:05.426002 Original DQ_B1 (3 6) =30, OEN = 27
8768 23:20:05.429063 24, 0x0, End_B0=24 End_B1=24
8769 23:20:05.429183 25, 0x0, End_B0=25 End_B1=25
8770 23:20:05.432436 26, 0x0, End_B0=26 End_B1=26
8771 23:20:05.435504 27, 0x0, End_B0=27 End_B1=27
8772 23:20:05.439106 28, 0x0, End_B0=28 End_B1=28
8773 23:20:05.439214 29, 0x0, End_B0=29 End_B1=29
8774 23:20:05.442439 30, 0x0, End_B0=30 End_B1=30
8775 23:20:05.445736 31, 0x4141, End_B0=30 End_B1=30
8776 23:20:05.449013 Byte0 end_step=30 best_step=27
8777 23:20:05.452546 Byte1 end_step=30 best_step=27
8778 23:20:05.455790 Byte0 TX OE(2T, 0.5T) = (3, 3)
8779 23:20:05.455894 Byte1 TX OE(2T, 0.5T) = (3, 3)
8780 23:20:05.455999
8781 23:20:05.458870
8782 23:20:05.465657 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8783 23:20:05.468777 CH1 RK0: MR19=303, MR18=1624
8784 23:20:05.475751 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8785 23:20:05.475835
8786 23:20:05.479031 ----->DramcWriteLeveling(PI) begin...
8787 23:20:05.479138 ==
8788 23:20:05.482188 Dram Type= 6, Freq= 0, CH_1, rank 1
8789 23:20:05.485581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8790 23:20:05.485661 ==
8791 23:20:05.489188 Write leveling (Byte 0): 26 => 26
8792 23:20:05.492360 Write leveling (Byte 1): 28 => 28
8793 23:20:05.495819 DramcWriteLeveling(PI) end<-----
8794 23:20:05.495898
8795 23:20:05.495983 ==
8796 23:20:05.499098 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 23:20:05.502476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 23:20:05.502558 ==
8799 23:20:05.505847 [Gating] SW mode calibration
8800 23:20:05.512473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8801 23:20:05.519210 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8802 23:20:05.522085 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 23:20:05.525431 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 23:20:05.532316 1 4 8 | B1->B0 | 3030 2323 | 1 0 | (0 0) (0 0)
8805 23:20:05.535709 1 4 12 | B1->B0 | 3434 302f | 1 1 | (1 1) (1 1)
8806 23:20:05.539448 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 23:20:05.545499 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 23:20:05.548945 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 23:20:05.552251 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 23:20:05.559016 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 23:20:05.562191 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8812 23:20:05.565346 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
8813 23:20:05.571973 1 5 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 0)
8814 23:20:05.575216 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 23:20:05.578906 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 23:20:05.582239 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 23:20:05.588969 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 23:20:05.592054 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 23:20:05.595518 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8820 23:20:05.602230 1 6 8 | B1->B0 | 4646 2626 | 0 0 | (0 0) (0 0)
8821 23:20:05.605535 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8822 23:20:05.608502 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 23:20:05.615348 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 23:20:05.618632 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 23:20:05.622071 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 23:20:05.628818 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 23:20:05.632101 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 23:20:05.635428 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8829 23:20:05.642168 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8830 23:20:05.645254 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 23:20:05.648514 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 23:20:05.655125 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 23:20:05.658905 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 23:20:05.662700 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 23:20:05.668448 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 23:20:05.672115 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 23:20:05.675336 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 23:20:05.681660 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 23:20:05.685008 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 23:20:05.688429 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 23:20:05.695382 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 23:20:05.698303 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 23:20:05.701615 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 23:20:05.708465 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8845 23:20:05.711610 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 23:20:05.715171 Total UI for P1: 0, mck2ui 16
8847 23:20:05.718306 best dqsien dly found for B0: ( 1, 9, 8)
8848 23:20:05.721990 Total UI for P1: 0, mck2ui 16
8849 23:20:05.725302 best dqsien dly found for B1: ( 1, 9, 8)
8850 23:20:05.728580 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8851 23:20:05.731510 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8852 23:20:05.731598
8853 23:20:05.735159 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8854 23:20:05.738733 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8855 23:20:05.741654 [Gating] SW calibration Done
8856 23:20:05.741740 ==
8857 23:20:05.745316 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 23:20:05.748196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 23:20:05.748283 ==
8860 23:20:05.751893 RX Vref Scan: 0
8861 23:20:05.751979
8862 23:20:05.752064 RX Vref 0 -> 0, step: 1
8863 23:20:05.754736
8864 23:20:05.754822 RX Delay 0 -> 252, step: 8
8865 23:20:05.758564 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8866 23:20:05.765266 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8867 23:20:05.768271 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8868 23:20:05.771858 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8869 23:20:05.774795 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8870 23:20:05.778236 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8871 23:20:05.784589 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8872 23:20:05.788243 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8873 23:20:05.791393 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8874 23:20:05.794734 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8875 23:20:05.797784 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8876 23:20:05.804517 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8877 23:20:05.807789 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8878 23:20:05.811352 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8879 23:20:05.814451 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8880 23:20:05.821074 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8881 23:20:05.821161 ==
8882 23:20:05.824372 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 23:20:05.827962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 23:20:05.828056 ==
8885 23:20:05.828143 DQS Delay:
8886 23:20:05.830937 DQS0 = 0, DQS1 = 0
8887 23:20:05.831049 DQM Delay:
8888 23:20:05.834540 DQM0 = 137, DQM1 = 132
8889 23:20:05.834654 DQ Delay:
8890 23:20:05.837940 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8891 23:20:05.840937 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =139
8892 23:20:05.844625 DQ8 =115, DQ9 =123, DQ10 =135, DQ11 =127
8893 23:20:05.847563 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =139
8894 23:20:05.847651
8895 23:20:05.847735
8896 23:20:05.847816 ==
8897 23:20:05.850941 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 23:20:05.857595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 23:20:05.857683 ==
8900 23:20:05.857768
8901 23:20:05.857848
8902 23:20:05.857927 TX Vref Scan disable
8903 23:20:05.861496 == TX Byte 0 ==
8904 23:20:05.864833 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8905 23:20:05.871069 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8906 23:20:05.871157 == TX Byte 1 ==
8907 23:20:05.874636 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8908 23:20:05.881120 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8909 23:20:05.881207 ==
8910 23:20:05.884618 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 23:20:05.887709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 23:20:05.887796 ==
8913 23:20:05.901603
8914 23:20:05.904558 TX Vref early break, caculate TX vref
8915 23:20:05.907834 TX Vref=16, minBit 9, minWin=22, winSum=381
8916 23:20:05.911448 TX Vref=18, minBit 8, minWin=22, winSum=387
8917 23:20:05.914656 TX Vref=20, minBit 1, minWin=24, winSum=398
8918 23:20:05.917994 TX Vref=22, minBit 8, minWin=24, winSum=404
8919 23:20:05.921092 TX Vref=24, minBit 13, minWin=24, winSum=416
8920 23:20:05.927982 TX Vref=26, minBit 8, minWin=25, winSum=420
8921 23:20:05.931229 TX Vref=28, minBit 9, minWin=25, winSum=420
8922 23:20:05.934673 TX Vref=30, minBit 10, minWin=24, winSum=416
8923 23:20:05.937658 TX Vref=32, minBit 10, minWin=24, winSum=407
8924 23:20:05.941156 TX Vref=34, minBit 9, minWin=24, winSum=402
8925 23:20:05.944624 TX Vref=36, minBit 0, minWin=23, winSum=393
8926 23:20:05.951335 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 26
8927 23:20:05.951421
8928 23:20:05.954585 Final TX Range 0 Vref 26
8929 23:20:05.954670
8930 23:20:05.954736 ==
8931 23:20:05.958101 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 23:20:05.960920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 23:20:05.961004 ==
8934 23:20:05.961071
8935 23:20:05.964339
8936 23:20:05.964423 TX Vref Scan disable
8937 23:20:05.971391 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8938 23:20:05.971475 == TX Byte 0 ==
8939 23:20:05.974566 u2DelayCellOfst[0]=13 cells (4 PI)
8940 23:20:05.978108 u2DelayCellOfst[1]=6 cells (2 PI)
8941 23:20:05.981154 u2DelayCellOfst[2]=0 cells (0 PI)
8942 23:20:05.984477 u2DelayCellOfst[3]=3 cells (1 PI)
8943 23:20:05.987815 u2DelayCellOfst[4]=6 cells (2 PI)
8944 23:20:05.990822 u2DelayCellOfst[5]=16 cells (5 PI)
8945 23:20:05.994187 u2DelayCellOfst[6]=16 cells (5 PI)
8946 23:20:05.997407 u2DelayCellOfst[7]=3 cells (1 PI)
8947 23:20:06.000696 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8948 23:20:06.004287 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8949 23:20:06.007687 == TX Byte 1 ==
8950 23:20:06.010963 u2DelayCellOfst[8]=0 cells (0 PI)
8951 23:20:06.011047 u2DelayCellOfst[9]=3 cells (1 PI)
8952 23:20:06.014101 u2DelayCellOfst[10]=10 cells (3 PI)
8953 23:20:06.017540 u2DelayCellOfst[11]=3 cells (1 PI)
8954 23:20:06.021099 u2DelayCellOfst[12]=13 cells (4 PI)
8955 23:20:06.024193 u2DelayCellOfst[13]=16 cells (5 PI)
8956 23:20:06.027527 u2DelayCellOfst[14]=20 cells (6 PI)
8957 23:20:06.030942 u2DelayCellOfst[15]=20 cells (6 PI)
8958 23:20:06.034073 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8959 23:20:06.040871 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8960 23:20:06.040957 DramC Write-DBI on
8961 23:20:06.041024 ==
8962 23:20:06.044329 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 23:20:06.050853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 23:20:06.050943 ==
8965 23:20:06.051011
8966 23:20:06.051073
8967 23:20:06.051133 TX Vref Scan disable
8968 23:20:06.054839 == TX Byte 0 ==
8969 23:20:06.058251 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8970 23:20:06.061325 == TX Byte 1 ==
8971 23:20:06.064547 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8972 23:20:06.067721 DramC Write-DBI off
8973 23:20:06.067806
8974 23:20:06.067873 [DATLAT]
8975 23:20:06.067933 Freq=1600, CH1 RK1
8976 23:20:06.067994
8977 23:20:06.071406 DATLAT Default: 0xf
8978 23:20:06.071490 0, 0xFFFF, sum = 0
8979 23:20:06.074312 1, 0xFFFF, sum = 0
8980 23:20:06.077871 2, 0xFFFF, sum = 0
8981 23:20:06.077956 3, 0xFFFF, sum = 0
8982 23:20:06.081244 4, 0xFFFF, sum = 0
8983 23:20:06.081329 5, 0xFFFF, sum = 0
8984 23:20:06.084349 6, 0xFFFF, sum = 0
8985 23:20:06.084435 7, 0xFFFF, sum = 0
8986 23:20:06.087587 8, 0xFFFF, sum = 0
8987 23:20:06.087673 9, 0xFFFF, sum = 0
8988 23:20:06.091285 10, 0xFFFF, sum = 0
8989 23:20:06.091371 11, 0xFFFF, sum = 0
8990 23:20:06.094076 12, 0xFFFF, sum = 0
8991 23:20:06.094161 13, 0xFFFF, sum = 0
8992 23:20:06.097628 14, 0x0, sum = 1
8993 23:20:06.097713 15, 0x0, sum = 2
8994 23:20:06.100829 16, 0x0, sum = 3
8995 23:20:06.100914 17, 0x0, sum = 4
8996 23:20:06.104276 best_step = 15
8997 23:20:06.104360
8998 23:20:06.104426 ==
8999 23:20:06.107344 Dram Type= 6, Freq= 0, CH_1, rank 1
9000 23:20:06.110779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9001 23:20:06.110864 ==
9002 23:20:06.114100 RX Vref Scan: 0
9003 23:20:06.114184
9004 23:20:06.114251 RX Vref 0 -> 0, step: 1
9005 23:20:06.114314
9006 23:20:06.117396 RX Delay 19 -> 252, step: 4
9007 23:20:06.120958 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
9008 23:20:06.127519 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9009 23:20:06.130632 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
9010 23:20:06.134155 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9011 23:20:06.137257 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9012 23:20:06.140848 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9013 23:20:06.144155 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9014 23:20:06.150821 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
9015 23:20:06.153845 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9016 23:20:06.157575 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9017 23:20:06.160900 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9018 23:20:06.164139 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9019 23:20:06.170511 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9020 23:20:06.173733 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9021 23:20:06.177200 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9022 23:20:06.180612 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9023 23:20:06.180714 ==
9024 23:20:06.183802 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 23:20:06.190397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 23:20:06.190484 ==
9027 23:20:06.190551 DQS Delay:
9028 23:20:06.193566 DQS0 = 0, DQS1 = 0
9029 23:20:06.193652 DQM Delay:
9030 23:20:06.193719 DQM0 = 134, DQM1 = 129
9031 23:20:06.196909 DQ Delay:
9032 23:20:06.200257 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =130
9033 23:20:06.203717 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
9034 23:20:06.207057 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9035 23:20:06.210343 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
9036 23:20:06.210430
9037 23:20:06.210514
9038 23:20:06.210595
9039 23:20:06.213914 [DramC_TX_OE_Calibration] TA2
9040 23:20:06.217145 Original DQ_B0 (3 6) =30, OEN = 27
9041 23:20:06.220422 Original DQ_B1 (3 6) =30, OEN = 27
9042 23:20:06.223569 24, 0x0, End_B0=24 End_B1=24
9043 23:20:06.223658 25, 0x0, End_B0=25 End_B1=25
9044 23:20:06.227293 26, 0x0, End_B0=26 End_B1=26
9045 23:20:06.230186 27, 0x0, End_B0=27 End_B1=27
9046 23:20:06.233612 28, 0x0, End_B0=28 End_B1=28
9047 23:20:06.237233 29, 0x0, End_B0=29 End_B1=29
9048 23:20:06.237324 30, 0x0, End_B0=30 End_B1=30
9049 23:20:06.240199 31, 0x5151, End_B0=30 End_B1=30
9050 23:20:06.243817 Byte0 end_step=30 best_step=27
9051 23:20:06.247298 Byte1 end_step=30 best_step=27
9052 23:20:06.250531 Byte0 TX OE(2T, 0.5T) = (3, 3)
9053 23:20:06.253798 Byte1 TX OE(2T, 0.5T) = (3, 3)
9054 23:20:06.253886
9055 23:20:06.253990
9056 23:20:06.260137 [DQSOSCAuto] RK1, (LSB)MR18= 0x1904, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
9057 23:20:06.263629 CH1 RK1: MR19=303, MR18=1904
9058 23:20:06.270290 CH1_RK1: MR19=0x303, MR18=0x1904, DQSOSC=397, MR23=63, INC=23, DEC=15
9059 23:20:06.273393 [RxdqsGatingPostProcess] freq 1600
9060 23:20:06.276804 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9061 23:20:06.280038 best DQS0 dly(2T, 0.5T) = (1, 1)
9062 23:20:06.283324 best DQS1 dly(2T, 0.5T) = (1, 1)
9063 23:20:06.286641 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9064 23:20:06.290094 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9065 23:20:06.293425 best DQS0 dly(2T, 0.5T) = (1, 1)
9066 23:20:06.296753 best DQS1 dly(2T, 0.5T) = (1, 1)
9067 23:20:06.299866 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9068 23:20:06.303412 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9069 23:20:06.306897 Pre-setting of DQS Precalculation
9070 23:20:06.310150 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9071 23:20:06.316807 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9072 23:20:06.326384 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9073 23:20:06.326478
9074 23:20:06.326566
9075 23:20:06.329789 [Calibration Summary] 3200 Mbps
9076 23:20:06.329877 CH 0, Rank 0
9077 23:20:06.333038 SW Impedance : PASS
9078 23:20:06.333126 DUTY Scan : NO K
9079 23:20:06.336279 ZQ Calibration : PASS
9080 23:20:06.336391 Jitter Meter : NO K
9081 23:20:06.340025 CBT Training : PASS
9082 23:20:06.343144 Write leveling : PASS
9083 23:20:06.343231 RX DQS gating : PASS
9084 23:20:06.346494 RX DQ/DQS(RDDQC) : PASS
9085 23:20:06.349689 TX DQ/DQS : PASS
9086 23:20:06.349777 RX DATLAT : PASS
9087 23:20:06.353098 RX DQ/DQS(Engine): PASS
9088 23:20:06.356721 TX OE : PASS
9089 23:20:06.356808 All Pass.
9090 23:20:06.356893
9091 23:20:06.356974 CH 0, Rank 1
9092 23:20:06.359946 SW Impedance : PASS
9093 23:20:06.363169 DUTY Scan : NO K
9094 23:20:06.363256 ZQ Calibration : PASS
9095 23:20:06.366426 Jitter Meter : NO K
9096 23:20:06.369826 CBT Training : PASS
9097 23:20:06.369912 Write leveling : PASS
9098 23:20:06.373085 RX DQS gating : PASS
9099 23:20:06.376294 RX DQ/DQS(RDDQC) : PASS
9100 23:20:06.376380 TX DQ/DQS : PASS
9101 23:20:06.379687 RX DATLAT : PASS
9102 23:20:06.379773 RX DQ/DQS(Engine): PASS
9103 23:20:06.383408 TX OE : PASS
9104 23:20:06.383495 All Pass.
9105 23:20:06.383582
9106 23:20:06.386280 CH 1, Rank 0
9107 23:20:06.386367 SW Impedance : PASS
9108 23:20:06.389679 DUTY Scan : NO K
9109 23:20:06.393332 ZQ Calibration : PASS
9110 23:20:06.393420 Jitter Meter : NO K
9111 23:20:06.396256 CBT Training : PASS
9112 23:20:06.399402 Write leveling : PASS
9113 23:20:06.399488 RX DQS gating : PASS
9114 23:20:06.402654 RX DQ/DQS(RDDQC) : PASS
9115 23:20:06.406106 TX DQ/DQS : PASS
9116 23:20:06.406193 RX DATLAT : PASS
9117 23:20:06.409535 RX DQ/DQS(Engine): PASS
9118 23:20:06.412850 TX OE : PASS
9119 23:20:06.412936 All Pass.
9120 23:20:06.413021
9121 23:20:06.413102 CH 1, Rank 1
9122 23:20:06.416224 SW Impedance : PASS
9123 23:20:06.419549 DUTY Scan : NO K
9124 23:20:06.419636 ZQ Calibration : PASS
9125 23:20:06.422694 Jitter Meter : NO K
9126 23:20:06.426255 CBT Training : PASS
9127 23:20:06.426341 Write leveling : PASS
9128 23:20:06.429611 RX DQS gating : PASS
9129 23:20:06.432794 RX DQ/DQS(RDDQC) : PASS
9130 23:20:06.432883 TX DQ/DQS : PASS
9131 23:20:06.436147 RX DATLAT : PASS
9132 23:20:06.436233 RX DQ/DQS(Engine): PASS
9133 23:20:06.439179 TX OE : PASS
9134 23:20:06.439266 All Pass.
9135 23:20:06.439352
9136 23:20:06.442769 DramC Write-DBI on
9137 23:20:06.446374 PER_BANK_REFRESH: Hybrid Mode
9138 23:20:06.446461 TX_TRACKING: ON
9139 23:20:06.456058 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9140 23:20:06.462399 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9141 23:20:06.472527 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9142 23:20:06.475948 [FAST_K] Save calibration result to emmc
9143 23:20:06.476040 sync common calibartion params.
9144 23:20:06.479053 sync cbt_mode0:1, 1:1
9145 23:20:06.482292 dram_init: ddr_geometry: 2
9146 23:20:06.485802 dram_init: ddr_geometry: 2
9147 23:20:06.485886 dram_init: ddr_geometry: 2
9148 23:20:06.489183 0:dram_rank_size:100000000
9149 23:20:06.492419 1:dram_rank_size:100000000
9150 23:20:06.495841 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9151 23:20:06.499314 DFS_SHUFFLE_HW_MODE: ON
9152 23:20:06.502682 dramc_set_vcore_voltage set vcore to 725000
9153 23:20:06.505910 Read voltage for 1600, 0
9154 23:20:06.505995 Vio18 = 0
9155 23:20:06.509286 Vcore = 725000
9156 23:20:06.509370 Vdram = 0
9157 23:20:06.509438 Vddq = 0
9158 23:20:06.509500 Vmddr = 0
9159 23:20:06.512528 switch to 3200 Mbps bootup
9160 23:20:06.515458 [DramcRunTimeConfig]
9161 23:20:06.515542 PHYPLL
9162 23:20:06.519256 DPM_CONTROL_AFTERK: ON
9163 23:20:06.519340 PER_BANK_REFRESH: ON
9164 23:20:06.522426 REFRESH_OVERHEAD_REDUCTION: ON
9165 23:20:06.525863 CMD_PICG_NEW_MODE: OFF
9166 23:20:06.525948 XRTWTW_NEW_MODE: ON
9167 23:20:06.529249 XRTRTR_NEW_MODE: ON
9168 23:20:06.529333 TX_TRACKING: ON
9169 23:20:06.532407 RDSEL_TRACKING: OFF
9170 23:20:06.532492 DQS Precalculation for DVFS: ON
9171 23:20:06.535444 RX_TRACKING: OFF
9172 23:20:06.535528 HW_GATING DBG: ON
9173 23:20:06.538814 ZQCS_ENABLE_LP4: ON
9174 23:20:06.542179 RX_PICG_NEW_MODE: ON
9175 23:20:06.542263 TX_PICG_NEW_MODE: ON
9176 23:20:06.545639 ENABLE_RX_DCM_DPHY: ON
9177 23:20:06.549117 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9178 23:20:06.549202 DUMMY_READ_FOR_TRACKING: OFF
9179 23:20:06.552395 !!! SPM_CONTROL_AFTERK: OFF
9180 23:20:06.555624 !!! SPM could not control APHY
9181 23:20:06.559105 IMPEDANCE_TRACKING: ON
9182 23:20:06.559189 TEMP_SENSOR: ON
9183 23:20:06.562289 HW_SAVE_FOR_SR: OFF
9184 23:20:06.565506 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9185 23:20:06.568608 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9186 23:20:06.568727 Read ODT Tracking: ON
9187 23:20:06.571919 Refresh Rate DeBounce: ON
9188 23:20:06.575369 DFS_NO_QUEUE_FLUSH: ON
9189 23:20:06.578491 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9190 23:20:06.578574 ENABLE_DFS_RUNTIME_MRW: OFF
9191 23:20:06.581727 DDR_RESERVE_NEW_MODE: ON
9192 23:20:06.585292 MR_CBT_SWITCH_FREQ: ON
9193 23:20:06.585414 =========================
9194 23:20:06.604983 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9195 23:20:06.608583 dram_init: ddr_geometry: 2
9196 23:20:06.626752 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9197 23:20:06.630161 dram_init: dram init end (result: 0)
9198 23:20:06.636616 DRAM-K: Full calibration passed in 24528 msecs
9199 23:20:06.640121 MRC: failed to locate region type 0.
9200 23:20:06.640207 DRAM rank0 size:0x100000000,
9201 23:20:06.643294 DRAM rank1 size=0x100000000
9202 23:20:06.653325 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9203 23:20:06.660040 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9204 23:20:06.666851 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9205 23:20:06.673392 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9206 23:20:06.676436 DRAM rank0 size:0x100000000,
9207 23:20:06.680055 DRAM rank1 size=0x100000000
9208 23:20:06.680139 CBMEM:
9209 23:20:06.683122 IMD: root @ 0xfffff000 254 entries.
9210 23:20:06.686538 IMD: root @ 0xffffec00 62 entries.
9211 23:20:06.689696 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9212 23:20:06.693808 WARNING: RO_VPD is uninitialized or empty.
9213 23:20:06.699771 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9214 23:20:06.706708 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9215 23:20:06.719863 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9216 23:20:06.731133 BS: romstage times (exec / console): total (unknown) / 24022 ms
9217 23:20:06.731233
9218 23:20:06.731301
9219 23:20:06.740793 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9220 23:20:06.744211 ARM64: Exception handlers installed.
9221 23:20:06.747803 ARM64: Testing exception
9222 23:20:06.751231 ARM64: Done test exception
9223 23:20:06.751318 Enumerating buses...
9224 23:20:06.754217 Show all devs... Before device enumeration.
9225 23:20:06.757571 Root Device: enabled 1
9226 23:20:06.760824 CPU_CLUSTER: 0: enabled 1
9227 23:20:06.760910 CPU: 00: enabled 1
9228 23:20:06.764391 Compare with tree...
9229 23:20:06.764476 Root Device: enabled 1
9230 23:20:06.767492 CPU_CLUSTER: 0: enabled 1
9231 23:20:06.770968 CPU: 00: enabled 1
9232 23:20:06.771052 Root Device scanning...
9233 23:20:06.774326 scan_static_bus for Root Device
9234 23:20:06.777561 CPU_CLUSTER: 0 enabled
9235 23:20:06.780920 scan_static_bus for Root Device done
9236 23:20:06.784410 scan_bus: bus Root Device finished in 8 msecs
9237 23:20:06.784494 done
9238 23:20:06.791046 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9239 23:20:06.794033 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9240 23:20:06.801073 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9241 23:20:06.804135 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9242 23:20:06.807337 Allocating resources...
9243 23:20:06.807423 Reading resources...
9244 23:20:06.814466 Root Device read_resources bus 0 link: 0
9245 23:20:06.814552 DRAM rank0 size:0x100000000,
9246 23:20:06.817592 DRAM rank1 size=0x100000000
9247 23:20:06.821110 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9248 23:20:06.824442 CPU: 00 missing read_resources
9249 23:20:06.827423 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9250 23:20:06.834409 Root Device read_resources bus 0 link: 0 done
9251 23:20:06.834500 Done reading resources.
9252 23:20:06.841040 Show resources in subtree (Root Device)...After reading.
9253 23:20:06.843877 Root Device child on link 0 CPU_CLUSTER: 0
9254 23:20:06.847724 CPU_CLUSTER: 0 child on link 0 CPU: 00
9255 23:20:06.857217 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9256 23:20:06.857304 CPU: 00
9257 23:20:06.860582 Root Device assign_resources, bus 0 link: 0
9258 23:20:06.863935 CPU_CLUSTER: 0 missing set_resources
9259 23:20:06.867351 Root Device assign_resources, bus 0 link: 0 done
9260 23:20:06.870676 Done setting resources.
9261 23:20:06.877033 Show resources in subtree (Root Device)...After assigning values.
9262 23:20:06.880629 Root Device child on link 0 CPU_CLUSTER: 0
9263 23:20:06.884087 CPU_CLUSTER: 0 child on link 0 CPU: 00
9264 23:20:06.893774 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9265 23:20:06.893866 CPU: 00
9266 23:20:06.897280 Done allocating resources.
9267 23:20:06.900593 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9268 23:20:06.903673 Enabling resources...
9269 23:20:06.903759 done.
9270 23:20:06.911006 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9271 23:20:06.911094 Initializing devices...
9272 23:20:06.913700 Root Device init
9273 23:20:06.913788 init hardware done!
9274 23:20:06.916969 0x00000018: ctrlr->caps
9275 23:20:06.920464 52.000 MHz: ctrlr->f_max
9276 23:20:06.920577 0.400 MHz: ctrlr->f_min
9277 23:20:06.923763 0x40ff8080: ctrlr->voltages
9278 23:20:06.923849 sclk: 390625
9279 23:20:06.927122 Bus Width = 1
9280 23:20:06.927207 sclk: 390625
9281 23:20:06.927274 Bus Width = 1
9282 23:20:06.930674 Early init status = 3
9283 23:20:06.937056 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9284 23:20:06.940840 in-header: 03 fc 00 00 01 00 00 00
9285 23:20:06.940925 in-data: 00
9286 23:20:06.946986 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9287 23:20:06.951789 in-header: 03 fd 00 00 00 00 00 00
9288 23:20:06.955040 in-data:
9289 23:20:06.958043 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9290 23:20:06.962673 in-header: 03 fc 00 00 01 00 00 00
9291 23:20:06.965657 in-data: 00
9292 23:20:06.969163 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9293 23:20:06.974549 in-header: 03 fd 00 00 00 00 00 00
9294 23:20:06.977732 in-data:
9295 23:20:06.981054 [SSUSB] Setting up USB HOST controller...
9296 23:20:06.984484 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9297 23:20:06.987950 [SSUSB] phy power-on done.
9298 23:20:06.991218 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9299 23:20:06.998153 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9300 23:20:07.001029 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9301 23:20:07.007830 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9302 23:20:07.014312 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9303 23:20:07.020985 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9304 23:20:07.028005 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9305 23:20:07.034657 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9306 23:20:07.038082 SPM: binary array size = 0x9dc
9307 23:20:07.041471 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9308 23:20:07.047799 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9309 23:20:07.054518 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9310 23:20:07.057724 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9311 23:20:07.064580 configure_display: Starting display init
9312 23:20:07.098037 anx7625_power_on_init: Init interface.
9313 23:20:07.101325 anx7625_disable_pd_protocol: Disabled PD feature.
9314 23:20:07.104612 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9315 23:20:07.132633 anx7625_start_dp_work: Secure OCM version=00
9316 23:20:07.135960 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9317 23:20:07.150538 sp_tx_get_edid_block: EDID Block = 1
9318 23:20:07.253066 Extracted contents:
9319 23:20:07.256130 header: 00 ff ff ff ff ff ff 00
9320 23:20:07.259665 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9321 23:20:07.262965 version: 01 04
9322 23:20:07.266026 basic params: 95 1f 11 78 0a
9323 23:20:07.269583 chroma info: 76 90 94 55 54 90 27 21 50 54
9324 23:20:07.272915 established: 00 00 00
9325 23:20:07.279502 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9326 23:20:07.282777 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9327 23:20:07.289281 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9328 23:20:07.296109 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9329 23:20:07.302598 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9330 23:20:07.305961 extensions: 00
9331 23:20:07.306046 checksum: fb
9332 23:20:07.306111
9333 23:20:07.309325 Manufacturer: IVO Model 57d Serial Number 0
9334 23:20:07.312753 Made week 0 of 2020
9335 23:20:07.312835 EDID version: 1.4
9336 23:20:07.315793 Digital display
9337 23:20:07.319199 6 bits per primary color channel
9338 23:20:07.319283 DisplayPort interface
9339 23:20:07.322353 Maximum image size: 31 cm x 17 cm
9340 23:20:07.325528 Gamma: 220%
9341 23:20:07.325610 Check DPMS levels
9342 23:20:07.329114 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9343 23:20:07.335577 First detailed timing is preferred timing
9344 23:20:07.335673 Established timings supported:
9345 23:20:07.338916 Standard timings supported:
9346 23:20:07.342087 Detailed timings
9347 23:20:07.345375 Hex of detail: 383680a07038204018303c0035ae10000019
9348 23:20:07.351927 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9349 23:20:07.355229 0780 0798 07c8 0820 hborder 0
9350 23:20:07.358680 0438 043b 0447 0458 vborder 0
9351 23:20:07.361977 -hsync -vsync
9352 23:20:07.362060 Did detailed timing
9353 23:20:07.368733 Hex of detail: 000000000000000000000000000000000000
9354 23:20:07.371589 Manufacturer-specified data, tag 0
9355 23:20:07.375057 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9356 23:20:07.378248 ASCII string: InfoVision
9357 23:20:07.381670 Hex of detail: 000000fe00523134304e574635205248200a
9358 23:20:07.385226 ASCII string: R140NWF5 RH
9359 23:20:07.385307 Checksum
9360 23:20:07.388537 Checksum: 0xfb (valid)
9361 23:20:07.391483 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9362 23:20:07.395091 DSI data_rate: 832800000 bps
9363 23:20:07.401733 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9364 23:20:07.404936 anx7625_parse_edid: pixelclock(138800).
9365 23:20:07.408208 hactive(1920), hsync(48), hfp(24), hbp(88)
9366 23:20:07.411600 vactive(1080), vsync(12), vfp(3), vbp(17)
9367 23:20:07.415070 anx7625_dsi_config: config dsi.
9368 23:20:07.421299 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9369 23:20:07.435265 anx7625_dsi_config: success to config DSI
9370 23:20:07.438162 anx7625_dp_start: MIPI phy setup OK.
9371 23:20:07.441689 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9372 23:20:07.445194 mtk_ddp_mode_set invalid vrefresh 60
9373 23:20:07.448264 main_disp_path_setup
9374 23:20:07.448346 ovl_layer_smi_id_en
9375 23:20:07.451521 ovl_layer_smi_id_en
9376 23:20:07.451603 ccorr_config
9377 23:20:07.451668 aal_config
9378 23:20:07.454980 gamma_config
9379 23:20:07.455064 postmask_config
9380 23:20:07.458148 dither_config
9381 23:20:07.461909 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9382 23:20:07.468109 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9383 23:20:07.471459 Root Device init finished in 555 msecs
9384 23:20:07.474875 CPU_CLUSTER: 0 init
9385 23:20:07.481336 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9386 23:20:07.484758 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9387 23:20:07.488094 APU_MBOX 0x190000b0 = 0x10001
9388 23:20:07.491574 APU_MBOX 0x190001b0 = 0x10001
9389 23:20:07.494538 APU_MBOX 0x190005b0 = 0x10001
9390 23:20:07.497945 APU_MBOX 0x190006b0 = 0x10001
9391 23:20:07.501321 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9392 23:20:07.514065 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9393 23:20:07.526455 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9394 23:20:07.533365 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9395 23:20:07.544971 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9396 23:20:07.553838 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9397 23:20:07.557257 CPU_CLUSTER: 0 init finished in 81 msecs
9398 23:20:07.560572 Devices initialized
9399 23:20:07.563646 Show all devs... After init.
9400 23:20:07.563732 Root Device: enabled 1
9401 23:20:07.567346 CPU_CLUSTER: 0: enabled 1
9402 23:20:07.570163 CPU: 00: enabled 1
9403 23:20:07.573671 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9404 23:20:07.576925 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9405 23:20:07.580424 ELOG: NV offset 0x57f000 size 0x1000
9406 23:20:07.587137 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9407 23:20:07.593544 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9408 23:20:07.596778 ELOG: Event(17) added with size 13 at 2024-04-03 23:19:06 UTC
9409 23:20:07.603403 out: cmd=0x121: 03 db 21 01 00 00 00 00
9410 23:20:07.606597 in-header: 03 14 00 00 2c 00 00 00
9411 23:20:07.616877 in-data: 4b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9412 23:20:07.623690 ELOG: Event(A1) added with size 10 at 2024-04-03 23:19:06 UTC
9413 23:20:07.629685 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9414 23:20:07.636381 ELOG: Event(A0) added with size 9 at 2024-04-03 23:19:06 UTC
9415 23:20:07.639806 elog_add_boot_reason: Logged dev mode boot
9416 23:20:07.646537 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9417 23:20:07.646624 Finalize devices...
9418 23:20:07.649467 Devices finalized
9419 23:20:07.653214 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9420 23:20:07.656325 Writing coreboot table at 0xffe64000
9421 23:20:07.659682 0. 000000000010a000-0000000000113fff: RAMSTAGE
9422 23:20:07.665975 1. 0000000040000000-00000000400fffff: RAM
9423 23:20:07.670018 2. 0000000040100000-000000004032afff: RAMSTAGE
9424 23:20:07.673417 3. 000000004032b000-00000000545fffff: RAM
9425 23:20:07.676358 4. 0000000054600000-000000005465ffff: BL31
9426 23:20:07.679520 5. 0000000054660000-00000000ffe63fff: RAM
9427 23:20:07.685928 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9428 23:20:07.689277 7. 0000000100000000-000000023fffffff: RAM
9429 23:20:07.692557 Passing 5 GPIOs to payload:
9430 23:20:07.696038 NAME | PORT | POLARITY | VALUE
9431 23:20:07.702564 EC in RW | 0x000000aa | low | undefined
9432 23:20:07.706005 EC interrupt | 0x00000005 | low | undefined
9433 23:20:07.709407 TPM interrupt | 0x000000ab | high | undefined
9434 23:20:07.716265 SD card detect | 0x00000011 | high | undefined
9435 23:20:07.719239 speaker enable | 0x00000093 | high | undefined
9436 23:20:07.722835 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9437 23:20:07.725700 in-header: 03 f9 00 00 02 00 00 00
9438 23:20:07.729412 in-data: 02 00
9439 23:20:07.732948 ADC[4]: Raw value=901032 ID=7
9440 23:20:07.733036 ADC[3]: Raw value=213179 ID=1
9441 23:20:07.735799 RAM Code: 0x71
9442 23:20:07.739138 ADC[6]: Raw value=74502 ID=0
9443 23:20:07.739222 ADC[5]: Raw value=212072 ID=1
9444 23:20:07.742532 SKU Code: 0x1
9445 23:20:07.745921 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7531
9446 23:20:07.749085 coreboot table: 964 bytes.
9447 23:20:07.752529 IMD ROOT 0. 0xfffff000 0x00001000
9448 23:20:07.755667 IMD SMALL 1. 0xffffe000 0x00001000
9449 23:20:07.759084 RO MCACHE 2. 0xffffc000 0x00001104
9450 23:20:07.762199 CONSOLE 3. 0xfff7c000 0x00080000
9451 23:20:07.765776 FMAP 4. 0xfff7b000 0x00000452
9452 23:20:07.769469 TIME STAMP 5. 0xfff7a000 0x00000910
9453 23:20:07.772188 VBOOT WORK 6. 0xfff66000 0x00014000
9454 23:20:07.775539 RAMOOPS 7. 0xffe66000 0x00100000
9455 23:20:07.778978 COREBOOT 8. 0xffe64000 0x00002000
9456 23:20:07.782501 IMD small region:
9457 23:20:07.786027 IMD ROOT 0. 0xffffec00 0x00000400
9458 23:20:07.789199 VPD 1. 0xffffeb80 0x0000006c
9459 23:20:07.792488 MMC STATUS 2. 0xffffeb60 0x00000004
9460 23:20:07.795601 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9461 23:20:07.798954 Probing TPM: done!
9462 23:20:07.802303 Connected to device vid:did:rid of 1ae0:0028:00
9463 23:20:07.812593 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9464 23:20:07.816099 Initialized TPM device CR50 revision 0
9465 23:20:07.819825 Checking cr50 for pending updates
9466 23:20:07.823610 Reading cr50 TPM mode
9467 23:20:07.832161 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9468 23:20:07.838909 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9469 23:20:07.878852 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9470 23:20:07.882014 Checking segment from ROM address 0x40100000
9471 23:20:07.885568 Checking segment from ROM address 0x4010001c
9472 23:20:07.892395 Loading segment from ROM address 0x40100000
9473 23:20:07.892481 code (compression=0)
9474 23:20:07.901956 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9475 23:20:07.908770 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9476 23:20:07.908856 it's not compressed!
9477 23:20:07.915623 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9478 23:20:07.918937 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9479 23:20:07.939423 Loading segment from ROM address 0x4010001c
9480 23:20:07.939550 Entry Point 0x80000000
9481 23:20:07.942887 Loaded segments
9482 23:20:07.946407 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9483 23:20:07.953089 Jumping to boot code at 0x80000000(0xffe64000)
9484 23:20:07.959599 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9485 23:20:07.966037 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9486 23:20:07.974208 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9487 23:20:07.977513 Checking segment from ROM address 0x40100000
9488 23:20:07.980931 Checking segment from ROM address 0x4010001c
9489 23:20:07.987225 Loading segment from ROM address 0x40100000
9490 23:20:07.987668 code (compression=1)
9491 23:20:07.994257 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9492 23:20:08.003891 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9493 23:20:08.004283 using LZMA
9494 23:20:08.012458 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9495 23:20:08.019065 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9496 23:20:08.022006 Loading segment from ROM address 0x4010001c
9497 23:20:08.025420 Entry Point 0x54601000
9498 23:20:08.025801 Loaded segments
9499 23:20:08.028613 NOTICE: MT8192 bl31_setup
9500 23:20:08.035807 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9501 23:20:08.039277 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9502 23:20:08.042466 WARNING: region 0:
9503 23:20:08.045760 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 23:20:08.046170 WARNING: region 1:
9505 23:20:08.052632 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9506 23:20:08.056087 WARNING: region 2:
9507 23:20:08.059439 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9508 23:20:08.062654 WARNING: region 3:
9509 23:20:08.065977 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9510 23:20:08.069230 WARNING: region 4:
9511 23:20:08.075660 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9512 23:20:08.076006 WARNING: region 5:
9513 23:20:08.079122 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 23:20:08.082534 WARNING: region 6:
9515 23:20:08.085682 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9516 23:20:08.085862 WARNING: region 7:
9517 23:20:08.092473 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 23:20:08.099434 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9519 23:20:08.103135 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9520 23:20:08.105678 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9521 23:20:08.112374 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9522 23:20:08.115663 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9523 23:20:08.119119 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9524 23:20:08.125779 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9525 23:20:08.129282 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9526 23:20:08.132403 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9527 23:20:08.139187 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9528 23:20:08.142571 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9529 23:20:08.149108 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9530 23:20:08.152607 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9531 23:20:08.156030 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9532 23:20:08.162539 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9533 23:20:08.165823 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9534 23:20:08.169033 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9535 23:20:08.175984 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9536 23:20:08.179234 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9537 23:20:08.186146 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9538 23:20:08.189392 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9539 23:20:08.192637 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9540 23:20:08.199412 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9541 23:20:08.202664 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9542 23:20:08.209033 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9543 23:20:08.212442 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9544 23:20:08.216147 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9545 23:20:08.222487 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9546 23:20:08.225878 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9547 23:20:08.229098 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9548 23:20:08.235570 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9549 23:20:08.239246 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9550 23:20:08.245682 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9551 23:20:08.249248 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9552 23:20:08.252377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9553 23:20:08.255795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9554 23:20:08.262377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9555 23:20:08.265799 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9556 23:20:08.268831 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9557 23:20:08.272407 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9558 23:20:08.275647 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9559 23:20:08.282058 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9560 23:20:08.285751 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9561 23:20:08.289245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9562 23:20:08.295946 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9563 23:20:08.299161 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9564 23:20:08.302201 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9565 23:20:08.305757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9566 23:20:08.312233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9567 23:20:08.315739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9568 23:20:08.322207 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9569 23:20:08.325657 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9570 23:20:08.328794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9571 23:20:08.335490 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9572 23:20:08.339178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9573 23:20:08.345775 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9574 23:20:08.349072 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9575 23:20:08.355614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9576 23:20:08.359047 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9577 23:20:08.362384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9578 23:20:08.369012 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9579 23:20:08.372414 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9580 23:20:08.379111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9581 23:20:08.381987 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9582 23:20:08.389223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9583 23:20:08.392524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9584 23:20:08.395523 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9585 23:20:08.402823 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9586 23:20:08.406144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9587 23:20:08.412158 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9588 23:20:08.415809 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9589 23:20:08.422365 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9590 23:20:08.425653 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9591 23:20:08.429130 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9592 23:20:08.436022 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9593 23:20:08.439412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9594 23:20:08.446173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9595 23:20:08.449656 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9596 23:20:08.455811 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9597 23:20:08.459412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9598 23:20:08.463097 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9599 23:20:08.469071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9600 23:20:08.473003 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9601 23:20:08.479478 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9602 23:20:08.483020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9603 23:20:08.489582 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9604 23:20:08.493017 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9605 23:20:08.496230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9606 23:20:08.502934 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9607 23:20:08.506176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9608 23:20:08.512582 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9609 23:20:08.515848 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9610 23:20:08.522493 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9611 23:20:08.526070 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9612 23:20:08.529498 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9613 23:20:08.536391 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9614 23:20:08.539892 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9615 23:20:08.543255 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9616 23:20:08.549610 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9617 23:20:08.553557 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9618 23:20:08.556393 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9619 23:20:08.559713 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9620 23:20:08.566561 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9621 23:20:08.569844 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9622 23:20:08.576631 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9623 23:20:08.580175 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9624 23:20:08.583711 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9625 23:20:08.590299 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9626 23:20:08.593471 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9627 23:20:08.600238 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9628 23:20:08.603250 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9629 23:20:08.606694 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9630 23:20:08.613200 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9631 23:20:08.616964 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9632 23:20:08.623446 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9633 23:20:08.626721 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9634 23:20:08.630074 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9635 23:20:08.636332 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9636 23:20:08.640025 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9637 23:20:08.643116 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9638 23:20:08.646553 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9639 23:20:08.653217 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9640 23:20:08.656747 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9641 23:20:08.659837 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9642 23:20:08.663245 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9643 23:20:08.670159 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9644 23:20:08.673578 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9645 23:20:08.680103 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9646 23:20:08.683361 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9647 23:20:08.686983 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9648 23:20:08.693759 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9649 23:20:08.696989 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9650 23:20:08.703427 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9651 23:20:08.706949 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9652 23:20:08.710302 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9653 23:20:08.717168 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9654 23:20:08.720312 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9655 23:20:08.723654 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9656 23:20:08.729988 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9657 23:20:08.733494 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9658 23:20:08.740106 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9659 23:20:08.743244 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9660 23:20:08.746733 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9661 23:20:08.754016 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9662 23:20:08.756884 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9663 23:20:08.763493 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9664 23:20:08.766663 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9665 23:20:08.770101 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9666 23:20:08.776854 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9667 23:20:08.779950 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9668 23:20:08.786977 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9669 23:20:08.790206 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9670 23:20:08.793839 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9671 23:20:08.800128 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9672 23:20:08.803323 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9673 23:20:08.806863 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9674 23:20:08.813312 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9675 23:20:08.816511 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9676 23:20:08.819826 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9677 23:20:08.826474 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9678 23:20:08.830355 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9679 23:20:08.836995 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9680 23:20:08.840201 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9681 23:20:08.846763 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9682 23:20:08.849994 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9683 23:20:08.853312 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9684 23:20:08.859758 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9685 23:20:08.863256 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9686 23:20:08.866956 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9687 23:20:08.873495 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9688 23:20:08.876823 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9689 23:20:08.884087 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9690 23:20:08.887025 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9691 23:20:08.890254 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9692 23:20:08.896759 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9693 23:20:08.900253 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9694 23:20:08.906539 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9695 23:20:08.909663 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9696 23:20:08.913119 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9697 23:20:08.920101 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9698 23:20:08.922942 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9699 23:20:08.929510 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9700 23:20:08.932692 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9701 23:20:08.936099 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9702 23:20:08.942663 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9703 23:20:08.946343 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9704 23:20:08.949287 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9705 23:20:08.956527 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9706 23:20:08.959494 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9707 23:20:08.966058 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9708 23:20:08.969231 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9709 23:20:08.976473 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9710 23:20:08.979373 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9711 23:20:08.983081 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9712 23:20:08.989596 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9713 23:20:08.992778 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9714 23:20:08.999232 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9715 23:20:09.002791 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9716 23:20:09.009258 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9717 23:20:09.012312 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9718 23:20:09.015719 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9719 23:20:09.022113 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9720 23:20:09.025534 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9721 23:20:09.032061 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9722 23:20:09.035498 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9723 23:20:09.042232 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9724 23:20:09.045255 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9725 23:20:09.048805 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9726 23:20:09.055359 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9727 23:20:09.058592 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9728 23:20:09.065374 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9729 23:20:09.068685 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9730 23:20:09.071899 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9731 23:20:09.078702 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9732 23:20:09.082091 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9733 23:20:09.089017 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9734 23:20:09.091874 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9735 23:20:09.095450 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9736 23:20:09.101916 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9737 23:20:09.104893 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9738 23:20:09.111905 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9739 23:20:09.114963 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9740 23:20:09.121709 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9741 23:20:09.125012 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9742 23:20:09.128141 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9743 23:20:09.134877 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9744 23:20:09.138130 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9745 23:20:09.144838 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9746 23:20:09.148037 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9747 23:20:09.151285 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9748 23:20:09.154689 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9749 23:20:09.161264 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9750 23:20:09.164614 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9751 23:20:09.167751 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9752 23:20:09.174283 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9753 23:20:09.177988 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9754 23:20:09.181667 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9755 23:20:09.187806 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9756 23:20:09.190810 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9757 23:20:09.194098 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9758 23:20:09.200923 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9759 23:20:09.203923 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9760 23:20:09.211159 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9761 23:20:09.214696 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9762 23:20:09.217909 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9763 23:20:09.224734 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9764 23:20:09.228319 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9765 23:20:09.231060 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9766 23:20:09.237604 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9767 23:20:09.241170 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9768 23:20:09.247400 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9769 23:20:09.250902 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9770 23:20:09.254104 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9771 23:20:09.260640 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9772 23:20:09.264171 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9773 23:20:09.267604 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9774 23:20:09.273944 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9775 23:20:09.277167 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9776 23:20:09.280751 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9777 23:20:09.287006 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9778 23:20:09.290620 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9779 23:20:09.296869 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9780 23:20:09.300561 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9781 23:20:09.303694 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9782 23:20:09.310128 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9783 23:20:09.313628 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9784 23:20:09.316634 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9785 23:20:09.323370 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9786 23:20:09.326901 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9787 23:20:09.329799 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9788 23:20:09.336829 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9789 23:20:09.339886 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9790 23:20:09.343403 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9791 23:20:09.346935 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9792 23:20:09.349937 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9793 23:20:09.356422 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9794 23:20:09.360222 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9795 23:20:09.363122 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9796 23:20:09.366754 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9797 23:20:09.373157 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9798 23:20:09.376796 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9799 23:20:09.379891 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9800 23:20:09.386646 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9801 23:20:09.389832 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9802 23:20:09.396327 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9803 23:20:09.399993 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9804 23:20:09.402947 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9805 23:20:09.409724 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9806 23:20:09.412863 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9807 23:20:09.419678 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9808 23:20:09.423053 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9809 23:20:09.426074 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9810 23:20:09.432616 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9811 23:20:09.436208 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9812 23:20:09.442665 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9813 23:20:09.446218 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9814 23:20:09.452565 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9815 23:20:09.456081 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9816 23:20:09.459054 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9817 23:20:09.465743 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9818 23:20:09.469196 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9819 23:20:09.476319 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9820 23:20:09.479194 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9821 23:20:09.482634 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9822 23:20:09.489498 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9823 23:20:09.492694 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9824 23:20:09.499463 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9825 23:20:09.502865 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9826 23:20:09.506141 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9827 23:20:09.512378 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9828 23:20:09.516277 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9829 23:20:09.522477 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9830 23:20:09.526491 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9831 23:20:09.529151 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9832 23:20:09.536068 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9833 23:20:09.539003 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9834 23:20:09.545948 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9835 23:20:09.549514 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9836 23:20:09.552351 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9837 23:20:09.559415 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9838 23:20:09.562322 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9839 23:20:09.569160 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9840 23:20:09.572236 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9841 23:20:09.575778 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9842 23:20:09.582574 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9843 23:20:09.585988 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9844 23:20:09.592301 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9845 23:20:09.595561 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9846 23:20:09.602689 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9847 23:20:09.605837 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9848 23:20:09.609208 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9849 23:20:09.615476 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9850 23:20:09.619057 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9851 23:20:09.625926 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9852 23:20:09.629101 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9853 23:20:09.635634 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9854 23:20:09.638472 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9855 23:20:09.642245 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9856 23:20:09.648835 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9857 23:20:09.652417 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9858 23:20:09.659298 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9859 23:20:09.662300 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9860 23:20:09.665014 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9861 23:20:09.671858 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9862 23:20:09.675466 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9863 23:20:09.682090 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9864 23:20:09.685157 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9865 23:20:09.688619 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9866 23:20:09.695146 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9867 23:20:09.698616 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9868 23:20:09.705748 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9869 23:20:09.708283 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9870 23:20:09.714954 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9871 23:20:09.718445 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9872 23:20:09.721583 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9873 23:20:09.727583 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9874 23:20:09.730966 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9875 23:20:09.737538 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9876 23:20:09.740818 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9877 23:20:09.747819 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9878 23:20:09.751233 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9879 23:20:09.754713 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9880 23:20:09.761191 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9881 23:20:09.764116 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9882 23:20:09.771155 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9883 23:20:09.774151 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9884 23:20:09.780925 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9885 23:20:09.784383 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9886 23:20:09.790794 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9887 23:20:09.794232 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9888 23:20:09.797301 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9889 23:20:09.804154 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9890 23:20:09.807290 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9891 23:20:09.814031 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9892 23:20:09.817523 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9893 23:20:09.823976 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9894 23:20:09.827311 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9895 23:20:09.830546 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9896 23:20:09.837379 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9897 23:20:09.840664 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9898 23:20:09.847209 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9899 23:20:09.850567 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9900 23:20:09.857121 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9901 23:20:09.860592 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9902 23:20:09.863566 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9903 23:20:09.870556 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9904 23:20:09.873598 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9905 23:20:09.880500 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9906 23:20:09.883910 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9907 23:20:09.890281 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9908 23:20:09.893697 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9909 23:20:09.900151 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9910 23:20:09.903660 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9911 23:20:09.907165 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9912 23:20:09.913661 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9913 23:20:09.916594 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9914 23:20:09.923366 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9915 23:20:09.926599 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9916 23:20:09.933357 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9917 23:20:09.936970 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9918 23:20:09.940253 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9919 23:20:09.946539 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9920 23:20:09.950143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9921 23:20:09.953746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9922 23:20:09.960293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9923 23:20:09.963360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9924 23:20:09.969709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9925 23:20:09.973410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9926 23:20:09.979648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9927 23:20:09.983189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9928 23:20:09.990065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9929 23:20:09.993184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9930 23:20:09.999631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9931 23:20:10.003166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9932 23:20:10.009785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9933 23:20:10.012654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9934 23:20:10.019652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9935 23:20:10.022639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9936 23:20:10.029367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9937 23:20:10.032786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9938 23:20:10.039498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9939 23:20:10.042932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9940 23:20:10.049484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9941 23:20:10.052514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9942 23:20:10.059399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9943 23:20:10.062796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9944 23:20:10.069190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9945 23:20:10.072897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9946 23:20:10.079376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9947 23:20:10.082898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9948 23:20:10.089343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9949 23:20:10.092607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9950 23:20:10.099194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9951 23:20:10.102769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9952 23:20:10.105697 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9953 23:20:10.109221 INFO: [APUAPC] vio 0
9954 23:20:10.115767 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9955 23:20:10.119241 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9956 23:20:10.122291 INFO: [APUAPC] D0_APC_0: 0x400510
9957 23:20:10.125667 INFO: [APUAPC] D0_APC_1: 0x0
9958 23:20:10.129132 INFO: [APUAPC] D0_APC_2: 0x1540
9959 23:20:10.132457 INFO: [APUAPC] D0_APC_3: 0x0
9960 23:20:10.136024 INFO: [APUAPC] D1_APC_0: 0xffffffff
9961 23:20:10.139270 INFO: [APUAPC] D1_APC_1: 0xffffffff
9962 23:20:10.142714 INFO: [APUAPC] D1_APC_2: 0x3fffff
9963 23:20:10.145943 INFO: [APUAPC] D1_APC_3: 0x0
9964 23:20:10.149565 INFO: [APUAPC] D2_APC_0: 0xffffffff
9965 23:20:10.152527 INFO: [APUAPC] D2_APC_1: 0xffffffff
9966 23:20:10.156023 INFO: [APUAPC] D2_APC_2: 0x3fffff
9967 23:20:10.159033 INFO: [APUAPC] D2_APC_3: 0x0
9968 23:20:10.162478 INFO: [APUAPC] D3_APC_0: 0xffffffff
9969 23:20:10.165783 INFO: [APUAPC] D3_APC_1: 0xffffffff
9970 23:20:10.169127 INFO: [APUAPC] D3_APC_2: 0x3fffff
9971 23:20:10.169210 INFO: [APUAPC] D3_APC_3: 0x0
9972 23:20:10.172344 INFO: [APUAPC] D4_APC_0: 0xffffffff
9973 23:20:10.178979 INFO: [APUAPC] D4_APC_1: 0xffffffff
9974 23:20:10.182181 INFO: [APUAPC] D4_APC_2: 0x3fffff
9975 23:20:10.182264 INFO: [APUAPC] D4_APC_3: 0x0
9976 23:20:10.185528 INFO: [APUAPC] D5_APC_0: 0xffffffff
9977 23:20:10.188579 INFO: [APUAPC] D5_APC_1: 0xffffffff
9978 23:20:10.192052 INFO: [APUAPC] D5_APC_2: 0x3fffff
9979 23:20:10.195306 INFO: [APUAPC] D5_APC_3: 0x0
9980 23:20:10.198851 INFO: [APUAPC] D6_APC_0: 0xffffffff
9981 23:20:10.201786 INFO: [APUAPC] D6_APC_1: 0xffffffff
9982 23:20:10.205268 INFO: [APUAPC] D6_APC_2: 0x3fffff
9983 23:20:10.208649 INFO: [APUAPC] D6_APC_3: 0x0
9984 23:20:10.211690 INFO: [APUAPC] D7_APC_0: 0xffffffff
9985 23:20:10.215110 INFO: [APUAPC] D7_APC_1: 0xffffffff
9986 23:20:10.218642 INFO: [APUAPC] D7_APC_2: 0x3fffff
9987 23:20:10.222107 INFO: [APUAPC] D7_APC_3: 0x0
9988 23:20:10.225219 INFO: [APUAPC] D8_APC_0: 0xffffffff
9989 23:20:10.228627 INFO: [APUAPC] D8_APC_1: 0xffffffff
9990 23:20:10.231723 INFO: [APUAPC] D8_APC_2: 0x3fffff
9991 23:20:10.235054 INFO: [APUAPC] D8_APC_3: 0x0
9992 23:20:10.238558 INFO: [APUAPC] D9_APC_0: 0xffffffff
9993 23:20:10.241556 INFO: [APUAPC] D9_APC_1: 0xffffffff
9994 23:20:10.245485 INFO: [APUAPC] D9_APC_2: 0x3fffff
9995 23:20:10.248354 INFO: [APUAPC] D9_APC_3: 0x0
9996 23:20:10.251903 INFO: [APUAPC] D10_APC_0: 0xffffffff
9997 23:20:10.254909 INFO: [APUAPC] D10_APC_1: 0xffffffff
9998 23:20:10.258187 INFO: [APUAPC] D10_APC_2: 0x3fffff
9999 23:20:10.261571 INFO: [APUAPC] D10_APC_3: 0x0
10000 23:20:10.265035 INFO: [APUAPC] D11_APC_0: 0xffffffff
10001 23:20:10.268124 INFO: [APUAPC] D11_APC_1: 0xffffffff
10002 23:20:10.271717 INFO: [APUAPC] D11_APC_2: 0x3fffff
10003 23:20:10.275235 INFO: [APUAPC] D11_APC_3: 0x0
10004 23:20:10.278091 INFO: [APUAPC] D12_APC_0: 0xffffffff
10005 23:20:10.281655 INFO: [APUAPC] D12_APC_1: 0xffffffff
10006 23:20:10.284693 INFO: [APUAPC] D12_APC_2: 0x3fffff
10007 23:20:10.288199 INFO: [APUAPC] D12_APC_3: 0x0
10008 23:20:10.291672 INFO: [APUAPC] D13_APC_0: 0xffffffff
10009 23:20:10.294704 INFO: [APUAPC] D13_APC_1: 0xffffffff
10010 23:20:10.297950 INFO: [APUAPC] D13_APC_2: 0x3fffff
10011 23:20:10.301477 INFO: [APUAPC] D13_APC_3: 0x0
10012 23:20:10.305008 INFO: [APUAPC] D14_APC_0: 0xffffffff
10013 23:20:10.308010 INFO: [APUAPC] D14_APC_1: 0xffffffff
10014 23:20:10.311424 INFO: [APUAPC] D14_APC_2: 0x3fffff
10015 23:20:10.314398 INFO: [APUAPC] D14_APC_3: 0x0
10016 23:20:10.317874 INFO: [APUAPC] D15_APC_0: 0xffffffff
10017 23:20:10.321480 INFO: [APUAPC] D15_APC_1: 0xffffffff
10018 23:20:10.324335 INFO: [APUAPC] D15_APC_2: 0x3fffff
10019 23:20:10.327869 INFO: [APUAPC] D15_APC_3: 0x0
10020 23:20:10.331356 INFO: [APUAPC] APC_CON: 0x4
10021 23:20:10.334855 INFO: [NOCDAPC] D0_APC_0: 0x0
10022 23:20:10.338058 INFO: [NOCDAPC] D0_APC_1: 0x0
10023 23:20:10.341023 INFO: [NOCDAPC] D1_APC_0: 0x0
10024 23:20:10.344497 INFO: [NOCDAPC] D1_APC_1: 0xfff
10025 23:20:10.344606 INFO: [NOCDAPC] D2_APC_0: 0x0
10026 23:20:10.347908 INFO: [NOCDAPC] D2_APC_1: 0xfff
10027 23:20:10.350765 INFO: [NOCDAPC] D3_APC_0: 0x0
10028 23:20:10.354282 INFO: [NOCDAPC] D3_APC_1: 0xfff
10029 23:20:10.357512 INFO: [NOCDAPC] D4_APC_0: 0x0
10030 23:20:10.361242 INFO: [NOCDAPC] D4_APC_1: 0xfff
10031 23:20:10.364573 INFO: [NOCDAPC] D5_APC_0: 0x0
10032 23:20:10.367431 INFO: [NOCDAPC] D5_APC_1: 0xfff
10033 23:20:10.371194 INFO: [NOCDAPC] D6_APC_0: 0x0
10034 23:20:10.374152 INFO: [NOCDAPC] D6_APC_1: 0xfff
10035 23:20:10.377566 INFO: [NOCDAPC] D7_APC_0: 0x0
10036 23:20:10.380729 INFO: [NOCDAPC] D7_APC_1: 0xfff
10037 23:20:10.380824 INFO: [NOCDAPC] D8_APC_0: 0x0
10038 23:20:10.384076 INFO: [NOCDAPC] D8_APC_1: 0xfff
10039 23:20:10.387577 INFO: [NOCDAPC] D9_APC_0: 0x0
10040 23:20:10.390702 INFO: [NOCDAPC] D9_APC_1: 0xfff
10041 23:20:10.394032 INFO: [NOCDAPC] D10_APC_0: 0x0
10042 23:20:10.397695 INFO: [NOCDAPC] D10_APC_1: 0xfff
10043 23:20:10.400583 INFO: [NOCDAPC] D11_APC_0: 0x0
10044 23:20:10.403842 INFO: [NOCDAPC] D11_APC_1: 0xfff
10045 23:20:10.407364 INFO: [NOCDAPC] D12_APC_0: 0x0
10046 23:20:10.410966 INFO: [NOCDAPC] D12_APC_1: 0xfff
10047 23:20:10.413849 INFO: [NOCDAPC] D13_APC_0: 0x0
10048 23:20:10.417314 INFO: [NOCDAPC] D13_APC_1: 0xfff
10049 23:20:10.420361 INFO: [NOCDAPC] D14_APC_0: 0x0
10050 23:20:10.423842 INFO: [NOCDAPC] D14_APC_1: 0xfff
10051 23:20:10.423925 INFO: [NOCDAPC] D15_APC_0: 0x0
10052 23:20:10.427323 INFO: [NOCDAPC] D15_APC_1: 0xfff
10053 23:20:10.430295 INFO: [NOCDAPC] APC_CON: 0x4
10054 23:20:10.433738 INFO: [APUAPC] set_apusys_apc done
10055 23:20:10.437243 INFO: [DEVAPC] devapc_init done
10056 23:20:10.443516 INFO: GICv3 without legacy support detected.
10057 23:20:10.447147 INFO: ARM GICv3 driver initialized in EL3
10058 23:20:10.449981 INFO: Maximum SPI INTID supported: 639
10059 23:20:10.453305 INFO: BL31: Initializing runtime services
10060 23:20:10.460183 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10061 23:20:10.463550 INFO: SPM: enable CPC mode
10062 23:20:10.466660 INFO: mcdi ready for mcusys-off-idle and system suspend
10063 23:20:10.473609 INFO: BL31: Preparing for EL3 exit to normal world
10064 23:20:10.476560 INFO: Entry point address = 0x80000000
10065 23:20:10.476650 INFO: SPSR = 0x8
10066 23:20:10.483499
10067 23:20:10.483581
10068 23:20:10.483646
10069 23:20:10.486946 Starting depthcharge on Spherion...
10070 23:20:10.487028
10071 23:20:10.487092 Wipe memory regions:
10072 23:20:10.487153
10073 23:20:10.487783 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10074 23:20:10.487885 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10075 23:20:10.487970 Setting prompt string to ['asurada:']
10076 23:20:10.488050 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10077 23:20:10.489907 [0x00000040000000, 0x00000054600000)
10078 23:20:10.612633
10079 23:20:10.612810 [0x00000054660000, 0x00000080000000)
10080 23:20:10.873180
10081 23:20:10.873335 [0x000000821a7280, 0x000000ffe64000)
10082 23:20:11.617038
10083 23:20:11.617197 [0x00000100000000, 0x00000240000000)
10084 23:20:13.505839
10085 23:20:13.509428 Initializing XHCI USB controller at 0x11200000.
10086 23:20:14.546971
10087 23:20:14.549985 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10088 23:20:14.550081
10089 23:20:14.550165
10090 23:20:14.550227
10091 23:20:14.550510 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10093 23:20:14.650855 asurada: tftpboot 192.168.201.1 13248443/tftp-deploy-j1vc58mq/kernel/image.itb 13248443/tftp-deploy-j1vc58mq/kernel/cmdline
10094 23:20:14.651037 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10095 23:20:14.651169 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10096 23:20:14.655507 tftpboot 192.168.201.1 13248443/tftp-deploy-j1vc58mq/kernel/image.itp-deploy-j1vc58mq/kernel/cmdline
10097 23:20:14.655592
10098 23:20:14.655658 Waiting for link
10099 23:20:14.816085
10100 23:20:14.816269 R8152: Initializing
10101 23:20:14.816414
10102 23:20:14.819490 Version 9 (ocp_data = 6010)
10103 23:20:14.819584
10104 23:20:14.822585 R8152: Done initializing
10105 23:20:14.822690
10106 23:20:14.822791 Adding net device
10107 23:20:16.695236
10108 23:20:16.695409 done.
10109 23:20:16.695513
10110 23:20:16.695606 MAC: 00:e0:4c:72:2d:d6
10111 23:20:16.695702
10112 23:20:16.698038 Sending DHCP discover... done.
10113 23:20:16.698124
10114 23:20:16.701764 Waiting for reply... done.
10115 23:20:16.701882
10116 23:20:16.705001 Sending DHCP request... done.
10117 23:20:16.705086
10118 23:20:16.705153 Waiting for reply... done.
10119 23:20:16.705217
10120 23:20:16.707997 My ip is 192.168.201.21
10121 23:20:16.708082
10122 23:20:16.711468 The DHCP server ip is 192.168.201.1
10123 23:20:16.711553
10124 23:20:16.715108 TFTP server IP predefined by user: 192.168.201.1
10125 23:20:16.715193
10126 23:20:16.721594 Bootfile predefined by user: 13248443/tftp-deploy-j1vc58mq/kernel/image.itb
10127 23:20:16.721688
10128 23:20:16.724973 Sending tftp read request... done.
10129 23:20:16.725058
10130 23:20:16.728043 Waiting for the transfer...
10131 23:20:16.728128
10132 23:20:16.983534 00000000 ################################################################
10133 23:20:16.983693
10134 23:20:17.236135 00080000 ################################################################
10135 23:20:17.236288
10136 23:20:17.498889 00100000 ################################################################
10137 23:20:17.499029
10138 23:20:17.757987 00180000 ################################################################
10139 23:20:17.758166
10140 23:20:18.035266 00200000 ################################################################
10141 23:20:18.035415
10142 23:20:18.293168 00280000 ################################################################
10143 23:20:18.293326
10144 23:20:18.561610 00300000 ################################################################
10145 23:20:18.561765
10146 23:20:18.818986 00380000 ################################################################
10147 23:20:18.819138
10148 23:20:19.074961 00400000 ################################################################
10149 23:20:19.075114
10150 23:20:19.332214 00480000 ################################################################
10151 23:20:19.332369
10152 23:20:19.585046 00500000 ################################################################
10153 23:20:19.585255
10154 23:20:19.839014 00580000 ################################################################
10155 23:20:19.839241
10156 23:20:20.094247 00600000 ################################################################
10157 23:20:20.094474
10158 23:20:20.351484 00680000 ################################################################
10159 23:20:20.351717
10160 23:20:20.625499 00700000 ################################################################
10161 23:20:20.625687
10162 23:20:20.883582 00780000 ################################################################
10163 23:20:20.883762
10164 23:20:21.150687 00800000 ################################################################
10165 23:20:21.150838
10166 23:20:21.421868 00880000 ################################################################
10167 23:20:21.422052
10168 23:20:21.702098 00900000 ################################################################
10169 23:20:21.702292
10170 23:20:22.011046 00980000 ################################################################
10171 23:20:22.011232
10172 23:20:22.344085 00a00000 ################################################################
10173 23:20:22.344315
10174 23:20:22.674824 00a80000 ################################################################
10175 23:20:22.674979
10176 23:20:23.010397 00b00000 ################################################################
10177 23:20:23.010553
10178 23:20:23.319522 00b80000 ################################################################
10179 23:20:23.319677
10180 23:20:23.569540 00c00000 ################################################################
10181 23:20:23.569720
10182 23:20:23.829241 00c80000 ################################################################
10183 23:20:23.829413
10184 23:20:24.092230 00d00000 ################################################################
10185 23:20:24.092424
10186 23:20:24.343794 00d80000 ################################################################
10187 23:20:24.344045
10188 23:20:24.607328 00e00000 ################################################################
10189 23:20:24.607488
10190 23:20:24.874081 00e80000 ################################################################
10191 23:20:24.874239
10192 23:20:25.134124 00f00000 ################################################################
10193 23:20:25.134278
10194 23:20:25.396504 00f80000 ################################################################
10195 23:20:25.396720
10196 23:20:25.649308 01000000 ################################################################
10197 23:20:25.649467
10198 23:20:25.901073 01080000 ################################################################
10199 23:20:25.901239
10200 23:20:26.152290 01100000 ################################################################
10201 23:20:26.152436
10202 23:20:26.408479 01180000 ################################################################
10203 23:20:26.408627
10204 23:20:26.661076 01200000 ################################################################
10205 23:20:26.661228
10206 23:20:26.912325 01280000 ################################################################
10207 23:20:26.912474
10208 23:20:27.171051 01300000 ################################################################
10209 23:20:27.171226
10210 23:20:27.432044 01380000 ################################################################
10211 23:20:27.432193
10212 23:20:27.692886 01400000 ################################################################
10213 23:20:27.693026
10214 23:20:27.957759 01480000 ################################################################
10215 23:20:27.957897
10216 23:20:28.226409 01500000 ################################################################
10217 23:20:28.226555
10218 23:20:28.500281 01580000 ################################################################
10219 23:20:28.500442
10220 23:20:28.775569 01600000 ################################################################
10221 23:20:28.775722
10222 23:20:29.048991 01680000 ################################################################
10223 23:20:29.049139
10224 23:20:29.314019 01700000 ################################################################
10225 23:20:29.314188
10226 23:20:29.595783 01780000 ################################################################
10227 23:20:29.595960
10228 23:20:29.870462 01800000 ################################################################
10229 23:20:29.870610
10230 23:20:30.141963 01880000 ################################################################
10231 23:20:30.142114
10232 23:20:30.397065 01900000 ################################################################
10233 23:20:30.397206
10234 23:20:30.650203 01980000 ################################################################
10235 23:20:30.650374
10236 23:20:30.920373 01a00000 ################################################################
10237 23:20:30.920517
10238 23:20:31.180833 01a80000 ################################################################
10239 23:20:31.180991
10240 23:20:31.446059 01b00000 ################################################################
10241 23:20:31.446208
10242 23:20:31.718467 01b80000 ################################################################
10243 23:20:31.718610
10244 23:20:31.978048 01c00000 ################################################################
10245 23:20:31.978223
10246 23:20:32.231012 01c80000 ################################################################
10247 23:20:32.231187
10248 23:20:32.486886 01d00000 ################################################################
10249 23:20:32.487061
10250 23:20:32.747912 01d80000 ################################################################
10251 23:20:32.748084
10252 23:20:32.884033 01e00000 ################################## done.
10253 23:20:32.884190
10254 23:20:32.887578 The bootfile was 31732978 bytes long.
10255 23:20:32.887680
10256 23:20:32.890848 Sending tftp read request... done.
10257 23:20:32.890950
10258 23:20:32.894238 Waiting for the transfer...
10259 23:20:32.894341
10260 23:20:32.897456 00000000 # done.
10261 23:20:32.897535
10262 23:20:32.904011 Command line loaded dynamically from TFTP file: 13248443/tftp-deploy-j1vc58mq/kernel/cmdline
10263 23:20:32.904115
10264 23:20:32.927257 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248443/extract-nfsrootfs-6x_hms3y,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10265 23:20:32.927345
10266 23:20:32.927429 Loading FIT.
10267 23:20:32.927513
10268 23:20:32.930337 Image ramdisk-1 has 18776442 bytes.
10269 23:20:32.930416
10270 23:20:32.933702 Image fdt-1 has 47230 bytes.
10271 23:20:32.933780
10272 23:20:32.937120 Image kernel-1 has 12907270 bytes.
10273 23:20:32.937197
10274 23:20:32.943706 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10275 23:20:32.943786
10276 23:20:32.963799 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10277 23:20:32.963885
10278 23:20:32.967239 Choosing best match conf-1 for compat google,spherion-rev2.
10279 23:20:32.972071
10280 23:20:32.976849 Connected to device vid:did:rid of 1ae0:0028:00
10281 23:20:32.984167
10282 23:20:32.987174 tpm_get_response: command 0x17b, return code 0x0
10283 23:20:32.987275
10284 23:20:32.990419 ec_init: CrosEC protocol v3 supported (256, 248)
10285 23:20:32.994701
10286 23:20:32.997994 tpm_cleanup: add release locality here.
10287 23:20:32.998069
10288 23:20:32.998132 Shutting down all USB controllers.
10289 23:20:32.998195
10290 23:20:33.001452 Removing current net device
10291 23:20:33.001524
10292 23:20:33.008419 Exiting depthcharge with code 4 at timestamp: 51849894
10293 23:20:33.008521
10294 23:20:33.011785 LZMA decompressing kernel-1 to 0x821a6718
10295 23:20:33.011883
10296 23:20:33.014892 LZMA decompressing kernel-1 to 0x40000000
10297 23:20:34.608147
10298 23:20:34.608315 jumping to kernel
10299 23:20:34.608845 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10300 23:20:34.608958 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10301 23:20:34.609039 Setting prompt string to ['Linux version [0-9]']
10302 23:20:34.609109 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10303 23:20:34.609195 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10304 23:20:34.691267
10305 23:20:34.694740 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10306 23:20:34.698249 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10307 23:20:34.698360 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10308 23:20:34.698444 Setting prompt string to []
10309 23:20:34.698541 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10310 23:20:34.698629 Using line separator: #'\n'#
10311 23:20:34.698702 No login prompt set.
10312 23:20:34.698783 Parsing kernel messages
10313 23:20:34.698876 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10314 23:20:34.699064 [login-action] Waiting for messages, (timeout 00:04:01)
10315 23:20:34.699166 Waiting using forced prompt support (timeout 00:02:00)
10316 23:20:34.717974 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10317 23:20:34.720885 [ 0.000000] random: crng init done
10318 23:20:34.727737 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10319 23:20:34.730872 [ 0.000000] efi: UEFI not found.
10320 23:20:34.737660 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10321 23:20:34.744380 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10322 23:20:34.754130 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10323 23:20:34.764344 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10324 23:20:34.771011 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10325 23:20:34.777651 [ 0.000000] printk: bootconsole [mtk8250] enabled
10326 23:20:34.784010 [ 0.000000] NUMA: No NUMA configuration found
10327 23:20:34.791051 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10328 23:20:34.794382 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10329 23:20:34.797588 [ 0.000000] Zone ranges:
10330 23:20:34.804064 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10331 23:20:34.807334 [ 0.000000] DMA32 empty
10332 23:20:34.813941 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10333 23:20:34.817569 [ 0.000000] Movable zone start for each node
10334 23:20:34.820640 [ 0.000000] Early memory node ranges
10335 23:20:34.826954 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10336 23:20:34.833630 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10337 23:20:34.840525 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10338 23:20:34.843791 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10339 23:20:34.850482 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10340 23:20:34.857266 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10341 23:20:34.915375 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10342 23:20:34.922171 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10343 23:20:34.928676 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10344 23:20:34.932014 [ 0.000000] psci: probing for conduit method from DT.
10345 23:20:34.938791 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10346 23:20:34.942114 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10347 23:20:34.948665 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10348 23:20:34.952245 [ 0.000000] psci: SMC Calling Convention v1.2
10349 23:20:34.958684 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10350 23:20:34.962285 [ 0.000000] Detected VIPT I-cache on CPU0
10351 23:20:34.969155 [ 0.000000] CPU features: detected: GIC system register CPU interface
10352 23:20:34.975455 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10353 23:20:34.982161 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10354 23:20:34.988916 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10355 23:20:34.995367 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10356 23:20:35.001939 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10357 23:20:35.008838 [ 0.000000] alternatives: applying boot alternatives
10358 23:20:35.012162 [ 0.000000] Fallback order for Node 0: 0
10359 23:20:35.018794 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10360 23:20:35.022203 [ 0.000000] Policy zone: Normal
10361 23:20:35.045097 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248443/extract-nfsrootfs-6x_hms3y,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10362 23:20:35.058285 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10363 23:20:35.068582 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10364 23:20:35.078552 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10365 23:20:35.084730 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10366 23:20:35.088287 <6>[ 0.000000] software IO TLB: area num 8.
10367 23:20:35.144803 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10368 23:20:35.293704 <6>[ 0.000000] Memory: 7946236K/8385536K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 406532K reserved, 32768K cma-reserved)
10369 23:20:35.300577 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10370 23:20:35.306961 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10371 23:20:35.310612 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10372 23:20:35.317240 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10373 23:20:35.323698 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10374 23:20:35.326840 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10375 23:20:35.336954 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10376 23:20:35.343324 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10377 23:20:35.350380 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10378 23:20:35.356569 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10379 23:20:35.359825 <6>[ 0.000000] GICv3: 608 SPIs implemented
10380 23:20:35.363291 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10381 23:20:35.369895 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10382 23:20:35.373093 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10383 23:20:35.379787 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10384 23:20:35.392960 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10385 23:20:35.406299 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10386 23:20:35.412559 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10387 23:20:35.420677 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10388 23:20:35.433737 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10389 23:20:35.440688 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10390 23:20:35.447157 <6>[ 0.009178] Console: colour dummy device 80x25
10391 23:20:35.457024 <6>[ 0.013895] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10392 23:20:35.460255 <6>[ 0.024337] pid_max: default: 32768 minimum: 301
10393 23:20:35.467009 <6>[ 0.029238] LSM: Security Framework initializing
10394 23:20:35.473949 <6>[ 0.034177] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10395 23:20:35.483804 <6>[ 0.041990] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10396 23:20:35.490693 <6>[ 0.051410] cblist_init_generic: Setting adjustable number of callback queues.
10397 23:20:35.497137 <6>[ 0.058901] cblist_init_generic: Setting shift to 3 and lim to 1.
10398 23:20:35.507094 <6>[ 0.065279] cblist_init_generic: Setting adjustable number of callback queues.
10399 23:20:35.510650 <6>[ 0.072706] cblist_init_generic: Setting shift to 3 and lim to 1.
10400 23:20:35.516786 <6>[ 0.079106] rcu: Hierarchical SRCU implementation.
10401 23:20:35.523434 <6>[ 0.084122] rcu: Max phase no-delay instances is 1000.
10402 23:20:35.530086 <6>[ 0.091139] EFI services will not be available.
10403 23:20:35.533403 <6>[ 0.096123] smp: Bringing up secondary CPUs ...
10404 23:20:35.541575 <6>[ 0.101174] Detected VIPT I-cache on CPU1
10405 23:20:35.548388 <6>[ 0.101247] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10406 23:20:35.554377 <6>[ 0.101277] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10407 23:20:35.557827 <6>[ 0.101613] Detected VIPT I-cache on CPU2
10408 23:20:35.564569 <6>[ 0.101664] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10409 23:20:35.574901 <6>[ 0.101683] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10410 23:20:35.577914 <6>[ 0.101943] Detected VIPT I-cache on CPU3
10411 23:20:35.584398 <6>[ 0.101991] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10412 23:20:35.591077 <6>[ 0.102006] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10413 23:20:35.594336 <6>[ 0.102310] CPU features: detected: Spectre-v4
10414 23:20:35.600886 <6>[ 0.102317] CPU features: detected: Spectre-BHB
10415 23:20:35.604327 <6>[ 0.102322] Detected PIPT I-cache on CPU4
10416 23:20:35.610898 <6>[ 0.102384] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10417 23:20:35.617537 <6>[ 0.102402] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10418 23:20:35.624138 <6>[ 0.102697] Detected PIPT I-cache on CPU5
10419 23:20:35.630526 <6>[ 0.102761] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10420 23:20:35.637354 <6>[ 0.102777] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10421 23:20:35.640748 <6>[ 0.103056] Detected PIPT I-cache on CPU6
10422 23:20:35.647060 <6>[ 0.103123] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10423 23:20:35.657186 <6>[ 0.103139] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10424 23:20:35.660024 <6>[ 0.103432] Detected PIPT I-cache on CPU7
10425 23:20:35.666869 <6>[ 0.103497] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10426 23:20:35.673657 <6>[ 0.103513] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10427 23:20:35.676628 <6>[ 0.103559] smp: Brought up 1 node, 8 CPUs
10428 23:20:35.683413 <6>[ 0.245063] SMP: Total of 8 processors activated.
10429 23:20:35.686743 <6>[ 0.249984] CPU features: detected: 32-bit EL0 Support
10430 23:20:35.696941 <6>[ 0.255348] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10431 23:20:35.703470 <6>[ 0.264148] CPU features: detected: Common not Private translations
10432 23:20:35.710306 <6>[ 0.270624] CPU features: detected: CRC32 instructions
10433 23:20:35.713559 <6>[ 0.276009] CPU features: detected: RCpc load-acquire (LDAPR)
10434 23:20:35.719867 <6>[ 0.282006] CPU features: detected: LSE atomic instructions
10435 23:20:35.726772 <6>[ 0.287788] CPU features: detected: Privileged Access Never
10436 23:20:35.733126 <6>[ 0.293604] CPU features: detected: RAS Extension Support
10437 23:20:35.739836 <6>[ 0.299213] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10438 23:20:35.743283 <6>[ 0.306432] CPU: All CPU(s) started at EL2
10439 23:20:35.749955 <6>[ 0.310749] alternatives: applying system-wide alternatives
10440 23:20:35.759490 <6>[ 0.321573] devtmpfs: initialized
10441 23:20:35.771448 <6>[ 0.330480] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10442 23:20:35.781691 <6>[ 0.340443] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10443 23:20:35.787970 <6>[ 0.348566] pinctrl core: initialized pinctrl subsystem
10444 23:20:35.791312 <6>[ 0.355231] DMI not present or invalid.
10445 23:20:35.797940 <6>[ 0.359642] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10446 23:20:35.807932 <6>[ 0.366485] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10447 23:20:35.814476 <6>[ 0.374075] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10448 23:20:35.824923 <6>[ 0.382290] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10449 23:20:35.828367 <6>[ 0.390529] audit: initializing netlink subsys (disabled)
10450 23:20:35.838024 <5>[ 0.396220] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10451 23:20:35.844554 <6>[ 0.396926] thermal_sys: Registered thermal governor 'step_wise'
10452 23:20:35.851147 <6>[ 0.404182] thermal_sys: Registered thermal governor 'power_allocator'
10453 23:20:35.854806 <6>[ 0.410438] cpuidle: using governor menu
10454 23:20:35.861209 <6>[ 0.421394] NET: Registered PF_QIPCRTR protocol family
10455 23:20:35.867528 <6>[ 0.426893] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10456 23:20:35.870828 <6>[ 0.433998] ASID allocator initialised with 32768 entries
10457 23:20:35.878373 <6>[ 0.440569] Serial: AMBA PL011 UART driver
10458 23:20:35.887427 <4>[ 0.449445] Trying to register duplicate clock ID: 134
10459 23:20:35.942074 <6>[ 0.507308] KASLR enabled
10460 23:20:35.956012 <6>[ 0.515072] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10461 23:20:35.962945 <6>[ 0.522082] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10462 23:20:35.969509 <6>[ 0.528575] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10463 23:20:35.975928 <6>[ 0.535580] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10464 23:20:35.982876 <6>[ 0.542063] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10465 23:20:35.989706 <6>[ 0.549069] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10466 23:20:35.996540 <6>[ 0.555555] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10467 23:20:36.003129 <6>[ 0.562562] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10468 23:20:36.005955 <6>[ 0.570092] ACPI: Interpreter disabled.
10469 23:20:36.014419 <6>[ 0.576517] iommu: Default domain type: Translated
10470 23:20:36.021163 <6>[ 0.581630] iommu: DMA domain TLB invalidation policy: strict mode
10471 23:20:36.024097 <5>[ 0.588292] SCSI subsystem initialized
10472 23:20:36.031071 <6>[ 0.592459] usbcore: registered new interface driver usbfs
10473 23:20:36.037355 <6>[ 0.598193] usbcore: registered new interface driver hub
10474 23:20:36.040621 <6>[ 0.603743] usbcore: registered new device driver usb
10475 23:20:36.047640 <6>[ 0.609840] pps_core: LinuxPPS API ver. 1 registered
10476 23:20:36.057477 <6>[ 0.615033] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10477 23:20:36.060864 <6>[ 0.624380] PTP clock support registered
10478 23:20:36.064468 <6>[ 0.628621] EDAC MC: Ver: 3.0.0
10479 23:20:36.071921 <6>[ 0.633765] FPGA manager framework
10480 23:20:36.078259 <6>[ 0.637447] Advanced Linux Sound Architecture Driver Initialized.
10481 23:20:36.081589 <6>[ 0.644229] vgaarb: loaded
10482 23:20:36.088103 <6>[ 0.647400] clocksource: Switched to clocksource arch_sys_counter
10483 23:20:36.091425 <5>[ 0.653836] VFS: Disk quotas dquot_6.6.0
10484 23:20:36.098261 <6>[ 0.658022] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10485 23:20:36.101466 <6>[ 0.665210] pnp: PnP ACPI: disabled
10486 23:20:36.109908 <6>[ 0.671843] NET: Registered PF_INET protocol family
10487 23:20:36.119967 <6>[ 0.677441] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10488 23:20:36.130855 <6>[ 0.689780] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10489 23:20:36.141069 <6>[ 0.698592] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10490 23:20:36.147471 <6>[ 0.706568] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10491 23:20:36.154213 <6>[ 0.715269] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10492 23:20:36.166052 <6>[ 0.725023] TCP: Hash tables configured (established 65536 bind 65536)
10493 23:20:36.172863 <6>[ 0.731886] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10494 23:20:36.179298 <6>[ 0.739087] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10495 23:20:36.185759 <6>[ 0.746789] NET: Registered PF_UNIX/PF_LOCAL protocol family
10496 23:20:36.192477 <6>[ 0.752938] RPC: Registered named UNIX socket transport module.
10497 23:20:36.195736 <6>[ 0.759089] RPC: Registered udp transport module.
10498 23:20:36.202470 <6>[ 0.764020] RPC: Registered tcp transport module.
10499 23:20:36.209266 <6>[ 0.768954] RPC: Registered tcp NFSv4.1 backchannel transport module.
10500 23:20:36.212533 <6>[ 0.775616] PCI: CLS 0 bytes, default 64
10501 23:20:36.215962 <6>[ 0.779952] Unpacking initramfs...
10502 23:20:36.240632 <6>[ 0.799490] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10503 23:20:36.250352 <6>[ 0.808166] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10504 23:20:36.253614 <6>[ 0.817024] kvm [1]: IPA Size Limit: 40 bits
10505 23:20:36.260143 <6>[ 0.821553] kvm [1]: GICv3: no GICV resource entry
10506 23:20:36.263766 <6>[ 0.826572] kvm [1]: disabling GICv2 emulation
10507 23:20:36.269988 <6>[ 0.831256] kvm [1]: GIC system register CPU interface enabled
10508 23:20:36.273426 <6>[ 0.837415] kvm [1]: vgic interrupt IRQ18
10509 23:20:36.279870 <6>[ 0.841768] kvm [1]: VHE mode initialized successfully
10510 23:20:36.286999 <5>[ 0.848250] Initialise system trusted keyrings
10511 23:20:36.293607 <6>[ 0.853106] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10512 23:20:36.301247 <6>[ 0.863296] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10513 23:20:36.307824 <5>[ 0.869691] NFS: Registering the id_resolver key type
10514 23:20:36.310813 <5>[ 0.874993] Key type id_resolver registered
10515 23:20:36.317456 <5>[ 0.879407] Key type id_legacy registered
10516 23:20:36.324319 <6>[ 0.883701] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10517 23:20:36.330754 <6>[ 0.890625] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10518 23:20:36.337129 <6>[ 0.898337] 9p: Installing v9fs 9p2000 file system support
10519 23:20:36.373619 <5>[ 0.936029] Key type asymmetric registered
10520 23:20:36.377086 <5>[ 0.940357] Asymmetric key parser 'x509' registered
10521 23:20:36.387058 <6>[ 0.945499] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10522 23:20:36.390248 <6>[ 0.953117] io scheduler mq-deadline registered
10523 23:20:36.393472 <6>[ 0.957915] io scheduler kyber registered
10524 23:20:36.412637 <6>[ 0.975147] EINJ: ACPI disabled.
10525 23:20:36.445796 <4>[ 1.001191] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10526 23:20:36.455853 <4>[ 1.011818] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10527 23:20:36.470580 <6>[ 1.032915] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10528 23:20:36.478949 <6>[ 1.041142] printk: console [ttyS0] disabled
10529 23:20:36.506794 <6>[ 1.065789] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10530 23:20:36.513905 <6>[ 1.075281] printk: console [ttyS0] enabled
10531 23:20:36.516870 <6>[ 1.075281] printk: console [ttyS0] enabled
10532 23:20:36.523565 <6>[ 1.084180] printk: bootconsole [mtk8250] disabled
10533 23:20:36.527005 <6>[ 1.084180] printk: bootconsole [mtk8250] disabled
10534 23:20:36.533364 <6>[ 1.095442] SuperH (H)SCI(F) driver initialized
10535 23:20:36.537178 <6>[ 1.100726] msm_serial: driver initialized
10536 23:20:36.550872 <6>[ 1.109735] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10537 23:20:36.560865 <6>[ 1.118293] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10538 23:20:36.567596 <6>[ 1.126835] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10539 23:20:36.577279 <6>[ 1.135463] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10540 23:20:36.583884 <6>[ 1.144169] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10541 23:20:36.593821 <6>[ 1.152882] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10542 23:20:36.604123 <6>[ 1.161432] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10543 23:20:36.610918 <6>[ 1.170227] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10544 23:20:36.620841 <6>[ 1.178771] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10545 23:20:36.633295 <6>[ 1.194502] loop: module loaded
10546 23:20:36.639392 <6>[ 1.200506] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10547 23:20:36.662222 <4>[ 1.223839] mtk-pmic-keys: Failed to locate of_node [id: -1]
10548 23:20:36.669455 <6>[ 1.230801] megasas: 07.719.03.00-rc1
10549 23:20:36.679059 <6>[ 1.240578] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10550 23:20:36.685509 <6>[ 1.246804] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10551 23:20:36.702205 <6>[ 1.263496] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10552 23:20:36.758229 <6>[ 1.313557] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10553 23:20:37.009845 <6>[ 1.571536] Freeing initrd memory: 18332K
10554 23:20:37.021644 <6>[ 1.583177] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10555 23:20:37.032478 <6>[ 1.594073] tun: Universal TUN/TAP device driver, 1.6
10556 23:20:37.035959 <6>[ 1.600147] thunder_xcv, ver 1.0
10557 23:20:37.038576 <6>[ 1.603650] thunder_bgx, ver 1.0
10558 23:20:37.042077 <6>[ 1.607144] nicpf, ver 1.0
10559 23:20:37.052941 <6>[ 1.611183] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10560 23:20:37.055709 <6>[ 1.618659] hns3: Copyright (c) 2017 Huawei Corporation.
10561 23:20:37.059388 <6>[ 1.624246] hclge is initializing
10562 23:20:37.066139 <6>[ 1.627823] e1000: Intel(R) PRO/1000 Network Driver
10563 23:20:37.073019 <6>[ 1.632951] e1000: Copyright (c) 1999-2006 Intel Corporation.
10564 23:20:37.076107 <6>[ 1.638967] e1000e: Intel(R) PRO/1000 Network Driver
10565 23:20:37.083219 <6>[ 1.644182] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10566 23:20:37.089575 <6>[ 1.650367] igb: Intel(R) Gigabit Ethernet Network Driver
10567 23:20:37.096329 <6>[ 1.656017] igb: Copyright (c) 2007-2014 Intel Corporation.
10568 23:20:37.102575 <6>[ 1.661854] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10569 23:20:37.109473 <6>[ 1.668371] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10570 23:20:37.112625 <6>[ 1.674857] sky2: driver version 1.30
10571 23:20:37.119151 <6>[ 1.679866] VFIO - User Level meta-driver version: 0.3
10572 23:20:37.126210 <6>[ 1.688122] usbcore: registered new interface driver usb-storage
10573 23:20:37.132879 <6>[ 1.694576] usbcore: registered new device driver onboard-usb-hub
10574 23:20:37.142071 <6>[ 1.703771] mt6397-rtc mt6359-rtc: registered as rtc0
10575 23:20:37.151865 <6>[ 1.709234] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:19:36 UTC (1712186376)
10576 23:20:37.155417 <6>[ 1.718801] i2c_dev: i2c /dev entries driver
10577 23:20:37.172465 <6>[ 1.730533] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10578 23:20:37.179134 <4>[ 1.739263] cpu cpu0: supply cpu not found, using dummy regulator
10579 23:20:37.185606 <4>[ 1.745686] cpu cpu1: supply cpu not found, using dummy regulator
10580 23:20:37.192104 <4>[ 1.752104] cpu cpu2: supply cpu not found, using dummy regulator
10581 23:20:37.198947 <4>[ 1.758503] cpu cpu3: supply cpu not found, using dummy regulator
10582 23:20:37.205110 <4>[ 1.764907] cpu cpu4: supply cpu not found, using dummy regulator
10583 23:20:37.212132 <4>[ 1.771321] cpu cpu5: supply cpu not found, using dummy regulator
10584 23:20:37.218722 <4>[ 1.777717] cpu cpu6: supply cpu not found, using dummy regulator
10585 23:20:37.225268 <4>[ 1.784116] cpu cpu7: supply cpu not found, using dummy regulator
10586 23:20:37.243962 <6>[ 1.805770] cpu cpu0: EM: created perf domain
10587 23:20:37.247607 <6>[ 1.810717] cpu cpu4: EM: created perf domain
10588 23:20:37.254666 <6>[ 1.816306] sdhci: Secure Digital Host Controller Interface driver
10589 23:20:37.260978 <6>[ 1.822737] sdhci: Copyright(c) Pierre Ossman
10590 23:20:37.268360 <6>[ 1.827711] Synopsys Designware Multimedia Card Interface Driver
10591 23:20:37.274933 <6>[ 1.834350] sdhci-pltfm: SDHCI platform and OF driver helper
10592 23:20:37.277776 <6>[ 1.834467] mmc0: CQHCI version 5.10
10593 23:20:37.284627 <6>[ 1.844431] ledtrig-cpu: registered to indicate activity on CPUs
10594 23:20:37.291159 <6>[ 1.851523] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10595 23:20:37.298012 <6>[ 1.858579] usbcore: registered new interface driver usbhid
10596 23:20:37.301022 <6>[ 1.864404] usbhid: USB HID core driver
10597 23:20:37.307883 <6>[ 1.868614] spi_master spi0: will run message pump with realtime priority
10598 23:20:37.350830 <6>[ 1.905868] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10599 23:20:37.369209 <6>[ 1.920817] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10600 23:20:37.372687 <6>[ 1.934955] mmc0: Command Queue Engine enabled
10601 23:20:37.379643 <6>[ 1.939716] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10602 23:20:37.385771 <6>[ 1.946482] cros-ec-spi spi0.0: Chrome EC device registered
10603 23:20:37.389097 <6>[ 1.947010] mmcblk0: mmc0:0001 DA4128 116 GiB
10604 23:20:37.405038 <6>[ 1.966457] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10605 23:20:37.414575 <6>[ 1.970099] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10606 23:20:37.421117 <6>[ 1.973722] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10607 23:20:37.424730 <6>[ 1.982977] NET: Registered PF_PACKET protocol family
10608 23:20:37.431713 <6>[ 1.987589] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10609 23:20:37.434661 <6>[ 1.992298] 9pnet: Installing 9P2000 support
10610 23:20:37.440912 <6>[ 1.998118] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10611 23:20:37.447779 <5>[ 2.001987] Key type dns_resolver registered
10612 23:20:37.451239 <6>[ 2.013432] registered taskstats version 1
10613 23:20:37.457322 <5>[ 2.017809] Loading compiled-in X.509 certificates
10614 23:20:37.485329 <4>[ 2.040335] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10615 23:20:37.495269 <4>[ 2.051069] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10616 23:20:37.501948 <3>[ 2.061605] debugfs: File 'uA_load' in directory '/' already present!
10617 23:20:37.508623 <3>[ 2.068356] debugfs: File 'min_uV' in directory '/' already present!
10618 23:20:37.515504 <3>[ 2.074973] debugfs: File 'max_uV' in directory '/' already present!
10619 23:20:37.521929 <3>[ 2.081586] debugfs: File 'constraint_flags' in directory '/' already present!
10620 23:20:37.533218 <3>[ 2.091222] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10621 23:20:37.543212 <6>[ 2.105035] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10622 23:20:37.550220 <6>[ 2.112068] xhci-mtk 11200000.usb: xHCI Host Controller
10623 23:20:37.556726 <6>[ 2.117577] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10624 23:20:37.567256 <6>[ 2.125384] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10625 23:20:37.573696 <6>[ 2.134797] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10626 23:20:37.580729 <6>[ 2.140858] xhci-mtk 11200000.usb: xHCI Host Controller
10627 23:20:37.586846 <6>[ 2.146332] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10628 23:20:37.593706 <6>[ 2.153975] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10629 23:20:37.600036 <6>[ 2.161633] hub 1-0:1.0: USB hub found
10630 23:20:37.603857 <6>[ 2.165643] hub 1-0:1.0: 1 port detected
10631 23:20:37.610267 <6>[ 2.169901] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10632 23:20:37.616958 <6>[ 2.178426] hub 2-0:1.0: USB hub found
10633 23:20:37.620400 <6>[ 2.182433] hub 2-0:1.0: 1 port detected
10634 23:20:37.628463 <6>[ 2.190065] mtk-msdc 11f70000.mmc: Got CD GPIO
10635 23:20:37.640560 <6>[ 2.199234] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10636 23:20:37.647777 <6>[ 2.207279] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10637 23:20:37.657130 <4>[ 2.215257] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10638 23:20:37.667546 <6>[ 2.224796] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10639 23:20:37.674004 <6>[ 2.232913] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10640 23:20:37.680477 <6>[ 2.241070] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10641 23:20:37.690371 <6>[ 2.249029] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10642 23:20:37.697362 <6>[ 2.256849] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10643 23:20:37.707097 <6>[ 2.264667] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10644 23:20:37.717126 <6>[ 2.275004] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10645 23:20:37.724074 <6>[ 2.283382] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10646 23:20:37.733524 <6>[ 2.291720] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10647 23:20:37.740624 <6>[ 2.300060] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10648 23:20:37.750235 <6>[ 2.308397] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10649 23:20:37.757347 <6>[ 2.316735] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10650 23:20:37.766693 <6>[ 2.325073] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10651 23:20:37.773304 <6>[ 2.333410] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10652 23:20:37.783296 <6>[ 2.341747] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10653 23:20:37.793047 <6>[ 2.350085] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10654 23:20:37.800084 <6>[ 2.358421] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10655 23:20:37.809898 <6>[ 2.366762] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10656 23:20:37.816375 <6>[ 2.375099] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10657 23:20:37.826527 <6>[ 2.383436] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10658 23:20:37.832917 <6>[ 2.391773] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10659 23:20:37.839380 <6>[ 2.400520] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10660 23:20:37.846102 <6>[ 2.407726] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10661 23:20:37.852306 <6>[ 2.414552] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10662 23:20:37.863158 <6>[ 2.421378] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10663 23:20:37.869477 <6>[ 2.428342] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10664 23:20:37.876165 <6>[ 2.435190] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10665 23:20:37.885775 <6>[ 2.444317] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10666 23:20:37.895869 <6>[ 2.453436] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10667 23:20:37.905800 <6>[ 2.462732] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10668 23:20:37.915745 <6>[ 2.472200] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10669 23:20:37.922871 <6>[ 2.481668] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10670 23:20:37.932527 <6>[ 2.490788] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10671 23:20:37.942040 <6>[ 2.500292] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10672 23:20:37.952276 <6>[ 2.509412] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10673 23:20:37.961842 <6>[ 2.518706] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10674 23:20:37.972056 <6>[ 2.528866] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10675 23:20:37.982236 <6>[ 2.540922] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10676 23:20:37.988934 <6>[ 2.550609] Trying to probe devices needed for running init ...
10677 23:20:38.008905 <6>[ 2.567742] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10678 23:20:38.037527 <6>[ 2.599151] hub 2-1:1.0: USB hub found
10679 23:20:38.041055 <6>[ 2.603638] hub 2-1:1.0: 3 ports detected
10680 23:20:38.049581 <6>[ 2.610848] hub 2-1:1.0: USB hub found
10681 23:20:38.052414 <6>[ 2.615205] hub 2-1:1.0: 3 ports detected
10682 23:20:38.160943 <6>[ 2.719672] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10683 23:20:38.315299 <6>[ 2.877152] hub 1-1:1.0: USB hub found
10684 23:20:38.319013 <6>[ 2.881662] hub 1-1:1.0: 4 ports detected
10685 23:20:38.328093 <6>[ 2.889611] hub 1-1:1.0: USB hub found
10686 23:20:38.330972 <6>[ 2.894087] hub 1-1:1.0: 4 ports detected
10687 23:20:38.397514 <6>[ 2.955801] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10688 23:20:38.652871 <6>[ 3.211719] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10689 23:20:38.785654 <6>[ 3.347561] hub 1-1.4:1.0: USB hub found
10690 23:20:38.789019 <6>[ 3.352231] hub 1-1.4:1.0: 2 ports detected
10691 23:20:38.799210 <6>[ 3.360924] hub 1-1.4:1.0: USB hub found
10692 23:20:38.802233 <6>[ 3.365527] hub 1-1.4:1.0: 2 ports detected
10693 23:20:39.100546 <6>[ 3.659687] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10694 23:20:39.288524 <6>[ 3.847690] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10695 23:20:50.266217 <6>[ 14.832968] ALSA device list:
10696 23:20:50.272529 <6>[ 14.836408] No soundcards found.
10697 23:20:50.279823 <6>[ 14.843725] Freeing unused kernel memory: 8448K
10698 23:20:50.283275 <6>[ 14.848651] Run /init as init process
10699 23:20:50.292357 Loading, please wait...
10700 23:20:50.318171 Starting systemd-udevd version 252.22-1~deb12u1
10701 23:20:50.318262
10702 23:20:50.556120 <6>[ 15.116500] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10703 23:20:50.564283 <6>[ 15.128051] remoteproc remoteproc0: scp is available
10704 23:20:50.570762 <6>[ 15.133528] remoteproc remoteproc0: powering up scp
10705 23:20:50.577761 <6>[ 15.138728] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10706 23:20:50.588128 <6>[ 15.140564] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10707 23:20:50.591534 <6>[ 15.150709] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10708 23:20:50.601243 <6>[ 15.162034] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10709 23:20:50.608377 <6>[ 15.167217] usbcore: registered new device driver r8152-cfgselector
10710 23:20:50.617822 <3>[ 15.169100] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 23:20:50.624603 <3>[ 15.169115] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 23:20:50.631081 <3>[ 15.169123] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 23:20:50.641104 <3>[ 15.169187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 23:20:50.648079 <3>[ 15.169195] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 23:20:50.657738 <3>[ 15.169202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 23:20:50.664521 <3>[ 15.169210] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 23:20:50.674425 <3>[ 15.169217] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 23:20:50.681295 <3>[ 15.169252] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 23:20:50.690836 <3>[ 15.169284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 23:20:50.697759 <3>[ 15.169292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 23:20:50.703925 <3>[ 15.169299] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 23:20:50.714213 <3>[ 15.169336] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 23:20:50.720452 <3>[ 15.169344] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 23:20:50.730743 <3>[ 15.169351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 23:20:50.737627 <3>[ 15.169358] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 23:20:50.747760 <3>[ 15.169364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 23:20:50.753970 <3>[ 15.169390] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 23:20:50.764017 <6>[ 15.177241] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10729 23:20:50.767415 <6>[ 15.183665] mc: Linux media interface: v0.10
10730 23:20:50.774257 <6>[ 15.187326] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10731 23:20:50.784152 <4>[ 15.195176] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10732 23:20:50.787517 <6>[ 15.210450] videodev: Linux video capture interface: v2.00
10733 23:20:50.794351 <4>[ 15.225067] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10734 23:20:50.804117 <6>[ 15.284050] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10735 23:20:50.810991 <6>[ 15.287477] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10736 23:20:50.820708 <6>[ 15.287566] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10737 23:20:50.827294 <6>[ 15.287578] remoteproc remoteproc0: remote processor scp is now up
10738 23:20:50.834180 <6>[ 15.292191] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10739 23:20:50.841089 <4>[ 15.294929] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10740 23:20:50.847874 <4>[ 15.294929] Fallback method does not support PEC.
10741 23:20:50.857680 <3>[ 15.312028] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10742 23:20:50.864762 <6>[ 15.312259] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10743 23:20:50.867691 <6>[ 15.312266] pci_bus 0000:00: root bus resource [bus 00-ff]
10744 23:20:50.874219 <6>[ 15.312274] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10745 23:20:50.884461 <6>[ 15.312279] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10746 23:20:50.891276 <6>[ 15.312315] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10747 23:20:50.901300 <6>[ 15.312338] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10748 23:20:50.904691 <6>[ 15.312435] pci 0000:00:00.0: supports D1 D2
10749 23:20:50.910927 <6>[ 15.312439] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10750 23:20:50.921155 <6>[ 15.314230] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10751 23:20:50.924468 <6>[ 15.314338] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10752 23:20:50.934238 <6>[ 15.314369] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10753 23:20:50.941085 <6>[ 15.314390] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10754 23:20:50.947282 <6>[ 15.314409] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10755 23:20:50.954333 <6>[ 15.314525] pci 0000:01:00.0: supports D1 D2
10756 23:20:50.960819 <6>[ 15.314529] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10757 23:20:50.967523 <6>[ 15.315468] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10758 23:20:50.973885 <6>[ 15.326344] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10759 23:20:50.984120 <6>[ 15.326932] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10760 23:20:50.993863 <4>[ 15.327226] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10761 23:20:51.000513 <4>[ 15.327236] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10762 23:20:51.010204 <6>[ 15.327257] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10763 23:20:51.020132 <6>[ 15.331937] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10764 23:20:51.023626 <6>[ 15.387616] r8152 2-1.3:1.0 eth0: v1.12.13
10765 23:20:51.030502 <6>[ 15.388308] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10766 23:20:51.036820 <6>[ 15.394788] usbcore: registered new interface driver r8152
10767 23:20:51.043376 <6>[ 15.402922] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10768 23:20:51.053515 <6>[ 15.407436] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10769 23:20:51.063494 <3>[ 15.409477] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10770 23:20:51.066985 <6>[ 15.438215] Bluetooth: Core ver 2.22
10771 23:20:51.073371 <6>[ 15.445045] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10772 23:20:51.079898 <6>[ 15.455191] NET: Registered PF_BLUETOOTH protocol family
10773 23:20:51.089836 <6>[ 15.461209] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10774 23:20:51.093546 <6>[ 15.461406] usbcore: registered new interface driver cdc_ether
10775 23:20:51.099679 <6>[ 15.468673] Bluetooth: HCI device and connection manager initialized
10776 23:20:51.106222 <6>[ 15.473202] pci 0000:00:00.0: PCI bridge to [bus 01]
10777 23:20:51.113101 <6>[ 15.473352] usbcore: registered new interface driver r8153_ecm
10778 23:20:51.116769 <6>[ 15.480070] Bluetooth: HCI socket layer initialized
10779 23:20:51.126020 <6>[ 15.488311] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10780 23:20:51.132838 <6>[ 15.490043] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10781 23:20:51.139704 <6>[ 15.490892] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10782 23:20:51.149595 <6>[ 15.491021] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10783 23:20:51.156304 <6>[ 15.491114] usbcore: registered new interface driver uvcvideo
10784 23:20:51.162674 <6>[ 15.494564] Bluetooth: L2CAP socket layer initialized
10785 23:20:51.169445 <6>[ 15.502186] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10786 23:20:51.172639 <6>[ 15.509506] Bluetooth: SCO socket layer initialized
10787 23:20:51.179200 <6>[ 15.522250] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10788 23:20:51.186244 <6>[ 15.529256] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10789 23:20:51.192786 <6>[ 15.553998] usbcore: registered new interface driver btusb
10790 23:20:51.202640 <4>[ 15.554759] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10791 23:20:51.209148 <3>[ 15.554772] Bluetooth: hci0: Failed to load firmware file (-2)
10792 23:20:51.215719 <3>[ 15.554778] Bluetooth: hci0: Failed to set up firmware (-2)
10793 23:20:51.225424 <4>[ 15.554783] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10794 23:20:51.232445 <6>[ 15.562917] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10795 23:20:51.255715 <5>[ 15.816485] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10796 23:20:51.276977 <5>[ 15.837716] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10797 23:20:51.283414 <5>[ 15.845130] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10798 23:20:51.293624 <4>[ 15.853622] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10799 23:20:51.297102 <6>[ 15.862542] cfg80211: failed to load regulatory.db
10800 23:20:51.355121 <6>[ 15.915689] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10801 23:20:51.361308 <6>[ 15.923253] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10802 23:20:51.386136 <6>[ 15.950210] mt7921e 0000:01:00.0: ASIC revision: 79610010
10803 23:20:51.492452 <6>[ 16.053258] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10804 23:20:51.495669 <6>[ 16.053258]
10805 23:20:51.505091 Begin: Loading essential drivers ... done.
10806 23:20:51.508912 Begin: Running /scripts/init-premount ... done.
10807 23:20:51.515409 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10808 23:20:51.525385 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10809 23:20:51.528962 Device /sys/class/net/enx00e04c722dd6 found
10810 23:20:51.529046 done.
10811 23:20:51.535110 Begin: Waiting up to 180 secs for any network device to become available ... done.
10812 23:20:51.575057 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10813 23:20:51.759953 <6>[ 16.320562] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10814 23:20:52.499424 <6>[ 17.063214] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10815 23:20:52.619645 <6>[ 17.183628] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10816 23:20:52.645151 IP-Config: no response after 2 secs - giving up
10817 23:20:52.695734 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:7b mtu 1500 DHCP
10818 23:20:53.415116 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10819 23:20:53.417861 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10820 23:20:53.424638 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10821 23:20:53.431551 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10822 23:20:53.437960 host : mt8192-asurada-spherion-r0-cbg-1
10823 23:20:53.444552 domain : lava-rack
10824 23:20:53.447892 rootserver: 192.168.201.1 rootpath:
10825 23:20:53.451182 filename :
10826 23:20:53.534219 done.
10827 23:20:53.537242 Begin: Running /scripts/nfs-bottom ... done.
10828 23:20:53.556585 Begin: Running /scripts/init-bottom ... done.
10829 23:20:54.859097 <6>[ 19.423330] NET: Registered PF_INET6 protocol family
10830 23:20:54.866087 <6>[ 19.430644] Segment Routing with IPv6
10831 23:20:54.869611 <6>[ 19.434597] In-situ OAM (IOAM) with IPv6
10832 23:20:55.049535 <30>[ 19.587492] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10833 23:20:55.056175 <30>[ 19.620585] systemd[1]: Detected architecture arm64.
10834 23:20:55.062783
10835 23:20:55.065989 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10836 23:20:55.066074
10837 23:20:55.066141
10838 23:20:55.087995 <30>[ 19.652427] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10839 23:20:55.994838 <30>[ 20.555918] systemd[1]: Queued start job for default target graphical.target.
10840 23:20:56.031448 <30>[ 20.592524] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10841 23:20:56.037756 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10842 23:20:56.037834
10843 23:20:56.060364 <30>[ 20.621515] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10844 23:20:56.070359 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10845 23:20:56.070457
10846 23:20:56.088451 <30>[ 20.649428] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10847 23:20:56.098033 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10848 23:20:56.098144
10849 23:20:56.116785 <30>[ 20.677922] systemd[1]: Created slice user.slice - User and Session Slice.
10850 23:20:56.123319 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10851 23:20:56.123424
10852 23:20:56.146495 <30>[ 20.704573] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10853 23:20:56.156474 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10854 23:20:56.156592
10855 23:20:56.174009 <30>[ 20.731940] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10856 23:20:56.180650 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10857 23:20:56.180751
10858 23:20:56.209152 <30>[ 20.760348] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10859 23:20:56.218791 <30>[ 20.780257] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10860 23:20:56.225376 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10861 23:20:56.225505
10862 23:20:56.242824 <30>[ 20.804112] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10863 23:20:56.249865 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10864 23:20:56.252530
10865 23:20:56.270829 <30>[ 20.831774] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10866 23:20:56.280241 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10867 23:20:56.280329
10868 23:20:56.295671 <30>[ 20.860203] systemd[1]: Reached target paths.target - Path Units.
10869 23:20:56.302439 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10870 23:20:56.305875
10871 23:20:56.322940 <30>[ 20.884166] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10872 23:20:56.329597 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10873 23:20:56.329682
10874 23:20:56.343005 <30>[ 20.907685] systemd[1]: Reached target slices.target - Slice Units.
10875 23:20:56.353095 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10876 23:20:56.353208
10877 23:20:56.367536 <30>[ 20.932214] systemd[1]: Reached target swap.target - Swaps.
10878 23:20:56.374256 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10879 23:20:56.374374
10880 23:20:56.394702 <30>[ 20.956202] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10881 23:20:56.404945 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10882 23:20:56.405075
10883 23:20:56.423331 <30>[ 20.984671] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10884 23:20:56.433163 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10885 23:20:56.433249
10886 23:20:56.452392 <30>[ 21.013612] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10887 23:20:56.462243 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10888 23:20:56.462326
10889 23:20:56.479501 <30>[ 21.040945] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10890 23:20:56.489598 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10891 23:20:56.489691
10892 23:20:56.507485 <30>[ 21.068374] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10893 23:20:56.513611 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10894 23:20:56.513718
10895 23:20:56.531610 <30>[ 21.093041] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10896 23:20:56.541689 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10897 23:20:56.541797
10898 23:20:56.561015 <30>[ 21.122161] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10899 23:20:56.570746 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10900 23:20:56.570832
10901 23:20:56.587321 <30>[ 21.148730] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10902 23:20:56.597218 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10903 23:20:56.597305
10904 23:20:56.646985 <30>[ 21.208110] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10905 23:20:56.653546 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10906 23:20:56.653666
10907 23:20:56.673215 <30>[ 21.234546] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10908 23:20:56.680035 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10909 23:20:56.680135
10910 23:20:56.704286 <30>[ 21.265367] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10911 23:20:56.710637 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10912 23:20:56.710724
10913 23:20:56.737519 <30>[ 21.292425] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10914 23:20:56.752579 <30>[ 21.313923] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10915 23:20:56.762376 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10916 23:20:56.762461
10917 23:20:56.783862 <30>[ 21.345264] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10918 23:20:56.790446 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10919 23:20:56.790531
10920 23:20:56.818045 <30>[ 21.379054] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10921 23:20:56.824558 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10922 23:20:56.824703
10923 23:20:56.847625 <30>[ 21.408734] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10924 23:20:56.853952 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10925 23:20:56.854042
10926 23:20:56.865389 <6>[ 21.426902] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10927 23:20:56.883179 <30>[ 21.444327] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10928 23:20:56.893031 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10929 23:20:56.893117
10930 23:20:56.920018 <30>[ 21.481238] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10931 23:20:56.926273 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10932 23:20:56.926358
10933 23:20:56.955525 <30>[ 21.516985] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10934 23:20:56.959058 <6>[ 21.517679] fuse: init (API version 7.37)
10935 23:20:56.965869 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10936 23:20:56.969189
10937 23:20:57.000274 <30>[ 21.561874] systemd[1]: Starting systemd-journald.service - Journal Service...
10938 23:20:57.007390 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10939 23:20:57.007481
10940 23:20:57.047074 <30>[ 21.608263] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10941 23:20:57.053445 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10942 23:20:57.053582
10943 23:20:57.087137 <30>[ 21.645088] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10944 23:20:57.093654 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10945 23:20:57.093739
10946 23:20:57.121560 <30>[ 21.682922] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10947 23:20:57.131677 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10948 23:20:57.131762
10949 23:20:57.187108 <30>[ 21.748610] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10950 23:20:57.197139 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10951 23:20:57.197226
10952 23:20:57.212229 <3>[ 21.773166] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 23:20:57.225650 <30>[ 21.786949] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10954 23:20:57.232281 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10955 23:20:57.232364
10956 23:20:57.250654 <30>[ 21.812113] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10957 23:20:57.260930 <3>[ 21.812943] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 23:20:57.267373 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10959 23:20:57.267459
10960 23:20:57.287690 <30>[ 21.848491] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10961 23:20:57.301410 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-<3>[ 21.859982] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 23:20:57.305028 debug.m…nt[0m - Kernel Debug File System.
10963 23:20:57.305105
10964 23:20:57.324090 <30>[ 21.884458] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10965 23:20:57.334066 <3>[ 21.890007] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 23:20:57.340639 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10967 23:20:57.340735
10968 23:20:57.359532 <30>[ 21.920706] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10969 23:20:57.366462 <3>[ 21.923689] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 23:20:57.376520 <30>[ 21.928630] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10971 23:20:57.383176 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10972 23:20:57.383256
10973 23:20:57.396639 <3>[ 21.958314] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 23:20:57.406962 <30>[ 21.968434] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10975 23:20:57.413956 <30>[ 21.976324] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10976 23:20:57.423381 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10977 23:20:57.423461
10978 23:20:57.441547 <3>[ 22.002670] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 23:20:57.452125 <30>[ 22.013205] systemd[1]: modprobe@drm.service: Deactivated successfully.
10980 23:20:57.458923 <30>[ 22.020745] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10981 23:20:57.472579 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 22.031851] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 23:20:57.475847 rm.service[0m - Load Kernel Module drm.
10983 23:20:57.475923
10984 23:20:57.495889 <30>[ 22.056777] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10985 23:20:57.502797 <3>[ 22.062318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 23:20:57.512767 <30>[ 22.065086] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10987 23:20:57.519624 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10988 23:20:57.519704
10989 23:20:57.533619 <3>[ 22.095061] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 23:20:57.545182 <30>[ 22.106649] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10991 23:20:57.552208 <30>[ 22.114505] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10992 23:20:57.559113 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10993 23:20:57.559201
10994 23:20:57.577341 <30>[ 22.141513] systemd[1]: modprobe@loop.service: Deactivated successfully.
10995 23:20:57.587702 <30>[ 22.149106] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10996 23:20:57.594208 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10997 23:20:57.594323
10998 23:20:57.623294 <4>[ 22.177751] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10999 23:20:57.633410 <3>[ 22.193405] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11000 23:20:57.639772 <30>[ 22.194159] systemd[1]: Started systemd-journald.service - Journal Service.
11001 23:20:57.646561 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11002 23:20:57.646645
11003 23:20:57.671072 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11004 23:20:57.671160
11005 23:20:57.692437 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11006 23:20:57.692522
11007 23:20:57.712149 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11008 23:20:57.712302
11009 23:20:57.731893 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11010 23:20:57.732088
11011 23:20:57.753321 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11012 23:20:57.753404
11013 23:20:57.798563 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11014 23:20:57.798652
11015 23:20:57.819532 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11016 23:20:57.819636
11017 23:20:57.867449 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11018 23:20:57.867567
11019 23:20:57.890221 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11020 23:20:57.890316
11021 23:20:57.918420 <46>[ 22.479701] systemd-journald[309]: Received client request to flush runtime journal.
11022 23:20:57.940371 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11023 23:20:57.940460
11024 23:20:57.965237 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11025 23:20:57.965327
11026 23:20:58.235464 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11027 23:20:58.235597
11028 23:20:58.255177 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11029 23:20:58.255269
11030 23:20:58.275923 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11031 23:20:58.276011
11032 23:20:58.868298 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11033 23:20:58.868444
11034 23:20:59.316230 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11035 23:20:59.316372
11036 23:20:59.336103 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11037 23:20:59.336190
11038 23:20:59.387584 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11039 23:20:59.387678
11040 23:20:59.455280 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11041 23:20:59.455382
11042 23:20:59.478777 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11043 23:20:59.478863
11044 23:20:59.502362 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11045 23:20:59.502448
11046 23:20:59.556314 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11047 23:20:59.556407
11048 23:20:59.580296 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11049 23:20:59.580384
11050 23:20:59.771119 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11051 23:20:59.771248
11052 23:20:59.795646 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11053 23:20:59.795735
11054 23:20:59.881809 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11055 23:20:59.881924
11056 23:20:59.959596 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11057 23:20:59.959707
11058 23:21:00.132848 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11059 23:21:00.132965
11060 23:21:00.161285 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11061 23:21:00.161380
11062 23:21:00.302348 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11063 23:21:00.302483
11064 23:21:00.319887 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11065 23:21:00.319969
11066 23:21:00.371557 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11067 23:21:00.371661
11068 23:21:00.419370 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11069 23:21:00.419468
11070 23:21:00.447462 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11071 23:21:00.447552
11072 23:21:00.467566 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11073 23:21:00.467654
11074 23:21:00.491251 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11075 23:21:00.491340
11076 23:21:00.514753 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11077 23:21:00.514839
11078 23:21:00.534150 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11079 23:21:00.534236
11080 23:21:00.557658 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m -<46>[ 25.120966] systemd-journald[309]: Time jumped backwards, rotating.
11081 23:21:00.560903 System Initialization.
11082 23:21:00.560989
11083 23:21:00.578358 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11084 23:21:00.578447
11085 23:21:00.594056 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11086 23:21:00.594246
11087 23:21:00.618271 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11088 23:21:00.618389
11089 23:21:00.636560 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11090 23:21:00.636674
11091 23:21:00.654601 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11092 23:21:00.654708
11093 23:21:01.090564 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11094 23:21:01.090718
11095 23:21:01.358619 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11096 23:21:01.358764
11097 23:21:01.378364 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11098 23:21:01.378469
11099 23:21:01.548514 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11100 23:21:01.548717
11101 23:21:01.565591 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11102 23:21:01.565677
11103 23:21:01.582416 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11104 23:21:01.582499
11105 23:21:01.708331 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11106 23:21:01.708459
11107 23:21:02.088692 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11108 23:21:02.088925
11109 23:21:02.195292 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11110 23:21:02.195791
11111 23:21:02.220425 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11112 23:21:02.220949
11113 23:21:02.244676 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11114 23:21:02.245173
11115 23:21:02.386548 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11116 23:21:02.387067
11117 23:21:02.442919 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11118 23:21:02.443025
11119 23:21:02.488128 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11120 23:21:02.488592
11121 23:21:02.506999 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11122 23:21:02.507480
11123 23:21:02.533918 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11124 23:21:02.534559
11125 23:21:02.551287 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11126 23:21:02.551853
11127 23:21:02.586621 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11128 23:21:02.587214
11129 23:21:02.608498 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11130 23:21:02.609076
11131 23:21:02.639676 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11132 23:21:02.640250
11133 23:21:02.659084 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11134 23:21:02.659717
11135 23:21:02.712778 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11136 23:21:02.713333
11137 23:21:02.746134 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11138 23:21:02.746233
11139 23:21:02.778965 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11140 23:21:02.779598
11141 23:21:02.863872 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11142 23:21:02.864442
11143 23:21:02.966539
11144 23:21:02.967102
11145 23:21:02.969595 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11146 23:21:02.970115
11147 23:21:02.973025 debian-bookworm-arm64 login: root (automatic login)
11148 23:21:02.973486
11149 23:21:02.973849
11150 23:21:03.207713 Linux debian-bookworm-arm64 6.1.83-cip18 #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024 aarch64
11151 23:21:03.208307
11152 23:21:03.214503 The programs included with the Debian GNU/Linux system are free software;
11153 23:21:03.220863 the exact distribution terms for each program are described in the
11154 23:21:03.224597 individual files in /usr/share/doc/*/copyright.
11155 23:21:03.225109
11156 23:21:03.231150 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11157 23:21:03.234071 permitted by applicable law.
11158 23:21:03.336626 Matched prompt #10: / #
11160 23:21:03.337959 Setting prompt string to ['/ #']
11161 23:21:03.338441 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11163 23:21:03.339506 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11164 23:21:03.339981 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
11165 23:21:03.340509 Setting prompt string to ['/ #']
11166 23:21:03.340907 Forcing a shell prompt, looking for ['/ #']
11168 23:21:03.391845 / #
11169 23:21:03.392508 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11170 23:21:03.393024 Waiting using forced prompt support (timeout 00:02:30)
11171 23:21:03.397754
11172 23:21:03.398570 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11173 23:21:03.399093 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
11175 23:21:03.500284 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248443/extract-nfsrootfs-6x_hms3y'
11176 23:21:03.506633 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248443/extract-nfsrootfs-6x_hms3y'
11178 23:21:03.608722 / # export NFS_SERVER_IP='192.168.201.1'
11179 23:21:03.615253 export NFS_SERVER_IP='192.168.201.1'
11180 23:21:03.616190 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11181 23:21:03.616765 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
11182 23:21:03.617257 end: 2 depthcharge-action (duration 00:01:28) [common]
11183 23:21:03.617768 start: 3 lava-test-retry (timeout 00:30:00) [common]
11184 23:21:03.618331 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11185 23:21:03.618772 Using namespace: common
11187 23:21:03.719995 / # #
11188 23:21:03.720696 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11189 23:21:03.726462 #
11190 23:21:03.727624 Using /lava-13248443
11192 23:21:03.828945 / # export SHELL=/bin/sh
11193 23:21:03.835756 export SHELL=/bin/sh
11195 23:21:03.937424 / # . /lava-13248443/environment
11196 23:21:03.943471 . /lava-13248443/environment
11198 23:21:04.050993 / # /lava-13248443/bin/lava-test-runner /lava-13248443/0
11199 23:21:04.051635 Test shell timeout: 10s (minimum of the action and connection timeout)
11200 23:21:04.057785 /lava-13248443/bin/lava-test-runner /lava-13248443/0
11201 23:21:04.274071 + export TESTRUN_ID=0_lc-compliance
11202 23:21:04.280478 + cd /lava-13248443/0/tests/0_lc-compliance
11203 23:21:04.280989 + cat uuid
11204 23:21:04.286184 + UUID=13248443_1.6.2.3.1
11205 23:21:04.286651 + set +x
11206 23:21:04.292757 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 13248443_1.6.2.3.1>
11207 23:21:04.293655 Received signal: <STARTRUN> 0_lc-compliance 13248443_1.6.2.3.1
11208 23:21:04.294199 Starting test lava.0_lc-compliance (13248443_1.6.2.3.1)
11209 23:21:04.294918 Skipping test definition patterns.
11210 23:21:04.296082 + /usr/bin/lc-compliance-parser.sh
11211 23:21:05.928229 [0:00:30.371435001] [416] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11212 23:21:05.931844 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11213 23:21:05.944608 [0:00:30.388060309] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11214 23:21:05.996014 [==========] Running 120 tests from 1 test suite.
11215 23:21:06.005995 [0:00:30.450026309] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11216 23:21:06.060397 [0:00:30.503585386] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11217 23:21:06.063760 [----------] Global test environment set-up.
11218 23:21:06.114511 [0:00:30.557308463] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11219 23:21:06.144176 [----------] 120 tests from CaptureTests/SingleStream
11220 23:21:06.215527 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11221 23:21:06.278165 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11222 23:21:06.278921 Received signal: <TESTSET> START CaptureTests/SingleStream
11223 23:21:06.279310 Starting test_set CaptureTests/SingleStream
11224 23:21:06.281588 Camera needs 4 requests, can't test only 1
11225 23:21:06.356749 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11226 23:21:06.429548
11227 23:21:06.507412 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (62 ms)
11228 23:21:06.544402 [0:00:30.987629001] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11229 23:21:06.599542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11230 23:21:06.600360 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11232 23:21:06.615289 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11233 23:21:06.666100 Camera needs 4 requests, can't test only 2
11234 23:21:06.742626 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11235 23:21:06.817716
11236 23:21:06.901081 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (53 ms)
11237 23:21:06.993768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11238 23:21:06.994552 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11240 23:21:07.008325 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11241 23:21:07.040365 [0:00:31.483726155] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11242 23:21:07.058558 Camera needs 4 requests, can't test only 3
11243 23:21:07.135750 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11244 23:21:07.208752
11245 23:21:07.291826 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (53 ms)
11246 23:21:07.380591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11247 23:21:07.381403 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11249 23:21:07.396773 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11250 23:21:07.447295 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (430 ms)
11251 23:21:07.539382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11252 23:21:07.540157 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11254 23:21:07.554333 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11255 23:21:07.604354 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (496 ms)
11256 23:21:07.691010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11257 23:21:07.691772 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11259 23:21:07.704580 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11260 23:21:07.736351 [0:00:32.179700847] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11261 23:21:07.753015 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (695 ms)
11262 23:21:07.847129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11263 23:21:07.847504 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11265 23:21:07.859948 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11266 23:21:08.625519 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (897 ms)
11267 23:21:08.635942 [0:00:33.079319463] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11268 23:21:08.718397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11269 23:21:08.719231 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11271 23:21:08.733719 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11272 23:21:10.023111 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1397 ms)
11273 23:21:10.032688 [0:00:34.476738540] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11274 23:21:10.096665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11275 23:21:10.097153 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11277 23:21:10.107989 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11278 23:21:12.153444 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2130 ms)
11279 23:21:12.163422 [0:00:36.607476540] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11280 23:21:12.244632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11281 23:21:12.245397 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11283 23:21:12.259446 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11284 23:21:15.382957 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3230 ms)
11285 23:21:15.393252 [0:00:39.837397309] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11286 23:21:15.449218 [0:00:39.893796694] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11287 23:21:15.471750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11288 23:21:15.472022 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11290 23:21:15.483702 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11291 23:21:15.503644 [0:00:39.948285617] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11292 23:21:15.531370 Camera needs 4 requests, can't test only 1
11293 23:21:15.560008 [0:00:40.004409617] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11294 23:21:15.604205 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11295 23:21:15.671111
11296 23:21:15.753730 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (57 ms)
11297 23:21:15.837377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11298 23:21:15.838120 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11300 23:21:15.852059 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11301 23:21:15.899181 Camera needs 4 requests, can't test only 2
11302 23:21:15.926747 [0:00:40.371087232] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11303 23:21:15.964071 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11304 23:21:16.032304
11305 23:21:16.113098 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (55 ms)
11306 23:21:16.201692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11307 23:21:16.202411 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11309 23:21:16.217651 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11310 23:21:16.267097 Camera needs 4 requests, can't test only 3
11311 23:21:16.337705 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11312 23:21:16.391122 [0:00:40.835698694] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11313 23:21:16.406321
11314 23:21:16.467478 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (56 ms)
11315 23:21:16.534363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11316 23:21:16.535072 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11318 23:21:16.547353 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11319 23:21:16.591542 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (366 ms)
11320 23:21:16.673150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11321 23:21:16.673857 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11323 23:21:16.688593 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11324 23:21:16.734832 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (464 ms)
11325 23:21:16.811455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11326 23:21:16.811732 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11328 23:21:16.823174 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11329 23:21:17.078642 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (695 ms)
11330 23:21:17.091616 [0:00:41.532298925] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11331 23:21:17.175726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11332 23:21:17.176541 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11334 23:21:17.189234 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11335 23:21:17.977638 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (899 ms)
11336 23:21:17.990817 [0:00:42.431588771] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11337 23:21:18.056596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11338 23:21:18.056893 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11340 23:21:18.068204 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11341 23:21:19.376102 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1397 ms)
11342 23:21:19.389123 [0:00:43.829639694] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11343 23:21:19.468130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11344 23:21:19.468841 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11346 23:21:19.483353 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11347 23:21:21.471975 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2096 ms)
11348 23:21:21.485328 [0:00:45.926382233] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11349 23:21:21.548968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11350 23:21:21.549435 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11352 23:21:21.561458 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11353 23:21:21.588953 <6>[ 46.159765] vpu: disabling
11354 23:21:21.592464 <6>[ 46.162903] vproc2: disabling
11355 23:21:21.595874 <6>[ 46.166214] vproc1: disabling
11356 23:21:21.598865 <6>[ 46.169539] vaud18: disabling
11357 23:21:21.605398 <6>[ 46.173040] vsram_others: disabling
11358 23:21:21.609104 <6>[ 46.177005] va09: disabling
11359 23:21:21.612326 <6>[ 46.180166] vsram_md: disabling
11360 23:21:21.615301 <6>[ 46.183740] Vgpu: disabling
11361 23:21:24.701913 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3230 ms)
11362 23:21:24.715231 [0:00:49.157021925] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11363 23:21:24.767604 [0:00:49.213415387] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11364 23:21:24.782845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11365 23:21:24.783116 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11367 23:21:24.793203 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11368 23:21:24.823018 [0:00:49.268990848] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11369 23:21:24.834010 Camera needs 4 requests, can't test only 1
11370 23:21:24.878996 [0:00:49.324375771] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11371 23:21:24.894006 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11372 23:21:24.946973
11373 23:21:25.003762 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (56 ms)
11374 23:21:25.060898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11375 23:21:25.061183 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11377 23:21:25.073076 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11378 23:21:25.110627 Camera needs 4 requests, can't test only 2
11379 23:21:25.161252 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11380 23:21:25.213213
11381 23:21:25.242813 [0:00:49.688222771] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11382 23:21:25.274537 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (56 ms)
11383 23:21:25.336129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11384 23:21:25.336436 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11386 23:21:25.346558 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11387 23:21:25.385854 Camera needs 4 requests, can't test only 3
11388 23:21:25.441591 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11389 23:21:25.497172
11390 23:21:25.558875 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (54 ms)
11391 23:21:25.625655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11392 23:21:25.625942 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11394 23:21:25.637767 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11395 23:21:25.677748 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (364 ms)
11396 23:21:25.705577 [0:00:50.151638464] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11397 23:21:25.754120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11398 23:21:25.754423 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11400 23:21:25.766052 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11401 23:21:25.805935 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (462 ms)
11402 23:21:25.883231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11403 23:21:25.884000 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11405 23:21:25.898783 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11406 23:21:26.393383 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (695 ms)
11407 23:21:26.406309 [0:00:50.848057464] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11408 23:21:26.466451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11409 23:21:26.466749 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11411 23:21:26.478065 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11412 23:21:27.291992 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (898 ms)
11413 23:21:27.305884 [0:00:51.747289079] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11414 23:21:27.388353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11415 23:21:27.389229 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11417 23:21:27.404806 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11418 23:21:28.689387 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1397 ms)
11419 23:21:28.702634 [0:00:53.146067464] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11420 23:21:28.783516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11421 23:21:28.784312 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11423 23:21:28.800191 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11424 23:21:30.819585 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2130 ms)
11425 23:21:30.832438 [0:00:55.276952618] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11426 23:21:30.889080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11427 23:21:30.889402 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11429 23:21:30.900840 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11430 23:21:34.049861 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3230 ms)
11431 23:21:34.062942 [0:00:58.508188970] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11432 23:21:34.115278 [0:00:58.562173056] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11433 23:21:34.125192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11434 23:21:34.125482 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11436 23:21:34.134879 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11437 23:21:34.168630 [0:00:58.615472785] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11438 23:21:34.179262 Camera needs 4 requests, can't test only 1
11439 23:21:34.222613 [0:00:58.669304714] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11440 23:21:34.242447 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11441 23:21:34.292424
11442 23:21:34.347068 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (57 ms)
11443 23:21:34.406291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11444 23:21:34.406618 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11446 23:21:34.417568 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11447 23:21:34.456145 Camera needs 4 requests, can't test only 2
11448 23:21:34.512949 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11449 23:21:34.567932
11450 23:21:34.589249 [0:00:59.035546804] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11451 23:21:34.641486 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (53 ms)
11452 23:21:34.700964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11453 23:21:34.701292 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11455 23:21:34.714701 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11456 23:21:34.753923 Camera needs 4 requests, can't test only 3
11457 23:21:34.819085 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11458 23:21:34.881098
11459 23:21:34.949815 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (53 ms)
11460 23:21:35.030402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11461 23:21:35.030729 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11463 23:21:35.045285 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11464 23:21:35.055468 [0:00:59.499346852] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11465 23:21:35.094976 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (365 ms)
11466 23:21:35.172908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11467 23:21:35.173237 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11469 23:21:35.184299 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11470 23:21:35.224955 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (463 ms)
11471 23:21:35.301272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11472 23:21:35.301596 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11474 23:21:35.313979 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11475 23:21:35.741591 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (696 ms)
11476 23:21:35.754597 [0:01:00.196373113] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11477 23:21:35.824154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11478 23:21:35.824477 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11480 23:21:35.837139 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11481 23:21:36.640261 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (898 ms)
11482 23:21:36.653545 [0:01:01.095274344] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11483 23:21:36.710565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11484 23:21:36.710891 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11486 23:21:36.723129 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11487 23:21:38.037184 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1396 ms)
11488 23:21:38.050676 [0:01:02.493824700] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11489 23:21:38.108384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11490 23:21:38.108698 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11492 23:21:38.120585 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11493 23:21:40.135035 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2097 ms)
11494 23:21:40.148455 [0:01:04.591396467] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11495 23:21:40.223549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11496 23:21:40.223922 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11498 23:21:40.236625 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11499 23:21:43.366392 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3229 ms)
11500 23:21:43.379356 [0:01:07.821355041] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11501 23:21:43.435108 [0:01:07.878881383] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11502 23:21:43.490206 [0:01:07.934045759] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11503 23:21:43.545226 [0:01:07.988738341] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11504 23:21:45.325234 [0:01:09.269115144] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11505 23:21:45.331297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11506 23:21:45.331610 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11508 23:21:45.346960 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11509 23:21:45.395650 Camera needs 4 requests, can't test only 1
11510 23:21:45.473442 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11511 23:21:45.513648
11512 23:21:45.586765 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (59 ms)
11513 23:21:45.665284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11514 23:21:45.665619 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11516 23:21:45.677793 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11517 23:21:45.718409 Camera needs 4 requests, can't test only 2
11518 23:21:45.781784 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11519 23:21:45.843481
11520 23:21:45.912048 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (54 ms)
11521 23:21:45.984274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11522 23:21:45.984591 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11524 23:21:45.995751 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11525 23:21:46.033090 Camera needs 4 requests, can't test only 3
11526 23:21:46.087729 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11527 23:21:46.144545
11528 23:21:46.206117 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (55 ms)
11529 23:21:46.268027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11530 23:21:46.268321 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11532 23:21:46.282719 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11533 23:21:46.308385 [0:01:10.752190918] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11534 23:21:46.330833 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1280 ms)
11535 23:21:46.403949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11536 23:21:46.404240 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11538 23:21:46.416511 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11539 23:21:46.458868 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1483 ms)
11540 23:21:46.531405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11541 23:21:46.531700 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11543 23:21:46.544399 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11544 23:21:48.346642 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2046 ms)
11545 23:21:48.360164 [0:01:12.801797619] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11546 23:21:48.435179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11547 23:21:48.435457 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11549 23:21:48.450128 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11550 23:21:51.032619 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2685 ms)
11551 23:21:51.045918 [0:01:15.487984081] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11552 23:21:51.119049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11553 23:21:51.119379 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11555 23:21:51.132615 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11556 23:21:55.214128 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4180 ms)
11557 23:21:55.227751 [0:01:19.669060929] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11558 23:21:55.295814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11559 23:21:55.296144 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11561 23:21:55.309382 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11562 23:22:01.494096 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6279 ms)
11563 23:22:01.506837 [0:01:25.948721500] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11564 23:22:01.577985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11565 23:22:01.578320 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11567 23:22:01.590666 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11568 23:22:11.108484 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9615 ms)
11569 23:22:11.121354 [0:01:35.563913819] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11570 23:22:11.175261 [0:01:35.619436699] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11571 23:22:11.229403 [0:01:35.673452417] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11572 23:22:11.284183 [0:01:35.728458551] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11573 23:22:11.334321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11574 23:22:11.334680 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11576 23:22:11.347337 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11577 23:22:11.386359 Camera needs 4 requests, can't test only 1
11578 23:22:11.444165 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11579 23:22:11.500012
11580 23:22:11.565322 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (58 ms)
11581 23:22:11.650020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11582 23:22:11.650357 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11584 23:22:11.662527 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11585 23:22:11.703295 Camera needs 4 requests, can't test only 2
11586 23:22:11.757583 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11587 23:22:11.815193
11588 23:22:11.872696 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (53 ms)
11589 23:22:12.025212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11590 23:22:12.025572 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11592 23:22:12.035047 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11593 23:22:12.088159 Camera needs 4 requests, can't test only 3
11594 23:22:12.142204 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11595 23:22:12.193838
11596 23:22:12.255307 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (54 ms)
11597 23:22:12.327217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11598 23:22:12.327550 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11600 23:22:12.336895 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11601 23:22:12.429021 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1150 ms)
11602 23:22:12.438778 [0:01:36.878943955] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11603 23:22:12.741296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11604 23:22:12.741696 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11606 23:22:12.751340 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11607 23:22:13.820712 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1392 ms)
11608 23:22:13.830622 [0:01:38.273973771] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11609 23:22:13.985139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11610 23:22:13.985494 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11612 23:22:13.995056 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11613 23:22:15.936281 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2115 ms)
11614 23:22:15.946078 [0:01:40.388881065] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11615 23:22:16.040518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11616 23:22:16.040980 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11618 23:22:16.051285 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11619 23:22:18.624245 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2688 ms)
11620 23:22:18.634263 [0:01:43.078088089] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11621 23:22:18.736809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11622 23:22:18.737189 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11624 23:22:18.746737 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11625 23:22:22.806233 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4181 ms)
11626 23:22:22.815838 [0:01:47.259304077] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11627 23:22:22.878254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11628 23:22:22.878586 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11630 23:22:22.887092 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11631 23:22:29.086647 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6281 ms)
11632 23:22:29.096433 [0:01:53.540541580] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11633 23:22:29.158821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11634 23:22:29.159106 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11636 23:22:29.168999 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11637 23:22:38.798070 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9712 ms)
11638 23:22:38.807866 [0:02:03.252698653] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11639 23:22:38.862824 [0:02:03.309085082] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11640 23:22:38.918983 [0:02:03.365175743] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11641 23:22:38.973908 [0:02:03.419998736] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11642 23:22:38.991083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11643 23:22:38.991423 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11645 23:22:39.002272 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11646 23:22:39.045355 Camera needs 4 requests, can't test only 1
11647 23:22:39.099924 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11648 23:22:39.155355
11649 23:22:39.219722 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (58 ms)
11650 23:22:39.393987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11651 23:22:39.394305 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11653 23:22:39.415317 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11654 23:22:39.458022 Camera needs 4 requests, can't test only 2
11655 23:22:39.513503 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11656 23:22:39.570014
11657 23:22:39.637113 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (56 ms)
11658 23:22:39.800784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11659 23:22:39.801111 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11661 23:22:39.812469 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11662 23:22:39.856150 Camera needs 4 requests, can't test only 3
11663 23:22:39.908110 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11664 23:22:39.958412
11665 23:22:40.020637 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (54 ms)
11666 23:22:40.191171 [0:02:04.637378059] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11667 23:22:40.236318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11668 23:22:40.236694 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11670 23:22:40.247186 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11671 23:22:40.293754 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1217 ms)
11672 23:22:40.642524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11673 23:22:40.642843 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11675 23:22:40.653154 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11676 23:22:41.730639 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1544 ms)
11677 23:22:41.740244 [0:02:06.184626242] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11678 23:22:42.212087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11679 23:22:42.212511 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11681 23:22:42.223218 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11682 23:22:43.814000 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2083 ms)
11683 23:22:43.823823 [0:02:08.267932122] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11684 23:22:43.886220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11685 23:22:43.886528 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11687 23:22:43.897145 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11688 23:22:46.501365 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2687 ms)
11689 23:22:46.511307 [0:02:10.954987521] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11690 23:22:46.576612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11691 23:22:46.576982 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11693 23:22:46.586731 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11694 23:22:50.682537 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4180 ms)
11695 23:22:50.692494 [0:02:15.135871373] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11696 23:22:50.765811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11697 23:22:50.766133 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11699 23:22:50.776003 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11700 23:22:56.962684 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6279 ms)
11701 23:22:56.972237 [0:02:21.415072019] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11702 23:22:57.327094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11703 23:22:57.327867 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11705 23:22:57.340804 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11706 23:23:06.576582 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9614 ms)
11707 23:23:06.586991 [0:02:31.029989240] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11708 23:23:06.642019 [0:02:31.086188395] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11709 23:23:06.676785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11710 23:23:06.677559 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11712 23:23:06.688566 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11713 23:23:06.698536 [0:02:31.143882979] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11714 23:23:06.733267 Camera needs 4 requests, can't test only 1
11715 23:23:06.755147 [0:02:31.199750888] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11716 23:23:06.793441 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11717 23:23:06.850434
11718 23:23:06.912838 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (58 ms)
11719 23:23:06.984630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11720 23:23:06.984977 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11722 23:23:06.994882 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11723 23:23:07.031482 Camera needs 4 requests, can't test only 2
11724 23:23:07.091412 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11725 23:23:07.149163
11726 23:23:07.227839 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (54 ms)
11727 23:23:07.299126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11728 23:23:07.299436 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11730 23:23:07.309139 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11731 23:23:07.350831 Camera needs 4 requests, can't test only 3
11732 23:23:07.416275 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11733 23:23:07.474632
11734 23:23:07.546472 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (59 ms)
11735 23:23:07.607913 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11737 23:23:07.611230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11738 23:23:07.619509 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11739 23:23:08.063467 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1312 ms)
11740 23:23:08.073134 [0:02:32.513744624] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11741 23:23:08.132203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11742 23:23:08.132515 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11744 23:23:08.139120 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11745 23:23:09.515414 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1451 ms)
11746 23:23:09.525157 [0:02:33.967799928] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11747 23:23:09.580338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11748 23:23:09.580672 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11750 23:23:09.590419 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11751 23:23:11.597250 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2082 ms)
11752 23:23:11.607214 [0:02:36.050282557] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11753 23:23:11.669155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11754 23:23:11.669470 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11756 23:23:11.679042 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11757 23:23:14.284394 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2687 ms)
11758 23:23:14.294496 [0:02:38.737652662] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11759 23:23:14.363441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11760 23:23:14.363804 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11762 23:23:14.372972 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11763 23:23:18.465541 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4181 ms)
11764 23:23:18.475928 [0:02:42.918495348] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11765 23:23:18.553364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11766 23:23:18.553708 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11768 23:23:18.563944 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11769 23:23:24.778689 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6313 ms)
11770 23:23:24.788562 [0:02:49.231940447] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11771 23:23:24.868390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11772 23:23:24.868675 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11774 23:23:24.880392 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11775 23:23:34.393917 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9615 ms)
11776 23:23:34.403756 [0:02:58.846875669] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11777 23:23:34.474150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11778 23:23:34.474490 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11780 23:23:34.483910 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11781 23:23:34.689800 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (299 ms)
11782 23:23:34.699911 [0:02:59.144170534] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11783 23:23:34.771457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11784 23:23:34.771791 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11786 23:23:34.784519 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11787 23:23:34.956235 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (266 ms)
11788 23:23:34.969758 [0:02:59.410779525] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11789 23:23:35.028633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11790 23:23:35.028936 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11792 23:23:35.041023 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11793 23:23:35.256247 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (299 ms)
11794 23:23:35.269295 [0:02:59.710682288] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11795 23:23:35.328118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11796 23:23:35.328422 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11798 23:23:35.341530 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11799 23:23:35.720922 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (464 ms)
11800 23:23:35.733882 [0:03:00.174906355] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11801 23:23:35.799157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11802 23:23:35.799465 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11804 23:23:35.811086 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11805 23:23:36.284558 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (563 ms)
11806 23:23:36.298035 [0:03:00.738943896] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11807 23:23:36.360874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11808 23:23:36.361227 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11810 23:23:36.372037 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11811 23:23:36.982328 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (697 ms)
11812 23:23:36.995425 [0:03:01.436488916] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11813 23:23:37.061110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11814 23:23:37.061446 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11816 23:23:37.073626 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11817 23:23:37.881725 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (899 ms)
11818 23:23:37.894732 [0:03:02.336285805] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11819 23:23:37.960490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11820 23:23:37.960817 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11822 23:23:37.974280 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11823 23:23:39.278850 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1397 ms)
11824 23:23:39.292127 [0:03:03.735360824] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11825 23:23:39.367279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11826 23:23:39.367612 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11828 23:23:39.380095 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11829 23:23:41.410083 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2130 ms)
11830 23:23:41.423049 [0:03:05.866710734] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11831 23:23:41.487789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11832 23:23:41.488101 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11834 23:23:41.501856 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11835 23:23:44.639911 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3230 ms)
11836 23:23:44.653378 [0:03:09.097639142] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11837 23:23:44.719925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11838 23:23:44.720226 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11840 23:23:44.733652 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11841 23:23:44.880145 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (236 ms)
11842 23:23:44.890344 [0:03:09.332148017] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11843 23:23:44.962567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11844 23:23:44.962880 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11846 23:23:44.972284 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11847 23:23:45.149534 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (268 ms)
11848 23:23:45.159283 [0:03:09.600373610] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11849 23:23:45.244069 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11851 23:23:45.247458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11852 23:23:45.261602 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11853 23:23:45.448885 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (299 ms)
11854 23:23:45.458625 [0:03:09.899462163] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11855 23:23:45.532242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11856 23:23:45.532573 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11858 23:23:45.543116 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11859 23:23:45.879578 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (430 ms)
11860 23:23:45.889584 [0:03:10.330859405] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11861 23:23:45.964001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11862 23:23:45.964338 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11864 23:23:45.973648 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11865 23:23:46.378573 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (499 ms)
11866 23:23:46.388852 [0:03:10.830438965] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11867 23:23:46.459982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11868 23:23:46.460298 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11870 23:23:46.470515 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11871 23:23:47.077336 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (698 ms)
11872 23:23:47.086780 [0:03:11.528635362] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11873 23:23:47.171334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11874 23:23:47.171683 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11876 23:23:47.182434 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11877 23:23:47.976895 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (899 ms)
11878 23:23:47.986372 [0:03:12.428527040] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11879 23:23:48.063584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11880 23:23:48.063951 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11882 23:23:48.074739 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11883 23:23:49.373798 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1397 ms)
11884 23:23:49.383532 [0:03:13.827958896] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11885 23:23:49.458009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11886 23:23:49.458387 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11888 23:23:49.468811 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11889 23:23:51.472784 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2099 ms)
11890 23:23:51.483013 [0:03:15.927215217] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11891 23:23:51.559585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11892 23:23:51.559964 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11894 23:23:51.570784 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11895 23:23:54.704462 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3231 ms)
11896 23:23:54.714414 [0:03:19.158959964] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11897 23:23:54.794798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11898 23:23:54.795184 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11900 23:23:54.806358 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11901 23:23:55.004365 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (299 ms)
11902 23:23:55.014318 [0:03:19.456381236] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11903 23:23:55.085905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11904 23:23:55.086235 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11906 23:23:55.096811 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11907 23:23:55.271271 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (266 ms)
11908 23:23:55.280824 [0:03:19.723238369] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11909 23:23:55.359924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11910 23:23:55.360275 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11912 23:23:55.370785 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11913 23:23:55.570694 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (299 ms)
11914 23:23:55.580437 [0:03:20.022711153] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11915 23:23:55.652015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11916 23:23:55.652404 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11918 23:23:55.663079 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11919 23:23:56.034404 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (463 ms)
11920 23:23:56.044563 [0:03:20.486857903] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11921 23:23:56.125983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11922 23:23:56.126319 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11924 23:23:56.135546 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11925 23:23:56.598821 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (564 ms)
11926 23:23:56.609008 [0:03:21.051015143] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11927 23:23:56.677042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11928 23:23:56.677358 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11930 23:23:56.689607 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11931 23:23:57.296637 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (697 ms)
11932 23:23:57.306474 [0:03:21.748599258] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11933 23:23:57.377569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11934 23:23:57.377927 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11936 23:23:57.388965 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11937 23:23:58.195435 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (899 ms)
11938 23:23:58.205951 [0:03:22.648189041] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11939 23:23:58.282497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11940 23:23:58.282875 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11942 23:23:58.293030 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11943 23:23:59.593578 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1397 ms)
11944 23:23:59.603069 [0:03:24.048212656] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11945 23:23:59.679139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11946 23:23:59.679510 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11948 23:23:59.689891 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11949 23:24:01.691696 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2098 ms)
11950 23:24:01.701586 [0:03:26.146576879] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11951 23:24:01.780249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11952 23:24:01.780577 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11954 23:24:01.789635 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11955 23:24:04.859765 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3168 ms)
11956 23:24:04.869344 [0:03:29.314893691] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11957 23:24:04.937214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11958 23:24:04.937516 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11960 23:24:04.947277 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11961 23:24:05.190765 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (330 ms)
11962 23:24:05.200692 [0:03:29.642572512] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11963 23:24:05.262282 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11965 23:24:05.265420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11966 23:24:05.272765 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11967 23:24:05.554831 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (363 ms)
11968 23:24:05.564985 [0:03:30.007469115] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11969 23:24:05.618863 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11971 23:24:05.621598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11972 23:24:05.631328 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11973 23:24:05.855947 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (301 ms)
11974 23:24:05.865883 [0:03:30.309085908] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11975 23:24:05.932031 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11977 23:24:05.935340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11978 23:24:05.944859 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11979 23:24:06.288117 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (431 ms)
11980 23:24:06.297949 [0:03:30.740620091] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11981 23:24:06.354339 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11983 23:24:06.357263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11984 23:24:06.364598 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11985 23:24:06.754784 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (466 ms)
11986 23:24:06.764311 [0:03:31.207735276] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11987 23:24:06.819200 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11989 23:24:06.822545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11990 23:24:06.831495 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11991 23:24:07.453039 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (698 ms)
11992 23:24:07.462400 [0:03:31.905836178] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11993 23:24:07.519990 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11995 23:24:07.522801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11996 23:24:07.531703 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11997 23:24:08.387138 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (934 ms)
11998 23:24:08.396887 [0:03:32.840497721] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11999 23:24:08.463101 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
12001 23:24:08.465790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
12002 23:24:08.474808 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
12003 23:24:09.721403 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1334 ms)
12004 23:24:09.731067 [0:03:34.175690318] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
12005 23:24:09.796035 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
12007 23:24:09.798551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
12008 23:24:09.808040 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
12009 23:24:11.851063 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2129 ms)
12010 23:24:11.861010 [0:03:36.306956642] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
12011 23:24:11.916821 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
12013 23:24:11.919648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
12014 23:24:11.929225 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
12015 23:24:15.082712 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3231 ms)
12016 23:24:15.145457 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
12018 23:24:15.148420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
12019 23:24:15.156951 [----------] 120 tests from CaptureTests/SingleStream (189148 ms total)
12020 23:24:15.214915
12021 23:24:15.277143 [----------] Global test environment tear-down
12022 23:24:15.332833 [==========] 120 tests from 1 test suite ran. (189148 ms total)
12023 23:24:15.392642 <LAVA_SIGNAL_TESTSET STOP>
12024 23:24:15.392969 Received signal: <TESTSET> STOP
12025 23:24:15.393052 Closing test_set CaptureTests/SingleStream
12026 23:24:15.396047 + set +x
12027 23:24:15.399207 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 13248443_1.6.2.3.1>
12028 23:24:15.399464 Received signal: <ENDRUN> 0_lc-compliance 13248443_1.6.2.3.1
12029 23:24:15.399549 Ending use of test pattern.
12030 23:24:15.399615 Ending test lava.0_lc-compliance (13248443_1.6.2.3.1), duration 191.11
12032 23:24:15.402707 <LAVA_TEST_RUNNER EXIT>
12033 23:24:15.402997 ok: lava_test_shell seems to have completed
12034 23:24:15.405720 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
12035 23:24:15.405913 end: 3.1 lava-test-shell (duration 00:03:12) [common]
12036 23:24:15.406012 end: 3 lava-test-retry (duration 00:03:12) [common]
12037 23:24:15.406105 start: 4 finalize (timeout 00:10:00) [common]
12038 23:24:15.406196 start: 4.1 power-off (timeout 00:00:30) [common]
12039 23:24:15.406355 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
12040 23:24:15.480166 >> Command sent successfully.
12041 23:24:15.482556 Returned 0 in 0 seconds
12042 23:24:15.582960 end: 4.1 power-off (duration 00:00:00) [common]
12044 23:24:15.583406 start: 4.2 read-feedback (timeout 00:10:00) [common]
12045 23:24:15.583706 Listened to connection for namespace 'common' for up to 1s
12046 23:24:16.584697 Finalising connection for namespace 'common'
12047 23:24:16.584880 Disconnecting from shell: Finalise
12048 23:24:16.584966 / #
12049 23:24:16.685263 end: 4.2 read-feedback (duration 00:00:01) [common]
12050 23:24:16.685438 end: 4 finalize (duration 00:00:01) [common]
12051 23:24:16.685566 Cleaning after the job
12052 23:24:16.685666 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/ramdisk
12053 23:24:16.687802 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/kernel
12054 23:24:16.698282 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/dtb
12055 23:24:16.698473 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/nfsrootfs
12056 23:24:16.738755 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248443/tftp-deploy-j1vc58mq/modules
12057 23:24:16.744413 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248443
12058 23:24:17.002260 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248443
12059 23:24:17.002442 Job finished correctly