Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 48
- Errors: 0
- Kernel Errors: 31
- Boot result: PASS
1 23:21:40.280911 lava-dispatcher, installed at version: 2024.01
2 23:21:40.281132 start: 0 validate
3 23:21:40.281272 Start time: 2024-04-03 23:21:40.281262+00:00 (UTC)
4 23:21:40.281400 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:21:40.281568 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:21:40.541253 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:21:40.541421 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:21:40.791403 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:21:40.791581 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:21:41.049246 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:21:41.049445 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:21:41.307853 validate duration: 1.03
14 23:21:41.308224 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:21:41.308357 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:21:41.308474 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:21:41.308631 Not decompressing ramdisk as can be used compressed.
18 23:21:41.308750 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/rootfs.cpio.gz
19 23:21:41.308843 saving as /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/ramdisk/rootfs.cpio.gz
20 23:21:41.308935 total size: 95552279 (91 MB)
21 23:21:41.310185 progress 0 % (0 MB)
22 23:21:41.336470 progress 5 % (4 MB)
23 23:21:41.362976 progress 10 % (9 MB)
24 23:21:41.388310 progress 15 % (13 MB)
25 23:21:41.413911 progress 20 % (18 MB)
26 23:21:41.439281 progress 25 % (22 MB)
27 23:21:41.464287 progress 30 % (27 MB)
28 23:21:41.490513 progress 35 % (31 MB)
29 23:21:41.516934 progress 40 % (36 MB)
30 23:21:41.543042 progress 45 % (41 MB)
31 23:21:41.568674 progress 50 % (45 MB)
32 23:21:41.594208 progress 55 % (50 MB)
33 23:21:41.620265 progress 60 % (54 MB)
34 23:21:41.646720 progress 65 % (59 MB)
35 23:21:41.672403 progress 70 % (63 MB)
36 23:21:41.698069 progress 75 % (68 MB)
37 23:21:41.724152 progress 80 % (72 MB)
38 23:21:41.750238 progress 85 % (77 MB)
39 23:21:41.776397 progress 90 % (82 MB)
40 23:21:41.801798 progress 95 % (86 MB)
41 23:21:41.826830 progress 100 % (91 MB)
42 23:21:41.827010 91 MB downloaded in 0.52 s (175.89 MB/s)
43 23:21:41.827187 end: 1.1.1 http-download (duration 00:00:01) [common]
45 23:21:41.827442 end: 1.1 download-retry (duration 00:00:01) [common]
46 23:21:41.827531 start: 1.2 download-retry (timeout 00:09:59) [common]
47 23:21:41.827617 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 23:21:41.827763 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:21:41.827833 saving as /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/kernel/Image
50 23:21:41.827895 total size: 54286848 (51 MB)
51 23:21:41.827958 No compression specified
52 23:21:41.829222 progress 0 % (0 MB)
53 23:21:41.843939 progress 5 % (2 MB)
54 23:21:41.858550 progress 10 % (5 MB)
55 23:21:41.873068 progress 15 % (7 MB)
56 23:21:41.887481 progress 20 % (10 MB)
57 23:21:41.901864 progress 25 % (12 MB)
58 23:21:41.916321 progress 30 % (15 MB)
59 23:21:41.930611 progress 35 % (18 MB)
60 23:21:41.945077 progress 40 % (20 MB)
61 23:21:41.959482 progress 45 % (23 MB)
62 23:21:41.973989 progress 50 % (25 MB)
63 23:21:41.988683 progress 55 % (28 MB)
64 23:21:42.003831 progress 60 % (31 MB)
65 23:21:42.018302 progress 65 % (33 MB)
66 23:21:42.033187 progress 70 % (36 MB)
67 23:21:42.047709 progress 75 % (38 MB)
68 23:21:42.062377 progress 80 % (41 MB)
69 23:21:42.077045 progress 85 % (44 MB)
70 23:21:42.091584 progress 90 % (46 MB)
71 23:21:42.105728 progress 95 % (49 MB)
72 23:21:42.119964 progress 100 % (51 MB)
73 23:21:42.120238 51 MB downloaded in 0.29 s (177.10 MB/s)
74 23:21:42.120397 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:21:42.120632 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:21:42.120724 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:21:42.120813 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:21:42.120957 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:21:42.121030 saving as /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/dtb/mt8192-asurada-spherion-r0.dtb
81 23:21:42.121092 total size: 47230 (0 MB)
82 23:21:42.121156 No compression specified
83 23:21:42.122267 progress 69 % (0 MB)
84 23:21:42.122553 progress 100 % (0 MB)
85 23:21:42.122716 0 MB downloaded in 0.00 s (27.80 MB/s)
86 23:21:42.122841 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:21:42.123075 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:21:42.123161 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:21:42.123245 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:21:42.123366 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:21:42.123434 saving as /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/modules/modules.tar
93 23:21:42.123495 total size: 8629908 (8 MB)
94 23:21:42.123574 Using unxz to decompress xz
95 23:21:42.127971 progress 0 % (0 MB)
96 23:21:42.147236 progress 5 % (0 MB)
97 23:21:42.172388 progress 10 % (0 MB)
98 23:21:42.200348 progress 15 % (1 MB)
99 23:21:42.228663 progress 20 % (1 MB)
100 23:21:42.255927 progress 25 % (2 MB)
101 23:21:42.283852 progress 30 % (2 MB)
102 23:21:42.310508 progress 35 % (2 MB)
103 23:21:42.338133 progress 40 % (3 MB)
104 23:21:42.364317 progress 45 % (3 MB)
105 23:21:42.391554 progress 50 % (4 MB)
106 23:21:42.418686 progress 55 % (4 MB)
107 23:21:42.448751 progress 60 % (4 MB)
108 23:21:42.475349 progress 65 % (5 MB)
109 23:21:42.502788 progress 70 % (5 MB)
110 23:21:42.529292 progress 75 % (6 MB)
111 23:21:42.556576 progress 80 % (6 MB)
112 23:21:42.584616 progress 85 % (7 MB)
113 23:21:42.614938 progress 90 % (7 MB)
114 23:21:42.646314 progress 95 % (7 MB)
115 23:21:42.673948 progress 100 % (8 MB)
116 23:21:42.679405 8 MB downloaded in 0.56 s (14.81 MB/s)
117 23:21:42.679673 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:21:42.679969 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:21:42.680082 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:21:42.680198 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:21:42.680298 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:21:42.680410 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:21:42.680676 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w
125 23:21:42.680872 makedir: /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin
126 23:21:42.681027 makedir: /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/tests
127 23:21:42.681168 makedir: /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/results
128 23:21:42.681331 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-add-keys
129 23:21:42.681530 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-add-sources
130 23:21:42.681671 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-background-process-start
131 23:21:42.681811 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-background-process-stop
132 23:21:42.681944 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-common-functions
133 23:21:42.682078 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-echo-ipv4
134 23:21:42.682209 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-install-packages
135 23:21:42.682339 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-installed-packages
136 23:21:42.682472 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-os-build
137 23:21:42.682601 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-probe-channel
138 23:21:42.682734 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-probe-ip
139 23:21:42.682864 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-target-ip
140 23:21:42.682996 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-target-mac
141 23:21:42.683141 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-target-storage
142 23:21:42.683297 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-test-case
143 23:21:42.683479 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-test-event
144 23:21:42.683656 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-test-feedback
145 23:21:42.683834 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-test-raise
146 23:21:42.684015 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-test-reference
147 23:21:42.684192 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-test-runner
148 23:21:42.684370 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-test-set
149 23:21:42.684548 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-test-shell
150 23:21:42.684733 Updating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-install-packages (oe)
151 23:21:42.684945 Updating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/bin/lava-installed-packages (oe)
152 23:21:42.685118 Creating /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/environment
153 23:21:42.685274 LAVA metadata
154 23:21:42.685389 - LAVA_JOB_ID=13248456
155 23:21:42.685500 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:21:42.685644 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:21:42.685752 skipped lava-vland-overlay
158 23:21:42.685877 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:21:42.686007 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:21:42.686107 skipped lava-multinode-overlay
161 23:21:42.686232 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:21:42.686372 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:21:42.686490 Loading test definitions
164 23:21:42.686633 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 23:21:42.686746 Using /lava-13248456 at stage 0
166 23:21:42.686901 Fetching tests from https://github.com/kernelci/kernelci-core
167 23:21:42.687037 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/0/tests/0_sleep'
168 23:21:43.318556 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/0/tests/0_sleep
169 23:21:43.320159 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 23:21:43.320676 uuid=13248456_1.5.2.3.1 testdef=None
171 23:21:43.320825 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 23:21:43.321089 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 23:21:43.321810 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 23:21:43.322069 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 23:21:43.323025 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 23:21:43.323410 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 23:21:43.324343 runner path: /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/0/tests/0_sleep test_uuid 13248456_1.5.2.3.1
181 23:21:43.324430 sleep_params='mem'
182 23:21:43.324583 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 23:21:43.324940 Creating lava-test-runner.conf files
185 23:21:43.325036 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248456/lava-overlay-0f16p80w/lava-13248456/0 for stage 0
186 23:21:43.325163 - 0_sleep
187 23:21:43.325337 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 23:21:43.325461 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 23:21:43.477588 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 23:21:43.477745 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 23:21:43.477842 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 23:21:43.477940 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 23:21:43.478029 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 23:21:46.489185 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 23:21:46.489615 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 23:21:46.489737 extracting modules file /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248456/extract-overlay-ramdisk-8wubtfpx/ramdisk
197 23:21:46.722791 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 23:21:46.722979 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 23:21:46.723088 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248456/compress-overlay-96wl6n2w/overlay-1.5.2.4.tar.gz to ramdisk
200 23:21:46.723158 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248456/compress-overlay-96wl6n2w/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248456/extract-overlay-ramdisk-8wubtfpx/ramdisk
201 23:21:46.832640 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 23:21:46.832835 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
203 23:21:46.832968 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 23:21:46.833088 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
205 23:21:46.833199 Building ramdisk /var/lib/lava/dispatcher/tmp/13248456/extract-overlay-ramdisk-8wubtfpx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248456/extract-overlay-ramdisk-8wubtfpx/ramdisk
206 23:21:48.664540 >> 675457 blocks
207 23:21:59.946505 rename /var/lib/lava/dispatcher/tmp/13248456/extract-overlay-ramdisk-8wubtfpx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/ramdisk/ramdisk.cpio.gz
208 23:21:59.947087 end: 1.5.7 compress-ramdisk (duration 00:00:13) [common]
209 23:21:59.947261 start: 1.5.8 prepare-kernel (timeout 00:09:41) [common]
210 23:21:59.947411 start: 1.5.8.1 prepare-fit (timeout 00:09:41) [common]
211 23:21:59.947569 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/kernel/Image'
212 23:22:13.585215 Returned 0 in 13 seconds
213 23:22:13.685852 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/kernel/image.itb
214 23:22:15.276875 output: FIT description: Kernel Image image with one or more FDT blobs
215 23:22:15.277263 output: Created: Thu Apr 4 00:22:14 2024
216 23:22:15.277364 output: Image 0 (kernel-1)
217 23:22:15.277460 output: Description:
218 23:22:15.277571 output: Created: Thu Apr 4 00:22:14 2024
219 23:22:15.277688 output: Type: Kernel Image
220 23:22:15.277799 output: Compression: lzma compressed
221 23:22:15.277882 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
222 23:22:15.277950 output: Architecture: AArch64
223 23:22:15.278016 output: OS: Linux
224 23:22:15.278078 output: Load Address: 0x00000000
225 23:22:15.278140 output: Entry Point: 0x00000000
226 23:22:15.278199 output: Hash algo: crc32
227 23:22:15.278257 output: Hash value: d7c9dcc1
228 23:22:15.278313 output: Image 1 (fdt-1)
229 23:22:15.278370 output: Description: mt8192-asurada-spherion-r0
230 23:22:15.278425 output: Created: Thu Apr 4 00:22:14 2024
231 23:22:15.278479 output: Type: Flat Device Tree
232 23:22:15.278532 output: Compression: uncompressed
233 23:22:15.278586 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
234 23:22:15.278639 output: Architecture: AArch64
235 23:22:15.278693 output: Hash algo: crc32
236 23:22:15.278746 output: Hash value: 4bf0d1ac
237 23:22:15.278800 output: Image 2 (ramdisk-1)
238 23:22:15.278853 output: Description: unavailable
239 23:22:15.278907 output: Created: Thu Apr 4 00:22:14 2024
240 23:22:15.278981 output: Type: RAMDisk Image
241 23:22:15.279038 output: Compression: Unknown Compression
242 23:22:15.279093 output: Data Size: 109017346 Bytes = 106462.25 KiB = 103.97 MiB
243 23:22:15.279147 output: Architecture: AArch64
244 23:22:15.279201 output: OS: Linux
245 23:22:15.279254 output: Load Address: unavailable
246 23:22:15.279308 output: Entry Point: unavailable
247 23:22:15.279369 output: Hash algo: crc32
248 23:22:15.279432 output: Hash value: a0663cc1
249 23:22:15.279486 output: Default Configuration: 'conf-1'
250 23:22:15.279540 output: Configuration 0 (conf-1)
251 23:22:15.279594 output: Description: mt8192-asurada-spherion-r0
252 23:22:15.279647 output: Kernel: kernel-1
253 23:22:15.279700 output: Init Ramdisk: ramdisk-1
254 23:22:15.279754 output: FDT: fdt-1
255 23:22:15.279807 output: Loadables: kernel-1
256 23:22:15.279860 output:
257 23:22:15.280064 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 23:22:15.280169 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 23:22:15.280275 end: 1.5 prepare-tftp-overlay (duration 00:00:33) [common]
260 23:22:15.280373 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:26) [common]
261 23:22:15.280458 No LXC device requested
262 23:22:15.280550 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 23:22:15.280653 start: 1.7 deploy-device-env (timeout 00:09:26) [common]
264 23:22:15.280738 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 23:22:15.280804 Checking files for TFTP limit of 4294967296 bytes.
266 23:22:15.281366 end: 1 tftp-deploy (duration 00:00:34) [common]
267 23:22:15.281522 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 23:22:15.281623 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 23:22:15.281761 substitutions:
270 23:22:15.281837 - {DTB}: 13248456/tftp-deploy-2l1och7h/dtb/mt8192-asurada-spherion-r0.dtb
271 23:22:15.281903 - {INITRD}: 13248456/tftp-deploy-2l1och7h/ramdisk/ramdisk.cpio.gz
272 23:22:15.281963 - {KERNEL}: 13248456/tftp-deploy-2l1och7h/kernel/Image
273 23:22:15.282022 - {LAVA_MAC}: None
274 23:22:15.282088 - {PRESEED_CONFIG}: None
275 23:22:15.282164 - {PRESEED_LOCAL}: None
276 23:22:15.282226 - {RAMDISK}: 13248456/tftp-deploy-2l1och7h/ramdisk/ramdisk.cpio.gz
277 23:22:15.282284 - {ROOT_PART}: None
278 23:22:15.282341 - {ROOT}: None
279 23:22:15.282397 - {SERVER_IP}: 192.168.201.1
280 23:22:15.282463 - {TEE}: None
281 23:22:15.282524 Parsed boot commands:
282 23:22:15.282593 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 23:22:15.282783 Parsed boot commands: tftpboot 192.168.201.1 13248456/tftp-deploy-2l1och7h/kernel/image.itb 13248456/tftp-deploy-2l1och7h/kernel/cmdline
284 23:22:15.282877 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 23:22:15.282984 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 23:22:15.283083 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 23:22:15.283171 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 23:22:15.283244 Not connected, no need to disconnect.
289 23:22:15.283319 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 23:22:15.283422 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 23:22:15.283494 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
292 23:22:15.287817 Setting prompt string to ['lava-test: # ']
293 23:22:15.288211 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 23:22:15.288323 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 23:22:15.288422 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 23:22:15.288514 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 23:22:15.288754 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
298 23:22:20.427428 >> Command sent successfully.
299 23:22:20.430125 Returned 0 in 5 seconds
300 23:22:20.530524 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 23:22:20.530952 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 23:22:20.531132 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 23:22:20.531269 Setting prompt string to 'Starting depthcharge on Spherion...'
305 23:22:20.531372 Changing prompt to 'Starting depthcharge on Spherion...'
306 23:22:20.531474 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 23:22:20.531847 [Enter `^Ec?' for help]
308 23:22:20.703046
309 23:22:20.703215
310 23:22:20.703360 F0: 102B 0000
311 23:22:20.703454
312 23:22:20.703543 F3: 1001 0000 [0200]
313 23:22:20.703633
314 23:22:20.706662 F3: 1001 0000
315 23:22:20.706755
316 23:22:20.706843 F7: 102D 0000
317 23:22:20.706931
318 23:22:20.707016 F1: 0000 0000
319 23:22:20.710487
320 23:22:20.710564 V0: 0000 0000 [0001]
321 23:22:20.710634
322 23:22:20.710696 00: 0007 8000
323 23:22:20.710757
324 23:22:20.714263 01: 0000 0000
325 23:22:20.714330
326 23:22:20.714394 BP: 0C00 0209 [0000]
327 23:22:20.714452
328 23:22:20.717812 G0: 1182 0000
329 23:22:20.717876
330 23:22:20.717936 EC: 0000 0021 [4000]
331 23:22:20.717992
332 23:22:20.721405 S7: 0000 0000 [0000]
333 23:22:20.721472
334 23:22:20.721569 CC: 0000 0000 [0001]
335 23:22:20.721627
336 23:22:20.725003 T0: 0000 0040 [010F]
337 23:22:20.725065
338 23:22:20.725125 Jump to BL
339 23:22:20.725180
340 23:22:20.750021
341 23:22:20.750099
342 23:22:20.750163
343 23:22:20.757425 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 23:22:20.761293 ARM64: Exception handlers installed.
345 23:22:20.764381 ARM64: Testing exception
346 23:22:20.768243 ARM64: Done test exception
347 23:22:20.774853 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 23:22:20.785821 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 23:22:20.792701 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 23:22:20.802528 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 23:22:20.809064 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 23:22:20.815817 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 23:22:20.826493 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 23:22:20.833101 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 23:22:20.852620 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 23:22:20.855852 WDT: Last reset was cold boot
357 23:22:20.859044 SPI1(PAD0) initialized at 2873684 Hz
358 23:22:20.862412 SPI5(PAD0) initialized at 992727 Hz
359 23:22:20.866097 VBOOT: Loading verstage.
360 23:22:20.872717 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 23:22:20.875765 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 23:22:20.879269 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 23:22:20.882408 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 23:22:20.889871 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 23:22:20.896482 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 23:22:20.907479 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
367 23:22:20.907556
368 23:22:20.907621
369 23:22:20.917868 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 23:22:20.920980 ARM64: Exception handlers installed.
371 23:22:20.924118 ARM64: Testing exception
372 23:22:20.924188 ARM64: Done test exception
373 23:22:20.931293 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 23:22:20.934792 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 23:22:20.948277 Probing TPM: . done!
376 23:22:20.948360 TPM ready after 0 ms
377 23:22:20.955094 Connected to device vid:did:rid of 1ae0:0028:00
378 23:22:20.965503 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 23:22:20.965597 Initialized TPM device CR50 revision 0
380 23:22:21.017273 tlcl_send_startup: Startup return code is 0
381 23:22:21.017366 TPM: setup succeeded
382 23:22:21.029032 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 23:22:21.037819 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 23:22:21.048932 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 23:22:21.059129 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 23:22:21.062824 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 23:22:21.066340 in-header: 03 07 00 00 08 00 00 00
388 23:22:21.069978 in-data: aa e4 47 04 13 02 00 00
389 23:22:21.070061 Chrome EC: UHEPI supported
390 23:22:21.077003 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 23:22:21.081162 in-header: 03 9d 00 00 08 00 00 00
392 23:22:21.085011 in-data: 10 20 20 08 00 00 00 00
393 23:22:21.085093 Phase 1
394 23:22:21.088405 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 23:22:21.096288 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 23:22:21.103401 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 23:22:21.103485 Recovery requested (1009000e)
398 23:22:21.111875 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 23:22:21.117566 tlcl_extend: response is 0
400 23:22:21.125639 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 23:22:21.130922 tlcl_extend: response is 0
402 23:22:21.137798 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 23:22:21.158801 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
404 23:22:21.165846 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 23:22:21.165932
406 23:22:21.165997
407 23:22:21.173375 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 23:22:21.177272 ARM64: Exception handlers installed.
409 23:22:21.180848 ARM64: Testing exception
410 23:22:21.184186 ARM64: Done test exception
411 23:22:21.204467 pmic_efuse_setting: Set efuses in 11 msecs
412 23:22:21.207852 pmwrap_interface_init: Select PMIF_VLD_RDY
413 23:22:21.211747 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 23:22:21.219469 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 23:22:21.222870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 23:22:21.226864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 23:22:21.234143 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 23:22:21.237681 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 23:22:21.241412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 23:22:21.248191 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 23:22:21.251455 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 23:22:21.255073 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 23:22:21.261438 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 23:22:21.264947 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 23:22:21.268352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 23:22:21.274937 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 23:22:21.281775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 23:22:21.288306 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 23:22:21.291843 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 23:22:21.298264 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 23:22:21.305102 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 23:22:21.308608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 23:22:21.316383 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 23:22:21.319755 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 23:22:21.326491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 23:22:21.333673 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 23:22:21.337557 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 23:22:21.344076 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 23:22:21.347672 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 23:22:21.354131 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 23:22:21.357691 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 23:22:21.361152 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 23:22:21.368479 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 23:22:21.372385 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 23:22:21.376235 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 23:22:21.383503 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 23:22:21.387083 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 23:22:21.394565 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 23:22:21.398171 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 23:22:21.401593 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 23:22:21.407829 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 23:22:21.411453 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 23:22:21.415010 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 23:22:21.421594 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 23:22:21.424893 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 23:22:21.428112 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 23:22:21.434782 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 23:22:21.438008 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 23:22:21.441357 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 23:22:21.444767 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 23:22:21.451411 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 23:22:21.454709 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 23:22:21.457844 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 23:22:21.467772 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 23:22:21.474692 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 23:22:21.477920 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 23:22:21.488223 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 23:22:21.494822 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 23:22:21.501397 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 23:22:21.504930 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 23:22:21.508161 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 23:22:21.516540 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x15
473 23:22:21.523239 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 23:22:21.526310 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
475 23:22:21.532719 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 23:22:21.541225 [RTC]rtc_get_frequency_meter,154: input=15, output=794
477 23:22:21.544448 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 23:22:21.551002 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 23:22:21.554295 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 23:22:21.557968 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 23:22:21.561353 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 23:22:21.564369 ADC[4]: Raw value=898890 ID=7
483 23:22:21.567875 ADC[3]: Raw value=213070 ID=1
484 23:22:21.571216 RAM Code: 0x71
485 23:22:21.574569 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 23:22:21.577751 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 23:22:21.587905 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 23:22:21.594992 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 23:22:21.598130 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 23:22:21.601593 in-header: 03 07 00 00 08 00 00 00
491 23:22:21.604739 in-data: aa e4 47 04 13 02 00 00
492 23:22:21.608319 Chrome EC: UHEPI supported
493 23:22:21.611784 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 23:22:21.616169 in-header: 03 d5 00 00 08 00 00 00
495 23:22:21.619604 in-data: 98 20 60 08 00 00 00 00
496 23:22:21.623334 MRC: failed to locate region type 0.
497 23:22:21.630466 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 23:22:21.634045 DRAM-K: Running full calibration
499 23:22:21.640947 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 23:22:21.641030 header.status = 0x0
501 23:22:21.644456 header.version = 0x6 (expected: 0x6)
502 23:22:21.648036 header.size = 0xd00 (expected: 0xd00)
503 23:22:21.648118 header.flags = 0x0
504 23:22:21.654650 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 23:22:21.673090 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
506 23:22:21.679742 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 23:22:21.683230 dram_init: ddr_geometry: 2
508 23:22:21.686332 [EMI] MDL number = 2
509 23:22:21.686418 [EMI] Get MDL freq = 0
510 23:22:21.689656 dram_init: ddr_type: 0
511 23:22:21.689737 is_discrete_lpddr4: 1
512 23:22:21.693107 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 23:22:21.693189
514 23:22:21.693253
515 23:22:21.696322 [Bian_co] ETT version 0.0.0.1
516 23:22:21.703139 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 23:22:21.703221
518 23:22:21.706433 dramc_set_vcore_voltage set vcore to 650000
519 23:22:21.706621 Read voltage for 800, 4
520 23:22:21.709846 Vio18 = 0
521 23:22:21.709930 Vcore = 650000
522 23:22:21.709996 Vdram = 0
523 23:22:21.713087 Vddq = 0
524 23:22:21.713169 Vmddr = 0
525 23:22:21.716377 dram_init: config_dvfs: 1
526 23:22:21.719848 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 23:22:21.726518 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 23:22:21.730007 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
529 23:22:21.733193 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
530 23:22:21.736831 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 23:22:21.740003 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 23:22:21.743179 MEM_TYPE=3, freq_sel=18
533 23:22:21.746687 sv_algorithm_assistance_LP4_1600
534 23:22:21.749838 ============ PULL DRAM RESETB DOWN ============
535 23:22:21.753459 ========== PULL DRAM RESETB DOWN end =========
536 23:22:21.760093 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 23:22:21.763215 ===================================
538 23:22:21.763299 LPDDR4 DRAM CONFIGURATION
539 23:22:21.766731 ===================================
540 23:22:21.769838 EX_ROW_EN[0] = 0x0
541 23:22:21.773270 EX_ROW_EN[1] = 0x0
542 23:22:21.773353 LP4Y_EN = 0x0
543 23:22:21.776488 WORK_FSP = 0x0
544 23:22:21.776572 WL = 0x2
545 23:22:21.780073 RL = 0x2
546 23:22:21.780156 BL = 0x2
547 23:22:21.783789 RPST = 0x0
548 23:22:21.783873 RD_PRE = 0x0
549 23:22:21.786657 WR_PRE = 0x1
550 23:22:21.786741 WR_PST = 0x0
551 23:22:21.790251 DBI_WR = 0x0
552 23:22:21.790335 DBI_RD = 0x0
553 23:22:21.793381 OTF = 0x1
554 23:22:21.796894 ===================================
555 23:22:21.800447 ===================================
556 23:22:21.800532 ANA top config
557 23:22:21.804039 ===================================
558 23:22:21.807583 DLL_ASYNC_EN = 0
559 23:22:21.807666 ALL_SLAVE_EN = 1
560 23:22:21.810878 NEW_RANK_MODE = 1
561 23:22:21.814563 DLL_IDLE_MODE = 1
562 23:22:21.818482 LP45_APHY_COMB_EN = 1
563 23:22:21.818599 TX_ODT_DIS = 1
564 23:22:21.822090 NEW_8X_MODE = 1
565 23:22:21.825859 ===================================
566 23:22:21.829724 ===================================
567 23:22:21.833462 data_rate = 1600
568 23:22:21.833584 CKR = 1
569 23:22:21.836745 DQ_P2S_RATIO = 8
570 23:22:21.840482 ===================================
571 23:22:21.844007 CA_P2S_RATIO = 8
572 23:22:21.848023 DQ_CA_OPEN = 0
573 23:22:21.848105 DQ_SEMI_OPEN = 0
574 23:22:21.851473 CA_SEMI_OPEN = 0
575 23:22:21.855268 CA_FULL_RATE = 0
576 23:22:21.858976 DQ_CKDIV4_EN = 1
577 23:22:21.859057 CA_CKDIV4_EN = 1
578 23:22:21.862886 CA_PREDIV_EN = 0
579 23:22:21.866402 PH8_DLY = 0
580 23:22:21.866510 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 23:22:21.870272 DQ_AAMCK_DIV = 4
582 23:22:21.873831 CA_AAMCK_DIV = 4
583 23:22:21.877837 CA_ADMCK_DIV = 4
584 23:22:21.877919 DQ_TRACK_CA_EN = 0
585 23:22:21.881393 CA_PICK = 800
586 23:22:21.885198 CA_MCKIO = 800
587 23:22:21.888486 MCKIO_SEMI = 0
588 23:22:21.891831 PLL_FREQ = 3068
589 23:22:21.891913 DQ_UI_PI_RATIO = 32
590 23:22:21.895411 CA_UI_PI_RATIO = 0
591 23:22:21.898422 ===================================
592 23:22:21.902114 ===================================
593 23:22:21.905217 memory_type:LPDDR4
594 23:22:21.908777 GP_NUM : 10
595 23:22:21.908859 SRAM_EN : 1
596 23:22:21.911971 MD32_EN : 0
597 23:22:21.915093 ===================================
598 23:22:21.918671 [ANA_INIT] >>>>>>>>>>>>>>
599 23:22:21.918754 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 23:22:21.922028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 23:22:21.925073 ===================================
602 23:22:21.928463 data_rate = 1600,PCW = 0X7600
603 23:22:21.931779 ===================================
604 23:22:21.935227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 23:22:21.941687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 23:22:21.948333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:22:21.951783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 23:22:21.955138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 23:22:21.959023 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:22:21.962886 [ANA_INIT] flow start
611 23:22:21.962969 [ANA_INIT] PLL >>>>>>>>
612 23:22:21.966157 [ANA_INIT] PLL <<<<<<<<
613 23:22:21.966241 [ANA_INIT] MIDPI >>>>>>>>
614 23:22:21.970255 [ANA_INIT] MIDPI <<<<<<<<
615 23:22:21.973789 [ANA_INIT] DLL >>>>>>>>
616 23:22:21.973873 [ANA_INIT] flow end
617 23:22:21.977340 ============ LP4 DIFF to SE enter ============
618 23:22:21.981229 ============ LP4 DIFF to SE exit ============
619 23:22:21.985150 [ANA_INIT] <<<<<<<<<<<<<
620 23:22:21.988733 [Flow] Enable top DCM control >>>>>
621 23:22:21.992115 [Flow] Enable top DCM control <<<<<
622 23:22:21.996241 Enable DLL master slave shuffle
623 23:22:21.999941 ==============================================================
624 23:22:22.000025 Gating Mode config
625 23:22:22.006890 ==============================================================
626 23:22:22.010330 Config description:
627 23:22:22.017080 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 23:22:22.023632 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 23:22:22.030413 SELPH_MODE 0: By rank 1: By Phase
630 23:22:22.036988 ==============================================================
631 23:22:22.040190 GAT_TRACK_EN = 1
632 23:22:22.040273 RX_GATING_MODE = 2
633 23:22:22.043758 RX_GATING_TRACK_MODE = 2
634 23:22:22.046950 SELPH_MODE = 1
635 23:22:22.050062 PICG_EARLY_EN = 1
636 23:22:22.053615 VALID_LAT_VALUE = 1
637 23:22:22.060041 ==============================================================
638 23:22:22.063269 Enter into Gating configuration >>>>
639 23:22:22.066793 Exit from Gating configuration <<<<
640 23:22:22.070045 Enter into DVFS_PRE_config >>>>>
641 23:22:22.079752 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 23:22:22.083305 Exit from DVFS_PRE_config <<<<<
643 23:22:22.086587 Enter into PICG configuration >>>>
644 23:22:22.090112 Exit from PICG configuration <<<<
645 23:22:22.093243 [RX_INPUT] configuration >>>>>
646 23:22:22.093327 [RX_INPUT] configuration <<<<<
647 23:22:22.100111 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 23:22:22.106578 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 23:22:22.113250 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 23:22:22.116874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 23:22:22.123444 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 23:22:22.130000 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 23:22:22.133307 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 23:22:22.136539 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 23:22:22.143344 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 23:22:22.146768 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 23:22:22.149904 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 23:22:22.156606 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 23:22:22.160102 ===================================
660 23:22:22.160185 LPDDR4 DRAM CONFIGURATION
661 23:22:22.163214 ===================================
662 23:22:22.166721 EX_ROW_EN[0] = 0x0
663 23:22:22.166803 EX_ROW_EN[1] = 0x0
664 23:22:22.170168 LP4Y_EN = 0x0
665 23:22:22.170249 WORK_FSP = 0x0
666 23:22:22.173237 WL = 0x2
667 23:22:22.173318 RL = 0x2
668 23:22:22.176536 BL = 0x2
669 23:22:22.180004 RPST = 0x0
670 23:22:22.180086 RD_PRE = 0x0
671 23:22:22.183324 WR_PRE = 0x1
672 23:22:22.183420 WR_PST = 0x0
673 23:22:22.186793 DBI_WR = 0x0
674 23:22:22.186882 DBI_RD = 0x0
675 23:22:22.190136 OTF = 0x1
676 23:22:22.193442 ===================================
677 23:22:22.196695 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 23:22:22.199904 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 23:22:22.203447 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 23:22:22.206596 ===================================
681 23:22:22.210072 LPDDR4 DRAM CONFIGURATION
682 23:22:22.213278 ===================================
683 23:22:22.216848 EX_ROW_EN[0] = 0x10
684 23:22:22.216931 EX_ROW_EN[1] = 0x0
685 23:22:22.219966 LP4Y_EN = 0x0
686 23:22:22.220055 WORK_FSP = 0x0
687 23:22:22.223435 WL = 0x2
688 23:22:22.223517 RL = 0x2
689 23:22:22.226779 BL = 0x2
690 23:22:22.226861 RPST = 0x0
691 23:22:22.229936 RD_PRE = 0x0
692 23:22:22.230044 WR_PRE = 0x1
693 23:22:22.233184 WR_PST = 0x0
694 23:22:22.233266 DBI_WR = 0x0
695 23:22:22.236614 DBI_RD = 0x0
696 23:22:22.236696 OTF = 0x1
697 23:22:22.240138 ===================================
698 23:22:22.246708 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 23:22:22.251538 nWR fixed to 40
700 23:22:22.254907 [ModeRegInit_LP4] CH0 RK0
701 23:22:22.255012 [ModeRegInit_LP4] CH0 RK1
702 23:22:22.258123 [ModeRegInit_LP4] CH1 RK0
703 23:22:22.261636 [ModeRegInit_LP4] CH1 RK1
704 23:22:22.261718 match AC timing 13
705 23:22:22.268151 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 23:22:22.271664 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 23:22:22.274904 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 23:22:22.281458 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 23:22:22.284894 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 23:22:22.284994 [EMI DOE] emi_dcm 0
711 23:22:22.291471 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 23:22:22.291554 ==
713 23:22:22.294691 Dram Type= 6, Freq= 0, CH_0, rank 0
714 23:22:22.298332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 23:22:22.298412 ==
716 23:22:22.304758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 23:22:22.311315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 23:22:22.319127 [CA 0] Center 38 (7~69) winsize 63
719 23:22:22.322253 [CA 1] Center 37 (7~68) winsize 62
720 23:22:22.325691 [CA 2] Center 35 (5~66) winsize 62
721 23:22:22.329212 [CA 3] Center 35 (5~66) winsize 62
722 23:22:22.332390 [CA 4] Center 34 (4~65) winsize 62
723 23:22:22.335873 [CA 5] Center 34 (3~65) winsize 63
724 23:22:22.335955
725 23:22:22.339105 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 23:22:22.339186
727 23:22:22.342554 [CATrainingPosCal] consider 1 rank data
728 23:22:22.345833 u2DelayCellTimex100 = 270/100 ps
729 23:22:22.349258 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
730 23:22:22.352471 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
731 23:22:22.359218 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
732 23:22:22.362375 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
733 23:22:22.365677 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
734 23:22:22.369021 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
735 23:22:22.369133
736 23:22:22.372565 CA PerBit enable=1, Macro0, CA PI delay=34
737 23:22:22.372647
738 23:22:22.375713 [CBTSetCACLKResult] CA Dly = 34
739 23:22:22.375794 CS Dly: 5 (0~36)
740 23:22:22.375860 ==
741 23:22:22.379215 Dram Type= 6, Freq= 0, CH_0, rank 1
742 23:22:22.386276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 23:22:22.386360 ==
744 23:22:22.390277 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 23:22:22.397133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 23:22:22.405870 [CA 0] Center 38 (7~69) winsize 63
747 23:22:22.409363 [CA 1] Center 38 (7~69) winsize 63
748 23:22:22.412858 [CA 2] Center 35 (5~66) winsize 62
749 23:22:22.416534 [CA 3] Center 35 (5~66) winsize 62
750 23:22:22.420280 [CA 4] Center 34 (4~65) winsize 62
751 23:22:22.423885 [CA 5] Center 34 (4~65) winsize 62
752 23:22:22.423968
753 23:22:22.427515 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 23:22:22.427607
755 23:22:22.431389 [CATrainingPosCal] consider 2 rank data
756 23:22:22.431473 u2DelayCellTimex100 = 270/100 ps
757 23:22:22.434997 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
758 23:22:22.438788 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
759 23:22:22.442770 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
760 23:22:22.446256 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
761 23:22:22.449753 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
762 23:22:22.453430 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
763 23:22:22.453551
764 23:22:22.457102 CA PerBit enable=1, Macro0, CA PI delay=34
765 23:22:22.457185
766 23:22:22.461190 [CBTSetCACLKResult] CA Dly = 34
767 23:22:22.464741 CS Dly: 6 (0~38)
768 23:22:22.464825
769 23:22:22.468305 ----->DramcWriteLeveling(PI) begin...
770 23:22:22.468390 ==
771 23:22:22.472267 Dram Type= 6, Freq= 0, CH_0, rank 0
772 23:22:22.475603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 23:22:22.475688 ==
774 23:22:22.479457 Write leveling (Byte 0): 35 => 35
775 23:22:22.479554 Write leveling (Byte 1): 31 => 31
776 23:22:22.483302 DramcWriteLeveling(PI) end<-----
777 23:22:22.483385
778 23:22:22.483452 ==
779 23:22:22.486833 Dram Type= 6, Freq= 0, CH_0, rank 0
780 23:22:22.490289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 23:22:22.490373 ==
782 23:22:22.493803 [Gating] SW mode calibration
783 23:22:22.501306 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 23:22:22.505157 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 23:22:22.512791 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 23:22:22.516406 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:22:22.520774 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
788 23:22:22.523884 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 23:22:22.527790 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:22:22.531540 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:22:22.539144 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:22:22.542708 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:22:22.546215 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:22:22.550055 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:22:22.553776 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:22:22.561147 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:22:22.564917 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:22:22.568521 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:22:22.572467 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:22:22.575757 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:22:22.583028 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:22:22.586821 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:22:22.590500 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 23:22:22.594003 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
805 23:22:22.597438 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:22:22.605070 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:22:22.608820 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:22:22.612343 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:22:22.615865 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:22:22.619736 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:22:22.627264 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:22:22.631123 0 9 12 | B1->B0 | 2626 3333 | 0 1 | (0 0) (1 1)
813 23:22:22.634517 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 23:22:22.638364 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:22:22.642084 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:22:22.649291 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:22:22.652874 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:22:22.656774 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:22:22.660673 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
820 23:22:22.663771 0 10 12 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
821 23:22:22.671028 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 23:22:22.674876 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:22:22.678487 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:22:22.681875 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:22:22.685734 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:22:22.692876 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:22:22.697078 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
828 23:22:22.700538 0 11 12 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
829 23:22:22.704484 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
830 23:22:22.707692 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:22:22.714790 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:22:22.717945 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:22:22.721088 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:22:22.727753 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:22:22.731065 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 23:22:22.734546 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 23:22:22.741155 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:22:22.744687 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:22:22.747816 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:22:22.751426 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:22:22.757745 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:22:22.761244 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:22:22.764477 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:22:22.771257 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:22:22.774764 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:22:22.778132 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:22:22.784666 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:22:22.787757 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:22:22.791224 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:22:22.797986 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:22:22.801041 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 23:22:22.804639 Total UI for P1: 0, mck2ui 16
853 23:22:22.807792 best dqsien dly found for B0: ( 0, 14, 6)
854 23:22:22.811273 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
855 23:22:22.817812 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 23:22:22.817894 Total UI for P1: 0, mck2ui 16
857 23:22:22.821320 best dqsien dly found for B1: ( 0, 14, 10)
858 23:22:22.828019 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 23:22:22.831157 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 23:22:22.831239
861 23:22:22.834860 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 23:22:22.837925 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 23:22:22.841167 [Gating] SW calibration Done
864 23:22:22.841249 ==
865 23:22:22.844514 Dram Type= 6, Freq= 0, CH_0, rank 0
866 23:22:22.848106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 23:22:22.848199 ==
868 23:22:22.851219 RX Vref Scan: 0
869 23:22:22.851300
870 23:22:22.851365 RX Vref 0 -> 0, step: 1
871 23:22:22.851425
872 23:22:22.854711 RX Delay -130 -> 252, step: 16
873 23:22:22.857922 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
874 23:22:22.864587 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 23:22:22.867717 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
876 23:22:22.871193 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
877 23:22:22.874417 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 23:22:22.877852 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 23:22:22.884602 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
880 23:22:22.887853 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
881 23:22:22.891091 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
882 23:22:22.894197 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 23:22:22.897300 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 23:22:22.904175 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
885 23:22:22.907387 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
886 23:22:22.910908 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
887 23:22:22.913924 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
888 23:22:22.917497 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
889 23:22:22.920573 ==
890 23:22:22.924004 Dram Type= 6, Freq= 0, CH_0, rank 0
891 23:22:22.927263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 23:22:22.927346 ==
893 23:22:22.927410 DQS Delay:
894 23:22:22.930816 DQS0 = 0, DQS1 = 0
895 23:22:22.930898 DQM Delay:
896 23:22:22.933910 DQM0 = 81, DQM1 = 69
897 23:22:22.933991 DQ Delay:
898 23:22:22.937256 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
899 23:22:22.940749 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
900 23:22:22.943828 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
901 23:22:22.947280 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
902 23:22:22.947362
903 23:22:22.947426
904 23:22:22.947486 ==
905 23:22:22.950794 Dram Type= 6, Freq= 0, CH_0, rank 0
906 23:22:22.954651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 23:22:22.954733 ==
908 23:22:22.954798
909 23:22:22.954858
910 23:22:22.958126 TX Vref Scan disable
911 23:22:22.958207 == TX Byte 0 ==
912 23:22:22.964412 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
913 23:22:22.967776 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
914 23:22:22.967871 == TX Byte 1 ==
915 23:22:22.974906 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 23:22:22.977703 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 23:22:22.977785 ==
918 23:22:22.981395 Dram Type= 6, Freq= 0, CH_0, rank 0
919 23:22:22.984435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 23:22:22.984517 ==
921 23:22:22.998920 TX Vref=22, minBit 9, minWin=26, winSum=431
922 23:22:23.002502 TX Vref=24, minBit 14, minWin=26, winSum=437
923 23:22:23.005596 TX Vref=26, minBit 11, minWin=26, winSum=439
924 23:22:23.008997 TX Vref=28, minBit 5, minWin=27, winSum=442
925 23:22:23.012301 TX Vref=30, minBit 4, minWin=27, winSum=443
926 23:22:23.018936 TX Vref=32, minBit 9, minWin=27, winSum=442
927 23:22:23.022464 [TxChooseVref] Worse bit 4, Min win 27, Win sum 443, Final Vref 30
928 23:22:23.022546
929 23:22:23.025538 Final TX Range 1 Vref 30
930 23:22:23.025620
931 23:22:23.025685 ==
932 23:22:23.028925 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:22:23.032521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:22:23.032604 ==
935 23:22:23.032669
936 23:22:23.035518
937 23:22:23.035599 TX Vref Scan disable
938 23:22:23.039308 == TX Byte 0 ==
939 23:22:23.042584 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
940 23:22:23.045724 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
941 23:22:23.049196 == TX Byte 1 ==
942 23:22:23.052290 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
943 23:22:23.055798 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
944 23:22:23.059248
945 23:22:23.059329 [DATLAT]
946 23:22:23.059393 Freq=800, CH0 RK0
947 23:22:23.059454
948 23:22:23.062376 DATLAT Default: 0xa
949 23:22:23.062449 0, 0xFFFF, sum = 0
950 23:22:23.065881 1, 0xFFFF, sum = 0
951 23:22:23.065957 2, 0xFFFF, sum = 0
952 23:22:23.069369 3, 0xFFFF, sum = 0
953 23:22:23.069440 4, 0xFFFF, sum = 0
954 23:22:23.072493 5, 0xFFFF, sum = 0
955 23:22:23.072567 6, 0xFFFF, sum = 0
956 23:22:23.075666 7, 0xFFFF, sum = 0
957 23:22:23.079100 8, 0xFFFF, sum = 0
958 23:22:23.079171 9, 0x0, sum = 1
959 23:22:23.079233 10, 0x0, sum = 2
960 23:22:23.082419 11, 0x0, sum = 3
961 23:22:23.082490 12, 0x0, sum = 4
962 23:22:23.085984 best_step = 10
963 23:22:23.086061
964 23:22:23.086122 ==
965 23:22:23.089112 Dram Type= 6, Freq= 0, CH_0, rank 0
966 23:22:23.092502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 23:22:23.092583 ==
968 23:22:23.095747 RX Vref Scan: 1
969 23:22:23.095833
970 23:22:23.095947 Set Vref Range= 32 -> 127
971 23:22:23.096010
972 23:22:23.099315 RX Vref 32 -> 127, step: 1
973 23:22:23.099386
974 23:22:23.102406 RX Delay -111 -> 252, step: 8
975 23:22:23.102478
976 23:22:23.105928 Set Vref, RX VrefLevel [Byte0]: 32
977 23:22:23.109317 [Byte1]: 32
978 23:22:23.109419
979 23:22:23.112410 Set Vref, RX VrefLevel [Byte0]: 33
980 23:22:23.115846 [Byte1]: 33
981 23:22:23.119659
982 23:22:23.119731 Set Vref, RX VrefLevel [Byte0]: 34
983 23:22:23.122733 [Byte1]: 34
984 23:22:23.127059
985 23:22:23.127131 Set Vref, RX VrefLevel [Byte0]: 35
986 23:22:23.130521 [Byte1]: 35
987 23:22:23.134795
988 23:22:23.134869 Set Vref, RX VrefLevel [Byte0]: 36
989 23:22:23.138211 [Byte1]: 36
990 23:22:23.142673
991 23:22:23.142745 Set Vref, RX VrefLevel [Byte0]: 37
992 23:22:23.145734 [Byte1]: 37
993 23:22:23.150062
994 23:22:23.150137 Set Vref, RX VrefLevel [Byte0]: 38
995 23:22:23.153674 [Byte1]: 38
996 23:22:23.157714
997 23:22:23.157792 Set Vref, RX VrefLevel [Byte0]: 39
998 23:22:23.161021 [Byte1]: 39
999 23:22:23.165324
1000 23:22:23.165404 Set Vref, RX VrefLevel [Byte0]: 40
1001 23:22:23.168794 [Byte1]: 40
1002 23:22:23.173060
1003 23:22:23.173138 Set Vref, RX VrefLevel [Byte0]: 41
1004 23:22:23.176559 [Byte1]: 41
1005 23:22:23.180761
1006 23:22:23.180835 Set Vref, RX VrefLevel [Byte0]: 42
1007 23:22:23.183895 [Byte1]: 42
1008 23:22:23.188623
1009 23:22:23.188695 Set Vref, RX VrefLevel [Byte0]: 43
1010 23:22:23.191743 [Byte1]: 43
1011 23:22:23.196034
1012 23:22:23.196113 Set Vref, RX VrefLevel [Byte0]: 44
1013 23:22:23.199235 [Byte1]: 44
1014 23:22:23.203686
1015 23:22:23.203761 Set Vref, RX VrefLevel [Byte0]: 45
1016 23:22:23.206925 [Byte1]: 45
1017 23:22:23.211649
1018 23:22:23.211724 Set Vref, RX VrefLevel [Byte0]: 46
1019 23:22:23.215271 [Byte1]: 46
1020 23:22:23.219325
1021 23:22:23.219407 Set Vref, RX VrefLevel [Byte0]: 47
1022 23:22:23.222718 [Byte1]: 47
1023 23:22:23.227099
1024 23:22:23.227181 Set Vref, RX VrefLevel [Byte0]: 48
1025 23:22:23.230210 [Byte1]: 48
1026 23:22:23.234738
1027 23:22:23.234809 Set Vref, RX VrefLevel [Byte0]: 49
1028 23:22:23.238192 [Byte1]: 49
1029 23:22:23.242524
1030 23:22:23.242596 Set Vref, RX VrefLevel [Byte0]: 50
1031 23:22:23.245639 [Byte1]: 50
1032 23:22:23.249529
1033 23:22:23.249602 Set Vref, RX VrefLevel [Byte0]: 51
1034 23:22:23.252850 [Byte1]: 51
1035 23:22:23.257209
1036 23:22:23.257280 Set Vref, RX VrefLevel [Byte0]: 52
1037 23:22:23.260352 [Byte1]: 52
1038 23:22:23.264904
1039 23:22:23.264977 Set Vref, RX VrefLevel [Byte0]: 53
1040 23:22:23.268037 [Byte1]: 53
1041 23:22:23.272368
1042 23:22:23.272450 Set Vref, RX VrefLevel [Byte0]: 54
1043 23:22:23.275858 [Byte1]: 54
1044 23:22:23.280271
1045 23:22:23.280343 Set Vref, RX VrefLevel [Byte0]: 55
1046 23:22:23.283401 [Byte1]: 55
1047 23:22:23.287735
1048 23:22:23.287805 Set Vref, RX VrefLevel [Byte0]: 56
1049 23:22:23.291195 [Byte1]: 56
1050 23:22:23.295190
1051 23:22:23.295260 Set Vref, RX VrefLevel [Byte0]: 57
1052 23:22:23.298567 [Byte1]: 57
1053 23:22:23.302819
1054 23:22:23.302900 Set Vref, RX VrefLevel [Byte0]: 58
1055 23:22:23.306180 [Byte1]: 58
1056 23:22:23.310839
1057 23:22:23.310919 Set Vref, RX VrefLevel [Byte0]: 59
1058 23:22:23.313758 [Byte1]: 59
1059 23:22:23.318331
1060 23:22:23.318411 Set Vref, RX VrefLevel [Byte0]: 60
1061 23:22:23.321428 [Byte1]: 60
1062 23:22:23.325909
1063 23:22:23.325989 Set Vref, RX VrefLevel [Byte0]: 61
1064 23:22:23.329082 [Byte1]: 61
1065 23:22:23.333440
1066 23:22:23.333537 Set Vref, RX VrefLevel [Byte0]: 62
1067 23:22:23.337091 [Byte1]: 62
1068 23:22:23.341156
1069 23:22:23.341245 Set Vref, RX VrefLevel [Byte0]: 63
1070 23:22:23.344682 [Byte1]: 63
1071 23:22:23.348993
1072 23:22:23.349080 Set Vref, RX VrefLevel [Byte0]: 64
1073 23:22:23.352133 [Byte1]: 64
1074 23:22:23.356849
1075 23:22:23.356933 Set Vref, RX VrefLevel [Byte0]: 65
1076 23:22:23.359940 [Byte1]: 65
1077 23:22:23.364257
1078 23:22:23.364345 Set Vref, RX VrefLevel [Byte0]: 66
1079 23:22:23.367616 [Byte1]: 66
1080 23:22:23.371918
1081 23:22:23.371996 Set Vref, RX VrefLevel [Byte0]: 67
1082 23:22:23.375101 [Byte1]: 67
1083 23:22:23.379362
1084 23:22:23.379441 Set Vref, RX VrefLevel [Byte0]: 68
1085 23:22:23.382628 [Byte1]: 68
1086 23:22:23.387246
1087 23:22:23.387324 Set Vref, RX VrefLevel [Byte0]: 69
1088 23:22:23.390505 [Byte1]: 69
1089 23:22:23.394873
1090 23:22:23.394949 Set Vref, RX VrefLevel [Byte0]: 70
1091 23:22:23.397965 [Byte1]: 70
1092 23:22:23.402498
1093 23:22:23.402575 Set Vref, RX VrefLevel [Byte0]: 71
1094 23:22:23.405678 [Byte1]: 71
1095 23:22:23.409858
1096 23:22:23.409934 Set Vref, RX VrefLevel [Byte0]: 72
1097 23:22:23.413379 [Byte1]: 72
1098 23:22:23.417685
1099 23:22:23.417762 Set Vref, RX VrefLevel [Byte0]: 73
1100 23:22:23.421055 [Byte1]: 73
1101 23:22:23.425392
1102 23:22:23.425548 Set Vref, RX VrefLevel [Byte0]: 74
1103 23:22:23.428713 [Byte1]: 74
1104 23:22:23.433015
1105 23:22:23.433090 Set Vref, RX VrefLevel [Byte0]: 75
1106 23:22:23.436189 [Byte1]: 75
1107 23:22:23.440412
1108 23:22:23.440488 Set Vref, RX VrefLevel [Byte0]: 76
1109 23:22:23.444145 [Byte1]: 76
1110 23:22:23.448201
1111 23:22:23.448278 Set Vref, RX VrefLevel [Byte0]: 77
1112 23:22:23.451544 [Byte1]: 77
1113 23:22:23.455824
1114 23:22:23.455907 Final RX Vref Byte 0 = 63 to rank0
1115 23:22:23.459334 Final RX Vref Byte 1 = 62 to rank0
1116 23:22:23.462803 Final RX Vref Byte 0 = 63 to rank1
1117 23:22:23.465894 Final RX Vref Byte 1 = 62 to rank1==
1118 23:22:23.469081 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 23:22:23.475833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 23:22:23.475916 ==
1121 23:22:23.475981 DQS Delay:
1122 23:22:23.476040 DQS0 = 0, DQS1 = 0
1123 23:22:23.479471 DQM Delay:
1124 23:22:23.479545 DQM0 = 81, DQM1 = 68
1125 23:22:23.482742 DQ Delay:
1126 23:22:23.486061 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1127 23:22:23.486141 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1128 23:22:23.489294 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1129 23:22:23.492681 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1130 23:22:23.495887
1131 23:22:23.495991
1132 23:22:23.502411 [DQSOSCAuto] RK0, (LSB)MR18= 0x2423, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1133 23:22:23.505788 CH0 RK0: MR19=606, MR18=2423
1134 23:22:23.512435 CH0_RK0: MR19=0x606, MR18=0x2423, DQSOSC=400, MR23=63, INC=92, DEC=61
1135 23:22:23.512521
1136 23:22:23.515659 ----->DramcWriteLeveling(PI) begin...
1137 23:22:23.515733 ==
1138 23:22:23.519106 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 23:22:23.522542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 23:22:23.522619 ==
1141 23:22:23.525705 Write leveling (Byte 0): 34 => 34
1142 23:22:23.529170 Write leveling (Byte 1): 30 => 30
1143 23:22:23.532600 DramcWriteLeveling(PI) end<-----
1144 23:22:23.532672
1145 23:22:23.532733 ==
1146 23:22:23.535774 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 23:22:23.539316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 23:22:23.539390 ==
1149 23:22:23.542654 [Gating] SW mode calibration
1150 23:22:23.548970 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 23:22:23.555737 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 23:22:23.559220 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 23:22:23.562339 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1154 23:22:23.568974 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 23:22:23.572418 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:22:23.575979 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:22:23.582677 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:22:23.585651 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:22:23.589314 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:22:23.595952 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:22:23.599213 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:22:23.602735 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:22:23.606089 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:22:23.612736 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:22:23.615774 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:22:23.619211 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:22:23.625877 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:22:23.670325 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:22:23.670592 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1170 23:22:23.670668 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1171 23:22:23.670768 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1172 23:22:23.671245 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:22:23.671521 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:22:23.671780 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:22:23.671847 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:22:23.672160 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:22:23.672422 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:22:23.714033 0 9 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1179 23:22:23.714451 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1180 23:22:23.714531 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:22:23.714792 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 23:22:23.714859 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 23:22:23.715106 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 23:22:23.715364 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 23:22:23.715431 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1186 23:22:23.715491 0 10 8 | B1->B0 | 3333 2a2a | 0 1 | (0 0) (1 0)
1187 23:22:23.715813 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:22:23.758184 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:22:23.758463 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:22:23.758535 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:22:23.758610 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 23:22:23.758797 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:22:23.758896 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1194 23:22:23.759005 0 11 8 | B1->B0 | 2c2c 3838 | 0 0 | (0 0) (0 0)
1195 23:22:23.759071 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1196 23:22:23.759151 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:22:23.759219 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:22:23.802392 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 23:22:23.802777 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 23:22:23.802851 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 23:22:23.803115 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1202 23:22:23.803201 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 23:22:23.803274 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:22:23.803355 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:22:23.803431 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:22:23.803501 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:22:23.803560 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:22:23.816268 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:22:23.816532 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:22:23.816603 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:22:23.819641 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:22:23.822665 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:22:23.826148 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:22:23.832856 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:22:23.836022 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:22:23.839420 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:22:23.846152 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 23:22:23.849402 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 23:22:23.852934 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 23:22:23.856264 Total UI for P1: 0, mck2ui 16
1221 23:22:23.859430 best dqsien dly found for B0: ( 0, 14, 8)
1222 23:22:23.862894 Total UI for P1: 0, mck2ui 16
1223 23:22:23.865941 best dqsien dly found for B1: ( 0, 14, 8)
1224 23:22:23.869442 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1225 23:22:23.872565 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 23:22:23.872642
1227 23:22:23.876206 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 23:22:23.882868 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 23:22:23.882952 [Gating] SW calibration Done
1230 23:22:23.883017 ==
1231 23:22:23.886101 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 23:22:23.892678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 23:22:23.892754 ==
1234 23:22:23.892818 RX Vref Scan: 0
1235 23:22:23.892891
1236 23:22:23.895987 RX Vref 0 -> 0, step: 1
1237 23:22:23.896060
1238 23:22:23.899408 RX Delay -130 -> 252, step: 16
1239 23:22:23.902762 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1240 23:22:23.905971 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1241 23:22:23.909431 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1242 23:22:23.915951 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1243 23:22:23.919481 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1244 23:22:23.922849 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1245 23:22:23.926073 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1246 23:22:23.929163 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1247 23:22:23.935846 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1248 23:22:23.939406 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1249 23:22:23.942324 iDelay=222, Bit 10, Center 61 (-66 ~ 189) 256
1250 23:22:23.945793 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1251 23:22:23.949078 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1252 23:22:23.955980 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1253 23:22:23.958947 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1254 23:22:23.962362 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1255 23:22:23.962434 ==
1256 23:22:23.965814 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 23:22:23.969233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 23:22:23.969304 ==
1259 23:22:23.972496 DQS Delay:
1260 23:22:23.972567 DQS0 = 0, DQS1 = 0
1261 23:22:23.975661 DQM Delay:
1262 23:22:23.975727 DQM0 = 77, DQM1 = 68
1263 23:22:23.975786 DQ Delay:
1264 23:22:23.979235 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1265 23:22:23.982351 DQ4 =77, DQ5 =61, DQ6 =93, DQ7 =93
1266 23:22:23.985835 DQ8 =61, DQ9 =53, DQ10 =61, DQ11 =61
1267 23:22:23.988952 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1268 23:22:23.989019
1269 23:22:23.989079
1270 23:22:23.992450 ==
1271 23:22:23.992520 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 23:22:23.999111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 23:22:23.999215 ==
1274 23:22:23.999302
1275 23:22:23.999368
1276 23:22:24.002196 TX Vref Scan disable
1277 23:22:24.002267 == TX Byte 0 ==
1278 23:22:24.005794 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1279 23:22:24.012525 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1280 23:22:24.012601 == TX Byte 1 ==
1281 23:22:24.015632 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1282 23:22:24.022313 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1283 23:22:24.022391 ==
1284 23:22:24.025806 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 23:22:24.028796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 23:22:24.028873 ==
1287 23:22:24.042470 TX Vref=22, minBit 2, minWin=27, winSum=437
1288 23:22:24.045772 TX Vref=24, minBit 1, minWin=27, winSum=438
1289 23:22:24.049201 TX Vref=26, minBit 1, minWin=27, winSum=441
1290 23:22:24.052257 TX Vref=28, minBit 11, minWin=26, winSum=438
1291 23:22:24.055714 TX Vref=30, minBit 1, minWin=27, winSum=442
1292 23:22:24.062505 TX Vref=32, minBit 11, minWin=26, winSum=440
1293 23:22:24.065707 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 30
1294 23:22:24.065782
1295 23:22:24.069114 Final TX Range 1 Vref 30
1296 23:22:24.069184
1297 23:22:24.069244 ==
1298 23:22:24.072627 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 23:22:24.075819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 23:22:24.075893 ==
1301 23:22:24.078979
1302 23:22:24.079050
1303 23:22:24.079110 TX Vref Scan disable
1304 23:22:24.082547 == TX Byte 0 ==
1305 23:22:24.086092 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1306 23:22:24.089208 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1307 23:22:24.092797 == TX Byte 1 ==
1308 23:22:24.095877 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1309 23:22:24.099398 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1310 23:22:24.102497
1311 23:22:24.102580 [DATLAT]
1312 23:22:24.102644 Freq=800, CH0 RK1
1313 23:22:24.102705
1314 23:22:24.106025 DATLAT Default: 0xa
1315 23:22:24.106098 0, 0xFFFF, sum = 0
1316 23:22:24.109092 1, 0xFFFF, sum = 0
1317 23:22:24.109167 2, 0xFFFF, sum = 0
1318 23:22:24.112556 3, 0xFFFF, sum = 0
1319 23:22:24.112631 4, 0xFFFF, sum = 0
1320 23:22:24.116064 5, 0xFFFF, sum = 0
1321 23:22:24.116145 6, 0xFFFF, sum = 0
1322 23:22:24.119194 7, 0xFFFF, sum = 0
1323 23:22:24.122780 8, 0xFFFF, sum = 0
1324 23:22:24.122854 9, 0x0, sum = 1
1325 23:22:24.122924 10, 0x0, sum = 2
1326 23:22:24.125978 11, 0x0, sum = 3
1327 23:22:24.126051 12, 0x0, sum = 4
1328 23:22:24.129233 best_step = 10
1329 23:22:24.129304
1330 23:22:24.129372 ==
1331 23:22:24.132467 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 23:22:24.136004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 23:22:24.136085 ==
1334 23:22:24.139309 RX Vref Scan: 0
1335 23:22:24.139399
1336 23:22:24.139460 RX Vref 0 -> 0, step: 1
1337 23:22:24.139527
1338 23:22:24.142473 RX Delay -111 -> 252, step: 8
1339 23:22:24.149400 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1340 23:22:24.152801 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1341 23:22:24.156170 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1342 23:22:24.159336 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1343 23:22:24.162698 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1344 23:22:24.169228 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1345 23:22:24.172572 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1346 23:22:24.175906 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1347 23:22:24.179232 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1348 23:22:24.182671 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1349 23:22:24.189159 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1350 23:22:24.192649 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1351 23:22:24.195779 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1352 23:22:24.199236 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1353 23:22:24.206053 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1354 23:22:24.209133 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1355 23:22:24.209212 ==
1356 23:22:24.212743 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 23:22:24.215822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 23:22:24.215925 ==
1359 23:22:24.216013 DQS Delay:
1360 23:22:24.219049 DQS0 = 0, DQS1 = 0
1361 23:22:24.219115 DQM Delay:
1362 23:22:24.222543 DQM0 = 79, DQM1 = 70
1363 23:22:24.222614 DQ Delay:
1364 23:22:24.226088 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1365 23:22:24.229163 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1366 23:22:24.232766 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1367 23:22:24.236091 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =80
1368 23:22:24.236163
1369 23:22:24.236231
1370 23:22:24.242664 [DQSOSCAuto] RK1, (LSB)MR18= 0x451f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1371 23:22:24.246064 CH0 RK1: MR19=606, MR18=451F
1372 23:22:24.252857 CH0_RK1: MR19=0x606, MR18=0x451F, DQSOSC=392, MR23=63, INC=96, DEC=64
1373 23:22:24.255956 [RxdqsGatingPostProcess] freq 800
1374 23:22:24.262569 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 23:22:24.266081 Pre-setting of DQS Precalculation
1376 23:22:24.269506 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 23:22:24.269587 ==
1378 23:22:24.272865 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 23:22:24.276061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 23:22:24.276141 ==
1381 23:22:24.282723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 23:22:24.289394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 23:22:24.297659 [CA 0] Center 36 (6~66) winsize 61
1384 23:22:24.301097 [CA 1] Center 36 (6~67) winsize 62
1385 23:22:24.304346 [CA 2] Center 34 (4~64) winsize 61
1386 23:22:24.307619 [CA 3] Center 34 (4~64) winsize 61
1387 23:22:24.311014 [CA 4] Center 34 (4~64) winsize 61
1388 23:22:24.314526 [CA 5] Center 34 (4~64) winsize 61
1389 23:22:24.314606
1390 23:22:24.317731 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1391 23:22:24.317811
1392 23:22:24.321225 [CATrainingPosCal] consider 1 rank data
1393 23:22:24.324401 u2DelayCellTimex100 = 270/100 ps
1394 23:22:24.327815 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1395 23:22:24.331367 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 23:22:24.334485 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 23:22:24.341206 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1398 23:22:24.344692 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1399 23:22:24.347823 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 23:22:24.347904
1401 23:22:24.351275 CA PerBit enable=1, Macro0, CA PI delay=34
1402 23:22:24.351355
1403 23:22:24.354402 [CBTSetCACLKResult] CA Dly = 34
1404 23:22:24.354482 CS Dly: 5 (0~36)
1405 23:22:24.354545 ==
1406 23:22:24.357920 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 23:22:24.364524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 23:22:24.364605 ==
1409 23:22:24.367593 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 23:22:24.374274 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 23:22:24.383814 [CA 0] Center 36 (6~67) winsize 62
1412 23:22:24.387287 [CA 1] Center 36 (6~67) winsize 62
1413 23:22:24.390526 [CA 2] Center 35 (5~65) winsize 61
1414 23:22:24.393937 [CA 3] Center 34 (4~64) winsize 61
1415 23:22:24.397178 [CA 4] Center 34 (4~65) winsize 62
1416 23:22:24.400347 [CA 5] Center 33 (3~64) winsize 62
1417 23:22:24.400428
1418 23:22:24.403733 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 23:22:24.403814
1420 23:22:24.406985 [CATrainingPosCal] consider 2 rank data
1421 23:22:24.410485 u2DelayCellTimex100 = 270/100 ps
1422 23:22:24.413737 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1423 23:22:24.416987 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 23:22:24.423809 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1425 23:22:24.427111 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 23:22:24.430395 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 23:22:24.433725 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 23:22:24.433807
1429 23:22:24.437194 CA PerBit enable=1, Macro0, CA PI delay=34
1430 23:22:24.437275
1431 23:22:24.440723 [CBTSetCACLKResult] CA Dly = 34
1432 23:22:24.440804 CS Dly: 6 (0~38)
1433 23:22:24.440868
1434 23:22:24.443950 ----->DramcWriteLeveling(PI) begin...
1435 23:22:24.444032 ==
1436 23:22:24.447370 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 23:22:24.451122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 23:22:24.455127 ==
1439 23:22:24.455208 Write leveling (Byte 0): 28 => 28
1440 23:22:24.458798 Write leveling (Byte 1): 29 => 29
1441 23:22:24.462228 DramcWriteLeveling(PI) end<-----
1442 23:22:24.462308
1443 23:22:24.462371 ==
1444 23:22:24.465742 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 23:22:24.469527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 23:22:24.469609 ==
1447 23:22:24.473064 [Gating] SW mode calibration
1448 23:22:24.480341 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 23:22:24.483967 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 23:22:24.490823 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 23:22:24.493870 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1452 23:22:24.497247 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 23:22:24.504043 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:22:24.507149 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:22:24.510716 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:22:24.517307 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:22:24.520460 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:22:24.523939 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:22:24.530522 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:22:24.533775 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:22:24.537048 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:22:24.543598 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:22:24.547020 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:22:24.550379 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:22:24.556936 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:22:24.560471 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:22:24.563573 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 23:22:24.567153 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1469 23:22:24.573795 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:22:24.576931 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:22:24.580507 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:22:24.586947 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:22:24.590495 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:22:24.593603 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:22:24.600366 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 23:22:24.603674 0 9 8 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)
1477 23:22:24.606905 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 23:22:24.613575 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 23:22:24.617156 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 23:22:24.620277 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 23:22:24.626943 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 23:22:24.630534 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 23:22:24.633577 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1484 23:22:24.640562 0 10 8 | B1->B0 | 2929 2e2e | 0 0 | (0 1) (0 0)
1485 23:22:24.643771 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:22:24.647171 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:22:24.653556 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:22:24.656951 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:22:24.660278 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 23:22:24.667109 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:22:24.670383 0 11 4 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
1492 23:22:24.673723 0 11 8 | B1->B0 | 3e3e 3939 | 0 1 | (0 0) (0 0)
1493 23:22:24.677084 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 23:22:24.683654 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:22:24.686837 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:22:24.690081 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 23:22:24.696662 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 23:22:24.700130 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 23:22:24.703360 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 23:22:24.710128 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1501 23:22:24.713392 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:22:24.716604 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:22:24.723725 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:22:24.727013 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:22:24.730422 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:22:24.736764 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:22:24.740282 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:22:24.743528 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:22:24.750283 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:22:24.753423 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:22:24.756849 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:22:24.763460 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:22:24.767038 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:22:24.770194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 23:22:24.773441 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 23:22:24.780301 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 23:22:24.783449 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 23:22:24.786961 Total UI for P1: 0, mck2ui 16
1519 23:22:24.790314 best dqsien dly found for B0: ( 0, 14, 6)
1520 23:22:24.793393 Total UI for P1: 0, mck2ui 16
1521 23:22:24.796983 best dqsien dly found for B1: ( 0, 14, 6)
1522 23:22:24.800038 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1523 23:22:24.803637 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1524 23:22:24.803745
1525 23:22:24.806639 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 23:22:24.810149 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1527 23:22:24.813626 [Gating] SW calibration Done
1528 23:22:24.813728 ==
1529 23:22:24.816796 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 23:22:24.820027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 23:22:24.823363 ==
1532 23:22:24.823462 RX Vref Scan: 0
1533 23:22:24.823566
1534 23:22:24.826738 RX Vref 0 -> 0, step: 1
1535 23:22:24.826848
1536 23:22:24.830086 RX Delay -130 -> 252, step: 16
1537 23:22:24.833601 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1538 23:22:24.836765 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1539 23:22:24.840232 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1540 23:22:24.843410 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1541 23:22:24.850290 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1542 23:22:24.853390 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1543 23:22:24.856900 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1544 23:22:24.859990 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1545 23:22:24.863399 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1546 23:22:24.869814 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1547 23:22:24.873208 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1548 23:22:24.876677 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1549 23:22:24.880090 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1550 23:22:24.883496 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1551 23:22:24.890007 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1552 23:22:24.893233 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1553 23:22:24.893338 ==
1554 23:22:24.896789 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 23:22:24.899957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 23:22:24.900068 ==
1557 23:22:24.903404 DQS Delay:
1558 23:22:24.903511 DQS0 = 0, DQS1 = 0
1559 23:22:24.903602 DQM Delay:
1560 23:22:24.906626 DQM0 = 81, DQM1 = 73
1561 23:22:24.906717 DQ Delay:
1562 23:22:24.909929 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1563 23:22:24.913330 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1564 23:22:24.916862 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1565 23:22:24.919857 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1566 23:22:24.919963
1567 23:22:24.920054
1568 23:22:24.920141 ==
1569 23:22:24.923353 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 23:22:24.929904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 23:22:24.930058 ==
1572 23:22:24.930189
1573 23:22:24.930251
1574 23:22:24.930308 TX Vref Scan disable
1575 23:22:24.933217 == TX Byte 0 ==
1576 23:22:24.936609 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1577 23:22:24.940016 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1578 23:22:24.943484 == TX Byte 1 ==
1579 23:22:24.946638 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1580 23:22:24.950091 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1581 23:22:24.953630 ==
1582 23:22:24.956723 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 23:22:24.960093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 23:22:24.960176 ==
1585 23:22:24.972353 TX Vref=22, minBit 8, minWin=27, winSum=446
1586 23:22:24.975547 TX Vref=24, minBit 8, minWin=27, winSum=447
1587 23:22:24.979024 TX Vref=26, minBit 8, minWin=27, winSum=452
1588 23:22:24.982223 TX Vref=28, minBit 11, minWin=27, winSum=458
1589 23:22:24.985706 TX Vref=30, minBit 8, minWin=28, winSum=459
1590 23:22:24.992180 TX Vref=32, minBit 9, minWin=27, winSum=454
1591 23:22:24.995651 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1592 23:22:24.995785
1593 23:22:24.999163 Final TX Range 1 Vref 30
1594 23:22:24.999244
1595 23:22:24.999308 ==
1596 23:22:25.002271 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 23:22:25.005835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 23:22:25.005916 ==
1599 23:22:25.005979
1600 23:22:25.008967
1601 23:22:25.009046 TX Vref Scan disable
1602 23:22:25.012494 == TX Byte 0 ==
1603 23:22:25.015836 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1604 23:22:25.018988 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1605 23:22:25.022443 == TX Byte 1 ==
1606 23:22:25.026384 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1607 23:22:25.030055 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1608 23:22:25.030168
1609 23:22:25.033365 [DATLAT]
1610 23:22:25.033472 Freq=800, CH1 RK0
1611 23:22:25.033599
1612 23:22:25.036794 DATLAT Default: 0xa
1613 23:22:25.036874 0, 0xFFFF, sum = 0
1614 23:22:25.039947 1, 0xFFFF, sum = 0
1615 23:22:25.040029 2, 0xFFFF, sum = 0
1616 23:22:25.043303 3, 0xFFFF, sum = 0
1617 23:22:25.043411 4, 0xFFFF, sum = 0
1618 23:22:25.046627 5, 0xFFFF, sum = 0
1619 23:22:25.046709 6, 0xFFFF, sum = 0
1620 23:22:25.050038 7, 0xFFFF, sum = 0
1621 23:22:25.050122 8, 0xFFFF, sum = 0
1622 23:22:25.053145 9, 0x0, sum = 1
1623 23:22:25.053279 10, 0x0, sum = 2
1624 23:22:25.056670 11, 0x0, sum = 3
1625 23:22:25.056760 12, 0x0, sum = 4
1626 23:22:25.056827 best_step = 10
1627 23:22:25.059849
1628 23:22:25.059920 ==
1629 23:22:25.063360 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 23:22:25.066658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 23:22:25.066731 ==
1632 23:22:25.066792 RX Vref Scan: 1
1633 23:22:25.066853
1634 23:22:25.069759 Set Vref Range= 32 -> 127
1635 23:22:25.069827
1636 23:22:25.073270 RX Vref 32 -> 127, step: 1
1637 23:22:25.073336
1638 23:22:25.076446 RX Delay -111 -> 252, step: 8
1639 23:22:25.076513
1640 23:22:25.079914 Set Vref, RX VrefLevel [Byte0]: 32
1641 23:22:25.083256 [Byte1]: 32
1642 23:22:25.083330
1643 23:22:25.086387 Set Vref, RX VrefLevel [Byte0]: 33
1644 23:22:25.089835 [Byte1]: 33
1645 23:22:25.089915
1646 23:22:25.093253 Set Vref, RX VrefLevel [Byte0]: 34
1647 23:22:25.096715 [Byte1]: 34
1648 23:22:25.100689
1649 23:22:25.100769 Set Vref, RX VrefLevel [Byte0]: 35
1650 23:22:25.103913 [Byte1]: 35
1651 23:22:25.108211
1652 23:22:25.108291 Set Vref, RX VrefLevel [Byte0]: 36
1653 23:22:25.111311 [Byte1]: 36
1654 23:22:25.115867
1655 23:22:25.115946 Set Vref, RX VrefLevel [Byte0]: 37
1656 23:22:25.119131 [Byte1]: 37
1657 23:22:25.123526
1658 23:22:25.123605 Set Vref, RX VrefLevel [Byte0]: 38
1659 23:22:25.126574 [Byte1]: 38
1660 23:22:25.131155
1661 23:22:25.131235 Set Vref, RX VrefLevel [Byte0]: 39
1662 23:22:25.134278 [Byte1]: 39
1663 23:22:25.138866
1664 23:22:25.138946 Set Vref, RX VrefLevel [Byte0]: 40
1665 23:22:25.141876 [Byte1]: 40
1666 23:22:25.146539
1667 23:22:25.146619 Set Vref, RX VrefLevel [Byte0]: 41
1668 23:22:25.149701 [Byte1]: 41
1669 23:22:25.153801
1670 23:22:25.153884 Set Vref, RX VrefLevel [Byte0]: 42
1671 23:22:25.157152 [Byte1]: 42
1672 23:22:25.161735
1673 23:22:25.161813 Set Vref, RX VrefLevel [Byte0]: 43
1674 23:22:25.164926 [Byte1]: 43
1675 23:22:25.169241
1676 23:22:25.172589 Set Vref, RX VrefLevel [Byte0]: 44
1677 23:22:25.175884 [Byte1]: 44
1678 23:22:25.175956
1679 23:22:25.179132 Set Vref, RX VrefLevel [Byte0]: 45
1680 23:22:25.182434 [Byte1]: 45
1681 23:22:25.182500
1682 23:22:25.185867 Set Vref, RX VrefLevel [Byte0]: 46
1683 23:22:25.188865 [Byte1]: 46
1684 23:22:25.192383
1685 23:22:25.192453 Set Vref, RX VrefLevel [Byte0]: 47
1686 23:22:25.195536 [Byte1]: 47
1687 23:22:25.199787
1688 23:22:25.199863 Set Vref, RX VrefLevel [Byte0]: 48
1689 23:22:25.203360 [Byte1]: 48
1690 23:22:25.207705
1691 23:22:25.207780 Set Vref, RX VrefLevel [Byte0]: 49
1692 23:22:25.210805 [Byte1]: 49
1693 23:22:25.215242
1694 23:22:25.215318 Set Vref, RX VrefLevel [Byte0]: 50
1695 23:22:25.218411 [Byte1]: 50
1696 23:22:25.222691
1697 23:22:25.222764 Set Vref, RX VrefLevel [Byte0]: 51
1698 23:22:25.225992 [Byte1]: 51
1699 23:22:25.230545
1700 23:22:25.230619 Set Vref, RX VrefLevel [Byte0]: 52
1701 23:22:25.233773 [Byte1]: 52
1702 23:22:25.238163
1703 23:22:25.238238 Set Vref, RX VrefLevel [Byte0]: 53
1704 23:22:25.241554 [Byte1]: 53
1705 23:22:25.245855
1706 23:22:25.245933 Set Vref, RX VrefLevel [Byte0]: 54
1707 23:22:25.249089 [Byte1]: 54
1708 23:22:25.253279
1709 23:22:25.253357 Set Vref, RX VrefLevel [Byte0]: 55
1710 23:22:25.256761 [Byte1]: 55
1711 23:22:25.261285
1712 23:22:25.261360 Set Vref, RX VrefLevel [Byte0]: 56
1713 23:22:25.264355 [Byte1]: 56
1714 23:22:25.268815
1715 23:22:25.268893 Set Vref, RX VrefLevel [Byte0]: 57
1716 23:22:25.271884 [Byte1]: 57
1717 23:22:25.276188
1718 23:22:25.276260 Set Vref, RX VrefLevel [Byte0]: 58
1719 23:22:25.279752 [Byte1]: 58
1720 23:22:25.283861
1721 23:22:25.283930 Set Vref, RX VrefLevel [Byte0]: 59
1722 23:22:25.287417 [Byte1]: 59
1723 23:22:25.291503
1724 23:22:25.291575 Set Vref, RX VrefLevel [Byte0]: 60
1725 23:22:25.295001 [Byte1]: 60
1726 23:22:25.299139
1727 23:22:25.299214 Set Vref, RX VrefLevel [Byte0]: 61
1728 23:22:25.302473 [Byte1]: 61
1729 23:22:25.307063
1730 23:22:25.307133 Set Vref, RX VrefLevel [Byte0]: 62
1731 23:22:25.310213 [Byte1]: 62
1732 23:22:25.314489
1733 23:22:25.314558 Set Vref, RX VrefLevel [Byte0]: 63
1734 23:22:25.317682 [Byte1]: 63
1735 23:22:25.322265
1736 23:22:25.322336 Set Vref, RX VrefLevel [Byte0]: 64
1737 23:22:25.325386 [Byte1]: 64
1738 23:22:25.329887
1739 23:22:25.329958 Set Vref, RX VrefLevel [Byte0]: 65
1740 23:22:25.333190 [Byte1]: 65
1741 23:22:25.337612
1742 23:22:25.337689 Set Vref, RX VrefLevel [Byte0]: 66
1743 23:22:25.340820 [Byte1]: 66
1744 23:22:25.345247
1745 23:22:25.345318 Set Vref, RX VrefLevel [Byte0]: 67
1746 23:22:25.348425 [Byte1]: 67
1747 23:22:25.352665
1748 23:22:25.352734 Set Vref, RX VrefLevel [Byte0]: 68
1749 23:22:25.355958 [Byte1]: 68
1750 23:22:25.360305
1751 23:22:25.360374 Set Vref, RX VrefLevel [Byte0]: 69
1752 23:22:25.363780 [Byte1]: 69
1753 23:22:25.367986
1754 23:22:25.368060 Set Vref, RX VrefLevel [Byte0]: 70
1755 23:22:25.371338 [Byte1]: 70
1756 23:22:25.375669
1757 23:22:25.375745 Set Vref, RX VrefLevel [Byte0]: 71
1758 23:22:25.379167 [Byte1]: 71
1759 23:22:25.383478
1760 23:22:25.383552 Set Vref, RX VrefLevel [Byte0]: 72
1761 23:22:25.386632 [Byte1]: 72
1762 23:22:25.391127
1763 23:22:25.391203 Set Vref, RX VrefLevel [Byte0]: 73
1764 23:22:25.394206 [Byte1]: 73
1765 23:22:25.398553
1766 23:22:25.398629 Set Vref, RX VrefLevel [Byte0]: 74
1767 23:22:25.401909 [Byte1]: 74
1768 23:22:25.406247
1769 23:22:25.406327 Set Vref, RX VrefLevel [Byte0]: 75
1770 23:22:25.409630 [Byte1]: 75
1771 23:22:25.414088
1772 23:22:25.414161 Set Vref, RX VrefLevel [Byte0]: 76
1773 23:22:25.417299 [Byte1]: 76
1774 23:22:25.421688
1775 23:22:25.421770 Final RX Vref Byte 0 = 55 to rank0
1776 23:22:25.424901 Final RX Vref Byte 1 = 54 to rank0
1777 23:22:25.428486 Final RX Vref Byte 0 = 55 to rank1
1778 23:22:25.431675 Final RX Vref Byte 1 = 54 to rank1==
1779 23:22:25.435107 Dram Type= 6, Freq= 0, CH_1, rank 0
1780 23:22:25.441584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 23:22:25.441666 ==
1782 23:22:25.441730 DQS Delay:
1783 23:22:25.441789 DQS0 = 0, DQS1 = 0
1784 23:22:25.444885 DQM Delay:
1785 23:22:25.444964 DQM0 = 80, DQM1 = 71
1786 23:22:25.448527 DQ Delay:
1787 23:22:25.451792 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1788 23:22:25.451871 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1789 23:22:25.455012 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1790 23:22:25.458145 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
1791 23:22:25.461526
1792 23:22:25.461605
1793 23:22:25.468310 [DQSOSCAuto] RK0, (LSB)MR18= 0xd18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1794 23:22:25.471878 CH1 RK0: MR19=606, MR18=D18
1795 23:22:25.478140 CH1_RK0: MR19=0x606, MR18=0xD18, DQSOSC=403, MR23=63, INC=90, DEC=60
1796 23:22:25.478221
1797 23:22:25.481645 ----->DramcWriteLeveling(PI) begin...
1798 23:22:25.481726 ==
1799 23:22:25.484780 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 23:22:25.488358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 23:22:25.488463 ==
1802 23:22:25.491657 Write leveling (Byte 0): 26 => 26
1803 23:22:25.494772 Write leveling (Byte 1): 30 => 30
1804 23:22:25.498125 DramcWriteLeveling(PI) end<-----
1805 23:22:25.498205
1806 23:22:25.498268 ==
1807 23:22:25.501467 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 23:22:25.504775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 23:22:25.504855 ==
1810 23:22:25.508146 [Gating] SW mode calibration
1811 23:22:25.514797 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1812 23:22:25.521698 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1813 23:22:25.524863 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1814 23:22:25.528279 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1815 23:22:25.535079 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 23:22:25.538529 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 23:22:25.541686 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:22:25.548229 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:22:25.551684 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:22:25.554724 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:22:25.558317 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:22:25.564733 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:22:25.568235 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:22:25.571388 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:22:25.578275 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:22:25.581513 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:22:25.584845 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:22:25.591465 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:22:25.594693 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:22:25.598174 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1831 23:22:25.604830 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1832 23:22:25.608204 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:22:25.611540 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:22:25.618013 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:22:25.621266 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:22:25.624723 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:22:25.631407 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:22:25.634642 0 9 4 | B1->B0 | 2323 2e2e | 1 0 | (1 1) (0 0)
1839 23:22:25.638340 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1840 23:22:25.645250 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 23:22:25.648009 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 23:22:25.651248 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 23:22:25.658173 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 23:22:25.661472 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 23:22:25.664899 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1846 23:22:25.668126 0 10 4 | B1->B0 | 3131 2d2d | 1 1 | (1 1) (1 1)
1847 23:22:25.674771 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 23:22:25.678142 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 23:22:25.681348 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:22:25.687982 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:22:25.691253 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:22:25.694698 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:22:25.701635 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1854 23:22:25.704681 0 11 4 | B1->B0 | 3030 3939 | 0 0 | (1 1) (1 1)
1855 23:22:25.708190 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1856 23:22:25.714639 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 23:22:25.718141 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 23:22:25.721240 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 23:22:25.727892 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 23:22:25.731471 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 23:22:25.734762 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 23:22:25.741339 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1863 23:22:25.744744 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1864 23:22:25.747857 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 23:22:25.754823 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 23:22:25.757946 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 23:22:25.761343 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 23:22:25.768121 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 23:22:25.771260 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 23:22:25.774694 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 23:22:25.777961 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 23:22:25.784849 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 23:22:25.788118 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 23:22:25.791487 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:22:25.797938 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:22:25.801389 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:22:25.804650 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1878 23:22:25.811380 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1879 23:22:25.814527 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 23:22:25.818130 Total UI for P1: 0, mck2ui 16
1881 23:22:25.821232 best dqsien dly found for B0: ( 0, 14, 2)
1882 23:22:25.824702 Total UI for P1: 0, mck2ui 16
1883 23:22:25.827866 best dqsien dly found for B1: ( 0, 14, 6)
1884 23:22:25.831349 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1885 23:22:25.834725 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1886 23:22:25.834806
1887 23:22:25.838012 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1888 23:22:25.841380 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1889 23:22:25.844660 [Gating] SW calibration Done
1890 23:22:25.844739 ==
1891 23:22:25.847917 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 23:22:25.851162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 23:22:25.851243 ==
1894 23:22:25.854609 RX Vref Scan: 0
1895 23:22:25.854688
1896 23:22:25.857766 RX Vref 0 -> 0, step: 1
1897 23:22:25.857845
1898 23:22:25.857909 RX Delay -130 -> 252, step: 16
1899 23:22:25.864821 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1900 23:22:25.868368 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1901 23:22:25.871322 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1902 23:22:25.874837 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1903 23:22:25.877955 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1904 23:22:25.884851 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1905 23:22:25.887827 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1906 23:22:25.891433 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1907 23:22:25.894785 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1908 23:22:25.897962 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1909 23:22:25.904707 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1910 23:22:25.908205 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1911 23:22:25.911325 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1912 23:22:25.914723 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1913 23:22:25.917859 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1914 23:22:25.924929 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1915 23:22:25.925008 ==
1916 23:22:25.928002 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 23:22:25.931230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 23:22:25.931311 ==
1919 23:22:25.931375 DQS Delay:
1920 23:22:25.934754 DQS0 = 0, DQS1 = 0
1921 23:22:25.934833 DQM Delay:
1922 23:22:25.937896 DQM0 = 79, DQM1 = 74
1923 23:22:25.937975 DQ Delay:
1924 23:22:25.941361 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1925 23:22:25.944466 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1926 23:22:25.948180 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1927 23:22:25.951590 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1928 23:22:25.951669
1929 23:22:25.951732
1930 23:22:25.951790 ==
1931 23:22:25.954532 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 23:22:25.958062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 23:22:25.958143 ==
1934 23:22:25.961103
1935 23:22:25.961185
1936 23:22:25.961267 TX Vref Scan disable
1937 23:22:25.964752 == TX Byte 0 ==
1938 23:22:25.967882 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1939 23:22:25.971518 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1940 23:22:25.974437 == TX Byte 1 ==
1941 23:22:25.977882 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1942 23:22:25.981430 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1943 23:22:25.981560 ==
1944 23:22:25.984679 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 23:22:25.991219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 23:22:25.991300 ==
1947 23:22:26.003353 TX Vref=22, minBit 11, minWin=27, winSum=451
1948 23:22:26.006825 TX Vref=24, minBit 3, minWin=28, winSum=455
1949 23:22:26.010176 TX Vref=26, minBit 3, minWin=28, winSum=459
1950 23:22:26.013745 TX Vref=28, minBit 8, minWin=28, winSum=459
1951 23:22:26.016694 TX Vref=30, minBit 3, minWin=28, winSum=462
1952 23:22:26.023399 TX Vref=32, minBit 3, minWin=28, winSum=457
1953 23:22:26.026792 [TxChooseVref] Worse bit 3, Min win 28, Win sum 462, Final Vref 30
1954 23:22:26.026872
1955 23:22:26.029898 Final TX Range 1 Vref 30
1956 23:22:26.029978
1957 23:22:26.030041 ==
1958 23:22:26.033440 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 23:22:26.036661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 23:22:26.039715 ==
1961 23:22:26.039801
1962 23:22:26.039869
1963 23:22:26.039929 TX Vref Scan disable
1964 23:22:26.043767 == TX Byte 0 ==
1965 23:22:26.046800 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1966 23:22:26.053733 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1967 23:22:26.053813 == TX Byte 1 ==
1968 23:22:26.056763 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1969 23:22:26.063702 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1970 23:22:26.063782
1971 23:22:26.063845 [DATLAT]
1972 23:22:26.063903 Freq=800, CH1 RK1
1973 23:22:26.063959
1974 23:22:26.066796 DATLAT Default: 0xa
1975 23:22:26.066876 0, 0xFFFF, sum = 0
1976 23:22:26.070146 1, 0xFFFF, sum = 0
1977 23:22:26.070228 2, 0xFFFF, sum = 0
1978 23:22:26.073224 3, 0xFFFF, sum = 0
1979 23:22:26.076674 4, 0xFFFF, sum = 0
1980 23:22:26.076781 5, 0xFFFF, sum = 0
1981 23:22:26.079951 6, 0xFFFF, sum = 0
1982 23:22:26.080032 7, 0xFFFF, sum = 0
1983 23:22:26.083223 8, 0xFFFF, sum = 0
1984 23:22:26.083307 9, 0x0, sum = 1
1985 23:22:26.086456 10, 0x0, sum = 2
1986 23:22:26.086537 11, 0x0, sum = 3
1987 23:22:26.086601 12, 0x0, sum = 4
1988 23:22:26.089905 best_step = 10
1989 23:22:26.089984
1990 23:22:26.090047 ==
1991 23:22:26.093293 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 23:22:26.096554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 23:22:26.096634 ==
1994 23:22:26.100077 RX Vref Scan: 0
1995 23:22:26.100156
1996 23:22:26.100219 RX Vref 0 -> 0, step: 1
1997 23:22:26.100278
1998 23:22:26.103181 RX Delay -111 -> 252, step: 8
1999 23:22:26.110194 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2000 23:22:26.113660 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2001 23:22:26.116966 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2002 23:22:26.120402 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2003 23:22:26.123833 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2004 23:22:26.130241 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2005 23:22:26.133746 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2006 23:22:26.136905 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2007 23:22:26.142798 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2008 23:22:26.143632 iDelay=209, Bit 9, Center 60 (-63 ~ 184) 248
2009 23:22:26.150296 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2010 23:22:26.153416 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2011 23:22:26.156828 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2012 23:22:26.160266 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2013 23:22:26.163471 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2014 23:22:26.170140 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2015 23:22:26.170216 ==
2016 23:22:26.173703 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 23:22:26.176890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 23:22:26.176964 ==
2019 23:22:26.177026 DQS Delay:
2020 23:22:26.180059 DQS0 = 0, DQS1 = 0
2021 23:22:26.180132 DQM Delay:
2022 23:22:26.183540 DQM0 = 77, DQM1 = 72
2023 23:22:26.183615 DQ Delay:
2024 23:22:26.186889 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2025 23:22:26.189980 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2026 23:22:26.193547 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =64
2027 23:22:26.196661 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
2028 23:22:26.196733
2029 23:22:26.196793
2030 23:22:26.206670 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e35, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2031 23:22:26.206758 CH1 RK1: MR19=606, MR18=1E35
2032 23:22:26.213273 CH1_RK1: MR19=0x606, MR18=0x1E35, DQSOSC=396, MR23=63, INC=94, DEC=62
2033 23:22:26.216857 [RxdqsGatingPostProcess] freq 800
2034 23:22:26.223298 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 23:22:26.226844 Pre-setting of DQS Precalculation
2036 23:22:26.229973 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 23:22:26.236817 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 23:22:26.243383 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 23:22:26.243487
2040 23:22:26.246839
2041 23:22:26.246910 [Calibration Summary] 1600 Mbps
2042 23:22:26.249959 CH 0, Rank 0
2043 23:22:26.250032 SW Impedance : PASS
2044 23:22:26.253437 DUTY Scan : NO K
2045 23:22:26.256610 ZQ Calibration : PASS
2046 23:22:26.256688 Jitter Meter : NO K
2047 23:22:26.259994 CBT Training : PASS
2048 23:22:26.263363 Write leveling : PASS
2049 23:22:26.263467 RX DQS gating : PASS
2050 23:22:26.266697 RX DQ/DQS(RDDQC) : PASS
2051 23:22:26.270091 TX DQ/DQS : PASS
2052 23:22:26.270169 RX DATLAT : PASS
2053 23:22:26.273096 RX DQ/DQS(Engine): PASS
2054 23:22:26.276724 TX OE : NO K
2055 23:22:26.276798 All Pass.
2056 23:22:26.276861
2057 23:22:26.276923 CH 0, Rank 1
2058 23:22:26.279935 SW Impedance : PASS
2059 23:22:26.283464 DUTY Scan : NO K
2060 23:22:26.283540 ZQ Calibration : PASS
2061 23:22:26.286446 Jitter Meter : NO K
2062 23:22:26.286513 CBT Training : PASS
2063 23:22:26.290028 Write leveling : PASS
2064 23:22:26.293240 RX DQS gating : PASS
2065 23:22:26.293316 RX DQ/DQS(RDDQC) : PASS
2066 23:22:26.296765 TX DQ/DQS : PASS
2067 23:22:26.299804 RX DATLAT : PASS
2068 23:22:26.299883 RX DQ/DQS(Engine): PASS
2069 23:22:26.302979 TX OE : NO K
2070 23:22:26.303081 All Pass.
2071 23:22:26.303173
2072 23:22:26.306617 CH 1, Rank 0
2073 23:22:26.306690 SW Impedance : PASS
2074 23:22:26.309863 DUTY Scan : NO K
2075 23:22:26.312986 ZQ Calibration : PASS
2076 23:22:26.313059 Jitter Meter : NO K
2077 23:22:26.316444 CBT Training : PASS
2078 23:22:26.319948 Write leveling : PASS
2079 23:22:26.320022 RX DQS gating : PASS
2080 23:22:26.323161 RX DQ/DQS(RDDQC) : PASS
2081 23:22:26.326252 TX DQ/DQS : PASS
2082 23:22:26.326327 RX DATLAT : PASS
2083 23:22:26.329847 RX DQ/DQS(Engine): PASS
2084 23:22:26.329925 TX OE : NO K
2085 23:22:26.333021 All Pass.
2086 23:22:26.333094
2087 23:22:26.333155 CH 1, Rank 1
2088 23:22:26.336484 SW Impedance : PASS
2089 23:22:26.336556 DUTY Scan : NO K
2090 23:22:26.339718 ZQ Calibration : PASS
2091 23:22:26.342846 Jitter Meter : NO K
2092 23:22:26.342917 CBT Training : PASS
2093 23:22:26.346170 Write leveling : PASS
2094 23:22:26.349779 RX DQS gating : PASS
2095 23:22:26.349853 RX DQ/DQS(RDDQC) : PASS
2096 23:22:26.353013 TX DQ/DQS : PASS
2097 23:22:26.356654 RX DATLAT : PASS
2098 23:22:26.356731 RX DQ/DQS(Engine): PASS
2099 23:22:26.359788 TX OE : NO K
2100 23:22:26.359860 All Pass.
2101 23:22:26.359925
2102 23:22:26.362969 DramC Write-DBI off
2103 23:22:26.366424 PER_BANK_REFRESH: Hybrid Mode
2104 23:22:26.366498 TX_TRACKING: ON
2105 23:22:26.369722 [GetDramInforAfterCalByMRR] Vendor 6.
2106 23:22:26.372956 [GetDramInforAfterCalByMRR] Revision 606.
2107 23:22:26.376488 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 23:22:26.380018 MR0 0x3b3b
2109 23:22:26.380094 MR8 0x5151
2110 23:22:26.383228 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 23:22:26.383303
2112 23:22:26.383365 MR0 0x3b3b
2113 23:22:26.386373 MR8 0x5151
2114 23:22:26.389468 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 23:22:26.389582
2116 23:22:26.399795 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 23:22:26.402904 [FAST_K] Save calibration result to emmc
2118 23:22:26.406387 [FAST_K] Save calibration result to emmc
2119 23:22:26.406465 dram_init: config_dvfs: 1
2120 23:22:26.412751 dramc_set_vcore_voltage set vcore to 662500
2121 23:22:26.412826 Read voltage for 1200, 2
2122 23:22:26.416254 Vio18 = 0
2123 23:22:26.416326 Vcore = 662500
2124 23:22:26.416390 Vdram = 0
2125 23:22:26.419442 Vddq = 0
2126 23:22:26.419509 Vmddr = 0
2127 23:22:26.422869 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 23:22:26.429370 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 23:22:26.432641 MEM_TYPE=3, freq_sel=15
2130 23:22:26.436214 sv_algorithm_assistance_LP4_1600
2131 23:22:26.439441 ============ PULL DRAM RESETB DOWN ============
2132 23:22:26.442954 ========== PULL DRAM RESETB DOWN end =========
2133 23:22:26.446120 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 23:22:26.449214 ===================================
2135 23:22:26.452796 LPDDR4 DRAM CONFIGURATION
2136 23:22:26.456155 ===================================
2137 23:22:26.459522 EX_ROW_EN[0] = 0x0
2138 23:22:26.459601 EX_ROW_EN[1] = 0x0
2139 23:22:26.462658 LP4Y_EN = 0x0
2140 23:22:26.462738 WORK_FSP = 0x0
2141 23:22:26.466204 WL = 0x4
2142 23:22:26.466284 RL = 0x4
2143 23:22:26.469438 BL = 0x2
2144 23:22:26.469564 RPST = 0x0
2145 23:22:26.472785 RD_PRE = 0x0
2146 23:22:26.472865 WR_PRE = 0x1
2147 23:22:26.475843 WR_PST = 0x0
2148 23:22:26.475922 DBI_WR = 0x0
2149 23:22:26.479238 DBI_RD = 0x0
2150 23:22:26.482839 OTF = 0x1
2151 23:22:26.482919 ===================================
2152 23:22:26.485923 ===================================
2153 23:22:26.489456 ANA top config
2154 23:22:26.492892 ===================================
2155 23:22:26.496117 DLL_ASYNC_EN = 0
2156 23:22:26.496198 ALL_SLAVE_EN = 0
2157 23:22:26.499621 NEW_RANK_MODE = 1
2158 23:22:26.502819 DLL_IDLE_MODE = 1
2159 23:22:26.505967 LP45_APHY_COMB_EN = 1
2160 23:22:26.509470 TX_ODT_DIS = 1
2161 23:22:26.509592 NEW_8X_MODE = 1
2162 23:22:26.512654 ===================================
2163 23:22:26.516000 ===================================
2164 23:22:26.519451 data_rate = 2400
2165 23:22:26.522556 CKR = 1
2166 23:22:26.526133 DQ_P2S_RATIO = 8
2167 23:22:26.529327 ===================================
2168 23:22:26.532847 CA_P2S_RATIO = 8
2169 23:22:26.532926 DQ_CA_OPEN = 0
2170 23:22:26.535858 DQ_SEMI_OPEN = 0
2171 23:22:26.539306 CA_SEMI_OPEN = 0
2172 23:22:26.542555 CA_FULL_RATE = 0
2173 23:22:26.546092 DQ_CKDIV4_EN = 0
2174 23:22:26.549145 CA_CKDIV4_EN = 0
2175 23:22:26.549224 CA_PREDIV_EN = 0
2176 23:22:26.552726 PH8_DLY = 17
2177 23:22:26.555861 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 23:22:26.559271 DQ_AAMCK_DIV = 4
2179 23:22:26.562677 CA_AAMCK_DIV = 4
2180 23:22:26.565705 CA_ADMCK_DIV = 4
2181 23:22:26.565820 DQ_TRACK_CA_EN = 0
2182 23:22:26.569100 CA_PICK = 1200
2183 23:22:26.572466 CA_MCKIO = 1200
2184 23:22:26.575972 MCKIO_SEMI = 0
2185 23:22:26.579458 PLL_FREQ = 2366
2186 23:22:26.582695 DQ_UI_PI_RATIO = 32
2187 23:22:26.585794 CA_UI_PI_RATIO = 0
2188 23:22:26.589287 ===================================
2189 23:22:26.592401 ===================================
2190 23:22:26.592481 memory_type:LPDDR4
2191 23:22:26.595771 GP_NUM : 10
2192 23:22:26.599234 SRAM_EN : 1
2193 23:22:26.599314 MD32_EN : 0
2194 23:22:26.602277 ===================================
2195 23:22:26.605957 [ANA_INIT] >>>>>>>>>>>>>>
2196 23:22:26.608920 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 23:22:26.612450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 23:22:26.616069 ===================================
2199 23:22:26.619196 data_rate = 2400,PCW = 0X5b00
2200 23:22:26.622294 ===================================
2201 23:22:26.625932 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 23:22:26.629073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 23:22:26.635866 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 23:22:26.639019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 23:22:26.642433 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 23:22:26.645745 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 23:22:26.648964 [ANA_INIT] flow start
2208 23:22:26.652426 [ANA_INIT] PLL >>>>>>>>
2209 23:22:26.652520 [ANA_INIT] PLL <<<<<<<<
2210 23:22:26.655775 [ANA_INIT] MIDPI >>>>>>>>
2211 23:22:26.659191 [ANA_INIT] MIDPI <<<<<<<<
2212 23:22:26.659266 [ANA_INIT] DLL >>>>>>>>
2213 23:22:26.662350 [ANA_INIT] DLL <<<<<<<<
2214 23:22:26.665578 [ANA_INIT] flow end
2215 23:22:26.668850 ============ LP4 DIFF to SE enter ============
2216 23:22:26.672377 ============ LP4 DIFF to SE exit ============
2217 23:22:26.675843 [ANA_INIT] <<<<<<<<<<<<<
2218 23:22:26.678866 [Flow] Enable top DCM control >>>>>
2219 23:22:26.682251 [Flow] Enable top DCM control <<<<<
2220 23:22:26.685773 Enable DLL master slave shuffle
2221 23:22:26.688841 ==============================================================
2222 23:22:26.692467 Gating Mode config
2223 23:22:26.698871 ==============================================================
2224 23:22:26.698967 Config description:
2225 23:22:26.709038 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 23:22:26.715532 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 23:22:26.722444 SELPH_MODE 0: By rank 1: By Phase
2228 23:22:26.725590 ==============================================================
2229 23:22:26.728858 GAT_TRACK_EN = 1
2230 23:22:26.732177 RX_GATING_MODE = 2
2231 23:22:26.735359 RX_GATING_TRACK_MODE = 2
2232 23:22:26.738799 SELPH_MODE = 1
2233 23:22:26.742452 PICG_EARLY_EN = 1
2234 23:22:26.745649 VALID_LAT_VALUE = 1
2235 23:22:26.748823 ==============================================================
2236 23:22:26.752236 Enter into Gating configuration >>>>
2237 23:22:26.755719 Exit from Gating configuration <<<<
2238 23:22:26.759184 Enter into DVFS_PRE_config >>>>>
2239 23:22:26.768994 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 23:22:26.772268 Exit from DVFS_PRE_config <<<<<
2241 23:22:26.775614 Enter into PICG configuration >>>>
2242 23:22:26.779067 Exit from PICG configuration <<<<
2243 23:22:26.782204 [RX_INPUT] configuration >>>>>
2244 23:22:26.785736 [RX_INPUT] configuration <<<<<
2245 23:22:26.792303 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 23:22:26.795644 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 23:22:26.802198 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 23:22:26.808833 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 23:22:26.815569 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 23:22:26.822289 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 23:22:26.825405 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 23:22:26.828852 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 23:22:26.832133 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 23:22:26.838998 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 23:22:26.842499 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 23:22:26.845468 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 23:22:26.849035 ===================================
2258 23:22:26.852485 LPDDR4 DRAM CONFIGURATION
2259 23:22:26.855586 ===================================
2260 23:22:26.855666 EX_ROW_EN[0] = 0x0
2261 23:22:26.859036 EX_ROW_EN[1] = 0x0
2262 23:22:26.859116 LP4Y_EN = 0x0
2263 23:22:26.862187 WORK_FSP = 0x0
2264 23:22:26.865661 WL = 0x4
2265 23:22:26.865741 RL = 0x4
2266 23:22:26.868990 BL = 0x2
2267 23:22:26.869070 RPST = 0x0
2268 23:22:26.872069 RD_PRE = 0x0
2269 23:22:26.872148 WR_PRE = 0x1
2270 23:22:26.875644 WR_PST = 0x0
2271 23:22:26.875723 DBI_WR = 0x0
2272 23:22:26.879079 DBI_RD = 0x0
2273 23:22:26.879159 OTF = 0x1
2274 23:22:26.882426 ===================================
2275 23:22:26.885457 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 23:22:26.892218 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 23:22:26.895704 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 23:22:26.898992 ===================================
2279 23:22:26.902256 LPDDR4 DRAM CONFIGURATION
2280 23:22:26.905732 ===================================
2281 23:22:26.905813 EX_ROW_EN[0] = 0x10
2282 23:22:26.908733 EX_ROW_EN[1] = 0x0
2283 23:22:26.908812 LP4Y_EN = 0x0
2284 23:22:26.912297 WORK_FSP = 0x0
2285 23:22:26.912376 WL = 0x4
2286 23:22:26.915446 RL = 0x4
2287 23:22:26.915526 BL = 0x2
2288 23:22:26.918933 RPST = 0x0
2289 23:22:26.919013 RD_PRE = 0x0
2290 23:22:26.922036 WR_PRE = 0x1
2291 23:22:26.925413 WR_PST = 0x0
2292 23:22:26.925514 DBI_WR = 0x0
2293 23:22:26.928939 DBI_RD = 0x0
2294 23:22:26.929019 OTF = 0x1
2295 23:22:26.932045 ===================================
2296 23:22:26.938962 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 23:22:26.939043 ==
2298 23:22:26.942105 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 23:22:26.945459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 23:22:26.945564 ==
2301 23:22:26.948834 [Duty_Offset_Calibration]
2302 23:22:26.948915 B0:2 B1:0 CA:3
2303 23:22:26.948978
2304 23:22:26.952282 [DutyScan_Calibration_Flow] k_type=0
2305 23:22:26.962973
2306 23:22:26.963053 ==CLK 0==
2307 23:22:26.966186 Final CLK duty delay cell = 0
2308 23:22:26.969795 [0] MAX Duty = 5031%(X100), DQS PI = 12
2309 23:22:26.972915 [0] MIN Duty = 4875%(X100), DQS PI = 58
2310 23:22:26.973020 [0] AVG Duty = 4953%(X100)
2311 23:22:26.976374
2312 23:22:26.979462 CH0 CLK Duty spec in!! Max-Min= 156%
2313 23:22:26.982985 [DutyScan_Calibration_Flow] ====Done====
2314 23:22:26.983064
2315 23:22:26.986241 [DutyScan_Calibration_Flow] k_type=1
2316 23:22:27.001283
2317 23:22:27.001402 ==DQS 0 ==
2318 23:22:27.004690 Final DQS duty delay cell = 0
2319 23:22:27.007968 [0] MAX Duty = 5062%(X100), DQS PI = 12
2320 23:22:27.011335 [0] MIN Duty = 4907%(X100), DQS PI = 2
2321 23:22:27.011414 [0] AVG Duty = 4984%(X100)
2322 23:22:27.014919
2323 23:22:27.014997 ==DQS 1 ==
2324 23:22:27.018161 Final DQS duty delay cell = -4
2325 23:22:27.021281 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2326 23:22:27.024858 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2327 23:22:27.028031 [-4] AVG Duty = 4937%(X100)
2328 23:22:27.028110
2329 23:22:27.031688 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2330 23:22:27.031767
2331 23:22:27.034866 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2332 23:22:27.038344 [DutyScan_Calibration_Flow] ====Done====
2333 23:22:27.038423
2334 23:22:27.041319 [DutyScan_Calibration_Flow] k_type=3
2335 23:22:27.059153
2336 23:22:27.059237 ==DQM 0 ==
2337 23:22:27.062246 Final DQM duty delay cell = 0
2338 23:22:27.065753 [0] MAX Duty = 5124%(X100), DQS PI = 28
2339 23:22:27.069138 [0] MIN Duty = 4907%(X100), DQS PI = 0
2340 23:22:27.069213 [0] AVG Duty = 5015%(X100)
2341 23:22:27.072159
2342 23:22:27.072227 ==DQM 1 ==
2343 23:22:27.075640 Final DQM duty delay cell = 4
2344 23:22:27.078840 [4] MAX Duty = 5124%(X100), DQS PI = 50
2345 23:22:27.082377 [4] MIN Duty = 5031%(X100), DQS PI = 10
2346 23:22:27.082451 [4] AVG Duty = 5077%(X100)
2347 23:22:27.082513
2348 23:22:27.088995 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2349 23:22:27.089074
2350 23:22:27.092352 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2351 23:22:27.095840 [DutyScan_Calibration_Flow] ====Done====
2352 23:22:27.095913
2353 23:22:27.099127 [DutyScan_Calibration_Flow] k_type=2
2354 23:22:27.113865
2355 23:22:27.113942 ==DQ 0 ==
2356 23:22:27.117175 Final DQ duty delay cell = -4
2357 23:22:27.120454 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2358 23:22:27.123970 [-4] MIN Duty = 4907%(X100), DQS PI = 42
2359 23:22:27.127140 [-4] AVG Duty = 4969%(X100)
2360 23:22:27.127219
2361 23:22:27.127283 ==DQ 1 ==
2362 23:22:27.130718 Final DQ duty delay cell = -4
2363 23:22:27.133826 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2364 23:22:27.137373 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2365 23:22:27.140464 [-4] AVG Duty = 4938%(X100)
2366 23:22:27.140564
2367 23:22:27.143920 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2368 23:22:27.143992
2369 23:22:27.147342 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2370 23:22:27.150650 [DutyScan_Calibration_Flow] ====Done====
2371 23:22:27.150730 ==
2372 23:22:27.153786 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 23:22:27.157264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 23:22:27.157341 ==
2375 23:22:27.160398 [Duty_Offset_Calibration]
2376 23:22:27.160468 B0:1 B1:-2 CA:1
2377 23:22:27.160531
2378 23:22:27.163604 [DutyScan_Calibration_Flow] k_type=0
2379 23:22:27.174612
2380 23:22:27.174685 ==CLK 0==
2381 23:22:27.177686 Final CLK duty delay cell = 0
2382 23:22:27.181240 [0] MAX Duty = 5031%(X100), DQS PI = 18
2383 23:22:27.184214 [0] MIN Duty = 4844%(X100), DQS PI = 2
2384 23:22:27.184290 [0] AVG Duty = 4937%(X100)
2385 23:22:27.187744
2386 23:22:27.187816 CH1 CLK Duty spec in!! Max-Min= 187%
2387 23:22:27.194302 [DutyScan_Calibration_Flow] ====Done====
2388 23:22:27.194377
2389 23:22:27.197459 [DutyScan_Calibration_Flow] k_type=1
2390 23:22:27.212977
2391 23:22:27.213061 ==DQS 0 ==
2392 23:22:27.216176 Final DQS duty delay cell = -4
2393 23:22:27.219810 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2394 23:22:27.222864 [-4] MIN Duty = 4907%(X100), DQS PI = 4
2395 23:22:27.226349 [-4] AVG Duty = 4969%(X100)
2396 23:22:27.226421
2397 23:22:27.226481 ==DQS 1 ==
2398 23:22:27.229657 Final DQS duty delay cell = 0
2399 23:22:27.232846 [0] MAX Duty = 5093%(X100), DQS PI = 0
2400 23:22:27.236169 [0] MIN Duty = 4875%(X100), DQS PI = 26
2401 23:22:27.239583 [0] AVG Duty = 4984%(X100)
2402 23:22:27.239654
2403 23:22:27.243023 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2404 23:22:27.243096
2405 23:22:27.246244 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2406 23:22:27.249381 [DutyScan_Calibration_Flow] ====Done====
2407 23:22:27.249451
2408 23:22:27.252785 [DutyScan_Calibration_Flow] k_type=3
2409 23:22:27.269586
2410 23:22:27.269667 ==DQM 0 ==
2411 23:22:27.272745 Final DQM duty delay cell = 0
2412 23:22:27.276196 [0] MAX Duty = 5000%(X100), DQS PI = 24
2413 23:22:27.279327 [0] MIN Duty = 4876%(X100), DQS PI = 0
2414 23:22:27.279399 [0] AVG Duty = 4938%(X100)
2415 23:22:27.282836
2416 23:22:27.282907 ==DQM 1 ==
2417 23:22:27.286348 Final DQM duty delay cell = 0
2418 23:22:27.289365 [0] MAX Duty = 5031%(X100), DQS PI = 34
2419 23:22:27.293125 [0] MIN Duty = 4907%(X100), DQS PI = 0
2420 23:22:27.293198 [0] AVG Duty = 4969%(X100)
2421 23:22:27.293263
2422 23:22:27.299784 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2423 23:22:27.299857
2424 23:22:27.302909 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2425 23:22:27.306082 [DutyScan_Calibration_Flow] ====Done====
2426 23:22:27.306155
2427 23:22:27.309434 [DutyScan_Calibration_Flow] k_type=2
2428 23:22:27.326052
2429 23:22:27.326128 ==DQ 0 ==
2430 23:22:27.329416 Final DQ duty delay cell = 0
2431 23:22:27.332800 [0] MAX Duty = 5062%(X100), DQS PI = 14
2432 23:22:27.335849 [0] MIN Duty = 4938%(X100), DQS PI = 54
2433 23:22:27.335921 [0] AVG Duty = 5000%(X100)
2434 23:22:27.335982
2435 23:22:27.339182 ==DQ 1 ==
2436 23:22:27.342503 Final DQ duty delay cell = 0
2437 23:22:27.346037 [0] MAX Duty = 5093%(X100), DQS PI = 20
2438 23:22:27.349172 [0] MIN Duty = 4938%(X100), DQS PI = 26
2439 23:22:27.349242 [0] AVG Duty = 5015%(X100)
2440 23:22:27.349306
2441 23:22:27.352740 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2442 23:22:27.355883
2443 23:22:27.359526 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2444 23:22:27.362499 [DutyScan_Calibration_Flow] ====Done====
2445 23:22:27.365817 nWR fixed to 30
2446 23:22:27.365898 [ModeRegInit_LP4] CH0 RK0
2447 23:22:27.369361 [ModeRegInit_LP4] CH0 RK1
2448 23:22:27.372714 [ModeRegInit_LP4] CH1 RK0
2449 23:22:27.372797 [ModeRegInit_LP4] CH1 RK1
2450 23:22:27.375753 match AC timing 7
2451 23:22:27.379285 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 23:22:27.382751 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 23:22:27.389331 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 23:22:27.392856 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 23:22:27.399170 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 23:22:27.399250 ==
2457 23:22:27.402406 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 23:22:27.405896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 23:22:27.405977 ==
2460 23:22:27.412234 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 23:22:27.419048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2462 23:22:27.426122 [CA 0] Center 40 (10~71) winsize 62
2463 23:22:27.429249 [CA 1] Center 39 (9~70) winsize 62
2464 23:22:27.432723 [CA 2] Center 36 (6~66) winsize 61
2465 23:22:27.435916 [CA 3] Center 35 (5~66) winsize 62
2466 23:22:27.439523 [CA 4] Center 34 (4~65) winsize 62
2467 23:22:27.442738 [CA 5] Center 33 (3~63) winsize 61
2468 23:22:27.442818
2469 23:22:27.445835 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2470 23:22:27.445915
2471 23:22:27.449235 [CATrainingPosCal] consider 1 rank data
2472 23:22:27.452631 u2DelayCellTimex100 = 270/100 ps
2473 23:22:27.455730 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2474 23:22:27.462382 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2475 23:22:27.465863 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2476 23:22:27.469034 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 23:22:27.472441 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2478 23:22:27.475849 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2479 23:22:27.475941
2480 23:22:27.479227 CA PerBit enable=1, Macro0, CA PI delay=33
2481 23:22:27.479332
2482 23:22:27.482510 [CBTSetCACLKResult] CA Dly = 33
2483 23:22:27.485655 CS Dly: 7 (0~38)
2484 23:22:27.485735 ==
2485 23:22:27.488864 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 23:22:27.492424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 23:22:27.492504 ==
2488 23:22:27.498839 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 23:22:27.502098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2490 23:22:27.512211 [CA 0] Center 40 (10~70) winsize 61
2491 23:22:27.515191 [CA 1] Center 39 (9~70) winsize 62
2492 23:22:27.518905 [CA 2] Center 35 (5~66) winsize 62
2493 23:22:27.522042 [CA 3] Center 35 (5~66) winsize 62
2494 23:22:27.525481 [CA 4] Center 34 (4~65) winsize 62
2495 23:22:27.528633 [CA 5] Center 33 (3~64) winsize 62
2496 23:22:27.528712
2497 23:22:27.532085 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2498 23:22:27.532165
2499 23:22:27.535455 [CATrainingPosCal] consider 2 rank data
2500 23:22:27.538662 u2DelayCellTimex100 = 270/100 ps
2501 23:22:27.542077 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2502 23:22:27.548525 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2503 23:22:27.551915 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2504 23:22:27.555493 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 23:22:27.558650 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2506 23:22:27.562152 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2507 23:22:27.562232
2508 23:22:27.565390 CA PerBit enable=1, Macro0, CA PI delay=33
2509 23:22:27.565529
2510 23:22:27.568905 [CBTSetCACLKResult] CA Dly = 33
2511 23:22:27.568985 CS Dly: 8 (0~40)
2512 23:22:27.569048
2513 23:22:27.572063 ----->DramcWriteLeveling(PI) begin...
2514 23:22:27.575659 ==
2515 23:22:27.578660 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 23:22:27.582228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 23:22:27.582308 ==
2518 23:22:27.585626 Write leveling (Byte 0): 31 => 31
2519 23:22:27.588694 Write leveling (Byte 1): 29 => 29
2520 23:22:27.592207 DramcWriteLeveling(PI) end<-----
2521 23:22:27.592286
2522 23:22:27.592350 ==
2523 23:22:27.595498 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 23:22:27.599017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 23:22:27.599097 ==
2526 23:22:27.602252 [Gating] SW mode calibration
2527 23:22:27.608674 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 23:22:27.612055 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 23:22:27.619012 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 23:22:27.622298 0 15 4 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
2531 23:22:27.625449 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 23:22:27.632413 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 23:22:27.635424 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 23:22:27.639032 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 23:22:27.645693 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 23:22:27.648659 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 23:22:27.652142 1 0 0 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (0 0)
2538 23:22:27.658759 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2539 23:22:27.662062 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 23:22:27.665483 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 23:22:27.672297 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 23:22:27.675270 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 23:22:27.678678 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 23:22:27.685341 1 0 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2545 23:22:27.688885 1 1 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2546 23:22:27.692031 1 1 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2547 23:22:27.698852 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 23:22:27.702220 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 23:22:27.705332 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 23:22:27.708820 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 23:22:27.715656 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 23:22:27.718796 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 23:22:27.722161 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2554 23:22:27.728926 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 23:22:27.732192 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 23:22:27.735809 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 23:22:27.742289 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 23:22:27.745336 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 23:22:27.748861 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 23:22:27.755740 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 23:22:27.758971 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 23:22:27.762134 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 23:22:27.768929 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 23:22:27.772094 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 23:22:27.775243 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:22:27.781951 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:22:27.785506 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 23:22:27.788735 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 23:22:27.795286 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2570 23:22:27.798849 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 23:22:27.801984 Total UI for P1: 0, mck2ui 16
2572 23:22:27.805481 best dqsien dly found for B0: ( 1, 3, 30)
2573 23:22:27.808717 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 23:22:27.812149 Total UI for P1: 0, mck2ui 16
2575 23:22:27.815222 best dqsien dly found for B1: ( 1, 4, 2)
2576 23:22:27.818757 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2577 23:22:27.822051 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2578 23:22:27.822130
2579 23:22:27.825134 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2580 23:22:27.831804 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2581 23:22:27.831904 [Gating] SW calibration Done
2582 23:22:27.831995 ==
2583 23:22:27.835222 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 23:22:27.842022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 23:22:27.842100 ==
2586 23:22:27.842170 RX Vref Scan: 0
2587 23:22:27.842231
2588 23:22:27.845207 RX Vref 0 -> 0, step: 1
2589 23:22:27.845303
2590 23:22:27.848733 RX Delay -40 -> 252, step: 8
2591 23:22:27.852128 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2592 23:22:27.855408 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2593 23:22:27.858825 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2594 23:22:27.862061 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2595 23:22:27.868651 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2596 23:22:27.872103 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2597 23:22:27.875194 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2598 23:22:27.878707 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2599 23:22:27.881826 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2600 23:22:27.885318 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2601 23:22:27.891944 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2602 23:22:27.895160 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2603 23:22:27.898739 iDelay=200, Bit 12, Center 103 (32 ~ 175) 144
2604 23:22:27.901753 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2605 23:22:27.908783 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2606 23:22:27.911890 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2607 23:22:27.911989 ==
2608 23:22:27.915313 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 23:22:27.918995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 23:22:27.919095 ==
2611 23:22:27.919185 DQS Delay:
2612 23:22:27.921859 DQS0 = 0, DQS1 = 0
2613 23:22:27.921957 DQM Delay:
2614 23:22:27.925401 DQM0 = 112, DQM1 = 101
2615 23:22:27.925526 DQ Delay:
2616 23:22:27.928782 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2617 23:22:27.931907 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2618 23:22:27.935298 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2619 23:22:27.938794 DQ12 =103, DQ13 =107, DQ14 =115, DQ15 =111
2620 23:22:27.938867
2621 23:22:27.938948
2622 23:22:27.942206 ==
2623 23:22:27.945466 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 23:22:27.948613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 23:22:27.948714 ==
2626 23:22:27.948804
2627 23:22:27.948891
2628 23:22:27.951834 TX Vref Scan disable
2629 23:22:27.951911 == TX Byte 0 ==
2630 23:22:27.955358 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2631 23:22:27.961771 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2632 23:22:27.961872 == TX Byte 1 ==
2633 23:22:27.965199 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2634 23:22:27.972096 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2635 23:22:27.972176 ==
2636 23:22:27.975162 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 23:22:27.978679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 23:22:27.978750 ==
2639 23:22:27.990718 TX Vref=22, minBit 12, minWin=25, winSum=416
2640 23:22:27.994279 TX Vref=24, minBit 12, minWin=25, winSum=422
2641 23:22:27.997380 TX Vref=26, minBit 4, minWin=26, winSum=431
2642 23:22:28.000841 TX Vref=28, minBit 8, minWin=26, winSum=436
2643 23:22:28.003989 TX Vref=30, minBit 8, minWin=26, winSum=432
2644 23:22:28.010556 TX Vref=32, minBit 2, minWin=26, winSum=429
2645 23:22:28.013949 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 28
2646 23:22:28.014025
2647 23:22:28.017216 Final TX Range 1 Vref 28
2648 23:22:28.017302
2649 23:22:28.017391 ==
2650 23:22:28.020725 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 23:22:28.024032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 23:22:28.024143 ==
2653 23:22:28.027452
2654 23:22:28.027521
2655 23:22:28.027581 TX Vref Scan disable
2656 23:22:28.030766 == TX Byte 0 ==
2657 23:22:28.033990 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2658 23:22:28.037409 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2659 23:22:28.040763 == TX Byte 1 ==
2660 23:22:28.044277 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2661 23:22:28.047355 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2662 23:22:28.050695
2663 23:22:28.050792 [DATLAT]
2664 23:22:28.050883 Freq=1200, CH0 RK0
2665 23:22:28.050970
2666 23:22:28.053955 DATLAT Default: 0xd
2667 23:22:28.054028 0, 0xFFFF, sum = 0
2668 23:22:28.057348 1, 0xFFFF, sum = 0
2669 23:22:28.057461 2, 0xFFFF, sum = 0
2670 23:22:28.060831 3, 0xFFFF, sum = 0
2671 23:22:28.060931 4, 0xFFFF, sum = 0
2672 23:22:28.063951 5, 0xFFFF, sum = 0
2673 23:22:28.067202 6, 0xFFFF, sum = 0
2674 23:22:28.067301 7, 0xFFFF, sum = 0
2675 23:22:28.070795 8, 0xFFFF, sum = 0
2676 23:22:28.070868 9, 0xFFFF, sum = 0
2677 23:22:28.073880 10, 0xFFFF, sum = 0
2678 23:22:28.073957 11, 0xFFFF, sum = 0
2679 23:22:28.077228 12, 0x0, sum = 1
2680 23:22:28.077327 13, 0x0, sum = 2
2681 23:22:28.080688 14, 0x0, sum = 3
2682 23:22:28.080759 15, 0x0, sum = 4
2683 23:22:28.080821 best_step = 13
2684 23:22:28.080879
2685 23:22:28.084102 ==
2686 23:22:28.087269 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 23:22:28.090695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 23:22:28.090768 ==
2689 23:22:28.090829 RX Vref Scan: 1
2690 23:22:28.090887
2691 23:22:28.094143 Set Vref Range= 32 -> 127
2692 23:22:28.094214
2693 23:22:28.097306 RX Vref 32 -> 127, step: 1
2694 23:22:28.097399
2695 23:22:28.100505 RX Delay -37 -> 252, step: 4
2696 23:22:28.100574
2697 23:22:28.104056 Set Vref, RX VrefLevel [Byte0]: 32
2698 23:22:28.107257 [Byte1]: 32
2699 23:22:28.107348
2700 23:22:28.110508 Set Vref, RX VrefLevel [Byte0]: 33
2701 23:22:28.114000 [Byte1]: 33
2702 23:22:28.117406
2703 23:22:28.117534 Set Vref, RX VrefLevel [Byte0]: 34
2704 23:22:28.120437 [Byte1]: 34
2705 23:22:28.125228
2706 23:22:28.125328 Set Vref, RX VrefLevel [Byte0]: 35
2707 23:22:28.128474 [Byte1]: 35
2708 23:22:28.133374
2709 23:22:28.133499 Set Vref, RX VrefLevel [Byte0]: 36
2710 23:22:28.136714 [Byte1]: 36
2711 23:22:28.141293
2712 23:22:28.141369 Set Vref, RX VrefLevel [Byte0]: 37
2713 23:22:28.144825 [Byte1]: 37
2714 23:22:28.149295
2715 23:22:28.149404 Set Vref, RX VrefLevel [Byte0]: 38
2716 23:22:28.152772 [Byte1]: 38
2717 23:22:28.157296
2718 23:22:28.157372 Set Vref, RX VrefLevel [Byte0]: 39
2719 23:22:28.160684 [Byte1]: 39
2720 23:22:28.165218
2721 23:22:28.165316 Set Vref, RX VrefLevel [Byte0]: 40
2722 23:22:28.168771 [Byte1]: 40
2723 23:22:28.173195
2724 23:22:28.173292 Set Vref, RX VrefLevel [Byte0]: 41
2725 23:22:28.176736 [Byte1]: 41
2726 23:22:28.181395
2727 23:22:28.181514 Set Vref, RX VrefLevel [Byte0]: 42
2728 23:22:28.184456 [Byte1]: 42
2729 23:22:28.189344
2730 23:22:28.189452 Set Vref, RX VrefLevel [Byte0]: 43
2731 23:22:28.192499 [Byte1]: 43
2732 23:22:28.197158
2733 23:22:28.197254 Set Vref, RX VrefLevel [Byte0]: 44
2734 23:22:28.200707 [Byte1]: 44
2735 23:22:28.205275
2736 23:22:28.205380 Set Vref, RX VrefLevel [Byte0]: 45
2737 23:22:28.208770 [Byte1]: 45
2738 23:22:28.213096
2739 23:22:28.213193 Set Vref, RX VrefLevel [Byte0]: 46
2740 23:22:28.216809 [Byte1]: 46
2741 23:22:28.221176
2742 23:22:28.221270 Set Vref, RX VrefLevel [Byte0]: 47
2743 23:22:28.224702 [Byte1]: 47
2744 23:22:28.229095
2745 23:22:28.229167 Set Vref, RX VrefLevel [Byte0]: 48
2746 23:22:28.232530 [Byte1]: 48
2747 23:22:28.237191
2748 23:22:28.240379 Set Vref, RX VrefLevel [Byte0]: 49
2749 23:22:28.240463 [Byte1]: 49
2750 23:22:28.245303
2751 23:22:28.245421 Set Vref, RX VrefLevel [Byte0]: 50
2752 23:22:28.248539 [Byte1]: 50
2753 23:22:28.253201
2754 23:22:28.253297 Set Vref, RX VrefLevel [Byte0]: 51
2755 23:22:28.256534 [Byte1]: 51
2756 23:22:28.261277
2757 23:22:28.261414 Set Vref, RX VrefLevel [Byte0]: 52
2758 23:22:28.264449 [Byte1]: 52
2759 23:22:28.269488
2760 23:22:28.269626 Set Vref, RX VrefLevel [Byte0]: 53
2761 23:22:28.272857 [Byte1]: 53
2762 23:22:28.277351
2763 23:22:28.277562 Set Vref, RX VrefLevel [Byte0]: 54
2764 23:22:28.280787 [Byte1]: 54
2765 23:22:28.285174
2766 23:22:28.285436 Set Vref, RX VrefLevel [Byte0]: 55
2767 23:22:28.288815 [Byte1]: 55
2768 23:22:28.293292
2769 23:22:28.293623 Set Vref, RX VrefLevel [Byte0]: 56
2770 23:22:28.296979 [Byte1]: 56
2771 23:22:28.301534
2772 23:22:28.302078 Set Vref, RX VrefLevel [Byte0]: 57
2773 23:22:28.304894 [Byte1]: 57
2774 23:22:28.309581
2775 23:22:28.309998 Set Vref, RX VrefLevel [Byte0]: 58
2776 23:22:28.312835 [Byte1]: 58
2777 23:22:28.317530
2778 23:22:28.317953 Set Vref, RX VrefLevel [Byte0]: 59
2779 23:22:28.321063 [Byte1]: 59
2780 23:22:28.325353
2781 23:22:28.325848 Set Vref, RX VrefLevel [Byte0]: 60
2782 23:22:28.328835 [Byte1]: 60
2783 23:22:28.333741
2784 23:22:28.334214 Set Vref, RX VrefLevel [Byte0]: 61
2785 23:22:28.340257 [Byte1]: 61
2786 23:22:28.340785
2787 23:22:28.343328 Set Vref, RX VrefLevel [Byte0]: 62
2788 23:22:28.346852 [Byte1]: 62
2789 23:22:28.347377
2790 23:22:28.350033 Set Vref, RX VrefLevel [Byte0]: 63
2791 23:22:28.353316 [Byte1]: 63
2792 23:22:28.357767
2793 23:22:28.358333 Set Vref, RX VrefLevel [Byte0]: 64
2794 23:22:28.360822 [Byte1]: 64
2795 23:22:28.365591
2796 23:22:28.366124 Set Vref, RX VrefLevel [Byte0]: 65
2797 23:22:28.369088 [Byte1]: 65
2798 23:22:28.373734
2799 23:22:28.374142 Set Vref, RX VrefLevel [Byte0]: 66
2800 23:22:28.377084 [Byte1]: 66
2801 23:22:28.381689
2802 23:22:28.382201 Set Vref, RX VrefLevel [Byte0]: 67
2803 23:22:28.384779 [Byte1]: 67
2804 23:22:28.389649
2805 23:22:28.390081 Set Vref, RX VrefLevel [Byte0]: 68
2806 23:22:28.392756 [Byte1]: 68
2807 23:22:28.397523
2808 23:22:28.397997 Set Vref, RX VrefLevel [Byte0]: 69
2809 23:22:28.400951 [Byte1]: 69
2810 23:22:28.405606
2811 23:22:28.406170 Set Vref, RX VrefLevel [Byte0]: 70
2812 23:22:28.408776 [Byte1]: 70
2813 23:22:28.413555
2814 23:22:28.414087 Set Vref, RX VrefLevel [Byte0]: 71
2815 23:22:28.417139 [Byte1]: 71
2816 23:22:28.421805
2817 23:22:28.422345 Set Vref, RX VrefLevel [Byte0]: 72
2818 23:22:28.424870 [Byte1]: 72
2819 23:22:28.429580
2820 23:22:28.430010 Set Vref, RX VrefLevel [Byte0]: 73
2821 23:22:28.433143 [Byte1]: 73
2822 23:22:28.437773
2823 23:22:28.438160 Set Vref, RX VrefLevel [Byte0]: 74
2824 23:22:28.440922 [Byte1]: 74
2825 23:22:28.445651
2826 23:22:28.446134 Final RX Vref Byte 0 = 60 to rank0
2827 23:22:28.449175 Final RX Vref Byte 1 = 54 to rank0
2828 23:22:28.452289 Final RX Vref Byte 0 = 60 to rank1
2829 23:22:28.455485 Final RX Vref Byte 1 = 54 to rank1==
2830 23:22:28.458978 Dram Type= 6, Freq= 0, CH_0, rank 0
2831 23:22:28.465432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2832 23:22:28.466001 ==
2833 23:22:28.466467 DQS Delay:
2834 23:22:28.466911 DQS0 = 0, DQS1 = 0
2835 23:22:28.469029 DQM Delay:
2836 23:22:28.469599 DQM0 = 112, DQM1 = 101
2837 23:22:28.472579 DQ Delay:
2838 23:22:28.475502 DQ0 =112, DQ1 =112, DQ2 =110, DQ3 =108
2839 23:22:28.478895 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2840 23:22:28.482073 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =94
2841 23:22:28.485429 DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =110
2842 23:22:28.485873
2843 23:22:28.486208
2844 23:22:28.492160 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2845 23:22:28.495168 CH0 RK0: MR19=303, MR18=FBFB
2846 23:22:28.501928 CH0_RK0: MR19=0x303, MR18=0xFBFB, DQSOSC=412, MR23=63, INC=38, DEC=25
2847 23:22:28.502010
2848 23:22:28.505149 ----->DramcWriteLeveling(PI) begin...
2849 23:22:28.505253 ==
2850 23:22:28.508367 Dram Type= 6, Freq= 0, CH_0, rank 1
2851 23:22:28.511715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2852 23:22:28.515141 ==
2853 23:22:28.515222 Write leveling (Byte 0): 32 => 32
2854 23:22:28.518323 Write leveling (Byte 1): 32 => 32
2855 23:22:28.521610 DramcWriteLeveling(PI) end<-----
2856 23:22:28.521712
2857 23:22:28.521814 ==
2858 23:22:28.524886 Dram Type= 6, Freq= 0, CH_0, rank 1
2859 23:22:28.531751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2860 23:22:28.531865 ==
2861 23:22:28.531959 [Gating] SW mode calibration
2862 23:22:28.541505 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2863 23:22:28.545100 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2864 23:22:28.548578 0 15 0 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
2865 23:22:28.555139 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 23:22:28.558303 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 23:22:28.561935 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 23:22:28.568437 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 23:22:28.572006 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 23:22:28.575148 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2871 23:22:28.581866 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2872 23:22:28.585255 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2873 23:22:28.588791 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 23:22:28.595519 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 23:22:28.598676 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 23:22:28.602036 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 23:22:28.608666 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 23:22:28.611929 1 0 24 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
2879 23:22:28.615158 1 0 28 | B1->B0 | 2727 4444 | 0 0 | (0 0) (0 0)
2880 23:22:28.621783 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2881 23:22:28.624972 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 23:22:28.628445 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 23:22:28.635013 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 23:22:28.638341 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 23:22:28.641771 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 23:22:28.645000 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2887 23:22:28.651692 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2888 23:22:28.655259 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2889 23:22:28.658422 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 23:22:28.665242 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 23:22:28.668358 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 23:22:28.671893 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 23:22:28.678093 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 23:22:28.681743 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 23:22:28.684865 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 23:22:28.691686 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 23:22:28.694856 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 23:22:28.698330 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 23:22:28.704988 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 23:22:28.708042 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 23:22:28.711363 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 23:22:28.718339 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 23:22:28.721800 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2904 23:22:28.724605 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2905 23:22:28.727912 Total UI for P1: 0, mck2ui 16
2906 23:22:28.731556 best dqsien dly found for B0: ( 1, 3, 28)
2907 23:22:28.738239 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 23:22:28.738318 Total UI for P1: 0, mck2ui 16
2909 23:22:28.741391 best dqsien dly found for B1: ( 1, 4, 0)
2910 23:22:28.748095 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2911 23:22:28.751449 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2912 23:22:28.751550
2913 23:22:28.755052 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2914 23:22:28.758460 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2915 23:22:28.761793 [Gating] SW calibration Done
2916 23:22:28.761875 ==
2917 23:22:28.764767 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 23:22:28.768209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 23:22:28.768292 ==
2920 23:22:28.768356 RX Vref Scan: 0
2921 23:22:28.771552
2922 23:22:28.771633 RX Vref 0 -> 0, step: 1
2923 23:22:28.771697
2924 23:22:28.774799 RX Delay -40 -> 252, step: 8
2925 23:22:28.778310 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2926 23:22:28.781508 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2927 23:22:28.788194 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2928 23:22:28.791459 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2929 23:22:28.794961 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2930 23:22:28.798448 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2931 23:22:28.801452 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2932 23:22:28.808242 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2933 23:22:28.811864 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2934 23:22:28.814961 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2935 23:22:28.818245 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2936 23:22:28.821710 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2937 23:22:28.824884 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2938 23:22:28.831870 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2939 23:22:28.835042 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2940 23:22:28.838125 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2941 23:22:28.838211 ==
2942 23:22:28.841682 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 23:22:28.844872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 23:22:28.844954 ==
2945 23:22:28.848482 DQS Delay:
2946 23:22:28.848564 DQS0 = 0, DQS1 = 0
2947 23:22:28.851494 DQM Delay:
2948 23:22:28.851575 DQM0 = 112, DQM1 = 101
2949 23:22:28.855033 DQ Delay:
2950 23:22:28.858202 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2951 23:22:28.861454 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2952 23:22:28.864917 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2953 23:22:28.868243 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
2954 23:22:28.868342
2955 23:22:28.868441
2956 23:22:28.868517 ==
2957 23:22:28.871660 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 23:22:28.875152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 23:22:28.875234 ==
2960 23:22:28.875298
2961 23:22:28.875358
2962 23:22:28.878379 TX Vref Scan disable
2963 23:22:28.881610 == TX Byte 0 ==
2964 23:22:28.885012 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2965 23:22:28.888466 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2966 23:22:28.891626 == TX Byte 1 ==
2967 23:22:28.895084 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2968 23:22:28.898139 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2969 23:22:28.898242 ==
2970 23:22:28.901712 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 23:22:28.905211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 23:22:28.905318 ==
2973 23:22:28.918264 TX Vref=22, minBit 1, minWin=25, winSum=425
2974 23:22:28.921262 TX Vref=24, minBit 4, minWin=26, winSum=430
2975 23:22:28.924632 TX Vref=26, minBit 5, minWin=26, winSum=431
2976 23:22:28.928023 TX Vref=28, minBit 13, minWin=26, winSum=441
2977 23:22:28.931473 TX Vref=30, minBit 13, minWin=26, winSum=439
2978 23:22:28.938154 TX Vref=32, minBit 13, minWin=26, winSum=439
2979 23:22:28.941567 [TxChooseVref] Worse bit 13, Min win 26, Win sum 441, Final Vref 28
2980 23:22:28.941656
2981 23:22:28.945021 Final TX Range 1 Vref 28
2982 23:22:28.945121
2983 23:22:28.945222 ==
2984 23:22:28.948165 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 23:22:28.951409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 23:22:28.951512 ==
2987 23:22:28.954756
2988 23:22:28.954862
2989 23:22:28.954953 TX Vref Scan disable
2990 23:22:28.958149 == TX Byte 0 ==
2991 23:22:28.961655 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2992 23:22:28.964779 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2993 23:22:28.968110 == TX Byte 1 ==
2994 23:22:28.971456 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2995 23:22:28.974641 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2996 23:22:28.978127
2997 23:22:28.978200 [DATLAT]
2998 23:22:28.978269 Freq=1200, CH0 RK1
2999 23:22:28.978367
3000 23:22:28.981697 DATLAT Default: 0xd
3001 23:22:28.981781 0, 0xFFFF, sum = 0
3002 23:22:28.984727 1, 0xFFFF, sum = 0
3003 23:22:28.984834 2, 0xFFFF, sum = 0
3004 23:22:28.988073 3, 0xFFFF, sum = 0
3005 23:22:28.988174 4, 0xFFFF, sum = 0
3006 23:22:28.991516 5, 0xFFFF, sum = 0
3007 23:22:28.994859 6, 0xFFFF, sum = 0
3008 23:22:28.994973 7, 0xFFFF, sum = 0
3009 23:22:28.998255 8, 0xFFFF, sum = 0
3010 23:22:28.998358 9, 0xFFFF, sum = 0
3011 23:22:29.001593 10, 0xFFFF, sum = 0
3012 23:22:29.001705 11, 0xFFFF, sum = 0
3013 23:22:29.004731 12, 0x0, sum = 1
3014 23:22:29.004835 13, 0x0, sum = 2
3015 23:22:29.008258 14, 0x0, sum = 3
3016 23:22:29.008361 15, 0x0, sum = 4
3017 23:22:29.008457 best_step = 13
3018 23:22:29.008526
3019 23:22:29.011373 ==
3020 23:22:29.014915 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 23:22:29.018040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 23:22:29.018141 ==
3023 23:22:29.018234 RX Vref Scan: 0
3024 23:22:29.018324
3025 23:22:29.021227 RX Vref 0 -> 0, step: 1
3026 23:22:29.021323
3027 23:22:29.024759 RX Delay -37 -> 252, step: 4
3028 23:22:29.028101 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3029 23:22:29.034527 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3030 23:22:29.037960 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3031 23:22:29.041192 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3032 23:22:29.044637 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3033 23:22:29.048089 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3034 23:22:29.054888 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3035 23:22:29.058070 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3036 23:22:29.061366 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3037 23:22:29.064664 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3038 23:22:29.068196 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3039 23:22:29.071307 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3040 23:22:29.078055 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3041 23:22:29.081136 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3042 23:22:29.084759 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3043 23:22:29.087840 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3044 23:22:29.087943 ==
3045 23:22:29.091347 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 23:22:29.097693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 23:22:29.097795 ==
3048 23:22:29.097889 DQS Delay:
3049 23:22:29.101017 DQS0 = 0, DQS1 = 0
3050 23:22:29.101113 DQM Delay:
3051 23:22:29.104523 DQM0 = 111, DQM1 = 101
3052 23:22:29.104624 DQ Delay:
3053 23:22:29.107798 DQ0 =108, DQ1 =110, DQ2 =110, DQ3 =108
3054 23:22:29.111080 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3055 23:22:29.114279 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3056 23:22:29.117840 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3057 23:22:29.117950
3058 23:22:29.118041
3059 23:22:29.127809 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3060 23:22:29.127912 CH0 RK1: MR19=403, MR18=13FC
3061 23:22:29.134286 CH0_RK1: MR19=0x403, MR18=0x13FC, DQSOSC=402, MR23=63, INC=40, DEC=27
3062 23:22:29.137647 [RxdqsGatingPostProcess] freq 1200
3063 23:22:29.144269 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3064 23:22:29.147399 best DQS0 dly(2T, 0.5T) = (0, 11)
3065 23:22:29.150968 best DQS1 dly(2T, 0.5T) = (0, 12)
3066 23:22:29.154336 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3067 23:22:29.157461 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3068 23:22:29.160673 best DQS0 dly(2T, 0.5T) = (0, 11)
3069 23:22:29.160755 best DQS1 dly(2T, 0.5T) = (0, 12)
3070 23:22:29.163994 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3071 23:22:29.167466 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3072 23:22:29.170845 Pre-setting of DQS Precalculation
3073 23:22:29.177482 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3074 23:22:29.177579 ==
3075 23:22:29.180875 Dram Type= 6, Freq= 0, CH_1, rank 0
3076 23:22:29.184035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 23:22:29.184117 ==
3078 23:22:29.190905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3079 23:22:29.197085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3080 23:22:29.204413 [CA 0] Center 37 (7~67) winsize 61
3081 23:22:29.207876 [CA 1] Center 38 (8~68) winsize 61
3082 23:22:29.211042 [CA 2] Center 34 (4~64) winsize 61
3083 23:22:29.214346 [CA 3] Center 33 (3~64) winsize 62
3084 23:22:29.217710 [CA 4] Center 34 (4~64) winsize 61
3085 23:22:29.220810 [CA 5] Center 33 (3~63) winsize 61
3086 23:22:29.220892
3087 23:22:29.224287 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3088 23:22:29.224369
3089 23:22:29.227877 [CATrainingPosCal] consider 1 rank data
3090 23:22:29.231091 u2DelayCellTimex100 = 270/100 ps
3091 23:22:29.234518 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3092 23:22:29.237663 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3093 23:22:29.244387 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 23:22:29.247457 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3095 23:22:29.251120 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 23:22:29.254267 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3097 23:22:29.254351
3098 23:22:29.257699 CA PerBit enable=1, Macro0, CA PI delay=33
3099 23:22:29.257781
3100 23:22:29.261068 [CBTSetCACLKResult] CA Dly = 33
3101 23:22:29.261149 CS Dly: 5 (0~36)
3102 23:22:29.261238 ==
3103 23:22:29.264444 Dram Type= 6, Freq= 0, CH_1, rank 1
3104 23:22:29.271108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 23:22:29.271207 ==
3106 23:22:29.274293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3107 23:22:29.281022 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3108 23:22:29.289790 [CA 0] Center 38 (8~68) winsize 61
3109 23:22:29.293079 [CA 1] Center 37 (7~68) winsize 62
3110 23:22:29.296525 [CA 2] Center 34 (4~65) winsize 62
3111 23:22:29.299896 [CA 3] Center 33 (3~64) winsize 62
3112 23:22:29.303428 [CA 4] Center 34 (4~65) winsize 62
3113 23:22:29.306495 [CA 5] Center 33 (3~64) winsize 62
3114 23:22:29.306574
3115 23:22:29.309880 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3116 23:22:29.309962
3117 23:22:29.313300 [CATrainingPosCal] consider 2 rank data
3118 23:22:29.316407 u2DelayCellTimex100 = 270/100 ps
3119 23:22:29.319903 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3120 23:22:29.323262 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3121 23:22:29.329791 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 23:22:29.333280 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3123 23:22:29.336481 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 23:22:29.339789 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3125 23:22:29.339870
3126 23:22:29.343316 CA PerBit enable=1, Macro0, CA PI delay=33
3127 23:22:29.343398
3128 23:22:29.346735 [CBTSetCACLKResult] CA Dly = 33
3129 23:22:29.346815 CS Dly: 7 (0~40)
3130 23:22:29.346880
3131 23:22:29.349722 ----->DramcWriteLeveling(PI) begin...
3132 23:22:29.353206 ==
3133 23:22:29.353287 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 23:22:29.360062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 23:22:29.360143 ==
3136 23:22:29.363132 Write leveling (Byte 0): 25 => 25
3137 23:22:29.366536 Write leveling (Byte 1): 29 => 29
3138 23:22:29.370051 DramcWriteLeveling(PI) end<-----
3139 23:22:29.370132
3140 23:22:29.370197 ==
3141 23:22:29.373054 Dram Type= 6, Freq= 0, CH_1, rank 0
3142 23:22:29.376456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 23:22:29.376539 ==
3144 23:22:29.379887 [Gating] SW mode calibration
3145 23:22:29.386552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3146 23:22:29.389667 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3147 23:22:29.396454 0 15 0 | B1->B0 | 2e2e 2b2b | 1 1 | (0 0) (1 1)
3148 23:22:29.399890 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 23:22:29.403269 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 23:22:29.409721 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 23:22:29.413164 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 23:22:29.416493 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 23:22:29.423123 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3154 23:22:29.426445 0 15 28 | B1->B0 | 2c2c 2c2c | 0 0 | (0 0) (0 0)
3155 23:22:29.429843 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3156 23:22:29.436415 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 23:22:29.439871 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 23:22:29.443134 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 23:22:29.449729 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 23:22:29.453126 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 23:22:29.456685 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 23:22:29.463270 1 0 28 | B1->B0 | 3c3c 3c3c | 0 0 | (0 0) (0 0)
3163 23:22:29.466405 1 1 0 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
3164 23:22:29.469814 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 23:22:29.476302 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 23:22:29.479710 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 23:22:29.483006 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 23:22:29.486495 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 23:22:29.492863 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 23:22:29.496383 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3171 23:22:29.499726 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3172 23:22:29.506233 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 23:22:29.509713 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 23:22:29.513197 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 23:22:29.519480 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 23:22:29.522797 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 23:22:29.526220 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 23:22:29.532970 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 23:22:29.536280 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 23:22:29.539469 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 23:22:29.546108 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 23:22:29.549653 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 23:22:29.552840 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 23:22:29.559294 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 23:22:29.562738 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 23:22:29.566156 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3187 23:22:29.572866 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3188 23:22:29.572947 Total UI for P1: 0, mck2ui 16
3189 23:22:29.579688 best dqsien dly found for B1: ( 1, 3, 28)
3190 23:22:29.582730 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 23:22:29.586376 Total UI for P1: 0, mck2ui 16
3192 23:22:29.589468 best dqsien dly found for B0: ( 1, 3, 30)
3193 23:22:29.592771 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3194 23:22:29.596262 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3195 23:22:29.596344
3196 23:22:29.599742 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3197 23:22:29.602999 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3198 23:22:29.606110 [Gating] SW calibration Done
3199 23:22:29.606227 ==
3200 23:22:29.609386 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 23:22:29.612983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 23:22:29.613080 ==
3203 23:22:29.616124 RX Vref Scan: 0
3204 23:22:29.616204
3205 23:22:29.619402 RX Vref 0 -> 0, step: 1
3206 23:22:29.619483
3207 23:22:29.619547 RX Delay -40 -> 252, step: 8
3208 23:22:29.626287 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3209 23:22:29.629607 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3210 23:22:29.632843 iDelay=208, Bit 2, Center 99 (24 ~ 175) 152
3211 23:22:29.636398 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3212 23:22:29.639410 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3213 23:22:29.646109 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3214 23:22:29.649438 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3215 23:22:29.652873 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3216 23:22:29.656309 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3217 23:22:29.659594 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3218 23:22:29.662833 iDelay=208, Bit 10, Center 103 (32 ~ 175) 144
3219 23:22:29.669398 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3220 23:22:29.672756 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3221 23:22:29.676068 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3222 23:22:29.679407 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3223 23:22:29.685953 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3224 23:22:29.686036 ==
3225 23:22:29.689221 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 23:22:29.692811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 23:22:29.692888 ==
3228 23:22:29.692951 DQS Delay:
3229 23:22:29.695833 DQS0 = 0, DQS1 = 0
3230 23:22:29.695907 DQM Delay:
3231 23:22:29.699349 DQM0 = 115, DQM1 = 106
3232 23:22:29.699423 DQ Delay:
3233 23:22:29.702725 DQ0 =119, DQ1 =111, DQ2 =99, DQ3 =111
3234 23:22:29.705938 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3235 23:22:29.709460 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3236 23:22:29.712405 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3237 23:22:29.712481
3238 23:22:29.712555
3239 23:22:29.712615 ==
3240 23:22:29.715749 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 23:22:29.722777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 23:22:29.722858 ==
3243 23:22:29.722940
3244 23:22:29.723016
3245 23:22:29.723091 TX Vref Scan disable
3246 23:22:29.726236 == TX Byte 0 ==
3247 23:22:29.729714 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3248 23:22:29.736143 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3249 23:22:29.736219 == TX Byte 1 ==
3250 23:22:29.739781 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3251 23:22:29.742975 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3252 23:22:29.746403 ==
3253 23:22:29.749459 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 23:22:29.752949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 23:22:29.753049 ==
3256 23:22:29.764425 TX Vref=22, minBit 8, minWin=24, winSum=410
3257 23:22:29.767368 TX Vref=24, minBit 11, minWin=24, winSum=416
3258 23:22:29.770966 TX Vref=26, minBit 8, minWin=25, winSum=423
3259 23:22:29.774093 TX Vref=28, minBit 11, minWin=25, winSum=427
3260 23:22:29.777711 TX Vref=30, minBit 9, minWin=25, winSum=426
3261 23:22:29.784225 TX Vref=32, minBit 9, minWin=25, winSum=422
3262 23:22:29.787553 [TxChooseVref] Worse bit 11, Min win 25, Win sum 427, Final Vref 28
3263 23:22:29.787634
3264 23:22:29.790775 Final TX Range 1 Vref 28
3265 23:22:29.790861
3266 23:22:29.790947 ==
3267 23:22:29.793990 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 23:22:29.797426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 23:22:29.800837 ==
3270 23:22:29.800921
3271 23:22:29.801006
3272 23:22:29.801087 TX Vref Scan disable
3273 23:22:29.804444 == TX Byte 0 ==
3274 23:22:29.807683 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3275 23:22:29.810859 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3276 23:22:29.814035 == TX Byte 1 ==
3277 23:22:29.817697 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3278 23:22:29.824185 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3279 23:22:29.824268
3280 23:22:29.824333 [DATLAT]
3281 23:22:29.824396 Freq=1200, CH1 RK0
3282 23:22:29.824461
3283 23:22:29.827638 DATLAT Default: 0xd
3284 23:22:29.827715 0, 0xFFFF, sum = 0
3285 23:22:29.830627 1, 0xFFFF, sum = 0
3286 23:22:29.834135 2, 0xFFFF, sum = 0
3287 23:22:29.834214 3, 0xFFFF, sum = 0
3288 23:22:29.837425 4, 0xFFFF, sum = 0
3289 23:22:29.837528 5, 0xFFFF, sum = 0
3290 23:22:29.840653 6, 0xFFFF, sum = 0
3291 23:22:29.840735 7, 0xFFFF, sum = 0
3292 23:22:29.843993 8, 0xFFFF, sum = 0
3293 23:22:29.844086 9, 0xFFFF, sum = 0
3294 23:22:29.847471 10, 0xFFFF, sum = 0
3295 23:22:29.847556 11, 0xFFFF, sum = 0
3296 23:22:29.850941 12, 0x0, sum = 1
3297 23:22:29.851026 13, 0x0, sum = 2
3298 23:22:29.854013 14, 0x0, sum = 3
3299 23:22:29.854120 15, 0x0, sum = 4
3300 23:22:29.857135 best_step = 13
3301 23:22:29.857215
3302 23:22:29.857279 ==
3303 23:22:29.860575 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 23:22:29.863986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 23:22:29.864067 ==
3306 23:22:29.864131 RX Vref Scan: 1
3307 23:22:29.864190
3308 23:22:29.867582 Set Vref Range= 32 -> 127
3309 23:22:29.867662
3310 23:22:29.870610 RX Vref 32 -> 127, step: 1
3311 23:22:29.870691
3312 23:22:29.873877 RX Delay -21 -> 252, step: 4
3313 23:22:29.873957
3314 23:22:29.877128 Set Vref, RX VrefLevel [Byte0]: 32
3315 23:22:29.880690 [Byte1]: 32
3316 23:22:29.880769
3317 23:22:29.883877 Set Vref, RX VrefLevel [Byte0]: 33
3318 23:22:29.887059 [Byte1]: 33
3319 23:22:29.890774
3320 23:22:29.890898 Set Vref, RX VrefLevel [Byte0]: 34
3321 23:22:29.894210 [Byte1]: 34
3322 23:22:29.898553
3323 23:22:29.898631 Set Vref, RX VrefLevel [Byte0]: 35
3324 23:22:29.902029 [Byte1]: 35
3325 23:22:29.906651
3326 23:22:29.906730 Set Vref, RX VrefLevel [Byte0]: 36
3327 23:22:29.909747 [Byte1]: 36
3328 23:22:29.914727
3329 23:22:29.914817 Set Vref, RX VrefLevel [Byte0]: 37
3330 23:22:29.917649 [Byte1]: 37
3331 23:22:29.922472
3332 23:22:29.922543 Set Vref, RX VrefLevel [Byte0]: 38
3333 23:22:29.925674 [Byte1]: 38
3334 23:22:29.930396
3335 23:22:29.930475 Set Vref, RX VrefLevel [Byte0]: 39
3336 23:22:29.933455 [Byte1]: 39
3337 23:22:29.938249
3338 23:22:29.938327 Set Vref, RX VrefLevel [Byte0]: 40
3339 23:22:29.941396 [Byte1]: 40
3340 23:22:29.946285
3341 23:22:29.946363 Set Vref, RX VrefLevel [Byte0]: 41
3342 23:22:29.949517 [Byte1]: 41
3343 23:22:29.954252
3344 23:22:29.954333 Set Vref, RX VrefLevel [Byte0]: 42
3345 23:22:29.957323 [Byte1]: 42
3346 23:22:29.962097
3347 23:22:29.962182 Set Vref, RX VrefLevel [Byte0]: 43
3348 23:22:29.965245 [Byte1]: 43
3349 23:22:29.969973
3350 23:22:29.970051 Set Vref, RX VrefLevel [Byte0]: 44
3351 23:22:29.973442 [Byte1]: 44
3352 23:22:29.977838
3353 23:22:29.977917 Set Vref, RX VrefLevel [Byte0]: 45
3354 23:22:29.981162 [Byte1]: 45
3355 23:22:29.985736
3356 23:22:29.985815 Set Vref, RX VrefLevel [Byte0]: 46
3357 23:22:29.989046 [Byte1]: 46
3358 23:22:29.994011
3359 23:22:29.994089 Set Vref, RX VrefLevel [Byte0]: 47
3360 23:22:29.996873 [Byte1]: 47
3361 23:22:30.001472
3362 23:22:30.001562 Set Vref, RX VrefLevel [Byte0]: 48
3363 23:22:30.004897 [Byte1]: 48
3364 23:22:30.009517
3365 23:22:30.009610 Set Vref, RX VrefLevel [Byte0]: 49
3366 23:22:30.012856 [Byte1]: 49
3367 23:22:30.017322
3368 23:22:30.017427 Set Vref, RX VrefLevel [Byte0]: 50
3369 23:22:30.020826 [Byte1]: 50
3370 23:22:30.025387
3371 23:22:30.025501 Set Vref, RX VrefLevel [Byte0]: 51
3372 23:22:30.028910 [Byte1]: 51
3373 23:22:30.033146
3374 23:22:30.033253 Set Vref, RX VrefLevel [Byte0]: 52
3375 23:22:30.036661 [Byte1]: 52
3376 23:22:30.041252
3377 23:22:30.041358 Set Vref, RX VrefLevel [Byte0]: 53
3378 23:22:30.044408 [Byte1]: 53
3379 23:22:30.049058
3380 23:22:30.049140 Set Vref, RX VrefLevel [Byte0]: 54
3381 23:22:30.052609 [Byte1]: 54
3382 23:22:30.057116
3383 23:22:30.057198 Set Vref, RX VrefLevel [Byte0]: 55
3384 23:22:30.060215 [Byte1]: 55
3385 23:22:30.064898
3386 23:22:30.064980 Set Vref, RX VrefLevel [Byte0]: 56
3387 23:22:30.068444 [Byte1]: 56
3388 23:22:30.072995
3389 23:22:30.073076 Set Vref, RX VrefLevel [Byte0]: 57
3390 23:22:30.076058 [Byte1]: 57
3391 23:22:30.081034
3392 23:22:30.081115 Set Vref, RX VrefLevel [Byte0]: 58
3393 23:22:30.084136 [Byte1]: 58
3394 23:22:30.088831
3395 23:22:30.088914 Set Vref, RX VrefLevel [Byte0]: 59
3396 23:22:30.092195 [Byte1]: 59
3397 23:22:30.096805
3398 23:22:30.096887 Set Vref, RX VrefLevel [Byte0]: 60
3399 23:22:30.099915 [Byte1]: 60
3400 23:22:30.104485
3401 23:22:30.104567 Set Vref, RX VrefLevel [Byte0]: 61
3402 23:22:30.107808 [Byte1]: 61
3403 23:22:30.112485
3404 23:22:30.112568 Final RX Vref Byte 0 = 55 to rank0
3405 23:22:30.115826 Final RX Vref Byte 1 = 45 to rank0
3406 23:22:30.119201 Final RX Vref Byte 0 = 55 to rank1
3407 23:22:30.122583 Final RX Vref Byte 1 = 45 to rank1==
3408 23:22:30.125977 Dram Type= 6, Freq= 0, CH_1, rank 0
3409 23:22:30.132525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3410 23:22:30.132607 ==
3411 23:22:30.132692 DQS Delay:
3412 23:22:30.132773 DQS0 = 0, DQS1 = 0
3413 23:22:30.135683 DQM Delay:
3414 23:22:30.135765 DQM0 = 115, DQM1 = 104
3415 23:22:30.139202 DQ Delay:
3416 23:22:30.142313 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =112
3417 23:22:30.145610 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =112
3418 23:22:30.149130 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =100
3419 23:22:30.152512 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3420 23:22:30.152594
3421 23:22:30.152677
3422 23:22:30.159170 [DQSOSCAuto] RK0, (LSB)MR18= 0xeff6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3423 23:22:30.162231 CH1 RK0: MR19=303, MR18=EFF6
3424 23:22:30.168972 CH1_RK0: MR19=0x303, MR18=0xEFF6, DQSOSC=414, MR23=63, INC=38, DEC=25
3425 23:22:30.169055
3426 23:22:30.172394 ----->DramcWriteLeveling(PI) begin...
3427 23:22:30.172478 ==
3428 23:22:30.175793 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 23:22:30.179164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 23:22:30.182712 ==
3431 23:22:30.182795 Write leveling (Byte 0): 23 => 23
3432 23:22:30.185917 Write leveling (Byte 1): 28 => 28
3433 23:22:30.189057 DramcWriteLeveling(PI) end<-----
3434 23:22:30.189139
3435 23:22:30.189232 ==
3436 23:22:30.192698 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 23:22:30.199197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 23:22:30.199280 ==
3439 23:22:30.199364 [Gating] SW mode calibration
3440 23:22:30.209114 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3441 23:22:30.212315 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3442 23:22:30.215842 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3443 23:22:30.222295 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 23:22:30.225733 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 23:22:30.229260 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 23:22:30.235821 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 23:22:30.239039 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 23:22:30.242491 0 15 24 | B1->B0 | 3434 2727 | 0 0 | (0 1) (0 0)
3449 23:22:30.248958 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
3450 23:22:30.252645 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 23:22:30.255819 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 23:22:30.262238 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 23:22:30.265759 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 23:22:30.269239 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 23:22:30.275690 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3456 23:22:30.279118 1 0 24 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
3457 23:22:30.282532 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3458 23:22:30.289149 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 23:22:30.292274 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 23:22:30.295746 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 23:22:30.302473 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 23:22:30.305681 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 23:22:30.308841 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 23:22:30.315706 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3465 23:22:30.318943 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3466 23:22:30.322109 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 23:22:30.325647 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 23:22:30.332316 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 23:22:30.335407 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 23:22:30.338672 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 23:22:30.345461 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 23:22:30.348508 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 23:22:30.355373 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 23:22:30.358471 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 23:22:30.361740 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 23:22:30.365133 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 23:22:30.371670 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 23:22:30.375197 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 23:22:30.378435 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3480 23:22:30.384768 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3481 23:22:30.388429 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3482 23:22:30.391711 Total UI for P1: 0, mck2ui 16
3483 23:22:30.394977 best dqsien dly found for B0: ( 1, 3, 22)
3484 23:22:30.398360 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 23:22:30.401503 Total UI for P1: 0, mck2ui 16
3486 23:22:30.404689 best dqsien dly found for B1: ( 1, 3, 26)
3487 23:22:30.408364 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3488 23:22:30.411505 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3489 23:22:30.414725
3490 23:22:30.418151 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3491 23:22:30.421292 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3492 23:22:30.424823 [Gating] SW calibration Done
3493 23:22:30.424898 ==
3494 23:22:30.428009 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 23:22:30.431349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 23:22:30.431433 ==
3497 23:22:30.431516 RX Vref Scan: 0
3498 23:22:30.434566
3499 23:22:30.434647 RX Vref 0 -> 0, step: 1
3500 23:22:30.434731
3501 23:22:30.437756 RX Delay -40 -> 252, step: 8
3502 23:22:30.441348 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3503 23:22:30.444451 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3504 23:22:30.451042 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3505 23:22:30.454540 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3506 23:22:30.457710 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3507 23:22:30.460967 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3508 23:22:30.464228 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3509 23:22:30.471067 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3510 23:22:30.474176 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3511 23:22:30.477740 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3512 23:22:30.481219 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3513 23:22:30.484286 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3514 23:22:30.490934 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3515 23:22:30.494357 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3516 23:22:30.497771 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3517 23:22:30.500953 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3518 23:22:30.501035 ==
3519 23:22:30.504395 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 23:22:30.511012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 23:22:30.511096 ==
3522 23:22:30.511180 DQS Delay:
3523 23:22:30.511259 DQS0 = 0, DQS1 = 0
3524 23:22:30.514241 DQM Delay:
3525 23:22:30.514323 DQM0 = 110, DQM1 = 105
3526 23:22:30.517724 DQ Delay:
3527 23:22:30.520846 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3528 23:22:30.524381 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3529 23:22:30.527557 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
3530 23:22:30.530769 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =115
3531 23:22:30.530851
3532 23:22:30.530950
3533 23:22:30.531047 ==
3534 23:22:30.534292 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 23:22:30.537383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 23:22:30.537467 ==
3537 23:22:30.540808
3538 23:22:30.540890
3539 23:22:30.540973 TX Vref Scan disable
3540 23:22:30.543958 == TX Byte 0 ==
3541 23:22:30.547521 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3542 23:22:30.550898 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3543 23:22:30.553879 == TX Byte 1 ==
3544 23:22:30.557050 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3545 23:22:30.560634 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3546 23:22:30.560717 ==
3547 23:22:30.563860 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 23:22:30.570331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 23:22:30.570415 ==
3550 23:22:30.581387 TX Vref=22, minBit 0, minWin=26, winSum=425
3551 23:22:30.584864 TX Vref=24, minBit 4, minWin=26, winSum=428
3552 23:22:30.588077 TX Vref=26, minBit 1, minWin=26, winSum=432
3553 23:22:30.591447 TX Vref=28, minBit 8, minWin=26, winSum=433
3554 23:22:30.594849 TX Vref=30, minBit 8, minWin=26, winSum=434
3555 23:22:30.601369 TX Vref=32, minBit 8, minWin=25, winSum=430
3556 23:22:30.604744 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
3557 23:22:30.604827
3558 23:22:30.608176 Final TX Range 1 Vref 30
3559 23:22:30.608259
3560 23:22:30.608358 ==
3561 23:22:30.611242 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 23:22:30.614740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 23:22:30.614826 ==
3564 23:22:30.617705
3565 23:22:30.617787
3566 23:22:30.617871 TX Vref Scan disable
3567 23:22:30.621200 == TX Byte 0 ==
3568 23:22:30.624667 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3569 23:22:30.631141 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3570 23:22:30.631223 == TX Byte 1 ==
3571 23:22:30.634382 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3572 23:22:30.641126 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3573 23:22:30.641207
3574 23:22:30.641274 [DATLAT]
3575 23:22:30.641333 Freq=1200, CH1 RK1
3576 23:22:30.641391
3577 23:22:30.644472 DATLAT Default: 0xd
3578 23:22:30.644552 0, 0xFFFF, sum = 0
3579 23:22:30.647733 1, 0xFFFF, sum = 0
3580 23:22:30.647815 2, 0xFFFF, sum = 0
3581 23:22:30.651344 3, 0xFFFF, sum = 0
3582 23:22:30.654445 4, 0xFFFF, sum = 0
3583 23:22:30.654527 5, 0xFFFF, sum = 0
3584 23:22:30.657716 6, 0xFFFF, sum = 0
3585 23:22:30.657798 7, 0xFFFF, sum = 0
3586 23:22:30.661144 8, 0xFFFF, sum = 0
3587 23:22:30.661227 9, 0xFFFF, sum = 0
3588 23:22:30.664277 10, 0xFFFF, sum = 0
3589 23:22:30.664359 11, 0xFFFF, sum = 0
3590 23:22:30.667754 12, 0x0, sum = 1
3591 23:22:30.667836 13, 0x0, sum = 2
3592 23:22:30.670864 14, 0x0, sum = 3
3593 23:22:30.670946 15, 0x0, sum = 4
3594 23:22:30.674455 best_step = 13
3595 23:22:30.674536
3596 23:22:30.674599 ==
3597 23:22:30.677634 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 23:22:30.680859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 23:22:30.680940 ==
3600 23:22:30.681033 RX Vref Scan: 0
3601 23:22:30.681096
3602 23:22:30.684161 RX Vref 0 -> 0, step: 1
3603 23:22:30.684241
3604 23:22:30.687656 RX Delay -21 -> 252, step: 4
3605 23:22:30.690860 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3606 23:22:30.697489 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3607 23:22:30.700684 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3608 23:22:30.704274 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3609 23:22:30.707557 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3610 23:22:30.710854 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3611 23:22:30.717343 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3612 23:22:30.720671 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3613 23:22:30.724178 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3614 23:22:30.727337 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3615 23:22:30.730759 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3616 23:22:30.737297 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3617 23:22:30.740419 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3618 23:22:30.744084 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3619 23:22:30.747409 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3620 23:22:30.754075 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3621 23:22:30.754156 ==
3622 23:22:30.757251 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 23:22:30.760621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 23:22:30.760702 ==
3625 23:22:30.760766 DQS Delay:
3626 23:22:30.764066 DQS0 = 0, DQS1 = 0
3627 23:22:30.764147 DQM Delay:
3628 23:22:30.767088 DQM0 = 111, DQM1 = 108
3629 23:22:30.767169 DQ Delay:
3630 23:22:30.770656 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3631 23:22:30.773739 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =108
3632 23:22:30.777098 DQ8 =94, DQ9 =98, DQ10 =110, DQ11 =100
3633 23:22:30.780660 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =116
3634 23:22:30.780741
3635 23:22:30.780805
3636 23:22:30.790145 [DQSOSCAuto] RK1, (LSB)MR18= 0xf606, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3637 23:22:30.793664 CH1 RK1: MR19=304, MR18=F606
3638 23:22:30.797117 CH1_RK1: MR19=0x304, MR18=0xF606, DQSOSC=407, MR23=63, INC=39, DEC=26
3639 23:22:30.800280 [RxdqsGatingPostProcess] freq 1200
3640 23:22:30.806796 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3641 23:22:30.810310 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 23:22:30.813376 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 23:22:30.816823 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 23:22:30.820203 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 23:22:30.823360 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 23:22:30.826792 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 23:22:30.829902 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 23:22:30.833193 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 23:22:30.836696 Pre-setting of DQS Precalculation
3650 23:22:30.839798 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3651 23:22:30.846410 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3652 23:22:30.853076 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3653 23:22:30.856439
3654 23:22:30.856522
3655 23:22:30.856606 [Calibration Summary] 2400 Mbps
3656 23:22:30.859785 CH 0, Rank 0
3657 23:22:30.859881 SW Impedance : PASS
3658 23:22:30.863072 DUTY Scan : NO K
3659 23:22:30.866454 ZQ Calibration : PASS
3660 23:22:30.866537 Jitter Meter : NO K
3661 23:22:30.869449 CBT Training : PASS
3662 23:22:30.873093 Write leveling : PASS
3663 23:22:30.873175 RX DQS gating : PASS
3664 23:22:30.876129 RX DQ/DQS(RDDQC) : PASS
3665 23:22:30.879645 TX DQ/DQS : PASS
3666 23:22:30.879728 RX DATLAT : PASS
3667 23:22:30.882836 RX DQ/DQS(Engine): PASS
3668 23:22:30.885964 TX OE : NO K
3669 23:22:30.886047 All Pass.
3670 23:22:30.886132
3671 23:22:30.886212 CH 0, Rank 1
3672 23:22:30.889390 SW Impedance : PASS
3673 23:22:30.892601 DUTY Scan : NO K
3674 23:22:30.892683 ZQ Calibration : PASS
3675 23:22:30.895925 Jitter Meter : NO K
3676 23:22:30.899379 CBT Training : PASS
3677 23:22:30.899462 Write leveling : PASS
3678 23:22:30.902465 RX DQS gating : PASS
3679 23:22:30.905977 RX DQ/DQS(RDDQC) : PASS
3680 23:22:30.906059 TX DQ/DQS : PASS
3681 23:22:30.909053 RX DATLAT : PASS
3682 23:22:30.912532 RX DQ/DQS(Engine): PASS
3683 23:22:30.912615 TX OE : NO K
3684 23:22:30.912699 All Pass.
3685 23:22:30.915661
3686 23:22:30.915743 CH 1, Rank 0
3687 23:22:30.919244 SW Impedance : PASS
3688 23:22:30.919326 DUTY Scan : NO K
3689 23:22:30.922409 ZQ Calibration : PASS
3690 23:22:30.922492 Jitter Meter : NO K
3691 23:22:30.925651 CBT Training : PASS
3692 23:22:30.929154 Write leveling : PASS
3693 23:22:30.929236 RX DQS gating : PASS
3694 23:22:30.932200 RX DQ/DQS(RDDQC) : PASS
3695 23:22:30.935732 TX DQ/DQS : PASS
3696 23:22:30.935815 RX DATLAT : PASS
3697 23:22:30.938845 RX DQ/DQS(Engine): PASS
3698 23:22:30.942359 TX OE : NO K
3699 23:22:30.942442 All Pass.
3700 23:22:30.942527
3701 23:22:30.942607 CH 1, Rank 1
3702 23:22:30.945404 SW Impedance : PASS
3703 23:22:30.948885 DUTY Scan : NO K
3704 23:22:30.948985 ZQ Calibration : PASS
3705 23:22:30.951968 Jitter Meter : NO K
3706 23:22:30.955534 CBT Training : PASS
3707 23:22:30.955616 Write leveling : PASS
3708 23:22:30.958867 RX DQS gating : PASS
3709 23:22:30.962030 RX DQ/DQS(RDDQC) : PASS
3710 23:22:30.962111 TX DQ/DQS : PASS
3711 23:22:30.965409 RX DATLAT : PASS
3712 23:22:30.968911 RX DQ/DQS(Engine): PASS
3713 23:22:30.968993 TX OE : NO K
3714 23:22:30.969076 All Pass.
3715 23:22:30.972261
3716 23:22:30.972344 DramC Write-DBI off
3717 23:22:30.975440 PER_BANK_REFRESH: Hybrid Mode
3718 23:22:30.975521 TX_TRACKING: ON
3719 23:22:30.985355 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3720 23:22:30.988737 [FAST_K] Save calibration result to emmc
3721 23:22:30.991876 dramc_set_vcore_voltage set vcore to 650000
3722 23:22:30.995243 Read voltage for 600, 5
3723 23:22:30.995326 Vio18 = 0
3724 23:22:30.998839 Vcore = 650000
3725 23:22:30.998921 Vdram = 0
3726 23:22:30.999006 Vddq = 0
3727 23:22:30.999085 Vmddr = 0
3728 23:22:31.005154 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3729 23:22:31.011908 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3730 23:22:31.011994 MEM_TYPE=3, freq_sel=19
3731 23:22:31.015099 sv_algorithm_assistance_LP4_1600
3732 23:22:31.021749 ============ PULL DRAM RESETB DOWN ============
3733 23:22:31.024805 ========== PULL DRAM RESETB DOWN end =========
3734 23:22:31.028101 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3735 23:22:31.031228 ===================================
3736 23:22:31.034905 LPDDR4 DRAM CONFIGURATION
3737 23:22:31.038052 ===================================
3738 23:22:31.038134 EX_ROW_EN[0] = 0x0
3739 23:22:31.041382 EX_ROW_EN[1] = 0x0
3740 23:22:31.044769 LP4Y_EN = 0x0
3741 23:22:31.044853 WORK_FSP = 0x0
3742 23:22:31.047952 WL = 0x2
3743 23:22:31.048034 RL = 0x2
3744 23:22:31.051138 BL = 0x2
3745 23:22:31.051220 RPST = 0x0
3746 23:22:31.054780 RD_PRE = 0x0
3747 23:22:31.054855 WR_PRE = 0x1
3748 23:22:31.057849 WR_PST = 0x0
3749 23:22:31.057946 DBI_WR = 0x0
3750 23:22:31.061067 DBI_RD = 0x0
3751 23:22:31.061141 OTF = 0x1
3752 23:22:31.064662 ===================================
3753 23:22:31.067873 ===================================
3754 23:22:31.071071 ANA top config
3755 23:22:31.074413 ===================================
3756 23:22:31.074496 DLL_ASYNC_EN = 0
3757 23:22:31.077837 ALL_SLAVE_EN = 1
3758 23:22:31.081268 NEW_RANK_MODE = 1
3759 23:22:31.084327 DLL_IDLE_MODE = 1
3760 23:22:31.087729 LP45_APHY_COMB_EN = 1
3761 23:22:31.087812 TX_ODT_DIS = 1
3762 23:22:31.091133 NEW_8X_MODE = 1
3763 23:22:31.094414 ===================================
3764 23:22:31.097815 ===================================
3765 23:22:31.101011 data_rate = 1200
3766 23:22:31.104564 CKR = 1
3767 23:22:31.107721 DQ_P2S_RATIO = 8
3768 23:22:31.110918 ===================================
3769 23:22:31.110999 CA_P2S_RATIO = 8
3770 23:22:31.114175 DQ_CA_OPEN = 0
3771 23:22:31.117437 DQ_SEMI_OPEN = 0
3772 23:22:31.121003 CA_SEMI_OPEN = 0
3773 23:22:31.124261 CA_FULL_RATE = 0
3774 23:22:31.127736 DQ_CKDIV4_EN = 1
3775 23:22:31.127817 CA_CKDIV4_EN = 1
3776 23:22:31.130779 CA_PREDIV_EN = 0
3777 23:22:31.134393 PH8_DLY = 0
3778 23:22:31.137507 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3779 23:22:31.141182 DQ_AAMCK_DIV = 4
3780 23:22:31.144100 CA_AAMCK_DIV = 4
3781 23:22:31.147717 CA_ADMCK_DIV = 4
3782 23:22:31.147798 DQ_TRACK_CA_EN = 0
3783 23:22:31.150812 CA_PICK = 600
3784 23:22:31.154139 CA_MCKIO = 600
3785 23:22:31.157281 MCKIO_SEMI = 0
3786 23:22:31.160874 PLL_FREQ = 2288
3787 23:22:31.164079 DQ_UI_PI_RATIO = 32
3788 23:22:31.167465 CA_UI_PI_RATIO = 0
3789 23:22:31.170660 ===================================
3790 23:22:31.170745 ===================================
3791 23:22:31.173852 memory_type:LPDDR4
3792 23:22:31.177189 GP_NUM : 10
3793 23:22:31.177269 SRAM_EN : 1
3794 23:22:31.180496 MD32_EN : 0
3795 23:22:31.183900 ===================================
3796 23:22:31.187058 [ANA_INIT] >>>>>>>>>>>>>>
3797 23:22:31.190550 <<<<<< [CONFIGURE PHASE]: ANA_TX
3798 23:22:31.193710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3799 23:22:31.197220 ===================================
3800 23:22:31.200343 data_rate = 1200,PCW = 0X5800
3801 23:22:31.203815 ===================================
3802 23:22:31.207185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3803 23:22:31.210443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 23:22:31.217255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 23:22:31.220320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3806 23:22:31.223775 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3807 23:22:31.226806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3808 23:22:31.230327 [ANA_INIT] flow start
3809 23:22:31.233402 [ANA_INIT] PLL >>>>>>>>
3810 23:22:31.233526 [ANA_INIT] PLL <<<<<<<<
3811 23:22:31.236941 [ANA_INIT] MIDPI >>>>>>>>
3812 23:22:31.240127 [ANA_INIT] MIDPI <<<<<<<<
3813 23:22:31.240207 [ANA_INIT] DLL >>>>>>>>
3814 23:22:31.243573 [ANA_INIT] flow end
3815 23:22:31.246659 ============ LP4 DIFF to SE enter ============
3816 23:22:31.253452 ============ LP4 DIFF to SE exit ============
3817 23:22:31.253577 [ANA_INIT] <<<<<<<<<<<<<
3818 23:22:31.256722 [Flow] Enable top DCM control >>>>>
3819 23:22:31.260117 [Flow] Enable top DCM control <<<<<
3820 23:22:31.263242 Enable DLL master slave shuffle
3821 23:22:31.269990 ==============================================================
3822 23:22:31.270071 Gating Mode config
3823 23:22:31.276414 ==============================================================
3824 23:22:31.279868 Config description:
3825 23:22:31.286549 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3826 23:22:31.293111 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3827 23:22:31.299726 SELPH_MODE 0: By rank 1: By Phase
3828 23:22:31.306208 ==============================================================
3829 23:22:31.309728 GAT_TRACK_EN = 1
3830 23:22:31.309817 RX_GATING_MODE = 2
3831 23:22:31.312912 RX_GATING_TRACK_MODE = 2
3832 23:22:31.316126 SELPH_MODE = 1
3833 23:22:31.319528 PICG_EARLY_EN = 1
3834 23:22:31.322872 VALID_LAT_VALUE = 1
3835 23:22:31.329689 ==============================================================
3836 23:22:31.332773 Enter into Gating configuration >>>>
3837 23:22:31.336213 Exit from Gating configuration <<<<
3838 23:22:31.339426 Enter into DVFS_PRE_config >>>>>
3839 23:22:31.349408 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3840 23:22:31.352755 Exit from DVFS_PRE_config <<<<<
3841 23:22:31.355856 Enter into PICG configuration >>>>
3842 23:22:31.359355 Exit from PICG configuration <<<<
3843 23:22:31.362775 [RX_INPUT] configuration >>>>>
3844 23:22:31.366027 [RX_INPUT] configuration <<<<<
3845 23:22:31.369151 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3846 23:22:31.375829 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3847 23:22:31.382325 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 23:22:31.385698 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 23:22:31.392485 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 23:22:31.398808 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 23:22:31.402349 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3852 23:22:31.408730 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3853 23:22:31.412079 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3854 23:22:31.415503 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3855 23:22:31.418978 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3856 23:22:31.425668 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 23:22:31.428749 ===================================
3858 23:22:31.428830 LPDDR4 DRAM CONFIGURATION
3859 23:22:31.432161 ===================================
3860 23:22:31.435509 EX_ROW_EN[0] = 0x0
3861 23:22:31.438774 EX_ROW_EN[1] = 0x0
3862 23:22:31.438855 LP4Y_EN = 0x0
3863 23:22:31.441948 WORK_FSP = 0x0
3864 23:22:31.442029 WL = 0x2
3865 23:22:31.445506 RL = 0x2
3866 23:22:31.445600 BL = 0x2
3867 23:22:31.448628 RPST = 0x0
3868 23:22:31.448708 RD_PRE = 0x0
3869 23:22:31.451704 WR_PRE = 0x1
3870 23:22:31.451785 WR_PST = 0x0
3871 23:22:31.455071 DBI_WR = 0x0
3872 23:22:31.455152 DBI_RD = 0x0
3873 23:22:31.458638 OTF = 0x1
3874 23:22:31.461705 ===================================
3875 23:22:31.465216 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3876 23:22:31.468478 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3877 23:22:31.475040 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 23:22:31.478410 ===================================
3879 23:22:31.478491 LPDDR4 DRAM CONFIGURATION
3880 23:22:31.482056 ===================================
3881 23:22:31.484928 EX_ROW_EN[0] = 0x10
3882 23:22:31.488524 EX_ROW_EN[1] = 0x0
3883 23:22:31.488605 LP4Y_EN = 0x0
3884 23:22:31.491681 WORK_FSP = 0x0
3885 23:22:31.491761 WL = 0x2
3886 23:22:31.494845 RL = 0x2
3887 23:22:31.494925 BL = 0x2
3888 23:22:31.498389 RPST = 0x0
3889 23:22:31.498469 RD_PRE = 0x0
3890 23:22:31.501651 WR_PRE = 0x1
3891 23:22:31.501731 WR_PST = 0x0
3892 23:22:31.504726 DBI_WR = 0x0
3893 23:22:31.504806 DBI_RD = 0x0
3894 23:22:31.508213 OTF = 0x1
3895 23:22:31.511427 ===================================
3896 23:22:31.517954 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3897 23:22:31.521427 nWR fixed to 30
3898 23:22:31.524626 [ModeRegInit_LP4] CH0 RK0
3899 23:22:31.524706 [ModeRegInit_LP4] CH0 RK1
3900 23:22:31.528131 [ModeRegInit_LP4] CH1 RK0
3901 23:22:31.531248 [ModeRegInit_LP4] CH1 RK1
3902 23:22:31.531329 match AC timing 17
3903 23:22:31.537841 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3904 23:22:31.541108 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3905 23:22:31.544693 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3906 23:22:31.551292 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3907 23:22:31.554769 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3908 23:22:31.554854 ==
3909 23:22:31.557764 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 23:22:31.561114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 23:22:31.561213 ==
3912 23:22:31.567854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 23:22:31.574696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3914 23:22:31.577814 [CA 0] Center 37 (7~67) winsize 61
3915 23:22:31.581236 [CA 1] Center 37 (7~67) winsize 61
3916 23:22:31.584416 [CA 2] Center 35 (5~65) winsize 61
3917 23:22:31.587937 [CA 3] Center 35 (5~65) winsize 61
3918 23:22:31.591068 [CA 4] Center 34 (4~65) winsize 62
3919 23:22:31.594351 [CA 5] Center 34 (4~65) winsize 62
3920 23:22:31.594434
3921 23:22:31.597428 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3922 23:22:31.597546
3923 23:22:31.600975 [CATrainingPosCal] consider 1 rank data
3924 23:22:31.604143 u2DelayCellTimex100 = 270/100 ps
3925 23:22:31.607644 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3926 23:22:31.610852 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3927 23:22:31.613987 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3928 23:22:31.617386 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3929 23:22:31.620470 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3930 23:22:31.623886 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
3931 23:22:31.627338
3932 23:22:31.630674 CA PerBit enable=1, Macro0, CA PI delay=34
3933 23:22:31.630757
3934 23:22:31.633742 [CBTSetCACLKResult] CA Dly = 34
3935 23:22:31.633825 CS Dly: 4 (0~35)
3936 23:22:31.633909 ==
3937 23:22:31.637291 Dram Type= 6, Freq= 0, CH_0, rank 1
3938 23:22:31.640523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 23:22:31.640610 ==
3940 23:22:31.647202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3941 23:22:31.653999 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3942 23:22:31.656996 [CA 0] Center 37 (7~67) winsize 61
3943 23:22:31.660590 [CA 1] Center 37 (7~67) winsize 61
3944 23:22:31.663723 [CA 2] Center 35 (5~65) winsize 61
3945 23:22:31.666886 [CA 3] Center 35 (5~65) winsize 61
3946 23:22:31.670389 [CA 4] Center 34 (4~64) winsize 61
3947 23:22:31.673367 [CA 5] Center 33 (3~64) winsize 62
3948 23:22:31.673473
3949 23:22:31.676784 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3950 23:22:31.676890
3951 23:22:31.680273 [CATrainingPosCal] consider 2 rank data
3952 23:22:31.683715 u2DelayCellTimex100 = 270/100 ps
3953 23:22:31.686697 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3954 23:22:31.690230 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3955 23:22:31.693381 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3956 23:22:31.699973 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3957 23:22:31.703272 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3958 23:22:31.706494 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3959 23:22:31.706576
3960 23:22:31.710030 CA PerBit enable=1, Macro0, CA PI delay=34
3961 23:22:31.710113
3962 23:22:31.713179 [CBTSetCACLKResult] CA Dly = 34
3963 23:22:31.713261 CS Dly: 5 (0~37)
3964 23:22:31.713360
3965 23:22:31.716614 ----->DramcWriteLeveling(PI) begin...
3966 23:22:31.716698 ==
3967 23:22:31.720040 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 23:22:31.726450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 23:22:31.726533 ==
3970 23:22:31.729657 Write leveling (Byte 0): 31 => 31
3971 23:22:31.732932 Write leveling (Byte 1): 31 => 31
3972 23:22:31.736452 DramcWriteLeveling(PI) end<-----
3973 23:22:31.736534
3974 23:22:31.736618 ==
3975 23:22:31.739496 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 23:22:31.743013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 23:22:31.743095 ==
3978 23:22:31.746486 [Gating] SW mode calibration
3979 23:22:31.753063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3980 23:22:31.756286 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3981 23:22:31.762744 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 23:22:31.766081 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 23:22:31.769419 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 23:22:31.775924 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3985 23:22:31.779538 0 9 16 | B1->B0 | 3434 2727 | 0 0 | (0 1) (1 1)
3986 23:22:31.782808 0 9 20 | B1->B0 | 2828 2323 | 1 0 | (0 0) (0 0)
3987 23:22:31.789357 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 23:22:31.792530 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 23:22:31.796086 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 23:22:31.802703 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 23:22:31.805858 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 23:22:31.809398 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3993 23:22:31.815624 0 10 16 | B1->B0 | 2e2e 3d3d | 0 0 | (0 0) (0 0)
3994 23:22:31.819093 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 23:22:31.822205 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 23:22:31.828807 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 23:22:31.832260 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 23:22:31.835748 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 23:22:31.842135 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 23:22:31.845466 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 23:22:31.849043 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4002 23:22:31.855445 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 23:22:31.858826 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 23:22:31.862238 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 23:22:31.868670 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 23:22:31.872143 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 23:22:31.875235 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 23:22:31.882096 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 23:22:31.885156 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 23:22:31.888683 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 23:22:31.895276 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 23:22:31.898442 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 23:22:31.902030 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 23:22:31.908592 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 23:22:31.911709 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 23:22:31.915090 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4017 23:22:31.918462 Total UI for P1: 0, mck2ui 16
4018 23:22:31.921824 best dqsien dly found for B0: ( 0, 13, 10)
4019 23:22:31.924894 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 23:22:31.928485 Total UI for P1: 0, mck2ui 16
4021 23:22:31.931682 best dqsien dly found for B1: ( 0, 13, 14)
4022 23:22:31.938244 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4023 23:22:31.941526 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4024 23:22:31.941607
4025 23:22:31.944961 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4026 23:22:31.948354 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4027 23:22:31.951586 [Gating] SW calibration Done
4028 23:22:31.951666 ==
4029 23:22:31.954746 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 23:22:31.958294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 23:22:31.958376 ==
4032 23:22:31.961372 RX Vref Scan: 0
4033 23:22:31.961510
4034 23:22:31.961592 RX Vref 0 -> 0, step: 1
4035 23:22:31.961657
4036 23:22:31.964829 RX Delay -230 -> 252, step: 16
4037 23:22:31.971273 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4038 23:22:31.974699 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4039 23:22:31.977899 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4040 23:22:31.981084 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4041 23:22:31.984604 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4042 23:22:31.991003 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4043 23:22:31.994718 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4044 23:22:31.998052 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4045 23:22:32.001142 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4046 23:22:32.007799 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4047 23:22:32.010908 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4048 23:22:32.014305 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4049 23:22:32.017678 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4050 23:22:32.024076 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4051 23:22:32.027401 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4052 23:22:32.030746 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4053 23:22:32.030826 ==
4054 23:22:32.034359 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 23:22:32.037385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 23:22:32.037467 ==
4057 23:22:32.040674 DQS Delay:
4058 23:22:32.040754 DQS0 = 0, DQS1 = 0
4059 23:22:32.044195 DQM Delay:
4060 23:22:32.044274 DQM0 = 37, DQM1 = 29
4061 23:22:32.044338 DQ Delay:
4062 23:22:32.047293 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4063 23:22:32.050816 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4064 23:22:32.053961 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4065 23:22:32.057277 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4066 23:22:32.057357
4067 23:22:32.057421
4068 23:22:32.060816 ==
4069 23:22:32.063910 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 23:22:32.067104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 23:22:32.067184 ==
4072 23:22:32.067247
4073 23:22:32.067306
4074 23:22:32.070537 TX Vref Scan disable
4075 23:22:32.070617 == TX Byte 0 ==
4076 23:22:32.077378 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4077 23:22:32.080386 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4078 23:22:32.080467 == TX Byte 1 ==
4079 23:22:32.087287 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4080 23:22:32.090506 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4081 23:22:32.090586 ==
4082 23:22:32.093603 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 23:22:32.097068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 23:22:32.097148 ==
4085 23:22:32.097211
4086 23:22:32.097269
4087 23:22:32.100140 TX Vref Scan disable
4088 23:22:32.103580 == TX Byte 0 ==
4089 23:22:32.106841 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4090 23:22:32.110352 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4091 23:22:32.113441 == TX Byte 1 ==
4092 23:22:32.116545 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4093 23:22:32.120097 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4094 23:22:32.123193
4095 23:22:32.123272 [DATLAT]
4096 23:22:32.123336 Freq=600, CH0 RK0
4097 23:22:32.123395
4098 23:22:32.126712 DATLAT Default: 0x9
4099 23:22:32.126791 0, 0xFFFF, sum = 0
4100 23:22:32.129815 1, 0xFFFF, sum = 0
4101 23:22:32.129897 2, 0xFFFF, sum = 0
4102 23:22:32.133213 3, 0xFFFF, sum = 0
4103 23:22:32.133294 4, 0xFFFF, sum = 0
4104 23:22:32.136540 5, 0xFFFF, sum = 0
4105 23:22:32.139810 6, 0xFFFF, sum = 0
4106 23:22:32.139891 7, 0xFFFF, sum = 0
4107 23:22:32.143225 8, 0x0, sum = 1
4108 23:22:32.143306 9, 0x0, sum = 2
4109 23:22:32.143370 10, 0x0, sum = 3
4110 23:22:32.146295 11, 0x0, sum = 4
4111 23:22:32.146376 best_step = 9
4112 23:22:32.146440
4113 23:22:32.146498 ==
4114 23:22:32.149503 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 23:22:32.156181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 23:22:32.156261 ==
4117 23:22:32.156324 RX Vref Scan: 1
4118 23:22:32.156383
4119 23:22:32.159715 RX Vref 0 -> 0, step: 1
4120 23:22:32.159795
4121 23:22:32.162802 RX Delay -195 -> 252, step: 8
4122 23:22:32.162881
4123 23:22:32.166416 Set Vref, RX VrefLevel [Byte0]: 60
4124 23:22:32.169430 [Byte1]: 54
4125 23:22:32.169558
4126 23:22:32.173097 Final RX Vref Byte 0 = 60 to rank0
4127 23:22:32.176096 Final RX Vref Byte 1 = 54 to rank0
4128 23:22:32.179613 Final RX Vref Byte 0 = 60 to rank1
4129 23:22:32.182773 Final RX Vref Byte 1 = 54 to rank1==
4130 23:22:32.186244 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 23:22:32.189663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 23:22:32.189743 ==
4133 23:22:32.192588 DQS Delay:
4134 23:22:32.192667 DQS0 = 0, DQS1 = 0
4135 23:22:32.195814 DQM Delay:
4136 23:22:32.195894 DQM0 = 34, DQM1 = 29
4137 23:22:32.195957 DQ Delay:
4138 23:22:32.199185 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4139 23:22:32.202301 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4140 23:22:32.205876 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4141 23:22:32.209042 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4142 23:22:32.209122
4143 23:22:32.209185
4144 23:22:32.218815 [DQSOSCAuto] RK0, (LSB)MR18= 0x4040, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4145 23:22:32.222203 CH0 RK0: MR19=808, MR18=4040
4146 23:22:32.228882 CH0_RK0: MR19=0x808, MR18=0x4040, DQSOSC=397, MR23=63, INC=166, DEC=110
4147 23:22:32.228968
4148 23:22:32.231958 ----->DramcWriteLeveling(PI) begin...
4149 23:22:32.232047 ==
4150 23:22:32.235494 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 23:22:32.238658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 23:22:32.238739 ==
4153 23:22:32.242111 Write leveling (Byte 0): 30 => 30
4154 23:22:32.245432 Write leveling (Byte 1): 30 => 30
4155 23:22:32.248853 DramcWriteLeveling(PI) end<-----
4156 23:22:32.248933
4157 23:22:32.248995 ==
4158 23:22:32.252148 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 23:22:32.255281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 23:22:32.255362 ==
4161 23:22:32.258857 [Gating] SW mode calibration
4162 23:22:32.265368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4163 23:22:32.272025 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4164 23:22:32.275323 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 23:22:32.278308 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 23:22:32.284843 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4167 23:22:32.288471 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4168 23:22:32.291722 0 9 16 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
4169 23:22:32.298246 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 23:22:32.301772 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 23:22:32.304682 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 23:22:32.311262 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 23:22:32.314832 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 23:22:32.318058 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 23:22:32.324656 0 10 12 | B1->B0 | 2929 3131 | 0 1 | (0 0) (0 0)
4176 23:22:32.328001 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4177 23:22:32.331157 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 23:22:32.337860 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 23:22:32.341088 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 23:22:32.344350 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 23:22:32.351010 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 23:22:32.354370 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 23:22:32.357697 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4184 23:22:32.364213 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4185 23:22:32.367425 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 23:22:32.370502 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 23:22:32.377231 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 23:22:32.380880 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 23:22:32.383675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 23:22:32.390754 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 23:22:32.393513 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 23:22:32.396947 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 23:22:32.403636 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 23:22:32.406778 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 23:22:32.410138 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 23:22:32.417018 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 23:22:32.420074 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 23:22:32.423346 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 23:22:32.430188 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4200 23:22:32.433285 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 23:22:32.436584 Total UI for P1: 0, mck2ui 16
4202 23:22:32.440005 best dqsien dly found for B0: ( 0, 13, 12)
4203 23:22:32.443466 Total UI for P1: 0, mck2ui 16
4204 23:22:32.446663 best dqsien dly found for B1: ( 0, 13, 14)
4205 23:22:32.449884 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4206 23:22:32.453267 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4207 23:22:32.453347
4208 23:22:32.456736 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4209 23:22:32.463251 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4210 23:22:32.463332 [Gating] SW calibration Done
4211 23:22:32.463397 ==
4212 23:22:32.466326 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 23:22:32.472899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 23:22:32.472982 ==
4215 23:22:32.473046 RX Vref Scan: 0
4216 23:22:32.473105
4217 23:22:32.476390 RX Vref 0 -> 0, step: 1
4218 23:22:32.476470
4219 23:22:32.479483 RX Delay -230 -> 252, step: 16
4220 23:22:32.482711 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4221 23:22:32.486332 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4222 23:22:32.492935 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4223 23:22:32.496050 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4224 23:22:32.499401 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4225 23:22:32.502970 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4226 23:22:32.506281 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4227 23:22:32.512827 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4228 23:22:32.515936 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4229 23:22:32.519489 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4230 23:22:32.522771 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4231 23:22:32.529172 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4232 23:22:32.532583 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4233 23:22:32.535944 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4234 23:22:32.539091 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4235 23:22:32.545763 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4236 23:22:32.545844 ==
4237 23:22:32.549113 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 23:22:32.552470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 23:22:32.552551 ==
4240 23:22:32.552615 DQS Delay:
4241 23:22:32.555784 DQS0 = 0, DQS1 = 0
4242 23:22:32.555865 DQM Delay:
4243 23:22:32.558771 DQM0 = 36, DQM1 = 29
4244 23:22:32.558851 DQ Delay:
4245 23:22:32.562018 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4246 23:22:32.565392 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4247 23:22:32.568784 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4248 23:22:32.572190 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4249 23:22:32.572270
4250 23:22:32.572334
4251 23:22:32.572393 ==
4252 23:22:32.575483 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 23:22:32.578929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 23:22:32.579010 ==
4255 23:22:32.582152
4256 23:22:32.582234
4257 23:22:32.582299 TX Vref Scan disable
4258 23:22:32.585333 == TX Byte 0 ==
4259 23:22:32.588870 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4260 23:22:32.592053 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4261 23:22:32.595497 == TX Byte 1 ==
4262 23:22:32.598906 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4263 23:22:32.602060 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4264 23:22:32.605467 ==
4265 23:22:32.605556 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 23:22:32.611933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 23:22:32.612016 ==
4268 23:22:32.612081
4269 23:22:32.612141
4270 23:22:32.615091 TX Vref Scan disable
4271 23:22:32.615173 == TX Byte 0 ==
4272 23:22:32.621920 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4273 23:22:32.625336 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4274 23:22:32.625418 == TX Byte 1 ==
4275 23:22:32.631944 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4276 23:22:32.635161 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4277 23:22:32.635242
4278 23:22:32.635307 [DATLAT]
4279 23:22:32.638195 Freq=600, CH0 RK1
4280 23:22:32.638277
4281 23:22:32.638341 DATLAT Default: 0x9
4282 23:22:32.641473 0, 0xFFFF, sum = 0
4283 23:22:32.641594 1, 0xFFFF, sum = 0
4284 23:22:32.645075 2, 0xFFFF, sum = 0
4285 23:22:32.645158 3, 0xFFFF, sum = 0
4286 23:22:32.648161 4, 0xFFFF, sum = 0
4287 23:22:32.651651 5, 0xFFFF, sum = 0
4288 23:22:32.651734 6, 0xFFFF, sum = 0
4289 23:22:32.654857 7, 0xFFFF, sum = 0
4290 23:22:32.654939 8, 0x0, sum = 1
4291 23:22:32.655005 9, 0x0, sum = 2
4292 23:22:32.658114 10, 0x0, sum = 3
4293 23:22:32.658205 11, 0x0, sum = 4
4294 23:22:32.661413 best_step = 9
4295 23:22:32.661534
4296 23:22:32.661618 ==
4297 23:22:32.664715 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 23:22:32.668244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 23:22:32.668326 ==
4300 23:22:32.671688 RX Vref Scan: 0
4301 23:22:32.671769
4302 23:22:32.671833 RX Vref 0 -> 0, step: 1
4303 23:22:32.671896
4304 23:22:32.674591 RX Delay -195 -> 252, step: 8
4305 23:22:32.682028 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4306 23:22:32.685472 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4307 23:22:32.688686 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4308 23:22:32.692134 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4309 23:22:32.698767 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4310 23:22:32.701938 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4311 23:22:32.704966 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4312 23:22:32.708462 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4313 23:22:32.715240 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4314 23:22:32.718481 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4315 23:22:32.721952 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4316 23:22:32.725369 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4317 23:22:32.728284 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4318 23:22:32.734863 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4319 23:22:32.738271 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4320 23:22:32.741412 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4321 23:22:32.741519 ==
4322 23:22:32.744738 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 23:22:32.751386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 23:22:32.751467 ==
4325 23:22:32.751531 DQS Delay:
4326 23:22:32.754892 DQS0 = 0, DQS1 = 0
4327 23:22:32.754972 DQM Delay:
4328 23:22:32.755036 DQM0 = 33, DQM1 = 27
4329 23:22:32.758046 DQ Delay:
4330 23:22:32.761451 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4331 23:22:32.764676 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4332 23:22:32.768021 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4333 23:22:32.771284 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4334 23:22:32.771365
4335 23:22:32.771428
4336 23:22:32.777629 [DQSOSCAuto] RK1, (LSB)MR18= 0x6937, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4337 23:22:32.781276 CH0 RK1: MR19=808, MR18=6937
4338 23:22:32.787547 CH0_RK1: MR19=0x808, MR18=0x6937, DQSOSC=390, MR23=63, INC=172, DEC=114
4339 23:22:32.790996 [RxdqsGatingPostProcess] freq 600
4340 23:22:32.794176 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4341 23:22:32.797703 Pre-setting of DQS Precalculation
4342 23:22:32.804338 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4343 23:22:32.804420 ==
4344 23:22:32.807434 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 23:22:32.811035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 23:22:32.811116 ==
4347 23:22:32.817662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4348 23:22:32.823884 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4349 23:22:32.827415 [CA 0] Center 36 (6~66) winsize 61
4350 23:22:32.830509 [CA 1] Center 36 (6~66) winsize 61
4351 23:22:32.834035 [CA 2] Center 34 (4~65) winsize 62
4352 23:22:32.837310 [CA 3] Center 34 (4~65) winsize 62
4353 23:22:32.840771 [CA 4] Center 34 (4~65) winsize 62
4354 23:22:32.844215 [CA 5] Center 33 (3~64) winsize 62
4355 23:22:32.844839
4356 23:22:32.847498 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4357 23:22:32.848066
4358 23:22:32.850834 [CATrainingPosCal] consider 1 rank data
4359 23:22:32.854218 u2DelayCellTimex100 = 270/100 ps
4360 23:22:32.857422 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4361 23:22:32.860513 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4362 23:22:32.863789 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4363 23:22:32.867044 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4364 23:22:32.870571 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4365 23:22:32.873715 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4366 23:22:32.876998
4367 23:22:32.880380 CA PerBit enable=1, Macro0, CA PI delay=33
4368 23:22:32.880857
4369 23:22:32.883649 [CBTSetCACLKResult] CA Dly = 33
4370 23:22:32.884106 CS Dly: 4 (0~35)
4371 23:22:32.884468 ==
4372 23:22:32.887205 Dram Type= 6, Freq= 0, CH_1, rank 1
4373 23:22:32.890170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 23:22:32.893612 ==
4375 23:22:32.896991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 23:22:32.903657 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4377 23:22:32.906824 [CA 0] Center 36 (6~66) winsize 61
4378 23:22:32.910117 [CA 1] Center 36 (6~66) winsize 61
4379 23:22:32.913548 [CA 2] Center 34 (4~65) winsize 62
4380 23:22:32.916826 [CA 3] Center 34 (3~65) winsize 63
4381 23:22:32.919843 [CA 4] Center 34 (4~65) winsize 62
4382 23:22:32.923343 [CA 5] Center 33 (3~64) winsize 62
4383 23:22:32.923796
4384 23:22:32.926727 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4385 23:22:32.927280
4386 23:22:32.929937 [CATrainingPosCal] consider 2 rank data
4387 23:22:32.933131 u2DelayCellTimex100 = 270/100 ps
4388 23:22:32.936571 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4389 23:22:32.940339 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4390 23:22:32.943556 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4391 23:22:32.949798 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4392 23:22:32.953018 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4393 23:22:32.956221 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4394 23:22:32.956706
4395 23:22:32.959558 CA PerBit enable=1, Macro0, CA PI delay=33
4396 23:22:32.960019
4397 23:22:32.962861 [CBTSetCACLKResult] CA Dly = 33
4398 23:22:32.963443 CS Dly: 4 (0~36)
4399 23:22:32.963821
4400 23:22:32.966190 ----->DramcWriteLeveling(PI) begin...
4401 23:22:32.966662 ==
4402 23:22:32.969541 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 23:22:32.976591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 23:22:32.977333 ==
4405 23:22:32.979782 Write leveling (Byte 0): 28 => 28
4406 23:22:32.982917 Write leveling (Byte 1): 30 => 30
4407 23:22:32.986263 DramcWriteLeveling(PI) end<-----
4408 23:22:32.986728
4409 23:22:32.987104 ==
4410 23:22:32.989549 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 23:22:32.992762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 23:22:32.993254 ==
4413 23:22:32.996645 [Gating] SW mode calibration
4414 23:22:33.002950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4415 23:22:33.006326 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4416 23:22:33.012562 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 23:22:33.016126 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 23:22:33.019263 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 23:22:33.026184 0 9 12 | B1->B0 | 3131 3030 | 1 1 | (1 1) (1 1)
4420 23:22:33.029715 0 9 16 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
4421 23:22:33.032842 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 23:22:33.039458 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 23:22:33.042476 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 23:22:33.045920 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 23:22:33.052599 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 23:22:33.055693 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 23:22:33.059088 0 10 12 | B1->B0 | 2828 2727 | 0 1 | (0 0) (0 0)
4428 23:22:33.065529 0 10 16 | B1->B0 | 4343 4242 | 0 1 | (0 0) (0 0)
4429 23:22:33.069412 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 23:22:33.072480 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 23:22:33.079225 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 23:22:33.082275 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 23:22:33.085697 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 23:22:33.092166 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 23:22:33.095831 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4436 23:22:33.098940 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4437 23:22:33.105907 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 23:22:33.108867 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 23:22:33.111835 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 23:22:33.118867 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 23:22:33.121957 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 23:22:33.125740 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 23:22:33.132196 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 23:22:33.135309 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 23:22:33.138625 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 23:22:33.145471 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 23:22:33.148649 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 23:22:33.151997 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 23:22:33.158454 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 23:22:33.161690 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 23:22:33.165234 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 23:22:33.171520 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4453 23:22:33.172095 Total UI for P1: 0, mck2ui 16
4454 23:22:33.178333 best dqsien dly found for B0: ( 0, 13, 14)
4455 23:22:33.181811 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 23:22:33.184950 Total UI for P1: 0, mck2ui 16
4457 23:22:33.187984 best dqsien dly found for B1: ( 0, 13, 16)
4458 23:22:33.191439 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4459 23:22:33.194918 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4460 23:22:33.195477
4461 23:22:33.198166 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4462 23:22:33.201382 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4463 23:22:33.204946 [Gating] SW calibration Done
4464 23:22:33.205545 ==
4465 23:22:33.208503 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 23:22:33.211564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 23:22:33.214699 ==
4468 23:22:33.215159 RX Vref Scan: 0
4469 23:22:33.215522
4470 23:22:33.218409 RX Vref 0 -> 0, step: 1
4471 23:22:33.218965
4472 23:22:33.221226 RX Delay -230 -> 252, step: 16
4473 23:22:33.224578 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4474 23:22:33.227716 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4475 23:22:33.231514 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4476 23:22:33.237760 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4477 23:22:33.241531 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4478 23:22:33.244598 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4479 23:22:33.248090 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4480 23:22:33.250893 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4481 23:22:33.257696 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4482 23:22:33.261142 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4483 23:22:33.264552 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4484 23:22:33.268034 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4485 23:22:33.274154 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4486 23:22:33.277602 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4487 23:22:33.280971 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4488 23:22:33.283921 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4489 23:22:33.284388 ==
4490 23:22:33.287377 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 23:22:33.293793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 23:22:33.294606 ==
4493 23:22:33.295153 DQS Delay:
4494 23:22:33.297123 DQS0 = 0, DQS1 = 0
4495 23:22:33.297638 DQM Delay:
4496 23:22:33.298017 DQM0 = 37, DQM1 = 28
4497 23:22:33.300755 DQ Delay:
4498 23:22:33.303935 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4499 23:22:33.307126 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4500 23:22:33.310641 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4501 23:22:33.314060 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4502 23:22:33.314524
4503 23:22:33.314938
4504 23:22:33.315285 ==
4505 23:22:33.317208 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 23:22:33.320620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 23:22:33.321089 ==
4508 23:22:33.321457
4509 23:22:33.321871
4510 23:22:33.323895 TX Vref Scan disable
4511 23:22:33.326904 == TX Byte 0 ==
4512 23:22:33.330307 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4513 23:22:33.333834 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4514 23:22:33.337002 == TX Byte 1 ==
4515 23:22:33.340424 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4516 23:22:33.343970 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4517 23:22:33.344529 ==
4518 23:22:33.347524 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 23:22:33.350350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 23:22:33.353316 ==
4521 23:22:33.353817
4522 23:22:33.354183
4523 23:22:33.354524 TX Vref Scan disable
4524 23:22:33.357356 == TX Byte 0 ==
4525 23:22:33.360958 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4526 23:22:33.367286 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4527 23:22:33.367842 == TX Byte 1 ==
4528 23:22:33.370763 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4529 23:22:33.377234 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4530 23:22:33.377727
4531 23:22:33.378092 [DATLAT]
4532 23:22:33.378435 Freq=600, CH1 RK0
4533 23:22:33.378766
4534 23:22:33.380690 DATLAT Default: 0x9
4535 23:22:33.381149 0, 0xFFFF, sum = 0
4536 23:22:33.384120 1, 0xFFFF, sum = 0
4537 23:22:33.387229 2, 0xFFFF, sum = 0
4538 23:22:33.387697 3, 0xFFFF, sum = 0
4539 23:22:33.390944 4, 0xFFFF, sum = 0
4540 23:22:33.391540 5, 0xFFFF, sum = 0
4541 23:22:33.394132 6, 0xFFFF, sum = 0
4542 23:22:33.394705 7, 0xFFFF, sum = 0
4543 23:22:33.397274 8, 0x0, sum = 1
4544 23:22:33.397783 9, 0x0, sum = 2
4545 23:22:33.398156 10, 0x0, sum = 3
4546 23:22:33.400536 11, 0x0, sum = 4
4547 23:22:33.401110 best_step = 9
4548 23:22:33.401510
4549 23:22:33.401860 ==
4550 23:22:33.403811 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 23:22:33.410523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 23:22:33.411180 ==
4553 23:22:33.411612 RX Vref Scan: 1
4554 23:22:33.411962
4555 23:22:33.413641 RX Vref 0 -> 0, step: 1
4556 23:22:33.414108
4557 23:22:33.417118 RX Delay -195 -> 252, step: 8
4558 23:22:33.417738
4559 23:22:33.420483 Set Vref, RX VrefLevel [Byte0]: 55
4560 23:22:33.423702 [Byte1]: 45
4561 23:22:33.424165
4562 23:22:33.427542 Final RX Vref Byte 0 = 55 to rank0
4563 23:22:33.430329 Final RX Vref Byte 1 = 45 to rank0
4564 23:22:33.433883 Final RX Vref Byte 0 = 55 to rank1
4565 23:22:33.437423 Final RX Vref Byte 1 = 45 to rank1==
4566 23:22:33.440143 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 23:22:33.443518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 23:22:33.443984 ==
4569 23:22:33.447325 DQS Delay:
4570 23:22:33.447912 DQS0 = 0, DQS1 = 0
4571 23:22:33.450559 DQM Delay:
4572 23:22:33.451112 DQM0 = 38, DQM1 = 28
4573 23:22:33.451481 DQ Delay:
4574 23:22:33.454111 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4575 23:22:33.457092 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4576 23:22:33.460640 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4577 23:22:33.463906 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =36
4578 23:22:33.464371
4579 23:22:33.464736
4580 23:22:33.473903 [DQSOSCAuto] RK0, (LSB)MR18= 0x212f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4581 23:22:33.477433 CH1 RK0: MR19=808, MR18=212F
4582 23:22:33.483569 CH1_RK0: MR19=0x808, MR18=0x212F, DQSOSC=400, MR23=63, INC=163, DEC=109
4583 23:22:33.484122
4584 23:22:33.486741 ----->DramcWriteLeveling(PI) begin...
4585 23:22:33.487244 ==
4586 23:22:33.489936 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 23:22:33.493891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 23:22:33.494456 ==
4589 23:22:33.496781 Write leveling (Byte 0): 28 => 28
4590 23:22:33.500272 Write leveling (Byte 1): 32 => 32
4591 23:22:33.503633 DramcWriteLeveling(PI) end<-----
4592 23:22:33.504101
4593 23:22:33.504674 ==
4594 23:22:33.506811 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 23:22:33.509859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 23:22:33.510331 ==
4597 23:22:33.513461 [Gating] SW mode calibration
4598 23:22:33.520093 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4599 23:22:33.526853 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4600 23:22:33.529549 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 23:22:33.532772 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 23:22:33.539981 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4603 23:22:33.543587 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4604 23:22:33.546463 0 9 16 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
4605 23:22:33.552855 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 23:22:33.556272 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 23:22:33.559281 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 23:22:33.566235 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 23:22:33.569561 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 23:22:33.572727 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4611 23:22:33.579417 0 10 12 | B1->B0 | 3131 3a3a | 1 0 | (0 0) (0 0)
4612 23:22:33.582673 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4613 23:22:33.585984 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 23:22:33.592258 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 23:22:33.595882 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 23:22:33.599466 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 23:22:33.605678 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 23:22:33.609242 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 23:22:33.612405 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4620 23:22:33.618687 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 23:22:33.622440 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 23:22:33.625639 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 23:22:33.632491 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 23:22:33.635780 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 23:22:33.638833 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 23:22:33.645320 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 23:22:33.648758 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 23:22:33.651813 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 23:22:33.658853 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 23:22:33.661943 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 23:22:33.665697 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 23:22:33.672221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 23:22:33.675175 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 23:22:33.678405 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 23:22:33.685655 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4636 23:22:33.688290 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 23:22:33.691629 Total UI for P1: 0, mck2ui 16
4638 23:22:33.694890 best dqsien dly found for B0: ( 0, 13, 12)
4639 23:22:33.698573 Total UI for P1: 0, mck2ui 16
4640 23:22:33.701565 best dqsien dly found for B1: ( 0, 13, 12)
4641 23:22:33.704868 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4642 23:22:33.708706 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4643 23:22:33.709282
4644 23:22:33.711462 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4645 23:22:33.714632 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4646 23:22:33.717796 [Gating] SW calibration Done
4647 23:22:33.718391 ==
4648 23:22:33.721286 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 23:22:33.728144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 23:22:33.728710 ==
4651 23:22:33.729082 RX Vref Scan: 0
4652 23:22:33.729428
4653 23:22:33.730952 RX Vref 0 -> 0, step: 1
4654 23:22:33.731414
4655 23:22:33.734549 RX Delay -230 -> 252, step: 16
4656 23:22:33.737928 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4657 23:22:33.741035 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4658 23:22:33.744893 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4659 23:22:33.750924 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4660 23:22:33.754167 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4661 23:22:33.757780 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4662 23:22:33.761103 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4663 23:22:33.767494 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4664 23:22:33.771016 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4665 23:22:33.774093 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4666 23:22:33.777433 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4667 23:22:33.784299 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4668 23:22:33.787596 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4669 23:22:33.790561 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4670 23:22:33.794182 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4671 23:22:33.797360 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4672 23:22:33.800700 ==
4673 23:22:33.804183 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 23:22:33.807219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 23:22:33.807689 ==
4676 23:22:33.808064 DQS Delay:
4677 23:22:33.810484 DQS0 = 0, DQS1 = 0
4678 23:22:33.811048 DQM Delay:
4679 23:22:33.813774 DQM0 = 36, DQM1 = 27
4680 23:22:33.814339 DQ Delay:
4681 23:22:33.816682 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4682 23:22:33.820603 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4683 23:22:33.823746 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4684 23:22:33.827298 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4685 23:22:33.827858
4686 23:22:33.828225
4687 23:22:33.828564 ==
4688 23:22:33.830002 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 23:22:33.833389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 23:22:33.833905 ==
4691 23:22:33.834275
4692 23:22:33.836804
4693 23:22:33.837363 TX Vref Scan disable
4694 23:22:33.840187 == TX Byte 0 ==
4695 23:22:33.843658 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4696 23:22:33.846589 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4697 23:22:33.850047 == TX Byte 1 ==
4698 23:22:33.853189 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4699 23:22:33.856667 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4700 23:22:33.857131 ==
4701 23:22:33.859633 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 23:22:33.866285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 23:22:33.866710 ==
4704 23:22:33.867042
4705 23:22:33.867348
4706 23:22:33.867644 TX Vref Scan disable
4707 23:22:33.871539 == TX Byte 0 ==
4708 23:22:33.874556 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4709 23:22:33.881195 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4710 23:22:33.881763 == TX Byte 1 ==
4711 23:22:33.884454 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4712 23:22:33.891063 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4713 23:22:33.891591
4714 23:22:33.891925 [DATLAT]
4715 23:22:33.892238 Freq=600, CH1 RK1
4716 23:22:33.892581
4717 23:22:33.894214 DATLAT Default: 0x9
4718 23:22:33.894632 0, 0xFFFF, sum = 0
4719 23:22:33.897724 1, 0xFFFF, sum = 0
4720 23:22:33.901168 2, 0xFFFF, sum = 0
4721 23:22:33.901733 3, 0xFFFF, sum = 0
4722 23:22:33.904217 4, 0xFFFF, sum = 0
4723 23:22:33.904644 5, 0xFFFF, sum = 0
4724 23:22:33.907895 6, 0xFFFF, sum = 0
4725 23:22:33.908423 7, 0xFFFF, sum = 0
4726 23:22:33.910715 8, 0x0, sum = 1
4727 23:22:33.911142 9, 0x0, sum = 2
4728 23:22:33.911484 10, 0x0, sum = 3
4729 23:22:33.914385 11, 0x0, sum = 4
4730 23:22:33.914931 best_step = 9
4731 23:22:33.915273
4732 23:22:33.915587 ==
4733 23:22:33.917250 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 23:22:33.924219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 23:22:33.924749 ==
4736 23:22:33.925087 RX Vref Scan: 0
4737 23:22:33.925397
4738 23:22:33.927603 RX Vref 0 -> 0, step: 1
4739 23:22:33.928134
4740 23:22:33.930778 RX Delay -195 -> 252, step: 8
4741 23:22:33.933866 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4742 23:22:33.940574 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4743 23:22:33.944053 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4744 23:22:33.947435 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4745 23:22:33.950583 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4746 23:22:33.956888 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4747 23:22:33.960468 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4748 23:22:33.963951 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4749 23:22:33.967057 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4750 23:22:33.973577 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4751 23:22:33.977019 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4752 23:22:33.980387 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4753 23:22:33.983527 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4754 23:22:33.986709 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4755 23:22:33.993531 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4756 23:22:33.997416 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4757 23:22:33.997978 ==
4758 23:22:34.000264 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 23:22:34.003442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 23:22:34.003867 ==
4761 23:22:34.006574 DQS Delay:
4762 23:22:34.006996 DQS0 = 0, DQS1 = 0
4763 23:22:34.010038 DQM Delay:
4764 23:22:34.010457 DQM0 = 36, DQM1 = 30
4765 23:22:34.010792 DQ Delay:
4766 23:22:34.013296 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4767 23:22:34.016648 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4768 23:22:34.020053 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4769 23:22:34.023186 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =36
4770 23:22:34.023782
4771 23:22:34.024294
4772 23:22:34.033172 [DQSOSCAuto] RK1, (LSB)MR18= 0x3454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4773 23:22:34.036565 CH1 RK1: MR19=808, MR18=3454
4774 23:22:34.043021 CH1_RK1: MR19=0x808, MR18=0x3454, DQSOSC=393, MR23=63, INC=169, DEC=113
4775 23:22:34.043446 [RxdqsGatingPostProcess] freq 600
4776 23:22:34.049954 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4777 23:22:34.053263 Pre-setting of DQS Precalculation
4778 23:22:34.056220 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4779 23:22:34.066302 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4780 23:22:34.072691 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4781 23:22:34.073113
4782 23:22:34.073540
4783 23:22:34.075995 [Calibration Summary] 1200 Mbps
4784 23:22:34.076414 CH 0, Rank 0
4785 23:22:34.079241 SW Impedance : PASS
4786 23:22:34.082692 DUTY Scan : NO K
4787 23:22:34.083115 ZQ Calibration : PASS
4788 23:22:34.086030 Jitter Meter : NO K
4789 23:22:34.086451 CBT Training : PASS
4790 23:22:34.089384 Write leveling : PASS
4791 23:22:34.092634 RX DQS gating : PASS
4792 23:22:34.093064 RX DQ/DQS(RDDQC) : PASS
4793 23:22:34.095775 TX DQ/DQS : PASS
4794 23:22:34.099327 RX DATLAT : PASS
4795 23:22:34.099743 RX DQ/DQS(Engine): PASS
4796 23:22:34.102515 TX OE : NO K
4797 23:22:34.102933 All Pass.
4798 23:22:34.103263
4799 23:22:34.105693 CH 0, Rank 1
4800 23:22:34.106107 SW Impedance : PASS
4801 23:22:34.108895 DUTY Scan : NO K
4802 23:22:34.112544 ZQ Calibration : PASS
4803 23:22:34.112963 Jitter Meter : NO K
4804 23:22:34.115707 CBT Training : PASS
4805 23:22:34.118807 Write leveling : PASS
4806 23:22:34.119225 RX DQS gating : PASS
4807 23:22:34.122138 RX DQ/DQS(RDDQC) : PASS
4808 23:22:34.125516 TX DQ/DQS : PASS
4809 23:22:34.125997 RX DATLAT : PASS
4810 23:22:34.128850 RX DQ/DQS(Engine): PASS
4811 23:22:34.132134 TX OE : NO K
4812 23:22:34.132561 All Pass.
4813 23:22:34.132898
4814 23:22:34.133208 CH 1, Rank 0
4815 23:22:34.135562 SW Impedance : PASS
4816 23:22:34.138552 DUTY Scan : NO K
4817 23:22:34.138968 ZQ Calibration : PASS
4818 23:22:34.141729 Jitter Meter : NO K
4819 23:22:34.145148 CBT Training : PASS
4820 23:22:34.145613 Write leveling : PASS
4821 23:22:34.148584 RX DQS gating : PASS
4822 23:22:34.151888 RX DQ/DQS(RDDQC) : PASS
4823 23:22:34.152319 TX DQ/DQS : PASS
4824 23:22:34.155236 RX DATLAT : PASS
4825 23:22:34.155650 RX DQ/DQS(Engine): PASS
4826 23:22:34.158634 TX OE : NO K
4827 23:22:34.159053 All Pass.
4828 23:22:34.159381
4829 23:22:34.161953 CH 1, Rank 1
4830 23:22:34.162367 SW Impedance : PASS
4831 23:22:34.165171 DUTY Scan : NO K
4832 23:22:34.168396 ZQ Calibration : PASS
4833 23:22:34.168817 Jitter Meter : NO K
4834 23:22:34.171918 CBT Training : PASS
4835 23:22:34.175055 Write leveling : PASS
4836 23:22:34.175493 RX DQS gating : PASS
4837 23:22:34.178187 RX DQ/DQS(RDDQC) : PASS
4838 23:22:34.181899 TX DQ/DQS : PASS
4839 23:22:34.182320 RX DATLAT : PASS
4840 23:22:34.185167 RX DQ/DQS(Engine): PASS
4841 23:22:34.188227 TX OE : NO K
4842 23:22:34.188648 All Pass.
4843 23:22:34.188981
4844 23:22:34.191520 DramC Write-DBI off
4845 23:22:34.191954 PER_BANK_REFRESH: Hybrid Mode
4846 23:22:34.195182 TX_TRACKING: ON
4847 23:22:34.201729 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4848 23:22:34.204980 [FAST_K] Save calibration result to emmc
4849 23:22:34.211597 dramc_set_vcore_voltage set vcore to 662500
4850 23:22:34.212022 Read voltage for 933, 3
4851 23:22:34.215021 Vio18 = 0
4852 23:22:34.215441 Vcore = 662500
4853 23:22:34.215773 Vdram = 0
4854 23:22:34.218137 Vddq = 0
4855 23:22:34.218694 Vmddr = 0
4856 23:22:34.221403 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4857 23:22:34.228150 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4858 23:22:34.231264 MEM_TYPE=3, freq_sel=17
4859 23:22:34.234831 sv_algorithm_assistance_LP4_1600
4860 23:22:34.238167 ============ PULL DRAM RESETB DOWN ============
4861 23:22:34.241084 ========== PULL DRAM RESETB DOWN end =========
4862 23:22:34.244469 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4863 23:22:34.248055 ===================================
4864 23:22:34.251084 LPDDR4 DRAM CONFIGURATION
4865 23:22:34.254404 ===================================
4866 23:22:34.257755 EX_ROW_EN[0] = 0x0
4867 23:22:34.258305 EX_ROW_EN[1] = 0x0
4868 23:22:34.261205 LP4Y_EN = 0x0
4869 23:22:34.261828 WORK_FSP = 0x0
4870 23:22:34.264502 WL = 0x3
4871 23:22:34.265101 RL = 0x3
4872 23:22:34.267776 BL = 0x2
4873 23:22:34.268365 RPST = 0x0
4874 23:22:34.271133 RD_PRE = 0x0
4875 23:22:34.274134 WR_PRE = 0x1
4876 23:22:34.274360 WR_PST = 0x0
4877 23:22:34.277672 DBI_WR = 0x0
4878 23:22:34.277895 DBI_RD = 0x0
4879 23:22:34.281008 OTF = 0x1
4880 23:22:34.284397 ===================================
4881 23:22:34.287850 ===================================
4882 23:22:34.288075 ANA top config
4883 23:22:34.291273 ===================================
4884 23:22:34.294278 DLL_ASYNC_EN = 0
4885 23:22:34.294511 ALL_SLAVE_EN = 1
4886 23:22:34.297650 NEW_RANK_MODE = 1
4887 23:22:34.301030 DLL_IDLE_MODE = 1
4888 23:22:34.304408 LP45_APHY_COMB_EN = 1
4889 23:22:34.307671 TX_ODT_DIS = 1
4890 23:22:34.307917 NEW_8X_MODE = 1
4891 23:22:34.310923 ===================================
4892 23:22:34.314278 ===================================
4893 23:22:34.317198 data_rate = 1866
4894 23:22:34.320772 CKR = 1
4895 23:22:34.324049 DQ_P2S_RATIO = 8
4896 23:22:34.327269 ===================================
4897 23:22:34.330889 CA_P2S_RATIO = 8
4898 23:22:34.334170 DQ_CA_OPEN = 0
4899 23:22:34.334421 DQ_SEMI_OPEN = 0
4900 23:22:34.337291 CA_SEMI_OPEN = 0
4901 23:22:34.340524 CA_FULL_RATE = 0
4902 23:22:34.344189 DQ_CKDIV4_EN = 1
4903 23:22:34.347224 CA_CKDIV4_EN = 1
4904 23:22:34.350364 CA_PREDIV_EN = 0
4905 23:22:34.350619 PH8_DLY = 0
4906 23:22:34.354074 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4907 23:22:34.357219 DQ_AAMCK_DIV = 4
4908 23:22:34.360509 CA_AAMCK_DIV = 4
4909 23:22:34.363867 CA_ADMCK_DIV = 4
4910 23:22:34.367195 DQ_TRACK_CA_EN = 0
4911 23:22:34.367420 CA_PICK = 933
4912 23:22:34.370369 CA_MCKIO = 933
4913 23:22:34.373948 MCKIO_SEMI = 0
4914 23:22:34.377147 PLL_FREQ = 3732
4915 23:22:34.380642 DQ_UI_PI_RATIO = 32
4916 23:22:34.384000 CA_UI_PI_RATIO = 0
4917 23:22:34.387108 ===================================
4918 23:22:34.390326 ===================================
4919 23:22:34.390552 memory_type:LPDDR4
4920 23:22:34.393985 GP_NUM : 10
4921 23:22:34.397190 SRAM_EN : 1
4922 23:22:34.397460 MD32_EN : 0
4923 23:22:34.400505 ===================================
4924 23:22:34.403933 [ANA_INIT] >>>>>>>>>>>>>>
4925 23:22:34.406923 <<<<<< [CONFIGURE PHASE]: ANA_TX
4926 23:22:34.410395 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4927 23:22:34.413907 ===================================
4928 23:22:34.417053 data_rate = 1866,PCW = 0X8f00
4929 23:22:34.420269 ===================================
4930 23:22:34.423750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4931 23:22:34.427115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 23:22:34.433812 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4933 23:22:34.437005 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4934 23:22:34.443347 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4935 23:22:34.446928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4936 23:22:34.447204 [ANA_INIT] flow start
4937 23:22:34.450499 [ANA_INIT] PLL >>>>>>>>
4938 23:22:34.453584 [ANA_INIT] PLL <<<<<<<<
4939 23:22:34.454016 [ANA_INIT] MIDPI >>>>>>>>
4940 23:22:34.456757 [ANA_INIT] MIDPI <<<<<<<<
4941 23:22:34.460422 [ANA_INIT] DLL >>>>>>>>
4942 23:22:34.460838 [ANA_INIT] flow end
4943 23:22:34.463473 ============ LP4 DIFF to SE enter ============
4944 23:22:34.470209 ============ LP4 DIFF to SE exit ============
4945 23:22:34.470629 [ANA_INIT] <<<<<<<<<<<<<
4946 23:22:34.473453 [Flow] Enable top DCM control >>>>>
4947 23:22:34.476728 [Flow] Enable top DCM control <<<<<
4948 23:22:34.480127 Enable DLL master slave shuffle
4949 23:22:34.486621 ==============================================================
4950 23:22:34.487045 Gating Mode config
4951 23:22:34.493597 ==============================================================
4952 23:22:34.496991 Config description:
4953 23:22:34.506618 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4954 23:22:34.513106 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4955 23:22:34.516634 SELPH_MODE 0: By rank 1: By Phase
4956 23:22:34.523313 ==============================================================
4957 23:22:34.526417 GAT_TRACK_EN = 1
4958 23:22:34.530076 RX_GATING_MODE = 2
4959 23:22:34.530490 RX_GATING_TRACK_MODE = 2
4960 23:22:34.533275 SELPH_MODE = 1
4961 23:22:34.536434 PICG_EARLY_EN = 1
4962 23:22:34.539931 VALID_LAT_VALUE = 1
4963 23:22:34.546412 ==============================================================
4964 23:22:34.549956 Enter into Gating configuration >>>>
4965 23:22:34.553035 Exit from Gating configuration <<<<
4966 23:22:34.556456 Enter into DVFS_PRE_config >>>>>
4967 23:22:34.566254 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4968 23:22:34.569504 Exit from DVFS_PRE_config <<<<<
4969 23:22:34.572837 Enter into PICG configuration >>>>
4970 23:22:34.576238 Exit from PICG configuration <<<<
4971 23:22:34.579635 [RX_INPUT] configuration >>>>>
4972 23:22:34.582717 [RX_INPUT] configuration <<<<<
4973 23:22:34.586143 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4974 23:22:34.592798 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4975 23:22:34.599416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 23:22:34.606179 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 23:22:34.612494 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 23:22:34.616226 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 23:22:34.622536 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4980 23:22:34.625598 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4981 23:22:34.629065 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4982 23:22:34.632489 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4983 23:22:34.639339 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4984 23:22:34.642606 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4985 23:22:34.646066 ===================================
4986 23:22:34.649237 LPDDR4 DRAM CONFIGURATION
4987 23:22:34.652516 ===================================
4988 23:22:34.652994 EX_ROW_EN[0] = 0x0
4989 23:22:34.656040 EX_ROW_EN[1] = 0x0
4990 23:22:34.656454 LP4Y_EN = 0x0
4991 23:22:34.659250 WORK_FSP = 0x0
4992 23:22:34.659667 WL = 0x3
4993 23:22:34.662480 RL = 0x3
4994 23:22:34.662898 BL = 0x2
4995 23:22:34.665961 RPST = 0x0
4996 23:22:34.666376 RD_PRE = 0x0
4997 23:22:34.669076 WR_PRE = 0x1
4998 23:22:34.669532 WR_PST = 0x0
4999 23:22:34.672612 DBI_WR = 0x0
5000 23:22:34.673028 DBI_RD = 0x0
5001 23:22:34.675745 OTF = 0x1
5002 23:22:34.679009 ===================================
5003 23:22:34.682094 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5004 23:22:34.685393 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5005 23:22:34.692043 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 23:22:34.695178 ===================================
5007 23:22:34.698805 LPDDR4 DRAM CONFIGURATION
5008 23:22:34.699030 ===================================
5009 23:22:34.701975 EX_ROW_EN[0] = 0x10
5010 23:22:34.705512 EX_ROW_EN[1] = 0x0
5011 23:22:34.705737 LP4Y_EN = 0x0
5012 23:22:34.708620 WORK_FSP = 0x0
5013 23:22:34.708842 WL = 0x3
5014 23:22:34.712125 RL = 0x3
5015 23:22:34.712348 BL = 0x2
5016 23:22:34.715285 RPST = 0x0
5017 23:22:34.715508 RD_PRE = 0x0
5018 23:22:34.718627 WR_PRE = 0x1
5019 23:22:34.718850 WR_PST = 0x0
5020 23:22:34.721745 DBI_WR = 0x0
5021 23:22:34.721969 DBI_RD = 0x0
5022 23:22:34.725099 OTF = 0x1
5023 23:22:34.728553 ===================================
5024 23:22:34.735075 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5025 23:22:34.738408 nWR fixed to 30
5026 23:22:34.741820 [ModeRegInit_LP4] CH0 RK0
5027 23:22:34.742050 [ModeRegInit_LP4] CH0 RK1
5028 23:22:34.745063 [ModeRegInit_LP4] CH1 RK0
5029 23:22:34.748491 [ModeRegInit_LP4] CH1 RK1
5030 23:22:34.748715 match AC timing 9
5031 23:22:34.755111 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5032 23:22:34.758311 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5033 23:22:34.761778 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5034 23:22:34.768216 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5035 23:22:34.771463 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5036 23:22:34.771687 ==
5037 23:22:34.774987 Dram Type= 6, Freq= 0, CH_0, rank 0
5038 23:22:34.778169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5039 23:22:34.778395 ==
5040 23:22:34.784924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5041 23:22:34.791587 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5042 23:22:34.794820 [CA 0] Center 38 (8~69) winsize 62
5043 23:22:34.798106 [CA 1] Center 38 (7~69) winsize 63
5044 23:22:34.801660 [CA 2] Center 35 (5~66) winsize 62
5045 23:22:34.804875 [CA 3] Center 35 (5~66) winsize 62
5046 23:22:34.807963 [CA 4] Center 34 (4~65) winsize 62
5047 23:22:34.811144 [CA 5] Center 33 (3~64) winsize 62
5048 23:22:34.811379
5049 23:22:34.814556 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5050 23:22:34.814861
5051 23:22:34.818076 [CATrainingPosCal] consider 1 rank data
5052 23:22:34.821150 u2DelayCellTimex100 = 270/100 ps
5053 23:22:34.824609 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5054 23:22:34.827629 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5055 23:22:34.831287 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5056 23:22:34.834345 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5057 23:22:34.837666 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5058 23:22:34.844506 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5059 23:22:34.844861
5060 23:22:34.847808 CA PerBit enable=1, Macro0, CA PI delay=33
5061 23:22:34.848162
5062 23:22:34.851266 [CBTSetCACLKResult] CA Dly = 33
5063 23:22:34.851695 CS Dly: 7 (0~38)
5064 23:22:34.852028 ==
5065 23:22:34.854299 Dram Type= 6, Freq= 0, CH_0, rank 1
5066 23:22:34.857576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5067 23:22:34.861089 ==
5068 23:22:34.864417 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5069 23:22:34.870752 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5070 23:22:34.874229 [CA 0] Center 38 (8~69) winsize 62
5071 23:22:34.877467 [CA 1] Center 38 (8~69) winsize 62
5072 23:22:34.881049 [CA 2] Center 35 (5~66) winsize 62
5073 23:22:34.884162 [CA 3] Center 35 (5~66) winsize 62
5074 23:22:34.887611 [CA 4] Center 34 (4~64) winsize 61
5075 23:22:34.891137 [CA 5] Center 33 (3~64) winsize 62
5076 23:22:34.891557
5077 23:22:34.894094 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5078 23:22:34.894512
5079 23:22:34.897577 [CATrainingPosCal] consider 2 rank data
5080 23:22:34.900782 u2DelayCellTimex100 = 270/100 ps
5081 23:22:34.904199 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5082 23:22:34.907291 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5083 23:22:34.910852 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5084 23:22:34.917438 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5085 23:22:34.920578 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5086 23:22:34.923907 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5087 23:22:34.924131
5088 23:22:34.927032 CA PerBit enable=1, Macro0, CA PI delay=33
5089 23:22:34.927256
5090 23:22:34.930440 [CBTSetCACLKResult] CA Dly = 33
5091 23:22:34.930664 CS Dly: 7 (0~39)
5092 23:22:34.930844
5093 23:22:34.933949 ----->DramcWriteLeveling(PI) begin...
5094 23:22:34.937019 ==
5095 23:22:34.937242 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 23:22:34.943688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 23:22:34.943915 ==
5098 23:22:34.946965 Write leveling (Byte 0): 33 => 33
5099 23:22:34.950061 Write leveling (Byte 1): 31 => 31
5100 23:22:34.953412 DramcWriteLeveling(PI) end<-----
5101 23:22:34.953662
5102 23:22:34.953840 ==
5103 23:22:34.956861 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 23:22:34.960293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 23:22:34.960518 ==
5106 23:22:34.963576 [Gating] SW mode calibration
5107 23:22:34.970219 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5108 23:22:34.976735 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5109 23:22:34.980877 0 14 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
5110 23:22:34.983293 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
5111 23:22:34.986650 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 23:22:34.993130 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 23:22:34.996664 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 23:22:34.999977 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 23:22:35.006731 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 23:22:35.010094 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5117 23:22:35.013296 0 15 0 | B1->B0 | 3333 2626 | 0 1 | (0 0) (1 0)
5118 23:22:35.020013 0 15 4 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
5119 23:22:35.023261 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5120 23:22:35.026427 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 23:22:35.032970 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 23:22:35.036434 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 23:22:35.039978 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 23:22:35.046696 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5125 23:22:35.049676 1 0 0 | B1->B0 | 2727 3939 | 0 1 | (0 0) (0 0)
5126 23:22:35.053317 1 0 4 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
5127 23:22:35.059821 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 23:22:35.063301 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 23:22:35.066636 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 23:22:35.073357 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 23:22:35.076787 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 23:22:35.079593 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5133 23:22:35.086564 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5134 23:22:35.089916 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5135 23:22:35.093249 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 23:22:35.099861 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 23:22:35.102992 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 23:22:35.106486 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 23:22:35.112987 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 23:22:35.116200 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 23:22:35.119797 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 23:22:35.122820 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 23:22:35.129540 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 23:22:35.132732 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 23:22:35.139175 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 23:22:35.142507 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 23:22:35.145778 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5148 23:22:35.149358 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 23:22:35.155832 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5150 23:22:35.159031 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5151 23:22:35.162561 Total UI for P1: 0, mck2ui 16
5152 23:22:35.165798 best dqsien dly found for B0: ( 1, 3, 0)
5153 23:22:35.169028 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 23:22:35.172405 Total UI for P1: 0, mck2ui 16
5155 23:22:35.175775 best dqsien dly found for B1: ( 1, 3, 4)
5156 23:22:35.178926 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5157 23:22:35.185458 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5158 23:22:35.185702
5159 23:22:35.188857 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5160 23:22:35.191983 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5161 23:22:35.195551 [Gating] SW calibration Done
5162 23:22:35.195780 ==
5163 23:22:35.198828 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 23:22:35.201906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 23:22:35.202135 ==
5166 23:22:35.202319 RX Vref Scan: 0
5167 23:22:35.205210
5168 23:22:35.205434 RX Vref 0 -> 0, step: 1
5169 23:22:35.205644
5170 23:22:35.208594 RX Delay -80 -> 252, step: 8
5171 23:22:35.212246 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5172 23:22:35.215259 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5173 23:22:35.221807 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5174 23:22:35.225396 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5175 23:22:35.228596 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5176 23:22:35.231969 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5177 23:22:35.235045 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5178 23:22:35.238603 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5179 23:22:35.245248 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5180 23:22:35.248589 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5181 23:22:35.252074 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5182 23:22:35.255047 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5183 23:22:35.258830 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5184 23:22:35.264911 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5185 23:22:35.268383 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5186 23:22:35.271485 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5187 23:22:35.271714 ==
5188 23:22:35.274902 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 23:22:35.278204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 23:22:35.278433 ==
5191 23:22:35.281530 DQS Delay:
5192 23:22:35.281755 DQS0 = 0, DQS1 = 0
5193 23:22:35.284892 DQM Delay:
5194 23:22:35.285118 DQM0 = 94, DQM1 = 82
5195 23:22:35.285298 DQ Delay:
5196 23:22:35.288282 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5197 23:22:35.291409 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5198 23:22:35.294994 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5199 23:22:35.298230 DQ12 =83, DQ13 =91, DQ14 =91, DQ15 =87
5200 23:22:35.301420
5201 23:22:35.301665
5202 23:22:35.301844 ==
5203 23:22:35.304527 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 23:22:35.308051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 23:22:35.308279 ==
5206 23:22:35.308459
5207 23:22:35.308628
5208 23:22:35.311260 TX Vref Scan disable
5209 23:22:35.311486 == TX Byte 0 ==
5210 23:22:35.317814 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5211 23:22:35.321180 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5212 23:22:35.321409 == TX Byte 1 ==
5213 23:22:35.327901 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5214 23:22:35.331141 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5215 23:22:35.331565 ==
5216 23:22:35.334496 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 23:22:35.337620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 23:22:35.338113 ==
5219 23:22:35.338574
5220 23:22:35.339037
5221 23:22:35.340978 TX Vref Scan disable
5222 23:22:35.344452 == TX Byte 0 ==
5223 23:22:35.348022 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5224 23:22:35.351104 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5225 23:22:35.354528 == TX Byte 1 ==
5226 23:22:35.357835 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5227 23:22:35.361129 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5228 23:22:35.361561
5229 23:22:35.364380 [DATLAT]
5230 23:22:35.364825 Freq=933, CH0 RK0
5231 23:22:35.365156
5232 23:22:35.367399 DATLAT Default: 0xd
5233 23:22:35.367808 0, 0xFFFF, sum = 0
5234 23:22:35.370845 1, 0xFFFF, sum = 0
5235 23:22:35.371267 2, 0xFFFF, sum = 0
5236 23:22:35.374004 3, 0xFFFF, sum = 0
5237 23:22:35.374302 4, 0xFFFF, sum = 0
5238 23:22:35.377522 5, 0xFFFF, sum = 0
5239 23:22:35.377822 6, 0xFFFF, sum = 0
5240 23:22:35.380722 7, 0xFFFF, sum = 0
5241 23:22:35.383883 8, 0xFFFF, sum = 0
5242 23:22:35.384177 9, 0xFFFF, sum = 0
5243 23:22:35.387272 10, 0x0, sum = 1
5244 23:22:35.387567 11, 0x0, sum = 2
5245 23:22:35.387804 12, 0x0, sum = 3
5246 23:22:35.390864 13, 0x0, sum = 4
5247 23:22:35.391208 best_step = 11
5248 23:22:35.391449
5249 23:22:35.391669 ==
5250 23:22:35.393849 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 23:22:35.400467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 23:22:35.400763 ==
5253 23:22:35.401098 RX Vref Scan: 1
5254 23:22:35.401464
5255 23:22:35.403697 RX Vref 0 -> 0, step: 1
5256 23:22:35.403987
5257 23:22:35.406862 RX Delay -69 -> 252, step: 4
5258 23:22:35.407160
5259 23:22:35.410419 Set Vref, RX VrefLevel [Byte0]: 60
5260 23:22:35.413671 [Byte1]: 54
5261 23:22:35.413932
5262 23:22:35.417147 Final RX Vref Byte 0 = 60 to rank0
5263 23:22:35.420372 Final RX Vref Byte 1 = 54 to rank0
5264 23:22:35.423557 Final RX Vref Byte 0 = 60 to rank1
5265 23:22:35.427028 Final RX Vref Byte 1 = 54 to rank1==
5266 23:22:35.430477 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 23:22:35.433408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 23:22:35.436915 ==
5269 23:22:35.437208 DQS Delay:
5270 23:22:35.437441 DQS0 = 0, DQS1 = 0
5271 23:22:35.439897 DQM Delay:
5272 23:22:35.440196 DQM0 = 95, DQM1 = 82
5273 23:22:35.443289 DQ Delay:
5274 23:22:35.443585 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5275 23:22:35.446615 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =106
5276 23:22:35.449906 DQ8 =76, DQ9 =68, DQ10 =82, DQ11 =76
5277 23:22:35.453271 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =90
5278 23:22:35.456502
5279 23:22:35.456724
5280 23:22:35.462876 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 417 ps
5281 23:22:35.466406 CH0 RK0: MR19=505, MR18=F0E
5282 23:22:35.472839 CH0_RK0: MR19=0x505, MR18=0xF0E, DQSOSC=417, MR23=63, INC=62, DEC=41
5283 23:22:35.473006
5284 23:22:35.475966 ----->DramcWriteLeveling(PI) begin...
5285 23:22:35.476125 ==
5286 23:22:35.479519 Dram Type= 6, Freq= 0, CH_0, rank 1
5287 23:22:35.482892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 23:22:35.483051 ==
5289 23:22:35.485910 Write leveling (Byte 0): 31 => 31
5290 23:22:35.489352 Write leveling (Byte 1): 31 => 31
5291 23:22:35.492659 DramcWriteLeveling(PI) end<-----
5292 23:22:35.492816
5293 23:22:35.492975 ==
5294 23:22:35.495882 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 23:22:35.499053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 23:22:35.499213 ==
5297 23:22:35.502429 [Gating] SW mode calibration
5298 23:22:35.509110 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5299 23:22:35.515688 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5300 23:22:35.519113 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5301 23:22:35.525437 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 23:22:35.529021 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 23:22:35.532166 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 23:22:35.538540 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 23:22:35.542065 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 23:22:35.545065 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 23:22:35.551819 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5308 23:22:35.555105 0 15 0 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
5309 23:22:35.558419 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 23:22:35.565535 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 23:22:35.568739 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 23:22:35.572184 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 23:22:35.578539 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 23:22:35.581744 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 23:22:35.585426 0 15 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5316 23:22:35.591828 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5317 23:22:35.595209 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 23:22:35.598456 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 23:22:35.605063 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 23:22:35.608592 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 23:22:35.611737 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 23:22:35.614993 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 23:22:35.621523 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5324 23:22:35.624976 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5325 23:22:35.631414 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 23:22:35.635056 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 23:22:35.638214 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 23:22:35.641504 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 23:22:35.648048 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 23:22:35.651505 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 23:22:35.654602 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 23:22:35.661221 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 23:22:35.664699 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 23:22:35.667817 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 23:22:35.674618 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 23:22:35.677648 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 23:22:35.680945 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 23:22:35.687802 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 23:22:35.690795 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5340 23:22:35.694148 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 23:22:35.697543 Total UI for P1: 0, mck2ui 16
5342 23:22:35.700906 best dqsien dly found for B0: ( 1, 2, 28)
5343 23:22:35.704042 Total UI for P1: 0, mck2ui 16
5344 23:22:35.707540 best dqsien dly found for B1: ( 1, 2, 30)
5345 23:22:35.710680 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5346 23:22:35.714144 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5347 23:22:35.717185
5348 23:22:35.720874 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5349 23:22:35.723835 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5350 23:22:35.727355 [Gating] SW calibration Done
5351 23:22:35.727685 ==
5352 23:22:35.730723 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 23:22:35.734002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 23:22:35.734229 ==
5355 23:22:35.734408 RX Vref Scan: 0
5356 23:22:35.734576
5357 23:22:35.737367 RX Vref 0 -> 0, step: 1
5358 23:22:35.737672
5359 23:22:35.740573 RX Delay -80 -> 252, step: 8
5360 23:22:35.744008 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5361 23:22:35.747370 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5362 23:22:35.753894 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5363 23:22:35.757181 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5364 23:22:35.760374 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5365 23:22:35.764012 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5366 23:22:35.767191 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5367 23:22:35.770334 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5368 23:22:35.777096 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5369 23:22:35.780262 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5370 23:22:35.783931 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5371 23:22:35.787055 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5372 23:22:35.790429 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5373 23:22:35.796897 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5374 23:22:35.800085 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5375 23:22:35.803700 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5376 23:22:35.803923 ==
5377 23:22:35.806852 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 23:22:35.810229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 23:22:35.810456 ==
5380 23:22:35.813489 DQS Delay:
5381 23:22:35.813715 DQS0 = 0, DQS1 = 0
5382 23:22:35.816609 DQM Delay:
5383 23:22:35.816832 DQM0 = 91, DQM1 = 83
5384 23:22:35.817010 DQ Delay:
5385 23:22:35.820233 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5386 23:22:35.823208 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =107
5387 23:22:35.826882 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5388 23:22:35.829876 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5389 23:22:35.830111
5390 23:22:35.833388
5391 23:22:35.833648 ==
5392 23:22:35.836866 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 23:22:35.840125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 23:22:35.840353 ==
5395 23:22:35.840533
5396 23:22:35.840701
5397 23:22:35.843449 TX Vref Scan disable
5398 23:22:35.843674 == TX Byte 0 ==
5399 23:22:35.849763 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5400 23:22:35.853392 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5401 23:22:35.853901 == TX Byte 1 ==
5402 23:22:35.859973 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5403 23:22:35.863354 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5404 23:22:35.863780 ==
5405 23:22:35.866520 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 23:22:35.870130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 23:22:35.870556 ==
5408 23:22:35.870888
5409 23:22:35.871199
5410 23:22:35.873407 TX Vref Scan disable
5411 23:22:35.876525 == TX Byte 0 ==
5412 23:22:35.880037 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5413 23:22:35.883256 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5414 23:22:35.886296 == TX Byte 1 ==
5415 23:22:35.889941 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5416 23:22:35.893074 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5417 23:22:35.893370
5418 23:22:35.896242 [DATLAT]
5419 23:22:35.896535 Freq=933, CH0 RK1
5420 23:22:35.896772
5421 23:22:35.899691 DATLAT Default: 0xb
5422 23:22:35.899985 0, 0xFFFF, sum = 0
5423 23:22:35.903076 1, 0xFFFF, sum = 0
5424 23:22:35.903392 2, 0xFFFF, sum = 0
5425 23:22:35.906204 3, 0xFFFF, sum = 0
5426 23:22:35.906504 4, 0xFFFF, sum = 0
5427 23:22:35.909700 5, 0xFFFF, sum = 0
5428 23:22:35.910000 6, 0xFFFF, sum = 0
5429 23:22:35.912828 7, 0xFFFF, sum = 0
5430 23:22:35.913219 8, 0xFFFF, sum = 0
5431 23:22:35.916341 9, 0xFFFF, sum = 0
5432 23:22:35.916656 10, 0x0, sum = 1
5433 23:22:35.919768 11, 0x0, sum = 2
5434 23:22:35.920083 12, 0x0, sum = 3
5435 23:22:35.922961 13, 0x0, sum = 4
5436 23:22:35.923263 best_step = 11
5437 23:22:35.923654
5438 23:22:35.923920 ==
5439 23:22:35.926307 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 23:22:35.932951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 23:22:35.933252 ==
5442 23:22:35.933521 RX Vref Scan: 0
5443 23:22:35.933767
5444 23:22:35.935982 RX Vref 0 -> 0, step: 1
5445 23:22:35.936370
5446 23:22:35.939185 RX Delay -77 -> 252, step: 4
5447 23:22:35.942780 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5448 23:22:35.946108 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5449 23:22:35.952585 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5450 23:22:35.955939 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5451 23:22:35.959349 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5452 23:22:35.962412 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5453 23:22:35.965910 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5454 23:22:35.972287 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5455 23:22:35.975898 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5456 23:22:35.978903 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5457 23:22:35.982085 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5458 23:22:35.985609 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5459 23:22:35.992305 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5460 23:22:35.995653 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5461 23:22:35.998763 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5462 23:22:36.002053 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5463 23:22:36.002406 ==
5464 23:22:36.005595 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 23:22:36.008779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 23:22:36.012296 ==
5467 23:22:36.012664 DQS Delay:
5468 23:22:36.012919 DQS0 = 0, DQS1 = 0
5469 23:22:36.015388 DQM Delay:
5470 23:22:36.015686 DQM0 = 92, DQM1 = 84
5471 23:22:36.018773 DQ Delay:
5472 23:22:36.019088 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5473 23:22:36.022152 DQ4 =90, DQ5 =82, DQ6 =106, DQ7 =104
5474 23:22:36.025345 DQ8 =78, DQ9 =68, DQ10 =84, DQ11 =78
5475 23:22:36.028930 DQ12 =90, DQ13 =92, DQ14 =96, DQ15 =92
5476 23:22:36.032099
5477 23:22:36.032430
5478 23:22:36.038948 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f12, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5479 23:22:36.042080 CH0 RK1: MR19=505, MR18=2F12
5480 23:22:36.048610 CH0_RK1: MR19=0x505, MR18=0x2F12, DQSOSC=407, MR23=63, INC=65, DEC=43
5481 23:22:36.051745 [RxdqsGatingPostProcess] freq 933
5482 23:22:36.055351 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5483 23:22:36.058672 best DQS0 dly(2T, 0.5T) = (0, 11)
5484 23:22:36.061777 best DQS1 dly(2T, 0.5T) = (0, 11)
5485 23:22:36.065320 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5486 23:22:36.068662 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5487 23:22:36.071964 best DQS0 dly(2T, 0.5T) = (0, 10)
5488 23:22:36.075347 best DQS1 dly(2T, 0.5T) = (0, 10)
5489 23:22:36.078363 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5490 23:22:36.081770 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5491 23:22:36.085208 Pre-setting of DQS Precalculation
5492 23:22:36.088418 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5493 23:22:36.088715 ==
5494 23:22:36.091592 Dram Type= 6, Freq= 0, CH_1, rank 0
5495 23:22:36.098369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 23:22:36.098670 ==
5497 23:22:36.101744 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5498 23:22:36.108357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5499 23:22:36.111708 [CA 0] Center 37 (7~67) winsize 61
5500 23:22:36.114819 [CA 1] Center 37 (7~67) winsize 61
5501 23:22:36.118410 [CA 2] Center 34 (5~64) winsize 60
5502 23:22:36.121500 [CA 3] Center 34 (4~64) winsize 61
5503 23:22:36.125032 [CA 4] Center 34 (5~64) winsize 60
5504 23:22:36.128234 [CA 5] Center 34 (4~64) winsize 61
5505 23:22:36.128532
5506 23:22:36.131280 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5507 23:22:36.131576
5508 23:22:36.134963 [CATrainingPosCal] consider 1 rank data
5509 23:22:36.142384 u2DelayCellTimex100 = 270/100 ps
5510 23:22:36.142798 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5511 23:22:36.144722 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5512 23:22:36.148154 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5513 23:22:36.154709 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5514 23:22:36.157837 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5515 23:22:36.161048 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5516 23:22:36.161449
5517 23:22:36.164564 CA PerBit enable=1, Macro0, CA PI delay=34
5518 23:22:36.164977
5519 23:22:36.167944 [CBTSetCACLKResult] CA Dly = 34
5520 23:22:36.168348 CS Dly: 5 (0~36)
5521 23:22:36.168741 ==
5522 23:22:36.171009 Dram Type= 6, Freq= 0, CH_1, rank 1
5523 23:22:36.177553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 23:22:36.177943 ==
5525 23:22:36.180999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5526 23:22:36.187678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5527 23:22:36.191007 [CA 0] Center 37 (8~67) winsize 60
5528 23:22:36.194463 [CA 1] Center 37 (7~68) winsize 62
5529 23:22:36.197984 [CA 2] Center 35 (6~64) winsize 59
5530 23:22:36.201251 [CA 3] Center 34 (4~64) winsize 61
5531 23:22:36.204322 [CA 4] Center 34 (5~64) winsize 60
5532 23:22:36.207656 [CA 5] Center 33 (3~64) winsize 62
5533 23:22:36.207951
5534 23:22:36.211186 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5535 23:22:36.211485
5536 23:22:36.214391 [CATrainingPosCal] consider 2 rank data
5537 23:22:36.217471 u2DelayCellTimex100 = 270/100 ps
5538 23:22:36.221146 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5539 23:22:36.227479 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5540 23:22:36.231112 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5541 23:22:36.234237 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5542 23:22:36.237786 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5543 23:22:36.240977 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5544 23:22:36.241271
5545 23:22:36.244386 CA PerBit enable=1, Macro0, CA PI delay=34
5546 23:22:36.244683
5547 23:22:36.247522 [CBTSetCACLKResult] CA Dly = 34
5548 23:22:36.247820 CS Dly: 6 (0~39)
5549 23:22:36.248056
5550 23:22:36.251124 ----->DramcWriteLeveling(PI) begin...
5551 23:22:36.254447 ==
5552 23:22:36.257580 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 23:22:36.261012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 23:22:36.261314 ==
5555 23:22:36.264137 Write leveling (Byte 0): 24 => 24
5556 23:22:36.267688 Write leveling (Byte 1): 32 => 32
5557 23:22:36.270903 DramcWriteLeveling(PI) end<-----
5558 23:22:36.271203
5559 23:22:36.271441 ==
5560 23:22:36.274160 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 23:22:36.277570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 23:22:36.277873 ==
5563 23:22:36.280864 [Gating] SW mode calibration
5564 23:22:36.287424 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5565 23:22:36.293881 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5566 23:22:36.297317 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5567 23:22:36.300650 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 23:22:36.307020 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 23:22:36.310294 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 23:22:36.313769 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 23:22:36.320413 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 23:22:36.323966 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 23:22:36.327071 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
5574 23:22:36.333871 0 15 0 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
5575 23:22:36.337111 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 23:22:36.340295 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 23:22:36.346896 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 23:22:36.350440 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 23:22:36.353539 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 23:22:36.360145 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 23:22:36.363463 0 15 28 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (0 0)
5582 23:22:36.366854 1 0 0 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
5583 23:22:36.370362 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 23:22:36.376884 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 23:22:36.380065 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 23:22:36.383322 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 23:22:36.390150 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 23:22:36.393069 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 23:22:36.396714 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5590 23:22:36.403127 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5591 23:22:36.406782 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 23:22:36.409707 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 23:22:36.416684 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 23:22:36.419985 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 23:22:36.423134 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 23:22:36.429669 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 23:22:36.433101 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 23:22:36.436527 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 23:22:36.443461 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 23:22:36.446271 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 23:22:36.450070 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 23:22:36.456435 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 23:22:36.460011 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 23:22:36.462911 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 23:22:36.469647 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5606 23:22:36.472940 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 23:22:36.476185 Total UI for P1: 0, mck2ui 16
5608 23:22:36.479411 best dqsien dly found for B0: ( 1, 2, 28)
5609 23:22:36.482697 Total UI for P1: 0, mck2ui 16
5610 23:22:36.485884 best dqsien dly found for B1: ( 1, 2, 28)
5611 23:22:36.489279 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5612 23:22:36.492594 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5613 23:22:36.493059
5614 23:22:36.495976 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5615 23:22:36.502471 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5616 23:22:36.503045 [Gating] SW calibration Done
5617 23:22:36.503417 ==
5618 23:22:36.505666 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 23:22:36.512518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 23:22:36.513084 ==
5621 23:22:36.513458 RX Vref Scan: 0
5622 23:22:36.513871
5623 23:22:36.515370 RX Vref 0 -> 0, step: 1
5624 23:22:36.515832
5625 23:22:36.519037 RX Delay -80 -> 252, step: 8
5626 23:22:36.522041 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5627 23:22:36.525417 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5628 23:22:36.528399 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5629 23:22:36.531861 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5630 23:22:36.538454 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5631 23:22:36.542066 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5632 23:22:36.545281 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5633 23:22:36.548379 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5634 23:22:36.551529 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5635 23:22:36.558296 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5636 23:22:36.561709 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5637 23:22:36.564855 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5638 23:22:36.568441 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5639 23:22:36.571387 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5640 23:22:36.578439 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5641 23:22:36.581456 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5642 23:22:36.581921 ==
5643 23:22:36.584641 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 23:22:36.588156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 23:22:36.588579 ==
5646 23:22:36.591657 DQS Delay:
5647 23:22:36.592189 DQS0 = 0, DQS1 = 0
5648 23:22:36.592537 DQM Delay:
5649 23:22:36.594488 DQM0 = 96, DQM1 = 87
5650 23:22:36.594911 DQ Delay:
5651 23:22:36.597914 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =91
5652 23:22:36.601057 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5653 23:22:36.604658 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5654 23:22:36.607897 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5655 23:22:36.608327
5656 23:22:36.608787
5657 23:22:36.609115 ==
5658 23:22:36.611154 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 23:22:36.617457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 23:22:36.617943 ==
5661 23:22:36.618281
5662 23:22:36.618593
5663 23:22:36.618890 TX Vref Scan disable
5664 23:22:36.621435 == TX Byte 0 ==
5665 23:22:36.624490 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5666 23:22:36.630935 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5667 23:22:36.631185 == TX Byte 1 ==
5668 23:22:36.634408 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5669 23:22:36.640917 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5670 23:22:36.641069 ==
5671 23:22:36.644427 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 23:22:36.647439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 23:22:36.647586 ==
5674 23:22:36.647706
5675 23:22:36.647817
5676 23:22:36.650839 TX Vref Scan disable
5677 23:22:36.650990 == TX Byte 0 ==
5678 23:22:36.657422 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5679 23:22:36.660670 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5680 23:22:36.660868 == TX Byte 1 ==
5681 23:22:36.667393 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5682 23:22:36.670884 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5683 23:22:36.671034
5684 23:22:36.671153 [DATLAT]
5685 23:22:36.673937 Freq=933, CH1 RK0
5686 23:22:36.674086
5687 23:22:36.674204 DATLAT Default: 0xd
5688 23:22:36.677511 0, 0xFFFF, sum = 0
5689 23:22:36.677664 1, 0xFFFF, sum = 0
5690 23:22:36.680570 2, 0xFFFF, sum = 0
5691 23:22:36.684350 3, 0xFFFF, sum = 0
5692 23:22:36.684610 4, 0xFFFF, sum = 0
5693 23:22:36.687504 5, 0xFFFF, sum = 0
5694 23:22:36.687722 6, 0xFFFF, sum = 0
5695 23:22:36.690680 7, 0xFFFF, sum = 0
5696 23:22:36.690921 8, 0xFFFF, sum = 0
5697 23:22:36.693939 9, 0xFFFF, sum = 0
5698 23:22:36.694182 10, 0x0, sum = 1
5699 23:22:36.697191 11, 0x0, sum = 2
5700 23:22:36.697520 12, 0x0, sum = 3
5701 23:22:36.700697 13, 0x0, sum = 4
5702 23:22:36.701076 best_step = 11
5703 23:22:36.701378
5704 23:22:36.701710 ==
5705 23:22:36.704018 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 23:22:36.707118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 23:22:36.707507 ==
5708 23:22:36.710527 RX Vref Scan: 1
5709 23:22:36.710905
5710 23:22:36.713929 RX Vref 0 -> 0, step: 1
5711 23:22:36.714310
5712 23:22:36.714611 RX Delay -69 -> 252, step: 4
5713 23:22:36.716931
5714 23:22:36.717306 Set Vref, RX VrefLevel [Byte0]: 55
5715 23:22:36.720119 [Byte1]: 45
5716 23:22:36.725551
5717 23:22:36.725935 Final RX Vref Byte 0 = 55 to rank0
5718 23:22:36.728866 Final RX Vref Byte 1 = 45 to rank0
5719 23:22:36.732141 Final RX Vref Byte 0 = 55 to rank1
5720 23:22:36.735428 Final RX Vref Byte 1 = 45 to rank1==
5721 23:22:36.738638 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 23:22:36.745193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 23:22:36.745607 ==
5724 23:22:36.745915 DQS Delay:
5725 23:22:36.746199 DQS0 = 0, DQS1 = 0
5726 23:22:36.748736 DQM Delay:
5727 23:22:36.749156 DQM0 = 95, DQM1 = 87
5728 23:22:36.751906 DQ Delay:
5729 23:22:36.755022 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
5730 23:22:36.758401 DQ4 =92, DQ5 =106, DQ6 =106, DQ7 =94
5731 23:22:36.761795 DQ8 =76, DQ9 =78, DQ10 =86, DQ11 =82
5732 23:22:36.765338 DQ12 =94, DQ13 =94, DQ14 =92, DQ15 =94
5733 23:22:36.765749
5734 23:22:36.766055
5735 23:22:36.771880 [DQSOSCAuto] RK0, (LSB)MR18= 0x8, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5736 23:22:36.775491 CH1 RK0: MR19=505, MR18=8
5737 23:22:36.781554 CH1_RK0: MR19=0x505, MR18=0x8, DQSOSC=419, MR23=63, INC=61, DEC=41
5738 23:22:36.781949
5739 23:22:36.785297 ----->DramcWriteLeveling(PI) begin...
5740 23:22:36.785712 ==
5741 23:22:36.788495 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 23:22:36.791858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 23:22:36.792242 ==
5744 23:22:36.795015 Write leveling (Byte 0): 27 => 27
5745 23:22:36.798087 Write leveling (Byte 1): 28 => 28
5746 23:22:36.801449 DramcWriteLeveling(PI) end<-----
5747 23:22:36.801743
5748 23:22:36.801958 ==
5749 23:22:36.804596 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 23:22:36.807833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 23:22:36.808046 ==
5752 23:22:36.811363 [Gating] SW mode calibration
5753 23:22:36.817947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5754 23:22:36.824575 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5755 23:22:36.828120 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5756 23:22:36.831497 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 23:22:36.838016 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 23:22:36.841839 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 23:22:36.844680 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 23:22:36.851426 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 23:22:36.854673 0 14 24 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
5762 23:22:36.857842 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 23:22:36.864479 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 23:22:36.867913 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 23:22:36.871333 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 23:22:36.877928 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 23:22:36.881145 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 23:22:36.884884 0 15 20 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5769 23:22:36.891516 0 15 24 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
5770 23:22:36.894677 0 15 28 | B1->B0 | 4242 4545 | 0 0 | (0 0) (0 0)
5771 23:22:36.897881 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 23:22:36.904637 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 23:22:36.908226 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 23:22:36.911421 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 23:22:36.917791 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 23:22:36.921338 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 23:22:36.924496 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 23:22:36.931110 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5779 23:22:36.934409 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 23:22:36.937733 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 23:22:36.944369 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 23:22:36.947527 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 23:22:36.950891 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 23:22:36.957230 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 23:22:36.960830 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 23:22:36.963921 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 23:22:36.970589 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 23:22:36.974018 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 23:22:36.977299 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 23:22:36.983875 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 23:22:36.987413 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 23:22:36.990275 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5793 23:22:36.997226 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5794 23:22:37.000294 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5795 23:22:37.003754 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 23:22:37.007021 Total UI for P1: 0, mck2ui 16
5797 23:22:37.010330 best dqsien dly found for B0: ( 1, 2, 24)
5798 23:22:37.013117 Total UI for P1: 0, mck2ui 16
5799 23:22:37.016715 best dqsien dly found for B1: ( 1, 2, 26)
5800 23:22:37.020176 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5801 23:22:37.023462 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5802 23:22:37.024007
5803 23:22:37.026739 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5804 23:22:37.033383 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5805 23:22:37.033905 [Gating] SW calibration Done
5806 23:22:37.034276 ==
5807 23:22:37.036465 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 23:22:37.043481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 23:22:37.044028 ==
5810 23:22:37.044367 RX Vref Scan: 0
5811 23:22:37.044678
5812 23:22:37.046577 RX Vref 0 -> 0, step: 1
5813 23:22:37.046996
5814 23:22:37.049929 RX Delay -80 -> 252, step: 8
5815 23:22:37.052953 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5816 23:22:37.056722 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5817 23:22:37.059881 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5818 23:22:37.066438 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5819 23:22:37.069910 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5820 23:22:37.072956 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5821 23:22:37.076669 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5822 23:22:37.079563 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5823 23:22:37.083423 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5824 23:22:37.089729 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5825 23:22:37.092920 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5826 23:22:37.096507 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5827 23:22:37.099840 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5828 23:22:37.102711 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5829 23:22:37.106350 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5830 23:22:37.112932 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5831 23:22:37.113693 ==
5832 23:22:37.115844 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 23:22:37.119178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 23:22:37.119782 ==
5835 23:22:37.120158 DQS Delay:
5836 23:22:37.122746 DQS0 = 0, DQS1 = 0
5837 23:22:37.123314 DQM Delay:
5838 23:22:37.125898 DQM0 = 93, DQM1 = 88
5839 23:22:37.126474 DQ Delay:
5840 23:22:37.129019 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5841 23:22:37.132586 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5842 23:22:37.135888 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5843 23:22:37.139043 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5844 23:22:37.139479
5845 23:22:37.139921
5846 23:22:37.140341 ==
5847 23:22:37.142469 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 23:22:37.145472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 23:22:37.149119 ==
5850 23:22:37.149594
5851 23:22:37.150040
5852 23:22:37.150463 TX Vref Scan disable
5853 23:22:37.152488 == TX Byte 0 ==
5854 23:22:37.155501 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5855 23:22:37.159028 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5856 23:22:37.162278 == TX Byte 1 ==
5857 23:22:37.165383 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5858 23:22:37.168644 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5859 23:22:37.172053 ==
5860 23:22:37.175478 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 23:22:37.178539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 23:22:37.178988 ==
5863 23:22:37.179344
5864 23:22:37.179656
5865 23:22:37.182014 TX Vref Scan disable
5866 23:22:37.182437 == TX Byte 0 ==
5867 23:22:37.188758 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5868 23:22:37.191935 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5869 23:22:37.192360 == TX Byte 1 ==
5870 23:22:37.198492 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5871 23:22:37.202100 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5872 23:22:37.202560
5873 23:22:37.202904 [DATLAT]
5874 23:22:37.205376 Freq=933, CH1 RK1
5875 23:22:37.205842
5876 23:22:37.206285 DATLAT Default: 0xb
5877 23:22:37.208869 0, 0xFFFF, sum = 0
5878 23:22:37.209429 1, 0xFFFF, sum = 0
5879 23:22:37.211837 2, 0xFFFF, sum = 0
5880 23:22:37.212281 3, 0xFFFF, sum = 0
5881 23:22:37.215061 4, 0xFFFF, sum = 0
5882 23:22:37.215505 5, 0xFFFF, sum = 0
5883 23:22:37.218576 6, 0xFFFF, sum = 0
5884 23:22:37.221930 7, 0xFFFF, sum = 0
5885 23:22:37.222370 8, 0xFFFF, sum = 0
5886 23:22:37.225032 9, 0xFFFF, sum = 0
5887 23:22:37.225473 10, 0x0, sum = 1
5888 23:22:37.225952 11, 0x0, sum = 2
5889 23:22:37.228601 12, 0x0, sum = 3
5890 23:22:37.229043 13, 0x0, sum = 4
5891 23:22:37.231659 best_step = 11
5892 23:22:37.232092
5893 23:22:37.232533 ==
5894 23:22:37.235234 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 23:22:37.238445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 23:22:37.238886 ==
5897 23:22:37.241815 RX Vref Scan: 0
5898 23:22:37.242250
5899 23:22:37.242692 RX Vref 0 -> 0, step: 1
5900 23:22:37.243113
5901 23:22:37.245093 RX Delay -69 -> 252, step: 4
5902 23:22:37.252344 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5903 23:22:37.255858 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5904 23:22:37.259222 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5905 23:22:37.262775 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5906 23:22:37.265928 iDelay=203, Bit 4, Center 92 (-5 ~ 190) 196
5907 23:22:37.272459 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5908 23:22:37.275814 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5909 23:22:37.279007 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5910 23:22:37.282386 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5911 23:22:37.285666 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5912 23:22:37.288886 iDelay=203, Bit 10, Center 92 (3 ~ 182) 180
5913 23:22:37.295399 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5914 23:22:37.298740 iDelay=203, Bit 12, Center 94 (3 ~ 186) 184
5915 23:22:37.302337 iDelay=203, Bit 13, Center 94 (3 ~ 186) 184
5916 23:22:37.305348 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5917 23:22:37.308663 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5918 23:22:37.309086 ==
5919 23:22:37.312063 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 23:22:37.318700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 23:22:37.319244 ==
5922 23:22:37.319592 DQS Delay:
5923 23:22:37.321806 DQS0 = 0, DQS1 = 0
5924 23:22:37.322235 DQM Delay:
5925 23:22:37.322566 DQM0 = 93, DQM1 = 88
5926 23:22:37.325324 DQ Delay:
5927 23:22:37.328689 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =90
5928 23:22:37.331831 DQ4 =92, DQ5 =102, DQ6 =104, DQ7 =90
5929 23:22:37.335506 DQ8 =76, DQ9 =80, DQ10 =92, DQ11 =82
5930 23:22:37.338600 DQ12 =94, DQ13 =94, DQ14 =94, DQ15 =94
5931 23:22:37.339109
5932 23:22:37.339568
5933 23:22:37.345117 [DQSOSCAuto] RK1, (LSB)MR18= 0xf22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
5934 23:22:37.348357 CH1 RK1: MR19=505, MR18=F22
5935 23:22:37.355124 CH1_RK1: MR19=0x505, MR18=0xF22, DQSOSC=411, MR23=63, INC=64, DEC=42
5936 23:22:37.358317 [RxdqsGatingPostProcess] freq 933
5937 23:22:37.361776 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5938 23:22:37.365186 best DQS0 dly(2T, 0.5T) = (0, 10)
5939 23:22:37.368265 best DQS1 dly(2T, 0.5T) = (0, 10)
5940 23:22:37.371380 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5941 23:22:37.374898 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5942 23:22:37.378276 best DQS0 dly(2T, 0.5T) = (0, 10)
5943 23:22:37.381304 best DQS1 dly(2T, 0.5T) = (0, 10)
5944 23:22:37.384857 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5945 23:22:37.388087 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5946 23:22:37.391275 Pre-setting of DQS Precalculation
5947 23:22:37.394687 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5948 23:22:37.404863 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5949 23:22:37.411566 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5950 23:22:37.412091
5951 23:22:37.412431
5952 23:22:37.414460 [Calibration Summary] 1866 Mbps
5953 23:22:37.414761 CH 0, Rank 0
5954 23:22:37.417695 SW Impedance : PASS
5955 23:22:37.417990 DUTY Scan : NO K
5956 23:22:37.421340 ZQ Calibration : PASS
5957 23:22:37.424555 Jitter Meter : NO K
5958 23:22:37.424864 CBT Training : PASS
5959 23:22:37.427680 Write leveling : PASS
5960 23:22:37.431072 RX DQS gating : PASS
5961 23:22:37.431439 RX DQ/DQS(RDDQC) : PASS
5962 23:22:37.434432 TX DQ/DQS : PASS
5963 23:22:37.437559 RX DATLAT : PASS
5964 23:22:37.437857 RX DQ/DQS(Engine): PASS
5965 23:22:37.441141 TX OE : NO K
5966 23:22:37.441438 All Pass.
5967 23:22:37.441712
5968 23:22:37.444673 CH 0, Rank 1
5969 23:22:37.444967 SW Impedance : PASS
5970 23:22:37.447891 DUTY Scan : NO K
5971 23:22:37.451005 ZQ Calibration : PASS
5972 23:22:37.451394 Jitter Meter : NO K
5973 23:22:37.454391 CBT Training : PASS
5974 23:22:37.457697 Write leveling : PASS
5975 23:22:37.457990 RX DQS gating : PASS
5976 23:22:37.460901 RX DQ/DQS(RDDQC) : PASS
5977 23:22:37.461226 TX DQ/DQS : PASS
5978 23:22:37.464404 RX DATLAT : PASS
5979 23:22:37.467783 RX DQ/DQS(Engine): PASS
5980 23:22:37.468078 TX OE : NO K
5981 23:22:37.471216 All Pass.
5982 23:22:37.471540
5983 23:22:37.471775 CH 1, Rank 0
5984 23:22:37.474266 SW Impedance : PASS
5985 23:22:37.474560 DUTY Scan : NO K
5986 23:22:37.477328 ZQ Calibration : PASS
5987 23:22:37.480873 Jitter Meter : NO K
5988 23:22:37.481165 CBT Training : PASS
5989 23:22:37.483964 Write leveling : PASS
5990 23:22:37.487219 RX DQS gating : PASS
5991 23:22:37.487514 RX DQ/DQS(RDDQC) : PASS
5992 23:22:37.490637 TX DQ/DQS : PASS
5993 23:22:37.493971 RX DATLAT : PASS
5994 23:22:37.494267 RX DQ/DQS(Engine): PASS
5995 23:22:37.497507 TX OE : NO K
5996 23:22:37.497900 All Pass.
5997 23:22:37.498146
5998 23:22:37.500612 CH 1, Rank 1
5999 23:22:37.500987 SW Impedance : PASS
6000 23:22:37.503947 DUTY Scan : NO K
6001 23:22:37.507406 ZQ Calibration : PASS
6002 23:22:37.507701 Jitter Meter : NO K
6003 23:22:37.510497 CBT Training : PASS
6004 23:22:37.514288 Write leveling : PASS
6005 23:22:37.514675 RX DQS gating : PASS
6006 23:22:37.517000 RX DQ/DQS(RDDQC) : PASS
6007 23:22:37.520534 TX DQ/DQS : PASS
6008 23:22:37.520832 RX DATLAT : PASS
6009 23:22:37.523881 RX DQ/DQS(Engine): PASS
6010 23:22:37.524220 TX OE : NO K
6011 23:22:37.527471 All Pass.
6012 23:22:37.527870
6013 23:22:37.528134 DramC Write-DBI off
6014 23:22:37.530552 PER_BANK_REFRESH: Hybrid Mode
6015 23:22:37.533978 TX_TRACKING: ON
6016 23:22:37.540984 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6017 23:22:37.544144 [FAST_K] Save calibration result to emmc
6018 23:22:37.550852 dramc_set_vcore_voltage set vcore to 650000
6019 23:22:37.551363 Read voltage for 400, 6
6020 23:22:37.551699 Vio18 = 0
6021 23:22:37.553925 Vcore = 650000
6022 23:22:37.554342 Vdram = 0
6023 23:22:37.554676 Vddq = 0
6024 23:22:37.557150 Vmddr = 0
6025 23:22:37.560552 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6026 23:22:37.567307 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6027 23:22:37.567820 MEM_TYPE=3, freq_sel=20
6028 23:22:37.570743 sv_algorithm_assistance_LP4_800
6029 23:22:37.577156 ============ PULL DRAM RESETB DOWN ============
6030 23:22:37.580488 ========== PULL DRAM RESETB DOWN end =========
6031 23:22:37.583773 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6032 23:22:37.587419 ===================================
6033 23:22:37.590347 LPDDR4 DRAM CONFIGURATION
6034 23:22:37.593616 ===================================
6035 23:22:37.596865 EX_ROW_EN[0] = 0x0
6036 23:22:37.597284 EX_ROW_EN[1] = 0x0
6037 23:22:37.599998 LP4Y_EN = 0x0
6038 23:22:37.600411 WORK_FSP = 0x0
6039 23:22:37.603386 WL = 0x2
6040 23:22:37.603801 RL = 0x2
6041 23:22:37.606572 BL = 0x2
6042 23:22:37.606986 RPST = 0x0
6043 23:22:37.610458 RD_PRE = 0x0
6044 23:22:37.610969 WR_PRE = 0x1
6045 23:22:37.613640 WR_PST = 0x0
6046 23:22:37.614148 DBI_WR = 0x0
6047 23:22:37.616631 DBI_RD = 0x0
6048 23:22:37.617046 OTF = 0x1
6049 23:22:37.619796 ===================================
6050 23:22:37.623328 ===================================
6051 23:22:37.626386 ANA top config
6052 23:22:37.629770 ===================================
6053 23:22:37.633034 DLL_ASYNC_EN = 0
6054 23:22:37.633666 ALL_SLAVE_EN = 1
6055 23:22:37.636226 NEW_RANK_MODE = 1
6056 23:22:37.639495 DLL_IDLE_MODE = 1
6057 23:22:37.643021 LP45_APHY_COMB_EN = 1
6058 23:22:37.646149 TX_ODT_DIS = 1
6059 23:22:37.646567 NEW_8X_MODE = 1
6060 23:22:37.649660 ===================================
6061 23:22:37.652876 ===================================
6062 23:22:37.656670 data_rate = 800
6063 23:22:37.659478 CKR = 1
6064 23:22:37.662997 DQ_P2S_RATIO = 4
6065 23:22:37.666102 ===================================
6066 23:22:37.669586 CA_P2S_RATIO = 4
6067 23:22:37.672698 DQ_CA_OPEN = 0
6068 23:22:37.673116 DQ_SEMI_OPEN = 1
6069 23:22:37.676109 CA_SEMI_OPEN = 1
6070 23:22:37.679326 CA_FULL_RATE = 0
6071 23:22:37.682701 DQ_CKDIV4_EN = 0
6072 23:22:37.685940 CA_CKDIV4_EN = 1
6073 23:22:37.689395 CA_PREDIV_EN = 0
6074 23:22:37.689867 PH8_DLY = 0
6075 23:22:37.692697 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6076 23:22:37.695748 DQ_AAMCK_DIV = 0
6077 23:22:37.699387 CA_AAMCK_DIV = 0
6078 23:22:37.702472 CA_ADMCK_DIV = 4
6079 23:22:37.705942 DQ_TRACK_CA_EN = 0
6080 23:22:37.706476 CA_PICK = 800
6081 23:22:37.709234 CA_MCKIO = 400
6082 23:22:37.712547 MCKIO_SEMI = 400
6083 23:22:37.715768 PLL_FREQ = 3016
6084 23:22:37.719268 DQ_UI_PI_RATIO = 32
6085 23:22:37.722367 CA_UI_PI_RATIO = 32
6086 23:22:37.725731 ===================================
6087 23:22:37.728706 ===================================
6088 23:22:37.732433 memory_type:LPDDR4
6089 23:22:37.732991 GP_NUM : 10
6090 23:22:37.735419 SRAM_EN : 1
6091 23:22:37.735835 MD32_EN : 0
6092 23:22:37.738817 ===================================
6093 23:22:37.742099 [ANA_INIT] >>>>>>>>>>>>>>
6094 23:22:37.745373 <<<<<< [CONFIGURE PHASE]: ANA_TX
6095 23:22:37.748481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6096 23:22:37.751897 ===================================
6097 23:22:37.755458 data_rate = 800,PCW = 0X7400
6098 23:22:37.758508 ===================================
6099 23:22:37.761649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6100 23:22:37.768304 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6101 23:22:37.778211 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6102 23:22:37.781257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6103 23:22:37.785117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6104 23:22:37.791234 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6105 23:22:37.791463 [ANA_INIT] flow start
6106 23:22:37.794844 [ANA_INIT] PLL >>>>>>>>
6107 23:22:37.795025 [ANA_INIT] PLL <<<<<<<<
6108 23:22:37.798000 [ANA_INIT] MIDPI >>>>>>>>
6109 23:22:37.801146 [ANA_INIT] MIDPI <<<<<<<<
6110 23:22:37.804461 [ANA_INIT] DLL >>>>>>>>
6111 23:22:37.804640 [ANA_INIT] flow end
6112 23:22:37.810987 ============ LP4 DIFF to SE enter ============
6113 23:22:37.814599 ============ LP4 DIFF to SE exit ============
6114 23:22:37.814860 [ANA_INIT] <<<<<<<<<<<<<
6115 23:22:37.817456 [Flow] Enable top DCM control >>>>>
6116 23:22:37.820803 [Flow] Enable top DCM control <<<<<
6117 23:22:37.824365 Enable DLL master slave shuffle
6118 23:22:37.830727 ==============================================================
6119 23:22:37.833817 Gating Mode config
6120 23:22:37.837038 ==============================================================
6121 23:22:37.840524 Config description:
6122 23:22:37.850550 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6123 23:22:37.857180 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6124 23:22:37.860535 SELPH_MODE 0: By rank 1: By Phase
6125 23:22:37.867240 ==============================================================
6126 23:22:37.870871 GAT_TRACK_EN = 0
6127 23:22:37.873924 RX_GATING_MODE = 2
6128 23:22:37.877868 RX_GATING_TRACK_MODE = 2
6129 23:22:37.881013 SELPH_MODE = 1
6130 23:22:37.881631 PICG_EARLY_EN = 1
6131 23:22:37.883859 VALID_LAT_VALUE = 1
6132 23:22:37.890553 ==============================================================
6133 23:22:37.893684 Enter into Gating configuration >>>>
6134 23:22:37.897260 Exit from Gating configuration <<<<
6135 23:22:37.900321 Enter into DVFS_PRE_config >>>>>
6136 23:22:37.910248 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6137 23:22:37.913861 Exit from DVFS_PRE_config <<<<<
6138 23:22:37.916937 Enter into PICG configuration >>>>
6139 23:22:37.919963 Exit from PICG configuration <<<<
6140 23:22:37.923408 [RX_INPUT] configuration >>>>>
6141 23:22:37.927126 [RX_INPUT] configuration <<<<<
6142 23:22:37.929936 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6143 23:22:37.936539 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6144 23:22:37.943310 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6145 23:22:37.950391 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6146 23:22:37.956753 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6147 23:22:37.963285 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6148 23:22:37.966770 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6149 23:22:37.969947 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6150 23:22:37.973095 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6151 23:22:37.979636 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6152 23:22:37.983219 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6153 23:22:37.986337 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6154 23:22:37.989575 ===================================
6155 23:22:37.993031 LPDDR4 DRAM CONFIGURATION
6156 23:22:37.996479 ===================================
6157 23:22:37.997003 EX_ROW_EN[0] = 0x0
6158 23:22:37.999520 EX_ROW_EN[1] = 0x0
6159 23:22:38.003001 LP4Y_EN = 0x0
6160 23:22:38.003418 WORK_FSP = 0x0
6161 23:22:38.006180 WL = 0x2
6162 23:22:38.006599 RL = 0x2
6163 23:22:38.009201 BL = 0x2
6164 23:22:38.009681 RPST = 0x0
6165 23:22:38.013015 RD_PRE = 0x0
6166 23:22:38.013580 WR_PRE = 0x1
6167 23:22:38.015771 WR_PST = 0x0
6168 23:22:38.016187 DBI_WR = 0x0
6169 23:22:38.019607 DBI_RD = 0x0
6170 23:22:38.020136 OTF = 0x1
6171 23:22:38.022553 ===================================
6172 23:22:38.026019 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6173 23:22:38.032342 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6174 23:22:38.035823 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6175 23:22:38.039095 ===================================
6176 23:22:38.042621 LPDDR4 DRAM CONFIGURATION
6177 23:22:38.045695 ===================================
6178 23:22:38.046115 EX_ROW_EN[0] = 0x10
6179 23:22:38.049046 EX_ROW_EN[1] = 0x0
6180 23:22:38.049466 LP4Y_EN = 0x0
6181 23:22:38.052665 WORK_FSP = 0x0
6182 23:22:38.055632 WL = 0x2
6183 23:22:38.056074 RL = 0x2
6184 23:22:38.058908 BL = 0x2
6185 23:22:38.059330 RPST = 0x0
6186 23:22:38.062204 RD_PRE = 0x0
6187 23:22:38.062624 WR_PRE = 0x1
6188 23:22:38.065508 WR_PST = 0x0
6189 23:22:38.066034 DBI_WR = 0x0
6190 23:22:38.068988 DBI_RD = 0x0
6191 23:22:38.069408 OTF = 0x1
6192 23:22:38.072607 ===================================
6193 23:22:38.079433 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6194 23:22:38.083359 nWR fixed to 30
6195 23:22:38.086422 [ModeRegInit_LP4] CH0 RK0
6196 23:22:38.086949 [ModeRegInit_LP4] CH0 RK1
6197 23:22:38.090109 [ModeRegInit_LP4] CH1 RK0
6198 23:22:38.092761 [ModeRegInit_LP4] CH1 RK1
6199 23:22:38.093186 match AC timing 19
6200 23:22:38.099448 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6201 23:22:38.103120 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6202 23:22:38.106242 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6203 23:22:38.112998 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6204 23:22:38.116541 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6205 23:22:38.117068 ==
6206 23:22:38.119631 Dram Type= 6, Freq= 0, CH_0, rank 0
6207 23:22:38.123292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6208 23:22:38.123819 ==
6209 23:22:38.129388 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6210 23:22:38.136200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6211 23:22:38.139622 [CA 0] Center 36 (8~64) winsize 57
6212 23:22:38.142770 [CA 1] Center 36 (8~64) winsize 57
6213 23:22:38.146235 [CA 2] Center 36 (8~64) winsize 57
6214 23:22:38.149505 [CA 3] Center 36 (8~64) winsize 57
6215 23:22:38.149941 [CA 4] Center 36 (8~64) winsize 57
6216 23:22:38.152908 [CA 5] Center 36 (8~64) winsize 57
6217 23:22:38.153327
6218 23:22:38.159281 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6219 23:22:38.159858
6220 23:22:38.162484 [CATrainingPosCal] consider 1 rank data
6221 23:22:38.165583 u2DelayCellTimex100 = 270/100 ps
6222 23:22:38.169213 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 23:22:38.172362 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 23:22:38.175827 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 23:22:38.179302 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 23:22:38.182589 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 23:22:38.185794 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 23:22:38.186346
6229 23:22:38.189330 CA PerBit enable=1, Macro0, CA PI delay=36
6230 23:22:38.190026
6231 23:22:38.192551 [CBTSetCACLKResult] CA Dly = 36
6232 23:22:38.195654 CS Dly: 1 (0~32)
6233 23:22:38.196196 ==
6234 23:22:38.198817 Dram Type= 6, Freq= 0, CH_0, rank 1
6235 23:22:38.202741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6236 23:22:38.203273 ==
6237 23:22:38.209124 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6238 23:22:38.216089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6239 23:22:38.216616 [CA 0] Center 36 (8~64) winsize 57
6240 23:22:38.218757 [CA 1] Center 36 (8~64) winsize 57
6241 23:22:38.222352 [CA 2] Center 36 (8~64) winsize 57
6242 23:22:38.225681 [CA 3] Center 36 (8~64) winsize 57
6243 23:22:38.229009 [CA 4] Center 36 (8~64) winsize 57
6244 23:22:38.232547 [CA 5] Center 36 (8~64) winsize 57
6245 23:22:38.233056
6246 23:22:38.235248 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6247 23:22:38.235666
6248 23:22:38.238914 [CATrainingPosCal] consider 2 rank data
6249 23:22:38.242065 u2DelayCellTimex100 = 270/100 ps
6250 23:22:38.245173 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 23:22:38.252078 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 23:22:38.255069 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 23:22:38.258336 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 23:22:38.261790 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 23:22:38.265425 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 23:22:38.265997
6257 23:22:38.268535 CA PerBit enable=1, Macro0, CA PI delay=36
6258 23:22:38.268948
6259 23:22:38.272020 [CBTSetCACLKResult] CA Dly = 36
6260 23:22:38.274874 CS Dly: 1 (0~32)
6261 23:22:38.275300
6262 23:22:38.278208 ----->DramcWriteLeveling(PI) begin...
6263 23:22:38.278777 ==
6264 23:22:38.281372 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 23:22:38.284577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 23:22:38.285002 ==
6267 23:22:38.288354 Write leveling (Byte 0): 40 => 8
6268 23:22:38.291526 Write leveling (Byte 1): 40 => 8
6269 23:22:38.294646 DramcWriteLeveling(PI) end<-----
6270 23:22:38.295095
6271 23:22:38.295440 ==
6272 23:22:38.298371 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 23:22:38.301456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 23:22:38.301922 ==
6275 23:22:38.304815 [Gating] SW mode calibration
6276 23:22:38.311864 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6277 23:22:38.318445 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6278 23:22:38.321222 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 23:22:38.325060 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6280 23:22:38.331350 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 23:22:38.334457 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 23:22:38.337941 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 23:22:38.344341 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 23:22:38.347776 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 23:22:38.351274 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 23:22:38.357797 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 23:22:38.358337 Total UI for P1: 0, mck2ui 16
6288 23:22:38.363971 best dqsien dly found for B0: ( 0, 14, 24)
6289 23:22:38.364486 Total UI for P1: 0, mck2ui 16
6290 23:22:38.371046 best dqsien dly found for B1: ( 0, 14, 24)
6291 23:22:38.374117 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6292 23:22:38.377829 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6293 23:22:38.378394
6294 23:22:38.381133 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6295 23:22:38.384127 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6296 23:22:38.387457 [Gating] SW calibration Done
6297 23:22:38.387882 ==
6298 23:22:38.390793 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 23:22:38.393992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 23:22:38.394411 ==
6301 23:22:38.397534 RX Vref Scan: 0
6302 23:22:38.398121
6303 23:22:38.398601 RX Vref 0 -> 0, step: 1
6304 23:22:38.399052
6305 23:22:38.400406 RX Delay -410 -> 252, step: 16
6306 23:22:38.407166 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6307 23:22:38.410473 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6308 23:22:38.413798 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6309 23:22:38.417675 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6310 23:22:38.423820 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6311 23:22:38.427257 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6312 23:22:38.430723 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6313 23:22:38.433936 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6314 23:22:38.440690 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6315 23:22:38.443671 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6316 23:22:38.447006 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6317 23:22:38.450310 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6318 23:22:38.457513 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6319 23:22:38.460395 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6320 23:22:38.463546 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6321 23:22:38.467246 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6322 23:22:38.470391 ==
6323 23:22:38.473773 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 23:22:38.477467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 23:22:38.478066 ==
6326 23:22:38.478403 DQS Delay:
6327 23:22:38.480475 DQS0 = 59, DQS1 = 59
6328 23:22:38.480989 DQM Delay:
6329 23:22:38.483483 DQM0 = 17, DQM1 = 10
6330 23:22:38.483895 DQ Delay:
6331 23:22:38.486595 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6332 23:22:38.490292 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6333 23:22:38.493617 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6334 23:22:38.496808 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6335 23:22:38.497328
6336 23:22:38.497715
6337 23:22:38.498028 ==
6338 23:22:38.499711 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 23:22:38.503434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 23:22:38.503962 ==
6341 23:22:38.504297
6342 23:22:38.504605
6343 23:22:38.506766 TX Vref Scan disable
6344 23:22:38.510163 == TX Byte 0 ==
6345 23:22:38.513267 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 23:22:38.516554 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 23:22:38.516974 == TX Byte 1 ==
6348 23:22:38.523253 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 23:22:38.526621 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 23:22:38.527040 ==
6351 23:22:38.530186 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 23:22:38.532952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 23:22:38.533463 ==
6354 23:22:38.533982
6355 23:22:38.534306
6356 23:22:38.536322 TX Vref Scan disable
6357 23:22:38.539878 == TX Byte 0 ==
6358 23:22:38.543475 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 23:22:38.546336 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 23:22:38.549616 == TX Byte 1 ==
6361 23:22:38.552855 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6362 23:22:38.556262 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6363 23:22:38.556782
6364 23:22:38.557114 [DATLAT]
6365 23:22:38.559869 Freq=400, CH0 RK0
6366 23:22:38.560389
6367 23:22:38.560723 DATLAT Default: 0xf
6368 23:22:38.562706 0, 0xFFFF, sum = 0
6369 23:22:38.566096 1, 0xFFFF, sum = 0
6370 23:22:38.566520 2, 0xFFFF, sum = 0
6371 23:22:38.569276 3, 0xFFFF, sum = 0
6372 23:22:38.569758 4, 0xFFFF, sum = 0
6373 23:22:38.572543 5, 0xFFFF, sum = 0
6374 23:22:38.572967 6, 0xFFFF, sum = 0
6375 23:22:38.576106 7, 0xFFFF, sum = 0
6376 23:22:38.576639 8, 0xFFFF, sum = 0
6377 23:22:38.579268 9, 0xFFFF, sum = 0
6378 23:22:38.579690 10, 0xFFFF, sum = 0
6379 23:22:38.583052 11, 0xFFFF, sum = 0
6380 23:22:38.583585 12, 0xFFFF, sum = 0
6381 23:22:38.585927 13, 0x0, sum = 1
6382 23:22:38.586382 14, 0x0, sum = 2
6383 23:22:38.589672 15, 0x0, sum = 3
6384 23:22:38.590201 16, 0x0, sum = 4
6385 23:22:38.592717 best_step = 14
6386 23:22:38.593134
6387 23:22:38.593466 ==
6388 23:22:38.595877 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 23:22:38.599144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 23:22:38.599566 ==
6391 23:22:38.602546 RX Vref Scan: 1
6392 23:22:38.603072
6393 23:22:38.603408 RX Vref 0 -> 0, step: 1
6394 23:22:38.603716
6395 23:22:38.605899 RX Delay -359 -> 252, step: 8
6396 23:22:38.606425
6397 23:22:38.608937 Set Vref, RX VrefLevel [Byte0]: 60
6398 23:22:38.612334 [Byte1]: 54
6399 23:22:38.617137
6400 23:22:38.617707 Final RX Vref Byte 0 = 60 to rank0
6401 23:22:38.620430 Final RX Vref Byte 1 = 54 to rank0
6402 23:22:38.623425 Final RX Vref Byte 0 = 60 to rank1
6403 23:22:38.626772 Final RX Vref Byte 1 = 54 to rank1==
6404 23:22:38.630453 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 23:22:38.637048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 23:22:38.637655 ==
6407 23:22:38.638010 DQS Delay:
6408 23:22:38.638325 DQS0 = 60, DQS1 = 68
6409 23:22:38.640275 DQM Delay:
6410 23:22:38.640797 DQM0 = 14, DQM1 = 13
6411 23:22:38.643865 DQ Delay:
6412 23:22:38.646681 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =16
6413 23:22:38.647124 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6414 23:22:38.650321 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6415 23:22:38.653564 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6416 23:22:38.654099
6417 23:22:38.657101
6418 23:22:38.663534 [DQSOSCAuto] RK0, (LSB)MR18= 0x8482, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6419 23:22:38.666580 CH0 RK0: MR19=C0C, MR18=8482
6420 23:22:38.673847 CH0_RK0: MR19=0xC0C, MR18=0x8482, DQSOSC=393, MR23=63, INC=382, DEC=254
6421 23:22:38.674374 ==
6422 23:22:38.676621 Dram Type= 6, Freq= 0, CH_0, rank 1
6423 23:22:38.680089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 23:22:38.680657 ==
6425 23:22:38.683425 [Gating] SW mode calibration
6426 23:22:38.690125 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6427 23:22:38.696727 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6428 23:22:38.699867 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 23:22:38.703246 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 23:22:38.709929 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 23:22:38.712917 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 23:22:38.716642 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 23:22:38.723020 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 23:22:38.726340 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 23:22:38.729661 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 23:22:38.736289 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 23:22:38.736878 Total UI for P1: 0, mck2ui 16
6438 23:22:38.742994 best dqsien dly found for B0: ( 0, 14, 24)
6439 23:22:38.743522 Total UI for P1: 0, mck2ui 16
6440 23:22:38.745758 best dqsien dly found for B1: ( 0, 14, 24)
6441 23:22:38.752527 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6442 23:22:38.756285 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6443 23:22:38.756821
6444 23:22:38.759426 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6445 23:22:38.762504 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6446 23:22:38.765642 [Gating] SW calibration Done
6447 23:22:38.766159 ==
6448 23:22:38.769043 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 23:22:38.772375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 23:22:38.772924 ==
6451 23:22:38.775629 RX Vref Scan: 0
6452 23:22:38.776048
6453 23:22:38.776381 RX Vref 0 -> 0, step: 1
6454 23:22:38.776690
6455 23:22:38.779244 RX Delay -410 -> 252, step: 16
6456 23:22:38.785590 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6457 23:22:38.788836 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6458 23:22:38.792077 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6459 23:22:38.795216 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6460 23:22:38.802287 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6461 23:22:38.805511 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6462 23:22:38.808928 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6463 23:22:38.811786 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6464 23:22:38.818408 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6465 23:22:38.821987 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6466 23:22:38.825358 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6467 23:22:38.828548 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6468 23:22:38.835136 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6469 23:22:38.838365 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6470 23:22:38.841871 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6471 23:22:38.845048 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6472 23:22:38.848498 ==
6473 23:22:38.851803 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 23:22:38.855500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 23:22:38.856026 ==
6476 23:22:38.856368 DQS Delay:
6477 23:22:38.858474 DQS0 = 59, DQS1 = 59
6478 23:22:38.858894 DQM Delay:
6479 23:22:38.861710 DQM0 = 16, DQM1 = 10
6480 23:22:38.862143 DQ Delay:
6481 23:22:38.865065 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6482 23:22:38.868334 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6483 23:22:38.871697 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6484 23:22:38.874668 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6485 23:22:38.875092
6486 23:22:38.875428
6487 23:22:38.875738 ==
6488 23:22:38.878241 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 23:22:38.881326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 23:22:38.881793 ==
6491 23:22:38.882130
6492 23:22:38.882497
6493 23:22:38.884674 TX Vref Scan disable
6494 23:22:38.887980 == TX Byte 0 ==
6495 23:22:38.891611 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6496 23:22:38.894990 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6497 23:22:38.895513 == TX Byte 1 ==
6498 23:22:38.901658 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6499 23:22:38.905032 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6500 23:22:38.905633 ==
6501 23:22:38.908355 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 23:22:38.911361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 23:22:38.911786 ==
6504 23:22:38.912121
6505 23:22:38.912511
6506 23:22:38.915012 TX Vref Scan disable
6507 23:22:38.918177 == TX Byte 0 ==
6508 23:22:38.921641 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6509 23:22:38.924797 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6510 23:22:38.925321 == TX Byte 1 ==
6511 23:22:38.931531 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6512 23:22:38.934641 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6513 23:22:38.935101
6514 23:22:38.935437 [DATLAT]
6515 23:22:38.938255 Freq=400, CH0 RK1
6516 23:22:38.938828
6517 23:22:38.939178 DATLAT Default: 0xe
6518 23:22:38.941374 0, 0xFFFF, sum = 0
6519 23:22:38.941836 1, 0xFFFF, sum = 0
6520 23:22:38.944741 2, 0xFFFF, sum = 0
6521 23:22:38.945271 3, 0xFFFF, sum = 0
6522 23:22:38.948212 4, 0xFFFF, sum = 0
6523 23:22:38.951347 5, 0xFFFF, sum = 0
6524 23:22:38.951876 6, 0xFFFF, sum = 0
6525 23:22:38.954677 7, 0xFFFF, sum = 0
6526 23:22:38.955207 8, 0xFFFF, sum = 0
6527 23:22:38.958079 9, 0xFFFF, sum = 0
6528 23:22:38.958610 10, 0xFFFF, sum = 0
6529 23:22:38.961040 11, 0xFFFF, sum = 0
6530 23:22:38.961469 12, 0xFFFF, sum = 0
6531 23:22:38.964627 13, 0x0, sum = 1
6532 23:22:38.965158 14, 0x0, sum = 2
6533 23:22:38.967971 15, 0x0, sum = 3
6534 23:22:38.968552 16, 0x0, sum = 4
6535 23:22:38.971118 best_step = 14
6536 23:22:38.971538
6537 23:22:38.971922 ==
6538 23:22:38.974445 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 23:22:38.977897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 23:22:38.978465 ==
6541 23:22:38.978974 RX Vref Scan: 0
6542 23:22:38.981192
6543 23:22:38.981778 RX Vref 0 -> 0, step: 1
6544 23:22:38.982122
6545 23:22:38.984395 RX Delay -359 -> 252, step: 8
6546 23:22:38.992139 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6547 23:22:38.995257 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6548 23:22:38.998409 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6549 23:22:39.001589 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6550 23:22:39.008465 iDelay=217, Bit 4, Center -48 (-295 ~ 200) 496
6551 23:22:39.011731 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6552 23:22:39.015169 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6553 23:22:39.021829 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6554 23:22:39.024755 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6555 23:22:39.027930 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6556 23:22:39.031724 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6557 23:22:39.038068 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6558 23:22:39.041181 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6559 23:22:39.044554 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6560 23:22:39.047745 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6561 23:22:39.054325 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6562 23:22:39.054838 ==
6563 23:22:39.057886 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 23:22:39.061074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 23:22:39.061661 ==
6566 23:22:39.062004 DQS Delay:
6567 23:22:39.064345 DQS0 = 60, DQS1 = 72
6568 23:22:39.064869 DQM Delay:
6569 23:22:39.067848 DQM0 = 12, DQM1 = 18
6570 23:22:39.068371 DQ Delay:
6571 23:22:39.070898 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6572 23:22:39.074258 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6573 23:22:39.077405 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6574 23:22:39.080898 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =24
6575 23:22:39.081528
6576 23:22:39.081927
6577 23:22:39.087550 [DQSOSCAuto] RK1, (LSB)MR18= 0xc97f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6578 23:22:39.090809 CH0 RK1: MR19=C0C, MR18=C97F
6579 23:22:39.097455 CH0_RK1: MR19=0xC0C, MR18=0xC97F, DQSOSC=384, MR23=63, INC=400, DEC=267
6580 23:22:39.100881 [RxdqsGatingPostProcess] freq 400
6581 23:22:39.107389 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6582 23:22:39.110801 best DQS0 dly(2T, 0.5T) = (0, 10)
6583 23:22:39.113919 best DQS1 dly(2T, 0.5T) = (0, 10)
6584 23:22:39.117208 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6585 23:22:39.120876 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6586 23:22:39.121400 best DQS0 dly(2T, 0.5T) = (0, 10)
6587 23:22:39.124125 best DQS1 dly(2T, 0.5T) = (0, 10)
6588 23:22:39.127470 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6589 23:22:39.130511 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6590 23:22:39.133805 Pre-setting of DQS Precalculation
6591 23:22:39.140548 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6592 23:22:39.141109 ==
6593 23:22:39.144275 Dram Type= 6, Freq= 0, CH_1, rank 0
6594 23:22:39.147151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 23:22:39.147595 ==
6596 23:22:39.153591 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6597 23:22:39.160473 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6598 23:22:39.164042 [CA 0] Center 36 (8~64) winsize 57
6599 23:22:39.164570 [CA 1] Center 36 (8~64) winsize 57
6600 23:22:39.166986 [CA 2] Center 36 (8~64) winsize 57
6601 23:22:39.170824 [CA 3] Center 36 (8~64) winsize 57
6602 23:22:39.173750 [CA 4] Center 36 (8~64) winsize 57
6603 23:22:39.176806 [CA 5] Center 36 (8~64) winsize 57
6604 23:22:39.177330
6605 23:22:39.180225 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6606 23:22:39.180749
6607 23:22:39.186570 [CATrainingPosCal] consider 1 rank data
6608 23:22:39.186991 u2DelayCellTimex100 = 270/100 ps
6609 23:22:39.193602 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 23:22:39.196884 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 23:22:39.200326 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 23:22:39.203265 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 23:22:39.206828 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 23:22:39.210115 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 23:22:39.210642
6616 23:22:39.213208 CA PerBit enable=1, Macro0, CA PI delay=36
6617 23:22:39.213658
6618 23:22:39.217052 [CBTSetCACLKResult] CA Dly = 36
6619 23:22:39.220158 CS Dly: 1 (0~32)
6620 23:22:39.220680 ==
6621 23:22:39.223057 Dram Type= 6, Freq= 0, CH_1, rank 1
6622 23:22:39.226630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6623 23:22:39.227051 ==
6624 23:22:39.233257 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6625 23:22:39.236538 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6626 23:22:39.239849 [CA 0] Center 36 (8~64) winsize 57
6627 23:22:39.243324 [CA 1] Center 36 (8~64) winsize 57
6628 23:22:39.246448 [CA 2] Center 36 (8~64) winsize 57
6629 23:22:39.250173 [CA 3] Center 36 (8~64) winsize 57
6630 23:22:39.253227 [CA 4] Center 36 (8~64) winsize 57
6631 23:22:39.256459 [CA 5] Center 36 (8~64) winsize 57
6632 23:22:39.256869
6633 23:22:39.260272 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6634 23:22:39.260826
6635 23:22:39.263204 [CATrainingPosCal] consider 2 rank data
6636 23:22:39.266612 u2DelayCellTimex100 = 270/100 ps
6637 23:22:39.269997 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 23:22:39.273178 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 23:22:39.276435 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 23:22:39.280171 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 23:22:39.286228 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 23:22:39.289716 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 23:22:39.290234
6644 23:22:39.293268 CA PerBit enable=1, Macro0, CA PI delay=36
6645 23:22:39.293831
6646 23:22:39.296456 [CBTSetCACLKResult] CA Dly = 36
6647 23:22:39.296981 CS Dly: 1 (0~32)
6648 23:22:39.297313
6649 23:22:39.299715 ----->DramcWriteLeveling(PI) begin...
6650 23:22:39.300238 ==
6651 23:22:39.302642 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 23:22:39.309812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 23:22:39.310331 ==
6654 23:22:39.312873 Write leveling (Byte 0): 40 => 8
6655 23:22:39.316436 Write leveling (Byte 1): 40 => 8
6656 23:22:39.316959 DramcWriteLeveling(PI) end<-----
6657 23:22:39.317292
6658 23:22:39.319148 ==
6659 23:22:39.322759 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 23:22:39.325995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 23:22:39.326566 ==
6662 23:22:39.329531 [Gating] SW mode calibration
6663 23:22:39.335859 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6664 23:22:39.339662 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6665 23:22:39.346147 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 23:22:39.349024 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6667 23:22:39.352572 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 23:22:39.358993 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 23:22:39.362437 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 23:22:39.365535 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 23:22:39.372617 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 23:22:39.375510 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 23:22:39.379128 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 23:22:39.382385 Total UI for P1: 0, mck2ui 16
6675 23:22:39.385300 best dqsien dly found for B0: ( 0, 14, 24)
6676 23:22:39.388897 Total UI for P1: 0, mck2ui 16
6677 23:22:39.392469 best dqsien dly found for B1: ( 0, 14, 24)
6678 23:22:39.395538 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6679 23:22:39.398981 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6680 23:22:39.399505
6681 23:22:39.405754 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6682 23:22:39.409013 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6683 23:22:39.412282 [Gating] SW calibration Done
6684 23:22:39.412807 ==
6685 23:22:39.415655 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 23:22:39.418838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 23:22:39.419369 ==
6688 23:22:39.419708 RX Vref Scan: 0
6689 23:22:39.420020
6690 23:22:39.422126 RX Vref 0 -> 0, step: 1
6691 23:22:39.422548
6692 23:22:39.425130 RX Delay -410 -> 252, step: 16
6693 23:22:39.428870 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6694 23:22:39.435225 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6695 23:22:39.438923 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6696 23:22:39.441609 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6697 23:22:39.445169 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6698 23:22:39.451856 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6699 23:22:39.454926 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6700 23:22:39.458314 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6701 23:22:39.461788 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6702 23:22:39.468057 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6703 23:22:39.472006 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6704 23:22:39.474874 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6705 23:22:39.478272 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6706 23:22:39.484964 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6707 23:22:39.488280 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6708 23:22:39.491189 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6709 23:22:39.491637 ==
6710 23:22:39.494508 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 23:22:39.501514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 23:22:39.502046 ==
6713 23:22:39.502385 DQS Delay:
6714 23:22:39.504702 DQS0 = 51, DQS1 = 67
6715 23:22:39.505121 DQM Delay:
6716 23:22:39.505457 DQM0 = 13, DQM1 = 18
6717 23:22:39.507689 DQ Delay:
6718 23:22:39.511145 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6719 23:22:39.514444 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6720 23:22:39.514864 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6721 23:22:39.518194 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6722 23:22:39.521326
6723 23:22:39.521892
6724 23:22:39.522230 ==
6725 23:22:39.524253 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 23:22:39.527949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 23:22:39.528494 ==
6728 23:22:39.528837
6729 23:22:39.529148
6730 23:22:39.531391 TX Vref Scan disable
6731 23:22:39.531912 == TX Byte 0 ==
6732 23:22:39.534213 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 23:22:39.540753 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 23:22:39.541179 == TX Byte 1 ==
6735 23:22:39.543943 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 23:22:39.550691 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 23:22:39.551115 ==
6738 23:22:39.554216 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 23:22:39.557272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 23:22:39.557731 ==
6741 23:22:39.558069
6742 23:22:39.558382
6743 23:22:39.560369 TX Vref Scan disable
6744 23:22:39.560787 == TX Byte 0 ==
6745 23:22:39.567434 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 23:22:39.570943 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 23:22:39.571468 == TX Byte 1 ==
6748 23:22:39.577313 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6749 23:22:39.581066 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6750 23:22:39.581631
6751 23:22:39.581972 [DATLAT]
6752 23:22:39.584198 Freq=400, CH1 RK0
6753 23:22:39.584719
6754 23:22:39.585055 DATLAT Default: 0xf
6755 23:22:39.587152 0, 0xFFFF, sum = 0
6756 23:22:39.587580 1, 0xFFFF, sum = 0
6757 23:22:39.590372 2, 0xFFFF, sum = 0
6758 23:22:39.590899 3, 0xFFFF, sum = 0
6759 23:22:39.593537 4, 0xFFFF, sum = 0
6760 23:22:39.594071 5, 0xFFFF, sum = 0
6761 23:22:39.596887 6, 0xFFFF, sum = 0
6762 23:22:39.597312 7, 0xFFFF, sum = 0
6763 23:22:39.600308 8, 0xFFFF, sum = 0
6764 23:22:39.600837 9, 0xFFFF, sum = 0
6765 23:22:39.603400 10, 0xFFFF, sum = 0
6766 23:22:39.607013 11, 0xFFFF, sum = 0
6767 23:22:39.607541 12, 0xFFFF, sum = 0
6768 23:22:39.610281 13, 0x0, sum = 1
6769 23:22:39.610814 14, 0x0, sum = 2
6770 23:22:39.613745 15, 0x0, sum = 3
6771 23:22:39.614271 16, 0x0, sum = 4
6772 23:22:39.614619 best_step = 14
6773 23:22:39.614933
6774 23:22:39.616755 ==
6775 23:22:39.620204 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 23:22:39.623580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 23:22:39.624128 ==
6778 23:22:39.624557 RX Vref Scan: 1
6779 23:22:39.624880
6780 23:22:39.626488 RX Vref 0 -> 0, step: 1
6781 23:22:39.626906
6782 23:22:39.630346 RX Delay -375 -> 252, step: 8
6783 23:22:39.630875
6784 23:22:39.633216 Set Vref, RX VrefLevel [Byte0]: 55
6785 23:22:39.636404 [Byte1]: 45
6786 23:22:39.640428
6787 23:22:39.640975 Final RX Vref Byte 0 = 55 to rank0
6788 23:22:39.643637 Final RX Vref Byte 1 = 45 to rank0
6789 23:22:39.647134 Final RX Vref Byte 0 = 55 to rank1
6790 23:22:39.650389 Final RX Vref Byte 1 = 45 to rank1==
6791 23:22:39.653519 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 23:22:39.660410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 23:22:39.660935 ==
6794 23:22:39.661276 DQS Delay:
6795 23:22:39.664077 DQS0 = 52, DQS1 = 68
6796 23:22:39.664601 DQM Delay:
6797 23:22:39.664941 DQM0 = 9, DQM1 = 14
6798 23:22:39.666718 DQ Delay:
6799 23:22:39.670293 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6800 23:22:39.670715 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6801 23:22:39.673590 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6802 23:22:39.677019 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6803 23:22:39.677440
6804 23:22:39.677807
6805 23:22:39.686783 [DQSOSCAuto] RK0, (LSB)MR18= 0x5569, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6806 23:22:39.690343 CH1 RK0: MR19=C0C, MR18=5569
6807 23:22:39.697001 CH1_RK0: MR19=0xC0C, MR18=0x5569, DQSOSC=396, MR23=63, INC=376, DEC=251
6808 23:22:39.697557 ==
6809 23:22:39.700541 Dram Type= 6, Freq= 0, CH_1, rank 1
6810 23:22:39.703377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 23:22:39.703803 ==
6812 23:22:39.706729 [Gating] SW mode calibration
6813 23:22:39.713880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6814 23:22:39.720247 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6815 23:22:39.723814 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6816 23:22:39.726607 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6817 23:22:39.730162 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 23:22:39.736688 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 23:22:39.740011 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 23:22:39.743226 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 23:22:39.749718 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 23:22:39.753310 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 23:22:39.756587 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 23:22:39.759884 Total UI for P1: 0, mck2ui 16
6825 23:22:39.763234 best dqsien dly found for B0: ( 0, 14, 24)
6826 23:22:39.766363 Total UI for P1: 0, mck2ui 16
6827 23:22:39.769699 best dqsien dly found for B1: ( 0, 14, 24)
6828 23:22:39.773212 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6829 23:22:39.779943 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6830 23:22:39.780469
6831 23:22:39.783243 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6832 23:22:39.786182 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6833 23:22:39.789962 [Gating] SW calibration Done
6834 23:22:39.790483 ==
6835 23:22:39.793234 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 23:22:39.796768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 23:22:39.797295 ==
6838 23:22:39.797675 RX Vref Scan: 0
6839 23:22:39.799940
6840 23:22:39.800462 RX Vref 0 -> 0, step: 1
6841 23:22:39.800799
6842 23:22:39.802841 RX Delay -410 -> 252, step: 16
6843 23:22:39.806166 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6844 23:22:39.813002 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6845 23:22:39.816557 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6846 23:22:39.819703 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6847 23:22:39.822680 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6848 23:22:39.829686 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6849 23:22:39.832912 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6850 23:22:39.836035 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6851 23:22:39.839453 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6852 23:22:39.845934 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6853 23:22:39.849063 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6854 23:22:39.852573 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6855 23:22:39.855781 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6856 23:22:39.862178 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6857 23:22:39.865606 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6858 23:22:39.869306 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6859 23:22:39.869887 ==
6860 23:22:39.872447 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 23:22:39.878875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 23:22:39.879387 ==
6863 23:22:39.879725 DQS Delay:
6864 23:22:39.882326 DQS0 = 59, DQS1 = 59
6865 23:22:39.882847 DQM Delay:
6866 23:22:39.885771 DQM0 = 20, DQM1 = 12
6867 23:22:39.886296 DQ Delay:
6868 23:22:39.888905 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6869 23:22:39.892023 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6870 23:22:39.895423 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6871 23:22:39.898485 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6872 23:22:39.898909
6873 23:22:39.899240
6874 23:22:39.899654 ==
6875 23:22:39.901991 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 23:22:39.905310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 23:22:39.905795 ==
6878 23:22:39.906134
6879 23:22:39.906446
6880 23:22:39.908413 TX Vref Scan disable
6881 23:22:39.908832 == TX Byte 0 ==
6882 23:22:39.915112 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6883 23:22:39.918553 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6884 23:22:39.918976 == TX Byte 1 ==
6885 23:22:39.925207 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6886 23:22:39.928558 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6887 23:22:39.928979 ==
6888 23:22:39.931752 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 23:22:39.935174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 23:22:39.935597 ==
6891 23:22:39.935931
6892 23:22:39.936242
6893 23:22:39.938550 TX Vref Scan disable
6894 23:22:39.938971 == TX Byte 0 ==
6895 23:22:39.945038 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6896 23:22:39.948492 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6897 23:22:39.948953 == TX Byte 1 ==
6898 23:22:39.954802 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6899 23:22:39.958084 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6900 23:22:39.958660
6901 23:22:39.959008 [DATLAT]
6902 23:22:39.961609 Freq=400, CH1 RK1
6903 23:22:39.962032
6904 23:22:39.962369 DATLAT Default: 0xe
6905 23:22:39.965074 0, 0xFFFF, sum = 0
6906 23:22:39.965542 1, 0xFFFF, sum = 0
6907 23:22:39.968070 2, 0xFFFF, sum = 0
6908 23:22:39.968498 3, 0xFFFF, sum = 0
6909 23:22:39.971276 4, 0xFFFF, sum = 0
6910 23:22:39.971580 5, 0xFFFF, sum = 0
6911 23:22:39.974778 6, 0xFFFF, sum = 0
6912 23:22:39.975027 7, 0xFFFF, sum = 0
6913 23:22:39.977814 8, 0xFFFF, sum = 0
6914 23:22:39.978043 9, 0xFFFF, sum = 0
6915 23:22:39.981093 10, 0xFFFF, sum = 0
6916 23:22:39.984570 11, 0xFFFF, sum = 0
6917 23:22:39.984755 12, 0xFFFF, sum = 0
6918 23:22:39.987830 13, 0x0, sum = 1
6919 23:22:39.987985 14, 0x0, sum = 2
6920 23:22:39.988108 15, 0x0, sum = 3
6921 23:22:39.990964 16, 0x0, sum = 4
6922 23:22:39.991097 best_step = 14
6923 23:22:39.991199
6924 23:22:39.994318 ==
6925 23:22:39.997917 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 23:22:40.000926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 23:22:40.001029 ==
6928 23:22:40.001110 RX Vref Scan: 0
6929 23:22:40.001185
6930 23:22:40.004193 RX Vref 0 -> 0, step: 1
6931 23:22:40.004294
6932 23:22:40.007304 RX Delay -359 -> 252, step: 8
6933 23:22:40.014357 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6934 23:22:40.017697 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6935 23:22:40.021171 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6936 23:22:40.024556 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6937 23:22:40.030787 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6938 23:22:40.034335 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6939 23:22:40.037424 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6940 23:22:40.044055 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6941 23:22:40.047611 iDelay=217, Bit 8, Center -68 (-319 ~ 184) 504
6942 23:22:40.050630 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6943 23:22:40.054110 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6944 23:22:40.060641 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6945 23:22:40.063977 iDelay=217, Bit 12, Center -44 (-295 ~ 208) 504
6946 23:22:40.067458 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6947 23:22:40.070633 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6948 23:22:40.077015 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6949 23:22:40.077106 ==
6950 23:22:40.080469 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 23:22:40.083718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 23:22:40.083810 ==
6953 23:22:40.083877 DQS Delay:
6954 23:22:40.087256 DQS0 = 60, DQS1 = 68
6955 23:22:40.087366 DQM Delay:
6956 23:22:40.090438 DQM0 = 13, DQM1 = 14
6957 23:22:40.090521 DQ Delay:
6958 23:22:40.093861 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6959 23:22:40.097312 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6960 23:22:40.100445 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6961 23:22:40.103597 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6962 23:22:40.103684
6963 23:22:40.103749
6964 23:22:40.110361 [DQSOSCAuto] RK1, (LSB)MR18= 0x78a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6965 23:22:40.113851 CH1 RK1: MR19=C0C, MR18=78A8
6966 23:22:40.120367 CH1_RK1: MR19=0xC0C, MR18=0x78A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6967 23:22:40.123634 [RxdqsGatingPostProcess] freq 400
6968 23:22:40.130165 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6969 23:22:40.133752 best DQS0 dly(2T, 0.5T) = (0, 10)
6970 23:22:40.137009 best DQS1 dly(2T, 0.5T) = (0, 10)
6971 23:22:40.140208 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6972 23:22:40.140293 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6973 23:22:40.143457 best DQS0 dly(2T, 0.5T) = (0, 10)
6974 23:22:40.146721 best DQS1 dly(2T, 0.5T) = (0, 10)
6975 23:22:40.150118 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6976 23:22:40.153517 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6977 23:22:40.157115 Pre-setting of DQS Precalculation
6978 23:22:40.163745 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6979 23:22:40.170443 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6980 23:22:40.177052 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6981 23:22:40.177134
6982 23:22:40.177199
6983 23:22:40.180167 [Calibration Summary] 800 Mbps
6984 23:22:40.180249 CH 0, Rank 0
6985 23:22:40.183544 SW Impedance : PASS
6986 23:22:40.186837 DUTY Scan : NO K
6987 23:22:40.186921 ZQ Calibration : PASS
6988 23:22:40.190218 Jitter Meter : NO K
6989 23:22:40.193675 CBT Training : PASS
6990 23:22:40.193834 Write leveling : PASS
6991 23:22:40.197233 RX DQS gating : PASS
6992 23:22:40.197391 RX DQ/DQS(RDDQC) : PASS
6993 23:22:40.200237 TX DQ/DQS : PASS
6994 23:22:40.203897 RX DATLAT : PASS
6995 23:22:40.204061 RX DQ/DQS(Engine): PASS
6996 23:22:40.206764 TX OE : NO K
6997 23:22:40.206925 All Pass.
6998 23:22:40.206996
6999 23:22:40.209936 CH 0, Rank 1
7000 23:22:40.210097 SW Impedance : PASS
7001 23:22:40.213503 DUTY Scan : NO K
7002 23:22:40.217160 ZQ Calibration : PASS
7003 23:22:40.217319 Jitter Meter : NO K
7004 23:22:40.220381 CBT Training : PASS
7005 23:22:40.223744 Write leveling : NO K
7006 23:22:40.223912 RX DQS gating : PASS
7007 23:22:40.226866 RX DQ/DQS(RDDQC) : PASS
7008 23:22:40.230214 TX DQ/DQS : PASS
7009 23:22:40.230362 RX DATLAT : PASS
7010 23:22:40.233487 RX DQ/DQS(Engine): PASS
7011 23:22:40.236875 TX OE : NO K
7012 23:22:40.237104 All Pass.
7013 23:22:40.237250
7014 23:22:40.237391 CH 1, Rank 0
7015 23:22:40.240098 SW Impedance : PASS
7016 23:22:40.243363 DUTY Scan : NO K
7017 23:22:40.243563 ZQ Calibration : PASS
7018 23:22:40.246808 Jitter Meter : NO K
7019 23:22:40.249861 CBT Training : PASS
7020 23:22:40.250013 Write leveling : PASS
7021 23:22:40.253237 RX DQS gating : PASS
7022 23:22:40.256817 RX DQ/DQS(RDDQC) : PASS
7023 23:22:40.257075 TX DQ/DQS : PASS
7024 23:22:40.260216 RX DATLAT : PASS
7025 23:22:40.260515 RX DQ/DQS(Engine): PASS
7026 23:22:40.262933 TX OE : NO K
7027 23:22:40.263140 All Pass.
7028 23:22:40.263299
7029 23:22:40.266445 CH 1, Rank 1
7030 23:22:40.266785 SW Impedance : PASS
7031 23:22:40.269919 DUTY Scan : NO K
7032 23:22:40.273303 ZQ Calibration : PASS
7033 23:22:40.273733 Jitter Meter : NO K
7034 23:22:40.276842 CBT Training : PASS
7035 23:22:40.279739 Write leveling : NO K
7036 23:22:40.280245 RX DQS gating : PASS
7037 23:22:40.283643 RX DQ/DQS(RDDQC) : PASS
7038 23:22:40.286814 TX DQ/DQS : PASS
7039 23:22:40.287339 RX DATLAT : PASS
7040 23:22:40.289744 RX DQ/DQS(Engine): PASS
7041 23:22:40.293199 TX OE : NO K
7042 23:22:40.293657 All Pass.
7043 23:22:40.293995
7044 23:22:40.296566 DramC Write-DBI off
7045 23:22:40.296983 PER_BANK_REFRESH: Hybrid Mode
7046 23:22:40.299640 TX_TRACKING: ON
7047 23:22:40.306563 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7048 23:22:40.312996 [FAST_K] Save calibration result to emmc
7049 23:22:40.316660 dramc_set_vcore_voltage set vcore to 725000
7050 23:22:40.317200 Read voltage for 1600, 0
7051 23:22:40.319593 Vio18 = 0
7052 23:22:40.320014 Vcore = 725000
7053 23:22:40.320349 Vdram = 0
7054 23:22:40.323213 Vddq = 0
7055 23:22:40.323630 Vmddr = 0
7056 23:22:40.326423 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7057 23:22:40.333234 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7058 23:22:40.336125 MEM_TYPE=3, freq_sel=13
7059 23:22:40.339879 sv_algorithm_assistance_LP4_3733
7060 23:22:40.342781 ============ PULL DRAM RESETB DOWN ============
7061 23:22:40.345750 ========== PULL DRAM RESETB DOWN end =========
7062 23:22:40.352763 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7063 23:22:40.356116 ===================================
7064 23:22:40.356540 LPDDR4 DRAM CONFIGURATION
7065 23:22:40.359426 ===================================
7066 23:22:40.362469 EX_ROW_EN[0] = 0x0
7067 23:22:40.365866 EX_ROW_EN[1] = 0x0
7068 23:22:40.366420 LP4Y_EN = 0x0
7069 23:22:40.369266 WORK_FSP = 0x1
7070 23:22:40.369851 WL = 0x5
7071 23:22:40.372573 RL = 0x5
7072 23:22:40.373095 BL = 0x2
7073 23:22:40.375817 RPST = 0x0
7074 23:22:40.376235 RD_PRE = 0x0
7075 23:22:40.378943 WR_PRE = 0x1
7076 23:22:40.379436 WR_PST = 0x1
7077 23:22:40.382215 DBI_WR = 0x0
7078 23:22:40.382723 DBI_RD = 0x0
7079 23:22:40.385805 OTF = 0x1
7080 23:22:40.388766 ===================================
7081 23:22:40.392576 ===================================
7082 23:22:40.393094 ANA top config
7083 23:22:40.395745 ===================================
7084 23:22:40.398861 DLL_ASYNC_EN = 0
7085 23:22:40.402334 ALL_SLAVE_EN = 0
7086 23:22:40.402758 NEW_RANK_MODE = 1
7087 23:22:40.405626 DLL_IDLE_MODE = 1
7088 23:22:40.408860 LP45_APHY_COMB_EN = 1
7089 23:22:40.412413 TX_ODT_DIS = 0
7090 23:22:40.415590 NEW_8X_MODE = 1
7091 23:22:40.418803 ===================================
7092 23:22:40.422118 ===================================
7093 23:22:40.425327 data_rate = 3200
7094 23:22:40.425798 CKR = 1
7095 23:22:40.428725 DQ_P2S_RATIO = 8
7096 23:22:40.432430 ===================================
7097 23:22:40.435041 CA_P2S_RATIO = 8
7098 23:22:40.438630 DQ_CA_OPEN = 0
7099 23:22:40.442057 DQ_SEMI_OPEN = 0
7100 23:22:40.442565 CA_SEMI_OPEN = 0
7101 23:22:40.445037 CA_FULL_RATE = 0
7102 23:22:40.448289 DQ_CKDIV4_EN = 0
7103 23:22:40.451836 CA_CKDIV4_EN = 0
7104 23:22:40.455432 CA_PREDIV_EN = 0
7105 23:22:40.458242 PH8_DLY = 12
7106 23:22:40.461711 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7107 23:22:40.462133 DQ_AAMCK_DIV = 4
7108 23:22:40.465006 CA_AAMCK_DIV = 4
7109 23:22:40.468468 CA_ADMCK_DIV = 4
7110 23:22:40.471866 DQ_TRACK_CA_EN = 0
7111 23:22:40.475283 CA_PICK = 1600
7112 23:22:40.478081 CA_MCKIO = 1600
7113 23:22:40.481449 MCKIO_SEMI = 0
7114 23:22:40.481903 PLL_FREQ = 3068
7115 23:22:40.485215 DQ_UI_PI_RATIO = 32
7116 23:22:40.488255 CA_UI_PI_RATIO = 0
7117 23:22:40.491824 ===================================
7118 23:22:40.495040 ===================================
7119 23:22:40.498419 memory_type:LPDDR4
7120 23:22:40.499068 GP_NUM : 10
7121 23:22:40.501427 SRAM_EN : 1
7122 23:22:40.504579 MD32_EN : 0
7123 23:22:40.508473 ===================================
7124 23:22:40.508995 [ANA_INIT] >>>>>>>>>>>>>>
7125 23:22:40.511272 <<<<<< [CONFIGURE PHASE]: ANA_TX
7126 23:22:40.514612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7127 23:22:40.517950 ===================================
7128 23:22:40.521120 data_rate = 3200,PCW = 0X7600
7129 23:22:40.524505 ===================================
7130 23:22:40.527988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7131 23:22:40.534234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7132 23:22:40.541197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7133 23:22:40.544228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7134 23:22:40.547430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7135 23:22:40.551081 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7136 23:22:40.554052 [ANA_INIT] flow start
7137 23:22:40.554473 [ANA_INIT] PLL >>>>>>>>
7138 23:22:40.557583 [ANA_INIT] PLL <<<<<<<<
7139 23:22:40.560975 [ANA_INIT] MIDPI >>>>>>>>
7140 23:22:40.561545 [ANA_INIT] MIDPI <<<<<<<<
7141 23:22:40.564474 [ANA_INIT] DLL >>>>>>>>
7142 23:22:40.567279 [ANA_INIT] DLL <<<<<<<<
7143 23:22:40.567699 [ANA_INIT] flow end
7144 23:22:40.574156 ============ LP4 DIFF to SE enter ============
7145 23:22:40.577376 ============ LP4 DIFF to SE exit ============
7146 23:22:40.580297 [ANA_INIT] <<<<<<<<<<<<<
7147 23:22:40.584026 [Flow] Enable top DCM control >>>>>
7148 23:22:40.586957 [Flow] Enable top DCM control <<<<<
7149 23:22:40.587380 Enable DLL master slave shuffle
7150 23:22:40.593661 ==============================================================
7151 23:22:40.596885 Gating Mode config
7152 23:22:40.600317 ==============================================================
7153 23:22:40.603638 Config description:
7154 23:22:40.613862 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7155 23:22:40.620430 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7156 23:22:40.623895 SELPH_MODE 0: By rank 1: By Phase
7157 23:22:40.630251 ==============================================================
7158 23:22:40.633711 GAT_TRACK_EN = 1
7159 23:22:40.636787 RX_GATING_MODE = 2
7160 23:22:40.640276 RX_GATING_TRACK_MODE = 2
7161 23:22:40.643002 SELPH_MODE = 1
7162 23:22:40.646665 PICG_EARLY_EN = 1
7163 23:22:40.647092 VALID_LAT_VALUE = 1
7164 23:22:40.653259 ==============================================================
7165 23:22:40.656282 Enter into Gating configuration >>>>
7166 23:22:40.660184 Exit from Gating configuration <<<<
7167 23:22:40.662946 Enter into DVFS_PRE_config >>>>>
7168 23:22:40.673511 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7169 23:22:40.676516 Exit from DVFS_PRE_config <<<<<
7170 23:22:40.679471 Enter into PICG configuration >>>>
7171 23:22:40.682875 Exit from PICG configuration <<<<
7172 23:22:40.686270 [RX_INPUT] configuration >>>>>
7173 23:22:40.689608 [RX_INPUT] configuration <<<<<
7174 23:22:40.696101 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7175 23:22:40.699639 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7176 23:22:40.706028 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7177 23:22:40.712919 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7178 23:22:40.719588 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7179 23:22:40.726099 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7180 23:22:40.729214 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7181 23:22:40.732701 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7182 23:22:40.735801 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7183 23:22:40.742176 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7184 23:22:40.745861 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7185 23:22:40.749223 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7186 23:22:40.752914 ===================================
7187 23:22:40.756102 LPDDR4 DRAM CONFIGURATION
7188 23:22:40.759269 ===================================
7189 23:22:40.759696 EX_ROW_EN[0] = 0x0
7190 23:22:40.762356 EX_ROW_EN[1] = 0x0
7191 23:22:40.766144 LP4Y_EN = 0x0
7192 23:22:40.766665 WORK_FSP = 0x1
7193 23:22:40.769174 WL = 0x5
7194 23:22:40.769626 RL = 0x5
7195 23:22:40.772452 BL = 0x2
7196 23:22:40.772846 RPST = 0x0
7197 23:22:40.775491 RD_PRE = 0x0
7198 23:22:40.775909 WR_PRE = 0x1
7199 23:22:40.779108 WR_PST = 0x1
7200 23:22:40.779527 DBI_WR = 0x0
7201 23:22:40.782426 DBI_RD = 0x0
7202 23:22:40.782955 OTF = 0x1
7203 23:22:40.785636 ===================================
7204 23:22:40.789000 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7205 23:22:40.795508 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7206 23:22:40.798780 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7207 23:22:40.801848 ===================================
7208 23:22:40.805583 LPDDR4 DRAM CONFIGURATION
7209 23:22:40.808513 ===================================
7210 23:22:40.808938 EX_ROW_EN[0] = 0x10
7211 23:22:40.812314 EX_ROW_EN[1] = 0x0
7212 23:22:40.815490 LP4Y_EN = 0x0
7213 23:22:40.816012 WORK_FSP = 0x1
7214 23:22:40.819040 WL = 0x5
7215 23:22:40.819565 RL = 0x5
7216 23:22:40.822224 BL = 0x2
7217 23:22:40.822748 RPST = 0x0
7218 23:22:40.825338 RD_PRE = 0x0
7219 23:22:40.825786 WR_PRE = 0x1
7220 23:22:40.828871 WR_PST = 0x1
7221 23:22:40.829395 DBI_WR = 0x0
7222 23:22:40.831899 DBI_RD = 0x0
7223 23:22:40.832422 OTF = 0x1
7224 23:22:40.835454 ===================================
7225 23:22:40.842101 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7226 23:22:40.842616 ==
7227 23:22:40.845417 Dram Type= 6, Freq= 0, CH_0, rank 0
7228 23:22:40.848440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7229 23:22:40.851952 ==
7230 23:22:40.852373 [Duty_Offset_Calibration]
7231 23:22:40.855212 B0:2 B1:0 CA:3
7232 23:22:40.855748
7233 23:22:40.858170 [DutyScan_Calibration_Flow] k_type=0
7234 23:22:40.867275
7235 23:22:40.867800 ==CLK 0==
7236 23:22:40.870363 Final CLK duty delay cell = 0
7237 23:22:40.873920 [0] MAX Duty = 5031%(X100), DQS PI = 12
7238 23:22:40.877401 [0] MIN Duty = 4907%(X100), DQS PI = 6
7239 23:22:40.877960 [0] AVG Duty = 4969%(X100)
7240 23:22:40.878302
7241 23:22:40.880266 CH0 CLK Duty spec in!! Max-Min= 124%
7242 23:22:40.887307 [DutyScan_Calibration_Flow] ====Done====
7243 23:22:40.887839
7244 23:22:40.890360 [DutyScan_Calibration_Flow] k_type=1
7245 23:22:40.906951
7246 23:22:40.907609 ==DQS 0 ==
7247 23:22:40.910164 Final DQS duty delay cell = 0
7248 23:22:40.913574 [0] MAX Duty = 5094%(X100), DQS PI = 14
7249 23:22:40.916755 [0] MIN Duty = 4875%(X100), DQS PI = 48
7250 23:22:40.920252 [0] AVG Duty = 4984%(X100)
7251 23:22:40.920781
7252 23:22:40.921119 ==DQS 1 ==
7253 23:22:40.923477 Final DQS duty delay cell = 0
7254 23:22:40.926777 [0] MAX Duty = 5156%(X100), DQS PI = 32
7255 23:22:40.929877 [0] MIN Duty = 5031%(X100), DQS PI = 14
7256 23:22:40.933051 [0] AVG Duty = 5093%(X100)
7257 23:22:40.933473
7258 23:22:40.936598 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7259 23:22:40.937017
7260 23:22:40.939886 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7261 23:22:40.943257 [DutyScan_Calibration_Flow] ====Done====
7262 23:22:40.943780
7263 23:22:40.946462 [DutyScan_Calibration_Flow] k_type=3
7264 23:22:40.964487
7265 23:22:40.964978 ==DQM 0 ==
7266 23:22:40.968122 Final DQM duty delay cell = 0
7267 23:22:40.971157 [0] MAX Duty = 5187%(X100), DQS PI = 30
7268 23:22:40.974305 [0] MIN Duty = 4875%(X100), DQS PI = 0
7269 23:22:40.977786 [0] AVG Duty = 5031%(X100)
7270 23:22:40.978356
7271 23:22:40.978894 ==DQM 1 ==
7272 23:22:40.980919 Final DQM duty delay cell = 4
7273 23:22:40.984515 [4] MAX Duty = 5187%(X100), DQS PI = 60
7274 23:22:40.987683 [4] MIN Duty = 5031%(X100), DQS PI = 12
7275 23:22:40.990944 [4] AVG Duty = 5109%(X100)
7276 23:22:40.991529
7277 23:22:40.994121 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7278 23:22:40.994610
7279 23:22:40.997342 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7280 23:22:41.000917 [DutyScan_Calibration_Flow] ====Done====
7281 23:22:41.001338
7282 23:22:41.003983 [DutyScan_Calibration_Flow] k_type=2
7283 23:22:41.020202
7284 23:22:41.020449 ==DQ 0 ==
7285 23:22:41.023548 Final DQ duty delay cell = -4
7286 23:22:41.026724 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7287 23:22:41.030148 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7288 23:22:41.033792 [-4] AVG Duty = 4938%(X100)
7289 23:22:41.033940
7290 23:22:41.034058 ==DQ 1 ==
7291 23:22:41.036829 Final DQ duty delay cell = 0
7292 23:22:41.040088 [0] MAX Duty = 5156%(X100), DQS PI = 60
7293 23:22:41.043606 [0] MIN Duty = 5000%(X100), DQS PI = 16
7294 23:22:41.046673 [0] AVG Duty = 5078%(X100)
7295 23:22:41.046933
7296 23:22:41.050058 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7297 23:22:41.050391
7298 23:22:41.053533 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7299 23:22:41.056751 [DutyScan_Calibration_Flow] ====Done====
7300 23:22:41.057051 ==
7301 23:22:41.059892 Dram Type= 6, Freq= 0, CH_1, rank 0
7302 23:22:41.063323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7303 23:22:41.063637 ==
7304 23:22:41.066816 [Duty_Offset_Calibration]
7305 23:22:41.067122 B0:1 B1:-2 CA:1
7306 23:22:41.067393
7307 23:22:41.070175 [DutyScan_Calibration_Flow] k_type=0
7308 23:22:41.080726
7309 23:22:41.080953 ==CLK 0==
7310 23:22:41.083961 Final CLK duty delay cell = 0
7311 23:22:41.087420 [0] MAX Duty = 5031%(X100), DQS PI = 0
7312 23:22:41.090761 [0] MIN Duty = 4875%(X100), DQS PI = 26
7313 23:22:41.090942 [0] AVG Duty = 4953%(X100)
7314 23:22:41.093845
7315 23:22:41.097210 CH1 CLK Duty spec in!! Max-Min= 156%
7316 23:22:41.100625 [DutyScan_Calibration_Flow] ====Done====
7317 23:22:41.100787
7318 23:22:41.103660 [DutyScan_Calibration_Flow] k_type=1
7319 23:22:41.120273
7320 23:22:41.120443 ==DQS 0 ==
7321 23:22:41.123615 Final DQS duty delay cell = 0
7322 23:22:41.126762 [0] MAX Duty = 5156%(X100), DQS PI = 0
7323 23:22:41.130322 [0] MIN Duty = 5062%(X100), DQS PI = 14
7324 23:22:41.130486 [0] AVG Duty = 5109%(X100)
7325 23:22:41.133433
7326 23:22:41.133630 ==DQS 1 ==
7327 23:22:41.136979 Final DQS duty delay cell = 0
7328 23:22:41.140515 [0] MAX Duty = 5125%(X100), DQS PI = 30
7329 23:22:41.143554 [0] MIN Duty = 4813%(X100), DQS PI = 58
7330 23:22:41.143715 [0] AVG Duty = 4969%(X100)
7331 23:22:41.146987
7332 23:22:41.150122 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7333 23:22:41.150284
7334 23:22:41.153666 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7335 23:22:41.156697 [DutyScan_Calibration_Flow] ====Done====
7336 23:22:41.156855
7337 23:22:41.160193 [DutyScan_Calibration_Flow] k_type=3
7338 23:22:41.177224
7339 23:22:41.177383 ==DQM 0 ==
7340 23:22:41.180275 Final DQM duty delay cell = 0
7341 23:22:41.183807 [0] MAX Duty = 5031%(X100), DQS PI = 60
7342 23:22:41.186925 [0] MIN Duty = 4844%(X100), DQS PI = 22
7343 23:22:41.190231 [0] AVG Duty = 4937%(X100)
7344 23:22:41.190310
7345 23:22:41.190374 ==DQM 1 ==
7346 23:22:41.193374 Final DQM duty delay cell = 0
7347 23:22:41.197087 [0] MAX Duty = 5062%(X100), DQS PI = 4
7348 23:22:41.200325 [0] MIN Duty = 4844%(X100), DQS PI = 58
7349 23:22:41.203605 [0] AVG Duty = 4953%(X100)
7350 23:22:41.203685
7351 23:22:41.207185 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7352 23:22:41.207343
7353 23:22:41.210395 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7354 23:22:41.213555 [DutyScan_Calibration_Flow] ====Done====
7355 23:22:41.213709
7356 23:22:41.216924 [DutyScan_Calibration_Flow] k_type=2
7357 23:22:41.234032
7358 23:22:41.234219 ==DQ 0 ==
7359 23:22:41.237386 Final DQ duty delay cell = 0
7360 23:22:41.240611 [0] MAX Duty = 5093%(X100), DQS PI = 62
7361 23:22:41.243742 [0] MIN Duty = 4938%(X100), DQS PI = 14
7362 23:22:41.243977 [0] AVG Duty = 5015%(X100)
7363 23:22:41.247102
7364 23:22:41.247252 ==DQ 1 ==
7365 23:22:41.250687 Final DQ duty delay cell = 0
7366 23:22:41.253790 [0] MAX Duty = 5156%(X100), DQS PI = 26
7367 23:22:41.257570 [0] MIN Duty = 4938%(X100), DQS PI = 56
7368 23:22:41.257860 [0] AVG Duty = 5047%(X100)
7369 23:22:41.258031
7370 23:22:41.260547 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7371 23:22:41.264370
7372 23:22:41.267673 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7373 23:22:41.270493 [DutyScan_Calibration_Flow] ====Done====
7374 23:22:41.274113 nWR fixed to 30
7375 23:22:41.274601 [ModeRegInit_LP4] CH0 RK0
7376 23:22:41.277593 [ModeRegInit_LP4] CH0 RK1
7377 23:22:41.281095 [ModeRegInit_LP4] CH1 RK0
7378 23:22:41.284212 [ModeRegInit_LP4] CH1 RK1
7379 23:22:41.284732 match AC timing 5
7380 23:22:41.287409 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7381 23:22:41.294294 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7382 23:22:41.297712 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7383 23:22:41.304072 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7384 23:22:41.307643 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7385 23:22:41.308160 [MiockJmeterHQA]
7386 23:22:41.308501
7387 23:22:41.310481 [DramcMiockJmeter] u1RxGatingPI = 0
7388 23:22:41.314224 0 : 4367, 4140
7389 23:22:41.314743 4 : 4363, 4137
7390 23:22:41.315082 8 : 4258, 4030
7391 23:22:41.317622 12 : 4257, 4029
7392 23:22:41.318145 16 : 4257, 4029
7393 23:22:41.320920 20 : 4368, 4140
7394 23:22:41.321439 24 : 4366, 4139
7395 23:22:41.323648 28 : 4254, 4029
7396 23:22:41.324199 32 : 4255, 4029
7397 23:22:41.327101 36 : 4252, 4029
7398 23:22:41.327519 40 : 4360, 4138
7399 23:22:41.327854 44 : 4253, 4029
7400 23:22:41.330451 48 : 4363, 4140
7401 23:22:41.330982 52 : 4257, 4032
7402 23:22:41.333835 56 : 4252, 4030
7403 23:22:41.334412 60 : 4253, 4029
7404 23:22:41.337146 64 : 4257, 4031
7405 23:22:41.337605 68 : 4255, 4029
7406 23:22:41.340425 72 : 4253, 4029
7407 23:22:41.340854 76 : 4368, 4142
7408 23:22:41.341196 80 : 4255, 4029
7409 23:22:41.343430 84 : 4258, 4031
7410 23:22:41.343857 88 : 4252, 4029
7411 23:22:41.346957 92 : 4253, 4030
7412 23:22:41.347384 96 : 4257, 4032
7413 23:22:41.349943 100 : 4255, 4029
7414 23:22:41.350371 104 : 4253, 3529
7415 23:22:41.353468 108 : 4253, 2
7416 23:22:41.354045 112 : 4253, 0
7417 23:22:41.354454 116 : 4255, 0
7418 23:22:41.356658 120 : 4258, 0
7419 23:22:41.357078 124 : 4255, 0
7420 23:22:41.360073 128 : 4255, 0
7421 23:22:41.360492 132 : 4257, 0
7422 23:22:41.360826 136 : 4365, 0
7423 23:22:41.363460 140 : 4255, 0
7424 23:22:41.363879 144 : 4255, 0
7425 23:22:41.364215 148 : 4255, 0
7426 23:22:41.366653 152 : 4255, 0
7427 23:22:41.367071 156 : 4368, 0
7428 23:22:41.370003 160 : 4253, 0
7429 23:22:41.370419 164 : 4255, 0
7430 23:22:41.370754 168 : 4368, 0
7431 23:22:41.373118 172 : 4255, 0
7432 23:22:41.373579 176 : 4253, 0
7433 23:22:41.376705 180 : 4250, 0
7434 23:22:41.377122 184 : 4258, 0
7435 23:22:41.377473 188 : 4253, 0
7436 23:22:41.380085 192 : 4255, 0
7437 23:22:41.380588 196 : 4257, 0
7438 23:22:41.383046 200 : 4255, 0
7439 23:22:41.383466 204 : 4250, 0
7440 23:22:41.383800 208 : 4257, 0
7441 23:22:41.386560 212 : 4255, 0
7442 23:22:41.386978 216 : 4255, 0
7443 23:22:41.387311 220 : 4368, 0
7444 23:22:41.389705 224 : 4252, 0
7445 23:22:41.390123 228 : 4366, 0
7446 23:22:41.392966 232 : 4255, 0
7447 23:22:41.393386 236 : 4255, 960
7448 23:22:41.396689 240 : 4363, 4140
7449 23:22:41.397214 244 : 4253, 4029
7450 23:22:41.399783 248 : 4363, 4140
7451 23:22:41.400200 252 : 4363, 4139
7452 23:22:41.400537 256 : 4255, 4029
7453 23:22:41.402942 260 : 4252, 4029
7454 23:22:41.403361 264 : 4252, 4030
7455 23:22:41.406458 268 : 4257, 4031
7456 23:22:41.406881 272 : 4250, 4027
7457 23:22:41.409778 276 : 4253, 4029
7458 23:22:41.410302 280 : 4253, 4030
7459 23:22:41.413175 284 : 4253, 4029
7460 23:22:41.413623 288 : 4253, 4029
7461 23:22:41.416405 292 : 4255, 4029
7462 23:22:41.416924 296 : 4253, 4029
7463 23:22:41.419793 300 : 4252, 4030
7464 23:22:41.420343 304 : 4368, 4142
7465 23:22:41.423107 308 : 4255, 4029
7466 23:22:41.423584 312 : 4253, 4029
7467 23:22:41.423925 316 : 4252, 4030
7468 23:22:41.426536 320 : 4252, 4029
7469 23:22:41.426956 324 : 4368, 4142
7470 23:22:41.429966 328 : 4365, 4140
7471 23:22:41.430385 332 : 4252, 4030
7472 23:22:41.432976 336 : 4255, 4029
7473 23:22:41.433395 340 : 4365, 4139
7474 23:22:41.436376 344 : 4253, 4029
7475 23:22:41.436794 348 : 4253, 4029
7476 23:22:41.439772 352 : 4257, 4014
7477 23:22:41.440201 356 : 4363, 2755
7478 23:22:41.443102 360 : 4363, 4
7479 23:22:41.443519
7480 23:22:41.443849 MIOCK jitter meter ch=0
7481 23:22:41.444155
7482 23:22:41.446327 1T = (360-108) = 252 dly cells
7483 23:22:41.453115 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7484 23:22:41.453646 ==
7485 23:22:41.456376 Dram Type= 6, Freq= 0, CH_0, rank 0
7486 23:22:41.459617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7487 23:22:41.460036 ==
7488 23:22:41.466120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7489 23:22:41.469427 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7490 23:22:41.472926 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7491 23:22:41.479304 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7492 23:22:41.488861 [CA 0] Center 44 (14~75) winsize 62
7493 23:22:41.492470 [CA 1] Center 43 (13~74) winsize 62
7494 23:22:41.495510 [CA 2] Center 40 (11~69) winsize 59
7495 23:22:41.499002 [CA 3] Center 39 (10~69) winsize 60
7496 23:22:41.502041 [CA 4] Center 37 (8~67) winsize 60
7497 23:22:41.505200 [CA 5] Center 37 (8~66) winsize 59
7498 23:22:41.505662
7499 23:22:41.508584 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7500 23:22:41.508869
7501 23:22:41.515218 [CATrainingPosCal] consider 1 rank data
7502 23:22:41.515443 u2DelayCellTimex100 = 258/100 ps
7503 23:22:41.521761 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7504 23:22:41.525161 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7505 23:22:41.528398 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7506 23:22:41.531699 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7507 23:22:41.534838 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7508 23:22:41.538403 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7509 23:22:41.538517
7510 23:22:41.541597 CA PerBit enable=1, Macro0, CA PI delay=37
7511 23:22:41.541723
7512 23:22:41.545044 [CBTSetCACLKResult] CA Dly = 37
7513 23:22:41.548011 CS Dly: 11 (0~42)
7514 23:22:41.551399 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7515 23:22:41.554882 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7516 23:22:41.555009 ==
7517 23:22:41.558052 Dram Type= 6, Freq= 0, CH_0, rank 1
7518 23:22:41.564691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7519 23:22:41.564780 ==
7520 23:22:41.568172 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7521 23:22:41.574607 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7522 23:22:41.578200 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7523 23:22:41.584596 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7524 23:22:41.592380 [CA 0] Center 44 (14~75) winsize 62
7525 23:22:41.595563 [CA 1] Center 43 (13~74) winsize 62
7526 23:22:41.599102 [CA 2] Center 39 (10~69) winsize 60
7527 23:22:41.602237 [CA 3] Center 39 (10~69) winsize 60
7528 23:22:41.605747 [CA 4] Center 37 (8~67) winsize 60
7529 23:22:41.608825 [CA 5] Center 37 (7~67) winsize 61
7530 23:22:41.608897
7531 23:22:41.612339 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7532 23:22:41.612408
7533 23:22:41.619006 [CATrainingPosCal] consider 2 rank data
7534 23:22:41.619088 u2DelayCellTimex100 = 258/100 ps
7535 23:22:41.625627 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7536 23:22:41.628751 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7537 23:22:41.632107 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7538 23:22:41.635469 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7539 23:22:41.638722 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7540 23:22:41.642069 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7541 23:22:41.642150
7542 23:22:41.645592 CA PerBit enable=1, Macro0, CA PI delay=37
7543 23:22:41.645673
7544 23:22:41.648727 [CBTSetCACLKResult] CA Dly = 37
7545 23:22:41.652256 CS Dly: 11 (0~43)
7546 23:22:41.655156 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7547 23:22:41.658856 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7548 23:22:41.658940
7549 23:22:41.661905 ----->DramcWriteLeveling(PI) begin...
7550 23:22:41.661987 ==
7551 23:22:41.665110 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 23:22:41.671927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 23:22:41.672009 ==
7554 23:22:41.675188 Write leveling (Byte 0): 36 => 36
7555 23:22:41.678634 Write leveling (Byte 1): 29 => 29
7556 23:22:41.678716 DramcWriteLeveling(PI) end<-----
7557 23:22:41.681714
7558 23:22:41.681795 ==
7559 23:22:41.684964 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 23:22:41.688398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 23:22:41.688520 ==
7562 23:22:41.691696 [Gating] SW mode calibration
7563 23:22:41.698392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7564 23:22:41.701713 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7565 23:22:41.707990 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 23:22:41.711538 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 23:22:41.718180 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 23:22:41.721290 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 23:22:41.724761 1 4 16 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7570 23:22:41.727956 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7571 23:22:41.734676 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7572 23:22:41.737831 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 23:22:41.741231 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 23:22:41.747824 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 23:22:41.751210 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7576 23:22:41.754818 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7577 23:22:41.761036 1 5 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
7578 23:22:41.764514 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
7579 23:22:41.767728 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7580 23:22:41.774485 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 23:22:41.777762 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 23:22:41.781114 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 23:22:41.787441 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 23:22:41.790869 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 23:22:41.794261 1 6 16 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7586 23:22:41.800737 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7587 23:22:41.803897 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7588 23:22:41.807279 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 23:22:41.814073 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 23:22:41.817340 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 23:22:41.820743 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 23:22:41.827088 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7593 23:22:41.830467 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7594 23:22:41.834034 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7595 23:22:41.840432 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7596 23:22:41.843982 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 23:22:41.847207 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 23:22:41.853857 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 23:22:41.857189 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 23:22:41.860551 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 23:22:41.867074 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 23:22:41.870229 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 23:22:41.873692 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 23:22:41.880494 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 23:22:41.883457 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 23:22:41.886950 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 23:22:41.893743 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 23:22:41.896957 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 23:22:41.900375 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7610 23:22:41.906965 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7611 23:22:41.910119 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7612 23:22:41.913399 Total UI for P1: 0, mck2ui 16
7613 23:22:41.916625 best dqsien dly found for B0: ( 1, 9, 18)
7614 23:22:41.920026 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 23:22:41.923258 Total UI for P1: 0, mck2ui 16
7616 23:22:41.926571 best dqsien dly found for B1: ( 1, 9, 24)
7617 23:22:41.930096 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7618 23:22:41.933204 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7619 23:22:41.933274
7620 23:22:41.936775 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7621 23:22:41.943103 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7622 23:22:41.943187 [Gating] SW calibration Done
7623 23:22:41.946546 ==
7624 23:22:41.949739 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 23:22:41.953236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 23:22:41.953351 ==
7627 23:22:41.953443 RX Vref Scan: 0
7628 23:22:41.953560
7629 23:22:41.956332 RX Vref 0 -> 0, step: 1
7630 23:22:41.956406
7631 23:22:41.959533 RX Delay 0 -> 252, step: 8
7632 23:22:41.963059 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7633 23:22:41.966433 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7634 23:22:41.969733 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7635 23:22:41.976485 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7636 23:22:41.979604 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7637 23:22:41.983053 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7638 23:22:41.986225 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7639 23:22:41.989390 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7640 23:22:41.996092 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7641 23:22:41.999301 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7642 23:22:42.002911 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7643 23:22:42.006286 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7644 23:22:42.009431 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7645 23:22:42.015949 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7646 23:22:42.019378 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7647 23:22:42.022519 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7648 23:22:42.022607 ==
7649 23:22:42.026086 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 23:22:42.029047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 23:22:42.032383 ==
7652 23:22:42.032457 DQS Delay:
7653 23:22:42.032518 DQS0 = 0, DQS1 = 0
7654 23:22:42.035590 DQM Delay:
7655 23:22:42.035658 DQM0 = 128, DQM1 = 124
7656 23:22:42.039084 DQ Delay:
7657 23:22:42.042246 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7658 23:22:42.045829 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7659 23:22:42.048990 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7660 23:22:42.052168 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7661 23:22:42.052250
7662 23:22:42.052315
7663 23:22:42.052374 ==
7664 23:22:42.055824 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 23:22:42.058968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 23:22:42.059049 ==
7667 23:22:42.062166
7668 23:22:42.062246
7669 23:22:42.062309 TX Vref Scan disable
7670 23:22:42.065670 == TX Byte 0 ==
7671 23:22:42.068813 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7672 23:22:42.072007 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7673 23:22:42.075539 == TX Byte 1 ==
7674 23:22:42.078869 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7675 23:22:42.082066 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7676 23:22:42.085405 ==
7677 23:22:42.085545 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 23:22:42.091764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 23:22:42.091846 ==
7680 23:22:42.104656
7681 23:22:42.107945 TX Vref early break, caculate TX vref
7682 23:22:42.111442 TX Vref=16, minBit 8, minWin=21, winSum=363
7683 23:22:42.114644 TX Vref=18, minBit 4, minWin=22, winSum=378
7684 23:22:42.117974 TX Vref=20, minBit 8, minWin=23, winSum=385
7685 23:22:42.121054 TX Vref=22, minBit 5, minWin=24, winSum=393
7686 23:22:42.124623 TX Vref=24, minBit 4, minWin=24, winSum=405
7687 23:22:42.130963 TX Vref=26, minBit 8, minWin=24, winSum=405
7688 23:22:42.134287 TX Vref=28, minBit 8, minWin=25, winSum=414
7689 23:22:42.137666 TX Vref=30, minBit 8, minWin=24, winSum=406
7690 23:22:42.141062 TX Vref=32, minBit 8, minWin=24, winSum=396
7691 23:22:42.144380 TX Vref=34, minBit 4, minWin=23, winSum=384
7692 23:22:42.150972 [TxChooseVref] Worse bit 8, Min win 25, Win sum 414, Final Vref 28
7693 23:22:42.151100
7694 23:22:42.154464 Final TX Range 0 Vref 28
7695 23:22:42.154545
7696 23:22:42.154610 ==
7697 23:22:42.157647 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 23:22:42.160707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 23:22:42.160789 ==
7700 23:22:42.160855
7701 23:22:42.160915
7702 23:22:42.164090 TX Vref Scan disable
7703 23:22:42.170701 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7704 23:22:42.170782 == TX Byte 0 ==
7705 23:22:42.174202 u2DelayCellOfst[0]=15 cells (4 PI)
7706 23:22:42.177401 u2DelayCellOfst[1]=18 cells (5 PI)
7707 23:22:42.180500 u2DelayCellOfst[2]=11 cells (3 PI)
7708 23:22:42.184026 u2DelayCellOfst[3]=15 cells (4 PI)
7709 23:22:42.187209 u2DelayCellOfst[4]=11 cells (3 PI)
7710 23:22:42.190748 u2DelayCellOfst[5]=0 cells (0 PI)
7711 23:22:42.193700 u2DelayCellOfst[6]=22 cells (6 PI)
7712 23:22:42.197309 u2DelayCellOfst[7]=22 cells (6 PI)
7713 23:22:42.200530 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7714 23:22:42.203604 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7715 23:22:42.207158 == TX Byte 1 ==
7716 23:22:42.210315 u2DelayCellOfst[8]=0 cells (0 PI)
7717 23:22:42.213801 u2DelayCellOfst[9]=3 cells (1 PI)
7718 23:22:42.213887 u2DelayCellOfst[10]=7 cells (2 PI)
7719 23:22:42.217177 u2DelayCellOfst[11]=7 cells (2 PI)
7720 23:22:42.220427 u2DelayCellOfst[12]=15 cells (4 PI)
7721 23:22:42.223762 u2DelayCellOfst[13]=11 cells (3 PI)
7722 23:22:42.226879 u2DelayCellOfst[14]=18 cells (5 PI)
7723 23:22:42.230254 u2DelayCellOfst[15]=11 cells (3 PI)
7724 23:22:42.236858 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7725 23:22:42.240318 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7726 23:22:42.240481 DramC Write-DBI on
7727 23:22:42.240587 ==
7728 23:22:42.243484 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 23:22:42.250062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 23:22:42.250150 ==
7731 23:22:42.250236
7732 23:22:42.250316
7733 23:22:42.250395 TX Vref Scan disable
7734 23:22:42.254186 == TX Byte 0 ==
7735 23:22:42.257355 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7736 23:22:42.260764 == TX Byte 1 ==
7737 23:22:42.264369 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7738 23:22:42.267475 DramC Write-DBI off
7739 23:22:42.267558
7740 23:22:42.267643 [DATLAT]
7741 23:22:42.267724 Freq=1600, CH0 RK0
7742 23:22:42.267803
7743 23:22:42.270991 DATLAT Default: 0xf
7744 23:22:42.271074 0, 0xFFFF, sum = 0
7745 23:22:42.274201 1, 0xFFFF, sum = 0
7746 23:22:42.277279 2, 0xFFFF, sum = 0
7747 23:22:42.277364 3, 0xFFFF, sum = 0
7748 23:22:42.280764 4, 0xFFFF, sum = 0
7749 23:22:42.280850 5, 0xFFFF, sum = 0
7750 23:22:42.283989 6, 0xFFFF, sum = 0
7751 23:22:42.284074 7, 0xFFFF, sum = 0
7752 23:22:42.287484 8, 0xFFFF, sum = 0
7753 23:22:42.287568 9, 0xFFFF, sum = 0
7754 23:22:42.290553 10, 0xFFFF, sum = 0
7755 23:22:42.290654 11, 0xFFFF, sum = 0
7756 23:22:42.294088 12, 0xFFFF, sum = 0
7757 23:22:42.294174 13, 0xFFFF, sum = 0
7758 23:22:42.297331 14, 0x0, sum = 1
7759 23:22:42.297416 15, 0x0, sum = 2
7760 23:22:42.300488 16, 0x0, sum = 3
7761 23:22:42.300573 17, 0x0, sum = 4
7762 23:22:42.304026 best_step = 15
7763 23:22:42.304110
7764 23:22:42.304194 ==
7765 23:22:42.307391 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 23:22:42.310728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 23:22:42.310813 ==
7768 23:22:42.313989 RX Vref Scan: 1
7769 23:22:42.314073
7770 23:22:42.314158 Set Vref Range= 24 -> 127
7771 23:22:42.314240
7772 23:22:42.317166 RX Vref 24 -> 127, step: 1
7773 23:22:42.317249
7774 23:22:42.320458 RX Delay 11 -> 252, step: 4
7775 23:22:42.320542
7776 23:22:42.323583 Set Vref, RX VrefLevel [Byte0]: 24
7777 23:22:42.327028 [Byte1]: 24
7778 23:22:42.327111
7779 23:22:42.330337 Set Vref, RX VrefLevel [Byte0]: 25
7780 23:22:42.333769 [Byte1]: 25
7781 23:22:42.336984
7782 23:22:42.337068 Set Vref, RX VrefLevel [Byte0]: 26
7783 23:22:42.340329 [Byte1]: 26
7784 23:22:42.344777
7785 23:22:42.344861 Set Vref, RX VrefLevel [Byte0]: 27
7786 23:22:42.347820 [Byte1]: 27
7787 23:22:42.352368
7788 23:22:42.352453 Set Vref, RX VrefLevel [Byte0]: 28
7789 23:22:42.355589 [Byte1]: 28
7790 23:22:42.359866
7791 23:22:42.359949 Set Vref, RX VrefLevel [Byte0]: 29
7792 23:22:42.363264 [Byte1]: 29
7793 23:22:42.367408
7794 23:22:42.367492 Set Vref, RX VrefLevel [Byte0]: 30
7795 23:22:42.370837 [Byte1]: 30
7796 23:22:42.375036
7797 23:22:42.375119 Set Vref, RX VrefLevel [Byte0]: 31
7798 23:22:42.378505 [Byte1]: 31
7799 23:22:42.382815
7800 23:22:42.382899 Set Vref, RX VrefLevel [Byte0]: 32
7801 23:22:42.385979 [Byte1]: 32
7802 23:22:42.390280
7803 23:22:42.393417 Set Vref, RX VrefLevel [Byte0]: 33
7804 23:22:42.393539 [Byte1]: 33
7805 23:22:42.398105
7806 23:22:42.398188 Set Vref, RX VrefLevel [Byte0]: 34
7807 23:22:42.401195 [Byte1]: 34
7808 23:22:42.405593
7809 23:22:42.405677 Set Vref, RX VrefLevel [Byte0]: 35
7810 23:22:42.409051 [Byte1]: 35
7811 23:22:42.413168
7812 23:22:42.413252 Set Vref, RX VrefLevel [Byte0]: 36
7813 23:22:42.416618 [Byte1]: 36
7814 23:22:42.420818
7815 23:22:42.420901 Set Vref, RX VrefLevel [Byte0]: 37
7816 23:22:42.424010 [Byte1]: 37
7817 23:22:42.428361
7818 23:22:42.428445 Set Vref, RX VrefLevel [Byte0]: 38
7819 23:22:42.431463 [Byte1]: 38
7820 23:22:42.436027
7821 23:22:42.436111 Set Vref, RX VrefLevel [Byte0]: 39
7822 23:22:42.439456 [Byte1]: 39
7823 23:22:42.443703
7824 23:22:42.443787 Set Vref, RX VrefLevel [Byte0]: 40
7825 23:22:42.446896 [Byte1]: 40
7826 23:22:42.451416
7827 23:22:42.451558 Set Vref, RX VrefLevel [Byte0]: 41
7828 23:22:42.454718 [Byte1]: 41
7829 23:22:42.458724
7830 23:22:42.458809 Set Vref, RX VrefLevel [Byte0]: 42
7831 23:22:42.462020 [Byte1]: 42
7832 23:22:42.466708
7833 23:22:42.466792 Set Vref, RX VrefLevel [Byte0]: 43
7834 23:22:42.469721 [Byte1]: 43
7835 23:22:42.474095
7836 23:22:42.474179 Set Vref, RX VrefLevel [Byte0]: 44
7837 23:22:42.477456 [Byte1]: 44
7838 23:22:42.481734
7839 23:22:42.481818 Set Vref, RX VrefLevel [Byte0]: 45
7840 23:22:42.485039 [Byte1]: 45
7841 23:22:42.489047
7842 23:22:42.492622 Set Vref, RX VrefLevel [Byte0]: 46
7843 23:22:42.495722 [Byte1]: 46
7844 23:22:42.495807
7845 23:22:42.498871 Set Vref, RX VrefLevel [Byte0]: 47
7846 23:22:42.502387 [Byte1]: 47
7847 23:22:42.502470
7848 23:22:42.505655 Set Vref, RX VrefLevel [Byte0]: 48
7849 23:22:42.508716 [Byte1]: 48
7850 23:22:42.512170
7851 23:22:42.512254 Set Vref, RX VrefLevel [Byte0]: 49
7852 23:22:42.515352 [Byte1]: 49
7853 23:22:42.519837
7854 23:22:42.519923 Set Vref, RX VrefLevel [Byte0]: 50
7855 23:22:42.522936 [Byte1]: 50
7856 23:22:42.527495
7857 23:22:42.527579 Set Vref, RX VrefLevel [Byte0]: 51
7858 23:22:42.530744 [Byte1]: 51
7859 23:22:42.535055
7860 23:22:42.535138 Set Vref, RX VrefLevel [Byte0]: 52
7861 23:22:42.538086 [Byte1]: 52
7862 23:22:42.542690
7863 23:22:42.542774 Set Vref, RX VrefLevel [Byte0]: 53
7864 23:22:42.545807 [Byte1]: 53
7865 23:22:42.550072
7866 23:22:42.550154 Set Vref, RX VrefLevel [Byte0]: 54
7867 23:22:42.553705 [Byte1]: 54
7868 23:22:42.557841
7869 23:22:42.557926 Set Vref, RX VrefLevel [Byte0]: 55
7870 23:22:42.561167 [Byte1]: 55
7871 23:22:42.565288
7872 23:22:42.565371 Set Vref, RX VrefLevel [Byte0]: 56
7873 23:22:42.568716 [Byte1]: 56
7874 23:22:42.572825
7875 23:22:42.572909 Set Vref, RX VrefLevel [Byte0]: 57
7876 23:22:42.576263 [Byte1]: 57
7877 23:22:42.580832
7878 23:22:42.580919 Set Vref, RX VrefLevel [Byte0]: 58
7879 23:22:42.583752 [Byte1]: 58
7880 23:22:42.588340
7881 23:22:42.588424 Set Vref, RX VrefLevel [Byte0]: 59
7882 23:22:42.591610 [Byte1]: 59
7883 23:22:42.595768
7884 23:22:42.595876 Set Vref, RX VrefLevel [Byte0]: 60
7885 23:22:42.599015 [Byte1]: 60
7886 23:22:42.603723
7887 23:22:42.603808 Set Vref, RX VrefLevel [Byte0]: 61
7888 23:22:42.606621 [Byte1]: 61
7889 23:22:42.611215
7890 23:22:42.611299 Set Vref, RX VrefLevel [Byte0]: 62
7891 23:22:42.614364 [Byte1]: 62
7892 23:22:42.618726
7893 23:22:42.618810 Set Vref, RX VrefLevel [Byte0]: 63
7894 23:22:42.621986 [Byte1]: 63
7895 23:22:42.626195
7896 23:22:42.626279 Set Vref, RX VrefLevel [Byte0]: 64
7897 23:22:42.629676 [Byte1]: 64
7898 23:22:42.634083
7899 23:22:42.634166 Set Vref, RX VrefLevel [Byte0]: 65
7900 23:22:42.637103 [Byte1]: 65
7901 23:22:42.641534
7902 23:22:42.641641 Set Vref, RX VrefLevel [Byte0]: 66
7903 23:22:42.644837 [Byte1]: 66
7904 23:22:42.649225
7905 23:22:42.649309 Set Vref, RX VrefLevel [Byte0]: 67
7906 23:22:42.652312 [Byte1]: 67
7907 23:22:42.656811
7908 23:22:42.656892 Set Vref, RX VrefLevel [Byte0]: 68
7909 23:22:42.660182 [Byte1]: 68
7910 23:22:42.664382
7911 23:22:42.664463 Set Vref, RX VrefLevel [Byte0]: 69
7912 23:22:42.667701 [Byte1]: 69
7913 23:22:42.672055
7914 23:22:42.672136 Set Vref, RX VrefLevel [Byte0]: 70
7915 23:22:42.675206 [Byte1]: 70
7916 23:22:42.679723
7917 23:22:42.679804 Set Vref, RX VrefLevel [Byte0]: 71
7918 23:22:42.682904 [Byte1]: 71
7919 23:22:42.687342
7920 23:22:42.687422 Set Vref, RX VrefLevel [Byte0]: 72
7921 23:22:42.690495 [Byte1]: 72
7922 23:22:42.694717
7923 23:22:42.694792 Set Vref, RX VrefLevel [Byte0]: 73
7924 23:22:42.698041 [Byte1]: 73
7925 23:22:42.702229
7926 23:22:42.702310 Set Vref, RX VrefLevel [Byte0]: 74
7927 23:22:42.705682 [Byte1]: 74
7928 23:22:42.709897
7929 23:22:42.709977 Set Vref, RX VrefLevel [Byte0]: 75
7930 23:22:42.713231 [Byte1]: 75
7931 23:22:42.717780
7932 23:22:42.717859 Set Vref, RX VrefLevel [Byte0]: 76
7933 23:22:42.720862 [Byte1]: 76
7934 23:22:42.725165
7935 23:22:42.725245 Final RX Vref Byte 0 = 63 to rank0
7936 23:22:42.728764 Final RX Vref Byte 1 = 59 to rank0
7937 23:22:42.731828 Final RX Vref Byte 0 = 63 to rank1
7938 23:22:42.735349 Final RX Vref Byte 1 = 59 to rank1==
7939 23:22:42.738822 Dram Type= 6, Freq= 0, CH_0, rank 0
7940 23:22:42.745194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 23:22:42.745275 ==
7942 23:22:42.745340 DQS Delay:
7943 23:22:42.748771 DQS0 = 0, DQS1 = 0
7944 23:22:42.748880 DQM Delay:
7945 23:22:42.748979 DQM0 = 126, DQM1 = 120
7946 23:22:42.751590 DQ Delay:
7947 23:22:42.754830 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7948 23:22:42.758438 DQ4 =126, DQ5 =112, DQ6 =134, DQ7 =138
7949 23:22:42.761421 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7950 23:22:42.764869 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7951 23:22:42.764982
7952 23:22:42.765083
7953 23:22:42.765174
7954 23:22:42.768324 [DramC_TX_OE_Calibration] TA2
7955 23:22:42.771622 Original DQ_B0 (3 6) =30, OEN = 27
7956 23:22:42.774785 Original DQ_B1 (3 6) =30, OEN = 27
7957 23:22:42.778354 24, 0x0, End_B0=24 End_B1=24
7958 23:22:42.778441 25, 0x0, End_B0=25 End_B1=25
7959 23:22:42.781587 26, 0x0, End_B0=26 End_B1=26
7960 23:22:42.784710 27, 0x0, End_B0=27 End_B1=27
7961 23:22:42.788245 28, 0x0, End_B0=28 End_B1=28
7962 23:22:42.791301 29, 0x0, End_B0=29 End_B1=29
7963 23:22:42.791386 30, 0x0, End_B0=30 End_B1=30
7964 23:22:42.794732 31, 0x4141, End_B0=30 End_B1=30
7965 23:22:42.798107 Byte0 end_step=30 best_step=27
7966 23:22:42.801239 Byte1 end_step=30 best_step=27
7967 23:22:42.804738 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 23:22:42.807935 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 23:22:42.808017
7970 23:22:42.808081
7971 23:22:42.814460 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
7972 23:22:42.817955 CH0 RK0: MR19=303, MR18=1111
7973 23:22:42.824629 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=22, DEC=15
7974 23:22:42.824717
7975 23:22:42.827796 ----->DramcWriteLeveling(PI) begin...
7976 23:22:42.827871 ==
7977 23:22:42.831112 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 23:22:42.834487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 23:22:42.834577 ==
7980 23:22:42.837793 Write leveling (Byte 0): 33 => 33
7981 23:22:42.841262 Write leveling (Byte 1): 28 => 28
7982 23:22:42.844417 DramcWriteLeveling(PI) end<-----
7983 23:22:42.844505
7984 23:22:42.844570 ==
7985 23:22:42.847847 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 23:22:42.851035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 23:22:42.851136 ==
7988 23:22:42.854239 [Gating] SW mode calibration
7989 23:22:42.861021 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7990 23:22:42.867358 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7991 23:22:42.870798 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 23:22:42.877582 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 23:22:42.880771 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7994 23:22:42.883935 1 4 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7995 23:22:42.890615 1 4 16 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
7996 23:22:42.893894 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7997 23:22:42.897400 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 23:22:42.903983 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 23:22:42.907693 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 23:22:42.910539 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 23:22:42.917345 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8002 23:22:42.920763 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8003 23:22:42.923989 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8004 23:22:42.927119 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8005 23:22:42.933869 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 23:22:42.937298 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 23:22:42.940571 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 23:22:42.947269 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 23:22:42.950733 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8010 23:22:42.954021 1 6 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8011 23:22:42.960275 1 6 16 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
8012 23:22:42.963826 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8013 23:22:42.967224 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 23:22:42.973666 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 23:22:42.976968 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 23:22:42.980112 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 23:22:42.986826 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 23:22:42.990006 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8019 23:22:42.993426 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8020 23:22:43.000122 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 23:22:43.003356 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 23:22:43.006667 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 23:22:43.013375 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 23:22:43.016397 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 23:22:43.019812 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 23:22:43.026401 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 23:22:43.029855 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 23:22:43.032779 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 23:22:43.039464 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 23:22:43.042732 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 23:22:43.046048 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 23:22:43.053088 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 23:22:43.056046 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8034 23:22:43.059163 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8035 23:22:43.062706 Total UI for P1: 0, mck2ui 16
8036 23:22:43.065786 best dqsien dly found for B0: ( 1, 9, 8)
8037 23:22:43.072341 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8038 23:22:43.075790 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8039 23:22:43.079190 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 23:22:43.082387 Total UI for P1: 0, mck2ui 16
8041 23:22:43.085747 best dqsien dly found for B1: ( 1, 9, 18)
8042 23:22:43.089089 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8043 23:22:43.092171 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8044 23:22:43.095694
8045 23:22:43.098810 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8046 23:22:43.102259 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8047 23:22:43.105376 [Gating] SW calibration Done
8048 23:22:43.105550 ==
8049 23:22:43.108722 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 23:22:43.112104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 23:22:43.112190 ==
8052 23:22:43.112256 RX Vref Scan: 0
8053 23:22:43.115211
8054 23:22:43.115284 RX Vref 0 -> 0, step: 1
8055 23:22:43.115347
8056 23:22:43.118797 RX Delay 0 -> 252, step: 8
8057 23:22:43.121933 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8058 23:22:43.125357 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8059 23:22:43.131665 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8060 23:22:43.134964 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8061 23:22:43.138312 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8062 23:22:43.141885 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8063 23:22:43.145002 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8064 23:22:43.151611 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8065 23:22:43.155040 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8066 23:22:43.158317 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8067 23:22:43.161663 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8068 23:22:43.165007 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8069 23:22:43.171734 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8070 23:22:43.175110 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8071 23:22:43.178488 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8072 23:22:43.181275 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8073 23:22:43.181385 ==
8074 23:22:43.184817 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 23:22:43.191258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 23:22:43.191343 ==
8077 23:22:43.191409 DQS Delay:
8078 23:22:43.194911 DQS0 = 0, DQS1 = 0
8079 23:22:43.194997 DQM Delay:
8080 23:22:43.198181 DQM0 = 128, DQM1 = 120
8081 23:22:43.198264 DQ Delay:
8082 23:22:43.201257 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8083 23:22:43.204418 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8084 23:22:43.207843 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
8085 23:22:43.211422 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8086 23:22:43.211507
8087 23:22:43.211593
8088 23:22:43.211673 ==
8089 23:22:43.214615 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 23:22:43.221125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 23:22:43.221211 ==
8092 23:22:43.221296
8093 23:22:43.221395
8094 23:22:43.221517 TX Vref Scan disable
8095 23:22:43.224659 == TX Byte 0 ==
8096 23:22:43.228082 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8097 23:22:43.234504 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8098 23:22:43.234584 == TX Byte 1 ==
8099 23:22:43.238047 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8100 23:22:43.244409 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8101 23:22:43.244489 ==
8102 23:22:43.247966 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 23:22:43.251020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 23:22:43.251105 ==
8105 23:22:43.265054
8106 23:22:43.268618 TX Vref early break, caculate TX vref
8107 23:22:43.271653 TX Vref=16, minBit 8, minWin=21, winSum=365
8108 23:22:43.274888 TX Vref=18, minBit 1, minWin=21, winSum=373
8109 23:22:43.278346 TX Vref=20, minBit 0, minWin=22, winSum=376
8110 23:22:43.281786 TX Vref=22, minBit 0, minWin=24, winSum=391
8111 23:22:43.284784 TX Vref=24, minBit 8, minWin=24, winSum=400
8112 23:22:43.291420 TX Vref=26, minBit 8, minWin=24, winSum=405
8113 23:22:43.294945 TX Vref=28, minBit 1, minWin=25, winSum=409
8114 23:22:43.298291 TX Vref=30, minBit 7, minWin=24, winSum=407
8115 23:22:43.301619 TX Vref=32, minBit 0, minWin=24, winSum=395
8116 23:22:43.304922 TX Vref=34, minBit 8, minWin=22, winSum=389
8117 23:22:43.308291 TX Vref=36, minBit 8, minWin=21, winSum=379
8118 23:22:43.314918 [TxChooseVref] Worse bit 1, Min win 25, Win sum 409, Final Vref 28
8119 23:22:43.315015
8120 23:22:43.318446 Final TX Range 0 Vref 28
8121 23:22:43.318531
8122 23:22:43.318597 ==
8123 23:22:43.321526 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 23:22:43.324729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 23:22:43.324814 ==
8126 23:22:43.324881
8127 23:22:43.324942
8128 23:22:43.328196 TX Vref Scan disable
8129 23:22:43.334738 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8130 23:22:43.334822 == TX Byte 0 ==
8131 23:22:43.338141 u2DelayCellOfst[0]=11 cells (3 PI)
8132 23:22:43.341403 u2DelayCellOfst[1]=18 cells (5 PI)
8133 23:22:43.344942 u2DelayCellOfst[2]=11 cells (3 PI)
8134 23:22:43.348140 u2DelayCellOfst[3]=11 cells (3 PI)
8135 23:22:43.351248 u2DelayCellOfst[4]=7 cells (2 PI)
8136 23:22:43.354691 u2DelayCellOfst[5]=0 cells (0 PI)
8137 23:22:43.358139 u2DelayCellOfst[6]=18 cells (5 PI)
8138 23:22:43.361193 u2DelayCellOfst[7]=18 cells (5 PI)
8139 23:22:43.364707 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8140 23:22:43.367735 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8141 23:22:43.371217 == TX Byte 1 ==
8142 23:22:43.374359 u2DelayCellOfst[8]=0 cells (0 PI)
8143 23:22:43.377829 u2DelayCellOfst[9]=0 cells (0 PI)
8144 23:22:43.380971 u2DelayCellOfst[10]=3 cells (1 PI)
8145 23:22:43.381054 u2DelayCellOfst[11]=0 cells (0 PI)
8146 23:22:43.384425 u2DelayCellOfst[12]=11 cells (3 PI)
8147 23:22:43.387623 u2DelayCellOfst[13]=11 cells (3 PI)
8148 23:22:43.390921 u2DelayCellOfst[14]=11 cells (3 PI)
8149 23:22:43.394211 u2DelayCellOfst[15]=7 cells (2 PI)
8150 23:22:43.400824 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8151 23:22:43.404322 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8152 23:22:43.404406 DramC Write-DBI on
8153 23:22:43.404471 ==
8154 23:22:43.407354 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 23:22:43.414062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 23:22:43.414146 ==
8157 23:22:43.414210
8158 23:22:43.414271
8159 23:22:43.414328 TX Vref Scan disable
8160 23:22:43.418602 == TX Byte 0 ==
8161 23:22:43.421763 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8162 23:22:43.425147 == TX Byte 1 ==
8163 23:22:43.428423 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8164 23:22:43.431700 DramC Write-DBI off
8165 23:22:43.431781
8166 23:22:43.431846 [DATLAT]
8167 23:22:43.431906 Freq=1600, CH0 RK1
8168 23:22:43.431964
8169 23:22:43.434870 DATLAT Default: 0xf
8170 23:22:43.434951 0, 0xFFFF, sum = 0
8171 23:22:43.438212 1, 0xFFFF, sum = 0
8172 23:22:43.441631 2, 0xFFFF, sum = 0
8173 23:22:43.441714 3, 0xFFFF, sum = 0
8174 23:22:43.445061 4, 0xFFFF, sum = 0
8175 23:22:43.445143 5, 0xFFFF, sum = 0
8176 23:22:43.448125 6, 0xFFFF, sum = 0
8177 23:22:43.448206 7, 0xFFFF, sum = 0
8178 23:22:43.451488 8, 0xFFFF, sum = 0
8179 23:22:43.451571 9, 0xFFFF, sum = 0
8180 23:22:43.454833 10, 0xFFFF, sum = 0
8181 23:22:43.454947 11, 0xFFFF, sum = 0
8182 23:22:43.458314 12, 0xFFFF, sum = 0
8183 23:22:43.458396 13, 0xCFFF, sum = 0
8184 23:22:43.461343 14, 0x0, sum = 1
8185 23:22:43.461426 15, 0x0, sum = 2
8186 23:22:43.464761 16, 0x0, sum = 3
8187 23:22:43.464844 17, 0x0, sum = 4
8188 23:22:43.468215 best_step = 15
8189 23:22:43.468296
8190 23:22:43.468361 ==
8191 23:22:43.471385 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 23:22:43.474549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 23:22:43.474632 ==
8194 23:22:43.478060 RX Vref Scan: 0
8195 23:22:43.478142
8196 23:22:43.478207 RX Vref 0 -> 0, step: 1
8197 23:22:43.478268
8198 23:22:43.481422 RX Delay 3 -> 252, step: 4
8199 23:22:43.484448 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8200 23:22:43.491107 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8201 23:22:43.494501 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8202 23:22:43.497953 iDelay=191, Bit 3, Center 120 (63 ~ 178) 116
8203 23:22:43.501200 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8204 23:22:43.504383 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8205 23:22:43.511143 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8206 23:22:43.514691 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8207 23:22:43.517816 iDelay=191, Bit 8, Center 108 (51 ~ 166) 116
8208 23:22:43.521155 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8209 23:22:43.524493 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8210 23:22:43.531157 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8211 23:22:43.534393 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8212 23:22:43.537707 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8213 23:22:43.541057 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8214 23:22:43.547582 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8215 23:22:43.547665 ==
8216 23:22:43.550945 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 23:22:43.554375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 23:22:43.554459 ==
8219 23:22:43.554525 DQS Delay:
8220 23:22:43.557413 DQS0 = 0, DQS1 = 0
8221 23:22:43.557542 DQM Delay:
8222 23:22:43.560779 DQM0 = 124, DQM1 = 117
8223 23:22:43.560860 DQ Delay:
8224 23:22:43.564251 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =120
8225 23:22:43.567425 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8226 23:22:43.570852 DQ8 =108, DQ9 =104, DQ10 =118, DQ11 =112
8227 23:22:43.573930 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8228 23:22:43.574058
8229 23:22:43.574161
8230 23:22:43.577158
8231 23:22:43.577266 [DramC_TX_OE_Calibration] TA2
8232 23:22:43.580640 Original DQ_B0 (3 6) =30, OEN = 27
8233 23:22:43.583983 Original DQ_B1 (3 6) =30, OEN = 27
8234 23:22:43.587184 24, 0x0, End_B0=24 End_B1=24
8235 23:22:43.590422 25, 0x0, End_B0=25 End_B1=25
8236 23:22:43.594031 26, 0x0, End_B0=26 End_B1=26
8237 23:22:43.594137 27, 0x0, End_B0=27 End_B1=27
8238 23:22:43.597102 28, 0x0, End_B0=28 End_B1=28
8239 23:22:43.600512 29, 0x0, End_B0=29 End_B1=29
8240 23:22:43.603902 30, 0x0, End_B0=30 End_B1=30
8241 23:22:43.606931 31, 0x4141, End_B0=30 End_B1=30
8242 23:22:43.607055 Byte0 end_step=30 best_step=27
8243 23:22:43.610113 Byte1 end_step=30 best_step=27
8244 23:22:43.613656 Byte0 TX OE(2T, 0.5T) = (3, 3)
8245 23:22:43.616761 Byte1 TX OE(2T, 0.5T) = (3, 3)
8246 23:22:43.616843
8247 23:22:43.616908
8248 23:22:43.626769 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8249 23:22:43.626852 CH0 RK1: MR19=303, MR18=210E
8250 23:22:43.633314 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8251 23:22:43.636691 [RxdqsGatingPostProcess] freq 1600
8252 23:22:43.643443 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8253 23:22:43.646753 best DQS0 dly(2T, 0.5T) = (1, 1)
8254 23:22:43.649887 best DQS1 dly(2T, 0.5T) = (1, 1)
8255 23:22:43.653319 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8256 23:22:43.653419 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8257 23:22:43.656404 best DQS0 dly(2T, 0.5T) = (1, 1)
8258 23:22:43.659783 best DQS1 dly(2T, 0.5T) = (1, 1)
8259 23:22:43.663432 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8260 23:22:43.666354 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8261 23:22:43.669777 Pre-setting of DQS Precalculation
8262 23:22:43.676203 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8263 23:22:43.676288 ==
8264 23:22:43.679672 Dram Type= 6, Freq= 0, CH_1, rank 0
8265 23:22:43.683136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 23:22:43.683221 ==
8267 23:22:43.689585 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 23:22:43.692808 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 23:22:43.696203 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 23:22:43.702783 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 23:22:43.711386 [CA 0] Center 42 (13~71) winsize 59
8272 23:22:43.714966 [CA 1] Center 42 (13~72) winsize 60
8273 23:22:43.717923 [CA 2] Center 38 (9~67) winsize 59
8274 23:22:43.721438 [CA 3] Center 37 (8~67) winsize 60
8275 23:22:43.724623 [CA 4] Center 37 (8~67) winsize 60
8276 23:22:43.727827 [CA 5] Center 36 (7~66) winsize 60
8277 23:22:43.727930
8278 23:22:43.731310 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8279 23:22:43.731395
8280 23:22:43.734442 [CATrainingPosCal] consider 1 rank data
8281 23:22:43.737937 u2DelayCellTimex100 = 258/100 ps
8282 23:22:43.744696 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8283 23:22:43.747736 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8284 23:22:43.751112 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8285 23:22:43.754298 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
8286 23:22:43.757457 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8287 23:22:43.761085 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8288 23:22:43.761170
8289 23:22:43.764375 CA PerBit enable=1, Macro0, CA PI delay=36
8290 23:22:43.764459
8291 23:22:43.767656 [CBTSetCACLKResult] CA Dly = 36
8292 23:22:43.771054 CS Dly: 9 (0~40)
8293 23:22:43.774244 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 23:22:43.777512 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 23:22:43.777598 ==
8296 23:22:43.781058 Dram Type= 6, Freq= 0, CH_1, rank 1
8297 23:22:43.784136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 23:22:43.787631 ==
8299 23:22:43.790694 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8300 23:22:43.794150 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8301 23:22:43.800641 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8302 23:22:43.807546 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8303 23:22:43.814462 [CA 0] Center 42 (13~71) winsize 59
8304 23:22:43.817978 [CA 1] Center 42 (12~72) winsize 61
8305 23:22:43.821105 [CA 2] Center 38 (9~68) winsize 60
8306 23:22:43.824602 [CA 3] Center 36 (7~66) winsize 60
8307 23:22:43.828097 [CA 4] Center 38 (9~68) winsize 60
8308 23:22:43.831222 [CA 5] Center 37 (7~67) winsize 61
8309 23:22:43.831304
8310 23:22:43.834811 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8311 23:22:43.834893
8312 23:22:43.837978 [CATrainingPosCal] consider 2 rank data
8313 23:22:43.841390 u2DelayCellTimex100 = 258/100 ps
8314 23:22:43.844641 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8315 23:22:43.851145 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8316 23:22:43.854609 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8317 23:22:43.857741 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8318 23:22:43.861284 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8319 23:22:43.864395 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8320 23:22:43.864476
8321 23:22:43.867724 CA PerBit enable=1, Macro0, CA PI delay=36
8322 23:22:43.867805
8323 23:22:43.871053 [CBTSetCACLKResult] CA Dly = 36
8324 23:22:43.874217 CS Dly: 10 (0~43)
8325 23:22:43.877586 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8326 23:22:43.880851 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8327 23:22:43.880932
8328 23:22:43.884359 ----->DramcWriteLeveling(PI) begin...
8329 23:22:43.884441 ==
8330 23:22:43.887598 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 23:22:43.894291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 23:22:43.894370 ==
8333 23:22:43.897864 Write leveling (Byte 0): 25 => 25
8334 23:22:43.897936 Write leveling (Byte 1): 27 => 27
8335 23:22:43.900750 DramcWriteLeveling(PI) end<-----
8336 23:22:43.900826
8337 23:22:43.900888 ==
8338 23:22:43.904188 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 23:22:43.910870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 23:22:43.910954 ==
8341 23:22:43.914007 [Gating] SW mode calibration
8342 23:22:43.920639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8343 23:22:43.924076 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8344 23:22:43.930405 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 23:22:43.933982 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 23:22:43.937162 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 23:22:43.943783 1 4 12 | B1->B0 | 2322 2323 | 1 0 | (1 1) (0 0)
8348 23:22:43.946955 1 4 16 | B1->B0 | 3232 2f2f | 1 0 | (0 0) (0 0)
8349 23:22:43.950172 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 23:22:43.956850 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 23:22:43.960104 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 23:22:43.963688 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 23:22:43.970176 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 23:22:43.973253 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8355 23:22:43.976809 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8356 23:22:43.983311 1 5 16 | B1->B0 | 2727 2626 | 0 0 | (1 0) (1 0)
8357 23:22:43.986312 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 23:22:43.989768 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 23:22:43.996289 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 23:22:43.999640 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 23:22:44.003039 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 23:22:44.009664 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 23:22:44.012950 1 6 12 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
8364 23:22:44.016194 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8365 23:22:44.022869 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 23:22:44.026354 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 23:22:44.029823 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 23:22:44.036060 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 23:22:44.039146 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 23:22:44.042774 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 23:22:44.049308 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 23:22:44.052563 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8373 23:22:44.055774 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 23:22:44.062404 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 23:22:44.065850 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 23:22:44.069289 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 23:22:44.075800 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 23:22:44.078995 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 23:22:44.082424 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 23:22:44.089136 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 23:22:44.092323 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 23:22:44.095661 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 23:22:44.102189 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 23:22:44.105295 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 23:22:44.108634 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 23:22:44.115173 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 23:22:44.118655 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8388 23:22:44.122244 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8389 23:22:44.128762 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8390 23:22:44.128846 Total UI for P1: 0, mck2ui 16
8391 23:22:44.132001 best dqsien dly found for B1: ( 1, 9, 16)
8392 23:22:44.138535 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 23:22:44.141670 Total UI for P1: 0, mck2ui 16
8394 23:22:44.145081 best dqsien dly found for B0: ( 1, 9, 16)
8395 23:22:44.148284 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8396 23:22:44.151815 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8397 23:22:44.151899
8398 23:22:44.154938 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8399 23:22:44.158430 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8400 23:22:44.161695 [Gating] SW calibration Done
8401 23:22:44.161802 ==
8402 23:22:44.165138 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 23:22:44.168338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 23:22:44.171560 ==
8405 23:22:44.171642 RX Vref Scan: 0
8406 23:22:44.171719
8407 23:22:44.174806 RX Vref 0 -> 0, step: 1
8408 23:22:44.174888
8409 23:22:44.174954 RX Delay 0 -> 252, step: 8
8410 23:22:44.181317 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8411 23:22:44.184903 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8412 23:22:44.188188 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8413 23:22:44.191392 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8414 23:22:44.194643 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8415 23:22:44.201438 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8416 23:22:44.204528 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8417 23:22:44.207935 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8418 23:22:44.211082 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8419 23:22:44.217811 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8420 23:22:44.221181 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8421 23:22:44.224631 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8422 23:22:44.227713 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8423 23:22:44.231015 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8424 23:22:44.237607 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8425 23:22:44.240766 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8426 23:22:44.240840 ==
8427 23:22:44.243976 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 23:22:44.247233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 23:22:44.247349 ==
8430 23:22:44.250602 DQS Delay:
8431 23:22:44.250744 DQS0 = 0, DQS1 = 0
8432 23:22:44.250846 DQM Delay:
8433 23:22:44.254179 DQM0 = 132, DQM1 = 125
8434 23:22:44.254292 DQ Delay:
8435 23:22:44.257373 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8436 23:22:44.260996 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8437 23:22:44.267405 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8438 23:22:44.270375 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8439 23:22:44.270454
8440 23:22:44.270517
8441 23:22:44.270575 ==
8442 23:22:44.273832 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 23:22:44.277284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 23:22:44.277366 ==
8445 23:22:44.277431
8446 23:22:44.277531
8447 23:22:44.280706 TX Vref Scan disable
8448 23:22:44.280816 == TX Byte 0 ==
8449 23:22:44.287293 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8450 23:22:44.290375 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8451 23:22:44.293873 == TX Byte 1 ==
8452 23:22:44.296952 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8453 23:22:44.300380 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8454 23:22:44.300479 ==
8455 23:22:44.303915 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 23:22:44.306977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 23:22:44.307059 ==
8458 23:22:44.321958
8459 23:22:44.325506 TX Vref early break, caculate TX vref
8460 23:22:44.328584 TX Vref=16, minBit 13, minWin=21, winSum=364
8461 23:22:44.332308 TX Vref=18, minBit 11, minWin=22, winSum=373
8462 23:22:44.335459 TX Vref=20, minBit 1, minWin=23, winSum=387
8463 23:22:44.338640 TX Vref=22, minBit 11, minWin=23, winSum=397
8464 23:22:44.345377 TX Vref=24, minBit 11, minWin=24, winSum=408
8465 23:22:44.348588 TX Vref=26, minBit 5, minWin=25, winSum=417
8466 23:22:44.351982 TX Vref=28, minBit 1, minWin=25, winSum=422
8467 23:22:44.354969 TX Vref=30, minBit 0, minWin=25, winSum=416
8468 23:22:44.358664 TX Vref=32, minBit 5, minWin=24, winSum=410
8469 23:22:44.361782 TX Vref=34, minBit 9, minWin=23, winSum=403
8470 23:22:44.368452 TX Vref=36, minBit 1, minWin=23, winSum=386
8471 23:22:44.371817 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28
8472 23:22:44.371951
8473 23:22:44.374992 Final TX Range 0 Vref 28
8474 23:22:44.375100
8475 23:22:44.375233 ==
8476 23:22:44.378241 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 23:22:44.381905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 23:22:44.385192 ==
8479 23:22:44.385276
8480 23:22:44.385343
8481 23:22:44.385404 TX Vref Scan disable
8482 23:22:44.391921 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8483 23:22:44.392054 == TX Byte 0 ==
8484 23:22:44.394968 u2DelayCellOfst[0]=18 cells (5 PI)
8485 23:22:44.398162 u2DelayCellOfst[1]=11 cells (3 PI)
8486 23:22:44.401578 u2DelayCellOfst[2]=0 cells (0 PI)
8487 23:22:44.405089 u2DelayCellOfst[3]=7 cells (2 PI)
8488 23:22:44.408510 u2DelayCellOfst[4]=11 cells (3 PI)
8489 23:22:44.411574 u2DelayCellOfst[5]=18 cells (5 PI)
8490 23:22:44.415076 u2DelayCellOfst[6]=22 cells (6 PI)
8491 23:22:44.418196 u2DelayCellOfst[7]=7 cells (2 PI)
8492 23:22:44.421746 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8493 23:22:44.424884 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8494 23:22:44.428356 == TX Byte 1 ==
8495 23:22:44.431673 u2DelayCellOfst[8]=0 cells (0 PI)
8496 23:22:44.434841 u2DelayCellOfst[9]=7 cells (2 PI)
8497 23:22:44.438144 u2DelayCellOfst[10]=15 cells (4 PI)
8498 23:22:44.441214 u2DelayCellOfst[11]=11 cells (3 PI)
8499 23:22:44.444675 u2DelayCellOfst[12]=18 cells (5 PI)
8500 23:22:44.448142 u2DelayCellOfst[13]=22 cells (6 PI)
8501 23:22:44.448215 u2DelayCellOfst[14]=22 cells (6 PI)
8502 23:22:44.451351 u2DelayCellOfst[15]=22 cells (6 PI)
8503 23:22:44.458047 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8504 23:22:44.461147 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8505 23:22:44.461254 DramC Write-DBI on
8506 23:22:44.464568 ==
8507 23:22:44.468122 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 23:22:44.471284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 23:22:44.471390 ==
8510 23:22:44.471497
8511 23:22:44.471587
8512 23:22:44.474586 TX Vref Scan disable
8513 23:22:44.474691 == TX Byte 0 ==
8514 23:22:44.481548 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8515 23:22:44.481629 == TX Byte 1 ==
8516 23:22:44.484618 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8517 23:22:44.487733 DramC Write-DBI off
8518 23:22:44.487834
8519 23:22:44.487940 [DATLAT]
8520 23:22:44.491381 Freq=1600, CH1 RK0
8521 23:22:44.491492
8522 23:22:44.491590 DATLAT Default: 0xf
8523 23:22:44.494594 0, 0xFFFF, sum = 0
8524 23:22:44.494671 1, 0xFFFF, sum = 0
8525 23:22:44.497843 2, 0xFFFF, sum = 0
8526 23:22:44.497916 3, 0xFFFF, sum = 0
8527 23:22:44.501249 4, 0xFFFF, sum = 0
8528 23:22:44.501350 5, 0xFFFF, sum = 0
8529 23:22:44.504536 6, 0xFFFF, sum = 0
8530 23:22:44.504643 7, 0xFFFF, sum = 0
8531 23:22:44.507823 8, 0xFFFF, sum = 0
8532 23:22:44.507925 9, 0xFFFF, sum = 0
8533 23:22:44.511280 10, 0xFFFF, sum = 0
8534 23:22:44.514555 11, 0xFFFF, sum = 0
8535 23:22:44.514637 12, 0xFFFF, sum = 0
8536 23:22:44.517755 13, 0x8FFF, sum = 0
8537 23:22:44.517829 14, 0x0, sum = 1
8538 23:22:44.521019 15, 0x0, sum = 2
8539 23:22:44.521123 16, 0x0, sum = 3
8540 23:22:44.524216 17, 0x0, sum = 4
8541 23:22:44.524324 best_step = 15
8542 23:22:44.524426
8543 23:22:44.524518 ==
8544 23:22:44.527774 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 23:22:44.531052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 23:22:44.531129 ==
8547 23:22:44.534126 RX Vref Scan: 1
8548 23:22:44.534238
8549 23:22:44.537597 Set Vref Range= 24 -> 127
8550 23:22:44.537698
8551 23:22:44.537796 RX Vref 24 -> 127, step: 1
8552 23:22:44.540881
8553 23:22:44.540957 RX Delay 11 -> 252, step: 4
8554 23:22:44.541028
8555 23:22:44.544147 Set Vref, RX VrefLevel [Byte0]: 24
8556 23:22:44.547453 [Byte1]: 24
8557 23:22:44.551204
8558 23:22:44.551288 Set Vref, RX VrefLevel [Byte0]: 25
8559 23:22:44.554250 [Byte1]: 25
8560 23:22:44.558587
8561 23:22:44.558671 Set Vref, RX VrefLevel [Byte0]: 26
8562 23:22:44.562041 [Byte1]: 26
8563 23:22:44.566224
8564 23:22:44.566338 Set Vref, RX VrefLevel [Byte0]: 27
8565 23:22:44.569577 [Byte1]: 27
8566 23:22:44.573905
8567 23:22:44.573998 Set Vref, RX VrefLevel [Byte0]: 28
8568 23:22:44.577020 [Byte1]: 28
8569 23:22:44.581399
8570 23:22:44.581528 Set Vref, RX VrefLevel [Byte0]: 29
8571 23:22:44.584554 [Byte1]: 29
8572 23:22:44.589169
8573 23:22:44.589272 Set Vref, RX VrefLevel [Byte0]: 30
8574 23:22:44.592411 [Byte1]: 30
8575 23:22:44.596852
8576 23:22:44.596977 Set Vref, RX VrefLevel [Byte0]: 31
8577 23:22:44.599827 [Byte1]: 31
8578 23:22:44.604094
8579 23:22:44.604168 Set Vref, RX VrefLevel [Byte0]: 32
8580 23:22:44.607744 [Byte1]: 32
8581 23:22:44.611993
8582 23:22:44.612062 Set Vref, RX VrefLevel [Byte0]: 33
8583 23:22:44.615057 [Byte1]: 33
8584 23:22:44.619414
8585 23:22:44.619527 Set Vref, RX VrefLevel [Byte0]: 34
8586 23:22:44.622899 [Byte1]: 34
8587 23:22:44.627137
8588 23:22:44.627210 Set Vref, RX VrefLevel [Byte0]: 35
8589 23:22:44.630591 [Byte1]: 35
8590 23:22:44.635079
8591 23:22:44.635187 Set Vref, RX VrefLevel [Byte0]: 36
8592 23:22:44.638123 [Byte1]: 36
8593 23:22:44.642553
8594 23:22:44.642657 Set Vref, RX VrefLevel [Byte0]: 37
8595 23:22:44.645473 [Byte1]: 37
8596 23:22:44.649937
8597 23:22:44.650047 Set Vref, RX VrefLevel [Byte0]: 38
8598 23:22:44.653248 [Byte1]: 38
8599 23:22:44.657631
8600 23:22:44.657718 Set Vref, RX VrefLevel [Byte0]: 39
8601 23:22:44.660677 [Byte1]: 39
8602 23:22:44.665194
8603 23:22:44.665310 Set Vref, RX VrefLevel [Byte0]: 40
8604 23:22:44.668276 [Byte1]: 40
8605 23:22:44.672976
8606 23:22:44.673051 Set Vref, RX VrefLevel [Byte0]: 41
8607 23:22:44.676020 [Byte1]: 41
8608 23:22:44.680164
8609 23:22:44.680271 Set Vref, RX VrefLevel [Byte0]: 42
8610 23:22:44.683614 [Byte1]: 42
8611 23:22:44.687996
8612 23:22:44.688078 Set Vref, RX VrefLevel [Byte0]: 43
8613 23:22:44.691084 [Byte1]: 43
8614 23:22:44.695409
8615 23:22:44.695505 Set Vref, RX VrefLevel [Byte0]: 44
8616 23:22:44.698963 [Byte1]: 44
8617 23:22:44.703177
8618 23:22:44.703256 Set Vref, RX VrefLevel [Byte0]: 45
8619 23:22:44.706342 [Byte1]: 45
8620 23:22:44.710959
8621 23:22:44.711067 Set Vref, RX VrefLevel [Byte0]: 46
8622 23:22:44.714047 [Byte1]: 46
8623 23:22:44.718293
8624 23:22:44.718376 Set Vref, RX VrefLevel [Byte0]: 47
8625 23:22:44.721799 [Byte1]: 47
8626 23:22:44.726124
8627 23:22:44.726200 Set Vref, RX VrefLevel [Byte0]: 48
8628 23:22:44.729228 [Byte1]: 48
8629 23:22:44.733590
8630 23:22:44.733679 Set Vref, RX VrefLevel [Byte0]: 49
8631 23:22:44.737040 [Byte1]: 49
8632 23:22:44.741302
8633 23:22:44.741410 Set Vref, RX VrefLevel [Byte0]: 50
8634 23:22:44.744784 [Byte1]: 50
8635 23:22:44.749114
8636 23:22:44.749202 Set Vref, RX VrefLevel [Byte0]: 51
8637 23:22:44.752331 [Byte1]: 51
8638 23:22:44.756698
8639 23:22:44.756814 Set Vref, RX VrefLevel [Byte0]: 52
8640 23:22:44.760040 [Byte1]: 52
8641 23:22:44.764198
8642 23:22:44.764284 Set Vref, RX VrefLevel [Byte0]: 53
8643 23:22:44.767475 [Byte1]: 53
8644 23:22:44.771715
8645 23:22:44.771828 Set Vref, RX VrefLevel [Byte0]: 54
8646 23:22:44.775034 [Byte1]: 54
8647 23:22:44.779446
8648 23:22:44.779529 Set Vref, RX VrefLevel [Byte0]: 55
8649 23:22:44.782723 [Byte1]: 55
8650 23:22:44.786960
8651 23:22:44.787071 Set Vref, RX VrefLevel [Byte0]: 56
8652 23:22:44.790302 [Byte1]: 56
8653 23:22:44.794752
8654 23:22:44.794835 Set Vref, RX VrefLevel [Byte0]: 57
8655 23:22:44.797737 [Byte1]: 57
8656 23:22:44.802068
8657 23:22:44.802154 Set Vref, RX VrefLevel [Byte0]: 58
8658 23:22:44.805664 [Byte1]: 58
8659 23:22:44.809935
8660 23:22:44.810020 Set Vref, RX VrefLevel [Byte0]: 59
8661 23:22:44.813118 [Byte1]: 59
8662 23:22:44.817255
8663 23:22:44.817368 Set Vref, RX VrefLevel [Byte0]: 60
8664 23:22:44.820590 [Byte1]: 60
8665 23:22:44.824809
8666 23:22:44.824900 Set Vref, RX VrefLevel [Byte0]: 61
8667 23:22:44.828410 [Byte1]: 61
8668 23:22:44.832751
8669 23:22:44.832837 Set Vref, RX VrefLevel [Byte0]: 62
8670 23:22:44.835904 [Byte1]: 62
8671 23:22:44.840255
8672 23:22:44.840339 Set Vref, RX VrefLevel [Byte0]: 63
8673 23:22:44.843750 [Byte1]: 63
8674 23:22:44.847730
8675 23:22:44.847815 Set Vref, RX VrefLevel [Byte0]: 64
8676 23:22:44.851330 [Byte1]: 64
8677 23:22:44.855606
8678 23:22:44.855693 Set Vref, RX VrefLevel [Byte0]: 65
8679 23:22:44.858651 [Byte1]: 65
8680 23:22:44.863065
8681 23:22:44.863151 Set Vref, RX VrefLevel [Byte0]: 66
8682 23:22:44.866398 [Byte1]: 66
8683 23:22:44.870614
8684 23:22:44.870717 Set Vref, RX VrefLevel [Byte0]: 67
8685 23:22:44.873991 [Byte1]: 67
8686 23:22:44.878369
8687 23:22:44.878480 Set Vref, RX VrefLevel [Byte0]: 68
8688 23:22:44.881517 [Byte1]: 68
8689 23:22:44.886117
8690 23:22:44.886200 Set Vref, RX VrefLevel [Byte0]: 69
8691 23:22:44.889210 [Byte1]: 69
8692 23:22:44.893552
8693 23:22:44.893660 Set Vref, RX VrefLevel [Byte0]: 70
8694 23:22:44.899871 [Byte1]: 70
8695 23:22:44.899956
8696 23:22:44.903225 Set Vref, RX VrefLevel [Byte0]: 71
8697 23:22:44.906564 [Byte1]: 71
8698 23:22:44.906649
8699 23:22:44.910024 Final RX Vref Byte 0 = 58 to rank0
8700 23:22:44.913179 Final RX Vref Byte 1 = 56 to rank0
8701 23:22:44.916431 Final RX Vref Byte 0 = 58 to rank1
8702 23:22:44.919743 Final RX Vref Byte 1 = 56 to rank1==
8703 23:22:44.923098 Dram Type= 6, Freq= 0, CH_1, rank 0
8704 23:22:44.926135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8705 23:22:44.926220 ==
8706 23:22:44.929675 DQS Delay:
8707 23:22:44.929765 DQS0 = 0, DQS1 = 0
8708 23:22:44.929832 DQM Delay:
8709 23:22:44.932806 DQM0 = 131, DQM1 = 123
8710 23:22:44.932915 DQ Delay:
8711 23:22:44.936334 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8712 23:22:44.939558 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8713 23:22:44.946297 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8714 23:22:44.949618 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8715 23:22:44.949702
8716 23:22:44.949769
8717 23:22:44.949830
8718 23:22:44.952664 [DramC_TX_OE_Calibration] TA2
8719 23:22:44.956145 Original DQ_B0 (3 6) =30, OEN = 27
8720 23:22:44.959739 Original DQ_B1 (3 6) =30, OEN = 27
8721 23:22:44.959829 24, 0x0, End_B0=24 End_B1=24
8722 23:22:44.962912 25, 0x0, End_B0=25 End_B1=25
8723 23:22:44.965981 26, 0x0, End_B0=26 End_B1=26
8724 23:22:44.969393 27, 0x0, End_B0=27 End_B1=27
8725 23:22:44.969512 28, 0x0, End_B0=28 End_B1=28
8726 23:22:44.972559 29, 0x0, End_B0=29 End_B1=29
8727 23:22:44.975995 30, 0x0, End_B0=30 End_B1=30
8728 23:22:44.979392 31, 0x4141, End_B0=30 End_B1=30
8729 23:22:44.982882 Byte0 end_step=30 best_step=27
8730 23:22:44.986017 Byte1 end_step=30 best_step=27
8731 23:22:44.986130 Byte0 TX OE(2T, 0.5T) = (3, 3)
8732 23:22:44.989085 Byte1 TX OE(2T, 0.5T) = (3, 3)
8733 23:22:44.989170
8734 23:22:44.989235
8735 23:22:44.998877 [DQSOSCAuto] RK0, (LSB)MR18= 0x60b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
8736 23:22:45.002335 CH1 RK0: MR19=303, MR18=60B
8737 23:22:45.005707 CH1_RK0: MR19=0x303, MR18=0x60B, DQSOSC=404, MR23=63, INC=22, DEC=15
8738 23:22:45.005815
8739 23:22:45.012189 ----->DramcWriteLeveling(PI) begin...
8740 23:22:45.012299 ==
8741 23:22:45.015511 Dram Type= 6, Freq= 0, CH_1, rank 1
8742 23:22:45.018688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 23:22:45.018789 ==
8744 23:22:45.022144 Write leveling (Byte 0): 25 => 25
8745 23:22:45.025569 Write leveling (Byte 1): 25 => 25
8746 23:22:45.028719 DramcWriteLeveling(PI) end<-----
8747 23:22:45.028802
8748 23:22:45.028868 ==
8749 23:22:45.031932 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 23:22:45.035279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 23:22:45.035390 ==
8752 23:22:45.038643 [Gating] SW mode calibration
8753 23:22:45.045211 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8754 23:22:45.051885 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8755 23:22:45.055089 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 23:22:45.058650 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 23:22:45.064995 1 4 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8758 23:22:45.068485 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8759 23:22:45.071651 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 23:22:45.078341 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 23:22:45.081631 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 23:22:45.084724 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 23:22:45.091464 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 23:22:45.094598 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 23:22:45.097739 1 5 8 | B1->B0 | 3333 2a2a | 1 0 | (1 0) (0 0)
8766 23:22:45.104683 1 5 12 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
8767 23:22:45.107882 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 23:22:45.111322 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 23:22:45.117862 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 23:22:45.121223 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 23:22:45.124659 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 23:22:45.131020 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8773 23:22:45.134640 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8774 23:22:45.137795 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8775 23:22:45.144515 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 23:22:45.147679 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 23:22:45.150867 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 23:22:45.157690 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 23:22:45.160882 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 23:22:45.164023 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 23:22:45.170612 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8782 23:22:45.173947 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8783 23:22:45.177084 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 23:22:45.183738 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 23:22:45.187364 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 23:22:45.190811 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 23:22:45.197302 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 23:22:45.200815 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 23:22:45.203670 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 23:22:45.210598 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 23:22:45.213543 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 23:22:45.216970 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 23:22:45.220352 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 23:22:45.226767 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 23:22:45.230284 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 23:22:45.233377 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 23:22:45.240064 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8798 23:22:45.243346 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8799 23:22:45.246740 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8800 23:22:45.250137 Total UI for P1: 0, mck2ui 16
8801 23:22:45.253689 best dqsien dly found for B0: ( 1, 9, 10)
8802 23:22:45.260200 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 23:22:45.263429 Total UI for P1: 0, mck2ui 16
8804 23:22:45.266757 best dqsien dly found for B1: ( 1, 9, 12)
8805 23:22:45.269865 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8806 23:22:45.273453 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8807 23:22:45.273551
8808 23:22:45.276542 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8809 23:22:45.279646 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8810 23:22:45.282970 [Gating] SW calibration Done
8811 23:22:45.283058 ==
8812 23:22:45.286592 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 23:22:45.289758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 23:22:45.289834 ==
8815 23:22:45.292874 RX Vref Scan: 0
8816 23:22:45.292948
8817 23:22:45.295988 RX Vref 0 -> 0, step: 1
8818 23:22:45.296061
8819 23:22:45.296123 RX Delay 0 -> 252, step: 8
8820 23:22:45.302749 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8821 23:22:45.305885 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8822 23:22:45.309262 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8823 23:22:45.312683 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8824 23:22:45.316081 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8825 23:22:45.322845 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8826 23:22:45.325826 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8827 23:22:45.329207 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8828 23:22:45.332538 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8829 23:22:45.335988 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8830 23:22:45.342556 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8831 23:22:45.345698 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8832 23:22:45.348781 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8833 23:22:45.352410 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8834 23:22:45.358713 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8835 23:22:45.362240 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8836 23:22:45.362346 ==
8837 23:22:45.365512 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 23:22:45.368766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 23:22:45.368844 ==
8840 23:22:45.372458 DQS Delay:
8841 23:22:45.372533 DQS0 = 0, DQS1 = 0
8842 23:22:45.372595 DQM Delay:
8843 23:22:45.375643 DQM0 = 129, DQM1 = 128
8844 23:22:45.375717 DQ Delay:
8845 23:22:45.378913 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =127
8846 23:22:45.382422 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8847 23:22:45.385354 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8848 23:22:45.391997 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =139
8849 23:22:45.392077
8850 23:22:45.392142
8851 23:22:45.392203 ==
8852 23:22:45.395178 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 23:22:45.398655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 23:22:45.398733 ==
8855 23:22:45.398800
8856 23:22:45.398860
8857 23:22:45.401728 TX Vref Scan disable
8858 23:22:45.401833 == TX Byte 0 ==
8859 23:22:45.408400 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8860 23:22:45.411740 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8861 23:22:45.411822 == TX Byte 1 ==
8862 23:22:45.418166 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8863 23:22:45.421631 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8864 23:22:45.421735 ==
8865 23:22:45.424819 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 23:22:45.428373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 23:22:45.431449 ==
8868 23:22:45.443297
8869 23:22:45.446744 TX Vref early break, caculate TX vref
8870 23:22:45.450246 TX Vref=16, minBit 0, minWin=23, winSum=386
8871 23:22:45.453647 TX Vref=18, minBit 0, minWin=23, winSum=396
8872 23:22:45.456743 TX Vref=20, minBit 0, minWin=24, winSum=406
8873 23:22:45.460266 TX Vref=22, minBit 0, minWin=25, winSum=415
8874 23:22:45.463321 TX Vref=24, minBit 0, minWin=24, winSum=420
8875 23:22:45.470135 TX Vref=26, minBit 5, minWin=25, winSum=430
8876 23:22:45.473350 TX Vref=28, minBit 5, minWin=25, winSum=428
8877 23:22:45.476653 TX Vref=30, minBit 1, minWin=25, winSum=426
8878 23:22:45.480154 TX Vref=32, minBit 5, minWin=24, winSum=413
8879 23:22:45.483414 TX Vref=34, minBit 1, minWin=23, winSum=410
8880 23:22:45.486714 TX Vref=36, minBit 5, minWin=23, winSum=399
8881 23:22:45.493344 [TxChooseVref] Worse bit 5, Min win 25, Win sum 430, Final Vref 26
8882 23:22:45.493435
8883 23:22:45.496589 Final TX Range 0 Vref 26
8884 23:22:45.496672
8885 23:22:45.496760 ==
8886 23:22:45.500062 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 23:22:45.503445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 23:22:45.503561 ==
8889 23:22:45.503627
8890 23:22:45.503687
8891 23:22:45.506774 TX Vref Scan disable
8892 23:22:45.513245 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8893 23:22:45.513357 == TX Byte 0 ==
8894 23:22:45.516327 u2DelayCellOfst[0]=18 cells (5 PI)
8895 23:22:45.519767 u2DelayCellOfst[1]=15 cells (4 PI)
8896 23:22:45.523038 u2DelayCellOfst[2]=0 cells (0 PI)
8897 23:22:45.526379 u2DelayCellOfst[3]=7 cells (2 PI)
8898 23:22:45.529867 u2DelayCellOfst[4]=7 cells (2 PI)
8899 23:22:45.532909 u2DelayCellOfst[5]=18 cells (5 PI)
8900 23:22:45.536384 u2DelayCellOfst[6]=18 cells (5 PI)
8901 23:22:45.539578 u2DelayCellOfst[7]=7 cells (2 PI)
8902 23:22:45.543069 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8903 23:22:45.546418 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8904 23:22:45.549726 == TX Byte 1 ==
8905 23:22:45.553239 u2DelayCellOfst[8]=0 cells (0 PI)
8906 23:22:45.553321 u2DelayCellOfst[9]=7 cells (2 PI)
8907 23:22:45.556356 u2DelayCellOfst[10]=15 cells (4 PI)
8908 23:22:45.559676 u2DelayCellOfst[11]=7 cells (2 PI)
8909 23:22:45.563117 u2DelayCellOfst[12]=15 cells (4 PI)
8910 23:22:45.566365 u2DelayCellOfst[13]=18 cells (5 PI)
8911 23:22:45.569486 u2DelayCellOfst[14]=22 cells (6 PI)
8912 23:22:45.572933 u2DelayCellOfst[15]=18 cells (5 PI)
8913 23:22:45.576232 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8914 23:22:45.583075 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8915 23:22:45.583186 DramC Write-DBI on
8916 23:22:45.583288 ==
8917 23:22:45.586017 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 23:22:45.592677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 23:22:45.592763 ==
8920 23:22:45.592829
8921 23:22:45.592890
8922 23:22:45.592949 TX Vref Scan disable
8923 23:22:45.596682 == TX Byte 0 ==
8924 23:22:45.599850 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8925 23:22:45.603334 == TX Byte 1 ==
8926 23:22:45.606576 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8927 23:22:45.609709 DramC Write-DBI off
8928 23:22:45.609808
8929 23:22:45.609875 [DATLAT]
8930 23:22:45.609936 Freq=1600, CH1 RK1
8931 23:22:45.609996
8932 23:22:45.613241 DATLAT Default: 0xf
8933 23:22:45.616309 0, 0xFFFF, sum = 0
8934 23:22:45.616393 1, 0xFFFF, sum = 0
8935 23:22:45.619829 2, 0xFFFF, sum = 0
8936 23:22:45.619913 3, 0xFFFF, sum = 0
8937 23:22:45.622952 4, 0xFFFF, sum = 0
8938 23:22:45.623036 5, 0xFFFF, sum = 0
8939 23:22:45.626164 6, 0xFFFF, sum = 0
8940 23:22:45.626279 7, 0xFFFF, sum = 0
8941 23:22:45.629714 8, 0xFFFF, sum = 0
8942 23:22:45.629825 9, 0xFFFF, sum = 0
8943 23:22:45.633074 10, 0xFFFF, sum = 0
8944 23:22:45.633157 11, 0xFFFF, sum = 0
8945 23:22:45.636050 12, 0xFFFF, sum = 0
8946 23:22:45.636162 13, 0x8FFF, sum = 0
8947 23:22:45.639396 14, 0x0, sum = 1
8948 23:22:45.639509 15, 0x0, sum = 2
8949 23:22:45.642833 16, 0x0, sum = 3
8950 23:22:45.642916 17, 0x0, sum = 4
8951 23:22:45.645947 best_step = 15
8952 23:22:45.646030
8953 23:22:45.646095 ==
8954 23:22:45.649297 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 23:22:45.652371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 23:22:45.652455 ==
8957 23:22:45.655795 RX Vref Scan: 0
8958 23:22:45.655905
8959 23:22:45.655999 RX Vref 0 -> 0, step: 1
8960 23:22:45.656091
8961 23:22:45.659043 RX Delay 3 -> 252, step: 4
8962 23:22:45.665994 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8963 23:22:45.669043 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8964 23:22:45.672230 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8965 23:22:45.675823 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8966 23:22:45.678825 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8967 23:22:45.685835 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8968 23:22:45.689039 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8969 23:22:45.691993 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8970 23:22:45.695590 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8971 23:22:45.698543 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8972 23:22:45.705539 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8973 23:22:45.708555 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8974 23:22:45.712120 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8975 23:22:45.715120 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8976 23:22:45.721978 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8977 23:22:45.725322 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8978 23:22:45.725428 ==
8979 23:22:45.728577 Dram Type= 6, Freq= 0, CH_1, rank 1
8980 23:22:45.731836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8981 23:22:45.731925 ==
8982 23:22:45.732012 DQS Delay:
8983 23:22:45.734896 DQS0 = 0, DQS1 = 0
8984 23:22:45.734979 DQM Delay:
8985 23:22:45.738393 DQM0 = 127, DQM1 = 124
8986 23:22:45.738478 DQ Delay:
8987 23:22:45.741846 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =126
8988 23:22:45.745052 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
8989 23:22:45.748420 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =120
8990 23:22:45.754919 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =134
8991 23:22:45.755005
8992 23:22:45.755071
8993 23:22:45.755131
8994 23:22:45.758174 [DramC_TX_OE_Calibration] TA2
8995 23:22:45.758258 Original DQ_B0 (3 6) =30, OEN = 27
8996 23:22:45.761523 Original DQ_B1 (3 6) =30, OEN = 27
8997 23:22:45.765204 24, 0x0, End_B0=24 End_B1=24
8998 23:22:45.768400 25, 0x0, End_B0=25 End_B1=25
8999 23:22:45.771551 26, 0x0, End_B0=26 End_B1=26
9000 23:22:45.771656 27, 0x0, End_B0=27 End_B1=27
9001 23:22:45.774889 28, 0x0, End_B0=28 End_B1=28
9002 23:22:45.778237 29, 0x0, End_B0=29 End_B1=29
9003 23:22:45.781462 30, 0x0, End_B0=30 End_B1=30
9004 23:22:45.784661 31, 0x4141, End_B0=30 End_B1=30
9005 23:22:45.787815 Byte0 end_step=30 best_step=27
9006 23:22:45.787899 Byte1 end_step=30 best_step=27
9007 23:22:45.791204 Byte0 TX OE(2T, 0.5T) = (3, 3)
9008 23:22:45.794398 Byte1 TX OE(2T, 0.5T) = (3, 3)
9009 23:22:45.794480
9010 23:22:45.794545
9011 23:22:45.804444 [DQSOSCAuto] RK1, (LSB)MR18= 0xd19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 403 ps
9012 23:22:45.804528 CH1 RK1: MR19=303, MR18=D19
9013 23:22:45.811107 CH1_RK1: MR19=0x303, MR18=0xD19, DQSOSC=397, MR23=63, INC=23, DEC=15
9014 23:22:45.814326 [RxdqsGatingPostProcess] freq 1600
9015 23:22:45.820895 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9016 23:22:45.824482 best DQS0 dly(2T, 0.5T) = (1, 1)
9017 23:22:45.827618 best DQS1 dly(2T, 0.5T) = (1, 1)
9018 23:22:45.830866 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9019 23:22:45.834596 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9020 23:22:45.834678 best DQS0 dly(2T, 0.5T) = (1, 1)
9021 23:22:45.837747 best DQS1 dly(2T, 0.5T) = (1, 1)
9022 23:22:45.840869 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9023 23:22:45.844159 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9024 23:22:45.847503 Pre-setting of DQS Precalculation
9025 23:22:45.854216 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9026 23:22:45.860874 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9027 23:22:45.867291 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9028 23:22:45.867378
9029 23:22:45.867444
9030 23:22:45.870531 [Calibration Summary] 3200 Mbps
9031 23:22:45.870614 CH 0, Rank 0
9032 23:22:45.873912 SW Impedance : PASS
9033 23:22:45.877004 DUTY Scan : NO K
9034 23:22:45.877090 ZQ Calibration : PASS
9035 23:22:45.880408 Jitter Meter : NO K
9036 23:22:45.883763 CBT Training : PASS
9037 23:22:45.883844 Write leveling : PASS
9038 23:22:45.886805 RX DQS gating : PASS
9039 23:22:45.890272 RX DQ/DQS(RDDQC) : PASS
9040 23:22:45.890378 TX DQ/DQS : PASS
9041 23:22:45.893409 RX DATLAT : PASS
9042 23:22:45.897052 RX DQ/DQS(Engine): PASS
9043 23:22:45.897132 TX OE : PASS
9044 23:22:45.900380 All Pass.
9045 23:22:45.900460
9046 23:22:45.900523 CH 0, Rank 1
9047 23:22:45.903633 SW Impedance : PASS
9048 23:22:45.903714 DUTY Scan : NO K
9049 23:22:45.906857 ZQ Calibration : PASS
9050 23:22:45.910050 Jitter Meter : NO K
9051 23:22:45.910185 CBT Training : PASS
9052 23:22:45.913306 Write leveling : PASS
9053 23:22:45.916696 RX DQS gating : PASS
9054 23:22:45.916772 RX DQ/DQS(RDDQC) : PASS
9055 23:22:45.919770 TX DQ/DQS : PASS
9056 23:22:45.923279 RX DATLAT : PASS
9057 23:22:45.923360 RX DQ/DQS(Engine): PASS
9058 23:22:45.926403 TX OE : PASS
9059 23:22:45.926491 All Pass.
9060 23:22:45.926559
9061 23:22:45.929604 CH 1, Rank 0
9062 23:22:45.929752 SW Impedance : PASS
9063 23:22:45.933148 DUTY Scan : NO K
9064 23:22:45.933270 ZQ Calibration : PASS
9065 23:22:45.936608 Jitter Meter : NO K
9066 23:22:45.939710 CBT Training : PASS
9067 23:22:45.939793 Write leveling : PASS
9068 23:22:45.943200 RX DQS gating : PASS
9069 23:22:45.946340 RX DQ/DQS(RDDQC) : PASS
9070 23:22:45.946420 TX DQ/DQS : PASS
9071 23:22:45.949693 RX DATLAT : PASS
9072 23:22:45.952752 RX DQ/DQS(Engine): PASS
9073 23:22:45.952848 TX OE : PASS
9074 23:22:45.956014 All Pass.
9075 23:22:45.956091
9076 23:22:45.956154 CH 1, Rank 1
9077 23:22:45.959521 SW Impedance : PASS
9078 23:22:45.959605 DUTY Scan : NO K
9079 23:22:45.962636 ZQ Calibration : PASS
9080 23:22:45.966057 Jitter Meter : NO K
9081 23:22:45.966140 CBT Training : PASS
9082 23:22:45.969261 Write leveling : PASS
9083 23:22:45.972839 RX DQS gating : PASS
9084 23:22:45.973003 RX DQ/DQS(RDDQC) : PASS
9085 23:22:45.975796 TX DQ/DQS : PASS
9086 23:22:45.979311 RX DATLAT : PASS
9087 23:22:45.979393 RX DQ/DQS(Engine): PASS
9088 23:22:45.982640 TX OE : PASS
9089 23:22:45.982718 All Pass.
9090 23:22:45.982810
9091 23:22:45.985800 DramC Write-DBI on
9092 23:22:45.989259 PER_BANK_REFRESH: Hybrid Mode
9093 23:22:45.989361 TX_TRACKING: ON
9094 23:22:45.999073 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9095 23:22:46.005738 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9096 23:22:46.012194 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9097 23:22:46.015513 [FAST_K] Save calibration result to emmc
9098 23:22:46.018648 sync common calibartion params.
9099 23:22:46.021962 sync cbt_mode0:1, 1:1
9100 23:22:46.025337 dram_init: ddr_geometry: 2
9101 23:22:46.025447 dram_init: ddr_geometry: 2
9102 23:22:46.028942 dram_init: ddr_geometry: 2
9103 23:22:46.032256 0:dram_rank_size:100000000
9104 23:22:46.035524 1:dram_rank_size:100000000
9105 23:22:46.038864 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9106 23:22:46.042154 DFS_SHUFFLE_HW_MODE: ON
9107 23:22:46.045489 dramc_set_vcore_voltage set vcore to 725000
9108 23:22:46.048955 Read voltage for 1600, 0
9109 23:22:46.049040 Vio18 = 0
9110 23:22:46.049106 Vcore = 725000
9111 23:22:46.051978 Vdram = 0
9112 23:22:46.052065 Vddq = 0
9113 23:22:46.052132 Vmddr = 0
9114 23:22:46.055631 switch to 3200 Mbps bootup
9115 23:22:46.058620 [DramcRunTimeConfig]
9116 23:22:46.058708 PHYPLL
9117 23:22:46.058776 DPM_CONTROL_AFTERK: ON
9118 23:22:46.062120 PER_BANK_REFRESH: ON
9119 23:22:46.065380 REFRESH_OVERHEAD_REDUCTION: ON
9120 23:22:46.065499 CMD_PICG_NEW_MODE: OFF
9121 23:22:46.068476 XRTWTW_NEW_MODE: ON
9122 23:22:46.072074 XRTRTR_NEW_MODE: ON
9123 23:22:46.072184 TX_TRACKING: ON
9124 23:22:46.075329 RDSEL_TRACKING: OFF
9125 23:22:46.075407 DQS Precalculation for DVFS: ON
9126 23:22:46.078708 RX_TRACKING: OFF
9127 23:22:46.078784 HW_GATING DBG: ON
9128 23:22:46.081826 ZQCS_ENABLE_LP4: ON
9129 23:22:46.081926 RX_PICG_NEW_MODE: ON
9130 23:22:46.085232 TX_PICG_NEW_MODE: ON
9131 23:22:46.088727 ENABLE_RX_DCM_DPHY: ON
9132 23:22:46.092076 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9133 23:22:46.092161 DUMMY_READ_FOR_TRACKING: OFF
9134 23:22:46.095190 !!! SPM_CONTROL_AFTERK: OFF
9135 23:22:46.098438 !!! SPM could not control APHY
9136 23:22:46.101820 IMPEDANCE_TRACKING: ON
9137 23:22:46.101903 TEMP_SENSOR: ON
9138 23:22:46.105355 HW_SAVE_FOR_SR: OFF
9139 23:22:46.105465 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9140 23:22:46.111717 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9141 23:22:46.111831 Read ODT Tracking: ON
9142 23:22:46.114995 Refresh Rate DeBounce: ON
9143 23:22:46.115081 DFS_NO_QUEUE_FLUSH: ON
9144 23:22:46.118484 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9145 23:22:46.121595 ENABLE_DFS_RUNTIME_MRW: OFF
9146 23:22:46.124812 DDR_RESERVE_NEW_MODE: ON
9147 23:22:46.128038 MR_CBT_SWITCH_FREQ: ON
9148 23:22:46.128123 =========================
9149 23:22:46.147789 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9150 23:22:46.150847 dram_init: ddr_geometry: 2
9151 23:22:46.169268 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9152 23:22:46.172675 dram_init: dram init end (result: 0)
9153 23:22:46.179438 DRAM-K: Full calibration passed in 24534 msecs
9154 23:22:46.182482 MRC: failed to locate region type 0.
9155 23:22:46.182598 DRAM rank0 size:0x100000000,
9156 23:22:46.185659 DRAM rank1 size=0x100000000
9157 23:22:46.196026 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9158 23:22:46.202364 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9159 23:22:46.209027 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9160 23:22:46.215839 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9161 23:22:46.219064 DRAM rank0 size:0x100000000,
9162 23:22:46.222110 DRAM rank1 size=0x100000000
9163 23:22:46.222194 CBMEM:
9164 23:22:46.225687 IMD: root @ 0xfffff000 254 entries.
9165 23:22:46.228837 IMD: root @ 0xffffec00 62 entries.
9166 23:22:46.232281 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9167 23:22:46.238762 WARNING: RO_VPD is uninitialized or empty.
9168 23:22:46.241954 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9169 23:22:46.249319 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9170 23:22:46.261950 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9171 23:22:46.273430 BS: romstage times (exec / console): total (unknown) / 24007 ms
9172 23:22:46.273572
9173 23:22:46.273687
9174 23:22:46.283656 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9175 23:22:46.286776 ARM64: Exception handlers installed.
9176 23:22:46.290209 ARM64: Testing exception
9177 23:22:46.293484 ARM64: Done test exception
9178 23:22:46.293568 Enumerating buses...
9179 23:22:46.296704 Show all devs... Before device enumeration.
9180 23:22:46.299944 Root Device: enabled 1
9181 23:22:46.303086 CPU_CLUSTER: 0: enabled 1
9182 23:22:46.303173 CPU: 00: enabled 1
9183 23:22:46.306534 Compare with tree...
9184 23:22:46.306619 Root Device: enabled 1
9185 23:22:46.309752 CPU_CLUSTER: 0: enabled 1
9186 23:22:46.313372 CPU: 00: enabled 1
9187 23:22:46.313458 Root Device scanning...
9188 23:22:46.316341 scan_static_bus for Root Device
9189 23:22:46.319858 CPU_CLUSTER: 0 enabled
9190 23:22:46.323062 scan_static_bus for Root Device done
9191 23:22:46.326403 scan_bus: bus Root Device finished in 8 msecs
9192 23:22:46.326490 done
9193 23:22:46.333180 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9194 23:22:46.336152 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9195 23:22:46.343043 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9196 23:22:46.346157 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9197 23:22:46.349520 Allocating resources...
9198 23:22:46.353104 Reading resources...
9199 23:22:46.356141 Root Device read_resources bus 0 link: 0
9200 23:22:46.356256 DRAM rank0 size:0x100000000,
9201 23:22:46.359750 DRAM rank1 size=0x100000000
9202 23:22:46.362924 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9203 23:22:46.366047 CPU: 00 missing read_resources
9204 23:22:46.372873 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9205 23:22:46.375998 Root Device read_resources bus 0 link: 0 done
9206 23:22:46.376084 Done reading resources.
9207 23:22:46.382616 Show resources in subtree (Root Device)...After reading.
9208 23:22:46.386198 Root Device child on link 0 CPU_CLUSTER: 0
9209 23:22:46.389276 CPU_CLUSTER: 0 child on link 0 CPU: 00
9210 23:22:46.399189 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9211 23:22:46.399301 CPU: 00
9212 23:22:46.402681 Root Device assign_resources, bus 0 link: 0
9213 23:22:46.406031 CPU_CLUSTER: 0 missing set_resources
9214 23:22:46.412627 Root Device assign_resources, bus 0 link: 0 done
9215 23:22:46.412763 Done setting resources.
9216 23:22:46.419063 Show resources in subtree (Root Device)...After assigning values.
9217 23:22:46.422322 Root Device child on link 0 CPU_CLUSTER: 0
9218 23:22:46.425918 CPU_CLUSTER: 0 child on link 0 CPU: 00
9219 23:22:46.435597 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9220 23:22:46.435691 CPU: 00
9221 23:22:46.439031 Done allocating resources.
9222 23:22:46.445517 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9223 23:22:46.445620 Enabling resources...
9224 23:22:46.445686 done.
9225 23:22:46.452332 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9226 23:22:46.452436 Initializing devices...
9227 23:22:46.455487 Root Device init
9228 23:22:46.455570 init hardware done!
9229 23:22:46.458828 0x00000018: ctrlr->caps
9230 23:22:46.462178 52.000 MHz: ctrlr->f_max
9231 23:22:46.462265 0.400 MHz: ctrlr->f_min
9232 23:22:46.465368 0x40ff8080: ctrlr->voltages
9233 23:22:46.468745 sclk: 390625
9234 23:22:46.468831 Bus Width = 1
9235 23:22:46.468897 sclk: 390625
9236 23:22:46.472253 Bus Width = 1
9237 23:22:46.472336 Early init status = 3
9238 23:22:46.478957 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9239 23:22:46.482149 in-header: 03 fc 00 00 01 00 00 00
9240 23:22:46.485317 in-data: 00
9241 23:22:46.488553 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9242 23:22:46.493306 in-header: 03 fd 00 00 00 00 00 00
9243 23:22:46.496551 in-data:
9244 23:22:46.499661 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9245 23:22:46.504188 in-header: 03 fc 00 00 01 00 00 00
9246 23:22:46.507361 in-data: 00
9247 23:22:46.510679 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9248 23:22:46.516104 in-header: 03 fd 00 00 00 00 00 00
9249 23:22:46.519599 in-data:
9250 23:22:46.522670 [SSUSB] Setting up USB HOST controller...
9251 23:22:46.526298 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9252 23:22:46.529315 [SSUSB] phy power-on done.
9253 23:22:46.532934 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9254 23:22:46.539237 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9255 23:22:46.542704 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9256 23:22:46.549557 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9257 23:22:46.555985 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9258 23:22:46.562674 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9259 23:22:46.569170 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9260 23:22:46.575983 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9261 23:22:46.579343 SPM: binary array size = 0x9dc
9262 23:22:46.582425 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9263 23:22:46.589131 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9264 23:22:46.595660 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9265 23:22:46.602399 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9266 23:22:46.605403 configure_display: Starting display init
9267 23:22:46.639581 anx7625_power_on_init: Init interface.
9268 23:22:46.643040 anx7625_disable_pd_protocol: Disabled PD feature.
9269 23:22:46.646126 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9270 23:22:46.673950 anx7625_start_dp_work: Secure OCM version=00
9271 23:22:46.677129 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9272 23:22:46.692000 sp_tx_get_edid_block: EDID Block = 1
9273 23:22:46.794725 Extracted contents:
9274 23:22:46.797859 header: 00 ff ff ff ff ff ff 00
9275 23:22:46.801306 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9276 23:22:46.804486 version: 01 04
9277 23:22:46.807956 basic params: 95 1f 11 78 0a
9278 23:22:46.811094 chroma info: 76 90 94 55 54 90 27 21 50 54
9279 23:22:46.814506 established: 00 00 00
9280 23:22:46.821338 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9281 23:22:46.824682 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9282 23:22:46.830955 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9283 23:22:46.837612 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9284 23:22:46.844295 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9285 23:22:46.847387 extensions: 00
9286 23:22:46.847473 checksum: fb
9287 23:22:46.847539
9288 23:22:46.850822 Manufacturer: IVO Model 57d Serial Number 0
9289 23:22:46.854003 Made week 0 of 2020
9290 23:22:46.854089 EDID version: 1.4
9291 23:22:46.857254 Digital display
9292 23:22:46.860702 6 bits per primary color channel
9293 23:22:46.860791 DisplayPort interface
9294 23:22:46.864002 Maximum image size: 31 cm x 17 cm
9295 23:22:46.867227 Gamma: 220%
9296 23:22:46.867311 Check DPMS levels
9297 23:22:46.870725 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9298 23:22:46.877323 First detailed timing is preferred timing
9299 23:22:46.877454 Established timings supported:
9300 23:22:46.880461 Standard timings supported:
9301 23:22:46.883567 Detailed timings
9302 23:22:46.887094 Hex of detail: 383680a07038204018303c0035ae10000019
9303 23:22:46.893650 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9304 23:22:46.896758 0780 0798 07c8 0820 hborder 0
9305 23:22:46.900336 0438 043b 0447 0458 vborder 0
9306 23:22:46.903323 -hsync -vsync
9307 23:22:46.903410 Did detailed timing
9308 23:22:46.910126 Hex of detail: 000000000000000000000000000000000000
9309 23:22:46.913261 Manufacturer-specified data, tag 0
9310 23:22:46.916843 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9311 23:22:46.919936 ASCII string: InfoVision
9312 23:22:46.923371 Hex of detail: 000000fe00523134304e574635205248200a
9313 23:22:46.926469 ASCII string: R140NWF5 RH
9314 23:22:46.926572 Checksum
9315 23:22:46.929883 Checksum: 0xfb (valid)
9316 23:22:46.933231 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9317 23:22:46.936380 DSI data_rate: 832800000 bps
9318 23:22:46.943091 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9319 23:22:46.946529 anx7625_parse_edid: pixelclock(138800).
9320 23:22:46.949734 hactive(1920), hsync(48), hfp(24), hbp(88)
9321 23:22:46.953113 vactive(1080), vsync(12), vfp(3), vbp(17)
9322 23:22:46.956259 anx7625_dsi_config: config dsi.
9323 23:22:46.963135 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9324 23:22:46.976675 anx7625_dsi_config: success to config DSI
9325 23:22:46.980089 anx7625_dp_start: MIPI phy setup OK.
9326 23:22:46.983237 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9327 23:22:46.986614 mtk_ddp_mode_set invalid vrefresh 60
9328 23:22:46.989894 main_disp_path_setup
9329 23:22:46.989978 ovl_layer_smi_id_en
9330 23:22:46.992962 ovl_layer_smi_id_en
9331 23:22:46.993043 ccorr_config
9332 23:22:46.993107 aal_config
9333 23:22:46.996568 gamma_config
9334 23:22:46.996677 postmask_config
9335 23:22:46.999880 dither_config
9336 23:22:47.002978 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9337 23:22:47.009455 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9338 23:22:47.012814 Root Device init finished in 554 msecs
9339 23:22:47.016355 CPU_CLUSTER: 0 init
9340 23:22:47.022787 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9341 23:22:47.029547 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9342 23:22:47.029633 APU_MBOX 0x190000b0 = 0x10001
9343 23:22:47.032943 APU_MBOX 0x190001b0 = 0x10001
9344 23:22:47.035985 APU_MBOX 0x190005b0 = 0x10001
9345 23:22:47.039492 APU_MBOX 0x190006b0 = 0x10001
9346 23:22:47.045987 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9347 23:22:47.055661 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9348 23:22:47.068195 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9349 23:22:47.074658 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9350 23:22:47.086329 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9351 23:22:47.095511 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9352 23:22:47.098602 CPU_CLUSTER: 0 init finished in 81 msecs
9353 23:22:47.101810 Devices initialized
9354 23:22:47.105024 Show all devs... After init.
9355 23:22:47.105107 Root Device: enabled 1
9356 23:22:47.108512 CPU_CLUSTER: 0: enabled 1
9357 23:22:47.111958 CPU: 00: enabled 1
9358 23:22:47.115117 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9359 23:22:47.118642 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9360 23:22:47.121723 ELOG: NV offset 0x57f000 size 0x1000
9361 23:22:47.128658 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9362 23:22:47.135159 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9363 23:22:47.138518 ELOG: Event(17) added with size 13 at 2024-04-03 23:22:48 UTC
9364 23:22:47.144836 out: cmd=0x121: 03 db 21 01 00 00 00 00
9365 23:22:47.148381 in-header: 03 82 00 00 2c 00 00 00
9366 23:22:47.158539 in-data: dd 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9367 23:22:47.164820 ELOG: Event(A1) added with size 10 at 2024-04-03 23:22:48 UTC
9368 23:22:47.171613 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9369 23:22:47.178066 ELOG: Event(A0) added with size 9 at 2024-04-03 23:22:48 UTC
9370 23:22:47.181617 elog_add_boot_reason: Logged dev mode boot
9371 23:22:47.184948 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9372 23:22:47.188213 Finalize devices...
9373 23:22:47.191599 Devices finalized
9374 23:22:47.194807 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9375 23:22:47.198053 Writing coreboot table at 0xffe64000
9376 23:22:47.201338 0. 000000000010a000-0000000000113fff: RAMSTAGE
9377 23:22:47.204657 1. 0000000040000000-00000000400fffff: RAM
9378 23:22:47.211308 2. 0000000040100000-000000004032afff: RAMSTAGE
9379 23:22:47.214733 3. 000000004032b000-00000000545fffff: RAM
9380 23:22:47.217812 4. 0000000054600000-000000005465ffff: BL31
9381 23:22:47.221204 5. 0000000054660000-00000000ffe63fff: RAM
9382 23:22:47.227770 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9383 23:22:47.231264 7. 0000000100000000-000000023fffffff: RAM
9384 23:22:47.234527 Passing 5 GPIOs to payload:
9385 23:22:47.237698 NAME | PORT | POLARITY | VALUE
9386 23:22:47.241025 EC in RW | 0x000000aa | low | undefined
9387 23:22:47.247598 EC interrupt | 0x00000005 | low | undefined
9388 23:22:47.250923 TPM interrupt | 0x000000ab | high | undefined
9389 23:22:47.257740 SD card detect | 0x00000011 | high | undefined
9390 23:22:47.260884 speaker enable | 0x00000093 | high | undefined
9391 23:22:47.264006 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9392 23:22:47.267498 in-header: 03 f9 00 00 02 00 00 00
9393 23:22:47.270864 in-data: 02 00
9394 23:22:47.274149 ADC[4]: Raw value=895191 ID=7
9395 23:22:47.274254 ADC[3]: Raw value=212700 ID=1
9396 23:22:47.277305 RAM Code: 0x71
9397 23:22:47.280777 ADC[6]: Raw value=74722 ID=0
9398 23:22:47.280875 ADC[5]: Raw value=211590 ID=1
9399 23:22:47.284074 SKU Code: 0x1
9400 23:22:47.287226 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 84da
9401 23:22:47.290611 coreboot table: 964 bytes.
9402 23:22:47.294040 IMD ROOT 0. 0xfffff000 0x00001000
9403 23:22:47.297256 IMD SMALL 1. 0xffffe000 0x00001000
9404 23:22:47.300393 RO MCACHE 2. 0xffffc000 0x00001104
9405 23:22:47.303860 CONSOLE 3. 0xfff7c000 0x00080000
9406 23:22:47.307225 FMAP 4. 0xfff7b000 0x00000452
9407 23:22:47.310377 TIME STAMP 5. 0xfff7a000 0x00000910
9408 23:22:47.313601 VBOOT WORK 6. 0xfff66000 0x00014000
9409 23:22:47.317098 RAMOOPS 7. 0xffe66000 0x00100000
9410 23:22:47.320260 COREBOOT 8. 0xffe64000 0x00002000
9411 23:22:47.323711 IMD small region:
9412 23:22:47.326886 IMD ROOT 0. 0xffffec00 0x00000400
9413 23:22:47.330313 VPD 1. 0xffffeb80 0x0000006c
9414 23:22:47.333563 MMC STATUS 2. 0xffffeb60 0x00000004
9415 23:22:47.336638 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9416 23:22:47.340093 Probing TPM: done!
9417 23:22:47.343747 Connected to device vid:did:rid of 1ae0:0028:00
9418 23:22:47.354336 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9419 23:22:47.357656 Initialized TPM device CR50 revision 0
9420 23:22:47.361183 Checking cr50 for pending updates
9421 23:22:47.365098 Reading cr50 TPM mode
9422 23:22:47.373765 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9423 23:22:47.380525 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9424 23:22:47.420654 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9425 23:22:47.423733 Checking segment from ROM address 0x40100000
9426 23:22:47.427107 Checking segment from ROM address 0x4010001c
9427 23:22:47.433962 Loading segment from ROM address 0x40100000
9428 23:22:47.434043 code (compression=0)
9429 23:22:47.443605 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9430 23:22:47.450603 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9431 23:22:47.450733 it's not compressed!
9432 23:22:47.457304 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9433 23:22:47.460460 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9434 23:22:47.480962 Loading segment from ROM address 0x4010001c
9435 23:22:47.481090 Entry Point 0x80000000
9436 23:22:47.484252 Loaded segments
9437 23:22:47.487496 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9438 23:22:47.493988 Jumping to boot code at 0x80000000(0xffe64000)
9439 23:22:47.500859 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9440 23:22:47.507265 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9441 23:22:47.515564 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9442 23:22:47.518549 Checking segment from ROM address 0x40100000
9443 23:22:47.522010 Checking segment from ROM address 0x4010001c
9444 23:22:47.528678 Loading segment from ROM address 0x40100000
9445 23:22:47.528756 code (compression=1)
9446 23:22:47.535381 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9447 23:22:47.545374 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9448 23:22:47.545493 using LZMA
9449 23:22:47.553762 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9450 23:22:47.560288 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9451 23:22:47.563505 Loading segment from ROM address 0x4010001c
9452 23:22:47.563609 Entry Point 0x54601000
9453 23:22:47.567023 Loaded segments
9454 23:22:47.570154 NOTICE: MT8192 bl31_setup
9455 23:22:47.577272 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9456 23:22:47.580495 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9457 23:22:47.584081 WARNING: region 0:
9458 23:22:47.587125 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 23:22:47.587200 WARNING: region 1:
9460 23:22:47.594033 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9461 23:22:47.597352 WARNING: region 2:
9462 23:22:47.600699 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9463 23:22:47.603807 WARNING: region 3:
9464 23:22:47.607267 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9465 23:22:47.610799 WARNING: region 4:
9466 23:22:47.617090 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9467 23:22:47.617206 WARNING: region 5:
9468 23:22:47.620605 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 23:22:47.623894 WARNING: region 6:
9470 23:22:47.627048 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 23:22:47.630553 WARNING: region 7:
9472 23:22:47.633680 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 23:22:47.640511 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9474 23:22:47.643755 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9475 23:22:47.647316 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9476 23:22:47.653864 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9477 23:22:47.657116 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9478 23:22:47.660522 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9479 23:22:47.667182 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9480 23:22:47.670678 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9481 23:22:47.676989 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9482 23:22:47.680541 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9483 23:22:47.683657 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9484 23:22:47.690308 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9485 23:22:47.693542 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9486 23:22:47.697013 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9487 23:22:47.703783 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9488 23:22:47.706819 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9489 23:22:47.713570 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9490 23:22:47.716818 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9491 23:22:47.720183 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9492 23:22:47.726684 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9493 23:22:47.730329 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9494 23:22:47.733605 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9495 23:22:47.740209 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9496 23:22:47.743728 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9497 23:22:47.750536 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9498 23:22:47.753670 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9499 23:22:47.756857 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9500 23:22:47.763535 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9501 23:22:47.766898 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9502 23:22:47.773550 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9503 23:22:47.777178 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9504 23:22:47.780344 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9505 23:22:47.786837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9506 23:22:47.790217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9507 23:22:47.793485 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9508 23:22:47.797014 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9509 23:22:47.803714 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9510 23:22:47.806825 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9511 23:22:47.810180 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9512 23:22:47.813386 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9513 23:22:47.820274 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9514 23:22:47.823433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9515 23:22:47.826803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9516 23:22:47.830239 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9517 23:22:47.836897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9518 23:22:47.840276 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9519 23:22:47.843430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9520 23:22:47.846709 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9521 23:22:47.853288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9522 23:22:47.856605 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9523 23:22:47.863586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9524 23:22:47.866758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9525 23:22:47.873469 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9526 23:22:47.876570 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9527 23:22:47.880063 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9528 23:22:47.886823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9529 23:22:47.889970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9530 23:22:47.896508 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9531 23:22:47.899825 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9532 23:22:47.906538 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9533 23:22:47.909877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9534 23:22:47.913579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9535 23:22:47.920350 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9536 23:22:47.923184 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9537 23:22:47.929870 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9538 23:22:47.933515 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9539 23:22:47.940013 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9540 23:22:47.943598 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9541 23:22:47.946815 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9542 23:22:47.953550 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9543 23:22:47.956722 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9544 23:22:47.963492 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9545 23:22:47.966806 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9546 23:22:47.973480 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9547 23:22:47.976758 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9548 23:22:47.979926 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9549 23:22:47.986741 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9550 23:22:47.990158 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9551 23:22:47.997010 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9552 23:22:48.000131 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9553 23:22:48.006960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9554 23:22:48.010184 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9555 23:22:48.016824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9556 23:22:48.020208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9557 23:22:48.023364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9558 23:22:48.029978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9559 23:22:48.033304 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9560 23:22:48.040020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9561 23:22:48.043518 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9562 23:22:48.046821 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9563 23:22:48.053742 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9564 23:22:48.056837 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9565 23:22:48.063474 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9566 23:22:48.066934 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9567 23:22:48.073652 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9568 23:22:48.076854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9569 23:22:48.080155 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9570 23:22:48.086742 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9571 23:22:48.090101 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9572 23:22:48.093722 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9573 23:22:48.096783 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9574 23:22:48.103349 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9575 23:22:48.106618 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9576 23:22:48.113194 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9577 23:22:48.116809 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9578 23:22:48.119981 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9579 23:22:48.126639 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9580 23:22:48.129670 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9581 23:22:48.136344 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9582 23:22:48.139690 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9583 23:22:48.142993 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9584 23:22:48.149849 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9585 23:22:48.153184 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9586 23:22:48.159545 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9587 23:22:48.162907 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9588 23:22:48.166415 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9589 23:22:48.172944 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9590 23:22:48.176359 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9591 23:22:48.179501 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9592 23:22:48.186276 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9593 23:22:48.189366 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9594 23:22:48.192660 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9595 23:22:48.195932 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9596 23:22:48.202538 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9597 23:22:48.206170 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9598 23:22:48.209393 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9599 23:22:48.215737 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9600 23:22:48.219244 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9601 23:22:48.225910 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9602 23:22:48.229536 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9603 23:22:48.232661 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9604 23:22:48.239275 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9605 23:22:48.242811 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9606 23:22:48.249070 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9607 23:22:48.252525 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9608 23:22:48.255878 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9609 23:22:48.262684 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9610 23:22:48.266003 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9611 23:22:48.269140 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9612 23:22:48.275962 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9613 23:22:48.279301 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9614 23:22:48.285857 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9615 23:22:48.289219 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9616 23:22:48.292575 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9617 23:22:48.298888 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9618 23:22:48.302363 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9619 23:22:48.308958 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9620 23:22:48.312403 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9621 23:22:48.315599 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9622 23:22:48.322241 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9623 23:22:48.325340 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9624 23:22:48.332056 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9625 23:22:48.335659 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9626 23:22:48.338761 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9627 23:22:48.345659 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9628 23:22:48.348806 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9629 23:22:48.355346 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9630 23:22:48.358919 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9631 23:22:48.362025 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9632 23:22:48.368660 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9633 23:22:48.372047 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9634 23:22:48.378571 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9635 23:22:48.381982 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9636 23:22:48.385239 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9637 23:22:48.392085 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9638 23:22:48.395255 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9639 23:22:48.398689 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9640 23:22:48.405201 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9641 23:22:48.408649 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9642 23:22:48.415000 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9643 23:22:48.418595 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9644 23:22:48.421760 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9645 23:22:48.428291 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9646 23:22:48.431716 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9647 23:22:48.438295 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9648 23:22:48.441500 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9649 23:22:48.444880 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9650 23:22:48.451585 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9651 23:22:48.454703 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9652 23:22:48.461368 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9653 23:22:48.464652 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9654 23:22:48.468123 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9655 23:22:48.474489 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9656 23:22:48.477968 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9657 23:22:48.484590 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9658 23:22:48.487690 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9659 23:22:48.491232 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9660 23:22:48.497831 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9661 23:22:48.501186 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9662 23:22:48.507613 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9663 23:22:48.513444 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9664 23:22:48.517718 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9665 23:22:48.521094 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9666 23:22:48.524330 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9667 23:22:48.531213 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9668 23:22:48.534309 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9669 23:22:48.540854 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9670 23:22:48.544344 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9671 23:22:48.547421 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9672 23:22:48.554324 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9673 23:22:48.557425 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9674 23:22:48.564097 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9675 23:22:48.567603 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9676 23:22:48.574256 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9677 23:22:48.577136 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9678 23:22:48.580649 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9679 23:22:48.587130 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9680 23:22:48.590727 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9681 23:22:48.597238 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9682 23:22:48.600764 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9683 23:22:48.603894 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9684 23:22:48.610664 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9685 23:22:48.613704 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9686 23:22:48.620550 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9687 23:22:48.623651 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9688 23:22:48.627049 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9689 23:22:48.633759 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9690 23:22:48.637105 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9691 23:22:48.643561 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9692 23:22:48.647130 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9693 23:22:48.653670 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9694 23:22:48.657034 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9695 23:22:48.660201 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9696 23:22:48.666864 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9697 23:22:48.670339 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9698 23:22:48.676739 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9699 23:22:48.680246 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9700 23:22:48.686903 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9701 23:22:48.690405 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9702 23:22:48.693649 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9703 23:22:48.696831 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9704 23:22:48.703363 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9705 23:22:48.706935 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9706 23:22:48.709953 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9707 23:22:48.713319 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9708 23:22:48.719935 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9709 23:22:48.723690 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9710 23:22:48.729783 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9711 23:22:48.733348 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9712 23:22:48.736406 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9713 23:22:48.743280 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9714 23:22:48.746773 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9715 23:22:48.749725 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9716 23:22:48.756341 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9717 23:22:48.759847 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9718 23:22:48.766400 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9719 23:22:48.769706 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9720 23:22:48.773180 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9721 23:22:48.779463 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9722 23:22:48.782899 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9723 23:22:48.786040 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9724 23:22:48.792601 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9725 23:22:48.796123 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9726 23:22:48.799265 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9727 23:22:48.805902 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9728 23:22:48.809093 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9729 23:22:48.815756 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9730 23:22:48.819233 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9731 23:22:48.822354 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9732 23:22:48.829077 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9733 23:22:48.832578 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9734 23:22:48.839062 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9735 23:22:48.842221 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9736 23:22:48.845756 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9737 23:22:48.852284 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9738 23:22:48.855454 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9739 23:22:48.858899 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9740 23:22:48.865557 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9741 23:22:48.868484 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9742 23:22:48.871986 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9743 23:22:48.875136 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9744 23:22:48.881952 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9745 23:22:48.885267 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9746 23:22:48.888347 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9747 23:22:48.891632 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9748 23:22:48.898388 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9749 23:22:48.901651 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9750 23:22:48.904762 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9751 23:22:48.908394 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9752 23:22:48.915024 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9753 23:22:48.918128 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9754 23:22:48.921214 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9755 23:22:48.928219 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9756 23:22:48.931374 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9757 23:22:48.937911 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9758 23:22:48.941101 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9759 23:22:48.947628 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9760 23:22:48.950993 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9761 23:22:48.954381 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9762 23:22:48.961216 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9763 23:22:48.964388 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9764 23:22:48.971086 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9765 23:22:48.974722 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9766 23:22:48.977846 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9767 23:22:48.984522 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9768 23:22:48.987446 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9769 23:22:48.994364 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9770 23:22:48.997301 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9771 23:22:49.000759 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9772 23:22:49.007406 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9773 23:22:49.010737 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9774 23:22:49.017493 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9775 23:22:49.020671 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9776 23:22:49.027059 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9777 23:22:49.030263 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9778 23:22:49.033499 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9779 23:22:49.040089 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9780 23:22:49.043737 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9781 23:22:49.050221 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9782 23:22:49.053282 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9783 23:22:49.060285 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9784 23:22:49.063306 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9785 23:22:49.066664 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9786 23:22:49.073309 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9787 23:22:49.076657 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9788 23:22:49.082973 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9789 23:22:49.086478 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9790 23:22:49.089582 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9791 23:22:49.096307 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9792 23:22:49.099530 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9793 23:22:49.106171 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9794 23:22:49.109427 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9795 23:22:49.112607 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9796 23:22:49.119455 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9797 23:22:49.122762 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9798 23:22:49.129370 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9799 23:22:49.132561 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9800 23:22:49.139305 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9801 23:22:49.142761 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9802 23:22:49.145937 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9803 23:22:49.152578 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9804 23:22:49.155663 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9805 23:22:49.162256 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9806 23:22:49.165704 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9807 23:22:49.169204 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9808 23:22:49.175616 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9809 23:22:49.179059 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9810 23:22:49.185692 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9811 23:22:49.189056 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9812 23:22:49.192092 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9813 23:22:49.198856 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9814 23:22:49.202299 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9815 23:22:49.208740 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9816 23:22:49.211898 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9817 23:22:49.218653 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9818 23:22:49.222187 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9819 23:22:49.225321 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9820 23:22:49.231705 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9821 23:22:49.235160 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9822 23:22:49.241754 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9823 23:22:49.244924 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9824 23:22:49.251738 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9825 23:22:49.254765 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9826 23:22:49.258370 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9827 23:22:49.264798 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9828 23:22:49.268285 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9829 23:22:49.274785 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9830 23:22:49.277737 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9831 23:22:49.284776 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9832 23:22:49.287892 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9833 23:22:49.294601 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9834 23:22:49.297982 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9835 23:22:49.301150 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9836 23:22:49.308026 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9837 23:22:49.310950 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9838 23:22:49.317546 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9839 23:22:49.320805 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9840 23:22:49.327680 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9841 23:22:49.330716 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9842 23:22:49.334143 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9843 23:22:49.340766 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9844 23:22:49.343836 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9845 23:22:49.350687 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9846 23:22:49.353851 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9847 23:22:49.360515 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9848 23:22:49.363638 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9849 23:22:49.370242 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9850 23:22:49.373675 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9851 23:22:49.376697 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9852 23:22:49.383626 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9853 23:22:49.386743 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9854 23:22:49.393465 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9855 23:22:49.396964 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9856 23:22:49.403527 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9857 23:22:49.407031 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9858 23:22:49.410405 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9859 23:22:49.416504 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9860 23:22:49.420405 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9861 23:22:49.426672 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9862 23:22:49.429774 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9863 23:22:49.436550 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9864 23:22:49.439718 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9865 23:22:49.446400 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9866 23:22:49.449787 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9867 23:22:49.453055 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9868 23:22:49.459759 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9869 23:22:49.462804 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9870 23:22:49.469346 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9871 23:22:49.472939 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9872 23:22:49.479460 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9873 23:22:49.482788 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9874 23:22:49.489341 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9875 23:22:49.492770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9876 23:22:49.495904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9877 23:22:49.502496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9878 23:22:49.505720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9879 23:22:49.512663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9880 23:22:49.515730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9881 23:22:49.522419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9882 23:22:49.525757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9883 23:22:49.532582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9884 23:22:49.535642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9885 23:22:49.542378 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9886 23:22:49.545676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9887 23:22:49.551964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9888 23:22:49.555348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9889 23:22:49.561983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9890 23:22:49.565084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9891 23:22:49.571666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9892 23:22:49.574981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9893 23:22:49.581609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9894 23:22:49.585114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9895 23:22:49.591758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9896 23:22:49.594952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9897 23:22:49.601724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9898 23:22:49.604895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9899 23:22:49.611659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9900 23:22:49.615150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9901 23:22:49.621714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9902 23:22:49.624874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9903 23:22:49.631389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9904 23:22:49.634769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9905 23:22:49.641369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9906 23:22:49.644708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9907 23:22:49.648548 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9908 23:22:49.651404 INFO: [APUAPC] vio 0
9909 23:22:49.658004 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9910 23:22:49.661184 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9911 23:22:49.664713 INFO: [APUAPC] D0_APC_0: 0x400510
9912 23:22:49.667752 INFO: [APUAPC] D0_APC_1: 0x0
9913 23:22:49.671047 INFO: [APUAPC] D0_APC_2: 0x1540
9914 23:22:49.674316 INFO: [APUAPC] D0_APC_3: 0x0
9915 23:22:49.677675 INFO: [APUAPC] D1_APC_0: 0xffffffff
9916 23:22:49.681092 INFO: [APUAPC] D1_APC_1: 0xffffffff
9917 23:22:49.684212 INFO: [APUAPC] D1_APC_2: 0x3fffff
9918 23:22:49.687641 INFO: [APUAPC] D1_APC_3: 0x0
9919 23:22:49.691064 INFO: [APUAPC] D2_APC_0: 0xffffffff
9920 23:22:49.694414 INFO: [APUAPC] D2_APC_1: 0xffffffff
9921 23:22:49.697345 INFO: [APUAPC] D2_APC_2: 0x3fffff
9922 23:22:49.700963 INFO: [APUAPC] D2_APC_3: 0x0
9923 23:22:49.704093 INFO: [APUAPC] D3_APC_0: 0xffffffff
9924 23:22:49.707546 INFO: [APUAPC] D3_APC_1: 0xffffffff
9925 23:22:49.710749 INFO: [APUAPC] D3_APC_2: 0x3fffff
9926 23:22:49.710855 INFO: [APUAPC] D3_APC_3: 0x0
9927 23:22:49.716993 INFO: [APUAPC] D4_APC_0: 0xffffffff
9928 23:22:49.720614 INFO: [APUAPC] D4_APC_1: 0xffffffff
9929 23:22:49.723666 INFO: [APUAPC] D4_APC_2: 0x3fffff
9930 23:22:49.723768 INFO: [APUAPC] D4_APC_3: 0x0
9931 23:22:49.727080 INFO: [APUAPC] D5_APC_0: 0xffffffff
9932 23:22:49.733608 INFO: [APUAPC] D5_APC_1: 0xffffffff
9933 23:22:49.733715 INFO: [APUAPC] D5_APC_2: 0x3fffff
9934 23:22:49.737091 INFO: [APUAPC] D5_APC_3: 0x0
9935 23:22:49.740224 INFO: [APUAPC] D6_APC_0: 0xffffffff
9936 23:22:49.743560 INFO: [APUAPC] D6_APC_1: 0xffffffff
9937 23:22:49.747209 INFO: [APUAPC] D6_APC_2: 0x3fffff
9938 23:22:49.750480 INFO: [APUAPC] D6_APC_3: 0x0
9939 23:22:49.753531 INFO: [APUAPC] D7_APC_0: 0xffffffff
9940 23:22:49.756771 INFO: [APUAPC] D7_APC_1: 0xffffffff
9941 23:22:49.760065 INFO: [APUAPC] D7_APC_2: 0x3fffff
9942 23:22:49.763590 INFO: [APUAPC] D7_APC_3: 0x0
9943 23:22:49.766689 INFO: [APUAPC] D8_APC_0: 0xffffffff
9944 23:22:49.770182 INFO: [APUAPC] D8_APC_1: 0xffffffff
9945 23:22:49.773456 INFO: [APUAPC] D8_APC_2: 0x3fffff
9946 23:22:49.776527 INFO: [APUAPC] D8_APC_3: 0x0
9947 23:22:49.779946 INFO: [APUAPC] D9_APC_0: 0xffffffff
9948 23:22:49.783212 INFO: [APUAPC] D9_APC_1: 0xffffffff
9949 23:22:49.786615 INFO: [APUAPC] D9_APC_2: 0x3fffff
9950 23:22:49.790061 INFO: [APUAPC] D9_APC_3: 0x0
9951 23:22:49.793264 INFO: [APUAPC] D10_APC_0: 0xffffffff
9952 23:22:49.796580 INFO: [APUAPC] D10_APC_1: 0xffffffff
9953 23:22:49.799652 INFO: [APUAPC] D10_APC_2: 0x3fffff
9954 23:22:49.803111 INFO: [APUAPC] D10_APC_3: 0x0
9955 23:22:49.806542 INFO: [APUAPC] D11_APC_0: 0xffffffff
9956 23:22:49.809829 INFO: [APUAPC] D11_APC_1: 0xffffffff
9957 23:22:49.813088 INFO: [APUAPC] D11_APC_2: 0x3fffff
9958 23:22:49.816341 INFO: [APUAPC] D11_APC_3: 0x0
9959 23:22:49.819607 INFO: [APUAPC] D12_APC_0: 0xffffffff
9960 23:22:49.823137 INFO: [APUAPC] D12_APC_1: 0xffffffff
9961 23:22:49.826281 INFO: [APUAPC] D12_APC_2: 0x3fffff
9962 23:22:49.829361 INFO: [APUAPC] D12_APC_3: 0x0
9963 23:22:49.832823 INFO: [APUAPC] D13_APC_0: 0xffffffff
9964 23:22:49.836444 INFO: [APUAPC] D13_APC_1: 0xffffffff
9965 23:22:49.839609 INFO: [APUAPC] D13_APC_2: 0x3fffff
9966 23:22:49.842821 INFO: [APUAPC] D13_APC_3: 0x0
9967 23:22:49.845921 INFO: [APUAPC] D14_APC_0: 0xffffffff
9968 23:22:49.849430 INFO: [APUAPC] D14_APC_1: 0xffffffff
9969 23:22:49.852478 INFO: [APUAPC] D14_APC_2: 0x3fffff
9970 23:22:49.855956 INFO: [APUAPC] D14_APC_3: 0x0
9971 23:22:49.859205 INFO: [APUAPC] D15_APC_0: 0xffffffff
9972 23:22:49.862969 INFO: [APUAPC] D15_APC_1: 0xffffffff
9973 23:22:49.866062 INFO: [APUAPC] D15_APC_2: 0x3fffff
9974 23:22:49.868983 INFO: [APUAPC] D15_APC_3: 0x0
9975 23:22:49.872729 INFO: [APUAPC] APC_CON: 0x4
9976 23:22:49.876096 INFO: [NOCDAPC] D0_APC_0: 0x0
9977 23:22:49.879326 INFO: [NOCDAPC] D0_APC_1: 0x0
9978 23:22:49.882346 INFO: [NOCDAPC] D1_APC_0: 0x0
9979 23:22:49.885790 INFO: [NOCDAPC] D1_APC_1: 0xfff
9980 23:22:49.888956 INFO: [NOCDAPC] D2_APC_0: 0x0
9981 23:22:49.892151 INFO: [NOCDAPC] D2_APC_1: 0xfff
9982 23:22:49.895617 INFO: [NOCDAPC] D3_APC_0: 0x0
9983 23:22:49.895737 INFO: [NOCDAPC] D3_APC_1: 0xfff
9984 23:22:49.899021 INFO: [NOCDAPC] D4_APC_0: 0x0
9985 23:22:49.902401 INFO: [NOCDAPC] D4_APC_1: 0xfff
9986 23:22:49.905495 INFO: [NOCDAPC] D5_APC_0: 0x0
9987 23:22:49.909084 INFO: [NOCDAPC] D5_APC_1: 0xfff
9988 23:22:49.912250 INFO: [NOCDAPC] D6_APC_0: 0x0
9989 23:22:49.915342 INFO: [NOCDAPC] D6_APC_1: 0xfff
9990 23:22:49.918931 INFO: [NOCDAPC] D7_APC_0: 0x0
9991 23:22:49.922182 INFO: [NOCDAPC] D7_APC_1: 0xfff
9992 23:22:49.925385 INFO: [NOCDAPC] D8_APC_0: 0x0
9993 23:22:49.928603 INFO: [NOCDAPC] D8_APC_1: 0xfff
9994 23:22:49.928721 INFO: [NOCDAPC] D9_APC_0: 0x0
9995 23:22:49.932098 INFO: [NOCDAPC] D9_APC_1: 0xfff
9996 23:22:49.935268 INFO: [NOCDAPC] D10_APC_0: 0x0
9997 23:22:49.938869 INFO: [NOCDAPC] D10_APC_1: 0xfff
9998 23:22:49.942047 INFO: [NOCDAPC] D11_APC_0: 0x0
9999 23:22:49.945437 INFO: [NOCDAPC] D11_APC_1: 0xfff
10000 23:22:49.948668 INFO: [NOCDAPC] D12_APC_0: 0x0
10001 23:22:49.952141 INFO: [NOCDAPC] D12_APC_1: 0xfff
10002 23:22:49.955222 INFO: [NOCDAPC] D13_APC_0: 0x0
10003 23:22:49.958438 INFO: [NOCDAPC] D13_APC_1: 0xfff
10004 23:22:49.961896 INFO: [NOCDAPC] D14_APC_0: 0x0
10005 23:22:49.965222 INFO: [NOCDAPC] D14_APC_1: 0xfff
10006 23:22:49.968586 INFO: [NOCDAPC] D15_APC_0: 0x0
10007 23:22:49.971793 INFO: [NOCDAPC] D15_APC_1: 0xfff
10008 23:22:49.975365 INFO: [NOCDAPC] APC_CON: 0x4
10009 23:22:49.978469 INFO: [APUAPC] set_apusys_apc done
10010 23:22:49.978551 INFO: [DEVAPC] devapc_init done
10011 23:22:49.984901 INFO: GICv3 without legacy support detected.
10012 23:22:49.988265 INFO: ARM GICv3 driver initialized in EL3
10013 23:22:49.991376 INFO: Maximum SPI INTID supported: 639
10014 23:22:49.994887 INFO: BL31: Initializing runtime services
10015 23:22:50.001655 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10016 23:22:50.004789 INFO: SPM: enable CPC mode
10017 23:22:50.008266 INFO: mcdi ready for mcusys-off-idle and system suspend
10018 23:22:50.014883 INFO: BL31: Preparing for EL3 exit to normal world
10019 23:22:50.018233 INFO: Entry point address = 0x80000000
10020 23:22:50.018370 INFO: SPSR = 0x8
10021 23:22:50.025773
10022 23:22:50.025913
10023 23:22:50.025977
10024 23:22:50.028774 Starting depthcharge on Spherion...
10025 23:22:50.028858
10026 23:22:50.028923 Wipe memory regions:
10027 23:22:50.028985
10028 23:22:50.029629 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10029 23:22:50.029731 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10030 23:22:50.029815 Setting prompt string to ['asurada:']
10031 23:22:50.029898 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10032 23:22:50.032327 [0x00000040000000, 0x00000054600000)
10033 23:22:50.154502
10034 23:22:50.154677 [0x00000054660000, 0x00000080000000)
10035 23:22:50.415123
10036 23:22:50.415266 [0x000000821a7280, 0x000000ffe64000)
10037 23:22:51.160091
10038 23:22:51.160230 [0x00000100000000, 0x00000240000000)
10039 23:22:53.050097
10040 23:22:53.053354 Initializing XHCI USB controller at 0x11200000.
10041 23:22:54.091415
10042 23:22:54.094489 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10043 23:22:54.094590
10044 23:22:54.094655
10045 23:22:54.094717
10046 23:22:54.095025 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10048 23:22:54.195420 asurada: tftpboot 192.168.201.1 13248456/tftp-deploy-2l1och7h/kernel/image.itb 13248456/tftp-deploy-2l1och7h/kernel/cmdline
10049 23:22:54.195597 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10050 23:22:54.195707 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10051 23:22:54.199799 tftpboot 192.168.201.1 13248456/tftp-deploy-2l1och7h/kernel/image.ittp-deploy-2l1och7h/kernel/cmdline
10052 23:22:54.199884
10053 23:22:54.199967 Waiting for link
10054 23:22:54.360209
10055 23:22:54.360389 R8152: Initializing
10056 23:22:54.360459
10057 23:22:54.363209 Version 6 (ocp_data = 5c30)
10058 23:22:54.363323
10059 23:22:54.366465 R8152: Done initializing
10060 23:22:54.366594
10061 23:22:54.366661 Adding net device
10062 23:22:56.223691
10063 23:22:56.223825 done.
10064 23:22:56.223894
10065 23:22:56.223955 MAC: 00:24:32:30:78:ff
10066 23:22:56.224014
10067 23:22:56.226851 Sending DHCP discover... done.
10068 23:22:56.226934
10069 23:22:56.230317 Waiting for reply... done.
10070 23:22:56.230400
10071 23:22:56.233545 Sending DHCP request... done.
10072 23:22:56.233627
10073 23:22:56.236791 Waiting for reply... done.
10074 23:22:56.236873
10075 23:22:56.236939 My ip is 192.168.201.21
10076 23:22:56.237001
10077 23:22:56.240248 The DHCP server ip is 192.168.201.1
10078 23:22:56.240330
10079 23:22:56.243521 TFTP server IP predefined by user: 192.168.201.1
10080 23:22:56.243604
10081 23:22:56.249936 Bootfile predefined by user: 13248456/tftp-deploy-2l1och7h/kernel/image.itb
10082 23:22:56.250019
10083 23:22:56.253547 Sending tftp read request... done.
10084 23:22:56.253629
10085 23:22:56.260081 Waiting for the transfer...
10086 23:22:56.260166
10087 23:22:56.818040 00000000 ################################################################
10088 23:22:56.818193
10089 23:22:57.386011 00080000 ################################################################
10090 23:22:57.386162
10091 23:22:57.953680 00100000 ################################################################
10092 23:22:57.953833
10093 23:22:58.521598 00180000 ################################################################
10094 23:22:58.521758
10095 23:22:59.233190 00200000 ################################################################
10096 23:22:59.233350
10097 23:22:59.956298 00280000 ################################################################
10098 23:22:59.956493
10099 23:23:00.670554 00300000 ################################################################
10100 23:23:00.670700
10101 23:23:01.391424 00380000 ################################################################
10102 23:23:01.391592
10103 23:23:02.080310 00400000 ################################################################
10104 23:23:02.080448
10105 23:23:02.699139 00480000 ################################################################
10106 23:23:02.699278
10107 23:23:03.414279 00500000 ################################################################
10108 23:23:03.414417
10109 23:23:04.121603 00580000 ################################################################
10110 23:23:04.121773
10111 23:23:04.851867 00600000 ################################################################
10112 23:23:04.852016
10113 23:23:05.538878 00680000 ################################################################
10114 23:23:05.539084
10115 23:23:06.203814 00700000 ################################################################
10116 23:23:06.203965
10117 23:23:06.883245 00780000 ################################################################
10118 23:23:06.883431
10119 23:23:07.609689 00800000 ################################################################
10120 23:23:07.609881
10121 23:23:08.324708 00880000 ################################################################
10122 23:23:08.324890
10123 23:23:09.070559 00900000 ################################################################
10124 23:23:09.070718
10125 23:23:09.758776 00980000 ################################################################
10126 23:23:09.758943
10127 23:23:10.386393 00a00000 ################################################################
10128 23:23:10.386549
10129 23:23:11.040804 00a80000 ################################################################
10130 23:23:11.040957
10131 23:23:11.787989 00b00000 ################################################################
10132 23:23:11.788149
10133 23:23:12.520455 00b80000 ################################################################
10134 23:23:12.520623
10135 23:23:13.260470 00c00000 ################################################################
10136 23:23:13.260650
10137 23:23:13.958766 00c80000 ################################################################
10138 23:23:13.958940
10139 23:23:14.641605 00d00000 ################################################################
10140 23:23:14.641758
10141 23:23:15.323528 00d80000 ################################################################
10142 23:23:15.323712
10143 23:23:16.010974 00e00000 ################################################################
10144 23:23:16.011145
10145 23:23:16.719258 00e80000 ################################################################
10146 23:23:16.719422
10147 23:23:17.447395 00f00000 ################################################################
10148 23:23:17.447545
10149 23:23:18.185748 00f80000 ################################################################
10150 23:23:18.185901
10151 23:23:18.877427 01000000 ################################################################
10152 23:23:18.877609
10153 23:23:19.581222 01080000 ################################################################
10154 23:23:19.581377
10155 23:23:20.268761 01100000 ################################################################
10156 23:23:20.268909
10157 23:23:21.005046 01180000 ################################################################
10158 23:23:21.005265
10159 23:23:21.726668 01200000 ################################################################
10160 23:23:21.726821
10161 23:23:22.433460 01280000 ################################################################
10162 23:23:22.433631
10163 23:23:23.154595 01300000 ################################################################
10164 23:23:23.154774
10165 23:23:23.844776 01380000 ################################################################
10166 23:23:23.844919
10167 23:23:24.564694 01400000 ################################################################
10168 23:23:24.564847
10169 23:23:25.248418 01480000 ################################################################
10170 23:23:25.248566
10171 23:23:25.966933 01500000 ################################################################
10172 23:23:25.967126
10173 23:23:26.672143 01580000 ################################################################
10174 23:23:26.672293
10175 23:23:27.366556 01600000 ################################################################
10176 23:23:27.366731
10177 23:23:28.067606 01680000 ################################################################
10178 23:23:28.067740
10179 23:23:28.772939 01700000 ################################################################
10180 23:23:28.773091
10181 23:23:29.513607 01780000 ################################################################
10182 23:23:29.513746
10183 23:23:30.200202 01800000 ################################################################
10184 23:23:30.200356
10185 23:23:30.886581 01880000 ################################################################
10186 23:23:30.886752
10187 23:23:31.566120 01900000 ################################################################
10188 23:23:31.566269
10189 23:23:32.249656 01980000 ################################################################
10190 23:23:32.249795
10191 23:23:32.924948 01a00000 ################################################################
10192 23:23:32.925124
10193 23:23:33.604318 01a80000 ################################################################
10194 23:23:33.604474
10195 23:23:34.277015 01b00000 ################################################################
10196 23:23:34.277187
10197 23:23:34.949786 01b80000 ################################################################
10198 23:23:34.949940
10199 23:23:35.620262 01c00000 ################################################################
10200 23:23:35.620437
10201 23:23:36.300423 01c80000 ################################################################
10202 23:23:36.300597
10203 23:23:36.974132 01d00000 ################################################################
10204 23:23:36.974275
10205 23:23:37.646735 01d80000 ################################################################
10206 23:23:37.646912
10207 23:23:38.316523 01e00000 ################################################################
10208 23:23:38.316660
10209 23:23:39.000801 01e80000 ################################################################
10210 23:23:39.000950
10211 23:23:39.674697 01f00000 ################################################################
10212 23:23:39.674835
10213 23:23:40.354086 01f80000 ################################################################
10214 23:23:40.354246
10215 23:23:41.027952 02000000 ################################################################
10216 23:23:41.028093
10217 23:23:41.713432 02080000 ################################################################
10218 23:23:41.713598
10219 23:23:42.401931 02100000 ################################################################
10220 23:23:42.402093
10221 23:23:43.098600 02180000 ################################################################
10222 23:23:43.098760
10223 23:23:43.785482 02200000 ################################################################
10224 23:23:43.785637
10225 23:23:44.481647 02280000 ################################################################
10226 23:23:44.481789
10227 23:23:45.156670 02300000 ################################################################
10228 23:23:45.156814
10229 23:23:45.839286 02380000 ################################################################
10230 23:23:45.839426
10231 23:23:46.512113 02400000 ################################################################
10232 23:23:46.512311
10233 23:23:47.182724 02480000 ################################################################
10234 23:23:47.182873
10235 23:23:47.888316 02500000 ################################################################
10236 23:23:47.888468
10237 23:23:48.592194 02580000 ################################################################
10238 23:23:48.592336
10239 23:23:49.312016 02600000 ################################################################
10240 23:23:49.312177
10241 23:23:50.011740 02680000 ################################################################
10242 23:23:50.011883
10243 23:23:50.731471 02700000 ################################################################
10244 23:23:50.731621
10245 23:23:51.424946 02780000 ################################################################
10246 23:23:51.425142
10247 23:23:52.128300 02800000 ################################################################
10248 23:23:52.128448
10249 23:23:52.823441 02880000 ################################################################
10250 23:23:52.823602
10251 23:23:53.521397 02900000 ################################################################
10252 23:23:53.521557
10253 23:23:54.229553 02980000 ################################################################
10254 23:23:54.229710
10255 23:23:54.929071 02a00000 ################################################################
10256 23:23:54.929260
10257 23:23:55.665514 02a80000 ################################################################
10258 23:23:55.665701
10259 23:23:56.381128 02b00000 ################################################################
10260 23:23:56.381316
10261 23:23:57.078577 02b80000 ################################################################
10262 23:23:57.078736
10263 23:23:57.764094 02c00000 ################################################################
10264 23:23:57.764273
10265 23:23:58.447029 02c80000 ################################################################
10266 23:23:58.447211
10267 23:23:59.134643 02d00000 ################################################################
10268 23:23:59.134797
10269 23:23:59.825672 02d80000 ################################################################
10270 23:23:59.825842
10271 23:24:00.536311 02e00000 ################################################################
10272 23:24:00.536466
10273 23:24:01.233917 02e80000 ################################################################
10274 23:24:01.234069
10275 23:24:01.963403 02f00000 ################################################################
10276 23:24:01.963552
10277 23:24:02.672234 02f80000 ################################################################
10278 23:24:02.672416
10279 23:24:03.397571 03000000 ################################################################
10280 23:24:03.397720
10281 23:24:04.160280 03080000 ################################################################
10282 23:24:04.160414
10283 23:24:04.914951 03100000 ################################################################
10284 23:24:04.915104
10285 23:24:05.626301 03180000 ################################################################
10286 23:24:05.626451
10287 23:24:06.343772 03200000 ################################################################
10288 23:24:06.343921
10289 23:24:07.044322 03280000 ################################################################
10290 23:24:07.044460
10291 23:24:07.749754 03300000 ################################################################
10292 23:24:07.749892
10293 23:24:08.447035 03380000 ################################################################
10294 23:24:08.447199
10295 23:24:09.157784 03400000 ################################################################
10296 23:24:09.157916
10297 23:24:09.863952 03480000 ################################################################
10298 23:24:09.864091
10299 23:24:10.557739 03500000 ################################################################
10300 23:24:10.557880
10301 23:24:11.268998 03580000 ################################################################
10302 23:24:11.269162
10303 23:24:11.958582 03600000 ################################################################
10304 23:24:11.958731
10305 23:24:12.643762 03680000 ################################################################
10306 23:24:12.643919
10307 23:24:13.341830 03700000 ################################################################
10308 23:24:13.342001
10309 23:24:14.023727 03780000 ################################################################
10310 23:24:14.023893
10311 23:24:14.720519 03800000 ################################################################
10312 23:24:14.720664
10313 23:24:15.417337 03880000 ################################################################
10314 23:24:15.417510
10315 23:24:16.106962 03900000 ################################################################
10316 23:24:16.107111
10317 23:24:16.797332 03980000 ################################################################
10318 23:24:16.797516
10319 23:24:17.475107 03a00000 ################################################################
10320 23:24:17.475262
10321 23:24:18.083021 03a80000 ################################################################
10322 23:24:18.083187
10323 23:24:18.619325 03b00000 ################################################################
10324 23:24:18.619479
10325 23:24:19.157672 03b80000 ################################################################
10326 23:24:19.157804
10327 23:24:19.688035 03c00000 ################################################################
10328 23:24:19.688261
10329 23:24:20.228990 03c80000 ################################################################
10330 23:24:20.229126
10331 23:24:20.801842 03d00000 ################################################################
10332 23:24:20.802001
10333 23:24:21.358147 03d80000 ################################################################
10334 23:24:21.358293
10335 23:24:21.917460 03e00000 ################################################################
10336 23:24:21.917656
10337 23:24:22.491201 03e80000 ################################################################
10338 23:24:22.491335
10339 23:24:23.039365 03f00000 ################################################################
10340 23:24:23.039524
10341 23:24:23.585745 03f80000 ################################################################
10342 23:24:23.585889
10343 23:24:24.152278 04000000 ################################################################
10344 23:24:24.152447
10345 23:24:24.723230 04080000 ################################################################
10346 23:24:24.723409
10347 23:24:25.262626 04100000 ################################################################
10348 23:24:25.262772
10349 23:24:25.788059 04180000 ################################################################
10350 23:24:25.788205
10351 23:24:26.327013 04200000 ################################################################
10352 23:24:26.327165
10353 23:24:26.857848 04280000 ################################################################
10354 23:24:26.858000
10355 23:24:27.398861 04300000 ################################################################
10356 23:24:27.399006
10357 23:24:27.938363 04380000 ################################################################
10358 23:24:27.938522
10359 23:24:28.475515 04400000 ################################################################
10360 23:24:28.475659
10361 23:24:29.019526 04480000 ################################################################
10362 23:24:29.019685
10363 23:24:29.572074 04500000 ################################################################
10364 23:24:29.572250
10365 23:24:30.120247 04580000 ################################################################
10366 23:24:30.120406
10367 23:24:30.662214 04600000 ################################################################
10368 23:24:30.662382
10369 23:24:31.219877 04680000 ################################################################
10370 23:24:31.220056
10371 23:24:31.766175 04700000 ################################################################
10372 23:24:31.766352
10373 23:24:32.309851 04780000 ################################################################
10374 23:24:32.309995
10375 23:24:32.847897 04800000 ################################################################
10376 23:24:32.848068
10377 23:24:33.403263 04880000 ################################################################
10378 23:24:33.403426
10379 23:24:33.966329 04900000 ################################################################
10380 23:24:33.966498
10381 23:24:34.502634 04980000 ################################################################
10382 23:24:34.502795
10383 23:24:35.041272 04a00000 ################################################################
10384 23:24:35.041454
10385 23:24:35.592819 04a80000 ################################################################
10386 23:24:35.592984
10387 23:24:36.134131 04b00000 ################################################################
10388 23:24:36.134294
10389 23:24:36.711035 04b80000 ################################################################
10390 23:24:36.711182
10391 23:24:37.285827 04c00000 ################################################################
10392 23:24:37.285973
10393 23:24:37.838704 04c80000 ################################################################
10394 23:24:37.838839
10395 23:24:38.399140 04d00000 ################################################################
10396 23:24:38.399305
10397 23:24:38.950304 04d80000 ################################################################
10398 23:24:38.950461
10399 23:24:39.651653 04e00000 ################################################################
10400 23:24:39.652278
10401 23:24:40.404142 04e80000 ################################################################
10402 23:24:40.404672
10403 23:24:41.118535 04f00000 ################################################################
10404 23:24:41.119043
10405 23:24:41.754625 04f80000 ################################################################
10406 23:24:41.755233
10407 23:24:42.313890 05000000 ################################################################
10408 23:24:42.314026
10409 23:24:42.904353 05080000 ################################################################
10410 23:24:42.904584
10411 23:24:43.625707 05100000 ################################################################
10412 23:24:43.626293
10413 23:24:44.271537 05180000 ################################################################
10414 23:24:44.271676
10415 23:24:44.922148 05200000 ################################################################
10416 23:24:44.922291
10417 23:24:45.512453 05280000 ################################################################
10418 23:24:45.512998
10419 23:24:46.247030 05300000 ################################################################
10420 23:24:46.247553
10421 23:24:46.969620 05380000 ################################################################
10422 23:24:46.970195
10423 23:24:47.707855 05400000 ################################################################
10424 23:24:47.708368
10425 23:24:48.420337 05480000 ################################################################
10426 23:24:48.420869
10427 23:24:49.145688 05500000 ################################################################
10428 23:24:49.146196
10429 23:24:49.878420 05580000 ################################################################
10430 23:24:49.878947
10431 23:24:50.585892 05600000 ################################################################
10432 23:24:50.586425
10433 23:24:51.301123 05680000 ################################################################
10434 23:24:51.301695
10435 23:24:52.035352 05700000 ################################################################
10436 23:24:52.035857
10437 23:24:52.771021 05780000 ################################################################
10438 23:24:52.771593
10439 23:24:53.501641 05800000 ################################################################
10440 23:24:53.502169
10441 23:24:54.236215 05880000 ################################################################
10442 23:24:54.236729
10443 23:24:54.959546 05900000 ################################################################
10444 23:24:54.960094
10445 23:24:55.649327 05980000 ################################################################
10446 23:24:55.649894
10447 23:24:56.383804 05a00000 ################################################################
10448 23:24:56.384317
10449 23:24:57.113247 05a80000 ################################################################
10450 23:24:57.113821
10451 23:24:57.855692 05b00000 ################################################################
10452 23:24:57.856322
10453 23:24:58.588612 05b80000 ################################################################
10454 23:24:58.589191
10455 23:24:59.264546 05c00000 ################################################################
10456 23:24:59.264922
10457 23:24:59.895552 05c80000 ################################################################
10458 23:24:59.896041
10459 23:25:00.537336 05d00000 ################################################################
10460 23:25:00.537761
10461 23:25:01.179658 05d80000 ################################################################
10462 23:25:01.179792
10463 23:25:01.830000 05e00000 ################################################################
10464 23:25:01.830370
10465 23:25:02.509081 05e80000 ################################################################
10466 23:25:02.509216
10467 23:25:03.089201 05f00000 ################################################################
10468 23:25:03.089338
10469 23:25:03.709617 05f80000 ################################################################
10470 23:25:03.710137
10471 23:25:04.430247 06000000 ################################################################
10472 23:25:04.430787
10473 23:25:05.162160 06080000 ################################################################
10474 23:25:05.162802
10475 23:25:05.916625 06100000 ################################################################
10476 23:25:05.917278
10477 23:25:06.660709 06180000 ################################################################
10478 23:25:06.661265
10479 23:25:07.400283 06200000 ################################################################
10480 23:25:07.400804
10481 23:25:08.154605 06280000 ################################################################
10482 23:25:08.155132
10483 23:25:08.908772 06300000 ################################################################
10484 23:25:08.909433
10485 23:25:09.648931 06380000 ################################################################
10486 23:25:09.649459
10487 23:25:10.403238 06400000 ################################################################
10488 23:25:10.403903
10489 23:25:11.129174 06480000 ################################################################
10490 23:25:11.129725
10491 23:25:11.832708 06500000 ################################################################
10492 23:25:11.833230
10493 23:25:12.548238 06580000 ################################################################
10494 23:25:12.548952
10495 23:25:13.257884 06600000 ################################################################
10496 23:25:13.258389
10497 23:25:13.966557 06680000 ################################################################
10498 23:25:13.967070
10499 23:25:14.703355 06700000 ################################################################
10500 23:25:14.703605
10501 23:25:15.413832 06780000 ################################################################
10502 23:25:15.414349
10503 23:25:16.118896 06800000 ################################################################
10504 23:25:16.119082
10505 23:25:16.857227 06880000 ################################################################
10506 23:25:16.857807
10507 23:25:17.610359 06900000 ################################################################
10508 23:25:17.610891
10509 23:25:18.340902 06980000 ################################################################
10510 23:25:18.341426
10511 23:25:19.069822 06a00000 ################################################################
10512 23:25:19.070504
10513 23:25:19.794536 06a80000 ################################################################
10514 23:25:19.795056
10515 23:25:20.528324 06b00000 ################################################################
10516 23:25:20.528852
10517 23:25:21.265358 06b80000 ################################################################
10518 23:25:21.265955
10519 23:25:22.004945 06c00000 ################################################################
10520 23:25:22.005508
10521 23:25:22.738578 06c80000 ################################################################
10522 23:25:22.739095
10523 23:25:23.469600 06d00000 ################################################################
10524 23:25:23.470120
10525 23:25:24.196713 06d80000 ################################################################
10526 23:25:24.197253
10527 23:25:24.932336 06e00000 ################################################################
10528 23:25:24.932859
10529 23:25:25.669716 06e80000 ################################################################
10530 23:25:25.670225
10531 23:25:26.418590 06f00000 ################################################################
10532 23:25:26.419122
10533 23:25:27.146446 06f80000 ################################################################
10534 23:25:27.146979
10535 23:25:27.880369 07000000 ################################################################
10536 23:25:27.880903
10537 23:25:28.622158 07080000 ################################################################
10538 23:25:28.622689
10539 23:25:29.362910 07100000 ################################################################
10540 23:25:29.363453
10541 23:25:30.107789 07180000 ################################################################
10542 23:25:30.108301
10543 23:25:30.857464 07200000 ################################################################
10544 23:25:30.858046
10545 23:25:31.592486 07280000 ################################################################
10546 23:25:31.593008
10547 23:25:32.341297 07300000 ################################################################
10548 23:25:32.341913
10549 23:25:33.099990 07380000 ################################################################
10550 23:25:33.100644
10551 23:25:33.579191 07400000 ########################################## done.
10552 23:25:33.579718
10553 23:25:33.582038 The bootfile was 121973882 bytes long.
10554 23:25:33.582459
10555 23:25:33.585549 Sending tftp read request... done.
10556 23:25:33.585964
10557 23:25:33.589378 Waiting for the transfer...
10558 23:25:33.589832
10559 23:25:33.590161 00000000 # done.
10560 23:25:33.590474
10561 23:25:33.596017 Command line loaded dynamically from TFTP file: 13248456/tftp-deploy-2l1och7h/kernel/cmdline
10562 23:25:33.596433
10563 23:25:33.609469 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10564 23:25:33.613066
10565 23:25:33.613645 Loading FIT.
10566 23:25:33.613991
10567 23:25:33.616270 Image ramdisk-1 has 109017346 bytes.
10568 23:25:33.616685
10569 23:25:33.619650 Image fdt-1 has 47230 bytes.
10570 23:25:33.620164
10571 23:25:33.622665 Image kernel-1 has 12907270 bytes.
10572 23:25:33.623124
10573 23:25:33.629218 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10574 23:25:33.629792
10575 23:25:33.649348 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10576 23:25:33.650071
10577 23:25:33.652888 Choosing best match conf-1 for compat google,spherion-rev2.
10578 23:25:33.657571
10579 23:25:33.662075 Connected to device vid:did:rid of 1ae0:0028:00
10580 23:25:33.670196
10581 23:25:33.673712 tpm_get_response: command 0x17b, return code 0x0
10582 23:25:33.674229
10583 23:25:33.676363 ec_init: CrosEC protocol v3 supported (256, 248)
10584 23:25:33.681093
10585 23:25:33.684016 tpm_cleanup: add release locality here.
10586 23:25:33.684431
10587 23:25:33.684767 Shutting down all USB controllers.
10588 23:25:33.687342
10589 23:25:33.687771 Removing current net device
10590 23:25:33.688101
10591 23:25:33.694071 Exiting depthcharge with code 4 at timestamp: 192940039
10592 23:25:33.694579
10593 23:25:33.697761 LZMA decompressing kernel-1 to 0x821a6718
10594 23:25:33.698178
10595 23:25:33.701042 LZMA decompressing kernel-1 to 0x40000000
10596 23:25:35.294861
10597 23:25:35.295359 jumping to kernel
10598 23:25:35.297678 end: 2.2.4 bootloader-commands (duration 00:02:45) [common]
10599 23:25:35.298181 start: 2.2.5 auto-login-action (timeout 00:01:40) [common]
10600 23:25:35.298565 Setting prompt string to ['Linux version [0-9]']
10601 23:25:35.298905 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10602 23:25:35.299246 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10603 23:25:35.377369
10604 23:25:35.380587 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10605 23:25:35.384056 start: 2.2.5.1 login-action (timeout 00:01:40) [common]
10606 23:25:35.384627 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10607 23:25:35.384987 Setting prompt string to []
10608 23:25:35.385429 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10609 23:25:35.385934 Using line separator: #'\n'#
10610 23:25:35.386272 No login prompt set.
10611 23:25:35.386692 Parsing kernel messages
10612 23:25:35.387041 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10613 23:25:35.387805 [login-action] Waiting for messages, (timeout 00:01:40)
10614 23:25:35.388329 Waiting using forced prompt support (timeout 00:00:50)
10615 23:25:35.403726 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10616 23:25:35.407131 [ 0.000000] random: crng init done
10617 23:25:35.413641 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10618 23:25:35.416978 [ 0.000000] efi: UEFI not found.
10619 23:25:35.423432 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10620 23:25:35.429981 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10621 23:25:35.440028 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10622 23:25:35.449737 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10623 23:25:35.456426 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10624 23:25:35.463065 [ 0.000000] printk: bootconsole [mtk8250] enabled
10625 23:25:35.469457 [ 0.000000] NUMA: No NUMA configuration found
10626 23:25:35.476212 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10627 23:25:35.479647 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10628 23:25:35.482775 [ 0.000000] Zone ranges:
10629 23:25:35.489450 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10630 23:25:35.492866 [ 0.000000] DMA32 empty
10631 23:25:35.499556 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10632 23:25:35.502723 [ 0.000000] Movable zone start for each node
10633 23:25:35.505968 [ 0.000000] Early memory node ranges
10634 23:25:35.512686 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10635 23:25:35.519341 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10636 23:25:35.525696 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10637 23:25:35.532645 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10638 23:25:35.538872 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10639 23:25:35.545598 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10640 23:25:35.601779 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10641 23:25:35.608382 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10642 23:25:35.615203 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10643 23:25:35.618071 [ 0.000000] psci: probing for conduit method from DT.
10644 23:25:35.624849 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10645 23:25:35.628152 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10646 23:25:35.634720 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10647 23:25:35.638134 [ 0.000000] psci: SMC Calling Convention v1.2
10648 23:25:35.644835 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10649 23:25:35.648041 [ 0.000000] Detected VIPT I-cache on CPU0
10650 23:25:35.654907 [ 0.000000] CPU features: detected: GIC system register CPU interface
10651 23:25:35.661423 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10652 23:25:35.668057 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10653 23:25:35.674441 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10654 23:25:35.681210 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10655 23:25:35.691066 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10656 23:25:35.694322 [ 0.000000] alternatives: applying boot alternatives
10657 23:25:35.701102 [ 0.000000] Fallback order for Node 0: 0
10658 23:25:35.707723 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10659 23:25:35.711027 [ 0.000000] Policy zone: Normal
10660 23:25:35.724533 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10661 23:25:35.734279 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10662 23:25:35.746080 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10663 23:25:35.756055 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10664 23:25:35.762735 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10665 23:25:35.766063 <6>[ 0.000000] software IO TLB: area num 8.
10666 23:25:35.822274 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10667 23:25:35.971665 <6>[ 0.000000] Memory: 7858108K/8385536K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 494660K reserved, 32768K cma-reserved)
10668 23:25:35.978274 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10669 23:25:35.984741 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10670 23:25:35.988071 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10671 23:25:35.994789 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10672 23:25:36.001260 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10673 23:25:36.004724 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10674 23:25:36.014479 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10675 23:25:36.021272 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10676 23:25:36.027580 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10677 23:25:36.034514 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10678 23:25:36.037378 <6>[ 0.000000] GICv3: 608 SPIs implemented
10679 23:25:36.040881 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10680 23:25:36.047799 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10681 23:25:36.051204 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10682 23:25:36.057452 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10683 23:25:36.070746 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10684 23:25:36.084109 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10685 23:25:36.090564 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10686 23:25:36.098174 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10687 23:25:36.111309 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10688 23:25:36.117596 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10689 23:25:36.124384 <6>[ 0.009182] Console: colour dummy device 80x25
10690 23:25:36.134513 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10691 23:25:36.141222 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10692 23:25:36.144560 <6>[ 0.029223] LSM: Security Framework initializing
10693 23:25:36.151313 <6>[ 0.034190] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10694 23:25:36.160894 <6>[ 0.042052] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10695 23:25:36.167453 <6>[ 0.051467] cblist_init_generic: Setting adjustable number of callback queues.
10696 23:25:36.174403 <6>[ 0.058911] cblist_init_generic: Setting shift to 3 and lim to 1.
10697 23:25:36.184247 <6>[ 0.065249] cblist_init_generic: Setting adjustable number of callback queues.
10698 23:25:36.190536 <6>[ 0.072676] cblist_init_generic: Setting shift to 3 and lim to 1.
10699 23:25:36.194059 <6>[ 0.079115] rcu: Hierarchical SRCU implementation.
10700 23:25:36.200355 <6>[ 0.084131] rcu: Max phase no-delay instances is 1000.
10701 23:25:36.207241 <6>[ 0.091159] EFI services will not be available.
10702 23:25:36.210350 <6>[ 0.096122] smp: Bringing up secondary CPUs ...
10703 23:25:36.219029 <6>[ 0.101174] Detected VIPT I-cache on CPU1
10704 23:25:36.225295 <6>[ 0.101243] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10705 23:25:36.232091 <6>[ 0.101274] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10706 23:25:36.235276 <6>[ 0.101611] Detected VIPT I-cache on CPU2
10707 23:25:36.245093 <6>[ 0.101662] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10708 23:25:36.251825 <6>[ 0.101679] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10709 23:25:36.255192 <6>[ 0.101937] Detected VIPT I-cache on CPU3
10710 23:25:36.261616 <6>[ 0.101984] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10711 23:25:36.268437 <6>[ 0.101999] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10712 23:25:36.271561 <6>[ 0.102305] CPU features: detected: Spectre-v4
10713 23:25:36.278339 <6>[ 0.102312] CPU features: detected: Spectre-BHB
10714 23:25:36.281750 <6>[ 0.102317] Detected PIPT I-cache on CPU4
10715 23:25:36.287974 <6>[ 0.102375] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10716 23:25:36.294980 <6>[ 0.102392] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10717 23:25:36.301790 <6>[ 0.102685] Detected PIPT I-cache on CPU5
10718 23:25:36.308334 <6>[ 0.102748] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10719 23:25:36.314738 <6>[ 0.102764] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10720 23:25:36.318034 <6>[ 0.103040] Detected PIPT I-cache on CPU6
10721 23:25:36.324511 <6>[ 0.103106] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10722 23:25:36.331181 <6>[ 0.103122] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10723 23:25:36.337818 <6>[ 0.103415] Detected PIPT I-cache on CPU7
10724 23:25:36.344248 <6>[ 0.103478] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10725 23:25:36.350903 <6>[ 0.103495] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10726 23:25:36.354270 <6>[ 0.103541] smp: Brought up 1 node, 8 CPUs
10727 23:25:36.361017 <6>[ 0.244908] SMP: Total of 8 processors activated.
10728 23:25:36.364059 <6>[ 0.249829] CPU features: detected: 32-bit EL0 Support
10729 23:25:36.374068 <6>[ 0.255225] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10730 23:25:36.380824 <6>[ 0.264024] CPU features: detected: Common not Private translations
10731 23:25:36.387247 <6>[ 0.270501] CPU features: detected: CRC32 instructions
10732 23:25:36.390556 <6>[ 0.275885] CPU features: detected: RCpc load-acquire (LDAPR)
10733 23:25:36.397348 <6>[ 0.281882] CPU features: detected: LSE atomic instructions
10734 23:25:36.403844 <6>[ 0.287664] CPU features: detected: Privileged Access Never
10735 23:25:36.410439 <6>[ 0.293444] CPU features: detected: RAS Extension Support
10736 23:25:36.417347 <6>[ 0.299082] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10737 23:25:36.420291 <6>[ 0.306346] CPU: All CPU(s) started at EL2
10738 23:25:36.426699 <6>[ 0.310690] alternatives: applying system-wide alternatives
10739 23:25:36.436681 <6>[ 0.321542] devtmpfs: initialized
10740 23:25:36.452102 <6>[ 0.330453] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10741 23:25:36.459015 <6>[ 0.340410] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10742 23:25:36.465565 <6>[ 0.348641] pinctrl core: initialized pinctrl subsystem
10743 23:25:36.468902 <6>[ 0.355310] DMI not present or invalid.
10744 23:25:36.475301 <6>[ 0.359725] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10745 23:25:36.484841 <6>[ 0.366614] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10746 23:25:36.491434 <6>[ 0.374196] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10747 23:25:36.501950 <6>[ 0.382428] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10748 23:25:36.505004 <6>[ 0.390675] audit: initializing netlink subsys (disabled)
10749 23:25:36.514995 <5>[ 0.396372] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10750 23:25:36.521603 <6>[ 0.397079] thermal_sys: Registered thermal governor 'step_wise'
10751 23:25:36.528402 <6>[ 0.404338] thermal_sys: Registered thermal governor 'power_allocator'
10752 23:25:36.531762 <6>[ 0.410591] cpuidle: using governor menu
10753 23:25:36.538400 <6>[ 0.421553] NET: Registered PF_QIPCRTR protocol family
10754 23:25:36.544740 <6>[ 0.427036] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10755 23:25:36.551390 <6>[ 0.434140] ASID allocator initialised with 32768 entries
10756 23:25:36.554591 <6>[ 0.440696] Serial: AMBA PL011 UART driver
10757 23:25:36.564633 <4>[ 0.449512] Trying to register duplicate clock ID: 134
10758 23:25:36.618832 <6>[ 0.507014] KASLR enabled
10759 23:25:36.633231 <6>[ 0.514911] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10760 23:25:36.639932 <6>[ 0.521923] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10761 23:25:36.646593 <6>[ 0.528410] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10762 23:25:36.653346 <6>[ 0.535417] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10763 23:25:36.659571 <6>[ 0.541905] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10764 23:25:36.666401 <6>[ 0.548909] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10765 23:25:36.672915 <6>[ 0.555395] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10766 23:25:36.679565 <6>[ 0.562399] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10767 23:25:36.682830 <6>[ 0.569927] ACPI: Interpreter disabled.
10768 23:25:36.691696 <6>[ 0.576427] iommu: Default domain type: Translated
10769 23:25:36.698402 <6>[ 0.581540] iommu: DMA domain TLB invalidation policy: strict mode
10770 23:25:36.701268 <5>[ 0.588197] SCSI subsystem initialized
10771 23:25:36.708256 <6>[ 0.592361] usbcore: registered new interface driver usbfs
10772 23:25:36.714943 <6>[ 0.598094] usbcore: registered new interface driver hub
10773 23:25:36.718310 <6>[ 0.603646] usbcore: registered new device driver usb
10774 23:25:36.725033 <6>[ 0.609743] pps_core: LinuxPPS API ver. 1 registered
10775 23:25:36.735172 <6>[ 0.614936] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10776 23:25:36.738027 <6>[ 0.624281] PTP clock support registered
10777 23:25:36.741518 <6>[ 0.628523] EDAC MC: Ver: 3.0.0
10778 23:25:36.749211 <6>[ 0.633702] FPGA manager framework
10779 23:25:36.755489 <6>[ 0.637382] Advanced Linux Sound Architecture Driver Initialized.
10780 23:25:36.758785 <6>[ 0.644163] vgaarb: loaded
10781 23:25:36.765543 <6>[ 0.647333] clocksource: Switched to clocksource arch_sys_counter
10782 23:25:36.768750 <5>[ 0.653773] VFS: Disk quotas dquot_6.6.0
10783 23:25:36.775470 <6>[ 0.657956] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10784 23:25:36.778609 <6>[ 0.665145] pnp: PnP ACPI: disabled
10785 23:25:36.787256 <6>[ 0.671817] NET: Registered PF_INET protocol family
10786 23:25:36.796928 <6>[ 0.677431] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10787 23:25:36.808416 <6>[ 0.689771] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10788 23:25:36.818233 <6>[ 0.698590] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10789 23:25:36.824584 <6>[ 0.706560] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10790 23:25:36.834504 <6>[ 0.715257] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10791 23:25:36.840947 <6>[ 0.724981] TCP: Hash tables configured (established 65536 bind 65536)
10792 23:25:36.847733 <6>[ 0.731847] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10793 23:25:36.857471 <6>[ 0.739046] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10794 23:25:36.864244 <6>[ 0.746748] NET: Registered PF_UNIX/PF_LOCAL protocol family
10795 23:25:36.870728 <6>[ 0.752895] RPC: Registered named UNIX socket transport module.
10796 23:25:36.873870 <6>[ 0.759049] RPC: Registered udp transport module.
10797 23:25:36.880564 <6>[ 0.763983] RPC: Registered tcp transport module.
10798 23:25:36.887309 <6>[ 0.768911] RPC: Registered tcp NFSv4.1 backchannel transport module.
10799 23:25:36.890564 <6>[ 0.775580] PCI: CLS 0 bytes, default 64
10800 23:25:36.893532 <6>[ 0.779921] Unpacking initramfs...
10801 23:25:36.917976 <6>[ 0.799468] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10802 23:25:36.927820 <6>[ 0.808135] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10803 23:25:36.931206 <6>[ 0.816982] kvm [1]: IPA Size Limit: 40 bits
10804 23:25:36.937707 <6>[ 0.821509] kvm [1]: GICv3: no GICV resource entry
10805 23:25:36.940944 <6>[ 0.826531] kvm [1]: disabling GICv2 emulation
10806 23:25:36.947951 <6>[ 0.831219] kvm [1]: GIC system register CPU interface enabled
10807 23:25:36.951324 <6>[ 0.837408] kvm [1]: vgic interrupt IRQ18
10808 23:25:36.957577 <6>[ 0.841764] kvm [1]: VHE mode initialized successfully
10809 23:25:36.964295 <5>[ 0.848204] Initialise system trusted keyrings
10810 23:25:36.970890 <6>[ 0.853008] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10811 23:25:36.978030 <6>[ 0.862997] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10812 23:25:36.984842 <5>[ 0.869411] NFS: Registering the id_resolver key type
10813 23:25:36.988153 <5>[ 0.874713] Key type id_resolver registered
10814 23:25:36.994694 <5>[ 0.879124] Key type id_legacy registered
10815 23:25:37.001468 <6>[ 0.883409] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10816 23:25:37.007916 <6>[ 0.890330] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10817 23:25:37.014316 <6>[ 0.898038] 9p: Installing v9fs 9p2000 file system support
10818 23:25:37.051858 <5>[ 0.936733] Key type asymmetric registered
10819 23:25:37.055259 <5>[ 0.941063] Asymmetric key parser 'x509' registered
10820 23:25:37.065179 <6>[ 0.946236] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10821 23:25:37.068519 <6>[ 0.953854] io scheduler mq-deadline registered
10822 23:25:37.071549 <6>[ 0.958617] io scheduler kyber registered
10823 23:25:37.091019 <6>[ 0.976061] EINJ: ACPI disabled.
10824 23:25:37.123639 <4>[ 1.002001] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10825 23:25:37.133514 <4>[ 1.012642] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10826 23:25:37.148393 <6>[ 1.033418] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10827 23:25:37.156502 <6>[ 1.041397] printk: console [ttyS0] disabled
10828 23:25:37.184325 <6>[ 1.066021] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10829 23:25:37.191309 <6>[ 1.075493] printk: console [ttyS0] enabled
10830 23:25:37.194479 <6>[ 1.075493] printk: console [ttyS0] enabled
10831 23:25:37.201104 <6>[ 1.084385] printk: bootconsole [mtk8250] disabled
10832 23:25:37.204467 <6>[ 1.084385] printk: bootconsole [mtk8250] disabled
10833 23:25:37.210999 <6>[ 1.095635] SuperH (H)SCI(F) driver initialized
10834 23:25:37.214506 <6>[ 1.100907] msm_serial: driver initialized
10835 23:25:37.228277 <6>[ 1.109899] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10836 23:25:37.238606 <6>[ 1.118444] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10837 23:25:37.245089 <6>[ 1.126986] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10838 23:25:37.254944 <6>[ 1.135615] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10839 23:25:37.261613 <6>[ 1.144321] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10840 23:25:37.271482 <6>[ 1.153043] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10841 23:25:37.281615 <6>[ 1.161585] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10842 23:25:37.287995 <6>[ 1.170388] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10843 23:25:37.297967 <6>[ 1.178933] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10844 23:25:37.309602 <6>[ 1.194528] loop: module loaded
10845 23:25:37.316057 <6>[ 1.200721] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10846 23:25:37.339450 <4>[ 1.224348] mtk-pmic-keys: Failed to locate of_node [id: -1]
10847 23:25:37.346637 <6>[ 1.231559] megasas: 07.719.03.00-rc1
10848 23:25:37.356342 <6>[ 1.241256] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10849 23:25:37.365786 <6>[ 1.250727] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10850 23:25:37.382749 <6>[ 1.267401] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10851 23:25:37.439387 <6>[ 1.317509] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10852 23:25:41.516169 <6>[ 5.401514] Freeing initrd memory: 106460K
10853 23:25:41.527911 <6>[ 5.413382] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10854 23:25:41.538774 <6>[ 5.424257] tun: Universal TUN/TAP device driver, 1.6
10855 23:25:41.542214 <6>[ 5.430330] thunder_xcv, ver 1.0
10856 23:25:41.545580 <6>[ 5.433834] thunder_bgx, ver 1.0
10857 23:25:41.548842 <6>[ 5.437330] nicpf, ver 1.0
10858 23:25:41.559193 <6>[ 5.441371] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10859 23:25:41.562700 <6>[ 5.448846] hns3: Copyright (c) 2017 Huawei Corporation.
10860 23:25:41.569221 <6>[ 5.454433] hclge is initializing
10861 23:25:41.572367 <6>[ 5.458007] e1000: Intel(R) PRO/1000 Network Driver
10862 23:25:41.579473 <6>[ 5.463136] e1000: Copyright (c) 1999-2006 Intel Corporation.
10863 23:25:41.582386 <6>[ 5.469152] e1000e: Intel(R) PRO/1000 Network Driver
10864 23:25:41.588616 <6>[ 5.474368] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10865 23:25:41.595262 <6>[ 5.480552] igb: Intel(R) Gigabit Ethernet Network Driver
10866 23:25:41.601759 <6>[ 5.486202] igb: Copyright (c) 2007-2014 Intel Corporation.
10867 23:25:41.608404 <6>[ 5.492038] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10868 23:25:41.615319 <6>[ 5.498556] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10869 23:25:41.618555 <6>[ 5.505029] sky2: driver version 1.30
10870 23:25:41.624997 <6>[ 5.510036] VFIO - User Level meta-driver version: 0.3
10871 23:25:41.632657 <6>[ 5.518304] usbcore: registered new interface driver usb-storage
10872 23:25:41.639335 <6>[ 5.524756] usbcore: registered new device driver onboard-usb-hub
10873 23:25:41.648154 <6>[ 5.533932] mt6397-rtc mt6359-rtc: registered as rtc0
10874 23:25:41.658003 <6>[ 5.539396] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:25:42 UTC (1712186742)
10875 23:25:41.661274 <6>[ 5.548957] i2c_dev: i2c /dev entries driver
10876 23:25:41.678503 <6>[ 5.560719] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10877 23:25:41.684887 <4>[ 5.569461] cpu cpu0: supply cpu not found, using dummy regulator
10878 23:25:41.691600 <4>[ 5.575885] cpu cpu1: supply cpu not found, using dummy regulator
10879 23:25:41.698204 <4>[ 5.582306] cpu cpu2: supply cpu not found, using dummy regulator
10880 23:25:41.704492 <4>[ 5.588706] cpu cpu3: supply cpu not found, using dummy regulator
10881 23:25:41.711559 <4>[ 5.595101] cpu cpu4: supply cpu not found, using dummy regulator
10882 23:25:41.718032 <4>[ 5.601495] cpu cpu5: supply cpu not found, using dummy regulator
10883 23:25:41.724714 <4>[ 5.607893] cpu cpu6: supply cpu not found, using dummy regulator
10884 23:25:41.731048 <4>[ 5.614306] cpu cpu7: supply cpu not found, using dummy regulator
10885 23:25:41.749592 <6>[ 5.634905] cpu cpu0: EM: created perf domain
10886 23:25:41.752734 <6>[ 5.639831] cpu cpu4: EM: created perf domain
10887 23:25:41.759916 <6>[ 5.645444] sdhci: Secure Digital Host Controller Interface driver
10888 23:25:41.766597 <6>[ 5.651876] sdhci: Copyright(c) Pierre Ossman
10889 23:25:41.773200 <6>[ 5.656824] Synopsys Designware Multimedia Card Interface Driver
10890 23:25:41.779799 <6>[ 5.663473] sdhci-pltfm: SDHCI platform and OF driver helper
10891 23:25:41.783119 <6>[ 5.663543] mmc0: CQHCI version 5.10
10892 23:25:41.789704 <6>[ 5.673793] ledtrig-cpu: registered to indicate activity on CPUs
10893 23:25:41.796310 <6>[ 5.680820] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10894 23:25:41.802812 <6>[ 5.687872] usbcore: registered new interface driver usbhid
10895 23:25:41.806182 <6>[ 5.693699] usbhid: USB HID core driver
10896 23:25:41.815966 <6>[ 5.697917] spi_master spi0: will run message pump with realtime priority
10897 23:25:41.854732 <6>[ 5.733452] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10898 23:25:41.873210 <6>[ 5.748662] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10899 23:25:41.880425 <6>[ 5.763381] cros-ec-spi spi0.0: Chrome EC device registered
10900 23:25:41.883535 <6>[ 5.769406] mmc0: Command Queue Engine enabled
10901 23:25:41.890429 <6>[ 5.774171] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10902 23:25:41.897045 <6>[ 5.781976] mmcblk0: mmc0:0001 DA4128 116 GiB
10903 23:25:41.905604 <6>[ 5.791017] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10904 23:25:41.912824 <6>[ 5.798337] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10905 23:25:41.922942 <6>[ 5.803805] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10906 23:25:41.929548 <6>[ 5.804312] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10907 23:25:41.932917 <6>[ 5.814570] NET: Registered PF_PACKET protocol family
10908 23:25:41.939478 <6>[ 5.818994] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10909 23:25:41.942776 <6>[ 5.823752] 9pnet: Installing 9P2000 support
10910 23:25:41.949206 <5>[ 5.834732] Key type dns_resolver registered
10911 23:25:41.952921 <6>[ 5.839710] registered taskstats version 1
10912 23:25:41.959204 <5>[ 5.844094] Loading compiled-in X.509 certificates
10913 23:25:41.988789 <4>[ 5.867543] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10914 23:25:41.998812 <4>[ 5.878524] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10915 23:25:42.005345 <3>[ 5.889071] debugfs: File 'uA_load' in directory '/' already present!
10916 23:25:42.012179 <3>[ 5.895780] debugfs: File 'min_uV' in directory '/' already present!
10917 23:25:42.018621 <3>[ 5.902399] debugfs: File 'max_uV' in directory '/' already present!
10918 23:25:42.025538 <3>[ 5.909015] debugfs: File 'constraint_flags' in directory '/' already present!
10919 23:25:42.037355 <3>[ 5.919338] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10920 23:25:42.050545 <6>[ 5.935682] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10921 23:25:42.056932 <6>[ 5.942498] xhci-mtk 11200000.usb: xHCI Host Controller
10922 23:25:42.063805 <6>[ 5.948003] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10923 23:25:42.073766 <6>[ 5.955852] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10924 23:25:42.080389 <6>[ 5.965284] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10925 23:25:42.086996 <6>[ 5.971451] xhci-mtk 11200000.usb: xHCI Host Controller
10926 23:25:42.093605 <6>[ 5.976945] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10927 23:25:42.100182 <6>[ 5.984596] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10928 23:25:42.107113 <6>[ 5.992427] hub 1-0:1.0: USB hub found
10929 23:25:42.110428 <6>[ 5.996451] hub 1-0:1.0: 1 port detected
10930 23:25:42.116875 <6>[ 6.000745] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10931 23:25:42.124070 <6>[ 6.009477] hub 2-0:1.0: USB hub found
10932 23:25:42.127145 <6>[ 6.013500] hub 2-0:1.0: 1 port detected
10933 23:25:42.134859 <6>[ 6.020363] mtk-msdc 11f70000.mmc: Got CD GPIO
10934 23:25:42.148032 <6>[ 6.030401] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10935 23:25:42.154756 <6>[ 6.038436] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10936 23:25:42.164573 <4>[ 6.046345] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10937 23:25:42.174506 <6>[ 6.055896] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10938 23:25:42.181203 <6>[ 6.063974] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10939 23:25:42.187956 <6>[ 6.072001] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10940 23:25:42.197896 <6>[ 6.079923] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10941 23:25:42.204614 <6>[ 6.087743] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10942 23:25:42.214303 <6>[ 6.095558] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10943 23:25:42.224313 <6>[ 6.105951] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10944 23:25:42.231044 <6>[ 6.114311] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10945 23:25:42.241049 <6>[ 6.122655] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10946 23:25:42.247592 <6>[ 6.130993] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10947 23:25:42.257235 <6>[ 6.139331] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10948 23:25:42.263934 <6>[ 6.147670] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10949 23:25:42.274125 <6>[ 6.156007] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10950 23:25:42.283823 <6>[ 6.164344] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10951 23:25:42.290321 <6>[ 6.172682] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10952 23:25:42.300234 <6>[ 6.181020] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10953 23:25:42.306991 <6>[ 6.189358] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10954 23:25:42.316703 <6>[ 6.197698] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10955 23:25:42.323549 <6>[ 6.206037] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10956 23:25:42.333384 <6>[ 6.214374] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10957 23:25:42.339839 <6>[ 6.222720] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10958 23:25:42.346720 <6>[ 6.231464] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10959 23:25:42.353346 <6>[ 6.238383] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10960 23:25:42.359544 <6>[ 6.245147] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10961 23:25:42.366586 <6>[ 6.251913] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10962 23:25:42.376779 <6>[ 6.258842] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10963 23:25:42.383485 <6>[ 6.265704] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10964 23:25:42.393109 <6>[ 6.274833] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10965 23:25:42.403047 <6>[ 6.283952] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10966 23:25:42.412632 <6>[ 6.293246] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10967 23:25:42.422458 <6>[ 6.302712] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10968 23:25:42.429004 <6>[ 6.312179] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10969 23:25:42.439055 <6>[ 6.321297] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10970 23:25:42.449072 <6>[ 6.330763] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10971 23:25:42.459260 <6>[ 6.339902] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10972 23:25:42.469022 <6>[ 6.349197] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10973 23:25:42.478957 <6>[ 6.359357] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10974 23:25:42.488942 <6>[ 6.370869] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10975 23:25:42.541366 <6>[ 6.423609] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10976 23:25:42.696152 <6>[ 6.581433] hub 1-1:1.0: USB hub found
10977 23:25:42.699225 <6>[ 6.585974] hub 1-1:1.0: 4 ports detected
10978 23:25:42.709278 <6>[ 6.594557] hub 1-1:1.0: USB hub found
10979 23:25:42.712329 <6>[ 6.598944] hub 1-1:1.0: 4 ports detected
10980 23:25:42.821345 <6>[ 6.703807] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10981 23:25:42.848298 <6>[ 6.733755] hub 2-1:1.0: USB hub found
10982 23:25:42.851412 <6>[ 6.738286] hub 2-1:1.0: 3 ports detected
10983 23:25:42.860397 <6>[ 6.745983] hub 2-1:1.0: USB hub found
10984 23:25:42.863763 <6>[ 6.750352] hub 2-1:1.0: 3 ports detected
10985 23:25:43.036863 <6>[ 6.919649] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10986 23:25:43.169016 <6>[ 7.054481] hub 1-1.4:1.0: USB hub found
10987 23:25:43.172210 <6>[ 7.059024] hub 1-1.4:1.0: 2 ports detected
10988 23:25:43.181140 <6>[ 7.066673] hub 1-1.4:1.0: USB hub found
10989 23:25:43.184216 <6>[ 7.071290] hub 1-1.4:1.0: 2 ports detected
10990 23:25:43.249463 <6>[ 7.131665] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10991 23:25:43.481205 <6>[ 7.363650] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10992 23:25:43.673135 <6>[ 7.555632] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10993 23:25:54.782692 <6>[ 18.672660] ALSA device list:
10994 23:25:54.788965 <6>[ 18.675948] No soundcards found.
10995 23:25:54.796946 <6>[ 18.683880] Freeing unused kernel memory: 8448K
10996 23:25:54.800145 <6>[ 18.689355] Run /init as init process
10997 23:25:54.839572 <6>[ 18.725902] NET: Registered PF_INET6 protocol family
10998 23:25:54.845849 <6>[ 18.732070] Segment Routing with IPv6
10999 23:25:54.849537 <6>[ 18.736016] In-situ OAM (IOAM) with IPv6
11000 23:25:54.891665 <30>[ 18.751908] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
11001 23:25:54.898402 <30>[ 18.785058] systemd[1]: Detected architecture arm64.
11002 23:25:54.898931
11003 23:25:54.904874 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
11004 23:25:54.905376
11005 23:25:54.905958
11006 23:25:54.920632 <30>[ 18.807666] systemd[1]: Hostname set to <debian-bookworm-arm64>.
11007 23:25:55.072175 <30>[ 18.955795] systemd[1]: Queued start job for default target graphical.target.
11008 23:25:55.106095 <30>[ 18.989593] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
11009 23:25:55.112573 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
11010 23:25:55.113016
11011 23:25:55.133000 <30>[ 19.016525] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
11012 23:25:55.142773 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
11013 23:25:55.143336
11014 23:25:55.161879 <30>[ 19.045223] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
11015 23:25:55.171696 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
11016 23:25:55.172225
11017 23:25:55.189540 <30>[ 19.073014] systemd[1]: Created slice user.slice - User and Session Slice.
11018 23:25:55.195992 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
11019 23:25:55.196414
11020 23:25:55.220069 <30>[ 19.100312] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
11021 23:25:55.230004 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
11022 23:25:55.230433
11023 23:25:55.247518 <30>[ 19.127806] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
11024 23:25:55.253954 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
11025 23:25:55.254063
11026 23:25:55.282237 <30>[ 19.156202] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
11027 23:25:55.292282 <30>[ 19.176164] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
11028 23:25:55.298664 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
11029 23:25:55.298745
11030 23:25:55.315905 <30>[ 19.200015] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
11031 23:25:55.325912 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
11032 23:25:55.326002
11033 23:25:55.343627 <30>[ 19.227742] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
11034 23:25:55.353792 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
11035 23:25:55.353875
11036 23:25:55.368632 <30>[ 19.256133] systemd[1]: Reached target paths.target - Path Units.
11037 23:25:55.376074 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
11038 23:25:55.379024
11039 23:25:55.396738 <30>[ 19.280103] systemd[1]: Reached target remote-fs.target - Remote File Systems.
11040 23:25:55.403026 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
11041 23:25:55.403448
11042 23:25:55.416525 <30>[ 19.303618] systemd[1]: Reached target slices.target - Slice Units.
11043 23:25:55.426728 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
11044 23:25:55.427149
11045 23:25:55.441259 <30>[ 19.328148] systemd[1]: Reached target swap.target - Swaps.
11046 23:25:55.447717 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
11047 23:25:55.448136
11048 23:25:55.468871 <30>[ 19.352148] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
11049 23:25:55.478286 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
11050 23:25:55.478712
11051 23:25:55.496991 <30>[ 19.380569] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
11052 23:25:55.506970 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
11053 23:25:55.507394
11054 23:25:55.526483 <30>[ 19.409841] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
11055 23:25:55.536157 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
11056 23:25:55.536735
11057 23:25:55.552779 <30>[ 19.436356] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
11058 23:25:55.562495 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
11059 23:25:55.562919
11060 23:25:55.580595 <30>[ 19.464333] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
11061 23:25:55.587245 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
11062 23:25:55.587664
11063 23:25:55.604873 <30>[ 19.488270] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
11064 23:25:55.614562 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
11065 23:25:55.615084
11066 23:25:55.632637 <30>[ 19.516102] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
11067 23:25:55.642151 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
11068 23:25:55.642598
11069 23:25:55.684370 <30>[ 19.567815] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
11070 23:25:55.691266 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
11071 23:25:55.692052
11072 23:25:55.709998 <30>[ 19.593515] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
11073 23:25:55.716538 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
11074 23:25:55.717054
11075 23:25:55.738996 <30>[ 19.622439] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
11076 23:25:55.745251 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
11077 23:25:55.745745
11078 23:25:55.770790 <30>[ 19.647825] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
11079 23:25:55.808404 <30>[ 19.692216] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
11080 23:25:55.818643 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
11081 23:25:55.819124
11082 23:25:55.841241 <30>[ 19.724754] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
11083 23:25:55.847656 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
11084 23:25:55.848136
11085 23:25:55.873461 <30>[ 19.757248] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
11086 23:25:55.883652 Startin<6>[ 19.766634] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
11087 23:25:55.890149 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
11088 23:25:55.890726
11089 23:25:55.913382 <30>[ 19.796943] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
11090 23:25:55.919797 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
11091 23:25:55.920409
11092 23:25:55.945538 <30>[ 19.829240] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
11093 23:25:55.955269 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
11094 23:25:55.955728
11095 23:25:55.992810 <30>[ 19.876419] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
11096 23:25:55.999111 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
11097 23:25:55.999576
11098 23:25:56.029033 <30>[ 19.912527] systemd[1]: Starting systemd-journald.service - Journal Service...
11099 23:25:56.035328 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
11100 23:25:56.035787
11101 23:25:56.054373 <30>[ 19.938314] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
11102 23:25:56.061060 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
11103 23:25:56.061577
11104 23:25:56.088183 <30>[ 19.968587] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
11105 23:25:56.095017 Starting [0;1;39msystemd-network-g… units from Kernel command line...
11106 23:25:56.095453
11107 23:25:56.114871 <30>[ 19.998624] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
11108 23:25:56.124688 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
11109 23:25:56.125271
11110 23:25:56.147563 <30>[ 20.031163] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
11111 23:25:56.154331 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
11112 23:25:56.154761
11113 23:25:56.177952 <30>[ 20.061446] systemd[1]: Started systemd-journald.service - Journal Service.
11114 23:25:56.184377 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11115 23:25:56.184803
11116 23:25:56.207590 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
11117 23:25:56.208058
11118 23:25:56.225156 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
11119 23:25:56.225783
11120 23:25:56.245136 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11121 23:25:56.245926
11122 23:25:56.265023 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11123 23:25:56.265452
11124 23:25:56.285385 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11125 23:25:56.285470
11126 23:25:56.311065 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11127 23:25:56.311150
11128 23:25:56.334845 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11129 23:25:56.334936
11130 23:25:56.354925 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11131 23:25:56.355008
11132 23:25:56.375362 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11133 23:25:56.375445
11134 23:25:56.397227 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11135 23:25:56.397311
11136 23:25:56.416840 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11137 23:25:56.416928
11138 23:25:56.438346 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
11139 23:25:56.438430
11140 23:25:56.456350 See 'systemctl status systemd-remount-fs.service' for details.
11141 23:25:56.456459
11142 23:25:56.466752 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11143 23:25:56.466835
11144 23:25:56.490239 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11145 23:25:56.490324
11146 23:25:56.540806 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11147 23:25:56.541168
11148 23:25:56.565546 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11149 23:25:56.565977
11150 23:25:56.576281 <46>[ 20.459836] systemd-journald[192]: Received client request to flush runtime journal.
11151 23:25:56.590193 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11152 23:25:56.590728
11153 23:25:56.613576 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11154 23:25:56.614135
11155 23:25:56.636291 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11156 23:25:56.636876
11157 23:25:56.662717 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11158 23:25:56.663262
11159 23:25:56.685646 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11160 23:25:56.686224
11161 23:25:56.705667 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11162 23:25:56.706251
11163 23:25:56.725287 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11164 23:25:56.725878
11165 23:25:56.745841 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11166 23:25:56.746413
11167 23:25:56.793616 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11168 23:25:56.794190
11169 23:25:56.818156 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11170 23:25:56.818704
11171 23:25:56.836799 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11172 23:25:56.837355
11173 23:25:56.856646 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11174 23:25:56.857220
11175 23:25:56.905074 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11176 23:25:56.905680
11177 23:25:56.930864 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11178 23:25:56.931429
11179 23:25:56.954898 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11180 23:25:56.955492
11181 23:25:57.003088 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11182 23:25:57.003654
11183 23:25:57.024684 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11184 23:25:57.025256
11185 23:25:57.043073 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11186 23:25:57.043701
11187 23:25:57.078073 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11188 23:25:57.078810
11189 23:25:57.101939 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11190 23:25:57.102506
11191 23:25:57.133812 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11192 23:25:57.134369
11193 23:25:57.245318 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11194 23:25:57.245921
11195 23:25:57.264927 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11196 23:25:57.265520
11197 23:25:57.285083 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11198 23:25:57.285666
11199 23:25:57.307392 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11200 23:25:57.307938
11201 23:25:57.324751 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11202 23:25:57.325271
11203 23:25:57.341934 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11204 23:25:57.342456
11205 23:25:57.360681 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11206 23:25:57.361237
11207 23:25:57.380416 <6>[ 21.263982] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11208 23:25:57.386979 <3>[ 21.271192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11209 23:25:57.396800 <6>[ 21.271622] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11210 23:25:57.406771 <6>[ 21.271630] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11211 23:25:57.413091 <3>[ 21.297287] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11212 23:25:57.420002 <3>[ 21.305399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11213 23:25:57.429716 [[0;32m OK [<3>[ 21.313675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11214 23:25:57.439729 0m] Reached targ<3>[ 21.323183] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11215 23:25:57.446604 <6>[ 21.331404] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11216 23:25:57.456359 <3>[ 21.332503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11217 23:25:57.466417 et [0;1;39mbasi<3>[ 21.347873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11218 23:25:57.475848 c.target[0m - B<3>[ 21.357340] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11219 23:25:57.476353 asic System.
11220 23:25:57.476689
11221 23:25:57.488781 <6>[ 21.375429] remoteproc remoteproc0: scp is available
11222 23:25:57.495485 <6>[ 21.381144] remoteproc remoteproc0: powering up scp
11223 23:25:57.502056 <6>[ 21.386302] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11224 23:25:57.508500 <6>[ 21.394907] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11225 23:25:57.518375 <3>[ 21.397736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11226 23:25:57.524933 <6>[ 21.404161] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11227 23:25:57.528273 <6>[ 21.409321] mc: Linux media interface: v0.10
11228 23:25:57.535100 <6>[ 21.416841] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11229 23:25:57.541708 <6>[ 21.428015] pci_bus 0000:00: root bus resource [bus 00-ff]
11230 23:25:57.551440 <4>[ 21.429437] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11231 23:25:57.554537 <4>[ 21.429437] Fallback method does not support PEC.
11232 23:25:57.561436 <6>[ 21.433769] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11233 23:25:57.571433 <6>[ 21.433772] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11234 23:25:57.578439 <6>[ 21.433808] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11235 23:25:57.588159 <3>[ 21.464782] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11236 23:25:57.594729 <6>[ 21.470730] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11237 23:25:57.604839 <3>[ 21.479747] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11238 23:25:57.607810 <6>[ 21.487105] pci 0000:00:00.0: supports D1 D2
11239 23:25:57.615372 <3>[ 21.495111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11240 23:25:57.621990 <6>[ 21.499620] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11241 23:25:57.631986 <3>[ 21.507825] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11242 23:25:57.638218 <3>[ 21.514697] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11243 23:25:57.648567 <6>[ 21.525924] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11244 23:25:57.654763 <6>[ 21.525983] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11245 23:25:57.661506 <6>[ 21.525992] remoteproc remoteproc0: remote processor scp is now up
11246 23:25:57.673340 <3>[ 21.557003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11247 23:25:57.679783 <4>[ 21.557153] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11248 23:25:57.689658 <3>[ 21.565124] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11249 23:25:57.696377 <3>[ 21.565130] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11250 23:25:57.706275 <3>[ 21.565137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11251 23:25:57.713013 <3>[ 21.565144] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11252 23:25:57.722584 <6>[ 21.565410] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11253 23:25:57.729357 <4>[ 21.573017] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11254 23:25:57.738966 <3>[ 21.590913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11255 23:25:57.749345 <6>[ 21.590992] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11256 23:25:57.762154 Starting [0;1;39mdbus.service[0m - D-Bus System Messa<6>[ 21.644517] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11257 23:25:57.762708 ge Bus...
11258 23:25:57.763046
11259 23:25:57.772134 <6>[ 21.657967] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11260 23:25:57.782316 <3>[ 21.663607] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11261 23:25:57.788677 <6>[ 21.664293] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11262 23:25:57.795302 <6>[ 21.676085] usbcore: registered new device driver r8152-cfgselector
11263 23:25:57.802224 <6>[ 21.680498] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11264 23:25:57.808697 <6>[ 21.680516] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11265 23:25:57.815463 <6>[ 21.702090] pci 0000:01:00.0: supports D1 D2
11266 23:25:57.821670 <6>[ 21.706615] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11267 23:25:57.833470 <6>[ 21.717170] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11268 23:25:57.846376 <6>[ 21.733435] videodev: Linux video capture interface: v2.00
11269 23:25:57.876062 <6>[ 21.759562] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11270 23:25:57.882556 <6>[ 21.766498] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11271 23:25:57.889237 <6>[ 21.774593] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11272 23:25:57.899401 <6>[ 21.782601] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11273 23:25:57.905664 <6>[ 21.790611] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11274 23:25:57.915897 <6>[ 21.798617] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11275 23:25:57.918823 <6>[ 21.806623] pci 0000:00:00.0: PCI bridge to [bus 01]
11276 23:25:57.922317 <6>[ 21.809084] Bluetooth: Core ver 2.22
11277 23:25:57.932297 <6>[ 21.811842] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11278 23:25:57.938822 <6>[ 21.825628] NET: Registered PF_BLUETOOTH protocol family
11279 23:25:57.945670 <6>[ 21.831885] Bluetooth: HCI device and connection manager initialized
11280 23:25:57.952464 <6>[ 21.839125] Bluetooth: HCI socket layer initialized
11281 23:25:57.958725 <6>[ 21.844740] Bluetooth: L2CAP socket layer initialized
11282 23:25:57.965131 Startin<6>[ 21.850240] Bluetooth: SCO socket layer initialized
11283 23:25:57.971924 <6>[ 21.850800] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11284 23:25:57.981749 g [0;1;39msyste<6>[ 21.859861] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11285 23:25:57.985303 md-logind.se…ice[0m - User Login Management...
11286 23:25:57.985897
11287 23:25:58.015218 <4>[ 21.898891] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11288 23:25:58.025121 <4>[ 21.908010] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11289 23:25:58.036468 <3>[ 21.919984] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11290 23:25:58.077515 <6>[ 21.960819] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11291 23:25:58.088404 <6>[ 21.974928] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11292 23:25:58.101634 <6>[ 21.975182] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11293 23:25:58.108327 <6>[ 21.994303] r8152 2-1.3:1.0 eth0: v1.12.13
11294 23:25:58.118417 <3>[ 21.999664] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11295 23:25:58.125246 <3>[ 22.000271] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
11296 23:25:58.131317 <6>[ 22.009359] usbcore: registered new interface driver uvcvideo
11297 23:25:58.137863 <6>[ 22.012978] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11298 23:25:58.144521 <6>[ 22.014963] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11299 23:25:58.148176 <6>[ 22.017480] usbcore: registered new interface driver btusb
11300 23:25:58.157848 <4>[ 22.018382] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11301 23:25:58.164253 <3>[ 22.018393] Bluetooth: hci0: Failed to load firmware file (-2)
11302 23:25:58.170940 <3>[ 22.018397] Bluetooth: hci0: Failed to set up firmware (-2)
11303 23:25:58.180846 <4>[ 22.018400] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11304 23:25:58.190910 <6>[ 22.068884] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11305 23:25:58.230574 <6>[ 22.092850] usbcore: registered new interface driver r8152
11306 23:25:58.240535 <5>[ 22.094321] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11307 23:25:58.247146 <5>[ 22.114308] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11308 23:25:58.253879 <5>[ 22.115317] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11309 23:25:58.263603 <4>[ 22.115583] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11310 23:25:58.266929 <6>[ 22.115610] cfg80211: failed to load regulatory.db
11311 23:25:58.276999 <6>[ 22.122579] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11312 23:25:58.283604 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11313 23:25:58.284056
11314 23:25:58.320388 <6>[ 22.189359] usbcore: registered new interface driver cdc_ether
11315 23:25:58.326631 <6>[ 22.191722] usbcore: registered new interface driver r8153_ecm
11316 23:25:58.342189 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11317 23:25:58.342705
11318 23:25:58.357567 <3>[ 22.241262] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11319 23:25:58.374017 <6>[ 22.257855] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11320 23:25:58.381078 [[0;32m OK [<6>[ 22.265777] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11321 23:25:58.387453 0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11322 23:25:58.387989
11323 23:25:58.404419 <3>[ 22.288159] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11324 23:25:58.411460 <6>[ 22.293847] mt7921e 0000:01:00.0: ASIC revision: 79610010
11325 23:25:58.418044 <6>[ 22.303540] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
11326 23:25:58.424314 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11327 23:25:58.424803
11328 23:25:58.443880 <3>[ 22.327758] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11329 23:25:58.457057 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11330 23:25:58.457620
11331 23:25:58.474078 <3>[ 22.357811] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11332 23:25:58.484012 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11333 23:25:58.484438
11334 23:25:58.506335 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11335 23:25:58.506849
11336 23:25:58.516376 <6>[ 22.399993] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11337 23:25:58.516980 <6>[ 22.399993]
11338 23:25:58.551001 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11339 23:25:58.551522
11340 23:25:58.575950 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11341 23:25:58.576475
11342 23:25:58.596175 <46>[ 22.467587] systemd-journald[192]: Data hash table of /var/log/journal/6cfa758ce87d4acd800e1258fdce5dda/system.journal has a fill level at 75.1 (1538 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11343 23:25:58.612361 <46>[ 22.488809] systemd-journald[192]: /var/log/journal/6cfa758ce87d4acd800e1258fdce5dda/system.journal: Journal header limits reached or header out-of-date, rotating.
11344 23:25:58.618569 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11345 23:25:58.619077
11346 23:25:58.636399 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11347 23:25:58.636828
11348 23:25:58.652631 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11349 23:25:58.653261
11350 23:25:58.705153 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11351 23:25:58.705707
11352 23:25:58.729292 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11353 23:25:58.729840
11354 23:25:58.756736 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11355 23:25:58.757240
11356 23:25:58.783942 <6>[ 22.668074] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11357 23:25:58.845277 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11358 23:25:58.845957
11359 23:25:58.865265 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11360 23:25:58.865747
11361 23:25:58.888305 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11362 23:25:58.888736
11363 23:25:58.930960
11364 23:25:58.931382
11365 23:25:58.934355 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11366 23:25:58.934810
11367 23:25:58.937336 debian-bookworm-arm64 login: root (automatic login)
11368 23:25:58.937858
11369 23:25:58.938192
11370 23:25:58.957800 Linux debian-bookworm-arm64 6.1.83-cip18 #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024 aarch64
11371 23:25:58.958274
11372 23:25:58.964165 The programs included with the Debian GNU/Linux system are free software;
11373 23:25:58.970568 the exact distribution terms for each program are described in the
11374 23:25:58.973933 individual files in /usr/share/doc/*/copyright.
11375 23:25:58.974348
11376 23:25:58.980873 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11377 23:25:58.983822 permitted by applicable law.
11378 23:25:58.985231 Matched prompt #10: / #
11380 23:25:58.986380 Setting prompt string to ['/ #']
11381 23:25:58.986995 end: 2.2.5.1 login-action (duration 00:00:24) [common]
11383 23:25:58.988365 end: 2.2.5 auto-login-action (duration 00:00:24) [common]
11384 23:25:58.988877 start: 2.2.6 expect-shell-connection (timeout 00:01:16) [common]
11385 23:25:58.989275 Setting prompt string to ['/ #']
11386 23:25:58.989625 Forcing a shell prompt, looking for ['/ #']
11388 23:25:59.040494 / #
11389 23:25:59.041117 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11390 23:25:59.041570 Waiting using forced prompt support (timeout 00:02:30)
11391 23:25:59.046143
11392 23:25:59.046953 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11393 23:25:59.047439 start: 2.2.7 export-device-env (timeout 00:01:16) [common]
11394 23:25:59.047907 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11395 23:25:59.048396 end: 2.2 depthcharge-retry (duration 00:03:44) [common]
11396 23:25:59.048956 end: 2 depthcharge-action (duration 00:03:44) [common]
11397 23:25:59.049451 start: 3 lava-test-retry (timeout 00:05:00) [common]
11398 23:25:59.049948 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11399 23:25:59.050366 Using namespace: common
11401 23:25:59.151406 / # #
11402 23:25:59.151929 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11403 23:25:59.157835 #
11404 23:25:59.158634 Using /lava-13248456
11406 23:25:59.259768 / # export SHELL=/bin/sh
11407 23:25:59.266330 export SHELL=/bin/sh
11409 23:25:59.367748 / # . /lava-13248456/environment
11410 23:25:59.373719 . /lava-13248456/environment
11412 23:25:59.475282 / # /lava-13248456/bin/lava-test-runner /lava-13248456/0
11413 23:25:59.475945 Test shell timeout: 10s (minimum of the action and connection timeout)
11414 23:25:59.481463 /lava-13248456/bin/lava-test-runner /lava-13248456/0
11415 23:25:59.500504 + export TESTRUN_ID=0_sleep
11416 23:25:59.503767 + cd /lava-13248456/0/tests/0_sleep
11417 23:25:59.507144 + cat uuid
11418 23:25:59.507576 + UUID=13248456_1.5.2.3.1
11419 23:25:59.510185 + set +x
11420 23:25:59.513620 <LAVA_SIGNAL_STARTRUN 0_sleep 13248456_1.5.2.3.1>
11421 23:25:59.514257 Received signal: <STARTRUN> 0_sleep 13248456_1.5.2.3.1
11422 23:25:59.514607 Starting test lava.0_sleep (13248456_1.5.2.3.1)
11423 23:25:59.515000 Skipping test definition patterns.
11424 23:25:59.517223 + ./config/lava/sleep/sleep.sh mem
11425 23:25:59.520390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11426 23:25:59.521108 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11428 23:25:59.526795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11429 23:25:59.527561 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11431 23:25:59.529961 rtcwake: assuming RTC uses UTC ...
11432 23:25:59.536768 rtcwake: wakeup from "mem" using rt<6>[ 23.425745] PM: suspend entry (deep)
11433 23:25:59.543409 c0 at Wed Apr 3<6>[ 23.429723] Filesystems sync: 0.000 seconds
11434 23:25:59.543893 23:26:06 2024
11435 23:25:59.550044 <6>[ 23.437487] Freezing user space processes
11436 23:25:59.560099 <6>[ 23.444020] Freezing user space processes completed (elapsed 0.001 seconds)
11437 23:25:59.563464 <6>[ 23.451261] OOM killer disabled.
11438 23:25:59.566747 <6>[ 23.454749] Freezing remaining freezable tasks
11439 23:25:59.576587 <6>[ 23.460829] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11440 23:25:59.583414 <6>[ 23.468499] printk: Suspending console(s) (use no_console_suspend to debug)
11441 23:26:05.394628 <4>[ 23.497931] ieee80211 phy0: PM: parent 0000:01:00.0 should not be sleeping
11442 23:26:05.401261 <4>[ 23.498713] net wlan0: PM: parent 0000:01:00.0 should not be sleeping
11443 23:26:05.404563 <6>[ 23.610502] Disabling non-boot CPUs ...
11444 23:26:05.407906 <4>[ 23.611476] IRQ282: set affinity failed(-22).
11445 23:26:05.414646 <4>[ 23.611493] IRQ283: set affinity failed(-22).
11446 23:26:05.417662 <6>[ 23.611579] psci: CPU1 killed (polled 0 ms)
11447 23:26:05.421098 <4>[ 23.612871] IRQ282: set affinity failed(-22).
11448 23:26:05.427851 <4>[ 23.612884] IRQ283: set affinity failed(-22).
11449 23:26:05.431311 <6>[ 23.612954] psci: CPU2 killed (polled 0 ms)
11450 23:26:05.437978 <4>[ 23.614246] IRQ282: set affinity failed(-22).
11451 23:26:05.441308 <4>[ 23.614258] IRQ283: set affinity failed(-22).
11452 23:26:05.444568 <6>[ 23.614332] psci: CPU3 killed (polled 0 ms)
11453 23:26:05.451105 <4>[ 23.615233] IRQ282: set affinity failed(-22).
11454 23:26:05.454335 <4>[ 23.615239] IRQ283: set affinity failed(-22).
11455 23:26:05.457776 <6>[ 23.615279] psci: CPU4 killed (polled 0 ms)
11456 23:26:05.464635 <4>[ 23.616254] IRQ282: set affinity failed(-22).
11457 23:26:05.467836 <4>[ 23.616262] IRQ283: set affinity failed(-22).
11458 23:26:05.474236 <6>[ 23.616303] psci: CPU5 killed (polled 0 ms)
11459 23:26:05.477392 <6>[ 23.617518] psci: CPU6 killed (polled 0 ms)
11460 23:26:05.480740 <6>[ 23.618477] psci: CPU7 killed (polled 0 ms)
11461 23:26:05.483689 <6>[ 23.619156] Enabling non-boot CPUs ...
11462 23:26:05.490710 <6>[ 23.619403] Detected VIPT I-cache on CPU1
11463 23:26:05.497546 <6>[ 23.619496] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11464 23:26:05.503714 <6>[ 23.619561] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11465 23:26:05.507296 <6>[ 23.620166] CPU1 is up
11466 23:26:05.510692 <6>[ 23.620328] Detected VIPT I-cache on CPU2
11467 23:26:05.517256 <6>[ 23.620390] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11468 23:26:05.523852 <6>[ 23.620435] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11469 23:26:05.527030 <6>[ 23.620935] CPU2 is up
11470 23:26:05.530837 <6>[ 23.621084] Detected VIPT I-cache on CPU3
11471 23:26:05.540390 <6>[ 23.621147] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11472 23:26:05.546933 <6>[ 23.621190] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11473 23:26:05.547449 <6>[ 23.621743] CPU3 is up
11474 23:26:05.553864 <6>[ 23.621872] CPU features: detected: Hardware dirty bit management
11475 23:26:05.560265 <6>[ 23.621895] Detected PIPT I-cache on CPU4
11476 23:26:05.567189 <6>[ 23.621926] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11477 23:26:05.574062 <6>[ 23.621950] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11478 23:26:05.577099 <6>[ 23.622330] CPU4 is up
11479 23:26:05.580311 <6>[ 23.622474] Detected PIPT I-cache on CPU5
11480 23:26:05.586698 <6>[ 23.622509] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11481 23:26:05.593620 <6>[ 23.622533] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11482 23:26:05.597203 <6>[ 23.622861] CPU5 is up
11483 23:26:05.600086 <6>[ 23.623006] Detected PIPT I-cache on CPU6
11484 23:26:05.606865 <6>[ 23.623040] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11485 23:26:05.613526 <6>[ 23.623064] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11486 23:26:05.616735 <6>[ 23.623430] CPU6 is up
11487 23:26:05.623389 <6>[ 23.623575] Detected PIPT I-cache on CPU7
11488 23:26:05.630151 <6>[ 23.623618] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11489 23:26:05.636866 <6>[ 23.623641] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11490 23:26:05.640104 <6>[ 23.623993] CPU7 is up
11491 23:26:05.646706 <4>[ 23.764651] typec port0-partner: PM: parent port0 should not be sleeping
11492 23:26:05.650036 <6>[ 24.225003] OOM killer enabled.
11493 23:26:05.653581 <6>[ 24.228394] Restarting tasks ... done.
11494 23:26:05.659976 <5>[ 24.232754] random: crng reseeded on system resumption
11495 23:26:05.663178 <6>[ 24.238892] PM: suspend exit
11496 23:26:05.671376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass>
11497 23:26:05.672277 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=pass
11499 23:26:05.674816 rtcwake: assuming RTC uses UTC ...
11500 23:26:05.681172 rtcwake: wakeup from "mem" using rtc0 at Wed Apr 3 23:26:12 2024
11501 23:26:05.688885 <6>[ 24.263563] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11502 23:26:05.692337 <6>[ 24.269427] PM: suspend entry (deep)
11503 23:26:05.699321 <6>[ 24.269500] Filesystems sync: 0.000 seconds
11504 23:26:05.702844 <6>[ 24.278374] Freezing user space processes
11505 23:26:05.740264 <6>[ 24.311538] Freezing user space processes completed (elapsed 0.028 seconds)
11506 23:26:05.743887 <6>[ 24.318812] OOM killer disabled.
11507 23:26:05.747175 <6>[ 24.322317] Freezing remaining freezable tasks
11508 23:26:05.757158 <6>[ 24.328325] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11509 23:26:05.763654 <6>[ 24.336005] printk: Suspending console(s) (use no_console_suspend to debug)
11510 23:26:11.389684 <6>[ 24.437003] Disabling non-boot CPUs ...
11511 23:26:11.392853 <6>[ 24.439007] psci: CPU1 killed (polled 0 ms)
11512 23:26:11.396261 <6>[ 24.441216] psci: CPU2 killed (polled 0 ms)
11513 23:26:11.402847 <6>[ 24.443219] psci: CPU3 killed (polled 0 ms)
11514 23:26:11.406386 <6>[ 24.444026] psci: CPU4 killed (polled 0 ms)
11515 23:26:11.409370 <6>[ 24.444863] psci: CPU5 killed (polled 0 ms)
11516 23:26:11.416572 <6>[ 24.446728] psci: CPU6 killed (polled 0 ms)
11517 23:26:11.419362 <6>[ 24.447391] psci: CPU7 killed (polled 0 ms)
11518 23:26:11.423103 <6>[ 24.447816] Enabling non-boot CPUs ...
11519 23:26:11.429545 <6>[ 24.448055] Detected VIPT I-cache on CPU1
11520 23:26:11.436024 <6>[ 24.448144] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11521 23:26:11.442784 <6>[ 24.448209] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11522 23:26:11.445995 <6>[ 24.448818] CPU1 is up
11523 23:26:11.449376 <6>[ 24.448962] Detected VIPT I-cache on CPU2
11524 23:26:11.456335 <6>[ 24.449019] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11525 23:26:11.462736 <6>[ 24.449060] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11526 23:26:11.466355 <6>[ 24.449552] CPU2 is up
11527 23:26:11.469435 <6>[ 24.449690] Detected VIPT I-cache on CPU3
11528 23:26:11.476254 <6>[ 24.449748] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11529 23:26:11.482783 <6>[ 24.449789] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11530 23:26:11.486049 <6>[ 24.450302] CPU3 is up
11531 23:26:11.492453 <6>[ 24.450449] Detected PIPT I-cache on CPU4
11532 23:26:11.498908 <6>[ 24.450488] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11533 23:26:11.506005 <6>[ 24.450515] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11534 23:26:11.509324 <6>[ 24.450914] CPU4 is up
11535 23:26:11.512647 <6>[ 24.451061] Detected PIPT I-cache on CPU5
11536 23:26:11.519403 <6>[ 24.451101] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11537 23:26:11.525849 <6>[ 24.451127] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11538 23:26:11.529271 <6>[ 24.451547] CPU5 is up
11539 23:26:11.532329 <6>[ 24.451699] Detected PIPT I-cache on CPU6
11540 23:26:11.539191 <6>[ 24.451740] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11541 23:26:11.545826 <6>[ 24.451766] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11542 23:26:11.549259 <6>[ 24.452170] CPU6 is up
11543 23:26:11.552221 <6>[ 24.452315] Detected PIPT I-cache on CPU7
11544 23:26:11.562082 <6>[ 24.452355] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11545 23:26:11.568896 <6>[ 24.452382] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11546 23:26:11.569320 <6>[ 24.452796] CPU7 is up
11547 23:26:11.576016 <6>[ 24.979795] OOM killer enabled.
11548 23:26:11.579399 <6>[ 24.983185] Restarting tasks ... done.
11549 23:26:11.582496 <5>[ 24.987552] random: crng reseeded on system resumption
11550 23:26:11.586421 <6>[ 24.993808] PM: suspend exit
11551 23:26:11.597471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=pass>
11552 23:26:11.598344 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=pass
11554 23:26:11.600412 rtcwake: assuming RTC uses UTC ...
11555 23:26:11.607115 rtcwake: wakeup from "mem" using rtc0 at Wed Apr 3 23:26:18 2024
11556 23:26:11.620400 <6>[ 25.024233] PM: suspend entry (deep)
11557 23:26:11.623782 <6>[ 25.028098] Filesystems sync: 0.000 seconds
11558 23:26:11.626893 <6>[ 25.032838] Freezing user space processes
11559 23:26:11.637857 <6>[ 25.038441] Freezing user space processes completed (elapsed 0.001 seconds)
11560 23:26:11.641105 <6>[ 25.045660] OOM killer disabled.
11561 23:26:11.644182 <6>[ 25.049139] Freezing remaining freezable tasks
11562 23:26:11.654600 <6>[ 25.055049] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11563 23:26:11.660986 <6>[ 25.062718] printk: Suspending console(s) (use no_console_suspend to debug)
11564 23:26:17.400441 <6>[ 25.144220] Disabling non-boot CPUs ...
11565 23:26:17.403392 <6>[ 25.145221] psci: CPU1 killed (polled 0 ms)
11566 23:26:17.406646 <6>[ 25.147263] psci: CPU2 killed (polled 4 ms)
11567 23:26:17.413288 <6>[ 25.149213] psci: CPU3 killed (polled 0 ms)
11568 23:26:17.416428 <6>[ 25.149857] psci: CPU4 killed (polled 0 ms)
11569 23:26:17.419794 <6>[ 25.150515] psci: CPU5 killed (polled 0 ms)
11570 23:26:17.426205 <6>[ 25.151055] psci: CPU6 killed (polled 0 ms)
11571 23:26:17.429703 <6>[ 25.151843] psci: CPU7 killed (polled 0 ms)
11572 23:26:17.433354 <6>[ 25.152237] Enabling non-boot CPUs ...
11573 23:26:17.440372 <6>[ 25.152465] Detected VIPT I-cache on CPU1
11574 23:26:17.446649 <6>[ 25.152552] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11575 23:26:17.453847 <6>[ 25.152613] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11576 23:26:17.456617 <6>[ 25.153227] CPU1 is up
11577 23:26:17.459944 <6>[ 25.153363] Detected VIPT I-cache on CPU2
11578 23:26:17.466783 <6>[ 25.153419] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11579 23:26:17.473726 <6>[ 25.153457] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11580 23:26:17.476563 <6>[ 25.153961] CPU2 is up
11581 23:26:17.479916 <6>[ 25.154096] Detected VIPT I-cache on CPU3
11582 23:26:17.486386 <6>[ 25.154152] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11583 23:26:17.493034 <6>[ 25.154189] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11584 23:26:17.496646 <6>[ 25.154719] CPU3 is up
11585 23:26:17.500069 <6>[ 25.154840] Detected PIPT I-cache on CPU4
11586 23:26:17.509544 <6>[ 25.154863] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11587 23:26:17.516104 <6>[ 25.154878] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11588 23:26:17.519905 <6>[ 25.155142] CPU4 is up
11589 23:26:17.522870 <6>[ 25.155338] Detected PIPT I-cache on CPU5
11590 23:26:17.529403 <6>[ 25.155360] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11591 23:26:17.535974 <6>[ 25.155375] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11592 23:26:17.539870 <6>[ 25.155615] CPU5 is up
11593 23:26:17.542952 <6>[ 25.155736] Detected PIPT I-cache on CPU6
11594 23:26:17.549323 <6>[ 25.155759] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11595 23:26:17.556033 <6>[ 25.155774] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11596 23:26:17.559216 <6>[ 25.156038] CPU6 is up
11597 23:26:17.562685 <6>[ 25.156158] Detected PIPT I-cache on CPU7
11598 23:26:17.572861 <6>[ 25.156181] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11599 23:26:17.579307 <6>[ 25.156196] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11600 23:26:17.579724 <6>[ 25.156461] CPU7 is up
11601 23:26:17.582474 <6>[ 25.695289] OOM killer enabled.
11602 23:26:17.589294 <6>[ 25.698678] Restarting tasks ... done.
11603 23:26:17.592567 <5>[ 25.703059] random: crng reseeded on system resumption
11604 23:26:17.596905 <6>[ 25.709347] PM: suspend exit
11605 23:26:17.607308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=pass>
11606 23:26:17.608139 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=pass
11608 23:26:17.610533 rtcwake: assuming RTC uses UTC ...
11609 23:26:17.616702 rtcwake: wakeup from "mem" using rtc0 at Wed Apr 3 23:26:24 2024
11610 23:26:17.629941 <6>[ 25.739368] PM: suspend entry (deep)
11611 23:26:17.633294 <6>[ 25.743230] Filesystems sync: 0.000 seconds
11612 23:26:17.636687 <6>[ 25.747961] Freezing user space processes
11613 23:26:17.647205 <6>[ 25.753505] Freezing user space processes completed (elapsed 0.001 seconds)
11614 23:26:17.650574 <6>[ 25.760728] OOM killer disabled.
11615 23:26:17.653942 <6>[ 25.764210] Freezing remaining freezable tasks
11616 23:26:17.664195 <6>[ 25.770111] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11617 23:26:17.670737 <6>[ 25.777783] printk: Suspending console(s) (use no_console_suspend to debug)
11618 23:26:23.401606 <6>[ 25.850976] Disabling non-boot CPUs ...
11619 23:26:23.404889 <6>[ 25.851843] psci: CPU1 killed (polled 0 ms)
11620 23:26:23.408346 <6>[ 25.853857] psci: CPU2 killed (polled 0 ms)
11621 23:26:23.414666 <6>[ 25.855209] psci: CPU3 killed (polled 4 ms)
11622 23:26:23.418086 <6>[ 25.855724] psci: CPU4 killed (polled 0 ms)
11623 23:26:23.421356 <6>[ 25.856261] psci: CPU5 killed (polled 0 ms)
11624 23:26:23.427803 <6>[ 25.856804] psci: CPU6 killed (polled 0 ms)
11625 23:26:23.431241 <6>[ 25.857336] psci: CPU7 killed (polled 0 ms)
11626 23:26:23.434818 <6>[ 25.857610] Enabling non-boot CPUs ...
11627 23:26:23.441646 <6>[ 25.857817] Detected VIPT I-cache on CPU1
11628 23:26:23.448002 <6>[ 25.857895] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11629 23:26:23.454344 <6>[ 25.857948] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11630 23:26:23.457697 <6>[ 25.858478] CPU1 is up
11631 23:26:23.461081 <6>[ 25.858595] Detected VIPT I-cache on CPU2
11632 23:26:23.467878 <6>[ 25.858641] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11633 23:26:23.475109 <6>[ 25.858672] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11634 23:26:23.477687 <6>[ 25.859075] CPU2 is up
11635 23:26:23.481451 <6>[ 25.859189] Detected VIPT I-cache on CPU3
11636 23:26:23.488009 <6>[ 25.859234] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11637 23:26:23.494395 <6>[ 25.859265] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11638 23:26:23.497802 <6>[ 25.859694] CPU3 is up
11639 23:26:23.504374 <6>[ 25.859806] Detected PIPT I-cache on CPU4
11640 23:26:23.511537 <6>[ 25.859828] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11641 23:26:23.517871 <6>[ 25.859842] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11642 23:26:23.520923 <6>[ 25.860087] CPU4 is up
11643 23:26:23.524231 <6>[ 25.860195] Detected PIPT I-cache on CPU5
11644 23:26:23.531085 <6>[ 25.860217] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11645 23:26:23.537996 <6>[ 25.860231] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11646 23:26:23.541258 <6>[ 25.860463] CPU5 is up
11647 23:26:23.544509 <6>[ 25.860583] Detected PIPT I-cache on CPU6
11648 23:26:23.551245 <6>[ 25.860605] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11649 23:26:23.557592 <6>[ 25.860619] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11650 23:26:23.560909 <6>[ 25.860852] CPU6 is up
11651 23:26:23.564405 <6>[ 25.860959] Detected PIPT I-cache on CPU7
11652 23:26:23.573990 <6>[ 25.860982] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11653 23:26:23.580843 <6>[ 25.860996] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11654 23:26:23.581260 <6>[ 25.861238] CPU7 is up
11655 23:26:23.587437 <6>[ 26.403244] OOM killer enabled.
11656 23:26:23.590868 <6>[ 26.406634] Restarting tasks ... done.
11657 23:26:23.593961 <5>[ 26.411049] random: crng reseeded on system resumption
11658 23:26:23.598150 <6>[ 26.417346] PM: suspend exit
11659 23:26:23.609013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=pass>
11660 23:26:23.609839 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=pass
11662 23:26:23.612288 rtcwake: assuming RTC uses UTC ...
11663 23:26:23.618690 rtcwake: wakeup from "mem" using rtc0 at Wed Apr 3 23:26:30 2024
11664 23:26:23.631470 <6>[ 26.447302] PM: suspend entry (deep)
11665 23:26:23.635230 <6>[ 26.451172] Filesystems sync: 0.000 seconds
11666 23:26:23.638176 <6>[ 26.455897] Freezing user space processes
11667 23:26:23.649004 <6>[ 26.461549] Freezing user space processes completed (elapsed 0.001 seconds)
11668 23:26:23.652445 <6>[ 26.468780] OOM killer disabled.
11669 23:26:23.655461 <6>[ 26.472259] Freezing remaining freezable tasks
11670 23:26:23.665666 <6>[ 26.478170] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11671 23:26:23.672420 <6>[ 26.485837] printk: Suspending console(s) (use no_console_suspend to debug)
11672 23:26:29.398493 <6>[ 26.559843] Disabling non-boot CPUs ...
11673 23:26:29.401972 <6>[ 26.561660] psci: CPU1 killed (polled 0 ms)
11674 23:26:29.405468 <6>[ 26.563169] psci: CPU2 killed (polled 4 ms)
11675 23:26:29.412025 <6>[ 26.564997] psci: CPU3 killed (polled 0 ms)
11676 23:26:29.415377 <6>[ 26.565515] psci: CPU4 killed (polled 0 ms)
11677 23:26:29.418705 <6>[ 26.566065] psci: CPU5 killed (polled 0 ms)
11678 23:26:29.425508 <6>[ 26.566589] psci: CPU6 killed (polled 0 ms)
11679 23:26:29.428749 <6>[ 26.567060] psci: CPU7 killed (polled 0 ms)
11680 23:26:29.431797 <6>[ 26.567396] Enabling non-boot CPUs ...
11681 23:26:29.438536 <6>[ 26.567603] Detected VIPT I-cache on CPU1
11682 23:26:29.444712 <6>[ 26.567678] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11683 23:26:29.451707 <6>[ 26.567732] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11684 23:26:29.454893 <6>[ 26.568247] CPU1 is up
11685 23:26:29.458321 <6>[ 26.568362] Detected VIPT I-cache on CPU2
11686 23:26:29.465017 <6>[ 26.568409] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11687 23:26:29.471308 <6>[ 26.568440] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11688 23:26:29.474638 <6>[ 26.568846] CPU2 is up
11689 23:26:29.477975 <6>[ 26.568962] Detected VIPT I-cache on CPU3
11690 23:26:29.487940 <6>[ 26.569008] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11691 23:26:29.494791 <6>[ 26.569038] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11692 23:26:29.495313 <6>[ 26.569462] CPU3 is up
11693 23:26:29.501273 <6>[ 26.569573] Detected PIPT I-cache on CPU4
11694 23:26:29.507858 <6>[ 26.569594] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11695 23:26:29.514785 <6>[ 26.569609] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11696 23:26:29.518069 <6>[ 26.569869] CPU4 is up
11697 23:26:29.521608 <6>[ 26.569988] Detected PIPT I-cache on CPU5
11698 23:26:29.527851 <6>[ 26.570010] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11699 23:26:29.534455 <6>[ 26.570024] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11700 23:26:29.537549 <6>[ 26.570246] CPU5 is up
11701 23:26:29.540962 <6>[ 26.570356] Detected PIPT I-cache on CPU6
11702 23:26:29.551062 <6>[ 26.570378] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11703 23:26:29.557465 <6>[ 26.570393] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11704 23:26:29.558035 <6>[ 26.570625] CPU6 is up
11705 23:26:29.564149 <6>[ 26.570734] Detected PIPT I-cache on CPU7
11706 23:26:29.570667 <6>[ 26.570756] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11707 23:26:29.577106 <6>[ 26.570770] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11708 23:26:29.580376 <6>[ 26.571014] CPU7 is up
11709 23:26:29.583898 <6>[ 27.111019] OOM killer enabled.
11710 23:26:29.587128 <6>[ 27.114411] Restarting tasks ... done.
11711 23:26:29.593959 <5>[ 27.118815] random: crng reseeded on system resumption
11712 23:26:29.596986 <6>[ 27.125046] PM: suspend exit
11713 23:26:29.605889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=pass>
11714 23:26:29.606625 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=pass
11716 23:26:29.608968 rtcwake: assuming RTC uses UTC ...
11717 23:26:29.615557 rtcwake: wakeup from "mem" using rtc0 at Wed Apr 3 23:26:36 2024
11718 23:26:29.628188 <6>[ 27.154492] PM: suspend entry (deep)
11719 23:26:29.631606 <6>[ 27.158382] Filesystems sync: 0.000 seconds
11720 23:26:29.635086 <6>[ 27.163138] Freezing user space processes
11721 23:26:29.645542 <6>[ 27.168843] Freezing user space processes completed (elapsed 0.001 seconds)
11722 23:26:29.648942 <6>[ 27.176071] OOM killer disabled.
11723 23:26:29.652665 <6>[ 27.179553] Freezing remaining freezable tasks
11724 23:26:29.662469 <6>[ 27.185460] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11725 23:26:29.668945 <6>[ 27.193124] printk: Suspending console(s) (use no_console_suspend to debug)
11726 23:26:35.400362 <6>[ 27.266054] Disabling non-boot CPUs ...
11727 23:26:35.403863 <6>[ 27.266971] psci: CPU1 killed (polled 0 ms)
11728 23:26:35.407211 <6>[ 27.268656] psci: CPU2 killed (polled 0 ms)
11729 23:26:35.413932 <6>[ 27.270590] psci: CPU3 killed (polled 0 ms)
11730 23:26:35.416790 <6>[ 27.271244] psci: CPU4 killed (polled 0 ms)
11731 23:26:35.420308 <6>[ 27.271843] psci: CPU5 killed (polled 0 ms)
11732 23:26:35.426685 <6>[ 27.272446] psci: CPU6 killed (polled 0 ms)
11733 23:26:35.429917 <6>[ 27.272982] psci: CPU7 killed (polled 0 ms)
11734 23:26:35.433324 <6>[ 27.273344] Enabling non-boot CPUs ...
11735 23:26:35.440014 <6>[ 27.273574] Detected VIPT I-cache on CPU1
11736 23:26:35.446638 <6>[ 27.273660] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11737 23:26:35.453296 <6>[ 27.273721] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11738 23:26:35.456793 <6>[ 27.274327] CPU1 is up
11739 23:26:35.459940 <6>[ 27.274461] Detected VIPT I-cache on CPU2
11740 23:26:35.466596 <6>[ 27.274517] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11741 23:26:35.473120 <6>[ 27.274555] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11742 23:26:35.476748 <6>[ 27.275120] CPU2 is up
11743 23:26:35.479690 <6>[ 27.275257] Detected VIPT I-cache on CPU3
11744 23:26:35.486341 <6>[ 27.275313] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11745 23:26:35.496324 <6>[ 27.275350] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11746 23:26:35.496749 <6>[ 27.275883] CPU3 is up
11747 23:26:35.502985 <6>[ 27.276005] Detected PIPT I-cache on CPU4
11748 23:26:35.509590 <6>[ 27.276027] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11749 23:26:35.516023 <6>[ 27.276042] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11750 23:26:35.519395 <6>[ 27.276312] CPU4 is up
11751 23:26:35.522510 <6>[ 27.276432] Detected PIPT I-cache on CPU5
11752 23:26:35.529164 <6>[ 27.276454] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11753 23:26:35.535990 <6>[ 27.276468] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11754 23:26:35.539219 <6>[ 27.276690] CPU5 is up
11755 23:26:35.542560 <6>[ 27.276807] Detected PIPT I-cache on CPU6
11756 23:26:35.549509 <6>[ 27.276829] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11757 23:26:35.556140 <6>[ 27.276843] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11758 23:26:35.559145 <6>[ 27.277085] CPU6 is up
11759 23:26:35.565893 <6>[ 27.277203] Detected PIPT I-cache on CPU7
11760 23:26:35.572592 <6>[ 27.277225] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11761 23:26:35.579284 <6>[ 27.277238] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11762 23:26:35.583082 <6>[ 27.277485] CPU7 is up
11763 23:26:35.586193 <6>[ 27.819380] OOM killer enabled.
11764 23:26:35.589712 <6>[ 27.822770] Restarting tasks ... done.
11765 23:26:35.592996 <5>[ 27.827132] random: crng reseeded on system resumption
11766 23:26:35.596944 <6>[ 27.833380] PM: suspend exit
11767 23:26:35.607202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=pass>
11768 23:26:35.608015 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=pass
11770 23:26:35.610383 rtcwake: assuming RTC uses UTC ...
11771 23:26:35.617240 rtcwake: wakeup from "mem" using rtc0 at Wed Apr 3 23:26:42 2024
11772 23:26:35.629602 <6>[ 27.862973] PM: suspend entry (deep)
11773 23:26:35.633167 <6>[ 27.866840] Filesystems sync: 0.000 seconds
11774 23:26:35.636613 <6>[ 27.871563] Freezing user space processes
11775 23:26:35.647526 <6>[ 27.877239] Freezing user space processes completed (elapsed 0.001 seconds)
11776 23:26:35.650720 <6>[ 27.884467] OOM killer disabled.
11777 23:26:35.653757 <6>[ 27.887951] Freezing remaining freezable tasks
11778 23:26:35.663987 <6>[ 27.893864] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11779 23:26:35.670647 <6>[ 27.901526] printk: Suspending console(s) (use no_console_suspend to debug)
11780 23:26:41.398854 <6>[ 27.975282] Disabling non-boot CPUs ...
11781 23:26:41.402243 <6>[ 27.976046] psci: CPU1 killed (polled 0 ms)
11782 23:26:41.405904 <6>[ 27.976883] psci: CPU2 killed (polled 0 ms)
11783 23:26:41.412230 <6>[ 27.978677] psci: CPU3 killed (polled 0 ms)
11784 23:26:41.415878 <6>[ 27.979233] psci: CPU4 killed (polled 0 ms)
11785 23:26:41.418960 <6>[ 27.979779] psci: CPU5 killed (polled 0 ms)
11786 23:26:41.425629 <6>[ 27.980303] psci: CPU6 killed (polled 0 ms)
11787 23:26:41.429238 <6>[ 27.980805] psci: CPU7 killed (polled 0 ms)
11788 23:26:41.432103 <6>[ 27.981047] Enabling non-boot CPUs ...
11789 23:26:41.438933 <6>[ 27.981247] Detected VIPT I-cache on CPU1
11790 23:26:41.445396 <6>[ 27.981321] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11791 23:26:41.452675 <6>[ 27.981372] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11792 23:26:41.455950 <6>[ 27.981864] CPU1 is up
11793 23:26:41.458697 <6>[ 27.981975] Detected VIPT I-cache on CPU2
11794 23:26:41.465421 <6>[ 27.982017] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11795 23:26:41.472067 <6>[ 27.982046] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11796 23:26:41.475364 <6>[ 27.982420] CPU2 is up
11797 23:26:41.478861 <6>[ 27.982529] Detected VIPT I-cache on CPU3
11798 23:26:41.485224 <6>[ 27.982572] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11799 23:26:41.492226 <6>[ 27.982601] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11800 23:26:41.495642 <6>[ 27.982993] CPU3 is up
11801 23:26:41.501917 <6>[ 27.983139] Detected PIPT I-cache on CPU4
11802 23:26:41.508497 <6>[ 27.983160] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11803 23:26:41.515055 <6>[ 27.983174] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11804 23:26:41.518314 <6>[ 27.983442] CPU4 is up
11805 23:26:41.522121 <6>[ 27.983556] Detected PIPT I-cache on CPU5
11806 23:26:41.528941 <6>[ 27.983578] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11807 23:26:41.535176 <6>[ 27.983593] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11808 23:26:41.538021 <6>[ 27.983816] CPU5 is up
11809 23:26:41.541556 <6>[ 27.983922] Detected PIPT I-cache on CPU6
11810 23:26:41.548330 <6>[ 27.983944] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11811 23:26:41.555040 <6>[ 27.983958] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11812 23:26:41.558022 <6>[ 27.984182] CPU6 is up
11813 23:26:41.564823 <6>[ 27.984286] Detected PIPT I-cache on CPU7
11814 23:26:41.571614 <6>[ 27.984308] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11815 23:26:41.578024 <6>[ 27.984322] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11816 23:26:41.581585 <6>[ 27.984560] CPU7 is up
11817 23:26:41.584928 <6>[ 28.526799] OOM killer enabled.
11818 23:26:41.588223 <6>[ 28.530190] Restarting tasks ... done.
11819 23:26:41.591700 <5>[ 28.534529] random: crng reseeded on system resumption
11820 23:26:41.596085 <6>[ 28.540890] PM: suspend exit
11821 23:26:41.608266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=pass>
11822 23:26:41.609061 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=pass
11824 23:26:41.611295 rtcwake: assuming RTC uses UTC ...
11825 23:26:41.617981 rtcwake: wakeup from "mem" using rtc0 at Wed Apr 3 23:26:48 2024
11826 23:26:41.631586 <6>[ 28.573244] PM: suspend entry (deep)
11827 23:26:41.634573 <6>[ 28.577116] Filesystems sync: 0.000 seconds
11828 23:26:41.637935 <6>[ 28.581862] Freezing user space processes
11829 23:26:41.649005 <6>[ 28.587095] Freezing user space processes completed (elapsed 0.000 seconds)
11830 23:26:41.652264 <6>[ 28.594313] OOM killer disabled.
11831 23:26:41.654826 <6>[ 28.597792] Freezing remaining freezable tasks
11832 23:26:41.665104 <6>[ 28.603604] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11833 23:26:41.671498 <6>[ 28.611253] printk: Suspending console(s) (use no_console_suspend to debug)
11834 23:26:47.406292 <6>[ 28.691537] Disabling non-boot CPUs ...
11835 23:26:47.409075 <4>[ 28.692385] migrate_one_irq: 88 callbacks suppressed
11836 23:26:47.416248 <4>[ 28.692397] IRQ282: set affinity failed(-22).
11837 23:26:47.419532 <4>[ 28.692407] IRQ283: set affinity failed(-22).
11838 23:26:47.423004 <6>[ 28.692490] psci: CPU1 killed (polled 0 ms)
11839 23:26:47.429544 <4>[ 28.693603] IRQ282: set affinity failed(-22).
11840 23:26:47.432683 <4>[ 28.693614] IRQ283: set affinity failed(-22).
11841 23:26:47.439250 <6>[ 28.693674] psci: CPU2 killed (polled 0 ms)
11842 23:26:47.442363 <4>[ 28.694590] IRQ282: set affinity failed(-22).
11843 23:26:47.445779 <4>[ 28.694601] IRQ283: set affinity failed(-22).
11844 23:26:47.452868 <6>[ 28.695043] psci: CPU3 killed (polled 4 ms)
11845 23:26:47.456504 <4>[ 28.695556] IRQ282: set affinity failed(-22).
11846 23:26:47.459552 <4>[ 28.695560] IRQ283: set affinity failed(-22).
11847 23:26:47.466160 <6>[ 28.695590] psci: CPU4 killed (polled 0 ms)
11848 23:26:47.469526 <4>[ 28.696236] IRQ282: set affinity failed(-22).
11849 23:26:47.472858 <4>[ 28.696240] IRQ283: set affinity failed(-22).
11850 23:26:47.479436 <6>[ 28.696274] psci: CPU5 killed (polled 0 ms)
11851 23:26:47.482956 <6>[ 28.696865] psci: CPU6 killed (polled 0 ms)
11852 23:26:47.489346 <6>[ 28.697394] psci: CPU7 killed (polled 0 ms)
11853 23:26:47.492775 <6>[ 28.697784] Enabling non-boot CPUs ...
11854 23:26:47.496060 <6>[ 28.698017] Detected VIPT I-cache on CPU1
11855 23:26:47.502213 <6>[ 28.698102] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11856 23:26:47.509095 <6>[ 28.698162] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11857 23:26:47.512349 <6>[ 28.698785] CPU1 is up
11858 23:26:47.516118 <6>[ 28.698922] Detected VIPT I-cache on CPU2
11859 23:26:47.526160 <6>[ 28.698977] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11860 23:26:47.532209 <6>[ 28.699015] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11861 23:26:47.532733 <6>[ 28.699523] CPU2 is up
11862 23:26:47.538771 <6>[ 28.699667] Detected VIPT I-cache on CPU3
11863 23:26:47.545879 <6>[ 28.699723] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11864 23:26:47.552572 <6>[ 28.699761] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11865 23:26:47.555414 <6>[ 28.700291] CPU3 is up
11866 23:26:47.558801 <6>[ 28.700412] Detected PIPT I-cache on CPU4
11867 23:26:47.565298 <6>[ 28.700435] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11868 23:26:47.572024 <6>[ 28.700449] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11869 23:26:47.575258 <6>[ 28.700716] CPU4 is up
11870 23:26:47.578681 <6>[ 28.700836] Detected PIPT I-cache on CPU5
11871 23:26:47.585239 <6>[ 28.700858] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11872 23:26:47.595170 <6>[ 28.700872] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11873 23:26:47.595689 <6>[ 28.701100] CPU5 is up
11874 23:26:47.601883 <6>[ 28.701218] Detected PIPT I-cache on CPU6
11875 23:26:47.608370 <6>[ 28.701240] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11876 23:26:47.615345 <6>[ 28.701254] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11877 23:26:47.618607 <6>[ 28.701492] CPU6 is up
11878 23:26:47.622156 <6>[ 28.701611] Detected PIPT I-cache on CPU7
11879 23:26:47.628604 <6>[ 28.701633] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11880 23:26:47.635037 <6>[ 28.701647] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11881 23:26:47.638074 <6>[ 28.701901] CPU7 is up
11882 23:26:47.641419 <6>[ 29.302539] OOM killer enabled.
11883 23:26:47.645073 <6>[ 29.305931] Restarting tasks ... done.
11884 23:26:47.651859 <5>[ 29.310288] random: crng reseeded on system resumption
11885 23:26:47.654866 <6>[ 29.316580] PM: suspend exit
11886 23:26:47.663910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=pass>
11887 23:26:47.664765 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=pass
11889 23:26:47.667499 rtcwake: assuming RTC uses UTC ...
11890 23:26:47.673868 rtcwake: wakeup from "mem" using rtc0 at Wed Apr 3 23:26:54 2024
11891 23:26:47.686976 <6>[ 29.346127] PM: suspend entry (deep)
11892 23:26:47.690259 <6>[ 29.349999] Filesystems sync: 0.000 seconds
11893 23:26:47.693747 <6>[ 29.354726] Freezing user space processes
11894 23:26:47.704307 <6>[ 29.360407] Freezing user space processes completed (elapsed 0.001 seconds)
11895 23:26:47.707681 <6>[ 29.367644] OOM killer disabled.
11896 23:26:47.711041 <6>[ 29.371125] Freezing remaining freezable tasks
11897 23:26:47.721399 <6>[ 29.377049] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11898 23:26:47.727790 <6>[ 29.384718] printk: Suspending console(s) (use no_console_suspend to debug)
11899 23:26:53.397189 <6>[ 29.470950] Disabling non-boot CPUs ...
11900 23:26:53.400557 <6>[ 29.472838] psci: CPU1 killed (polled 0 ms)
11901 23:26:53.403703 <6>[ 29.473743] psci: CPU2 killed (polled 0 ms)
11902 23:26:53.410372 <6>[ 29.474995] psci: CPU3 killed (polled 4 ms)
11903 23:26:53.413661 <6>[ 29.475463] psci: CPU4 killed (polled 0 ms)
11904 23:26:53.416819 <6>[ 29.476035] psci: CPU5 killed (polled 0 ms)
11905 23:26:53.423380 <6>[ 29.476586] psci: CPU6 killed (polled 0 ms)
11906 23:26:53.427052 <6>[ 29.477055] psci: CPU7 killed (polled 0 ms)
11907 23:26:53.430130 <6>[ 29.477463] Enabling non-boot CPUs ...
11908 23:26:53.437136 <6>[ 29.477673] Detected VIPT I-cache on CPU1
11909 23:26:53.443742 <6>[ 29.477749] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11910 23:26:53.450111 <6>[ 29.477802] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11911 23:26:53.453550 <6>[ 29.478324] CPU1 is up
11912 23:26:53.457039 <6>[ 29.478444] Detected VIPT I-cache on CPU2
11913 23:26:53.463507 <6>[ 29.478490] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11914 23:26:53.470454 <6>[ 29.478521] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11915 23:26:53.473317 <6>[ 29.478971] CPU2 is up
11916 23:26:53.476666 <6>[ 29.479089] Detected VIPT I-cache on CPU3
11917 23:26:53.483051 <6>[ 29.479135] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11918 23:26:53.489791 <6>[ 29.479166] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11919 23:26:53.493216 <6>[ 29.479593] CPU3 is up
11920 23:26:53.500459 <6>[ 29.479704] Detected PIPT I-cache on CPU4
11921 23:26:53.506751 <6>[ 29.479725] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11922 23:26:53.513163 <6>[ 29.479740] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11923 23:26:53.516550 <6>[ 29.480006] CPU4 is up
11924 23:26:53.519931 <6>[ 29.480125] Detected PIPT I-cache on CPU5
11925 23:26:53.526226 <6>[ 29.480147] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11926 23:26:53.533002 <6>[ 29.480161] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11927 23:26:53.536692 <6>[ 29.480380] CPU5 is up
11928 23:26:53.539705 <6>[ 29.480488] Detected PIPT I-cache on CPU6
11929 23:26:53.545827 <6>[ 29.480510] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11930 23:26:53.552670 <6>[ 29.480524] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11931 23:26:53.556035 <6>[ 29.480757] CPU6 is up
11932 23:26:53.562826 <6>[ 29.480863] Detected PIPT I-cache on CPU7
11933 23:26:53.569814 <6>[ 29.480885] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11934 23:26:53.575989 <6>[ 29.480899] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11935 23:26:53.579453 <6>[ 29.481146] CPU7 is up
11936 23:26:53.582511 <6>[ 30.022853] OOM killer enabled.
11937 23:26:53.585919 <6>[ 30.026244] Restarting tasks ... done.
11938 23:26:53.592787 <5>[ 30.030610] random: crng reseeded on system resumption
11939 23:26:53.595702 <6>[ 30.036894] PM: suspend exit
11940 23:26:53.604473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=pass>
11941 23:26:53.605352 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=pass
11943 23:26:53.607531 rtcwake: assuming RTC uses UTC ...
11944 23:26:53.614166 rtcwake: wakeup from "mem" using rtc0 at Wed Apr 3 23:27:00 2024
11945 23:26:53.626998 <6>[ 30.066989] PM: suspend entry (deep)
11946 23:26:53.630352 <6>[ 30.070841] Filesystems sync: 0.000 seconds
11947 23:26:53.633683 <6>[ 30.075577] Freezing user space processes
11948 23:26:53.644795 <6>[ 30.081308] Freezing user space processes completed (elapsed 0.001 seconds)
11949 23:26:53.648064 <6>[ 30.088546] OOM killer disabled.
11950 23:26:53.651266 <6>[ 30.092028] Freezing remaining freezable tasks
11951 23:26:53.661719 <6>[ 30.097942] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11952 23:26:53.668184 <6>[ 30.105617] printk: Suspending console(s) (use no_console_suspend to debug)
11953 23:26:59.399894 <6>[ 30.178656] Disabling non-boot CPUs ...
11954 23:26:59.403216 <6>[ 30.179596] psci: CPU1 killed (polled 0 ms)
11955 23:26:59.406722 <6>[ 30.181682] psci: CPU2 killed (polled 0 ms)
11956 23:26:59.413803 <6>[ 30.182957] psci: CPU3 killed (polled 4 ms)
11957 23:26:59.416775 <6>[ 30.183412] psci: CPU4 killed (polled 0 ms)
11958 23:26:59.420223 <6>[ 30.184007] psci: CPU5 killed (polled 0 ms)
11959 23:26:59.426398 <6>[ 30.184564] psci: CPU6 killed (polled 0 ms)
11960 23:26:59.430064 <6>[ 30.185167] psci: CPU7 killed (polled 0 ms)
11961 23:26:59.433246 <6>[ 30.185501] Enabling non-boot CPUs ...
11962 23:26:59.440040 <6>[ 30.185717] Detected VIPT I-cache on CPU1
11963 23:26:59.446649 <6>[ 30.185797] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11964 23:26:59.453177 <6>[ 30.185854] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11965 23:26:59.456627 <6>[ 30.186420] CPU1 is up
11966 23:26:59.459752 <6>[ 30.186543] Detected VIPT I-cache on CPU2
11967 23:26:59.466130 <6>[ 30.186593] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11968 23:26:59.473183 <6>[ 30.186627] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11969 23:26:59.476437 <6>[ 30.187097] CPU2 is up
11970 23:26:59.479872 <6>[ 30.187222] Detected VIPT I-cache on CPU3
11971 23:26:59.486460 <6>[ 30.187272] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11972 23:26:59.492959 <6>[ 30.187305] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11973 23:26:59.496125 <6>[ 30.187775] CPU3 is up
11974 23:26:59.503163 <6>[ 30.187890] Detected PIPT I-cache on CPU4
11975 23:26:59.509562 <6>[ 30.187912] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11976 23:26:59.516692 <6>[ 30.187926] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11977 23:26:59.519768 <6>[ 30.188192] CPU4 is up
11978 23:26:59.522841 <6>[ 30.188317] Detected PIPT I-cache on CPU5
11979 23:26:59.529578 <6>[ 30.188339] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11980 23:26:59.536623 <6>[ 30.188353] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11981 23:26:59.539860 <6>[ 30.188578] CPU5 is up
11982 23:26:59.543148 <6>[ 30.188691] Detected PIPT I-cache on CPU6
11983 23:26:59.549896 <6>[ 30.188713] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11984 23:26:59.556195 <6>[ 30.188726] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11985 23:26:59.559354 <6>[ 30.188963] CPU6 is up
11986 23:26:59.562843 <6>[ 30.189076] Detected PIPT I-cache on CPU7
11987 23:26:59.573124 <6>[ 30.189098] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11988 23:26:59.579725 <6>[ 30.189112] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11989 23:26:59.580239 <6>[ 30.189357] CPU7 is up
11990 23:26:59.586006 <6>[ 30.734954] OOM killer enabled.
11991 23:26:59.589268 <6>[ 30.738344] Restarting tasks ... done.
11992 23:26:59.592754 <5>[ 30.742687] random: crng reseeded on system resumption
11993 23:26:59.596803 <6>[ 30.748995] PM: suspend exit
11994 23:26:59.607174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=pass>
11995 23:26:59.607815 + set +x
11996 23:26:59.608510 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=pass
11998 23:26:59.613892 <LAVA_SIGNAL_ENDRUN 0_sleep 13248456_1.5.2.3.1>
11999 23:26:59.614407 <LAVA_TEST_RUNNER EXIT>
12000 23:26:59.615010 Received signal: <ENDRUN> 0_sleep 13248456_1.5.2.3.1
12001 23:26:59.615387 Ending use of test pattern.
12002 23:26:59.615689 Ending test lava.0_sleep (13248456_1.5.2.3.1), duration 60.10
12004 23:26:59.616786 ok: lava_test_shell seems to have completed
12005 23:26:59.617580 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-mem-1: pass
rtcwake-mem-10: pass
rtcwake-mem-2: pass
rtcwake-mem-3: pass
rtcwake-mem-4: pass
rtcwake-mem-5: pass
rtcwake-mem-6: pass
rtcwake-mem-7: pass
rtcwake-mem-8: pass
rtcwake-mem-9: pass
12006 23:26:59.618062 end: 3.1 lava-test-shell (duration 00:01:01) [common]
12007 23:26:59.618480 end: 3 lava-test-retry (duration 00:01:01) [common]
12008 23:26:59.618905 start: 4 finalize (timeout 00:04:42) [common]
12009 23:26:59.619338 start: 4.1 power-off (timeout 00:00:30) [common]
12010 23:26:59.620080 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
12011 23:26:59.739842 >> Command sent successfully.
12012 23:26:59.743389 Returned 0 in 0 seconds
12013 23:26:59.844185 end: 4.1 power-off (duration 00:00:00) [common]
12015 23:26:59.845659 start: 4.2 read-feedback (timeout 00:04:41) [common]
12016 23:26:59.846831 Listened to connection for namespace 'common' for up to 1s
12017 23:27:00.847534 Finalising connection for namespace 'common'
12018 23:27:00.848177 Disconnecting from shell: Finalise
12019 23:27:00.848713 / #
12020 23:27:00.949761 end: 4.2 read-feedback (duration 00:00:01) [common]
12021 23:27:00.950347 end: 4 finalize (duration 00:00:01) [common]
12022 23:27:00.950899 Cleaning after the job
12023 23:27:00.951363 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/ramdisk
12024 23:27:00.995615 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/kernel
12025 23:27:01.025416 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/dtb
12026 23:27:01.025690 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248456/tftp-deploy-2l1och7h/modules
12027 23:27:01.033055 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248456
12028 23:27:01.219728 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248456
12029 23:27:01.219900 Job finished correctly