Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 1
- Kernel Errors: 31
- Boot result: PASS
1 23:21:29.471663 lava-dispatcher, installed at version: 2024.01
2 23:21:29.471891 start: 0 validate
3 23:21:29.472033 Start time: 2024-04-03 23:21:29.472024+00:00 (UTC)
4 23:21:29.472153 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:21:29.472283 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:21:29.742477 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:21:29.743139 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:21:30.003881 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:21:30.004848 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:21:30.265935 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:21:30.266632 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:21:30.534943 validate duration: 1.06
14 23:21:30.536216 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:21:30.536816 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:21:30.537272 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:21:30.537840 Not decompressing ramdisk as can be used compressed.
18 23:21:30.538263 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 23:21:30.538583 saving as /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/ramdisk/rootfs.cpio.gz
20 23:21:30.538905 total size: 28105535 (26 MB)
21 23:21:30.544190 progress 0 % (0 MB)
22 23:21:30.576915 progress 5 % (1 MB)
23 23:21:30.585338 progress 10 % (2 MB)
24 23:21:30.592550 progress 15 % (4 MB)
25 23:21:30.599908 progress 20 % (5 MB)
26 23:21:30.607273 progress 25 % (6 MB)
27 23:21:30.614617 progress 30 % (8 MB)
28 23:21:30.622541 progress 35 % (9 MB)
29 23:21:30.630366 progress 40 % (10 MB)
30 23:21:30.637931 progress 45 % (12 MB)
31 23:21:30.645821 progress 50 % (13 MB)
32 23:21:30.653437 progress 55 % (14 MB)
33 23:21:30.660738 progress 60 % (16 MB)
34 23:21:30.668322 progress 65 % (17 MB)
35 23:21:30.676036 progress 70 % (18 MB)
36 23:21:30.684006 progress 75 % (20 MB)
37 23:21:30.691808 progress 80 % (21 MB)
38 23:21:30.699564 progress 85 % (22 MB)
39 23:21:30.707192 progress 90 % (24 MB)
40 23:21:30.715043 progress 95 % (25 MB)
41 23:21:30.722757 progress 100 % (26 MB)
42 23:21:30.722994 26 MB downloaded in 0.18 s (145.58 MB/s)
43 23:21:30.723165 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:21:30.723424 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:21:30.723511 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:21:30.723605 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:21:30.723744 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:21:30.723812 saving as /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/kernel/Image
50 23:21:30.723885 total size: 54286848 (51 MB)
51 23:21:30.723949 No compression specified
52 23:21:30.725217 progress 0 % (0 MB)
53 23:21:30.740019 progress 5 % (2 MB)
54 23:21:30.755099 progress 10 % (5 MB)
55 23:21:30.769981 progress 15 % (7 MB)
56 23:21:30.784937 progress 20 % (10 MB)
57 23:21:30.799814 progress 25 % (12 MB)
58 23:21:30.814639 progress 30 % (15 MB)
59 23:21:30.829322 progress 35 % (18 MB)
60 23:21:30.844221 progress 40 % (20 MB)
61 23:21:30.858888 progress 45 % (23 MB)
62 23:21:30.873459 progress 50 % (25 MB)
63 23:21:30.888378 progress 55 % (28 MB)
64 23:21:30.903437 progress 60 % (31 MB)
65 23:21:30.918068 progress 65 % (33 MB)
66 23:21:30.932902 progress 70 % (36 MB)
67 23:21:30.947738 progress 75 % (38 MB)
68 23:21:30.962234 progress 80 % (41 MB)
69 23:21:30.977138 progress 85 % (44 MB)
70 23:21:30.991918 progress 90 % (46 MB)
71 23:21:31.006484 progress 95 % (49 MB)
72 23:21:31.021322 progress 100 % (51 MB)
73 23:21:31.021587 51 MB downloaded in 0.30 s (173.91 MB/s)
74 23:21:31.021786 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:21:31.022165 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:21:31.022281 start: 1.3 download-retry (timeout 00:10:00) [common]
78 23:21:31.022402 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 23:21:31.022579 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:21:31.022682 saving as /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/dtb/mt8192-asurada-spherion-r0.dtb
81 23:21:31.022773 total size: 47230 (0 MB)
82 23:21:31.022863 No compression specified
83 23:21:31.024557 progress 69 % (0 MB)
84 23:21:31.024884 progress 100 % (0 MB)
85 23:21:31.025078 0 MB downloaded in 0.00 s (19.56 MB/s)
86 23:21:31.025254 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:21:31.025614 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:21:31.025727 start: 1.4 download-retry (timeout 00:10:00) [common]
90 23:21:31.025849 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 23:21:31.025992 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:21:31.026095 saving as /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/modules/modules.tar
93 23:21:31.026185 total size: 8629908 (8 MB)
94 23:21:31.026274 Using unxz to decompress xz
95 23:21:31.031065 progress 0 % (0 MB)
96 23:21:31.050086 progress 5 % (0 MB)
97 23:21:31.074699 progress 10 % (0 MB)
98 23:21:31.098702 progress 15 % (1 MB)
99 23:21:31.122019 progress 20 % (1 MB)
100 23:21:31.146640 progress 25 % (2 MB)
101 23:21:31.172127 progress 30 % (2 MB)
102 23:21:31.196502 progress 35 % (2 MB)
103 23:21:31.222288 progress 40 % (3 MB)
104 23:21:31.246765 progress 45 % (3 MB)
105 23:21:31.271959 progress 50 % (4 MB)
106 23:21:31.297115 progress 55 % (4 MB)
107 23:21:31.325313 progress 60 % (4 MB)
108 23:21:31.350484 progress 65 % (5 MB)
109 23:21:31.375518 progress 70 % (5 MB)
110 23:21:31.399507 progress 75 % (6 MB)
111 23:21:31.424760 progress 80 % (6 MB)
112 23:21:31.450695 progress 85 % (7 MB)
113 23:21:31.479261 progress 90 % (7 MB)
114 23:21:31.508366 progress 95 % (7 MB)
115 23:21:31.534721 progress 100 % (8 MB)
116 23:21:31.540068 8 MB downloaded in 0.51 s (16.02 MB/s)
117 23:21:31.540321 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:21:31.540583 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:21:31.540677 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:21:31.540819 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:21:31.540898 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:21:31.540986 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:21:31.541205 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs
125 23:21:31.541341 makedir: /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin
126 23:21:31.541444 makedir: /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/tests
127 23:21:31.541542 makedir: /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/results
128 23:21:31.541656 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-add-keys
129 23:21:31.541810 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-add-sources
130 23:21:31.541952 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-background-process-start
131 23:21:31.542083 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-background-process-stop
132 23:21:31.542208 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-common-functions
133 23:21:31.542334 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-echo-ipv4
134 23:21:31.542460 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-install-packages
135 23:21:31.542583 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-installed-packages
136 23:21:31.542706 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-os-build
137 23:21:31.542830 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-probe-channel
138 23:21:31.542955 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-probe-ip
139 23:21:31.543080 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-target-ip
140 23:21:31.543204 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-target-mac
141 23:21:31.543328 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-target-storage
142 23:21:31.543456 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-test-case
143 23:21:31.543580 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-test-event
144 23:21:31.543706 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-test-feedback
145 23:21:31.543831 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-test-raise
146 23:21:31.543956 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-test-reference
147 23:21:31.544080 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-test-runner
148 23:21:31.544203 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-test-set
149 23:21:31.544329 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-test-shell
150 23:21:31.544458 Updating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-install-packages (oe)
151 23:21:31.544610 Updating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/bin/lava-installed-packages (oe)
152 23:21:31.544779 Creating /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/environment
153 23:21:31.544884 LAVA metadata
154 23:21:31.544963 - LAVA_JOB_ID=13248448
155 23:21:31.545028 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:21:31.545131 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:21:31.545197 skipped lava-vland-overlay
158 23:21:31.545270 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:21:31.545351 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:21:31.545412 skipped lava-multinode-overlay
161 23:21:31.545496 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:21:31.545588 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:21:31.545661 Loading test definitions
164 23:21:31.545750 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:21:31.545828 Using /lava-13248448 at stage 0
166 23:21:31.546139 uuid=13248448_1.5.2.3.1 testdef=None
167 23:21:31.546226 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:21:31.546315 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:21:31.546839 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:21:31.547055 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:21:31.547665 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:21:31.547890 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:21:31.548478 runner path: /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 13248448_1.5.2.3.1
176 23:21:31.548637 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:21:31.548882 Creating lava-test-runner.conf files
179 23:21:31.548944 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248448/lava-overlay-amhmfxqs/lava-13248448/0 for stage 0
180 23:21:31.549032 - 0_v4l2-compliance-mtk-vcodec-enc
181 23:21:31.549126 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:21:31.549208 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:21:31.556594 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:21:31.556729 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:21:31.556855 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:21:31.556938 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:21:31.557024 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:21:32.477184 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:21:32.477583 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 23:21:32.477701 extracting modules file /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248448/extract-overlay-ramdisk-rpi7rg1e/ramdisk
191 23:21:32.707545 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:21:32.707702 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 23:21:32.707794 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248448/compress-overlay-qfbvdl0x/overlay-1.5.2.4.tar.gz to ramdisk
194 23:21:32.707866 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248448/compress-overlay-qfbvdl0x/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248448/extract-overlay-ramdisk-rpi7rg1e/ramdisk
195 23:21:32.714718 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:21:32.714828 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 23:21:32.714921 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:21:32.715011 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 23:21:32.715092 Building ramdisk /var/lib/lava/dispatcher/tmp/13248448/extract-overlay-ramdisk-rpi7rg1e/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248448/extract-overlay-ramdisk-rpi7rg1e/ramdisk
200 23:21:33.475415 >> 276140 blocks
201 23:21:37.678984 rename /var/lib/lava/dispatcher/tmp/13248448/extract-overlay-ramdisk-rpi7rg1e/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/ramdisk/ramdisk.cpio.gz
202 23:21:37.679444 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 23:21:37.679568 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 23:21:37.679669 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 23:21:37.679780 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/kernel/Image'
206 23:21:50.482653 Returned 0 in 12 seconds
207 23:21:50.583627 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/kernel/image.itb
208 23:21:51.261576 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:21:51.261960 output: Created: Thu Apr 4 00:21:51 2024
210 23:21:51.262036 output: Image 0 (kernel-1)
211 23:21:51.262102 output: Description:
212 23:21:51.262162 output: Created: Thu Apr 4 00:21:51 2024
213 23:21:51.262223 output: Type: Kernel Image
214 23:21:51.262286 output: Compression: lzma compressed
215 23:21:51.262344 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
216 23:21:51.262404 output: Architecture: AArch64
217 23:21:51.262460 output: OS: Linux
218 23:21:51.262517 output: Load Address: 0x00000000
219 23:21:51.262573 output: Entry Point: 0x00000000
220 23:21:51.262631 output: Hash algo: crc32
221 23:21:51.262686 output: Hash value: d7c9dcc1
222 23:21:51.262740 output: Image 1 (fdt-1)
223 23:21:51.262796 output: Description: mt8192-asurada-spherion-r0
224 23:21:51.262850 output: Created: Thu Apr 4 00:21:51 2024
225 23:21:51.262904 output: Type: Flat Device Tree
226 23:21:51.262956 output: Compression: uncompressed
227 23:21:51.263009 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 23:21:51.263061 output: Architecture: AArch64
229 23:21:51.263112 output: Hash algo: crc32
230 23:21:51.263164 output: Hash value: 4bf0d1ac
231 23:21:51.263216 output: Image 2 (ramdisk-1)
232 23:21:51.263268 output: Description: unavailable
233 23:21:51.263319 output: Created: Thu Apr 4 00:21:51 2024
234 23:21:51.263371 output: Type: RAMDisk Image
235 23:21:51.263422 output: Compression: Unknown Compression
236 23:21:51.263474 output: Data Size: 41255191 Bytes = 40288.27 KiB = 39.34 MiB
237 23:21:51.263526 output: Architecture: AArch64
238 23:21:51.263577 output: OS: Linux
239 23:21:51.263629 output: Load Address: unavailable
240 23:21:51.263680 output: Entry Point: unavailable
241 23:21:51.263731 output: Hash algo: crc32
242 23:21:51.263782 output: Hash value: 8673cce7
243 23:21:51.263833 output: Default Configuration: 'conf-1'
244 23:21:51.263885 output: Configuration 0 (conf-1)
245 23:21:51.263937 output: Description: mt8192-asurada-spherion-r0
246 23:21:51.263988 output: Kernel: kernel-1
247 23:21:51.264039 output: Init Ramdisk: ramdisk-1
248 23:21:51.264089 output: FDT: fdt-1
249 23:21:51.264141 output: Loadables: kernel-1
250 23:21:51.264191 output:
251 23:21:51.264396 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 23:21:51.264494 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 23:21:51.264597 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 23:21:51.264692 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 23:21:51.264818 No LXC device requested
256 23:21:51.264908 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:21:51.264993 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 23:21:51.265068 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:21:51.265139 Checking files for TFTP limit of 4294967296 bytes.
260 23:21:51.265633 end: 1 tftp-deploy (duration 00:00:21) [common]
261 23:21:51.265739 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:21:51.265832 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:21:51.265963 substitutions:
264 23:21:51.266033 - {DTB}: 13248448/tftp-deploy-hxgkz2eb/dtb/mt8192-asurada-spherion-r0.dtb
265 23:21:51.266097 - {INITRD}: 13248448/tftp-deploy-hxgkz2eb/ramdisk/ramdisk.cpio.gz
266 23:21:51.266156 - {KERNEL}: 13248448/tftp-deploy-hxgkz2eb/kernel/Image
267 23:21:51.266213 - {LAVA_MAC}: None
268 23:21:51.266269 - {PRESEED_CONFIG}: None
269 23:21:51.266323 - {PRESEED_LOCAL}: None
270 23:21:51.266378 - {RAMDISK}: 13248448/tftp-deploy-hxgkz2eb/ramdisk/ramdisk.cpio.gz
271 23:21:51.266431 - {ROOT_PART}: None
272 23:21:51.266484 - {ROOT}: None
273 23:21:51.266537 - {SERVER_IP}: 192.168.201.1
274 23:21:51.266590 - {TEE}: None
275 23:21:51.266642 Parsed boot commands:
276 23:21:51.266698 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:21:51.266878 Parsed boot commands: tftpboot 192.168.201.1 13248448/tftp-deploy-hxgkz2eb/kernel/image.itb 13248448/tftp-deploy-hxgkz2eb/kernel/cmdline
278 23:21:51.266970 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:21:51.267058 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:21:51.267147 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:21:51.267234 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:21:51.267305 Not connected, no need to disconnect.
283 23:21:51.267378 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:21:51.267459 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:21:51.267524 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 23:21:51.271626 Setting prompt string to ['lava-test: # ']
287 23:21:51.271993 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:21:51.272102 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:21:51.272202 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:21:51.272290 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:21:51.272490 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 23:21:56.422084 >> Command sent successfully.
293 23:21:56.434099 Returned 0 in 5 seconds
294 23:21:56.535603 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:21:56.537190 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:21:56.537735 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:21:56.538218 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:21:56.538611 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:21:56.538980 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:21:56.540270 [Enter `^Ec?' for help]
302 23:21:56.722707
303 23:21:56.723248
304 23:21:56.723600 F0: 102B 0000
305 23:21:56.723938
306 23:21:56.724256 F3: 1001 0000 [0200]
307 23:21:56.724578
308 23:21:56.725879 F3: 1001 0000
309 23:21:56.726321
310 23:21:56.726670 F7: 102D 0000
311 23:21:56.726989
312 23:21:56.727291 F1: 0000 0000
313 23:21:56.727590
314 23:21:56.729984 V0: 0000 0000 [0001]
315 23:21:56.730421
316 23:21:56.730762 00: 0007 8000
317 23:21:56.731085
318 23:21:56.733226 01: 0000 0000
319 23:21:56.733842
320 23:21:56.734197 BP: 0C00 0209 [0000]
321 23:21:56.734569
322 23:21:56.736700 G0: 1182 0000
323 23:21:56.737174
324 23:21:56.737517 EC: 0000 0021 [4000]
325 23:21:56.737841
326 23:21:56.740605 S7: 0000 0000 [0000]
327 23:21:56.741084
328 23:21:56.741429 CC: 0000 0000 [0001]
329 23:21:56.741807
330 23:21:56.743858 T0: 0000 0040 [010F]
331 23:21:56.744483
332 23:21:56.745007 Jump to BL
333 23:21:56.745351
334 23:21:56.768538
335 23:21:56.769100
336 23:21:56.769444
337 23:21:56.775649 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:21:56.779558 ARM64: Exception handlers installed.
339 23:21:56.783204 ARM64: Testing exception
340 23:21:56.785999 ARM64: Done test exception
341 23:21:56.792332 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:21:56.803936 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:21:56.809932 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:21:56.820298 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:21:56.826939 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:21:56.837033 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:21:56.846594 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:21:56.853907 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:21:56.871276 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:21:56.874920 WDT: Last reset was cold boot
351 23:21:56.878136 SPI1(PAD0) initialized at 2873684 Hz
352 23:21:56.881687 SPI5(PAD0) initialized at 992727 Hz
353 23:21:56.884916 VBOOT: Loading verstage.
354 23:21:56.891538 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:21:56.895254 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:21:56.898370 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:21:56.901246 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:21:56.909517 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:21:56.915255 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:21:56.926819 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 23:21:56.927493
362 23:21:56.927874
363 23:21:56.936395 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:21:56.940430 ARM64: Exception handlers installed.
365 23:21:56.943649 ARM64: Testing exception
366 23:21:56.944120 ARM64: Done test exception
367 23:21:56.950855 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:21:56.953196 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:21:56.967423 Probing TPM: . done!
370 23:21:56.968021 TPM ready after 0 ms
371 23:21:56.974105 Connected to device vid:did:rid of 1ae0:0028:00
372 23:21:56.981320 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 23:21:56.984627 Initialized TPM device CR50 revision 0
374 23:21:57.035798 tlcl_send_startup: Startup return code is 0
375 23:21:57.036368 TPM: setup succeeded
376 23:21:57.046985 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:21:57.055770 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:21:57.065979 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:21:57.074602 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:21:57.079176 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:21:57.081887 in-header: 03 07 00 00 08 00 00 00
382 23:21:57.085551 in-data: aa e4 47 04 13 02 00 00
383 23:21:57.088438 Chrome EC: UHEPI supported
384 23:21:57.094525 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:21:57.097902 in-header: 03 9d 00 00 08 00 00 00
386 23:21:57.101360 in-data: 10 20 20 08 00 00 00 00
387 23:21:57.101839 Phase 1
388 23:21:57.104575 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:21:57.111198 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:21:57.118128 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:21:57.121164 Recovery requested (1009000e)
392 23:21:57.128414 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:21:57.133593 tlcl_extend: response is 0
394 23:21:57.141419 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:21:57.147461 tlcl_extend: response is 0
396 23:21:57.153998 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:21:57.173784 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 23:21:57.180983 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:21:57.181565
400 23:21:57.181943
401 23:21:57.190735 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:21:57.193521 ARM64: Exception handlers installed.
403 23:21:57.196835 ARM64: Testing exception
404 23:21:57.197308 ARM64: Done test exception
405 23:21:57.219755 pmic_efuse_setting: Set efuses in 11 msecs
406 23:21:57.223234 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:21:57.230174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:21:57.233763 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:21:57.240350 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:21:57.243788 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:21:57.247392 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:21:57.254715 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:21:57.258705 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:21:57.261442 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:21:57.269651 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:21:57.271901 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:21:57.278254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:21:57.283040 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:21:57.285296 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:21:57.291777 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:21:57.298383 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:21:57.305062 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:21:57.308357 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:21:57.316159 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:21:57.319166 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:21:57.325950 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:21:57.332941 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:21:57.335730 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:21:57.342240 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:21:57.348819 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:21:57.352216 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:21:57.358918 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:21:57.365641 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:21:57.368809 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:21:57.373154 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:21:57.379641 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:21:57.382658 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:21:57.388973 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:21:57.392252 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:21:57.399329 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:21:57.402878 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:21:57.409355 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:21:57.413144 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:21:57.419086 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:21:57.423001 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:21:57.429940 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:21:57.432508 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:21:57.435831 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:21:57.442785 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:21:57.445269 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:21:57.449104 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:21:57.452323 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:21:57.459382 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:21:57.462359 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:21:57.465400 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:21:57.469029 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:21:57.475951 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:21:57.482229 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:21:57.492040 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:21:57.495249 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:21:57.502387 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:21:57.512592 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:21:57.516392 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:21:57.522821 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:21:57.526135 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:21:57.532358 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 23:21:57.539366 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:21:57.542626 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 23:21:57.545246 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:21:57.557092 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 23:21:57.566470 [RTC]rtc_get_frequency_meter,154: input=23, output=949
472 23:21:57.576917 [RTC]rtc_get_frequency_meter,154: input=19, output=858
473 23:21:57.585374 [RTC]rtc_get_frequency_meter,154: input=17, output=811
474 23:21:57.594910 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 23:21:57.604661 [RTC]rtc_get_frequency_meter,154: input=16, output=787
476 23:21:57.613692 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 23:21:57.617131 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 23:21:57.624548 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 23:21:57.627624 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:21:57.631189 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 23:21:57.638546 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:21:57.641063 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 23:21:57.645104 ADC[4]: Raw value=670063 ID=5
484 23:21:57.645673 ADC[3]: Raw value=212917 ID=1
485 23:21:57.647622 RAM Code: 0x51
486 23:21:57.651369 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:21:57.657690 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:21:57.664296 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 23:21:57.670623 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 23:21:57.673904 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:21:57.677684 in-header: 03 07 00 00 08 00 00 00
492 23:21:57.681272 in-data: aa e4 47 04 13 02 00 00
493 23:21:57.683794 Chrome EC: UHEPI supported
494 23:21:57.690795 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:21:57.693462 in-header: 03 d5 00 00 08 00 00 00
496 23:21:57.697422 in-data: 98 20 60 08 00 00 00 00
497 23:21:57.700310 MRC: failed to locate region type 0.
498 23:21:57.708106 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:21:57.710000 DRAM-K: Running full calibration
500 23:21:57.713390 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 23:21:57.717289 header.status = 0x0
502 23:21:57.720580 header.version = 0x6 (expected: 0x6)
503 23:21:57.723787 header.size = 0xd00 (expected: 0xd00)
504 23:21:57.724361 header.flags = 0x0
505 23:21:57.730011 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:21:57.749012 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 23:21:57.755517 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:21:57.759940 dram_init: ddr_geometry: 0
509 23:21:57.762451 [EMI] MDL number = 0
510 23:21:57.763025 [EMI] Get MDL freq = 0
511 23:21:57.765994 dram_init: ddr_type: 0
512 23:21:57.766571 is_discrete_lpddr4: 1
513 23:21:57.769446 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:21:57.770033
515 23:21:57.770414
516 23:21:57.772951 [Bian_co] ETT version 0.0.0.1
517 23:21:57.775879 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 23:21:57.779703
519 23:21:57.782865 dramc_set_vcore_voltage set vcore to 650000
520 23:21:57.783491 Read voltage for 800, 4
521 23:21:57.785903 Vio18 = 0
522 23:21:57.786474 Vcore = 650000
523 23:21:57.786857 Vdram = 0
524 23:21:57.789224 Vddq = 0
525 23:21:57.789699 Vmddr = 0
526 23:21:57.792752 dram_init: config_dvfs: 1
527 23:21:57.796155 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:21:57.802875 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:21:57.805833 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 23:21:57.809418 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 23:21:57.813270 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 23:21:57.817029 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 23:21:57.819702 MEM_TYPE=3, freq_sel=18
534 23:21:57.822307 sv_algorithm_assistance_LP4_1600
535 23:21:57.826230 ============ PULL DRAM RESETB DOWN ============
536 23:21:57.829675 ========== PULL DRAM RESETB DOWN end =========
537 23:21:57.836262 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:21:57.839096 ===================================
539 23:21:57.839575 LPDDR4 DRAM CONFIGURATION
540 23:21:57.842704 ===================================
541 23:21:57.845519 EX_ROW_EN[0] = 0x0
542 23:21:57.848798 EX_ROW_EN[1] = 0x0
543 23:21:57.849273 LP4Y_EN = 0x0
544 23:21:57.852586 WORK_FSP = 0x0
545 23:21:57.853110 WL = 0x2
546 23:21:57.855790 RL = 0x2
547 23:21:57.856259 BL = 0x2
548 23:21:57.859397 RPST = 0x0
549 23:21:57.859937 RD_PRE = 0x0
550 23:21:57.862142 WR_PRE = 0x1
551 23:21:57.862563 WR_PST = 0x0
552 23:21:57.866077 DBI_WR = 0x0
553 23:21:57.866502 DBI_RD = 0x0
554 23:21:57.869209 OTF = 0x1
555 23:21:57.872672 ===================================
556 23:21:57.876049 ===================================
557 23:21:57.876470 ANA top config
558 23:21:57.879535 ===================================
559 23:21:57.882585 DLL_ASYNC_EN = 0
560 23:21:57.886699 ALL_SLAVE_EN = 1
561 23:21:57.887235 NEW_RANK_MODE = 1
562 23:21:57.889318 DLL_IDLE_MODE = 1
563 23:21:57.892461 LP45_APHY_COMB_EN = 1
564 23:21:57.895958 TX_ODT_DIS = 1
565 23:21:57.898919 NEW_8X_MODE = 1
566 23:21:57.902137 ===================================
567 23:21:57.905855 ===================================
568 23:21:57.906288 data_rate = 1600
569 23:21:57.909335 CKR = 1
570 23:21:57.913003 DQ_P2S_RATIO = 8
571 23:21:57.915795 ===================================
572 23:21:57.919249 CA_P2S_RATIO = 8
573 23:21:57.922745 DQ_CA_OPEN = 0
574 23:21:57.925892 DQ_SEMI_OPEN = 0
575 23:21:57.926327 CA_SEMI_OPEN = 0
576 23:21:57.930001 CA_FULL_RATE = 0
577 23:21:57.933183 DQ_CKDIV4_EN = 1
578 23:21:57.935384 CA_CKDIV4_EN = 1
579 23:21:57.939354 CA_PREDIV_EN = 0
580 23:21:57.942869 PH8_DLY = 0
581 23:21:57.943598 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:21:57.945388 DQ_AAMCK_DIV = 4
583 23:21:57.949058 CA_AAMCK_DIV = 4
584 23:21:57.952587 CA_ADMCK_DIV = 4
585 23:21:57.955907 DQ_TRACK_CA_EN = 0
586 23:21:57.959380 CA_PICK = 800
587 23:21:57.959812 CA_MCKIO = 800
588 23:21:57.962068 MCKIO_SEMI = 0
589 23:21:57.965926 PLL_FREQ = 3068
590 23:21:57.969266 DQ_UI_PI_RATIO = 32
591 23:21:57.972317 CA_UI_PI_RATIO = 0
592 23:21:57.975907 ===================================
593 23:21:57.979430 ===================================
594 23:21:57.982675 memory_type:LPDDR4
595 23:21:57.983107 GP_NUM : 10
596 23:21:57.985931 SRAM_EN : 1
597 23:21:57.986462 MD32_EN : 0
598 23:21:57.989078 ===================================
599 23:21:57.992239 [ANA_INIT] >>>>>>>>>>>>>>
600 23:21:57.995594 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:21:57.998728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:21:58.002252 ===================================
603 23:21:58.005733 data_rate = 1600,PCW = 0X7600
604 23:21:58.009200 ===================================
605 23:21:58.012945 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:21:58.015450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:21:58.022134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:21:58.025536 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:21:58.032861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:21:58.035893 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:21:58.036419 [ANA_INIT] flow start
612 23:21:58.039040 [ANA_INIT] PLL >>>>>>>>
613 23:21:58.042422 [ANA_INIT] PLL <<<<<<<<
614 23:21:58.042952 [ANA_INIT] MIDPI >>>>>>>>
615 23:21:58.045916 [ANA_INIT] MIDPI <<<<<<<<
616 23:21:58.048876 [ANA_INIT] DLL >>>>>>>>
617 23:21:58.049403 [ANA_INIT] flow end
618 23:21:58.052269 ============ LP4 DIFF to SE enter ============
619 23:21:58.059234 ============ LP4 DIFF to SE exit ============
620 23:21:58.059765 [ANA_INIT] <<<<<<<<<<<<<
621 23:21:58.062090 [Flow] Enable top DCM control >>>>>
622 23:21:58.065548 [Flow] Enable top DCM control <<<<<
623 23:21:58.068848 Enable DLL master slave shuffle
624 23:21:58.075553 ==============================================================
625 23:21:58.078378 Gating Mode config
626 23:21:58.083252 ==============================================================
627 23:21:58.086821 Config description:
628 23:21:58.095877 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:21:58.101934 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:21:58.105608 SELPH_MODE 0: By rank 1: By Phase
631 23:21:58.111989 ==============================================================
632 23:21:58.115066 GAT_TRACK_EN = 1
633 23:21:58.118898 RX_GATING_MODE = 2
634 23:21:58.119427 RX_GATING_TRACK_MODE = 2
635 23:21:58.121521 SELPH_MODE = 1
636 23:21:58.125135 PICG_EARLY_EN = 1
637 23:21:58.129518 VALID_LAT_VALUE = 1
638 23:21:58.135709 ==============================================================
639 23:21:58.138838 Enter into Gating configuration >>>>
640 23:21:58.142913 Exit from Gating configuration <<<<
641 23:21:58.145452 Enter into DVFS_PRE_config >>>>>
642 23:21:58.155252 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:21:58.158844 Exit from DVFS_PRE_config <<<<<
644 23:21:58.161977 Enter into PICG configuration >>>>
645 23:21:58.165852 Exit from PICG configuration <<<<
646 23:21:58.168495 [RX_INPUT] configuration >>>>>
647 23:21:58.172407 [RX_INPUT] configuration <<<<<
648 23:21:58.175389 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:21:58.182327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:21:58.188889 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:21:58.191760 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:21:58.198759 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:21:58.205753 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:21:58.209076 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:21:58.212270 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:21:58.219408 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:21:58.221897 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:21:58.225314 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:21:58.231774 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:21:58.235512 ===================================
661 23:21:58.236027 LPDDR4 DRAM CONFIGURATION
662 23:21:58.238302 ===================================
663 23:21:58.241901 EX_ROW_EN[0] = 0x0
664 23:21:58.242380 EX_ROW_EN[1] = 0x0
665 23:21:58.246128 LP4Y_EN = 0x0
666 23:21:58.248257 WORK_FSP = 0x0
667 23:21:58.248686 WL = 0x2
668 23:21:58.252326 RL = 0x2
669 23:21:58.252960 BL = 0x2
670 23:21:58.255122 RPST = 0x0
671 23:21:58.255595 RD_PRE = 0x0
672 23:21:58.258796 WR_PRE = 0x1
673 23:21:58.259266 WR_PST = 0x0
674 23:21:58.262411 DBI_WR = 0x0
675 23:21:58.262974 DBI_RD = 0x0
676 23:21:58.266256 OTF = 0x1
677 23:21:58.268879 ===================================
678 23:21:58.271981 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:21:58.275488 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:21:58.278695 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:21:58.281952 ===================================
682 23:21:58.285680 LPDDR4 DRAM CONFIGURATION
683 23:21:58.288595 ===================================
684 23:21:58.291613 EX_ROW_EN[0] = 0x10
685 23:21:58.292135 EX_ROW_EN[1] = 0x0
686 23:21:58.295508 LP4Y_EN = 0x0
687 23:21:58.295985 WORK_FSP = 0x0
688 23:21:58.299066 WL = 0x2
689 23:21:58.299591 RL = 0x2
690 23:21:58.301756 BL = 0x2
691 23:21:58.302321 RPST = 0x0
692 23:21:58.304884 RD_PRE = 0x0
693 23:21:58.309083 WR_PRE = 0x1
694 23:21:58.309654 WR_PST = 0x0
695 23:21:58.312021 DBI_WR = 0x0
696 23:21:58.312590 DBI_RD = 0x0
697 23:21:58.315290 OTF = 0x1
698 23:21:58.318500 ===================================
699 23:21:58.321565 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:21:58.327245 nWR fixed to 40
701 23:21:58.330580 [ModeRegInit_LP4] CH0 RK0
702 23:21:58.331151 [ModeRegInit_LP4] CH0 RK1
703 23:21:58.333846 [ModeRegInit_LP4] CH1 RK0
704 23:21:58.337421 [ModeRegInit_LP4] CH1 RK1
705 23:21:58.338041 match AC timing 12
706 23:21:58.343900 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 23:21:58.346899 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:21:58.350785 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:21:58.357537 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:21:58.360915 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:21:58.361480 [EMI DOE] emi_dcm 0
712 23:21:58.367024 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:21:58.367596 ==
714 23:21:58.370814 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:21:58.373636 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 23:21:58.374214 ==
717 23:21:58.380781 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:21:58.387013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:21:58.394724 [CA 0] Center 37 (7~68) winsize 62
720 23:21:58.397632 [CA 1] Center 37 (7~68) winsize 62
721 23:21:58.400908 [CA 2] Center 35 (5~66) winsize 62
722 23:21:58.404512 [CA 3] Center 35 (5~66) winsize 62
723 23:21:58.408239 [CA 4] Center 34 (3~65) winsize 63
724 23:21:58.410924 [CA 5] Center 33 (3~64) winsize 62
725 23:21:58.411436
726 23:21:58.415154 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 23:21:58.415865
728 23:21:58.418600 [CATrainingPosCal] consider 1 rank data
729 23:21:58.421291 u2DelayCellTimex100 = 270/100 ps
730 23:21:58.424859 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 23:21:58.427768 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 23:21:58.434363 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 23:21:58.438561 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
734 23:21:58.441380 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 23:21:58.444386 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 23:21:58.445014
737 23:21:58.447452 CA PerBit enable=1, Macro0, CA PI delay=33
738 23:21:58.447949
739 23:21:58.450516 [CBTSetCACLKResult] CA Dly = 33
740 23:21:58.450991 CS Dly: 6 (0~37)
741 23:21:58.454466 ==
742 23:21:58.457601 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:21:58.460936 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 23:21:58.461503 ==
745 23:21:58.464362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:21:58.470825 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:21:58.480198 [CA 0] Center 37 (7~68) winsize 62
748 23:21:58.484127 [CA 1] Center 37 (6~68) winsize 63
749 23:21:58.487751 [CA 2] Center 35 (4~66) winsize 63
750 23:21:58.490603 [CA 3] Center 35 (4~66) winsize 63
751 23:21:58.493391 [CA 4] Center 33 (3~64) winsize 62
752 23:21:58.496881 [CA 5] Center 34 (3~65) winsize 63
753 23:21:58.497357
754 23:21:58.500478 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 23:21:58.501013
756 23:21:58.503801 [CATrainingPosCal] consider 2 rank data
757 23:21:58.507527 u2DelayCellTimex100 = 270/100 ps
758 23:21:58.510348 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 23:21:58.513773 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 23:21:58.520984 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 23:21:58.523997 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
762 23:21:58.527681 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 23:21:58.530235 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 23:21:58.530805
765 23:21:58.533884 CA PerBit enable=1, Macro0, CA PI delay=33
766 23:21:58.534360
767 23:21:58.536881 [CBTSetCACLKResult] CA Dly = 33
768 23:21:58.537356 CS Dly: 6 (0~37)
769 23:21:58.537735
770 23:21:58.540276 ----->DramcWriteLeveling(PI) begin...
771 23:21:58.543815 ==
772 23:21:58.547216 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:21:58.550871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 23:21:58.551349 ==
775 23:21:58.554121 Write leveling (Byte 0): 29 => 29
776 23:21:58.557154 Write leveling (Byte 1): 26 => 26
777 23:21:58.560916 DramcWriteLeveling(PI) end<-----
778 23:21:58.561489
779 23:21:58.561865 ==
780 23:21:58.563650 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:21:58.567178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 23:21:58.567747 ==
783 23:21:58.570348 [Gating] SW mode calibration
784 23:21:58.576964 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:21:58.580781 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:21:58.587285 0 6 0 | B1->B0 | 3434 3232 | 0 0 | (1 0) (0 0)
787 23:21:58.590306 0 6 4 | B1->B0 | 2929 2626 | 1 0 | (1 0) (1 0)
788 23:21:58.594132 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:21:58.600554 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:21:58.604698 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:21:58.606811 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:21:58.613556 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:21:58.617066 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:21:58.620954 0 7 0 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (1 1)
795 23:21:58.627783 0 7 4 | B1->B0 | 3737 3b3b | 0 0 | (0 0) (0 0)
796 23:21:58.630459 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 23:21:58.633270 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 23:21:58.640580 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 23:21:58.645090 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 23:21:58.646984 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 23:21:58.653727 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 23:21:58.656806 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
803 23:21:58.660413 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 23:21:58.666959 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 23:21:58.670229 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 23:21:58.673246 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 23:21:58.680402 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 23:21:58.683310 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 23:21:58.687068 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 23:21:58.693442 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 23:21:58.696907 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 23:21:58.700056 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 23:21:58.703741 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 23:21:58.710281 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 23:21:58.713476 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 23:21:58.716750 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 23:21:58.723309 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 23:21:58.726971 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
819 23:21:58.730053 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 23:21:58.733826 Total UI for P1: 0, mck2ui 16
821 23:21:58.736694 best dqsien dly found for B0: ( 0, 10, 0)
822 23:21:58.740489 Total UI for P1: 0, mck2ui 16
823 23:21:58.743945 best dqsien dly found for B1: ( 0, 10, 0)
824 23:21:58.747358 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
825 23:21:58.750293 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
826 23:21:58.750766
827 23:21:58.756921 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
828 23:21:58.760141 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 23:21:58.760610 [Gating] SW calibration Done
830 23:21:58.763416 ==
831 23:21:58.767608 Dram Type= 6, Freq= 0, CH_0, rank 0
832 23:21:58.770983 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 23:21:58.771456 ==
834 23:21:58.771832 RX Vref Scan: 0
835 23:21:58.772182
836 23:21:58.775018 RX Vref 0 -> 0, step: 1
837 23:21:58.775592
838 23:21:58.777976 RX Delay -130 -> 252, step: 16
839 23:21:58.780688 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
840 23:21:58.784290 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 23:21:58.787801 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
842 23:21:58.790773 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 23:21:58.798712 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 23:21:58.801099 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 23:21:58.804058 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 23:21:58.807781 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 23:21:58.811211 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 23:21:58.817760 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 23:21:58.820677 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 23:21:58.824063 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 23:21:58.828006 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 23:21:58.830839 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 23:21:58.837470 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 23:21:58.841090 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 23:21:58.841561 ==
856 23:21:58.844566 Dram Type= 6, Freq= 0, CH_0, rank 0
857 23:21:58.847475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 23:21:58.848099 ==
859 23:21:58.851245 DQS Delay:
860 23:21:58.851865 DQS0 = 0, DQS1 = 0
861 23:21:58.852259 DQM Delay:
862 23:21:58.854293 DQM0 = 82, DQM1 = 74
863 23:21:58.854919 DQ Delay:
864 23:21:58.857639 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
865 23:21:58.860932 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
866 23:21:58.864245 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
867 23:21:58.867403 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 23:21:58.868128
869 23:21:58.868668
870 23:21:58.869088 ==
871 23:21:58.870843 Dram Type= 6, Freq= 0, CH_0, rank 0
872 23:21:58.877683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 23:21:58.878385 ==
874 23:21:58.878826
875 23:21:58.879178
876 23:21:58.879516 TX Vref Scan disable
877 23:21:58.880759 == TX Byte 0 ==
878 23:21:58.884208 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
879 23:21:58.887881 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
880 23:21:58.891065 == TX Byte 1 ==
881 23:21:58.894731 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
882 23:21:58.897898 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
883 23:21:58.901572 ==
884 23:21:58.904229 Dram Type= 6, Freq= 0, CH_0, rank 0
885 23:21:58.907683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 23:21:58.908233 ==
887 23:21:58.920336 TX Vref=22, minBit 0, minWin=27, winSum=441
888 23:21:58.923441 TX Vref=24, minBit 0, minWin=27, winSum=444
889 23:21:58.926450 TX Vref=26, minBit 5, minWin=27, winSum=450
890 23:21:58.930220 TX Vref=28, minBit 0, minWin=28, winSum=449
891 23:21:58.933247 TX Vref=30, minBit 0, minWin=28, winSum=451
892 23:21:58.939978 TX Vref=32, minBit 0, minWin=28, winSum=453
893 23:21:58.943675 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
894 23:21:58.944247
895 23:21:58.947251 Final TX Range 1 Vref 32
896 23:21:58.947869
897 23:21:58.948250 ==
898 23:21:58.950081 Dram Type= 6, Freq= 0, CH_0, rank 0
899 23:21:58.953441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 23:21:58.954010 ==
901 23:21:58.956127
902 23:21:58.956597
903 23:21:58.957033 TX Vref Scan disable
904 23:21:58.960491 == TX Byte 0 ==
905 23:21:58.962930 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
906 23:21:58.971370 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
907 23:21:58.971842 == TX Byte 1 ==
908 23:21:58.973502 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
909 23:21:58.980147 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
910 23:21:58.980802
911 23:21:58.981196 [DATLAT]
912 23:21:58.981545 Freq=800, CH0 RK0
913 23:21:58.981881
914 23:21:58.983456 DATLAT Default: 0xa
915 23:21:58.984023 0, 0xFFFF, sum = 0
916 23:21:58.987006 1, 0xFFFF, sum = 0
917 23:21:58.987490 2, 0xFFFF, sum = 0
918 23:21:58.990560 3, 0xFFFF, sum = 0
919 23:21:58.991040 4, 0xFFFF, sum = 0
920 23:21:58.993643 5, 0xFFFF, sum = 0
921 23:21:58.996608 6, 0xFFFF, sum = 0
922 23:21:58.997138 7, 0xFFFF, sum = 0
923 23:21:58.997525 8, 0x0, sum = 1
924 23:21:58.999987 9, 0x0, sum = 2
925 23:21:59.000583 10, 0x0, sum = 3
926 23:21:59.002891 11, 0x0, sum = 4
927 23:21:59.003368 best_step = 9
928 23:21:59.003738
929 23:21:59.004092 ==
930 23:21:59.006326 Dram Type= 6, Freq= 0, CH_0, rank 0
931 23:21:59.013919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 23:21:59.014461 ==
933 23:21:59.014809 RX Vref Scan: 1
934 23:21:59.015125
935 23:21:59.016894 Set Vref Range= 32 -> 127
936 23:21:59.017477
937 23:21:59.019928 RX Vref 32 -> 127, step: 1
938 23:21:59.020361
939 23:21:59.023001 RX Delay -111 -> 252, step: 8
940 23:21:59.023594
941 23:21:59.027060 Set Vref, RX VrefLevel [Byte0]: 32
942 23:21:59.027494 [Byte1]: 32
943 23:21:59.030894
944 23:21:59.031317 Set Vref, RX VrefLevel [Byte0]: 33
945 23:21:59.034569 [Byte1]: 33
946 23:21:59.039326
947 23:21:59.039778 Set Vref, RX VrefLevel [Byte0]: 34
948 23:21:59.042231 [Byte1]: 34
949 23:21:59.046899
950 23:21:59.047445 Set Vref, RX VrefLevel [Byte0]: 35
951 23:21:59.049650 [Byte1]: 35
952 23:21:59.054017
953 23:21:59.054439 Set Vref, RX VrefLevel [Byte0]: 36
954 23:21:59.057091 [Byte1]: 36
955 23:21:59.061622
956 23:21:59.062150 Set Vref, RX VrefLevel [Byte0]: 37
957 23:21:59.065663 [Byte1]: 37
958 23:21:59.069046
959 23:21:59.069468 Set Vref, RX VrefLevel [Byte0]: 38
960 23:21:59.072561 [Byte1]: 38
961 23:21:59.076837
962 23:21:59.077305 Set Vref, RX VrefLevel [Byte0]: 39
963 23:21:59.079888 [Byte1]: 39
964 23:21:59.084562
965 23:21:59.085105 Set Vref, RX VrefLevel [Byte0]: 40
966 23:21:59.089048 [Byte1]: 40
967 23:21:59.092296
968 23:21:59.092914 Set Vref, RX VrefLevel [Byte0]: 41
969 23:21:59.095920 [Byte1]: 41
970 23:21:59.100635
971 23:21:59.101175 Set Vref, RX VrefLevel [Byte0]: 42
972 23:21:59.103074 [Byte1]: 42
973 23:21:59.107766
974 23:21:59.108230 Set Vref, RX VrefLevel [Byte0]: 43
975 23:21:59.111333 [Byte1]: 43
976 23:21:59.114835
977 23:21:59.115302 Set Vref, RX VrefLevel [Byte0]: 44
978 23:21:59.118156 [Byte1]: 44
979 23:21:59.122814
980 23:21:59.123387 Set Vref, RX VrefLevel [Byte0]: 45
981 23:21:59.126675 [Byte1]: 45
982 23:21:59.130825
983 23:21:59.131406 Set Vref, RX VrefLevel [Byte0]: 46
984 23:21:59.133704 [Byte1]: 46
985 23:21:59.138215
986 23:21:59.138839 Set Vref, RX VrefLevel [Byte0]: 47
987 23:21:59.141324 [Byte1]: 47
988 23:21:59.145704
989 23:21:59.146171 Set Vref, RX VrefLevel [Byte0]: 48
990 23:21:59.149160 [Byte1]: 48
991 23:21:59.153036
992 23:21:59.153506 Set Vref, RX VrefLevel [Byte0]: 49
993 23:21:59.156521 [Byte1]: 49
994 23:21:59.160824
995 23:21:59.161334 Set Vref, RX VrefLevel [Byte0]: 50
996 23:21:59.164368 [Byte1]: 50
997 23:21:59.169993
998 23:21:59.170525 Set Vref, RX VrefLevel [Byte0]: 51
999 23:21:59.171697 [Byte1]: 51
1000 23:21:59.176240
1001 23:21:59.176663 Set Vref, RX VrefLevel [Byte0]: 52
1002 23:21:59.179654 [Byte1]: 52
1003 23:21:59.184696
1004 23:21:59.185309 Set Vref, RX VrefLevel [Byte0]: 53
1005 23:21:59.186947 [Byte1]: 53
1006 23:21:59.191397
1007 23:21:59.191822 Set Vref, RX VrefLevel [Byte0]: 54
1008 23:21:59.194935 [Byte1]: 54
1009 23:21:59.199489
1010 23:21:59.200029 Set Vref, RX VrefLevel [Byte0]: 55
1011 23:21:59.203629 [Byte1]: 55
1012 23:21:59.207763
1013 23:21:59.208229 Set Vref, RX VrefLevel [Byte0]: 56
1014 23:21:59.210276 [Byte1]: 56
1015 23:21:59.215060
1016 23:21:59.215780 Set Vref, RX VrefLevel [Byte0]: 57
1017 23:21:59.219000 [Byte1]: 57
1018 23:21:59.222375
1019 23:21:59.222948 Set Vref, RX VrefLevel [Byte0]: 58
1020 23:21:59.225275 [Byte1]: 58
1021 23:21:59.229465
1022 23:21:59.229934 Set Vref, RX VrefLevel [Byte0]: 59
1023 23:21:59.233508 [Byte1]: 59
1024 23:21:59.237438
1025 23:21:59.237878 Set Vref, RX VrefLevel [Byte0]: 60
1026 23:21:59.240519 [Byte1]: 60
1027 23:21:59.245414
1028 23:21:59.245833 Set Vref, RX VrefLevel [Byte0]: 61
1029 23:21:59.248438 [Byte1]: 61
1030 23:21:59.252977
1031 23:21:59.253480 Set Vref, RX VrefLevel [Byte0]: 62
1032 23:21:59.256354 [Byte1]: 62
1033 23:21:59.260590
1034 23:21:59.261150 Set Vref, RX VrefLevel [Byte0]: 63
1035 23:21:59.263551 [Byte1]: 63
1036 23:21:59.267935
1037 23:21:59.268460 Set Vref, RX VrefLevel [Byte0]: 64
1038 23:21:59.273277 [Byte1]: 64
1039 23:21:59.275974
1040 23:21:59.276501 Set Vref, RX VrefLevel [Byte0]: 65
1041 23:21:59.279697 [Byte1]: 65
1042 23:21:59.283313
1043 23:21:59.283793 Set Vref, RX VrefLevel [Byte0]: 66
1044 23:21:59.286493 [Byte1]: 66
1045 23:21:59.291397
1046 23:21:59.292018 Set Vref, RX VrefLevel [Byte0]: 67
1047 23:21:59.294424 [Byte1]: 67
1048 23:21:59.298318
1049 23:21:59.298851 Set Vref, RX VrefLevel [Byte0]: 68
1050 23:21:59.305513 [Byte1]: 68
1051 23:21:59.305935
1052 23:21:59.308689 Set Vref, RX VrefLevel [Byte0]: 69
1053 23:21:59.312020 [Byte1]: 69
1054 23:21:59.312543
1055 23:21:59.315037 Set Vref, RX VrefLevel [Byte0]: 70
1056 23:21:59.318295 [Byte1]: 70
1057 23:21:59.318716
1058 23:21:59.321580 Set Vref, RX VrefLevel [Byte0]: 71
1059 23:21:59.325257 [Byte1]: 71
1060 23:21:59.329250
1061 23:21:59.329665 Set Vref, RX VrefLevel [Byte0]: 72
1062 23:21:59.332693 [Byte1]: 72
1063 23:21:59.337019
1064 23:21:59.337526 Set Vref, RX VrefLevel [Byte0]: 73
1065 23:21:59.341295 [Byte1]: 73
1066 23:21:59.345040
1067 23:21:59.345544 Final RX Vref Byte 0 = 51 to rank0
1068 23:21:59.347687 Final RX Vref Byte 1 = 54 to rank0
1069 23:21:59.352035 Final RX Vref Byte 0 = 51 to rank1
1070 23:21:59.355434 Final RX Vref Byte 1 = 54 to rank1==
1071 23:21:59.357737 Dram Type= 6, Freq= 0, CH_0, rank 0
1072 23:21:59.364561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1073 23:21:59.365144 ==
1074 23:21:59.365483 DQS Delay:
1075 23:21:59.365796 DQS0 = 0, DQS1 = 0
1076 23:21:59.367658 DQM Delay:
1077 23:21:59.368193 DQM0 = 84, DQM1 = 73
1078 23:21:59.371133 DQ Delay:
1079 23:21:59.374381 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1080 23:21:59.374810 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1081 23:21:59.378013 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1082 23:21:59.384850 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1083 23:21:59.385398
1084 23:21:59.385764
1085 23:21:59.391618 [DQSOSCAuto] RK0, (LSB)MR18= 0x3131, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1086 23:21:59.394153 CH0 RK0: MR19=606, MR18=3131
1087 23:21:59.401494 CH0_RK0: MR19=0x606, MR18=0x3131, DQSOSC=397, MR23=63, INC=93, DEC=62
1088 23:21:59.402066
1089 23:21:59.404889 ----->DramcWriteLeveling(PI) begin...
1090 23:21:59.405450 ==
1091 23:21:59.407431 Dram Type= 6, Freq= 0, CH_0, rank 1
1092 23:21:59.411582 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1093 23:21:59.412145 ==
1094 23:21:59.414809 Write leveling (Byte 0): 29 => 29
1095 23:21:59.417764 Write leveling (Byte 1): 28 => 28
1096 23:21:59.421117 DramcWriteLeveling(PI) end<-----
1097 23:21:59.421677
1098 23:21:59.422061 ==
1099 23:21:59.424295 Dram Type= 6, Freq= 0, CH_0, rank 1
1100 23:21:59.428413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1101 23:21:59.429038 ==
1102 23:21:59.431326 [Gating] SW mode calibration
1103 23:21:59.437655 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1104 23:21:59.444117 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1105 23:21:59.448081 0 6 0 | B1->B0 | 2f2f 3030 | 1 1 | (1 0) (1 1)
1106 23:21:59.451162 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1107 23:21:59.458089 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1108 23:21:59.461532 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1109 23:21:59.464853 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 23:21:59.471738 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 23:21:59.474346 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 23:21:59.478380 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 23:21:59.484388 0 7 0 | B1->B0 | 2828 3333 | 0 1 | (0 0) (0 0)
1114 23:21:59.487466 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1115 23:21:59.491003 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1116 23:21:59.497832 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1117 23:21:59.501194 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1118 23:21:59.504464 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 23:21:59.508365 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 23:21:59.516348 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 23:21:59.517641 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1122 23:21:59.521965 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1123 23:21:59.527653 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1124 23:21:59.531663 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 23:21:59.534076 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 23:21:59.541577 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 23:21:59.544752 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 23:21:59.547937 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 23:21:59.554541 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 23:21:59.558461 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 23:21:59.561522 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 23:21:59.568222 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 23:21:59.571435 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 23:21:59.574622 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 23:21:59.581332 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 23:21:59.584898 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1137 23:21:59.587862 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1138 23:21:59.594519 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1139 23:21:59.597480 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1140 23:21:59.600702 Total UI for P1: 0, mck2ui 16
1141 23:21:59.604273 best dqsien dly found for B0: ( 0, 10, 0)
1142 23:21:59.607396 Total UI for P1: 0, mck2ui 16
1143 23:21:59.610824 best dqsien dly found for B1: ( 0, 10, 4)
1144 23:21:59.614240 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1145 23:21:59.617497 best DQS1 dly(MCK, UI, PI) = (0, 10, 4)
1146 23:21:59.617965
1147 23:21:59.621178 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1148 23:21:59.624471 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 4)
1149 23:21:59.628312 [Gating] SW calibration Done
1150 23:21:59.628931 ==
1151 23:21:59.630960 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 23:21:59.634390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1153 23:21:59.634950 ==
1154 23:21:59.637765 RX Vref Scan: 0
1155 23:21:59.638229
1156 23:21:59.640927 RX Vref 0 -> 0, step: 1
1157 23:21:59.641390
1158 23:21:59.641761 RX Delay -130 -> 252, step: 16
1159 23:21:59.647617 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1160 23:21:59.691817 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1161 23:21:59.692503 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1162 23:21:59.692958 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1163 23:21:59.693312 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1164 23:21:59.694120 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1165 23:21:59.694566 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1166 23:21:59.695032 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1167 23:21:59.695561 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1168 23:21:59.695922 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1169 23:21:59.696246 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1170 23:21:59.696629 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1171 23:21:59.719500 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1172 23:21:59.720059 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1173 23:21:59.720860 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1174 23:21:59.721245 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1175 23:21:59.721622 ==
1176 23:21:59.722012 Dram Type= 6, Freq= 0, CH_0, rank 1
1177 23:21:59.722433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1178 23:21:59.722772 ==
1179 23:21:59.723090 DQS Delay:
1180 23:21:59.723497 DQS0 = 0, DQS1 = 0
1181 23:21:59.723852 DQM Delay:
1182 23:21:59.724195 DQM0 = 80, DQM1 = 74
1183 23:21:59.724506 DQ Delay:
1184 23:21:59.724923 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1185 23:21:59.727460 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1186 23:21:59.730779 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1187 23:21:59.733999 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1188 23:21:59.734564
1189 23:21:59.734935
1190 23:21:59.735277 ==
1191 23:21:59.737373 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 23:21:59.740923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1193 23:21:59.741480 ==
1194 23:21:59.741855
1195 23:21:59.744607
1196 23:21:59.745119 TX Vref Scan disable
1197 23:21:59.747926 == TX Byte 0 ==
1198 23:21:59.751250 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1199 23:21:59.754780 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1200 23:21:59.757525 == TX Byte 1 ==
1201 23:21:59.760700 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1202 23:21:59.764917 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1203 23:21:59.765507 ==
1204 23:21:59.768573 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 23:21:59.773946 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1206 23:21:59.774487 ==
1207 23:21:59.785838 TX Vref=22, minBit 7, minWin=27, winSum=449
1208 23:21:59.788971 TX Vref=24, minBit 0, minWin=28, winSum=452
1209 23:21:59.792941 TX Vref=26, minBit 2, minWin=28, winSum=457
1210 23:21:59.796176 TX Vref=28, minBit 2, minWin=28, winSum=457
1211 23:21:59.799234 TX Vref=30, minBit 2, minWin=28, winSum=461
1212 23:21:59.806409 TX Vref=32, minBit 0, minWin=28, winSum=454
1213 23:21:59.808801 [TxChooseVref] Worse bit 2, Min win 28, Win sum 461, Final Vref 30
1214 23:21:59.809410
1215 23:21:59.812099 Final TX Range 1 Vref 30
1216 23:21:59.812635
1217 23:21:59.813149 ==
1218 23:21:59.816632 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 23:21:59.819321 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1220 23:21:59.819786 ==
1221 23:21:59.823139
1222 23:21:59.823655
1223 23:21:59.824008 TX Vref Scan disable
1224 23:21:59.826333 == TX Byte 0 ==
1225 23:21:59.829321 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1226 23:21:59.832862 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1227 23:21:59.836084 == TX Byte 1 ==
1228 23:21:59.839474 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1229 23:21:59.842196 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1230 23:21:59.845666
1231 23:21:59.846125 [DATLAT]
1232 23:21:59.846492 Freq=800, CH0 RK1
1233 23:21:59.846839
1234 23:21:59.849341 DATLAT Default: 0x9
1235 23:21:59.849827 0, 0xFFFF, sum = 0
1236 23:21:59.852161 1, 0xFFFF, sum = 0
1237 23:21:59.852593 2, 0xFFFF, sum = 0
1238 23:21:59.856360 3, 0xFFFF, sum = 0
1239 23:21:59.856828 4, 0xFFFF, sum = 0
1240 23:21:59.859155 5, 0xFFFF, sum = 0
1241 23:21:59.862346 6, 0xFFFF, sum = 0
1242 23:21:59.862870 7, 0xFFFF, sum = 0
1243 23:21:59.863220 8, 0x0, sum = 1
1244 23:21:59.865902 9, 0x0, sum = 2
1245 23:21:59.866428 10, 0x0, sum = 3
1246 23:21:59.869014 11, 0x0, sum = 4
1247 23:21:59.869538 best_step = 9
1248 23:21:59.869876
1249 23:21:59.870189 ==
1250 23:21:59.872059 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 23:21:59.879256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1252 23:21:59.879802 ==
1253 23:21:59.880169 RX Vref Scan: 0
1254 23:21:59.880488
1255 23:21:59.882146 RX Vref 0 -> 0, step: 1
1256 23:21:59.882571
1257 23:21:59.885550 RX Delay -111 -> 252, step: 8
1258 23:21:59.889575 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1259 23:21:59.891889 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1260 23:21:59.898658 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1261 23:21:59.902091 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1262 23:21:59.905325 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1263 23:21:59.909196 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1264 23:21:59.912628 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1265 23:21:59.919687 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1266 23:21:59.922928 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1267 23:21:59.926409 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1268 23:21:59.929242 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1269 23:21:59.932192 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1270 23:21:59.939185 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1271 23:21:59.942093 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1272 23:21:59.945134 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1273 23:21:59.948582 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1274 23:21:59.949082 ==
1275 23:21:59.951938 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 23:21:59.958849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1277 23:21:59.959413 ==
1278 23:21:59.959779 DQS Delay:
1279 23:21:59.960116 DQS0 = 0, DQS1 = 0
1280 23:21:59.962259 DQM Delay:
1281 23:21:59.962821 DQM0 = 85, DQM1 = 74
1282 23:21:59.965111 DQ Delay:
1283 23:21:59.968498 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1284 23:21:59.971900 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1285 23:21:59.972421 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1286 23:21:59.979102 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1287 23:21:59.979670
1288 23:21:59.980040
1289 23:21:59.986075 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1290 23:21:59.988284 CH0 RK1: MR19=606, MR18=4141
1291 23:21:59.995360 CH0_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1292 23:21:59.999198 [RxdqsGatingPostProcess] freq 800
1293 23:22:00.001721 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1294 23:22:00.005202 Pre-setting of DQS Precalculation
1295 23:22:00.012048 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1296 23:22:00.012515 ==
1297 23:22:00.015592 Dram Type= 6, Freq= 0, CH_1, rank 0
1298 23:22:00.018401 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1299 23:22:00.018872 ==
1300 23:22:00.021828 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1301 23:22:00.028947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1302 23:22:00.038377 [CA 0] Center 36 (6~67) winsize 62
1303 23:22:00.042085 [CA 1] Center 37 (6~68) winsize 63
1304 23:22:00.044605 [CA 2] Center 34 (4~65) winsize 62
1305 23:22:00.048859 [CA 3] Center 34 (4~65) winsize 62
1306 23:22:00.052067 [CA 4] Center 33 (3~64) winsize 62
1307 23:22:00.055387 [CA 5] Center 33 (3~64) winsize 62
1308 23:22:00.055941
1309 23:22:00.058697 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1310 23:22:00.059359
1311 23:22:00.061981 [CATrainingPosCal] consider 1 rank data
1312 23:22:00.065474 u2DelayCellTimex100 = 270/100 ps
1313 23:22:00.068792 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1314 23:22:00.072011 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1315 23:22:00.078397 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1316 23:22:00.081994 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1317 23:22:00.085055 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1318 23:22:00.088198 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1319 23:22:00.088804
1320 23:22:00.091614 CA PerBit enable=1, Macro0, CA PI delay=33
1321 23:22:00.092172
1322 23:22:00.095267 [CBTSetCACLKResult] CA Dly = 33
1323 23:22:00.095819 CS Dly: 4 (0~35)
1324 23:22:00.098090 ==
1325 23:22:00.098548 Dram Type= 6, Freq= 0, CH_1, rank 1
1326 23:22:00.105094 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1327 23:22:00.105654 ==
1328 23:22:00.108270 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1329 23:22:00.115631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1330 23:22:00.125352 [CA 0] Center 36 (6~67) winsize 62
1331 23:22:00.127802 [CA 1] Center 36 (5~68) winsize 64
1332 23:22:00.131109 [CA 2] Center 34 (4~65) winsize 62
1333 23:22:00.134627 [CA 3] Center 34 (4~65) winsize 62
1334 23:22:00.137858 [CA 4] Center 33 (3~64) winsize 62
1335 23:22:00.142193 [CA 5] Center 33 (3~64) winsize 62
1336 23:22:00.142754
1337 23:22:00.144517 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1338 23:22:00.145027
1339 23:22:00.148702 [CATrainingPosCal] consider 2 rank data
1340 23:22:00.150664 u2DelayCellTimex100 = 270/100 ps
1341 23:22:00.154302 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1342 23:22:00.157540 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1343 23:22:00.164552 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1344 23:22:00.167717 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1345 23:22:00.171414 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1346 23:22:00.174764 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1347 23:22:00.175262
1348 23:22:00.177652 CA PerBit enable=1, Macro0, CA PI delay=33
1349 23:22:00.178107
1350 23:22:00.180978 [CBTSetCACLKResult] CA Dly = 33
1351 23:22:00.181532 CS Dly: 5 (0~37)
1352 23:22:00.181896
1353 23:22:00.184356 ----->DramcWriteLeveling(PI) begin...
1354 23:22:00.187535 ==
1355 23:22:00.191554 Dram Type= 6, Freq= 0, CH_1, rank 0
1356 23:22:00.194348 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1357 23:22:00.194816 ==
1358 23:22:00.197318 Write leveling (Byte 0): 24 => 24
1359 23:22:00.200831 Write leveling (Byte 1): 24 => 24
1360 23:22:00.203935 DramcWriteLeveling(PI) end<-----
1361 23:22:00.204400
1362 23:22:00.204811 ==
1363 23:22:00.207743 Dram Type= 6, Freq= 0, CH_1, rank 0
1364 23:22:00.210486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1365 23:22:00.210975 ==
1366 23:22:00.214083 [Gating] SW mode calibration
1367 23:22:00.220468 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1368 23:22:00.223926 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1369 23:22:00.230744 0 6 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
1370 23:22:00.233656 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1371 23:22:00.237122 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1372 23:22:00.244356 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1373 23:22:00.247889 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 23:22:00.250453 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 23:22:00.257209 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 23:22:00.261135 0 6 28 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
1377 23:22:00.264568 0 7 0 | B1->B0 | 3131 3d3d | 1 1 | (1 1) (0 0)
1378 23:22:00.270914 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1379 23:22:00.274257 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1380 23:22:00.277243 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1381 23:22:00.284264 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 23:22:00.287761 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 23:22:00.290962 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 23:22:00.297634 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1385 23:22:00.301009 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1386 23:22:00.304560 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1387 23:22:00.308245 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 23:22:00.314869 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 23:22:00.317571 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 23:22:00.320937 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 23:22:00.327667 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 23:22:00.331381 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 23:22:00.334697 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 23:22:00.341141 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 23:22:00.344257 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 23:22:00.347551 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 23:22:00.353968 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 23:22:00.357280 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 23:22:00.361718 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 23:22:00.367861 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1401 23:22:00.371538 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1402 23:22:00.374310 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1403 23:22:00.377790 Total UI for P1: 0, mck2ui 16
1404 23:22:00.381180 best dqsien dly found for B0: ( 0, 9, 30)
1405 23:22:00.384733 Total UI for P1: 0, mck2ui 16
1406 23:22:00.387929 best dqsien dly found for B1: ( 0, 10, 0)
1407 23:22:00.391147 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1408 23:22:00.393940 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1409 23:22:00.394500
1410 23:22:00.398183 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1411 23:22:00.404695 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1412 23:22:00.405282 [Gating] SW calibration Done
1413 23:22:00.407747 ==
1414 23:22:00.408213 Dram Type= 6, Freq= 0, CH_1, rank 0
1415 23:22:00.413931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1416 23:22:00.414479 ==
1417 23:22:00.414858 RX Vref Scan: 0
1418 23:22:00.415292
1419 23:22:00.417916 RX Vref 0 -> 0, step: 1
1420 23:22:00.418402
1421 23:22:00.420775 RX Delay -130 -> 252, step: 16
1422 23:22:00.423771 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1423 23:22:00.427504 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1424 23:22:00.430615 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1425 23:22:00.438002 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1426 23:22:00.441372 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1427 23:22:00.444753 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1428 23:22:00.447387 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1429 23:22:00.450482 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1430 23:22:00.457395 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1431 23:22:00.460148 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1432 23:22:00.464138 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1433 23:22:00.467603 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1434 23:22:00.470728 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1435 23:22:00.477297 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1436 23:22:00.481589 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1437 23:22:00.483855 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1438 23:22:00.484415 ==
1439 23:22:00.487240 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 23:22:00.491083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1441 23:22:00.493749 ==
1442 23:22:00.494213 DQS Delay:
1443 23:22:00.494589 DQS0 = 0, DQS1 = 0
1444 23:22:00.497532 DQM Delay:
1445 23:22:00.497997 DQM0 = 80, DQM1 = 73
1446 23:22:00.500564 DQ Delay:
1447 23:22:00.501087 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1448 23:22:00.504222 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1449 23:22:00.507556 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1450 23:22:00.510487 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1451 23:22:00.510952
1452 23:22:00.511319
1453 23:22:00.513385 ==
1454 23:22:00.517539 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 23:22:00.521116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1456 23:22:00.521590 ==
1457 23:22:00.522169
1458 23:22:00.522551
1459 23:22:00.523935 TX Vref Scan disable
1460 23:22:00.524400 == TX Byte 0 ==
1461 23:22:00.531256 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1462 23:22:00.533790 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1463 23:22:00.534261 == TX Byte 1 ==
1464 23:22:00.540515 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1465 23:22:00.544273 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1466 23:22:00.544884 ==
1467 23:22:00.547180 Dram Type= 6, Freq= 0, CH_1, rank 0
1468 23:22:00.550307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1469 23:22:00.550887 ==
1470 23:22:00.564125 TX Vref=22, minBit 3, minWin=27, winSum=446
1471 23:22:00.567511 TX Vref=24, minBit 3, minWin=27, winSum=451
1472 23:22:00.570255 TX Vref=26, minBit 3, minWin=27, winSum=452
1473 23:22:00.574332 TX Vref=28, minBit 0, minWin=28, winSum=456
1474 23:22:00.576837 TX Vref=30, minBit 0, minWin=28, winSum=460
1475 23:22:00.580418 TX Vref=32, minBit 0, minWin=28, winSum=456
1476 23:22:00.587567 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1477 23:22:00.588125
1478 23:22:00.590780 Final TX Range 1 Vref 30
1479 23:22:00.591348
1480 23:22:00.591721 ==
1481 23:22:00.593506 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 23:22:00.597208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1483 23:22:00.597681 ==
1484 23:22:00.598052
1485 23:22:00.600284
1486 23:22:00.600778 TX Vref Scan disable
1487 23:22:00.603574 == TX Byte 0 ==
1488 23:22:00.606601 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1489 23:22:00.610576 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1490 23:22:00.613803 == TX Byte 1 ==
1491 23:22:00.617981 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1492 23:22:00.620040 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1493 23:22:00.620513
1494 23:22:00.624204 [DATLAT]
1495 23:22:00.624837 Freq=800, CH1 RK0
1496 23:22:00.625222
1497 23:22:00.627471 DATLAT Default: 0xa
1498 23:22:00.627935 0, 0xFFFF, sum = 0
1499 23:22:00.630545 1, 0xFFFF, sum = 0
1500 23:22:00.631102 2, 0xFFFF, sum = 0
1501 23:22:00.633430 3, 0xFFFF, sum = 0
1502 23:22:00.633901 4, 0xFFFF, sum = 0
1503 23:22:00.636535 5, 0xFFFF, sum = 0
1504 23:22:00.637051 6, 0xFFFF, sum = 0
1505 23:22:00.640077 7, 0xFFFF, sum = 0
1506 23:22:00.640550 8, 0x0, sum = 1
1507 23:22:00.643642 9, 0x0, sum = 2
1508 23:22:00.644207 10, 0x0, sum = 3
1509 23:22:00.646606 11, 0x0, sum = 4
1510 23:22:00.647174 best_step = 9
1511 23:22:00.647548
1512 23:22:00.647892 ==
1513 23:22:00.650230 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 23:22:00.657112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1515 23:22:00.657679 ==
1516 23:22:00.658060 RX Vref Scan: 1
1517 23:22:00.658408
1518 23:22:00.659716 Set Vref Range= 32 -> 127
1519 23:22:00.660182
1520 23:22:00.663428 RX Vref 32 -> 127, step: 1
1521 23:22:00.663987
1522 23:22:00.667033 RX Delay -111 -> 252, step: 8
1523 23:22:00.667597
1524 23:22:00.667971 Set Vref, RX VrefLevel [Byte0]: 32
1525 23:22:00.670164 [Byte1]: 32
1526 23:22:00.674825
1527 23:22:00.675378 Set Vref, RX VrefLevel [Byte0]: 33
1528 23:22:00.677676 [Byte1]: 33
1529 23:22:00.682643
1530 23:22:00.683199 Set Vref, RX VrefLevel [Byte0]: 34
1531 23:22:00.684893 [Byte1]: 34
1532 23:22:00.689922
1533 23:22:00.690479 Set Vref, RX VrefLevel [Byte0]: 35
1534 23:22:00.693418 [Byte1]: 35
1535 23:22:00.697385
1536 23:22:00.697851 Set Vref, RX VrefLevel [Byte0]: 36
1537 23:22:00.700780 [Byte1]: 36
1538 23:22:00.704812
1539 23:22:00.705282 Set Vref, RX VrefLevel [Byte0]: 37
1540 23:22:00.707903 [Byte1]: 37
1541 23:22:00.712702
1542 23:22:00.713344 Set Vref, RX VrefLevel [Byte0]: 38
1543 23:22:00.715860 [Byte1]: 38
1544 23:22:00.720374
1545 23:22:00.720979 Set Vref, RX VrefLevel [Byte0]: 39
1546 23:22:00.723749 [Byte1]: 39
1547 23:22:00.727976
1548 23:22:00.728531 Set Vref, RX VrefLevel [Byte0]: 40
1549 23:22:00.731528 [Byte1]: 40
1550 23:22:00.736293
1551 23:22:00.736901 Set Vref, RX VrefLevel [Byte0]: 41
1552 23:22:00.738865 [Byte1]: 41
1553 23:22:00.743477
1554 23:22:00.744036 Set Vref, RX VrefLevel [Byte0]: 42
1555 23:22:00.746878 [Byte1]: 42
1556 23:22:00.750625
1557 23:22:00.751217 Set Vref, RX VrefLevel [Byte0]: 43
1558 23:22:00.754702 [Byte1]: 43
1559 23:22:00.759439
1560 23:22:00.759994 Set Vref, RX VrefLevel [Byte0]: 44
1561 23:22:00.762238 [Byte1]: 44
1562 23:22:00.766215
1563 23:22:00.766772 Set Vref, RX VrefLevel [Byte0]: 45
1564 23:22:00.769775 [Byte1]: 45
1565 23:22:00.774097
1566 23:22:00.774652 Set Vref, RX VrefLevel [Byte0]: 46
1567 23:22:00.776843 [Byte1]: 46
1568 23:22:00.781675
1569 23:22:00.782231 Set Vref, RX VrefLevel [Byte0]: 47
1570 23:22:00.784768 [Byte1]: 47
1571 23:22:00.789107
1572 23:22:00.789660 Set Vref, RX VrefLevel [Byte0]: 48
1573 23:22:00.792558 [Byte1]: 48
1574 23:22:00.797277
1575 23:22:00.797834 Set Vref, RX VrefLevel [Byte0]: 49
1576 23:22:00.800146 [Byte1]: 49
1577 23:22:00.804237
1578 23:22:00.804945 Set Vref, RX VrefLevel [Byte0]: 50
1579 23:22:00.807837 [Byte1]: 50
1580 23:22:00.812102
1581 23:22:00.812659 Set Vref, RX VrefLevel [Byte0]: 51
1582 23:22:00.815056 [Byte1]: 51
1583 23:22:00.819776
1584 23:22:00.820337 Set Vref, RX VrefLevel [Byte0]: 52
1585 23:22:00.823848 [Byte1]: 52
1586 23:22:00.826984
1587 23:22:00.827451 Set Vref, RX VrefLevel [Byte0]: 53
1588 23:22:00.830838 [Byte1]: 53
1589 23:22:00.836804
1590 23:22:00.837361 Set Vref, RX VrefLevel [Byte0]: 54
1591 23:22:00.838352 [Byte1]: 54
1592 23:22:00.843199
1593 23:22:00.843760 Set Vref, RX VrefLevel [Byte0]: 55
1594 23:22:00.846133 [Byte1]: 55
1595 23:22:00.851263
1596 23:22:00.851818 Set Vref, RX VrefLevel [Byte0]: 56
1597 23:22:00.854227 [Byte1]: 56
1598 23:22:00.858672
1599 23:22:00.859235 Set Vref, RX VrefLevel [Byte0]: 57
1600 23:22:00.861950 [Byte1]: 57
1601 23:22:00.865633
1602 23:22:00.866186 Set Vref, RX VrefLevel [Byte0]: 58
1603 23:22:00.869401 [Byte1]: 58
1604 23:22:00.874633
1605 23:22:00.875187 Set Vref, RX VrefLevel [Byte0]: 59
1606 23:22:00.876193 [Byte1]: 59
1607 23:22:00.881402
1608 23:22:00.881962 Set Vref, RX VrefLevel [Byte0]: 60
1609 23:22:00.883840 [Byte1]: 60
1610 23:22:00.889074
1611 23:22:00.889627 Set Vref, RX VrefLevel [Byte0]: 61
1612 23:22:00.891760 [Byte1]: 61
1613 23:22:00.896291
1614 23:22:00.896884 Set Vref, RX VrefLevel [Byte0]: 62
1615 23:22:00.899543 [Byte1]: 62
1616 23:22:00.904417
1617 23:22:00.905135 Set Vref, RX VrefLevel [Byte0]: 63
1618 23:22:00.906883 [Byte1]: 63
1619 23:22:00.912515
1620 23:22:00.913121 Set Vref, RX VrefLevel [Byte0]: 64
1621 23:22:00.914953 [Byte1]: 64
1622 23:22:00.919278
1623 23:22:00.919831 Set Vref, RX VrefLevel [Byte0]: 65
1624 23:22:00.922230 [Byte1]: 65
1625 23:22:00.927349
1626 23:22:00.927901 Set Vref, RX VrefLevel [Byte0]: 66
1627 23:22:00.930144 [Byte1]: 66
1628 23:22:00.934375
1629 23:22:00.934929 Set Vref, RX VrefLevel [Byte0]: 67
1630 23:22:00.937695 [Byte1]: 67
1631 23:22:00.941927
1632 23:22:00.942487 Set Vref, RX VrefLevel [Byte0]: 68
1633 23:22:00.946386 [Byte1]: 68
1634 23:22:00.950268
1635 23:22:00.950817 Set Vref, RX VrefLevel [Byte0]: 69
1636 23:22:00.953440 [Byte1]: 69
1637 23:22:00.957074
1638 23:22:00.957625 Set Vref, RX VrefLevel [Byte0]: 70
1639 23:22:00.960451 [Byte1]: 70
1640 23:22:00.965944
1641 23:22:00.966510 Set Vref, RX VrefLevel [Byte0]: 71
1642 23:22:00.968349 [Byte1]: 71
1643 23:22:00.972756
1644 23:22:00.973311 Set Vref, RX VrefLevel [Byte0]: 72
1645 23:22:00.976036 [Byte1]: 72
1646 23:22:00.980683
1647 23:22:00.981282 Set Vref, RX VrefLevel [Byte0]: 73
1648 23:22:00.983600 [Byte1]: 73
1649 23:22:00.988424
1650 23:22:00.989046 Set Vref, RX VrefLevel [Byte0]: 74
1651 23:22:00.991552 [Byte1]: 74
1652 23:22:00.995709
1653 23:22:00.996263 Set Vref, RX VrefLevel [Byte0]: 75
1654 23:22:00.998888 [Byte1]: 75
1655 23:22:01.003276
1656 23:22:01.003827 Set Vref, RX VrefLevel [Byte0]: 76
1657 23:22:01.006984 [Byte1]: 76
1658 23:22:01.010420
1659 23:22:01.010889 Final RX Vref Byte 0 = 59 to rank0
1660 23:22:01.014723 Final RX Vref Byte 1 = 56 to rank0
1661 23:22:01.017806 Final RX Vref Byte 0 = 59 to rank1
1662 23:22:01.021324 Final RX Vref Byte 1 = 56 to rank1==
1663 23:22:01.024462 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 23:22:01.030696 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1665 23:22:01.031238 ==
1666 23:22:01.031615 DQS Delay:
1667 23:22:01.031962 DQS0 = 0, DQS1 = 0
1668 23:22:01.034125 DQM Delay:
1669 23:22:01.034679 DQM0 = 81, DQM1 = 74
1670 23:22:01.037325 DQ Delay:
1671 23:22:01.041634 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1672 23:22:01.044319 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1673 23:22:01.048085 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1674 23:22:01.050826 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
1675 23:22:01.051293
1676 23:22:01.051770
1677 23:22:01.057146 [DQSOSCAuto] RK0, (LSB)MR18= 0x5353, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1678 23:22:01.061223 CH1 RK0: MR19=606, MR18=5353
1679 23:22:01.067686 CH1_RK0: MR19=0x606, MR18=0x5353, DQSOSC=389, MR23=63, INC=97, DEC=65
1680 23:22:01.068267
1681 23:22:01.070396 ----->DramcWriteLeveling(PI) begin...
1682 23:22:01.070869 ==
1683 23:22:01.074201 Dram Type= 6, Freq= 0, CH_1, rank 1
1684 23:22:01.077356 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1685 23:22:01.077920 ==
1686 23:22:01.080316 Write leveling (Byte 0): 26 => 26
1687 23:22:01.084561 Write leveling (Byte 1): 26 => 26
1688 23:22:01.087293 DramcWriteLeveling(PI) end<-----
1689 23:22:01.087760
1690 23:22:01.088129 ==
1691 23:22:01.090663 Dram Type= 6, Freq= 0, CH_1, rank 1
1692 23:22:01.094080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1693 23:22:01.094604 ==
1694 23:22:01.097202 [Gating] SW mode calibration
1695 23:22:01.104880 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1696 23:22:01.110611 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1697 23:22:01.113949 0 6 0 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
1698 23:22:01.117432 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1699 23:22:01.124150 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1700 23:22:01.127553 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1701 23:22:01.130885 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1702 23:22:01.137079 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1703 23:22:01.140775 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1704 23:22:01.144275 0 6 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
1705 23:22:01.150980 0 7 0 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
1706 23:22:01.154003 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1707 23:22:01.156953 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1708 23:22:01.163893 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1709 23:22:01.167346 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1710 23:22:01.170425 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1711 23:22:01.177001 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1712 23:22:01.180611 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1713 23:22:01.183564 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1714 23:22:01.191117 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 23:22:01.193627 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 23:22:01.197151 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 23:22:01.201626 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 23:22:01.207774 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 23:22:01.210594 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 23:22:01.214221 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 23:22:01.220838 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 23:22:01.224108 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 23:22:01.227103 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 23:22:01.234817 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 23:22:01.237571 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 23:22:01.240935 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 23:22:01.247285 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 23:22:01.251274 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1729 23:22:01.254332 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1730 23:22:01.257461 Total UI for P1: 0, mck2ui 16
1731 23:22:01.260668 best dqsien dly found for B0: ( 0, 9, 28)
1732 23:22:01.264024 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1733 23:22:01.267916 Total UI for P1: 0, mck2ui 16
1734 23:22:01.270617 best dqsien dly found for B1: ( 0, 10, 0)
1735 23:22:01.274525 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1736 23:22:01.281068 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1737 23:22:01.281631
1738 23:22:01.284648 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1739 23:22:01.288669 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1740 23:22:01.291613 [Gating] SW calibration Done
1741 23:22:01.292179 ==
1742 23:22:01.294593 Dram Type= 6, Freq= 0, CH_1, rank 1
1743 23:22:01.298441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1744 23:22:01.298912 ==
1745 23:22:01.299281 RX Vref Scan: 0
1746 23:22:01.301225
1747 23:22:01.301683 RX Vref 0 -> 0, step: 1
1748 23:22:01.302055
1749 23:22:01.304514 RX Delay -130 -> 252, step: 16
1750 23:22:01.307889 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1751 23:22:01.311511 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1752 23:22:01.317425 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1753 23:22:01.321784 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1754 23:22:01.323803 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1755 23:22:01.327398 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1756 23:22:01.331059 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1757 23:22:01.337622 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1758 23:22:01.340988 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1759 23:22:01.345178 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1760 23:22:01.347355 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1761 23:22:01.351208 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1762 23:22:01.357179 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1763 23:22:01.360805 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1764 23:22:01.363795 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1765 23:22:01.368036 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1766 23:22:01.368594 ==
1767 23:22:01.370872 Dram Type= 6, Freq= 0, CH_1, rank 1
1768 23:22:01.377234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1769 23:22:01.377702 ==
1770 23:22:01.378071 DQS Delay:
1771 23:22:01.380376 DQS0 = 0, DQS1 = 0
1772 23:22:01.380984 DQM Delay:
1773 23:22:01.381362 DQM0 = 85, DQM1 = 74
1774 23:22:01.384315 DQ Delay:
1775 23:22:01.387047 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1776 23:22:01.390758 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1777 23:22:01.394100 DQ8 =53, DQ9 =69, DQ10 =69, DQ11 =69
1778 23:22:01.397512 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1779 23:22:01.398076
1780 23:22:01.398445
1781 23:22:01.398785 ==
1782 23:22:01.400647 Dram Type= 6, Freq= 0, CH_1, rank 1
1783 23:22:01.403825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1784 23:22:01.404289 ==
1785 23:22:01.404656
1786 23:22:01.405067
1787 23:22:01.406992 TX Vref Scan disable
1788 23:22:01.410634 == TX Byte 0 ==
1789 23:22:01.413954 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1790 23:22:01.418301 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1791 23:22:01.421025 == TX Byte 1 ==
1792 23:22:01.424327 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1793 23:22:01.426750 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1794 23:22:01.427215 ==
1795 23:22:01.430470 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 23:22:01.434242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1797 23:22:01.434810 ==
1798 23:22:01.448051 TX Vref=22, minBit 0, minWin=27, winSum=445
1799 23:22:01.452159 TX Vref=24, minBit 0, minWin=27, winSum=450
1800 23:22:01.454517 TX Vref=26, minBit 9, minWin=27, winSum=456
1801 23:22:01.458447 TX Vref=28, minBit 9, minWin=27, winSum=455
1802 23:22:01.460929 TX Vref=30, minBit 9, minWin=27, winSum=454
1803 23:22:01.464501 TX Vref=32, minBit 0, minWin=28, winSum=454
1804 23:22:01.470950 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1805 23:22:01.471497
1806 23:22:01.474587 Final TX Range 1 Vref 32
1807 23:22:01.475050
1808 23:22:01.475416 ==
1809 23:22:01.478312 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 23:22:01.481256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1811 23:22:01.481718 ==
1812 23:22:01.482160
1813 23:22:01.484466
1814 23:22:01.485175 TX Vref Scan disable
1815 23:22:01.487881 == TX Byte 0 ==
1816 23:22:01.490810 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1817 23:22:01.494434 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1818 23:22:01.498487 == TX Byte 1 ==
1819 23:22:01.501193 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1820 23:22:01.504673 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1821 23:22:01.505284
1822 23:22:01.508327 [DATLAT]
1823 23:22:01.508942 Freq=800, CH1 RK1
1824 23:22:01.509323
1825 23:22:01.511702 DATLAT Default: 0x9
1826 23:22:01.512288 0, 0xFFFF, sum = 0
1827 23:22:01.515338 1, 0xFFFF, sum = 0
1828 23:22:01.515805 2, 0xFFFF, sum = 0
1829 23:22:01.517445 3, 0xFFFF, sum = 0
1830 23:22:01.517950 4, 0xFFFF, sum = 0
1831 23:22:01.521166 5, 0xFFFF, sum = 0
1832 23:22:01.521629 6, 0xFFFF, sum = 0
1833 23:22:01.524181 7, 0xFFFF, sum = 0
1834 23:22:01.524644 8, 0x0, sum = 1
1835 23:22:01.528237 9, 0x0, sum = 2
1836 23:22:01.528875 10, 0x0, sum = 3
1837 23:22:01.531651 11, 0x0, sum = 4
1838 23:22:01.532211 best_step = 9
1839 23:22:01.532820
1840 23:22:01.533365 ==
1841 23:22:01.534786 Dram Type= 6, Freq= 0, CH_1, rank 1
1842 23:22:01.541753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1843 23:22:01.542307 ==
1844 23:22:01.542713 RX Vref Scan: 0
1845 23:22:01.543058
1846 23:22:01.543952 RX Vref 0 -> 0, step: 1
1847 23:22:01.544408
1848 23:22:01.547768 RX Delay -111 -> 252, step: 8
1849 23:22:01.550872 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1850 23:22:01.554970 iDelay=217, Bit 1, Center 80 (-39 ~ 200) 240
1851 23:22:01.561170 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1852 23:22:01.564752 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1853 23:22:01.567552 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1854 23:22:01.571439 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1855 23:22:01.574926 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1856 23:22:01.577567 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1857 23:22:01.584319 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1858 23:22:01.587723 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1859 23:22:01.590721 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1860 23:22:01.594864 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1861 23:22:01.601177 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1862 23:22:01.604953 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1863 23:22:01.607632 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1864 23:22:01.611025 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1865 23:22:01.611494 ==
1866 23:22:01.615717 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 23:22:01.617591 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1868 23:22:01.621523 ==
1869 23:22:01.621981 DQS Delay:
1870 23:22:01.622348 DQS0 = 0, DQS1 = 0
1871 23:22:01.624627 DQM Delay:
1872 23:22:01.625129 DQM0 = 84, DQM1 = 75
1873 23:22:01.627760 DQ Delay:
1874 23:22:01.628316 DQ0 =84, DQ1 =80, DQ2 =76, DQ3 =84
1875 23:22:01.631369 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1876 23:22:01.634532 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1877 23:22:01.637587 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1878 23:22:01.638052
1879 23:22:01.641701
1880 23:22:01.647232 [DQSOSCAuto] RK1, (LSB)MR18= 0x3434, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1881 23:22:01.651636 CH1 RK1: MR19=606, MR18=3434
1882 23:22:01.657616 CH1_RK1: MR19=0x606, MR18=0x3434, DQSOSC=396, MR23=63, INC=94, DEC=62
1883 23:22:01.658329 [RxdqsGatingPostProcess] freq 800
1884 23:22:01.664342 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1885 23:22:01.668073 Pre-setting of DQS Precalculation
1886 23:22:01.670588 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1887 23:22:01.681375 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1888 23:22:01.688175 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1889 23:22:01.688782
1890 23:22:01.689182
1891 23:22:01.691211 [Calibration Summary] 1600 Mbps
1892 23:22:01.691673 CH 0, Rank 0
1893 23:22:01.694755 SW Impedance : PASS
1894 23:22:01.695314 DUTY Scan : NO K
1895 23:22:01.697937 ZQ Calibration : PASS
1896 23:22:01.701580 Jitter Meter : NO K
1897 23:22:01.702138 CBT Training : PASS
1898 23:22:01.705244 Write leveling : PASS
1899 23:22:01.707570 RX DQS gating : PASS
1900 23:22:01.708036 RX DQ/DQS(RDDQC) : PASS
1901 23:22:01.711050 TX DQ/DQS : PASS
1902 23:22:01.713888 RX DATLAT : PASS
1903 23:22:01.714353 RX DQ/DQS(Engine): PASS
1904 23:22:01.717894 TX OE : NO K
1905 23:22:01.718357 All Pass.
1906 23:22:01.718725
1907 23:22:01.721223 CH 0, Rank 1
1908 23:22:01.721698 SW Impedance : PASS
1909 23:22:01.724285 DUTY Scan : NO K
1910 23:22:01.724912 ZQ Calibration : PASS
1911 23:22:01.727571 Jitter Meter : NO K
1912 23:22:01.731466 CBT Training : PASS
1913 23:22:01.732038 Write leveling : PASS
1914 23:22:01.734956 RX DQS gating : PASS
1915 23:22:01.737722 RX DQ/DQS(RDDQC) : PASS
1916 23:22:01.738283 TX DQ/DQS : PASS
1917 23:22:01.740986 RX DATLAT : PASS
1918 23:22:01.744282 RX DQ/DQS(Engine): PASS
1919 23:22:01.744906 TX OE : NO K
1920 23:22:01.748699 All Pass.
1921 23:22:01.749314
1922 23:22:01.749684 CH 1, Rank 0
1923 23:22:01.751083 SW Impedance : PASS
1924 23:22:01.751546 DUTY Scan : NO K
1925 23:22:01.754888 ZQ Calibration : PASS
1926 23:22:01.757688 Jitter Meter : NO K
1927 23:22:01.758149 CBT Training : PASS
1928 23:22:01.761262 Write leveling : PASS
1929 23:22:01.764623 RX DQS gating : PASS
1930 23:22:01.765280 RX DQ/DQS(RDDQC) : PASS
1931 23:22:01.767370 TX DQ/DQS : PASS
1932 23:22:01.767828 RX DATLAT : PASS
1933 23:22:01.770797 RX DQ/DQS(Engine): PASS
1934 23:22:01.774379 TX OE : NO K
1935 23:22:01.774940 All Pass.
1936 23:22:01.775309
1937 23:22:01.775651 CH 1, Rank 1
1938 23:22:01.777406 SW Impedance : PASS
1939 23:22:01.781196 DUTY Scan : NO K
1940 23:22:01.781841 ZQ Calibration : PASS
1941 23:22:01.784440 Jitter Meter : NO K
1942 23:22:01.787793 CBT Training : PASS
1943 23:22:01.788260 Write leveling : PASS
1944 23:22:01.791294 RX DQS gating : PASS
1945 23:22:01.794613 RX DQ/DQS(RDDQC) : PASS
1946 23:22:01.795181 TX DQ/DQS : PASS
1947 23:22:01.797465 RX DATLAT : PASS
1948 23:22:01.801847 RX DQ/DQS(Engine): PASS
1949 23:22:01.802411 TX OE : NO K
1950 23:22:01.803990 All Pass.
1951 23:22:01.804448
1952 23:22:01.804903 DramC Write-DBI off
1953 23:22:01.808170 PER_BANK_REFRESH: Hybrid Mode
1954 23:22:01.808785 TX_TRACKING: ON
1955 23:22:01.810541 [GetDramInforAfterCalByMRR] Vendor 6.
1956 23:22:01.814735 [GetDramInforAfterCalByMRR] Revision 606.
1957 23:22:01.821032 [GetDramInforAfterCalByMRR] Revision 2 0.
1958 23:22:01.821496 MR0 0x3939
1959 23:22:01.821864 MR8 0x1111
1960 23:22:01.824408 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1961 23:22:01.824920
1962 23:22:01.828061 MR0 0x3939
1963 23:22:01.828625 MR8 0x1111
1964 23:22:01.830996 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1965 23:22:01.831557
1966 23:22:01.841063 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1967 23:22:01.844913 [FAST_K] Save calibration result to emmc
1968 23:22:01.847418 [FAST_K] Save calibration result to emmc
1969 23:22:01.851155 dram_init: config_dvfs: 1
1970 23:22:01.853859 dramc_set_vcore_voltage set vcore to 662500
1971 23:22:01.857394 Read voltage for 1200, 2
1972 23:22:01.857852 Vio18 = 0
1973 23:22:01.858220 Vcore = 662500
1974 23:22:01.860674 Vdram = 0
1975 23:22:01.861209 Vddq = 0
1976 23:22:01.861578 Vmddr = 0
1977 23:22:01.867773 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1978 23:22:01.870879 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1979 23:22:01.874165 MEM_TYPE=3, freq_sel=15
1980 23:22:01.878480 sv_algorithm_assistance_LP4_1600
1981 23:22:01.881213 ============ PULL DRAM RESETB DOWN ============
1982 23:22:01.884774 ========== PULL DRAM RESETB DOWN end =========
1983 23:22:01.890951 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1984 23:22:01.893966 ===================================
1985 23:22:01.894774 LPDDR4 DRAM CONFIGURATION
1986 23:22:01.897256 ===================================
1987 23:22:01.900667 EX_ROW_EN[0] = 0x0
1988 23:22:01.901157 EX_ROW_EN[1] = 0x0
1989 23:22:01.904158 LP4Y_EN = 0x0
1990 23:22:01.907905 WORK_FSP = 0x0
1991 23:22:01.908365 WL = 0x4
1992 23:22:01.910913 RL = 0x4
1993 23:22:01.911373 BL = 0x2
1994 23:22:01.914575 RPST = 0x0
1995 23:22:01.915204 RD_PRE = 0x0
1996 23:22:01.917528 WR_PRE = 0x1
1997 23:22:01.917987 WR_PST = 0x0
1998 23:22:01.920476 DBI_WR = 0x0
1999 23:22:01.921099 DBI_RD = 0x0
2000 23:22:01.923899 OTF = 0x1
2001 23:22:01.927873 ===================================
2002 23:22:01.930476 ===================================
2003 23:22:01.930937 ANA top config
2004 23:22:01.933921 ===================================
2005 23:22:01.937769 DLL_ASYNC_EN = 0
2006 23:22:01.941176 ALL_SLAVE_EN = 0
2007 23:22:01.941637 NEW_RANK_MODE = 1
2008 23:22:01.943591 DLL_IDLE_MODE = 1
2009 23:22:01.947394 LP45_APHY_COMB_EN = 1
2010 23:22:01.950681 TX_ODT_DIS = 1
2011 23:22:01.953663 NEW_8X_MODE = 1
2012 23:22:01.957289 ===================================
2013 23:22:01.960202 ===================================
2014 23:22:01.960620 data_rate = 2400
2015 23:22:01.963806 CKR = 1
2016 23:22:01.967182 DQ_P2S_RATIO = 8
2017 23:22:01.970748 ===================================
2018 23:22:01.974816 CA_P2S_RATIO = 8
2019 23:22:01.976831 DQ_CA_OPEN = 0
2020 23:22:01.980904 DQ_SEMI_OPEN = 0
2021 23:22:01.981471 CA_SEMI_OPEN = 0
2022 23:22:01.983958 CA_FULL_RATE = 0
2023 23:22:01.986849 DQ_CKDIV4_EN = 0
2024 23:22:01.990414 CA_CKDIV4_EN = 0
2025 23:22:01.993542 CA_PREDIV_EN = 0
2026 23:22:01.996827 PH8_DLY = 17
2027 23:22:01.997293 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2028 23:22:02.000260 DQ_AAMCK_DIV = 4
2029 23:22:02.003264 CA_AAMCK_DIV = 4
2030 23:22:02.006804 CA_ADMCK_DIV = 4
2031 23:22:02.009841 DQ_TRACK_CA_EN = 0
2032 23:22:02.013283 CA_PICK = 1200
2033 23:22:02.016892 CA_MCKIO = 1200
2034 23:22:02.017218 MCKIO_SEMI = 0
2035 23:22:02.019730 PLL_FREQ = 2366
2036 23:22:02.023310 DQ_UI_PI_RATIO = 32
2037 23:22:02.026211 CA_UI_PI_RATIO = 0
2038 23:22:02.029353 ===================================
2039 23:22:02.033424 ===================================
2040 23:22:02.036181 memory_type:LPDDR4
2041 23:22:02.036316 GP_NUM : 10
2042 23:22:02.040346 SRAM_EN : 1
2043 23:22:02.042703 MD32_EN : 0
2044 23:22:02.046955 ===================================
2045 23:22:02.047059 [ANA_INIT] >>>>>>>>>>>>>>
2046 23:22:02.049547 <<<<<< [CONFIGURE PHASE]: ANA_TX
2047 23:22:02.052661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2048 23:22:02.056328 ===================================
2049 23:22:02.059649 data_rate = 2400,PCW = 0X5b00
2050 23:22:02.063311 ===================================
2051 23:22:02.066373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2052 23:22:02.072685 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2053 23:22:02.076374 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2054 23:22:02.084055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2055 23:22:02.086021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2056 23:22:02.089821 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2057 23:22:02.089902 [ANA_INIT] flow start
2058 23:22:02.092931 [ANA_INIT] PLL >>>>>>>>
2059 23:22:02.096323 [ANA_INIT] PLL <<<<<<<<
2060 23:22:02.096478 [ANA_INIT] MIDPI >>>>>>>>
2061 23:22:02.099893 [ANA_INIT] MIDPI <<<<<<<<
2062 23:22:02.103159 [ANA_INIT] DLL >>>>>>>>
2063 23:22:02.106881 [ANA_INIT] DLL <<<<<<<<
2064 23:22:02.107015 [ANA_INIT] flow end
2065 23:22:02.110458 ============ LP4 DIFF to SE enter ============
2066 23:22:02.116659 ============ LP4 DIFF to SE exit ============
2067 23:22:02.117178 [ANA_INIT] <<<<<<<<<<<<<
2068 23:22:02.119851 [Flow] Enable top DCM control >>>>>
2069 23:22:02.123660 [Flow] Enable top DCM control <<<<<
2070 23:22:02.126687 Enable DLL master slave shuffle
2071 23:22:02.134280 ==============================================================
2072 23:22:02.134845 Gating Mode config
2073 23:22:02.140139 ==============================================================
2074 23:22:02.144435 Config description:
2075 23:22:02.150514 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2076 23:22:02.157626 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2077 23:22:02.163779 SELPH_MODE 0: By rank 1: By Phase
2078 23:22:02.170470 ==============================================================
2079 23:22:02.171028 GAT_TRACK_EN = 1
2080 23:22:02.173219 RX_GATING_MODE = 2
2081 23:22:02.176900 RX_GATING_TRACK_MODE = 2
2082 23:22:02.180362 SELPH_MODE = 1
2083 23:22:02.183512 PICG_EARLY_EN = 1
2084 23:22:02.186857 VALID_LAT_VALUE = 1
2085 23:22:02.193508 ==============================================================
2086 23:22:02.196645 Enter into Gating configuration >>>>
2087 23:22:02.200127 Exit from Gating configuration <<<<
2088 23:22:02.203918 Enter into DVFS_PRE_config >>>>>
2089 23:22:02.213188 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2090 23:22:02.216610 Exit from DVFS_PRE_config <<<<<
2091 23:22:02.219730 Enter into PICG configuration >>>>
2092 23:22:02.223116 Exit from PICG configuration <<<<
2093 23:22:02.226623 [RX_INPUT] configuration >>>>>
2094 23:22:02.227084 [RX_INPUT] configuration <<<<<
2095 23:22:02.232941 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2096 23:22:02.240034 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2097 23:22:02.242901 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2098 23:22:02.249438 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2099 23:22:02.256643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2100 23:22:02.263029 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2101 23:22:02.265963 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2102 23:22:02.269824 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2103 23:22:02.276371 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2104 23:22:02.279511 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2105 23:22:02.283607 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2106 23:22:02.289441 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2107 23:22:02.292520 ===================================
2108 23:22:02.292970 LPDDR4 DRAM CONFIGURATION
2109 23:22:02.296107 ===================================
2110 23:22:02.299429 EX_ROW_EN[0] = 0x0
2111 23:22:02.299842 EX_ROW_EN[1] = 0x0
2112 23:22:02.302404 LP4Y_EN = 0x0
2113 23:22:02.302833 WORK_FSP = 0x0
2114 23:22:02.306197 WL = 0x4
2115 23:22:02.306662 RL = 0x4
2116 23:22:02.309678 BL = 0x2
2117 23:22:02.313009 RPST = 0x0
2118 23:22:02.313424 RD_PRE = 0x0
2119 23:22:02.316751 WR_PRE = 0x1
2120 23:22:02.317193 WR_PST = 0x0
2121 23:22:02.319508 DBI_WR = 0x0
2122 23:22:02.319920 DBI_RD = 0x0
2123 23:22:02.323163 OTF = 0x1
2124 23:22:02.326137 ===================================
2125 23:22:02.329336 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2126 23:22:02.332902 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2127 23:22:02.336282 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2128 23:22:02.339485 ===================================
2129 23:22:02.342578 LPDDR4 DRAM CONFIGURATION
2130 23:22:02.346181 ===================================
2131 23:22:02.349370 EX_ROW_EN[0] = 0x10
2132 23:22:02.349784 EX_ROW_EN[1] = 0x0
2133 23:22:02.352689 LP4Y_EN = 0x0
2134 23:22:02.353152 WORK_FSP = 0x0
2135 23:22:02.355880 WL = 0x4
2136 23:22:02.356295 RL = 0x4
2137 23:22:02.359047 BL = 0x2
2138 23:22:02.359460 RPST = 0x0
2139 23:22:02.362377 RD_PRE = 0x0
2140 23:22:02.362823 WR_PRE = 0x1
2141 23:22:02.365992 WR_PST = 0x0
2142 23:22:02.366405 DBI_WR = 0x0
2143 23:22:02.369568 DBI_RD = 0x0
2144 23:22:02.369984 OTF = 0x1
2145 23:22:02.372822 ===================================
2146 23:22:02.379781 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2147 23:22:02.380200 ==
2148 23:22:02.382631 Dram Type= 6, Freq= 0, CH_0, rank 0
2149 23:22:02.389526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2150 23:22:02.389947 ==
2151 23:22:02.390280 [Duty_Offset_Calibration]
2152 23:22:02.392741 B0:0 B1:2 CA:1
2153 23:22:02.393168
2154 23:22:02.396257 [DutyScan_Calibration_Flow] k_type=0
2155 23:22:02.404697
2156 23:22:02.405162 ==CLK 0==
2157 23:22:02.408355 Final CLK duty delay cell = 0
2158 23:22:02.411653 [0] MAX Duty = 5093%(X100), DQS PI = 12
2159 23:22:02.414976 [0] MIN Duty = 4938%(X100), DQS PI = 52
2160 23:22:02.415574 [0] AVG Duty = 5015%(X100)
2161 23:22:02.418439
2162 23:22:02.418855 CH0 CLK Duty spec in!! Max-Min= 155%
2163 23:22:02.424842 [DutyScan_Calibration_Flow] ====Done====
2164 23:22:02.425281
2165 23:22:02.428015 [DutyScan_Calibration_Flow] k_type=1
2166 23:22:02.444178
2167 23:22:02.444593 ==DQS 0 ==
2168 23:22:02.447732 Final DQS duty delay cell = 0
2169 23:22:02.450816 [0] MAX Duty = 5125%(X100), DQS PI = 30
2170 23:22:02.454146 [0] MIN Duty = 5031%(X100), DQS PI = 4
2171 23:22:02.457617 [0] AVG Duty = 5078%(X100)
2172 23:22:02.458041
2173 23:22:02.458381 ==DQS 1 ==
2174 23:22:02.461042 Final DQS duty delay cell = 0
2175 23:22:02.464687 [0] MAX Duty = 5062%(X100), DQS PI = 56
2176 23:22:02.467418 [0] MIN Duty = 4906%(X100), DQS PI = 14
2177 23:22:02.467840 [0] AVG Duty = 4984%(X100)
2178 23:22:02.470875
2179 23:22:02.473900 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2180 23:22:02.474319
2181 23:22:02.477232 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2182 23:22:02.481659 [DutyScan_Calibration_Flow] ====Done====
2183 23:22:02.482079
2184 23:22:02.484168 [DutyScan_Calibration_Flow] k_type=3
2185 23:22:02.501378
2186 23:22:02.501793 ==DQM 0 ==
2187 23:22:02.504634 Final DQM duty delay cell = 0
2188 23:22:02.508091 [0] MAX Duty = 5156%(X100), DQS PI = 22
2189 23:22:02.511238 [0] MIN Duty = 4969%(X100), DQS PI = 40
2190 23:22:02.514419 [0] AVG Duty = 5062%(X100)
2191 23:22:02.514852
2192 23:22:02.515339 ==DQM 1 ==
2193 23:22:02.518130 Final DQM duty delay cell = 4
2194 23:22:02.521438 [4] MAX Duty = 5187%(X100), DQS PI = 52
2195 23:22:02.525241 [4] MIN Duty = 5000%(X100), DQS PI = 16
2196 23:22:02.528370 [4] AVG Duty = 5093%(X100)
2197 23:22:02.528831
2198 23:22:02.531180 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2199 23:22:02.531598
2200 23:22:02.535134 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2201 23:22:02.538256 [DutyScan_Calibration_Flow] ====Done====
2202 23:22:02.538670
2203 23:22:02.541633 [DutyScan_Calibration_Flow] k_type=2
2204 23:22:02.556990
2205 23:22:02.557406 ==DQ 0 ==
2206 23:22:02.560137 Final DQ duty delay cell = -4
2207 23:22:02.563694 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2208 23:22:02.566663 [-4] MIN Duty = 4782%(X100), DQS PI = 54
2209 23:22:02.569966 [-4] AVG Duty = 4922%(X100)
2210 23:22:02.570382
2211 23:22:02.570713 ==DQ 1 ==
2212 23:22:02.573671 Final DQ duty delay cell = -4
2213 23:22:02.576500 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2214 23:22:02.579987 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2215 23:22:02.583245 [-4] AVG Duty = 4969%(X100)
2216 23:22:02.583697
2217 23:22:02.586175 CH0 DQ 0 Duty spec in!! Max-Min= 280%
2218 23:22:02.586596
2219 23:22:02.590165 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2220 23:22:02.593496 [DutyScan_Calibration_Flow] ====Done====
2221 23:22:02.593997 ==
2222 23:22:02.596617 Dram Type= 6, Freq= 0, CH_1, rank 0
2223 23:22:02.599422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2224 23:22:02.599840 ==
2225 23:22:02.603462 [Duty_Offset_Calibration]
2226 23:22:02.603879 B0:0 B1:4 CA:-5
2227 23:22:02.604211
2228 23:22:02.606094 [DutyScan_Calibration_Flow] k_type=0
2229 23:22:02.617660
2230 23:22:02.618078 ==CLK 0==
2231 23:22:02.620660 Final CLK duty delay cell = 0
2232 23:22:02.623568 [0] MAX Duty = 5093%(X100), DQS PI = 42
2233 23:22:02.627280 [0] MIN Duty = 4875%(X100), DQS PI = 14
2234 23:22:02.627701 [0] AVG Duty = 4984%(X100)
2235 23:22:02.630993
2236 23:22:02.631405 CH1 CLK Duty spec in!! Max-Min= 218%
2237 23:22:02.636826 [DutyScan_Calibration_Flow] ====Done====
2238 23:22:02.637246
2239 23:22:02.640055 [DutyScan_Calibration_Flow] k_type=1
2240 23:22:02.655271
2241 23:22:02.655685 ==DQS 0 ==
2242 23:22:02.658839 Final DQS duty delay cell = 0
2243 23:22:02.661943 [0] MAX Duty = 5125%(X100), DQS PI = 50
2244 23:22:02.665277 [0] MIN Duty = 4875%(X100), DQS PI = 8
2245 23:22:02.665695 [0] AVG Duty = 5000%(X100)
2246 23:22:02.668893
2247 23:22:02.669313 ==DQS 1 ==
2248 23:22:02.671917 Final DQS duty delay cell = -4
2249 23:22:02.676151 [-4] MAX Duty = 5031%(X100), DQS PI = 36
2250 23:22:02.678363 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2251 23:22:02.682314 [-4] AVG Duty = 4969%(X100)
2252 23:22:02.682730
2253 23:22:02.685165 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2254 23:22:02.685581
2255 23:22:02.688898 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2256 23:22:02.692496 [DutyScan_Calibration_Flow] ====Done====
2257 23:22:02.692953
2258 23:22:02.695328 [DutyScan_Calibration_Flow] k_type=3
2259 23:22:02.710588
2260 23:22:02.711002 ==DQM 0 ==
2261 23:22:02.714735 Final DQM duty delay cell = -4
2262 23:22:02.717052 [-4] MAX Duty = 5062%(X100), DQS PI = 0
2263 23:22:02.720645 [-4] MIN Duty = 4875%(X100), DQS PI = 6
2264 23:22:02.723871 [-4] AVG Duty = 4968%(X100)
2265 23:22:02.724290
2266 23:22:02.724624 ==DQM 1 ==
2267 23:22:02.727086 Final DQM duty delay cell = -4
2268 23:22:02.731164 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2269 23:22:02.733589 [-4] MIN Duty = 4875%(X100), DQS PI = 28
2270 23:22:02.737734 [-4] AVG Duty = 4968%(X100)
2271 23:22:02.738253
2272 23:22:02.740303 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2273 23:22:02.740770
2274 23:22:02.743650 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2275 23:22:02.747028 [DutyScan_Calibration_Flow] ====Done====
2276 23:22:02.747451
2277 23:22:02.750707 [DutyScan_Calibration_Flow] k_type=2
2278 23:22:02.767703
2279 23:22:02.768166 ==DQ 0 ==
2280 23:22:02.770862 Final DQ duty delay cell = 0
2281 23:22:02.774211 [0] MAX Duty = 5093%(X100), DQS PI = 32
2282 23:22:02.777260 [0] MIN Duty = 4969%(X100), DQS PI = 10
2283 23:22:02.777685 [0] AVG Duty = 5031%(X100)
2284 23:22:02.780997
2285 23:22:02.781415 ==DQ 1 ==
2286 23:22:02.784211 Final DQ duty delay cell = 0
2287 23:22:02.787868 [0] MAX Duty = 5031%(X100), DQS PI = 40
2288 23:22:02.790844 [0] MIN Duty = 4907%(X100), DQS PI = 0
2289 23:22:02.791268 [0] AVG Duty = 4969%(X100)
2290 23:22:02.791603
2291 23:22:02.794149 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2292 23:22:02.797905
2293 23:22:02.801053 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2294 23:22:02.804482 [DutyScan_Calibration_Flow] ====Done====
2295 23:22:02.808072 nWR fixed to 30
2296 23:22:02.808488 [ModeRegInit_LP4] CH0 RK0
2297 23:22:02.811093 [ModeRegInit_LP4] CH0 RK1
2298 23:22:02.814130 [ModeRegInit_LP4] CH1 RK0
2299 23:22:02.814544 [ModeRegInit_LP4] CH1 RK1
2300 23:22:02.817792 match AC timing 6
2301 23:22:02.821138 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2302 23:22:02.823948 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2303 23:22:02.830829 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2304 23:22:02.833939 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2305 23:22:02.840590 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2306 23:22:02.840734 ==
2307 23:22:02.844251 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 23:22:02.847085 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2309 23:22:02.847215 ==
2310 23:22:02.854020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2311 23:22:02.860239 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2312 23:22:02.866927 [CA 0] Center 39 (9~70) winsize 62
2313 23:22:02.871130 [CA 1] Center 39 (8~70) winsize 63
2314 23:22:02.874197 [CA 2] Center 36 (5~67) winsize 63
2315 23:22:02.877032 [CA 3] Center 35 (4~66) winsize 63
2316 23:22:02.880502 [CA 4] Center 34 (3~65) winsize 63
2317 23:22:02.883794 [CA 5] Center 33 (3~64) winsize 62
2318 23:22:02.884057
2319 23:22:02.887511 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2320 23:22:02.887781
2321 23:22:02.890613 [CATrainingPosCal] consider 1 rank data
2322 23:22:02.894082 u2DelayCellTimex100 = 270/100 ps
2323 23:22:02.897770 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2324 23:22:02.901048 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2325 23:22:02.907136 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2326 23:22:02.910570 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2327 23:22:02.914190 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2328 23:22:02.917144 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2329 23:22:02.917570
2330 23:22:02.920612 CA PerBit enable=1, Macro0, CA PI delay=33
2331 23:22:02.921091
2332 23:22:02.924288 [CBTSetCACLKResult] CA Dly = 33
2333 23:22:02.924737 CS Dly: 7 (0~38)
2334 23:22:02.925085 ==
2335 23:22:02.927457 Dram Type= 6, Freq= 0, CH_0, rank 1
2336 23:22:02.934029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2337 23:22:02.934445 ==
2338 23:22:02.937338 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2339 23:22:02.943763 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2340 23:22:02.953291 [CA 0] Center 39 (8~70) winsize 63
2341 23:22:02.956696 [CA 1] Center 39 (8~70) winsize 63
2342 23:22:02.959844 [CA 2] Center 36 (5~67) winsize 63
2343 23:22:02.962962 [CA 3] Center 35 (4~66) winsize 63
2344 23:22:02.966481 [CA 4] Center 33 (3~64) winsize 62
2345 23:22:02.969485 [CA 5] Center 34 (3~65) winsize 63
2346 23:22:02.969898
2347 23:22:02.973067 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2348 23:22:02.973480
2349 23:22:02.976344 [CATrainingPosCal] consider 2 rank data
2350 23:22:02.979028 u2DelayCellTimex100 = 270/100 ps
2351 23:22:02.982676 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2352 23:22:02.986225 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2353 23:22:02.992519 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2354 23:22:02.995892 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2355 23:22:02.999228 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2356 23:22:03.002458 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2357 23:22:03.002539
2358 23:22:03.005866 CA PerBit enable=1, Macro0, CA PI delay=33
2359 23:22:03.005954
2360 23:22:03.009163 [CBTSetCACLKResult] CA Dly = 33
2361 23:22:03.009273 CS Dly: 7 (0~39)
2362 23:22:03.009340
2363 23:22:03.012987 ----->DramcWriteLeveling(PI) begin...
2364 23:22:03.015635 ==
2365 23:22:03.015716 Dram Type= 6, Freq= 0, CH_0, rank 0
2366 23:22:03.022449 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2367 23:22:03.022534 ==
2368 23:22:03.026106 Write leveling (Byte 0): 26 => 26
2369 23:22:03.029514 Write leveling (Byte 1): 25 => 25
2370 23:22:03.029597 DramcWriteLeveling(PI) end<-----
2371 23:22:03.032982
2372 23:22:03.033063 ==
2373 23:22:03.036022 Dram Type= 6, Freq= 0, CH_0, rank 0
2374 23:22:03.039496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2375 23:22:03.039578 ==
2376 23:22:03.043462 [Gating] SW mode calibration
2377 23:22:03.048910 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2378 23:22:03.052964 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2379 23:22:03.058824 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2380 23:22:03.063037 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2381 23:22:03.065888 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2382 23:22:03.072499 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2383 23:22:03.075667 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2384 23:22:03.079210 0 11 20 | B1->B0 | 2e2e 2a2a | 0 0 | (1 0) (0 1)
2385 23:22:03.085490 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2386 23:22:03.089359 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2387 23:22:03.092689 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2388 23:22:03.099961 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2389 23:22:03.102704 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2390 23:22:03.105665 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2391 23:22:03.112354 0 12 16 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
2392 23:22:03.115600 0 12 20 | B1->B0 | 3333 3939 | 0 1 | (0 0) (0 0)
2393 23:22:03.118726 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 23:22:03.125675 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2395 23:22:03.128855 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2396 23:22:03.133615 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2397 23:22:03.138942 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2398 23:22:03.142374 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2399 23:22:03.145248 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2400 23:22:03.153509 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2401 23:22:03.155927 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2402 23:22:03.158550 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 23:22:03.165655 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 23:22:03.168676 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 23:22:03.172418 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 23:22:03.175540 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 23:22:03.182160 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 23:22:03.185848 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 23:22:03.189693 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 23:22:03.195251 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 23:22:03.199014 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 23:22:03.202230 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 23:22:03.208950 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 23:22:03.212213 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 23:22:03.215288 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2416 23:22:03.222814 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2417 23:22:03.225663 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2418 23:22:03.229128 Total UI for P1: 0, mck2ui 16
2419 23:22:03.232211 best dqsien dly found for B0: ( 0, 15, 18)
2420 23:22:03.234993 Total UI for P1: 0, mck2ui 16
2421 23:22:03.238594 best dqsien dly found for B1: ( 0, 15, 18)
2422 23:22:03.241697 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2423 23:22:03.245086 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2424 23:22:03.245167
2425 23:22:03.248563 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2426 23:22:03.253509 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2427 23:22:03.255189 [Gating] SW calibration Done
2428 23:22:03.255296 ==
2429 23:22:03.259109 Dram Type= 6, Freq= 0, CH_0, rank 0
2430 23:22:03.264820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2431 23:22:03.264903 ==
2432 23:22:03.264968 RX Vref Scan: 0
2433 23:22:03.265030
2434 23:22:03.268541 RX Vref 0 -> 0, step: 1
2435 23:22:03.268648
2436 23:22:03.271992 RX Delay -40 -> 252, step: 8
2437 23:22:03.275178 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2438 23:22:03.278669 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2439 23:22:03.281937 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2440 23:22:03.286209 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2441 23:22:03.291987 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2442 23:22:03.295187 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2443 23:22:03.299496 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2444 23:22:03.302984 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2445 23:22:03.305539 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2446 23:22:03.308201 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2447 23:22:03.315497 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2448 23:22:03.318651 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2449 23:22:03.322786 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2450 23:22:03.326324 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2451 23:22:03.332600 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2452 23:22:03.335635 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2453 23:22:03.335717 ==
2454 23:22:03.338654 Dram Type= 6, Freq= 0, CH_0, rank 0
2455 23:22:03.342348 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2456 23:22:03.342430 ==
2457 23:22:03.342495 DQS Delay:
2458 23:22:03.345413 DQS0 = 0, DQS1 = 0
2459 23:22:03.345495 DQM Delay:
2460 23:22:03.348640 DQM0 = 115, DQM1 = 106
2461 23:22:03.348782 DQ Delay:
2462 23:22:03.351993 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2463 23:22:03.355584 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2464 23:22:03.358272 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2465 23:22:03.362924 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2466 23:22:03.363006
2467 23:22:03.366461
2468 23:22:03.366542 ==
2469 23:22:03.368677 Dram Type= 6, Freq= 0, CH_0, rank 0
2470 23:22:03.372030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2471 23:22:03.372112 ==
2472 23:22:03.372177
2473 23:22:03.372237
2474 23:22:03.375221 TX Vref Scan disable
2475 23:22:03.375303 == TX Byte 0 ==
2476 23:22:03.381577 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2477 23:22:03.385372 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2478 23:22:03.385454 == TX Byte 1 ==
2479 23:22:03.391854 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2480 23:22:03.395005 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2481 23:22:03.395085 ==
2482 23:22:03.398813 Dram Type= 6, Freq= 0, CH_0, rank 0
2483 23:22:03.401885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2484 23:22:03.401962 ==
2485 23:22:03.413624 TX Vref=22, minBit 8, minWin=24, winSum=407
2486 23:22:03.417725 TX Vref=24, minBit 8, minWin=24, winSum=415
2487 23:22:03.420958 TX Vref=26, minBit 15, minWin=25, winSum=427
2488 23:22:03.423948 TX Vref=28, minBit 9, minWin=25, winSum=428
2489 23:22:03.426895 TX Vref=30, minBit 5, minWin=26, winSum=428
2490 23:22:03.434120 TX Vref=32, minBit 5, minWin=26, winSum=429
2491 23:22:03.437114 [TxChooseVref] Worse bit 5, Min win 26, Win sum 429, Final Vref 32
2492 23:22:03.437192
2493 23:22:03.440282 Final TX Range 1 Vref 32
2494 23:22:03.440358
2495 23:22:03.440438 ==
2496 23:22:03.443714 Dram Type= 6, Freq= 0, CH_0, rank 0
2497 23:22:03.447088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2498 23:22:03.447167 ==
2499 23:22:03.450887
2500 23:22:03.451062
2501 23:22:03.451171 TX Vref Scan disable
2502 23:22:03.454232 == TX Byte 0 ==
2503 23:22:03.457918 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2504 23:22:03.460908 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2505 23:22:03.464635 == TX Byte 1 ==
2506 23:22:03.467636 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2507 23:22:03.470780 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2508 23:22:03.470920
2509 23:22:03.474159 [DATLAT]
2510 23:22:03.474285 Freq=1200, CH0 RK0
2511 23:22:03.474413
2512 23:22:03.477203 DATLAT Default: 0xd
2513 23:22:03.477412 0, 0xFFFF, sum = 0
2514 23:22:03.480834 1, 0xFFFF, sum = 0
2515 23:22:03.480990 2, 0xFFFF, sum = 0
2516 23:22:03.484223 3, 0xFFFF, sum = 0
2517 23:22:03.484382 4, 0xFFFF, sum = 0
2518 23:22:03.487183 5, 0xFFFF, sum = 0
2519 23:22:03.487450 6, 0xFFFF, sum = 0
2520 23:22:03.490529 7, 0xFFFF, sum = 0
2521 23:22:03.494181 8, 0xFFFF, sum = 0
2522 23:22:03.494391 9, 0xFFFF, sum = 0
2523 23:22:03.497251 10, 0xFFFF, sum = 0
2524 23:22:03.497524 11, 0x0, sum = 1
2525 23:22:03.500494 12, 0x0, sum = 2
2526 23:22:03.500804 13, 0x0, sum = 3
2527 23:22:03.501150 14, 0x0, sum = 4
2528 23:22:03.504225 best_step = 12
2529 23:22:03.504530
2530 23:22:03.504894 ==
2531 23:22:03.507419 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 23:22:03.511587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2533 23:22:03.512111 ==
2534 23:22:03.514057 RX Vref Scan: 1
2535 23:22:03.514627
2536 23:22:03.517554 Set Vref Range= 32 -> 127
2537 23:22:03.518003
2538 23:22:03.518743 RX Vref 32 -> 127, step: 1
2539 23:22:03.519291
2540 23:22:03.520838 RX Delay -21 -> 252, step: 4
2541 23:22:03.521382
2542 23:22:03.524058 Set Vref, RX VrefLevel [Byte0]: 32
2543 23:22:03.527953 [Byte1]: 32
2544 23:22:03.531112
2545 23:22:03.531550 Set Vref, RX VrefLevel [Byte0]: 33
2546 23:22:03.534431 [Byte1]: 33
2547 23:22:03.539903
2548 23:22:03.540508 Set Vref, RX VrefLevel [Byte0]: 34
2549 23:22:03.541961 [Byte1]: 34
2550 23:22:03.546710
2551 23:22:03.547246 Set Vref, RX VrefLevel [Byte0]: 35
2552 23:22:03.550513 [Byte1]: 35
2553 23:22:03.554980
2554 23:22:03.555533 Set Vref, RX VrefLevel [Byte0]: 36
2555 23:22:03.557893 [Byte1]: 36
2556 23:22:03.562833
2557 23:22:03.563317 Set Vref, RX VrefLevel [Byte0]: 37
2558 23:22:03.565540 [Byte1]: 37
2559 23:22:03.570193
2560 23:22:03.570599 Set Vref, RX VrefLevel [Byte0]: 38
2561 23:22:03.574006 [Byte1]: 38
2562 23:22:03.578274
2563 23:22:03.578796 Set Vref, RX VrefLevel [Byte0]: 39
2564 23:22:03.585485 [Byte1]: 39
2565 23:22:03.585951
2566 23:22:03.588475 Set Vref, RX VrefLevel [Byte0]: 40
2567 23:22:03.591794 [Byte1]: 40
2568 23:22:03.592285
2569 23:22:03.595145 Set Vref, RX VrefLevel [Byte0]: 41
2570 23:22:03.598063 [Byte1]: 41
2571 23:22:03.602463
2572 23:22:03.602978 Set Vref, RX VrefLevel [Byte0]: 42
2573 23:22:03.605689 [Byte1]: 42
2574 23:22:03.610456
2575 23:22:03.610877 Set Vref, RX VrefLevel [Byte0]: 43
2576 23:22:03.613742 [Byte1]: 43
2577 23:22:03.617841
2578 23:22:03.618261 Set Vref, RX VrefLevel [Byte0]: 44
2579 23:22:03.621120 [Byte1]: 44
2580 23:22:03.625899
2581 23:22:03.626319 Set Vref, RX VrefLevel [Byte0]: 45
2582 23:22:03.629120 [Byte1]: 45
2583 23:22:03.634134
2584 23:22:03.634558 Set Vref, RX VrefLevel [Byte0]: 46
2585 23:22:03.637547 [Byte1]: 46
2586 23:22:03.642269
2587 23:22:03.642731 Set Vref, RX VrefLevel [Byte0]: 47
2588 23:22:03.645132 [Byte1]: 47
2589 23:22:03.649380
2590 23:22:03.649845 Set Vref, RX VrefLevel [Byte0]: 48
2591 23:22:03.653119 [Byte1]: 48
2592 23:22:03.657237
2593 23:22:03.657674 Set Vref, RX VrefLevel [Byte0]: 49
2594 23:22:03.661165 [Byte1]: 49
2595 23:22:03.665628
2596 23:22:03.666046 Set Vref, RX VrefLevel [Byte0]: 50
2597 23:22:03.668890 [Byte1]: 50
2598 23:22:03.673914
2599 23:22:03.674424 Set Vref, RX VrefLevel [Byte0]: 51
2600 23:22:03.676938 [Byte1]: 51
2601 23:22:03.681646
2602 23:22:03.684534 Set Vref, RX VrefLevel [Byte0]: 52
2603 23:22:03.687529 [Byte1]: 52
2604 23:22:03.687996
2605 23:22:03.690971 Set Vref, RX VrefLevel [Byte0]: 53
2606 23:22:03.694537 [Byte1]: 53
2607 23:22:03.695002
2608 23:22:03.697725 Set Vref, RX VrefLevel [Byte0]: 54
2609 23:22:03.701318 [Byte1]: 54
2610 23:22:03.705381
2611 23:22:03.705884 Set Vref, RX VrefLevel [Byte0]: 55
2612 23:22:03.708903 [Byte1]: 55
2613 23:22:03.713461
2614 23:22:03.713921 Set Vref, RX VrefLevel [Byte0]: 56
2615 23:22:03.716578 [Byte1]: 56
2616 23:22:03.720830
2617 23:22:03.721301 Set Vref, RX VrefLevel [Byte0]: 57
2618 23:22:03.724300 [Byte1]: 57
2619 23:22:03.728885
2620 23:22:03.729491 Set Vref, RX VrefLevel [Byte0]: 58
2621 23:22:03.731888 [Byte1]: 58
2622 23:22:03.736888
2623 23:22:03.737394 Set Vref, RX VrefLevel [Byte0]: 59
2624 23:22:03.739788 [Byte1]: 59
2625 23:22:03.745276
2626 23:22:03.745994 Set Vref, RX VrefLevel [Byte0]: 60
2627 23:22:03.748480 [Byte1]: 60
2628 23:22:03.752895
2629 23:22:03.753418 Set Vref, RX VrefLevel [Byte0]: 61
2630 23:22:03.756323 [Byte1]: 61
2631 23:22:03.761586
2632 23:22:03.762200 Set Vref, RX VrefLevel [Byte0]: 62
2633 23:22:03.764071 [Byte1]: 62
2634 23:22:03.768565
2635 23:22:03.769110 Set Vref, RX VrefLevel [Byte0]: 63
2636 23:22:03.772426 [Byte1]: 63
2637 23:22:03.777240
2638 23:22:03.777905 Set Vref, RX VrefLevel [Byte0]: 64
2639 23:22:03.782769 [Byte1]: 64
2640 23:22:03.783477
2641 23:22:03.786241 Set Vref, RX VrefLevel [Byte0]: 65
2642 23:22:03.789430 [Byte1]: 65
2643 23:22:03.789963
2644 23:22:03.793496 Final RX Vref Byte 0 = 52 to rank0
2645 23:22:03.796490 Final RX Vref Byte 1 = 49 to rank0
2646 23:22:03.799243 Final RX Vref Byte 0 = 52 to rank1
2647 23:22:03.803215 Final RX Vref Byte 1 = 49 to rank1==
2648 23:22:03.806134 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 23:22:03.810014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2650 23:22:03.810544 ==
2651 23:22:03.812666 DQS Delay:
2652 23:22:03.813189 DQS0 = 0, DQS1 = 0
2653 23:22:03.816534 DQM Delay:
2654 23:22:03.817158 DQM0 = 114, DQM1 = 105
2655 23:22:03.819602 DQ Delay:
2656 23:22:03.822859 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2657 23:22:03.826654 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2658 23:22:03.829966 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2659 23:22:03.832839 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2660 23:22:03.833307
2661 23:22:03.833671
2662 23:22:03.839899 [DQSOSCAuto] RK0, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2663 23:22:03.843061 CH0 RK0: MR19=404, MR18=606
2664 23:22:03.849731 CH0_RK0: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
2665 23:22:03.850340
2666 23:22:03.853274 ----->DramcWriteLeveling(PI) begin...
2667 23:22:03.853908 ==
2668 23:22:03.856852 Dram Type= 6, Freq= 0, CH_0, rank 1
2669 23:22:03.859399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2670 23:22:03.859934 ==
2671 23:22:03.863148 Write leveling (Byte 0): 28 => 28
2672 23:22:03.866374 Write leveling (Byte 1): 26 => 26
2673 23:22:03.869636 DramcWriteLeveling(PI) end<-----
2674 23:22:03.870179
2675 23:22:03.870624 ==
2676 23:22:03.872627 Dram Type= 6, Freq= 0, CH_0, rank 1
2677 23:22:03.876507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2678 23:22:03.877242 ==
2679 23:22:03.879275 [Gating] SW mode calibration
2680 23:22:03.887094 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2681 23:22:03.893228 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2682 23:22:03.896485 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2683 23:22:03.903322 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2684 23:22:03.906346 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2685 23:22:03.909201 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2686 23:22:03.912471 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
2687 23:22:03.919251 0 11 20 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (1 0)
2688 23:22:03.922857 0 11 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2689 23:22:03.926112 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2690 23:22:03.932437 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2691 23:22:03.936003 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2692 23:22:03.939446 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2693 23:22:03.945849 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2694 23:22:03.948825 0 12 16 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (0 0)
2695 23:22:03.952614 0 12 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2696 23:22:03.959350 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2697 23:22:03.962082 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2698 23:22:03.965771 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2699 23:22:03.973156 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2700 23:22:03.975758 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2701 23:22:03.979300 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2702 23:22:03.985594 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2703 23:22:03.989257 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2704 23:22:03.992440 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2705 23:22:03.999574 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2706 23:22:04.002546 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2707 23:22:04.005580 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 23:22:04.012576 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 23:22:04.016270 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 23:22:04.019090 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 23:22:04.025293 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 23:22:04.029011 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 23:22:04.032093 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 23:22:04.036044 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 23:22:04.042232 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 23:22:04.046192 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 23:22:04.048726 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 23:22:04.055299 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2719 23:22:04.058750 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2720 23:22:04.062766 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2721 23:22:04.065311 Total UI for P1: 0, mck2ui 16
2722 23:22:04.068562 best dqsien dly found for B0: ( 0, 15, 18)
2723 23:22:04.071821 Total UI for P1: 0, mck2ui 16
2724 23:22:04.075187 best dqsien dly found for B1: ( 0, 15, 20)
2725 23:22:04.078811 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2726 23:22:04.081911 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2727 23:22:04.085193
2728 23:22:04.088815 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2729 23:22:04.092111 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2730 23:22:04.095708 [Gating] SW calibration Done
2731 23:22:04.096121 ==
2732 23:22:04.099322 Dram Type= 6, Freq= 0, CH_0, rank 1
2733 23:22:04.102368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2734 23:22:04.102791 ==
2735 23:22:04.103122 RX Vref Scan: 0
2736 23:22:04.103431
2737 23:22:04.105585 RX Vref 0 -> 0, step: 1
2738 23:22:04.106002
2739 23:22:04.108877 RX Delay -40 -> 252, step: 8
2740 23:22:04.112681 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2741 23:22:04.115540 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2742 23:22:04.122570 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2743 23:22:04.126386 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2744 23:22:04.129159 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2745 23:22:04.132161 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2746 23:22:04.135516 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2747 23:22:04.142603 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2748 23:22:04.145535 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2749 23:22:04.148786 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2750 23:22:04.152067 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2751 23:22:04.155731 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2752 23:22:04.159932 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2753 23:22:04.165741 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2754 23:22:04.168976 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2755 23:22:04.172326 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2756 23:22:04.172916 ==
2757 23:22:04.175828 Dram Type= 6, Freq= 0, CH_0, rank 1
2758 23:22:04.179253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2759 23:22:04.179860 ==
2760 23:22:04.181975 DQS Delay:
2761 23:22:04.182510 DQS0 = 0, DQS1 = 0
2762 23:22:04.185278 DQM Delay:
2763 23:22:04.185774 DQM0 = 115, DQM1 = 106
2764 23:22:04.189474 DQ Delay:
2765 23:22:04.192246 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2766 23:22:04.195821 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2767 23:22:04.199071 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2768 23:22:04.202737 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2769 23:22:04.203263
2770 23:22:04.203597
2771 23:22:04.203904 ==
2772 23:22:04.206006 Dram Type= 6, Freq= 0, CH_0, rank 1
2773 23:22:04.208800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2774 23:22:04.209229 ==
2775 23:22:04.209567
2776 23:22:04.209878
2777 23:22:04.212642 TX Vref Scan disable
2778 23:22:04.216012 == TX Byte 0 ==
2779 23:22:04.219287 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2780 23:22:04.222296 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2781 23:22:04.225178 == TX Byte 1 ==
2782 23:22:04.228450 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2783 23:22:04.232413 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2784 23:22:04.232875 ==
2785 23:22:04.235045 Dram Type= 6, Freq= 0, CH_0, rank 1
2786 23:22:04.238681 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2787 23:22:04.241961 ==
2788 23:22:04.252092 TX Vref=22, minBit 0, minWin=26, winSum=420
2789 23:22:04.255643 TX Vref=24, minBit 10, minWin=25, winSum=424
2790 23:22:04.259677 TX Vref=26, minBit 8, minWin=26, winSum=431
2791 23:22:04.262617 TX Vref=28, minBit 8, minWin=26, winSum=431
2792 23:22:04.265895 TX Vref=30, minBit 10, minWin=25, winSum=435
2793 23:22:04.272745 TX Vref=32, minBit 8, minWin=26, winSum=433
2794 23:22:04.275407 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 32
2795 23:22:04.275857
2796 23:22:04.278550 Final TX Range 1 Vref 32
2797 23:22:04.278970
2798 23:22:04.279301 ==
2799 23:22:04.282023 Dram Type= 6, Freq= 0, CH_0, rank 1
2800 23:22:04.285691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2801 23:22:04.286266 ==
2802 23:22:04.288597
2803 23:22:04.289088
2804 23:22:04.289424 TX Vref Scan disable
2805 23:22:04.292666 == TX Byte 0 ==
2806 23:22:04.295754 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2807 23:22:04.299211 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2808 23:22:04.302279 == TX Byte 1 ==
2809 23:22:04.305701 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2810 23:22:04.309096 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2811 23:22:04.309816
2812 23:22:04.312039 [DATLAT]
2813 23:22:04.312771 Freq=1200, CH0 RK1
2814 23:22:04.313430
2815 23:22:04.315786 DATLAT Default: 0xc
2816 23:22:04.316276 0, 0xFFFF, sum = 0
2817 23:22:04.318950 1, 0xFFFF, sum = 0
2818 23:22:04.319372 2, 0xFFFF, sum = 0
2819 23:22:04.323282 3, 0xFFFF, sum = 0
2820 23:22:04.323711 4, 0xFFFF, sum = 0
2821 23:22:04.325801 5, 0xFFFF, sum = 0
2822 23:22:04.326165 6, 0xFFFF, sum = 0
2823 23:22:04.328804 7, 0xFFFF, sum = 0
2824 23:22:04.331818 8, 0xFFFF, sum = 0
2825 23:22:04.332048 9, 0xFFFF, sum = 0
2826 23:22:04.334935 10, 0xFFFF, sum = 0
2827 23:22:04.335164 11, 0x0, sum = 1
2828 23:22:04.338562 12, 0x0, sum = 2
2829 23:22:04.338747 13, 0x0, sum = 3
2830 23:22:04.338895 14, 0x0, sum = 4
2831 23:22:04.341432 best_step = 12
2832 23:22:04.341584
2833 23:22:04.341704 ==
2834 23:22:04.345141 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 23:22:04.348974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2836 23:22:04.349106 ==
2837 23:22:04.351979 RX Vref Scan: 0
2838 23:22:04.352093
2839 23:22:04.352184 RX Vref 0 -> 0, step: 1
2840 23:22:04.355306
2841 23:22:04.355421 RX Delay -21 -> 252, step: 4
2842 23:22:04.361913 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2843 23:22:04.365791 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2844 23:22:04.368471 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2845 23:22:04.372249 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2846 23:22:04.375756 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2847 23:22:04.381859 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2848 23:22:04.385248 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2849 23:22:04.388568 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2850 23:22:04.392396 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2851 23:22:04.395087 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2852 23:22:04.401675 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2853 23:22:04.405292 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2854 23:22:04.408672 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2855 23:22:04.411991 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2856 23:22:04.415738 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2857 23:22:04.422271 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2858 23:22:04.422402 ==
2859 23:22:04.425246 Dram Type= 6, Freq= 0, CH_0, rank 1
2860 23:22:04.428521 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2861 23:22:04.428631 ==
2862 23:22:04.428776 DQS Delay:
2863 23:22:04.432174 DQS0 = 0, DQS1 = 0
2864 23:22:04.432277 DQM Delay:
2865 23:22:04.435193 DQM0 = 115, DQM1 = 105
2866 23:22:04.435275 DQ Delay:
2867 23:22:04.439391 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2868 23:22:04.441668 DQ4 =116, DQ5 =108, DQ6 =124, DQ7 =124
2869 23:22:04.446085 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2870 23:22:04.448979 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2871 23:22:04.449081
2872 23:22:04.449162
2873 23:22:04.458691 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2874 23:22:04.461479 CH0 RK1: MR19=404, MR18=E0E
2875 23:22:04.465187 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2876 23:22:04.468479 [RxdqsGatingPostProcess] freq 1200
2877 23:22:04.475081 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2878 23:22:04.478283 Pre-setting of DQS Precalculation
2879 23:22:04.481876 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2880 23:22:04.482013 ==
2881 23:22:04.485727 Dram Type= 6, Freq= 0, CH_1, rank 0
2882 23:22:04.491914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2883 23:22:04.492050 ==
2884 23:22:04.496299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2885 23:22:04.502862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2886 23:22:04.510784 [CA 0] Center 37 (7~67) winsize 61
2887 23:22:04.514170 [CA 1] Center 37 (7~67) winsize 61
2888 23:22:04.517395 [CA 2] Center 34 (3~65) winsize 63
2889 23:22:04.520314 [CA 3] Center 33 (3~64) winsize 62
2890 23:22:04.524164 [CA 4] Center 32 (1~63) winsize 63
2891 23:22:04.527485 [CA 5] Center 32 (2~63) winsize 62
2892 23:22:04.527767
2893 23:22:04.530637 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2894 23:22:04.530877
2895 23:22:04.534300 [CATrainingPosCal] consider 1 rank data
2896 23:22:04.537210 u2DelayCellTimex100 = 270/100 ps
2897 23:22:04.540699 CA0 delay=37 (7~67),Diff = 5 PI (24 cell)
2898 23:22:04.544575 CA1 delay=37 (7~67),Diff = 5 PI (24 cell)
2899 23:22:04.550757 CA2 delay=34 (3~65),Diff = 2 PI (9 cell)
2900 23:22:04.554485 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2901 23:22:04.557369 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2902 23:22:04.560829 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2903 23:22:04.561294
2904 23:22:04.564000 CA PerBit enable=1, Macro0, CA PI delay=32
2905 23:22:04.564458
2906 23:22:04.568032 [CBTSetCACLKResult] CA Dly = 32
2907 23:22:04.568446 CS Dly: 6 (0~37)
2908 23:22:04.570742 ==
2909 23:22:04.571166 Dram Type= 6, Freq= 0, CH_1, rank 1
2910 23:22:04.577542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2911 23:22:04.577975 ==
2912 23:22:04.580739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2913 23:22:04.587495 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2914 23:22:04.596618 [CA 0] Center 36 (6~67) winsize 62
2915 23:22:04.600304 [CA 1] Center 36 (6~67) winsize 62
2916 23:22:04.604770 [CA 2] Center 34 (4~64) winsize 61
2917 23:22:04.606430 [CA 3] Center 33 (3~64) winsize 62
2918 23:22:04.609142 [CA 4] Center 32 (2~63) winsize 62
2919 23:22:04.612684 [CA 5] Center 32 (1~63) winsize 63
2920 23:22:04.613213
2921 23:22:04.616440 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2922 23:22:04.616942
2923 23:22:04.619132 [CATrainingPosCal] consider 2 rank data
2924 23:22:04.622908 u2DelayCellTimex100 = 270/100 ps
2925 23:22:04.625982 CA0 delay=37 (7~67),Diff = 5 PI (24 cell)
2926 23:22:04.629208 CA1 delay=37 (7~67),Diff = 5 PI (24 cell)
2927 23:22:04.636667 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2928 23:22:04.639330 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2929 23:22:04.642849 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2930 23:22:04.646067 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2931 23:22:04.646510
2932 23:22:04.649069 CA PerBit enable=1, Macro0, CA PI delay=32
2933 23:22:04.649485
2934 23:22:04.652650 [CBTSetCACLKResult] CA Dly = 32
2935 23:22:04.653109 CS Dly: 6 (0~38)
2936 23:22:04.653439
2937 23:22:04.656110 ----->DramcWriteLeveling(PI) begin...
2938 23:22:04.659454 ==
2939 23:22:04.662489 Dram Type= 6, Freq= 0, CH_1, rank 0
2940 23:22:04.666318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2941 23:22:04.666752 ==
2942 23:22:04.669449 Write leveling (Byte 0): 19 => 19
2943 23:22:04.672663 Write leveling (Byte 1): 23 => 23
2944 23:22:04.675837 DramcWriteLeveling(PI) end<-----
2945 23:22:04.676376
2946 23:22:04.676749 ==
2947 23:22:04.679420 Dram Type= 6, Freq= 0, CH_1, rank 0
2948 23:22:04.682983 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2949 23:22:04.683400 ==
2950 23:22:04.686519 [Gating] SW mode calibration
2951 23:22:04.693037 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2952 23:22:04.695968 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2953 23:22:04.703180 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 23:22:04.707039 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 23:22:04.709769 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2956 23:22:04.716246 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2957 23:22:04.719962 0 11 16 | B1->B0 | 3333 2727 | 0 0 | (0 0) (0 0)
2958 23:22:04.722999 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2959 23:22:04.729395 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 23:22:04.733313 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 23:22:04.736119 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 23:22:04.742916 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 23:22:04.746547 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 23:22:04.749507 0 12 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2965 23:22:04.756239 0 12 16 | B1->B0 | 2c2c 4545 | 0 0 | (0 0) (0 0)
2966 23:22:04.759453 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 23:22:04.762887 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 23:22:04.769596 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 23:22:04.772648 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 23:22:04.775858 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 23:22:04.783192 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 23:22:04.786135 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2973 23:22:04.789760 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2974 23:22:04.793050 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 23:22:04.799358 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 23:22:04.802211 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 23:22:04.805696 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 23:22:04.813651 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 23:22:04.816798 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 23:22:04.820229 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 23:22:04.825661 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 23:22:04.829290 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 23:22:04.833059 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 23:22:04.839318 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 23:22:04.843099 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 23:22:04.845854 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 23:22:04.852437 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 23:22:04.856063 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2989 23:22:04.858993 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2990 23:22:04.866389 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2991 23:22:04.866941 Total UI for P1: 0, mck2ui 16
2992 23:22:04.869248 best dqsien dly found for B0: ( 0, 15, 14)
2993 23:22:04.876409 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2994 23:22:04.879699 Total UI for P1: 0, mck2ui 16
2995 23:22:04.883172 best dqsien dly found for B1: ( 0, 15, 20)
2996 23:22:04.886376 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
2997 23:22:04.889087 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2998 23:22:04.889545
2999 23:22:04.892574 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3000 23:22:04.896206 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3001 23:22:04.899516 [Gating] SW calibration Done
3002 23:22:04.900048 ==
3003 23:22:04.902973 Dram Type= 6, Freq= 0, CH_1, rank 0
3004 23:22:04.906231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3005 23:22:04.906814 ==
3006 23:22:04.910287 RX Vref Scan: 0
3007 23:22:04.910746
3008 23:22:04.912776 RX Vref 0 -> 0, step: 1
3009 23:22:04.913367
3010 23:22:04.913738 RX Delay -40 -> 252, step: 8
3011 23:22:04.919674 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3012 23:22:04.923342 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3013 23:22:04.926715 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3014 23:22:04.929465 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3015 23:22:04.932665 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3016 23:22:04.939199 iDelay=208, Bit 5, Center 123 (40 ~ 207) 168
3017 23:22:04.942552 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3018 23:22:04.945924 iDelay=208, Bit 7, Center 111 (32 ~ 191) 160
3019 23:22:04.948892 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3020 23:22:04.952800 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3021 23:22:04.959333 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3022 23:22:04.962365 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3023 23:22:04.966549 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3024 23:22:04.969317 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3025 23:22:04.972894 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3026 23:22:04.979417 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3027 23:22:04.979875 ==
3028 23:22:04.982860 Dram Type= 6, Freq= 0, CH_1, rank 0
3029 23:22:04.986195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3030 23:22:04.986765 ==
3031 23:22:04.987183 DQS Delay:
3032 23:22:04.988969 DQS0 = 0, DQS1 = 0
3033 23:22:04.989452 DQM Delay:
3034 23:22:04.992090 DQM0 = 114, DQM1 = 107
3035 23:22:04.992549 DQ Delay:
3036 23:22:04.996022 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3037 23:22:04.999371 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =111
3038 23:22:05.002487 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
3039 23:22:05.005507 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =115
3040 23:22:05.005976
3041 23:22:05.006343
3042 23:22:05.006684 ==
3043 23:22:05.009212 Dram Type= 6, Freq= 0, CH_1, rank 0
3044 23:22:05.017533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3045 23:22:05.018097 ==
3046 23:22:05.018500
3047 23:22:05.018849
3048 23:22:05.019173 TX Vref Scan disable
3049 23:22:05.021894 == TX Byte 0 ==
3050 23:22:05.023258 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3051 23:22:05.025934 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3052 23:22:05.030348 == TX Byte 1 ==
3053 23:22:05.032889 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3054 23:22:05.039698 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3055 23:22:05.040247 ==
3056 23:22:05.043028 Dram Type= 6, Freq= 0, CH_1, rank 0
3057 23:22:05.046925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3058 23:22:05.047491 ==
3059 23:22:05.057716 TX Vref=22, minBit 5, minWin=25, winSum=413
3060 23:22:05.061514 TX Vref=24, minBit 15, minWin=25, winSum=419
3061 23:22:05.064233 TX Vref=26, minBit 15, minWin=25, winSum=426
3062 23:22:05.067646 TX Vref=28, minBit 8, minWin=26, winSum=428
3063 23:22:05.071025 TX Vref=30, minBit 8, minWin=26, winSum=431
3064 23:22:05.078101 TX Vref=32, minBit 9, minWin=26, winSum=430
3065 23:22:05.080614 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 30
3066 23:22:05.081124
3067 23:22:05.084335 Final TX Range 1 Vref 30
3068 23:22:05.084934
3069 23:22:05.085308 ==
3070 23:22:05.087380 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 23:22:05.091354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3072 23:22:05.093453 ==
3073 23:22:05.093918
3074 23:22:05.094301
3075 23:22:05.094638 TX Vref Scan disable
3076 23:22:05.097458 == TX Byte 0 ==
3077 23:22:05.100657 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3078 23:22:05.104189 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3079 23:22:05.107410 == TX Byte 1 ==
3080 23:22:05.110775 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3081 23:22:05.113975 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3082 23:22:05.117521
3083 23:22:05.118096 [DATLAT]
3084 23:22:05.118481 Freq=1200, CH1 RK0
3085 23:22:05.118822
3086 23:22:05.120678 DATLAT Default: 0xd
3087 23:22:05.121192 0, 0xFFFF, sum = 0
3088 23:22:05.124056 1, 0xFFFF, sum = 0
3089 23:22:05.124536 2, 0xFFFF, sum = 0
3090 23:22:05.127207 3, 0xFFFF, sum = 0
3091 23:22:05.127909 4, 0xFFFF, sum = 0
3092 23:22:05.131325 5, 0xFFFF, sum = 0
3093 23:22:05.133966 6, 0xFFFF, sum = 0
3094 23:22:05.134432 7, 0xFFFF, sum = 0
3095 23:22:05.137926 8, 0xFFFF, sum = 0
3096 23:22:05.138545 9, 0xFFFF, sum = 0
3097 23:22:05.140837 10, 0xFFFF, sum = 0
3098 23:22:05.141306 11, 0x0, sum = 1
3099 23:22:05.144353 12, 0x0, sum = 2
3100 23:22:05.144867 13, 0x0, sum = 3
3101 23:22:05.145288 14, 0x0, sum = 4
3102 23:22:05.147055 best_step = 12
3103 23:22:05.147516
3104 23:22:05.147874 ==
3105 23:22:05.151263 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 23:22:05.153852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3107 23:22:05.154318 ==
3108 23:22:05.157478 RX Vref Scan: 1
3109 23:22:05.158082
3110 23:22:05.160476 Set Vref Range= 32 -> 127
3111 23:22:05.161057
3112 23:22:05.161427 RX Vref 32 -> 127, step: 1
3113 23:22:05.161769
3114 23:22:05.164243 RX Delay -21 -> 252, step: 4
3115 23:22:05.164854
3116 23:22:05.167778 Set Vref, RX VrefLevel [Byte0]: 32
3117 23:22:05.171045 [Byte1]: 32
3118 23:22:05.174312
3119 23:22:05.174881 Set Vref, RX VrefLevel [Byte0]: 33
3120 23:22:05.177542 [Byte1]: 33
3121 23:22:05.182200
3122 23:22:05.182805 Set Vref, RX VrefLevel [Byte0]: 34
3123 23:22:05.185783 [Byte1]: 34
3124 23:22:05.189987
3125 23:22:05.190519 Set Vref, RX VrefLevel [Byte0]: 35
3126 23:22:05.193679 [Byte1]: 35
3127 23:22:05.197817
3128 23:22:05.198374 Set Vref, RX VrefLevel [Byte0]: 36
3129 23:22:05.201480 [Byte1]: 36
3130 23:22:05.206093
3131 23:22:05.206626 Set Vref, RX VrefLevel [Byte0]: 37
3132 23:22:05.209312 [Byte1]: 37
3133 23:22:05.213896
3134 23:22:05.214448 Set Vref, RX VrefLevel [Byte0]: 38
3135 23:22:05.217041 [Byte1]: 38
3136 23:22:05.222349
3137 23:22:05.222917 Set Vref, RX VrefLevel [Byte0]: 39
3138 23:22:05.225202 [Byte1]: 39
3139 23:22:05.229544
3140 23:22:05.230006 Set Vref, RX VrefLevel [Byte0]: 40
3141 23:22:05.235967 [Byte1]: 40
3142 23:22:05.236442
3143 23:22:05.239107 Set Vref, RX VrefLevel [Byte0]: 41
3144 23:22:05.243725 [Byte1]: 41
3145 23:22:05.244320
3146 23:22:05.246629 Set Vref, RX VrefLevel [Byte0]: 42
3147 23:22:05.249527 [Byte1]: 42
3148 23:22:05.253655
3149 23:22:05.254130 Set Vref, RX VrefLevel [Byte0]: 43
3150 23:22:05.256436 [Byte1]: 43
3151 23:22:05.261546
3152 23:22:05.262018 Set Vref, RX VrefLevel [Byte0]: 44
3153 23:22:05.264458 [Byte1]: 44
3154 23:22:05.269205
3155 23:22:05.269756 Set Vref, RX VrefLevel [Byte0]: 45
3156 23:22:05.272854 [Byte1]: 45
3157 23:22:05.277437
3158 23:22:05.278006 Set Vref, RX VrefLevel [Byte0]: 46
3159 23:22:05.280561 [Byte1]: 46
3160 23:22:05.284702
3161 23:22:05.285309 Set Vref, RX VrefLevel [Byte0]: 47
3162 23:22:05.289096 [Byte1]: 47
3163 23:22:05.293227
3164 23:22:05.293804 Set Vref, RX VrefLevel [Byte0]: 48
3165 23:22:05.296657 [Byte1]: 48
3166 23:22:05.300890
3167 23:22:05.301481 Set Vref, RX VrefLevel [Byte0]: 49
3168 23:22:05.304291 [Byte1]: 49
3169 23:22:05.309032
3170 23:22:05.309600 Set Vref, RX VrefLevel [Byte0]: 50
3171 23:22:05.312261 [Byte1]: 50
3172 23:22:05.316317
3173 23:22:05.316930 Set Vref, RX VrefLevel [Byte0]: 51
3174 23:22:05.319725 [Byte1]: 51
3175 23:22:05.324613
3176 23:22:05.325190 Set Vref, RX VrefLevel [Byte0]: 52
3177 23:22:05.328210 [Byte1]: 52
3178 23:22:05.332517
3179 23:22:05.333114 Set Vref, RX VrefLevel [Byte0]: 53
3180 23:22:05.336898 [Byte1]: 53
3181 23:22:05.340221
3182 23:22:05.340678 Set Vref, RX VrefLevel [Byte0]: 54
3183 23:22:05.344222 [Byte1]: 54
3184 23:22:05.349451
3185 23:22:05.350023 Set Vref, RX VrefLevel [Byte0]: 55
3186 23:22:05.351916 [Byte1]: 55
3187 23:22:05.356963
3188 23:22:05.357438 Set Vref, RX VrefLevel [Byte0]: 56
3189 23:22:05.360198 [Byte1]: 56
3190 23:22:05.364476
3191 23:22:05.365084 Set Vref, RX VrefLevel [Byte0]: 57
3192 23:22:05.367476 [Byte1]: 57
3193 23:22:05.371949
3194 23:22:05.372407 Set Vref, RX VrefLevel [Byte0]: 58
3195 23:22:05.375795 [Byte1]: 58
3196 23:22:05.380257
3197 23:22:05.380876 Set Vref, RX VrefLevel [Byte0]: 59
3198 23:22:05.383493 [Byte1]: 59
3199 23:22:05.387721
3200 23:22:05.388299 Set Vref, RX VrefLevel [Byte0]: 60
3201 23:22:05.391899 [Byte1]: 60
3202 23:22:05.396009
3203 23:22:05.396557 Set Vref, RX VrefLevel [Byte0]: 61
3204 23:22:05.399369 [Byte1]: 61
3205 23:22:05.403769
3206 23:22:05.404225 Set Vref, RX VrefLevel [Byte0]: 62
3207 23:22:05.407457 [Byte1]: 62
3208 23:22:05.411384
3209 23:22:05.411849 Set Vref, RX VrefLevel [Byte0]: 63
3210 23:22:05.415227 [Byte1]: 63
3211 23:22:05.419708
3212 23:22:05.420167 Set Vref, RX VrefLevel [Byte0]: 64
3213 23:22:05.423149 [Byte1]: 64
3214 23:22:05.427510
3215 23:22:05.428027 Set Vref, RX VrefLevel [Byte0]: 65
3216 23:22:05.433873 [Byte1]: 65
3217 23:22:05.434525
3218 23:22:05.437300 Set Vref, RX VrefLevel [Byte0]: 66
3219 23:22:05.440552 [Byte1]: 66
3220 23:22:05.441061
3221 23:22:05.444058 Set Vref, RX VrefLevel [Byte0]: 67
3222 23:22:05.447230 [Byte1]: 67
3223 23:22:05.451405
3224 23:22:05.451945 Set Vref, RX VrefLevel [Byte0]: 68
3225 23:22:05.454504 [Byte1]: 68
3226 23:22:05.459322
3227 23:22:05.459896 Final RX Vref Byte 0 = 52 to rank0
3228 23:22:05.462217 Final RX Vref Byte 1 = 49 to rank0
3229 23:22:05.465890 Final RX Vref Byte 0 = 52 to rank1
3230 23:22:05.469913 Final RX Vref Byte 1 = 49 to rank1==
3231 23:22:05.472801 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 23:22:05.479826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3233 23:22:05.480446 ==
3234 23:22:05.481052 DQS Delay:
3235 23:22:05.481417 DQS0 = 0, DQS1 = 0
3236 23:22:05.483584 DQM Delay:
3237 23:22:05.484153 DQM0 = 114, DQM1 = 105
3238 23:22:05.485837 DQ Delay:
3239 23:22:05.489692 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =112
3240 23:22:05.492345 DQ4 =112, DQ5 =126, DQ6 =122, DQ7 =112
3241 23:22:05.495805 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3242 23:22:05.499037 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =114
3243 23:22:05.499575
3244 23:22:05.499945
3245 23:22:05.505791 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3246 23:22:05.509227 CH1 RK0: MR19=404, MR18=1717
3247 23:22:05.515400 CH1_RK0: MR19=0x404, MR18=0x1717, DQSOSC=401, MR23=63, INC=40, DEC=27
3248 23:22:05.515930
3249 23:22:05.519136 ----->DramcWriteLeveling(PI) begin...
3250 23:22:05.519708 ==
3251 23:22:05.522160 Dram Type= 6, Freq= 0, CH_1, rank 1
3252 23:22:05.525884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3253 23:22:05.529211 ==
3254 23:22:05.529671 Write leveling (Byte 0): 20 => 20
3255 23:22:05.531943 Write leveling (Byte 1): 20 => 20
3256 23:22:05.535823 DramcWriteLeveling(PI) end<-----
3257 23:22:05.536415
3258 23:22:05.536859 ==
3259 23:22:05.539291 Dram Type= 6, Freq= 0, CH_1, rank 1
3260 23:22:05.545990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3261 23:22:05.546556 ==
3262 23:22:05.547024 [Gating] SW mode calibration
3263 23:22:05.555797 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3264 23:22:05.559506 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3265 23:22:05.565367 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3266 23:22:05.568861 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3267 23:22:05.572230 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3268 23:22:05.579192 0 11 12 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
3269 23:22:05.581998 0 11 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3270 23:22:05.585622 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3271 23:22:05.588477 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3272 23:22:05.595793 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3273 23:22:05.599177 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3274 23:22:05.602077 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3275 23:22:05.608379 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3276 23:22:05.611900 0 12 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
3277 23:22:05.615330 0 12 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3278 23:22:05.622966 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3279 23:22:05.625458 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3280 23:22:05.628330 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3281 23:22:05.635000 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3282 23:22:05.638713 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3283 23:22:05.642332 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3284 23:22:05.648944 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3285 23:22:05.652025 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3286 23:22:05.655447 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 23:22:05.661655 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 23:22:05.664918 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 23:22:05.668602 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 23:22:05.674748 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 23:22:05.678064 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 23:22:05.681715 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 23:22:05.688971 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 23:22:05.691536 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 23:22:05.695422 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 23:22:05.701389 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 23:22:05.705071 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 23:22:05.708885 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 23:22:05.711518 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 23:22:05.718434 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3301 23:22:05.721685 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3302 23:22:05.725221 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3303 23:22:05.728683 Total UI for P1: 0, mck2ui 16
3304 23:22:05.731734 best dqsien dly found for B0: ( 0, 15, 14)
3305 23:22:05.735687 Total UI for P1: 0, mck2ui 16
3306 23:22:05.738674 best dqsien dly found for B1: ( 0, 15, 16)
3307 23:22:05.741444 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3308 23:22:05.745194 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3309 23:22:05.748808
3310 23:22:05.751567 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3311 23:22:05.755079 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3312 23:22:05.759081 [Gating] SW calibration Done
3313 23:22:05.759626 ==
3314 23:22:05.762247 Dram Type= 6, Freq= 0, CH_1, rank 1
3315 23:22:05.765062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3316 23:22:05.765492 ==
3317 23:22:05.765825 RX Vref Scan: 0
3318 23:22:05.766190
3319 23:22:05.768860 RX Vref 0 -> 0, step: 1
3320 23:22:05.769273
3321 23:22:05.771834 RX Delay -40 -> 252, step: 8
3322 23:22:05.774738 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3323 23:22:05.778204 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3324 23:22:05.784775 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3325 23:22:05.789556 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3326 23:22:05.791603 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3327 23:22:05.794801 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3328 23:22:05.798575 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3329 23:22:05.805358 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3330 23:22:05.808686 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3331 23:22:05.811796 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3332 23:22:05.815554 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3333 23:22:05.819415 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3334 23:22:05.821935 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3335 23:22:05.828470 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3336 23:22:05.831640 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3337 23:22:05.835020 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3338 23:22:05.835441 ==
3339 23:22:05.838172 Dram Type= 6, Freq= 0, CH_1, rank 1
3340 23:22:05.841876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3341 23:22:05.845223 ==
3342 23:22:05.845716 DQS Delay:
3343 23:22:05.846063 DQS0 = 0, DQS1 = 0
3344 23:22:05.848590 DQM Delay:
3345 23:22:05.849064 DQM0 = 116, DQM1 = 108
3346 23:22:05.853339 DQ Delay:
3347 23:22:05.855147 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3348 23:22:05.858638 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3349 23:22:05.862562 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3350 23:22:05.865725 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3351 23:22:05.866281
3352 23:22:05.866644
3353 23:22:05.866980 ==
3354 23:22:05.868295 Dram Type= 6, Freq= 0, CH_1, rank 1
3355 23:22:05.872216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3356 23:22:05.872828 ==
3357 23:22:05.873208
3358 23:22:05.873550
3359 23:22:05.875578 TX Vref Scan disable
3360 23:22:05.878546 == TX Byte 0 ==
3361 23:22:05.881859 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3362 23:22:05.885085 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3363 23:22:05.888193 == TX Byte 1 ==
3364 23:22:05.891548 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3365 23:22:05.895712 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3366 23:22:05.896133 ==
3367 23:22:05.898409 Dram Type= 6, Freq= 0, CH_1, rank 1
3368 23:22:05.902357 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3369 23:22:05.902883 ==
3370 23:22:05.915885 TX Vref=22, minBit 0, minWin=25, winSum=419
3371 23:22:05.918476 TX Vref=24, minBit 0, minWin=26, winSum=425
3372 23:22:05.921497 TX Vref=26, minBit 0, minWin=26, winSum=428
3373 23:22:05.925112 TX Vref=28, minBit 8, minWin=26, winSum=431
3374 23:22:05.928191 TX Vref=30, minBit 0, minWin=26, winSum=432
3375 23:22:05.932395 TX Vref=32, minBit 0, minWin=26, winSum=432
3376 23:22:05.938940 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 30
3377 23:22:05.939403
3378 23:22:05.942057 Final TX Range 1 Vref 30
3379 23:22:05.942520
3380 23:22:05.942886 ==
3381 23:22:05.945124 Dram Type= 6, Freq= 0, CH_1, rank 1
3382 23:22:05.948242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3383 23:22:05.948732 ==
3384 23:22:05.949104
3385 23:22:05.951573
3386 23:22:05.952132 TX Vref Scan disable
3387 23:22:05.954625 == TX Byte 0 ==
3388 23:22:05.959096 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3389 23:22:05.961511 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3390 23:22:05.965405 == TX Byte 1 ==
3391 23:22:05.968161 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3392 23:22:05.971404 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3393 23:22:05.972112
3394 23:22:05.974751 [DATLAT]
3395 23:22:05.975483 Freq=1200, CH1 RK1
3396 23:22:05.976056
3397 23:22:05.978352 DATLAT Default: 0xc
3398 23:22:05.978906 0, 0xFFFF, sum = 0
3399 23:22:05.981381 1, 0xFFFF, sum = 0
3400 23:22:05.981935 2, 0xFFFF, sum = 0
3401 23:22:05.984470 3, 0xFFFF, sum = 0
3402 23:22:05.985116 4, 0xFFFF, sum = 0
3403 23:22:05.988264 5, 0xFFFF, sum = 0
3404 23:22:05.988971 6, 0xFFFF, sum = 0
3405 23:22:05.992232 7, 0xFFFF, sum = 0
3406 23:22:05.992744 8, 0xFFFF, sum = 0
3407 23:22:05.994847 9, 0xFFFF, sum = 0
3408 23:22:05.998513 10, 0xFFFF, sum = 0
3409 23:22:05.998988 11, 0x0, sum = 1
3410 23:22:05.999364 12, 0x0, sum = 2
3411 23:22:06.001226 13, 0x0, sum = 3
3412 23:22:06.001696 14, 0x0, sum = 4
3413 23:22:06.004630 best_step = 12
3414 23:22:06.005133
3415 23:22:06.005501 ==
3416 23:22:06.008112 Dram Type= 6, Freq= 0, CH_1, rank 1
3417 23:22:06.011138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3418 23:22:06.011562 ==
3419 23:22:06.015134 RX Vref Scan: 0
3420 23:22:06.015750
3421 23:22:06.016211 RX Vref 0 -> 0, step: 1
3422 23:22:06.016583
3423 23:22:06.017935 RX Delay -21 -> 252, step: 4
3424 23:22:06.024649 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3425 23:22:06.029230 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3426 23:22:06.031208 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3427 23:22:06.034742 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3428 23:22:06.037797 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3429 23:22:06.044886 iDelay=199, Bit 5, Center 126 (55 ~ 198) 144
3430 23:22:06.047738 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
3431 23:22:06.052193 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3432 23:22:06.055317 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3433 23:22:06.058764 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3434 23:22:06.065059 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3435 23:22:06.068916 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3436 23:22:06.071794 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3437 23:22:06.075246 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3438 23:22:06.078981 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3439 23:22:06.085811 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3440 23:22:06.086367 ==
3441 23:22:06.088012 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 23:22:06.092156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3443 23:22:06.092578 ==
3444 23:22:06.092970 DQS Delay:
3445 23:22:06.095117 DQS0 = 0, DQS1 = 0
3446 23:22:06.095529 DQM Delay:
3447 23:22:06.098286 DQM0 = 115, DQM1 = 104
3448 23:22:06.098700 DQ Delay:
3449 23:22:06.101305 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =112
3450 23:22:06.105196 DQ4 =116, DQ5 =126, DQ6 =124, DQ7 =112
3451 23:22:06.108344 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3452 23:22:06.111497 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =112
3453 23:22:06.111956
3454 23:22:06.112282
3455 23:22:06.121948 [DQSOSCAuto] RK1, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3456 23:22:06.124685 CH1 RK1: MR19=404, MR18=909
3457 23:22:06.128814 CH1_RK1: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
3458 23:22:06.131781 [RxdqsGatingPostProcess] freq 1200
3459 23:22:06.138038 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3460 23:22:06.141654 Pre-setting of DQS Precalculation
3461 23:22:06.144762 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3462 23:22:06.155015 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3463 23:22:06.161581 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3464 23:22:06.162156
3465 23:22:06.162660
3466 23:22:06.165070 [Calibration Summary] 2400 Mbps
3467 23:22:06.165619 CH 0, Rank 0
3468 23:22:06.168626 SW Impedance : PASS
3469 23:22:06.169191 DUTY Scan : NO K
3470 23:22:06.171272 ZQ Calibration : PASS
3471 23:22:06.175186 Jitter Meter : NO K
3472 23:22:06.175599 CBT Training : PASS
3473 23:22:06.178200 Write leveling : PASS
3474 23:22:06.181331 RX DQS gating : PASS
3475 23:22:06.181746 RX DQ/DQS(RDDQC) : PASS
3476 23:22:06.184836 TX DQ/DQS : PASS
3477 23:22:06.185255 RX DATLAT : PASS
3478 23:22:06.188453 RX DQ/DQS(Engine): PASS
3479 23:22:06.191251 TX OE : NO K
3480 23:22:06.191812 All Pass.
3481 23:22:06.192150
3482 23:22:06.192459 CH 0, Rank 1
3483 23:22:06.194849 SW Impedance : PASS
3484 23:22:06.198495 DUTY Scan : NO K
3485 23:22:06.198909 ZQ Calibration : PASS
3486 23:22:06.201231 Jitter Meter : NO K
3487 23:22:06.205521 CBT Training : PASS
3488 23:22:06.205935 Write leveling : PASS
3489 23:22:06.207912 RX DQS gating : PASS
3490 23:22:06.211610 RX DQ/DQS(RDDQC) : PASS
3491 23:22:06.212024 TX DQ/DQS : PASS
3492 23:22:06.214995 RX DATLAT : PASS
3493 23:22:06.218995 RX DQ/DQS(Engine): PASS
3494 23:22:06.219408 TX OE : NO K
3495 23:22:06.221478 All Pass.
3496 23:22:06.221890
3497 23:22:06.222216 CH 1, Rank 0
3498 23:22:06.224653 SW Impedance : PASS
3499 23:22:06.225155 DUTY Scan : NO K
3500 23:22:06.228058 ZQ Calibration : PASS
3501 23:22:06.231211 Jitter Meter : NO K
3502 23:22:06.231741 CBT Training : PASS
3503 23:22:06.234629 Write leveling : PASS
3504 23:22:06.235062 RX DQS gating : PASS
3505 23:22:06.238515 RX DQ/DQS(RDDQC) : PASS
3506 23:22:06.241435 TX DQ/DQS : PASS
3507 23:22:06.241893 RX DATLAT : PASS
3508 23:22:06.245116 RX DQ/DQS(Engine): PASS
3509 23:22:06.248059 TX OE : NO K
3510 23:22:06.248504 All Pass.
3511 23:22:06.248962
3512 23:22:06.249328 CH 1, Rank 1
3513 23:22:06.251174 SW Impedance : PASS
3514 23:22:06.254885 DUTY Scan : NO K
3515 23:22:06.255351 ZQ Calibration : PASS
3516 23:22:06.258316 Jitter Meter : NO K
3517 23:22:06.262133 CBT Training : PASS
3518 23:22:06.262678 Write leveling : PASS
3519 23:22:06.264819 RX DQS gating : PASS
3520 23:22:06.268159 RX DQ/DQS(RDDQC) : PASS
3521 23:22:06.268780 TX DQ/DQS : PASS
3522 23:22:06.271331 RX DATLAT : PASS
3523 23:22:06.275359 RX DQ/DQS(Engine): PASS
3524 23:22:06.275905 TX OE : NO K
3525 23:22:06.276342 All Pass.
3526 23:22:06.278088
3527 23:22:06.278670 DramC Write-DBI off
3528 23:22:06.281494 PER_BANK_REFRESH: Hybrid Mode
3529 23:22:06.281976 TX_TRACKING: ON
3530 23:22:06.291233 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3531 23:22:06.294811 [FAST_K] Save calibration result to emmc
3532 23:22:06.298259 dramc_set_vcore_voltage set vcore to 650000
3533 23:22:06.301597 Read voltage for 600, 5
3534 23:22:06.302017 Vio18 = 0
3535 23:22:06.304821 Vcore = 650000
3536 23:22:06.305252 Vdram = 0
3537 23:22:06.305589 Vddq = 0
3538 23:22:06.305903 Vmddr = 0
3539 23:22:06.311963 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3540 23:22:06.318229 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3541 23:22:06.318744 MEM_TYPE=3, freq_sel=19
3542 23:22:06.320963 sv_algorithm_assistance_LP4_1600
3543 23:22:06.324688 ============ PULL DRAM RESETB DOWN ============
3544 23:22:06.331562 ========== PULL DRAM RESETB DOWN end =========
3545 23:22:06.334686 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3546 23:22:06.338012 ===================================
3547 23:22:06.341698 LPDDR4 DRAM CONFIGURATION
3548 23:22:06.344521 ===================================
3549 23:22:06.344993 EX_ROW_EN[0] = 0x0
3550 23:22:06.347936 EX_ROW_EN[1] = 0x0
3551 23:22:06.348350 LP4Y_EN = 0x0
3552 23:22:06.351482 WORK_FSP = 0x0
3553 23:22:06.351905 WL = 0x2
3554 23:22:06.354452 RL = 0x2
3555 23:22:06.354943 BL = 0x2
3556 23:22:06.358514 RPST = 0x0
3557 23:22:06.358930 RD_PRE = 0x0
3558 23:22:06.361422 WR_PRE = 0x1
3559 23:22:06.361885 WR_PST = 0x0
3560 23:22:06.364701 DBI_WR = 0x0
3561 23:22:06.368856 DBI_RD = 0x0
3562 23:22:06.369269 OTF = 0x1
3563 23:22:06.370965 ===================================
3564 23:22:06.374636 ===================================
3565 23:22:06.375051 ANA top config
3566 23:22:06.378777 ===================================
3567 23:22:06.380802 DLL_ASYNC_EN = 0
3568 23:22:06.384250 ALL_SLAVE_EN = 1
3569 23:22:06.387472 NEW_RANK_MODE = 1
3570 23:22:06.390850 DLL_IDLE_MODE = 1
3571 23:22:06.391296 LP45_APHY_COMB_EN = 1
3572 23:22:06.393977 TX_ODT_DIS = 1
3573 23:22:06.397368 NEW_8X_MODE = 1
3574 23:22:06.400440 ===================================
3575 23:22:06.404458 ===================================
3576 23:22:06.407412 data_rate = 1200
3577 23:22:06.410528 CKR = 1
3578 23:22:06.414031 DQ_P2S_RATIO = 8
3579 23:22:06.414464 ===================================
3580 23:22:06.418541 CA_P2S_RATIO = 8
3581 23:22:06.421411 DQ_CA_OPEN = 0
3582 23:22:06.424083 DQ_SEMI_OPEN = 0
3583 23:22:06.427572 CA_SEMI_OPEN = 0
3584 23:22:06.430495 CA_FULL_RATE = 0
3585 23:22:06.430912 DQ_CKDIV4_EN = 1
3586 23:22:06.433988 CA_CKDIV4_EN = 1
3587 23:22:06.438044 CA_PREDIV_EN = 0
3588 23:22:06.440768 PH8_DLY = 0
3589 23:22:06.444214 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3590 23:22:06.447581 DQ_AAMCK_DIV = 4
3591 23:22:06.448116 CA_AAMCK_DIV = 4
3592 23:22:06.450823 CA_ADMCK_DIV = 4
3593 23:22:06.454079 DQ_TRACK_CA_EN = 0
3594 23:22:06.457228 CA_PICK = 600
3595 23:22:06.460781 CA_MCKIO = 600
3596 23:22:06.464003 MCKIO_SEMI = 0
3597 23:22:06.467066 PLL_FREQ = 2288
3598 23:22:06.467495 DQ_UI_PI_RATIO = 32
3599 23:22:06.470419 CA_UI_PI_RATIO = 0
3600 23:22:06.473870 ===================================
3601 23:22:06.476913 ===================================
3602 23:22:06.480442 memory_type:LPDDR4
3603 23:22:06.484086 GP_NUM : 10
3604 23:22:06.484605 SRAM_EN : 1
3605 23:22:06.487010 MD32_EN : 0
3606 23:22:06.490512 ===================================
3607 23:22:06.494277 [ANA_INIT] >>>>>>>>>>>>>>
3608 23:22:06.494736 <<<<<< [CONFIGURE PHASE]: ANA_TX
3609 23:22:06.500088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3610 23:22:06.503766 ===================================
3611 23:22:06.504296 data_rate = 1200,PCW = 0X5800
3612 23:22:06.507061 ===================================
3613 23:22:06.510601 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3614 23:22:06.516346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3615 23:22:06.523797 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3616 23:22:06.526401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3617 23:22:06.530116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3618 23:22:06.533230 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3619 23:22:06.536244 [ANA_INIT] flow start
3620 23:22:06.539809 [ANA_INIT] PLL >>>>>>>>
3621 23:22:06.540347 [ANA_INIT] PLL <<<<<<<<
3622 23:22:06.542777 [ANA_INIT] MIDPI >>>>>>>>
3623 23:22:06.547085 [ANA_INIT] MIDPI <<<<<<<<
3624 23:22:06.547617 [ANA_INIT] DLL >>>>>>>>
3625 23:22:06.549626 [ANA_INIT] flow end
3626 23:22:06.552985 ============ LP4 DIFF to SE enter ============
3627 23:22:06.556400 ============ LP4 DIFF to SE exit ============
3628 23:22:06.559760 [ANA_INIT] <<<<<<<<<<<<<
3629 23:22:06.563099 [Flow] Enable top DCM control >>>>>
3630 23:22:06.566042 [Flow] Enable top DCM control <<<<<
3631 23:22:06.569756 Enable DLL master slave shuffle
3632 23:22:06.576403 ==============================================================
3633 23:22:06.576990 Gating Mode config
3634 23:22:06.582822 ==============================================================
3635 23:22:06.583361 Config description:
3636 23:22:06.592449 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3637 23:22:06.599327 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3638 23:22:06.606556 SELPH_MODE 0: By rank 1: By Phase
3639 23:22:06.609346 ==============================================================
3640 23:22:06.612461 GAT_TRACK_EN = 1
3641 23:22:06.616021 RX_GATING_MODE = 2
3642 23:22:06.619032 RX_GATING_TRACK_MODE = 2
3643 23:22:06.622346 SELPH_MODE = 1
3644 23:22:06.625488 PICG_EARLY_EN = 1
3645 23:22:06.628622 VALID_LAT_VALUE = 1
3646 23:22:06.635772 ==============================================================
3647 23:22:06.639642 Enter into Gating configuration >>>>
3648 23:22:06.642287 Exit from Gating configuration <<<<
3649 23:22:06.645376 Enter into DVFS_PRE_config >>>>>
3650 23:22:06.655144 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3651 23:22:06.658458 Exit from DVFS_PRE_config <<<<<
3652 23:22:06.661874 Enter into PICG configuration >>>>
3653 23:22:06.665630 Exit from PICG configuration <<<<
3654 23:22:06.668385 [RX_INPUT] configuration >>>>>
3655 23:22:06.668902 [RX_INPUT] configuration <<<<<
3656 23:22:06.675477 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3657 23:22:06.682029 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3658 23:22:06.688557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3659 23:22:06.691324 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3660 23:22:06.697951 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3661 23:22:06.704739 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3662 23:22:06.708414 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3663 23:22:06.714848 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3664 23:22:06.718640 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3665 23:22:06.721462 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3666 23:22:06.724551 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3667 23:22:06.731162 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3668 23:22:06.734706 ===================================
3669 23:22:06.735179 LPDDR4 DRAM CONFIGURATION
3670 23:22:06.738016 ===================================
3671 23:22:06.740880 EX_ROW_EN[0] = 0x0
3672 23:22:06.745984 EX_ROW_EN[1] = 0x0
3673 23:22:06.746481 LP4Y_EN = 0x0
3674 23:22:06.747563 WORK_FSP = 0x0
3675 23:22:06.748026 WL = 0x2
3676 23:22:06.751175 RL = 0x2
3677 23:22:06.751638 BL = 0x2
3678 23:22:06.754327 RPST = 0x0
3679 23:22:06.754791 RD_PRE = 0x0
3680 23:22:06.757846 WR_PRE = 0x1
3681 23:22:06.758307 WR_PST = 0x0
3682 23:22:06.761049 DBI_WR = 0x0
3683 23:22:06.761514 DBI_RD = 0x0
3684 23:22:06.764338 OTF = 0x1
3685 23:22:06.767401 ===================================
3686 23:22:06.770705 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3687 23:22:06.774247 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3688 23:22:06.781053 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3689 23:22:06.784061 ===================================
3690 23:22:06.784483 LPDDR4 DRAM CONFIGURATION
3691 23:22:06.787573 ===================================
3692 23:22:06.790591 EX_ROW_EN[0] = 0x10
3693 23:22:06.794415 EX_ROW_EN[1] = 0x0
3694 23:22:06.794905 LP4Y_EN = 0x0
3695 23:22:06.797651 WORK_FSP = 0x0
3696 23:22:06.798225 WL = 0x2
3697 23:22:06.800609 RL = 0x2
3698 23:22:06.801181 BL = 0x2
3699 23:22:06.804115 RPST = 0x0
3700 23:22:06.804537 RD_PRE = 0x0
3701 23:22:06.807577 WR_PRE = 0x1
3702 23:22:06.807998 WR_PST = 0x0
3703 23:22:06.810074 DBI_WR = 0x0
3704 23:22:06.810496 DBI_RD = 0x0
3705 23:22:06.814030 OTF = 0x1
3706 23:22:06.817036 ===================================
3707 23:22:06.823374 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3708 23:22:06.826969 nWR fixed to 30
3709 23:22:06.829903 [ModeRegInit_LP4] CH0 RK0
3710 23:22:06.830115 [ModeRegInit_LP4] CH0 RK1
3711 23:22:06.833838 [ModeRegInit_LP4] CH1 RK0
3712 23:22:06.836355 [ModeRegInit_LP4] CH1 RK1
3713 23:22:06.836439 match AC timing 16
3714 23:22:06.843283 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3715 23:22:06.846396 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3716 23:22:06.849521 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3717 23:22:06.855938 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3718 23:22:06.859529 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3719 23:22:06.859629 ==
3720 23:22:06.862613 Dram Type= 6, Freq= 0, CH_0, rank 0
3721 23:22:06.865894 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3722 23:22:06.865977 ==
3723 23:22:06.872709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3724 23:22:06.879784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3725 23:22:06.883463 [CA 0] Center 35 (5~66) winsize 62
3726 23:22:06.886655 [CA 1] Center 35 (5~66) winsize 62
3727 23:22:06.889858 [CA 2] Center 34 (4~65) winsize 62
3728 23:22:06.893187 [CA 3] Center 34 (4~65) winsize 62
3729 23:22:06.896140 [CA 4] Center 33 (3~64) winsize 62
3730 23:22:06.899474 [CA 5] Center 33 (3~64) winsize 62
3731 23:22:06.900004
3732 23:22:06.903329 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3733 23:22:06.903797
3734 23:22:06.906322 [CATrainingPosCal] consider 1 rank data
3735 23:22:06.909268 u2DelayCellTimex100 = 270/100 ps
3736 23:22:06.913321 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3737 23:22:06.916493 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3738 23:22:06.919284 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3739 23:22:06.922846 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3740 23:22:06.926163 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3741 23:22:06.932925 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3742 23:22:06.933351
3743 23:22:06.936166 CA PerBit enable=1, Macro0, CA PI delay=33
3744 23:22:06.936588
3745 23:22:06.939714 [CBTSetCACLKResult] CA Dly = 33
3746 23:22:06.940137 CS Dly: 4 (0~35)
3747 23:22:06.940473 ==
3748 23:22:06.942993 Dram Type= 6, Freq= 0, CH_0, rank 1
3749 23:22:06.948922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3750 23:22:06.949349 ==
3751 23:22:06.952164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3752 23:22:06.958950 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3753 23:22:06.962661 [CA 0] Center 35 (5~66) winsize 62
3754 23:22:06.966280 [CA 1] Center 35 (5~66) winsize 62
3755 23:22:06.968643 [CA 2] Center 34 (4~65) winsize 62
3756 23:22:06.972195 [CA 3] Center 34 (4~65) winsize 62
3757 23:22:06.975552 [CA 4] Center 33 (3~64) winsize 62
3758 23:22:06.979041 [CA 5] Center 33 (3~64) winsize 62
3759 23:22:06.979466
3760 23:22:06.981901 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3761 23:22:06.982324
3762 23:22:06.985169 [CATrainingPosCal] consider 2 rank data
3763 23:22:06.989037 u2DelayCellTimex100 = 270/100 ps
3764 23:22:06.992073 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3765 23:22:06.995580 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3766 23:22:07.002538 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3767 23:22:07.005328 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3768 23:22:07.008274 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3769 23:22:07.011839 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3770 23:22:07.012022
3771 23:22:07.015067 CA PerBit enable=1, Macro0, CA PI delay=33
3772 23:22:07.015248
3773 23:22:07.017961 [CBTSetCACLKResult] CA Dly = 33
3774 23:22:07.018177 CS Dly: 4 (0~36)
3775 23:22:07.018325
3776 23:22:07.021591 ----->DramcWriteLeveling(PI) begin...
3777 23:22:07.024668 ==
3778 23:22:07.028176 Dram Type= 6, Freq= 0, CH_0, rank 0
3779 23:22:07.031565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3780 23:22:07.031749 ==
3781 23:22:07.035191 Write leveling (Byte 0): 29 => 29
3782 23:22:07.037961 Write leveling (Byte 1): 31 => 31
3783 23:22:07.041397 DramcWriteLeveling(PI) end<-----
3784 23:22:07.041580
3785 23:22:07.041723 ==
3786 23:22:07.045550 Dram Type= 6, Freq= 0, CH_0, rank 0
3787 23:22:07.048246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3788 23:22:07.048504 ==
3789 23:22:07.051225 [Gating] SW mode calibration
3790 23:22:07.058022 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3791 23:22:07.065171 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3792 23:22:07.068196 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3793 23:22:07.071116 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3794 23:22:07.078195 0 5 8 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 0)
3795 23:22:07.081040 0 5 12 | B1->B0 | 2929 2424 | 0 0 | (0 0) (1 0)
3796 23:22:07.084812 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3797 23:22:07.090965 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3798 23:22:07.094616 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3799 23:22:07.098002 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3800 23:22:07.104565 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3801 23:22:07.107851 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3802 23:22:07.111543 0 6 8 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (0 0)
3803 23:22:07.118027 0 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3804 23:22:07.121835 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3805 23:22:07.124626 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3806 23:22:07.131345 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3807 23:22:07.134023 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3808 23:22:07.137988 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3809 23:22:07.140812 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3810 23:22:07.148081 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3811 23:22:07.151188 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 23:22:07.154080 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 23:22:07.160543 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 23:22:07.163968 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 23:22:07.167178 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 23:22:07.174498 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 23:22:07.177371 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 23:22:07.180222 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 23:22:07.186767 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 23:22:07.189932 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 23:22:07.193387 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 23:22:07.200103 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 23:22:07.203106 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 23:22:07.206583 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 23:22:07.212946 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 23:22:07.216325 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3827 23:22:07.219661 Total UI for P1: 0, mck2ui 16
3828 23:22:07.223086 best dqsien dly found for B0: ( 0, 9, 6)
3829 23:22:07.226377 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3830 23:22:07.229738 Total UI for P1: 0, mck2ui 16
3831 23:22:07.233143 best dqsien dly found for B1: ( 0, 9, 8)
3832 23:22:07.236213 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3833 23:22:07.239706 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3834 23:22:07.244415
3835 23:22:07.246055 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3836 23:22:07.250000 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3837 23:22:07.253187 [Gating] SW calibration Done
3838 23:22:07.253415 ==
3839 23:22:07.256553 Dram Type= 6, Freq= 0, CH_0, rank 0
3840 23:22:07.259458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3841 23:22:07.259686 ==
3842 23:22:07.259868 RX Vref Scan: 0
3843 23:22:07.260037
3844 23:22:07.263134 RX Vref 0 -> 0, step: 1
3845 23:22:07.263366
3846 23:22:07.266262 RX Delay -230 -> 252, step: 16
3847 23:22:07.269396 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3848 23:22:07.276026 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3849 23:22:07.279645 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3850 23:22:07.283095 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3851 23:22:07.286521 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3852 23:22:07.289832 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3853 23:22:07.297695 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3854 23:22:07.299553 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3855 23:22:07.302960 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3856 23:22:07.306341 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3857 23:22:07.312497 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3858 23:22:07.315621 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3859 23:22:07.319128 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3860 23:22:07.322549 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3861 23:22:07.325824 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3862 23:22:07.332468 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3863 23:22:07.332778 ==
3864 23:22:07.335643 Dram Type= 6, Freq= 0, CH_0, rank 0
3865 23:22:07.339069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3866 23:22:07.339467 ==
3867 23:22:07.339696 DQS Delay:
3868 23:22:07.342918 DQS0 = 0, DQS1 = 0
3869 23:22:07.343199 DQM Delay:
3870 23:22:07.346057 DQM0 = 39, DQM1 = 33
3871 23:22:07.346335 DQ Delay:
3872 23:22:07.348998 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
3873 23:22:07.352500 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3874 23:22:07.355590 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3875 23:22:07.359399 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3876 23:22:07.359688
3877 23:22:07.359910
3878 23:22:07.360115 ==
3879 23:22:07.362416 Dram Type= 6, Freq= 0, CH_0, rank 0
3880 23:22:07.366351 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3881 23:22:07.369065 ==
3882 23:22:07.369342
3883 23:22:07.369563
3884 23:22:07.369767 TX Vref Scan disable
3885 23:22:07.372570 == TX Byte 0 ==
3886 23:22:07.376112 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3887 23:22:07.380028 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3888 23:22:07.382222 == TX Byte 1 ==
3889 23:22:07.385471 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3890 23:22:07.388938 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3891 23:22:07.392561 ==
3892 23:22:07.395751 Dram Type= 6, Freq= 0, CH_0, rank 0
3893 23:22:07.399575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3894 23:22:07.399854 ==
3895 23:22:07.400075
3896 23:22:07.400280
3897 23:22:07.403461 TX Vref Scan disable
3898 23:22:07.403740 == TX Byte 0 ==
3899 23:22:07.409034 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3900 23:22:07.412152 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3901 23:22:07.412431 == TX Byte 1 ==
3902 23:22:07.418824 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3903 23:22:07.421989 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3904 23:22:07.422268
3905 23:22:07.422489 [DATLAT]
3906 23:22:07.425693 Freq=600, CH0 RK0
3907 23:22:07.425972
3908 23:22:07.426193 DATLAT Default: 0x9
3909 23:22:07.428922 0, 0xFFFF, sum = 0
3910 23:22:07.431897 1, 0xFFFF, sum = 0
3911 23:22:07.432173 2, 0xFFFF, sum = 0
3912 23:22:07.435094 3, 0xFFFF, sum = 0
3913 23:22:07.435373 4, 0xFFFF, sum = 0
3914 23:22:07.438750 5, 0xFFFF, sum = 0
3915 23:22:07.439027 6, 0xFFFF, sum = 0
3916 23:22:07.441831 7, 0x0, sum = 1
3917 23:22:07.442091 8, 0x0, sum = 2
3918 23:22:07.442261 9, 0x0, sum = 3
3919 23:22:07.445180 10, 0x0, sum = 4
3920 23:22:07.445392 best_step = 8
3921 23:22:07.445558
3922 23:22:07.445742 ==
3923 23:22:07.448615 Dram Type= 6, Freq= 0, CH_0, rank 0
3924 23:22:07.454973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3925 23:22:07.455144 ==
3926 23:22:07.455280 RX Vref Scan: 1
3927 23:22:07.455406
3928 23:22:07.458665 RX Vref 0 -> 0, step: 1
3929 23:22:07.458834
3930 23:22:07.461625 RX Delay -195 -> 252, step: 8
3931 23:22:07.461829
3932 23:22:07.464966 Set Vref, RX VrefLevel [Byte0]: 52
3933 23:22:07.468013 [Byte1]: 49
3934 23:22:07.468185
3935 23:22:07.471432 Final RX Vref Byte 0 = 52 to rank0
3936 23:22:07.475551 Final RX Vref Byte 1 = 49 to rank0
3937 23:22:07.479110 Final RX Vref Byte 0 = 52 to rank1
3938 23:22:07.481681 Final RX Vref Byte 1 = 49 to rank1==
3939 23:22:07.485007 Dram Type= 6, Freq= 0, CH_0, rank 0
3940 23:22:07.488202 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3941 23:22:07.488373 ==
3942 23:22:07.491988 DQS Delay:
3943 23:22:07.492159 DQS0 = 0, DQS1 = 0
3944 23:22:07.494848 DQM Delay:
3945 23:22:07.495019 DQM0 = 40, DQM1 = 30
3946 23:22:07.495154 DQ Delay:
3947 23:22:07.498050 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =40
3948 23:22:07.501832 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
3949 23:22:07.504985 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3950 23:22:07.507863 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3951 23:22:07.508032
3952 23:22:07.508166
3953 23:22:07.517954 [DQSOSCAuto] RK0, (LSB)MR18= 0x5151, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
3954 23:22:07.521646 CH0 RK0: MR19=808, MR18=5151
3955 23:22:07.528001 CH0_RK0: MR19=0x808, MR18=0x5151, DQSOSC=394, MR23=63, INC=168, DEC=112
3956 23:22:07.528172
3957 23:22:07.531891 ----->DramcWriteLeveling(PI) begin...
3958 23:22:07.532064 ==
3959 23:22:07.534889 Dram Type= 6, Freq= 0, CH_0, rank 1
3960 23:22:07.537647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3961 23:22:07.537819 ==
3962 23:22:07.541217 Write leveling (Byte 0): 30 => 30
3963 23:22:07.544753 Write leveling (Byte 1): 30 => 30
3964 23:22:07.548584 DramcWriteLeveling(PI) end<-----
3965 23:22:07.548779
3966 23:22:07.548917 ==
3967 23:22:07.551215 Dram Type= 6, Freq= 0, CH_0, rank 1
3968 23:22:07.554374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3969 23:22:07.554545 ==
3970 23:22:07.557757 [Gating] SW mode calibration
3971 23:22:07.564905 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3972 23:22:07.571528 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3973 23:22:07.574688 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 23:22:07.577299 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 23:22:07.584205 0 5 8 | B1->B0 | 3333 2f2f | 0 1 | (0 1) (1 1)
3976 23:22:07.587328 0 5 12 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
3977 23:22:07.590653 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 23:22:07.597272 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 23:22:07.600596 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 23:22:07.604667 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 23:22:07.611235 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 23:22:07.614190 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 23:22:07.617071 0 6 8 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
3984 23:22:07.624082 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 23:22:07.627162 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 23:22:07.630399 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 23:22:07.638009 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 23:22:07.640245 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 23:22:07.643888 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 23:22:07.650599 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 23:22:07.653507 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3992 23:22:07.657157 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 23:22:07.664023 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 23:22:07.667293 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 23:22:07.670250 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 23:22:07.677167 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 23:22:07.680518 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 23:22:07.683481 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 23:22:07.686988 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 23:22:07.693621 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 23:22:07.696668 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 23:22:07.700280 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 23:22:07.706569 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 23:22:07.710499 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 23:22:07.713250 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 23:22:07.720248 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 23:22:07.723023 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4008 23:22:07.726661 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4009 23:22:07.729622 Total UI for P1: 0, mck2ui 16
4010 23:22:07.733112 best dqsien dly found for B0: ( 0, 9, 10)
4011 23:22:07.740364 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 23:22:07.743965 Total UI for P1: 0, mck2ui 16
4013 23:22:07.746501 best dqsien dly found for B1: ( 0, 9, 10)
4014 23:22:07.750076 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
4015 23:22:07.752833 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4016 23:22:07.752914
4017 23:22:07.756320 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
4018 23:22:07.759581 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4019 23:22:07.763202 [Gating] SW calibration Done
4020 23:22:07.763282 ==
4021 23:22:07.766185 Dram Type= 6, Freq= 0, CH_0, rank 1
4022 23:22:07.770319 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4023 23:22:07.770402 ==
4024 23:22:07.773128 RX Vref Scan: 0
4025 23:22:07.773210
4026 23:22:07.775953 RX Vref 0 -> 0, step: 1
4027 23:22:07.776035
4028 23:22:07.776101 RX Delay -230 -> 252, step: 16
4029 23:22:07.782509 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4030 23:22:07.785899 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4031 23:22:07.789640 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4032 23:22:07.793157 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4033 23:22:07.799079 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4034 23:22:07.802734 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4035 23:22:07.806523 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4036 23:22:07.809131 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4037 23:22:07.815749 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4038 23:22:07.819104 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4039 23:22:07.822188 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4040 23:22:07.825370 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4041 23:22:07.832563 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4042 23:22:07.835693 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4043 23:22:07.838756 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4044 23:22:07.842569 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4045 23:22:07.842651 ==
4046 23:22:07.846213 Dram Type= 6, Freq= 0, CH_0, rank 1
4047 23:22:07.852515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4048 23:22:07.852623 ==
4049 23:22:07.852726 DQS Delay:
4050 23:22:07.852790 DQS0 = 0, DQS1 = 0
4051 23:22:07.856823 DQM Delay:
4052 23:22:07.856904 DQM0 = 41, DQM1 = 33
4053 23:22:07.858670 DQ Delay:
4054 23:22:07.862747 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4055 23:22:07.865897 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4056 23:22:07.869814 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4057 23:22:07.872505 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4058 23:22:07.872586
4059 23:22:07.872650
4060 23:22:07.872739 ==
4061 23:22:07.875720 Dram Type= 6, Freq= 0, CH_0, rank 1
4062 23:22:07.878912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4063 23:22:07.878995 ==
4064 23:22:07.879059
4065 23:22:07.879119
4066 23:22:07.882211 TX Vref Scan disable
4067 23:22:07.882293 == TX Byte 0 ==
4068 23:22:07.888593 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4069 23:22:07.891612 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4070 23:22:07.895498 == TX Byte 1 ==
4071 23:22:07.898451 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4072 23:22:07.901622 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4073 23:22:07.901704 ==
4074 23:22:07.905968 Dram Type= 6, Freq= 0, CH_0, rank 1
4075 23:22:07.908617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4076 23:22:07.908765 ==
4077 23:22:07.911758
4078 23:22:07.911838
4079 23:22:07.911903 TX Vref Scan disable
4080 23:22:07.915824 == TX Byte 0 ==
4081 23:22:07.918346 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4082 23:22:07.925101 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4083 23:22:07.925184 == TX Byte 1 ==
4084 23:22:07.929002 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4085 23:22:07.935084 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4086 23:22:07.935166
4087 23:22:07.935231 [DATLAT]
4088 23:22:07.935291 Freq=600, CH0 RK1
4089 23:22:07.935351
4090 23:22:07.939079 DATLAT Default: 0x8
4091 23:22:07.939162 0, 0xFFFF, sum = 0
4092 23:22:07.941896 1, 0xFFFF, sum = 0
4093 23:22:07.941980 2, 0xFFFF, sum = 0
4094 23:22:07.945277 3, 0xFFFF, sum = 0
4095 23:22:07.948237 4, 0xFFFF, sum = 0
4096 23:22:07.948321 5, 0xFFFF, sum = 0
4097 23:22:07.951567 6, 0xFFFF, sum = 0
4098 23:22:07.951651 7, 0x0, sum = 1
4099 23:22:07.951718 8, 0x0, sum = 2
4100 23:22:07.954678 9, 0x0, sum = 3
4101 23:22:07.954762 10, 0x0, sum = 4
4102 23:22:07.958600 best_step = 8
4103 23:22:07.958682
4104 23:22:07.958747 ==
4105 23:22:07.961403 Dram Type= 6, Freq= 0, CH_0, rank 1
4106 23:22:07.965326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4107 23:22:07.965409 ==
4108 23:22:07.968210 RX Vref Scan: 0
4109 23:22:07.968298
4110 23:22:07.968367 RX Vref 0 -> 0, step: 1
4111 23:22:07.968432
4112 23:22:07.972158 RX Delay -195 -> 252, step: 8
4113 23:22:07.979199 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4114 23:22:07.982831 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4115 23:22:07.986317 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4116 23:22:07.989111 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4117 23:22:07.995741 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4118 23:22:07.999778 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4119 23:22:08.002915 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4120 23:22:08.005659 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4121 23:22:08.012643 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4122 23:22:08.015441 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4123 23:22:08.019700 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4124 23:22:08.022062 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4125 23:22:08.025491 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4126 23:22:08.032217 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4127 23:22:08.035616 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4128 23:22:08.039043 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4129 23:22:08.039641 ==
4130 23:22:08.042447 Dram Type= 6, Freq= 0, CH_0, rank 1
4131 23:22:08.048581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4132 23:22:08.049066 ==
4133 23:22:08.049405 DQS Delay:
4134 23:22:08.052107 DQS0 = 0, DQS1 = 0
4135 23:22:08.052538 DQM Delay:
4136 23:22:08.052920 DQM0 = 42, DQM1 = 32
4137 23:22:08.055616 DQ Delay:
4138 23:22:08.059394 DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =36
4139 23:22:08.062858 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =52
4140 23:22:08.064956 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4141 23:22:08.068627 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4142 23:22:08.069089
4143 23:22:08.069424
4144 23:22:08.074830 [DQSOSCAuto] RK1, (LSB)MR18= 0x6565, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4145 23:22:08.078316 CH0 RK1: MR19=808, MR18=6565
4146 23:22:08.085215 CH0_RK1: MR19=0x808, MR18=0x6565, DQSOSC=390, MR23=63, INC=172, DEC=114
4147 23:22:08.088671 [RxdqsGatingPostProcess] freq 600
4148 23:22:08.091329 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4149 23:22:08.095089 Pre-setting of DQS Precalculation
4150 23:22:08.101565 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4151 23:22:08.101989 ==
4152 23:22:08.104462 Dram Type= 6, Freq= 0, CH_1, rank 0
4153 23:22:08.108369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4154 23:22:08.108850 ==
4155 23:22:08.115777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4156 23:22:08.121471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4157 23:22:08.124232 [CA 0] Center 35 (5~66) winsize 62
4158 23:22:08.127465 [CA 1] Center 35 (4~66) winsize 63
4159 23:22:08.131822 [CA 2] Center 33 (3~64) winsize 62
4160 23:22:08.134001 [CA 3] Center 33 (3~64) winsize 62
4161 23:22:08.137576 [CA 4] Center 33 (2~64) winsize 63
4162 23:22:08.141206 [CA 5] Center 33 (2~64) winsize 63
4163 23:22:08.141650
4164 23:22:08.144495 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4165 23:22:08.145021
4166 23:22:08.147412 [CATrainingPosCal] consider 1 rank data
4167 23:22:08.152356 u2DelayCellTimex100 = 270/100 ps
4168 23:22:08.154866 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4169 23:22:08.157606 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4170 23:22:08.160351 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4171 23:22:08.164444 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4172 23:22:08.167056 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4173 23:22:08.171840 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4174 23:22:08.172267
4175 23:22:08.177271 CA PerBit enable=1, Macro0, CA PI delay=33
4176 23:22:08.177695
4177 23:22:08.181175 [CBTSetCACLKResult] CA Dly = 33
4178 23:22:08.181611 CS Dly: 3 (0~34)
4179 23:22:08.181956 ==
4180 23:22:08.183860 Dram Type= 6, Freq= 0, CH_1, rank 1
4181 23:22:08.187831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4182 23:22:08.188257 ==
4183 23:22:08.193970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4184 23:22:08.200643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4185 23:22:08.203598 [CA 0] Center 35 (5~66) winsize 62
4186 23:22:08.206981 [CA 1] Center 34 (4~65) winsize 62
4187 23:22:08.210501 [CA 2] Center 33 (3~64) winsize 62
4188 23:22:08.213268 [CA 3] Center 33 (3~64) winsize 62
4189 23:22:08.216613 [CA 4] Center 32 (2~63) winsize 62
4190 23:22:08.219972 [CA 5] Center 32 (2~63) winsize 62
4191 23:22:08.220603
4192 23:22:08.223150 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4193 23:22:08.223572
4194 23:22:08.226953 [CATrainingPosCal] consider 2 rank data
4195 23:22:08.230436 u2DelayCellTimex100 = 270/100 ps
4196 23:22:08.233863 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4197 23:22:08.237092 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4198 23:22:08.240013 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4199 23:22:08.246552 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4200 23:22:08.249651 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4201 23:22:08.253515 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4202 23:22:08.253976
4203 23:22:08.256403 CA PerBit enable=1, Macro0, CA PI delay=32
4204 23:22:08.256895
4205 23:22:08.260030 [CBTSetCACLKResult] CA Dly = 32
4206 23:22:08.260456 CS Dly: 4 (0~37)
4207 23:22:08.260855
4208 23:22:08.262945 ----->DramcWriteLeveling(PI) begin...
4209 23:22:08.263377 ==
4210 23:22:08.266312 Dram Type= 6, Freq= 0, CH_1, rank 0
4211 23:22:08.273298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4212 23:22:08.273797 ==
4213 23:22:08.276170 Write leveling (Byte 0): 26 => 26
4214 23:22:08.280498 Write leveling (Byte 1): 27 => 27
4215 23:22:08.280970 DramcWriteLeveling(PI) end<-----
4216 23:22:08.282682
4217 23:22:08.283101 ==
4218 23:22:08.286043 Dram Type= 6, Freq= 0, CH_1, rank 0
4219 23:22:08.289846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4220 23:22:08.290307 ==
4221 23:22:08.293160 [Gating] SW mode calibration
4222 23:22:08.299236 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4223 23:22:08.302993 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4224 23:22:08.310116 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 23:22:08.312249 0 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4226 23:22:08.315890 0 5 8 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (0 0)
4227 23:22:08.322377 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 23:22:08.325796 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 23:22:08.329174 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 23:22:08.335746 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 23:22:08.339457 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 23:22:08.342488 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 23:22:08.349149 0 6 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4234 23:22:08.352529 0 6 8 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
4235 23:22:08.355318 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 23:22:08.362909 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 23:22:08.365624 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 23:22:08.369465 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 23:22:08.375773 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 23:22:08.378805 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 23:22:08.383381 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4242 23:22:08.388746 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:22:08.392059 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:22:08.395432 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:22:08.402962 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:22:08.405463 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:22:08.408579 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:22:08.415772 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:22:08.418453 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 23:22:08.421498 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:22:08.428133 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:22:08.431688 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:22:08.435079 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:22:08.442052 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 23:22:08.444658 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 23:22:08.447935 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 23:22:08.454577 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4258 23:22:08.458217 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 23:22:08.461178 Total UI for P1: 0, mck2ui 16
4260 23:22:08.464791 best dqsien dly found for B0: ( 0, 9, 4)
4261 23:22:08.468017 Total UI for P1: 0, mck2ui 16
4262 23:22:08.470723 best dqsien dly found for B1: ( 0, 9, 6)
4263 23:22:08.474371 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4264 23:22:08.477803 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4265 23:22:08.478276
4266 23:22:08.481158 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4267 23:22:08.484410 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4268 23:22:08.487706 [Gating] SW calibration Done
4269 23:22:08.488165 ==
4270 23:22:08.491292 Dram Type= 6, Freq= 0, CH_1, rank 0
4271 23:22:08.494380 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4272 23:22:08.497660 ==
4273 23:22:08.498116 RX Vref Scan: 0
4274 23:22:08.498460
4275 23:22:08.502542 RX Vref 0 -> 0, step: 1
4276 23:22:08.503067
4277 23:22:08.503749 RX Delay -230 -> 252, step: 16
4278 23:22:08.507781 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4279 23:22:08.511086 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4280 23:22:08.514558 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4281 23:22:08.520697 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4282 23:22:08.524159 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4283 23:22:08.528335 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4284 23:22:08.530769 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4285 23:22:08.533909 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4286 23:22:08.540836 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4287 23:22:08.544010 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4288 23:22:08.547418 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4289 23:22:08.550611 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4290 23:22:08.557334 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4291 23:22:08.560405 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4292 23:22:08.564159 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4293 23:22:08.566857 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4294 23:22:08.570273 ==
4295 23:22:08.573659 Dram Type= 6, Freq= 0, CH_1, rank 0
4296 23:22:08.576512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4297 23:22:08.576968 ==
4298 23:22:08.577297 DQS Delay:
4299 23:22:08.580112 DQS0 = 0, DQS1 = 0
4300 23:22:08.580522 DQM Delay:
4301 23:22:08.582973 DQM0 = 41, DQM1 = 33
4302 23:22:08.583381 DQ Delay:
4303 23:22:08.586540 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4304 23:22:08.590969 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41
4305 23:22:08.593302 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4306 23:22:08.596396 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4307 23:22:08.596991
4308 23:22:08.597470
4309 23:22:08.597901 ==
4310 23:22:08.600162 Dram Type= 6, Freq= 0, CH_1, rank 0
4311 23:22:08.603091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4312 23:22:08.603841 ==
4313 23:22:08.604432
4314 23:22:08.604958
4315 23:22:08.606470 TX Vref Scan disable
4316 23:22:08.609392 == TX Byte 0 ==
4317 23:22:08.613494 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4318 23:22:08.616316 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4319 23:22:08.619993 == TX Byte 1 ==
4320 23:22:08.622805 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4321 23:22:08.626310 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4322 23:22:08.626722 ==
4323 23:22:08.630323 Dram Type= 6, Freq= 0, CH_1, rank 0
4324 23:22:08.636078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4325 23:22:08.636491 ==
4326 23:22:08.636962
4327 23:22:08.637280
4328 23:22:08.637630 TX Vref Scan disable
4329 23:22:08.640684 == TX Byte 0 ==
4330 23:22:08.644067 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4331 23:22:08.650933 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4332 23:22:08.651445 == TX Byte 1 ==
4333 23:22:08.653982 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4334 23:22:08.660468 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4335 23:22:08.661045
4336 23:22:08.661386 [DATLAT]
4337 23:22:08.661694 Freq=600, CH1 RK0
4338 23:22:08.661988
4339 23:22:08.664445 DATLAT Default: 0x9
4340 23:22:08.665065 0, 0xFFFF, sum = 0
4341 23:22:08.667436 1, 0xFFFF, sum = 0
4342 23:22:08.667981 2, 0xFFFF, sum = 0
4343 23:22:08.671097 3, 0xFFFF, sum = 0
4344 23:22:08.673855 4, 0xFFFF, sum = 0
4345 23:22:08.674448 5, 0xFFFF, sum = 0
4346 23:22:08.677449 6, 0xFFFF, sum = 0
4347 23:22:08.678059 7, 0x0, sum = 1
4348 23:22:08.678596 8, 0x0, sum = 2
4349 23:22:08.680368 9, 0x0, sum = 3
4350 23:22:08.680962 10, 0x0, sum = 4
4351 23:22:08.683382 best_step = 8
4352 23:22:08.683937
4353 23:22:08.684442 ==
4354 23:22:08.686706 Dram Type= 6, Freq= 0, CH_1, rank 0
4355 23:22:08.690517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4356 23:22:08.691056 ==
4357 23:22:08.693651 RX Vref Scan: 1
4358 23:22:08.694099
4359 23:22:08.694474 RX Vref 0 -> 0, step: 1
4360 23:22:08.694865
4361 23:22:08.696998 RX Delay -195 -> 252, step: 8
4362 23:22:08.697424
4363 23:22:08.701201 Set Vref, RX VrefLevel [Byte0]: 52
4364 23:22:08.703330 [Byte1]: 49
4365 23:22:08.707535
4366 23:22:08.708155 Final RX Vref Byte 0 = 52 to rank0
4367 23:22:08.710723 Final RX Vref Byte 1 = 49 to rank0
4368 23:22:08.714460 Final RX Vref Byte 0 = 52 to rank1
4369 23:22:08.717362 Final RX Vref Byte 1 = 49 to rank1==
4370 23:22:08.720889 Dram Type= 6, Freq= 0, CH_1, rank 0
4371 23:22:08.727307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4372 23:22:08.727892 ==
4373 23:22:08.728369 DQS Delay:
4374 23:22:08.728895 DQS0 = 0, DQS1 = 0
4375 23:22:08.730459 DQM Delay:
4376 23:22:08.731013 DQM0 = 37, DQM1 = 30
4377 23:22:08.734084 DQ Delay:
4378 23:22:08.737043 DQ0 =36, DQ1 =32, DQ2 =28, DQ3 =36
4379 23:22:08.740834 DQ4 =36, DQ5 =52, DQ6 =44, DQ7 =36
4380 23:22:08.743853 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4381 23:22:08.747707 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4382 23:22:08.748150
4383 23:22:08.748478
4384 23:22:08.753512 [DQSOSCAuto] RK0, (LSB)MR18= 0x7272, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4385 23:22:08.757168 CH1 RK0: MR19=808, MR18=7272
4386 23:22:08.764319 CH1_RK0: MR19=0x808, MR18=0x7272, DQSOSC=388, MR23=63, INC=174, DEC=116
4387 23:22:08.764841
4388 23:22:08.767076 ----->DramcWriteLeveling(PI) begin...
4389 23:22:08.767492 ==
4390 23:22:08.770843 Dram Type= 6, Freq= 0, CH_1, rank 1
4391 23:22:08.774051 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4392 23:22:08.774465 ==
4393 23:22:08.776942 Write leveling (Byte 0): 28 => 28
4394 23:22:08.780048 Write leveling (Byte 1): 28 => 28
4395 23:22:08.784172 DramcWriteLeveling(PI) end<-----
4396 23:22:08.784584
4397 23:22:08.784943 ==
4398 23:22:08.787579 Dram Type= 6, Freq= 0, CH_1, rank 1
4399 23:22:08.790194 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4400 23:22:08.790608 ==
4401 23:22:08.794193 [Gating] SW mode calibration
4402 23:22:08.800571 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4403 23:22:08.806615 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4404 23:22:08.810269 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4405 23:22:08.816913 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4406 23:22:08.820082 0 5 8 | B1->B0 | 3030 2626 | 1 0 | (1 0) (0 0)
4407 23:22:08.823437 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 23:22:08.830111 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 23:22:08.833281 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 23:22:08.837531 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 23:22:08.843577 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 23:22:08.846717 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 23:22:08.851525 0 6 4 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 0)
4414 23:22:08.856142 0 6 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4415 23:22:08.859786 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 23:22:08.863534 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 23:22:08.870308 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 23:22:08.873814 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 23:22:08.876410 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 23:22:08.883921 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 23:22:08.886346 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 23:22:08.890761 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4423 23:22:08.897094 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 23:22:08.899967 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 23:22:08.902590 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 23:22:08.909057 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 23:22:08.912984 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 23:22:08.916246 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 23:22:08.922518 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 23:22:08.925691 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 23:22:08.929499 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 23:22:08.932876 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 23:22:08.939184 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 23:22:08.942441 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 23:22:08.945707 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 23:22:08.952741 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4437 23:22:08.955823 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4438 23:22:08.959222 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 23:22:08.962378 Total UI for P1: 0, mck2ui 16
4440 23:22:08.966149 best dqsien dly found for B0: ( 0, 9, 2)
4441 23:22:08.968993 Total UI for P1: 0, mck2ui 16
4442 23:22:08.972321 best dqsien dly found for B1: ( 0, 9, 6)
4443 23:22:08.975684 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4444 23:22:08.978995 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4445 23:22:08.979576
4446 23:22:08.985783 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4447 23:22:08.990070 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4448 23:22:08.991966 [Gating] SW calibration Done
4449 23:22:08.992508 ==
4450 23:22:08.996754 Dram Type= 6, Freq= 0, CH_1, rank 1
4451 23:22:08.998675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4452 23:22:08.999216 ==
4453 23:22:08.999715 RX Vref Scan: 0
4454 23:22:09.000194
4455 23:22:09.002317 RX Vref 0 -> 0, step: 1
4456 23:22:09.002868
4457 23:22:09.005428 RX Delay -230 -> 252, step: 16
4458 23:22:09.008668 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4459 23:22:09.012579 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4460 23:22:09.018721 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4461 23:22:09.021912 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4462 23:22:09.026306 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4463 23:22:09.030089 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4464 23:22:09.035403 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4465 23:22:09.038390 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4466 23:22:09.042072 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4467 23:22:09.044897 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4468 23:22:09.051278 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4469 23:22:09.054903 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4470 23:22:09.058239 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4471 23:22:09.062177 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4472 23:22:09.067857 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4473 23:22:09.071469 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4474 23:22:09.071886 ==
4475 23:22:09.075705 Dram Type= 6, Freq= 0, CH_1, rank 1
4476 23:22:09.078769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4477 23:22:09.079188 ==
4478 23:22:09.081219 DQS Delay:
4479 23:22:09.081875 DQS0 = 0, DQS1 = 0
4480 23:22:09.082233 DQM Delay:
4481 23:22:09.085580 DQM0 = 39, DQM1 = 33
4482 23:22:09.086128 DQ Delay:
4483 23:22:09.088512 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4484 23:22:09.091363 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4485 23:22:09.094358 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4486 23:22:09.097884 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4487 23:22:09.098299
4488 23:22:09.098627
4489 23:22:09.098931 ==
4490 23:22:09.100933 Dram Type= 6, Freq= 0, CH_1, rank 1
4491 23:22:09.107690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4492 23:22:09.108109 ==
4493 23:22:09.108443
4494 23:22:09.108799
4495 23:22:09.109109 TX Vref Scan disable
4496 23:22:09.111857 == TX Byte 0 ==
4497 23:22:09.114634 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4498 23:22:09.121249 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4499 23:22:09.121670 == TX Byte 1 ==
4500 23:22:09.124790 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4501 23:22:09.130980 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4502 23:22:09.131395 ==
4503 23:22:09.134830 Dram Type= 6, Freq= 0, CH_1, rank 1
4504 23:22:09.137637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4505 23:22:09.138055 ==
4506 23:22:09.138387
4507 23:22:09.138694
4508 23:22:09.140886 TX Vref Scan disable
4509 23:22:09.144127 == TX Byte 0 ==
4510 23:22:09.147631 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4511 23:22:09.152021 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4512 23:22:09.154324 == TX Byte 1 ==
4513 23:22:09.157902 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4514 23:22:09.160551 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4515 23:22:09.161013
4516 23:22:09.161629 [DATLAT]
4517 23:22:09.163948 Freq=600, CH1 RK1
4518 23:22:09.164542
4519 23:22:09.167912 DATLAT Default: 0x8
4520 23:22:09.168327 0, 0xFFFF, sum = 0
4521 23:22:09.170789 1, 0xFFFF, sum = 0
4522 23:22:09.171211 2, 0xFFFF, sum = 0
4523 23:22:09.174184 3, 0xFFFF, sum = 0
4524 23:22:09.174604 4, 0xFFFF, sum = 0
4525 23:22:09.177891 5, 0xFFFF, sum = 0
4526 23:22:09.178312 6, 0xFFFF, sum = 0
4527 23:22:09.181345 7, 0x0, sum = 1
4528 23:22:09.181761 8, 0x0, sum = 2
4529 23:22:09.183879 9, 0x0, sum = 3
4530 23:22:09.184298 10, 0x0, sum = 4
4531 23:22:09.184633 best_step = 8
4532 23:22:09.185014
4533 23:22:09.187633 ==
4534 23:22:09.190738 Dram Type= 6, Freq= 0, CH_1, rank 1
4535 23:22:09.194100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4536 23:22:09.194521 ==
4537 23:22:09.194855 RX Vref Scan: 0
4538 23:22:09.195212
4539 23:22:09.197061 RX Vref 0 -> 0, step: 1
4540 23:22:09.197480
4541 23:22:09.201052 RX Delay -195 -> 252, step: 8
4542 23:22:09.207461 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4543 23:22:09.210705 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4544 23:22:09.213933 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4545 23:22:09.217267 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4546 23:22:09.221062 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4547 23:22:09.227211 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4548 23:22:09.230546 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4549 23:22:09.234199 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4550 23:22:09.237057 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4551 23:22:09.243252 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4552 23:22:09.246584 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4553 23:22:09.249843 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4554 23:22:09.253149 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4555 23:22:09.260298 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4556 23:22:09.263584 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4557 23:22:09.266399 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4558 23:22:09.266826 ==
4559 23:22:09.270318 Dram Type= 6, Freq= 0, CH_1, rank 1
4560 23:22:09.273214 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4561 23:22:09.276503 ==
4562 23:22:09.276964 DQS Delay:
4563 23:22:09.277301 DQS0 = 0, DQS1 = 0
4564 23:22:09.280653 DQM Delay:
4565 23:22:09.281118 DQM0 = 36, DQM1 = 31
4566 23:22:09.283121 DQ Delay:
4567 23:22:09.283534 DQ0 =40, DQ1 =32, DQ2 =32, DQ3 =32
4568 23:22:09.286971 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4569 23:22:09.291924 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4570 23:22:09.293521 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4571 23:22:09.293934
4572 23:22:09.296488
4573 23:22:09.303300 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4574 23:22:09.306286 CH1 RK1: MR19=808, MR18=5B5B
4575 23:22:09.312949 CH1_RK1: MR19=0x808, MR18=0x5B5B, DQSOSC=392, MR23=63, INC=170, DEC=113
4576 23:22:09.316251 [RxdqsGatingPostProcess] freq 600
4577 23:22:09.319681 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4578 23:22:09.322716 Pre-setting of DQS Precalculation
4579 23:22:09.329351 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4580 23:22:09.335782 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4581 23:22:09.342744 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4582 23:22:09.343211
4583 23:22:09.343581
4584 23:22:09.345848 [Calibration Summary] 1200 Mbps
4585 23:22:09.346293 CH 0, Rank 0
4586 23:22:09.349629 SW Impedance : PASS
4587 23:22:09.352803 DUTY Scan : NO K
4588 23:22:09.353405 ZQ Calibration : PASS
4589 23:22:09.355632 Jitter Meter : NO K
4590 23:22:09.359247 CBT Training : PASS
4591 23:22:09.359661 Write leveling : PASS
4592 23:22:09.362288 RX DQS gating : PASS
4593 23:22:09.365465 RX DQ/DQS(RDDQC) : PASS
4594 23:22:09.365879 TX DQ/DQS : PASS
4595 23:22:09.369138 RX DATLAT : PASS
4596 23:22:09.369553 RX DQ/DQS(Engine): PASS
4597 23:22:09.373069 TX OE : NO K
4598 23:22:09.373482 All Pass.
4599 23:22:09.373812
4600 23:22:09.375374 CH 0, Rank 1
4601 23:22:09.375839 SW Impedance : PASS
4602 23:22:09.379320 DUTY Scan : NO K
4603 23:22:09.382158 ZQ Calibration : PASS
4604 23:22:09.382571 Jitter Meter : NO K
4605 23:22:09.385575 CBT Training : PASS
4606 23:22:09.389497 Write leveling : PASS
4607 23:22:09.389912 RX DQS gating : PASS
4608 23:22:09.392250 RX DQ/DQS(RDDQC) : PASS
4609 23:22:09.397878 TX DQ/DQS : PASS
4610 23:22:09.398297 RX DATLAT : PASS
4611 23:22:09.398987 RX DQ/DQS(Engine): PASS
4612 23:22:09.402151 TX OE : NO K
4613 23:22:09.402569 All Pass.
4614 23:22:09.402900
4615 23:22:09.403204 CH 1, Rank 0
4616 23:22:09.405783 SW Impedance : PASS
4617 23:22:09.408785 DUTY Scan : NO K
4618 23:22:09.409196 ZQ Calibration : PASS
4619 23:22:09.412206 Jitter Meter : NO K
4620 23:22:09.415540 CBT Training : PASS
4621 23:22:09.415951 Write leveling : PASS
4622 23:22:09.418577 RX DQS gating : PASS
4623 23:22:09.422064 RX DQ/DQS(RDDQC) : PASS
4624 23:22:09.422696 TX DQ/DQS : PASS
4625 23:22:09.424975 RX DATLAT : PASS
4626 23:22:09.425391 RX DQ/DQS(Engine): PASS
4627 23:22:09.428675 TX OE : NO K
4628 23:22:09.429133 All Pass.
4629 23:22:09.429465
4630 23:22:09.431839 CH 1, Rank 1
4631 23:22:09.435279 SW Impedance : PASS
4632 23:22:09.435689 DUTY Scan : NO K
4633 23:22:09.438353 ZQ Calibration : PASS
4634 23:22:09.438765 Jitter Meter : NO K
4635 23:22:09.441509 CBT Training : PASS
4636 23:22:09.445427 Write leveling : PASS
4637 23:22:09.445843 RX DQS gating : PASS
4638 23:22:09.448681 RX DQ/DQS(RDDQC) : PASS
4639 23:22:09.451392 TX DQ/DQS : PASS
4640 23:22:09.451811 RX DATLAT : PASS
4641 23:22:09.455024 RX DQ/DQS(Engine): PASS
4642 23:22:09.458209 TX OE : NO K
4643 23:22:09.458625 All Pass.
4644 23:22:09.458952
4645 23:22:09.461926 DramC Write-DBI off
4646 23:22:09.462351 PER_BANK_REFRESH: Hybrid Mode
4647 23:22:09.465763 TX_TRACKING: ON
4648 23:22:09.472587 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4649 23:22:09.477897 [FAST_K] Save calibration result to emmc
4650 23:22:09.481253 dramc_set_vcore_voltage set vcore to 662500
4651 23:22:09.481676 Read voltage for 933, 3
4652 23:22:09.484855 Vio18 = 0
4653 23:22:09.485279 Vcore = 662500
4654 23:22:09.485616 Vdram = 0
4655 23:22:09.488668 Vddq = 0
4656 23:22:09.489127 Vmddr = 0
4657 23:22:09.491667 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4658 23:22:09.497747 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4659 23:22:09.501224 MEM_TYPE=3, freq_sel=17
4660 23:22:09.505493 sv_algorithm_assistance_LP4_1600
4661 23:22:09.508181 ============ PULL DRAM RESETB DOWN ============
4662 23:22:09.511003 ========== PULL DRAM RESETB DOWN end =========
4663 23:22:09.517773 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4664 23:22:09.521352 ===================================
4665 23:22:09.521769 LPDDR4 DRAM CONFIGURATION
4666 23:22:09.524393 ===================================
4667 23:22:09.528089 EX_ROW_EN[0] = 0x0
4668 23:22:09.531264 EX_ROW_EN[1] = 0x0
4669 23:22:09.531680 LP4Y_EN = 0x0
4670 23:22:09.533929 WORK_FSP = 0x0
4671 23:22:09.534342 WL = 0x3
4672 23:22:09.537356 RL = 0x3
4673 23:22:09.537769 BL = 0x2
4674 23:22:09.540633 RPST = 0x0
4675 23:22:09.541079 RD_PRE = 0x0
4676 23:22:09.543722 WR_PRE = 0x1
4677 23:22:09.544139 WR_PST = 0x0
4678 23:22:09.547532 DBI_WR = 0x0
4679 23:22:09.547945 DBI_RD = 0x0
4680 23:22:09.550792 OTF = 0x1
4681 23:22:09.553969 ===================================
4682 23:22:09.557369 ===================================
4683 23:22:09.557787 ANA top config
4684 23:22:09.561272 ===================================
4685 23:22:09.563850 DLL_ASYNC_EN = 0
4686 23:22:09.567210 ALL_SLAVE_EN = 1
4687 23:22:09.567625 NEW_RANK_MODE = 1
4688 23:22:09.570937 DLL_IDLE_MODE = 1
4689 23:22:09.574219 LP45_APHY_COMB_EN = 1
4690 23:22:09.577023 TX_ODT_DIS = 1
4691 23:22:09.581171 NEW_8X_MODE = 1
4692 23:22:09.584193 ===================================
4693 23:22:09.587176 ===================================
4694 23:22:09.590381 data_rate = 1866
4695 23:22:09.590897 CKR = 1
4696 23:22:09.594202 DQ_P2S_RATIO = 8
4697 23:22:09.597438 ===================================
4698 23:22:09.600817 CA_P2S_RATIO = 8
4699 23:22:09.603616 DQ_CA_OPEN = 0
4700 23:22:09.606694 DQ_SEMI_OPEN = 0
4701 23:22:09.610532 CA_SEMI_OPEN = 0
4702 23:22:09.610962 CA_FULL_RATE = 0
4703 23:22:09.613403 DQ_CKDIV4_EN = 1
4704 23:22:09.617065 CA_CKDIV4_EN = 1
4705 23:22:09.620435 CA_PREDIV_EN = 0
4706 23:22:09.623878 PH8_DLY = 0
4707 23:22:09.626779 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4708 23:22:09.627195 DQ_AAMCK_DIV = 4
4709 23:22:09.630051 CA_AAMCK_DIV = 4
4710 23:22:09.633299 CA_ADMCK_DIV = 4
4711 23:22:09.637330 DQ_TRACK_CA_EN = 0
4712 23:22:09.639865 CA_PICK = 933
4713 23:22:09.643181 CA_MCKIO = 933
4714 23:22:09.646699 MCKIO_SEMI = 0
4715 23:22:09.647215 PLL_FREQ = 3732
4716 23:22:09.649982 DQ_UI_PI_RATIO = 32
4717 23:22:09.652842 CA_UI_PI_RATIO = 0
4718 23:22:09.656353 ===================================
4719 23:22:09.659588 ===================================
4720 23:22:09.663202 memory_type:LPDDR4
4721 23:22:09.663619 GP_NUM : 10
4722 23:22:09.665888 SRAM_EN : 1
4723 23:22:09.669601 MD32_EN : 0
4724 23:22:09.672789 ===================================
4725 23:22:09.673211 [ANA_INIT] >>>>>>>>>>>>>>
4726 23:22:09.676228 <<<<<< [CONFIGURE PHASE]: ANA_TX
4727 23:22:09.679375 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4728 23:22:09.683696 ===================================
4729 23:22:09.686595 data_rate = 1866,PCW = 0X8f00
4730 23:22:09.690818 ===================================
4731 23:22:09.692701 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4732 23:22:09.699603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4733 23:22:09.703366 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4734 23:22:09.709723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4735 23:22:09.712898 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4736 23:22:09.716389 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4737 23:22:09.716956 [ANA_INIT] flow start
4738 23:22:09.719527 [ANA_INIT] PLL >>>>>>>>
4739 23:22:09.723452 [ANA_INIT] PLL <<<<<<<<
4740 23:22:09.727140 [ANA_INIT] MIDPI >>>>>>>>
4741 23:22:09.727654 [ANA_INIT] MIDPI <<<<<<<<
4742 23:22:09.729425 [ANA_INIT] DLL >>>>>>>>
4743 23:22:09.732898 [ANA_INIT] flow end
4744 23:22:09.736391 ============ LP4 DIFF to SE enter ============
4745 23:22:09.740263 ============ LP4 DIFF to SE exit ============
4746 23:22:09.742839 [ANA_INIT] <<<<<<<<<<<<<
4747 23:22:09.746117 [Flow] Enable top DCM control >>>>>
4748 23:22:09.749230 [Flow] Enable top DCM control <<<<<
4749 23:22:09.752592 Enable DLL master slave shuffle
4750 23:22:09.756040 ==============================================================
4751 23:22:09.759381 Gating Mode config
4752 23:22:09.765791 ==============================================================
4753 23:22:09.766297 Config description:
4754 23:22:09.775252 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4755 23:22:09.782458 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4756 23:22:09.785121 SELPH_MODE 0: By rank 1: By Phase
4757 23:22:09.792198 ==============================================================
4758 23:22:09.795636 GAT_TRACK_EN = 1
4759 23:22:09.798658 RX_GATING_MODE = 2
4760 23:22:09.802241 RX_GATING_TRACK_MODE = 2
4761 23:22:09.805750 SELPH_MODE = 1
4762 23:22:09.808651 PICG_EARLY_EN = 1
4763 23:22:09.812210 VALID_LAT_VALUE = 1
4764 23:22:09.816162 ==============================================================
4765 23:22:09.818603 Enter into Gating configuration >>>>
4766 23:22:09.821985 Exit from Gating configuration <<<<
4767 23:22:09.825289 Enter into DVFS_PRE_config >>>>>
4768 23:22:09.839359 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4769 23:22:09.840027 Exit from DVFS_PRE_config <<<<<
4770 23:22:09.841855 Enter into PICG configuration >>>>
4771 23:22:09.845442 Exit from PICG configuration <<<<
4772 23:22:09.848521 [RX_INPUT] configuration >>>>>
4773 23:22:09.851661 [RX_INPUT] configuration <<<<<
4774 23:22:09.858310 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4775 23:22:09.861849 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4776 23:22:09.868105 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4777 23:22:09.874764 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4778 23:22:09.881833 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4779 23:22:09.890081 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4780 23:22:09.891921 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4781 23:22:09.894795 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4782 23:22:09.897786 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4783 23:22:09.904635 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4784 23:22:09.908311 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4785 23:22:09.911374 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4786 23:22:09.914737 ===================================
4787 23:22:09.917920 LPDDR4 DRAM CONFIGURATION
4788 23:22:09.921269 ===================================
4789 23:22:09.924202 EX_ROW_EN[0] = 0x0
4790 23:22:09.924618 EX_ROW_EN[1] = 0x0
4791 23:22:09.927971 LP4Y_EN = 0x0
4792 23:22:09.928483 WORK_FSP = 0x0
4793 23:22:09.931796 WL = 0x3
4794 23:22:09.932208 RL = 0x3
4795 23:22:09.934839 BL = 0x2
4796 23:22:09.935255 RPST = 0x0
4797 23:22:09.937766 RD_PRE = 0x0
4798 23:22:09.938180 WR_PRE = 0x1
4799 23:22:09.941030 WR_PST = 0x0
4800 23:22:09.941442 DBI_WR = 0x0
4801 23:22:09.944455 DBI_RD = 0x0
4802 23:22:09.944908 OTF = 0x1
4803 23:22:09.947598 ===================================
4804 23:22:09.954937 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4805 23:22:09.957934 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4806 23:22:09.961784 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4807 23:22:09.964625 ===================================
4808 23:22:09.968125 LPDDR4 DRAM CONFIGURATION
4809 23:22:09.971836 ===================================
4810 23:22:09.972249 EX_ROW_EN[0] = 0x10
4811 23:22:09.975577 EX_ROW_EN[1] = 0x0
4812 23:22:09.977567 LP4Y_EN = 0x0
4813 23:22:09.977985 WORK_FSP = 0x0
4814 23:22:09.980995 WL = 0x3
4815 23:22:09.981414 RL = 0x3
4816 23:22:09.984282 BL = 0x2
4817 23:22:09.984773 RPST = 0x0
4818 23:22:09.987598 RD_PRE = 0x0
4819 23:22:09.988159 WR_PRE = 0x1
4820 23:22:09.991305 WR_PST = 0x0
4821 23:22:09.991873 DBI_WR = 0x0
4822 23:22:09.994518 DBI_RD = 0x0
4823 23:22:09.995085 OTF = 0x1
4824 23:22:09.997970 ===================================
4825 23:22:10.004621 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4826 23:22:10.008507 nWR fixed to 30
4827 23:22:10.012035 [ModeRegInit_LP4] CH0 RK0
4828 23:22:10.012492 [ModeRegInit_LP4] CH0 RK1
4829 23:22:10.015118 [ModeRegInit_LP4] CH1 RK0
4830 23:22:10.018524 [ModeRegInit_LP4] CH1 RK1
4831 23:22:10.019076 match AC timing 8
4832 23:22:10.025397 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4833 23:22:10.028579 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4834 23:22:10.031775 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4835 23:22:10.038694 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4836 23:22:10.041933 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4837 23:22:10.042394 ==
4838 23:22:10.045023 Dram Type= 6, Freq= 0, CH_0, rank 0
4839 23:22:10.048531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4840 23:22:10.049045 ==
4841 23:22:10.055429 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4842 23:22:10.062555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4843 23:22:10.065169 [CA 0] Center 38 (8~69) winsize 62
4844 23:22:10.068004 [CA 1] Center 38 (8~69) winsize 62
4845 23:22:10.071423 [CA 2] Center 36 (6~67) winsize 62
4846 23:22:10.074697 [CA 3] Center 36 (6~66) winsize 61
4847 23:22:10.078052 [CA 4] Center 34 (4~65) winsize 62
4848 23:22:10.082163 [CA 5] Center 34 (4~65) winsize 62
4849 23:22:10.082722
4850 23:22:10.085249 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4851 23:22:10.085705
4852 23:22:10.088392 [CATrainingPosCal] consider 1 rank data
4853 23:22:10.091422 u2DelayCellTimex100 = 270/100 ps
4854 23:22:10.094610 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4855 23:22:10.097853 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4856 23:22:10.101449 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4857 23:22:10.105596 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4858 23:22:10.112365 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4859 23:22:10.114570 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4860 23:22:10.115128
4861 23:22:10.117701 CA PerBit enable=1, Macro0, CA PI delay=34
4862 23:22:10.118177
4863 23:22:10.121127 [CBTSetCACLKResult] CA Dly = 34
4864 23:22:10.121586 CS Dly: 7 (0~38)
4865 23:22:10.121947 ==
4866 23:22:10.123932 Dram Type= 6, Freq= 0, CH_0, rank 1
4867 23:22:10.131031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4868 23:22:10.131499 ==
4869 23:22:10.134104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4870 23:22:10.141342 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4871 23:22:10.144132 [CA 0] Center 38 (8~69) winsize 62
4872 23:22:10.147925 [CA 1] Center 38 (8~69) winsize 62
4873 23:22:10.150512 [CA 2] Center 36 (6~67) winsize 62
4874 23:22:10.153970 [CA 3] Center 35 (5~66) winsize 62
4875 23:22:10.158732 [CA 4] Center 34 (4~65) winsize 62
4876 23:22:10.160550 [CA 5] Center 34 (4~65) winsize 62
4877 23:22:10.161086
4878 23:22:10.164598 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4879 23:22:10.165130
4880 23:22:10.168123 [CATrainingPosCal] consider 2 rank data
4881 23:22:10.170952 u2DelayCellTimex100 = 270/100 ps
4882 23:22:10.174714 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4883 23:22:10.177785 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4884 23:22:10.181253 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4885 23:22:10.187792 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4886 23:22:10.191515 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4887 23:22:10.193785 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4888 23:22:10.194246
4889 23:22:10.197239 CA PerBit enable=1, Macro0, CA PI delay=34
4890 23:22:10.197700
4891 23:22:10.200882 [CBTSetCACLKResult] CA Dly = 34
4892 23:22:10.201435 CS Dly: 7 (0~39)
4893 23:22:10.201807
4894 23:22:10.204130 ----->DramcWriteLeveling(PI) begin...
4895 23:22:10.208235 ==
4896 23:22:10.211076 Dram Type= 6, Freq= 0, CH_0, rank 0
4897 23:22:10.214461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4898 23:22:10.215022 ==
4899 23:22:10.217544 Write leveling (Byte 0): 32 => 32
4900 23:22:10.220339 Write leveling (Byte 1): 26 => 26
4901 23:22:10.223972 DramcWriteLeveling(PI) end<-----
4902 23:22:10.224443
4903 23:22:10.225120 ==
4904 23:22:10.227123 Dram Type= 6, Freq= 0, CH_0, rank 0
4905 23:22:10.230896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4906 23:22:10.231363 ==
4907 23:22:10.233601 [Gating] SW mode calibration
4908 23:22:10.240241 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4909 23:22:10.246859 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4910 23:22:10.250354 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4911 23:22:10.253613 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4912 23:22:10.259896 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4913 23:22:10.263970 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4914 23:22:10.267176 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4915 23:22:10.273362 0 10 20 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
4916 23:22:10.276518 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4917 23:22:10.280567 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4918 23:22:10.287051 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4919 23:22:10.289852 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4920 23:22:10.293178 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4921 23:22:10.300273 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4922 23:22:10.303949 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4923 23:22:10.306849 0 11 20 | B1->B0 | 2626 2d2d | 0 1 | (0 0) (0 0)
4924 23:22:10.312850 0 11 24 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4925 23:22:10.316611 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4926 23:22:10.319800 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4927 23:22:10.325860 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4928 23:22:10.329399 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4929 23:22:10.332336 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4930 23:22:10.340002 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4931 23:22:10.342918 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4932 23:22:10.346841 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 23:22:10.352449 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 23:22:10.356460 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 23:22:10.358726 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 23:22:10.365532 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 23:22:10.368658 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 23:22:10.372298 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 23:22:10.378763 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 23:22:10.382104 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 23:22:10.385439 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 23:22:10.391803 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 23:22:10.395507 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 23:22:10.399263 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 23:22:10.405735 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 23:22:10.407783 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 23:22:10.411416 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4948 23:22:10.417901 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4949 23:22:10.417983 Total UI for P1: 0, mck2ui 16
4950 23:22:10.421949 best dqsien dly found for B0: ( 0, 14, 20)
4951 23:22:10.424971 Total UI for P1: 0, mck2ui 16
4952 23:22:10.428643 best dqsien dly found for B1: ( 0, 14, 20)
4953 23:22:10.434243 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4954 23:22:10.438025 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4955 23:22:10.438106
4956 23:22:10.441032 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4957 23:22:10.444635 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4958 23:22:10.447364 [Gating] SW calibration Done
4959 23:22:10.447471 ==
4960 23:22:10.451216 Dram Type= 6, Freq= 0, CH_0, rank 0
4961 23:22:10.454496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4962 23:22:10.454578 ==
4963 23:22:10.458335 RX Vref Scan: 0
4964 23:22:10.458417
4965 23:22:10.458481 RX Vref 0 -> 0, step: 1
4966 23:22:10.458541
4967 23:22:10.460883 RX Delay -80 -> 252, step: 8
4968 23:22:10.464410 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
4969 23:22:10.470666 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4970 23:22:10.474645 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4971 23:22:10.477946 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4972 23:22:10.480696 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4973 23:22:10.483910 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
4974 23:22:10.487721 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
4975 23:22:10.494051 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4976 23:22:10.497249 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4977 23:22:10.500563 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4978 23:22:10.504108 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4979 23:22:10.507145 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4980 23:22:10.514044 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
4981 23:22:10.516904 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
4982 23:22:10.520453 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
4983 23:22:10.523538 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4984 23:22:10.523620 ==
4985 23:22:10.527066 Dram Type= 6, Freq= 0, CH_0, rank 0
4986 23:22:10.534076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4987 23:22:10.534160 ==
4988 23:22:10.534225 DQS Delay:
4989 23:22:10.534286 DQS0 = 0, DQS1 = 0
4990 23:22:10.536902 DQM Delay:
4991 23:22:10.536984 DQM0 = 96, DQM1 = 84
4992 23:22:10.540479 DQ Delay:
4993 23:22:10.543609 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
4994 23:22:10.547046 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
4995 23:22:10.550064 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
4996 23:22:10.553171 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
4997 23:22:10.553253
4998 23:22:10.553318
4999 23:22:10.553382 ==
5000 23:22:10.556460 Dram Type= 6, Freq= 0, CH_0, rank 0
5001 23:22:10.560918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5002 23:22:10.560999 ==
5003 23:22:10.561065
5004 23:22:10.561125
5005 23:22:10.563489 TX Vref Scan disable
5006 23:22:10.563571 == TX Byte 0 ==
5007 23:22:10.569997 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5008 23:22:10.573433 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5009 23:22:10.573516 == TX Byte 1 ==
5010 23:22:10.579510 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5011 23:22:10.583376 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5012 23:22:10.583508 ==
5013 23:22:10.586001 Dram Type= 6, Freq= 0, CH_0, rank 0
5014 23:22:10.589734 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5015 23:22:10.589853 ==
5016 23:22:10.593182
5017 23:22:10.593262
5018 23:22:10.593327 TX Vref Scan disable
5019 23:22:10.596641 == TX Byte 0 ==
5020 23:22:10.599541 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5021 23:22:10.606429 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5022 23:22:10.606513 == TX Byte 1 ==
5023 23:22:10.609741 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5024 23:22:10.616029 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5025 23:22:10.616109
5026 23:22:10.616173 [DATLAT]
5027 23:22:10.616233 Freq=933, CH0 RK0
5028 23:22:10.616290
5029 23:22:10.619329 DATLAT Default: 0xd
5030 23:22:10.619410 0, 0xFFFF, sum = 0
5031 23:22:10.622805 1, 0xFFFF, sum = 0
5032 23:22:10.625928 2, 0xFFFF, sum = 0
5033 23:22:10.626010 3, 0xFFFF, sum = 0
5034 23:22:10.629196 4, 0xFFFF, sum = 0
5035 23:22:10.629278 5, 0xFFFF, sum = 0
5036 23:22:10.633032 6, 0xFFFF, sum = 0
5037 23:22:10.633114 7, 0xFFFF, sum = 0
5038 23:22:10.636234 8, 0xFFFF, sum = 0
5039 23:22:10.636316 9, 0xFFFF, sum = 0
5040 23:22:10.639336 10, 0x0, sum = 1
5041 23:22:10.639417 11, 0x0, sum = 2
5042 23:22:10.642586 12, 0x0, sum = 3
5043 23:22:10.642668 13, 0x0, sum = 4
5044 23:22:10.642732 best_step = 11
5045 23:22:10.645580
5046 23:22:10.645660 ==
5047 23:22:10.649182 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 23:22:10.652346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5049 23:22:10.652428 ==
5050 23:22:10.652492 RX Vref Scan: 1
5051 23:22:10.652552
5052 23:22:10.655805 RX Vref 0 -> 0, step: 1
5053 23:22:10.655886
5054 23:22:10.659498 RX Delay -69 -> 252, step: 4
5055 23:22:10.659579
5056 23:22:10.662163 Set Vref, RX VrefLevel [Byte0]: 52
5057 23:22:10.665249 [Byte1]: 49
5058 23:22:10.669076
5059 23:22:10.669156 Final RX Vref Byte 0 = 52 to rank0
5060 23:22:10.672421 Final RX Vref Byte 1 = 49 to rank0
5061 23:22:10.675551 Final RX Vref Byte 0 = 52 to rank1
5062 23:22:10.679239 Final RX Vref Byte 1 = 49 to rank1==
5063 23:22:10.682255 Dram Type= 6, Freq= 0, CH_0, rank 0
5064 23:22:10.688554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5065 23:22:10.688636 ==
5066 23:22:10.688700 DQS Delay:
5067 23:22:10.692054 DQS0 = 0, DQS1 = 0
5068 23:22:10.692134 DQM Delay:
5069 23:22:10.692198 DQM0 = 96, DQM1 = 86
5070 23:22:10.695628 DQ Delay:
5071 23:22:10.698962 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5072 23:22:10.702011 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =102
5073 23:22:10.705239 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =78
5074 23:22:10.709122 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5075 23:22:10.709202
5076 23:22:10.709265
5077 23:22:10.714896 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5078 23:22:10.718561 CH0 RK0: MR19=505, MR18=1E1E
5079 23:22:10.724971 CH0_RK0: MR19=0x505, MR18=0x1E1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5080 23:22:10.725052
5081 23:22:10.728355 ----->DramcWriteLeveling(PI) begin...
5082 23:22:10.728436 ==
5083 23:22:10.731498 Dram Type= 6, Freq= 0, CH_0, rank 1
5084 23:22:10.734852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5085 23:22:10.734932 ==
5086 23:22:10.738407 Write leveling (Byte 0): 28 => 28
5087 23:22:10.741435 Write leveling (Byte 1): 27 => 27
5088 23:22:10.745322 DramcWriteLeveling(PI) end<-----
5089 23:22:10.745402
5090 23:22:10.745465 ==
5091 23:22:10.748102 Dram Type= 6, Freq= 0, CH_0, rank 1
5092 23:22:10.751449 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5093 23:22:10.755183 ==
5094 23:22:10.755264 [Gating] SW mode calibration
5095 23:22:10.761597 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5096 23:22:10.769627 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5097 23:22:10.771675 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 23:22:10.778362 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 23:22:10.781716 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 23:22:10.784652 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 23:22:10.791704 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5102 23:22:10.794688 0 10 20 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (0 0)
5103 23:22:10.797848 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5104 23:22:10.805096 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 23:22:10.808198 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 23:22:10.811226 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 23:22:10.818508 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 23:22:10.821450 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 23:22:10.824961 0 11 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5110 23:22:10.831538 0 11 20 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (1 1)
5111 23:22:10.834956 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5112 23:22:10.838154 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 23:22:10.844682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 23:22:10.848075 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 23:22:10.851730 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 23:22:10.858633 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 23:22:10.861350 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 23:22:10.864596 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5119 23:22:10.871106 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 23:22:10.874428 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 23:22:10.877506 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 23:22:10.884936 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 23:22:10.888141 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 23:22:10.891474 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 23:22:10.897371 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 23:22:10.900913 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 23:22:10.903713 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 23:22:10.911692 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 23:22:10.915047 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 23:22:10.917617 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 23:22:10.923869 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 23:22:10.927427 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 23:22:10.931023 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 23:22:10.937523 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5135 23:22:10.940602 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 23:22:10.943976 Total UI for P1: 0, mck2ui 16
5137 23:22:10.947479 best dqsien dly found for B0: ( 0, 14, 20)
5138 23:22:10.950364 Total UI for P1: 0, mck2ui 16
5139 23:22:10.953650 best dqsien dly found for B1: ( 0, 14, 20)
5140 23:22:10.957205 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5141 23:22:10.960604 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5142 23:22:10.961101
5143 23:22:10.963511 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5144 23:22:10.966962 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5145 23:22:10.970236 [Gating] SW calibration Done
5146 23:22:10.970702 ==
5147 23:22:10.973406 Dram Type= 6, Freq= 0, CH_0, rank 1
5148 23:22:10.976643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5149 23:22:10.980461 ==
5150 23:22:10.980968 RX Vref Scan: 0
5151 23:22:10.981338
5152 23:22:10.983747 RX Vref 0 -> 0, step: 1
5153 23:22:10.984214
5154 23:22:10.984582 RX Delay -80 -> 252, step: 8
5155 23:22:10.990382 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5156 23:22:10.993414 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5157 23:22:10.997132 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5158 23:22:11.001394 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5159 23:22:11.003900 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5160 23:22:11.007329 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5161 23:22:11.013605 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5162 23:22:11.017182 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5163 23:22:11.020139 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5164 23:22:11.023242 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5165 23:22:11.026708 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5166 23:22:11.033134 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5167 23:22:11.037020 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5168 23:22:11.040153 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5169 23:22:11.043261 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5170 23:22:11.046343 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5171 23:22:11.050209 ==
5172 23:22:11.053458 Dram Type= 6, Freq= 0, CH_0, rank 1
5173 23:22:11.056296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5174 23:22:11.056815 ==
5175 23:22:11.057199 DQS Delay:
5176 23:22:11.059752 DQS0 = 0, DQS1 = 0
5177 23:22:11.060215 DQM Delay:
5178 23:22:11.063102 DQM0 = 95, DQM1 = 83
5179 23:22:11.063566 DQ Delay:
5180 23:22:11.066352 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87
5181 23:22:11.069751 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5182 23:22:11.073048 DQ8 =71, DQ9 =71, DQ10 =83, DQ11 =79
5183 23:22:11.076106 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5184 23:22:11.076538
5185 23:22:11.076923
5186 23:22:11.077237 ==
5187 23:22:11.079551 Dram Type= 6, Freq= 0, CH_0, rank 1
5188 23:22:11.082862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5189 23:22:11.083291 ==
5190 23:22:11.083642
5191 23:22:11.083948
5192 23:22:11.086070 TX Vref Scan disable
5193 23:22:11.089583 == TX Byte 0 ==
5194 23:22:11.093065 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5195 23:22:11.096388 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5196 23:22:11.100865 == TX Byte 1 ==
5197 23:22:11.104202 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5198 23:22:11.105918 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5199 23:22:11.106340 ==
5200 23:22:11.109109 Dram Type= 6, Freq= 0, CH_0, rank 1
5201 23:22:11.115848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5202 23:22:11.116649 ==
5203 23:22:11.117143
5204 23:22:11.117470
5205 23:22:11.117776 TX Vref Scan disable
5206 23:22:11.120410 == TX Byte 0 ==
5207 23:22:11.125351 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5208 23:22:11.126756 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5209 23:22:11.130159 == TX Byte 1 ==
5210 23:22:11.133228 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5211 23:22:11.136952 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5212 23:22:11.140192
5213 23:22:11.140812 [DATLAT]
5214 23:22:11.141197 Freq=933, CH0 RK1
5215 23:22:11.141546
5216 23:22:11.143129 DATLAT Default: 0xb
5217 23:22:11.143592 0, 0xFFFF, sum = 0
5218 23:22:11.146617 1, 0xFFFF, sum = 0
5219 23:22:11.147196 2, 0xFFFF, sum = 0
5220 23:22:11.150028 3, 0xFFFF, sum = 0
5221 23:22:11.152815 4, 0xFFFF, sum = 0
5222 23:22:11.153540 5, 0xFFFF, sum = 0
5223 23:22:11.156766 6, 0xFFFF, sum = 0
5224 23:22:11.157244 7, 0xFFFF, sum = 0
5225 23:22:11.160357 8, 0xFFFF, sum = 0
5226 23:22:11.161034 9, 0xFFFF, sum = 0
5227 23:22:11.163722 10, 0x0, sum = 1
5228 23:22:11.164194 11, 0x0, sum = 2
5229 23:22:11.167368 12, 0x0, sum = 3
5230 23:22:11.167840 13, 0x0, sum = 4
5231 23:22:11.168216 best_step = 11
5232 23:22:11.168556
5233 23:22:11.169719 ==
5234 23:22:11.170198 Dram Type= 6, Freq= 0, CH_0, rank 1
5235 23:22:11.176559 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5236 23:22:11.177076 ==
5237 23:22:11.177563 RX Vref Scan: 0
5238 23:22:11.178023
5239 23:22:11.180194 RX Vref 0 -> 0, step: 1
5240 23:22:11.180675
5241 23:22:11.184100 RX Delay -69 -> 252, step: 4
5242 23:22:11.186681 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5243 23:22:11.192993 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5244 23:22:11.196768 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5245 23:22:11.200608 iDelay=203, Bit 3, Center 90 (-1 ~ 182) 184
5246 23:22:11.202854 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5247 23:22:11.207831 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5248 23:22:11.210318 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5249 23:22:11.216486 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5250 23:22:11.219479 iDelay=203, Bit 8, Center 74 (-13 ~ 162) 176
5251 23:22:11.222542 iDelay=203, Bit 9, Center 70 (-21 ~ 162) 184
5252 23:22:11.225958 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5253 23:22:11.229254 iDelay=203, Bit 11, Center 76 (-13 ~ 166) 180
5254 23:22:11.235957 iDelay=203, Bit 12, Center 92 (3 ~ 182) 180
5255 23:22:11.239963 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5256 23:22:11.242852 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5257 23:22:11.245994 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5258 23:22:11.246464 ==
5259 23:22:11.249806 Dram Type= 6, Freq= 0, CH_0, rank 1
5260 23:22:11.252505 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5261 23:22:11.256058 ==
5262 23:22:11.256787 DQS Delay:
5263 23:22:11.257240 DQS0 = 0, DQS1 = 0
5264 23:22:11.259024 DQM Delay:
5265 23:22:11.259614 DQM0 = 97, DQM1 = 85
5266 23:22:11.262352 DQ Delay:
5267 23:22:11.265911 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =90
5268 23:22:11.269634 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =108
5269 23:22:11.273489 DQ8 =74, DQ9 =70, DQ10 =88, DQ11 =76
5270 23:22:11.276503 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =96
5271 23:22:11.277080
5272 23:22:11.277426
5273 23:22:11.282535 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5274 23:22:11.286305 CH0 RK1: MR19=505, MR18=2F2F
5275 23:22:11.292296 CH0_RK1: MR19=0x505, MR18=0x2F2F, DQSOSC=407, MR23=63, INC=65, DEC=43
5276 23:22:11.295666 [RxdqsGatingPostProcess] freq 933
5277 23:22:11.299027 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5278 23:22:11.302327 Pre-setting of DQS Precalculation
5279 23:22:11.309180 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5280 23:22:11.309742 ==
5281 23:22:11.312453 Dram Type= 6, Freq= 0, CH_1, rank 0
5282 23:22:11.315409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5283 23:22:11.315972 ==
5284 23:22:11.321964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5285 23:22:11.328540 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5286 23:22:11.331764 [CA 0] Center 37 (6~68) winsize 63
5287 23:22:11.335350 [CA 1] Center 37 (6~68) winsize 63
5288 23:22:11.338676 [CA 2] Center 34 (4~65) winsize 62
5289 23:22:11.342404 [CA 3] Center 34 (4~65) winsize 62
5290 23:22:11.345129 [CA 4] Center 33 (3~64) winsize 62
5291 23:22:11.348528 [CA 5] Center 33 (3~64) winsize 62
5292 23:22:11.349117
5293 23:22:11.351583 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5294 23:22:11.352161
5295 23:22:11.354965 [CATrainingPosCal] consider 1 rank data
5296 23:22:11.358813 u2DelayCellTimex100 = 270/100 ps
5297 23:22:11.361650 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5298 23:22:11.364985 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5299 23:22:11.368869 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5300 23:22:11.371956 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5301 23:22:11.374661 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5302 23:22:11.378414 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5303 23:22:11.378995
5304 23:22:11.385124 CA PerBit enable=1, Macro0, CA PI delay=33
5305 23:22:11.385577
5306 23:22:11.385942 [CBTSetCACLKResult] CA Dly = 33
5307 23:22:11.388269 CS Dly: 5 (0~36)
5308 23:22:11.388870 ==
5309 23:22:11.391496 Dram Type= 6, Freq= 0, CH_1, rank 1
5310 23:22:11.394854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5311 23:22:11.395423 ==
5312 23:22:11.401458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5313 23:22:11.408125 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5314 23:22:11.411697 [CA 0] Center 37 (6~68) winsize 63
5315 23:22:11.414941 [CA 1] Center 37 (6~68) winsize 63
5316 23:22:11.417855 [CA 2] Center 34 (4~65) winsize 62
5317 23:22:11.421396 [CA 3] Center 34 (4~65) winsize 62
5318 23:22:11.425077 [CA 4] Center 33 (2~64) winsize 63
5319 23:22:11.427810 [CA 5] Center 33 (2~64) winsize 63
5320 23:22:11.428226
5321 23:22:11.431296 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5322 23:22:11.431814
5323 23:22:11.434320 [CATrainingPosCal] consider 2 rank data
5324 23:22:11.438046 u2DelayCellTimex100 = 270/100 ps
5325 23:22:11.441206 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5326 23:22:11.444948 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5327 23:22:11.447820 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5328 23:22:11.450885 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5329 23:22:11.454255 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5330 23:22:11.457576 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5331 23:22:11.460884
5332 23:22:11.464331 CA PerBit enable=1, Macro0, CA PI delay=33
5333 23:22:11.464945
5334 23:22:11.468302 [CBTSetCACLKResult] CA Dly = 33
5335 23:22:11.468928 CS Dly: 5 (0~37)
5336 23:22:11.469438
5337 23:22:11.470539 ----->DramcWriteLeveling(PI) begin...
5338 23:22:11.471073 ==
5339 23:22:11.473843 Dram Type= 6, Freq= 0, CH_1, rank 0
5340 23:22:11.477393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5341 23:22:11.480608 ==
5342 23:22:11.484099 Write leveling (Byte 0): 23 => 23
5343 23:22:11.484648 Write leveling (Byte 1): 23 => 23
5344 23:22:11.487331 DramcWriteLeveling(PI) end<-----
5345 23:22:11.487915
5346 23:22:11.488373 ==
5347 23:22:11.490976 Dram Type= 6, Freq= 0, CH_1, rank 0
5348 23:22:11.496943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5349 23:22:11.497424 ==
5350 23:22:11.500279 [Gating] SW mode calibration
5351 23:22:11.507692 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5352 23:22:11.510789 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5353 23:22:11.517556 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 23:22:11.519925 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 23:22:11.523309 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 23:22:11.531090 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 23:22:11.533413 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
5358 23:22:11.537035 0 10 20 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
5359 23:22:11.543282 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5360 23:22:11.547009 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 23:22:11.550211 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 23:22:11.557451 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 23:22:11.561138 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 23:22:11.563543 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 23:22:11.570258 0 11 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5366 23:22:11.573741 0 11 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
5367 23:22:11.576579 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5368 23:22:11.583329 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 23:22:11.586833 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 23:22:11.589928 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 23:22:11.593033 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 23:22:11.600099 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 23:22:11.603149 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5374 23:22:11.606561 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5375 23:22:11.613076 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:22:11.616196 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:22:11.619820 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:22:11.626297 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:22:11.630617 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:22:11.633088 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:22:11.640758 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:22:11.642997 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:22:11.646750 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:22:11.653186 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 23:22:11.655928 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:22:11.659426 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:22:11.666723 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 23:22:11.669247 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 23:22:11.673197 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5390 23:22:11.680423 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5391 23:22:11.682670 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 23:22:11.686613 Total UI for P1: 0, mck2ui 16
5393 23:22:11.689490 best dqsien dly found for B0: ( 0, 14, 18)
5394 23:22:11.693395 Total UI for P1: 0, mck2ui 16
5395 23:22:11.695907 best dqsien dly found for B1: ( 0, 14, 18)
5396 23:22:11.699651 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5397 23:22:11.702252 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5398 23:22:11.702709
5399 23:22:11.706422 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5400 23:22:11.712270 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5401 23:22:11.712772 [Gating] SW calibration Done
5402 23:22:11.713170 ==
5403 23:22:11.715402 Dram Type= 6, Freq= 0, CH_1, rank 0
5404 23:22:11.722504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5405 23:22:11.722964 ==
5406 23:22:11.723342 RX Vref Scan: 0
5407 23:22:11.723870
5408 23:22:11.726028 RX Vref 0 -> 0, step: 1
5409 23:22:11.726588
5410 23:22:11.728663 RX Delay -80 -> 252, step: 8
5411 23:22:11.732385 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5412 23:22:11.735699 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5413 23:22:11.738820 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5414 23:22:11.742052 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5415 23:22:11.749029 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5416 23:22:11.752142 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5417 23:22:11.755170 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5418 23:22:11.758687 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5419 23:22:11.761768 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5420 23:22:11.768468 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5421 23:22:11.771692 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5422 23:22:11.775350 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5423 23:22:11.778254 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5424 23:22:11.781789 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5425 23:22:11.788216 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5426 23:22:11.791624 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5427 23:22:11.792083 ==
5428 23:22:11.794779 Dram Type= 6, Freq= 0, CH_1, rank 0
5429 23:22:11.798594 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5430 23:22:11.799053 ==
5431 23:22:11.799418 DQS Delay:
5432 23:22:11.801645 DQS0 = 0, DQS1 = 0
5433 23:22:11.802103 DQM Delay:
5434 23:22:11.804572 DQM0 = 93, DQM1 = 87
5435 23:22:11.805061 DQ Delay:
5436 23:22:11.808149 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5437 23:22:11.811139 DQ4 =91, DQ5 =103, DQ6 =99, DQ7 =91
5438 23:22:11.814322 DQ8 =71, DQ9 =79, DQ10 =87, DQ11 =79
5439 23:22:11.817868 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5440 23:22:11.818281
5441 23:22:11.818610
5442 23:22:11.818917 ==
5443 23:22:11.821022 Dram Type= 6, Freq= 0, CH_1, rank 0
5444 23:22:11.828031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5445 23:22:11.828785 ==
5446 23:22:11.829173
5447 23:22:11.829515
5448 23:22:11.829897 TX Vref Scan disable
5449 23:22:11.831085 == TX Byte 0 ==
5450 23:22:11.834519 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5451 23:22:11.841340 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5452 23:22:11.841892 == TX Byte 1 ==
5453 23:22:11.844359 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5454 23:22:11.850970 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5455 23:22:11.851527 ==
5456 23:22:11.854288 Dram Type= 6, Freq= 0, CH_1, rank 0
5457 23:22:11.857452 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5458 23:22:11.857981 ==
5459 23:22:11.858357
5460 23:22:11.858691
5461 23:22:11.860570 TX Vref Scan disable
5462 23:22:11.861063 == TX Byte 0 ==
5463 23:22:11.867991 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5464 23:22:11.870505 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5465 23:22:11.874397 == TX Byte 1 ==
5466 23:22:11.877527 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5467 23:22:11.880887 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5468 23:22:11.881358
5469 23:22:11.881731 [DATLAT]
5470 23:22:11.884052 Freq=933, CH1 RK0
5471 23:22:11.884670
5472 23:22:11.885100 DATLAT Default: 0xd
5473 23:22:11.887476 0, 0xFFFF, sum = 0
5474 23:22:11.890730 1, 0xFFFF, sum = 0
5475 23:22:11.891204 2, 0xFFFF, sum = 0
5476 23:22:11.895771 3, 0xFFFF, sum = 0
5477 23:22:11.896357 4, 0xFFFF, sum = 0
5478 23:22:11.897127 5, 0xFFFF, sum = 0
5479 23:22:11.897524 6, 0xFFFF, sum = 0
5480 23:22:11.900537 7, 0xFFFF, sum = 0
5481 23:22:11.901158 8, 0xFFFF, sum = 0
5482 23:22:11.904260 9, 0xFFFF, sum = 0
5483 23:22:11.904766 10, 0x0, sum = 1
5484 23:22:11.907212 11, 0x0, sum = 2
5485 23:22:11.907687 12, 0x0, sum = 3
5486 23:22:11.910076 13, 0x0, sum = 4
5487 23:22:11.910547 best_step = 11
5488 23:22:11.910913
5489 23:22:11.911255 ==
5490 23:22:11.913680 Dram Type= 6, Freq= 0, CH_1, rank 0
5491 23:22:11.916972 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5492 23:22:11.917440 ==
5493 23:22:11.920012 RX Vref Scan: 1
5494 23:22:11.920477
5495 23:22:11.923180 RX Vref 0 -> 0, step: 1
5496 23:22:11.923262
5497 23:22:11.923327 RX Delay -69 -> 252, step: 4
5498 23:22:11.926688
5499 23:22:11.926769 Set Vref, RX VrefLevel [Byte0]: 52
5500 23:22:11.929662 [Byte1]: 49
5501 23:22:11.934436
5502 23:22:11.934530 Final RX Vref Byte 0 = 52 to rank0
5503 23:22:11.938427 Final RX Vref Byte 1 = 49 to rank0
5504 23:22:11.941467 Final RX Vref Byte 0 = 52 to rank1
5505 23:22:11.944804 Final RX Vref Byte 1 = 49 to rank1==
5506 23:22:11.947751 Dram Type= 6, Freq= 0, CH_1, rank 0
5507 23:22:11.954874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5508 23:22:11.955027 ==
5509 23:22:11.955136 DQS Delay:
5510 23:22:11.958560 DQS0 = 0, DQS1 = 0
5511 23:22:11.959026 DQM Delay:
5512 23:22:11.959423 DQM0 = 94, DQM1 = 87
5513 23:22:11.961302 DQ Delay:
5514 23:22:11.964513 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90
5515 23:22:11.969081 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5516 23:22:11.972066 DQ8 =70, DQ9 =78, DQ10 =88, DQ11 =80
5517 23:22:11.974904 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5518 23:22:11.975370
5519 23:22:11.975736
5520 23:22:11.981694 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5521 23:22:11.985288 CH1 RK0: MR19=505, MR18=3939
5522 23:22:11.991079 CH1_RK0: MR19=0x505, MR18=0x3939, DQSOSC=404, MR23=63, INC=66, DEC=44
5523 23:22:11.991504
5524 23:22:11.994622 ----->DramcWriteLeveling(PI) begin...
5525 23:22:11.995049 ==
5526 23:22:11.999588 Dram Type= 6, Freq= 0, CH_1, rank 1
5527 23:22:12.001091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5528 23:22:12.001584 ==
5529 23:22:12.004785 Write leveling (Byte 0): 22 => 22
5530 23:22:12.007896 Write leveling (Byte 1): 22 => 22
5531 23:22:12.011561 DramcWriteLeveling(PI) end<-----
5532 23:22:12.012115
5533 23:22:12.012489 ==
5534 23:22:12.014339 Dram Type= 6, Freq= 0, CH_1, rank 1
5535 23:22:12.017807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5536 23:22:12.021190 ==
5537 23:22:12.021657 [Gating] SW mode calibration
5538 23:22:12.030904 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5539 23:22:12.034569 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5540 23:22:12.037572 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 23:22:12.044163 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 23:22:12.047346 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 23:22:12.050380 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5544 23:22:12.057413 0 10 16 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (0 0)
5545 23:22:12.060438 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5546 23:22:12.063668 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5547 23:22:12.070587 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 23:22:12.073679 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 23:22:12.077210 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 23:22:12.084162 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 23:22:12.087276 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5552 23:22:12.090286 0 11 16 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
5553 23:22:12.098042 0 11 20 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
5554 23:22:12.101113 0 11 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5555 23:22:12.104071 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 23:22:12.110785 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 23:22:12.114125 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 23:22:12.116781 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 23:22:12.123716 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 23:22:12.127300 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5561 23:22:12.130672 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5562 23:22:12.136860 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 23:22:12.140836 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 23:22:12.143848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 23:22:12.150532 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 23:22:12.153701 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 23:22:12.157108 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 23:22:12.163507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 23:22:12.166623 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 23:22:12.169887 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 23:22:12.176229 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 23:22:12.179625 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 23:22:12.183029 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 23:22:12.189893 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 23:22:12.193157 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5576 23:22:12.196609 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5577 23:22:12.202676 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5578 23:22:12.203361 Total UI for P1: 0, mck2ui 16
5579 23:22:12.209118 best dqsien dly found for B0: ( 0, 14, 14)
5580 23:22:12.213072 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 23:22:12.216462 Total UI for P1: 0, mck2ui 16
5582 23:22:12.219584 best dqsien dly found for B1: ( 0, 14, 18)
5583 23:22:12.222677 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5584 23:22:12.225992 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5585 23:22:12.226495
5586 23:22:12.229672 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5587 23:22:12.232239 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5588 23:22:12.235684 [Gating] SW calibration Done
5589 23:22:12.236260 ==
5590 23:22:12.238562 Dram Type= 6, Freq= 0, CH_1, rank 1
5591 23:22:12.243414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5592 23:22:12.245815 ==
5593 23:22:12.246300 RX Vref Scan: 0
5594 23:22:12.246696
5595 23:22:12.249799 RX Vref 0 -> 0, step: 1
5596 23:22:12.250357
5597 23:22:12.252541 RX Delay -80 -> 252, step: 8
5598 23:22:12.255939 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5599 23:22:12.258616 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5600 23:22:12.262193 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5601 23:22:12.265177 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5602 23:22:12.269120 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5603 23:22:12.275505 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5604 23:22:12.278825 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5605 23:22:12.282216 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5606 23:22:12.285431 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5607 23:22:12.289468 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5608 23:22:12.295277 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5609 23:22:12.299131 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5610 23:22:12.302253 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5611 23:22:12.305461 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5612 23:22:12.308602 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5613 23:22:12.312477 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5614 23:22:12.315371 ==
5615 23:22:12.318718 Dram Type= 6, Freq= 0, CH_1, rank 1
5616 23:22:12.322210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5617 23:22:12.322771 ==
5618 23:22:12.323141 DQS Delay:
5619 23:22:12.325745 DQS0 = 0, DQS1 = 0
5620 23:22:12.326317 DQM Delay:
5621 23:22:12.328752 DQM0 = 95, DQM1 = 86
5622 23:22:12.329240 DQ Delay:
5623 23:22:12.331879 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =91
5624 23:22:12.335163 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5625 23:22:12.338243 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5626 23:22:12.342061 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =95
5627 23:22:12.342528
5628 23:22:12.342893
5629 23:22:12.343237 ==
5630 23:22:12.344511 Dram Type= 6, Freq= 0, CH_1, rank 1
5631 23:22:12.348254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5632 23:22:12.348336 ==
5633 23:22:12.348402
5634 23:22:12.348462
5635 23:22:12.351033 TX Vref Scan disable
5636 23:22:12.354525 == TX Byte 0 ==
5637 23:22:12.358225 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5638 23:22:12.361090 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5639 23:22:12.364904 == TX Byte 1 ==
5640 23:22:12.367897 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5641 23:22:12.371797 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5642 23:22:12.371967 ==
5643 23:22:12.374310 Dram Type= 6, Freq= 0, CH_1, rank 1
5644 23:22:12.380826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5645 23:22:12.381055 ==
5646 23:22:12.381225
5647 23:22:12.381393
5648 23:22:12.381540 TX Vref Scan disable
5649 23:22:12.385394 == TX Byte 0 ==
5650 23:22:12.388431 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5651 23:22:12.394922 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5652 23:22:12.395194 == TX Byte 1 ==
5653 23:22:12.398981 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5654 23:22:12.405900 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5655 23:22:12.406683
5656 23:22:12.407282 [DATLAT]
5657 23:22:12.407775 Freq=933, CH1 RK1
5658 23:22:12.408304
5659 23:22:12.409219 DATLAT Default: 0xb
5660 23:22:12.409647 0, 0xFFFF, sum = 0
5661 23:22:12.411893 1, 0xFFFF, sum = 0
5662 23:22:12.415026 2, 0xFFFF, sum = 0
5663 23:22:12.415686 3, 0xFFFF, sum = 0
5664 23:22:12.419350 4, 0xFFFF, sum = 0
5665 23:22:12.420054 5, 0xFFFF, sum = 0
5666 23:22:12.421602 6, 0xFFFF, sum = 0
5667 23:22:12.422272 7, 0xFFFF, sum = 0
5668 23:22:12.424877 8, 0xFFFF, sum = 0
5669 23:22:12.425511 9, 0xFFFF, sum = 0
5670 23:22:12.428455 10, 0x0, sum = 1
5671 23:22:12.429211 11, 0x0, sum = 2
5672 23:22:12.431308 12, 0x0, sum = 3
5673 23:22:12.431854 13, 0x0, sum = 4
5674 23:22:12.432312 best_step = 11
5675 23:22:12.434831
5676 23:22:12.435426 ==
5677 23:22:12.438553 Dram Type= 6, Freq= 0, CH_1, rank 1
5678 23:22:12.441686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5679 23:22:12.442281 ==
5680 23:22:12.442834 RX Vref Scan: 0
5681 23:22:12.443459
5682 23:22:12.445204 RX Vref 0 -> 0, step: 1
5683 23:22:12.445901
5684 23:22:12.448437 RX Delay -69 -> 252, step: 4
5685 23:22:12.455172 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5686 23:22:12.458182 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5687 23:22:12.461522 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5688 23:22:12.464544 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5689 23:22:12.468448 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5690 23:22:12.471276 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5691 23:22:12.478154 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5692 23:22:12.481591 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5693 23:22:12.484377 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5694 23:22:12.488151 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5695 23:22:12.491713 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5696 23:22:12.497678 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5697 23:22:12.500813 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5698 23:22:12.504513 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5699 23:22:12.508098 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5700 23:22:12.510808 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5701 23:22:12.511385 ==
5702 23:22:12.514582 Dram Type= 6, Freq= 0, CH_1, rank 1
5703 23:22:12.521259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5704 23:22:12.521728 ==
5705 23:22:12.522103 DQS Delay:
5706 23:22:12.524228 DQS0 = 0, DQS1 = 0
5707 23:22:12.524784 DQM Delay:
5708 23:22:12.525156 DQM0 = 95, DQM1 = 87
5709 23:22:12.528011 DQ Delay:
5710 23:22:12.530626 DQ0 =94, DQ1 =90, DQ2 =88, DQ3 =92
5711 23:22:12.534247 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5712 23:22:12.538212 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5713 23:22:12.540479 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96
5714 23:22:12.540955
5715 23:22:12.541290
5716 23:22:12.547886 [DQSOSCAuto] RK1, (LSB)MR18= 0x2626, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5717 23:22:12.551131 CH1 RK1: MR19=505, MR18=2626
5718 23:22:12.557460 CH1_RK1: MR19=0x505, MR18=0x2626, DQSOSC=409, MR23=63, INC=64, DEC=43
5719 23:22:12.560309 [RxdqsGatingPostProcess] freq 933
5720 23:22:12.564173 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5721 23:22:12.567789 Pre-setting of DQS Precalculation
5722 23:22:12.573951 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5723 23:22:12.580436 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5724 23:22:12.587060 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5725 23:22:12.587607
5726 23:22:12.587976
5727 23:22:12.590280 [Calibration Summary] 1866 Mbps
5728 23:22:12.593695 CH 0, Rank 0
5729 23:22:12.594160 SW Impedance : PASS
5730 23:22:12.596837 DUTY Scan : NO K
5731 23:22:12.600335 ZQ Calibration : PASS
5732 23:22:12.600845 Jitter Meter : NO K
5733 23:22:12.603856 CBT Training : PASS
5734 23:22:12.606657 Write leveling : PASS
5735 23:22:12.607124 RX DQS gating : PASS
5736 23:22:12.610094 RX DQ/DQS(RDDQC) : PASS
5737 23:22:12.610560 TX DQ/DQS : PASS
5738 23:22:12.613889 RX DATLAT : PASS
5739 23:22:12.617272 RX DQ/DQS(Engine): PASS
5740 23:22:12.617740 TX OE : NO K
5741 23:22:12.619615 All Pass.
5742 23:22:12.620075
5743 23:22:12.620445 CH 0, Rank 1
5744 23:22:12.623973 SW Impedance : PASS
5745 23:22:12.624437 DUTY Scan : NO K
5746 23:22:12.627066 ZQ Calibration : PASS
5747 23:22:12.629885 Jitter Meter : NO K
5748 23:22:12.630358 CBT Training : PASS
5749 23:22:12.634303 Write leveling : PASS
5750 23:22:12.636218 RX DQS gating : PASS
5751 23:22:12.636921 RX DQ/DQS(RDDQC) : PASS
5752 23:22:12.641180 TX DQ/DQS : PASS
5753 23:22:12.643398 RX DATLAT : PASS
5754 23:22:12.643979 RX DQ/DQS(Engine): PASS
5755 23:22:12.648049 TX OE : NO K
5756 23:22:12.648638 All Pass.
5757 23:22:12.649123
5758 23:22:12.650198 CH 1, Rank 0
5759 23:22:12.650660 SW Impedance : PASS
5760 23:22:12.653026 DUTY Scan : NO K
5761 23:22:12.656648 ZQ Calibration : PASS
5762 23:22:12.657152 Jitter Meter : NO K
5763 23:22:12.659526 CBT Training : PASS
5764 23:22:12.662790 Write leveling : PASS
5765 23:22:12.663250 RX DQS gating : PASS
5766 23:22:12.666028 RX DQ/DQS(RDDQC) : PASS
5767 23:22:12.669941 TX DQ/DQS : PASS
5768 23:22:12.670368 RX DATLAT : PASS
5769 23:22:12.673794 RX DQ/DQS(Engine): PASS
5770 23:22:12.674217 TX OE : NO K
5771 23:22:12.676426 All Pass.
5772 23:22:12.676893
5773 23:22:12.677237 CH 1, Rank 1
5774 23:22:12.679524 SW Impedance : PASS
5775 23:22:12.679945 DUTY Scan : NO K
5776 23:22:12.682657 ZQ Calibration : PASS
5777 23:22:12.686035 Jitter Meter : NO K
5778 23:22:12.686117 CBT Training : PASS
5779 23:22:12.688655 Write leveling : PASS
5780 23:22:12.693058 RX DQS gating : PASS
5781 23:22:12.693140 RX DQ/DQS(RDDQC) : PASS
5782 23:22:12.695616 TX DQ/DQS : PASS
5783 23:22:12.699029 RX DATLAT : PASS
5784 23:22:12.699111 RX DQ/DQS(Engine): PASS
5785 23:22:12.701903 TX OE : NO K
5786 23:22:12.701985 All Pass.
5787 23:22:12.702050
5788 23:22:12.705658 DramC Write-DBI off
5789 23:22:12.708679 PER_BANK_REFRESH: Hybrid Mode
5790 23:22:12.708799 TX_TRACKING: ON
5791 23:22:12.718986 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5792 23:22:12.722503 [FAST_K] Save calibration result to emmc
5793 23:22:12.726429 dramc_set_vcore_voltage set vcore to 650000
5794 23:22:12.729134 Read voltage for 400, 6
5795 23:22:12.729316 Vio18 = 0
5796 23:22:12.731621 Vcore = 650000
5797 23:22:12.731803 Vdram = 0
5798 23:22:12.731896 Vddq = 0
5799 23:22:12.731979 Vmddr = 0
5800 23:22:12.738749 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5801 23:22:12.746091 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5802 23:22:12.746305 MEM_TYPE=3, freq_sel=20
5803 23:22:12.750017 sv_algorithm_assistance_LP4_800
5804 23:22:12.751640 ============ PULL DRAM RESETB DOWN ============
5805 23:22:12.758802 ========== PULL DRAM RESETB DOWN end =========
5806 23:22:12.761853 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5807 23:22:12.765027 ===================================
5808 23:22:12.769297 LPDDR4 DRAM CONFIGURATION
5809 23:22:12.772184 ===================================
5810 23:22:12.772507 EX_ROW_EN[0] = 0x0
5811 23:22:12.775524 EX_ROW_EN[1] = 0x0
5812 23:22:12.776004 LP4Y_EN = 0x0
5813 23:22:12.778037 WORK_FSP = 0x0
5814 23:22:12.778502 WL = 0x2
5815 23:22:12.781603 RL = 0x2
5816 23:22:12.782103 BL = 0x2
5817 23:22:12.785031 RPST = 0x0
5818 23:22:12.785494 RD_PRE = 0x0
5819 23:22:12.788812 WR_PRE = 0x1
5820 23:22:12.792037 WR_PST = 0x0
5821 23:22:12.792594 DBI_WR = 0x0
5822 23:22:12.795384 DBI_RD = 0x0
5823 23:22:12.795942 OTF = 0x1
5824 23:22:12.798499 ===================================
5825 23:22:12.801713 ===================================
5826 23:22:12.805036 ANA top config
5827 23:22:12.808357 ===================================
5828 23:22:12.808968 DLL_ASYNC_EN = 0
5829 23:22:12.811804 ALL_SLAVE_EN = 1
5830 23:22:12.815184 NEW_RANK_MODE = 1
5831 23:22:12.818219 DLL_IDLE_MODE = 1
5832 23:22:12.818772 LP45_APHY_COMB_EN = 1
5833 23:22:12.821814 TX_ODT_DIS = 1
5834 23:22:12.824675 NEW_8X_MODE = 1
5835 23:22:12.827878 ===================================
5836 23:22:12.831019 ===================================
5837 23:22:12.834868 data_rate = 800
5838 23:22:12.838202 CKR = 1
5839 23:22:12.841629 DQ_P2S_RATIO = 4
5840 23:22:12.844613 ===================================
5841 23:22:12.845243 CA_P2S_RATIO = 4
5842 23:22:12.847493 DQ_CA_OPEN = 0
5843 23:22:12.851213 DQ_SEMI_OPEN = 1
5844 23:22:12.854382 CA_SEMI_OPEN = 1
5845 23:22:12.858448 CA_FULL_RATE = 0
5846 23:22:12.860797 DQ_CKDIV4_EN = 0
5847 23:22:12.861514 CA_CKDIV4_EN = 1
5848 23:22:12.864546 CA_PREDIV_EN = 0
5849 23:22:12.867714 PH8_DLY = 0
5850 23:22:12.870949 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5851 23:22:12.874961 DQ_AAMCK_DIV = 0
5852 23:22:12.877664 CA_AAMCK_DIV = 0
5853 23:22:12.878225 CA_ADMCK_DIV = 4
5854 23:22:12.880534 DQ_TRACK_CA_EN = 0
5855 23:22:12.883995 CA_PICK = 800
5856 23:22:12.887136 CA_MCKIO = 400
5857 23:22:12.890689 MCKIO_SEMI = 400
5858 23:22:12.893869 PLL_FREQ = 3016
5859 23:22:12.897445 DQ_UI_PI_RATIO = 32
5860 23:22:12.900495 CA_UI_PI_RATIO = 32
5861 23:22:12.903815 ===================================
5862 23:22:12.907214 ===================================
5863 23:22:12.907775 memory_type:LPDDR4
5864 23:22:12.910551 GP_NUM : 10
5865 23:22:12.913819 SRAM_EN : 1
5866 23:22:12.914388 MD32_EN : 0
5867 23:22:12.917263 ===================================
5868 23:22:12.920613 [ANA_INIT] >>>>>>>>>>>>>>
5869 23:22:12.924033 <<<<<< [CONFIGURE PHASE]: ANA_TX
5870 23:22:12.927009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5871 23:22:12.930218 ===================================
5872 23:22:12.933571 data_rate = 800,PCW = 0X7400
5873 23:22:12.936933 ===================================
5874 23:22:12.940222 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5875 23:22:12.944692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5876 23:22:12.956648 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5877 23:22:12.960505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5878 23:22:12.963478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5879 23:22:12.966220 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5880 23:22:12.970396 [ANA_INIT] flow start
5881 23:22:12.970863 [ANA_INIT] PLL >>>>>>>>
5882 23:22:12.973206 [ANA_INIT] PLL <<<<<<<<
5883 23:22:12.976780 [ANA_INIT] MIDPI >>>>>>>>
5884 23:22:12.980254 [ANA_INIT] MIDPI <<<<<<<<
5885 23:22:12.980757 [ANA_INIT] DLL >>>>>>>>
5886 23:22:12.983589 [ANA_INIT] flow end
5887 23:22:12.986796 ============ LP4 DIFF to SE enter ============
5888 23:22:12.990247 ============ LP4 DIFF to SE exit ============
5889 23:22:12.993484 [ANA_INIT] <<<<<<<<<<<<<
5890 23:22:12.996457 [Flow] Enable top DCM control >>>>>
5891 23:22:12.999854 [Flow] Enable top DCM control <<<<<
5892 23:22:13.003319 Enable DLL master slave shuffle
5893 23:22:13.010198 ==============================================================
5894 23:22:13.010763 Gating Mode config
5895 23:22:13.016883 ==============================================================
5896 23:22:13.017440 Config description:
5897 23:22:13.026142 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5898 23:22:13.033012 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5899 23:22:13.039125 SELPH_MODE 0: By rank 1: By Phase
5900 23:22:13.042462 ==============================================================
5901 23:22:13.045339 GAT_TRACK_EN = 0
5902 23:22:13.049546 RX_GATING_MODE = 2
5903 23:22:13.052157 RX_GATING_TRACK_MODE = 2
5904 23:22:13.055658 SELPH_MODE = 1
5905 23:22:13.059036 PICG_EARLY_EN = 1
5906 23:22:13.061989 VALID_LAT_VALUE = 1
5907 23:22:13.068424 ==============================================================
5908 23:22:13.071826 Enter into Gating configuration >>>>
5909 23:22:13.075323 Exit from Gating configuration <<<<
5910 23:22:13.078845 Enter into DVFS_PRE_config >>>>>
5911 23:22:13.088878 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5912 23:22:13.091672 Exit from DVFS_PRE_config <<<<<
5913 23:22:13.095259 Enter into PICG configuration >>>>
5914 23:22:13.098710 Exit from PICG configuration <<<<
5915 23:22:13.101941 [RX_INPUT] configuration >>>>>
5916 23:22:13.102269 [RX_INPUT] configuration <<<<<
5917 23:22:13.109160 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5918 23:22:13.115308 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5919 23:22:13.122273 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5920 23:22:13.125530 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5921 23:22:13.131778 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5922 23:22:13.138607 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5923 23:22:13.141636 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5924 23:22:13.148050 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5925 23:22:13.151573 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5926 23:22:13.155136 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5927 23:22:13.158153 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5928 23:22:13.164930 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5929 23:22:13.168074 ===================================
5930 23:22:13.168631 LPDDR4 DRAM CONFIGURATION
5931 23:22:13.171994 ===================================
5932 23:22:13.174550 EX_ROW_EN[0] = 0x0
5933 23:22:13.178508 EX_ROW_EN[1] = 0x0
5934 23:22:13.179139 LP4Y_EN = 0x0
5935 23:22:13.181118 WORK_FSP = 0x0
5936 23:22:13.181583 WL = 0x2
5937 23:22:13.184696 RL = 0x2
5938 23:22:13.185304 BL = 0x2
5939 23:22:13.187825 RPST = 0x0
5940 23:22:13.188376 RD_PRE = 0x0
5941 23:22:13.191889 WR_PRE = 0x1
5942 23:22:13.192445 WR_PST = 0x0
5943 23:22:13.195863 DBI_WR = 0x0
5944 23:22:13.196423 DBI_RD = 0x0
5945 23:22:13.199414 OTF = 0x1
5946 23:22:13.200789 ===================================
5947 23:22:13.204650 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5948 23:22:13.207788 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5949 23:22:13.215162 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5950 23:22:13.217866 ===================================
5951 23:22:13.218426 LPDDR4 DRAM CONFIGURATION
5952 23:22:13.221677 ===================================
5953 23:22:13.225181 EX_ROW_EN[0] = 0x10
5954 23:22:13.227862 EX_ROW_EN[1] = 0x0
5955 23:22:13.228422 LP4Y_EN = 0x0
5956 23:22:13.231372 WORK_FSP = 0x0
5957 23:22:13.231867 WL = 0x2
5958 23:22:13.234642 RL = 0x2
5959 23:22:13.235211 BL = 0x2
5960 23:22:13.238307 RPST = 0x0
5961 23:22:13.238770 RD_PRE = 0x0
5962 23:22:13.240880 WR_PRE = 0x1
5963 23:22:13.241436 WR_PST = 0x0
5964 23:22:13.244375 DBI_WR = 0x0
5965 23:22:13.244887 DBI_RD = 0x0
5966 23:22:13.248007 OTF = 0x1
5967 23:22:13.250689 ===================================
5968 23:22:13.257357 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5969 23:22:13.260819 nWR fixed to 30
5970 23:22:13.261391 [ModeRegInit_LP4] CH0 RK0
5971 23:22:13.264782 [ModeRegInit_LP4] CH0 RK1
5972 23:22:13.268394 [ModeRegInit_LP4] CH1 RK0
5973 23:22:13.270892 [ModeRegInit_LP4] CH1 RK1
5974 23:22:13.271562 match AC timing 18
5975 23:22:13.273899 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5976 23:22:13.281007 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5977 23:22:13.284055 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5978 23:22:13.291095 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5979 23:22:13.293610 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5980 23:22:13.294078 ==
5981 23:22:13.296956 Dram Type= 6, Freq= 0, CH_0, rank 0
5982 23:22:13.300605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5983 23:22:13.301216 ==
5984 23:22:13.307970 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5985 23:22:13.313448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5986 23:22:13.316960 [CA 0] Center 36 (8~64) winsize 57
5987 23:22:13.319959 [CA 1] Center 36 (8~64) winsize 57
5988 23:22:13.320425 [CA 2] Center 36 (8~64) winsize 57
5989 23:22:13.323472 [CA 3] Center 36 (8~64) winsize 57
5990 23:22:13.326543 [CA 4] Center 36 (8~64) winsize 57
5991 23:22:13.330596 [CA 5] Center 36 (8~64) winsize 57
5992 23:22:13.331152
5993 23:22:13.334812 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5994 23:22:13.336461
5995 23:22:13.341211 [CATrainingPosCal] consider 1 rank data
5996 23:22:13.341770 u2DelayCellTimex100 = 270/100 ps
5997 23:22:13.347321 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5998 23:22:13.350449 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5999 23:22:13.353450 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6000 23:22:13.357436 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6001 23:22:13.359944 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6002 23:22:13.363575 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6003 23:22:13.364227
6004 23:22:13.367033 CA PerBit enable=1, Macro0, CA PI delay=36
6005 23:22:13.367495
6006 23:22:13.369289 [CBTSetCACLKResult] CA Dly = 36
6007 23:22:13.372858 CS Dly: 1 (0~32)
6008 23:22:13.373381 ==
6009 23:22:13.376066 Dram Type= 6, Freq= 0, CH_0, rank 1
6010 23:22:13.379912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6011 23:22:13.380377 ==
6012 23:22:13.386608 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6013 23:22:13.389437 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6014 23:22:13.392614 [CA 0] Center 36 (8~64) winsize 57
6015 23:22:13.396143 [CA 1] Center 36 (8~64) winsize 57
6016 23:22:13.399951 [CA 2] Center 36 (8~64) winsize 57
6017 23:22:13.402859 [CA 3] Center 36 (8~64) winsize 57
6018 23:22:13.406160 [CA 4] Center 36 (8~64) winsize 57
6019 23:22:13.409557 [CA 5] Center 36 (8~64) winsize 57
6020 23:22:13.410115
6021 23:22:13.414246 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6022 23:22:13.414955
6023 23:22:13.415827 [CATrainingPosCal] consider 2 rank data
6024 23:22:13.419938 u2DelayCellTimex100 = 270/100 ps
6025 23:22:13.422410 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6026 23:22:13.428907 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6027 23:22:13.431888 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6028 23:22:13.436155 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6029 23:22:13.439413 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6030 23:22:13.442343 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6031 23:22:13.442909
6032 23:22:13.445385 CA PerBit enable=1, Macro0, CA PI delay=36
6033 23:22:13.445882
6034 23:22:13.449192 [CBTSetCACLKResult] CA Dly = 36
6035 23:22:13.449727 CS Dly: 1 (0~32)
6036 23:22:13.452309
6037 23:22:13.455288 ----->DramcWriteLeveling(PI) begin...
6038 23:22:13.455758 ==
6039 23:22:13.458778 Dram Type= 6, Freq= 0, CH_0, rank 0
6040 23:22:13.462487 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6041 23:22:13.463021 ==
6042 23:22:13.465321 Write leveling (Byte 0): 32 => 0
6043 23:22:13.469131 Write leveling (Byte 1): 32 => 0
6044 23:22:13.471844 DramcWriteLeveling(PI) end<-----
6045 23:22:13.472375
6046 23:22:13.472886 ==
6047 23:22:13.474936 Dram Type= 6, Freq= 0, CH_0, rank 0
6048 23:22:13.479052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6049 23:22:13.479553 ==
6050 23:22:13.482193 [Gating] SW mode calibration
6051 23:22:13.488730 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6052 23:22:13.495171 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6053 23:22:13.498642 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6054 23:22:13.501974 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6055 23:22:13.508334 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6056 23:22:13.511501 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6057 23:22:13.514894 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6058 23:22:13.521140 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6059 23:22:13.524265 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6060 23:22:13.527875 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6061 23:22:13.534618 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6062 23:22:13.535265 Total UI for P1: 0, mck2ui 16
6063 23:22:13.541100 best dqsien dly found for B0: ( 0, 10, 16)
6064 23:22:13.541730 Total UI for P1: 0, mck2ui 16
6065 23:22:13.547451 best dqsien dly found for B1: ( 0, 10, 24)
6066 23:22:13.551755 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6067 23:22:13.554236 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6068 23:22:13.554687
6069 23:22:13.557899 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6070 23:22:13.560614 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6071 23:22:13.564364 [Gating] SW calibration Done
6072 23:22:13.564438 ==
6073 23:22:13.567309 Dram Type= 6, Freq= 0, CH_0, rank 0
6074 23:22:13.570115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6075 23:22:13.570198 ==
6076 23:22:13.573849 RX Vref Scan: 0
6077 23:22:13.573944
6078 23:22:13.574013 RX Vref 0 -> 0, step: 1
6079 23:22:13.577298
6080 23:22:13.577378 RX Delay -410 -> 252, step: 16
6081 23:22:13.583782 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6082 23:22:13.586681 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6083 23:22:13.590613 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6084 23:22:13.593641 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6085 23:22:13.600267 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6086 23:22:13.603397 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6087 23:22:13.606978 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6088 23:22:13.610037 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6089 23:22:13.616879 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6090 23:22:13.619688 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6091 23:22:13.623608 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6092 23:22:13.630541 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6093 23:22:13.633282 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6094 23:22:13.636420 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6095 23:22:13.639908 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6096 23:22:13.646322 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6097 23:22:13.646428 ==
6098 23:22:13.649621 Dram Type= 6, Freq= 0, CH_0, rank 0
6099 23:22:13.653558 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6100 23:22:13.653637 ==
6101 23:22:13.653701 DQS Delay:
6102 23:22:13.656791 DQS0 = 51, DQS1 = 59
6103 23:22:13.656861 DQM Delay:
6104 23:22:13.660095 DQM0 = 12, DQM1 = 14
6105 23:22:13.660170 DQ Delay:
6106 23:22:13.662562 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6107 23:22:13.666169 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6108 23:22:13.669392 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6109 23:22:13.673008 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6110 23:22:13.673078
6111 23:22:13.673138
6112 23:22:13.673196 ==
6113 23:22:13.676069 Dram Type= 6, Freq= 0, CH_0, rank 0
6114 23:22:13.679656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6115 23:22:13.679728 ==
6116 23:22:13.679798
6117 23:22:13.679866
6118 23:22:13.683001 TX Vref Scan disable
6119 23:22:13.685998 == TX Byte 0 ==
6120 23:22:13.689822 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6121 23:22:13.692592 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6122 23:22:13.696612 == TX Byte 1 ==
6123 23:22:13.700050 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6124 23:22:13.703000 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6125 23:22:13.703430 ==
6126 23:22:13.706975 Dram Type= 6, Freq= 0, CH_0, rank 0
6127 23:22:13.710025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6128 23:22:13.710543 ==
6129 23:22:13.712989
6130 23:22:13.713445
6131 23:22:13.713917 TX Vref Scan disable
6132 23:22:13.716294 == TX Byte 0 ==
6133 23:22:13.719917 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6134 23:22:13.723523 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6135 23:22:13.726214 == TX Byte 1 ==
6136 23:22:13.729839 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6137 23:22:13.732910 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6138 23:22:13.733462
6139 23:22:13.736264 [DATLAT]
6140 23:22:13.736768 Freq=400, CH0 RK0
6141 23:22:13.737149
6142 23:22:13.740677 DATLAT Default: 0xf
6143 23:22:13.741252 0, 0xFFFF, sum = 0
6144 23:22:13.742563 1, 0xFFFF, sum = 0
6145 23:22:13.743123 2, 0xFFFF, sum = 0
6146 23:22:13.746214 3, 0xFFFF, sum = 0
6147 23:22:13.746779 4, 0xFFFF, sum = 0
6148 23:22:13.750226 5, 0xFFFF, sum = 0
6149 23:22:13.750879 6, 0xFFFF, sum = 0
6150 23:22:13.753211 7, 0xFFFF, sum = 0
6151 23:22:13.753757 8, 0xFFFF, sum = 0
6152 23:22:13.756066 9, 0xFFFF, sum = 0
6153 23:22:13.756610 10, 0xFFFF, sum = 0
6154 23:22:13.759434 11, 0xFFFF, sum = 0
6155 23:22:13.759976 12, 0x0, sum = 1
6156 23:22:13.762322 13, 0x0, sum = 2
6157 23:22:13.762807 14, 0x0, sum = 3
6158 23:22:13.765958 15, 0x0, sum = 4
6159 23:22:13.766461 best_step = 13
6160 23:22:13.766908
6161 23:22:13.767318 ==
6162 23:22:13.769354 Dram Type= 6, Freq= 0, CH_0, rank 0
6163 23:22:13.776678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6164 23:22:13.777209 ==
6165 23:22:13.777579 RX Vref Scan: 1
6166 23:22:13.777913
6167 23:22:13.779953 RX Vref 0 -> 0, step: 1
6168 23:22:13.780549
6169 23:22:13.783342 RX Delay -359 -> 252, step: 8
6170 23:22:13.783855
6171 23:22:13.785819 Set Vref, RX VrefLevel [Byte0]: 52
6172 23:22:13.789085 [Byte1]: 49
6173 23:22:13.792867
6174 23:22:13.793324 Final RX Vref Byte 0 = 52 to rank0
6175 23:22:13.795998 Final RX Vref Byte 1 = 49 to rank0
6176 23:22:13.799105 Final RX Vref Byte 0 = 52 to rank1
6177 23:22:13.802123 Final RX Vref Byte 1 = 49 to rank1==
6178 23:22:13.805372 Dram Type= 6, Freq= 0, CH_0, rank 0
6179 23:22:13.812214 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6180 23:22:13.812631 ==
6181 23:22:13.813034 DQS Delay:
6182 23:22:13.815440 DQS0 = 52, DQS1 = 68
6183 23:22:13.815854 DQM Delay:
6184 23:22:13.816179 DQM0 = 8, DQM1 = 16
6185 23:22:13.819232 DQ Delay:
6186 23:22:13.822209 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6187 23:22:13.822624 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6188 23:22:13.825210 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6189 23:22:13.828753 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6190 23:22:13.832487
6191 23:22:13.833021
6192 23:22:13.838618 [DQSOSCAuto] RK0, (LSB)MR18= 0x9d9d, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6193 23:22:13.841593 CH0 RK0: MR19=C0C, MR18=9D9D
6194 23:22:13.848578 CH0_RK0: MR19=0xC0C, MR18=0x9D9D, DQSOSC=390, MR23=63, INC=388, DEC=258
6195 23:22:13.849043 ==
6196 23:22:13.852926 Dram Type= 6, Freq= 0, CH_0, rank 1
6197 23:22:13.855311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6198 23:22:13.855772 ==
6199 23:22:13.858490 [Gating] SW mode calibration
6200 23:22:13.865859 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6201 23:22:13.871839 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6202 23:22:13.875421 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6203 23:22:13.878064 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6204 23:22:13.884885 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6205 23:22:13.888462 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6206 23:22:13.891156 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6207 23:22:13.898331 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6208 23:22:13.901521 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6209 23:22:13.904185 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6210 23:22:13.911152 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6211 23:22:13.911232 Total UI for P1: 0, mck2ui 16
6212 23:22:13.917326 best dqsien dly found for B0: ( 0, 10, 16)
6213 23:22:13.917489 Total UI for P1: 0, mck2ui 16
6214 23:22:13.924385 best dqsien dly found for B1: ( 0, 10, 16)
6215 23:22:13.927293 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6216 23:22:13.930787 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6217 23:22:13.930949
6218 23:22:13.933842 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6219 23:22:13.938255 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6220 23:22:13.940925 [Gating] SW calibration Done
6221 23:22:13.941012 ==
6222 23:22:13.943675 Dram Type= 6, Freq= 0, CH_0, rank 1
6223 23:22:13.947008 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6224 23:22:13.947101 ==
6225 23:22:13.950258 RX Vref Scan: 0
6226 23:22:13.950359
6227 23:22:13.953871 RX Vref 0 -> 0, step: 1
6228 23:22:13.953980
6229 23:22:13.954066 RX Delay -410 -> 252, step: 16
6230 23:22:13.960116 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6231 23:22:13.963518 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6232 23:22:13.967146 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6233 23:22:13.969927 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6234 23:22:13.976617 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6235 23:22:13.981020 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6236 23:22:13.984652 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6237 23:22:13.986546 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6238 23:22:13.993080 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6239 23:22:13.997513 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6240 23:22:13.999454 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6241 23:22:14.006675 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6242 23:22:14.010442 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6243 23:22:14.013571 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6244 23:22:14.016856 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6245 23:22:14.022672 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6246 23:22:14.022753 ==
6247 23:22:14.026681 Dram Type= 6, Freq= 0, CH_0, rank 1
6248 23:22:14.030231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6249 23:22:14.030312 ==
6250 23:22:14.030376 DQS Delay:
6251 23:22:14.033711 DQS0 = 43, DQS1 = 59
6252 23:22:14.033791 DQM Delay:
6253 23:22:14.036176 DQM0 = 6, DQM1 = 15
6254 23:22:14.036256 DQ Delay:
6255 23:22:14.039597 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6256 23:22:14.042697 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6257 23:22:14.046056 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6258 23:22:14.049330 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6259 23:22:14.049411
6260 23:22:14.049474
6261 23:22:14.049532 ==
6262 23:22:14.052859 Dram Type= 6, Freq= 0, CH_0, rank 1
6263 23:22:14.056957 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6264 23:22:14.057038 ==
6265 23:22:14.057102
6266 23:22:14.057160
6267 23:22:14.059655 TX Vref Scan disable
6268 23:22:14.063022 == TX Byte 0 ==
6269 23:22:14.065984 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6270 23:22:14.069097 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6271 23:22:14.069180 == TX Byte 1 ==
6272 23:22:14.075808 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6273 23:22:14.078877 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6274 23:22:14.078960 ==
6275 23:22:14.082259 Dram Type= 6, Freq= 0, CH_0, rank 1
6276 23:22:14.085782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6277 23:22:14.085866 ==
6278 23:22:14.085951
6279 23:22:14.089158
6280 23:22:14.089240 TX Vref Scan disable
6281 23:22:14.092513 == TX Byte 0 ==
6282 23:22:14.095553 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6283 23:22:14.098631 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6284 23:22:14.102598 == TX Byte 1 ==
6285 23:22:14.105288 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6286 23:22:14.108608 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6287 23:22:14.108691
6288 23:22:14.108811 [DATLAT]
6289 23:22:14.111942 Freq=400, CH0 RK1
6290 23:22:14.112025
6291 23:22:14.115442 DATLAT Default: 0xd
6292 23:22:14.115525 0, 0xFFFF, sum = 0
6293 23:22:14.118848 1, 0xFFFF, sum = 0
6294 23:22:14.118957 2, 0xFFFF, sum = 0
6295 23:22:14.122034 3, 0xFFFF, sum = 0
6296 23:22:14.122115 4, 0xFFFF, sum = 0
6297 23:22:14.125222 5, 0xFFFF, sum = 0
6298 23:22:14.125303 6, 0xFFFF, sum = 0
6299 23:22:14.128588 7, 0xFFFF, sum = 0
6300 23:22:14.128669 8, 0xFFFF, sum = 0
6301 23:22:14.132073 9, 0xFFFF, sum = 0
6302 23:22:14.132154 10, 0xFFFF, sum = 0
6303 23:22:14.135165 11, 0xFFFF, sum = 0
6304 23:22:14.135245 12, 0x0, sum = 1
6305 23:22:14.138411 13, 0x0, sum = 2
6306 23:22:14.138491 14, 0x0, sum = 3
6307 23:22:14.141514 15, 0x0, sum = 4
6308 23:22:14.141594 best_step = 13
6309 23:22:14.141657
6310 23:22:14.141716 ==
6311 23:22:14.145205 Dram Type= 6, Freq= 0, CH_0, rank 1
6312 23:22:14.151371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6313 23:22:14.151451 ==
6314 23:22:14.151515 RX Vref Scan: 0
6315 23:22:14.151573
6316 23:22:14.154748 RX Vref 0 -> 0, step: 1
6317 23:22:14.154827
6318 23:22:14.158426 RX Delay -359 -> 252, step: 8
6319 23:22:14.164699 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6320 23:22:14.167821 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6321 23:22:14.171941 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6322 23:22:14.175277 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6323 23:22:14.181250 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6324 23:22:14.184907 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6325 23:22:14.188455 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6326 23:22:14.191008 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6327 23:22:14.197728 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6328 23:22:14.201703 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6329 23:22:14.204514 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6330 23:22:14.207927 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6331 23:22:14.215002 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6332 23:22:14.218483 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6333 23:22:14.221015 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6334 23:22:14.227461 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6335 23:22:14.227540 ==
6336 23:22:14.231187 Dram Type= 6, Freq= 0, CH_0, rank 1
6337 23:22:14.234508 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6338 23:22:14.234588 ==
6339 23:22:14.234652 DQS Delay:
6340 23:22:14.237708 DQS0 = 52, DQS1 = 64
6341 23:22:14.237787 DQM Delay:
6342 23:22:14.241732 DQM0 = 10, DQM1 = 15
6343 23:22:14.241812 DQ Delay:
6344 23:22:14.244432 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6345 23:22:14.247670 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6346 23:22:14.251081 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6347 23:22:14.254331 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6348 23:22:14.254410
6349 23:22:14.254473
6350 23:22:14.261138 [DQSOSCAuto] RK1, (LSB)MR18= 0xb4b4, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6351 23:22:14.264923 CH0 RK1: MR19=C0C, MR18=B4B4
6352 23:22:14.270687 CH0_RK1: MR19=0xC0C, MR18=0xB4B4, DQSOSC=387, MR23=63, INC=394, DEC=262
6353 23:22:14.274248 [RxdqsGatingPostProcess] freq 400
6354 23:22:14.280724 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6355 23:22:14.280819 Pre-setting of DQS Precalculation
6356 23:22:14.287133 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6357 23:22:14.287213 ==
6358 23:22:14.290440 Dram Type= 6, Freq= 0, CH_1, rank 0
6359 23:22:14.293758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6360 23:22:14.293839 ==
6361 23:22:14.300407 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6362 23:22:14.306986 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6363 23:22:14.310233 [CA 0] Center 36 (8~64) winsize 57
6364 23:22:14.313450 [CA 1] Center 36 (8~64) winsize 57
6365 23:22:14.316945 [CA 2] Center 36 (8~64) winsize 57
6366 23:22:14.320111 [CA 3] Center 36 (8~64) winsize 57
6367 23:22:14.320194 [CA 4] Center 36 (8~64) winsize 57
6368 23:22:14.324095 [CA 5] Center 36 (8~64) winsize 57
6369 23:22:14.324178
6370 23:22:14.330347 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6371 23:22:14.330430
6372 23:22:14.333544 [CATrainingPosCal] consider 1 rank data
6373 23:22:14.336960 u2DelayCellTimex100 = 270/100 ps
6374 23:22:14.340146 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 23:22:14.343566 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6376 23:22:14.346835 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6377 23:22:14.349796 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6378 23:22:14.353225 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6379 23:22:14.356646 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6380 23:22:14.356786
6381 23:22:14.359911 CA PerBit enable=1, Macro0, CA PI delay=36
6382 23:22:14.359994
6383 23:22:14.363289 [CBTSetCACLKResult] CA Dly = 36
6384 23:22:14.366273 CS Dly: 1 (0~32)
6385 23:22:14.366356 ==
6386 23:22:14.370133 Dram Type= 6, Freq= 0, CH_1, rank 1
6387 23:22:14.373480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6388 23:22:14.373562 ==
6389 23:22:14.379978 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6390 23:22:14.386417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6391 23:22:14.389776 [CA 0] Center 36 (8~64) winsize 57
6392 23:22:14.389857 [CA 1] Center 36 (8~64) winsize 57
6393 23:22:14.392915 [CA 2] Center 36 (8~64) winsize 57
6394 23:22:14.396566 [CA 3] Center 36 (8~64) winsize 57
6395 23:22:14.399465 [CA 4] Center 36 (8~64) winsize 57
6396 23:22:14.403140 [CA 5] Center 36 (8~64) winsize 57
6397 23:22:14.403221
6398 23:22:14.406377 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6399 23:22:14.406458
6400 23:22:14.410431 [CATrainingPosCal] consider 2 rank data
6401 23:22:14.412845 u2DelayCellTimex100 = 270/100 ps
6402 23:22:14.416323 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6403 23:22:14.422898 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6404 23:22:14.425907 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6405 23:22:14.429172 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6406 23:22:14.433040 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6407 23:22:14.436344 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6408 23:22:14.436424
6409 23:22:14.439291 CA PerBit enable=1, Macro0, CA PI delay=36
6410 23:22:14.439375
6411 23:22:14.442272 [CBTSetCACLKResult] CA Dly = 36
6412 23:22:14.445849 CS Dly: 1 (0~32)
6413 23:22:14.445932
6414 23:22:14.449480 ----->DramcWriteLeveling(PI) begin...
6415 23:22:14.449910 ==
6416 23:22:14.452809 Dram Type= 6, Freq= 0, CH_1, rank 0
6417 23:22:14.456179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6418 23:22:14.456788 ==
6419 23:22:14.459453 Write leveling (Byte 0): 32 => 0
6420 23:22:14.463217 Write leveling (Byte 1): 32 => 0
6421 23:22:14.465876 DramcWriteLeveling(PI) end<-----
6422 23:22:14.466300
6423 23:22:14.466735 ==
6424 23:22:14.469581 Dram Type= 6, Freq= 0, CH_1, rank 0
6425 23:22:14.472880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6426 23:22:14.473296 ==
6427 23:22:14.476554 [Gating] SW mode calibration
6428 23:22:14.482828 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6429 23:22:14.490219 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6430 23:22:14.493166 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 23:22:14.495935 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6432 23:22:14.502909 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 23:22:14.506857 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6434 23:22:14.509329 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 23:22:14.516376 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 23:22:14.519011 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 23:22:14.522874 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6438 23:22:14.529468 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 23:22:14.530029 Total UI for P1: 0, mck2ui 16
6440 23:22:14.535956 best dqsien dly found for B0: ( 0, 10, 16)
6441 23:22:14.536513 Total UI for P1: 0, mck2ui 16
6442 23:22:14.542748 best dqsien dly found for B1: ( 0, 10, 16)
6443 23:22:14.545725 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6444 23:22:14.549029 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6445 23:22:14.549488
6446 23:22:14.551962 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6447 23:22:14.555210 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6448 23:22:14.559223 [Gating] SW calibration Done
6449 23:22:14.559804 ==
6450 23:22:14.562250 Dram Type= 6, Freq= 0, CH_1, rank 0
6451 23:22:14.565206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6452 23:22:14.565683 ==
6453 23:22:14.568533 RX Vref Scan: 0
6454 23:22:14.569245
6455 23:22:14.569643 RX Vref 0 -> 0, step: 1
6456 23:22:14.572072
6457 23:22:14.572525 RX Delay -410 -> 252, step: 16
6458 23:22:14.578630 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6459 23:22:14.581920 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6460 23:22:14.584841 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6461 23:22:14.588805 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6462 23:22:14.595061 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6463 23:22:14.598611 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6464 23:22:14.601621 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6465 23:22:14.604910 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6466 23:22:14.611504 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6467 23:22:14.615190 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6468 23:22:14.618182 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6469 23:22:14.621339 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6470 23:22:14.628315 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6471 23:22:14.631312 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6472 23:22:14.635115 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6473 23:22:14.640946 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6474 23:22:14.641422 ==
6475 23:22:14.644470 Dram Type= 6, Freq= 0, CH_1, rank 0
6476 23:22:14.648641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6477 23:22:14.649298 ==
6478 23:22:14.649779 DQS Delay:
6479 23:22:14.651684 DQS0 = 43, DQS1 = 59
6480 23:22:14.652154 DQM Delay:
6481 23:22:14.654376 DQM0 = 6, DQM1 = 15
6482 23:22:14.654934 DQ Delay:
6483 23:22:14.657812 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6484 23:22:14.660868 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6485 23:22:14.664191 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6486 23:22:14.667831 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6487 23:22:14.668685
6488 23:22:14.669149
6489 23:22:14.669496 ==
6490 23:22:14.671334 Dram Type= 6, Freq= 0, CH_1, rank 0
6491 23:22:14.674074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6492 23:22:14.674536 ==
6493 23:22:14.674918
6494 23:22:14.675408
6495 23:22:14.677556 TX Vref Scan disable
6496 23:22:14.680450 == TX Byte 0 ==
6497 23:22:14.684266 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6498 23:22:14.687452 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6499 23:22:14.690623 == TX Byte 1 ==
6500 23:22:14.693933 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6501 23:22:14.697575 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6502 23:22:14.698138 ==
6503 23:22:14.700366 Dram Type= 6, Freq= 0, CH_1, rank 0
6504 23:22:14.704358 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6505 23:22:14.707793 ==
6506 23:22:14.708355
6507 23:22:14.708767
6508 23:22:14.709114 TX Vref Scan disable
6509 23:22:14.710548 == TX Byte 0 ==
6510 23:22:14.714355 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6511 23:22:14.717137 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6512 23:22:14.720747 == TX Byte 1 ==
6513 23:22:14.723442 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6514 23:22:14.727051 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6515 23:22:14.727606
6516 23:22:14.730025 [DATLAT]
6517 23:22:14.730485 Freq=400, CH1 RK0
6518 23:22:14.730853
6519 23:22:14.735063 DATLAT Default: 0xf
6520 23:22:14.735519 0, 0xFFFF, sum = 0
6521 23:22:14.737238 1, 0xFFFF, sum = 0
6522 23:22:14.737698 2, 0xFFFF, sum = 0
6523 23:22:14.741101 3, 0xFFFF, sum = 0
6524 23:22:14.741666 4, 0xFFFF, sum = 0
6525 23:22:14.744859 5, 0xFFFF, sum = 0
6526 23:22:14.745418 6, 0xFFFF, sum = 0
6527 23:22:14.747654 7, 0xFFFF, sum = 0
6528 23:22:14.748210 8, 0xFFFF, sum = 0
6529 23:22:14.749891 9, 0xFFFF, sum = 0
6530 23:22:14.750360 10, 0xFFFF, sum = 0
6531 23:22:14.753930 11, 0xFFFF, sum = 0
6532 23:22:14.757510 12, 0x0, sum = 1
6533 23:22:14.758093 13, 0x0, sum = 2
6534 23:22:14.758584 14, 0x0, sum = 3
6535 23:22:14.762337 15, 0x0, sum = 4
6536 23:22:14.762927 best_step = 13
6537 23:22:14.763412
6538 23:22:14.763861 ==
6539 23:22:14.764661 Dram Type= 6, Freq= 0, CH_1, rank 0
6540 23:22:14.770471 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6541 23:22:14.770946 ==
6542 23:22:14.771424 RX Vref Scan: 1
6543 23:22:14.771876
6544 23:22:14.773006 RX Vref 0 -> 0, step: 1
6545 23:22:14.773477
6546 23:22:14.776413 RX Delay -359 -> 252, step: 8
6547 23:22:14.776966
6548 23:22:14.780400 Set Vref, RX VrefLevel [Byte0]: 52
6549 23:22:14.783316 [Byte1]: 49
6550 23:22:14.787338
6551 23:22:14.787893 Final RX Vref Byte 0 = 52 to rank0
6552 23:22:14.790461 Final RX Vref Byte 1 = 49 to rank0
6553 23:22:14.793422 Final RX Vref Byte 0 = 52 to rank1
6554 23:22:14.796649 Final RX Vref Byte 1 = 49 to rank1==
6555 23:22:14.801770 Dram Type= 6, Freq= 0, CH_1, rank 0
6556 23:22:14.806687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6557 23:22:14.807250 ==
6558 23:22:14.807620 DQS Delay:
6559 23:22:14.810252 DQS0 = 48, DQS1 = 64
6560 23:22:14.810716 DQM Delay:
6561 23:22:14.811085 DQM0 = 8, DQM1 = 16
6562 23:22:14.813114 DQ Delay:
6563 23:22:14.817047 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6564 23:22:14.817509 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6565 23:22:14.820645 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6566 23:22:14.823316 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6567 23:22:14.823876
6568 23:22:14.824246
6569 23:22:14.833222 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0d0, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6570 23:22:14.836351 CH1 RK0: MR19=C0C, MR18=D0D0
6571 23:22:14.843604 CH1_RK0: MR19=0xC0C, MR18=0xD0D0, DQSOSC=384, MR23=63, INC=400, DEC=267
6572 23:22:14.844180 ==
6573 23:22:14.846235 Dram Type= 6, Freq= 0, CH_1, rank 1
6574 23:22:14.849559 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6575 23:22:14.850033 ==
6576 23:22:14.853821 [Gating] SW mode calibration
6577 23:22:14.859871 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6578 23:22:14.862885 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6579 23:22:14.869663 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6580 23:22:14.872687 0 7 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6581 23:22:14.876935 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6582 23:22:14.883436 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6583 23:22:14.886340 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6584 23:22:14.889232 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6585 23:22:14.896077 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6586 23:22:14.899738 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6587 23:22:14.903055 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6588 23:22:14.906639 Total UI for P1: 0, mck2ui 16
6589 23:22:14.909546 best dqsien dly found for B0: ( 0, 10, 16)
6590 23:22:14.913269 Total UI for P1: 0, mck2ui 16
6591 23:22:14.916535 best dqsien dly found for B1: ( 0, 10, 16)
6592 23:22:14.919335 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6593 23:22:14.922924 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6594 23:22:14.926185
6595 23:22:14.929430 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6596 23:22:14.933787 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6597 23:22:14.935941 [Gating] SW calibration Done
6598 23:22:14.936413 ==
6599 23:22:14.939265 Dram Type= 6, Freq= 0, CH_1, rank 1
6600 23:22:14.942804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6601 23:22:14.943281 ==
6602 23:22:14.943770 RX Vref Scan: 0
6603 23:22:14.946739
6604 23:22:14.947212 RX Vref 0 -> 0, step: 1
6605 23:22:14.947694
6606 23:22:14.949610 RX Delay -410 -> 252, step: 16
6607 23:22:14.953191 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6608 23:22:14.959584 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6609 23:22:14.962396 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6610 23:22:14.966148 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6611 23:22:14.968621 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6612 23:22:14.975150 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6613 23:22:14.979344 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6614 23:22:14.982627 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6615 23:22:14.985025 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6616 23:22:14.991853 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6617 23:22:14.995527 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6618 23:22:14.998664 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6619 23:22:15.005250 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6620 23:22:15.009000 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6621 23:22:15.012604 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6622 23:22:15.015061 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6623 23:22:15.015347 ==
6624 23:22:15.018691 Dram Type= 6, Freq= 0, CH_1, rank 1
6625 23:22:15.024764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6626 23:22:15.025160 ==
6627 23:22:15.025403 DQS Delay:
6628 23:22:15.028551 DQS0 = 43, DQS1 = 59
6629 23:22:15.028980 DQM Delay:
6630 23:22:15.031943 DQM0 = 10, DQM1 = 17
6631 23:22:15.032449 DQ Delay:
6632 23:22:15.034765 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6633 23:22:15.038674 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6634 23:22:15.039134 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6635 23:22:15.045212 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6636 23:22:15.045775
6637 23:22:15.046144
6638 23:22:15.046479 ==
6639 23:22:15.048794 Dram Type= 6, Freq= 0, CH_1, rank 1
6640 23:22:15.052148 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6641 23:22:15.052783 ==
6642 23:22:15.053176
6643 23:22:15.053520
6644 23:22:15.054548 TX Vref Scan disable
6645 23:22:15.055006 == TX Byte 0 ==
6646 23:22:15.058239 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6647 23:22:15.064871 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6648 23:22:15.065433 == TX Byte 1 ==
6649 23:22:15.068532 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6650 23:22:15.075417 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6651 23:22:15.076021 ==
6652 23:22:15.078138 Dram Type= 6, Freq= 0, CH_1, rank 1
6653 23:22:15.081383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6654 23:22:15.082111 ==
6655 23:22:15.082611
6656 23:22:15.083351
6657 23:22:15.084326 TX Vref Scan disable
6658 23:22:15.084897 == TX Byte 0 ==
6659 23:22:15.090940 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6660 23:22:15.094126 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6661 23:22:15.094599 == TX Byte 1 ==
6662 23:22:15.101169 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6663 23:22:15.104557 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6664 23:22:15.105172
6665 23:22:15.105656 [DATLAT]
6666 23:22:15.107853 Freq=400, CH1 RK1
6667 23:22:15.108426
6668 23:22:15.109002 DATLAT Default: 0xd
6669 23:22:15.111661 0, 0xFFFF, sum = 0
6670 23:22:15.112141 1, 0xFFFF, sum = 0
6671 23:22:15.114759 2, 0xFFFF, sum = 0
6672 23:22:15.115334 3, 0xFFFF, sum = 0
6673 23:22:15.117934 4, 0xFFFF, sum = 0
6674 23:22:15.118513 5, 0xFFFF, sum = 0
6675 23:22:15.121025 6, 0xFFFF, sum = 0
6676 23:22:15.121504 7, 0xFFFF, sum = 0
6677 23:22:15.124791 8, 0xFFFF, sum = 0
6678 23:22:15.125363 9, 0xFFFF, sum = 0
6679 23:22:15.127688 10, 0xFFFF, sum = 0
6680 23:22:15.128170 11, 0xFFFF, sum = 0
6681 23:22:15.130544 12, 0x0, sum = 1
6682 23:22:15.131022 13, 0x0, sum = 2
6683 23:22:15.133899 14, 0x0, sum = 3
6684 23:22:15.134398 15, 0x0, sum = 4
6685 23:22:15.137397 best_step = 13
6686 23:22:15.137856
6687 23:22:15.138221 ==
6688 23:22:15.140672 Dram Type= 6, Freq= 0, CH_1, rank 1
6689 23:22:15.143843 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6690 23:22:15.144380 ==
6691 23:22:15.148083 RX Vref Scan: 0
6692 23:22:15.148655
6693 23:22:15.149087 RX Vref 0 -> 0, step: 1
6694 23:22:15.149434
6695 23:22:15.150574 RX Delay -359 -> 252, step: 8
6696 23:22:15.158853 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6697 23:22:15.162378 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6698 23:22:15.165652 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6699 23:22:15.172635 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6700 23:22:15.175535 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6701 23:22:15.179006 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6702 23:22:15.182285 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6703 23:22:15.189312 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6704 23:22:15.192485 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6705 23:22:15.195239 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6706 23:22:15.198518 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6707 23:22:15.205178 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6708 23:22:15.209492 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6709 23:22:15.211433 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6710 23:22:15.216021 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6711 23:22:15.221562 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6712 23:22:15.222020 ==
6713 23:22:15.224758 Dram Type= 6, Freq= 0, CH_1, rank 1
6714 23:22:15.228275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6715 23:22:15.228772 ==
6716 23:22:15.229147 DQS Delay:
6717 23:22:15.231940 DQS0 = 48, DQS1 = 64
6718 23:22:15.232393 DQM Delay:
6719 23:22:15.234481 DQM0 = 9, DQM1 = 15
6720 23:22:15.234952 DQ Delay:
6721 23:22:15.238268 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6722 23:22:15.241226 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6723 23:22:15.244290 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6724 23:22:15.248169 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6725 23:22:15.248778
6726 23:22:15.249162
6727 23:22:15.255117 [DQSOSCAuto] RK1, (LSB)MR18= 0xa4a4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6728 23:22:15.257796 CH1 RK1: MR19=C0C, MR18=A4A4
6729 23:22:15.264514 CH1_RK1: MR19=0xC0C, MR18=0xA4A4, DQSOSC=389, MR23=63, INC=390, DEC=260
6730 23:22:15.268121 [RxdqsGatingPostProcess] freq 400
6731 23:22:15.274540 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6732 23:22:15.277930 Pre-setting of DQS Precalculation
6733 23:22:15.280993 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6734 23:22:15.287546 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6735 23:22:15.298326 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6736 23:22:15.298889
6737 23:22:15.299376
6738 23:22:15.299868 [Calibration Summary] 800 Mbps
6739 23:22:15.300778 CH 0, Rank 0
6740 23:22:15.301159 SW Impedance : PASS
6741 23:22:15.304113 DUTY Scan : NO K
6742 23:22:15.307978 ZQ Calibration : PASS
6743 23:22:15.308527 Jitter Meter : NO K
6744 23:22:15.310681 CBT Training : PASS
6745 23:22:15.314868 Write leveling : PASS
6746 23:22:15.315429 RX DQS gating : PASS
6747 23:22:15.317521 RX DQ/DQS(RDDQC) : PASS
6748 23:22:15.320882 TX DQ/DQS : PASS
6749 23:22:15.321439 RX DATLAT : PASS
6750 23:22:15.324268 RX DQ/DQS(Engine): PASS
6751 23:22:15.327100 TX OE : NO K
6752 23:22:15.327556 All Pass.
6753 23:22:15.327921
6754 23:22:15.328256 CH 0, Rank 1
6755 23:22:15.330453 SW Impedance : PASS
6756 23:22:15.333762 DUTY Scan : NO K
6757 23:22:15.334392 ZQ Calibration : PASS
6758 23:22:15.336876 Jitter Meter : NO K
6759 23:22:15.340678 CBT Training : PASS
6760 23:22:15.341423 Write leveling : NO K
6761 23:22:15.344120 RX DQS gating : PASS
6762 23:22:15.347012 RX DQ/DQS(RDDQC) : PASS
6763 23:22:15.347613 TX DQ/DQS : PASS
6764 23:22:15.351086 RX DATLAT : PASS
6765 23:22:15.354103 RX DQ/DQS(Engine): PASS
6766 23:22:15.354560 TX OE : NO K
6767 23:22:15.354929 All Pass.
6768 23:22:15.356900
6769 23:22:15.357353 CH 1, Rank 0
6770 23:22:15.360173 SW Impedance : PASS
6771 23:22:15.360629 DUTY Scan : NO K
6772 23:22:15.363391 ZQ Calibration : PASS
6773 23:22:15.363851 Jitter Meter : NO K
6774 23:22:15.366951 CBT Training : PASS
6775 23:22:15.369813 Write leveling : PASS
6776 23:22:15.370268 RX DQS gating : PASS
6777 23:22:15.373099 RX DQ/DQS(RDDQC) : PASS
6778 23:22:15.376876 TX DQ/DQS : PASS
6779 23:22:15.377432 RX DATLAT : PASS
6780 23:22:15.379821 RX DQ/DQS(Engine): PASS
6781 23:22:15.383513 TX OE : NO K
6782 23:22:15.384066 All Pass.
6783 23:22:15.384435
6784 23:22:15.384830 CH 1, Rank 1
6785 23:22:15.386312 SW Impedance : PASS
6786 23:22:15.390261 DUTY Scan : NO K
6787 23:22:15.390812 ZQ Calibration : PASS
6788 23:22:15.393175 Jitter Meter : NO K
6789 23:22:15.396650 CBT Training : PASS
6790 23:22:15.397176 Write leveling : NO K
6791 23:22:15.399792 RX DQS gating : PASS
6792 23:22:15.403515 RX DQ/DQS(RDDQC) : PASS
6793 23:22:15.404093 TX DQ/DQS : PASS
6794 23:22:15.407377 RX DATLAT : PASS
6795 23:22:15.410450 RX DQ/DQS(Engine): PASS
6796 23:22:15.410923 TX OE : NO K
6797 23:22:15.413910 All Pass.
6798 23:22:15.414473
6799 23:22:15.414958 DramC Write-DBI off
6800 23:22:15.416552 PER_BANK_REFRESH: Hybrid Mode
6801 23:22:15.417106 TX_TRACKING: ON
6802 23:22:15.426282 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6803 23:22:15.429923 [FAST_K] Save calibration result to emmc
6804 23:22:15.433252 dramc_set_vcore_voltage set vcore to 725000
6805 23:22:15.436640 Read voltage for 1600, 0
6806 23:22:15.437166 Vio18 = 0
6807 23:22:15.439919 Vcore = 725000
6808 23:22:15.440482 Vdram = 0
6809 23:22:15.441021 Vddq = 0
6810 23:22:15.443191 Vmddr = 0
6811 23:22:15.446613 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6812 23:22:15.452806 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6813 23:22:15.453533 MEM_TYPE=3, freq_sel=13
6814 23:22:15.456056 sv_algorithm_assistance_LP4_3733
6815 23:22:15.462339 ============ PULL DRAM RESETB DOWN ============
6816 23:22:15.465637 ========== PULL DRAM RESETB DOWN end =========
6817 23:22:15.469099 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6818 23:22:15.472632 ===================================
6819 23:22:15.475352 LPDDR4 DRAM CONFIGURATION
6820 23:22:15.479712 ===================================
6821 23:22:15.479791 EX_ROW_EN[0] = 0x0
6822 23:22:15.482184 EX_ROW_EN[1] = 0x0
6823 23:22:15.485275 LP4Y_EN = 0x0
6824 23:22:15.485350 WORK_FSP = 0x1
6825 23:22:15.488907 WL = 0x5
6826 23:22:15.488985 RL = 0x5
6827 23:22:15.492258 BL = 0x2
6828 23:22:15.492332 RPST = 0x0
6829 23:22:15.495631 RD_PRE = 0x0
6830 23:22:15.495714 WR_PRE = 0x1
6831 23:22:15.498614 WR_PST = 0x1
6832 23:22:15.498703 DBI_WR = 0x0
6833 23:22:15.501860 DBI_RD = 0x0
6834 23:22:15.501949 OTF = 0x1
6835 23:22:15.505076 ===================================
6836 23:22:15.508338 ===================================
6837 23:22:15.512311 ANA top config
6838 23:22:15.514932 ===================================
6839 23:22:15.518290 DLL_ASYNC_EN = 0
6840 23:22:15.518474 ALL_SLAVE_EN = 0
6841 23:22:15.521572 NEW_RANK_MODE = 1
6842 23:22:15.525066 DLL_IDLE_MODE = 1
6843 23:22:15.528379 LP45_APHY_COMB_EN = 1
6844 23:22:15.528588 TX_ODT_DIS = 0
6845 23:22:15.532055 NEW_8X_MODE = 1
6846 23:22:15.534682 ===================================
6847 23:22:15.538247 ===================================
6848 23:22:15.542249 data_rate = 3200
6849 23:22:15.545099 CKR = 1
6850 23:22:15.548417 DQ_P2S_RATIO = 8
6851 23:22:15.552129 ===================================
6852 23:22:15.555271 CA_P2S_RATIO = 8
6853 23:22:15.555655 DQ_CA_OPEN = 0
6854 23:22:15.558462 DQ_SEMI_OPEN = 0
6855 23:22:15.561654 CA_SEMI_OPEN = 0
6856 23:22:15.565549 CA_FULL_RATE = 0
6857 23:22:15.568189 DQ_CKDIV4_EN = 0
6858 23:22:15.571688 CA_CKDIV4_EN = 0
6859 23:22:15.574714 CA_PREDIV_EN = 0
6860 23:22:15.575273 PH8_DLY = 12
6861 23:22:15.578583 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6862 23:22:15.581204 DQ_AAMCK_DIV = 4
6863 23:22:15.584802 CA_AAMCK_DIV = 4
6864 23:22:15.588874 CA_ADMCK_DIV = 4
6865 23:22:15.591309 DQ_TRACK_CA_EN = 0
6866 23:22:15.591765 CA_PICK = 1600
6867 23:22:15.594268 CA_MCKIO = 1600
6868 23:22:15.597501 MCKIO_SEMI = 0
6869 23:22:15.602150 PLL_FREQ = 3068
6870 23:22:15.604522 DQ_UI_PI_RATIO = 32
6871 23:22:15.608985 CA_UI_PI_RATIO = 0
6872 23:22:15.611567 ===================================
6873 23:22:15.614604 ===================================
6874 23:22:15.617388 memory_type:LPDDR4
6875 23:22:15.618077 GP_NUM : 10
6876 23:22:15.620751 SRAM_EN : 1
6877 23:22:15.621440 MD32_EN : 0
6878 23:22:15.624089 ===================================
6879 23:22:15.627513 [ANA_INIT] >>>>>>>>>>>>>>
6880 23:22:15.630593 <<<<<< [CONFIGURE PHASE]: ANA_TX
6881 23:22:15.634801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6882 23:22:15.637956 ===================================
6883 23:22:15.640434 data_rate = 3200,PCW = 0X7600
6884 23:22:15.644344 ===================================
6885 23:22:15.648478 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6886 23:22:15.654233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6887 23:22:15.657351 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6888 23:22:15.663791 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6889 23:22:15.666980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6890 23:22:15.670212 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6891 23:22:15.670638 [ANA_INIT] flow start
6892 23:22:15.673559 [ANA_INIT] PLL >>>>>>>>
6893 23:22:15.677165 [ANA_INIT] PLL <<<<<<<<
6894 23:22:15.677596 [ANA_INIT] MIDPI >>>>>>>>
6895 23:22:15.680636 [ANA_INIT] MIDPI <<<<<<<<
6896 23:22:15.684351 [ANA_INIT] DLL >>>>>>>>
6897 23:22:15.687028 [ANA_INIT] DLL <<<<<<<<
6898 23:22:15.687532 [ANA_INIT] flow end
6899 23:22:15.690096 ============ LP4 DIFF to SE enter ============
6900 23:22:15.696859 ============ LP4 DIFF to SE exit ============
6901 23:22:15.697295 [ANA_INIT] <<<<<<<<<<<<<
6902 23:22:15.700433 [Flow] Enable top DCM control >>>>>
6903 23:22:15.703228 [Flow] Enable top DCM control <<<<<
6904 23:22:15.706395 Enable DLL master slave shuffle
6905 23:22:15.713350 ==============================================================
6906 23:22:15.713787 Gating Mode config
6907 23:22:15.719911 ==============================================================
6908 23:22:15.723222 Config description:
6909 23:22:15.733183 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6910 23:22:15.739856 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6911 23:22:15.743203 SELPH_MODE 0: By rank 1: By Phase
6912 23:22:15.749727 ==============================================================
6913 23:22:15.753294 GAT_TRACK_EN = 1
6914 23:22:15.756330 RX_GATING_MODE = 2
6915 23:22:15.756787 RX_GATING_TRACK_MODE = 2
6916 23:22:15.759344 SELPH_MODE = 1
6917 23:22:15.762710 PICG_EARLY_EN = 1
6918 23:22:15.765965 VALID_LAT_VALUE = 1
6919 23:22:15.772943 ==============================================================
6920 23:22:15.775860 Enter into Gating configuration >>>>
6921 23:22:15.780535 Exit from Gating configuration <<<<
6922 23:22:15.782699 Enter into DVFS_PRE_config >>>>>
6923 23:22:15.792421 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6924 23:22:15.796034 Exit from DVFS_PRE_config <<<<<
6925 23:22:15.799598 Enter into PICG configuration >>>>
6926 23:22:15.802983 Exit from PICG configuration <<<<
6927 23:22:15.806151 [RX_INPUT] configuration >>>>>
6928 23:22:15.808999 [RX_INPUT] configuration <<<<<
6929 23:22:15.812596 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6930 23:22:15.819342 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6931 23:22:15.825758 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6932 23:22:15.832183 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6933 23:22:15.835547 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6934 23:22:15.842224 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6935 23:22:15.845983 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6936 23:22:15.852073 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6937 23:22:15.856513 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6938 23:22:15.858865 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6939 23:22:15.862252 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6940 23:22:15.868695 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6941 23:22:15.871974 ===================================
6942 23:22:15.875294 LPDDR4 DRAM CONFIGURATION
6943 23:22:15.878430 ===================================
6944 23:22:15.878851 EX_ROW_EN[0] = 0x0
6945 23:22:15.881575 EX_ROW_EN[1] = 0x0
6946 23:22:15.881994 LP4Y_EN = 0x0
6947 23:22:15.885367 WORK_FSP = 0x1
6948 23:22:15.885787 WL = 0x5
6949 23:22:15.888160 RL = 0x5
6950 23:22:15.888579 BL = 0x2
6951 23:22:15.891685 RPST = 0x0
6952 23:22:15.892099 RD_PRE = 0x0
6953 23:22:15.894691 WR_PRE = 0x1
6954 23:22:15.898301 WR_PST = 0x1
6955 23:22:15.898722 DBI_WR = 0x0
6956 23:22:15.902069 DBI_RD = 0x0
6957 23:22:15.902491 OTF = 0x1
6958 23:22:15.905326 ===================================
6959 23:22:15.908226 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6960 23:22:15.914888 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6961 23:22:15.917844 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6962 23:22:15.921896 ===================================
6963 23:22:15.924417 LPDDR4 DRAM CONFIGURATION
6964 23:22:15.927988 ===================================
6965 23:22:15.928409 EX_ROW_EN[0] = 0x10
6966 23:22:15.931268 EX_ROW_EN[1] = 0x0
6967 23:22:15.931688 LP4Y_EN = 0x0
6968 23:22:15.934359 WORK_FSP = 0x1
6969 23:22:15.934782 WL = 0x5
6970 23:22:15.937765 RL = 0x5
6971 23:22:15.938184 BL = 0x2
6972 23:22:15.941612 RPST = 0x0
6973 23:22:15.942032 RD_PRE = 0x0
6974 23:22:15.944667 WR_PRE = 0x1
6975 23:22:15.947826 WR_PST = 0x1
6976 23:22:15.948246 DBI_WR = 0x0
6977 23:22:15.951077 DBI_RD = 0x0
6978 23:22:15.951500 OTF = 0x1
6979 23:22:15.954003 ===================================
6980 23:22:15.960805 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6981 23:22:15.961232 ==
6982 23:22:15.965154 Dram Type= 6, Freq= 0, CH_0, rank 0
6983 23:22:15.969281 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6984 23:22:15.969707 ==
6985 23:22:15.972779 [Duty_Offset_Calibration]
6986 23:22:15.973208 B0:0 B1:2 CA:1
6987 23:22:15.975221
6988 23:22:15.977341 [DutyScan_Calibration_Flow] k_type=0
6989 23:22:15.985500
6990 23:22:15.985909 ==CLK 0==
6991 23:22:15.988775 Final CLK duty delay cell = 0
6992 23:22:15.991819 [0] MAX Duty = 5187%(X100), DQS PI = 24
6993 23:22:15.995458 [0] MIN Duty = 4938%(X100), DQS PI = 54
6994 23:22:15.998876 [0] AVG Duty = 5062%(X100)
6995 23:22:15.999289
6996 23:22:16.002217 CH0 CLK Duty spec in!! Max-Min= 249%
6997 23:22:16.005805 [DutyScan_Calibration_Flow] ====Done====
6998 23:22:16.006217
6999 23:22:16.008703 [DutyScan_Calibration_Flow] k_type=1
7000 23:22:16.025627
7001 23:22:16.026037 ==DQS 0 ==
7002 23:22:16.028739 Final DQS duty delay cell = 0
7003 23:22:16.032844 [0] MAX Duty = 5125%(X100), DQS PI = 2
7004 23:22:16.035916 [0] MIN Duty = 5031%(X100), DQS PI = 10
7005 23:22:16.039237 [0] AVG Duty = 5078%(X100)
7006 23:22:16.039649
7007 23:22:16.039977 ==DQS 1 ==
7008 23:22:16.042337 Final DQS duty delay cell = 0
7009 23:22:16.046076 [0] MAX Duty = 5031%(X100), DQS PI = 6
7010 23:22:16.049030 [0] MIN Duty = 4876%(X100), DQS PI = 18
7011 23:22:16.049444 [0] AVG Duty = 4953%(X100)
7012 23:22:16.052517
7013 23:22:16.055691 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7014 23:22:16.056104
7015 23:22:16.059270 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7016 23:22:16.062310 [DutyScan_Calibration_Flow] ====Done====
7017 23:22:16.062723
7018 23:22:16.065308 [DutyScan_Calibration_Flow] k_type=3
7019 23:22:16.083530
7020 23:22:16.083945 ==DQM 0 ==
7021 23:22:16.086054 Final DQM duty delay cell = 0
7022 23:22:16.089281 [0] MAX Duty = 5187%(X100), DQS PI = 22
7023 23:22:16.093319 [0] MIN Duty = 4907%(X100), DQS PI = 56
7024 23:22:16.093844 [0] AVG Duty = 5047%(X100)
7025 23:22:16.096150
7026 23:22:16.096575 ==DQM 1 ==
7027 23:22:16.099343 Final DQM duty delay cell = 0
7028 23:22:16.102899 [0] MAX Duty = 5031%(X100), DQS PI = 52
7029 23:22:16.105866 [0] MIN Duty = 4782%(X100), DQS PI = 14
7030 23:22:16.106298 [0] AVG Duty = 4906%(X100)
7031 23:22:16.109716
7032 23:22:16.113055 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7033 23:22:16.113484
7034 23:22:16.116860 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7035 23:22:16.119524 [DutyScan_Calibration_Flow] ====Done====
7036 23:22:16.119949
7037 23:22:16.122552 [DutyScan_Calibration_Flow] k_type=2
7038 23:22:16.139405
7039 23:22:16.139826 ==DQ 0 ==
7040 23:22:16.142997 Final DQ duty delay cell = 0
7041 23:22:16.145647 [0] MAX Duty = 5187%(X100), DQS PI = 18
7042 23:22:16.148827 [0] MIN Duty = 4938%(X100), DQS PI = 56
7043 23:22:16.152155 [0] AVG Duty = 5062%(X100)
7044 23:22:16.152581
7045 23:22:16.153054 ==DQ 1 ==
7046 23:22:16.156063 Final DQ duty delay cell = -4
7047 23:22:16.159825 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7048 23:22:16.161834 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7049 23:22:16.165530 [-4] AVG Duty = 4969%(X100)
7050 23:22:16.165957
7051 23:22:16.168821 CH0 DQ 0 Duty spec in!! Max-Min= 249%
7052 23:22:16.169247
7053 23:22:16.172320 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7054 23:22:16.175129 [DutyScan_Calibration_Flow] ====Done====
7055 23:22:16.175212 ==
7056 23:22:16.178183 Dram Type= 6, Freq= 0, CH_1, rank 0
7057 23:22:16.181696 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7058 23:22:16.181785 ==
7059 23:22:16.185115 [Duty_Offset_Calibration]
7060 23:22:16.185210 B0:0 B1:4 CA:-5
7061 23:22:16.185306
7062 23:22:16.188996 [DutyScan_Calibration_Flow] k_type=0
7063 23:22:16.199951
7064 23:22:16.200376 ==CLK 0==
7065 23:22:16.203493 Final CLK duty delay cell = 0
7066 23:22:16.208349 [0] MAX Duty = 5156%(X100), DQS PI = 20
7067 23:22:16.209467 [0] MIN Duty = 4875%(X100), DQS PI = 50
7068 23:22:16.212868 [0] AVG Duty = 5015%(X100)
7069 23:22:16.213296
7070 23:22:16.216840 CH1 CLK Duty spec in!! Max-Min= 281%
7071 23:22:16.219533 [DutyScan_Calibration_Flow] ====Done====
7072 23:22:16.219958
7073 23:22:16.222764 [DutyScan_Calibration_Flow] k_type=1
7074 23:22:16.239092
7075 23:22:16.239516 ==DQS 0 ==
7076 23:22:16.242364 Final DQS duty delay cell = 0
7077 23:22:16.245439 [0] MAX Duty = 5187%(X100), DQS PI = 20
7078 23:22:16.248786 [0] MIN Duty = 4876%(X100), DQS PI = 44
7079 23:22:16.252022 [0] AVG Duty = 5031%(X100)
7080 23:22:16.252533
7081 23:22:16.253011 ==DQS 1 ==
7082 23:22:16.255194 Final DQS duty delay cell = -4
7083 23:22:16.258473 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7084 23:22:16.262054 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7085 23:22:16.265169 [-4] AVG Duty = 4922%(X100)
7086 23:22:16.265596
7087 23:22:16.268240 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7088 23:22:16.268664
7089 23:22:16.271623 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7090 23:22:16.274814 [DutyScan_Calibration_Flow] ====Done====
7091 23:22:16.275238
7092 23:22:16.278493 [DutyScan_Calibration_Flow] k_type=3
7093 23:22:16.294960
7094 23:22:16.295373 ==DQM 0 ==
7095 23:22:16.297558 Final DQM duty delay cell = -4
7096 23:22:16.300874 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7097 23:22:16.304357 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7098 23:22:16.307969 [-4] AVG Duty = 4922%(X100)
7099 23:22:16.308380
7100 23:22:16.308734 ==DQM 1 ==
7101 23:22:16.311767 Final DQM duty delay cell = -4
7102 23:22:16.314684 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7103 23:22:16.317372 [-4] MIN Duty = 4907%(X100), DQS PI = 32
7104 23:22:16.320930 [-4] AVG Duty = 4984%(X100)
7105 23:22:16.321340
7106 23:22:16.324401 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7107 23:22:16.324973
7108 23:22:16.327185 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7109 23:22:16.330634 [DutyScan_Calibration_Flow] ====Done====
7110 23:22:16.331044
7111 23:22:16.334212 [DutyScan_Calibration_Flow] k_type=2
7112 23:22:16.352256
7113 23:22:16.352941 ==DQ 0 ==
7114 23:22:16.354949 Final DQ duty delay cell = 0
7115 23:22:16.359373 [0] MAX Duty = 5093%(X100), DQS PI = 18
7116 23:22:16.362267 [0] MIN Duty = 4938%(X100), DQS PI = 46
7117 23:22:16.362698 [0] AVG Duty = 5015%(X100)
7118 23:22:16.365183
7119 23:22:16.365596 ==DQ 1 ==
7120 23:22:16.368484 Final DQ duty delay cell = 0
7121 23:22:16.371796 [0] MAX Duty = 5031%(X100), DQS PI = 4
7122 23:22:16.374887 [0] MIN Duty = 4907%(X100), DQS PI = 14
7123 23:22:16.375301 [0] AVG Duty = 4969%(X100)
7124 23:22:16.375631
7125 23:22:16.378459 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7126 23:22:16.382647
7127 23:22:16.385331 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7128 23:22:16.388810 [DutyScan_Calibration_Flow] ====Done====
7129 23:22:16.391674 nWR fixed to 30
7130 23:22:16.392089 [ModeRegInit_LP4] CH0 RK0
7131 23:22:16.394824 [ModeRegInit_LP4] CH0 RK1
7132 23:22:16.398194 [ModeRegInit_LP4] CH1 RK0
7133 23:22:16.398607 [ModeRegInit_LP4] CH1 RK1
7134 23:22:16.402055 match AC timing 4
7135 23:22:16.405370 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7136 23:22:16.411654 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7137 23:22:16.414837 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7138 23:22:16.422268 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7139 23:22:16.425060 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7140 23:22:16.425474 [MiockJmeterHQA]
7141 23:22:16.425799
7142 23:22:16.428673 [DramcMiockJmeter] u1RxGatingPI = 0
7143 23:22:16.431597 0 : 4363, 4138
7144 23:22:16.432017 4 : 4252, 4027
7145 23:22:16.432352 8 : 4363, 4140
7146 23:22:16.435338 12 : 4253, 4026
7147 23:22:16.435771 16 : 4252, 4027
7148 23:22:16.438507 20 : 4364, 4137
7149 23:22:16.438944 24 : 4361, 4137
7150 23:22:16.441675 28 : 4253, 4027
7151 23:22:16.442092 32 : 4250, 4027
7152 23:22:16.444851 36 : 4252, 4029
7153 23:22:16.445276 40 : 4363, 4138
7154 23:22:16.445609 44 : 4250, 4027
7155 23:22:16.447562 48 : 4361, 4137
7156 23:22:16.447979 52 : 4250, 4027
7157 23:22:16.451360 56 : 4250, 4027
7158 23:22:16.451775 60 : 4250, 4027
7159 23:22:16.454488 64 : 4250, 4027
7160 23:22:16.454908 68 : 4361, 4137
7161 23:22:16.458566 72 : 4250, 4026
7162 23:22:16.458981 76 : 4360, 4138
7163 23:22:16.459315 80 : 4250, 4027
7164 23:22:16.460883 84 : 4250, 4027
7165 23:22:16.461301 88 : 4250, 4027
7166 23:22:16.464227 92 : 4361, 4138
7167 23:22:16.464648 96 : 4250, 4027
7168 23:22:16.468865 100 : 4361, 1360
7169 23:22:16.469286 104 : 4360, 0
7170 23:22:16.469621 108 : 4250, 0
7171 23:22:16.471232 112 : 4250, 0
7172 23:22:16.471649 116 : 4250, 0
7173 23:22:16.474072 120 : 4361, 0
7174 23:22:16.474491 124 : 4360, 0
7175 23:22:16.474846 128 : 4250, 0
7176 23:22:16.477370 132 : 4250, 0
7177 23:22:16.477999 136 : 4250, 0
7178 23:22:16.481239 140 : 4250, 0
7179 23:22:16.481661 144 : 4250, 0
7180 23:22:16.481997 148 : 4249, 0
7181 23:22:16.484583 152 : 4252, 0
7182 23:22:16.485047 156 : 4361, 0
7183 23:22:16.487539 160 : 4360, 0
7184 23:22:16.487957 164 : 4247, 0
7185 23:22:16.488295 168 : 4250, 0
7186 23:22:16.490828 172 : 4361, 0
7187 23:22:16.491249 176 : 4360, 0
7188 23:22:16.494036 180 : 4250, 0
7189 23:22:16.494455 184 : 4250, 0
7190 23:22:16.494788 188 : 4250, 0
7191 23:22:16.497317 192 : 4250, 0
7192 23:22:16.497736 196 : 4250, 0
7193 23:22:16.501324 200 : 4250, 0
7194 23:22:16.501744 204 : 4250, 0
7195 23:22:16.502075 208 : 4360, 0
7196 23:22:16.504094 212 : 4361, 0
7197 23:22:16.504510 216 : 4247, 0
7198 23:22:16.507481 220 : 4250, 1076
7199 23:22:16.507898 224 : 4250, 4027
7200 23:22:16.508230 228 : 4250, 4027
7201 23:22:16.510944 232 : 4360, 4137
7202 23:22:16.511362 236 : 4361, 4137
7203 23:22:16.514147 240 : 4247, 4024
7204 23:22:16.514565 244 : 4360, 4138
7205 23:22:16.517674 248 : 4361, 4137
7206 23:22:16.518093 252 : 4250, 4027
7207 23:22:16.520952 256 : 4250, 4027
7208 23:22:16.521392 260 : 4250, 4027
7209 23:22:16.524601 264 : 4250, 4027
7210 23:22:16.525065 268 : 4250, 4027
7211 23:22:16.528530 272 : 4250, 4027
7212 23:22:16.528995 276 : 4250, 4027
7213 23:22:16.531002 280 : 4250, 4027
7214 23:22:16.531467 284 : 4361, 4137
7215 23:22:16.533949 288 : 4361, 4138
7216 23:22:16.534367 292 : 4247, 4024
7217 23:22:16.534703 296 : 4360, 4138
7218 23:22:16.537521 300 : 4361, 4137
7219 23:22:16.538054 304 : 4250, 4027
7220 23:22:16.540939 308 : 4250, 4027
7221 23:22:16.541372 312 : 4250, 4027
7222 23:22:16.544815 316 : 4250, 4027
7223 23:22:16.545251 320 : 4250, 4027
7224 23:22:16.547392 324 : 4250, 4027
7225 23:22:16.547826 328 : 4250, 4027
7226 23:22:16.550231 332 : 4250, 4027
7227 23:22:16.550667 336 : 4361, 3358
7228 23:22:16.553930 340 : 4361, 897
7229 23:22:16.554602
7230 23:22:16.555037 MIOCK jitter meter ch=0
7231 23:22:16.555466
7232 23:22:16.556660 1T = (340-100) = 240 dly cells
7233 23:22:16.563396 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7234 23:22:16.563480 ==
7235 23:22:16.567026 Dram Type= 6, Freq= 0, CH_0, rank 0
7236 23:22:16.569886 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7237 23:22:16.569970 ==
7238 23:22:16.576967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7239 23:22:16.581053 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7240 23:22:16.583238 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7241 23:22:16.590027 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7242 23:22:16.598752 [CA 0] Center 41 (11~72) winsize 62
7243 23:22:16.601680 [CA 1] Center 41 (11~72) winsize 62
7244 23:22:16.605206 [CA 2] Center 37 (7~67) winsize 61
7245 23:22:16.609213 [CA 3] Center 37 (7~67) winsize 61
7246 23:22:16.611981 [CA 4] Center 35 (5~66) winsize 62
7247 23:22:16.615171 [CA 5] Center 35 (5~65) winsize 61
7248 23:22:16.615250
7249 23:22:16.618957 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7250 23:22:16.619038
7251 23:22:16.621763 [CATrainingPosCal] consider 1 rank data
7252 23:22:16.624911 u2DelayCellTimex100 = 271/100 ps
7253 23:22:16.628636 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7254 23:22:16.635179 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7255 23:22:16.638579 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7256 23:22:16.641438 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7257 23:22:16.644743 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7258 23:22:16.648222 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7259 23:22:16.648302
7260 23:22:16.651828 CA PerBit enable=1, Macro0, CA PI delay=35
7261 23:22:16.651908
7262 23:22:16.654905 [CBTSetCACLKResult] CA Dly = 35
7263 23:22:16.658089 CS Dly: 11 (0~42)
7264 23:22:16.661680 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7265 23:22:16.664766 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7266 23:22:16.664846 ==
7267 23:22:16.668051 Dram Type= 6, Freq= 0, CH_0, rank 1
7268 23:22:16.671802 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7269 23:22:16.675377 ==
7270 23:22:16.679089 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7271 23:22:16.681584 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7272 23:22:16.688984 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7273 23:22:16.694453 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7274 23:22:16.701681 [CA 0] Center 42 (12~73) winsize 62
7275 23:22:16.704509 [CA 1] Center 41 (11~72) winsize 62
7276 23:22:16.708176 [CA 2] Center 38 (8~68) winsize 61
7277 23:22:16.711233 [CA 3] Center 37 (7~67) winsize 61
7278 23:22:16.714122 [CA 4] Center 35 (5~65) winsize 61
7279 23:22:16.717728 [CA 5] Center 35 (5~66) winsize 62
7280 23:22:16.717808
7281 23:22:16.721422 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7282 23:22:16.721501
7283 23:22:16.728589 [CATrainingPosCal] consider 2 rank data
7284 23:22:16.729051 u2DelayCellTimex100 = 271/100 ps
7285 23:22:16.734531 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7286 23:22:16.737895 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7287 23:22:16.741881 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7288 23:22:16.744333 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7289 23:22:16.747579 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7290 23:22:16.752827 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7291 23:22:16.753255
7292 23:22:16.754845 CA PerBit enable=1, Macro0, CA PI delay=35
7293 23:22:16.755272
7294 23:22:16.757317 [CBTSetCACLKResult] CA Dly = 35
7295 23:22:16.760489 CS Dly: 11 (0~43)
7296 23:22:16.764192 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7297 23:22:16.767087 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7298 23:22:16.767507
7299 23:22:16.770892 ----->DramcWriteLeveling(PI) begin...
7300 23:22:16.771318 ==
7301 23:22:16.773735 Dram Type= 6, Freq= 0, CH_0, rank 0
7302 23:22:16.781827 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7303 23:22:16.782279 ==
7304 23:22:16.783883 Write leveling (Byte 0): 32 => 32
7305 23:22:16.787409 Write leveling (Byte 1): 28 => 28
7306 23:22:16.787827 DramcWriteLeveling(PI) end<-----
7307 23:22:16.788160
7308 23:22:16.790815 ==
7309 23:22:16.793932 Dram Type= 6, Freq= 0, CH_0, rank 0
7310 23:22:16.797401 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7311 23:22:16.797826 ==
7312 23:22:16.800055 [Gating] SW mode calibration
7313 23:22:16.807127 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7314 23:22:16.810460 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7315 23:22:16.817260 0 12 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7316 23:22:16.820476 0 12 4 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
7317 23:22:16.824833 0 12 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7318 23:22:16.831196 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7319 23:22:16.834081 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7320 23:22:16.837098 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7321 23:22:16.843705 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7322 23:22:16.847393 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7323 23:22:16.850299 0 13 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
7324 23:22:16.856670 0 13 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
7325 23:22:16.860015 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7326 23:22:16.863398 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7327 23:22:16.870096 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7328 23:22:16.873717 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7329 23:22:16.876478 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7330 23:22:16.883412 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7331 23:22:16.886753 0 14 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7332 23:22:16.889630 0 14 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7333 23:22:16.896592 0 14 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7334 23:22:16.899482 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7335 23:22:16.903524 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7336 23:22:16.909387 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7337 23:22:16.912948 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7338 23:22:16.916184 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7339 23:22:16.922966 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7340 23:22:16.926255 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7341 23:22:16.929714 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7342 23:22:16.935950 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 23:22:16.939704 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 23:22:16.942972 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 23:22:16.949436 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 23:22:16.952988 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 23:22:16.956856 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 23:22:16.962709 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 23:22:16.966491 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 23:22:16.969103 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 23:22:16.975739 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 23:22:16.979075 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 23:22:16.982384 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 23:22:16.989019 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7355 23:22:16.992345 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7356 23:22:16.996346 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7357 23:22:17.002243 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7358 23:22:17.002668 Total UI for P1: 0, mck2ui 16
7359 23:22:17.009035 best dqsien dly found for B0: ( 1, 1, 0)
7360 23:22:17.011912 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7361 23:22:17.015568 Total UI for P1: 0, mck2ui 16
7362 23:22:17.019213 best dqsien dly found for B1: ( 1, 1, 6)
7363 23:22:17.022034 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7364 23:22:17.025311 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7365 23:22:17.025393
7366 23:22:17.028790 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7367 23:22:17.032466 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7368 23:22:17.035232 [Gating] SW calibration Done
7369 23:22:17.035314 ==
7370 23:22:17.038390 Dram Type= 6, Freq= 0, CH_0, rank 0
7371 23:22:17.041777 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7372 23:22:17.041860 ==
7373 23:22:17.044883 RX Vref Scan: 0
7374 23:22:17.044964
7375 23:22:17.048763 RX Vref 0 -> 0, step: 1
7376 23:22:17.048844
7377 23:22:17.048910 RX Delay 0 -> 252, step: 8
7378 23:22:17.055032 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7379 23:22:17.058057 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7380 23:22:17.061552 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7381 23:22:17.064817 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7382 23:22:17.067952 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7383 23:22:17.074520 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7384 23:22:17.078253 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7385 23:22:17.081879 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7386 23:22:17.085192 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7387 23:22:17.087916 iDelay=200, Bit 9, Center 103 (48 ~ 159) 112
7388 23:22:17.095112 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7389 23:22:17.097407 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7390 23:22:17.100915 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7391 23:22:17.104905 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7392 23:22:17.107628 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7393 23:22:17.113968 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7394 23:22:17.114050 ==
7395 23:22:17.117319 Dram Type= 6, Freq= 0, CH_0, rank 0
7396 23:22:17.120958 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7397 23:22:17.121040 ==
7398 23:22:17.121106 DQS Delay:
7399 23:22:17.124051 DQS0 = 0, DQS1 = 0
7400 23:22:17.124132 DQM Delay:
7401 23:22:17.127252 DQM0 = 130, DQM1 = 124
7402 23:22:17.127334 DQ Delay:
7403 23:22:17.130575 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7404 23:22:17.134283 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7405 23:22:17.137597 DQ8 =115, DQ9 =103, DQ10 =123, DQ11 =115
7406 23:22:17.144006 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7407 23:22:17.144087
7408 23:22:17.144151
7409 23:22:17.144211 ==
7410 23:22:17.146985 Dram Type= 6, Freq= 0, CH_0, rank 0
7411 23:22:17.150756 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7412 23:22:17.150838 ==
7413 23:22:17.150904
7414 23:22:17.150964
7415 23:22:17.154206 TX Vref Scan disable
7416 23:22:17.154288 == TX Byte 0 ==
7417 23:22:17.160643 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7418 23:22:17.163790 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7419 23:22:17.163871 == TX Byte 1 ==
7420 23:22:17.170520 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7421 23:22:17.174629 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7422 23:22:17.174711 ==
7423 23:22:17.177290 Dram Type= 6, Freq= 0, CH_0, rank 0
7424 23:22:17.180436 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7425 23:22:17.180518 ==
7426 23:22:17.194759
7427 23:22:17.197858 TX Vref early break, caculate TX vref
7428 23:22:17.201064 TX Vref=16, minBit 8, minWin=22, winSum=377
7429 23:22:17.204258 TX Vref=18, minBit 9, minWin=23, winSum=391
7430 23:22:17.208110 TX Vref=20, minBit 8, minWin=23, winSum=389
7431 23:22:17.210749 TX Vref=22, minBit 8, minWin=23, winSum=402
7432 23:22:17.214645 TX Vref=24, minBit 9, minWin=24, winSum=411
7433 23:22:17.220667 TX Vref=26, minBit 3, minWin=25, winSum=417
7434 23:22:17.223802 TX Vref=28, minBit 8, minWin=25, winSum=422
7435 23:22:17.228050 TX Vref=30, minBit 8, minWin=24, winSum=414
7436 23:22:17.230661 TX Vref=32, minBit 3, minWin=24, winSum=413
7437 23:22:17.233952 TX Vref=34, minBit 3, minWin=23, winSum=395
7438 23:22:17.240962 [TxChooseVref] Worse bit 8, Min win 25, Win sum 422, Final Vref 28
7439 23:22:17.241045
7440 23:22:17.243775 Final TX Range 0 Vref 28
7441 23:22:17.243857
7442 23:22:17.243922 ==
7443 23:22:17.247154 Dram Type= 6, Freq= 0, CH_0, rank 0
7444 23:22:17.250427 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7445 23:22:17.250509 ==
7446 23:22:17.250573
7447 23:22:17.250633
7448 23:22:17.254182 TX Vref Scan disable
7449 23:22:17.259916 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7450 23:22:17.259998 == TX Byte 0 ==
7451 23:22:17.263663 u2DelayCellOfst[0]=14 cells (4 PI)
7452 23:22:17.266594 u2DelayCellOfst[1]=18 cells (5 PI)
7453 23:22:17.270602 u2DelayCellOfst[2]=14 cells (4 PI)
7454 23:22:17.273740 u2DelayCellOfst[3]=10 cells (3 PI)
7455 23:22:17.276364 u2DelayCellOfst[4]=10 cells (3 PI)
7456 23:22:17.279836 u2DelayCellOfst[5]=0 cells (0 PI)
7457 23:22:17.283180 u2DelayCellOfst[6]=18 cells (5 PI)
7458 23:22:17.286687 u2DelayCellOfst[7]=18 cells (5 PI)
7459 23:22:17.289591 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7460 23:22:17.292974 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7461 23:22:17.296605 == TX Byte 1 ==
7462 23:22:17.300525 u2DelayCellOfst[8]=0 cells (0 PI)
7463 23:22:17.303468 u2DelayCellOfst[9]=0 cells (0 PI)
7464 23:22:17.306722 u2DelayCellOfst[10]=7 cells (2 PI)
7465 23:22:17.306804 u2DelayCellOfst[11]=3 cells (1 PI)
7466 23:22:17.309899 u2DelayCellOfst[12]=14 cells (4 PI)
7467 23:22:17.312934 u2DelayCellOfst[13]=14 cells (4 PI)
7468 23:22:17.316304 u2DelayCellOfst[14]=18 cells (5 PI)
7469 23:22:17.319993 u2DelayCellOfst[15]=14 cells (4 PI)
7470 23:22:17.326420 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7471 23:22:17.329414 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7472 23:22:17.329496 DramC Write-DBI on
7473 23:22:17.329562 ==
7474 23:22:17.333104 Dram Type= 6, Freq= 0, CH_0, rank 0
7475 23:22:17.339688 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7476 23:22:17.339770 ==
7477 23:22:17.339835
7478 23:22:17.339940
7479 23:22:17.342423 TX Vref Scan disable
7480 23:22:17.342505 == TX Byte 0 ==
7481 23:22:17.349310 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
7482 23:22:17.349391 == TX Byte 1 ==
7483 23:22:17.352735 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7484 23:22:17.356021 DramC Write-DBI off
7485 23:22:17.356103
7486 23:22:17.356167 [DATLAT]
7487 23:22:17.358862 Freq=1600, CH0 RK0
7488 23:22:17.358943
7489 23:22:17.359008 DATLAT Default: 0xf
7490 23:22:17.362401 0, 0xFFFF, sum = 0
7491 23:22:17.362485 1, 0xFFFF, sum = 0
7492 23:22:17.365819 2, 0xFFFF, sum = 0
7493 23:22:17.365902 3, 0xFFFF, sum = 0
7494 23:22:17.369043 4, 0xFFFF, sum = 0
7495 23:22:17.369126 5, 0xFFFF, sum = 0
7496 23:22:17.372591 6, 0xFFFF, sum = 0
7497 23:22:17.375876 7, 0xFFFF, sum = 0
7498 23:22:17.375959 8, 0xFFFF, sum = 0
7499 23:22:17.378925 9, 0xFFFF, sum = 0
7500 23:22:17.379008 10, 0xFFFF, sum = 0
7501 23:22:17.383308 11, 0xFFFF, sum = 0
7502 23:22:17.383392 12, 0xFFF, sum = 0
7503 23:22:17.385429 13, 0x0, sum = 1
7504 23:22:17.385512 14, 0x0, sum = 2
7505 23:22:17.388783 15, 0x0, sum = 3
7506 23:22:17.388867 16, 0x0, sum = 4
7507 23:22:17.392106 best_step = 14
7508 23:22:17.392187
7509 23:22:17.392251 ==
7510 23:22:17.395407 Dram Type= 6, Freq= 0, CH_0, rank 0
7511 23:22:17.398154 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7512 23:22:17.398236 ==
7513 23:22:17.398301 RX Vref Scan: 1
7514 23:22:17.401769
7515 23:22:17.401850 Set Vref Range= 24 -> 127
7516 23:22:17.401914
7517 23:22:17.405409 RX Vref 24 -> 127, step: 1
7518 23:22:17.405490
7519 23:22:17.408329 RX Delay 3 -> 252, step: 4
7520 23:22:17.408411
7521 23:22:17.411941 Set Vref, RX VrefLevel [Byte0]: 24
7522 23:22:17.416330 [Byte1]: 24
7523 23:22:17.416412
7524 23:22:17.418582 Set Vref, RX VrefLevel [Byte0]: 25
7525 23:22:17.422550 [Byte1]: 25
7526 23:22:17.422632
7527 23:22:17.424964 Set Vref, RX VrefLevel [Byte0]: 26
7528 23:22:17.428768 [Byte1]: 26
7529 23:22:17.432533
7530 23:22:17.432618 Set Vref, RX VrefLevel [Byte0]: 27
7531 23:22:17.435875 [Byte1]: 27
7532 23:22:17.440341
7533 23:22:17.440423 Set Vref, RX VrefLevel [Byte0]: 28
7534 23:22:17.443474 [Byte1]: 28
7535 23:22:17.447463
7536 23:22:17.447544 Set Vref, RX VrefLevel [Byte0]: 29
7537 23:22:17.450709 [Byte1]: 29
7538 23:22:17.455376
7539 23:22:17.455457 Set Vref, RX VrefLevel [Byte0]: 30
7540 23:22:17.458441 [Byte1]: 30
7541 23:22:17.463539
7542 23:22:17.463620 Set Vref, RX VrefLevel [Byte0]: 31
7543 23:22:17.466478 [Byte1]: 31
7544 23:22:17.471153
7545 23:22:17.471234 Set Vref, RX VrefLevel [Byte0]: 32
7546 23:22:17.474384 [Byte1]: 32
7547 23:22:17.478696
7548 23:22:17.478789 Set Vref, RX VrefLevel [Byte0]: 33
7549 23:22:17.481861 [Byte1]: 33
7550 23:22:17.485953
7551 23:22:17.486054 Set Vref, RX VrefLevel [Byte0]: 34
7552 23:22:17.488966 [Byte1]: 34
7553 23:22:17.494198
7554 23:22:17.494319 Set Vref, RX VrefLevel [Byte0]: 35
7555 23:22:17.497348 [Byte1]: 35
7556 23:22:17.501439
7557 23:22:17.501576 Set Vref, RX VrefLevel [Byte0]: 36
7558 23:22:17.504418 [Byte1]: 36
7559 23:22:17.509142
7560 23:22:17.509566 Set Vref, RX VrefLevel [Byte0]: 37
7561 23:22:17.512353 [Byte1]: 37
7562 23:22:17.517249
7563 23:22:17.517675 Set Vref, RX VrefLevel [Byte0]: 38
7564 23:22:17.519970 [Byte1]: 38
7565 23:22:17.523801
7566 23:22:17.523884 Set Vref, RX VrefLevel [Byte0]: 39
7567 23:22:17.527479 [Byte1]: 39
7568 23:22:17.531645
7569 23:22:17.531728 Set Vref, RX VrefLevel [Byte0]: 40
7570 23:22:17.534915 [Byte1]: 40
7571 23:22:17.539344
7572 23:22:17.539426 Set Vref, RX VrefLevel [Byte0]: 41
7573 23:22:17.542548 [Byte1]: 41
7574 23:22:17.547617
7575 23:22:17.547699 Set Vref, RX VrefLevel [Byte0]: 42
7576 23:22:17.550815 [Byte1]: 42
7577 23:22:17.555216
7578 23:22:17.555298 Set Vref, RX VrefLevel [Byte0]: 43
7579 23:22:17.558129 [Byte1]: 43
7580 23:22:17.562974
7581 23:22:17.563056 Set Vref, RX VrefLevel [Byte0]: 44
7582 23:22:17.565707 [Byte1]: 44
7583 23:22:17.570752
7584 23:22:17.570835 Set Vref, RX VrefLevel [Byte0]: 45
7585 23:22:17.573711 [Byte1]: 45
7586 23:22:17.577508
7587 23:22:17.577591 Set Vref, RX VrefLevel [Byte0]: 46
7588 23:22:17.581485 [Byte1]: 46
7589 23:22:17.585483
7590 23:22:17.585567 Set Vref, RX VrefLevel [Byte0]: 47
7591 23:22:17.589886 [Byte1]: 47
7592 23:22:17.593165
7593 23:22:17.593253 Set Vref, RX VrefLevel [Byte0]: 48
7594 23:22:17.596830 [Byte1]: 48
7595 23:22:17.600970
7596 23:22:17.601053 Set Vref, RX VrefLevel [Byte0]: 49
7597 23:22:17.604250 [Byte1]: 49
7598 23:22:17.608914
7599 23:22:17.608996 Set Vref, RX VrefLevel [Byte0]: 50
7600 23:22:17.611714 [Byte1]: 50
7601 23:22:17.616680
7602 23:22:17.616768 Set Vref, RX VrefLevel [Byte0]: 51
7603 23:22:17.619234 [Byte1]: 51
7604 23:22:17.623482
7605 23:22:17.623563 Set Vref, RX VrefLevel [Byte0]: 52
7606 23:22:17.627887 [Byte1]: 52
7607 23:22:17.631576
7608 23:22:17.631658 Set Vref, RX VrefLevel [Byte0]: 53
7609 23:22:17.634790 [Byte1]: 53
7610 23:22:17.639628
7611 23:22:17.639710 Set Vref, RX VrefLevel [Byte0]: 54
7612 23:22:17.642195 [Byte1]: 54
7613 23:22:17.647444
7614 23:22:17.647527 Set Vref, RX VrefLevel [Byte0]: 55
7615 23:22:17.649712 [Byte1]: 55
7616 23:22:17.654097
7617 23:22:17.654179 Set Vref, RX VrefLevel [Byte0]: 56
7618 23:22:17.657592 [Byte1]: 56
7619 23:22:17.661937
7620 23:22:17.662019 Set Vref, RX VrefLevel [Byte0]: 57
7621 23:22:17.665092 [Byte1]: 57
7622 23:22:17.669501
7623 23:22:17.669585 Set Vref, RX VrefLevel [Byte0]: 58
7624 23:22:17.673656 [Byte1]: 58
7625 23:22:17.678292
7626 23:22:17.678374 Set Vref, RX VrefLevel [Byte0]: 59
7627 23:22:17.680757 [Byte1]: 59
7628 23:22:17.685259
7629 23:22:17.685341 Set Vref, RX VrefLevel [Byte0]: 60
7630 23:22:17.688316 [Byte1]: 60
7631 23:22:17.692614
7632 23:22:17.692695 Set Vref, RX VrefLevel [Byte0]: 61
7633 23:22:17.696365 [Byte1]: 61
7634 23:22:17.700344
7635 23:22:17.700425 Set Vref, RX VrefLevel [Byte0]: 62
7636 23:22:17.703589 [Byte1]: 62
7637 23:22:17.708632
7638 23:22:17.708737 Set Vref, RX VrefLevel [Byte0]: 63
7639 23:22:17.711123 [Byte1]: 63
7640 23:22:17.715339
7641 23:22:17.715420 Set Vref, RX VrefLevel [Byte0]: 64
7642 23:22:17.719488 [Byte1]: 64
7643 23:22:17.723266
7644 23:22:17.723347 Set Vref, RX VrefLevel [Byte0]: 65
7645 23:22:17.727371 [Byte1]: 65
7646 23:22:17.730952
7647 23:22:17.731033 Set Vref, RX VrefLevel [Byte0]: 66
7648 23:22:17.734049 [Byte1]: 66
7649 23:22:17.739226
7650 23:22:17.739307 Set Vref, RX VrefLevel [Byte0]: 67
7651 23:22:17.745197 [Byte1]: 67
7652 23:22:17.745278
7653 23:22:17.748597 Set Vref, RX VrefLevel [Byte0]: 68
7654 23:22:17.751784 [Byte1]: 68
7655 23:22:17.751866
7656 23:22:17.754712 Set Vref, RX VrefLevel [Byte0]: 69
7657 23:22:17.759688 [Byte1]: 69
7658 23:22:17.761261
7659 23:22:17.761346 Set Vref, RX VrefLevel [Byte0]: 70
7660 23:22:17.764855 [Byte1]: 70
7661 23:22:17.769660
7662 23:22:17.769741 Set Vref, RX VrefLevel [Byte0]: 71
7663 23:22:17.772192 [Byte1]: 71
7664 23:22:17.776487
7665 23:22:17.776569 Final RX Vref Byte 0 = 51 to rank0
7666 23:22:17.779968 Final RX Vref Byte 1 = 55 to rank0
7667 23:22:17.783261 Final RX Vref Byte 0 = 51 to rank1
7668 23:22:17.786361 Final RX Vref Byte 1 = 55 to rank1==
7669 23:22:17.790120 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 23:22:17.796610 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7671 23:22:17.796711 ==
7672 23:22:17.796784 DQS Delay:
7673 23:22:17.796849 DQS0 = 0, DQS1 = 0
7674 23:22:17.799922 DQM Delay:
7675 23:22:17.800103 DQM0 = 126, DQM1 = 121
7676 23:22:17.803187 DQ Delay:
7677 23:22:17.806798 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7678 23:22:17.809676 DQ4 =130, DQ5 =116, DQ6 =136, DQ7 =134
7679 23:22:17.813421 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7680 23:22:17.816486 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7681 23:22:17.816660
7682 23:22:17.816790
7683 23:22:17.816897
7684 23:22:17.819900 [DramC_TX_OE_Calibration] TA2
7685 23:22:17.823423 Original DQ_B0 (3 6) =30, OEN = 27
7686 23:22:17.826467 Original DQ_B1 (3 6) =30, OEN = 27
7687 23:22:17.829786 24, 0x0, End_B0=24 End_B1=24
7688 23:22:17.829963 25, 0x0, End_B0=25 End_B1=25
7689 23:22:17.832684 26, 0x0, End_B0=26 End_B1=26
7690 23:22:17.835930 27, 0x0, End_B0=27 End_B1=27
7691 23:22:17.839766 28, 0x0, End_B0=28 End_B1=28
7692 23:22:17.842741 29, 0x0, End_B0=29 End_B1=29
7693 23:22:17.842825 30, 0x0, End_B0=30 End_B1=30
7694 23:22:17.846109 31, 0x4545, End_B0=30 End_B1=30
7695 23:22:17.849188 Byte0 end_step=30 best_step=27
7696 23:22:17.853538 Byte1 end_step=30 best_step=27
7697 23:22:17.856524 Byte0 TX OE(2T, 0.5T) = (3, 3)
7698 23:22:17.859516 Byte1 TX OE(2T, 0.5T) = (3, 3)
7699 23:22:17.859605
7700 23:22:17.859674
7701 23:22:17.867126 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
7702 23:22:17.870295 CH0 RK0: MR19=303, MR18=1717
7703 23:22:17.876396 CH0_RK0: MR19=0x303, MR18=0x1717, DQSOSC=398, MR23=63, INC=23, DEC=15
7704 23:22:17.876863
7705 23:22:17.880196 ----->DramcWriteLeveling(PI) begin...
7706 23:22:17.880639 ==
7707 23:22:17.883469 Dram Type= 6, Freq= 0, CH_0, rank 1
7708 23:22:17.886811 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7709 23:22:17.887251 ==
7710 23:22:17.889464 Write leveling (Byte 0): 29 => 29
7711 23:22:17.892785 Write leveling (Byte 1): 27 => 27
7712 23:22:17.896450 DramcWriteLeveling(PI) end<-----
7713 23:22:17.896913
7714 23:22:17.897252 ==
7715 23:22:17.899815 Dram Type= 6, Freq= 0, CH_0, rank 1
7716 23:22:17.902650 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7717 23:22:17.903090 ==
7718 23:22:17.906281 [Gating] SW mode calibration
7719 23:22:17.912605 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7720 23:22:17.919245 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7721 23:22:17.922809 0 12 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7722 23:22:17.928938 0 12 4 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
7723 23:22:17.932353 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7724 23:22:17.936363 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7725 23:22:17.942598 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7726 23:22:17.946505 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7727 23:22:17.948913 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7728 23:22:17.956090 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7729 23:22:17.958857 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
7730 23:22:17.962466 0 13 4 | B1->B0 | 3131 2323 | 0 0 | (0 1) (1 0)
7731 23:22:17.969552 0 13 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
7732 23:22:17.972767 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7733 23:22:17.975975 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7734 23:22:17.982339 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7735 23:22:17.985411 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7736 23:22:17.989013 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7737 23:22:17.995687 0 14 0 | B1->B0 | 2727 4343 | 0 0 | (0 0) (0 0)
7738 23:22:17.999703 0 14 4 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7739 23:22:18.002793 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7740 23:22:18.008982 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7741 23:22:18.012610 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7742 23:22:18.015471 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7743 23:22:18.023471 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7744 23:22:18.025312 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7745 23:22:18.029204 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7746 23:22:18.034942 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7747 23:22:18.038411 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 23:22:18.042033 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 23:22:18.048199 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 23:22:18.052182 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 23:22:18.055813 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 23:22:18.061995 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 23:22:18.064580 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 23:22:18.068097 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 23:22:18.071669 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 23:22:18.077860 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 23:22:18.081398 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 23:22:18.084832 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 23:22:18.091105 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 23:22:18.094393 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7761 23:22:18.097323 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7762 23:22:18.104379 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7763 23:22:18.107478 Total UI for P1: 0, mck2ui 16
7764 23:22:18.110399 best dqsien dly found for B0: ( 1, 0, 30)
7765 23:22:18.113810 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7766 23:22:18.117673 Total UI for P1: 0, mck2ui 16
7767 23:22:18.120736 best dqsien dly found for B1: ( 1, 1, 2)
7768 23:22:18.124461 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7769 23:22:18.127507 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7770 23:22:18.127690
7771 23:22:18.130834 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7772 23:22:18.134035 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7773 23:22:18.137102 [Gating] SW calibration Done
7774 23:22:18.137284 ==
7775 23:22:18.140164 Dram Type= 6, Freq= 0, CH_0, rank 1
7776 23:22:18.146651 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7777 23:22:18.146734 ==
7778 23:22:18.146799 RX Vref Scan: 0
7779 23:22:18.146860
7780 23:22:18.150239 RX Vref 0 -> 0, step: 1
7781 23:22:18.150321
7782 23:22:18.153468 RX Delay 0 -> 252, step: 8
7783 23:22:18.157234 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7784 23:22:18.160315 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7785 23:22:18.163143 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7786 23:22:18.166712 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7787 23:22:18.173392 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7788 23:22:18.176750 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7789 23:22:18.179994 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7790 23:22:18.183170 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7791 23:22:18.186521 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7792 23:22:18.193867 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7793 23:22:18.196553 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7794 23:22:18.199582 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7795 23:22:18.202924 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7796 23:22:18.209737 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7797 23:22:18.213064 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7798 23:22:18.216322 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7799 23:22:18.216403 ==
7800 23:22:18.219477 Dram Type= 6, Freq= 0, CH_0, rank 1
7801 23:22:18.222956 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7802 23:22:18.223038 ==
7803 23:22:18.226552 DQS Delay:
7804 23:22:18.226635 DQS0 = 0, DQS1 = 0
7805 23:22:18.229565 DQM Delay:
7806 23:22:18.229648 DQM0 = 130, DQM1 = 124
7807 23:22:18.229713 DQ Delay:
7808 23:22:18.236206 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7809 23:22:18.239953 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7810 23:22:18.242459 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7811 23:22:18.246300 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7812 23:22:18.246382
7813 23:22:18.246448
7814 23:22:18.246509 ==
7815 23:22:18.249010 Dram Type= 6, Freq= 0, CH_0, rank 1
7816 23:22:18.252493 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7817 23:22:18.252576 ==
7818 23:22:18.252641
7819 23:22:18.252702
7820 23:22:18.255939 TX Vref Scan disable
7821 23:22:18.259067 == TX Byte 0 ==
7822 23:22:18.263211 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7823 23:22:18.265853 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7824 23:22:18.269180 == TX Byte 1 ==
7825 23:22:18.272509 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7826 23:22:18.276283 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7827 23:22:18.276365 ==
7828 23:22:18.279089 Dram Type= 6, Freq= 0, CH_0, rank 1
7829 23:22:18.285563 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7830 23:22:18.285650 ==
7831 23:22:18.297699
7832 23:22:18.300307 TX Vref early break, caculate TX vref
7833 23:22:18.303370 TX Vref=16, minBit 8, minWin=22, winSum=379
7834 23:22:18.307334 TX Vref=18, minBit 1, minWin=23, winSum=386
7835 23:22:18.310171 TX Vref=20, minBit 1, minWin=24, winSum=395
7836 23:22:18.313437 TX Vref=22, minBit 1, minWin=23, winSum=397
7837 23:22:18.317278 TX Vref=24, minBit 1, minWin=24, winSum=406
7838 23:22:18.323178 TX Vref=26, minBit 1, minWin=25, winSum=415
7839 23:22:18.326619 TX Vref=28, minBit 8, minWin=25, winSum=421
7840 23:22:18.330925 TX Vref=30, minBit 4, minWin=25, winSum=413
7841 23:22:18.333626 TX Vref=32, minBit 1, minWin=24, winSum=399
7842 23:22:18.336476 TX Vref=34, minBit 8, minWin=23, winSum=395
7843 23:22:18.343816 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 28
7844 23:22:18.343924
7845 23:22:18.346565 Final TX Range 0 Vref 28
7846 23:22:18.346647
7847 23:22:18.346712 ==
7848 23:22:18.350035 Dram Type= 6, Freq= 0, CH_0, rank 1
7849 23:22:18.353340 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7850 23:22:18.353422 ==
7851 23:22:18.353487
7852 23:22:18.353567
7853 23:22:18.357062 TX Vref Scan disable
7854 23:22:18.363886 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7855 23:22:18.363968 == TX Byte 0 ==
7856 23:22:18.366334 u2DelayCellOfst[0]=14 cells (4 PI)
7857 23:22:18.369960 u2DelayCellOfst[1]=18 cells (5 PI)
7858 23:22:18.373468 u2DelayCellOfst[2]=14 cells (4 PI)
7859 23:22:18.376556 u2DelayCellOfst[3]=14 cells (4 PI)
7860 23:22:18.379537 u2DelayCellOfst[4]=10 cells (3 PI)
7861 23:22:18.382988 u2DelayCellOfst[5]=0 cells (0 PI)
7862 23:22:18.386108 u2DelayCellOfst[6]=18 cells (5 PI)
7863 23:22:18.389880 u2DelayCellOfst[7]=18 cells (5 PI)
7864 23:22:18.393161 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7865 23:22:18.396123 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7866 23:22:18.399156 == TX Byte 1 ==
7867 23:22:18.403242 u2DelayCellOfst[8]=3 cells (1 PI)
7868 23:22:18.406246 u2DelayCellOfst[9]=0 cells (0 PI)
7869 23:22:18.406329 u2DelayCellOfst[10]=10 cells (3 PI)
7870 23:22:18.409098 u2DelayCellOfst[11]=3 cells (1 PI)
7871 23:22:18.413004 u2DelayCellOfst[12]=14 cells (4 PI)
7872 23:22:18.416134 u2DelayCellOfst[13]=14 cells (4 PI)
7873 23:22:18.419257 u2DelayCellOfst[14]=18 cells (5 PI)
7874 23:22:18.422880 u2DelayCellOfst[15]=14 cells (4 PI)
7875 23:22:18.429486 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7876 23:22:18.433027 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7877 23:22:18.433110 DramC Write-DBI on
7878 23:22:18.433176 ==
7879 23:22:18.436241 Dram Type= 6, Freq= 0, CH_0, rank 1
7880 23:22:18.442842 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7881 23:22:18.442925 ==
7882 23:22:18.442989
7883 23:22:18.443050
7884 23:22:18.443107 TX Vref Scan disable
7885 23:22:18.446986 == TX Byte 0 ==
7886 23:22:18.450047 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7887 23:22:18.453298 == TX Byte 1 ==
7888 23:22:18.456408 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7889 23:22:18.459948 DramC Write-DBI off
7890 23:22:18.460030
7891 23:22:18.460094 [DATLAT]
7892 23:22:18.460155 Freq=1600, CH0 RK1
7893 23:22:18.460214
7894 23:22:18.462762 DATLAT Default: 0xe
7895 23:22:18.466366 0, 0xFFFF, sum = 0
7896 23:22:18.466449 1, 0xFFFF, sum = 0
7897 23:22:18.470008 2, 0xFFFF, sum = 0
7898 23:22:18.470091 3, 0xFFFF, sum = 0
7899 23:22:18.473450 4, 0xFFFF, sum = 0
7900 23:22:18.473539 5, 0xFFFF, sum = 0
7901 23:22:18.476678 6, 0xFFFF, sum = 0
7902 23:22:18.476778 7, 0xFFFF, sum = 0
7903 23:22:18.479777 8, 0xFFFF, sum = 0
7904 23:22:18.479872 9, 0xFFFF, sum = 0
7905 23:22:18.483053 10, 0xFFFF, sum = 0
7906 23:22:18.483148 11, 0xFFFF, sum = 0
7907 23:22:18.486446 12, 0x8FFF, sum = 0
7908 23:22:18.486528 13, 0x0, sum = 1
7909 23:22:18.489504 14, 0x0, sum = 2
7910 23:22:18.489587 15, 0x0, sum = 3
7911 23:22:18.492838 16, 0x0, sum = 4
7912 23:22:18.492921 best_step = 14
7913 23:22:18.492988
7914 23:22:18.493048 ==
7915 23:22:18.496146 Dram Type= 6, Freq= 0, CH_0, rank 1
7916 23:22:18.500661 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7917 23:22:18.503317 ==
7918 23:22:18.503398 RX Vref Scan: 0
7919 23:22:18.503463
7920 23:22:18.506672 RX Vref 0 -> 0, step: 1
7921 23:22:18.506754
7922 23:22:18.509794 RX Delay 11 -> 252, step: 4
7923 23:22:18.513023 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7924 23:22:18.516157 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7925 23:22:18.519198 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7926 23:22:18.526013 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7927 23:22:18.528990 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
7928 23:22:18.532755 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7929 23:22:18.536016 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
7930 23:22:18.539657 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7931 23:22:18.545852 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7932 23:22:18.548993 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7933 23:22:18.552411 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7934 23:22:18.555524 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7935 23:22:18.559017 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7936 23:22:18.566672 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7937 23:22:18.569368 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7938 23:22:18.572620 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7939 23:22:18.572733 ==
7940 23:22:18.575715 Dram Type= 6, Freq= 0, CH_0, rank 1
7941 23:22:18.579463 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7942 23:22:18.579552 ==
7943 23:22:18.583077 DQS Delay:
7944 23:22:18.583176 DQS0 = 0, DQS1 = 0
7945 23:22:18.585870 DQM Delay:
7946 23:22:18.585964 DQM0 = 129, DQM1 = 120
7947 23:22:18.586038 DQ Delay:
7948 23:22:18.592973 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7949 23:22:18.595790 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
7950 23:22:18.598686 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7951 23:22:18.602433 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7952 23:22:18.602524
7953 23:22:18.602590
7954 23:22:18.602650
7955 23:22:18.605496 [DramC_TX_OE_Calibration] TA2
7956 23:22:18.609847 Original DQ_B0 (3 6) =30, OEN = 27
7957 23:22:18.612323 Original DQ_B1 (3 6) =30, OEN = 27
7958 23:22:18.612405 24, 0x0, End_B0=24 End_B1=24
7959 23:22:18.615651 25, 0x0, End_B0=25 End_B1=25
7960 23:22:18.618960 26, 0x0, End_B0=26 End_B1=26
7961 23:22:18.623052 27, 0x0, End_B0=27 End_B1=27
7962 23:22:18.625402 28, 0x0, End_B0=28 End_B1=28
7963 23:22:18.625485 29, 0x0, End_B0=29 End_B1=29
7964 23:22:18.628958 30, 0x0, End_B0=30 End_B1=30
7965 23:22:18.632048 31, 0x4141, End_B0=30 End_B1=30
7966 23:22:18.635881 Byte0 end_step=30 best_step=27
7967 23:22:18.638533 Byte1 end_step=30 best_step=27
7968 23:22:18.641690 Byte0 TX OE(2T, 0.5T) = (3, 3)
7969 23:22:18.641774 Byte1 TX OE(2T, 0.5T) = (3, 3)
7970 23:22:18.641839
7971 23:22:18.645214
7972 23:22:18.651749 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7973 23:22:18.655256 CH0 RK1: MR19=303, MR18=1D1D
7974 23:22:18.662330 CH0_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
7975 23:22:18.664988 [RxdqsGatingPostProcess] freq 1600
7976 23:22:18.668664 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7977 23:22:18.672041 Pre-setting of DQS Precalculation
7978 23:22:18.678246 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7979 23:22:18.678329 ==
7980 23:22:18.681635 Dram Type= 6, Freq= 0, CH_1, rank 0
7981 23:22:18.685006 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7982 23:22:18.685088 ==
7983 23:22:18.692016 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7984 23:22:18.695664 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7985 23:22:18.698593 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7986 23:22:18.704524 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7987 23:22:18.712698 [CA 0] Center 40 (10~70) winsize 61
7988 23:22:18.715759 [CA 1] Center 39 (9~69) winsize 61
7989 23:22:18.718764 [CA 2] Center 35 (6~65) winsize 60
7990 23:22:18.722493 [CA 3] Center 35 (5~65) winsize 61
7991 23:22:18.727083 [CA 4] Center 33 (3~63) winsize 61
7992 23:22:18.729148 [CA 5] Center 33 (3~63) winsize 61
7993 23:22:18.729230
7994 23:22:18.732505 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7995 23:22:18.732587
7996 23:22:18.736041 [CATrainingPosCal] consider 1 rank data
7997 23:22:18.738518 u2DelayCellTimex100 = 271/100 ps
7998 23:22:18.745319 CA0 delay=40 (10~70),Diff = 7 PI (25 cell)
7999 23:22:18.748611 CA1 delay=39 (9~69),Diff = 6 PI (21 cell)
8000 23:22:18.752186 CA2 delay=35 (6~65),Diff = 2 PI (7 cell)
8001 23:22:18.755292 CA3 delay=35 (5~65),Diff = 2 PI (7 cell)
8002 23:22:18.758935 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
8003 23:22:18.761967 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
8004 23:22:18.762049
8005 23:22:18.765310 CA PerBit enable=1, Macro0, CA PI delay=33
8006 23:22:18.765392
8007 23:22:18.768699 [CBTSetCACLKResult] CA Dly = 33
8008 23:22:18.771505 CS Dly: 8 (0~39)
8009 23:22:18.775034 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8010 23:22:18.779226 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8011 23:22:18.779307 ==
8012 23:22:18.781848 Dram Type= 6, Freq= 0, CH_1, rank 1
8013 23:22:18.785640 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8014 23:22:18.789215 ==
8015 23:22:18.792038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8016 23:22:18.794834 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8017 23:22:18.801478 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8018 23:22:18.808110 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8019 23:22:18.814627 [CA 0] Center 41 (11~71) winsize 61
8020 23:22:18.818148 [CA 1] Center 40 (10~71) winsize 62
8021 23:22:18.821778 [CA 2] Center 36 (7~66) winsize 60
8022 23:22:18.824906 [CA 3] Center 36 (7~65) winsize 59
8023 23:22:18.828474 [CA 4] Center 34 (5~64) winsize 60
8024 23:22:18.831314 [CA 5] Center 34 (5~64) winsize 60
8025 23:22:18.831396
8026 23:22:18.834819 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8027 23:22:18.834901
8028 23:22:18.839016 [CATrainingPosCal] consider 2 rank data
8029 23:22:18.840842 u2DelayCellTimex100 = 271/100 ps
8030 23:22:18.847413 CA0 delay=40 (11~70),Diff = 6 PI (21 cell)
8031 23:22:18.851138 CA1 delay=39 (10~69),Diff = 5 PI (18 cell)
8032 23:22:18.854009 CA2 delay=36 (7~65),Diff = 2 PI (7 cell)
8033 23:22:18.857584 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8034 23:22:18.861450 CA4 delay=34 (5~63),Diff = 0 PI (0 cell)
8035 23:22:18.864342 CA5 delay=34 (5~63),Diff = 0 PI (0 cell)
8036 23:22:18.864424
8037 23:22:18.867929 CA PerBit enable=1, Macro0, CA PI delay=34
8038 23:22:18.868010
8039 23:22:18.871032 [CBTSetCACLKResult] CA Dly = 34
8040 23:22:18.875165 CS Dly: 9 (0~41)
8041 23:22:18.877183 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8042 23:22:18.880592 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8043 23:22:18.880674
8044 23:22:18.884568 ----->DramcWriteLeveling(PI) begin...
8045 23:22:18.884677 ==
8046 23:22:18.887655 Dram Type= 6, Freq= 0, CH_1, rank 0
8047 23:22:18.893697 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8048 23:22:18.893780 ==
8049 23:22:18.897126 Write leveling (Byte 0): 22 => 22
8050 23:22:18.900284 Write leveling (Byte 1): 21 => 21
8051 23:22:18.900421 DramcWriteLeveling(PI) end<-----
8052 23:22:18.900530
8053 23:22:18.903847 ==
8054 23:22:18.906771 Dram Type= 6, Freq= 0, CH_1, rank 0
8055 23:22:18.910534 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8056 23:22:18.910616 ==
8057 23:22:18.914437 [Gating] SW mode calibration
8058 23:22:18.920539 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8059 23:22:18.923946 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8060 23:22:18.930462 0 12 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8061 23:22:18.934008 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 23:22:18.936667 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 23:22:18.943947 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 23:22:18.946678 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 23:22:18.950766 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 23:22:18.956385 0 12 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8067 23:22:18.960187 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8068 23:22:18.963331 0 13 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
8069 23:22:18.969551 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 23:22:18.973550 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8071 23:22:18.977338 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 23:22:18.983553 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 23:22:18.986479 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 23:22:18.989725 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8075 23:22:18.996813 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8076 23:22:18.999864 0 14 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8077 23:22:19.003324 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 23:22:19.009584 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 23:22:19.012826 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 23:22:19.015863 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 23:22:19.022797 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 23:22:19.025801 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8083 23:22:19.029520 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8084 23:22:19.036401 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8085 23:22:19.039506 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 23:22:19.043155 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 23:22:19.050027 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 23:22:19.052679 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 23:22:19.056424 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 23:22:19.062212 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 23:22:19.065716 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 23:22:19.068816 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 23:22:19.076621 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 23:22:19.078986 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 23:22:19.082351 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 23:22:19.089314 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 23:22:19.092029 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 23:22:19.095677 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 23:22:19.103331 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8100 23:22:19.105740 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8101 23:22:19.109556 Total UI for P1: 0, mck2ui 16
8102 23:22:19.112149 best dqsien dly found for B0: ( 1, 0, 28)
8103 23:22:19.115724 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8104 23:22:19.122140 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 23:22:19.122223 Total UI for P1: 0, mck2ui 16
8106 23:22:19.125230 best dqsien dly found for B1: ( 1, 1, 2)
8107 23:22:19.131680 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8108 23:22:19.135224 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8109 23:22:19.135306
8110 23:22:19.138609 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8111 23:22:19.142488 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8112 23:22:19.145123 [Gating] SW calibration Done
8113 23:22:19.145231 ==
8114 23:22:19.148545 Dram Type= 6, Freq= 0, CH_1, rank 0
8115 23:22:19.152689 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8116 23:22:19.152823 ==
8117 23:22:19.154609 RX Vref Scan: 0
8118 23:22:19.154697
8119 23:22:19.154758 RX Vref 0 -> 0, step: 1
8120 23:22:19.154816
8121 23:22:19.159417 RX Delay 0 -> 252, step: 8
8122 23:22:19.161294 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8123 23:22:19.168182 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8124 23:22:19.171243 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8125 23:22:19.175460 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8126 23:22:19.178003 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8127 23:22:19.181343 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8128 23:22:19.188234 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8129 23:22:19.191107 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8130 23:22:19.194408 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8131 23:22:19.197762 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8132 23:22:19.201020 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8133 23:22:19.207860 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8134 23:22:19.210687 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8135 23:22:19.214220 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8136 23:22:19.217683 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8137 23:22:19.220810 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8138 23:22:19.224609 ==
8139 23:22:19.227602 Dram Type= 6, Freq= 0, CH_1, rank 0
8140 23:22:19.231933 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8141 23:22:19.232015 ==
8142 23:22:19.232079 DQS Delay:
8143 23:22:19.234565 DQS0 = 0, DQS1 = 0
8144 23:22:19.234647 DQM Delay:
8145 23:22:19.237649 DQM0 = 129, DQM1 = 126
8146 23:22:19.237731 DQ Delay:
8147 23:22:19.240710 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8148 23:22:19.244014 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8149 23:22:19.247225 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8150 23:22:19.250673 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8151 23:22:19.250755
8152 23:22:19.250820
8153 23:22:19.250881 ==
8154 23:22:19.254626 Dram Type= 6, Freq= 0, CH_1, rank 0
8155 23:22:19.260831 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8156 23:22:19.260914 ==
8157 23:22:19.260979
8158 23:22:19.261039
8159 23:22:19.263601 TX Vref Scan disable
8160 23:22:19.263682 == TX Byte 0 ==
8161 23:22:19.267505 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8162 23:22:19.274518 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8163 23:22:19.274600 == TX Byte 1 ==
8164 23:22:19.276934 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8165 23:22:19.283778 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8166 23:22:19.283860 ==
8167 23:22:19.287096 Dram Type= 6, Freq= 0, CH_1, rank 0
8168 23:22:19.291005 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8169 23:22:19.291088 ==
8170 23:22:19.302656
8171 23:22:19.306270 TX Vref early break, caculate TX vref
8172 23:22:19.309452 TX Vref=16, minBit 0, minWin=21, winSum=366
8173 23:22:19.312641 TX Vref=18, minBit 1, minWin=22, winSum=378
8174 23:22:19.316333 TX Vref=20, minBit 3, minWin=22, winSum=384
8175 23:22:19.319322 TX Vref=22, minBit 3, minWin=22, winSum=392
8176 23:22:19.322667 TX Vref=24, minBit 3, minWin=23, winSum=402
8177 23:22:19.329562 TX Vref=26, minBit 0, minWin=24, winSum=412
8178 23:22:19.332834 TX Vref=28, minBit 3, minWin=24, winSum=411
8179 23:22:19.336147 TX Vref=30, minBit 3, minWin=24, winSum=407
8180 23:22:19.338985 TX Vref=32, minBit 3, minWin=23, winSum=396
8181 23:22:19.343001 TX Vref=34, minBit 3, minWin=22, winSum=389
8182 23:22:19.348670 [TxChooseVref] Worse bit 0, Min win 24, Win sum 412, Final Vref 26
8183 23:22:19.348771
8184 23:22:19.352132 Final TX Range 0 Vref 26
8185 23:22:19.352213
8186 23:22:19.352277 ==
8187 23:22:19.355658 Dram Type= 6, Freq= 0, CH_1, rank 0
8188 23:22:19.359139 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8189 23:22:19.359222 ==
8190 23:22:19.359286
8191 23:22:19.359346
8192 23:22:19.362860 TX Vref Scan disable
8193 23:22:19.368687 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8194 23:22:19.368808 == TX Byte 0 ==
8195 23:22:19.372534 u2DelayCellOfst[0]=18 cells (5 PI)
8196 23:22:19.375718 u2DelayCellOfst[1]=10 cells (3 PI)
8197 23:22:19.379530 u2DelayCellOfst[2]=0 cells (0 PI)
8198 23:22:19.382183 u2DelayCellOfst[3]=7 cells (2 PI)
8199 23:22:19.386101 u2DelayCellOfst[4]=10 cells (3 PI)
8200 23:22:19.389107 u2DelayCellOfst[5]=21 cells (6 PI)
8201 23:22:19.392333 u2DelayCellOfst[6]=18 cells (5 PI)
8202 23:22:19.396086 u2DelayCellOfst[7]=7 cells (2 PI)
8203 23:22:19.399006 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8204 23:22:19.402141 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8205 23:22:19.405272 == TX Byte 1 ==
8206 23:22:19.405354 u2DelayCellOfst[8]=0 cells (0 PI)
8207 23:22:19.408623 u2DelayCellOfst[9]=7 cells (2 PI)
8208 23:22:19.411910 u2DelayCellOfst[10]=10 cells (3 PI)
8209 23:22:19.415114 u2DelayCellOfst[11]=3 cells (1 PI)
8210 23:22:19.418567 u2DelayCellOfst[12]=14 cells (4 PI)
8211 23:22:19.422025 u2DelayCellOfst[13]=18 cells (5 PI)
8212 23:22:19.425821 u2DelayCellOfst[14]=21 cells (6 PI)
8213 23:22:19.428560 u2DelayCellOfst[15]=18 cells (5 PI)
8214 23:22:19.432248 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8215 23:22:19.439064 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8216 23:22:19.439147 DramC Write-DBI on
8217 23:22:19.439212 ==
8218 23:22:19.442343 Dram Type= 6, Freq= 0, CH_1, rank 0
8219 23:22:19.445143 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8220 23:22:19.448265 ==
8221 23:22:19.448347
8222 23:22:19.448411
8223 23:22:19.448472 TX Vref Scan disable
8224 23:22:19.451852 == TX Byte 0 ==
8225 23:22:19.455364 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8226 23:22:19.458948 == TX Byte 1 ==
8227 23:22:19.461939 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8228 23:22:19.465770 DramC Write-DBI off
8229 23:22:19.465851
8230 23:22:19.465916 [DATLAT]
8231 23:22:19.465977 Freq=1600, CH1 RK0
8232 23:22:19.466036
8233 23:22:19.468873 DATLAT Default: 0xf
8234 23:22:19.468954 0, 0xFFFF, sum = 0
8235 23:22:19.471841 1, 0xFFFF, sum = 0
8236 23:22:19.474947 2, 0xFFFF, sum = 0
8237 23:22:19.475035 3, 0xFFFF, sum = 0
8238 23:22:19.478726 4, 0xFFFF, sum = 0
8239 23:22:19.478822 5, 0xFFFF, sum = 0
8240 23:22:19.482000 6, 0xFFFF, sum = 0
8241 23:22:19.482127 7, 0xFFFF, sum = 0
8242 23:22:19.485042 8, 0xFFFF, sum = 0
8243 23:22:19.485146 9, 0xFFFF, sum = 0
8244 23:22:19.488721 10, 0xFFFF, sum = 0
8245 23:22:19.488834 11, 0xFFFF, sum = 0
8246 23:22:19.492222 12, 0xF7F, sum = 0
8247 23:22:19.492334 13, 0x0, sum = 1
8248 23:22:19.495169 14, 0x0, sum = 2
8249 23:22:19.495294 15, 0x0, sum = 3
8250 23:22:19.498886 16, 0x0, sum = 4
8251 23:22:19.499024 best_step = 14
8252 23:22:19.499131
8253 23:22:19.499233 ==
8254 23:22:19.501607 Dram Type= 6, Freq= 0, CH_1, rank 0
8255 23:22:19.504715 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8256 23:22:19.508206 ==
8257 23:22:19.508379 RX Vref Scan: 1
8258 23:22:19.508517
8259 23:22:19.511722 Set Vref Range= 24 -> 127
8260 23:22:19.511895
8261 23:22:19.514870 RX Vref 24 -> 127, step: 1
8262 23:22:19.515070
8263 23:22:19.515231 RX Delay 3 -> 252, step: 4
8264 23:22:19.515381
8265 23:22:19.518337 Set Vref, RX VrefLevel [Byte0]: 24
8266 23:22:19.521406 [Byte1]: 24
8267 23:22:19.525537
8268 23:22:19.525834 Set Vref, RX VrefLevel [Byte0]: 25
8269 23:22:19.529277 [Byte1]: 25
8270 23:22:19.532860
8271 23:22:19.532941 Set Vref, RX VrefLevel [Byte0]: 26
8272 23:22:19.535893 [Byte1]: 26
8273 23:22:19.540278
8274 23:22:19.540359 Set Vref, RX VrefLevel [Byte0]: 27
8275 23:22:19.544637 [Byte1]: 27
8276 23:22:19.548318
8277 23:22:19.548399 Set Vref, RX VrefLevel [Byte0]: 28
8278 23:22:19.551674 [Byte1]: 28
8279 23:22:19.555797
8280 23:22:19.555879 Set Vref, RX VrefLevel [Byte0]: 29
8281 23:22:19.559073 [Byte1]: 29
8282 23:22:19.563887
8283 23:22:19.563968 Set Vref, RX VrefLevel [Byte0]: 30
8284 23:22:19.566594 [Byte1]: 30
8285 23:22:19.571347
8286 23:22:19.571428 Set Vref, RX VrefLevel [Byte0]: 31
8287 23:22:19.574734 [Byte1]: 31
8288 23:22:19.578493
8289 23:22:19.578575 Set Vref, RX VrefLevel [Byte0]: 32
8290 23:22:19.581972 [Byte1]: 32
8291 23:22:19.586689
8292 23:22:19.586770 Set Vref, RX VrefLevel [Byte0]: 33
8293 23:22:19.589899 [Byte1]: 33
8294 23:22:19.594609
8295 23:22:19.594691 Set Vref, RX VrefLevel [Byte0]: 34
8296 23:22:19.597897 [Byte1]: 34
8297 23:22:19.602251
8298 23:22:19.602332 Set Vref, RX VrefLevel [Byte0]: 35
8299 23:22:19.606541 [Byte1]: 35
8300 23:22:19.610147
8301 23:22:19.610227 Set Vref, RX VrefLevel [Byte0]: 36
8302 23:22:19.612698 [Byte1]: 36
8303 23:22:19.617928
8304 23:22:19.618013 Set Vref, RX VrefLevel [Byte0]: 37
8305 23:22:19.620452 [Byte1]: 37
8306 23:22:19.624641
8307 23:22:19.624730 Set Vref, RX VrefLevel [Byte0]: 38
8308 23:22:19.627812 [Byte1]: 38
8309 23:22:19.632118
8310 23:22:19.632199 Set Vref, RX VrefLevel [Byte0]: 39
8311 23:22:19.635813 [Byte1]: 39
8312 23:22:19.640679
8313 23:22:19.640769 Set Vref, RX VrefLevel [Byte0]: 40
8314 23:22:19.643422 [Byte1]: 40
8315 23:22:19.647696
8316 23:22:19.647776 Set Vref, RX VrefLevel [Byte0]: 41
8317 23:22:19.650836 [Byte1]: 41
8318 23:22:19.655369
8319 23:22:19.655454 Set Vref, RX VrefLevel [Byte0]: 42
8320 23:22:19.658765 [Byte1]: 42
8321 23:22:19.663036
8322 23:22:19.663116 Set Vref, RX VrefLevel [Byte0]: 43
8323 23:22:19.666359 [Byte1]: 43
8324 23:22:19.670647
8325 23:22:19.670727 Set Vref, RX VrefLevel [Byte0]: 44
8326 23:22:19.674402 [Byte1]: 44
8327 23:22:19.678120
8328 23:22:19.678250 Set Vref, RX VrefLevel [Byte0]: 45
8329 23:22:19.681986 [Byte1]: 45
8330 23:22:19.686231
8331 23:22:19.686401 Set Vref, RX VrefLevel [Byte0]: 46
8332 23:22:19.688939 [Byte1]: 46
8333 23:22:19.694303
8334 23:22:19.694424 Set Vref, RX VrefLevel [Byte0]: 47
8335 23:22:19.696596 [Byte1]: 47
8336 23:22:19.701068
8337 23:22:19.701202 Set Vref, RX VrefLevel [Byte0]: 48
8338 23:22:19.705092 [Byte1]: 48
8339 23:22:19.710173
8340 23:22:19.710590 Set Vref, RX VrefLevel [Byte0]: 49
8341 23:22:19.712601 [Byte1]: 49
8342 23:22:19.716446
8343 23:22:19.716528 Set Vref, RX VrefLevel [Byte0]: 50
8344 23:22:19.719529 [Byte1]: 50
8345 23:22:19.724098
8346 23:22:19.724179 Set Vref, RX VrefLevel [Byte0]: 51
8347 23:22:19.727306 [Byte1]: 51
8348 23:22:19.731532
8349 23:22:19.731613 Set Vref, RX VrefLevel [Byte0]: 52
8350 23:22:19.735054 [Byte1]: 52
8351 23:22:19.739270
8352 23:22:19.739350 Set Vref, RX VrefLevel [Byte0]: 53
8353 23:22:19.742854 [Byte1]: 53
8354 23:22:19.747734
8355 23:22:19.747815 Set Vref, RX VrefLevel [Byte0]: 54
8356 23:22:19.750708 [Byte1]: 54
8357 23:22:19.754762
8358 23:22:19.754842 Set Vref, RX VrefLevel [Byte0]: 55
8359 23:22:19.758067 [Byte1]: 55
8360 23:22:19.762488
8361 23:22:19.762568 Set Vref, RX VrefLevel [Byte0]: 56
8362 23:22:19.765455 [Byte1]: 56
8363 23:22:19.770010
8364 23:22:19.770091 Set Vref, RX VrefLevel [Byte0]: 57
8365 23:22:19.773209 [Byte1]: 57
8366 23:22:19.777767
8367 23:22:19.777848 Set Vref, RX VrefLevel [Byte0]: 58
8368 23:22:19.781449 [Byte1]: 58
8369 23:22:19.786169
8370 23:22:19.786250 Set Vref, RX VrefLevel [Byte0]: 59
8371 23:22:19.788989 [Byte1]: 59
8372 23:22:19.792945
8373 23:22:19.793025 Set Vref, RX VrefLevel [Byte0]: 60
8374 23:22:19.796474 [Byte1]: 60
8375 23:22:19.803549
8376 23:22:19.803979 Set Vref, RX VrefLevel [Byte0]: 61
8377 23:22:19.804912 [Byte1]: 61
8378 23:22:19.808545
8379 23:22:19.809008 Set Vref, RX VrefLevel [Byte0]: 62
8380 23:22:19.812129 [Byte1]: 62
8381 23:22:19.816589
8382 23:22:19.817057 Set Vref, RX VrefLevel [Byte0]: 63
8383 23:22:19.819786 [Byte1]: 63
8384 23:22:19.823943
8385 23:22:19.824357 Set Vref, RX VrefLevel [Byte0]: 64
8386 23:22:19.828083 [Byte1]: 64
8387 23:22:19.831335
8388 23:22:19.831748 Set Vref, RX VrefLevel [Byte0]: 65
8389 23:22:19.834800 [Byte1]: 65
8390 23:22:19.839195
8391 23:22:19.839610 Set Vref, RX VrefLevel [Byte0]: 66
8392 23:22:19.843269 [Byte1]: 66
8393 23:22:19.846887
8394 23:22:19.847303 Set Vref, RX VrefLevel [Byte0]: 67
8395 23:22:19.850262 [Byte1]: 67
8396 23:22:19.854611
8397 23:22:19.855132 Set Vref, RX VrefLevel [Byte0]: 68
8398 23:22:19.858069 [Byte1]: 68
8399 23:22:19.862055
8400 23:22:19.862136 Set Vref, RX VrefLevel [Byte0]: 69
8401 23:22:19.866147 [Byte1]: 69
8402 23:22:19.869884
8403 23:22:19.870306 Set Vref, RX VrefLevel [Byte0]: 70
8404 23:22:19.873344 [Byte1]: 70
8405 23:22:19.878061
8406 23:22:19.878480 Set Vref, RX VrefLevel [Byte0]: 71
8407 23:22:19.880854 [Byte1]: 71
8408 23:22:19.885387
8409 23:22:19.885940 Set Vref, RX VrefLevel [Byte0]: 72
8410 23:22:19.888278 [Byte1]: 72
8411 23:22:19.893246
8412 23:22:19.893662 Set Vref, RX VrefLevel [Byte0]: 73
8413 23:22:19.896079 [Byte1]: 73
8414 23:22:19.900325
8415 23:22:19.900934 Set Vref, RX VrefLevel [Byte0]: 74
8416 23:22:19.904088 [Byte1]: 74
8417 23:22:19.908336
8418 23:22:19.908785 Set Vref, RX VrefLevel [Byte0]: 75
8419 23:22:19.911341 [Byte1]: 75
8420 23:22:19.916045
8421 23:22:19.916464 Final RX Vref Byte 0 = 56 to rank0
8422 23:22:19.919051 Final RX Vref Byte 1 = 55 to rank0
8423 23:22:19.922306 Final RX Vref Byte 0 = 56 to rank1
8424 23:22:19.926384 Final RX Vref Byte 1 = 55 to rank1==
8425 23:22:19.929346 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 23:22:19.935626 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8427 23:22:19.936048 ==
8428 23:22:19.936384 DQS Delay:
8429 23:22:19.938826 DQS0 = 0, DQS1 = 0
8430 23:22:19.939247 DQM Delay:
8431 23:22:19.939582 DQM0 = 128, DQM1 = 123
8432 23:22:19.942703 DQ Delay:
8433 23:22:19.945384 DQ0 =130, DQ1 =124, DQ2 =118, DQ3 =128
8434 23:22:19.948796 DQ4 =128, DQ5 =140, DQ6 =136, DQ7 =126
8435 23:22:19.952323 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =110
8436 23:22:19.955996 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =132
8437 23:22:19.956422
8438 23:22:19.956821
8439 23:22:19.957155
8440 23:22:19.958504 [DramC_TX_OE_Calibration] TA2
8441 23:22:19.961957 Original DQ_B0 (3 6) =30, OEN = 27
8442 23:22:19.965212 Original DQ_B1 (3 6) =30, OEN = 27
8443 23:22:19.968776 24, 0x0, End_B0=24 End_B1=24
8444 23:22:19.969237 25, 0x0, End_B0=25 End_B1=25
8445 23:22:19.971991 26, 0x0, End_B0=26 End_B1=26
8446 23:22:19.975364 27, 0x0, End_B0=27 End_B1=27
8447 23:22:19.978402 28, 0x0, End_B0=28 End_B1=28
8448 23:22:19.982088 29, 0x0, End_B0=29 End_B1=29
8449 23:22:19.982519 30, 0x0, End_B0=30 End_B1=30
8450 23:22:19.985544 31, 0x4141, End_B0=30 End_B1=30
8451 23:22:19.988535 Byte0 end_step=30 best_step=27
8452 23:22:19.991739 Byte1 end_step=30 best_step=27
8453 23:22:19.995418 Byte0 TX OE(2T, 0.5T) = (3, 3)
8454 23:22:19.998788 Byte1 TX OE(2T, 0.5T) = (3, 3)
8455 23:22:19.999252
8456 23:22:19.999715
8457 23:22:20.005225 [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8458 23:22:20.009116 CH1 RK0: MR19=303, MR18=2828
8459 23:22:20.014889 CH1_RK0: MR19=0x303, MR18=0x2828, DQSOSC=389, MR23=63, INC=24, DEC=16
8460 23:22:20.015320
8461 23:22:20.019476 ----->DramcWriteLeveling(PI) begin...
8462 23:22:20.019902 ==
8463 23:22:20.021595 Dram Type= 6, Freq= 0, CH_1, rank 1
8464 23:22:20.025341 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8465 23:22:20.025834 ==
8466 23:22:20.028156 Write leveling (Byte 0): 22 => 22
8467 23:22:20.031220 Write leveling (Byte 1): 21 => 21
8468 23:22:20.035492 DramcWriteLeveling(PI) end<-----
8469 23:22:20.035914
8470 23:22:20.036343 ==
8471 23:22:20.039026 Dram Type= 6, Freq= 0, CH_1, rank 1
8472 23:22:20.041894 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8473 23:22:20.042322 ==
8474 23:22:20.045042 [Gating] SW mode calibration
8475 23:22:20.051752 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8476 23:22:20.057938 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8477 23:22:20.061155 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8478 23:22:20.068063 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8479 23:22:20.071329 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8480 23:22:20.074512 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8481 23:22:20.081131 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8482 23:22:20.084046 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8483 23:22:20.087613 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 1)
8484 23:22:20.094178 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8485 23:22:20.097938 0 13 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
8486 23:22:20.100853 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8487 23:22:20.107460 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 23:22:20.110990 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8489 23:22:20.114149 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8490 23:22:20.120578 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8491 23:22:20.123984 0 13 24 | B1->B0 | 2323 4242 | 0 0 | (0 0) (1 1)
8492 23:22:20.127606 0 13 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8493 23:22:20.133782 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8494 23:22:20.136943 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8495 23:22:20.140383 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 23:22:20.147457 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 23:22:20.150352 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8498 23:22:20.153598 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8499 23:22:20.159916 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8500 23:22:20.163691 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8501 23:22:20.166904 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8502 23:22:20.173495 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 23:22:20.177216 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 23:22:20.181092 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 23:22:20.186528 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 23:22:20.189725 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 23:22:20.193432 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 23:22:20.200097 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 23:22:20.203215 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 23:22:20.206370 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 23:22:20.213014 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 23:22:20.216412 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 23:22:20.220072 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 23:22:20.226200 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8515 23:22:20.230070 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8516 23:22:20.233374 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8517 23:22:20.236108 Total UI for P1: 0, mck2ui 16
8518 23:22:20.239945 best dqsien dly found for B0: ( 1, 0, 22)
8519 23:22:20.243146 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8520 23:22:20.246533 Total UI for P1: 0, mck2ui 16
8521 23:22:20.250431 best dqsien dly found for B1: ( 1, 0, 28)
8522 23:22:20.256162 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8523 23:22:20.259288 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8524 23:22:20.259712
8525 23:22:20.263262 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8526 23:22:20.266293 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8527 23:22:20.269754 [Gating] SW calibration Done
8528 23:22:20.270175 ==
8529 23:22:20.272490 Dram Type= 6, Freq= 0, CH_1, rank 1
8530 23:22:20.276264 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8531 23:22:20.276687 ==
8532 23:22:20.279098 RX Vref Scan: 0
8533 23:22:20.279523
8534 23:22:20.279858 RX Vref 0 -> 0, step: 1
8535 23:22:20.280172
8536 23:22:20.283042 RX Delay 0 -> 252, step: 8
8537 23:22:20.286560 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8538 23:22:20.290602 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8539 23:22:20.296495 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8540 23:22:20.299980 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8541 23:22:20.302847 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8542 23:22:20.306645 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8543 23:22:20.309289 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8544 23:22:20.316497 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8545 23:22:20.319139 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8546 23:22:20.322676 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8547 23:22:20.325670 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8548 23:22:20.329587 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8549 23:22:20.335526 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8550 23:22:20.339500 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8551 23:22:20.342129 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8552 23:22:20.345280 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8553 23:22:20.345705 ==
8554 23:22:20.348943 Dram Type= 6, Freq= 0, CH_1, rank 1
8555 23:22:20.355577 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8556 23:22:20.356210 ==
8557 23:22:20.356697 DQS Delay:
8558 23:22:20.358821 DQS0 = 0, DQS1 = 0
8559 23:22:20.359280 DQM Delay:
8560 23:22:20.362361 DQM0 = 131, DQM1 = 124
8561 23:22:20.362782 DQ Delay:
8562 23:22:20.365695 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8563 23:22:20.368809 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8564 23:22:20.372166 DQ8 =107, DQ9 =111, DQ10 =127, DQ11 =115
8565 23:22:20.375568 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8566 23:22:20.375993
8567 23:22:20.376326
8568 23:22:20.376671 ==
8569 23:22:20.379380 Dram Type= 6, Freq= 0, CH_1, rank 1
8570 23:22:20.385587 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8571 23:22:20.386015 ==
8572 23:22:20.386350
8573 23:22:20.386663
8574 23:22:20.386973 TX Vref Scan disable
8575 23:22:20.388756 == TX Byte 0 ==
8576 23:22:20.392530 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8577 23:22:20.399129 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8578 23:22:20.399577 == TX Byte 1 ==
8579 23:22:20.402209 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8580 23:22:20.408922 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8581 23:22:20.409348 ==
8582 23:22:20.411852 Dram Type= 6, Freq= 0, CH_1, rank 1
8583 23:22:20.414973 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8584 23:22:20.415399 ==
8585 23:22:20.428237
8586 23:22:20.432085 TX Vref early break, caculate TX vref
8587 23:22:20.435000 TX Vref=16, minBit 2, minWin=22, winSum=376
8588 23:22:20.438226 TX Vref=18, minBit 4, minWin=22, winSum=386
8589 23:22:20.441916 TX Vref=20, minBit 0, minWin=23, winSum=392
8590 23:22:20.444479 TX Vref=22, minBit 0, minWin=24, winSum=401
8591 23:22:20.448227 TX Vref=24, minBit 0, minWin=25, winSum=413
8592 23:22:20.454631 TX Vref=26, minBit 0, minWin=24, winSum=418
8593 23:22:20.457926 TX Vref=28, minBit 0, minWin=25, winSum=419
8594 23:22:20.461219 TX Vref=30, minBit 0, minWin=25, winSum=417
8595 23:22:20.464500 TX Vref=32, minBit 0, minWin=24, winSum=409
8596 23:22:20.467999 TX Vref=34, minBit 0, minWin=24, winSum=401
8597 23:22:20.474982 TX Vref=36, minBit 0, minWin=21, winSum=390
8598 23:22:20.477806 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8599 23:22:20.478231
8600 23:22:20.482017 Final TX Range 0 Vref 28
8601 23:22:20.482461
8602 23:22:20.482816 ==
8603 23:22:20.484470 Dram Type= 6, Freq= 0, CH_1, rank 1
8604 23:22:20.490592 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8605 23:22:20.491016 ==
8606 23:22:20.492337
8607 23:22:20.492815
8608 23:22:20.493159 TX Vref Scan disable
8609 23:22:20.497971 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8610 23:22:20.498394 == TX Byte 0 ==
8611 23:22:20.500863 u2DelayCellOfst[0]=14 cells (4 PI)
8612 23:22:20.504562 u2DelayCellOfst[1]=7 cells (2 PI)
8613 23:22:20.507527 u2DelayCellOfst[2]=0 cells (0 PI)
8614 23:22:20.511391 u2DelayCellOfst[3]=3 cells (1 PI)
8615 23:22:20.514169 u2DelayCellOfst[4]=7 cells (2 PI)
8616 23:22:20.517821 u2DelayCellOfst[5]=14 cells (4 PI)
8617 23:22:20.520863 u2DelayCellOfst[6]=14 cells (4 PI)
8618 23:22:20.524370 u2DelayCellOfst[7]=3 cells (1 PI)
8619 23:22:20.527522 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8620 23:22:20.530954 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8621 23:22:20.534287 == TX Byte 1 ==
8622 23:22:20.537461 u2DelayCellOfst[8]=0 cells (0 PI)
8623 23:22:20.540532 u2DelayCellOfst[9]=3 cells (1 PI)
8624 23:22:20.540614 u2DelayCellOfst[10]=10 cells (3 PI)
8625 23:22:20.544047 u2DelayCellOfst[11]=0 cells (0 PI)
8626 23:22:20.547978 u2DelayCellOfst[12]=14 cells (4 PI)
8627 23:22:20.550968 u2DelayCellOfst[13]=18 cells (5 PI)
8628 23:22:20.553635 u2DelayCellOfst[14]=18 cells (5 PI)
8629 23:22:20.556955 u2DelayCellOfst[15]=18 cells (5 PI)
8630 23:22:20.563372 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8631 23:22:20.567204 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8632 23:22:20.567286 DramC Write-DBI on
8633 23:22:20.567352 ==
8634 23:22:20.570301 Dram Type= 6, Freq= 0, CH_1, rank 1
8635 23:22:20.576586 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8636 23:22:20.576669 ==
8637 23:22:20.576748
8638 23:22:20.576810
8639 23:22:20.576868 TX Vref Scan disable
8640 23:22:20.580637 == TX Byte 0 ==
8641 23:22:20.584976 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8642 23:22:20.587875 == TX Byte 1 ==
8643 23:22:20.591060 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8644 23:22:20.595736 DramC Write-DBI off
8645 23:22:20.595818
8646 23:22:20.595884 [DATLAT]
8647 23:22:20.595945 Freq=1600, CH1 RK1
8648 23:22:20.596004
8649 23:22:20.599283 DATLAT Default: 0xe
8650 23:22:20.599364 0, 0xFFFF, sum = 0
8651 23:22:20.600685 1, 0xFFFF, sum = 0
8652 23:22:20.604986 2, 0xFFFF, sum = 0
8653 23:22:20.605069 3, 0xFFFF, sum = 0
8654 23:22:20.607191 4, 0xFFFF, sum = 0
8655 23:22:20.607274 5, 0xFFFF, sum = 0
8656 23:22:20.612303 6, 0xFFFF, sum = 0
8657 23:22:20.612386 7, 0xFFFF, sum = 0
8658 23:22:20.614501 8, 0xFFFF, sum = 0
8659 23:22:20.614585 9, 0xFFFF, sum = 0
8660 23:22:20.617066 10, 0xFFFF, sum = 0
8661 23:22:20.617149 11, 0xFFFF, sum = 0
8662 23:22:20.621126 12, 0xF7F, sum = 0
8663 23:22:20.621209 13, 0x0, sum = 1
8664 23:22:20.623898 14, 0x0, sum = 2
8665 23:22:20.623981 15, 0x0, sum = 3
8666 23:22:20.627920 16, 0x0, sum = 4
8667 23:22:20.628003 best_step = 14
8668 23:22:20.628068
8669 23:22:20.628128 ==
8670 23:22:20.630230 Dram Type= 6, Freq= 0, CH_1, rank 1
8671 23:22:20.633421 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8672 23:22:20.637151 ==
8673 23:22:20.637233 RX Vref Scan: 0
8674 23:22:20.637298
8675 23:22:20.640199 RX Vref 0 -> 0, step: 1
8676 23:22:20.640280
8677 23:22:20.643691 RX Delay 3 -> 252, step: 4
8678 23:22:20.646901 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8679 23:22:20.650102 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8680 23:22:20.653798 iDelay=195, Bit 2, Center 118 (63 ~ 174) 112
8681 23:22:20.660082 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8682 23:22:20.663306 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8683 23:22:20.667196 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8684 23:22:20.670481 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8685 23:22:20.673127 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8686 23:22:20.679895 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8687 23:22:20.683233 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8688 23:22:20.686645 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8689 23:22:20.689936 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8690 23:22:20.693251 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8691 23:22:20.699774 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8692 23:22:20.703691 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8693 23:22:20.706139 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8694 23:22:20.706220 ==
8695 23:22:20.710283 Dram Type= 6, Freq= 0, CH_1, rank 1
8696 23:22:20.713808 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8697 23:22:20.716606 ==
8698 23:22:20.716687 DQS Delay:
8699 23:22:20.716810 DQS0 = 0, DQS1 = 0
8700 23:22:20.720022 DQM Delay:
8701 23:22:20.720102 DQM0 = 127, DQM1 = 122
8702 23:22:20.723429 DQ Delay:
8703 23:22:20.726205 DQ0 =128, DQ1 =124, DQ2 =118, DQ3 =124
8704 23:22:20.730179 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8705 23:22:20.732908 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8706 23:22:20.736115 DQ12 =130, DQ13 =132, DQ14 =134, DQ15 =132
8707 23:22:20.736218
8708 23:22:20.736283
8709 23:22:20.736342
8710 23:22:20.739393 [DramC_TX_OE_Calibration] TA2
8711 23:22:20.743032 Original DQ_B0 (3 6) =30, OEN = 27
8712 23:22:20.746174 Original DQ_B1 (3 6) =30, OEN = 27
8713 23:22:20.749709 24, 0x0, End_B0=24 End_B1=24
8714 23:22:20.749790 25, 0x0, End_B0=25 End_B1=25
8715 23:22:20.752999 26, 0x0, End_B0=26 End_B1=26
8716 23:22:20.756159 27, 0x0, End_B0=27 End_B1=27
8717 23:22:20.759790 28, 0x0, End_B0=28 End_B1=28
8718 23:22:20.759872 29, 0x0, End_B0=29 End_B1=29
8719 23:22:20.763162 30, 0x0, End_B0=30 End_B1=30
8720 23:22:20.766058 31, 0x4141, End_B0=30 End_B1=30
8721 23:22:20.770181 Byte0 end_step=30 best_step=27
8722 23:22:20.772888 Byte1 end_step=30 best_step=27
8723 23:22:20.775655 Byte0 TX OE(2T, 0.5T) = (3, 3)
8724 23:22:20.775735 Byte1 TX OE(2T, 0.5T) = (3, 3)
8725 23:22:20.779273
8726 23:22:20.779353
8727 23:22:20.785756 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8728 23:22:20.789048 CH1 RK1: MR19=303, MR18=1C1C
8729 23:22:20.796297 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8730 23:22:20.799150 [RxdqsGatingPostProcess] freq 1600
8731 23:22:20.802354 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8732 23:22:20.805613 Pre-setting of DQS Precalculation
8733 23:22:20.812518 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8734 23:22:20.819852 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8735 23:22:20.825780 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8736 23:22:20.825951
8737 23:22:20.826037
8738 23:22:20.829364 [Calibration Summary] 3200 Mbps
8739 23:22:20.829474 CH 0, Rank 0
8740 23:22:20.832369 SW Impedance : PASS
8741 23:22:20.836242 DUTY Scan : NO K
8742 23:22:20.836358 ZQ Calibration : PASS
8743 23:22:20.838611 Jitter Meter : NO K
8744 23:22:20.842880 CBT Training : PASS
8745 23:22:20.843026 Write leveling : PASS
8746 23:22:20.846113 RX DQS gating : PASS
8747 23:22:20.849102 RX DQ/DQS(RDDQC) : PASS
8748 23:22:20.849254 TX DQ/DQS : PASS
8749 23:22:20.854382 RX DATLAT : PASS
8750 23:22:20.856194 RX DQ/DQS(Engine): PASS
8751 23:22:20.856430 TX OE : PASS
8752 23:22:20.856577 All Pass.
8753 23:22:20.858458
8754 23:22:20.858660 CH 0, Rank 1
8755 23:22:20.862318 SW Impedance : PASS
8756 23:22:20.862522 DUTY Scan : NO K
8757 23:22:20.865768 ZQ Calibration : PASS
8758 23:22:20.868437 Jitter Meter : NO K
8759 23:22:20.868850 CBT Training : PASS
8760 23:22:20.872013 Write leveling : PASS
8761 23:22:20.872333 RX DQS gating : PASS
8762 23:22:20.876261 RX DQ/DQS(RDDQC) : PASS
8763 23:22:20.878460 TX DQ/DQS : PASS
8764 23:22:20.878885 RX DATLAT : PASS
8765 23:22:20.881988 RX DQ/DQS(Engine): PASS
8766 23:22:20.885202 TX OE : PASS
8767 23:22:20.885624 All Pass.
8768 23:22:20.885960
8769 23:22:20.886272 CH 1, Rank 0
8770 23:22:20.889018 SW Impedance : PASS
8771 23:22:20.891709 DUTY Scan : NO K
8772 23:22:20.892208 ZQ Calibration : PASS
8773 23:22:20.895627 Jitter Meter : NO K
8774 23:22:20.898560 CBT Training : PASS
8775 23:22:20.898985 Write leveling : PASS
8776 23:22:20.901793 RX DQS gating : PASS
8777 23:22:20.905781 RX DQ/DQS(RDDQC) : PASS
8778 23:22:20.906202 TX DQ/DQS : PASS
8779 23:22:20.908624 RX DATLAT : PASS
8780 23:22:20.911809 RX DQ/DQS(Engine): PASS
8781 23:22:20.912229 TX OE : PASS
8782 23:22:20.915656 All Pass.
8783 23:22:20.916077
8784 23:22:20.916411 CH 1, Rank 1
8785 23:22:20.918818 SW Impedance : PASS
8786 23:22:20.919241 DUTY Scan : NO K
8787 23:22:20.922016 ZQ Calibration : PASS
8788 23:22:20.925111 Jitter Meter : NO K
8789 23:22:20.925192 CBT Training : PASS
8790 23:22:20.929106 Write leveling : PASS
8791 23:22:20.929188 RX DQS gating : PASS
8792 23:22:20.932375 RX DQ/DQS(RDDQC) : PASS
8793 23:22:20.934973 TX DQ/DQS : PASS
8794 23:22:20.935056 RX DATLAT : PASS
8795 23:22:20.938075 RX DQ/DQS(Engine): PASS
8796 23:22:20.941917 TX OE : PASS
8797 23:22:20.941999 All Pass.
8798 23:22:20.942064
8799 23:22:20.945272 DramC Write-DBI on
8800 23:22:20.945371 PER_BANK_REFRESH: Hybrid Mode
8801 23:22:20.947863 TX_TRACKING: ON
8802 23:22:20.957990 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8803 23:22:20.965089 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8804 23:22:20.971872 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8805 23:22:20.974605 [FAST_K] Save calibration result to emmc
8806 23:22:20.977891 sync common calibartion params.
8807 23:22:20.981097 sync cbt_mode0:0, 1:0
8808 23:22:20.981179 dram_init: ddr_geometry: 0
8809 23:22:20.984399 dram_init: ddr_geometry: 0
8810 23:22:20.987742 dram_init: ddr_geometry: 0
8811 23:22:20.991212 0:dram_rank_size:80000000
8812 23:22:20.991302 1:dram_rank_size:80000000
8813 23:22:20.997574 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8814 23:22:21.001513 DFS_SHUFFLE_HW_MODE: ON
8815 23:22:21.004754 dramc_set_vcore_voltage set vcore to 725000
8816 23:22:21.004866 Read voltage for 1600, 0
8817 23:22:21.008188 Vio18 = 0
8818 23:22:21.008309 Vcore = 725000
8819 23:22:21.008406 Vdram = 0
8820 23:22:21.012043 Vddq = 0
8821 23:22:21.012243 Vmddr = 0
8822 23:22:21.014667 switch to 3200 Mbps bootup
8823 23:22:21.014818 [DramcRunTimeConfig]
8824 23:22:21.014927 PHYPLL
8825 23:22:21.017882 DPM_CONTROL_AFTERK: ON
8826 23:22:21.022011 PER_BANK_REFRESH: ON
8827 23:22:21.022163 REFRESH_OVERHEAD_REDUCTION: ON
8828 23:22:21.025034 CMD_PICG_NEW_MODE: OFF
8829 23:22:21.028581 XRTWTW_NEW_MODE: ON
8830 23:22:21.028802 XRTRTR_NEW_MODE: ON
8831 23:22:21.031173 TX_TRACKING: ON
8832 23:22:21.031376 RDSEL_TRACKING: OFF
8833 23:22:21.034930 DQS Precalculation for DVFS: ON
8834 23:22:21.035171 RX_TRACKING: OFF
8835 23:22:21.037847 HW_GATING DBG: ON
8836 23:22:21.040980 ZQCS_ENABLE_LP4: ON
8837 23:22:21.041137 RX_PICG_NEW_MODE: ON
8838 23:22:21.044668 TX_PICG_NEW_MODE: ON
8839 23:22:21.044793 ENABLE_RX_DCM_DPHY: ON
8840 23:22:21.047514 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8841 23:22:21.050627 DUMMY_READ_FOR_TRACKING: OFF
8842 23:22:21.054184 !!! SPM_CONTROL_AFTERK: OFF
8843 23:22:21.057676 !!! SPM could not control APHY
8844 23:22:21.057759 IMPEDANCE_TRACKING: ON
8845 23:22:21.061362 TEMP_SENSOR: ON
8846 23:22:21.061523 HW_SAVE_FOR_SR: OFF
8847 23:22:21.064587 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8848 23:22:21.068044 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8849 23:22:21.070775 Read ODT Tracking: ON
8850 23:22:21.074654 Refresh Rate DeBounce: ON
8851 23:22:21.074737 DFS_NO_QUEUE_FLUSH: ON
8852 23:22:21.077045 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8853 23:22:21.080530 ENABLE_DFS_RUNTIME_MRW: OFF
8854 23:22:21.084024 DDR_RESERVE_NEW_MODE: ON
8855 23:22:21.084106 MR_CBT_SWITCH_FREQ: ON
8856 23:22:21.087159 =========================
8857 23:22:21.105492 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8858 23:22:21.108960 dram_init: ddr_geometry: 0
8859 23:22:21.127038 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8860 23:22:21.130333 dram_init: dram init end (result: 0)
8861 23:22:21.136718 DRAM-K: Full calibration passed in 23416 msecs
8862 23:22:21.140428 MRC: failed to locate region type 0.
8863 23:22:21.140630 DRAM rank0 size:0x80000000,
8864 23:22:21.143312 DRAM rank1 size=0x80000000
8865 23:22:21.154522 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8866 23:22:21.160031 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8867 23:22:21.166592 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8868 23:22:21.173002 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8869 23:22:21.176692 DRAM rank0 size:0x80000000,
8870 23:22:21.179823 DRAM rank1 size=0x80000000
8871 23:22:21.179905 CBMEM:
8872 23:22:21.183934 IMD: root @ 0xfffff000 254 entries.
8873 23:22:21.186842 IMD: root @ 0xffffec00 62 entries.
8874 23:22:21.190187 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8875 23:22:21.192997 WARNING: RO_VPD is uninitialized or empty.
8876 23:22:21.199404 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8877 23:22:21.207035 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8878 23:22:21.219171 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8879 23:22:21.230915 BS: romstage times (exec / console): total (unknown) / 22955 ms
8880 23:22:21.231812
8881 23:22:21.232579
8882 23:22:21.240476 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8883 23:22:21.243711 ARM64: Exception handlers installed.
8884 23:22:21.247458 ARM64: Testing exception
8885 23:22:21.250460 ARM64: Done test exception
8886 23:22:21.250579 Enumerating buses...
8887 23:22:21.253823 Show all devs... Before device enumeration.
8888 23:22:21.256718 Root Device: enabled 1
8889 23:22:21.260559 CPU_CLUSTER: 0: enabled 1
8890 23:22:21.260681 CPU: 00: enabled 1
8891 23:22:21.264381 Compare with tree...
8892 23:22:21.264516 Root Device: enabled 1
8893 23:22:21.266789 CPU_CLUSTER: 0: enabled 1
8894 23:22:21.270636 CPU: 00: enabled 1
8895 23:22:21.270789 Root Device scanning...
8896 23:22:21.273856 scan_static_bus for Root Device
8897 23:22:21.277059 CPU_CLUSTER: 0 enabled
8898 23:22:21.279926 scan_static_bus for Root Device done
8899 23:22:21.283184 scan_bus: bus Root Device finished in 8 msecs
8900 23:22:21.283427 done
8901 23:22:21.290148 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8902 23:22:21.294109 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8903 23:22:21.300294 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8904 23:22:21.303527 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8905 23:22:21.306354 Allocating resources...
8906 23:22:21.309845 Reading resources...
8907 23:22:21.313066 Root Device read_resources bus 0 link: 0
8908 23:22:21.318007 DRAM rank0 size:0x80000000,
8909 23:22:21.318430 DRAM rank1 size=0x80000000
8910 23:22:21.319628 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8911 23:22:21.323310 CPU: 00 missing read_resources
8912 23:22:21.329672 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8913 23:22:21.333256 Root Device read_resources bus 0 link: 0 done
8914 23:22:21.333679 Done reading resources.
8915 23:22:21.340341 Show resources in subtree (Root Device)...After reading.
8916 23:22:21.343383 Root Device child on link 0 CPU_CLUSTER: 0
8917 23:22:21.346411 CPU_CLUSTER: 0 child on link 0 CPU: 00
8918 23:22:21.356847 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8919 23:22:21.357408 CPU: 00
8920 23:22:21.359465 Root Device assign_resources, bus 0 link: 0
8921 23:22:21.363001 CPU_CLUSTER: 0 missing set_resources
8922 23:22:21.369878 Root Device assign_resources, bus 0 link: 0 done
8923 23:22:21.370448 Done setting resources.
8924 23:22:21.376414 Show resources in subtree (Root Device)...After assigning values.
8925 23:22:21.379705 Root Device child on link 0 CPU_CLUSTER: 0
8926 23:22:21.383180 CPU_CLUSTER: 0 child on link 0 CPU: 00
8927 23:22:21.392898 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8928 23:22:21.393371 CPU: 00
8929 23:22:21.396357 Done allocating resources.
8930 23:22:21.402889 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8931 23:22:21.403358 Enabling resources...
8932 23:22:21.403728 done.
8933 23:22:21.409218 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8934 23:22:21.409701 Initializing devices...
8935 23:22:21.412972 Root Device init
8936 23:22:21.413436 init hardware done!
8937 23:22:21.416982 0x00000018: ctrlr->caps
8938 23:22:21.419759 52.000 MHz: ctrlr->f_max
8939 23:22:21.420237 0.400 MHz: ctrlr->f_min
8940 23:22:21.422917 0x40ff8080: ctrlr->voltages
8941 23:22:21.426335 sclk: 390625
8942 23:22:21.426797 Bus Width = 1
8943 23:22:21.427171 sclk: 390625
8944 23:22:21.429325 Bus Width = 1
8945 23:22:21.429786 Early init status = 3
8946 23:22:21.436671 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8947 23:22:21.440113 in-header: 03 fc 00 00 01 00 00 00
8948 23:22:21.442428 in-data: 00
8949 23:22:21.446029 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8950 23:22:21.450195 in-header: 03 fd 00 00 00 00 00 00
8951 23:22:21.454796 in-data:
8952 23:22:21.456260 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8953 23:22:21.460223 in-header: 03 fc 00 00 01 00 00 00
8954 23:22:21.463522 in-data: 00
8955 23:22:21.466479 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8956 23:22:21.471562 in-header: 03 fd 00 00 00 00 00 00
8957 23:22:21.475054 in-data:
8958 23:22:21.478970 [SSUSB] Setting up USB HOST controller...
8959 23:22:21.481520 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8960 23:22:21.484782 [SSUSB] phy power-on done.
8961 23:22:21.489011 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8962 23:22:21.494798 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8963 23:22:21.498118 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8964 23:22:21.504992 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8965 23:22:21.511408 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
8966 23:22:21.518747 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8967 23:22:21.525229 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8968 23:22:21.530967 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8969 23:22:21.534249 SPM: binary array size = 0x9dc
8970 23:22:21.538208 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8971 23:22:21.544342 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8972 23:22:21.550429 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8973 23:22:21.557798 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8974 23:22:21.561286 configure_display: Starting display init
8975 23:22:21.594890 anx7625_power_on_init: Init interface.
8976 23:22:21.598419 anx7625_disable_pd_protocol: Disabled PD feature.
8977 23:22:21.601852 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8978 23:22:21.629579 anx7625_start_dp_work: Secure OCM version=00
8979 23:22:21.632964 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8980 23:22:21.646903 sp_tx_get_edid_block: EDID Block = 1
8981 23:22:21.750394 Extracted contents:
8982 23:22:21.753283 header: 00 ff ff ff ff ff ff 00
8983 23:22:21.757320 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8984 23:22:21.759902 version: 01 04
8985 23:22:21.763162 basic params: 95 1f 11 78 0a
8986 23:22:21.766467 chroma info: 76 90 94 55 54 90 27 21 50 54
8987 23:22:21.769714 established: 00 00 00
8988 23:22:21.776772 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8989 23:22:21.780524 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8990 23:22:21.786789 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8991 23:22:21.793716 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8992 23:22:21.799874 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8993 23:22:21.802996 extensions: 00
8994 23:22:21.803463 checksum: fb
8995 23:22:21.803835
8996 23:22:21.806595 Manufacturer: IVO Model 57d Serial Number 0
8997 23:22:21.809628 Made week 0 of 2020
8998 23:22:21.810093 EDID version: 1.4
8999 23:22:21.812671 Digital display
9000 23:22:21.815988 6 bits per primary color channel
9001 23:22:21.816417 DisplayPort interface
9002 23:22:21.819967 Maximum image size: 31 cm x 17 cm
9003 23:22:21.823375 Gamma: 220%
9004 23:22:21.823798 Check DPMS levels
9005 23:22:21.825949 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9006 23:22:21.832699 First detailed timing is preferred timing
9007 23:22:21.833160 Established timings supported:
9008 23:22:21.836945 Standard timings supported:
9009 23:22:21.839655 Detailed timings
9010 23:22:21.843448 Hex of detail: 383680a07038204018303c0035ae10000019
9011 23:22:21.849154 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9012 23:22:21.852809 0780 0798 07c8 0820 hborder 0
9013 23:22:21.855766 0438 043b 0447 0458 vborder 0
9014 23:22:21.858721 -hsync -vsync
9015 23:22:21.858803 Did detailed timing
9016 23:22:21.865921 Hex of detail: 000000000000000000000000000000000000
9017 23:22:21.868744 Manufacturer-specified data, tag 0
9018 23:22:21.872270 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9019 23:22:21.875648 ASCII string: InfoVision
9020 23:22:21.878554 Hex of detail: 000000fe00523134304e574635205248200a
9021 23:22:21.881815 ASCII string: R140NWF5 RH
9022 23:22:21.881896 Checksum
9023 23:22:21.884997 Checksum: 0xfb (valid)
9024 23:22:21.889351 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9025 23:22:21.892321 DSI data_rate: 832800000 bps
9026 23:22:21.898630 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9027 23:22:21.901787 anx7625_parse_edid: pixelclock(138800).
9028 23:22:21.904968 hactive(1920), hsync(48), hfp(24), hbp(88)
9029 23:22:21.908720 vactive(1080), vsync(12), vfp(3), vbp(17)
9030 23:22:21.912236 anx7625_dsi_config: config dsi.
9031 23:22:21.918689 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9032 23:22:21.931747 anx7625_dsi_config: success to config DSI
9033 23:22:21.935135 anx7625_dp_start: MIPI phy setup OK.
9034 23:22:21.938620 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9035 23:22:21.942460 mtk_ddp_mode_set invalid vrefresh 60
9036 23:22:21.945341 main_disp_path_setup
9037 23:22:21.945424 ovl_layer_smi_id_en
9038 23:22:21.948490 ovl_layer_smi_id_en
9039 23:22:21.948578 ccorr_config
9040 23:22:21.948650 aal_config
9041 23:22:21.952332 gamma_config
9042 23:22:21.952495 postmask_config
9043 23:22:21.955518 dither_config
9044 23:22:21.958645 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9045 23:22:21.965810 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9046 23:22:21.968495 Root Device init finished in 552 msecs
9047 23:22:21.972159 CPU_CLUSTER: 0 init
9048 23:22:21.978146 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9049 23:22:21.981611 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9050 23:22:21.984779 APU_MBOX 0x190000b0 = 0x10001
9051 23:22:21.988120 APU_MBOX 0x190001b0 = 0x10001
9052 23:22:21.992250 APU_MBOX 0x190005b0 = 0x10001
9053 23:22:21.994878 APU_MBOX 0x190006b0 = 0x10001
9054 23:22:21.998606 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9055 23:22:22.011455 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9056 23:22:22.023712 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9057 23:22:22.030388 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9058 23:22:22.042344 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9059 23:22:22.050920 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9060 23:22:22.054242 CPU_CLUSTER: 0 init finished in 81 msecs
9061 23:22:22.057662 Devices initialized
9062 23:22:22.060817 Show all devs... After init.
9063 23:22:22.061294 Root Device: enabled 1
9064 23:22:22.063900 CPU_CLUSTER: 0: enabled 1
9065 23:22:22.067738 CPU: 00: enabled 1
9066 23:22:22.070853 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9067 23:22:22.073817 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9068 23:22:22.077402 ELOG: NV offset 0x57f000 size 0x1000
9069 23:22:22.083708 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9070 23:22:22.090722 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9071 23:22:22.093800 ELOG: Event(17) added with size 13 at 2024-04-03 23:22:22 UTC
9072 23:22:22.100433 out: cmd=0x121: 03 db 21 01 00 00 00 00
9073 23:22:22.103838 in-header: 03 03 00 00 2c 00 00 00
9074 23:22:22.113554 in-data: 60 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9075 23:22:22.120664 ELOG: Event(A1) added with size 10 at 2024-04-03 23:22:22 UTC
9076 23:22:22.127594 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9077 23:22:22.133489 ELOG: Event(A0) added with size 9 at 2024-04-03 23:22:22 UTC
9078 23:22:22.137468 elog_add_boot_reason: Logged dev mode boot
9079 23:22:22.143812 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9080 23:22:22.144385 Finalize devices...
9081 23:22:22.147477 Devices finalized
9082 23:22:22.150103 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9083 23:22:22.153417 Writing coreboot table at 0xffe64000
9084 23:22:22.156816 0. 000000000010a000-0000000000113fff: RAMSTAGE
9085 23:22:22.163486 1. 0000000040000000-00000000400fffff: RAM
9086 23:22:22.166169 2. 0000000040100000-000000004032afff: RAMSTAGE
9087 23:22:22.169533 3. 000000004032b000-00000000545fffff: RAM
9088 23:22:22.172899 4. 0000000054600000-000000005465ffff: BL31
9089 23:22:22.177014 5. 0000000054660000-00000000ffe63fff: RAM
9090 23:22:22.183353 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9091 23:22:22.186759 7. 0000000100000000-000000013fffffff: RAM
9092 23:22:22.189296 Passing 5 GPIOs to payload:
9093 23:22:22.192820 NAME | PORT | POLARITY | VALUE
9094 23:22:22.199845 EC in RW | 0x000000aa | low | undefined
9095 23:22:22.203003 EC interrupt | 0x00000005 | low | undefined
9096 23:22:22.205962 TPM interrupt | 0x000000ab | high | undefined
9097 23:22:22.212379 SD card detect | 0x00000011 | high | undefined
9098 23:22:22.216652 speaker enable | 0x00000093 | high | undefined
9099 23:22:22.219165 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9100 23:22:22.222768 in-header: 03 f8 00 00 02 00 00 00
9101 23:22:22.225509 in-data: 03 00
9102 23:22:22.229477 ADC[4]: Raw value=669327 ID=5
9103 23:22:22.232560 ADC[3]: Raw value=212549 ID=1
9104 23:22:22.233074 RAM Code: 0x51
9105 23:22:22.235900 ADC[6]: Raw value=74410 ID=0
9106 23:22:22.239651 ADC[5]: Raw value=212180 ID=1
9107 23:22:22.240213 SKU Code: 0x1
9108 23:22:22.245464 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c27f
9109 23:22:22.245937 coreboot table: 964 bytes.
9110 23:22:22.248876 IMD ROOT 0. 0xfffff000 0x00001000
9111 23:22:22.252540 IMD SMALL 1. 0xffffe000 0x00001000
9112 23:22:22.255903 RO MCACHE 2. 0xffffc000 0x00001104
9113 23:22:22.259735 CONSOLE 3. 0xfff7c000 0x00080000
9114 23:22:22.262626 FMAP 4. 0xfff7b000 0x00000452
9115 23:22:22.265517 TIME STAMP 5. 0xfff7a000 0x00000910
9116 23:22:22.269122 VBOOT WORK 6. 0xfff66000 0x00014000
9117 23:22:22.272034 RAMOOPS 7. 0xffe66000 0x00100000
9118 23:22:22.275484 COREBOOT 8. 0xffe64000 0x00002000
9119 23:22:22.278735 IMD small region:
9120 23:22:22.282150 IMD ROOT 0. 0xffffec00 0x00000400
9121 23:22:22.284803 VPD 1. 0xffffeb80 0x0000006c
9122 23:22:22.288192 MMC STATUS 2. 0xffffeb60 0x00000004
9123 23:22:22.294801 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9124 23:22:22.295477 Probing TPM: done!
9125 23:22:22.302134 Connected to device vid:did:rid of 1ae0:0028:00
9126 23:22:22.308250 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9127 23:22:22.311832 Initialized TPM device CR50 revision 0
9128 23:22:22.314870 Checking cr50 for pending updates
9129 23:22:22.320258 Reading cr50 TPM mode
9130 23:22:22.329976 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9131 23:22:22.336173 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9132 23:22:22.375905 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9133 23:22:22.379295 Checking segment from ROM address 0x40100000
9134 23:22:22.382623 Checking segment from ROM address 0x4010001c
9135 23:22:22.389096 Loading segment from ROM address 0x40100000
9136 23:22:22.389566 code (compression=0)
9137 23:22:22.396660 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9138 23:22:22.405849 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9139 23:22:22.406318 it's not compressed!
9140 23:22:22.412485 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9141 23:22:22.416017 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9142 23:22:22.436843 Loading segment from ROM address 0x4010001c
9143 23:22:22.437370 Entry Point 0x80000000
9144 23:22:22.440160 Loaded segments
9145 23:22:22.443001 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9146 23:22:22.449876 Jumping to boot code at 0x80000000(0xffe64000)
9147 23:22:22.456845 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9148 23:22:22.463096 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9149 23:22:22.471000 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9150 23:22:22.474656 Checking segment from ROM address 0x40100000
9151 23:22:22.477311 Checking segment from ROM address 0x4010001c
9152 23:22:22.484410 Loading segment from ROM address 0x40100000
9153 23:22:22.484987 code (compression=1)
9154 23:22:22.490750 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9155 23:22:22.500623 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9156 23:22:22.501191 using LZMA
9157 23:22:22.509342 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9158 23:22:22.516235 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9159 23:22:22.519053 Loading segment from ROM address 0x4010001c
9160 23:22:22.519520 Entry Point 0x54601000
9161 23:22:22.522739 Loaded segments
9162 23:22:22.525345 NOTICE: MT8192 bl31_setup
9163 23:22:22.533126 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9164 23:22:22.536902 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9165 23:22:22.539554 WARNING: region 0:
9166 23:22:22.542680 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9167 23:22:22.543244 WARNING: region 1:
9168 23:22:22.549228 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9169 23:22:22.552946 WARNING: region 2:
9170 23:22:22.555718 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9171 23:22:22.559440 WARNING: region 3:
9172 23:22:22.563407 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9173 23:22:22.566918 WARNING: region 4:
9174 23:22:22.572454 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9175 23:22:22.572997 WARNING: region 5:
9176 23:22:22.576176 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9177 23:22:22.579167 WARNING: region 6:
9178 23:22:22.582978 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9179 23:22:22.586468 WARNING: region 7:
9180 23:22:22.589404 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9181 23:22:22.595587 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9182 23:22:22.599233 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9183 23:22:22.603510 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9184 23:22:22.609698 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9185 23:22:22.613189 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9186 23:22:22.616384 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9187 23:22:22.622541 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9188 23:22:22.626181 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9189 23:22:22.632555 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9190 23:22:22.635807 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9191 23:22:22.639516 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9192 23:22:22.645541 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9193 23:22:22.649004 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9194 23:22:22.652526 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9195 23:22:22.659214 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9196 23:22:22.662087 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9197 23:22:22.669390 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9198 23:22:22.672341 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9199 23:22:22.675923 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9200 23:22:22.682800 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9201 23:22:22.685393 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9202 23:22:22.688849 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9203 23:22:22.696078 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9204 23:22:22.698816 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9205 23:22:22.706199 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9206 23:22:22.709768 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9207 23:22:22.712506 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9208 23:22:22.719062 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9209 23:22:22.722226 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9210 23:22:22.729346 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9211 23:22:22.732242 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9212 23:22:22.735936 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9213 23:22:22.742620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9214 23:22:22.745285 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9215 23:22:22.749441 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9216 23:22:22.752264 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9217 23:22:22.758596 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9218 23:22:22.762028 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9219 23:22:22.765482 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9220 23:22:22.768830 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9221 23:22:22.775335 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9222 23:22:22.778561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9223 23:22:22.781899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9224 23:22:22.785119 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9225 23:22:22.791960 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9226 23:22:22.795681 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9227 23:22:22.798305 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9228 23:22:22.805310 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9229 23:22:22.808647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9230 23:22:22.812001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9231 23:22:22.819194 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9232 23:22:22.822173 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9233 23:22:22.828738 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9234 23:22:22.831961 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9235 23:22:22.835481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9236 23:22:22.841620 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9237 23:22:22.845024 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9238 23:22:22.852003 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9239 23:22:22.854842 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9240 23:22:22.861595 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9241 23:22:22.864945 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9242 23:22:22.871902 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9243 23:22:22.875306 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9244 23:22:22.878597 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9245 23:22:22.885277 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9246 23:22:22.889210 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9247 23:22:22.895062 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9248 23:22:22.898468 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9249 23:22:22.905050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9250 23:22:22.908615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9251 23:22:22.911859 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9252 23:22:22.918976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9253 23:22:22.921777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9254 23:22:22.928184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9255 23:22:22.931950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9256 23:22:22.938445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9257 23:22:22.943211 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9258 23:22:22.948328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9259 23:22:22.951739 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9260 23:22:22.955531 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9261 23:22:22.962984 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9262 23:22:22.965052 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9263 23:22:22.971954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9264 23:22:22.975129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9265 23:22:22.981824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9266 23:22:22.985927 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9267 23:22:22.988373 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9268 23:22:22.995413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9269 23:22:22.998430 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9270 23:22:23.005425 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9271 23:22:23.008559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9272 23:22:23.015329 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9273 23:22:23.018580 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9274 23:22:23.021794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9275 23:22:23.028668 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9276 23:22:23.032126 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9277 23:22:23.038687 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9278 23:22:23.042218 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9279 23:22:23.045386 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9280 23:22:23.048841 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9281 23:22:23.052513 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9282 23:22:23.059149 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9283 23:22:23.061510 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9284 23:22:23.068312 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9285 23:22:23.071460 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9286 23:22:23.078761 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9287 23:22:23.081910 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9288 23:22:23.085605 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9289 23:22:23.091571 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9290 23:22:23.095037 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9291 23:22:23.098323 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9292 23:22:23.105287 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9293 23:22:23.108148 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9294 23:22:23.115137 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9295 23:22:23.118338 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9296 23:22:23.121926 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9297 23:22:23.128332 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9298 23:22:23.132126 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9299 23:22:23.134610 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9300 23:22:23.141835 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9301 23:22:23.145617 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9302 23:22:23.148003 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9303 23:22:23.151265 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9304 23:22:23.158643 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9305 23:22:23.161297 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9306 23:22:23.164626 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9307 23:22:23.171096 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9308 23:22:23.174475 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9309 23:22:23.181620 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9310 23:22:23.184559 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9311 23:22:23.188395 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9312 23:22:23.194998 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9313 23:22:23.198182 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9314 23:22:23.204797 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9315 23:22:23.207821 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9316 23:22:23.211247 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9317 23:22:23.218531 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9318 23:22:23.221502 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9319 23:22:23.224687 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9320 23:22:23.231001 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9321 23:22:23.234683 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9322 23:22:23.241371 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9323 23:22:23.244591 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9324 23:22:23.247900 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9325 23:22:23.254951 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9326 23:22:23.258444 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9327 23:22:23.261844 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9328 23:22:23.268244 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9329 23:22:23.272290 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9330 23:22:23.279087 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9331 23:22:23.281346 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9332 23:22:23.284804 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9333 23:22:23.291839 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9334 23:22:23.295244 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9335 23:22:23.301759 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9336 23:22:23.305057 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9337 23:22:23.308889 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9338 23:22:23.315399 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9339 23:22:23.319314 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9340 23:22:23.321972 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9341 23:22:23.329117 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9342 23:22:23.331654 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9343 23:22:23.338222 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9344 23:22:23.341437 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9345 23:22:23.345801 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9346 23:22:23.351430 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9347 23:22:23.354482 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9348 23:22:23.361206 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9349 23:22:23.364465 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9350 23:22:23.370996 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9351 23:22:23.374695 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9352 23:22:23.377816 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9353 23:22:23.384784 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9354 23:22:23.387376 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9355 23:22:23.390617 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9356 23:22:23.397511 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9357 23:22:23.400921 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9358 23:22:23.407854 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9359 23:22:23.410400 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9360 23:22:23.414079 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9361 23:22:23.421582 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9362 23:22:23.423555 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9363 23:22:23.430733 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9364 23:22:23.433747 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9365 23:22:23.437300 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9366 23:22:23.444035 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9367 23:22:23.447246 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9368 23:22:23.453201 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9369 23:22:23.457127 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9370 23:22:23.460394 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9371 23:22:23.467299 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9372 23:22:23.470364 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9373 23:22:23.476651 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9374 23:22:23.479756 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9375 23:22:23.487002 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9376 23:22:23.490193 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9377 23:22:23.493093 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9378 23:22:23.500196 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9379 23:22:23.503588 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9380 23:22:23.509786 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9381 23:22:23.513108 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9382 23:22:23.519483 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9383 23:22:23.522687 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9384 23:22:23.526394 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9385 23:22:23.532882 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9386 23:22:23.535910 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9387 23:22:23.543490 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9388 23:22:23.546079 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9389 23:22:23.552630 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9390 23:22:23.555952 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9391 23:22:23.559231 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9392 23:22:23.565868 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9393 23:22:23.569197 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9394 23:22:23.576535 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9395 23:22:23.578883 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9396 23:22:23.582761 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9397 23:22:23.588978 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9398 23:22:23.592574 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9399 23:22:23.599289 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9400 23:22:23.602849 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9401 23:22:23.609415 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9402 23:22:23.612200 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9403 23:22:23.615980 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9404 23:22:23.622429 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9405 23:22:23.625685 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9406 23:22:23.631619 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9407 23:22:23.635517 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9408 23:22:23.642303 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9409 23:22:23.645173 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9410 23:22:23.649069 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9411 23:22:23.651811 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9412 23:22:23.658380 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9413 23:22:23.661432 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9414 23:22:23.665324 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9415 23:22:23.671522 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9416 23:22:23.675947 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9417 23:22:23.678026 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9418 23:22:23.685236 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9419 23:22:23.688095 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9420 23:22:23.691409 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9421 23:22:23.698459 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9422 23:22:23.701050 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9423 23:22:23.707892 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9424 23:22:23.711855 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9425 23:22:23.714771 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9426 23:22:23.721617 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9427 23:22:23.724426 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9428 23:22:23.727785 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9429 23:22:23.734239 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9430 23:22:23.738057 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9431 23:22:23.744299 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9432 23:22:23.747520 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9433 23:22:23.750824 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9434 23:22:23.757616 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9435 23:22:23.761215 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9436 23:22:23.764261 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9437 23:22:23.770593 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9438 23:22:23.773889 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9439 23:22:23.777576 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9440 23:22:23.784108 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9441 23:22:23.787611 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9442 23:22:23.793672 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9443 23:22:23.797196 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9444 23:22:23.800791 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9445 23:22:23.806626 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9446 23:22:23.810070 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9447 23:22:23.814083 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9448 23:22:23.820487 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9449 23:22:23.823399 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9450 23:22:23.826782 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9451 23:22:23.833688 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9452 23:22:23.837681 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9453 23:22:23.840324 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9454 23:22:23.844109 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9455 23:22:23.849791 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9456 23:22:23.853149 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9457 23:22:23.856830 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9458 23:22:23.859837 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9459 23:22:23.867083 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9460 23:22:23.869964 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9461 23:22:23.872939 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9462 23:22:23.876313 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9463 23:22:23.883104 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9464 23:22:23.886593 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9465 23:22:23.892538 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9466 23:22:23.896374 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9467 23:22:23.903686 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9468 23:22:23.905782 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9469 23:22:23.909324 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9470 23:22:23.915800 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9471 23:22:23.918973 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9472 23:22:23.925696 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9473 23:22:23.929259 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9474 23:22:23.935505 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9475 23:22:23.939662 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9476 23:22:23.943290 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9477 23:22:23.949652 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9478 23:22:23.951946 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9479 23:22:23.958882 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9480 23:22:23.961864 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9481 23:22:23.965248 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9482 23:22:23.972144 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9483 23:22:23.975676 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9484 23:22:23.981546 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9485 23:22:23.985499 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9486 23:22:23.988309 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9487 23:22:23.995267 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9488 23:22:23.998695 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9489 23:22:24.004999 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9490 23:22:24.008376 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9491 23:22:24.014803 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9492 23:22:24.019164 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9493 23:22:24.024677 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9494 23:22:24.028244 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9495 23:22:24.031623 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9496 23:22:24.037827 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9497 23:22:24.041392 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9498 23:22:24.044371 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9499 23:22:24.050891 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9500 23:22:24.054679 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9501 23:22:24.061052 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9502 23:22:24.065294 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9503 23:22:24.071175 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9504 23:22:24.075091 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9505 23:22:24.077842 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9506 23:22:24.084766 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9507 23:22:24.087990 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9508 23:22:24.094505 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9509 23:22:24.098771 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9510 23:22:24.100943 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9511 23:22:24.108524 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9512 23:22:24.110989 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9513 23:22:24.117739 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9514 23:22:24.120824 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9515 23:22:24.127309 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9516 23:22:24.131322 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9517 23:22:24.134310 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9518 23:22:24.141006 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9519 23:22:24.143785 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9520 23:22:24.150574 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9521 23:22:24.153431 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9522 23:22:24.160305 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9523 23:22:24.163429 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9524 23:22:24.167832 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9525 23:22:24.173578 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9526 23:22:24.177139 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9527 23:22:24.183328 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9528 23:22:24.187321 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9529 23:22:24.190418 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9530 23:22:24.196859 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9531 23:22:24.199805 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9532 23:22:24.207926 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9533 23:22:24.210078 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9534 23:22:24.212967 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9535 23:22:24.219849 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9536 23:22:24.223085 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9537 23:22:24.229716 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9538 23:22:24.232957 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9539 23:22:24.240906 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9540 23:22:24.242950 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9541 23:22:24.249597 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9542 23:22:24.252537 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9543 23:22:24.256333 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9544 23:22:24.262631 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9545 23:22:24.266251 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9546 23:22:24.273346 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9547 23:22:24.275917 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9548 23:22:24.282449 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9549 23:22:24.286237 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9550 23:22:24.289187 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9551 23:22:24.297526 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9552 23:22:24.299699 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9553 23:22:24.306379 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9554 23:22:24.309335 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9555 23:22:24.315389 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9556 23:22:24.319241 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9557 23:22:24.325905 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9558 23:22:24.328678 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9559 23:22:24.332522 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9560 23:22:24.339334 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9561 23:22:24.342086 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9562 23:22:24.348754 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9563 23:22:24.352393 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9564 23:22:24.358807 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9565 23:22:24.361973 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9566 23:22:24.368914 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9567 23:22:24.372102 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9568 23:22:24.375018 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9569 23:22:24.381882 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9570 23:22:24.385211 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9571 23:22:24.391408 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9572 23:22:24.394437 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9573 23:22:24.402090 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9574 23:22:24.404881 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9575 23:22:24.408346 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9576 23:22:24.414635 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9577 23:22:24.418239 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9578 23:22:24.424692 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9579 23:22:24.428504 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9580 23:22:24.435293 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9581 23:22:24.437915 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9582 23:22:24.444552 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9583 23:22:24.448131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9584 23:22:24.450964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9585 23:22:24.457252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9586 23:22:24.461707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9587 23:22:24.467579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9588 23:22:24.470860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9589 23:22:24.477684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9590 23:22:24.480494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9591 23:22:24.487043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9592 23:22:24.490577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9593 23:22:24.497026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9594 23:22:24.500439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9595 23:22:24.506768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9596 23:22:24.510271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9597 23:22:24.517445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9598 23:22:24.520229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9599 23:22:24.527347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9600 23:22:24.530385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9601 23:22:24.537695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9602 23:22:24.540232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9603 23:22:24.547028 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9604 23:22:24.550402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9605 23:22:24.556853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9606 23:22:24.560169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9607 23:22:24.566259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9608 23:22:24.569685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9609 23:22:24.576239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9610 23:22:24.579754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9611 23:22:24.586254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9612 23:22:24.589385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9613 23:22:24.596530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9614 23:22:24.599861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9615 23:22:24.605751 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9616 23:22:24.606388 INFO: [APUAPC] vio 0
9617 23:22:24.613096 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9618 23:22:24.616115 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9619 23:22:24.619062 INFO: [APUAPC] D0_APC_0: 0x400510
9620 23:22:24.622767 INFO: [APUAPC] D0_APC_1: 0x0
9621 23:22:24.625354 INFO: [APUAPC] D0_APC_2: 0x1540
9622 23:22:24.629594 INFO: [APUAPC] D0_APC_3: 0x0
9623 23:22:24.632640 INFO: [APUAPC] D1_APC_0: 0xffffffff
9624 23:22:24.636537 INFO: [APUAPC] D1_APC_1: 0xffffffff
9625 23:22:24.639409 INFO: [APUAPC] D1_APC_2: 0x3fffff
9626 23:22:24.642587 INFO: [APUAPC] D1_APC_3: 0x0
9627 23:22:24.646462 INFO: [APUAPC] D2_APC_0: 0xffffffff
9628 23:22:24.649205 INFO: [APUAPC] D2_APC_1: 0xffffffff
9629 23:22:24.652803 INFO: [APUAPC] D2_APC_2: 0x3fffff
9630 23:22:24.655513 INFO: [APUAPC] D2_APC_3: 0x0
9631 23:22:24.658938 INFO: [APUAPC] D3_APC_0: 0xffffffff
9632 23:22:24.663317 INFO: [APUAPC] D3_APC_1: 0xffffffff
9633 23:22:24.665509 INFO: [APUAPC] D3_APC_2: 0x3fffff
9634 23:22:24.669312 INFO: [APUAPC] D3_APC_3: 0x0
9635 23:22:24.672139 INFO: [APUAPC] D4_APC_0: 0xffffffff
9636 23:22:24.675683 INFO: [APUAPC] D4_APC_1: 0xffffffff
9637 23:22:24.679568 INFO: [APUAPC] D4_APC_2: 0x3fffff
9638 23:22:24.682152 INFO: [APUAPC] D4_APC_3: 0x0
9639 23:22:24.685794 INFO: [APUAPC] D5_APC_0: 0xffffffff
9640 23:22:24.689126 INFO: [APUAPC] D5_APC_1: 0xffffffff
9641 23:22:24.692204 INFO: [APUAPC] D5_APC_2: 0x3fffff
9642 23:22:24.692812 INFO: [APUAPC] D5_APC_3: 0x0
9643 23:22:24.695044 INFO: [APUAPC] D6_APC_0: 0xffffffff
9644 23:22:24.701926 INFO: [APUAPC] D6_APC_1: 0xffffffff
9645 23:22:24.705503 INFO: [APUAPC] D6_APC_2: 0x3fffff
9646 23:22:24.706073 INFO: [APUAPC] D6_APC_3: 0x0
9647 23:22:24.708529 INFO: [APUAPC] D7_APC_0: 0xffffffff
9648 23:22:24.712746 INFO: [APUAPC] D7_APC_1: 0xffffffff
9649 23:22:24.715806 INFO: [APUAPC] D7_APC_2: 0x3fffff
9650 23:22:24.718625 INFO: [APUAPC] D7_APC_3: 0x0
9651 23:22:24.721483 INFO: [APUAPC] D8_APC_0: 0xffffffff
9652 23:22:24.724881 INFO: [APUAPC] D8_APC_1: 0xffffffff
9653 23:22:24.728613 INFO: [APUAPC] D8_APC_2: 0x3fffff
9654 23:22:24.731143 INFO: [APUAPC] D8_APC_3: 0x0
9655 23:22:24.735357 INFO: [APUAPC] D9_APC_0: 0xffffffff
9656 23:22:24.738924 INFO: [APUAPC] D9_APC_1: 0xffffffff
9657 23:22:24.741459 INFO: [APUAPC] D9_APC_2: 0x3fffff
9658 23:22:24.746259 INFO: [APUAPC] D9_APC_3: 0x0
9659 23:22:24.749140 INFO: [APUAPC] D10_APC_0: 0xffffffff
9660 23:22:24.751979 INFO: [APUAPC] D10_APC_1: 0xffffffff
9661 23:22:24.755448 INFO: [APUAPC] D10_APC_2: 0x3fffff
9662 23:22:24.758364 INFO: [APUAPC] D10_APC_3: 0x0
9663 23:22:24.761529 INFO: [APUAPC] D11_APC_0: 0xffffffff
9664 23:22:24.764626 INFO: [APUAPC] D11_APC_1: 0xffffffff
9665 23:22:24.767921 INFO: [APUAPC] D11_APC_2: 0x3fffff
9666 23:22:24.771454 INFO: [APUAPC] D11_APC_3: 0x0
9667 23:22:24.774842 INFO: [APUAPC] D12_APC_0: 0xffffffff
9668 23:22:24.778396 INFO: [APUAPC] D12_APC_1: 0xffffffff
9669 23:22:24.781624 INFO: [APUAPC] D12_APC_2: 0x3fffff
9670 23:22:24.784589 INFO: [APUAPC] D12_APC_3: 0x0
9671 23:22:24.788225 INFO: [APUAPC] D13_APC_0: 0xffffffff
9672 23:22:24.792029 INFO: [APUAPC] D13_APC_1: 0xffffffff
9673 23:22:24.797467 INFO: [APUAPC] D13_APC_2: 0x3fffff
9674 23:22:24.798029 INFO: [APUAPC] D13_APC_3: 0x0
9675 23:22:24.802396 INFO: [APUAPC] D14_APC_0: 0xffffffff
9676 23:22:24.807814 INFO: [APUAPC] D14_APC_1: 0xffffffff
9677 23:22:24.811081 INFO: [APUAPC] D14_APC_2: 0x3fffff
9678 23:22:24.811899 INFO: [APUAPC] D14_APC_3: 0x0
9679 23:22:24.817428 INFO: [APUAPC] D15_APC_0: 0xffffffff
9680 23:22:24.821736 INFO: [APUAPC] D15_APC_1: 0xffffffff
9681 23:22:24.824319 INFO: [APUAPC] D15_APC_2: 0x3fffff
9682 23:22:24.824938 INFO: [APUAPC] D15_APC_3: 0x0
9683 23:22:24.827939 INFO: [APUAPC] APC_CON: 0x4
9684 23:22:24.830329 INFO: [NOCDAPC] D0_APC_0: 0x0
9685 23:22:24.833885 INFO: [NOCDAPC] D0_APC_1: 0x0
9686 23:22:24.838373 INFO: [NOCDAPC] D1_APC_0: 0x0
9687 23:22:24.840592 INFO: [NOCDAPC] D1_APC_1: 0xfff
9688 23:22:24.844049 INFO: [NOCDAPC] D2_APC_0: 0x0
9689 23:22:24.847121 INFO: [NOCDAPC] D2_APC_1: 0xfff
9690 23:22:24.850565 INFO: [NOCDAPC] D3_APC_0: 0x0
9691 23:22:24.853606 INFO: [NOCDAPC] D3_APC_1: 0xfff
9692 23:22:24.854192 INFO: [NOCDAPC] D4_APC_0: 0x0
9693 23:22:24.856906 INFO: [NOCDAPC] D4_APC_1: 0xfff
9694 23:22:24.860412 INFO: [NOCDAPC] D5_APC_0: 0x0
9695 23:22:24.863981 INFO: [NOCDAPC] D5_APC_1: 0xfff
9696 23:22:24.867081 INFO: [NOCDAPC] D6_APC_0: 0x0
9697 23:22:24.870319 INFO: [NOCDAPC] D6_APC_1: 0xfff
9698 23:22:24.873328 INFO: [NOCDAPC] D7_APC_0: 0x0
9699 23:22:24.876750 INFO: [NOCDAPC] D7_APC_1: 0xfff
9700 23:22:24.880113 INFO: [NOCDAPC] D8_APC_0: 0x0
9701 23:22:24.884069 INFO: [NOCDAPC] D8_APC_1: 0xfff
9702 23:22:24.886897 INFO: [NOCDAPC] D9_APC_0: 0x0
9703 23:22:24.889807 INFO: [NOCDAPC] D9_APC_1: 0xfff
9704 23:22:24.890279 INFO: [NOCDAPC] D10_APC_0: 0x0
9705 23:22:24.893455 INFO: [NOCDAPC] D10_APC_1: 0xfff
9706 23:22:24.896351 INFO: [NOCDAPC] D11_APC_0: 0x0
9707 23:22:24.900962 INFO: [NOCDAPC] D11_APC_1: 0xfff
9708 23:22:24.904398 INFO: [NOCDAPC] D12_APC_0: 0x0
9709 23:22:24.907288 INFO: [NOCDAPC] D12_APC_1: 0xfff
9710 23:22:24.909898 INFO: [NOCDAPC] D13_APC_0: 0x0
9711 23:22:24.913215 INFO: [NOCDAPC] D13_APC_1: 0xfff
9712 23:22:24.916238 INFO: [NOCDAPC] D14_APC_0: 0x0
9713 23:22:24.920603 INFO: [NOCDAPC] D14_APC_1: 0xfff
9714 23:22:24.923448 INFO: [NOCDAPC] D15_APC_0: 0x0
9715 23:22:24.926268 INFO: [NOCDAPC] D15_APC_1: 0xfff
9716 23:22:24.929914 INFO: [NOCDAPC] APC_CON: 0x4
9717 23:22:24.933638 INFO: [APUAPC] set_apusys_apc done
9718 23:22:24.936269 INFO: [DEVAPC] devapc_init done
9719 23:22:24.939945 INFO: GICv3 without legacy support detected.
9720 23:22:24.943431 INFO: ARM GICv3 driver initialized in EL3
9721 23:22:24.947019 INFO: Maximum SPI INTID supported: 639
9722 23:22:24.950010 INFO: BL31: Initializing runtime services
9723 23:22:24.956531 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9724 23:22:24.959351 INFO: SPM: enable CPC mode
9725 23:22:24.966094 INFO: mcdi ready for mcusys-off-idle and system suspend
9726 23:22:24.969228 INFO: BL31: Preparing for EL3 exit to normal world
9727 23:22:24.973257 INFO: Entry point address = 0x80000000
9728 23:22:24.976218 INFO: SPSR = 0x8
9729 23:22:24.980779
9730 23:22:24.981340
9731 23:22:24.981713
9732 23:22:24.984068 Starting depthcharge on Spherion...
9733 23:22:24.984538
9734 23:22:24.984952 Wipe memory regions:
9735 23:22:24.985302
9736 23:22:24.988148 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9737 23:22:24.988692 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9738 23:22:24.989181 Setting prompt string to ['asurada:']
9739 23:22:24.989611 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9740 23:22:24.990333 [0x00000040000000, 0x00000054600000)
9741 23:22:25.108956
9742 23:22:25.109369 [0x00000054660000, 0x00000080000000)
9743 23:22:25.369690
9744 23:22:25.369827 [0x000000821a7280, 0x000000ffe64000)
9745 23:22:26.114729
9746 23:22:26.115051 [0x00000100000000, 0x00000140000000)
9747 23:22:26.495833
9748 23:22:26.499650 Initializing XHCI USB controller at 0x11200000.
9749 23:22:27.536516
9750 23:22:27.540124 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9751 23:22:27.540686
9752 23:22:27.541102
9753 23:22:27.541449
9754 23:22:27.542270 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9756 23:22:27.643652 asurada: tftpboot 192.168.201.1 13248448/tftp-deploy-hxgkz2eb/kernel/image.itb 13248448/tftp-deploy-hxgkz2eb/kernel/cmdline
9757 23:22:27.644308 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9758 23:22:27.644796 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9759 23:22:27.649504 tftpboot 192.168.201.1 13248448/tftp-deploy-hxgkz2eb/kernel/image.itp-deploy-hxgkz2eb/kernel/cmdline
9760 23:22:27.649978
9761 23:22:27.650347 Waiting for link
9762 23:22:27.810888
9763 23:22:27.811412 R8152: Initializing
9764 23:22:27.811756
9765 23:22:27.813479 Version 9 (ocp_data = 6010)
9766 23:22:27.814053
9767 23:22:27.817448 R8152: Done initializing
9768 23:22:27.817980
9769 23:22:27.818320 Adding net device
9770 23:22:29.825183
9771 23:22:29.825747 done.
9772 23:22:29.826114
9773 23:22:29.826456 MAC: 00:e0:4c:68:03:bd
9774 23:22:29.826787
9775 23:22:29.827750 Sending DHCP discover... done.
9776 23:22:29.828212
9777 23:22:39.530606 Waiting for reply... R8152: Bulk read error 0xffffffbf
9778 23:22:39.531186
9779 23:22:39.533662 Receive failed.
9780 23:22:39.534127
9781 23:22:39.534497 done.
9782 23:22:39.534839
9783 23:22:39.538202 Sending DHCP request... done.
9784 23:22:39.538673
9785 23:22:39.546018 Waiting for reply... done.
9786 23:22:39.546591
9787 23:22:39.546963 My ip is 192.168.201.16
9788 23:22:39.547309
9789 23:22:39.548829 The DHCP server ip is 192.168.201.1
9790 23:22:39.549298
9791 23:22:39.555622 TFTP server IP predefined by user: 192.168.201.1
9792 23:22:39.556197
9793 23:22:39.562111 Bootfile predefined by user: 13248448/tftp-deploy-hxgkz2eb/kernel/image.itb
9794 23:22:39.562684
9795 23:22:39.565090 Sending tftp read request... done.
9796 23:22:39.565693
9797 23:22:39.573163 Waiting for the transfer...
9798 23:22:39.573729
9799 23:22:39.961961 00000000 ################################################################
9800 23:22:39.962471
9801 23:22:40.259411 00080000 ################################################################
9802 23:22:40.259555
9803 23:22:40.557383 00100000 ################################################################
9804 23:22:40.557531
9805 23:22:40.860201 00180000 ################################################################
9806 23:22:40.860341
9807 23:22:41.155656 00200000 ################################################################
9808 23:22:41.155801
9809 23:22:41.438247 00280000 ################################################################
9810 23:22:41.438387
9811 23:22:41.723858 00300000 ################################################################
9812 23:22:41.723996
9813 23:22:42.028289 00380000 ################################################################
9814 23:22:42.028430
9815 23:22:42.324518 00400000 ################################################################
9816 23:22:42.324661
9817 23:22:42.615342 00480000 ################################################################
9818 23:22:42.615487
9819 23:22:42.913680 00500000 ################################################################
9820 23:22:42.913821
9821 23:22:43.215219 00580000 ################################################################
9822 23:22:43.215360
9823 23:22:43.506121 00600000 ################################################################
9824 23:22:43.506266
9825 23:22:43.799580 00680000 ################################################################
9826 23:22:43.799720
9827 23:22:44.090690 00700000 ################################################################
9828 23:22:44.090830
9829 23:22:44.375621 00780000 ################################################################
9830 23:22:44.375786
9831 23:22:44.673182 00800000 ################################################################
9832 23:22:44.673328
9833 23:22:44.964186 00880000 ################################################################
9834 23:22:44.964326
9835 23:22:45.266100 00900000 ################################################################
9836 23:22:45.266245
9837 23:22:45.559369 00980000 ################################################################
9838 23:22:45.559535
9839 23:22:45.860665 00a00000 ################################################################
9840 23:22:45.860819
9841 23:22:46.163868 00a80000 ################################################################
9842 23:22:46.164010
9843 23:22:46.465477 00b00000 ################################################################
9844 23:22:46.465617
9845 23:22:46.738401 00b80000 ################################################################
9846 23:22:46.738545
9847 23:22:46.989272 00c00000 ################################################################
9848 23:22:46.989403
9849 23:22:47.264762 00c80000 ################################################################
9850 23:22:47.264901
9851 23:22:47.559927 00d00000 ################################################################
9852 23:22:47.560089
9853 23:22:47.857438 00d80000 ################################################################
9854 23:22:47.857580
9855 23:22:48.157008 00e00000 ################################################################
9856 23:22:48.157143
9857 23:22:48.453084 00e80000 ################################################################
9858 23:22:48.453220
9859 23:22:48.751802 00f00000 ################################################################
9860 23:22:48.751964
9861 23:22:49.050562 00f80000 ################################################################
9862 23:22:49.050699
9863 23:22:49.347367 01000000 ################################################################
9864 23:22:49.347537
9865 23:22:49.689393 01080000 ################################################################
9866 23:22:49.689934
9867 23:22:50.093730 01100000 ################################################################
9868 23:22:50.094253
9869 23:22:50.483305 01180000 ################################################################
9870 23:22:50.483920
9871 23:22:50.871359 01200000 ################################################################
9872 23:22:50.871494
9873 23:22:51.147937 01280000 ################################################################
9874 23:22:51.148096
9875 23:22:51.429953 01300000 ################################################################
9876 23:22:51.430100
9877 23:22:51.712136 01380000 ################################################################
9878 23:22:51.712283
9879 23:22:52.000354 01400000 ################################################################
9880 23:22:52.000504
9881 23:22:52.292854 01480000 ################################################################
9882 23:22:52.293002
9883 23:22:52.580335 01500000 ################################################################
9884 23:22:52.580474
9885 23:22:52.831396 01580000 ################################################################
9886 23:22:52.831547
9887 23:22:53.103637 01600000 ################################################################
9888 23:22:53.103787
9889 23:22:53.358620 01680000 ################################################################
9890 23:22:53.358773
9891 23:22:53.642681 01700000 ################################################################
9892 23:22:53.642832
9893 23:22:53.938143 01780000 ################################################################
9894 23:22:53.938288
9895 23:22:54.230445 01800000 ################################################################
9896 23:22:54.230598
9897 23:22:54.504961 01880000 ################################################################
9898 23:22:54.505127
9899 23:22:54.757002 01900000 ################################################################
9900 23:22:54.757149
9901 23:22:55.033418 01980000 ################################################################
9902 23:22:55.033567
9903 23:22:55.332499 01a00000 ################################################################
9904 23:22:55.332646
9905 23:22:55.584931 01a80000 ################################################################
9906 23:22:55.585076
9907 23:22:55.847103 01b00000 ################################################################
9908 23:22:55.847288
9909 23:22:56.125057 01b80000 ################################################################
9910 23:22:56.125207
9911 23:22:56.424264 01c00000 ################################################################
9912 23:22:56.424407
9913 23:22:56.708456 01c80000 ################################################################
9914 23:22:56.708606
9915 23:22:57.005051 01d00000 ################################################################
9916 23:22:57.005224
9917 23:22:57.292492 01d80000 ################################################################
9918 23:22:57.292656
9919 23:22:57.582778 01e00000 ################################################################
9920 23:22:57.582930
9921 23:22:57.870383 01e80000 ################################################################
9922 23:22:57.870517
9923 23:22:58.168360 01f00000 ################################################################
9924 23:22:58.168527
9925 23:22:58.469447 01f80000 ################################################################
9926 23:22:58.469619
9927 23:22:58.763437 02000000 ################################################################
9928 23:22:58.763607
9929 23:22:59.060674 02080000 ################################################################
9930 23:22:59.060831
9931 23:22:59.357298 02100000 ################################################################
9932 23:22:59.357441
9933 23:22:59.659616 02180000 ################################################################
9934 23:22:59.659807
9935 23:22:59.952017 02200000 ################################################################
9936 23:22:59.952197
9937 23:23:00.252391 02280000 ################################################################
9938 23:23:00.252564
9939 23:23:00.554131 02300000 ################################################################
9940 23:23:00.554293
9941 23:23:00.852582 02380000 ################################################################
9942 23:23:00.852826
9943 23:23:01.138346 02400000 ################################################################
9944 23:23:01.138498
9945 23:23:01.419448 02480000 ################################################################
9946 23:23:01.419606
9947 23:23:01.710747 02500000 ################################################################
9948 23:23:01.710890
9949 23:23:02.011845 02580000 ################################################################
9950 23:23:02.012019
9951 23:23:02.321460 02600000 ################################################################
9952 23:23:02.321660
9953 23:23:02.675663 02680000 ################################################################
9954 23:23:02.675849
9955 23:23:03.025784 02700000 ################################################################
9956 23:23:03.025982
9957 23:23:03.374528 02780000 ################################################################
9958 23:23:03.374703
9959 23:23:03.665818 02800000 ################################################################
9960 23:23:03.665993
9961 23:23:03.960131 02880000 ################################################################
9962 23:23:03.960266
9963 23:23:04.258350 02900000 ################################################################
9964 23:23:04.258505
9965 23:23:04.548855 02980000 ################################################################
9966 23:23:04.549010
9967 23:23:04.830540 02a00000 ################################################################
9968 23:23:04.830686
9969 23:23:05.105684 02a80000 ################################################################
9970 23:23:05.105900
9971 23:23:05.382285 02b00000 ################################################################
9972 23:23:05.382427
9973 23:23:05.677550 02b80000 ################################################################
9974 23:23:05.677697
9975 23:23:05.980180 02c00000 ################################################################
9976 23:23:05.980322
9977 23:23:06.284048 02c80000 ################################################################
9978 23:23:06.284186
9979 23:23:06.584826 02d00000 ################################################################
9980 23:23:06.584975
9981 23:23:06.873952 02d80000 ################################################################
9982 23:23:06.874095
9983 23:23:07.169092 02e00000 ################################################################
9984 23:23:07.169231
9985 23:23:07.450731 02e80000 ################################################################
9986 23:23:07.450921
9987 23:23:07.726668 02f00000 ################################################################
9988 23:23:07.726807
9989 23:23:08.022430 02f80000 ################################################################
9990 23:23:08.022595
9991 23:23:08.319262 03000000 ################################################################
9992 23:23:08.319432
9993 23:23:08.614980 03080000 ################################################################
9994 23:23:08.615151
9995 23:23:08.916098 03100000 ################################################################
9996 23:23:08.916268
9997 23:23:09.219848 03180000 ################################################################
9998 23:23:09.220013
9999 23:23:09.522989 03200000 ################################################################
10000 23:23:09.523131
10001 23:23:09.821805 03280000 ################################################################
10002 23:23:09.821968
10003 23:23:10.103479 03300000 ################################################################
10004 23:23:10.103645
10005 23:23:10.224637 03380000 ########################## done.
10006 23:23:10.224760
10007 23:23:10.227891 The bootfile was 54211726 bytes long.
10008 23:23:10.227978
10009 23:23:10.231313 Sending tftp read request... done.
10010 23:23:10.231395
10011 23:23:10.231460 Waiting for the transfer...
10012 23:23:10.231521
10013 23:23:10.235112 00000000 # done.
10014 23:23:10.235195
10015 23:23:10.241234 Command line loaded dynamically from TFTP file: 13248448/tftp-deploy-hxgkz2eb/kernel/cmdline
10016 23:23:10.241318
10017 23:23:10.254788 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10018 23:23:10.254899
10019 23:23:10.258010 Loading FIT.
10020 23:23:10.258091
10021 23:23:10.261821 Image ramdisk-1 has 41255191 bytes.
10022 23:23:10.261904
10023 23:23:10.261969 Image fdt-1 has 47230 bytes.
10024 23:23:10.262031
10025 23:23:10.264837 Image kernel-1 has 12907270 bytes.
10026 23:23:10.264945
10027 23:23:10.274672 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10028 23:23:10.274755
10029 23:23:10.291411 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10030 23:23:10.291499
10031 23:23:10.297291 Choosing best match conf-1 for compat google,spherion-rev3.
10032 23:23:10.301387
10033 23:23:10.306143 Connected to device vid:did:rid of 1ae0:0028:00
10034 23:23:10.313514
10035 23:23:10.316598 tpm_get_response: command 0x17b, return code 0x0
10036 23:23:10.316680
10037 23:23:10.320002 ec_init: CrosEC protocol v3 supported (256, 248)
10038 23:23:10.324424
10039 23:23:10.327728 tpm_cleanup: add release locality here.
10040 23:23:10.327810
10041 23:23:10.327875 Shutting down all USB controllers.
10042 23:23:10.330015
10043 23:23:10.330095 Removing current net device
10044 23:23:10.330161
10045 23:23:10.336725 Exiting depthcharge with code 4 at timestamp: 73565316
10046 23:23:10.336823
10047 23:23:10.340657 LZMA decompressing kernel-1 to 0x821a6718
10048 23:23:10.340775
10049 23:23:10.343436 LZMA decompressing kernel-1 to 0x40000000
10050 23:23:11.935742
10051 23:23:11.935912 jumping to kernel
10052 23:23:11.936426 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10053 23:23:11.936528 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10054 23:23:11.936606 Setting prompt string to ['Linux version [0-9]']
10055 23:23:11.936675 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10056 23:23:11.936783 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10057 23:23:11.986390
10058 23:23:11.989522 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10059 23:23:11.993344 start: 2.2.5.1 login-action (timeout 00:03:39) [common]
10060 23:23:11.993437 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10061 23:23:11.993508 Setting prompt string to []
10062 23:23:11.993590 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10063 23:23:11.993667 Using line separator: #'\n'#
10064 23:23:11.993726 No login prompt set.
10065 23:23:11.993784 Parsing kernel messages
10066 23:23:11.993838 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10067 23:23:11.993937 [login-action] Waiting for messages, (timeout 00:03:39)
10068 23:23:11.994000 Waiting using forced prompt support (timeout 00:01:50)
10069 23:23:12.012378 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10070 23:23:12.015790 [ 0.000000] random: crng init done
10071 23:23:12.022900 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10072 23:23:12.026071 [ 0.000000] efi: UEFI not found.
10073 23:23:12.033398 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10074 23:23:12.039177 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10075 23:23:12.049477 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10076 23:23:12.059055 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10077 23:23:12.065421 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10078 23:23:12.072401 [ 0.000000] printk: bootconsole [mtk8250] enabled
10079 23:23:12.079140 [ 0.000000] NUMA: No NUMA configuration found
10080 23:23:12.085768 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10081 23:23:12.088575 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10082 23:23:12.093099 [ 0.000000] Zone ranges:
10083 23:23:12.098780 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10084 23:23:12.101604 [ 0.000000] DMA32 empty
10085 23:23:12.108482 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10086 23:23:12.111570 [ 0.000000] Movable zone start for each node
10087 23:23:12.115113 [ 0.000000] Early memory node ranges
10088 23:23:12.123063 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10089 23:23:12.128430 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10090 23:23:12.135255 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10091 23:23:12.141676 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10092 23:23:12.147925 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10093 23:23:12.154458 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10094 23:23:12.184771 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10095 23:23:12.190918 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10096 23:23:12.197813 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10097 23:23:12.201305 [ 0.000000] psci: probing for conduit method from DT.
10098 23:23:12.207485 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10099 23:23:12.210978 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10100 23:23:12.217830 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10101 23:23:12.220974 [ 0.000000] psci: SMC Calling Convention v1.2
10102 23:23:12.228238 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10103 23:23:12.231269 [ 0.000000] Detected VIPT I-cache on CPU0
10104 23:23:12.238158 [ 0.000000] CPU features: detected: GIC system register CPU interface
10105 23:23:12.244235 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10106 23:23:12.250636 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10107 23:23:12.257557 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10108 23:23:12.267045 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10109 23:23:12.273917 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10110 23:23:12.276389 [ 0.000000] alternatives: applying boot alternatives
10111 23:23:12.283402 [ 0.000000] Fallback order for Node 0: 0
10112 23:23:12.290126 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10113 23:23:12.293212 [ 0.000000] Policy zone: Normal
10114 23:23:12.306783 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10115 23:23:12.316279 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10116 23:23:12.327613 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10117 23:23:12.338928 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10118 23:23:12.343764 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10119 23:23:12.347022 <6>[ 0.000000] software IO TLB: area num 8.
10120 23:23:12.402753 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10121 23:23:12.482871 <6>[ 0.000000] Memory: 3809868K/4191232K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 348596K reserved, 32768K cma-reserved)
10122 23:23:12.489460 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10123 23:23:12.496141 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10124 23:23:12.499400 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10125 23:23:12.506113 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10126 23:23:12.512637 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10127 23:23:12.515716 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10128 23:23:12.525868 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10129 23:23:12.533200 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10130 23:23:12.539113 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10131 23:23:12.545874 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10132 23:23:12.549047 <6>[ 0.000000] GICv3: 608 SPIs implemented
10133 23:23:12.553381 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10134 23:23:12.559793 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10135 23:23:12.562849 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10136 23:23:12.568548 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10137 23:23:12.582588 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10138 23:23:12.595510 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10139 23:23:12.601491 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10140 23:23:12.609585 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10141 23:23:12.622908 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10142 23:23:12.630253 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10143 23:23:12.635690 <6>[ 0.009177] Console: colour dummy device 80x25
10144 23:23:12.646092 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10145 23:23:12.652655 <6>[ 0.024407] pid_max: default: 32768 minimum: 301
10146 23:23:12.655797 <6>[ 0.029310] LSM: Security Framework initializing
10147 23:23:12.662197 <6>[ 0.034224] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10148 23:23:12.672349 <6>[ 0.041831] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10149 23:23:12.681777 <6>[ 0.051062] cblist_init_generic: Setting adjustable number of callback queues.
10150 23:23:12.685036 <6>[ 0.058504] cblist_init_generic: Setting shift to 3 and lim to 1.
10151 23:23:12.695153 <6>[ 0.064842] cblist_init_generic: Setting adjustable number of callback queues.
10152 23:23:12.701804 <6>[ 0.072269] cblist_init_generic: Setting shift to 3 and lim to 1.
10153 23:23:12.705433 <6>[ 0.078709] rcu: Hierarchical SRCU implementation.
10154 23:23:12.712109 <6>[ 0.083755] rcu: Max phase no-delay instances is 1000.
10155 23:23:12.718212 <6>[ 0.090773] EFI services will not be available.
10156 23:23:12.721951 <6>[ 0.095731] smp: Bringing up secondary CPUs ...
10157 23:23:12.729964 <6>[ 0.100807] Detected VIPT I-cache on CPU1
10158 23:23:12.736832 <6>[ 0.100876] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10159 23:23:12.743015 <6>[ 0.100906] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10160 23:23:12.746317 <6>[ 0.101233] Detected VIPT I-cache on CPU2
10161 23:23:12.756505 <6>[ 0.101285] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10162 23:23:12.763528 <6>[ 0.101301] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10163 23:23:12.766616 <6>[ 0.101557] Detected VIPT I-cache on CPU3
10164 23:23:12.774007 <6>[ 0.101605] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10165 23:23:12.779742 <6>[ 0.101619] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10166 23:23:12.782498 <6>[ 0.101923] CPU features: detected: Spectre-v4
10167 23:23:12.789445 <6>[ 0.101929] CPU features: detected: Spectre-BHB
10168 23:23:12.792948 <6>[ 0.101935] Detected PIPT I-cache on CPU4
10169 23:23:12.799727 <6>[ 0.101994] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10170 23:23:12.805679 <6>[ 0.102011] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10171 23:23:12.812977 <6>[ 0.102297] Detected PIPT I-cache on CPU5
10172 23:23:12.819195 <6>[ 0.102359] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10173 23:23:12.826067 <6>[ 0.102375] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10174 23:23:12.828688 <6>[ 0.102655] Detected PIPT I-cache on CPU6
10175 23:23:12.835250 <6>[ 0.102717] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10176 23:23:12.845788 <6>[ 0.102733] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10177 23:23:12.848905 <6>[ 0.103032] Detected PIPT I-cache on CPU7
10178 23:23:12.855493 <6>[ 0.103096] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10179 23:23:12.861901 <6>[ 0.103112] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10180 23:23:12.865088 <6>[ 0.103158] smp: Brought up 1 node, 8 CPUs
10181 23:23:12.872109 <6>[ 0.244544] SMP: Total of 8 processors activated.
10182 23:23:12.874972 <6>[ 0.249466] CPU features: detected: 32-bit EL0 Support
10183 23:23:12.885492 <6>[ 0.254861] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10184 23:23:12.892174 <6>[ 0.263716] CPU features: detected: Common not Private translations
10185 23:23:12.898306 <6>[ 0.270193] CPU features: detected: CRC32 instructions
10186 23:23:12.904662 <6>[ 0.275544] CPU features: detected: RCpc load-acquire (LDAPR)
10187 23:23:12.907792 <6>[ 0.281504] CPU features: detected: LSE atomic instructions
10188 23:23:12.914922 <6>[ 0.287286] CPU features: detected: Privileged Access Never
10189 23:23:12.921403 <6>[ 0.293066] CPU features: detected: RAS Extension Support
10190 23:23:12.928197 <6>[ 0.298674] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10191 23:23:12.931429 <6>[ 0.305896] CPU: All CPU(s) started at EL2
10192 23:23:12.938221 <6>[ 0.310212] alternatives: applying system-wide alternatives
10193 23:23:12.947380 <6>[ 0.320230] devtmpfs: initialized
10194 23:23:12.961597 <6>[ 0.328364] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10195 23:23:12.968904 <6>[ 0.338323] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10196 23:23:12.974726 <6>[ 0.346581] pinctrl core: initialized pinctrl subsystem
10197 23:23:12.978042 <6>[ 0.353251] DMI not present or invalid.
10198 23:23:12.985032 <6>[ 0.357654] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10199 23:23:12.995040 <6>[ 0.364532] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10200 23:23:13.001983 <6>[ 0.371981] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10201 23:23:13.011312 <6>[ 0.380072] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10202 23:23:13.015147 <6>[ 0.388224] audit: initializing netlink subsys (disabled)
10203 23:23:13.024639 <5>[ 0.393920] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10204 23:23:13.031078 <6>[ 0.394617] thermal_sys: Registered thermal governor 'step_wise'
10205 23:23:13.037508 <6>[ 0.401884] thermal_sys: Registered thermal governor 'power_allocator'
10206 23:23:13.040909 <6>[ 0.408138] cpuidle: using governor menu
10207 23:23:13.048042 <6>[ 0.419098] NET: Registered PF_QIPCRTR protocol family
10208 23:23:13.054050 <6>[ 0.424588] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10209 23:23:13.060631 <6>[ 0.431686] ASID allocator initialised with 32768 entries
10210 23:23:13.064398 <6>[ 0.438235] Serial: AMBA PL011 UART driver
10211 23:23:13.073891 <4>[ 0.447028] Trying to register duplicate clock ID: 134
10212 23:23:13.128375 <6>[ 0.504778] KASLR enabled
10213 23:23:13.142869 <6>[ 0.512496] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10214 23:23:13.149091 <6>[ 0.519508] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10215 23:23:13.155805 <6>[ 0.525994] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10216 23:23:13.162189 <6>[ 0.533000] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10217 23:23:13.168827 <6>[ 0.539484] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10218 23:23:13.175194 <6>[ 0.546492] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10219 23:23:13.182322 <6>[ 0.552979] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10220 23:23:13.189272 <6>[ 0.559978] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10221 23:23:13.191678 <6>[ 0.567492] ACPI: Interpreter disabled.
10222 23:23:13.200866 <6>[ 0.573958] iommu: Default domain type: Translated
10223 23:23:13.207200 <6>[ 0.579067] iommu: DMA domain TLB invalidation policy: strict mode
10224 23:23:13.211015 <5>[ 0.585724] SCSI subsystem initialized
10225 23:23:13.217897 <6>[ 0.589886] usbcore: registered new interface driver usbfs
10226 23:23:13.225926 <6>[ 0.595617] usbcore: registered new interface driver hub
10227 23:23:13.227276 <6>[ 0.601170] usbcore: registered new device driver usb
10228 23:23:13.234070 <6>[ 0.607262] pps_core: LinuxPPS API ver. 1 registered
10229 23:23:13.243890 <6>[ 0.612456] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10230 23:23:13.247954 <6>[ 0.621799] PTP clock support registered
10231 23:23:13.251399 <6>[ 0.626040] EDAC MC: Ver: 3.0.0
10232 23:23:13.258611 <6>[ 0.631177] FPGA manager framework
10233 23:23:13.261284 <6>[ 0.634857] Advanced Linux Sound Architecture Driver Initialized.
10234 23:23:13.264958 <6>[ 0.641631] vgaarb: loaded
10235 23:23:13.271398 <6>[ 0.644793] clocksource: Switched to clocksource arch_sys_counter
10236 23:23:13.278551 <5>[ 0.651237] VFS: Disk quotas dquot_6.6.0
10237 23:23:13.284997 <6>[ 0.655422] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10238 23:23:13.287967 <6>[ 0.662612] pnp: PnP ACPI: disabled
10239 23:23:13.296079 <6>[ 0.669232] NET: Registered PF_INET protocol family
10240 23:23:13.302243 <6>[ 0.674629] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10241 23:23:13.315694 <6>[ 0.684648] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10242 23:23:13.324600 <6>[ 0.693428] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10243 23:23:13.331589 <6>[ 0.701395] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10244 23:23:13.337960 <6>[ 0.709800] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10245 23:23:13.348397 <6>[ 0.718453] TCP: Hash tables configured (established 32768 bind 32768)
10246 23:23:13.355160 <6>[ 0.725310] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10247 23:23:13.361827 <6>[ 0.732328] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10248 23:23:13.368664 <6>[ 0.739848] NET: Registered PF_UNIX/PF_LOCAL protocol family
10249 23:23:13.375084 <6>[ 0.745996] RPC: Registered named UNIX socket transport module.
10250 23:23:13.378680 <6>[ 0.752154] RPC: Registered udp transport module.
10251 23:23:13.385309 <6>[ 0.757087] RPC: Registered tcp transport module.
10252 23:23:13.391318 <6>[ 0.762018] RPC: Registered tcp NFSv4.1 backchannel transport module.
10253 23:23:13.395468 <6>[ 0.768685] PCI: CLS 0 bytes, default 64
10254 23:23:13.397978 <6>[ 0.772967] Unpacking initramfs...
10255 23:23:13.408056 <6>[ 0.776957] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10256 23:23:13.414413 <6>[ 0.785585] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10257 23:23:13.421972 <6>[ 0.794367] kvm [1]: IPA Size Limit: 40 bits
10258 23:23:13.424471 <6>[ 0.798892] kvm [1]: GICv3: no GICV resource entry
10259 23:23:13.432511 <6>[ 0.803913] kvm [1]: disabling GICv2 emulation
10260 23:23:13.437913 <6>[ 0.808601] kvm [1]: GIC system register CPU interface enabled
10261 23:23:13.440878 <6>[ 0.814750] kvm [1]: vgic interrupt IRQ18
10262 23:23:13.448173 <6>[ 0.819106] kvm [1]: VHE mode initialized successfully
10263 23:23:13.450711 <5>[ 0.825471] Initialise system trusted keyrings
10264 23:23:13.457566 <6>[ 0.830267] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10265 23:23:13.467177 <6>[ 0.840209] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10266 23:23:13.473690 <5>[ 0.846608] NFS: Registering the id_resolver key type
10267 23:23:13.477632 <5>[ 0.851906] Key type id_resolver registered
10268 23:23:13.483736 <5>[ 0.856323] Key type id_legacy registered
10269 23:23:13.489594 <6>[ 0.860601] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10270 23:23:13.496302 <6>[ 0.867524] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10271 23:23:13.503086 <6>[ 0.875254] 9p: Installing v9fs 9p2000 file system support
10272 23:23:13.540600 <5>[ 0.913762] Key type asymmetric registered
10273 23:23:13.544191 <5>[ 0.918096] Asymmetric key parser 'x509' registered
10274 23:23:13.553701 <6>[ 0.923243] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10275 23:23:13.557246 <6>[ 0.930855] io scheduler mq-deadline registered
10276 23:23:13.559980 <6>[ 0.935615] io scheduler kyber registered
10277 23:23:13.579627 <6>[ 0.953052] EINJ: ACPI disabled.
10278 23:23:13.612505 <4>[ 0.978905] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10279 23:23:13.622080 <4>[ 0.989533] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10280 23:23:13.637292 <6>[ 1.010347] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10281 23:23:13.646585 <6>[ 1.018387] printk: console [ttyS0] disabled
10282 23:23:13.673070 <6>[ 1.043021] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10283 23:23:13.679706 <6>[ 1.052493] printk: console [ttyS0] enabled
10284 23:23:13.683808 <6>[ 1.052493] printk: console [ttyS0] enabled
10285 23:23:13.689333 <6>[ 1.061386] printk: bootconsole [mtk8250] disabled
10286 23:23:13.693100 <6>[ 1.061386] printk: bootconsole [mtk8250] disabled
10287 23:23:13.700125 <6>[ 1.072680] SuperH (H)SCI(F) driver initialized
10288 23:23:13.702984 <6>[ 1.077964] msm_serial: driver initialized
10289 23:23:13.716845 <6>[ 1.086893] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10290 23:23:13.727016 <6>[ 1.095440] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10291 23:23:13.733689 <6>[ 1.103984] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10292 23:23:13.743316 <6>[ 1.112612] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10293 23:23:13.753154 <6>[ 1.121318] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10294 23:23:13.760579 <6>[ 1.130034] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10295 23:23:13.770316 <6>[ 1.138576] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10296 23:23:13.776453 <6>[ 1.147394] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10297 23:23:13.786647 <6>[ 1.155938] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10298 23:23:13.798097 <6>[ 1.171433] loop: module loaded
10299 23:23:13.804383 <6>[ 1.177374] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10300 23:23:13.826880 <4>[ 1.200291] mtk-pmic-keys: Failed to locate of_node [id: -1]
10301 23:23:13.834008 <6>[ 1.207456] megasas: 07.719.03.00-rc1
10302 23:23:13.843998 <6>[ 1.217225] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10303 23:23:13.851296 <6>[ 1.224194] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10304 23:23:13.868688 <6>[ 1.240391] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10305 23:23:13.922645 <6>[ 1.289007] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10306 23:23:15.152513 <6>[ 2.526223] Freeing initrd memory: 40284K
10307 23:23:15.164579 <6>[ 2.538152] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10308 23:23:15.175912 <6>[ 2.549349] tun: Universal TUN/TAP device driver, 1.6
10309 23:23:15.179306 <6>[ 2.555421] thunder_xcv, ver 1.0
10310 23:23:15.183222 <6>[ 2.558929] thunder_bgx, ver 1.0
10311 23:23:15.186072 <6>[ 2.562425] nicpf, ver 1.0
10312 23:23:15.196315 <6>[ 2.566490] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10313 23:23:15.200202 <6>[ 2.573969] hns3: Copyright (c) 2017 Huawei Corporation.
10314 23:23:15.206092 <6>[ 2.579557] hclge is initializing
10315 23:23:15.209664 <6>[ 2.583138] e1000: Intel(R) PRO/1000 Network Driver
10316 23:23:15.216457 <6>[ 2.588268] e1000: Copyright (c) 1999-2006 Intel Corporation.
10317 23:23:15.220192 <6>[ 2.594281] e1000e: Intel(R) PRO/1000 Network Driver
10318 23:23:15.226648 <6>[ 2.599498] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10319 23:23:15.233214 <6>[ 2.605683] igb: Intel(R) Gigabit Ethernet Network Driver
10320 23:23:15.239241 <6>[ 2.611333] igb: Copyright (c) 2007-2014 Intel Corporation.
10321 23:23:15.245969 <6>[ 2.617173] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10322 23:23:15.252683 <6>[ 2.623692] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10323 23:23:15.256417 <6>[ 2.630162] sky2: driver version 1.30
10324 23:23:15.263055 <6>[ 2.635187] VFIO - User Level meta-driver version: 0.3
10325 23:23:15.270494 <6>[ 2.643503] usbcore: registered new interface driver usb-storage
10326 23:23:15.276516 <6>[ 2.649949] usbcore: registered new device driver onboard-usb-hub
10327 23:23:15.285575 <6>[ 2.659104] mt6397-rtc mt6359-rtc: registered as rtc0
10328 23:23:15.295950 <6>[ 2.664576] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:23:15 UTC (1712186595)
10329 23:23:15.298725 <6>[ 2.674186] i2c_dev: i2c /dev entries driver
10330 23:23:15.316125 <6>[ 2.686059] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10331 23:23:15.322911 <4>[ 2.694806] cpu cpu0: supply cpu not found, using dummy regulator
10332 23:23:15.329843 <4>[ 2.701229] cpu cpu1: supply cpu not found, using dummy regulator
10333 23:23:15.335924 <4>[ 2.707630] cpu cpu2: supply cpu not found, using dummy regulator
10334 23:23:15.342517 <4>[ 2.714048] cpu cpu3: supply cpu not found, using dummy regulator
10335 23:23:15.348821 <4>[ 2.720441] cpu cpu4: supply cpu not found, using dummy regulator
10336 23:23:15.355655 <4>[ 2.726841] cpu cpu5: supply cpu not found, using dummy regulator
10337 23:23:15.362019 <4>[ 2.733257] cpu cpu6: supply cpu not found, using dummy regulator
10338 23:23:15.368621 <4>[ 2.739651] cpu cpu7: supply cpu not found, using dummy regulator
10339 23:23:15.387903 <6>[ 2.761292] cpu cpu0: EM: created perf domain
10340 23:23:15.391331 <6>[ 2.766213] cpu cpu4: EM: created perf domain
10341 23:23:15.399161 <6>[ 2.771741] sdhci: Secure Digital Host Controller Interface driver
10342 23:23:15.404998 <6>[ 2.778173] sdhci: Copyright(c) Pierre Ossman
10343 23:23:15.411695 <6>[ 2.783092] Synopsys Designware Multimedia Card Interface Driver
10344 23:23:15.418468 <6>[ 2.789692] sdhci-pltfm: SDHCI platform and OF driver helper
10345 23:23:15.421829 <6>[ 2.789856] mmc0: CQHCI version 5.10
10346 23:23:15.427632 <6>[ 2.799672] ledtrig-cpu: registered to indicate activity on CPUs
10347 23:23:15.435157 <6>[ 2.806619] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10348 23:23:15.441426 <6>[ 2.813641] usbcore: registered new interface driver usbhid
10349 23:23:15.444230 <6>[ 2.819464] usbhid: USB HID core driver
10350 23:23:15.450881 <6>[ 2.823658] spi_master spi0: will run message pump with realtime priority
10351 23:23:15.494359 <6>[ 2.861158] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10352 23:23:15.513805 <6>[ 2.876883] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10353 23:23:15.516938 <6>[ 2.891114] mmc0: Command Queue Engine enabled
10354 23:23:15.523502 <6>[ 2.895886] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10355 23:23:15.530669 <6>[ 2.902801] cros-ec-spi spi0.0: Chrome EC device registered
10356 23:23:15.533562 <6>[ 2.903307] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10357 23:23:15.546000 <6>[ 2.919447] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10358 23:23:15.553141 <6>[ 2.926924] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10359 23:23:15.559924 <6>[ 2.933145] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10360 23:23:15.570061 <6>[ 2.937733] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10361 23:23:15.576273 <6>[ 2.939178] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10362 23:23:15.579827 <6>[ 2.948923] NET: Registered PF_PACKET protocol family
10363 23:23:15.586714 <6>[ 2.959542] 9pnet: Installing 9P2000 support
10364 23:23:15.589676 <5>[ 2.964126] Key type dns_resolver registered
10365 23:23:15.597136 <6>[ 2.969215] registered taskstats version 1
10366 23:23:15.599869 <5>[ 2.973632] Loading compiled-in X.509 certificates
10367 23:23:15.629723 <4>[ 2.996113] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10368 23:23:15.639929 <4>[ 3.006887] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10369 23:23:15.645718 <3>[ 3.017481] debugfs: File 'uA_load' in directory '/' already present!
10370 23:23:15.652337 <3>[ 3.024188] debugfs: File 'min_uV' in directory '/' already present!
10371 23:23:15.659345 <3>[ 3.030798] debugfs: File 'max_uV' in directory '/' already present!
10372 23:23:15.665938 <3>[ 3.037406] debugfs: File 'constraint_flags' in directory '/' already present!
10373 23:23:15.677314 <3>[ 3.047215] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10374 23:23:15.691406 <6>[ 3.064807] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10375 23:23:15.697979 <6>[ 3.071593] xhci-mtk 11200000.usb: xHCI Host Controller
10376 23:23:15.704677 <6>[ 3.077105] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10377 23:23:15.714807 <6>[ 3.085069] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10378 23:23:15.721919 <6>[ 3.094534] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10379 23:23:15.728047 <6>[ 3.100626] xhci-mtk 11200000.usb: xHCI Host Controller
10380 23:23:15.734468 <6>[ 3.106111] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10381 23:23:15.741808 <6>[ 3.113763] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10382 23:23:15.749143 <6>[ 3.121654] hub 1-0:1.0: USB hub found
10383 23:23:15.752023 <6>[ 3.125689] hub 1-0:1.0: 1 port detected
10384 23:23:15.762309 <6>[ 3.129988] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10385 23:23:15.765695 <6>[ 3.138788] hub 2-0:1.0: USB hub found
10386 23:23:15.768609 <6>[ 3.142814] hub 2-0:1.0: 1 port detected
10387 23:23:15.777167 <6>[ 3.150571] mtk-msdc 11f70000.mmc: Got CD GPIO
10388 23:23:15.791129 <6>[ 3.161139] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10389 23:23:15.797557 <6>[ 3.169169] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10390 23:23:15.807521 <4>[ 3.177099] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10391 23:23:15.817439 <6>[ 3.186667] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10392 23:23:15.824603 <6>[ 3.194745] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10393 23:23:15.830758 <6>[ 3.202770] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10394 23:23:15.840267 <6>[ 3.210682] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10395 23:23:15.847009 <6>[ 3.218499] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10396 23:23:15.857899 <6>[ 3.226316] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10397 23:23:15.867258 <6>[ 3.236658] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10398 23:23:15.873442 <6>[ 3.245017] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10399 23:23:15.883690 <6>[ 3.253371] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10400 23:23:15.890906 <6>[ 3.261709] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10401 23:23:15.900434 <6>[ 3.270046] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10402 23:23:15.907418 <6>[ 3.278383] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10403 23:23:15.917049 <6>[ 3.286719] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10404 23:23:15.926611 <6>[ 3.295056] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10405 23:23:15.933208 <6>[ 3.303395] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10406 23:23:15.943183 <6>[ 3.311733] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10407 23:23:15.949303 <6>[ 3.320081] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10408 23:23:15.959170 <6>[ 3.328419] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10409 23:23:15.966598 <6>[ 3.336756] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10410 23:23:15.976448 <6>[ 3.345093] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10411 23:23:15.982335 <6>[ 3.353430] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10412 23:23:15.989242 <6>[ 3.361993] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10413 23:23:15.995502 <6>[ 3.369121] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10414 23:23:16.003161 <6>[ 3.375858] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10415 23:23:16.012254 <6>[ 3.382593] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10416 23:23:16.019889 <6>[ 3.389502] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10417 23:23:16.026285 <6>[ 3.396354] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10418 23:23:16.035396 <6>[ 3.405481] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10419 23:23:16.045965 <6>[ 3.414603] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10420 23:23:16.055324 <6>[ 3.423900] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10421 23:23:16.065006 <6>[ 3.433369] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10422 23:23:16.075850 <6>[ 3.442834] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10423 23:23:16.081950 <6>[ 3.451952] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10424 23:23:16.091898 <6>[ 3.461418] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10425 23:23:16.101401 <6>[ 3.470536] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10426 23:23:16.111181 <6>[ 3.479828] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10427 23:23:16.122991 <6>[ 3.489989] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10428 23:23:16.131232 <6>[ 3.501385] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10429 23:23:16.182573 <6>[ 3.553056] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10430 23:23:16.338061 <6>[ 3.711086] hub 1-1:1.0: USB hub found
10431 23:23:16.341424 <6>[ 3.715606] hub 1-1:1.0: 4 ports detected
10432 23:23:16.350881 <6>[ 3.723944] hub 1-1:1.0: USB hub found
10433 23:23:16.353587 <6>[ 3.728282] hub 1-1:1.0: 4 ports detected
10434 23:23:16.463320 <6>[ 3.833392] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10435 23:23:16.489357 <6>[ 3.862927] hub 2-1:1.0: USB hub found
10436 23:23:16.493317 <6>[ 3.867424] hub 2-1:1.0: 3 ports detected
10437 23:23:16.501628 <6>[ 3.875493] hub 2-1:1.0: USB hub found
10438 23:23:16.505196 <6>[ 3.879982] hub 2-1:1.0: 3 ports detected
10439 23:23:16.678564 <6>[ 4.049053] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10440 23:23:16.810886 <6>[ 4.184474] hub 1-1.4:1.0: USB hub found
10441 23:23:16.814399 <6>[ 4.189121] hub 1-1.4:1.0: 2 ports detected
10442 23:23:16.823230 <6>[ 4.196228] hub 1-1.4:1.0: USB hub found
10443 23:23:16.826814 <6>[ 4.200810] hub 1-1.4:1.0: 2 ports detected
10444 23:23:16.894958 <6>[ 4.265215] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10445 23:23:17.123563 <6>[ 4.493108] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10446 23:23:17.314816 <6>[ 4.685090] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10447 23:23:28.411770 <6>[ 15.790105] ALSA device list:
10448 23:23:28.418586 <6>[ 15.793394] No soundcards found.
10449 23:23:28.427021 <6>[ 15.801297] Freeing unused kernel memory: 8448K
10450 23:23:28.430055 <6>[ 15.806638] Run /init as init process
10451 23:23:28.481513 <6>[ 15.854860] NET: Registered PF_INET6 protocol family
10452 23:23:28.487253 <6>[ 15.861375] Segment Routing with IPv6
10453 23:23:28.489814 <6>[ 15.865327] In-situ OAM (IOAM) with IPv6
10454 23:23:28.534967 <30>[ 15.883773] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10455 23:23:28.542052 <30>[ 15.916985] systemd[1]: Detected architecture arm64.
10456 23:23:28.542153
10457 23:23:28.548806 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10458 23:23:28.548905
10459 23:23:28.548999
10460 23:23:28.565799 <30>[ 15.941056] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10461 23:23:28.750902 <30>[ 16.121586] systemd[1]: Queued start job for default target graphical.target.
10462 23:23:28.796301 <30>[ 16.166953] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10463 23:23:28.802904 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10464 23:23:28.803426
10465 23:23:28.822427 <30>[ 16.193538] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10466 23:23:28.829017 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10467 23:23:28.832694
10468 23:23:28.850604 <30>[ 16.221765] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10469 23:23:28.860334 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10470 23:23:28.860882
10471 23:23:28.879383 <30>[ 16.250462] systemd[1]: Created slice user.slice - User and Session Slice.
10472 23:23:28.885901 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10473 23:23:28.886404
10474 23:23:28.910374 <30>[ 16.277707] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10475 23:23:28.917132 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10476 23:23:28.919848
10477 23:23:28.938292 <30>[ 16.305173] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10478 23:23:28.943487 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10479 23:23:28.944004
10480 23:23:28.972116 <30>[ 16.333599] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10481 23:23:28.982212 <30>[ 16.353509] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10482 23:23:28.989550 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10483 23:23:28.990055
10484 23:23:29.006224 <30>[ 16.377081] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10485 23:23:29.013841 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10486 23:23:29.014365
10487 23:23:29.029838 <30>[ 16.401156] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10488 23:23:29.039600 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10489 23:23:29.040142
10490 23:23:29.055378 <30>[ 16.429219] systemd[1]: Reached target paths.target - Path Units.
10491 23:23:29.061250 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10492 23:23:29.064915
10493 23:23:29.082269 <30>[ 16.453544] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10494 23:23:29.089130 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10495 23:23:29.089656
10496 23:23:29.102582 <30>[ 16.477066] systemd[1]: Reached target slices.target - Slice Units.
10497 23:23:29.112336 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10498 23:23:29.112816
10499 23:23:29.127363 <30>[ 16.501569] systemd[1]: Reached target swap.target - Swaps.
10500 23:23:29.133509 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10501 23:23:29.134012
10502 23:23:29.154681 <30>[ 16.525588] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10503 23:23:29.164776 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10504 23:23:29.165512
10505 23:23:29.181922 <30>[ 16.553609] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10506 23:23:29.192194 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10507 23:23:29.192739
10508 23:23:29.212852 <30>[ 16.583061] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10509 23:23:29.221697 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10510 23:23:29.222213
10511 23:23:29.238150 <30>[ 16.609718] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10512 23:23:29.248668 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10513 23:23:29.249242
10514 23:23:29.266065 <30>[ 16.637693] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10515 23:23:29.272896 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10516 23:23:29.273414
10517 23:23:29.291033 <30>[ 16.661758] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10518 23:23:29.299996 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10519 23:23:29.300426
10520 23:23:29.319872 <30>[ 16.690474] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10521 23:23:29.329500 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10522 23:23:29.330022
10523 23:23:29.346353 <30>[ 16.717578] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10524 23:23:29.356164 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10525 23:23:29.356677
10526 23:23:29.413767 <30>[ 16.785264] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10527 23:23:29.420606 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10528 23:23:29.421188
10529 23:23:29.442369 <30>[ 16.812775] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10530 23:23:29.449124 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10531 23:23:29.449643
10532 23:23:29.467980 <30>[ 16.839328] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10533 23:23:29.474519 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10534 23:23:29.474942
10535 23:23:29.500589 <30>[ 16.865276] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10536 23:23:29.512460 <30>[ 16.883568] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10537 23:23:29.521990 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10538 23:23:29.522540
10539 23:23:29.542109 <30>[ 16.913410] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10540 23:23:29.548943 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10541 23:23:29.549482
10542 23:23:29.606341 <30>[ 16.977840] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10543 23:23:29.616480 Startin<6>[ 16.987500] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10544 23:23:29.622973 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10545 23:23:29.623499
10546 23:23:29.647615 <30>[ 17.018366] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10547 23:23:29.653382 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10548 23:23:29.653917
10549 23:23:29.678404 <30>[ 17.049699] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10550 23:23:29.685380 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10551 23:23:29.685916
10552 23:23:29.746435 <30>[ 17.117650] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10553 23:23:29.753762 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10554 23:23:29.754301
10555 23:23:29.782925 <30>[ 17.154041] systemd[1]: Starting systemd-journald.service - Journal Service...
10556 23:23:29.789297 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10557 23:23:29.789850
10558 23:23:29.808527 <30>[ 17.179734] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10559 23:23:29.814588 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10560 23:23:29.815029
10561 23:23:29.841121 <30>[ 17.209143] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10562 23:23:29.847675 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10563 23:23:29.848118
10564 23:23:29.873144 <30>[ 17.244698] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10565 23:23:29.882851 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10566 23:23:29.883441
10567 23:23:29.905313 <30>[ 17.276558] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10568 23:23:29.911927 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10569 23:23:29.912468
10570 23:23:29.937663 <30>[ 17.308347] systemd[1]: Started systemd-journald.service - Journal Service.
10571 23:23:29.944070 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10572 23:23:29.944604
10573 23:23:29.966080 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10574 23:23:29.966596
10575 23:23:29.982897 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10576 23:23:29.983426
10577 23:23:30.003335 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10578 23:23:30.003867
10579 23:23:30.023817 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10580 23:23:30.024340
10581 23:23:30.045523 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10582 23:23:30.046064
10583 23:23:30.063806 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10584 23:23:30.064330
10585 23:23:30.085092 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10586 23:23:30.085620
10587 23:23:30.105299 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10588 23:23:30.105838
10589 23:23:30.124480 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10590 23:23:30.125259
10591 23:23:30.143550 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10592 23:23:30.144123
10593 23:23:30.163425 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10594 23:23:30.163979
10595 23:23:30.184379 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10596 23:23:30.184989
10597 23:23:30.190978 See 'systemctl status systemd-remount-fs.service' for details.
10598 23:23:30.191481
10599 23:23:30.200658 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10600 23:23:30.201129
10601 23:23:30.220696 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10602 23:23:30.221281
10603 23:23:30.282900 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10604 23:23:30.283476
10605 23:23:30.304439 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10606 23:23:30.305058
10607 23:23:30.317456 <46>[ 17.688532] systemd-journald[180]: Received client request to flush runtime journal.
10608 23:23:30.328879 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10609 23:23:30.329437
10610 23:23:30.350060 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10611 23:23:30.350649
10612 23:23:30.374667 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10613 23:23:30.375214
10614 23:23:30.404563 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10615 23:23:30.405187
10616 23:23:30.427379 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10617 23:23:30.427950
10618 23:23:30.451151 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10619 23:23:30.451718
10620 23:23:30.475509 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10621 23:23:30.476065
10622 23:23:30.495899 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10623 23:23:30.496459
10624 23:23:30.555865 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10625 23:23:30.556430
10626 23:23:30.576374 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10627 23:23:30.576865
10628 23:23:30.594101 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10629 23:23:30.594540
10630 23:23:30.609898 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10631 23:23:30.610401
10632 23:23:30.646532 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10633 23:23:30.647083
10634 23:23:30.676426 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10635 23:23:30.677036
10636 23:23:30.706622 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10637 23:23:30.707185
10638 23:23:30.728695 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10639 23:23:30.729318
10640 23:23:30.776404 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10641 23:23:30.777016
10642 23:23:30.915192 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10643 23:23:30.915703
10644 23:23:30.943491 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10645 23:23:30.944002
10646 23:23:30.971782 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10647 23:23:30.972292
10648 23:23:31.010882 <5>[ 18.382216] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10649 23:23:31.021212 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10650 23:23:31.021855
10651 23:23:31.041822 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10652 23:23:31.042393
10653 23:23:31.055326 <5>[ 18.426812] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10654 23:23:31.062391 <5>[ 18.433962] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10655 23:23:31.069234 <6>[ 18.434828] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10656 23:23:31.078807 <4>[ 18.442499] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10657 23:23:31.088701 <6>[ 18.450764] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10658 23:23:31.091688 <6>[ 18.459275] cfg80211: failed to load regulatory.db
10659 23:23:31.102138 <3>[ 18.467808] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 23:23:31.108567 <6>[ 18.467957] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10661 23:23:31.118769 <6>[ 18.489113] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10662 23:23:31.124909 <3>[ 18.489432] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 23:23:31.134919 <3>[ 18.505187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 23:23:31.141641 <3>[ 18.509548] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 23:23:31.148703 <6>[ 18.510462] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10666 23:23:31.157892 <4>[ 18.513659] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10667 23:23:31.161962 <4>[ 18.513659] Fallback method does not support PEC.
10668 23:23:31.172169 [[0;32m OK [<6>[ 18.516017] usbcore: registered new device driver r8152-cfgselector
10669 23:23:31.179252 0m] Created slic<3>[ 18.521407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 23:23:31.188674 e [0;1;39msyste<3>[ 18.521417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 23:23:31.198239 m-syste…- Slic<3>[ 18.521426] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 23:23:31.209402 e /system/system<3>[ 18.521428] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 23:23:31.209962 d-backlight.
10674 23:23:31.210326
10675 23:23:31.216170 <3>[ 18.521493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 23:23:31.223632 <6>[ 18.522270] mc: Linux media interface: v0.10
10677 23:23:31.226657 <6>[ 18.529350] remoteproc remoteproc0: scp is available
10678 23:23:31.236356 <3>[ 18.543630] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10679 23:23:31.246337 <3>[ 18.550548] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10680 23:23:31.249589 <6>[ 18.550794] remoteproc remoteproc0: powering up scp
10681 23:23:31.259856 <6>[ 18.550801] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10682 23:23:31.262725 <6>[ 18.550828] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10683 23:23:31.272559 <4>[ 18.563477] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10684 23:23:31.279262 <3>[ 18.570223] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10685 23:23:31.289045 <3>[ 18.592015] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10686 23:23:31.295774 <4>[ 18.592019] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10687 23:23:31.305866 <3>[ 18.593224] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10688 23:23:31.308876 <6>[ 18.596549] videodev: Linux video capture interface: v2.00
10689 23:23:31.318741 <3>[ 18.597607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 23:23:31.326430 <3>[ 18.599459] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 23:23:31.331963 <6>[ 18.600391] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10692 23:23:31.339085 <6>[ 18.600410] pci_bus 0000:00: root bus resource [bus 00-ff]
10693 23:23:31.346857 <6>[ 18.600418] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10694 23:23:31.355380 <6>[ 18.600421] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10695 23:23:31.362724 <6>[ 18.600465] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10696 23:23:31.368488 <6>[ 18.600478] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10697 23:23:31.375327 <6>[ 18.600543] pci 0000:00:00.0: supports D1 D2
10698 23:23:31.382661 <6>[ 18.600544] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10699 23:23:31.388409 <6>[ 18.607266] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10700 23:23:31.398621 <3>[ 18.607612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 23:23:31.402940 <6>[ 18.616694] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10702 23:23:31.414000 <3>[ 18.624450] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 23:23:31.420054 <3>[ 18.624457] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 23:23:31.426471 <6>[ 18.629625] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10705 23:23:31.436868 <3>[ 18.638007] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 23:23:31.448772 <6>[ 18.638423] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10707 23:23:31.454352 <6>[ 18.638776] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10708 23:23:31.463766 <6>[ 18.643687] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10709 23:23:31.470738 <3>[ 18.650980] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 23:23:31.478707 <6>[ 18.659052] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10711 23:23:31.487409 <6>[ 18.676611] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10712 23:23:31.493402 <6>[ 18.676649] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10713 23:23:31.500219 <6>[ 18.676656] remoteproc remoteproc0: remote processor scp is now up
10714 23:23:31.503670 <6>[ 18.684437] pci 0000:01:00.0: supports D1 D2
10715 23:23:31.514262 <6>[ 18.693206] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10716 23:23:31.522977 <6>[ 18.696862] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10717 23:23:31.529979 <6>[ 18.700426] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10718 23:23:31.533467 <6>[ 18.714005] Bluetooth: Core ver 2.22
10719 23:23:31.540499 <6>[ 18.720597] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10720 23:23:31.547322 <6>[ 18.726174] NET: Registered PF_BLUETOOTH protocol family
10721 23:23:31.557178 <4>[ 18.728443] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10722 23:23:31.563699 <4>[ 18.728449] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10723 23:23:31.569676 <6>[ 18.728867] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10724 23:23:31.579781 <6>[ 18.728893] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10725 23:23:31.586156 <6>[ 18.728896] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10726 23:23:31.595905 <6>[ 18.728903] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10727 23:23:31.602632 <6>[ 18.728916] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10728 23:23:31.612426 <6>[ 18.728928] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10729 23:23:31.615848 <6>[ 18.728940] pci 0000:00:00.0: PCI bridge to [bus 01]
10730 23:23:31.625310 <6>[ 18.728944] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10731 23:23:31.628974 <6>[ 18.729058] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10732 23:23:31.635511 <6>[ 18.729482] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10733 23:23:31.642024 <6>[ 18.729691] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10734 23:23:31.652586 <6>[ 18.745785] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10735 23:23:31.658735 <6>[ 18.749754] Bluetooth: HCI device and connection manager initialized
10736 23:23:31.662642 <6>[ 18.749780] Bluetooth: HCI socket layer initialized
10737 23:23:31.668836 <6>[ 18.755303] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10738 23:23:31.675654 <6>[ 18.761153] Bluetooth: L2CAP socket layer initialized
10739 23:23:31.688496 <6>[ 18.770768] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10740 23:23:31.693172 <6>[ 18.777493] Bluetooth: SCO socket layer initialized
10741 23:23:31.701661 <3>[ 18.787512] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10742 23:23:31.707957 <6>[ 18.792087] usbcore: registered new interface driver uvcvideo
10743 23:23:31.715292 <6>[ 18.793398] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10744 23:23:31.721993 <3>[ 18.793421] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10745 23:23:31.731605 <3>[ 18.794180] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10746 23:23:31.734530 <6>[ 18.800247] r8152 2-1.3:1.0 eth0: v1.12.13
10747 23:23:31.744238 <3>[ 18.822677] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10748 23:23:31.751254 <6>[ 18.826173] usbcore: registered new interface driver r8152
10749 23:23:31.757746 <6>[ 18.830973] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10750 23:23:31.765562 <6>[ 18.831073] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10751 23:23:31.771101 <6>[ 18.835694] usbcore: registered new interface driver btusb
10752 23:23:31.781104 <4>[ 18.836217] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10753 23:23:31.787516 <3>[ 18.836225] Bluetooth: hci0: Failed to load firmware file (-2)
10754 23:23:31.790703 <3>[ 18.836228] Bluetooth: hci0: Failed to set up firmware (-2)
10755 23:23:31.800942 <4>[ 18.836229] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10756 23:23:31.806996 <6>[ 18.848946] mt7921e 0000:01:00.0: ASIC revision: 79610010
10757 23:23:31.813628 <6>[ 18.874140] usbcore: registered new interface driver cdc_ether
10758 23:23:31.823892 <6>[ 18.971893] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10759 23:23:31.824457 <6>[ 18.971893]
10760 23:23:31.830707 <6>[ 18.991221] usbcore: registered new interface driver r8153_ecm
10761 23:23:31.836807 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10762 23:23:31.837401
10763 23:23:31.858523 <3>[ 19.230178] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10764 23:23:31.870154 <6>[ 19.244102] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10765 23:23:31.886017 <6>[ 19.256609] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10766 23:23:31.899728 <3>[ 19.270253] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10767 23:23:31.908676 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10768 23:23:31.909395
10769 23:23:31.928134 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10770 23:23:31.928749
10771 23:23:31.938944 <3>[ 19.307369] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10772 23:23:31.948621 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10773 23:23:31.949245
10774 23:23:32.009690 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10775 23:23:32.010237
10776 23:23:32.022780 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10777 23:23:32.023377
10778 23:23:32.041943 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10779 23:23:32.042493
10780 23:23:32.058803 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10781 23:23:32.059317
10782 23:23:32.077605 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10783 23:23:32.078045
10784 23:23:32.093416 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10785 23:23:32.093934
10786 23:23:32.110107 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10787 23:23:32.110850
10788 23:23:32.125869 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10789 23:23:32.126323
10790 23:23:32.131823 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10791 23:23:32.132263
10792 23:23:32.149705 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10793 23:23:32.149942
10794 23:23:32.202746 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10795 23:23:32.202892
10796 23:23:32.230743 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10797 23:23:32.230864
10798 23:23:32.254848 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10799 23:23:32.255006
10800 23:23:32.276284 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10801 23:23:32.276603
10802 23:23:32.307653 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10803 23:23:32.307830
10804 23:23:32.366548 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10805 23:23:32.366698
10806 23:23:32.418091 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10807 23:23:32.418242
10808 23:23:32.437199 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10809 23:23:32.437332
10810 23:23:32.493936 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10811 23:23:32.494084
10812 23:23:32.511067 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10813 23:23:32.511760
10814 23:23:32.529677 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10815 23:23:32.529911
10816 23:23:32.548086 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10817 23:23:32.548243
10818 23:23:32.566742 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10819 23:23:32.566993
10820 23:23:32.618934 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10821 23:23:32.619097
10822 23:23:32.658970 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10823 23:23:32.659133
10824 23:23:32.681052
10825 23:23:32.681222
10826 23:23:32.684327 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10827 23:23:32.684462
10828 23:23:32.687680 debian-bookworm-arm64 login: root (automatic login)
10829 23:23:32.687862
10830 23:23:32.687957
10831 23:23:32.698816 Linux debian-bookworm-arm64 6.1.83-cip18 #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024 aarch64
10832 23:23:32.699034
10833 23:23:32.705863 The programs included with the Debian GNU/Linux system are free software;
10834 23:23:32.712479 the exact distribution terms for each program are described in the
10835 23:23:32.715345 individual files in /usr/share/doc/*/copyright.
10836 23:23:32.715555
10837 23:23:32.722386 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10838 23:23:32.725511 permitted by applicable law.
10839 23:23:32.726554 Matched prompt #10: / #
10841 23:23:32.727323 Setting prompt string to ['/ #']
10842 23:23:32.727656 end: 2.2.5.1 login-action (duration 00:00:21) [common]
10844 23:23:32.728393 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10845 23:23:32.728784 start: 2.2.6 expect-shell-connection (timeout 00:03:19) [common]
10846 23:23:32.729157 Setting prompt string to ['/ #']
10847 23:23:32.729465 Forcing a shell prompt, looking for ['/ #']
10849 23:23:32.780262 / #
10850 23:23:32.780981 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10851 23:23:32.781400 Waiting using forced prompt support (timeout 00:02:30)
10852 23:23:32.781934 <6>[ 20.113251] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10853 23:23:32.787065
10854 23:23:32.788002 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10855 23:23:32.788536 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
10856 23:23:32.789104 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10857 23:23:32.789572 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
10858 23:23:32.790032 end: 2 depthcharge-action (duration 00:01:42) [common]
10859 23:23:32.790531 start: 3 lava-test-retry (timeout 00:07:58) [common]
10860 23:23:32.790995 start: 3.1 lava-test-shell (timeout 00:07:58) [common]
10861 23:23:32.791404 Using namespace: common
10863 23:23:32.892814 / # #
10864 23:23:32.893463 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10865 23:23:32.899911 #
10866 23:23:32.900853 Using /lava-13248448
10868 23:23:33.002318 / # export SHELL=/bin/sh
10869 23:23:33.003117 export SHELL=/bin/sh<6>[ 20.375806] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10870 23:23:33.009044
10872 23:23:33.111166 / # . /lava-13248448/environment
10873 23:23:33.117968 . /lava-13248448/environment
10875 23:23:33.219879 / # /lava-13248448/bin/lava-test-runner /lava-13248448/0
10876 23:23:33.220549 Test shell timeout: 10s (minimum of the action and connection timeout)
10877 23:23:33.227584 /lava-13248448/bin/lava-test-runner /lava-13248448/0
10878 23:23:33.247207 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10879 23:23:33.254014 + cd /lava-13248448/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10880 23:23:33.254480 + cat uuid
10881 23:23:33.257419 + UUID=13248448_1.5.2.3.1
10882 23:23:33.257882 + set +x
10883 23:23:33.263977 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 13248448_1.5.2.3.1>
10884 23:23:33.264778 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 13248448_1.5.2.3.1
10885 23:23:33.265198 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (13248448_1.5.2.3.1)
10886 23:23:33.265640 Skipping test definition patterns.
10887 23:23:33.267655 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
10888 23:23:33.273954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10889 23:23:33.274785 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10891 23:23:33.283744 device: /dev/vide<4>[ 20.653593] use of bytesused == 0 is deprecated and will be removed in the future,
10892 23:23:33.284266 o2
10893 23:23:33.286692 <4>[ 20.662330] use the actual size instead.
10894 23:23:33.301037 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
10895 23:23:33.311817 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
10896 23:23:33.317762
10897 23:23:33.333758 Compliance test for mtk-vcodec-enc device /dev/video2:
10898 23:23:33.339727
10899 23:23:33.348250 Driver Info:
10900 23:23:33.359019 Driver name : mtk-vcodec-enc
10901 23:23:33.372328 Card type : MT8192 video encoder
10902 23:23:33.386581 Bus info : platform:17020000.vcodec
10903 23:23:33.394415 Driver version : 6.1.83
10904 23:23:33.404301 Capabilities : 0x84204000
10905 23:23:33.416634 Video Memory-to-Memory Multiplanar
10906 23:23:33.427317 Streaming
10907 23:23:33.438695 Extended Pix Format
10908 23:23:33.456114 <6>[ 20.827981] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c6803bd: link becomes ready
10909 23:23:33.456659 Device Capabilities
10910 23:23:33.469434 Device Caps : 0x04204000
10911 23:23:33.480427 Video Memory-to-Memory Multiplanar
10912 23:23:33.489844 Streaming
10913 23:23:33.503339 Extended Pix Format
10914 23:23:33.514796 Detected Stateful Encoder
10915 23:23:33.522380
10916 23:23:33.532245 Required ioctls:
10917 23:23:33.561413 <LAVA_SIGNAL_TESTSET START Required-ioctls>
10918 23:23:33.561955 test VIDIOC_QUERYCAP: OK
10919 23:23:33.562591 Received signal: <TESTSET> START Required-ioctls
10920 23:23:33.562978 Starting test_set Required-ioctls
10921 23:23:33.586709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10922 23:23:33.587560 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10924 23:23:33.589420 test invalid ioctls: OK
10925 23:23:33.611410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
10926 23:23:33.611952
10927 23:23:33.612577 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
10929 23:23:33.630706 Allow for multiple opens:
10930 23:23:33.638233 <LAVA_SIGNAL_TESTSET STOP>
10931 23:23:33.639069 Received signal: <TESTSET> STOP
10932 23:23:33.639486 Closing test_set Required-ioctls
10933 23:23:33.646582 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
10934 23:23:33.647325 Received signal: <TESTSET> START Allow-for-multiple-opens
10935 23:23:33.647708 Starting test_set Allow-for-multiple-opens
10936 23:23:33.649749 test second /dev/video2 open: OK
10937 23:23:33.669464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
10938 23:23:33.670274 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
10940 23:23:33.672694 test VIDIOC_QUERYCAP: OK
10941 23:23:33.694552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10942 23:23:33.695408 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10944 23:23:33.698095 test VIDIOC_G/S_PRIORITY: OK
10945 23:23:33.717465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
10946 23:23:33.718372 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
10948 23:23:33.720280 test for unlimited opens: OK
10949 23:23:33.742163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
10950 23:23:33.742728
10951 23:23:33.743488 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
10953 23:23:33.751896 Debug ioctls:
10954 23:23:33.758709 <LAVA_SIGNAL_TESTSET STOP>
10955 23:23:33.759460 Received signal: <TESTSET> STOP
10956 23:23:33.759875 Closing test_set Allow-for-multiple-opens
10957 23:23:33.768333 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
10958 23:23:33.769240 Received signal: <TESTSET> START Debug-ioctls
10959 23:23:33.769671 Starting test_set Debug-ioctls
10960 23:23:33.771851 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
10961 23:23:33.794480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
10962 23:23:33.795356 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
10964 23:23:33.800922 test VIDIOC_LOG_STATUS: OK (Not Supported)
10965 23:23:33.818147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
10966 23:23:33.818722
10967 23:23:33.819477 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
10969 23:23:33.828374 Input ioctls:
10970 23:23:33.835582 <LAVA_SIGNAL_TESTSET STOP>
10971 23:23:33.836454 Received signal: <TESTSET> STOP
10972 23:23:33.836908 Closing test_set Debug-ioctls
10973 23:23:33.845013 <LAVA_SIGNAL_TESTSET START Input-ioctls>
10974 23:23:33.845880 Received signal: <TESTSET> START Input-ioctls
10975 23:23:33.846310 Starting test_set Input-ioctls
10976 23:23:33.848248 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
10977 23:23:33.875398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
10978 23:23:33.876271 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
10980 23:23:33.877685 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
10981 23:23:33.894559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
10982 23:23:33.895407 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
10984 23:23:33.901011 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
10985 23:23:33.920209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
10986 23:23:33.921088 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
10988 23:23:33.927542 test VIDIOC_ENUMAUDIO: OK (Not Supported)
10989 23:23:33.943660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
10990 23:23:33.944507 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
10992 23:23:33.947037 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
10993 23:23:33.967032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
10994 23:23:33.967867 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
10996 23:23:33.969200 test VIDIOC_G/S_AUDIO: OK (Not Supported)
10997 23:23:33.990594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
10998 23:23:33.991432 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11000 23:23:33.994224 Inputs: 0 Audio Inputs: 0 Tuners: 0
11001 23:23:34.001458
11002 23:23:34.017704 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11003 23:23:34.037054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11004 23:23:34.037889 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11006 23:23:34.043285 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11007 23:23:34.060359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11008 23:23:34.061244 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11010 23:23:34.062790 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11011 23:23:34.084023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11012 23:23:34.084913 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11014 23:23:34.090114 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11015 23:23:34.107383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11016 23:23:34.108256 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11018 23:23:34.113628 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11019 23:23:34.131878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11020 23:23:34.132452
11021 23:23:34.133296 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11023 23:23:34.150051 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11024 23:23:34.172613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11025 23:23:34.173541 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11027 23:23:34.179223 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11028 23:23:34.199934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11029 23:23:34.200771 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11031 23:23:34.203072 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11032 23:23:34.220408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11033 23:23:34.221431 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11035 23:23:34.223597 test VIDIOC_G/S_EDID: OK (Not Supported)
11036 23:23:34.249041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11037 23:23:34.249567
11038 23:23:34.250200 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11040 23:23:34.259647 Control ioctls:
11041 23:23:34.264860 <LAVA_SIGNAL_TESTSET STOP>
11042 23:23:34.265669 Received signal: <TESTSET> STOP
11043 23:23:34.266056 Closing test_set Input-ioctls
11044 23:23:34.274824 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11045 23:23:34.275638 Received signal: <TESTSET> START Control-ioctls
11046 23:23:34.276027 Starting test_set Control-ioctls
11047 23:23:34.277796 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11048 23:23:34.300064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11049 23:23:34.300622 test VIDIOC_QUERYCTRL: OK
11050 23:23:34.301398 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11052 23:23:34.323739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11053 23:23:34.324536 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11055 23:23:34.326738 test VIDIOC_G/S_CTRL: OK
11056 23:23:34.351106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11057 23:23:34.351951 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11059 23:23:34.353524 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11060 23:23:34.374670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11061 23:23:34.375607 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11063 23:23:34.380911 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11064 23:23:34.388749 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11065 23:23:34.415763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11066 23:23:34.416602 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11068 23:23:34.419261 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11069 23:23:34.436900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11070 23:23:34.437727 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11072 23:23:34.440328 Standard Controls: 16 Private Controls: 0
11073 23:23:34.447156
11074 23:23:34.459383 Format ioctls:
11075 23:23:34.468053 <LAVA_SIGNAL_TESTSET STOP>
11076 23:23:34.468887 Received signal: <TESTSET> STOP
11077 23:23:34.469279 Closing test_set Control-ioctls
11078 23:23:34.478487 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11079 23:23:34.479305 Received signal: <TESTSET> START Format-ioctls
11080 23:23:34.479712 Starting test_set Format-ioctls
11081 23:23:34.481158 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11082 23:23:34.505138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11083 23:23:34.505980 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11085 23:23:34.508462 test VIDIOC_G/S_PARM: OK
11086 23:23:34.527710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11087 23:23:34.528676 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11089 23:23:34.530517 test VIDIOC_G_FBUF: OK (Not Supported)
11090 23:23:34.555891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11091 23:23:34.556750 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11093 23:23:34.559094 test VIDIOC_G_FMT: OK
11094 23:23:34.578184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11095 23:23:34.579002 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11097 23:23:34.581218 test VIDIOC_TRY_FMT: OK
11098 23:23:34.604881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11099 23:23:34.605673 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11101 23:23:34.610822 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11102 23:23:34.614917 test VIDIOC_S_FMT: FAIL
11103 23:23:34.636780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11104 23:23:34.637574 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11106 23:23:34.640904 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11107 23:23:34.659937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11108 23:23:34.660760 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11110 23:23:34.662805 test Cropping: OK
11111 23:23:34.681204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11112 23:23:34.682001 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11114 23:23:34.684289 test Composing: OK (Not Supported)
11115 23:23:34.705039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11116 23:23:34.705835 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11118 23:23:34.708011 test Scaling: OK (Not Supported)
11119 23:23:34.729070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11120 23:23:34.729605
11121 23:23:34.730243 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11123 23:23:34.740205 Codec ioctls:
11124 23:23:34.746678 <LAVA_SIGNAL_TESTSET STOP>
11125 23:23:34.747487 Received signal: <TESTSET> STOP
11126 23:23:34.747874 Closing test_set Format-ioctls
11127 23:23:34.759178 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11128 23:23:34.760008 Received signal: <TESTSET> START Codec-ioctls
11129 23:23:34.760406 Starting test_set Codec-ioctls
11130 23:23:34.763287 test VIDIOC_(TRY_)ENCODER_CMD: OK
11131 23:23:34.786023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11132 23:23:34.786866 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11134 23:23:34.792276 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11135 23:23:34.809166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11136 23:23:34.810014 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11138 23:23:34.815395 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11139 23:23:34.838059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11140 23:23:34.838621
11141 23:23:34.839252 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11143 23:23:34.849180 Buffer ioctls:
11144 23:23:34.857378 <LAVA_SIGNAL_TESTSET STOP>
11145 23:23:34.858244 Received signal: <TESTSET> STOP
11146 23:23:34.858778 Closing test_set Codec-ioctls
11147 23:23:34.867474 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11148 23:23:34.868315 Received signal: <TESTSET> START Buffer-ioctls
11149 23:23:34.868702 Starting test_set Buffer-ioctls
11150 23:23:34.870458 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11151 23:23:34.891876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11152 23:23:34.892818 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11154 23:23:34.895595 test CREATE_BUFS maximum buffers: OK
11155 23:23:34.915994 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11157 23:23:34.918684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11158 23:23:34.919147 test VIDIOC_EXPBUF: OK
11159 23:23:34.939395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11160 23:23:34.940245 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11162 23:23:34.941961 test Requests: OK (Not Supported)
11163 23:23:34.962629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11164 23:23:34.963205
11165 23:23:34.963848 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11167 23:23:34.973038 Test input 0:
11168 23:23:34.983664
11169 23:23:34.995633 Streaming ioctls:
11170 23:23:35.003968 <LAVA_SIGNAL_TESTSET STOP>
11171 23:23:35.004775 Received signal: <TESTSET> STOP
11172 23:23:35.005175 Closing test_set Buffer-ioctls
11173 23:23:35.012741 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11174 23:23:35.013476 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11175 23:23:35.013881 Starting test_set Streaming-ioctls_Test-input-0
11176 23:23:35.016291 test read/write: OK (Not Supported)
11177 23:23:35.038370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11178 23:23:35.039188 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11180 23:23:35.045178 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11181 23:23:35.052960 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11182 23:23:35.064778 test blocking wait: FAIL
11183 23:23:35.092782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11184 23:23:35.093635 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11186 23:23:35.098565 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11187 23:23:35.101851 test MMAP (select): FAIL
11188 23:23:35.130859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11189 23:23:35.131719 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11191 23:23:35.139051 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11192 23:23:35.141461 test MMAP (epoll): FAIL
11193 23:23:35.166984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11194 23:23:35.167814 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11196 23:23:35.172395 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11197 23:23:35.179272 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11198 23:23:35.184815 test USERPTR (select): FAIL
11199 23:23:35.215829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11200 23:23:35.216666 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11202 23:23:35.222057 test DMABUF: Cannot test, specify --expbuf-device
11203 23:23:35.228457
11204 23:23:35.244383 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11205 23:23:35.247474 <LAVA_TEST_RUNNER EXIT>
11206 23:23:35.248543 ok: lava_test_shell seems to have completed
11207 23:23:35.249302 Marking unfinished test run as failed
11209 23:23:35.255334 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11210 23:23:35.256029 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11211 23:23:35.256506 end: 3 lava-test-retry (duration 00:00:02) [common]
11212 23:23:35.257018 start: 4 finalize (timeout 00:07:55) [common]
11213 23:23:35.257568 start: 4.1 power-off (timeout 00:00:30) [common]
11214 23:23:35.258935 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11215 23:23:35.387480 >> Command sent successfully.
11216 23:23:35.391305 Returned 0 in 0 seconds
11217 23:23:35.492424 end: 4.1 power-off (duration 00:00:00) [common]
11219 23:23:35.494210 start: 4.2 read-feedback (timeout 00:07:55) [common]
11220 23:23:35.495489 Listened to connection for namespace 'common' for up to 1s
11221 23:23:36.495440 Finalising connection for namespace 'common'
11222 23:23:36.496107 Disconnecting from shell: Finalise
11223 23:23:36.496516 / #
11224 23:23:36.597497 end: 4.2 read-feedback (duration 00:00:01) [common]
11225 23:23:36.598159 end: 4 finalize (duration 00:00:01) [common]
11226 23:23:36.598727 Cleaning after the job
11227 23:23:36.599254 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/ramdisk
11228 23:23:36.624677 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/kernel
11229 23:23:36.644924 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/dtb
11230 23:23:36.645212 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248448/tftp-deploy-hxgkz2eb/modules
11231 23:23:36.654842 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248448
11232 23:23:36.726734 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248448
11233 23:23:36.726908 Job finished correctly