Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 1
- Kernel Errors: 29
- Boot result: PASS
1 23:20:44.691364 lava-dispatcher, installed at version: 2024.01
2 23:20:44.691591 start: 0 validate
3 23:20:44.691733 Start time: 2024-04-03 23:20:44.691725+00:00 (UTC)
4 23:20:44.691865 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:20:44.692009 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:20:44.954795 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:20:44.955056 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:21:12.207315 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:21:12.207561 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:21:12.465184 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:21:12.465444 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:21:16.218662 validate duration: 31.53
14 23:21:16.218935 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:21:16.219038 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:21:16.219129 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:21:16.219252 Not decompressing ramdisk as can be used compressed.
18 23:21:16.219341 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 23:21:16.219408 saving as /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/ramdisk/rootfs.cpio.gz
20 23:21:16.219472 total size: 28105535 (26 MB)
21 23:21:16.468223 progress 0 % (0 MB)
22 23:21:16.476650 progress 5 % (1 MB)
23 23:21:16.485106 progress 10 % (2 MB)
24 23:21:16.493790 progress 15 % (4 MB)
25 23:21:16.501780 progress 20 % (5 MB)
26 23:21:16.509430 progress 25 % (6 MB)
27 23:21:16.517016 progress 30 % (8 MB)
28 23:21:16.524594 progress 35 % (9 MB)
29 23:21:16.532497 progress 40 % (10 MB)
30 23:21:16.540184 progress 45 % (12 MB)
31 23:21:16.547821 progress 50 % (13 MB)
32 23:21:16.555729 progress 55 % (14 MB)
33 23:21:16.563825 progress 60 % (16 MB)
34 23:21:16.571903 progress 65 % (17 MB)
35 23:21:16.580031 progress 70 % (18 MB)
36 23:21:16.588195 progress 75 % (20 MB)
37 23:21:16.596363 progress 80 % (21 MB)
38 23:21:16.605081 progress 85 % (22 MB)
39 23:21:16.613652 progress 90 % (24 MB)
40 23:21:16.621749 progress 95 % (25 MB)
41 23:21:16.629717 progress 100 % (26 MB)
42 23:21:16.630022 26 MB downloaded in 0.41 s (65.29 MB/s)
43 23:21:16.630221 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:21:16.630477 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:21:16.630569 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:21:16.630655 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:21:16.630807 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:21:16.630880 saving as /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/kernel/Image
50 23:21:16.630953 total size: 54286848 (51 MB)
51 23:21:16.631022 No compression specified
52 23:21:16.632177 progress 0 % (0 MB)
53 23:21:16.651530 progress 5 % (2 MB)
54 23:21:16.670671 progress 10 % (5 MB)
55 23:21:16.687109 progress 15 % (7 MB)
56 23:21:16.707627 progress 20 % (10 MB)
57 23:21:16.724814 progress 25 % (12 MB)
58 23:21:16.745465 progress 30 % (15 MB)
59 23:21:16.763452 progress 35 % (18 MB)
60 23:21:16.779835 progress 40 % (20 MB)
61 23:21:16.800421 progress 45 % (23 MB)
62 23:21:16.821864 progress 50 % (25 MB)
63 23:21:16.843761 progress 55 % (28 MB)
64 23:21:16.861110 progress 60 % (31 MB)
65 23:21:16.878475 progress 65 % (33 MB)
66 23:21:16.897591 progress 70 % (36 MB)
67 23:21:16.918945 progress 75 % (38 MB)
68 23:21:16.940066 progress 80 % (41 MB)
69 23:21:16.961364 progress 85 % (44 MB)
70 23:21:16.982130 progress 90 % (46 MB)
71 23:21:16.999873 progress 95 % (49 MB)
72 23:21:17.021424 progress 100 % (51 MB)
73 23:21:17.021843 51 MB downloaded in 0.39 s (132.45 MB/s)
74 23:21:17.022113 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:21:17.022587 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:21:17.022767 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:21:17.022947 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:21:17.023214 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:21:17.023350 saving as /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/dtb/mt8192-asurada-spherion-r0.dtb
81 23:21:17.023499 total size: 47230 (0 MB)
82 23:21:17.023642 No compression specified
83 23:21:17.025508 progress 69 % (0 MB)
84 23:21:17.025967 progress 100 % (0 MB)
85 23:21:17.026272 0 MB downloaded in 0.00 s (16.27 MB/s)
86 23:21:17.026514 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:21:17.026979 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:21:17.027123 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:21:17.027293 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:21:17.027559 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:21:17.027688 saving as /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/modules/modules.tar
93 23:21:17.027829 total size: 8629908 (8 MB)
94 23:21:17.027947 Using unxz to decompress xz
95 23:21:17.033483 progress 0 % (0 MB)
96 23:21:17.055501 progress 5 % (0 MB)
97 23:21:17.085210 progress 10 % (0 MB)
98 23:21:17.112166 progress 15 % (1 MB)
99 23:21:17.138556 progress 20 % (1 MB)
100 23:21:17.165545 progress 25 % (2 MB)
101 23:21:17.193854 progress 30 % (2 MB)
102 23:21:17.220764 progress 35 % (2 MB)
103 23:21:17.250183 progress 40 % (3 MB)
104 23:21:17.283460 progress 45 % (3 MB)
105 23:21:17.312209 progress 50 % (4 MB)
106 23:21:17.340166 progress 55 % (4 MB)
107 23:21:17.377603 progress 60 % (4 MB)
108 23:21:17.406390 progress 65 % (5 MB)
109 23:21:17.436054 progress 70 % (5 MB)
110 23:21:17.463181 progress 75 % (6 MB)
111 23:21:17.491811 progress 80 % (6 MB)
112 23:21:17.527162 progress 85 % (7 MB)
113 23:21:17.564557 progress 90 % (7 MB)
114 23:21:17.606589 progress 95 % (7 MB)
115 23:21:17.639114 progress 100 % (8 MB)
116 23:21:17.645101 8 MB downloaded in 0.62 s (13.33 MB/s)
117 23:21:17.645537 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:21:17.646062 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:21:17.646247 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:21:17.646416 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:21:17.646573 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:21:17.646738 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:21:17.647110 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp
125 23:21:17.647372 makedir: /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin
126 23:21:17.647574 makedir: /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/tests
127 23:21:17.647799 makedir: /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/results
128 23:21:17.648014 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-add-keys
129 23:21:17.648276 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-add-sources
130 23:21:17.648514 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-background-process-start
131 23:21:17.648748 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-background-process-stop
132 23:21:17.648978 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-common-functions
133 23:21:17.649224 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-echo-ipv4
134 23:21:17.649459 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-install-packages
135 23:21:17.649698 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-installed-packages
136 23:21:17.649971 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-os-build
137 23:21:17.650257 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-probe-channel
138 23:21:17.650535 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-probe-ip
139 23:21:17.650813 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-target-ip
140 23:21:17.651033 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-target-mac
141 23:21:17.651281 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-target-storage
142 23:21:17.651510 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-test-case
143 23:21:17.651730 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-test-event
144 23:21:17.651945 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-test-feedback
145 23:21:17.652171 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-test-raise
146 23:21:17.652411 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-test-reference
147 23:21:17.652657 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-test-runner
148 23:21:17.652932 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-test-set
149 23:21:17.653175 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-test-shell
150 23:21:17.653450 Updating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-install-packages (oe)
151 23:21:17.653735 Updating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/bin/lava-installed-packages (oe)
152 23:21:17.653973 Creating /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/environment
153 23:21:17.654175 LAVA metadata
154 23:21:17.654343 - LAVA_JOB_ID=13248400
155 23:21:17.654499 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:21:17.654770 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:21:17.654909 skipped lava-vland-overlay
158 23:21:17.655099 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:21:17.655250 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:21:17.655367 skipped lava-multinode-overlay
161 23:21:17.655569 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:21:17.655779 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:21:17.655940 Loading test definitions
164 23:21:17.656126 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:21:17.656273 Using /lava-13248400 at stage 0
166 23:21:17.657062 uuid=13248400_1.5.2.3.1 testdef=None
167 23:21:17.657220 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:21:17.657373 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:21:17.658380 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:21:17.658904 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:21:17.660105 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:21:17.660618 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:21:17.661753 runner path: /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/0/tests/0_v4l2-compliance-uvc test_uuid 13248400_1.5.2.3.1
176 23:21:17.662022 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:21:17.662455 Creating lava-test-runner.conf files
179 23:21:17.662583 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248400/lava-overlay-obtsugmp/lava-13248400/0 for stage 0
180 23:21:17.662747 - 0_v4l2-compliance-uvc
181 23:21:17.662922 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:21:17.663077 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:21:17.675468 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:21:17.675751 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:21:17.675973 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:21:17.676143 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:21:17.676314 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:21:18.723512 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:21:18.723953 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 23:21:18.724106 extracting modules file /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248400/extract-overlay-ramdisk-zw5xgolf/ramdisk
191 23:21:19.046385 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:21:19.046656 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 23:21:19.046835 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248400/compress-overlay-9048jpq6/overlay-1.5.2.4.tar.gz to ramdisk
194 23:21:19.046980 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248400/compress-overlay-9048jpq6/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248400/extract-overlay-ramdisk-zw5xgolf/ramdisk
195 23:21:19.057423 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:21:19.057588 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 23:21:19.057683 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:21:19.057786 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 23:21:19.057875 Building ramdisk /var/lib/lava/dispatcher/tmp/13248400/extract-overlay-ramdisk-zw5xgolf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248400/extract-overlay-ramdisk-zw5xgolf/ramdisk
200 23:21:19.884857 >> 276140 blocks
201 23:21:24.536026 rename /var/lib/lava/dispatcher/tmp/13248400/extract-overlay-ramdisk-zw5xgolf/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/ramdisk/ramdisk.cpio.gz
202 23:21:24.536636 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 23:21:24.536810 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 23:21:24.536951 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 23:21:24.537110 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/kernel/Image'
206 23:21:41.234378 Returned 0 in 16 seconds
207 23:21:41.335094 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/kernel/image.itb
208 23:21:42.072227 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:21:42.072631 output: Created: Thu Apr 4 00:21:41 2024
210 23:21:42.072735 output: Image 0 (kernel-1)
211 23:21:42.072826 output: Description:
212 23:21:42.072913 output: Created: Thu Apr 4 00:21:41 2024
213 23:21:42.072995 output: Type: Kernel Image
214 23:21:42.073078 output: Compression: lzma compressed
215 23:21:42.073158 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
216 23:21:42.073260 output: Architecture: AArch64
217 23:21:42.073358 output: OS: Linux
218 23:21:42.073460 output: Load Address: 0x00000000
219 23:21:42.073558 output: Entry Point: 0x00000000
220 23:21:42.073657 output: Hash algo: crc32
221 23:21:42.073758 output: Hash value: d7c9dcc1
222 23:21:42.073858 output: Image 1 (fdt-1)
223 23:21:42.073958 output: Description: mt8192-asurada-spherion-r0
224 23:21:42.074056 output: Created: Thu Apr 4 00:21:41 2024
225 23:21:42.074151 output: Type: Flat Device Tree
226 23:21:42.074249 output: Compression: uncompressed
227 23:21:42.074345 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 23:21:42.074441 output: Architecture: AArch64
229 23:21:42.074536 output: Hash algo: crc32
230 23:21:42.074630 output: Hash value: 4bf0d1ac
231 23:21:42.074725 output: Image 2 (ramdisk-1)
232 23:21:42.074819 output: Description: unavailable
233 23:21:42.074913 output: Created: Thu Apr 4 00:21:41 2024
234 23:21:42.075008 output: Type: RAMDisk Image
235 23:21:42.075102 output: Compression: Unknown Compression
236 23:21:42.075196 output: Data Size: 41250775 Bytes = 40283.96 KiB = 39.34 MiB
237 23:21:42.075291 output: Architecture: AArch64
238 23:21:42.075386 output: OS: Linux
239 23:21:42.075480 output: Load Address: unavailable
240 23:21:42.075574 output: Entry Point: unavailable
241 23:21:42.075669 output: Hash algo: crc32
242 23:21:42.075762 output: Hash value: 8bb1692b
243 23:21:42.075856 output: Default Configuration: 'conf-1'
244 23:21:42.075950 output: Configuration 0 (conf-1)
245 23:21:42.076044 output: Description: mt8192-asurada-spherion-r0
246 23:21:42.076139 output: Kernel: kernel-1
247 23:21:42.076234 output: Init Ramdisk: ramdisk-1
248 23:21:42.076340 output: FDT: fdt-1
249 23:21:42.076436 output: Loadables: kernel-1
250 23:21:42.076532 output:
251 23:21:42.076789 end: 1.5.8.1 prepare-fit (duration 00:00:18) [common]
252 23:21:42.076935 end: 1.5.8 prepare-kernel (duration 00:00:18) [common]
253 23:21:42.077094 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 23:21:42.077235 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:34) [common]
255 23:21:42.077360 No LXC device requested
256 23:21:42.077487 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:21:42.077621 start: 1.7 deploy-device-env (timeout 00:09:34) [common]
258 23:21:42.077745 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:21:42.077857 Checking files for TFTP limit of 4294967296 bytes.
260 23:21:42.078559 end: 1 tftp-deploy (duration 00:00:26) [common]
261 23:21:42.078703 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:21:42.078842 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:21:42.079027 substitutions:
264 23:21:42.079129 - {DTB}: 13248400/tftp-deploy-netd99_i/dtb/mt8192-asurada-spherion-r0.dtb
265 23:21:42.079237 - {INITRD}: 13248400/tftp-deploy-netd99_i/ramdisk/ramdisk.cpio.gz
266 23:21:42.079338 - {KERNEL}: 13248400/tftp-deploy-netd99_i/kernel/Image
267 23:21:42.079438 - {LAVA_MAC}: None
268 23:21:42.079539 - {PRESEED_CONFIG}: None
269 23:21:42.079637 - {PRESEED_LOCAL}: None
270 23:21:42.079736 - {RAMDISK}: 13248400/tftp-deploy-netd99_i/ramdisk/ramdisk.cpio.gz
271 23:21:42.079834 - {ROOT_PART}: None
272 23:21:42.079932 - {ROOT}: None
273 23:21:42.080029 - {SERVER_IP}: 192.168.201.1
274 23:21:42.080126 - {TEE}: None
275 23:21:42.080222 Parsed boot commands:
276 23:21:42.080326 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:21:42.080572 Parsed boot commands: tftpboot 192.168.201.1 13248400/tftp-deploy-netd99_i/kernel/image.itb 13248400/tftp-deploy-netd99_i/kernel/cmdline
278 23:21:42.080703 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:21:42.080839 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:21:42.080992 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:21:42.081122 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:21:42.081231 Not connected, no need to disconnect.
283 23:21:42.081363 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:21:42.081506 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:21:42.081612 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 23:21:42.086100 Setting prompt string to ['lava-test: # ']
287 23:21:42.086703 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:21:42.086920 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:21:42.087129 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:21:42.087328 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:21:42.087731 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 23:21:47.226767 >> Command sent successfully.
293 23:21:47.230025 Returned 0 in 5 seconds
294 23:21:47.330494 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:21:47.330970 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:21:47.331089 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:21:47.331228 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:21:47.331298 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:21:47.331366 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:21:47.331636 [Enter `^Ec?' for help]
302 23:21:47.501260
303 23:21:47.501474
304 23:21:47.501590 F0: 102B 0000
305 23:21:47.501692
306 23:21:47.501791 F3: 1001 0000 [0200]
307 23:21:47.504257
308 23:21:47.504381 F3: 1001 0000
309 23:21:47.504481
310 23:21:47.504581 F7: 102D 0000
311 23:21:47.504675
312 23:21:47.507592 F1: 0000 0000
313 23:21:47.507721
314 23:21:47.507821 V0: 0000 0000 [0001]
315 23:21:47.507920
316 23:21:47.511028 00: 0007 8000
317 23:21:47.511151
318 23:21:47.511249 01: 0000 0000
319 23:21:47.511347
320 23:21:47.514485 BP: 0C00 0209 [0000]
321 23:21:47.514606
322 23:21:47.514708 G0: 1182 0000
323 23:21:47.514804
324 23:21:47.517816 EC: 0000 0021 [4000]
325 23:21:47.517934
326 23:21:47.518033 S7: 0000 0000 [0000]
327 23:21:47.518128
328 23:21:47.521647 CC: 0000 0000 [0001]
329 23:21:47.521770
330 23:21:47.521868 T0: 0000 0040 [010F]
331 23:21:47.521969
332 23:21:47.522063 Jump to BL
333 23:21:47.522156
334 23:21:47.548201
335 23:21:47.548382
336 23:21:47.548454
337 23:21:47.555635 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:21:47.559254 ARM64: Exception handlers installed.
339 23:21:47.563063 ARM64: Testing exception
340 23:21:47.566497 ARM64: Done test exception
341 23:21:47.572851 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:21:47.583060 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:21:47.590182 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:21:47.600331 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:21:47.606817 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:21:47.613805 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:21:47.624861 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:21:47.631667 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:21:47.650863 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:21:47.654304 WDT: Last reset was cold boot
351 23:21:47.657544 SPI1(PAD0) initialized at 2873684 Hz
352 23:21:47.661068 SPI5(PAD0) initialized at 992727 Hz
353 23:21:47.664304 VBOOT: Loading verstage.
354 23:21:47.670796 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:21:47.675759 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:21:47.678912 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:21:47.682177 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:21:47.689081 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:21:47.695566 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:21:47.706146 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 23:21:47.706333
362 23:21:47.706440
363 23:21:47.716688 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:21:47.720155 ARM64: Exception handlers installed.
365 23:21:47.720315 ARM64: Testing exception
366 23:21:47.723239 ARM64: Done test exception
367 23:21:47.726721 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:21:47.733473 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:21:47.746967 Probing TPM: . done!
370 23:21:47.747166 TPM ready after 0 ms
371 23:21:47.753923 Connected to device vid:did:rid of 1ae0:0028:00
372 23:21:47.760847 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 23:21:47.820790 Initialized TPM device CR50 revision 0
374 23:21:47.832325 tlcl_send_startup: Startup return code is 0
375 23:21:47.832512 TPM: setup succeeded
376 23:21:47.843734 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:21:47.852703 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:21:47.864949 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:21:47.875353 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:21:47.879030 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:21:47.882304 in-header: 03 07 00 00 08 00 00 00
382 23:21:47.886057 in-data: aa e4 47 04 13 02 00 00
383 23:21:47.886189 Chrome EC: UHEPI supported
384 23:21:47.893941 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:21:47.897284 in-header: 03 95 00 00 08 00 00 00
386 23:21:47.901304 in-data: 18 20 20 08 00 00 00 00
387 23:21:47.901452 Phase 1
388 23:21:47.904521 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:21:47.912220 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:21:47.919443 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:21:47.919590 Recovery requested (1009000e)
392 23:21:47.931408 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:21:47.935424 tlcl_extend: response is 0
394 23:21:47.944196 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:21:47.949859 tlcl_extend: response is 0
396 23:21:47.957160 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:21:47.976522 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 23:21:47.983504 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:21:47.983644
400 23:21:47.983742
401 23:21:47.993215 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:21:47.996910 ARM64: Exception handlers installed.
403 23:21:47.999901 ARM64: Testing exception
404 23:21:48.000037 ARM64: Done test exception
405 23:21:48.022477 pmic_efuse_setting: Set efuses in 11 msecs
406 23:21:48.025656 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:21:48.032336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:21:48.035896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:21:48.039736 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:21:48.046767 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:21:48.050410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:21:48.054243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:21:48.062152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:21:48.065798 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:21:48.069374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:21:48.073277 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:21:48.080525 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:21:48.084526 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:21:48.088416 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:21:48.095670 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:21:48.099484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:21:48.106592 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:21:48.110214 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:21:48.118124 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:21:48.121356 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:21:48.128799 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:21:48.132392 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:21:48.140192 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:21:48.143608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:21:48.151357 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:21:48.154797 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:21:48.162049 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:21:48.165235 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:21:48.172683 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:21:48.176313 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:21:48.179745 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:21:48.187504 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:21:48.190927 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:21:48.194575 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:21:48.202006 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:21:48.205594 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:21:48.213149 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:21:48.216935 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:21:48.220560 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:21:48.224169 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:21:48.231925 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:21:48.235241 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:21:48.238724 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:21:48.242141 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:21:48.249553 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:21:48.253248 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:21:48.257044 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:21:48.260929 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:21:48.264427 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:21:48.268242 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:21:48.272040 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:21:48.275457 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:21:48.286784 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:21:48.294437 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:21:48.297910 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:21:48.305288 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:21:48.316365 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:21:48.320433 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:21:48.324213 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:21:48.327607 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:21:48.335515 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x23
467 23:21:48.339210 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:21:48.347923 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 23:21:48.351355 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:21:48.359825 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 23:21:48.369414 [RTC]rtc_get_frequency_meter,154: input=23, output=941
472 23:21:48.379034 [RTC]rtc_get_frequency_meter,154: input=19, output=849
473 23:21:48.388380 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 23:21:48.397641 [RTC]rtc_get_frequency_meter,154: input=16, output=780
475 23:21:48.407845 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 23:21:48.417148 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 23:21:48.420952 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 23:21:48.424743 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 23:21:48.432241 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:21:48.435678 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 23:21:48.439398 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:21:48.442958 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 23:21:48.446793 ADC[4]: Raw value=906203 ID=7
484 23:21:48.446932 ADC[3]: Raw value=213441 ID=1
485 23:21:48.450708 RAM Code: 0x71
486 23:21:48.454582 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:21:48.458706 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:21:48.469428 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 23:21:48.473500 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 23:21:48.476928 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:21:48.482224 in-header: 03 07 00 00 08 00 00 00
492 23:21:48.486267 in-data: aa e4 47 04 13 02 00 00
493 23:21:48.489819 Chrome EC: UHEPI supported
494 23:21:48.493145 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:21:48.497222 in-header: 03 95 00 00 08 00 00 00
496 23:21:48.500723 in-data: 18 20 20 08 00 00 00 00
497 23:21:48.504610 MRC: failed to locate region type 0.
498 23:21:48.512061 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:21:48.516119 DRAM-K: Running full calibration
500 23:21:48.519608 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 23:21:48.523156 header.status = 0x0
502 23:21:48.527491 header.version = 0x6 (expected: 0x6)
503 23:21:48.530764 header.size = 0xd00 (expected: 0xd00)
504 23:21:48.530925 header.flags = 0x0
505 23:21:48.538115 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:21:48.555463 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 23:21:48.563121 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:21:48.563311 dram_init: ddr_geometry: 2
509 23:21:48.566992 [EMI] MDL number = 2
510 23:21:48.570213 [EMI] Get MDL freq = 0
511 23:21:48.570373 dram_init: ddr_type: 0
512 23:21:48.574300 is_discrete_lpddr4: 1
513 23:21:48.574463 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:21:48.578009
515 23:21:48.578176
516 23:21:48.578303 [Bian_co] ETT version 0.0.0.1
517 23:21:48.581960 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 23:21:48.585281
519 23:21:48.589007 dramc_set_vcore_voltage set vcore to 650000
520 23:21:48.589166 Read voltage for 800, 4
521 23:21:48.592256 Vio18 = 0
522 23:21:48.592437 Vcore = 650000
523 23:21:48.592563 Vdram = 0
524 23:21:48.592670 Vddq = 0
525 23:21:48.596265 Vmddr = 0
526 23:21:48.596431 dram_init: config_dvfs: 1
527 23:21:48.603606 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:21:48.607568 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:21:48.611331 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 23:21:48.615255 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 23:21:48.618715 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 23:21:48.622333 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 23:21:48.626263 MEM_TYPE=3, freq_sel=18
534 23:21:48.629270 sv_algorithm_assistance_LP4_1600
535 23:21:48.632582 ============ PULL DRAM RESETB DOWN ============
536 23:21:48.636030 ========== PULL DRAM RESETB DOWN end =========
537 23:21:48.642724 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:21:48.642872 ===================================
539 23:21:48.646254 LPDDR4 DRAM CONFIGURATION
540 23:21:48.650047 ===================================
541 23:21:48.653778 EX_ROW_EN[0] = 0x0
542 23:21:48.653932 EX_ROW_EN[1] = 0x0
543 23:21:48.657164 LP4Y_EN = 0x0
544 23:21:48.657290 WORK_FSP = 0x0
545 23:21:48.661102 WL = 0x2
546 23:21:48.661283 RL = 0x2
547 23:21:48.661410 BL = 0x2
548 23:21:48.664475 RPST = 0x0
549 23:21:48.664628 RD_PRE = 0x0
550 23:21:48.668359 WR_PRE = 0x1
551 23:21:48.668522 WR_PST = 0x0
552 23:21:48.671470 DBI_WR = 0x0
553 23:21:48.671583 DBI_RD = 0x0
554 23:21:48.675085 OTF = 0x1
555 23:21:48.678300 ===================================
556 23:21:48.681467 ===================================
557 23:21:48.681575 ANA top config
558 23:21:48.685035 ===================================
559 23:21:48.688426 DLL_ASYNC_EN = 0
560 23:21:48.691553 ALL_SLAVE_EN = 1
561 23:21:48.695289 NEW_RANK_MODE = 1
562 23:21:48.695430 DLL_IDLE_MODE = 1
563 23:21:48.698229 LP45_APHY_COMB_EN = 1
564 23:21:48.701544 TX_ODT_DIS = 1
565 23:21:48.705329 NEW_8X_MODE = 1
566 23:21:48.709216 ===================================
567 23:21:48.709372 ===================================
568 23:21:48.712640 data_rate = 1600
569 23:21:48.715978 CKR = 1
570 23:21:48.719411 DQ_P2S_RATIO = 8
571 23:21:48.722625 ===================================
572 23:21:48.725656 CA_P2S_RATIO = 8
573 23:21:48.728979 DQ_CA_OPEN = 0
574 23:21:48.729106 DQ_SEMI_OPEN = 0
575 23:21:48.732659 CA_SEMI_OPEN = 0
576 23:21:48.735566 CA_FULL_RATE = 0
577 23:21:48.739017 DQ_CKDIV4_EN = 1
578 23:21:48.742355 CA_CKDIV4_EN = 1
579 23:21:48.745579 CA_PREDIV_EN = 0
580 23:21:48.745722 PH8_DLY = 0
581 23:21:48.749089 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:21:48.752541 DQ_AAMCK_DIV = 4
583 23:21:48.755897 CA_AAMCK_DIV = 4
584 23:21:48.759204 CA_ADMCK_DIV = 4
585 23:21:48.759339 DQ_TRACK_CA_EN = 0
586 23:21:48.762539 CA_PICK = 800
587 23:21:48.765903 CA_MCKIO = 800
588 23:21:48.769832 MCKIO_SEMI = 0
589 23:21:48.773315 PLL_FREQ = 3068
590 23:21:48.777055 DQ_UI_PI_RATIO = 32
591 23:21:48.777201 CA_UI_PI_RATIO = 0
592 23:21:48.780782 ===================================
593 23:21:48.784464 ===================================
594 23:21:48.787881 memory_type:LPDDR4
595 23:21:48.788027 GP_NUM : 10
596 23:21:48.792325 SRAM_EN : 1
597 23:21:48.792477 MD32_EN : 0
598 23:21:48.796222 ===================================
599 23:21:48.799760 [ANA_INIT] >>>>>>>>>>>>>>
600 23:21:48.803547 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:21:48.806884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:21:48.807047 ===================================
603 23:21:48.810159 data_rate = 1600,PCW = 0X7600
604 23:21:48.813460 ===================================
605 23:21:48.816752 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:21:48.823199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:21:48.830234 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:21:48.833526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:21:48.836601 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:21:48.839992 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:21:48.843385 [ANA_INIT] flow start
612 23:21:48.843531 [ANA_INIT] PLL >>>>>>>>
613 23:21:48.846730 [ANA_INIT] PLL <<<<<<<<
614 23:21:48.850032 [ANA_INIT] MIDPI >>>>>>>>
615 23:21:48.853260 [ANA_INIT] MIDPI <<<<<<<<
616 23:21:48.853399 [ANA_INIT] DLL >>>>>>>>
617 23:21:48.856453 [ANA_INIT] flow end
618 23:21:48.859879 ============ LP4 DIFF to SE enter ============
619 23:21:48.863369 ============ LP4 DIFF to SE exit ============
620 23:21:48.866524 [ANA_INIT] <<<<<<<<<<<<<
621 23:21:48.870029 [Flow] Enable top DCM control >>>>>
622 23:21:48.873515 [Flow] Enable top DCM control <<<<<
623 23:21:48.876769 Enable DLL master slave shuffle
624 23:21:48.880113 ==============================================================
625 23:21:48.883489 Gating Mode config
626 23:21:48.890161 ==============================================================
627 23:21:48.890342 Config description:
628 23:21:48.899991 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:21:48.906780 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:21:48.910423 SELPH_MODE 0: By rank 1: By Phase
631 23:21:48.917021 ==============================================================
632 23:21:48.920383 GAT_TRACK_EN = 1
633 23:21:48.923659 RX_GATING_MODE = 2
634 23:21:48.927024 RX_GATING_TRACK_MODE = 2
635 23:21:48.930190 SELPH_MODE = 1
636 23:21:48.933706 PICG_EARLY_EN = 1
637 23:21:48.933855 VALID_LAT_VALUE = 1
638 23:21:48.940572 ==============================================================
639 23:21:48.943779 Enter into Gating configuration >>>>
640 23:21:48.947050 Exit from Gating configuration <<<<
641 23:21:48.950286 Enter into DVFS_PRE_config >>>>>
642 23:21:48.960677 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:21:48.963867 Exit from DVFS_PRE_config <<<<<
644 23:21:48.967060 Enter into PICG configuration >>>>
645 23:21:48.970633 Exit from PICG configuration <<<<
646 23:21:48.973990 [RX_INPUT] configuration >>>>>
647 23:21:48.977169 [RX_INPUT] configuration <<<<<
648 23:21:48.980585 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:21:48.987434 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:21:48.993827 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:21:49.000312 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:21:49.007325 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:21:49.010724 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:21:49.017286 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:21:49.020630 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:21:49.024079 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:21:49.027371 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:21:49.033772 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:21:49.037115 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:21:49.040330 ===================================
661 23:21:49.043742 LPDDR4 DRAM CONFIGURATION
662 23:21:49.047326 ===================================
663 23:21:49.047490 EX_ROW_EN[0] = 0x0
664 23:21:49.050323 EX_ROW_EN[1] = 0x0
665 23:21:49.050453 LP4Y_EN = 0x0
666 23:21:49.053954 WORK_FSP = 0x0
667 23:21:49.054097 WL = 0x2
668 23:21:49.057238 RL = 0x2
669 23:21:49.057389 BL = 0x2
670 23:21:49.060361 RPST = 0x0
671 23:21:49.060483 RD_PRE = 0x0
672 23:21:49.063832 WR_PRE = 0x1
673 23:21:49.063947 WR_PST = 0x0
674 23:21:49.067249 DBI_WR = 0x0
675 23:21:49.067393 DBI_RD = 0x0
676 23:21:49.070600 OTF = 0x1
677 23:21:49.073900 ===================================
678 23:21:49.077500 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:21:49.080488 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:21:49.087400 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:21:49.090357 ===================================
682 23:21:49.090460 LPDDR4 DRAM CONFIGURATION
683 23:21:49.093667 ===================================
684 23:21:49.097487 EX_ROW_EN[0] = 0x10
685 23:21:49.100456 EX_ROW_EN[1] = 0x0
686 23:21:49.100551 LP4Y_EN = 0x0
687 23:21:49.103938 WORK_FSP = 0x0
688 23:21:49.104044 WL = 0x2
689 23:21:49.107326 RL = 0x2
690 23:21:49.107471 BL = 0x2
691 23:21:49.110748 RPST = 0x0
692 23:21:49.110866 RD_PRE = 0x0
693 23:21:49.113876 WR_PRE = 0x1
694 23:21:49.113976 WR_PST = 0x0
695 23:21:49.117249 DBI_WR = 0x0
696 23:21:49.117363 DBI_RD = 0x0
697 23:21:49.120637 OTF = 0x1
698 23:21:49.123947 ===================================
699 23:21:49.130849 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:21:49.133803 nWR fixed to 40
701 23:21:49.133925 [ModeRegInit_LP4] CH0 RK0
702 23:21:49.137346 [ModeRegInit_LP4] CH0 RK1
703 23:21:49.140646 [ModeRegInit_LP4] CH1 RK0
704 23:21:49.143955 [ModeRegInit_LP4] CH1 RK1
705 23:21:49.144080 match AC timing 13
706 23:21:49.147334 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 23:21:49.150555 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:21:49.157438 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:21:49.160582 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:21:49.167379 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:21:49.167546 [EMI DOE] emi_dcm 0
712 23:21:49.170622 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:21:49.174171 ==
714 23:21:49.177295 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:21:49.180705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 23:21:49.180834 ==
717 23:21:49.183993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:21:49.190774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:21:49.200534 [CA 0] Center 36 (6~67) winsize 62
720 23:21:49.204250 [CA 1] Center 36 (6~67) winsize 62
721 23:21:49.207306 [CA 2] Center 34 (4~65) winsize 62
722 23:21:49.210879 [CA 3] Center 33 (3~64) winsize 62
723 23:21:49.213903 [CA 4] Center 32 (2~63) winsize 62
724 23:21:49.217342 [CA 5] Center 32 (2~62) winsize 61
725 23:21:49.217447
726 23:21:49.220803 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 23:21:49.220936
728 23:21:49.224236 [CATrainingPosCal] consider 1 rank data
729 23:21:49.227455 u2DelayCellTimex100 = 270/100 ps
730 23:21:49.230974 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 23:21:49.234032 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 23:21:49.240951 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 23:21:49.243985 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 23:21:49.247468 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
735 23:21:49.251082 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 23:21:49.251242
737 23:21:49.254235 CA PerBit enable=1, Macro0, CA PI delay=32
738 23:21:49.254358
739 23:21:49.257533 [CBTSetCACLKResult] CA Dly = 32
740 23:21:49.257656 CS Dly: 4 (0~35)
741 23:21:49.257765 ==
742 23:21:49.260830 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:21:49.267794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 23:21:49.267943 ==
745 23:21:49.271061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:21:49.277375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:21:49.286665 [CA 0] Center 36 (6~67) winsize 62
748 23:21:49.290289 [CA 1] Center 36 (6~67) winsize 62
749 23:21:49.293566 [CA 2] Center 34 (3~65) winsize 63
750 23:21:49.296979 [CA 3] Center 33 (3~64) winsize 62
751 23:21:49.300230 [CA 4] Center 32 (2~63) winsize 62
752 23:21:49.303439 [CA 5] Center 32 (2~63) winsize 62
753 23:21:49.303580
754 23:21:49.307033 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 23:21:49.307156
756 23:21:49.310619 [CATrainingPosCal] consider 2 rank data
757 23:21:49.313789 u2DelayCellTimex100 = 270/100 ps
758 23:21:49.317373 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 23:21:49.320368 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 23:21:49.323816 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 23:21:49.330681 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 23:21:49.333929 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
763 23:21:49.337421 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 23:21:49.337569
765 23:21:49.340379 CA PerBit enable=1, Macro0, CA PI delay=32
766 23:21:49.340532
767 23:21:49.343872 [CBTSetCACLKResult] CA Dly = 32
768 23:21:49.344034 CS Dly: 5 (0~37)
769 23:21:49.344152
770 23:21:49.347352 ----->DramcWriteLeveling(PI) begin...
771 23:21:49.347520 ==
772 23:21:49.351197 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:21:49.354960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 23:21:49.355118 ==
775 23:21:49.358531 Write leveling (Byte 0): 35 => 35
776 23:21:49.362343 Write leveling (Byte 1): 30 => 30
777 23:21:49.365600 DramcWriteLeveling(PI) end<-----
778 23:21:49.365745
779 23:21:49.365866 ==
780 23:21:49.369009 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:21:49.372387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:21:49.372525 ==
783 23:21:49.375825 [Gating] SW mode calibration
784 23:21:49.383011 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:21:49.389535 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:21:49.393116 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:21:49.396481 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 23:21:49.402932 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 23:21:49.406254 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 23:21:49.409672 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:21:49.416273 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:21:49.419567 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:21:49.423042 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:21:49.426377 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:21:49.433075 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:21:49.436338 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:21:49.439436 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:21:49.446143 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:21:49.449567 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:21:49.452998 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:21:49.459663 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:21:49.462825 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 23:21:49.466279 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 23:21:49.472705 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 23:21:49.476163 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 23:21:49.479596 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:21:49.486206 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:21:49.489709 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:21:49.493014 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:21:49.499480 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:21:49.502836 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:21:49.506273 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
813 23:21:49.509796 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
814 23:21:49.516191 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:21:49.519520 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:21:49.523093 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:21:49.529918 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:21:49.533353 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:21:49.536422 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
820 23:21:49.543201 0 10 8 | B1->B0 | 3333 2626 | 1 0 | (1 1) (0 0)
821 23:21:49.546434 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 23:21:49.549697 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:21:49.556552 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:21:49.559965 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:21:49.562942 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:21:49.569720 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:21:49.573386 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:21:49.576388 0 11 8 | B1->B0 | 2c2c 4040 | 0 0 | (0 0) (0 0)
829 23:21:49.583191 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
830 23:21:49.586587 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:21:49.589731 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:21:49.596364 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:21:49.600011 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:21:49.603136 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:21:49.606480 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 23:21:49.613230 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 23:21:49.616271 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 23:21:49.619672 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:21:49.626380 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:21:49.629800 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:21:49.633245 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:21:49.640230 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:21:49.643238 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:21:49.646809 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:21:49.653611 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:21:49.656586 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:21:49.660109 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:21:49.666862 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:21:49.670031 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:21:49.673577 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:21:49.676867 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 23:21:49.683279 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 23:21:49.686652 Total UI for P1: 0, mck2ui 16
854 23:21:49.689920 best dqsien dly found for B0: ( 0, 14, 4)
855 23:21:49.693370 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 23:21:49.696862 Total UI for P1: 0, mck2ui 16
857 23:21:49.700831 best dqsien dly found for B1: ( 0, 14, 8)
858 23:21:49.704263 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 23:21:49.707469 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 23:21:49.707604
861 23:21:49.710904 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 23:21:49.714220 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 23:21:49.717706 [Gating] SW calibration Done
864 23:21:49.717869 ==
865 23:21:49.721227 Dram Type= 6, Freq= 0, CH_0, rank 0
866 23:21:49.724192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 23:21:49.724345 ==
868 23:21:49.727567 RX Vref Scan: 0
869 23:21:49.727701
870 23:21:49.727801 RX Vref 0 -> 0, step: 1
871 23:21:49.727867
872 23:21:49.730919 RX Delay -130 -> 252, step: 16
873 23:21:49.737711 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 23:21:49.741080 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 23:21:49.744096 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
876 23:21:49.747691 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
877 23:21:49.750932 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 23:21:49.754440 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 23:21:49.760969 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 23:21:49.764422 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 23:21:49.767485 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 23:21:49.771069 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
883 23:21:49.774440 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
884 23:21:49.780920 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 23:21:49.784382 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
886 23:21:49.787644 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 23:21:49.790750 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 23:21:49.797455 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
889 23:21:49.797617 ==
890 23:21:49.800851 Dram Type= 6, Freq= 0, CH_0, rank 0
891 23:21:49.804530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 23:21:49.804661 ==
893 23:21:49.804767 DQS Delay:
894 23:21:49.807623 DQS0 = 0, DQS1 = 0
895 23:21:49.807734 DQM Delay:
896 23:21:49.811140 DQM0 = 92, DQM1 = 86
897 23:21:49.811237 DQ Delay:
898 23:21:49.814476 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
899 23:21:49.817405 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 23:21:49.820957 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
901 23:21:49.824311 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 23:21:49.824465
903 23:21:49.824582
904 23:21:49.824700 ==
905 23:21:49.827436 Dram Type= 6, Freq= 0, CH_0, rank 0
906 23:21:49.830832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 23:21:49.830985 ==
908 23:21:49.831103
909 23:21:49.831227
910 23:21:49.834277 TX Vref Scan disable
911 23:21:49.837880 == TX Byte 0 ==
912 23:21:49.841281 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
913 23:21:49.844184 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
914 23:21:49.847620 == TX Byte 1 ==
915 23:21:49.851039 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 23:21:49.854242 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 23:21:49.854390 ==
918 23:21:49.857653 Dram Type= 6, Freq= 0, CH_0, rank 0
919 23:21:49.861241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 23:21:49.864162 ==
921 23:21:49.876221 TX Vref=22, minBit 8, minWin=27, winSum=448
922 23:21:49.879523 TX Vref=24, minBit 10, minWin=27, winSum=452
923 23:21:49.883083 TX Vref=26, minBit 5, minWin=28, winSum=455
924 23:21:49.886152 TX Vref=28, minBit 8, minWin=28, winSum=458
925 23:21:49.889831 TX Vref=30, minBit 5, minWin=28, winSum=458
926 23:21:49.896429 TX Vref=32, minBit 10, minWin=27, winSum=450
927 23:21:49.899628 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28
928 23:21:49.899728
929 23:21:49.903199 Final TX Range 1 Vref 28
930 23:21:49.903305
931 23:21:49.903375 ==
932 23:21:49.906402 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:21:49.909745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:21:49.909899 ==
935 23:21:49.910011
936 23:21:49.912867
937 23:21:49.912989 TX Vref Scan disable
938 23:21:49.916415 == TX Byte 0 ==
939 23:21:49.919802 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
940 23:21:49.923221 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
941 23:21:49.926627 == TX Byte 1 ==
942 23:21:49.930091 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 23:21:49.932930 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 23:21:49.936307
945 23:21:49.936444 [DATLAT]
946 23:21:49.936558 Freq=800, CH0 RK0
947 23:21:49.936657
948 23:21:49.939525 DATLAT Default: 0xa
949 23:21:49.939635 0, 0xFFFF, sum = 0
950 23:21:49.943006 1, 0xFFFF, sum = 0
951 23:21:49.943097 2, 0xFFFF, sum = 0
952 23:21:49.946437 3, 0xFFFF, sum = 0
953 23:21:49.946567 4, 0xFFFF, sum = 0
954 23:21:49.949583 5, 0xFFFF, sum = 0
955 23:21:49.953001 6, 0xFFFF, sum = 0
956 23:21:49.953128 7, 0xFFFF, sum = 0
957 23:21:49.956378 8, 0xFFFF, sum = 0
958 23:21:49.956543 9, 0x0, sum = 1
959 23:21:49.956661 10, 0x0, sum = 2
960 23:21:49.959822 11, 0x0, sum = 3
961 23:21:49.959936 12, 0x0, sum = 4
962 23:21:49.963223 best_step = 10
963 23:21:49.963338
964 23:21:49.963425 ==
965 23:21:49.966235 Dram Type= 6, Freq= 0, CH_0, rank 0
966 23:21:49.969589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 23:21:49.969687 ==
968 23:21:49.972842 RX Vref Scan: 1
969 23:21:49.972981
970 23:21:49.975919 Set Vref Range= 32 -> 127
971 23:21:49.976037
972 23:21:49.976132 RX Vref 32 -> 127, step: 1
973 23:21:49.976226
974 23:21:49.979445 RX Delay -79 -> 252, step: 8
975 23:21:49.979560
976 23:21:49.982761 Set Vref, RX VrefLevel [Byte0]: 32
977 23:21:49.986011 [Byte1]: 32
978 23:21:49.986132
979 23:21:49.989566 Set Vref, RX VrefLevel [Byte0]: 33
980 23:21:49.992910 [Byte1]: 33
981 23:21:49.996873
982 23:21:49.997000 Set Vref, RX VrefLevel [Byte0]: 34
983 23:21:49.999921 [Byte1]: 34
984 23:21:50.004296
985 23:21:50.004398 Set Vref, RX VrefLevel [Byte0]: 35
986 23:21:50.007619 [Byte1]: 35
987 23:21:50.012278
988 23:21:50.012424 Set Vref, RX VrefLevel [Byte0]: 36
989 23:21:50.015443 [Byte1]: 36
990 23:21:50.019894
991 23:21:50.020025 Set Vref, RX VrefLevel [Byte0]: 37
992 23:21:50.023321 [Byte1]: 37
993 23:21:50.027460
994 23:21:50.027611 Set Vref, RX VrefLevel [Byte0]: 38
995 23:21:50.030686 [Byte1]: 38
996 23:21:50.034786
997 23:21:50.034945 Set Vref, RX VrefLevel [Byte0]: 39
998 23:21:50.038472 [Byte1]: 39
999 23:21:50.042182
1000 23:21:50.042286 Set Vref, RX VrefLevel [Byte0]: 40
1001 23:21:50.045962 [Byte1]: 40
1002 23:21:50.049751
1003 23:21:50.049890 Set Vref, RX VrefLevel [Byte0]: 41
1004 23:21:50.053022 [Byte1]: 41
1005 23:21:50.057342
1006 23:21:50.057505 Set Vref, RX VrefLevel [Byte0]: 42
1007 23:21:50.060189 [Byte1]: 42
1008 23:21:50.064650
1009 23:21:50.064829 Set Vref, RX VrefLevel [Byte0]: 43
1010 23:21:50.067847 [Byte1]: 43
1011 23:21:50.072246
1012 23:21:50.072425 Set Vref, RX VrefLevel [Byte0]: 44
1013 23:21:50.075465 [Byte1]: 44
1014 23:21:50.079760
1015 23:21:50.079932 Set Vref, RX VrefLevel [Byte0]: 45
1016 23:21:50.082773 [Byte1]: 45
1017 23:21:50.087480
1018 23:21:50.087591 Set Vref, RX VrefLevel [Byte0]: 46
1019 23:21:50.090410 [Byte1]: 46
1020 23:21:50.094774
1021 23:21:50.094910 Set Vref, RX VrefLevel [Byte0]: 47
1022 23:21:50.098220 [Byte1]: 47
1023 23:21:50.102579
1024 23:21:50.102691 Set Vref, RX VrefLevel [Byte0]: 48
1025 23:21:50.105514 [Byte1]: 48
1026 23:21:50.109904
1027 23:21:50.110000 Set Vref, RX VrefLevel [Byte0]: 49
1028 23:21:50.113463 [Byte1]: 49
1029 23:21:50.117348
1030 23:21:50.117511 Set Vref, RX VrefLevel [Byte0]: 50
1031 23:21:50.120645 [Byte1]: 50
1032 23:21:50.124887
1033 23:21:50.124996 Set Vref, RX VrefLevel [Byte0]: 51
1034 23:21:50.128147 [Byte1]: 51
1035 23:21:50.132841
1036 23:21:50.132962 Set Vref, RX VrefLevel [Byte0]: 52
1037 23:21:50.135835 [Byte1]: 52
1038 23:21:50.140234
1039 23:21:50.140382 Set Vref, RX VrefLevel [Byte0]: 53
1040 23:21:50.143509 [Byte1]: 53
1041 23:21:50.147783
1042 23:21:50.147922 Set Vref, RX VrefLevel [Byte0]: 54
1043 23:21:50.150768 [Byte1]: 54
1044 23:21:50.155287
1045 23:21:50.155431 Set Vref, RX VrefLevel [Byte0]: 55
1046 23:21:50.158527 [Byte1]: 55
1047 23:21:50.162609
1048 23:21:50.162761 Set Vref, RX VrefLevel [Byte0]: 56
1049 23:21:50.166243 [Byte1]: 56
1050 23:21:50.170253
1051 23:21:50.170393 Set Vref, RX VrefLevel [Byte0]: 57
1052 23:21:50.173760 [Byte1]: 57
1053 23:21:50.177662
1054 23:21:50.177799 Set Vref, RX VrefLevel [Byte0]: 58
1055 23:21:50.181049 [Byte1]: 58
1056 23:21:50.185352
1057 23:21:50.185453 Set Vref, RX VrefLevel [Byte0]: 59
1058 23:21:50.188752 [Byte1]: 59
1059 23:21:50.192982
1060 23:21:50.193093 Set Vref, RX VrefLevel [Byte0]: 60
1061 23:21:50.196374 [Byte1]: 60
1062 23:21:50.200442
1063 23:21:50.200585 Set Vref, RX VrefLevel [Byte0]: 61
1064 23:21:50.203893 [Byte1]: 61
1065 23:21:50.208194
1066 23:21:50.208337 Set Vref, RX VrefLevel [Byte0]: 62
1067 23:21:50.211157 [Byte1]: 62
1068 23:21:50.215541
1069 23:21:50.215674 Set Vref, RX VrefLevel [Byte0]: 63
1070 23:21:50.218917 [Byte1]: 63
1071 23:21:50.223282
1072 23:21:50.223409 Set Vref, RX VrefLevel [Byte0]: 64
1073 23:21:50.226611 [Byte1]: 64
1074 23:21:50.230733
1075 23:21:50.230900 Set Vref, RX VrefLevel [Byte0]: 65
1076 23:21:50.234105 [Byte1]: 65
1077 23:21:50.238186
1078 23:21:50.238323 Set Vref, RX VrefLevel [Byte0]: 66
1079 23:21:50.241689 [Byte1]: 66
1080 23:21:50.245951
1081 23:21:50.246098 Set Vref, RX VrefLevel [Byte0]: 67
1082 23:21:50.249072 [Byte1]: 67
1083 23:21:50.253391
1084 23:21:50.253501 Set Vref, RX VrefLevel [Byte0]: 68
1085 23:21:50.256839 [Byte1]: 68
1086 23:21:50.260778
1087 23:21:50.260893 Set Vref, RX VrefLevel [Byte0]: 69
1088 23:21:50.264112 [Byte1]: 69
1089 23:21:50.268327
1090 23:21:50.268436 Set Vref, RX VrefLevel [Byte0]: 70
1091 23:21:50.271681 [Byte1]: 70
1092 23:21:50.275796
1093 23:21:50.275919 Set Vref, RX VrefLevel [Byte0]: 71
1094 23:21:50.279287 [Byte1]: 71
1095 23:21:50.283648
1096 23:21:50.283783 Set Vref, RX VrefLevel [Byte0]: 72
1097 23:21:50.286872 [Byte1]: 72
1098 23:21:50.291292
1099 23:21:50.291419 Set Vref, RX VrefLevel [Byte0]: 73
1100 23:21:50.294309 [Byte1]: 73
1101 23:21:50.298518
1102 23:21:50.298687 Set Vref, RX VrefLevel [Byte0]: 74
1103 23:21:50.301932 [Byte1]: 74
1104 23:21:50.306180
1105 23:21:50.306287 Set Vref, RX VrefLevel [Byte0]: 75
1106 23:21:50.309434 [Byte1]: 75
1107 23:21:50.313859
1108 23:21:50.313976 Set Vref, RX VrefLevel [Byte0]: 76
1109 23:21:50.317231 [Byte1]: 76
1110 23:21:50.321038
1111 23:21:50.321180 Set Vref, RX VrefLevel [Byte0]: 77
1112 23:21:50.324484 [Byte1]: 77
1113 23:21:50.328925
1114 23:21:50.329033 Set Vref, RX VrefLevel [Byte0]: 78
1115 23:21:50.331925 [Byte1]: 78
1116 23:21:50.336427
1117 23:21:50.336593 Set Vref, RX VrefLevel [Byte0]: 79
1118 23:21:50.339652 [Byte1]: 79
1119 23:21:50.343854
1120 23:21:50.343995 Final RX Vref Byte 0 = 51 to rank0
1121 23:21:50.347183 Final RX Vref Byte 1 = 59 to rank0
1122 23:21:50.350648 Final RX Vref Byte 0 = 51 to rank1
1123 23:21:50.353807 Final RX Vref Byte 1 = 59 to rank1==
1124 23:21:50.357178 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 23:21:50.363993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 23:21:50.364119 ==
1127 23:21:50.364190 DQS Delay:
1128 23:21:50.364253 DQS0 = 0, DQS1 = 0
1129 23:21:50.367400 DQM Delay:
1130 23:21:50.367495 DQM0 = 91, DQM1 = 86
1131 23:21:50.370754 DQ Delay:
1132 23:21:50.374192 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1133 23:21:50.377153 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1134 23:21:50.380477 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
1135 23:21:50.383877 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1136 23:21:50.383998
1137 23:21:50.384093
1138 23:21:50.390467 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1139 23:21:50.393841 CH0 RK0: MR19=606, MR18=4B41
1140 23:21:50.400662 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1141 23:21:50.400829
1142 23:21:50.403778 ----->DramcWriteLeveling(PI) begin...
1143 23:21:50.403863 ==
1144 23:21:50.407224 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 23:21:50.410455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 23:21:50.410545 ==
1147 23:21:50.413817 Write leveling (Byte 0): 33 => 33
1148 23:21:50.417255 Write leveling (Byte 1): 31 => 31
1149 23:21:50.461476 DramcWriteLeveling(PI) end<-----
1150 23:21:50.461681
1151 23:21:50.461802 ==
1152 23:21:50.461919 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 23:21:50.462231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 23:21:50.462352 ==
1155 23:21:50.462466 [Gating] SW mode calibration
1156 23:21:50.462579 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 23:21:50.462694 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 23:21:50.462805 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 23:21:50.462918 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1160 23:21:50.463030 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1161 23:21:50.463139 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:21:50.491838 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:21:50.492264 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:21:50.492402 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:21:50.492524 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:21:50.492632 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:21:50.492746 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:21:50.495516 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:21:50.495614 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:21:50.498977 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:21:50.505680 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:21:50.508919 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:21:50.511961 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:21:50.518754 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:21:50.521950 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1176 23:21:50.525485 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1177 23:21:50.532193 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:21:50.535553 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 23:21:50.538905 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 23:21:50.545339 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 23:21:50.548783 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 23:21:50.552224 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 23:21:50.558728 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 23:21:50.562169 0 9 8 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
1185 23:21:50.565166 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 23:21:50.572019 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 23:21:50.575545 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 23:21:50.578716 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 23:21:50.582030 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 23:21:50.588657 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 23:21:50.592888 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1192 23:21:50.596308 0 10 8 | B1->B0 | 2b2b 2b2b | 0 0 | (1 0) (0 1)
1193 23:21:50.599700 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 23:21:50.607033 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 23:21:50.610339 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 23:21:50.613553 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:21:50.620611 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 23:21:50.624483 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 23:21:50.627801 0 11 4 | B1->B0 | 2a2a 2424 | 0 0 | (1 1) (0 0)
1200 23:21:50.631248 0 11 8 | B1->B0 | 3c3c 4040 | 0 1 | (0 0) (0 0)
1201 23:21:50.637658 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 23:21:50.641067 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 23:21:50.644642 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 23:21:50.651335 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 23:21:50.654330 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 23:21:50.657723 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 23:21:50.661024 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1208 23:21:50.667762 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1209 23:21:50.671057 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:21:50.674407 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:21:50.681303 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:21:50.684249 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:21:50.687702 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:21:50.694571 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:21:50.697958 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:21:50.701230 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:21:50.707604 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 23:21:50.711121 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 23:21:50.714660 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 23:21:50.721159 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 23:21:50.724414 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 23:21:50.727999 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 23:21:50.734743 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 23:21:50.738009 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1225 23:21:50.741054 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 23:21:50.744541 Total UI for P1: 0, mck2ui 16
1227 23:21:50.747944 best dqsien dly found for B0: ( 0, 14, 8)
1228 23:21:50.751194 Total UI for P1: 0, mck2ui 16
1229 23:21:50.754730 best dqsien dly found for B1: ( 0, 14, 8)
1230 23:21:50.757930 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1231 23:21:50.761165 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1232 23:21:50.761325
1233 23:21:50.764553 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1234 23:21:50.767938 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1235 23:21:50.771210 [Gating] SW calibration Done
1236 23:21:50.771351 ==
1237 23:21:50.774581 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 23:21:50.777956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 23:21:50.781153 ==
1240 23:21:50.781278 RX Vref Scan: 0
1241 23:21:50.781347
1242 23:21:50.784757 RX Vref 0 -> 0, step: 1
1243 23:21:50.784885
1244 23:21:50.787888 RX Delay -130 -> 252, step: 16
1245 23:21:50.791438 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1246 23:21:50.794788 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1247 23:21:50.798251 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1248 23:21:50.801460 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1249 23:21:50.807880 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1250 23:21:50.811312 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1251 23:21:50.814630 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1252 23:21:50.818064 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
1253 23:21:50.821390 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1254 23:21:50.824643 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1255 23:21:50.831388 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1256 23:21:50.834771 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1257 23:21:50.838098 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1258 23:21:50.841713 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1259 23:21:50.848262 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1260 23:21:50.851710 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1261 23:21:50.851837 ==
1262 23:21:50.854865 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 23:21:50.858166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 23:21:50.858276 ==
1265 23:21:50.858344 DQS Delay:
1266 23:21:50.861488 DQS0 = 0, DQS1 = 0
1267 23:21:50.861584 DQM Delay:
1268 23:21:50.864879 DQM0 = 90, DQM1 = 81
1269 23:21:50.864987 DQ Delay:
1270 23:21:50.868194 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1271 23:21:50.871710 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1272 23:21:50.875056 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1273 23:21:50.878282 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1274 23:21:50.878410
1275 23:21:50.878492
1276 23:21:50.878561 ==
1277 23:21:50.881791 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 23:21:50.884996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 23:21:50.888192 ==
1280 23:21:50.888353
1281 23:21:50.888456
1282 23:21:50.888551 TX Vref Scan disable
1283 23:21:50.891611 == TX Byte 0 ==
1284 23:21:50.894947 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1285 23:21:50.898422 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1286 23:21:50.901390 == TX Byte 1 ==
1287 23:21:50.904970 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1288 23:21:50.908071 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1289 23:21:50.911496 ==
1290 23:21:50.911595 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 23:21:50.918281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 23:21:50.918398 ==
1293 23:21:50.930586 TX Vref=22, minBit 8, minWin=27, winSum=446
1294 23:21:50.933932 TX Vref=24, minBit 9, minWin=27, winSum=450
1295 23:21:50.937329 TX Vref=26, minBit 2, minWin=28, winSum=455
1296 23:21:50.940368 TX Vref=28, minBit 1, minWin=28, winSum=454
1297 23:21:50.943850 TX Vref=30, minBit 6, minWin=28, winSum=457
1298 23:21:50.947111 TX Vref=32, minBit 8, minWin=27, winSum=451
1299 23:21:50.953925 [TxChooseVref] Worse bit 6, Min win 28, Win sum 457, Final Vref 30
1300 23:21:50.954053
1301 23:21:50.957091 Final TX Range 1 Vref 30
1302 23:21:50.957188
1303 23:21:50.957254 ==
1304 23:21:50.960480 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 23:21:50.963892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 23:21:50.964019 ==
1307 23:21:50.966827
1308 23:21:50.966931
1309 23:21:50.967023 TX Vref Scan disable
1310 23:21:50.970568 == TX Byte 0 ==
1311 23:21:50.973857 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1312 23:21:50.977328 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1313 23:21:50.980656 == TX Byte 1 ==
1314 23:21:50.984009 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1315 23:21:50.987415 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1316 23:21:50.990438
1317 23:21:50.990551 [DATLAT]
1318 23:21:50.990644 Freq=800, CH0 RK1
1319 23:21:50.990745
1320 23:21:50.993800 DATLAT Default: 0xa
1321 23:21:50.993889 0, 0xFFFF, sum = 0
1322 23:21:50.997284 1, 0xFFFF, sum = 0
1323 23:21:50.997368 2, 0xFFFF, sum = 0
1324 23:21:51.000530 3, 0xFFFF, sum = 0
1325 23:21:51.000622 4, 0xFFFF, sum = 0
1326 23:21:51.003795 5, 0xFFFF, sum = 0
1327 23:21:51.007205 6, 0xFFFF, sum = 0
1328 23:21:51.007326 7, 0xFFFF, sum = 0
1329 23:21:51.010511 8, 0xFFFF, sum = 0
1330 23:21:51.010636 9, 0x0, sum = 1
1331 23:21:51.010736 10, 0x0, sum = 2
1332 23:21:51.013603 11, 0x0, sum = 3
1333 23:21:51.013714 12, 0x0, sum = 4
1334 23:21:51.016936 best_step = 10
1335 23:21:51.017029
1336 23:21:51.017098 ==
1337 23:21:51.020401 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 23:21:51.023589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 23:21:51.023715 ==
1340 23:21:51.027220 RX Vref Scan: 0
1341 23:21:51.027310
1342 23:21:51.027377 RX Vref 0 -> 0, step: 1
1343 23:21:51.027438
1344 23:21:51.030309 RX Delay -95 -> 252, step: 8
1345 23:21:51.037014 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1346 23:21:51.040192 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1347 23:21:51.043679 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1348 23:21:51.047187 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1349 23:21:51.050483 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1350 23:21:51.057167 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1351 23:21:51.060558 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1352 23:21:51.063797 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1353 23:21:51.067054 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1354 23:21:51.070409 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1355 23:21:51.077205 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1356 23:21:51.080212 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1357 23:21:51.083475 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1358 23:21:51.086966 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1359 23:21:51.090156 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1360 23:21:51.097055 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1361 23:21:51.097183 ==
1362 23:21:51.100427 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 23:21:51.103879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 23:21:51.104014 ==
1365 23:21:51.104111 DQS Delay:
1366 23:21:51.107285 DQS0 = 0, DQS1 = 0
1367 23:21:51.107404 DQM Delay:
1368 23:21:51.110509 DQM0 = 92, DQM1 = 82
1369 23:21:51.110606 DQ Delay:
1370 23:21:51.113628 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1371 23:21:51.116985 DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100
1372 23:21:51.120354 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1373 23:21:51.123571 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =92
1374 23:21:51.123692
1375 23:21:51.123771
1376 23:21:51.130527 [DQSOSCAuto] RK1, (LSB)MR18= 0x4212, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1377 23:21:51.133977 CH0 RK1: MR19=606, MR18=4212
1378 23:21:51.140280 CH0_RK1: MR19=0x606, MR18=0x4212, DQSOSC=393, MR23=63, INC=95, DEC=63
1379 23:21:51.143980 [RxdqsGatingPostProcess] freq 800
1380 23:21:51.150475 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 23:21:51.153832 Pre-setting of DQS Precalculation
1382 23:21:51.157233 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 23:21:51.157378 ==
1384 23:21:51.160675 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 23:21:51.163759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 23:21:51.163868 ==
1387 23:21:51.170601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 23:21:51.177139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 23:21:51.185438 [CA 0] Center 36 (6~67) winsize 62
1390 23:21:51.188984 [CA 1] Center 36 (6~67) winsize 62
1391 23:21:51.192163 [CA 2] Center 35 (5~66) winsize 62
1392 23:21:51.195311 [CA 3] Center 35 (5~65) winsize 61
1393 23:21:51.198626 [CA 4] Center 34 (4~65) winsize 62
1394 23:21:51.202020 [CA 5] Center 34 (4~64) winsize 61
1395 23:21:51.202146
1396 23:21:51.205399 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1397 23:21:51.205490
1398 23:21:51.208744 [CATrainingPosCal] consider 1 rank data
1399 23:21:51.212191 u2DelayCellTimex100 = 270/100 ps
1400 23:21:51.215374 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1401 23:21:51.218753 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1402 23:21:51.225482 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1403 23:21:51.228931 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1404 23:21:51.231910 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1405 23:21:51.235291 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1406 23:21:51.235400
1407 23:21:51.238757 CA PerBit enable=1, Macro0, CA PI delay=34
1408 23:21:51.238882
1409 23:21:51.242253 [CBTSetCACLKResult] CA Dly = 34
1410 23:21:51.242355 CS Dly: 6 (0~37)
1411 23:21:51.242424 ==
1412 23:21:51.245369 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 23:21:51.252218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 23:21:51.252362 ==
1415 23:21:51.255542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 23:21:51.262764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 23:21:51.271765 [CA 0] Center 36 (6~67) winsize 62
1418 23:21:51.275831 [CA 1] Center 37 (6~68) winsize 63
1419 23:21:51.279693 [CA 2] Center 35 (5~66) winsize 62
1420 23:21:51.283662 [CA 3] Center 34 (4~65) winsize 62
1421 23:21:51.287864 [CA 4] Center 34 (4~65) winsize 62
1422 23:21:51.287979 [CA 5] Center 34 (4~65) winsize 62
1423 23:21:51.288049
1424 23:21:51.291495 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1425 23:21:51.291594
1426 23:21:51.294808 [CATrainingPosCal] consider 2 rank data
1427 23:21:51.298097 u2DelayCellTimex100 = 270/100 ps
1428 23:21:51.301448 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1429 23:21:51.304726 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 23:21:51.311345 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1431 23:21:51.314816 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1432 23:21:51.318205 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1433 23:21:51.321536 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1434 23:21:51.321660
1435 23:21:51.324721 CA PerBit enable=1, Macro0, CA PI delay=34
1436 23:21:51.324834
1437 23:21:51.327969 [CBTSetCACLKResult] CA Dly = 34
1438 23:21:51.328061 CS Dly: 6 (0~38)
1439 23:21:51.328126
1440 23:21:51.331473 ----->DramcWriteLeveling(PI) begin...
1441 23:21:51.334788 ==
1442 23:21:51.337933 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 23:21:51.341268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 23:21:51.341371 ==
1445 23:21:51.344742 Write leveling (Byte 0): 28 => 28
1446 23:21:51.348079 Write leveling (Byte 1): 29 => 29
1447 23:21:51.351429 DramcWriteLeveling(PI) end<-----
1448 23:21:51.351537
1449 23:21:51.351647 ==
1450 23:21:51.354541 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 23:21:51.358178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 23:21:51.358335 ==
1453 23:21:51.361288 [Gating] SW mode calibration
1454 23:21:51.367875 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 23:21:51.371379 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 23:21:51.378078 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1457 23:21:51.381540 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1458 23:21:51.384921 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:21:51.391287 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:21:51.394783 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:21:51.398024 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:21:51.404760 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:21:51.407834 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:21:51.411219 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:21:51.418141 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:21:51.421156 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:21:51.424598 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:21:51.431304 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:21:51.434549 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:21:51.437997 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:21:51.444630 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:21:51.447967 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1473 23:21:51.451431 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1474 23:21:51.457973 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:21:51.461345 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 23:21:51.464707 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 23:21:51.467916 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 23:21:51.474728 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 23:21:51.478096 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 23:21:51.481185 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 23:21:51.487823 0 9 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
1482 23:21:51.491011 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1483 23:21:51.494598 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 23:21:51.501170 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 23:21:51.504402 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 23:21:51.507776 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 23:21:51.514443 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 23:21:51.517910 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1489 23:21:51.521304 0 10 4 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 0)
1490 23:21:51.528022 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1491 23:21:51.531146 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 23:21:51.534508 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 23:21:51.541247 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 23:21:51.544575 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 23:21:51.548020 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:21:51.554480 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1497 23:21:51.557796 0 11 4 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
1498 23:21:51.561168 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1499 23:21:51.567789 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 23:21:51.571242 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 23:21:51.574388 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 23:21:51.577985 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 23:21:51.584619 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 23:21:51.587970 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1505 23:21:51.591129 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1506 23:21:51.597793 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:21:51.601531 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:21:51.604940 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:21:51.611252 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:21:51.614674 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:21:51.618180 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:21:51.624788 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:21:51.628156 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:21:51.631183 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 23:21:51.638255 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 23:21:51.641632 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 23:21:51.644880 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 23:21:51.651553 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 23:21:51.654890 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 23:21:51.658213 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1521 23:21:51.661623 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1522 23:21:51.667913 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 23:21:51.671422 Total UI for P1: 0, mck2ui 16
1524 23:21:51.674774 best dqsien dly found for B0: ( 0, 14, 2)
1525 23:21:51.678282 Total UI for P1: 0, mck2ui 16
1526 23:21:51.681549 best dqsien dly found for B1: ( 0, 14, 4)
1527 23:21:51.685013 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1528 23:21:51.688434 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1529 23:21:51.688585
1530 23:21:51.691538 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1531 23:21:51.694980 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1532 23:21:51.698545 [Gating] SW calibration Done
1533 23:21:51.698653 ==
1534 23:21:51.701935 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 23:21:51.705198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1536 23:21:51.705310 ==
1537 23:21:51.708316 RX Vref Scan: 0
1538 23:21:51.708407
1539 23:21:51.708470 RX Vref 0 -> 0, step: 1
1540 23:21:51.708529
1541 23:21:51.711551 RX Delay -130 -> 252, step: 16
1542 23:21:51.715234 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1543 23:21:51.721902 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1544 23:21:51.725180 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1545 23:21:51.728398 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1546 23:21:51.731575 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1547 23:21:51.734987 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1548 23:21:51.738595 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1549 23:21:51.745168 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1550 23:21:51.748468 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1551 23:21:51.751649 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1552 23:21:51.755051 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1553 23:21:51.758401 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1554 23:21:51.764902 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1555 23:21:51.768478 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1556 23:21:51.771898 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1557 23:21:51.775254 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1558 23:21:51.775383 ==
1559 23:21:51.778588 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 23:21:51.784965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 23:21:51.785120 ==
1562 23:21:51.785219 DQS Delay:
1563 23:21:51.788314 DQS0 = 0, DQS1 = 0
1564 23:21:51.788415 DQM Delay:
1565 23:21:51.788518 DQM0 = 92, DQM1 = 87
1566 23:21:51.791759 DQ Delay:
1567 23:21:51.794927 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1568 23:21:51.798332 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1569 23:21:51.801852 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1570 23:21:51.805224 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1571 23:21:51.805350
1572 23:21:51.805451
1573 23:21:51.805540 ==
1574 23:21:51.808242 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 23:21:51.811634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 23:21:51.811752 ==
1577 23:21:51.811854
1578 23:21:51.811944
1579 23:21:51.814940 TX Vref Scan disable
1580 23:21:51.815057 == TX Byte 0 ==
1581 23:21:51.821731 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1582 23:21:51.824903 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1583 23:21:51.825035 == TX Byte 1 ==
1584 23:21:51.831616 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1585 23:21:51.834919 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1586 23:21:51.835062 ==
1587 23:21:51.838726 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 23:21:51.842060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 23:21:51.842188 ==
1590 23:21:51.855826 TX Vref=22, minBit 0, minWin=27, winSum=436
1591 23:21:51.859272 TX Vref=24, minBit 0, minWin=27, winSum=441
1592 23:21:51.862702 TX Vref=26, minBit 1, minWin=27, winSum=447
1593 23:21:51.865850 TX Vref=28, minBit 3, minWin=26, winSum=445
1594 23:21:51.869442 TX Vref=30, minBit 0, minWin=27, winSum=452
1595 23:21:51.872478 TX Vref=32, minBit 0, minWin=27, winSum=447
1596 23:21:51.879211 [TxChooseVref] Worse bit 0, Min win 27, Win sum 452, Final Vref 30
1597 23:21:51.879357
1598 23:21:51.882394 Final TX Range 1 Vref 30
1599 23:21:51.882481
1600 23:21:51.882546 ==
1601 23:21:51.885764 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 23:21:51.889224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 23:21:51.889363 ==
1604 23:21:51.889473
1605 23:21:51.889573
1606 23:21:51.892616 TX Vref Scan disable
1607 23:21:51.896083 == TX Byte 0 ==
1608 23:21:51.899116 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1609 23:21:51.902391 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1610 23:21:51.905984 == TX Byte 1 ==
1611 23:21:51.909324 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1612 23:21:51.912311 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1613 23:21:51.915774
1614 23:21:51.915908 [DATLAT]
1615 23:21:51.916018 Freq=800, CH1 RK0
1616 23:21:51.916120
1617 23:21:51.919174 DATLAT Default: 0xa
1618 23:21:51.919316 0, 0xFFFF, sum = 0
1619 23:21:51.922690 1, 0xFFFF, sum = 0
1620 23:21:51.922838 2, 0xFFFF, sum = 0
1621 23:21:51.925739 3, 0xFFFF, sum = 0
1622 23:21:51.925897 4, 0xFFFF, sum = 0
1623 23:21:51.928982 5, 0xFFFF, sum = 0
1624 23:21:51.929106 6, 0xFFFF, sum = 0
1625 23:21:51.932255 7, 0xFFFF, sum = 0
1626 23:21:51.935801 8, 0xFFFF, sum = 0
1627 23:21:51.935940 9, 0x0, sum = 1
1628 23:21:51.936054 10, 0x0, sum = 2
1629 23:21:51.939178 11, 0x0, sum = 3
1630 23:21:51.939299 12, 0x0, sum = 4
1631 23:21:51.942187 best_step = 10
1632 23:21:51.942311
1633 23:21:51.942421 ==
1634 23:21:51.945781 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 23:21:51.948931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 23:21:51.949061 ==
1637 23:21:51.952136 RX Vref Scan: 1
1638 23:21:51.952265
1639 23:21:51.952388 Set Vref Range= 32 -> 127
1640 23:21:51.955639
1641 23:21:51.955765 RX Vref 32 -> 127, step: 1
1642 23:21:51.955868
1643 23:21:51.959060 RX Delay -79 -> 252, step: 8
1644 23:21:51.959186
1645 23:21:51.962526 Set Vref, RX VrefLevel [Byte0]: 32
1646 23:21:51.965634 [Byte1]: 32
1647 23:21:51.965767
1648 23:21:51.969047 Set Vref, RX VrefLevel [Byte0]: 33
1649 23:21:51.972331 [Byte1]: 33
1650 23:21:51.975871
1651 23:21:51.976009 Set Vref, RX VrefLevel [Byte0]: 34
1652 23:21:51.979282 [Byte1]: 34
1653 23:21:51.983533
1654 23:21:51.983679 Set Vref, RX VrefLevel [Byte0]: 35
1655 23:21:51.986613 [Byte1]: 35
1656 23:21:51.990956
1657 23:21:51.991092 Set Vref, RX VrefLevel [Byte0]: 36
1658 23:21:51.994329 [Byte1]: 36
1659 23:21:51.998716
1660 23:21:51.998845 Set Vref, RX VrefLevel [Byte0]: 37
1661 23:21:52.001856 [Byte1]: 37
1662 23:21:52.006174
1663 23:21:52.006302 Set Vref, RX VrefLevel [Byte0]: 38
1664 23:21:52.009682 [Byte1]: 38
1665 23:21:52.013670
1666 23:21:52.013813 Set Vref, RX VrefLevel [Byte0]: 39
1667 23:21:52.017278 [Byte1]: 39
1668 23:21:52.021552
1669 23:21:52.021688 Set Vref, RX VrefLevel [Byte0]: 40
1670 23:21:52.024456 [Byte1]: 40
1671 23:21:52.028662
1672 23:21:52.028773 Set Vref, RX VrefLevel [Byte0]: 41
1673 23:21:52.032157 [Byte1]: 41
1674 23:21:52.036460
1675 23:21:52.036594 Set Vref, RX VrefLevel [Byte0]: 42
1676 23:21:52.039789 [Byte1]: 42
1677 23:21:52.043991
1678 23:21:52.044110 Set Vref, RX VrefLevel [Byte0]: 43
1679 23:21:52.047011 [Byte1]: 43
1680 23:21:52.051555
1681 23:21:52.051718 Set Vref, RX VrefLevel [Byte0]: 44
1682 23:21:52.054683 [Byte1]: 44
1683 23:21:52.059021
1684 23:21:52.059167 Set Vref, RX VrefLevel [Byte0]: 45
1685 23:21:52.062330 [Byte1]: 45
1686 23:21:52.066523
1687 23:21:52.066656 Set Vref, RX VrefLevel [Byte0]: 46
1688 23:21:52.069791 [Byte1]: 46
1689 23:21:52.074183
1690 23:21:52.074327 Set Vref, RX VrefLevel [Byte0]: 47
1691 23:21:52.077519 [Byte1]: 47
1692 23:21:52.081375
1693 23:21:52.081519 Set Vref, RX VrefLevel [Byte0]: 48
1694 23:21:52.084896 [Byte1]: 48
1695 23:21:52.089242
1696 23:21:52.089350 Set Vref, RX VrefLevel [Byte0]: 49
1697 23:21:52.092303 [Byte1]: 49
1698 23:21:52.096715
1699 23:21:52.096821 Set Vref, RX VrefLevel [Byte0]: 50
1700 23:21:52.100018 [Byte1]: 50
1701 23:21:52.104165
1702 23:21:52.104309 Set Vref, RX VrefLevel [Byte0]: 51
1703 23:21:52.107415 [Byte1]: 51
1704 23:21:52.111654
1705 23:21:52.111787 Set Vref, RX VrefLevel [Byte0]: 52
1706 23:21:52.115253 [Byte1]: 52
1707 23:21:52.119322
1708 23:21:52.119426 Set Vref, RX VrefLevel [Byte0]: 53
1709 23:21:52.122421 [Byte1]: 53
1710 23:21:52.126795
1711 23:21:52.126898 Set Vref, RX VrefLevel [Byte0]: 54
1712 23:21:52.130290 [Byte1]: 54
1713 23:21:52.134247
1714 23:21:52.134368 Set Vref, RX VrefLevel [Byte0]: 55
1715 23:21:52.137758 [Byte1]: 55
1716 23:21:52.141749
1717 23:21:52.141890 Set Vref, RX VrefLevel [Byte0]: 56
1718 23:21:52.145526 [Byte1]: 56
1719 23:21:52.149391
1720 23:21:52.149532 Set Vref, RX VrefLevel [Byte0]: 57
1721 23:21:52.152750 [Byte1]: 57
1722 23:21:52.157137
1723 23:21:52.157283 Set Vref, RX VrefLevel [Byte0]: 58
1724 23:21:52.160418 [Byte1]: 58
1725 23:21:52.164571
1726 23:21:52.164685 Set Vref, RX VrefLevel [Byte0]: 59
1727 23:21:52.167971 [Byte1]: 59
1728 23:21:52.172385
1729 23:21:52.172593 Set Vref, RX VrefLevel [Byte0]: 60
1730 23:21:52.175393 [Byte1]: 60
1731 23:21:52.179865
1732 23:21:52.180074 Set Vref, RX VrefLevel [Byte0]: 61
1733 23:21:52.183065 [Byte1]: 61
1734 23:21:52.187260
1735 23:21:52.187480 Set Vref, RX VrefLevel [Byte0]: 62
1736 23:21:52.190323 [Byte1]: 62
1737 23:21:52.194672
1738 23:21:52.194870 Set Vref, RX VrefLevel [Byte0]: 63
1739 23:21:52.198151 [Byte1]: 63
1740 23:21:52.202441
1741 23:21:52.202623 Set Vref, RX VrefLevel [Byte0]: 64
1742 23:21:52.205882 [Byte1]: 64
1743 23:21:52.209909
1744 23:21:52.210098 Set Vref, RX VrefLevel [Byte0]: 65
1745 23:21:52.213116 [Byte1]: 65
1746 23:21:52.217316
1747 23:21:52.217501 Set Vref, RX VrefLevel [Byte0]: 66
1748 23:21:52.220653 [Byte1]: 66
1749 23:21:52.225004
1750 23:21:52.225190 Set Vref, RX VrefLevel [Byte0]: 67
1751 23:21:52.228201 [Byte1]: 67
1752 23:21:52.232462
1753 23:21:52.232593 Set Vref, RX VrefLevel [Byte0]: 68
1754 23:21:52.236071 [Byte1]: 68
1755 23:21:52.240220
1756 23:21:52.240344 Set Vref, RX VrefLevel [Byte0]: 69
1757 23:21:52.243243 [Byte1]: 69
1758 23:21:52.247406
1759 23:21:52.247549 Set Vref, RX VrefLevel [Byte0]: 70
1760 23:21:52.250911 [Byte1]: 70
1761 23:21:52.255313
1762 23:21:52.255463 Set Vref, RX VrefLevel [Byte0]: 71
1763 23:21:52.258292 [Byte1]: 71
1764 23:21:52.262968
1765 23:21:52.263123 Final RX Vref Byte 0 = 58 to rank0
1766 23:21:52.265950 Final RX Vref Byte 1 = 57 to rank0
1767 23:21:52.269521 Final RX Vref Byte 0 = 58 to rank1
1768 23:21:52.272556 Final RX Vref Byte 1 = 57 to rank1==
1769 23:21:52.275988 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 23:21:52.282678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 23:21:52.282840 ==
1772 23:21:52.282944 DQS Delay:
1773 23:21:52.283041 DQS0 = 0, DQS1 = 0
1774 23:21:52.286036 DQM Delay:
1775 23:21:52.286152 DQM0 = 95, DQM1 = 91
1776 23:21:52.289251 DQ Delay:
1777 23:21:52.292842 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1778 23:21:52.296131 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1779 23:21:52.296262 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =84
1780 23:21:52.303055 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =96
1781 23:21:52.303211
1782 23:21:52.303308
1783 23:21:52.309500 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1784 23:21:52.312921 CH1 RK0: MR19=606, MR18=2B48
1785 23:21:52.319420 CH1_RK0: MR19=0x606, MR18=0x2B48, DQSOSC=391, MR23=63, INC=96, DEC=64
1786 23:21:52.319577
1787 23:21:52.322746 ----->DramcWriteLeveling(PI) begin...
1788 23:21:52.322875 ==
1789 23:21:52.326012 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 23:21:52.329449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 23:21:52.329582 ==
1792 23:21:52.332862 Write leveling (Byte 0): 26 => 26
1793 23:21:52.336215 Write leveling (Byte 1): 27 => 27
1794 23:21:52.339623 DramcWriteLeveling(PI) end<-----
1795 23:21:52.339751
1796 23:21:52.339848 ==
1797 23:21:52.342849 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 23:21:52.346282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 23:21:52.346417 ==
1800 23:21:52.349539 [Gating] SW mode calibration
1801 23:21:52.356324 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 23:21:52.362815 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 23:21:52.366414 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1804 23:21:52.369852 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1805 23:21:52.376325 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 23:21:52.379688 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 23:21:52.383148 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 23:21:52.389783 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 23:21:52.393222 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 23:21:52.396151 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 23:21:52.403297 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 23:21:52.406522 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 23:21:52.409618 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 23:21:52.413058 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 23:21:52.419981 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 23:21:52.423239 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 23:21:52.426202 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:21:52.432986 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:21:52.436368 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1820 23:21:52.439585 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1821 23:21:52.446431 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:21:52.449973 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:21:52.453310 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:21:52.459657 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:21:52.462957 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:21:52.466606 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:21:52.473056 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:21:52.476449 0 9 4 | B1->B0 | 2626 2323 | 1 0 | (1 1) (1 1)
1829 23:21:52.479833 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1830 23:21:52.486386 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 23:21:52.489774 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 23:21:52.492916 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 23:21:52.499670 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 23:21:52.502867 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 23:21:52.506251 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1836 23:21:52.509590 0 10 4 | B1->B0 | 2929 3131 | 0 0 | (1 1) (0 1)
1837 23:21:52.516192 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1838 23:21:52.519584 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:21:52.522881 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:21:52.529488 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:21:52.532971 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 23:21:52.536260 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 23:21:52.543010 0 11 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1844 23:21:52.546134 0 11 4 | B1->B0 | 3737 2f2f | 0 0 | (0 0) (0 0)
1845 23:21:52.549499 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1846 23:21:52.556377 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 23:21:52.559328 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 23:21:52.562799 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 23:21:52.569715 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 23:21:52.572726 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 23:21:52.576211 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 23:21:52.582962 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1853 23:21:52.586227 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 23:21:52.589510 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 23:21:52.596282 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 23:21:52.599747 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 23:21:52.603047 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 23:21:52.609460 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 23:21:52.613112 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 23:21:52.616227 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 23:21:52.619717 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 23:21:52.626332 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 23:21:52.629513 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 23:21:52.633042 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 23:21:52.639795 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 23:21:52.643208 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 23:21:52.646261 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 23:21:52.652982 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1869 23:21:52.653147 Total UI for P1: 0, mck2ui 16
1870 23:21:52.659871 best dqsien dly found for B1: ( 0, 14, 2)
1871 23:21:52.662875 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1872 23:21:52.666712 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 23:21:52.669710 Total UI for P1: 0, mck2ui 16
1874 23:21:52.673147 best dqsien dly found for B0: ( 0, 14, 6)
1875 23:21:52.676577 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1876 23:21:52.680042 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1877 23:21:52.680168
1878 23:21:52.683133 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1879 23:21:52.689928 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1880 23:21:52.690079 [Gating] SW calibration Done
1881 23:21:52.690185 ==
1882 23:21:52.693299 Dram Type= 6, Freq= 0, CH_1, rank 1
1883 23:21:52.699613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1884 23:21:52.699731 ==
1885 23:21:52.699836 RX Vref Scan: 0
1886 23:21:52.699937
1887 23:21:52.703020 RX Vref 0 -> 0, step: 1
1888 23:21:52.703130
1889 23:21:52.706329 RX Delay -130 -> 252, step: 16
1890 23:21:52.709680 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1891 23:21:52.713040 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1892 23:21:52.716370 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1893 23:21:52.723026 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1894 23:21:52.726404 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1895 23:21:52.729804 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1896 23:21:52.733319 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1897 23:21:52.736568 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1898 23:21:52.739742 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1899 23:21:52.746289 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1900 23:21:52.749785 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1901 23:21:52.753190 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1902 23:21:52.756270 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1903 23:21:52.763213 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1904 23:21:52.766303 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1905 23:21:52.769703 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1906 23:21:52.769812 ==
1907 23:21:52.773118 Dram Type= 6, Freq= 0, CH_1, rank 1
1908 23:21:52.776268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1909 23:21:52.776376 ==
1910 23:21:52.779663 DQS Delay:
1911 23:21:52.779776 DQS0 = 0, DQS1 = 0
1912 23:21:52.782971 DQM Delay:
1913 23:21:52.783075 DQM0 = 94, DQM1 = 90
1914 23:21:52.783166 DQ Delay:
1915 23:21:52.786451 DQ0 =101, DQ1 =93, DQ2 =85, DQ3 =85
1916 23:21:52.789784 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1917 23:21:52.792947 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1918 23:21:52.796194 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1919 23:21:52.796349
1920 23:21:52.799700
1921 23:21:52.799789 ==
1922 23:21:52.802704 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 23:21:52.806547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 23:21:52.806644 ==
1925 23:21:52.806712
1926 23:21:52.806774
1927 23:21:52.809430 TX Vref Scan disable
1928 23:21:52.809521 == TX Byte 0 ==
1929 23:21:52.816074 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1930 23:21:52.819483 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1931 23:21:52.819585 == TX Byte 1 ==
1932 23:21:52.822874 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1933 23:21:52.829664 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1934 23:21:52.829809 ==
1935 23:21:52.833220 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 23:21:52.836463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 23:21:52.836597 ==
1938 23:21:52.849681 TX Vref=22, minBit 3, minWin=25, winSum=436
1939 23:21:52.852904 TX Vref=24, minBit 1, minWin=27, winSum=445
1940 23:21:52.856385 TX Vref=26, minBit 3, minWin=26, winSum=444
1941 23:21:52.859502 TX Vref=28, minBit 1, minWin=26, winSum=445
1942 23:21:52.862787 TX Vref=30, minBit 3, minWin=26, winSum=449
1943 23:21:52.866261 TX Vref=32, minBit 7, minWin=26, winSum=445
1944 23:21:52.872650 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 24
1945 23:21:52.872796
1946 23:21:52.875971 Final TX Range 1 Vref 24
1947 23:21:52.876121
1948 23:21:52.876239 ==
1949 23:21:52.879268 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 23:21:52.882694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 23:21:52.882846 ==
1952 23:21:52.882968
1953 23:21:52.886172
1954 23:21:52.886326 TX Vref Scan disable
1955 23:21:52.889595 == TX Byte 0 ==
1956 23:21:52.892610 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1957 23:21:52.896058 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1958 23:21:52.899406 == TX Byte 1 ==
1959 23:21:52.902636 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1960 23:21:52.909367 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1961 23:21:52.909545
1962 23:21:52.909663 [DATLAT]
1963 23:21:52.909777 Freq=800, CH1 RK1
1964 23:21:52.909891
1965 23:21:52.912697 DATLAT Default: 0xa
1966 23:21:52.912824 0, 0xFFFF, sum = 0
1967 23:21:52.916077 1, 0xFFFF, sum = 0
1968 23:21:52.916218 2, 0xFFFF, sum = 0
1969 23:21:52.919435 3, 0xFFFF, sum = 0
1970 23:21:52.919576 4, 0xFFFF, sum = 0
1971 23:21:52.922406 5, 0xFFFF, sum = 0
1972 23:21:52.926165 6, 0xFFFF, sum = 0
1973 23:21:52.926307 7, 0xFFFF, sum = 0
1974 23:21:52.929133 8, 0xFFFF, sum = 0
1975 23:21:52.929272 9, 0x0, sum = 1
1976 23:21:52.929392 10, 0x0, sum = 2
1977 23:21:52.932524 11, 0x0, sum = 3
1978 23:21:52.932660 12, 0x0, sum = 4
1979 23:21:52.935823 best_step = 10
1980 23:21:52.935967
1981 23:21:52.936081 ==
1982 23:21:52.939177 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 23:21:52.942506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 23:21:52.942649 ==
1985 23:21:52.945918 RX Vref Scan: 0
1986 23:21:52.946057
1987 23:21:52.946174 RX Vref 0 -> 0, step: 1
1988 23:21:52.946285
1989 23:21:52.949309 RX Delay -79 -> 252, step: 8
1990 23:21:52.956145 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1991 23:21:52.959336 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1992 23:21:52.962775 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1993 23:21:52.966402 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1994 23:21:52.969537 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1995 23:21:52.972934 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1996 23:21:52.979493 iDelay=209, Bit 6, Center 112 (17 ~ 208) 192
1997 23:21:52.983022 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1998 23:21:52.986038 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1999 23:21:52.989537 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2000 23:21:52.992980 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2001 23:21:52.999466 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2002 23:21:53.002707 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2003 23:21:53.006152 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2004 23:21:53.009541 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2005 23:21:53.012701 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2006 23:21:53.016310 ==
2007 23:21:53.016430 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 23:21:53.022736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 23:21:53.022890 ==
2010 23:21:53.022989 DQS Delay:
2011 23:21:53.026224 DQS0 = 0, DQS1 = 0
2012 23:21:53.026357 DQM Delay:
2013 23:21:53.029639 DQM0 = 98, DQM1 = 90
2014 23:21:53.029759 DQ Delay:
2015 23:21:53.033121 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2016 23:21:53.036489 DQ4 =92, DQ5 =112, DQ6 =112, DQ7 =96
2017 23:21:53.039375 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =88
2018 23:21:53.043145 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2019 23:21:53.043280
2020 23:21:53.043381
2021 23:21:53.049664 [DQSOSCAuto] RK1, (LSB)MR18= 0x440d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2022 23:21:53.053056 CH1 RK1: MR19=606, MR18=440D
2023 23:21:53.059857 CH1_RK1: MR19=0x606, MR18=0x440D, DQSOSC=392, MR23=63, INC=96, DEC=64
2024 23:21:53.062892 [RxdqsGatingPostProcess] freq 800
2025 23:21:53.066444 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2026 23:21:53.069871 Pre-setting of DQS Precalculation
2027 23:21:53.076521 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2028 23:21:53.083003 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2029 23:21:53.089852 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2030 23:21:53.089966
2031 23:21:53.090034
2032 23:21:53.093160 [Calibration Summary] 1600 Mbps
2033 23:21:53.093279 CH 0, Rank 0
2034 23:21:53.096387 SW Impedance : PASS
2035 23:21:53.099826 DUTY Scan : NO K
2036 23:21:53.099950 ZQ Calibration : PASS
2037 23:21:53.103210 Jitter Meter : NO K
2038 23:21:53.106316 CBT Training : PASS
2039 23:21:53.106443 Write leveling : PASS
2040 23:21:53.109945 RX DQS gating : PASS
2041 23:21:53.113081 RX DQ/DQS(RDDQC) : PASS
2042 23:21:53.113205 TX DQ/DQS : PASS
2043 23:21:53.116562 RX DATLAT : PASS
2044 23:21:53.119972 RX DQ/DQS(Engine): PASS
2045 23:21:53.120100 TX OE : NO K
2046 23:21:53.120197 All Pass.
2047 23:21:53.120299
2048 23:21:53.123351 CH 0, Rank 1
2049 23:21:53.126555 SW Impedance : PASS
2050 23:21:53.126680 DUTY Scan : NO K
2051 23:21:53.129836 ZQ Calibration : PASS
2052 23:21:53.129960 Jitter Meter : NO K
2053 23:21:53.133189 CBT Training : PASS
2054 23:21:53.136471 Write leveling : PASS
2055 23:21:53.136583 RX DQS gating : PASS
2056 23:21:53.139815 RX DQ/DQS(RDDQC) : PASS
2057 23:21:53.143250 TX DQ/DQS : PASS
2058 23:21:53.143369 RX DATLAT : PASS
2059 23:21:53.146648 RX DQ/DQS(Engine): PASS
2060 23:21:53.149939 TX OE : NO K
2061 23:21:53.150073 All Pass.
2062 23:21:53.150187
2063 23:21:53.150280 CH 1, Rank 0
2064 23:21:53.153432 SW Impedance : PASS
2065 23:21:53.156399 DUTY Scan : NO K
2066 23:21:53.156527 ZQ Calibration : PASS
2067 23:21:53.159755 Jitter Meter : NO K
2068 23:21:53.163239 CBT Training : PASS
2069 23:21:53.163365 Write leveling : PASS
2070 23:21:53.166556 RX DQS gating : PASS
2071 23:21:53.166637 RX DQ/DQS(RDDQC) : PASS
2072 23:21:53.169889 TX DQ/DQS : PASS
2073 23:21:53.173292 RX DATLAT : PASS
2074 23:21:53.173375 RX DQ/DQS(Engine): PASS
2075 23:21:53.176637 TX OE : NO K
2076 23:21:53.176731 All Pass.
2077 23:21:53.176797
2078 23:21:53.180080 CH 1, Rank 1
2079 23:21:53.180179 SW Impedance : PASS
2080 23:21:53.183490 DUTY Scan : NO K
2081 23:21:53.186744 ZQ Calibration : PASS
2082 23:21:53.186849 Jitter Meter : NO K
2083 23:21:53.189894 CBT Training : PASS
2084 23:21:53.193172 Write leveling : PASS
2085 23:21:53.193267 RX DQS gating : PASS
2086 23:21:53.196666 RX DQ/DQS(RDDQC) : PASS
2087 23:21:53.199858 TX DQ/DQS : PASS
2088 23:21:53.200018 RX DATLAT : PASS
2089 23:21:53.203350 RX DQ/DQS(Engine): PASS
2090 23:21:53.203523 TX OE : NO K
2091 23:21:53.206859 All Pass.
2092 23:21:53.207012
2093 23:21:53.207110 DramC Write-DBI off
2094 23:21:53.210094 PER_BANK_REFRESH: Hybrid Mode
2095 23:21:53.213557 TX_TRACKING: ON
2096 23:21:53.216746 [GetDramInforAfterCalByMRR] Vendor 6.
2097 23:21:53.220190 [GetDramInforAfterCalByMRR] Revision 606.
2098 23:21:53.223478 [GetDramInforAfterCalByMRR] Revision 2 0.
2099 23:21:53.223646 MR0 0x3b3b
2100 23:21:53.223761 MR8 0x5151
2101 23:21:53.230382 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 23:21:53.230574
2103 23:21:53.230679 MR0 0x3b3b
2104 23:21:53.230784 MR8 0x5151
2105 23:21:53.233304 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2106 23:21:53.233441
2107 23:21:53.243295 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2108 23:21:53.246779 [FAST_K] Save calibration result to emmc
2109 23:21:53.249967 [FAST_K] Save calibration result to emmc
2110 23:21:53.253529 dram_init: config_dvfs: 1
2111 23:21:53.256548 dramc_set_vcore_voltage set vcore to 662500
2112 23:21:53.259965 Read voltage for 1200, 2
2113 23:21:53.260115 Vio18 = 0
2114 23:21:53.260233 Vcore = 662500
2115 23:21:53.263152 Vdram = 0
2116 23:21:53.263288 Vddq = 0
2117 23:21:53.263404 Vmddr = 0
2118 23:21:53.270116 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2119 23:21:53.273313 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2120 23:21:53.276957 MEM_TYPE=3, freq_sel=15
2121 23:21:53.280177 sv_algorithm_assistance_LP4_1600
2122 23:21:53.283271 ============ PULL DRAM RESETB DOWN ============
2123 23:21:53.286912 ========== PULL DRAM RESETB DOWN end =========
2124 23:21:53.293450 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2125 23:21:53.297036 ===================================
2126 23:21:53.300200 LPDDR4 DRAM CONFIGURATION
2127 23:21:53.303225 ===================================
2128 23:21:53.303354 EX_ROW_EN[0] = 0x0
2129 23:21:53.306641 EX_ROW_EN[1] = 0x0
2130 23:21:53.306754 LP4Y_EN = 0x0
2131 23:21:53.310133 WORK_FSP = 0x0
2132 23:21:53.310214 WL = 0x4
2133 23:21:53.313680 RL = 0x4
2134 23:21:53.313790 BL = 0x2
2135 23:21:53.316826 RPST = 0x0
2136 23:21:53.316909 RD_PRE = 0x0
2137 23:21:53.319945 WR_PRE = 0x1
2138 23:21:53.320021 WR_PST = 0x0
2139 23:21:53.323506 DBI_WR = 0x0
2140 23:21:53.323597 DBI_RD = 0x0
2141 23:21:53.327082 OTF = 0x1
2142 23:21:53.330358 ===================================
2143 23:21:53.333591 ===================================
2144 23:21:53.333683 ANA top config
2145 23:21:53.336880 ===================================
2146 23:21:53.340329 DLL_ASYNC_EN = 0
2147 23:21:53.343369 ALL_SLAVE_EN = 0
2148 23:21:53.346838 NEW_RANK_MODE = 1
2149 23:21:53.346938 DLL_IDLE_MODE = 1
2150 23:21:53.350031 LP45_APHY_COMB_EN = 1
2151 23:21:53.353708 TX_ODT_DIS = 1
2152 23:21:53.356774 NEW_8X_MODE = 1
2153 23:21:53.360168 ===================================
2154 23:21:53.363298 ===================================
2155 23:21:53.366742 data_rate = 2400
2156 23:21:53.366860 CKR = 1
2157 23:21:53.370167 DQ_P2S_RATIO = 8
2158 23:21:53.373244 ===================================
2159 23:21:53.376652 CA_P2S_RATIO = 8
2160 23:21:53.380118 DQ_CA_OPEN = 0
2161 23:21:53.383298 DQ_SEMI_OPEN = 0
2162 23:21:53.383414 CA_SEMI_OPEN = 0
2163 23:21:53.386913 CA_FULL_RATE = 0
2164 23:21:53.390346 DQ_CKDIV4_EN = 0
2165 23:21:53.393544 CA_CKDIV4_EN = 0
2166 23:21:53.396906 CA_PREDIV_EN = 0
2167 23:21:53.400077 PH8_DLY = 17
2168 23:21:53.400197 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2169 23:21:53.403863 DQ_AAMCK_DIV = 4
2170 23:21:53.406835 CA_AAMCK_DIV = 4
2171 23:21:53.410168 CA_ADMCK_DIV = 4
2172 23:21:53.413472 DQ_TRACK_CA_EN = 0
2173 23:21:53.416900 CA_PICK = 1200
2174 23:21:53.420184 CA_MCKIO = 1200
2175 23:21:53.420276 MCKIO_SEMI = 0
2176 23:21:53.423529 PLL_FREQ = 2366
2177 23:21:53.427064 DQ_UI_PI_RATIO = 32
2178 23:21:53.430156 CA_UI_PI_RATIO = 0
2179 23:21:53.433671 ===================================
2180 23:21:53.436944 ===================================
2181 23:21:53.440520 memory_type:LPDDR4
2182 23:21:53.440627 GP_NUM : 10
2183 23:21:53.443733 SRAM_EN : 1
2184 23:21:53.443824 MD32_EN : 0
2185 23:21:53.446989 ===================================
2186 23:21:53.450426 [ANA_INIT] >>>>>>>>>>>>>>
2187 23:21:53.453942 <<<<<< [CONFIGURE PHASE]: ANA_TX
2188 23:21:53.457224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2189 23:21:53.460397 ===================================
2190 23:21:53.463736 data_rate = 2400,PCW = 0X5b00
2191 23:21:53.467321 ===================================
2192 23:21:53.470309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2193 23:21:53.477507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 23:21:53.480625 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2195 23:21:53.487070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2196 23:21:53.490464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2197 23:21:53.493651 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2198 23:21:53.493750 [ANA_INIT] flow start
2199 23:21:53.497078 [ANA_INIT] PLL >>>>>>>>
2200 23:21:53.500563 [ANA_INIT] PLL <<<<<<<<
2201 23:21:53.500658 [ANA_INIT] MIDPI >>>>>>>>
2202 23:21:53.503929 [ANA_INIT] MIDPI <<<<<<<<
2203 23:21:53.507178 [ANA_INIT] DLL >>>>>>>>
2204 23:21:53.507273 [ANA_INIT] DLL <<<<<<<<
2205 23:21:53.510418 [ANA_INIT] flow end
2206 23:21:53.513608 ============ LP4 DIFF to SE enter ============
2207 23:21:53.517192 ============ LP4 DIFF to SE exit ============
2208 23:21:53.520269 [ANA_INIT] <<<<<<<<<<<<<
2209 23:21:53.523427 [Flow] Enable top DCM control >>>>>
2210 23:21:53.526849 [Flow] Enable top DCM control <<<<<
2211 23:21:53.530397 Enable DLL master slave shuffle
2212 23:21:53.536710 ==============================================================
2213 23:21:53.536846 Gating Mode config
2214 23:21:53.543697 ==============================================================
2215 23:21:53.543820 Config description:
2216 23:21:53.553520 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2217 23:21:53.560612 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2218 23:21:53.566986 SELPH_MODE 0: By rank 1: By Phase
2219 23:21:53.570193 ==============================================================
2220 23:21:53.573626 GAT_TRACK_EN = 1
2221 23:21:53.577132 RX_GATING_MODE = 2
2222 23:21:53.580214 RX_GATING_TRACK_MODE = 2
2223 23:21:53.583876 SELPH_MODE = 1
2224 23:21:53.587176 PICG_EARLY_EN = 1
2225 23:21:53.590306 VALID_LAT_VALUE = 1
2226 23:21:53.593931 ==============================================================
2227 23:21:53.600491 Enter into Gating configuration >>>>
2228 23:21:53.600624 Exit from Gating configuration <<<<
2229 23:21:53.603724 Enter into DVFS_PRE_config >>>>>
2230 23:21:53.616999 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2231 23:21:53.620183 Exit from DVFS_PRE_config <<<<<
2232 23:21:53.623801 Enter into PICG configuration >>>>
2233 23:21:53.623946 Exit from PICG configuration <<<<
2234 23:21:53.627246 [RX_INPUT] configuration >>>>>
2235 23:21:53.630456 [RX_INPUT] configuration <<<<<
2236 23:21:53.637191 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2237 23:21:53.640720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2238 23:21:53.647287 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 23:21:53.654024 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 23:21:53.660437 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 23:21:53.667246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 23:21:53.670527 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2243 23:21:53.674112 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2244 23:21:53.677432 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2245 23:21:53.684082 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2246 23:21:53.687375 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2247 23:21:53.690600 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2248 23:21:53.694193 ===================================
2249 23:21:53.697400 LPDDR4 DRAM CONFIGURATION
2250 23:21:53.700624 ===================================
2251 23:21:53.700732 EX_ROW_EN[0] = 0x0
2252 23:21:53.703965 EX_ROW_EN[1] = 0x0
2253 23:21:53.707165 LP4Y_EN = 0x0
2254 23:21:53.707262 WORK_FSP = 0x0
2255 23:21:53.710797 WL = 0x4
2256 23:21:53.710891 RL = 0x4
2257 23:21:53.713977 BL = 0x2
2258 23:21:53.714069 RPST = 0x0
2259 23:21:53.717625 RD_PRE = 0x0
2260 23:21:53.717718 WR_PRE = 0x1
2261 23:21:53.720976 WR_PST = 0x0
2262 23:21:53.721065 DBI_WR = 0x0
2263 23:21:53.724233 DBI_RD = 0x0
2264 23:21:53.724341 OTF = 0x1
2265 23:21:53.727800 ===================================
2266 23:21:53.730946 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2267 23:21:53.737832 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2268 23:21:53.740872 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2269 23:21:53.744445 ===================================
2270 23:21:53.747527 LPDDR4 DRAM CONFIGURATION
2271 23:21:53.750913 ===================================
2272 23:21:53.751018 EX_ROW_EN[0] = 0x10
2273 23:21:53.754504 EX_ROW_EN[1] = 0x0
2274 23:21:53.754598 LP4Y_EN = 0x0
2275 23:21:53.757539 WORK_FSP = 0x0
2276 23:21:53.757630 WL = 0x4
2277 23:21:53.760821 RL = 0x4
2278 23:21:53.760913 BL = 0x2
2279 23:21:53.764252 RPST = 0x0
2280 23:21:53.764353 RD_PRE = 0x0
2281 23:21:53.767498 WR_PRE = 0x1
2282 23:21:53.767589 WR_PST = 0x0
2283 23:21:53.770875 DBI_WR = 0x0
2284 23:21:53.774491 DBI_RD = 0x0
2285 23:21:53.774590 OTF = 0x1
2286 23:21:53.777676 ===================================
2287 23:21:53.784346 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2288 23:21:53.784460 ==
2289 23:21:53.787457 Dram Type= 6, Freq= 0, CH_0, rank 0
2290 23:21:53.791051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2291 23:21:53.791165 ==
2292 23:21:53.794231 [Duty_Offset_Calibration]
2293 23:21:53.794352 B0:2 B1:1 CA:1
2294 23:21:53.794446
2295 23:21:53.797440 [DutyScan_Calibration_Flow] k_type=0
2296 23:21:53.808170
2297 23:21:53.808334 ==CLK 0==
2298 23:21:53.811594 Final CLK duty delay cell = 0
2299 23:21:53.814901 [0] MAX Duty = 5187%(X100), DQS PI = 24
2300 23:21:53.818209 [0] MIN Duty = 4844%(X100), DQS PI = 48
2301 23:21:53.818346 [0] AVG Duty = 5015%(X100)
2302 23:21:53.821828
2303 23:21:53.825050 CH0 CLK Duty spec in!! Max-Min= 343%
2304 23:21:53.828244 [DutyScan_Calibration_Flow] ====Done====
2305 23:21:53.828391
2306 23:21:53.831431 [DutyScan_Calibration_Flow] k_type=1
2307 23:21:53.846206
2308 23:21:53.846369 ==DQS 0 ==
2309 23:21:53.849379 Final DQS duty delay cell = -4
2310 23:21:53.852823 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2311 23:21:53.856063 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2312 23:21:53.859514 [-4] AVG Duty = 4937%(X100)
2313 23:21:53.859659
2314 23:21:53.859772 ==DQS 1 ==
2315 23:21:53.862855 Final DQS duty delay cell = -4
2316 23:21:53.866049 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2317 23:21:53.869626 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2318 23:21:53.872713 [-4] AVG Duty = 4906%(X100)
2319 23:21:53.872805
2320 23:21:53.876316 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2321 23:21:53.876418
2322 23:21:53.879723 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2323 23:21:53.883017 [DutyScan_Calibration_Flow] ====Done====
2324 23:21:53.883206
2325 23:21:53.886308 [DutyScan_Calibration_Flow] k_type=3
2326 23:21:53.903209
2327 23:21:53.903404 ==DQM 0 ==
2328 23:21:53.906812 Final DQM duty delay cell = 0
2329 23:21:53.910064 [0] MAX Duty = 5156%(X100), DQS PI = 30
2330 23:21:53.913295 [0] MIN Duty = 4906%(X100), DQS PI = 58
2331 23:21:53.916810 [0] AVG Duty = 5031%(X100)
2332 23:21:53.916959
2333 23:21:53.917069 ==DQM 1 ==
2334 23:21:53.919858 Final DQM duty delay cell = 0
2335 23:21:53.923481 [0] MAX Duty = 5093%(X100), DQS PI = 0
2336 23:21:53.926726 [0] MIN Duty = 5031%(X100), DQS PI = 14
2337 23:21:53.926848 [0] AVG Duty = 5062%(X100)
2338 23:21:53.929927
2339 23:21:53.933175 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2340 23:21:53.933312
2341 23:21:53.936812 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2342 23:21:53.940024 [DutyScan_Calibration_Flow] ====Done====
2343 23:21:53.940182
2344 23:21:53.943206 [DutyScan_Calibration_Flow] k_type=2
2345 23:21:53.959556
2346 23:21:53.959731 ==DQ 0 ==
2347 23:21:53.962940 Final DQ duty delay cell = 0
2348 23:21:53.966302 [0] MAX Duty = 5031%(X100), DQS PI = 26
2349 23:21:53.969834 [0] MIN Duty = 4875%(X100), DQS PI = 62
2350 23:21:53.970013 [0] AVG Duty = 4953%(X100)
2351 23:21:53.972927
2352 23:21:53.973072 ==DQ 1 ==
2353 23:21:53.976351 Final DQ duty delay cell = 0
2354 23:21:53.979842 [0] MAX Duty = 5093%(X100), DQS PI = 24
2355 23:21:53.982949 [0] MIN Duty = 4907%(X100), DQS PI = 36
2356 23:21:53.983050 [0] AVG Duty = 5000%(X100)
2357 23:21:53.983118
2358 23:21:53.986316 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2359 23:21:53.989832
2360 23:21:53.992905 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2361 23:21:53.996432 [DutyScan_Calibration_Flow] ====Done====
2362 23:21:53.996582 ==
2363 23:21:53.999553 Dram Type= 6, Freq= 0, CH_1, rank 0
2364 23:21:54.003021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2365 23:21:54.003135 ==
2366 23:21:54.006316 [Duty_Offset_Calibration]
2367 23:21:54.006452 B0:1 B1:0 CA:0
2368 23:21:54.006594
2369 23:21:54.009605 [DutyScan_Calibration_Flow] k_type=0
2370 23:21:54.019014
2371 23:21:54.019150 ==CLK 0==
2372 23:21:54.022649 Final CLK duty delay cell = -4
2373 23:21:54.025520 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2374 23:21:54.029128 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2375 23:21:54.032314 [-4] AVG Duty = 4969%(X100)
2376 23:21:54.032426
2377 23:21:54.035929 CH1 CLK Duty spec in!! Max-Min= 124%
2378 23:21:54.039140 [DutyScan_Calibration_Flow] ====Done====
2379 23:21:54.039266
2380 23:21:54.042422 [DutyScan_Calibration_Flow] k_type=1
2381 23:21:54.058900
2382 23:21:54.059043 ==DQS 0 ==
2383 23:21:54.061997 Final DQS duty delay cell = 0
2384 23:21:54.065147 [0] MAX Duty = 5094%(X100), DQS PI = 28
2385 23:21:54.068662 [0] MIN Duty = 4844%(X100), DQS PI = 0
2386 23:21:54.068783 [0] AVG Duty = 4969%(X100)
2387 23:21:54.072435
2388 23:21:54.072531 ==DQS 1 ==
2389 23:21:54.075370 Final DQS duty delay cell = 0
2390 23:21:54.078818 [0] MAX Duty = 5187%(X100), DQS PI = 20
2391 23:21:54.081849 [0] MIN Duty = 4969%(X100), DQS PI = 10
2392 23:21:54.081957 [0] AVG Duty = 5078%(X100)
2393 23:21:54.085613
2394 23:21:54.088762 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2395 23:21:54.088848
2396 23:21:54.091937 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2397 23:21:54.095551 [DutyScan_Calibration_Flow] ====Done====
2398 23:21:54.095706
2399 23:21:54.098623 [DutyScan_Calibration_Flow] k_type=3
2400 23:21:54.115473
2401 23:21:54.115615 ==DQM 0 ==
2402 23:21:54.118688 Final DQM duty delay cell = 0
2403 23:21:54.121906 [0] MAX Duty = 5156%(X100), DQS PI = 8
2404 23:21:54.125230 [0] MIN Duty = 5000%(X100), DQS PI = 0
2405 23:21:54.125330 [0] AVG Duty = 5078%(X100)
2406 23:21:54.128600
2407 23:21:54.128744 ==DQM 1 ==
2408 23:21:54.131676 Final DQM duty delay cell = 0
2409 23:21:54.135200 [0] MAX Duty = 5031%(X100), DQS PI = 26
2410 23:21:54.138862 [0] MIN Duty = 4907%(X100), DQS PI = 34
2411 23:21:54.139007 [0] AVG Duty = 4969%(X100)
2412 23:21:54.141976
2413 23:21:54.145202 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2414 23:21:54.145326
2415 23:21:54.148374 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2416 23:21:54.151818 [DutyScan_Calibration_Flow] ====Done====
2417 23:21:54.151957
2418 23:21:54.154913 [DutyScan_Calibration_Flow] k_type=2
2419 23:21:54.170998
2420 23:21:54.171189 ==DQ 0 ==
2421 23:21:54.174239 Final DQ duty delay cell = -4
2422 23:21:54.177589 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2423 23:21:54.181218 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2424 23:21:54.184229 [-4] AVG Duty = 5000%(X100)
2425 23:21:54.184368
2426 23:21:54.184472 ==DQ 1 ==
2427 23:21:54.187671 Final DQ duty delay cell = 0
2428 23:21:54.191253 [0] MAX Duty = 5125%(X100), DQS PI = 18
2429 23:21:54.194487 [0] MIN Duty = 4969%(X100), DQS PI = 12
2430 23:21:54.197534 [0] AVG Duty = 5047%(X100)
2431 23:21:54.197673
2432 23:21:54.201028 CH1 DQ 0 Duty spec in!! Max-Min= 188%
2433 23:21:54.201159
2434 23:21:54.204191 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2435 23:21:54.207715 [DutyScan_Calibration_Flow] ====Done====
2436 23:21:54.211218 nWR fixed to 30
2437 23:21:54.211369 [ModeRegInit_LP4] CH0 RK0
2438 23:21:54.214253 [ModeRegInit_LP4] CH0 RK1
2439 23:21:54.217855 [ModeRegInit_LP4] CH1 RK0
2440 23:21:54.221139 [ModeRegInit_LP4] CH1 RK1
2441 23:21:54.221278 match AC timing 7
2442 23:21:54.224307 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2443 23:21:54.230914 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2444 23:21:54.234284 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2445 23:21:54.241201 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2446 23:21:54.244339 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2447 23:21:54.244438 ==
2448 23:21:54.247634 Dram Type= 6, Freq= 0, CH_0, rank 0
2449 23:21:54.251136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2450 23:21:54.251266 ==
2451 23:21:54.257868 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2452 23:21:54.264237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2453 23:21:54.271414 [CA 0] Center 39 (8~70) winsize 63
2454 23:21:54.274847 [CA 1] Center 39 (8~70) winsize 63
2455 23:21:54.278069 [CA 2] Center 35 (5~66) winsize 62
2456 23:21:54.281205 [CA 3] Center 34 (4~65) winsize 62
2457 23:21:54.284206 [CA 4] Center 33 (3~64) winsize 62
2458 23:21:54.287593 [CA 5] Center 32 (3~62) winsize 60
2459 23:21:54.287697
2460 23:21:54.291164 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2461 23:21:54.291259
2462 23:21:54.294566 [CATrainingPosCal] consider 1 rank data
2463 23:21:54.297774 u2DelayCellTimex100 = 270/100 ps
2464 23:21:54.301218 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2465 23:21:54.307571 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2466 23:21:54.311164 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2467 23:21:54.314432 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2468 23:21:54.317787 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2469 23:21:54.321261 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2470 23:21:54.321355
2471 23:21:54.324713 CA PerBit enable=1, Macro0, CA PI delay=32
2472 23:21:54.324797
2473 23:21:54.327812 [CBTSetCACLKResult] CA Dly = 32
2474 23:21:54.327914 CS Dly: 6 (0~37)
2475 23:21:54.331014 ==
2476 23:21:54.334407 Dram Type= 6, Freq= 0, CH_0, rank 1
2477 23:21:54.337707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2478 23:21:54.337827 ==
2479 23:21:54.341329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2480 23:21:54.347903 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2481 23:21:54.357008 [CA 0] Center 38 (8~69) winsize 62
2482 23:21:54.360497 [CA 1] Center 38 (8~69) winsize 62
2483 23:21:54.363658 [CA 2] Center 35 (4~66) winsize 63
2484 23:21:54.367170 [CA 3] Center 34 (4~65) winsize 62
2485 23:21:54.370744 [CA 4] Center 33 (3~64) winsize 62
2486 23:21:54.373750 [CA 5] Center 32 (3~62) winsize 60
2487 23:21:54.373853
2488 23:21:54.377093 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2489 23:21:54.377196
2490 23:21:54.380779 [CATrainingPosCal] consider 2 rank data
2491 23:21:54.383755 u2DelayCellTimex100 = 270/100 ps
2492 23:21:54.387466 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2493 23:21:54.390594 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2494 23:21:54.397291 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2495 23:21:54.400409 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2496 23:21:54.403970 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2497 23:21:54.407000 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2498 23:21:54.407096
2499 23:21:54.410675 CA PerBit enable=1, Macro0, CA PI delay=32
2500 23:21:54.410769
2501 23:21:54.413916 [CBTSetCACLKResult] CA Dly = 32
2502 23:21:54.414009 CS Dly: 6 (0~38)
2503 23:21:54.414076
2504 23:21:54.417204 ----->DramcWriteLeveling(PI) begin...
2505 23:21:54.420415 ==
2506 23:21:54.420511 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 23:21:54.427505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 23:21:54.427622 ==
2509 23:21:54.430794 Write leveling (Byte 0): 33 => 33
2510 23:21:54.433949 Write leveling (Byte 1): 30 => 30
2511 23:21:54.434049 DramcWriteLeveling(PI) end<-----
2512 23:21:54.437070
2513 23:21:54.437162 ==
2514 23:21:54.440587 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 23:21:54.443720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 23:21:54.443820 ==
2517 23:21:54.447348 [Gating] SW mode calibration
2518 23:21:54.454046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2519 23:21:54.457541 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2520 23:21:54.463808 0 15 0 | B1->B0 | 2424 3232 | 0 1 | (0 0) (1 1)
2521 23:21:54.467186 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2522 23:21:54.470636 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 23:21:54.477467 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 23:21:54.480663 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 23:21:54.483927 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 23:21:54.490839 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2527 23:21:54.493922 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
2528 23:21:54.497589 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2529 23:21:54.504261 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 23:21:54.507525 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 23:21:54.510662 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 23:21:54.514432 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 23:21:54.520763 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 23:21:54.524562 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2535 23:21:54.527726 1 0 28 | B1->B0 | 2d2d 4646 | 0 0 | (1 1) (0 0)
2536 23:21:54.534507 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2537 23:21:54.537579 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 23:21:54.540880 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 23:21:54.547970 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 23:21:54.551173 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 23:21:54.554624 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 23:21:54.560971 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 23:21:54.564465 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2544 23:21:54.567761 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2545 23:21:54.574549 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 23:21:54.577988 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 23:21:54.581064 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 23:21:54.584716 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 23:21:54.591438 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 23:21:54.594435 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 23:21:54.597683 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 23:21:54.604305 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 23:21:54.608030 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 23:21:54.611021 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 23:21:54.617975 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 23:21:54.621378 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 23:21:54.624647 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 23:21:54.631429 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2559 23:21:54.634689 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2560 23:21:54.637847 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 23:21:54.641082 Total UI for P1: 0, mck2ui 16
2562 23:21:54.644296 best dqsien dly found for B0: ( 1, 3, 26)
2563 23:21:54.647962 Total UI for P1: 0, mck2ui 16
2564 23:21:54.651057 best dqsien dly found for B1: ( 1, 3, 30)
2565 23:21:54.654456 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2566 23:21:54.657770 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2567 23:21:54.657857
2568 23:21:54.661087 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2569 23:21:54.667789 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2570 23:21:54.667904 [Gating] SW calibration Done
2571 23:21:54.671323 ==
2572 23:21:54.671414 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 23:21:54.677505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 23:21:54.677590 ==
2575 23:21:54.677674 RX Vref Scan: 0
2576 23:21:54.677737
2577 23:21:54.680958 RX Vref 0 -> 0, step: 1
2578 23:21:54.681042
2579 23:21:54.684528 RX Delay -40 -> 252, step: 8
2580 23:21:54.687502 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2581 23:21:54.691194 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2582 23:21:54.694201 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2583 23:21:54.700937 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2584 23:21:54.704447 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2585 23:21:54.707803 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2586 23:21:54.711067 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2587 23:21:54.714211 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2588 23:21:54.721324 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2589 23:21:54.724319 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2590 23:21:54.727466 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2591 23:21:54.731215 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2592 23:21:54.734311 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2593 23:21:54.740959 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2594 23:21:54.744181 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2595 23:21:54.747833 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2596 23:21:54.747958 ==
2597 23:21:54.750907 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 23:21:54.754187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 23:21:54.754313 ==
2600 23:21:54.757831 DQS Delay:
2601 23:21:54.757954 DQS0 = 0, DQS1 = 0
2602 23:21:54.761007 DQM Delay:
2603 23:21:54.761133 DQM0 = 121, DQM1 = 114
2604 23:21:54.761243 DQ Delay:
2605 23:21:54.764578 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2606 23:21:54.770897 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2607 23:21:54.774238 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2608 23:21:54.777649 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2609 23:21:54.777781
2610 23:21:54.777898
2611 23:21:54.778008 ==
2612 23:21:54.781333 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 23:21:54.784235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 23:21:54.784379 ==
2615 23:21:54.784493
2616 23:21:54.784606
2617 23:21:54.787711 TX Vref Scan disable
2618 23:21:54.791065 == TX Byte 0 ==
2619 23:21:54.794399 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2620 23:21:54.797856 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2621 23:21:54.801202 == TX Byte 1 ==
2622 23:21:54.804622 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2623 23:21:54.807905 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2624 23:21:54.808029 ==
2625 23:21:54.811200 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 23:21:54.814270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 23:21:54.814383 ==
2628 23:21:54.827641 TX Vref=22, minBit 4, minWin=24, winSum=405
2629 23:21:54.830847 TX Vref=24, minBit 1, minWin=25, winSum=415
2630 23:21:54.834120 TX Vref=26, minBit 12, minWin=25, winSum=419
2631 23:21:54.837538 TX Vref=28, minBit 0, minWin=26, winSum=423
2632 23:21:54.840901 TX Vref=30, minBit 0, minWin=26, winSum=424
2633 23:21:54.847600 TX Vref=32, minBit 13, minWin=25, winSum=425
2634 23:21:54.850689 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
2635 23:21:54.850797
2636 23:21:54.854265 Final TX Range 1 Vref 30
2637 23:21:54.854343
2638 23:21:54.854442 ==
2639 23:21:54.857437 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 23:21:54.860689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 23:21:54.860790 ==
2642 23:21:54.863935
2643 23:21:54.864018
2644 23:21:54.864118 TX Vref Scan disable
2645 23:21:54.867174 == TX Byte 0 ==
2646 23:21:54.870808 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2647 23:21:54.877440 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2648 23:21:54.877561 == TX Byte 1 ==
2649 23:21:54.880527 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2650 23:21:54.887314 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2651 23:21:54.887425
2652 23:21:54.887511 [DATLAT]
2653 23:21:54.887614 Freq=1200, CH0 RK0
2654 23:21:54.887712
2655 23:21:54.890505 DATLAT Default: 0xd
2656 23:21:54.890609 0, 0xFFFF, sum = 0
2657 23:21:54.894036 1, 0xFFFF, sum = 0
2658 23:21:54.894140 2, 0xFFFF, sum = 0
2659 23:21:54.897385 3, 0xFFFF, sum = 0
2660 23:21:54.900782 4, 0xFFFF, sum = 0
2661 23:21:54.900868 5, 0xFFFF, sum = 0
2662 23:21:54.903689 6, 0xFFFF, sum = 0
2663 23:21:54.903793 7, 0xFFFF, sum = 0
2664 23:21:54.907279 8, 0xFFFF, sum = 0
2665 23:21:54.907385 9, 0xFFFF, sum = 0
2666 23:21:54.910306 10, 0xFFFF, sum = 0
2667 23:21:54.910387 11, 0xFFFF, sum = 0
2668 23:21:54.913860 12, 0x0, sum = 1
2669 23:21:54.913944 13, 0x0, sum = 2
2670 23:21:54.916911 14, 0x0, sum = 3
2671 23:21:54.916993 15, 0x0, sum = 4
2672 23:21:54.920303 best_step = 13
2673 23:21:54.920406
2674 23:21:54.920506 ==
2675 23:21:54.923935 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 23:21:54.927165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 23:21:54.927245 ==
2678 23:21:54.927328 RX Vref Scan: 1
2679 23:21:54.927427
2680 23:21:54.930372 Set Vref Range= 32 -> 127
2681 23:21:54.930457
2682 23:21:54.933911 RX Vref 32 -> 127, step: 1
2683 23:21:54.933996
2684 23:21:54.937229 RX Delay -13 -> 252, step: 4
2685 23:21:54.937307
2686 23:21:54.940435 Set Vref, RX VrefLevel [Byte0]: 32
2687 23:21:54.943906 [Byte1]: 32
2688 23:21:54.943978
2689 23:21:54.947244 Set Vref, RX VrefLevel [Byte0]: 33
2690 23:21:54.950197 [Byte1]: 33
2691 23:21:54.953991
2692 23:21:54.954094 Set Vref, RX VrefLevel [Byte0]: 34
2693 23:21:54.957237 [Byte1]: 34
2694 23:21:54.961860
2695 23:21:54.961964 Set Vref, RX VrefLevel [Byte0]: 35
2696 23:21:54.965109 [Byte1]: 35
2697 23:21:54.969689
2698 23:21:54.969798 Set Vref, RX VrefLevel [Byte0]: 36
2699 23:21:54.972856 [Byte1]: 36
2700 23:21:54.977285
2701 23:21:54.977391 Set Vref, RX VrefLevel [Byte0]: 37
2702 23:21:54.980767 [Byte1]: 37
2703 23:21:54.985206
2704 23:21:54.985283 Set Vref, RX VrefLevel [Byte0]: 38
2705 23:21:54.988434 [Byte1]: 38
2706 23:21:54.993283
2707 23:21:54.993394 Set Vref, RX VrefLevel [Byte0]: 39
2708 23:21:54.996535 [Byte1]: 39
2709 23:21:55.001128
2710 23:21:55.001213 Set Vref, RX VrefLevel [Byte0]: 40
2711 23:21:55.004201 [Byte1]: 40
2712 23:21:55.009171
2713 23:21:55.009253 Set Vref, RX VrefLevel [Byte0]: 41
2714 23:21:55.012397 [Byte1]: 41
2715 23:21:55.017033
2716 23:21:55.017120 Set Vref, RX VrefLevel [Byte0]: 42
2717 23:21:55.020085 [Byte1]: 42
2718 23:21:55.024798
2719 23:21:55.024904 Set Vref, RX VrefLevel [Byte0]: 43
2720 23:21:55.028174 [Byte1]: 43
2721 23:21:55.032881
2722 23:21:55.032990 Set Vref, RX VrefLevel [Byte0]: 44
2723 23:21:55.036221 [Byte1]: 44
2724 23:21:55.040483
2725 23:21:55.040569 Set Vref, RX VrefLevel [Byte0]: 45
2726 23:21:55.043869 [Byte1]: 45
2727 23:21:55.048315
2728 23:21:55.048442 Set Vref, RX VrefLevel [Byte0]: 46
2729 23:21:55.051883 [Byte1]: 46
2730 23:21:55.056197
2731 23:21:55.056327 Set Vref, RX VrefLevel [Byte0]: 47
2732 23:21:55.059469 [Byte1]: 47
2733 23:21:55.064294
2734 23:21:55.064402 Set Vref, RX VrefLevel [Byte0]: 48
2735 23:21:55.067357 [Byte1]: 48
2736 23:21:55.071913
2737 23:21:55.072013 Set Vref, RX VrefLevel [Byte0]: 49
2738 23:21:55.075533 [Byte1]: 49
2739 23:21:55.080164
2740 23:21:55.080267 Set Vref, RX VrefLevel [Byte0]: 50
2741 23:21:55.083341 [Byte1]: 50
2742 23:21:55.087926
2743 23:21:55.088003 Set Vref, RX VrefLevel [Byte0]: 51
2744 23:21:55.091110 [Byte1]: 51
2745 23:21:55.095903
2746 23:21:55.096002 Set Vref, RX VrefLevel [Byte0]: 52
2747 23:21:55.099026 [Byte1]: 52
2748 23:21:55.103528
2749 23:21:55.103603 Set Vref, RX VrefLevel [Byte0]: 53
2750 23:21:55.106758 [Byte1]: 53
2751 23:21:55.111541
2752 23:21:55.111622 Set Vref, RX VrefLevel [Byte0]: 54
2753 23:21:55.114787 [Byte1]: 54
2754 23:21:55.119369
2755 23:21:55.119478 Set Vref, RX VrefLevel [Byte0]: 55
2756 23:21:55.122860 [Byte1]: 55
2757 23:21:55.127199
2758 23:21:55.127316 Set Vref, RX VrefLevel [Byte0]: 56
2759 23:21:55.130435 [Byte1]: 56
2760 23:21:55.135289
2761 23:21:55.135392 Set Vref, RX VrefLevel [Byte0]: 57
2762 23:21:55.138586 [Byte1]: 57
2763 23:21:55.142953
2764 23:21:55.143064 Set Vref, RX VrefLevel [Byte0]: 58
2765 23:21:55.146530 [Byte1]: 58
2766 23:21:55.150853
2767 23:21:55.150958 Set Vref, RX VrefLevel [Byte0]: 59
2768 23:21:55.154233 [Byte1]: 59
2769 23:21:55.158690
2770 23:21:55.158777 Set Vref, RX VrefLevel [Byte0]: 60
2771 23:21:55.162214 [Byte1]: 60
2772 23:21:55.166848
2773 23:21:55.166952 Set Vref, RX VrefLevel [Byte0]: 61
2774 23:21:55.169914 [Byte1]: 61
2775 23:21:55.174497
2776 23:21:55.174580 Set Vref, RX VrefLevel [Byte0]: 62
2777 23:21:55.177969 [Byte1]: 62
2778 23:21:55.182669
2779 23:21:55.182790 Set Vref, RX VrefLevel [Byte0]: 63
2780 23:21:55.185738 [Byte1]: 63
2781 23:21:55.190476
2782 23:21:55.190568 Set Vref, RX VrefLevel [Byte0]: 64
2783 23:21:55.193690 [Byte1]: 64
2784 23:21:55.198217
2785 23:21:55.198322 Set Vref, RX VrefLevel [Byte0]: 65
2786 23:21:55.201713 [Byte1]: 65
2787 23:21:55.206347
2788 23:21:55.206476 Set Vref, RX VrefLevel [Byte0]: 66
2789 23:21:55.209573 [Byte1]: 66
2790 23:21:55.213991
2791 23:21:55.214162 Set Vref, RX VrefLevel [Byte0]: 67
2792 23:21:55.217434 [Byte1]: 67
2793 23:21:55.221875
2794 23:21:55.221990 Set Vref, RX VrefLevel [Byte0]: 68
2795 23:21:55.225161 [Byte1]: 68
2796 23:21:55.230064
2797 23:21:55.230149 Set Vref, RX VrefLevel [Byte0]: 69
2798 23:21:55.233145 [Byte1]: 69
2799 23:21:55.238036
2800 23:21:55.238122 Final RX Vref Byte 0 = 56 to rank0
2801 23:21:55.241270 Final RX Vref Byte 1 = 47 to rank0
2802 23:21:55.244278 Final RX Vref Byte 0 = 56 to rank1
2803 23:21:55.247727 Final RX Vref Byte 1 = 47 to rank1==
2804 23:21:55.251226 Dram Type= 6, Freq= 0, CH_0, rank 0
2805 23:21:55.257772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2806 23:21:55.257921 ==
2807 23:21:55.258039 DQS Delay:
2808 23:21:55.258155 DQS0 = 0, DQS1 = 0
2809 23:21:55.261289 DQM Delay:
2810 23:21:55.261406 DQM0 = 120, DQM1 = 110
2811 23:21:55.264616 DQ Delay:
2812 23:21:55.267639 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =118
2813 23:21:55.271270 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2814 23:21:55.274480 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =102
2815 23:21:55.278075 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2816 23:21:55.278194
2817 23:21:55.278292
2818 23:21:55.284625 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2819 23:21:55.287664 CH0 RK0: MR19=404, MR18=130C
2820 23:21:55.294463 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2821 23:21:55.294585
2822 23:21:55.298000 ----->DramcWriteLeveling(PI) begin...
2823 23:21:55.298112 ==
2824 23:21:55.301294 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 23:21:55.304447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 23:21:55.304538 ==
2827 23:21:55.307979 Write leveling (Byte 0): 33 => 33
2828 23:21:55.311200 Write leveling (Byte 1): 27 => 27
2829 23:21:55.314442 DramcWriteLeveling(PI) end<-----
2830 23:21:55.314545
2831 23:21:55.314636 ==
2832 23:21:55.318065 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 23:21:55.324604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 23:21:55.324687 ==
2835 23:21:55.324753 [Gating] SW mode calibration
2836 23:21:55.334886 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2837 23:21:55.338009 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2838 23:21:55.341694 0 15 0 | B1->B0 | 3434 302f | 1 1 | (1 1) (0 0)
2839 23:21:55.348108 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 23:21:55.351548 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 23:21:55.354744 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 23:21:55.361616 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 23:21:55.365021 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 23:21:55.368210 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 23:21:55.374944 0 15 28 | B1->B0 | 3232 3030 | 1 1 | (1 0) (1 0)
2846 23:21:55.377990 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
2847 23:21:55.381662 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 23:21:55.388370 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 23:21:55.391411 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 23:21:55.394799 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 23:21:55.398135 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 23:21:55.404962 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2853 23:21:55.408281 1 0 28 | B1->B0 | 3c3c 3b3a | 0 1 | (1 1) (0 0)
2854 23:21:55.411364 1 1 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (1 1)
2855 23:21:55.418215 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 23:21:55.421642 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 23:21:55.424834 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 23:21:55.431747 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 23:21:55.434674 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 23:21:55.438255 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2861 23:21:55.445251 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2862 23:21:55.448582 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2863 23:21:55.451689 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 23:21:55.458107 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 23:21:55.461668 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 23:21:55.464971 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 23:21:55.471419 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 23:21:55.475037 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 23:21:55.478069 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 23:21:55.485052 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 23:21:55.488360 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 23:21:55.491494 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 23:21:55.494946 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 23:21:55.501772 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 23:21:55.505084 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 23:21:55.508455 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 23:21:55.514665 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2878 23:21:55.518354 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2879 23:21:55.521448 Total UI for P1: 0, mck2ui 16
2880 23:21:55.525002 best dqsien dly found for B1: ( 1, 3, 28)
2881 23:21:55.528195 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 23:21:55.531476 Total UI for P1: 0, mck2ui 16
2883 23:21:55.535025 best dqsien dly found for B0: ( 1, 3, 30)
2884 23:21:55.538069 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2885 23:21:55.541426 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2886 23:21:55.541592
2887 23:21:55.548406 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2888 23:21:55.551578 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2889 23:21:55.551694 [Gating] SW calibration Done
2890 23:21:55.554769 ==
2891 23:21:55.558481 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 23:21:55.561500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 23:21:55.561603 ==
2894 23:21:55.561668 RX Vref Scan: 0
2895 23:21:55.561739
2896 23:21:55.565136 RX Vref 0 -> 0, step: 1
2897 23:21:55.565295
2898 23:21:55.568420 RX Delay -40 -> 252, step: 8
2899 23:21:55.571881 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2900 23:21:55.575043 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2901 23:21:55.578301 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2902 23:21:55.585071 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2903 23:21:55.588485 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2904 23:21:55.591864 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2905 23:21:55.595296 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2906 23:21:55.598498 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2907 23:21:55.601889 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2908 23:21:55.608329 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2909 23:21:55.611766 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2910 23:21:55.615005 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2911 23:21:55.618483 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2912 23:21:55.625315 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2913 23:21:55.628349 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2914 23:21:55.631974 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2915 23:21:55.632108 ==
2916 23:21:55.635262 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 23:21:55.638384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 23:21:55.638473 ==
2919 23:21:55.641993 DQS Delay:
2920 23:21:55.642078 DQS0 = 0, DQS1 = 0
2921 23:21:55.642142 DQM Delay:
2922 23:21:55.645205 DQM0 = 121, DQM1 = 111
2923 23:21:55.645281 DQ Delay:
2924 23:21:55.648767 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2925 23:21:55.652115 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2926 23:21:55.658668 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103
2927 23:21:55.661828 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2928 23:21:55.661945
2929 23:21:55.662039
2930 23:21:55.662133 ==
2931 23:21:55.665405 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 23:21:55.668313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 23:21:55.668393 ==
2934 23:21:55.668456
2935 23:21:55.668517
2936 23:21:55.671936 TX Vref Scan disable
2937 23:21:55.672070 == TX Byte 0 ==
2938 23:21:55.678498 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2939 23:21:55.681705 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2940 23:21:55.681803 == TX Byte 1 ==
2941 23:21:55.688519 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2942 23:21:55.691702 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2943 23:21:55.691830 ==
2944 23:21:55.695198 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 23:21:55.698347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 23:21:55.698481 ==
2947 23:21:55.711995 TX Vref=22, minBit 1, minWin=25, winSum=410
2948 23:21:55.715761 TX Vref=24, minBit 3, minWin=25, winSum=421
2949 23:21:55.718866 TX Vref=26, minBit 1, minWin=25, winSum=423
2950 23:21:55.722138 TX Vref=28, minBit 0, minWin=26, winSum=426
2951 23:21:55.725509 TX Vref=30, minBit 0, minWin=26, winSum=429
2952 23:21:55.728988 TX Vref=32, minBit 12, minWin=25, winSum=424
2953 23:21:55.735670 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 30
2954 23:21:55.735835
2955 23:21:55.738734 Final TX Range 1 Vref 30
2956 23:21:55.738859
2957 23:21:55.738971 ==
2958 23:21:55.742427 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 23:21:55.745660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 23:21:55.745792 ==
2961 23:21:55.745907
2962 23:21:55.746022
2963 23:21:55.748817 TX Vref Scan disable
2964 23:21:55.752387 == TX Byte 0 ==
2965 23:21:55.755539 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2966 23:21:55.759017 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2967 23:21:55.762428 == TX Byte 1 ==
2968 23:21:55.765690 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2969 23:21:55.768749 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2970 23:21:55.768881
2971 23:21:55.772196 [DATLAT]
2972 23:21:55.772344 Freq=1200, CH0 RK1
2973 23:21:55.772458
2974 23:21:55.775575 DATLAT Default: 0xd
2975 23:21:55.775729 0, 0xFFFF, sum = 0
2976 23:21:55.778705 1, 0xFFFF, sum = 0
2977 23:21:55.778835 2, 0xFFFF, sum = 0
2978 23:21:55.782030 3, 0xFFFF, sum = 0
2979 23:21:55.782159 4, 0xFFFF, sum = 0
2980 23:21:55.785738 5, 0xFFFF, sum = 0
2981 23:21:55.785864 6, 0xFFFF, sum = 0
2982 23:21:55.788878 7, 0xFFFF, sum = 0
2983 23:21:55.789003 8, 0xFFFF, sum = 0
2984 23:21:55.792071 9, 0xFFFF, sum = 0
2985 23:21:55.795416 10, 0xFFFF, sum = 0
2986 23:21:55.795543 11, 0xFFFF, sum = 0
2987 23:21:55.798649 12, 0x0, sum = 1
2988 23:21:55.798770 13, 0x0, sum = 2
2989 23:21:55.802158 14, 0x0, sum = 3
2990 23:21:55.802282 15, 0x0, sum = 4
2991 23:21:55.802400 best_step = 13
2992 23:21:55.802508
2993 23:21:55.805606 ==
2994 23:21:55.808789 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 23:21:55.812192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 23:21:55.812331 ==
2997 23:21:55.812443 RX Vref Scan: 0
2998 23:21:55.812561
2999 23:21:55.815596 RX Vref 0 -> 0, step: 1
3000 23:21:55.815718
3001 23:21:55.818694 RX Delay -13 -> 252, step: 4
3002 23:21:55.822344 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3003 23:21:55.825475 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3004 23:21:55.832357 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3005 23:21:55.835505 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3006 23:21:55.838918 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3007 23:21:55.842109 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3008 23:21:55.845448 iDelay=195, Bit 6, Center 126 (63 ~ 190) 128
3009 23:21:55.852080 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3010 23:21:55.855574 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3011 23:21:55.859191 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3012 23:21:55.862422 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3013 23:21:55.865540 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3014 23:21:55.872035 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3015 23:21:55.875375 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3016 23:21:55.878760 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3017 23:21:55.882144 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3018 23:21:55.882255 ==
3019 23:21:55.885488 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 23:21:55.892683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 23:21:55.892779 ==
3022 23:21:55.892845 DQS Delay:
3023 23:21:55.892905 DQS0 = 0, DQS1 = 0
3024 23:21:55.895420 DQM Delay:
3025 23:21:55.895491 DQM0 = 121, DQM1 = 109
3026 23:21:55.898986 DQ Delay:
3027 23:21:55.902308 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3028 23:21:55.905503 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3029 23:21:55.909054 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3030 23:21:55.912216 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =118
3031 23:21:55.912308
3032 23:21:55.912373
3033 23:21:55.918831 [DQSOSCAuto] RK1, (LSB)MR18= 0xded, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3034 23:21:55.922385 CH0 RK1: MR19=403, MR18=DED
3035 23:21:55.928786 CH0_RK1: MR19=0x403, MR18=0xDED, DQSOSC=405, MR23=63, INC=39, DEC=26
3036 23:21:55.931908 [RxdqsGatingPostProcess] freq 1200
3037 23:21:55.938765 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3038 23:21:55.942238 best DQS0 dly(2T, 0.5T) = (0, 11)
3039 23:21:55.942330 best DQS1 dly(2T, 0.5T) = (0, 11)
3040 23:21:55.945254 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3041 23:21:55.948863 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3042 23:21:55.952170 best DQS0 dly(2T, 0.5T) = (0, 11)
3043 23:21:55.955414 best DQS1 dly(2T, 0.5T) = (0, 11)
3044 23:21:55.958655 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3045 23:21:55.962012 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3046 23:21:55.965540 Pre-setting of DQS Precalculation
3047 23:21:55.972204 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3048 23:21:55.972349 ==
3049 23:21:55.975208 Dram Type= 6, Freq= 0, CH_1, rank 0
3050 23:21:55.978797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 23:21:55.978888 ==
3052 23:21:55.985587 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3053 23:21:55.988553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3054 23:21:55.998198 [CA 0] Center 37 (7~68) winsize 62
3055 23:21:56.001772 [CA 1] Center 37 (7~68) winsize 62
3056 23:21:56.004889 [CA 2] Center 35 (5~65) winsize 61
3057 23:21:56.008671 [CA 3] Center 35 (5~65) winsize 61
3058 23:21:56.011805 [CA 4] Center 34 (5~64) winsize 60
3059 23:21:56.015275 [CA 5] Center 33 (3~63) winsize 61
3060 23:21:56.015429
3061 23:21:56.018355 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3062 23:21:56.018483
3063 23:21:56.021886 [CATrainingPosCal] consider 1 rank data
3064 23:21:56.024988 u2DelayCellTimex100 = 270/100 ps
3065 23:21:56.028550 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3066 23:21:56.032131 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3067 23:21:56.035320 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3068 23:21:56.041901 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3069 23:21:56.045097 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3070 23:21:56.048509 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3071 23:21:56.048728
3072 23:21:56.052050 CA PerBit enable=1, Macro0, CA PI delay=33
3073 23:21:56.052170
3074 23:21:56.055310 [CBTSetCACLKResult] CA Dly = 33
3075 23:21:56.055436 CS Dly: 8 (0~39)
3076 23:21:56.055562 ==
3077 23:21:56.058558 Dram Type= 6, Freq= 0, CH_1, rank 1
3078 23:21:56.065195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 23:21:56.065329 ==
3080 23:21:56.068601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3081 23:21:56.075256 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3082 23:21:56.083918 [CA 0] Center 37 (7~68) winsize 62
3083 23:21:56.087218 [CA 1] Center 38 (8~68) winsize 61
3084 23:21:56.090515 [CA 2] Center 35 (5~65) winsize 61
3085 23:21:56.093924 [CA 3] Center 34 (4~65) winsize 62
3086 23:21:56.097252 [CA 4] Center 34 (4~65) winsize 62
3087 23:21:56.100596 [CA 5] Center 34 (4~64) winsize 61
3088 23:21:56.100682
3089 23:21:56.104024 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3090 23:21:56.104114
3091 23:21:56.107508 [CATrainingPosCal] consider 2 rank data
3092 23:21:56.110744 u2DelayCellTimex100 = 270/100 ps
3093 23:21:56.113927 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3094 23:21:56.117216 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3095 23:21:56.123836 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3096 23:21:56.127243 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3097 23:21:56.130442 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3098 23:21:56.133907 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3099 23:21:56.133998
3100 23:21:56.137453 CA PerBit enable=1, Macro0, CA PI delay=33
3101 23:21:56.137544
3102 23:21:56.140627 [CBTSetCACLKResult] CA Dly = 33
3103 23:21:56.140752 CS Dly: 8 (0~40)
3104 23:21:56.140849
3105 23:21:56.143766 ----->DramcWriteLeveling(PI) begin...
3106 23:21:56.147288 ==
3107 23:21:56.147396 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 23:21:56.153790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 23:21:56.153884 ==
3110 23:21:56.157436 Write leveling (Byte 0): 26 => 26
3111 23:21:56.160655 Write leveling (Byte 1): 28 => 28
3112 23:21:56.163903 DramcWriteLeveling(PI) end<-----
3113 23:21:56.164007
3114 23:21:56.164113 ==
3115 23:21:56.167105 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 23:21:56.170563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 23:21:56.170642 ==
3118 23:21:56.173632 [Gating] SW mode calibration
3119 23:21:56.180488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3120 23:21:56.183636 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3121 23:21:56.190637 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3122 23:21:56.194182 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 23:21:56.197390 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 23:21:56.203873 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 23:21:56.207578 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 23:21:56.210597 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 23:21:56.217298 0 15 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
3128 23:21:56.220816 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3129 23:21:56.224053 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 23:21:56.230478 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 23:21:56.233861 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 23:21:56.237505 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 23:21:56.244240 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 23:21:56.247401 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 23:21:56.250693 1 0 24 | B1->B0 | 2e2e 4140 | 0 1 | (0 0) (0 0)
3136 23:21:56.253859 1 0 28 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
3137 23:21:56.261005 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 23:21:56.264065 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 23:21:56.267760 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 23:21:56.274194 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 23:21:56.277376 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 23:21:56.280895 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 23:21:56.287370 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3144 23:21:56.291039 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3145 23:21:56.294200 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 23:21:56.300862 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 23:21:56.304132 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 23:21:56.307439 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 23:21:56.314288 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 23:21:56.317661 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 23:21:56.321158 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 23:21:56.327758 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 23:21:56.331227 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 23:21:56.334513 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 23:21:56.337536 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 23:21:56.344204 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 23:21:56.347655 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 23:21:56.351109 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 23:21:56.357546 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3160 23:21:56.361061 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3161 23:21:56.364330 Total UI for P1: 0, mck2ui 16
3162 23:21:56.367861 best dqsien dly found for B0: ( 1, 3, 24)
3163 23:21:56.370886 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 23:21:56.374596 Total UI for P1: 0, mck2ui 16
3165 23:21:56.377793 best dqsien dly found for B1: ( 1, 3, 26)
3166 23:21:56.381017 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3167 23:21:56.384408 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3168 23:21:56.384493
3169 23:21:56.387689 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3170 23:21:56.394603 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3171 23:21:56.394698 [Gating] SW calibration Done
3172 23:21:56.397813 ==
3173 23:21:56.397893 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 23:21:56.404642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 23:21:56.404744 ==
3176 23:21:56.404829 RX Vref Scan: 0
3177 23:21:56.404893
3178 23:21:56.407977 RX Vref 0 -> 0, step: 1
3179 23:21:56.408060
3180 23:21:56.411179 RX Delay -40 -> 252, step: 8
3181 23:21:56.414442 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3182 23:21:56.417997 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3183 23:21:56.421420 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3184 23:21:56.428089 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3185 23:21:56.431146 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3186 23:21:56.434683 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3187 23:21:56.437715 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3188 23:21:56.441071 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3189 23:21:56.447838 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
3190 23:21:56.451200 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3191 23:21:56.454595 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3192 23:21:56.457770 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3193 23:21:56.461369 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3194 23:21:56.467636 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3195 23:21:56.471112 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3196 23:21:56.474527 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3197 23:21:56.474639 ==
3198 23:21:56.477820 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 23:21:56.481435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 23:21:56.481575 ==
3201 23:21:56.484591 DQS Delay:
3202 23:21:56.484726 DQS0 = 0, DQS1 = 0
3203 23:21:56.488243 DQM Delay:
3204 23:21:56.488402 DQM0 = 119, DQM1 = 117
3205 23:21:56.488528 DQ Delay:
3206 23:21:56.491436 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3207 23:21:56.495011 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3208 23:21:56.501506 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =111
3209 23:21:56.504729 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3210 23:21:56.504871
3211 23:21:56.504967
3212 23:21:56.505082 ==
3213 23:21:56.507989 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 23:21:56.511688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 23:21:56.511811 ==
3216 23:21:56.511962
3217 23:21:56.512080
3218 23:21:56.514847 TX Vref Scan disable
3219 23:21:56.514961 == TX Byte 0 ==
3220 23:21:56.521671 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3221 23:21:56.524653 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3222 23:21:56.524761 == TX Byte 1 ==
3223 23:21:56.531411 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3224 23:21:56.534775 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3225 23:21:56.534916 ==
3226 23:21:56.538263 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 23:21:56.541490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 23:21:56.541599 ==
3229 23:21:56.554232 TX Vref=22, minBit 12, minWin=24, winSum=411
3230 23:21:56.557584 TX Vref=24, minBit 9, minWin=25, winSum=420
3231 23:21:56.561056 TX Vref=26, minBit 1, minWin=26, winSum=422
3232 23:21:56.564447 TX Vref=28, minBit 1, minWin=26, winSum=427
3233 23:21:56.567640 TX Vref=30, minBit 9, minWin=25, winSum=427
3234 23:21:56.574517 TX Vref=32, minBit 10, minWin=25, winSum=434
3235 23:21:56.577525 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
3236 23:21:56.577679
3237 23:21:56.580714 Final TX Range 1 Vref 28
3238 23:21:56.580804
3239 23:21:56.580866 ==
3240 23:21:56.584418 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 23:21:56.587530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 23:21:56.587659 ==
3243 23:21:56.587753
3244 23:21:56.591013
3245 23:21:56.591126 TX Vref Scan disable
3246 23:21:56.594251 == TX Byte 0 ==
3247 23:21:56.597818 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3248 23:21:56.600963 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3249 23:21:56.604279 == TX Byte 1 ==
3250 23:21:56.607813 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3251 23:21:56.610977 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3252 23:21:56.611084
3253 23:21:56.614144 [DATLAT]
3254 23:21:56.614244 Freq=1200, CH1 RK0
3255 23:21:56.614335
3256 23:21:56.617848 DATLAT Default: 0xd
3257 23:21:56.617922 0, 0xFFFF, sum = 0
3258 23:21:56.621032 1, 0xFFFF, sum = 0
3259 23:21:56.621126 2, 0xFFFF, sum = 0
3260 23:21:56.624552 3, 0xFFFF, sum = 0
3261 23:21:56.624632 4, 0xFFFF, sum = 0
3262 23:21:56.627919 5, 0xFFFF, sum = 0
3263 23:21:56.628023 6, 0xFFFF, sum = 0
3264 23:21:56.631217 7, 0xFFFF, sum = 0
3265 23:21:56.631319 8, 0xFFFF, sum = 0
3266 23:21:56.634137 9, 0xFFFF, sum = 0
3267 23:21:56.637638 10, 0xFFFF, sum = 0
3268 23:21:56.637750 11, 0xFFFF, sum = 0
3269 23:21:56.641049 12, 0x0, sum = 1
3270 23:21:56.641173 13, 0x0, sum = 2
3271 23:21:56.641268 14, 0x0, sum = 3
3272 23:21:56.644436 15, 0x0, sum = 4
3273 23:21:56.644520 best_step = 13
3274 23:21:56.644596
3275 23:21:56.647478 ==
3276 23:21:56.647571 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 23:21:56.654186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 23:21:56.654313 ==
3279 23:21:56.654414 RX Vref Scan: 1
3280 23:21:56.654508
3281 23:21:56.657641 Set Vref Range= 32 -> 127
3282 23:21:56.657750
3283 23:21:56.661012 RX Vref 32 -> 127, step: 1
3284 23:21:56.661131
3285 23:21:56.664350 RX Delay -5 -> 252, step: 4
3286 23:21:56.664456
3287 23:21:56.667939 Set Vref, RX VrefLevel [Byte0]: 32
3288 23:21:56.671170 [Byte1]: 32
3289 23:21:56.671274
3290 23:21:56.674552 Set Vref, RX VrefLevel [Byte0]: 33
3291 23:21:56.677764 [Byte1]: 33
3292 23:21:56.677872
3293 23:21:56.681069 Set Vref, RX VrefLevel [Byte0]: 34
3294 23:21:56.684255 [Byte1]: 34
3295 23:21:56.687955
3296 23:21:56.688068 Set Vref, RX VrefLevel [Byte0]: 35
3297 23:21:56.691494 [Byte1]: 35
3298 23:21:56.696108
3299 23:21:56.696213 Set Vref, RX VrefLevel [Byte0]: 36
3300 23:21:56.699120 [Byte1]: 36
3301 23:21:56.704115
3302 23:21:56.704229 Set Vref, RX VrefLevel [Byte0]: 37
3303 23:21:56.707411 [Byte1]: 37
3304 23:21:56.711629
3305 23:21:56.711762 Set Vref, RX VrefLevel [Byte0]: 38
3306 23:21:56.714863 [Byte1]: 38
3307 23:21:56.719503
3308 23:21:56.719632 Set Vref, RX VrefLevel [Byte0]: 39
3309 23:21:56.722773 [Byte1]: 39
3310 23:21:56.727253
3311 23:21:56.727371 Set Vref, RX VrefLevel [Byte0]: 40
3312 23:21:56.730801 [Byte1]: 40
3313 23:21:56.735258
3314 23:21:56.735362 Set Vref, RX VrefLevel [Byte0]: 41
3315 23:21:56.738609 [Byte1]: 41
3316 23:21:56.743084
3317 23:21:56.743201 Set Vref, RX VrefLevel [Byte0]: 42
3318 23:21:56.746246 [Byte1]: 42
3319 23:21:56.750966
3320 23:21:56.751071 Set Vref, RX VrefLevel [Byte0]: 43
3321 23:21:56.754196 [Byte1]: 43
3322 23:21:56.758650
3323 23:21:56.758763 Set Vref, RX VrefLevel [Byte0]: 44
3324 23:21:56.761940 [Byte1]: 44
3325 23:21:56.766564
3326 23:21:56.766650 Set Vref, RX VrefLevel [Byte0]: 45
3327 23:21:56.769769 [Byte1]: 45
3328 23:21:56.774590
3329 23:21:56.774698 Set Vref, RX VrefLevel [Byte0]: 46
3330 23:21:56.777702 [Byte1]: 46
3331 23:21:56.782134
3332 23:21:56.782239 Set Vref, RX VrefLevel [Byte0]: 47
3333 23:21:56.785881 [Byte1]: 47
3334 23:21:56.790052
3335 23:21:56.790157 Set Vref, RX VrefLevel [Byte0]: 48
3336 23:21:56.793413 [Byte1]: 48
3337 23:21:56.798155
3338 23:21:56.798259 Set Vref, RX VrefLevel [Byte0]: 49
3339 23:21:56.801522 [Byte1]: 49
3340 23:21:56.805980
3341 23:21:56.806067 Set Vref, RX VrefLevel [Byte0]: 50
3342 23:21:56.808990 [Byte1]: 50
3343 23:21:56.813923
3344 23:21:56.814023 Set Vref, RX VrefLevel [Byte0]: 51
3345 23:21:56.817139 [Byte1]: 51
3346 23:21:56.821866
3347 23:21:56.821949 Set Vref, RX VrefLevel [Byte0]: 52
3348 23:21:56.825067 [Byte1]: 52
3349 23:21:56.829722
3350 23:21:56.829805 Set Vref, RX VrefLevel [Byte0]: 53
3351 23:21:56.832857 [Byte1]: 53
3352 23:21:56.837312
3353 23:21:56.837394 Set Vref, RX VrefLevel [Byte0]: 54
3354 23:21:56.840367 [Byte1]: 54
3355 23:21:56.845404
3356 23:21:56.845516 Set Vref, RX VrefLevel [Byte0]: 55
3357 23:21:56.848521 [Byte1]: 55
3358 23:21:56.853052
3359 23:21:56.853163 Set Vref, RX VrefLevel [Byte0]: 56
3360 23:21:56.856334 [Byte1]: 56
3361 23:21:56.861108
3362 23:21:56.861197 Set Vref, RX VrefLevel [Byte0]: 57
3363 23:21:56.864482 [Byte1]: 57
3364 23:21:56.868508
3365 23:21:56.868601 Set Vref, RX VrefLevel [Byte0]: 58
3366 23:21:56.871819 [Byte1]: 58
3367 23:21:56.876446
3368 23:21:56.876540 Set Vref, RX VrefLevel [Byte0]: 59
3369 23:21:56.879713 [Byte1]: 59
3370 23:21:56.884409
3371 23:21:56.884532 Set Vref, RX VrefLevel [Byte0]: 60
3372 23:21:56.887700 [Byte1]: 60
3373 23:21:56.892352
3374 23:21:56.892445 Set Vref, RX VrefLevel [Byte0]: 61
3375 23:21:56.895599 [Byte1]: 61
3376 23:21:56.900120
3377 23:21:56.900232 Set Vref, RX VrefLevel [Byte0]: 62
3378 23:21:56.903350 [Byte1]: 62
3379 23:21:56.907918
3380 23:21:56.908026 Set Vref, RX VrefLevel [Byte0]: 63
3381 23:21:56.911173 [Byte1]: 63
3382 23:21:56.915685
3383 23:21:56.915801 Set Vref, RX VrefLevel [Byte0]: 64
3384 23:21:56.919172 [Byte1]: 64
3385 23:21:56.923668
3386 23:21:56.923787 Set Vref, RX VrefLevel [Byte0]: 65
3387 23:21:56.926906 [Byte1]: 65
3388 23:21:56.931541
3389 23:21:56.931650 Set Vref, RX VrefLevel [Byte0]: 66
3390 23:21:56.934761 [Byte1]: 66
3391 23:21:56.939549
3392 23:21:56.939672 Set Vref, RX VrefLevel [Byte0]: 67
3393 23:21:56.942667 [Byte1]: 67
3394 23:21:56.947025
3395 23:21:56.947141 Set Vref, RX VrefLevel [Byte0]: 68
3396 23:21:56.950687 [Byte1]: 68
3397 23:21:56.955013
3398 23:21:56.955120 Final RX Vref Byte 0 = 55 to rank0
3399 23:21:56.958267 Final RX Vref Byte 1 = 52 to rank0
3400 23:21:56.961884 Final RX Vref Byte 0 = 55 to rank1
3401 23:21:56.964991 Final RX Vref Byte 1 = 52 to rank1==
3402 23:21:56.968452 Dram Type= 6, Freq= 0, CH_1, rank 0
3403 23:21:56.971582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3404 23:21:56.975192 ==
3405 23:21:56.975299 DQS Delay:
3406 23:21:56.975392 DQS0 = 0, DQS1 = 0
3407 23:21:56.978215 DQM Delay:
3408 23:21:56.978319 DQM0 = 120, DQM1 = 117
3409 23:21:56.981885 DQ Delay:
3410 23:21:56.984974 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3411 23:21:56.988208 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =120
3412 23:21:56.991662 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3413 23:21:56.994984 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3414 23:21:56.995090
3415 23:21:56.995187
3416 23:21:57.001636 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3417 23:21:57.005211 CH1 RK0: MR19=304, MR18=FE11
3418 23:21:57.011540 CH1_RK0: MR19=0x304, MR18=0xFE11, DQSOSC=403, MR23=63, INC=40, DEC=26
3419 23:21:57.011634
3420 23:21:57.015129 ----->DramcWriteLeveling(PI) begin...
3421 23:21:57.015234 ==
3422 23:21:57.018334 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 23:21:57.021726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 23:21:57.025065 ==
3425 23:21:57.025156 Write leveling (Byte 0): 27 => 27
3426 23:21:57.028480 Write leveling (Byte 1): 29 => 29
3427 23:21:57.031731 DramcWriteLeveling(PI) end<-----
3428 23:21:57.031809
3429 23:21:57.031876 ==
3430 23:21:57.035042 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 23:21:57.041887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 23:21:57.041981 ==
3433 23:21:57.042048 [Gating] SW mode calibration
3434 23:21:57.051851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3435 23:21:57.055233 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3436 23:21:57.058452 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 23:21:57.064865 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 23:21:57.068489 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 23:21:57.071652 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 23:21:57.078239 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 23:21:57.081446 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3442 23:21:57.084905 0 15 24 | B1->B0 | 2b2b 3232 | 0 1 | (1 0) (1 0)
3443 23:21:57.091558 0 15 28 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 0)
3444 23:21:57.094812 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 23:21:57.098182 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 23:21:57.105002 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 23:21:57.108379 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 23:21:57.111485 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 23:21:57.118297 1 0 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3450 23:21:57.121537 1 0 24 | B1->B0 | 4242 2929 | 0 0 | (0 0) (0 0)
3451 23:21:57.125113 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 23:21:57.131397 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 23:21:57.134883 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 23:21:57.138457 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 23:21:57.144882 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 23:21:57.148198 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 23:21:57.151364 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3458 23:21:57.158400 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3459 23:21:57.161678 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3460 23:21:57.164947 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 23:21:57.171265 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 23:21:57.174757 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 23:21:57.177855 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 23:21:57.184549 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 23:21:57.187760 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 23:21:57.191454 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 23:21:57.197572 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 23:21:57.201175 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 23:21:57.204704 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 23:21:57.207775 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 23:21:57.214235 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 23:21:57.217796 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 23:21:57.224552 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3474 23:21:57.227733 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3475 23:21:57.230737 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 23:21:57.234332 Total UI for P1: 0, mck2ui 16
3477 23:21:57.237535 best dqsien dly found for B0: ( 1, 3, 24)
3478 23:21:57.241133 Total UI for P1: 0, mck2ui 16
3479 23:21:57.244549 best dqsien dly found for B1: ( 1, 3, 22)
3480 23:21:57.247722 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3481 23:21:57.251364 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3482 23:21:57.251444
3483 23:21:57.254568 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3484 23:21:57.257688 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3485 23:21:57.260983 [Gating] SW calibration Done
3486 23:21:57.261098 ==
3487 23:21:57.264672 Dram Type= 6, Freq= 0, CH_1, rank 1
3488 23:21:57.268246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 23:21:57.271147 ==
3490 23:21:57.271260 RX Vref Scan: 0
3491 23:21:57.271350
3492 23:21:57.274510 RX Vref 0 -> 0, step: 1
3493 23:21:57.274616
3494 23:21:57.277656 RX Delay -40 -> 252, step: 8
3495 23:21:57.281404 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3496 23:21:57.284367 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3497 23:21:57.287810 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3498 23:21:57.291131 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3499 23:21:57.298035 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3500 23:21:57.301028 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3501 23:21:57.304453 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3502 23:21:57.307762 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3503 23:21:57.310965 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3504 23:21:57.314718 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3505 23:21:57.321365 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3506 23:21:57.324536 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3507 23:21:57.328008 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3508 23:21:57.331348 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3509 23:21:57.337779 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3510 23:21:57.340941 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3511 23:21:57.341059 ==
3512 23:21:57.344193 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 23:21:57.347820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 23:21:57.347938 ==
3515 23:21:57.351297 DQS Delay:
3516 23:21:57.351408 DQS0 = 0, DQS1 = 0
3517 23:21:57.351501 DQM Delay:
3518 23:21:57.354441 DQM0 = 121, DQM1 = 118
3519 23:21:57.354515 DQ Delay:
3520 23:21:57.357659 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3521 23:21:57.360866 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3522 23:21:57.364467 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3523 23:21:57.370936 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3524 23:21:57.371042
3525 23:21:57.371111
3526 23:21:57.371173 ==
3527 23:21:57.374288 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 23:21:57.377758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 23:21:57.377870 ==
3530 23:21:57.377968
3531 23:21:57.378032
3532 23:21:57.380801 TX Vref Scan disable
3533 23:21:57.380935 == TX Byte 0 ==
3534 23:21:57.387429 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3535 23:21:57.390791 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3536 23:21:57.390942 == TX Byte 1 ==
3537 23:21:57.397568 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3538 23:21:57.400866 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3539 23:21:57.400963 ==
3540 23:21:57.404007 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 23:21:57.407287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 23:21:57.407375 ==
3543 23:21:57.419875 TX Vref=22, minBit 10, minWin=24, winSum=419
3544 23:21:57.423569 TX Vref=24, minBit 9, minWin=25, winSum=423
3545 23:21:57.426753 TX Vref=26, minBit 2, minWin=26, winSum=428
3546 23:21:57.429942 TX Vref=28, minBit 9, minWin=26, winSum=432
3547 23:21:57.433443 TX Vref=30, minBit 9, minWin=26, winSum=437
3548 23:21:57.440051 TX Vref=32, minBit 6, minWin=26, winSum=434
3549 23:21:57.443257 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3550 23:21:57.443393
3551 23:21:57.446556 Final TX Range 1 Vref 30
3552 23:21:57.446642
3553 23:21:57.446711 ==
3554 23:21:57.450232 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 23:21:57.453343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 23:21:57.453446 ==
3557 23:21:57.456262
3558 23:21:57.456354
3559 23:21:57.456418 TX Vref Scan disable
3560 23:21:57.460081 == TX Byte 0 ==
3561 23:21:57.463322 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3562 23:21:57.469643 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3563 23:21:57.469739 == TX Byte 1 ==
3564 23:21:57.472933 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3565 23:21:57.479697 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3566 23:21:57.479795
3567 23:21:57.479862 [DATLAT]
3568 23:21:57.479924 Freq=1200, CH1 RK1
3569 23:21:57.479984
3570 23:21:57.483214 DATLAT Default: 0xd
3571 23:21:57.483299 0, 0xFFFF, sum = 0
3572 23:21:57.486460 1, 0xFFFF, sum = 0
3573 23:21:57.489499 2, 0xFFFF, sum = 0
3574 23:21:57.489594 3, 0xFFFF, sum = 0
3575 23:21:57.492747 4, 0xFFFF, sum = 0
3576 23:21:57.492873 5, 0xFFFF, sum = 0
3577 23:21:57.496172 6, 0xFFFF, sum = 0
3578 23:21:57.496298 7, 0xFFFF, sum = 0
3579 23:21:57.499670 8, 0xFFFF, sum = 0
3580 23:21:57.499777 9, 0xFFFF, sum = 0
3581 23:21:57.502819 10, 0xFFFF, sum = 0
3582 23:21:57.502911 11, 0xFFFF, sum = 0
3583 23:21:57.506559 12, 0x0, sum = 1
3584 23:21:57.506670 13, 0x0, sum = 2
3585 23:21:57.509320 14, 0x0, sum = 3
3586 23:21:57.509414 15, 0x0, sum = 4
3587 23:21:57.513012 best_step = 13
3588 23:21:57.513093
3589 23:21:57.513158 ==
3590 23:21:57.516221 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 23:21:57.519441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 23:21:57.519525 ==
3593 23:21:57.519627 RX Vref Scan: 0
3594 23:21:57.519735
3595 23:21:57.522686 RX Vref 0 -> 0, step: 1
3596 23:21:57.522771
3597 23:21:57.526014 RX Delay -5 -> 252, step: 4
3598 23:21:57.529469 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3599 23:21:57.536165 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3600 23:21:57.539480 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3601 23:21:57.542697 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3602 23:21:57.546036 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3603 23:21:57.549233 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3604 23:21:57.556050 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3605 23:21:57.559136 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3606 23:21:57.562738 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3607 23:21:57.565840 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3608 23:21:57.569530 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3609 23:21:57.575930 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3610 23:21:57.579245 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3611 23:21:57.582411 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3612 23:21:57.585684 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3613 23:21:57.592500 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3614 23:21:57.592595 ==
3615 23:21:57.595913 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 23:21:57.599244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 23:21:57.599337 ==
3618 23:21:57.599404 DQS Delay:
3619 23:21:57.602310 DQS0 = 0, DQS1 = 0
3620 23:21:57.602390 DQM Delay:
3621 23:21:57.605561 DQM0 = 120, DQM1 = 118
3622 23:21:57.605644 DQ Delay:
3623 23:21:57.609157 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3624 23:21:57.612145 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3625 23:21:57.615468 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3626 23:21:57.619148 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3627 23:21:57.619233
3628 23:21:57.619297
3629 23:21:57.629083 [DQSOSCAuto] RK1, (LSB)MR18= 0xfed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3630 23:21:57.632483 CH1 RK1: MR19=403, MR18=FED
3631 23:21:57.635872 CH1_RK1: MR19=0x403, MR18=0xFED, DQSOSC=404, MR23=63, INC=40, DEC=26
3632 23:21:57.638955 [RxdqsGatingPostProcess] freq 1200
3633 23:21:57.645729 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3634 23:21:57.648831 best DQS0 dly(2T, 0.5T) = (0, 11)
3635 23:21:57.652261 best DQS1 dly(2T, 0.5T) = (0, 11)
3636 23:21:57.655223 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3637 23:21:57.658866 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3638 23:21:57.661948 best DQS0 dly(2T, 0.5T) = (0, 11)
3639 23:21:57.665228 best DQS1 dly(2T, 0.5T) = (0, 11)
3640 23:21:57.668756 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3641 23:21:57.671932 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3642 23:21:57.675232 Pre-setting of DQS Precalculation
3643 23:21:57.678887 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3644 23:21:57.685274 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3645 23:21:57.692254 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3646 23:21:57.692382
3647 23:21:57.692452
3648 23:21:57.695541 [Calibration Summary] 2400 Mbps
3649 23:21:57.698737 CH 0, Rank 0
3650 23:21:57.698813 SW Impedance : PASS
3651 23:21:57.701775 DUTY Scan : NO K
3652 23:21:57.705137 ZQ Calibration : PASS
3653 23:21:57.705214 Jitter Meter : NO K
3654 23:21:57.708575 CBT Training : PASS
3655 23:21:57.712232 Write leveling : PASS
3656 23:21:57.712333 RX DQS gating : PASS
3657 23:21:57.715443 RX DQ/DQS(RDDQC) : PASS
3658 23:21:57.715517 TX DQ/DQS : PASS
3659 23:21:57.718678 RX DATLAT : PASS
3660 23:21:57.721717 RX DQ/DQS(Engine): PASS
3661 23:21:57.721802 TX OE : NO K
3662 23:21:57.725095 All Pass.
3663 23:21:57.725189
3664 23:21:57.725257 CH 0, Rank 1
3665 23:21:57.728538 SW Impedance : PASS
3666 23:21:57.728621 DUTY Scan : NO K
3667 23:21:57.731834 ZQ Calibration : PASS
3668 23:21:57.735241 Jitter Meter : NO K
3669 23:21:57.735328 CBT Training : PASS
3670 23:21:57.738401 Write leveling : PASS
3671 23:21:57.741809 RX DQS gating : PASS
3672 23:21:57.741918 RX DQ/DQS(RDDQC) : PASS
3673 23:21:57.745030 TX DQ/DQS : PASS
3674 23:21:57.748268 RX DATLAT : PASS
3675 23:21:57.748394 RX DQ/DQS(Engine): PASS
3676 23:21:57.751627 TX OE : NO K
3677 23:21:57.751706 All Pass.
3678 23:21:57.751768
3679 23:21:57.755139 CH 1, Rank 0
3680 23:21:57.755232 SW Impedance : PASS
3681 23:21:57.758393 DUTY Scan : NO K
3682 23:21:57.762046 ZQ Calibration : PASS
3683 23:21:57.762131 Jitter Meter : NO K
3684 23:21:57.765245 CBT Training : PASS
3685 23:21:57.768417 Write leveling : PASS
3686 23:21:57.768508 RX DQS gating : PASS
3687 23:21:57.771850 RX DQ/DQS(RDDQC) : PASS
3688 23:21:57.771939 TX DQ/DQS : PASS
3689 23:21:57.775054 RX DATLAT : PASS
3690 23:21:57.778186 RX DQ/DQS(Engine): PASS
3691 23:21:57.778282 TX OE : NO K
3692 23:21:57.781601 All Pass.
3693 23:21:57.781718
3694 23:21:57.781788 CH 1, Rank 1
3695 23:21:57.784943 SW Impedance : PASS
3696 23:21:57.785047 DUTY Scan : NO K
3697 23:21:57.788483 ZQ Calibration : PASS
3698 23:21:57.791627 Jitter Meter : NO K
3699 23:21:57.791712 CBT Training : PASS
3700 23:21:57.794778 Write leveling : PASS
3701 23:21:57.797941 RX DQS gating : PASS
3702 23:21:57.798058 RX DQ/DQS(RDDQC) : PASS
3703 23:21:57.801251 TX DQ/DQS : PASS
3704 23:21:57.804953 RX DATLAT : PASS
3705 23:21:57.805039 RX DQ/DQS(Engine): PASS
3706 23:21:57.808134 TX OE : NO K
3707 23:21:57.808238 All Pass.
3708 23:21:57.808338
3709 23:21:57.811242 DramC Write-DBI off
3710 23:21:57.814586 PER_BANK_REFRESH: Hybrid Mode
3711 23:21:57.814671 TX_TRACKING: ON
3712 23:21:57.824923 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3713 23:21:57.828188 [FAST_K] Save calibration result to emmc
3714 23:21:57.831422 dramc_set_vcore_voltage set vcore to 650000
3715 23:21:57.834524 Read voltage for 600, 5
3716 23:21:57.834610 Vio18 = 0
3717 23:21:57.834712 Vcore = 650000
3718 23:21:57.837978 Vdram = 0
3719 23:21:57.838103 Vddq = 0
3720 23:21:57.838221 Vmddr = 0
3721 23:21:57.844577 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3722 23:21:57.847764 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3723 23:21:57.850995 MEM_TYPE=3, freq_sel=19
3724 23:21:57.854535 sv_algorithm_assistance_LP4_1600
3725 23:21:57.857860 ============ PULL DRAM RESETB DOWN ============
3726 23:21:57.861207 ========== PULL DRAM RESETB DOWN end =========
3727 23:21:57.867762 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3728 23:21:57.871172 ===================================
3729 23:21:57.874423 LPDDR4 DRAM CONFIGURATION
3730 23:21:57.877657 ===================================
3731 23:21:57.877800 EX_ROW_EN[0] = 0x0
3732 23:21:57.880788 EX_ROW_EN[1] = 0x0
3733 23:21:57.880881 LP4Y_EN = 0x0
3734 23:21:57.884316 WORK_FSP = 0x0
3735 23:21:57.884399 WL = 0x2
3736 23:21:57.887513 RL = 0x2
3737 23:21:57.887594 BL = 0x2
3738 23:21:57.890690 RPST = 0x0
3739 23:21:57.890776 RD_PRE = 0x0
3740 23:21:57.894104 WR_PRE = 0x1
3741 23:21:57.894220 WR_PST = 0x0
3742 23:21:57.897531 DBI_WR = 0x0
3743 23:21:57.897610 DBI_RD = 0x0
3744 23:21:57.900752 OTF = 0x1
3745 23:21:57.904249 ===================================
3746 23:21:57.907523 ===================================
3747 23:21:57.907603 ANA top config
3748 23:21:57.910801 ===================================
3749 23:21:57.913967 DLL_ASYNC_EN = 0
3750 23:21:57.917426 ALL_SLAVE_EN = 1
3751 23:21:57.920675 NEW_RANK_MODE = 1
3752 23:21:57.920762 DLL_IDLE_MODE = 1
3753 23:21:57.924068 LP45_APHY_COMB_EN = 1
3754 23:21:57.927389 TX_ODT_DIS = 1
3755 23:21:57.930573 NEW_8X_MODE = 1
3756 23:21:57.933816 ===================================
3757 23:21:57.937113 ===================================
3758 23:21:57.940359 data_rate = 1200
3759 23:21:57.944018 CKR = 1
3760 23:21:57.944130 DQ_P2S_RATIO = 8
3761 23:21:57.947186 ===================================
3762 23:21:57.950687 CA_P2S_RATIO = 8
3763 23:21:57.954044 DQ_CA_OPEN = 0
3764 23:21:57.957253 DQ_SEMI_OPEN = 0
3765 23:21:57.960382 CA_SEMI_OPEN = 0
3766 23:21:57.963900 CA_FULL_RATE = 0
3767 23:21:57.963984 DQ_CKDIV4_EN = 1
3768 23:21:57.966941 CA_CKDIV4_EN = 1
3769 23:21:57.970715 CA_PREDIV_EN = 0
3770 23:21:57.973822 PH8_DLY = 0
3771 23:21:57.977381 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3772 23:21:57.977467 DQ_AAMCK_DIV = 4
3773 23:21:57.980659 CA_AAMCK_DIV = 4
3774 23:21:57.983908 CA_ADMCK_DIV = 4
3775 23:21:57.987247 DQ_TRACK_CA_EN = 0
3776 23:21:57.990373 CA_PICK = 600
3777 23:21:57.993707 CA_MCKIO = 600
3778 23:21:57.996977 MCKIO_SEMI = 0
3779 23:21:57.997073 PLL_FREQ = 2288
3780 23:21:58.000452 DQ_UI_PI_RATIO = 32
3781 23:21:58.003751 CA_UI_PI_RATIO = 0
3782 23:21:58.007180 ===================================
3783 23:21:58.010660 ===================================
3784 23:21:58.013635 memory_type:LPDDR4
3785 23:21:58.013726 GP_NUM : 10
3786 23:21:58.017130 SRAM_EN : 1
3787 23:21:58.020238 MD32_EN : 0
3788 23:21:58.023729 ===================================
3789 23:21:58.023821 [ANA_INIT] >>>>>>>>>>>>>>
3790 23:21:58.026912 <<<<<< [CONFIGURE PHASE]: ANA_TX
3791 23:21:58.030387 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3792 23:21:58.033661 ===================================
3793 23:21:58.037253 data_rate = 1200,PCW = 0X5800
3794 23:21:58.040434 ===================================
3795 23:21:58.043653 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3796 23:21:58.050351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 23:21:58.053816 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3798 23:21:58.060301 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3799 23:21:58.063537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3800 23:21:58.066736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3801 23:21:58.066824 [ANA_INIT] flow start
3802 23:21:58.070426 [ANA_INIT] PLL >>>>>>>>
3803 23:21:58.073998 [ANA_INIT] PLL <<<<<<<<
3804 23:21:58.077201 [ANA_INIT] MIDPI >>>>>>>>
3805 23:21:58.077330 [ANA_INIT] MIDPI <<<<<<<<
3806 23:21:58.080445 [ANA_INIT] DLL >>>>>>>>
3807 23:21:58.080578 [ANA_INIT] flow end
3808 23:21:58.087236 ============ LP4 DIFF to SE enter ============
3809 23:21:58.090179 ============ LP4 DIFF to SE exit ============
3810 23:21:58.093413 [ANA_INIT] <<<<<<<<<<<<<
3811 23:21:58.097183 [Flow] Enable top DCM control >>>>>
3812 23:21:58.100361 [Flow] Enable top DCM control <<<<<
3813 23:21:58.103704 Enable DLL master slave shuffle
3814 23:21:58.106987 ==============================================================
3815 23:21:58.110313 Gating Mode config
3816 23:21:58.113626 ==============================================================
3817 23:21:58.117000 Config description:
3818 23:21:58.126825 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3819 23:21:58.133819 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3820 23:21:58.137021 SELPH_MODE 0: By rank 1: By Phase
3821 23:21:58.143618 ==============================================================
3822 23:21:58.146860 GAT_TRACK_EN = 1
3823 23:21:58.149999 RX_GATING_MODE = 2
3824 23:21:58.153752 RX_GATING_TRACK_MODE = 2
3825 23:21:58.156990 SELPH_MODE = 1
3826 23:21:58.160033 PICG_EARLY_EN = 1
3827 23:21:58.160123 VALID_LAT_VALUE = 1
3828 23:21:58.166474 ==============================================================
3829 23:21:58.170146 Enter into Gating configuration >>>>
3830 23:21:58.173195 Exit from Gating configuration <<<<
3831 23:21:58.176860 Enter into DVFS_PRE_config >>>>>
3832 23:21:58.186546 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3833 23:21:58.189794 Exit from DVFS_PRE_config <<<<<
3834 23:21:58.193463 Enter into PICG configuration >>>>
3835 23:21:58.196623 Exit from PICG configuration <<<<
3836 23:21:58.199981 [RX_INPUT] configuration >>>>>
3837 23:21:58.203078 [RX_INPUT] configuration <<<<<
3838 23:21:58.206730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3839 23:21:58.213227 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3840 23:21:58.219784 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3841 23:21:58.226376 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3842 23:21:58.233151 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 23:21:58.239609 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 23:21:58.242792 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3845 23:21:58.246169 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3846 23:21:58.249938 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3847 23:21:58.256134 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3848 23:21:58.259438 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3849 23:21:58.262758 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3850 23:21:58.266334 ===================================
3851 23:21:58.269394 LPDDR4 DRAM CONFIGURATION
3852 23:21:58.272821 ===================================
3853 23:21:58.272913 EX_ROW_EN[0] = 0x0
3854 23:21:58.276011 EX_ROW_EN[1] = 0x0
3855 23:21:58.276120 LP4Y_EN = 0x0
3856 23:21:58.279234 WORK_FSP = 0x0
3857 23:21:58.282876 WL = 0x2
3858 23:21:58.282957 RL = 0x2
3859 23:21:58.286128 BL = 0x2
3860 23:21:58.286210 RPST = 0x0
3861 23:21:58.289198 RD_PRE = 0x0
3862 23:21:58.289276 WR_PRE = 0x1
3863 23:21:58.292881 WR_PST = 0x0
3864 23:21:58.292958 DBI_WR = 0x0
3865 23:21:58.296174 DBI_RD = 0x0
3866 23:21:58.296277 OTF = 0x1
3867 23:21:58.299279 ===================================
3868 23:21:58.302481 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3869 23:21:58.309245 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3870 23:21:58.312256 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3871 23:21:58.315899 ===================================
3872 23:21:58.318982 LPDDR4 DRAM CONFIGURATION
3873 23:21:58.322437 ===================================
3874 23:21:58.322519 EX_ROW_EN[0] = 0x10
3875 23:21:58.325438 EX_ROW_EN[1] = 0x0
3876 23:21:58.325520 LP4Y_EN = 0x0
3877 23:21:58.328926 WORK_FSP = 0x0
3878 23:21:58.332258 WL = 0x2
3879 23:21:58.332372 RL = 0x2
3880 23:21:58.335716 BL = 0x2
3881 23:21:58.335803 RPST = 0x0
3882 23:21:58.338885 RD_PRE = 0x0
3883 23:21:58.338965 WR_PRE = 0x1
3884 23:21:58.342143 WR_PST = 0x0
3885 23:21:58.342236 DBI_WR = 0x0
3886 23:21:58.345616 DBI_RD = 0x0
3887 23:21:58.345713 OTF = 0x1
3888 23:21:58.348929 ===================================
3889 23:21:58.355440 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3890 23:21:58.359411 nWR fixed to 30
3891 23:21:58.362801 [ModeRegInit_LP4] CH0 RK0
3892 23:21:58.362897 [ModeRegInit_LP4] CH0 RK1
3893 23:21:58.365929 [ModeRegInit_LP4] CH1 RK0
3894 23:21:58.369570 [ModeRegInit_LP4] CH1 RK1
3895 23:21:58.369652 match AC timing 17
3896 23:21:58.376156 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3897 23:21:58.379425 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3898 23:21:58.382766 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3899 23:21:58.389502 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3900 23:21:58.392695 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3901 23:21:58.392794 ==
3902 23:21:58.395899 Dram Type= 6, Freq= 0, CH_0, rank 0
3903 23:21:58.399122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3904 23:21:58.399198 ==
3905 23:21:58.405917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3906 23:21:58.412725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3907 23:21:58.416054 [CA 0] Center 36 (5~67) winsize 63
3908 23:21:58.419170 [CA 1] Center 36 (5~67) winsize 63
3909 23:21:58.422823 [CA 2] Center 33 (3~64) winsize 62
3910 23:21:58.426018 [CA 3] Center 33 (2~64) winsize 63
3911 23:21:58.429288 [CA 4] Center 33 (2~64) winsize 63
3912 23:21:58.432876 [CA 5] Center 32 (2~63) winsize 62
3913 23:21:58.432964
3914 23:21:58.436187 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3915 23:21:58.436297
3916 23:21:58.439623 [CATrainingPosCal] consider 1 rank data
3917 23:21:58.442701 u2DelayCellTimex100 = 270/100 ps
3918 23:21:58.446057 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3919 23:21:58.449397 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3920 23:21:58.452830 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3921 23:21:58.455760 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3922 23:21:58.459285 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3923 23:21:58.462421 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3924 23:21:58.465729
3925 23:21:58.468949 CA PerBit enable=1, Macro0, CA PI delay=32
3926 23:21:58.469044
3927 23:21:58.472624 [CBTSetCACLKResult] CA Dly = 32
3928 23:21:58.472715 CS Dly: 5 (0~36)
3929 23:21:58.472782 ==
3930 23:21:58.475653 Dram Type= 6, Freq= 0, CH_0, rank 1
3931 23:21:58.479482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3932 23:21:58.479578 ==
3933 23:21:58.485790 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3934 23:21:58.492331 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3935 23:21:58.495617 [CA 0] Center 35 (5~66) winsize 62
3936 23:21:58.498982 [CA 1] Center 35 (5~66) winsize 62
3937 23:21:58.502206 [CA 2] Center 33 (3~64) winsize 62
3938 23:21:58.505439 [CA 3] Center 33 (3~64) winsize 62
3939 23:21:58.508912 [CA 4] Center 33 (2~64) winsize 63
3940 23:21:58.512475 [CA 5] Center 32 (2~63) winsize 62
3941 23:21:58.512568
3942 23:21:58.515635 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3943 23:21:58.515715
3944 23:21:58.518679 [CATrainingPosCal] consider 2 rank data
3945 23:21:58.522083 u2DelayCellTimex100 = 270/100 ps
3946 23:21:58.525629 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3947 23:21:58.528900 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3948 23:21:58.532083 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3949 23:21:58.535291 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3950 23:21:58.542107 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3951 23:21:58.545372 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3952 23:21:58.545479
3953 23:21:58.548346 CA PerBit enable=1, Macro0, CA PI delay=32
3954 23:21:58.548436
3955 23:21:58.551719 [CBTSetCACLKResult] CA Dly = 32
3956 23:21:58.551819 CS Dly: 5 (0~36)
3957 23:21:58.551886
3958 23:21:58.555314 ----->DramcWriteLeveling(PI) begin...
3959 23:21:58.555410 ==
3960 23:21:58.558560 Dram Type= 6, Freq= 0, CH_0, rank 0
3961 23:21:58.565031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 23:21:58.565145 ==
3963 23:21:58.568965 Write leveling (Byte 0): 34 => 34
3964 23:21:58.571648 Write leveling (Byte 1): 30 => 30
3965 23:21:58.571751 DramcWriteLeveling(PI) end<-----
3966 23:21:58.571820
3967 23:21:58.575048 ==
3968 23:21:58.578370 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 23:21:58.581832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 23:21:58.581923 ==
3971 23:21:58.585050 [Gating] SW mode calibration
3972 23:21:58.591604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3973 23:21:58.595233 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3974 23:21:58.601700 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 23:21:58.605274 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 23:21:58.608236 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 23:21:58.615169 0 9 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
3978 23:21:58.618511 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3979 23:21:58.621802 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 23:21:58.628249 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 23:21:58.631712 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 23:21:58.635038 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 23:21:58.641623 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 23:21:58.644842 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 23:21:58.648059 0 10 12 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
3986 23:21:58.654773 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
3987 23:21:58.657970 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 23:21:58.661440 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 23:21:58.667837 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 23:21:58.671408 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 23:21:58.674839 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 23:21:58.681256 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3993 23:21:58.684579 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3994 23:21:58.687909 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3995 23:21:58.691177 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 23:21:58.698145 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 23:21:58.701424 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 23:21:58.704514 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 23:21:58.711259 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 23:21:58.714404 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 23:21:58.718010 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 23:21:58.724327 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 23:21:58.727846 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 23:21:58.731224 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 23:21:58.737456 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 23:21:58.740804 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 23:21:58.744307 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 23:21:58.750974 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 23:21:58.754260 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4010 23:21:58.757383 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4011 23:21:58.760876 Total UI for P1: 0, mck2ui 16
4012 23:21:58.764308 best dqsien dly found for B0: ( 0, 13, 12)
4013 23:21:58.771012 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 23:21:58.771108 Total UI for P1: 0, mck2ui 16
4015 23:21:58.777344 best dqsien dly found for B1: ( 0, 13, 16)
4016 23:21:58.781036 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4017 23:21:58.784067 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4018 23:21:58.784153
4019 23:21:58.787488 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4020 23:21:58.790675 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4021 23:21:58.794032 [Gating] SW calibration Done
4022 23:21:58.794119 ==
4023 23:21:58.797243 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 23:21:58.800913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 23:21:58.800999 ==
4026 23:21:58.804156 RX Vref Scan: 0
4027 23:21:58.804274
4028 23:21:58.804397 RX Vref 0 -> 0, step: 1
4029 23:21:58.804498
4030 23:21:58.807332 RX Delay -230 -> 252, step: 16
4031 23:21:58.814316 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4032 23:21:58.817366 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4033 23:21:58.820595 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4034 23:21:58.824098 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4035 23:21:58.827292 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4036 23:21:58.833777 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4037 23:21:58.837542 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4038 23:21:58.840685 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4039 23:21:58.843724 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4040 23:21:58.850563 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4041 23:21:58.853622 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4042 23:21:58.856921 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4043 23:21:58.860514 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4044 23:21:58.866811 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4045 23:21:58.870233 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4046 23:21:58.873769 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4047 23:21:58.873858 ==
4048 23:21:58.877134 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 23:21:58.880294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 23:21:58.880384 ==
4051 23:21:58.883663 DQS Delay:
4052 23:21:58.883795 DQS0 = 0, DQS1 = 0
4053 23:21:58.886758 DQM Delay:
4054 23:21:58.886888 DQM0 = 53, DQM1 = 46
4055 23:21:58.887019 DQ Delay:
4056 23:21:58.890397 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4057 23:21:58.893587 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4058 23:21:58.896878 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4059 23:21:58.900111 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4060 23:21:58.900220
4061 23:21:58.900327
4062 23:21:58.900431 ==
4063 23:21:58.903419 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 23:21:58.910469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 23:21:58.910587 ==
4066 23:21:58.910711
4067 23:21:58.910809
4068 23:21:58.910910 TX Vref Scan disable
4069 23:21:58.914236 == TX Byte 0 ==
4070 23:21:58.917496 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4071 23:21:58.924374 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4072 23:21:58.924494 == TX Byte 1 ==
4073 23:21:58.927516 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4074 23:21:58.934055 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4075 23:21:58.934175 ==
4076 23:21:58.937723 Dram Type= 6, Freq= 0, CH_0, rank 0
4077 23:21:58.940946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4078 23:21:58.941048 ==
4079 23:21:58.941130
4080 23:21:58.941203
4081 23:21:58.943972 TX Vref Scan disable
4082 23:21:58.947725 == TX Byte 0 ==
4083 23:21:58.950893 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4084 23:21:58.954007 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4085 23:21:58.957565 == TX Byte 1 ==
4086 23:21:58.960523 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4087 23:21:58.963740 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4088 23:21:58.963818
4089 23:21:58.963887 [DATLAT]
4090 23:21:58.967414 Freq=600, CH0 RK0
4091 23:21:58.967491
4092 23:21:58.970716 DATLAT Default: 0x9
4093 23:21:58.970797 0, 0xFFFF, sum = 0
4094 23:21:58.973690 1, 0xFFFF, sum = 0
4095 23:21:58.973770 2, 0xFFFF, sum = 0
4096 23:21:58.977069 3, 0xFFFF, sum = 0
4097 23:21:58.977149 4, 0xFFFF, sum = 0
4098 23:21:58.980688 5, 0xFFFF, sum = 0
4099 23:21:58.980800 6, 0xFFFF, sum = 0
4100 23:21:58.983663 7, 0xFFFF, sum = 0
4101 23:21:58.983763 8, 0x0, sum = 1
4102 23:21:58.987037 9, 0x0, sum = 2
4103 23:21:58.987114 10, 0x0, sum = 3
4104 23:21:58.990343 11, 0x0, sum = 4
4105 23:21:58.990424 best_step = 9
4106 23:21:58.990488
4107 23:21:58.990548 ==
4108 23:21:58.993828 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 23:21:58.997203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 23:21:58.997287 ==
4111 23:21:59.000404 RX Vref Scan: 1
4112 23:21:59.000485
4113 23:21:59.000585 RX Vref 0 -> 0, step: 1
4114 23:21:59.003495
4115 23:21:59.003592 RX Delay -163 -> 252, step: 8
4116 23:21:59.003685
4117 23:21:59.006845 Set Vref, RX VrefLevel [Byte0]: 56
4118 23:21:59.010113 [Byte1]: 47
4119 23:21:59.014618
4120 23:21:59.014705 Final RX Vref Byte 0 = 56 to rank0
4121 23:21:59.017884 Final RX Vref Byte 1 = 47 to rank0
4122 23:21:59.021571 Final RX Vref Byte 0 = 56 to rank1
4123 23:21:59.024692 Final RX Vref Byte 1 = 47 to rank1==
4124 23:21:59.028228 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 23:21:59.034588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 23:21:59.034681 ==
4127 23:21:59.034749 DQS Delay:
4128 23:21:59.034811 DQS0 = 0, DQS1 = 0
4129 23:21:59.038281 DQM Delay:
4130 23:21:59.038367 DQM0 = 52, DQM1 = 47
4131 23:21:59.041614 DQ Delay:
4132 23:21:59.044714 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4133 23:21:59.044831 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4134 23:21:59.047958 DQ8 =36, DQ9 =36, DQ10 =52, DQ11 =40
4135 23:21:59.054898 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4136 23:21:59.055014
4137 23:21:59.055111
4138 23:21:59.061546 [DQSOSCAuto] RK0, (LSB)MR18= 0x7165, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4139 23:21:59.064825 CH0 RK0: MR19=808, MR18=7165
4140 23:21:59.071198 CH0_RK0: MR19=0x808, MR18=0x7165, DQSOSC=388, MR23=63, INC=174, DEC=116
4141 23:21:59.071288
4142 23:21:59.074846 ----->DramcWriteLeveling(PI) begin...
4143 23:21:59.074959 ==
4144 23:21:59.077993 Dram Type= 6, Freq= 0, CH_0, rank 1
4145 23:21:59.081509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 23:21:59.081596 ==
4147 23:21:59.084382 Write leveling (Byte 0): 34 => 34
4148 23:21:59.087997 Write leveling (Byte 1): 31 => 31
4149 23:21:59.091328 DramcWriteLeveling(PI) end<-----
4150 23:21:59.091415
4151 23:21:59.091482 ==
4152 23:21:59.094413 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 23:21:59.097883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 23:21:59.097970 ==
4155 23:21:59.101366 [Gating] SW mode calibration
4156 23:21:59.107847 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4157 23:21:59.114248 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4158 23:21:59.117587 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 23:21:59.121140 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 23:21:59.127770 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 23:21:59.130981 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (0 1) (0 0)
4162 23:21:59.134198 0 9 16 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
4163 23:21:59.140898 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 23:21:59.144361 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 23:21:59.147548 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 23:21:59.154840 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 23:21:59.157893 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 23:21:59.161157 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 23:21:59.167606 0 10 12 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
4170 23:21:59.171318 0 10 16 | B1->B0 | 3c3c 4140 | 0 1 | (0 0) (0 0)
4171 23:21:59.174513 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 23:21:59.180910 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 23:21:59.184534 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 23:21:59.187548 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 23:21:59.194434 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 23:21:59.197408 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 23:21:59.201125 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4178 23:21:59.207760 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 23:21:59.210975 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 23:21:59.214177 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 23:21:59.220802 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 23:21:59.224260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 23:21:59.227729 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 23:21:59.234154 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 23:21:59.237369 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 23:21:59.240672 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 23:21:59.243975 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 23:21:59.250763 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 23:21:59.254192 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 23:21:59.257516 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 23:21:59.263855 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 23:21:59.267560 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4193 23:21:59.270409 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4194 23:21:59.273909 Total UI for P1: 0, mck2ui 16
4195 23:21:59.277149 best dqsien dly found for B0: ( 0, 13, 10)
4196 23:21:59.283882 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 23:21:59.287090 Total UI for P1: 0, mck2ui 16
4198 23:21:59.290817 best dqsien dly found for B1: ( 0, 13, 10)
4199 23:21:59.294000 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4200 23:21:59.297326 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4201 23:21:59.297436
4202 23:21:59.300460 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4203 23:21:59.303933 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4204 23:21:59.307144 [Gating] SW calibration Done
4205 23:21:59.307250 ==
4206 23:21:59.310670 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 23:21:59.313630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 23:21:59.313747 ==
4209 23:21:59.316862 RX Vref Scan: 0
4210 23:21:59.316957
4211 23:21:59.320504 RX Vref 0 -> 0, step: 1
4212 23:21:59.320617
4213 23:21:59.320712 RX Delay -230 -> 252, step: 16
4214 23:21:59.327011 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4215 23:21:59.330456 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4216 23:21:59.333455 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4217 23:21:59.337047 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4218 23:21:59.343836 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4219 23:21:59.346811 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4220 23:21:59.350403 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4221 23:21:59.353566 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4222 23:21:59.357015 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4223 23:21:59.363535 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4224 23:21:59.366987 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4225 23:21:59.370120 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4226 23:21:59.373832 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4227 23:21:59.380138 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4228 23:21:59.383561 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4229 23:21:59.387072 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4230 23:21:59.387216 ==
4231 23:21:59.390322 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 23:21:59.393461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 23:21:59.393599 ==
4234 23:21:59.397110 DQS Delay:
4235 23:21:59.397225 DQS0 = 0, DQS1 = 0
4236 23:21:59.400267 DQM Delay:
4237 23:21:59.400399 DQM0 = 54, DQM1 = 44
4238 23:21:59.400482 DQ Delay:
4239 23:21:59.403560 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4240 23:21:59.406788 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =65
4241 23:21:59.410299 DQ8 =41, DQ9 =33, DQ10 =49, DQ11 =33
4242 23:21:59.413687 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4243 23:21:59.413784
4244 23:21:59.413851
4245 23:21:59.416810 ==
4246 23:21:59.416898 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 23:21:59.423536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 23:21:59.423635 ==
4249 23:21:59.423702
4250 23:21:59.423763
4251 23:21:59.426823 TX Vref Scan disable
4252 23:21:59.426929 == TX Byte 0 ==
4253 23:21:59.429964 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4254 23:21:59.436904 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4255 23:21:59.436997 == TX Byte 1 ==
4256 23:21:59.439920 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4257 23:21:59.446786 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4258 23:21:59.446928 ==
4259 23:21:59.450309 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 23:21:59.453279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 23:21:59.453367 ==
4262 23:21:59.453435
4263 23:21:59.453497
4264 23:21:59.456681 TX Vref Scan disable
4265 23:21:59.459868 == TX Byte 0 ==
4266 23:21:59.463623 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4267 23:21:59.466793 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4268 23:21:59.470332 == TX Byte 1 ==
4269 23:21:59.473212 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4270 23:21:59.476543 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4271 23:21:59.476694
4272 23:21:59.480105 [DATLAT]
4273 23:21:59.480221 Freq=600, CH0 RK1
4274 23:21:59.480328
4275 23:21:59.483218 DATLAT Default: 0x9
4276 23:21:59.483326 0, 0xFFFF, sum = 0
4277 23:21:59.486640 1, 0xFFFF, sum = 0
4278 23:21:59.486744 2, 0xFFFF, sum = 0
4279 23:21:59.489831 3, 0xFFFF, sum = 0
4280 23:21:59.489954 4, 0xFFFF, sum = 0
4281 23:21:59.492983 5, 0xFFFF, sum = 0
4282 23:21:59.493093 6, 0xFFFF, sum = 0
4283 23:21:59.496426 7, 0xFFFF, sum = 0
4284 23:21:59.496539 8, 0x0, sum = 1
4285 23:21:59.499627 9, 0x0, sum = 2
4286 23:21:59.499745 10, 0x0, sum = 3
4287 23:21:59.503029 11, 0x0, sum = 4
4288 23:21:59.503151 best_step = 9
4289 23:21:59.503251
4290 23:21:59.503348 ==
4291 23:21:59.506340 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 23:21:59.509901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 23:21:59.513044 ==
4294 23:21:59.513194 RX Vref Scan: 0
4295 23:21:59.513306
4296 23:21:59.516527 RX Vref 0 -> 0, step: 1
4297 23:21:59.516667
4298 23:21:59.519679 RX Delay -163 -> 252, step: 8
4299 23:21:59.522895 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4300 23:21:59.526492 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4301 23:21:59.532895 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4302 23:21:59.536197 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4303 23:21:59.539414 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4304 23:21:59.542883 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4305 23:21:59.546046 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4306 23:21:59.552878 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4307 23:21:59.555928 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4308 23:21:59.559390 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4309 23:21:59.562676 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4310 23:21:59.565919 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4311 23:21:59.572829 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4312 23:21:59.576034 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4313 23:21:59.579148 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4314 23:21:59.582612 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4315 23:21:59.582759 ==
4316 23:21:59.585852 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 23:21:59.592627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 23:21:59.592781 ==
4319 23:21:59.592885 DQS Delay:
4320 23:21:59.596124 DQS0 = 0, DQS1 = 0
4321 23:21:59.596269 DQM Delay:
4322 23:21:59.596379 DQM0 = 54, DQM1 = 46
4323 23:21:59.599207 DQ Delay:
4324 23:21:59.602640 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4325 23:21:59.605911 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =64
4326 23:21:59.609291 DQ8 =40, DQ9 =32, DQ10 =48, DQ11 =40
4327 23:21:59.612587 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4328 23:21:59.612694
4329 23:21:59.612760
4330 23:21:59.619284 [DQSOSCAuto] RK1, (LSB)MR18= 0x6425, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4331 23:21:59.622807 CH0 RK1: MR19=808, MR18=6425
4332 23:21:59.629337 CH0_RK1: MR19=0x808, MR18=0x6425, DQSOSC=391, MR23=63, INC=171, DEC=114
4333 23:21:59.632407 [RxdqsGatingPostProcess] freq 600
4334 23:21:59.635864 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4335 23:21:59.639057 Pre-setting of DQS Precalculation
4336 23:21:59.645666 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4337 23:21:59.645817 ==
4338 23:21:59.648818 Dram Type= 6, Freq= 0, CH_1, rank 0
4339 23:21:59.652505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 23:21:59.652597 ==
4341 23:21:59.658993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4342 23:21:59.665426 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4343 23:21:59.668918 [CA 0] Center 36 (5~67) winsize 63
4344 23:21:59.672505 [CA 1] Center 36 (5~67) winsize 63
4345 23:21:59.675548 [CA 2] Center 34 (4~65) winsize 62
4346 23:21:59.678733 [CA 3] Center 34 (4~65) winsize 62
4347 23:21:59.681935 [CA 4] Center 34 (4~65) winsize 62
4348 23:21:59.685694 [CA 5] Center 34 (4~64) winsize 61
4349 23:21:59.685780
4350 23:21:59.688612 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4351 23:21:59.688690
4352 23:21:59.692074 [CATrainingPosCal] consider 1 rank data
4353 23:21:59.695518 u2DelayCellTimex100 = 270/100 ps
4354 23:21:59.698978 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4355 23:21:59.702361 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4356 23:21:59.705314 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4357 23:21:59.708817 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4358 23:21:59.712217 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4359 23:21:59.715391 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4360 23:21:59.715549
4361 23:21:59.718791 CA PerBit enable=1, Macro0, CA PI delay=34
4362 23:21:59.718907
4363 23:21:59.722104 [CBTSetCACLKResult] CA Dly = 34
4364 23:21:59.725341 CS Dly: 5 (0~36)
4365 23:21:59.725468 ==
4366 23:21:59.728540 Dram Type= 6, Freq= 0, CH_1, rank 1
4367 23:21:59.731940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 23:21:59.732064 ==
4369 23:21:59.738933 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4370 23:21:59.745452 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4371 23:21:59.748401 [CA 0] Center 36 (5~67) winsize 63
4372 23:21:59.751871 [CA 1] Center 36 (5~67) winsize 63
4373 23:21:59.755031 [CA 2] Center 35 (4~66) winsize 63
4374 23:21:59.758308 [CA 3] Center 34 (3~65) winsize 63
4375 23:21:59.762008 [CA 4] Center 34 (4~65) winsize 62
4376 23:21:59.765241 [CA 5] Center 34 (3~65) winsize 63
4377 23:21:59.765383
4378 23:21:59.768440 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4379 23:21:59.768556
4380 23:21:59.771636 [CATrainingPosCal] consider 2 rank data
4381 23:21:59.775150 u2DelayCellTimex100 = 270/100 ps
4382 23:21:59.778445 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4383 23:21:59.782028 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4384 23:21:59.785178 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4385 23:21:59.788425 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4386 23:21:59.791562 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4387 23:21:59.795137 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4388 23:21:59.795269
4389 23:21:59.801862 CA PerBit enable=1, Macro0, CA PI delay=34
4390 23:21:59.802000
4391 23:21:59.802114 [CBTSetCACLKResult] CA Dly = 34
4392 23:21:59.804950 CS Dly: 6 (0~38)
4393 23:21:59.805086
4394 23:21:59.808437 ----->DramcWriteLeveling(PI) begin...
4395 23:21:59.808567 ==
4396 23:21:59.811879 Dram Type= 6, Freq= 0, CH_1, rank 0
4397 23:21:59.815220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 23:21:59.815374 ==
4399 23:21:59.818537 Write leveling (Byte 0): 29 => 29
4400 23:21:59.821480 Write leveling (Byte 1): 32 => 32
4401 23:21:59.825116 DramcWriteLeveling(PI) end<-----
4402 23:21:59.825257
4403 23:21:59.825338 ==
4404 23:21:59.828320 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 23:21:59.831573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 23:21:59.834731 ==
4407 23:21:59.834875 [Gating] SW mode calibration
4408 23:21:59.845030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4409 23:21:59.848519 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4410 23:21:59.851505 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 23:21:59.858197 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 23:21:59.861719 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4413 23:21:59.865009 0 9 12 | B1->B0 | 3030 2727 | 0 0 | (0 1) (0 0)
4414 23:21:59.871798 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 23:21:59.874888 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 23:21:59.878130 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 23:21:59.884751 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 23:21:59.888169 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 23:21:59.891809 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 23:21:59.898230 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 23:21:59.901638 0 10 12 | B1->B0 | 3737 3a3a | 0 0 | (0 0) (0 0)
4422 23:21:59.904779 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 23:21:59.911596 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 23:21:59.914689 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 23:21:59.918106 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 23:21:59.924721 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 23:21:59.928033 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 23:21:59.931445 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 23:21:59.934668 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 23:21:59.941227 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 23:21:59.944892 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 23:21:59.947920 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 23:21:59.954661 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 23:21:59.957966 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 23:21:59.961335 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 23:21:59.967727 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 23:21:59.971262 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 23:21:59.974422 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 23:21:59.981254 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 23:21:59.984594 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 23:21:59.987723 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 23:21:59.994597 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 23:21:59.997567 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 23:22:00.001206 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4445 23:22:00.007813 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 23:22:00.010948 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 23:22:00.014510 Total UI for P1: 0, mck2ui 16
4448 23:22:00.017606 best dqsien dly found for B0: ( 0, 13, 14)
4449 23:22:00.021204 Total UI for P1: 0, mck2ui 16
4450 23:22:00.024087 best dqsien dly found for B1: ( 0, 13, 14)
4451 23:22:00.027770 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4452 23:22:00.030877 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4453 23:22:00.031001
4454 23:22:00.034314 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4455 23:22:00.037667 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4456 23:22:00.040559 [Gating] SW calibration Done
4457 23:22:00.040693 ==
4458 23:22:00.044238 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 23:22:00.050531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 23:22:00.050686 ==
4461 23:22:00.050809 RX Vref Scan: 0
4462 23:22:00.050928
4463 23:22:00.053913 RX Vref 0 -> 0, step: 1
4464 23:22:00.054028
4465 23:22:00.057229 RX Delay -230 -> 252, step: 16
4466 23:22:00.060822 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4467 23:22:00.064267 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4468 23:22:00.067609 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4469 23:22:00.074434 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4470 23:22:00.077148 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4471 23:22:00.080739 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4472 23:22:00.083929 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4473 23:22:00.087442 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4474 23:22:00.094072 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4475 23:22:00.097124 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4476 23:22:00.100678 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4477 23:22:00.104085 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4478 23:22:00.110568 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4479 23:22:00.113671 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4480 23:22:00.117356 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4481 23:22:00.120599 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4482 23:22:00.120739 ==
4483 23:22:00.123694 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 23:22:00.130704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 23:22:00.130861 ==
4486 23:22:00.130986 DQS Delay:
4487 23:22:00.133861 DQS0 = 0, DQS1 = 0
4488 23:22:00.133987 DQM Delay:
4489 23:22:00.134104 DQM0 = 52, DQM1 = 49
4490 23:22:00.137077 DQ Delay:
4491 23:22:00.140341 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4492 23:22:00.143850 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4493 23:22:00.147104 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4494 23:22:00.150534 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4495 23:22:00.150649
4496 23:22:00.150744
4497 23:22:00.150835 ==
4498 23:22:00.153805 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 23:22:00.156951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 23:22:00.157028 ==
4501 23:22:00.157092
4502 23:22:00.157151
4503 23:22:00.160444 TX Vref Scan disable
4504 23:22:00.163495 == TX Byte 0 ==
4505 23:22:00.167137 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4506 23:22:00.170334 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4507 23:22:00.173563 == TX Byte 1 ==
4508 23:22:00.176793 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4509 23:22:00.180473 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4510 23:22:00.180619 ==
4511 23:22:00.183603 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 23:22:00.186824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 23:22:00.190399 ==
4514 23:22:00.190535
4515 23:22:00.190655
4516 23:22:00.190772 TX Vref Scan disable
4517 23:22:00.194051 == TX Byte 0 ==
4518 23:22:00.197258 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4519 23:22:00.203896 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4520 23:22:00.204002 == TX Byte 1 ==
4521 23:22:00.207174 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4522 23:22:00.213794 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4523 23:22:00.213892
4524 23:22:00.213961 [DATLAT]
4525 23:22:00.214023 Freq=600, CH1 RK0
4526 23:22:00.214082
4527 23:22:00.217159 DATLAT Default: 0x9
4528 23:22:00.217244 0, 0xFFFF, sum = 0
4529 23:22:00.220585 1, 0xFFFF, sum = 0
4530 23:22:00.220673 2, 0xFFFF, sum = 0
4531 23:22:00.223578 3, 0xFFFF, sum = 0
4532 23:22:00.226947 4, 0xFFFF, sum = 0
4533 23:22:00.227036 5, 0xFFFF, sum = 0
4534 23:22:00.230201 6, 0xFFFF, sum = 0
4535 23:22:00.230289 7, 0xFFFF, sum = 0
4536 23:22:00.233674 8, 0x0, sum = 1
4537 23:22:00.233762 9, 0x0, sum = 2
4538 23:22:00.233830 10, 0x0, sum = 3
4539 23:22:00.236968 11, 0x0, sum = 4
4540 23:22:00.237056 best_step = 9
4541 23:22:00.237123
4542 23:22:00.237184 ==
4543 23:22:00.240474 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 23:22:00.247087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 23:22:00.247188 ==
4546 23:22:00.247256 RX Vref Scan: 1
4547 23:22:00.247317
4548 23:22:00.250295 RX Vref 0 -> 0, step: 1
4549 23:22:00.250383
4550 23:22:00.253566 RX Delay -147 -> 252, step: 8
4551 23:22:00.253651
4552 23:22:00.257230 Set Vref, RX VrefLevel [Byte0]: 55
4553 23:22:00.260485 [Byte1]: 52
4554 23:22:00.260572
4555 23:22:00.263456 Final RX Vref Byte 0 = 55 to rank0
4556 23:22:00.267242 Final RX Vref Byte 1 = 52 to rank0
4557 23:22:00.270199 Final RX Vref Byte 0 = 55 to rank1
4558 23:22:00.273638 Final RX Vref Byte 1 = 52 to rank1==
4559 23:22:00.276924 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 23:22:00.280413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 23:22:00.280550 ==
4562 23:22:00.283666 DQS Delay:
4563 23:22:00.283790 DQS0 = 0, DQS1 = 0
4564 23:22:00.283895 DQM Delay:
4565 23:22:00.286788 DQM0 = 49, DQM1 = 46
4566 23:22:00.286903 DQ Delay:
4567 23:22:00.290026 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4568 23:22:00.293635 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4569 23:22:00.296839 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4570 23:22:00.299932 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4571 23:22:00.300045
4572 23:22:00.300145
4573 23:22:00.310297 [DQSOSCAuto] RK0, (LSB)MR18= 0x446a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4574 23:22:00.313539 CH1 RK0: MR19=808, MR18=446A
4575 23:22:00.316656 CH1_RK0: MR19=0x808, MR18=0x446A, DQSOSC=389, MR23=63, INC=173, DEC=115
4576 23:22:00.316770
4577 23:22:00.320306 ----->DramcWriteLeveling(PI) begin...
4578 23:22:00.323540 ==
4579 23:22:00.326772 Dram Type= 6, Freq= 0, CH_1, rank 1
4580 23:22:00.329925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 23:22:00.330013 ==
4582 23:22:00.333461 Write leveling (Byte 0): 32 => 32
4583 23:22:00.336595 Write leveling (Byte 1): 33 => 33
4584 23:22:00.340159 DramcWriteLeveling(PI) end<-----
4585 23:22:00.340270
4586 23:22:00.340352 ==
4587 23:22:00.343218 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 23:22:00.346512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 23:22:00.346626 ==
4590 23:22:00.350429 [Gating] SW mode calibration
4591 23:22:00.356646 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4592 23:22:00.363183 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4593 23:22:00.366381 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 23:22:00.369895 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 23:22:00.376393 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 23:22:00.379648 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (0 1)
4597 23:22:00.383336 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4598 23:22:00.386451 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 23:22:00.393206 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 23:22:00.396388 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 23:22:00.399637 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 23:22:00.406344 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 23:22:00.410038 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4604 23:22:00.413200 0 10 12 | B1->B0 | 3f3f 3737 | 1 1 | (0 0) (0 0)
4605 23:22:00.419542 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 23:22:00.422889 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 23:22:00.426635 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 23:22:00.432928 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 23:22:00.436607 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 23:22:00.439643 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 23:22:00.446560 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 23:22:00.449765 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4613 23:22:00.453100 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 23:22:00.459646 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 23:22:00.463227 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 23:22:00.466348 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 23:22:00.472935 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 23:22:00.476694 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 23:22:00.479650 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 23:22:00.486029 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 23:22:00.489231 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 23:22:00.492602 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 23:22:00.499216 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 23:22:00.502611 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 23:22:00.506228 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 23:22:00.512799 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 23:22:00.515913 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 23:22:00.519278 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 23:22:00.522728 Total UI for P1: 0, mck2ui 16
4630 23:22:00.526238 best dqsien dly found for B0: ( 0, 13, 10)
4631 23:22:00.529168 Total UI for P1: 0, mck2ui 16
4632 23:22:00.532402 best dqsien dly found for B1: ( 0, 13, 10)
4633 23:22:00.536004 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4634 23:22:00.539203 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4635 23:22:00.539311
4636 23:22:00.542778 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4637 23:22:00.549277 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4638 23:22:00.549379 [Gating] SW calibration Done
4639 23:22:00.549496 ==
4640 23:22:00.552406 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 23:22:00.559192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 23:22:00.559337 ==
4643 23:22:00.559459 RX Vref Scan: 0
4644 23:22:00.559573
4645 23:22:00.562505 RX Vref 0 -> 0, step: 1
4646 23:22:00.562641
4647 23:22:00.565736 RX Delay -230 -> 252, step: 16
4648 23:22:00.569256 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4649 23:22:00.572436 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4650 23:22:00.575671 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4651 23:22:00.582533 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4652 23:22:00.585610 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4653 23:22:00.588993 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4654 23:22:00.592304 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4655 23:22:00.595614 iDelay=218, Bit 7, Center 57 (-86 ~ 201) 288
4656 23:22:00.602435 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4657 23:22:00.605746 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4658 23:22:00.609062 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4659 23:22:00.612499 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4660 23:22:00.618745 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4661 23:22:00.622314 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4662 23:22:00.625497 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4663 23:22:00.628954 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4664 23:22:00.629072 ==
4665 23:22:00.632138 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 23:22:00.638944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 23:22:00.639080 ==
4668 23:22:00.639197 DQS Delay:
4669 23:22:00.642047 DQS0 = 0, DQS1 = 0
4670 23:22:00.642174 DQM Delay:
4671 23:22:00.642283 DQM0 = 56, DQM1 = 52
4672 23:22:00.645229 DQ Delay:
4673 23:22:00.648485 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =57
4674 23:22:00.651801 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =57
4675 23:22:00.655204 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4676 23:22:00.658631 DQ12 =65, DQ13 =65, DQ14 =57, DQ15 =65
4677 23:22:00.658753
4678 23:22:00.658855
4679 23:22:00.658922 ==
4680 23:22:00.661785 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 23:22:00.665381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 23:22:00.665501 ==
4683 23:22:00.665607
4684 23:22:00.665700
4685 23:22:00.668572 TX Vref Scan disable
4686 23:22:00.668666 == TX Byte 0 ==
4687 23:22:00.675223 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4688 23:22:00.678244 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4689 23:22:00.681905 == TX Byte 1 ==
4690 23:22:00.685101 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4691 23:22:00.688323 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4692 23:22:00.688404 ==
4693 23:22:00.691864 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 23:22:00.695326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 23:22:00.695407 ==
4696 23:22:00.695471
4697 23:22:00.698294
4698 23:22:00.698383 TX Vref Scan disable
4699 23:22:00.702051 == TX Byte 0 ==
4700 23:22:00.705268 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4701 23:22:00.711726 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4702 23:22:00.711822 == TX Byte 1 ==
4703 23:22:00.715399 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4704 23:22:00.721906 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4705 23:22:00.722031
4706 23:22:00.722149 [DATLAT]
4707 23:22:00.722243 Freq=600, CH1 RK1
4708 23:22:00.722354
4709 23:22:00.725076 DATLAT Default: 0x9
4710 23:22:00.725207 0, 0xFFFF, sum = 0
4711 23:22:00.728254 1, 0xFFFF, sum = 0
4712 23:22:00.728397 2, 0xFFFF, sum = 0
4713 23:22:00.731786 3, 0xFFFF, sum = 0
4714 23:22:00.735238 4, 0xFFFF, sum = 0
4715 23:22:00.735378 5, 0xFFFF, sum = 0
4716 23:22:00.738415 6, 0xFFFF, sum = 0
4717 23:22:00.738550 7, 0xFFFF, sum = 0
4718 23:22:00.741568 8, 0x0, sum = 1
4719 23:22:00.741681 9, 0x0, sum = 2
4720 23:22:00.741779 10, 0x0, sum = 3
4721 23:22:00.744889 11, 0x0, sum = 4
4722 23:22:00.744969 best_step = 9
4723 23:22:00.745040
4724 23:22:00.745126 ==
4725 23:22:00.748199 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 23:22:00.754957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 23:22:00.755057 ==
4728 23:22:00.755126 RX Vref Scan: 0
4729 23:22:00.755188
4730 23:22:00.758033 RX Vref 0 -> 0, step: 1
4731 23:22:00.758112
4732 23:22:00.761408 RX Delay -163 -> 252, step: 8
4733 23:22:00.764916 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4734 23:22:00.771322 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4735 23:22:00.774968 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4736 23:22:00.778075 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4737 23:22:00.781605 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4738 23:22:00.784697 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4739 23:22:00.791418 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4740 23:22:00.794623 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4741 23:22:00.798222 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4742 23:22:00.801229 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4743 23:22:00.804603 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4744 23:22:00.811229 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4745 23:22:00.814541 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4746 23:22:00.817860 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4747 23:22:00.820979 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4748 23:22:00.827676 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4749 23:22:00.827785 ==
4750 23:22:00.831248 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 23:22:00.834394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 23:22:00.834476 ==
4753 23:22:00.834540 DQS Delay:
4754 23:22:00.837627 DQS0 = 0, DQS1 = 0
4755 23:22:00.837703 DQM Delay:
4756 23:22:00.841161 DQM0 = 48, DQM1 = 45
4757 23:22:00.841237 DQ Delay:
4758 23:22:00.844392 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4759 23:22:00.847560 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4760 23:22:00.851022 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4761 23:22:00.854424 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4762 23:22:00.854514
4763 23:22:00.854579
4764 23:22:00.861200 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e25, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4765 23:22:00.864368 CH1 RK1: MR19=808, MR18=6E25
4766 23:22:00.871205 CH1_RK1: MR19=0x808, MR18=0x6E25, DQSOSC=389, MR23=63, INC=173, DEC=115
4767 23:22:00.874453 [RxdqsGatingPostProcess] freq 600
4768 23:22:00.880967 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4769 23:22:00.884391 Pre-setting of DQS Precalculation
4770 23:22:00.887702 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4771 23:22:00.894558 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4772 23:22:00.901169 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4773 23:22:00.901333
4774 23:22:00.901453
4775 23:22:00.904230 [Calibration Summary] 1200 Mbps
4776 23:22:00.907484 CH 0, Rank 0
4777 23:22:00.907573 SW Impedance : PASS
4778 23:22:00.910989 DUTY Scan : NO K
4779 23:22:00.914157 ZQ Calibration : PASS
4780 23:22:00.914253 Jitter Meter : NO K
4781 23:22:00.917466 CBT Training : PASS
4782 23:22:00.920755 Write leveling : PASS
4783 23:22:00.920850 RX DQS gating : PASS
4784 23:22:00.924439 RX DQ/DQS(RDDQC) : PASS
4785 23:22:00.924526 TX DQ/DQS : PASS
4786 23:22:00.927713 RX DATLAT : PASS
4787 23:22:00.930878 RX DQ/DQS(Engine): PASS
4788 23:22:00.930963 TX OE : NO K
4789 23:22:00.934098 All Pass.
4790 23:22:00.934187
4791 23:22:00.934281 CH 0, Rank 1
4792 23:22:00.937742 SW Impedance : PASS
4793 23:22:00.937828 DUTY Scan : NO K
4794 23:22:00.940986 ZQ Calibration : PASS
4795 23:22:00.944162 Jitter Meter : NO K
4796 23:22:00.944250 CBT Training : PASS
4797 23:22:00.947692 Write leveling : PASS
4798 23:22:00.950792 RX DQS gating : PASS
4799 23:22:00.950928 RX DQ/DQS(RDDQC) : PASS
4800 23:22:00.953911 TX DQ/DQS : PASS
4801 23:22:00.957496 RX DATLAT : PASS
4802 23:22:00.957620 RX DQ/DQS(Engine): PASS
4803 23:22:00.960936 TX OE : NO K
4804 23:22:00.961067 All Pass.
4805 23:22:00.961175
4806 23:22:00.964023 CH 1, Rank 0
4807 23:22:00.964148 SW Impedance : PASS
4808 23:22:00.967259 DUTY Scan : NO K
4809 23:22:00.970941 ZQ Calibration : PASS
4810 23:22:00.971070 Jitter Meter : NO K
4811 23:22:00.974099 CBT Training : PASS
4812 23:22:00.974220 Write leveling : PASS
4813 23:22:00.977280 RX DQS gating : PASS
4814 23:22:00.980930 RX DQ/DQS(RDDQC) : PASS
4815 23:22:00.981064 TX DQ/DQS : PASS
4816 23:22:00.984161 RX DATLAT : PASS
4817 23:22:00.987239 RX DQ/DQS(Engine): PASS
4818 23:22:00.987324 TX OE : NO K
4819 23:22:00.990719 All Pass.
4820 23:22:00.990806
4821 23:22:00.990871 CH 1, Rank 1
4822 23:22:00.993838 SW Impedance : PASS
4823 23:22:00.993925 DUTY Scan : NO K
4824 23:22:00.996969 ZQ Calibration : PASS
4825 23:22:01.000549 Jitter Meter : NO K
4826 23:22:01.000631 CBT Training : PASS
4827 23:22:01.003690 Write leveling : PASS
4828 23:22:01.007072 RX DQS gating : PASS
4829 23:22:01.007153 RX DQ/DQS(RDDQC) : PASS
4830 23:22:01.010257 TX DQ/DQS : PASS
4831 23:22:01.013795 RX DATLAT : PASS
4832 23:22:01.013925 RX DQ/DQS(Engine): PASS
4833 23:22:01.017175 TX OE : NO K
4834 23:22:01.017305 All Pass.
4835 23:22:01.017423
4836 23:22:01.020398 DramC Write-DBI off
4837 23:22:01.023622 PER_BANK_REFRESH: Hybrid Mode
4838 23:22:01.023748 TX_TRACKING: ON
4839 23:22:01.033444 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4840 23:22:01.036699 [FAST_K] Save calibration result to emmc
4841 23:22:01.040358 dramc_set_vcore_voltage set vcore to 662500
4842 23:22:01.043395 Read voltage for 933, 3
4843 23:22:01.043488 Vio18 = 0
4844 23:22:01.043574 Vcore = 662500
4845 23:22:01.047244 Vdram = 0
4846 23:22:01.047322 Vddq = 0
4847 23:22:01.047396 Vmddr = 0
4848 23:22:01.053885 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4849 23:22:01.056922 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4850 23:22:01.060532 MEM_TYPE=3, freq_sel=17
4851 23:22:01.063726 sv_algorithm_assistance_LP4_1600
4852 23:22:01.066994 ============ PULL DRAM RESETB DOWN ============
4853 23:22:01.070114 ========== PULL DRAM RESETB DOWN end =========
4854 23:22:01.076592 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4855 23:22:01.080139 ===================================
4856 23:22:01.080237 LPDDR4 DRAM CONFIGURATION
4857 23:22:01.083303 ===================================
4858 23:22:01.086578 EX_ROW_EN[0] = 0x0
4859 23:22:01.090287 EX_ROW_EN[1] = 0x0
4860 23:22:01.090405 LP4Y_EN = 0x0
4861 23:22:01.093363 WORK_FSP = 0x0
4862 23:22:01.093454 WL = 0x3
4863 23:22:01.096712 RL = 0x3
4864 23:22:01.096801 BL = 0x2
4865 23:22:01.100021 RPST = 0x0
4866 23:22:01.100111 RD_PRE = 0x0
4867 23:22:01.103190 WR_PRE = 0x1
4868 23:22:01.103316 WR_PST = 0x0
4869 23:22:01.106863 DBI_WR = 0x0
4870 23:22:01.106949 DBI_RD = 0x0
4871 23:22:01.109916 OTF = 0x1
4872 23:22:01.113470 ===================================
4873 23:22:01.116605 ===================================
4874 23:22:01.116692 ANA top config
4875 23:22:01.120063 ===================================
4876 23:22:01.123059 DLL_ASYNC_EN = 0
4877 23:22:01.126302 ALL_SLAVE_EN = 1
4878 23:22:01.129916 NEW_RANK_MODE = 1
4879 23:22:01.130010 DLL_IDLE_MODE = 1
4880 23:22:01.133210 LP45_APHY_COMB_EN = 1
4881 23:22:01.136311 TX_ODT_DIS = 1
4882 23:22:01.139752 NEW_8X_MODE = 1
4883 23:22:01.143089 ===================================
4884 23:22:01.146261 ===================================
4885 23:22:01.149535 data_rate = 1866
4886 23:22:01.149651 CKR = 1
4887 23:22:01.153004 DQ_P2S_RATIO = 8
4888 23:22:01.156369 ===================================
4889 23:22:01.159776 CA_P2S_RATIO = 8
4890 23:22:01.162747 DQ_CA_OPEN = 0
4891 23:22:01.166458 DQ_SEMI_OPEN = 0
4892 23:22:01.169680 CA_SEMI_OPEN = 0
4893 23:22:01.169772 CA_FULL_RATE = 0
4894 23:22:01.172776 DQ_CKDIV4_EN = 1
4895 23:22:01.176253 CA_CKDIV4_EN = 1
4896 23:22:01.179521 CA_PREDIV_EN = 0
4897 23:22:01.182709 PH8_DLY = 0
4898 23:22:01.186265 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4899 23:22:01.186361 DQ_AAMCK_DIV = 4
4900 23:22:01.189417 CA_AAMCK_DIV = 4
4901 23:22:01.192644 CA_ADMCK_DIV = 4
4902 23:22:01.196336 DQ_TRACK_CA_EN = 0
4903 23:22:01.199562 CA_PICK = 933
4904 23:22:01.202957 CA_MCKIO = 933
4905 23:22:01.203047 MCKIO_SEMI = 0
4906 23:22:01.206068 PLL_FREQ = 3732
4907 23:22:01.209263 DQ_UI_PI_RATIO = 32
4908 23:22:01.212788 CA_UI_PI_RATIO = 0
4909 23:22:01.215904 ===================================
4910 23:22:01.219527 ===================================
4911 23:22:01.222656 memory_type:LPDDR4
4912 23:22:01.222749 GP_NUM : 10
4913 23:22:01.226287 SRAM_EN : 1
4914 23:22:01.229571 MD32_EN : 0
4915 23:22:01.232804 ===================================
4916 23:22:01.232896 [ANA_INIT] >>>>>>>>>>>>>>
4917 23:22:01.235938 <<<<<< [CONFIGURE PHASE]: ANA_TX
4918 23:22:01.239188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4919 23:22:01.242852 ===================================
4920 23:22:01.246038 data_rate = 1866,PCW = 0X8f00
4921 23:22:01.249105 ===================================
4922 23:22:01.252730 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4923 23:22:01.259038 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 23:22:01.262350 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 23:22:01.269211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4926 23:22:01.272658 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4927 23:22:01.275588 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4928 23:22:01.275679 [ANA_INIT] flow start
4929 23:22:01.279153 [ANA_INIT] PLL >>>>>>>>
4930 23:22:01.282320 [ANA_INIT] PLL <<<<<<<<
4931 23:22:01.285664 [ANA_INIT] MIDPI >>>>>>>>
4932 23:22:01.285788 [ANA_INIT] MIDPI <<<<<<<<
4933 23:22:01.288898 [ANA_INIT] DLL >>>>>>>>
4934 23:22:01.292438 [ANA_INIT] flow end
4935 23:22:01.295714 ============ LP4 DIFF to SE enter ============
4936 23:22:01.298856 ============ LP4 DIFF to SE exit ============
4937 23:22:01.302204 [ANA_INIT] <<<<<<<<<<<<<
4938 23:22:01.305729 [Flow] Enable top DCM control >>>>>
4939 23:22:01.308809 [Flow] Enable top DCM control <<<<<
4940 23:22:01.312158 Enable DLL master slave shuffle
4941 23:22:01.315352 ==============================================================
4942 23:22:01.318773 Gating Mode config
4943 23:22:01.322417 ==============================================================
4944 23:22:01.325508 Config description:
4945 23:22:01.335852 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4946 23:22:01.342379 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4947 23:22:01.345590 SELPH_MODE 0: By rank 1: By Phase
4948 23:22:01.352283 ==============================================================
4949 23:22:01.355437 GAT_TRACK_EN = 1
4950 23:22:01.359018 RX_GATING_MODE = 2
4951 23:22:01.362135 RX_GATING_TRACK_MODE = 2
4952 23:22:01.365720 SELPH_MODE = 1
4953 23:22:01.368790 PICG_EARLY_EN = 1
4954 23:22:01.368917 VALID_LAT_VALUE = 1
4955 23:22:01.375677 ==============================================================
4956 23:22:01.378894 Enter into Gating configuration >>>>
4957 23:22:01.382114 Exit from Gating configuration <<<<
4958 23:22:01.385623 Enter into DVFS_PRE_config >>>>>
4959 23:22:01.395421 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4960 23:22:01.398844 Exit from DVFS_PRE_config <<<<<
4961 23:22:01.402038 Enter into PICG configuration >>>>
4962 23:22:01.405257 Exit from PICG configuration <<<<
4963 23:22:01.408505 [RX_INPUT] configuration >>>>>
4964 23:22:01.411726 [RX_INPUT] configuration <<<<<
4965 23:22:01.418516 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4966 23:22:01.421914 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4967 23:22:01.428459 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 23:22:01.435170 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 23:22:01.441695 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 23:22:01.448258 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 23:22:01.451562 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4972 23:22:01.455231 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4973 23:22:01.458555 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4974 23:22:01.464821 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4975 23:22:01.468095 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4976 23:22:01.471530 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4977 23:22:01.475062 ===================================
4978 23:22:01.478476 LPDDR4 DRAM CONFIGURATION
4979 23:22:01.481523 ===================================
4980 23:22:01.481604 EX_ROW_EN[0] = 0x0
4981 23:22:01.484814 EX_ROW_EN[1] = 0x0
4982 23:22:01.484895 LP4Y_EN = 0x0
4983 23:22:01.488139 WORK_FSP = 0x0
4984 23:22:01.488247 WL = 0x3
4985 23:22:01.491652 RL = 0x3
4986 23:22:01.494970 BL = 0x2
4987 23:22:01.495083 RPST = 0x0
4988 23:22:01.498235 RD_PRE = 0x0
4989 23:22:01.498338 WR_PRE = 0x1
4990 23:22:01.501456 WR_PST = 0x0
4991 23:22:01.501571 DBI_WR = 0x0
4992 23:22:01.504981 DBI_RD = 0x0
4993 23:22:01.505058 OTF = 0x1
4994 23:22:01.508206 ===================================
4995 23:22:01.511399 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4996 23:22:01.518146 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4997 23:22:01.521527 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 23:22:01.524951 ===================================
4999 23:22:01.527959 LPDDR4 DRAM CONFIGURATION
5000 23:22:01.531367 ===================================
5001 23:22:01.531490 EX_ROW_EN[0] = 0x10
5002 23:22:01.534843 EX_ROW_EN[1] = 0x0
5003 23:22:01.534919 LP4Y_EN = 0x0
5004 23:22:01.538248 WORK_FSP = 0x0
5005 23:22:01.538372 WL = 0x3
5006 23:22:01.541413 RL = 0x3
5007 23:22:01.541488 BL = 0x2
5008 23:22:01.544724 RPST = 0x0
5009 23:22:01.544798 RD_PRE = 0x0
5010 23:22:01.547992 WR_PRE = 0x1
5011 23:22:01.548120 WR_PST = 0x0
5012 23:22:01.551281 DBI_WR = 0x0
5013 23:22:01.554670 DBI_RD = 0x0
5014 23:22:01.554754 OTF = 0x1
5015 23:22:01.558207 ===================================
5016 23:22:01.564578 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5017 23:22:01.568352 nWR fixed to 30
5018 23:22:01.571660 [ModeRegInit_LP4] CH0 RK0
5019 23:22:01.571782 [ModeRegInit_LP4] CH0 RK1
5020 23:22:01.574826 [ModeRegInit_LP4] CH1 RK0
5021 23:22:01.577999 [ModeRegInit_LP4] CH1 RK1
5022 23:22:01.578123 match AC timing 9
5023 23:22:01.584895 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5024 23:22:01.588281 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5025 23:22:01.591533 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5026 23:22:01.598192 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5027 23:22:01.601356 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5028 23:22:01.601437 ==
5029 23:22:01.604627 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 23:22:01.608050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5031 23:22:01.608128 ==
5032 23:22:01.614901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5033 23:22:01.621237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5034 23:22:01.624384 [CA 0] Center 37 (6~68) winsize 63
5035 23:22:01.627853 [CA 1] Center 37 (7~68) winsize 62
5036 23:22:01.631419 [CA 2] Center 34 (4~65) winsize 62
5037 23:22:01.634572 [CA 3] Center 33 (3~64) winsize 62
5038 23:22:01.637711 [CA 4] Center 33 (3~64) winsize 62
5039 23:22:01.641324 [CA 5] Center 32 (2~62) winsize 61
5040 23:22:01.641453
5041 23:22:01.644483 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5042 23:22:01.644598
5043 23:22:01.647695 [CATrainingPosCal] consider 1 rank data
5044 23:22:01.650882 u2DelayCellTimex100 = 270/100 ps
5045 23:22:01.654338 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5046 23:22:01.657709 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5047 23:22:01.660756 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5048 23:22:01.664330 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5049 23:22:01.667402 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5050 23:22:01.674125 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5051 23:22:01.674213
5052 23:22:01.677597 CA PerBit enable=1, Macro0, CA PI delay=32
5053 23:22:01.677718
5054 23:22:01.680989 [CBTSetCACLKResult] CA Dly = 32
5055 23:22:01.681100 CS Dly: 5 (0~36)
5056 23:22:01.681194 ==
5057 23:22:01.684112 Dram Type= 6, Freq= 0, CH_0, rank 1
5058 23:22:01.687566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 23:22:01.690725 ==
5060 23:22:01.694211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 23:22:01.700708 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5062 23:22:01.704172 [CA 0] Center 37 (6~68) winsize 63
5063 23:22:01.707719 [CA 1] Center 37 (7~68) winsize 62
5064 23:22:01.710853 [CA 2] Center 34 (4~65) winsize 62
5065 23:22:01.714090 [CA 3] Center 34 (3~65) winsize 63
5066 23:22:01.717641 [CA 4] Center 32 (2~63) winsize 62
5067 23:22:01.720793 [CA 5] Center 32 (2~62) winsize 61
5068 23:22:01.720876
5069 23:22:01.723973 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5070 23:22:01.724083
5071 23:22:01.727651 [CATrainingPosCal] consider 2 rank data
5072 23:22:01.730583 u2DelayCellTimex100 = 270/100 ps
5073 23:22:01.734044 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5074 23:22:01.737291 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5075 23:22:01.740509 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5076 23:22:01.743871 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5077 23:22:01.750725 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5078 23:22:01.754004 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5079 23:22:01.754108
5080 23:22:01.757036 CA PerBit enable=1, Macro0, CA PI delay=32
5081 23:22:01.757130
5082 23:22:01.760107 [CBTSetCACLKResult] CA Dly = 32
5083 23:22:01.760227 CS Dly: 5 (0~37)
5084 23:22:01.760346
5085 23:22:01.763611 ----->DramcWriteLeveling(PI) begin...
5086 23:22:01.763714 ==
5087 23:22:01.767074 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 23:22:01.773800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 23:22:01.773892 ==
5090 23:22:01.776996 Write leveling (Byte 0): 33 => 33
5091 23:22:01.780167 Write leveling (Byte 1): 32 => 32
5092 23:22:01.780259 DramcWriteLeveling(PI) end<-----
5093 23:22:01.783710
5094 23:22:01.783792 ==
5095 23:22:01.787258 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 23:22:01.790258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 23:22:01.790371 ==
5098 23:22:01.793685 [Gating] SW mode calibration
5099 23:22:01.800164 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5100 23:22:01.803649 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5101 23:22:01.810222 0 14 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5102 23:22:01.813617 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 23:22:01.816870 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 23:22:01.823685 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 23:22:01.826843 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 23:22:01.830091 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 23:22:01.836785 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5108 23:22:01.840281 0 14 28 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
5109 23:22:01.843411 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5110 23:22:01.850154 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 23:22:01.853322 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 23:22:01.856503 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 23:22:01.863476 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 23:22:01.866873 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 23:22:01.869817 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5116 23:22:01.876817 0 15 28 | B1->B0 | 2323 3837 | 0 1 | (0 0) (0 0)
5117 23:22:01.880000 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5118 23:22:01.883245 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 23:22:01.889822 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 23:22:01.893195 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 23:22:01.896572 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 23:22:01.903330 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 23:22:01.906550 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5124 23:22:01.909569 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5125 23:22:01.913017 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 23:22:01.919766 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 23:22:01.922861 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 23:22:01.926305 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 23:22:01.932744 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 23:22:01.936109 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 23:22:01.939397 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 23:22:01.946217 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 23:22:01.949640 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 23:22:01.952712 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 23:22:01.959385 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 23:22:01.962847 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 23:22:01.966119 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 23:22:01.972747 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 23:22:01.976174 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5140 23:22:01.979293 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5141 23:22:01.982877 Total UI for P1: 0, mck2ui 16
5142 23:22:01.986062 best dqsien dly found for B0: ( 1, 2, 24)
5143 23:22:01.992608 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5144 23:22:01.996221 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 23:22:01.999515 Total UI for P1: 0, mck2ui 16
5146 23:22:02.002787 best dqsien dly found for B1: ( 1, 3, 0)
5147 23:22:02.006077 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5148 23:22:02.009224 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5149 23:22:02.009349
5150 23:22:02.012769 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5151 23:22:02.015907 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5152 23:22:02.019375 [Gating] SW calibration Done
5153 23:22:02.019502 ==
5154 23:22:02.022661 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 23:22:02.026265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 23:22:02.026351 ==
5157 23:22:02.029430 RX Vref Scan: 0
5158 23:22:02.029530
5159 23:22:02.032456 RX Vref 0 -> 0, step: 1
5160 23:22:02.032586
5161 23:22:02.032703 RX Delay -80 -> 252, step: 8
5162 23:22:02.039193 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5163 23:22:02.042763 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5164 23:22:02.046212 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5165 23:22:02.049266 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5166 23:22:02.052628 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5167 23:22:02.055996 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5168 23:22:02.062687 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5169 23:22:02.065996 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5170 23:22:02.069403 iDelay=208, Bit 8, Center 83 (0 ~ 167) 168
5171 23:22:02.072526 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5172 23:22:02.075852 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5173 23:22:02.082817 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5174 23:22:02.086059 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5175 23:22:02.089315 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5176 23:22:02.092469 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5177 23:22:02.095868 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5178 23:22:02.095974 ==
5179 23:22:02.099380 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 23:22:02.102563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 23:22:02.106070 ==
5182 23:22:02.106199 DQS Delay:
5183 23:22:02.106266 DQS0 = 0, DQS1 = 0
5184 23:22:02.109364 DQM Delay:
5185 23:22:02.109479 DQM0 = 106, DQM1 = 93
5186 23:22:02.112518 DQ Delay:
5187 23:22:02.116156 DQ0 =107, DQ1 =111, DQ2 =99, DQ3 =99
5188 23:22:02.119388 DQ4 =111, DQ5 =95, DQ6 =115, DQ7 =115
5189 23:22:02.122900 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5190 23:22:02.126068 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5191 23:22:02.126241
5192 23:22:02.126389
5193 23:22:02.126535 ==
5194 23:22:02.129288 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 23:22:02.132893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 23:22:02.133057 ==
5197 23:22:02.133198
5198 23:22:02.133336
5199 23:22:02.136068 TX Vref Scan disable
5200 23:22:02.136225 == TX Byte 0 ==
5201 23:22:02.142695 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5202 23:22:02.145837 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5203 23:22:02.146008 == TX Byte 1 ==
5204 23:22:02.152373 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5205 23:22:02.156025 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5206 23:22:02.156148 ==
5207 23:22:02.159175 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 23:22:02.162330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 23:22:02.162478 ==
5210 23:22:02.162575
5211 23:22:02.162671
5212 23:22:02.165849 TX Vref Scan disable
5213 23:22:02.169329 == TX Byte 0 ==
5214 23:22:02.172575 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5215 23:22:02.175897 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5216 23:22:02.179072 == TX Byte 1 ==
5217 23:22:02.182489 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5218 23:22:02.185899 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5219 23:22:02.186012
5220 23:22:02.188797 [DATLAT]
5221 23:22:02.188896 Freq=933, CH0 RK0
5222 23:22:02.188958
5223 23:22:02.192456 DATLAT Default: 0xd
5224 23:22:02.192558 0, 0xFFFF, sum = 0
5225 23:22:02.195596 1, 0xFFFF, sum = 0
5226 23:22:02.195719 2, 0xFFFF, sum = 0
5227 23:22:02.198908 3, 0xFFFF, sum = 0
5228 23:22:02.199021 4, 0xFFFF, sum = 0
5229 23:22:02.202293 5, 0xFFFF, sum = 0
5230 23:22:02.202404 6, 0xFFFF, sum = 0
5231 23:22:02.205814 7, 0xFFFF, sum = 0
5232 23:22:02.205917 8, 0xFFFF, sum = 0
5233 23:22:02.209109 9, 0xFFFF, sum = 0
5234 23:22:02.209196 10, 0x0, sum = 1
5235 23:22:02.212256 11, 0x0, sum = 2
5236 23:22:02.212356 12, 0x0, sum = 3
5237 23:22:02.215725 13, 0x0, sum = 4
5238 23:22:02.215805 best_step = 11
5239 23:22:02.215888
5240 23:22:02.215967 ==
5241 23:22:02.219030 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 23:22:02.225624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 23:22:02.225739 ==
5244 23:22:02.225847 RX Vref Scan: 1
5245 23:22:02.225948
5246 23:22:02.229086 RX Vref 0 -> 0, step: 1
5247 23:22:02.229197
5248 23:22:02.232275 RX Delay -53 -> 252, step: 4
5249 23:22:02.232366
5250 23:22:02.235404 Set Vref, RX VrefLevel [Byte0]: 56
5251 23:22:02.239030 [Byte1]: 47
5252 23:22:02.239134
5253 23:22:02.242087 Final RX Vref Byte 0 = 56 to rank0
5254 23:22:02.245690 Final RX Vref Byte 1 = 47 to rank0
5255 23:22:02.248938 Final RX Vref Byte 0 = 56 to rank1
5256 23:22:02.252180 Final RX Vref Byte 1 = 47 to rank1==
5257 23:22:02.255713 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 23:22:02.258895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 23:22:02.259007 ==
5260 23:22:02.262499 DQS Delay:
5261 23:22:02.262632 DQS0 = 0, DQS1 = 0
5262 23:22:02.265616 DQM Delay:
5263 23:22:02.265732 DQM0 = 104, DQM1 = 94
5264 23:22:02.265835 DQ Delay:
5265 23:22:02.268799 DQ0 =102, DQ1 =104, DQ2 =104, DQ3 =102
5266 23:22:02.271943 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =110
5267 23:22:02.275332 DQ8 =84, DQ9 =82, DQ10 =96, DQ11 =90
5268 23:22:02.282348 DQ12 =98, DQ13 =98, DQ14 =106, DQ15 =100
5269 23:22:02.282482
5270 23:22:02.282601
5271 23:22:02.288763 [DQSOSCAuto] RK0, (LSB)MR18= 0x3229, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5272 23:22:02.292389 CH0 RK0: MR19=505, MR18=3229
5273 23:22:02.298778 CH0_RK0: MR19=0x505, MR18=0x3229, DQSOSC=406, MR23=63, INC=65, DEC=43
5274 23:22:02.298911
5275 23:22:02.301899 ----->DramcWriteLeveling(PI) begin...
5276 23:22:02.302041 ==
5277 23:22:02.305336 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 23:22:02.308746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 23:22:02.308931 ==
5280 23:22:02.312260 Write leveling (Byte 0): 34 => 34
5281 23:22:02.315737 Write leveling (Byte 1): 31 => 31
5282 23:22:02.318691 DramcWriteLeveling(PI) end<-----
5283 23:22:02.318840
5284 23:22:02.318959 ==
5285 23:22:02.321900 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 23:22:02.325108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 23:22:02.325242 ==
5288 23:22:02.328625 [Gating] SW mode calibration
5289 23:22:02.335036 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 23:22:02.341762 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 23:22:02.345297 0 14 0 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 1)
5292 23:22:02.348241 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 23:22:02.355199 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 23:22:02.358237 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 23:22:02.361635 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 23:22:02.368209 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 23:22:02.371444 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 23:22:02.375071 0 14 28 | B1->B0 | 2525 2929 | 0 0 | (0 0) (0 1)
5299 23:22:02.381758 0 15 0 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
5300 23:22:02.385065 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 23:22:02.388448 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 23:22:02.395009 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 23:22:02.398211 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 23:22:02.401514 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 23:22:02.408412 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 23:22:02.411366 0 15 28 | B1->B0 | 3a3a 3535 | 0 1 | (0 0) (0 0)
5307 23:22:02.414916 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 23:22:02.421287 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 23:22:02.424897 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 23:22:02.428165 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 23:22:02.434596 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 23:22:02.437979 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 23:22:02.441456 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 23:22:02.447661 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5315 23:22:02.451156 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 23:22:02.454532 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 23:22:02.461251 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 23:22:02.464239 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 23:22:02.467658 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 23:22:02.474523 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 23:22:02.477545 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 23:22:02.481251 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 23:22:02.487728 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 23:22:02.490846 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 23:22:02.494308 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 23:22:02.500683 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 23:22:02.504395 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 23:22:02.507613 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 23:22:02.514104 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 23:22:02.517604 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5331 23:22:02.520761 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 23:22:02.524438 Total UI for P1: 0, mck2ui 16
5333 23:22:02.527553 best dqsien dly found for B0: ( 1, 2, 28)
5334 23:22:02.530735 Total UI for P1: 0, mck2ui 16
5335 23:22:02.534297 best dqsien dly found for B1: ( 1, 2, 28)
5336 23:22:02.537187 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5337 23:22:02.540843 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5338 23:22:02.540918
5339 23:22:02.544104 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5340 23:22:02.550496 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5341 23:22:02.550618 [Gating] SW calibration Done
5342 23:22:02.550732 ==
5343 23:22:02.553782 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 23:22:02.560651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 23:22:02.560733 ==
5346 23:22:02.560796 RX Vref Scan: 0
5347 23:22:02.560854
5348 23:22:02.563652 RX Vref 0 -> 0, step: 1
5349 23:22:02.563753
5350 23:22:02.567068 RX Delay -80 -> 252, step: 8
5351 23:22:02.570427 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5352 23:22:02.573955 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5353 23:22:02.577211 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5354 23:22:02.583682 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5355 23:22:02.587175 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5356 23:22:02.590339 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5357 23:22:02.593701 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5358 23:22:02.597040 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5359 23:22:02.600180 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5360 23:22:02.606909 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5361 23:22:02.610303 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5362 23:22:02.613717 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5363 23:22:02.616916 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5364 23:22:02.620251 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5365 23:22:02.623713 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5366 23:22:02.630217 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5367 23:22:02.630330 ==
5368 23:22:02.633727 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 23:22:02.636968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 23:22:02.637068 ==
5371 23:22:02.637159 DQS Delay:
5372 23:22:02.640215 DQS0 = 0, DQS1 = 0
5373 23:22:02.640308 DQM Delay:
5374 23:22:02.643428 DQM0 = 105, DQM1 = 93
5375 23:22:02.643510 DQ Delay:
5376 23:22:02.647031 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5377 23:22:02.650264 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5378 23:22:02.653457 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5379 23:22:02.656766 DQ12 =95, DQ13 =103, DQ14 =103, DQ15 =99
5380 23:22:02.656850
5381 23:22:02.656916
5382 23:22:02.656976 ==
5383 23:22:02.660135 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 23:22:02.666649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 23:22:02.666735 ==
5386 23:22:02.666801
5387 23:22:02.666861
5388 23:22:02.666919 TX Vref Scan disable
5389 23:22:02.670716 == TX Byte 0 ==
5390 23:22:02.673586 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5391 23:22:02.680152 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5392 23:22:02.680271 == TX Byte 1 ==
5393 23:22:02.683849 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5394 23:22:02.687065 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5395 23:22:02.690183 ==
5396 23:22:02.693477 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 23:22:02.697059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 23:22:02.697160 ==
5399 23:22:02.697223
5400 23:22:02.697282
5401 23:22:02.700035 TX Vref Scan disable
5402 23:22:02.700111 == TX Byte 0 ==
5403 23:22:02.706872 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5404 23:22:02.710139 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5405 23:22:02.710225 == TX Byte 1 ==
5406 23:22:02.716872 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5407 23:22:02.720052 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5408 23:22:02.720130
5409 23:22:02.720198 [DATLAT]
5410 23:22:02.723369 Freq=933, CH0 RK1
5411 23:22:02.723445
5412 23:22:02.723512 DATLAT Default: 0xb
5413 23:22:02.726643 0, 0xFFFF, sum = 0
5414 23:22:02.726776 1, 0xFFFF, sum = 0
5415 23:22:02.729922 2, 0xFFFF, sum = 0
5416 23:22:02.730034 3, 0xFFFF, sum = 0
5417 23:22:02.733460 4, 0xFFFF, sum = 0
5418 23:22:02.736708 5, 0xFFFF, sum = 0
5419 23:22:02.736806 6, 0xFFFF, sum = 0
5420 23:22:02.740151 7, 0xFFFF, sum = 0
5421 23:22:02.740254 8, 0xFFFF, sum = 0
5422 23:22:02.743565 9, 0xFFFF, sum = 0
5423 23:22:02.743640 10, 0x0, sum = 1
5424 23:22:02.746900 11, 0x0, sum = 2
5425 23:22:02.746981 12, 0x0, sum = 3
5426 23:22:02.747049 13, 0x0, sum = 4
5427 23:22:02.750202 best_step = 11
5428 23:22:02.750285
5429 23:22:02.750355 ==
5430 23:22:02.753447 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 23:22:02.756528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 23:22:02.756605 ==
5433 23:22:02.760224 RX Vref Scan: 0
5434 23:22:02.760327
5435 23:22:02.760412 RX Vref 0 -> 0, step: 1
5436 23:22:02.763486
5437 23:22:02.763569 RX Delay -53 -> 252, step: 4
5438 23:22:02.770978 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5439 23:22:02.774220 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5440 23:22:02.777394 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5441 23:22:02.780601 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5442 23:22:02.784083 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5443 23:22:02.790682 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5444 23:22:02.793907 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5445 23:22:02.797101 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5446 23:22:02.800583 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5447 23:22:02.803769 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5448 23:22:02.810618 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5449 23:22:02.813775 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5450 23:22:02.817267 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5451 23:22:02.820395 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5452 23:22:02.823628 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5453 23:22:02.830693 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5454 23:22:02.830774 ==
5455 23:22:02.833777 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 23:22:02.837253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 23:22:02.837337 ==
5458 23:22:02.837404 DQS Delay:
5459 23:22:02.840860 DQS0 = 0, DQS1 = 0
5460 23:22:02.840966 DQM Delay:
5461 23:22:02.844090 DQM0 = 104, DQM1 = 93
5462 23:22:02.844191 DQ Delay:
5463 23:22:02.847141 DQ0 =100, DQ1 =108, DQ2 =102, DQ3 =102
5464 23:22:02.850404 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5465 23:22:02.854140 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =86
5466 23:22:02.857228 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5467 23:22:02.857320
5468 23:22:02.857393
5469 23:22:02.867029 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5470 23:22:02.867154 CH0 RK1: MR19=505, MR18=2A03
5471 23:22:02.873923 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5472 23:22:02.877192 [RxdqsGatingPostProcess] freq 933
5473 23:22:02.883917 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5474 23:22:02.887193 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 23:22:02.890398 best DQS1 dly(2T, 0.5T) = (0, 11)
5476 23:22:02.893766 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 23:22:02.897052 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5478 23:22:02.900458 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 23:22:02.900566 best DQS1 dly(2T, 0.5T) = (0, 10)
5480 23:22:02.903468 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 23:22:02.907189 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5482 23:22:02.910421 Pre-setting of DQS Precalculation
5483 23:22:02.916774 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5484 23:22:02.916854 ==
5485 23:22:02.920202 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 23:22:02.923389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 23:22:02.923466 ==
5488 23:22:02.930255 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5489 23:22:02.936849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5490 23:22:02.939812 [CA 0] Center 36 (6~67) winsize 62
5491 23:22:02.943493 [CA 1] Center 37 (6~68) winsize 63
5492 23:22:02.946345 [CA 2] Center 34 (4~65) winsize 62
5493 23:22:02.950064 [CA 3] Center 34 (4~65) winsize 62
5494 23:22:02.953045 [CA 4] Center 34 (4~64) winsize 61
5495 23:22:02.956522 [CA 5] Center 33 (3~64) winsize 62
5496 23:22:02.956603
5497 23:22:02.959942 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5498 23:22:02.960052
5499 23:22:02.962870 [CATrainingPosCal] consider 1 rank data
5500 23:22:02.966331 u2DelayCellTimex100 = 270/100 ps
5501 23:22:02.969649 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 23:22:02.973127 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5503 23:22:02.976350 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5504 23:22:02.979742 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5505 23:22:02.982955 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5506 23:22:02.986380 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5507 23:22:02.986499
5508 23:22:02.993122 CA PerBit enable=1, Macro0, CA PI delay=33
5509 23:22:02.993245
5510 23:22:02.996146 [CBTSetCACLKResult] CA Dly = 33
5511 23:22:02.996256 CS Dly: 7 (0~38)
5512 23:22:02.996348 ==
5513 23:22:02.999825 Dram Type= 6, Freq= 0, CH_1, rank 1
5514 23:22:03.002888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 23:22:03.002965 ==
5516 23:22:03.009666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 23:22:03.016326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5518 23:22:03.019768 [CA 0] Center 37 (6~68) winsize 63
5519 23:22:03.023104 [CA 1] Center 37 (7~68) winsize 62
5520 23:22:03.026055 [CA 2] Center 35 (4~66) winsize 63
5521 23:22:03.029777 [CA 3] Center 34 (4~65) winsize 62
5522 23:22:03.032999 [CA 4] Center 34 (4~65) winsize 62
5523 23:22:03.036276 [CA 5] Center 34 (4~64) winsize 61
5524 23:22:03.036391
5525 23:22:03.039442 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5526 23:22:03.039561
5527 23:22:03.042972 [CATrainingPosCal] consider 2 rank data
5528 23:22:03.046170 u2DelayCellTimex100 = 270/100 ps
5529 23:22:03.049420 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5530 23:22:03.053059 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5531 23:22:03.056349 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5532 23:22:03.059435 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5533 23:22:03.062890 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5534 23:22:03.065965 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5535 23:22:03.066066
5536 23:22:03.073085 CA PerBit enable=1, Macro0, CA PI delay=34
5537 23:22:03.073215
5538 23:22:03.076235 [CBTSetCACLKResult] CA Dly = 34
5539 23:22:03.076418 CS Dly: 7 (0~39)
5540 23:22:03.076560
5541 23:22:03.079682 ----->DramcWriteLeveling(PI) begin...
5542 23:22:03.079800 ==
5543 23:22:03.082985 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 23:22:03.086314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 23:22:03.086487 ==
5546 23:22:03.089396 Write leveling (Byte 0): 25 => 25
5547 23:22:03.092724 Write leveling (Byte 1): 25 => 25
5548 23:22:03.096018 DramcWriteLeveling(PI) end<-----
5549 23:22:03.096159
5550 23:22:03.096268 ==
5551 23:22:03.099246 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 23:22:03.106080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 23:22:03.106227 ==
5554 23:22:03.106351 [Gating] SW mode calibration
5555 23:22:03.116082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5556 23:22:03.119474 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5557 23:22:03.125739 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 23:22:03.129204 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 23:22:03.132383 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 23:22:03.139224 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 23:22:03.142395 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 23:22:03.145719 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 23:22:03.149206 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
5564 23:22:03.155572 0 14 28 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
5565 23:22:03.158817 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 23:22:03.162537 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 23:22:03.168844 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 23:22:03.172465 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 23:22:03.175585 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 23:22:03.182081 0 15 20 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
5571 23:22:03.185671 0 15 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
5572 23:22:03.188857 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5573 23:22:03.195392 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 23:22:03.198725 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 23:22:03.202325 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 23:22:03.208879 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 23:22:03.212304 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 23:22:03.215717 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 23:22:03.222174 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5580 23:22:03.225542 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 23:22:03.228761 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 23:22:03.235454 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 23:22:03.239027 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 23:22:03.242216 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 23:22:03.249143 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 23:22:03.252312 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 23:22:03.255832 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 23:22:03.258929 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 23:22:03.265757 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 23:22:03.268983 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 23:22:03.272314 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 23:22:03.278678 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 23:22:03.282337 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 23:22:03.285523 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 23:22:03.292015 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5596 23:22:03.295633 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 23:22:03.298930 Total UI for P1: 0, mck2ui 16
5598 23:22:03.302179 best dqsien dly found for B0: ( 1, 2, 26)
5599 23:22:03.305369 Total UI for P1: 0, mck2ui 16
5600 23:22:03.308940 best dqsien dly found for B1: ( 1, 2, 24)
5601 23:22:03.312156 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5602 23:22:03.315396 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5603 23:22:03.315473
5604 23:22:03.318600 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5605 23:22:03.321765 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5606 23:22:03.325304 [Gating] SW calibration Done
5607 23:22:03.325414 ==
5608 23:22:03.328363 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 23:22:03.335003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 23:22:03.335097 ==
5611 23:22:03.335163 RX Vref Scan: 0
5612 23:22:03.335227
5613 23:22:03.338372 RX Vref 0 -> 0, step: 1
5614 23:22:03.338456
5615 23:22:03.341959 RX Delay -80 -> 252, step: 8
5616 23:22:03.345047 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5617 23:22:03.348571 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5618 23:22:03.351688 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5619 23:22:03.354977 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5620 23:22:03.358525 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5621 23:22:03.365250 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5622 23:22:03.368420 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5623 23:22:03.371723 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5624 23:22:03.374936 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5625 23:22:03.378141 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5626 23:22:03.381822 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5627 23:22:03.388479 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5628 23:22:03.391566 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5629 23:22:03.395213 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5630 23:22:03.398506 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5631 23:22:03.401823 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5632 23:22:03.404936 ==
5633 23:22:03.405039 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 23:22:03.411777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 23:22:03.411864 ==
5636 23:22:03.411931 DQS Delay:
5637 23:22:03.415315 DQS0 = 0, DQS1 = 0
5638 23:22:03.415400 DQM Delay:
5639 23:22:03.418445 DQM0 = 102, DQM1 = 98
5640 23:22:03.418528 DQ Delay:
5641 23:22:03.421689 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5642 23:22:03.424895 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5643 23:22:03.428229 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5644 23:22:03.431928 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5645 23:22:03.432012
5646 23:22:03.432077
5647 23:22:03.432138 ==
5648 23:22:03.434749 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 23:22:03.438530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 23:22:03.438623 ==
5651 23:22:03.441838
5652 23:22:03.441923
5653 23:22:03.441988 TX Vref Scan disable
5654 23:22:03.444824 == TX Byte 0 ==
5655 23:22:03.448300 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5656 23:22:03.451510 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5657 23:22:03.454772 == TX Byte 1 ==
5658 23:22:03.458149 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5659 23:22:03.461590 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5660 23:22:03.461697 ==
5661 23:22:03.464889 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 23:22:03.471358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 23:22:03.471449 ==
5664 23:22:03.471523
5665 23:22:03.471584
5666 23:22:03.471645 TX Vref Scan disable
5667 23:22:03.475942 == TX Byte 0 ==
5668 23:22:03.479213 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5669 23:22:03.485616 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5670 23:22:03.485693 == TX Byte 1 ==
5671 23:22:03.489258 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5672 23:22:03.495827 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5673 23:22:03.495925
5674 23:22:03.495991 [DATLAT]
5675 23:22:03.496051 Freq=933, CH1 RK0
5676 23:22:03.496119
5677 23:22:03.499087 DATLAT Default: 0xd
5678 23:22:03.499208 0, 0xFFFF, sum = 0
5679 23:22:03.502254 1, 0xFFFF, sum = 0
5680 23:22:03.502376 2, 0xFFFF, sum = 0
5681 23:22:03.505674 3, 0xFFFF, sum = 0
5682 23:22:03.508939 4, 0xFFFF, sum = 0
5683 23:22:03.509050 5, 0xFFFF, sum = 0
5684 23:22:03.512197 6, 0xFFFF, sum = 0
5685 23:22:03.512305 7, 0xFFFF, sum = 0
5686 23:22:03.515412 8, 0xFFFF, sum = 0
5687 23:22:03.515494 9, 0xFFFF, sum = 0
5688 23:22:03.519155 10, 0x0, sum = 1
5689 23:22:03.519261 11, 0x0, sum = 2
5690 23:22:03.522275 12, 0x0, sum = 3
5691 23:22:03.522350 13, 0x0, sum = 4
5692 23:22:03.522413 best_step = 11
5693 23:22:03.522474
5694 23:22:03.525555 ==
5695 23:22:03.525635 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 23:22:03.532492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 23:22:03.532571 ==
5698 23:22:03.532634 RX Vref Scan: 1
5699 23:22:03.532719
5700 23:22:03.535683 RX Vref 0 -> 0, step: 1
5701 23:22:03.535757
5702 23:22:03.538810 RX Delay -45 -> 252, step: 4
5703 23:22:03.538900
5704 23:22:03.542029 Set Vref, RX VrefLevel [Byte0]: 55
5705 23:22:03.545404 [Byte1]: 52
5706 23:22:03.545525
5707 23:22:03.548664 Final RX Vref Byte 0 = 55 to rank0
5708 23:22:03.552218 Final RX Vref Byte 1 = 52 to rank0
5709 23:22:03.555345 Final RX Vref Byte 0 = 55 to rank1
5710 23:22:03.559040 Final RX Vref Byte 1 = 52 to rank1==
5711 23:22:03.562004 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 23:22:03.565369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 23:22:03.565445 ==
5714 23:22:03.568446 DQS Delay:
5715 23:22:03.568550 DQS0 = 0, DQS1 = 0
5716 23:22:03.571949 DQM Delay:
5717 23:22:03.572052 DQM0 = 103, DQM1 = 100
5718 23:22:03.575226 DQ Delay:
5719 23:22:03.575329 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5720 23:22:03.581774 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5721 23:22:03.585394 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5722 23:22:03.588621 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =108
5723 23:22:03.588697
5724 23:22:03.588759
5725 23:22:03.595451 [DQSOSCAuto] RK0, (LSB)MR18= 0x172e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5726 23:22:03.598778 CH1 RK0: MR19=505, MR18=172E
5727 23:22:03.605360 CH1_RK0: MR19=0x505, MR18=0x172E, DQSOSC=407, MR23=63, INC=65, DEC=43
5728 23:22:03.605462
5729 23:22:03.608515 ----->DramcWriteLeveling(PI) begin...
5730 23:22:03.608613 ==
5731 23:22:03.611762 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 23:22:03.615122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 23:22:03.615232 ==
5734 23:22:03.618264 Write leveling (Byte 0): 26 => 26
5735 23:22:03.621715 Write leveling (Byte 1): 30 => 30
5736 23:22:03.625055 DramcWriteLeveling(PI) end<-----
5737 23:22:03.625162
5738 23:22:03.625253 ==
5739 23:22:03.628270 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 23:22:03.631413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 23:22:03.635032 ==
5742 23:22:03.635162 [Gating] SW mode calibration
5743 23:22:03.644651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5744 23:22:03.647892 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5745 23:22:03.651137 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 23:22:03.657825 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 23:22:03.661189 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 23:22:03.664343 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 23:22:03.671171 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 23:22:03.674361 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 23:22:03.677675 0 14 24 | B1->B0 | 2929 2f2f | 0 1 | (1 0) (1 0)
5752 23:22:03.684486 0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5753 23:22:03.687347 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5754 23:22:03.691007 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 23:22:03.697250 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 23:22:03.700809 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 23:22:03.704263 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 23:22:03.710835 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 23:22:03.714140 0 15 24 | B1->B0 | 3838 2727 | 0 0 | (0 0) (0 0)
5760 23:22:03.717357 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5761 23:22:03.723798 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 23:22:03.727126 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 23:22:03.730618 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 23:22:03.737162 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 23:22:03.740660 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 23:22:03.743656 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 23:22:03.750613 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5768 23:22:03.753736 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5769 23:22:03.757383 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 23:22:03.763679 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 23:22:03.767172 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 23:22:03.770457 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 23:22:03.776965 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 23:22:03.780250 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 23:22:03.783832 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 23:22:03.790429 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 23:22:03.793767 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 23:22:03.796822 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 23:22:03.803360 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 23:22:03.806893 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 23:22:03.810426 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 23:22:03.817052 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 23:22:03.820185 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5784 23:22:03.823447 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 23:22:03.827104 Total UI for P1: 0, mck2ui 16
5786 23:22:03.830330 best dqsien dly found for B0: ( 1, 2, 24)
5787 23:22:03.833531 Total UI for P1: 0, mck2ui 16
5788 23:22:03.836687 best dqsien dly found for B1: ( 1, 2, 24)
5789 23:22:03.840274 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5790 23:22:03.843519 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5791 23:22:03.843599
5792 23:22:03.847207 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5793 23:22:03.850357 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5794 23:22:03.853374 [Gating] SW calibration Done
5795 23:22:03.853506 ==
5796 23:22:03.856672 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 23:22:03.863305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 23:22:03.863432 ==
5799 23:22:03.863548 RX Vref Scan: 0
5800 23:22:03.863655
5801 23:22:03.866838 RX Vref 0 -> 0, step: 1
5802 23:22:03.866960
5803 23:22:03.869877 RX Delay -80 -> 252, step: 8
5804 23:22:03.873341 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5805 23:22:03.876558 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5806 23:22:03.880311 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5807 23:22:03.883556 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5808 23:22:03.889999 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5809 23:22:03.893336 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5810 23:22:03.896802 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5811 23:22:03.899872 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5812 23:22:03.903377 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5813 23:22:03.906582 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5814 23:22:03.910200 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5815 23:22:03.916678 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5816 23:22:03.920299 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5817 23:22:03.923456 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5818 23:22:03.926848 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5819 23:22:03.929815 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5820 23:22:03.933332 ==
5821 23:22:03.936483 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 23:22:03.940192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 23:22:03.940304 ==
5824 23:22:03.940385 DQS Delay:
5825 23:22:03.943401 DQS0 = 0, DQS1 = 0
5826 23:22:03.943500 DQM Delay:
5827 23:22:03.946652 DQM0 = 102, DQM1 = 99
5828 23:22:03.946725 DQ Delay:
5829 23:22:03.949920 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5830 23:22:03.953121 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5831 23:22:03.956315 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5832 23:22:03.959892 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5833 23:22:03.959995
5834 23:22:03.960059
5835 23:22:03.960118 ==
5836 23:22:03.963139 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 23:22:03.966595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 23:22:03.969614 ==
5839 23:22:03.969697
5840 23:22:03.969778
5841 23:22:03.969840 TX Vref Scan disable
5842 23:22:03.973122 == TX Byte 0 ==
5843 23:22:03.976194 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5844 23:22:03.979553 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5845 23:22:03.983250 == TX Byte 1 ==
5846 23:22:03.986432 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5847 23:22:03.989666 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5848 23:22:03.989743 ==
5849 23:22:03.993324 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 23:22:03.999822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 23:22:03.999927 ==
5852 23:22:04.000026
5853 23:22:04.000117
5854 23:22:04.002895 TX Vref Scan disable
5855 23:22:04.002969 == TX Byte 0 ==
5856 23:22:04.009771 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5857 23:22:04.012762 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5858 23:22:04.012846 == TX Byte 1 ==
5859 23:22:04.019373 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5860 23:22:04.022923 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5861 23:22:04.023007
5862 23:22:04.023071 [DATLAT]
5863 23:22:04.026362 Freq=933, CH1 RK1
5864 23:22:04.026473
5865 23:22:04.026567 DATLAT Default: 0xb
5866 23:22:04.029672 0, 0xFFFF, sum = 0
5867 23:22:04.029756 1, 0xFFFF, sum = 0
5868 23:22:04.032914 2, 0xFFFF, sum = 0
5869 23:22:04.033000 3, 0xFFFF, sum = 0
5870 23:22:04.035996 4, 0xFFFF, sum = 0
5871 23:22:04.036113 5, 0xFFFF, sum = 0
5872 23:22:04.039300 6, 0xFFFF, sum = 0
5873 23:22:04.039432 7, 0xFFFF, sum = 0
5874 23:22:04.042911 8, 0xFFFF, sum = 0
5875 23:22:04.043052 9, 0xFFFF, sum = 0
5876 23:22:04.046443 10, 0x0, sum = 1
5877 23:22:04.046570 11, 0x0, sum = 2
5878 23:22:04.049487 12, 0x0, sum = 3
5879 23:22:04.049610 13, 0x0, sum = 4
5880 23:22:04.052535 best_step = 11
5881 23:22:04.052664
5882 23:22:04.052783 ==
5883 23:22:04.055978 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 23:22:04.059459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 23:22:04.059561 ==
5886 23:22:04.062643 RX Vref Scan: 0
5887 23:22:04.062786
5888 23:22:04.062920 RX Vref 0 -> 0, step: 1
5889 23:22:04.063026
5890 23:22:04.066129 RX Delay -45 -> 252, step: 4
5891 23:22:04.073087 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5892 23:22:04.076613 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5893 23:22:04.079791 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5894 23:22:04.082823 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5895 23:22:04.086584 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5896 23:22:04.093074 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5897 23:22:04.096354 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5898 23:22:04.099469 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5899 23:22:04.103139 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5900 23:22:04.106225 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5901 23:22:04.113118 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5902 23:22:04.116277 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5903 23:22:04.119528 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5904 23:22:04.122761 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5905 23:22:04.126329 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5906 23:22:04.132678 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5907 23:22:04.132763 ==
5908 23:22:04.136547 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 23:22:04.139623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 23:22:04.139703 ==
5911 23:22:04.139767 DQS Delay:
5912 23:22:04.142694 DQS0 = 0, DQS1 = 0
5913 23:22:04.142769 DQM Delay:
5914 23:22:04.145880 DQM0 = 104, DQM1 = 100
5915 23:22:04.145964 DQ Delay:
5916 23:22:04.149535 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5917 23:22:04.152808 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =102
5918 23:22:04.156077 DQ8 =92, DQ9 =88, DQ10 =98, DQ11 =94
5919 23:22:04.159330 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5920 23:22:04.159415
5921 23:22:04.159480
5922 23:22:04.169301 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5923 23:22:04.172611 CH1 RK1: MR19=504, MR18=2AFD
5924 23:22:04.175867 CH1_RK1: MR19=0x504, MR18=0x2AFD, DQSOSC=408, MR23=63, INC=65, DEC=43
5925 23:22:04.179121 [RxdqsGatingPostProcess] freq 933
5926 23:22:04.185782 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5927 23:22:04.189041 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 23:22:04.192472 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 23:22:04.195685 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 23:22:04.199236 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 23:22:04.202252 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 23:22:04.205745 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 23:22:04.209007 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 23:22:04.212502 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 23:22:04.215799 Pre-setting of DQS Precalculation
5936 23:22:04.219045 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5937 23:22:04.225812 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5938 23:22:04.232129 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5939 23:22:04.232240
5940 23:22:04.232332
5941 23:22:04.235580 [Calibration Summary] 1866 Mbps
5942 23:22:04.238996 CH 0, Rank 0
5943 23:22:04.239080 SW Impedance : PASS
5944 23:22:04.242362 DUTY Scan : NO K
5945 23:22:04.245441 ZQ Calibration : PASS
5946 23:22:04.245548 Jitter Meter : NO K
5947 23:22:04.248900 CBT Training : PASS
5948 23:22:04.252075 Write leveling : PASS
5949 23:22:04.252187 RX DQS gating : PASS
5950 23:22:04.255727 RX DQ/DQS(RDDQC) : PASS
5951 23:22:04.258943 TX DQ/DQS : PASS
5952 23:22:04.259023 RX DATLAT : PASS
5953 23:22:04.262213 RX DQ/DQS(Engine): PASS
5954 23:22:04.265499 TX OE : NO K
5955 23:22:04.265574 All Pass.
5956 23:22:04.265637
5957 23:22:04.265698 CH 0, Rank 1
5958 23:22:04.268772 SW Impedance : PASS
5959 23:22:04.272141 DUTY Scan : NO K
5960 23:22:04.272241 ZQ Calibration : PASS
5961 23:22:04.275407 Jitter Meter : NO K
5962 23:22:04.275491 CBT Training : PASS
5963 23:22:04.278646 Write leveling : PASS
5964 23:22:04.282114 RX DQS gating : PASS
5965 23:22:04.282233 RX DQ/DQS(RDDQC) : PASS
5966 23:22:04.285255 TX DQ/DQS : PASS
5967 23:22:04.288515 RX DATLAT : PASS
5968 23:22:04.288645 RX DQ/DQS(Engine): PASS
5969 23:22:04.291906 TX OE : NO K
5970 23:22:04.292021 All Pass.
5971 23:22:04.292119
5972 23:22:04.295201 CH 1, Rank 0
5973 23:22:04.295315 SW Impedance : PASS
5974 23:22:04.298496 DUTY Scan : NO K
5975 23:22:04.301794 ZQ Calibration : PASS
5976 23:22:04.301912 Jitter Meter : NO K
5977 23:22:04.305263 CBT Training : PASS
5978 23:22:04.308368 Write leveling : PASS
5979 23:22:04.308495 RX DQS gating : PASS
5980 23:22:04.311857 RX DQ/DQS(RDDQC) : PASS
5981 23:22:04.315152 TX DQ/DQS : PASS
5982 23:22:04.315266 RX DATLAT : PASS
5983 23:22:04.318634 RX DQ/DQS(Engine): PASS
5984 23:22:04.318747 TX OE : NO K
5985 23:22:04.321764 All Pass.
5986 23:22:04.321881
5987 23:22:04.321980 CH 1, Rank 1
5988 23:22:04.325315 SW Impedance : PASS
5989 23:22:04.325424 DUTY Scan : NO K
5990 23:22:04.328371 ZQ Calibration : PASS
5991 23:22:04.331912 Jitter Meter : NO K
5992 23:22:04.332024 CBT Training : PASS
5993 23:22:04.335003 Write leveling : PASS
5994 23:22:04.338633 RX DQS gating : PASS
5995 23:22:04.338738 RX DQ/DQS(RDDQC) : PASS
5996 23:22:04.341868 TX DQ/DQS : PASS
5997 23:22:04.345275 RX DATLAT : PASS
5998 23:22:04.345393 RX DQ/DQS(Engine): PASS
5999 23:22:04.348409 TX OE : NO K
6000 23:22:04.348515 All Pass.
6001 23:22:04.348620
6002 23:22:04.351900 DramC Write-DBI off
6003 23:22:04.354948 PER_BANK_REFRESH: Hybrid Mode
6004 23:22:04.355053 TX_TRACKING: ON
6005 23:22:04.364881 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6006 23:22:04.368573 [FAST_K] Save calibration result to emmc
6007 23:22:04.371774 dramc_set_vcore_voltage set vcore to 650000
6008 23:22:04.375079 Read voltage for 400, 6
6009 23:22:04.375208 Vio18 = 0
6010 23:22:04.375327 Vcore = 650000
6011 23:22:04.378279 Vdram = 0
6012 23:22:04.378385 Vddq = 0
6013 23:22:04.378481 Vmddr = 0
6014 23:22:04.384997 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6015 23:22:04.388126 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6016 23:22:04.391776 MEM_TYPE=3, freq_sel=20
6017 23:22:04.395082 sv_algorithm_assistance_LP4_800
6018 23:22:04.398534 ============ PULL DRAM RESETB DOWN ============
6019 23:22:04.401689 ========== PULL DRAM RESETB DOWN end =========
6020 23:22:04.408217 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6021 23:22:04.411863 ===================================
6022 23:22:04.411979 LPDDR4 DRAM CONFIGURATION
6023 23:22:04.415019 ===================================
6024 23:22:04.418286 EX_ROW_EN[0] = 0x0
6025 23:22:04.421423 EX_ROW_EN[1] = 0x0
6026 23:22:04.421530 LP4Y_EN = 0x0
6027 23:22:04.425029 WORK_FSP = 0x0
6028 23:22:04.425134 WL = 0x2
6029 23:22:04.428092 RL = 0x2
6030 23:22:04.428194 BL = 0x2
6031 23:22:04.431310 RPST = 0x0
6032 23:22:04.431416 RD_PRE = 0x0
6033 23:22:04.434765 WR_PRE = 0x1
6034 23:22:04.434870 WR_PST = 0x0
6035 23:22:04.438289 DBI_WR = 0x0
6036 23:22:04.438398 DBI_RD = 0x0
6037 23:22:04.441538 OTF = 0x1
6038 23:22:04.444734 ===================================
6039 23:22:04.448304 ===================================
6040 23:22:04.448413 ANA top config
6041 23:22:04.451474 ===================================
6042 23:22:04.454567 DLL_ASYNC_EN = 0
6043 23:22:04.457757 ALL_SLAVE_EN = 1
6044 23:22:04.461332 NEW_RANK_MODE = 1
6045 23:22:04.461442 DLL_IDLE_MODE = 1
6046 23:22:04.464629 LP45_APHY_COMB_EN = 1
6047 23:22:04.467686 TX_ODT_DIS = 1
6048 23:22:04.471193 NEW_8X_MODE = 1
6049 23:22:04.474406 ===================================
6050 23:22:04.478002 ===================================
6051 23:22:04.481230 data_rate = 800
6052 23:22:04.481340 CKR = 1
6053 23:22:04.484432 DQ_P2S_RATIO = 4
6054 23:22:04.487903 ===================================
6055 23:22:04.491298 CA_P2S_RATIO = 4
6056 23:22:04.494552 DQ_CA_OPEN = 0
6057 23:22:04.497798 DQ_SEMI_OPEN = 1
6058 23:22:04.500937 CA_SEMI_OPEN = 1
6059 23:22:04.501047 CA_FULL_RATE = 0
6060 23:22:04.504392 DQ_CKDIV4_EN = 0
6061 23:22:04.507618 CA_CKDIV4_EN = 1
6062 23:22:04.510894 CA_PREDIV_EN = 0
6063 23:22:04.514173 PH8_DLY = 0
6064 23:22:04.517740 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6065 23:22:04.517849 DQ_AAMCK_DIV = 0
6066 23:22:04.521030 CA_AAMCK_DIV = 0
6067 23:22:04.524247 CA_ADMCK_DIV = 4
6068 23:22:04.527439 DQ_TRACK_CA_EN = 0
6069 23:22:04.530748 CA_PICK = 800
6070 23:22:04.533926 CA_MCKIO = 400
6071 23:22:04.537620 MCKIO_SEMI = 400
6072 23:22:04.537737 PLL_FREQ = 3016
6073 23:22:04.540653 DQ_UI_PI_RATIO = 32
6074 23:22:04.543997 CA_UI_PI_RATIO = 32
6075 23:22:04.547527 ===================================
6076 23:22:04.550836 ===================================
6077 23:22:04.554000 memory_type:LPDDR4
6078 23:22:04.557425 GP_NUM : 10
6079 23:22:04.557512 SRAM_EN : 1
6080 23:22:04.560974 MD32_EN : 0
6081 23:22:04.564032 ===================================
6082 23:22:04.564152 [ANA_INIT] >>>>>>>>>>>>>>
6083 23:22:04.567417 <<<<<< [CONFIGURE PHASE]: ANA_TX
6084 23:22:04.570531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6085 23:22:04.574182 ===================================
6086 23:22:04.577149 data_rate = 800,PCW = 0X7400
6087 23:22:04.580749 ===================================
6088 23:22:04.583803 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6089 23:22:04.590737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 23:22:04.600385 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 23:22:04.607151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6092 23:22:04.610339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6093 23:22:04.613525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6094 23:22:04.613604 [ANA_INIT] flow start
6095 23:22:04.617126 [ANA_INIT] PLL >>>>>>>>
6096 23:22:04.620304 [ANA_INIT] PLL <<<<<<<<
6097 23:22:04.620381 [ANA_INIT] MIDPI >>>>>>>>
6098 23:22:04.623569 [ANA_INIT] MIDPI <<<<<<<<
6099 23:22:04.627324 [ANA_INIT] DLL >>>>>>>>
6100 23:22:04.627403 [ANA_INIT] flow end
6101 23:22:04.633681 ============ LP4 DIFF to SE enter ============
6102 23:22:04.636876 ============ LP4 DIFF to SE exit ============
6103 23:22:04.640224 [ANA_INIT] <<<<<<<<<<<<<
6104 23:22:04.643461 [Flow] Enable top DCM control >>>>>
6105 23:22:04.647022 [Flow] Enable top DCM control <<<<<
6106 23:22:04.647154 Enable DLL master slave shuffle
6107 23:22:04.653672 ==============================================================
6108 23:22:04.656889 Gating Mode config
6109 23:22:04.660273 ==============================================================
6110 23:22:04.663639 Config description:
6111 23:22:04.673571 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6112 23:22:04.680040 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6113 23:22:04.683401 SELPH_MODE 0: By rank 1: By Phase
6114 23:22:04.690025 ==============================================================
6115 23:22:04.693685 GAT_TRACK_EN = 0
6116 23:22:04.696988 RX_GATING_MODE = 2
6117 23:22:04.700263 RX_GATING_TRACK_MODE = 2
6118 23:22:04.700406 SELPH_MODE = 1
6119 23:22:04.703319 PICG_EARLY_EN = 1
6120 23:22:04.706625 VALID_LAT_VALUE = 1
6121 23:22:04.713430 ==============================================================
6122 23:22:04.716547 Enter into Gating configuration >>>>
6123 23:22:04.720208 Exit from Gating configuration <<<<
6124 23:22:04.723437 Enter into DVFS_PRE_config >>>>>
6125 23:22:04.733538 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6126 23:22:04.736730 Exit from DVFS_PRE_config <<<<<
6127 23:22:04.739921 Enter into PICG configuration >>>>
6128 23:22:04.743090 Exit from PICG configuration <<<<
6129 23:22:04.746739 [RX_INPUT] configuration >>>>>
6130 23:22:04.749932 [RX_INPUT] configuration <<<<<
6131 23:22:04.753132 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6132 23:22:04.759999 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6133 23:22:04.766416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 23:22:04.773261 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 23:22:04.779634 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 23:22:04.783297 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 23:22:04.789672 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6138 23:22:04.793258 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6139 23:22:04.796426 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6140 23:22:04.799591 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6141 23:22:04.806444 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6142 23:22:04.809611 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6143 23:22:04.812908 ===================================
6144 23:22:04.816122 LPDDR4 DRAM CONFIGURATION
6145 23:22:04.819469 ===================================
6146 23:22:04.819567 EX_ROW_EN[0] = 0x0
6147 23:22:04.822873 EX_ROW_EN[1] = 0x0
6148 23:22:04.822970 LP4Y_EN = 0x0
6149 23:22:04.826105 WORK_FSP = 0x0
6150 23:22:04.826190 WL = 0x2
6151 23:22:04.829622 RL = 0x2
6152 23:22:04.829702 BL = 0x2
6153 23:22:04.833018 RPST = 0x0
6154 23:22:04.833105 RD_PRE = 0x0
6155 23:22:04.836261 WR_PRE = 0x1
6156 23:22:04.836359 WR_PST = 0x0
6157 23:22:04.839610 DBI_WR = 0x0
6158 23:22:04.842800 DBI_RD = 0x0
6159 23:22:04.842887 OTF = 0x1
6160 23:22:04.846364 ===================================
6161 23:22:04.849508 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6162 23:22:04.852985 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6163 23:22:04.859471 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 23:22:04.862769 ===================================
6165 23:22:04.865974 LPDDR4 DRAM CONFIGURATION
6166 23:22:04.869202 ===================================
6167 23:22:04.869315 EX_ROW_EN[0] = 0x10
6168 23:22:04.872684 EX_ROW_EN[1] = 0x0
6169 23:22:04.872762 LP4Y_EN = 0x0
6170 23:22:04.875892 WORK_FSP = 0x0
6171 23:22:04.875991 WL = 0x2
6172 23:22:04.879497 RL = 0x2
6173 23:22:04.879600 BL = 0x2
6174 23:22:04.882913 RPST = 0x0
6175 23:22:04.883001 RD_PRE = 0x0
6176 23:22:04.886121 WR_PRE = 0x1
6177 23:22:04.886194 WR_PST = 0x0
6178 23:22:04.889379 DBI_WR = 0x0
6179 23:22:04.889454 DBI_RD = 0x0
6180 23:22:04.892773 OTF = 0x1
6181 23:22:04.895930 ===================================
6182 23:22:04.902435 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6183 23:22:04.906287 nWR fixed to 30
6184 23:22:04.909506 [ModeRegInit_LP4] CH0 RK0
6185 23:22:04.909623 [ModeRegInit_LP4] CH0 RK1
6186 23:22:04.913051 [ModeRegInit_LP4] CH1 RK0
6187 23:22:04.916278 [ModeRegInit_LP4] CH1 RK1
6188 23:22:04.916371 match AC timing 19
6189 23:22:04.922665 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6190 23:22:04.925860 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6191 23:22:04.929197 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6192 23:22:04.936029 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6193 23:22:04.939330 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6194 23:22:04.939442 ==
6195 23:22:04.942570 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 23:22:04.945828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6197 23:22:04.945943 ==
6198 23:22:04.952530 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6199 23:22:04.959196 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6200 23:22:04.962303 [CA 0] Center 36 (8~64) winsize 57
6201 23:22:04.965720 [CA 1] Center 36 (8~64) winsize 57
6202 23:22:04.969142 [CA 2] Center 36 (8~64) winsize 57
6203 23:22:04.969223 [CA 3] Center 36 (8~64) winsize 57
6204 23:22:04.972413 [CA 4] Center 36 (8~64) winsize 57
6205 23:22:04.975588 [CA 5] Center 36 (8~64) winsize 57
6206 23:22:04.975699
6207 23:22:04.978857 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6208 23:22:04.982114
6209 23:22:04.985577 [CATrainingPosCal] consider 1 rank data
6210 23:22:04.985659 u2DelayCellTimex100 = 270/100 ps
6211 23:22:04.992403 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 23:22:04.995532 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 23:22:04.998911 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 23:22:05.002358 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 23:22:05.005489 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 23:22:05.009056 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 23:22:05.009135
6218 23:22:05.012274 CA PerBit enable=1, Macro0, CA PI delay=36
6219 23:22:05.012362
6220 23:22:05.015499 [CBTSetCACLKResult] CA Dly = 36
6221 23:22:05.018582 CS Dly: 1 (0~32)
6222 23:22:05.018693 ==
6223 23:22:05.022207 Dram Type= 6, Freq= 0, CH_0, rank 1
6224 23:22:05.025592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 23:22:05.025706 ==
6226 23:22:05.031948 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 23:22:05.035221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6228 23:22:05.038421 [CA 0] Center 36 (8~64) winsize 57
6229 23:22:05.041975 [CA 1] Center 36 (8~64) winsize 57
6230 23:22:05.045268 [CA 2] Center 36 (8~64) winsize 57
6231 23:22:05.048709 [CA 3] Center 36 (8~64) winsize 57
6232 23:22:05.051926 [CA 4] Center 36 (8~64) winsize 57
6233 23:22:05.055322 [CA 5] Center 36 (8~64) winsize 57
6234 23:22:05.055421
6235 23:22:05.058368 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6236 23:22:05.058473
6237 23:22:05.061951 [CATrainingPosCal] consider 2 rank data
6238 23:22:05.065074 u2DelayCellTimex100 = 270/100 ps
6239 23:22:05.068198 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 23:22:05.071926 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 23:22:05.078615 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 23:22:05.081677 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 23:22:05.085213 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 23:22:05.088595 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 23:22:05.088672
6246 23:22:05.091910 CA PerBit enable=1, Macro0, CA PI delay=36
6247 23:22:05.092012
6248 23:22:05.095167 [CBTSetCACLKResult] CA Dly = 36
6249 23:22:05.095275 CS Dly: 1 (0~32)
6250 23:22:05.095370
6251 23:22:05.098277 ----->DramcWriteLeveling(PI) begin...
6252 23:22:05.101778 ==
6253 23:22:05.101902 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 23:22:05.108306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 23:22:05.108429 ==
6256 23:22:05.111821 Write leveling (Byte 0): 40 => 8
6257 23:22:05.114960 Write leveling (Byte 1): 40 => 8
6258 23:22:05.115069 DramcWriteLeveling(PI) end<-----
6259 23:22:05.115170
6260 23:22:05.118331 ==
6261 23:22:05.121903 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 23:22:05.124949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 23:22:05.125055 ==
6264 23:22:05.128449 [Gating] SW mode calibration
6265 23:22:05.134930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6266 23:22:05.138095 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6267 23:22:05.144977 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 23:22:05.148255 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 23:22:05.151427 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 23:22:05.158318 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 23:22:05.161483 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 23:22:05.164773 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 23:22:05.171469 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 23:22:05.174685 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 23:22:05.178103 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 23:22:05.181279 Total UI for P1: 0, mck2ui 16
6277 23:22:05.184815 best dqsien dly found for B0: ( 0, 14, 24)
6278 23:22:05.188002 Total UI for P1: 0, mck2ui 16
6279 23:22:05.191499 best dqsien dly found for B1: ( 0, 14, 24)
6280 23:22:05.194627 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6281 23:22:05.197826 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6282 23:22:05.197946
6283 23:22:05.204623 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 23:22:05.207792 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 23:22:05.211497 [Gating] SW calibration Done
6286 23:22:05.211627 ==
6287 23:22:05.214750 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 23:22:05.218221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 23:22:05.218353 ==
6290 23:22:05.218471 RX Vref Scan: 0
6291 23:22:05.218586
6292 23:22:05.221231 RX Vref 0 -> 0, step: 1
6293 23:22:05.221360
6294 23:22:05.224683 RX Delay -410 -> 252, step: 16
6295 23:22:05.227917 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6296 23:22:05.234672 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6297 23:22:05.237947 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6298 23:22:05.241198 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6299 23:22:05.244524 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6300 23:22:05.247978 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6301 23:22:05.254450 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6302 23:22:05.257883 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6303 23:22:05.261114 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6304 23:22:05.264431 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6305 23:22:05.271373 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6306 23:22:05.274329 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6307 23:22:05.277520 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6308 23:22:05.284481 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6309 23:22:05.287671 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6310 23:22:05.290801 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6311 23:22:05.290885 ==
6312 23:22:05.294460 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 23:22:05.297614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 23:22:05.300838 ==
6315 23:22:05.300955 DQS Delay:
6316 23:22:05.301051 DQS0 = 27, DQS1 = 35
6317 23:22:05.303961 DQM Delay:
6318 23:22:05.304033 DQM0 = 10, DQM1 = 12
6319 23:22:05.307450 DQ Delay:
6320 23:22:05.307528 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6321 23:22:05.311185 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6322 23:22:05.314437 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6323 23:22:05.317493 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6324 23:22:05.317567
6325 23:22:05.317628
6326 23:22:05.317690 ==
6327 23:22:05.320804 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 23:22:05.327324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 23:22:05.327413 ==
6330 23:22:05.327477
6331 23:22:05.327536
6332 23:22:05.330659 TX Vref Scan disable
6333 23:22:05.330731 == TX Byte 0 ==
6334 23:22:05.334157 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 23:22:05.337347 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 23:22:05.340939 == TX Byte 1 ==
6337 23:22:05.344214 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 23:22:05.347453 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 23:22:05.350642 ==
6340 23:22:05.350748 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 23:22:05.357421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 23:22:05.357551 ==
6343 23:22:05.357651
6344 23:22:05.357746
6345 23:22:05.360961 TX Vref Scan disable
6346 23:22:05.361080 == TX Byte 0 ==
6347 23:22:05.363984 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 23:22:05.367537 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 23:22:05.370871 == TX Byte 1 ==
6350 23:22:05.374370 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 23:22:05.377424 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 23:22:05.377515
6353 23:22:05.380981 [DATLAT]
6354 23:22:05.381090 Freq=400, CH0 RK0
6355 23:22:05.381185
6356 23:22:05.384252 DATLAT Default: 0xf
6357 23:22:05.384354 0, 0xFFFF, sum = 0
6358 23:22:05.387724 1, 0xFFFF, sum = 0
6359 23:22:05.387834 2, 0xFFFF, sum = 0
6360 23:22:05.390786 3, 0xFFFF, sum = 0
6361 23:22:05.390894 4, 0xFFFF, sum = 0
6362 23:22:05.394130 5, 0xFFFF, sum = 0
6363 23:22:05.394246 6, 0xFFFF, sum = 0
6364 23:22:05.397493 7, 0xFFFF, sum = 0
6365 23:22:05.397601 8, 0xFFFF, sum = 0
6366 23:22:05.400900 9, 0xFFFF, sum = 0
6367 23:22:05.404131 10, 0xFFFF, sum = 0
6368 23:22:05.404236 11, 0xFFFF, sum = 0
6369 23:22:05.407419 12, 0xFFFF, sum = 0
6370 23:22:05.407531 13, 0x0, sum = 1
6371 23:22:05.410941 14, 0x0, sum = 2
6372 23:22:05.411052 15, 0x0, sum = 3
6373 23:22:05.411149 16, 0x0, sum = 4
6374 23:22:05.413961 best_step = 14
6375 23:22:05.414039
6376 23:22:05.414110 ==
6377 23:22:05.417230 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 23:22:05.420908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 23:22:05.420986 ==
6380 23:22:05.424262 RX Vref Scan: 1
6381 23:22:05.424354
6382 23:22:05.427328 RX Vref 0 -> 0, step: 1
6383 23:22:05.427443
6384 23:22:05.427542 RX Delay -311 -> 252, step: 8
6385 23:22:05.427637
6386 23:22:05.430785 Set Vref, RX VrefLevel [Byte0]: 56
6387 23:22:05.434185 [Byte1]: 47
6388 23:22:05.439314
6389 23:22:05.439420 Final RX Vref Byte 0 = 56 to rank0
6390 23:22:05.442878 Final RX Vref Byte 1 = 47 to rank0
6391 23:22:05.446116 Final RX Vref Byte 0 = 56 to rank1
6392 23:22:05.449214 Final RX Vref Byte 1 = 47 to rank1==
6393 23:22:05.452400 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 23:22:05.459362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 23:22:05.459488 ==
6396 23:22:05.459592 DQS Delay:
6397 23:22:05.459685 DQS0 = 28, DQS1 = 36
6398 23:22:05.462577 DQM Delay:
6399 23:22:05.462684 DQM0 = 10, DQM1 = 13
6400 23:22:05.465764 DQ Delay:
6401 23:22:05.468975 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6402 23:22:05.469055 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6403 23:22:05.472260 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6404 23:22:05.475470 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6405 23:22:05.475573
6406 23:22:05.479171
6407 23:22:05.485800 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6408 23:22:05.488966 CH0 RK0: MR19=C0C, MR18=CDBA
6409 23:22:05.495740 CH0_RK0: MR19=0xC0C, MR18=0xCDBA, DQSOSC=384, MR23=63, INC=400, DEC=267
6410 23:22:05.495855 ==
6411 23:22:05.498663 Dram Type= 6, Freq= 0, CH_0, rank 1
6412 23:22:05.502224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 23:22:05.502339 ==
6414 23:22:05.505433 [Gating] SW mode calibration
6415 23:22:05.512089 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6416 23:22:05.518739 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6417 23:22:05.521938 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 23:22:05.525301 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 23:22:05.532116 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 23:22:05.535608 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 23:22:05.538636 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 23:22:05.545144 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 23:22:05.548648 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 23:22:05.551919 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 23:22:05.558402 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 23:22:05.558487 Total UI for P1: 0, mck2ui 16
6427 23:22:05.561627 best dqsien dly found for B0: ( 0, 14, 24)
6428 23:22:05.565316 Total UI for P1: 0, mck2ui 16
6429 23:22:05.568393 best dqsien dly found for B1: ( 0, 14, 24)
6430 23:22:05.571639 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6431 23:22:05.578513 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6432 23:22:05.578619
6433 23:22:05.581741 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 23:22:05.584921 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 23:22:05.588163 [Gating] SW calibration Done
6436 23:22:05.588267 ==
6437 23:22:05.591402 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 23:22:05.594726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 23:22:05.594831 ==
6440 23:22:05.598226 RX Vref Scan: 0
6441 23:22:05.598333
6442 23:22:05.598436 RX Vref 0 -> 0, step: 1
6443 23:22:05.598536
6444 23:22:05.601515 RX Delay -410 -> 252, step: 16
6445 23:22:05.608040 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6446 23:22:05.611388 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6447 23:22:05.614854 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6448 23:22:05.618442 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6449 23:22:05.621570 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6450 23:22:05.628114 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6451 23:22:05.631649 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6452 23:22:05.634593 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6453 23:22:05.637937 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6454 23:22:05.644714 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6455 23:22:05.647870 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6456 23:22:05.651571 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6457 23:22:05.654848 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6458 23:22:05.661402 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6459 23:22:05.664617 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6460 23:22:05.667767 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6461 23:22:05.667870 ==
6462 23:22:05.671420 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 23:22:05.678035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 23:22:05.678119 ==
6465 23:22:05.678220 DQS Delay:
6466 23:22:05.681332 DQS0 = 19, DQS1 = 35
6467 23:22:05.681418 DQM Delay:
6468 23:22:05.681505 DQM0 = 5, DQM1 = 12
6469 23:22:05.684647 DQ Delay:
6470 23:22:05.687798 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6471 23:22:05.687911 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6472 23:22:05.691445 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6473 23:22:05.694763 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6474 23:22:05.694877
6475 23:22:05.694983
6476 23:22:05.697887 ==
6477 23:22:05.701521 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 23:22:05.704661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 23:22:05.704772 ==
6480 23:22:05.704877
6481 23:22:05.704976
6482 23:22:05.707885 TX Vref Scan disable
6483 23:22:05.707997 == TX Byte 0 ==
6484 23:22:05.711090 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6485 23:22:05.717908 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6486 23:22:05.718026 == TX Byte 1 ==
6487 23:22:05.720987 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6488 23:22:05.727515 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6489 23:22:05.727629 ==
6490 23:22:05.730799 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 23:22:05.734459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 23:22:05.734576 ==
6493 23:22:05.734673
6494 23:22:05.734762
6495 23:22:05.737818 TX Vref Scan disable
6496 23:22:05.737911 == TX Byte 0 ==
6497 23:22:05.741034 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6498 23:22:05.747562 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6499 23:22:05.747674 == TX Byte 1 ==
6500 23:22:05.751091 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6501 23:22:05.757588 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6502 23:22:05.757674
6503 23:22:05.757754 [DATLAT]
6504 23:22:05.757834 Freq=400, CH0 RK1
6505 23:22:05.757923
6506 23:22:05.760725 DATLAT Default: 0xe
6507 23:22:05.760812 0, 0xFFFF, sum = 0
6508 23:22:05.764283 1, 0xFFFF, sum = 0
6509 23:22:05.767419 2, 0xFFFF, sum = 0
6510 23:22:05.767525 3, 0xFFFF, sum = 0
6511 23:22:05.770876 4, 0xFFFF, sum = 0
6512 23:22:05.770985 5, 0xFFFF, sum = 0
6513 23:22:05.774055 6, 0xFFFF, sum = 0
6514 23:22:05.774166 7, 0xFFFF, sum = 0
6515 23:22:05.777404 8, 0xFFFF, sum = 0
6516 23:22:05.777513 9, 0xFFFF, sum = 0
6517 23:22:05.780824 10, 0xFFFF, sum = 0
6518 23:22:05.780917 11, 0xFFFF, sum = 0
6519 23:22:05.783784 12, 0xFFFF, sum = 0
6520 23:22:05.783896 13, 0x0, sum = 1
6521 23:22:05.787361 14, 0x0, sum = 2
6522 23:22:05.787476 15, 0x0, sum = 3
6523 23:22:05.790549 16, 0x0, sum = 4
6524 23:22:05.790657 best_step = 14
6525 23:22:05.790764
6526 23:22:05.790868 ==
6527 23:22:05.793725 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 23:22:05.797304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 23:22:05.800376 ==
6530 23:22:05.800465 RX Vref Scan: 0
6531 23:22:05.800532
6532 23:22:05.803991 RX Vref 0 -> 0, step: 1
6533 23:22:05.804088
6534 23:22:05.807001 RX Delay -311 -> 252, step: 8
6535 23:22:05.813835 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6536 23:22:05.817090 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6537 23:22:05.820142 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6538 23:22:05.823573 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6539 23:22:05.830175 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6540 23:22:05.833560 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6541 23:22:05.836759 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6542 23:22:05.840463 iDelay=217, Bit 7, Center -4 (-223 ~ 216) 440
6543 23:22:05.843723 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6544 23:22:05.850233 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6545 23:22:05.853364 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6546 23:22:05.856888 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6547 23:22:05.863307 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6548 23:22:05.866787 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6549 23:22:05.869886 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6550 23:22:05.873543 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6551 23:22:05.873658 ==
6552 23:22:05.876795 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 23:22:05.883325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 23:22:05.883442 ==
6555 23:22:05.883534 DQS Delay:
6556 23:22:05.886652 DQS0 = 24, DQS1 = 36
6557 23:22:05.886753 DQM Delay:
6558 23:22:05.886855 DQM0 = 9, DQM1 = 13
6559 23:22:05.890162 DQ Delay:
6560 23:22:05.893434 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6561 23:22:05.896679 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =20
6562 23:22:05.896782 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6563 23:22:05.900159 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6564 23:22:05.903423
6565 23:22:05.903532
6566 23:22:05.909914 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6567 23:22:05.913377 CH0 RK1: MR19=C0C, MR18=BD5C
6568 23:22:05.920210 CH0_RK1: MR19=0xC0C, MR18=0xBD5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6569 23:22:05.923544 [RxdqsGatingPostProcess] freq 400
6570 23:22:05.926654 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6571 23:22:05.929666 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 23:22:05.933354 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 23:22:05.936316 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 23:22:05.940031 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 23:22:05.942938 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 23:22:05.946633 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 23:22:05.949826 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 23:22:05.953186 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 23:22:05.956357 Pre-setting of DQS Precalculation
6580 23:22:05.959600 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6581 23:22:05.959709 ==
6582 23:22:05.963123 Dram Type= 6, Freq= 0, CH_1, rank 0
6583 23:22:05.969656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 23:22:05.969770 ==
6585 23:22:05.972900 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6586 23:22:05.979521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6587 23:22:05.983181 [CA 0] Center 36 (8~64) winsize 57
6588 23:22:05.986403 [CA 1] Center 36 (8~64) winsize 57
6589 23:22:05.989748 [CA 2] Center 36 (8~64) winsize 57
6590 23:22:05.992975 [CA 3] Center 36 (8~64) winsize 57
6591 23:22:05.996418 [CA 4] Center 36 (8~64) winsize 57
6592 23:22:05.999456 [CA 5] Center 36 (8~64) winsize 57
6593 23:22:05.999536
6594 23:22:06.002995 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6595 23:22:06.003103
6596 23:22:06.006115 [CATrainingPosCal] consider 1 rank data
6597 23:22:06.009671 u2DelayCellTimex100 = 270/100 ps
6598 23:22:06.012729 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 23:22:06.016267 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 23:22:06.019563 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 23:22:06.022580 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 23:22:06.025954 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 23:22:06.029383 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 23:22:06.029466
6605 23:22:06.035883 CA PerBit enable=1, Macro0, CA PI delay=36
6606 23:22:06.035977
6607 23:22:06.039187 [CBTSetCACLKResult] CA Dly = 36
6608 23:22:06.039295 CS Dly: 1 (0~32)
6609 23:22:06.039392 ==
6610 23:22:06.042773 Dram Type= 6, Freq= 0, CH_1, rank 1
6611 23:22:06.045767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 23:22:06.045846 ==
6613 23:22:06.052551 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 23:22:06.059119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6615 23:22:06.062456 [CA 0] Center 36 (8~64) winsize 57
6616 23:22:06.065777 [CA 1] Center 36 (8~64) winsize 57
6617 23:22:06.069497 [CA 2] Center 36 (8~64) winsize 57
6618 23:22:06.072659 [CA 3] Center 36 (8~64) winsize 57
6619 23:22:06.072744 [CA 4] Center 36 (8~64) winsize 57
6620 23:22:06.076016 [CA 5] Center 36 (8~64) winsize 57
6621 23:22:06.076133
6622 23:22:06.082745 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6623 23:22:06.082875
6624 23:22:06.085908 [CATrainingPosCal] consider 2 rank data
6625 23:22:06.089192 u2DelayCellTimex100 = 270/100 ps
6626 23:22:06.092514 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 23:22:06.095748 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 23:22:06.099344 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 23:22:06.102575 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 23:22:06.106075 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 23:22:06.109029 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 23:22:06.109126
6633 23:22:06.112417 CA PerBit enable=1, Macro0, CA PI delay=36
6634 23:22:06.112494
6635 23:22:06.115647 [CBTSetCACLKResult] CA Dly = 36
6636 23:22:06.119127 CS Dly: 1 (0~32)
6637 23:22:06.119202
6638 23:22:06.122723 ----->DramcWriteLeveling(PI) begin...
6639 23:22:06.122820 ==
6640 23:22:06.125962 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 23:22:06.129170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 23:22:06.129278 ==
6643 23:22:06.132521 Write leveling (Byte 0): 40 => 8
6644 23:22:06.135837 Write leveling (Byte 1): 40 => 8
6645 23:22:06.138947 DramcWriteLeveling(PI) end<-----
6646 23:22:06.139025
6647 23:22:06.139106 ==
6648 23:22:06.142419 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 23:22:06.145827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 23:22:06.145906 ==
6651 23:22:06.149342 [Gating] SW mode calibration
6652 23:22:06.155941 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6653 23:22:06.162431 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6654 23:22:06.165578 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 23:22:06.169212 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 23:22:06.175593 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 23:22:06.178884 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 23:22:06.182422 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 23:22:06.189032 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 23:22:06.192166 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 23:22:06.195442 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 23:22:06.202319 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 23:22:06.202404 Total UI for P1: 0, mck2ui 16
6664 23:22:06.208835 best dqsien dly found for B0: ( 0, 14, 24)
6665 23:22:06.208943 Total UI for P1: 0, mck2ui 16
6666 23:22:06.215585 best dqsien dly found for B1: ( 0, 14, 24)
6667 23:22:06.218970 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6668 23:22:06.221955 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6669 23:22:06.222039
6670 23:22:06.225391 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 23:22:06.228871 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 23:22:06.231947 [Gating] SW calibration Done
6673 23:22:06.232054 ==
6674 23:22:06.235652 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 23:22:06.238799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 23:22:06.238880 ==
6677 23:22:06.241912 RX Vref Scan: 0
6678 23:22:06.241994
6679 23:22:06.242077 RX Vref 0 -> 0, step: 1
6680 23:22:06.242180
6681 23:22:06.245598 RX Delay -410 -> 252, step: 16
6682 23:22:06.252043 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6683 23:22:06.255270 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6684 23:22:06.258556 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6685 23:22:06.262007 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6686 23:22:06.268776 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6687 23:22:06.272081 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6688 23:22:06.275672 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6689 23:22:06.278611 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6690 23:22:06.282287 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6691 23:22:06.288485 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6692 23:22:06.291903 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6693 23:22:06.295341 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6694 23:22:06.301838 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6695 23:22:06.305162 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6696 23:22:06.308921 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6697 23:22:06.312056 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6698 23:22:06.312170 ==
6699 23:22:06.315338 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 23:22:06.322147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 23:22:06.322270 ==
6702 23:22:06.322399 DQS Delay:
6703 23:22:06.325224 DQS0 = 35, DQS1 = 35
6704 23:22:06.325342 DQM Delay:
6705 23:22:06.325437 DQM0 = 18, DQM1 = 13
6706 23:22:06.328494 DQ Delay:
6707 23:22:06.331885 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6708 23:22:06.335352 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6709 23:22:06.338323 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6710 23:22:06.341862 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6711 23:22:06.341980
6712 23:22:06.342101
6713 23:22:06.342218 ==
6714 23:22:06.344941 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 23:22:06.348528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 23:22:06.348666 ==
6717 23:22:06.348788
6718 23:22:06.348930
6719 23:22:06.351713 TX Vref Scan disable
6720 23:22:06.351833 == TX Byte 0 ==
6721 23:22:06.358162 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 23:22:06.361784 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 23:22:06.361908 == TX Byte 1 ==
6724 23:22:06.368275 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 23:22:06.371408 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 23:22:06.371549 ==
6727 23:22:06.374992 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 23:22:06.378015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 23:22:06.378140 ==
6730 23:22:06.378255
6731 23:22:06.378368
6732 23:22:06.381548 TX Vref Scan disable
6733 23:22:06.381632 == TX Byte 0 ==
6734 23:22:06.387956 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 23:22:06.391536 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 23:22:06.391686 == TX Byte 1 ==
6737 23:22:06.397876 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 23:22:06.401334 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 23:22:06.401425
6740 23:22:06.401490 [DATLAT]
6741 23:22:06.404645 Freq=400, CH1 RK0
6742 23:22:06.404776
6743 23:22:06.404886 DATLAT Default: 0xf
6744 23:22:06.407894 0, 0xFFFF, sum = 0
6745 23:22:06.408023 1, 0xFFFF, sum = 0
6746 23:22:06.411520 2, 0xFFFF, sum = 0
6747 23:22:06.411649 3, 0xFFFF, sum = 0
6748 23:22:06.414702 4, 0xFFFF, sum = 0
6749 23:22:06.414828 5, 0xFFFF, sum = 0
6750 23:22:06.417844 6, 0xFFFF, sum = 0
6751 23:22:06.417966 7, 0xFFFF, sum = 0
6752 23:22:06.421195 8, 0xFFFF, sum = 0
6753 23:22:06.421317 9, 0xFFFF, sum = 0
6754 23:22:06.424380 10, 0xFFFF, sum = 0
6755 23:22:06.427869 11, 0xFFFF, sum = 0
6756 23:22:06.427991 12, 0xFFFF, sum = 0
6757 23:22:06.431074 13, 0x0, sum = 1
6758 23:22:06.431182 14, 0x0, sum = 2
6759 23:22:06.434895 15, 0x0, sum = 3
6760 23:22:06.435021 16, 0x0, sum = 4
6761 23:22:06.435138 best_step = 14
6762 23:22:06.435250
6763 23:22:06.438106 ==
6764 23:22:06.441278 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 23:22:06.444843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 23:22:06.444967 ==
6767 23:22:06.445083 RX Vref Scan: 1
6768 23:22:06.445196
6769 23:22:06.448160 RX Vref 0 -> 0, step: 1
6770 23:22:06.448279
6771 23:22:06.451395 RX Delay -311 -> 252, step: 8
6772 23:22:06.451501
6773 23:22:06.454394 Set Vref, RX VrefLevel [Byte0]: 55
6774 23:22:06.457867 [Byte1]: 52
6775 23:22:06.461124
6776 23:22:06.461233 Final RX Vref Byte 0 = 55 to rank0
6777 23:22:06.464321 Final RX Vref Byte 1 = 52 to rank0
6778 23:22:06.467693 Final RX Vref Byte 0 = 55 to rank1
6779 23:22:06.471351 Final RX Vref Byte 1 = 52 to rank1==
6780 23:22:06.474274 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 23:22:06.481278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 23:22:06.481368 ==
6783 23:22:06.481435 DQS Delay:
6784 23:22:06.484155 DQS0 = 28, DQS1 = 32
6785 23:22:06.484265 DQM Delay:
6786 23:22:06.484348 DQM0 = 9, DQM1 = 10
6787 23:22:06.487524 DQ Delay:
6788 23:22:06.490893 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6789 23:22:06.490986 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6790 23:22:06.494266 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6791 23:22:06.497785 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6792 23:22:06.497876
6793 23:22:06.497962
6794 23:22:06.507438 [DQSOSCAuto] RK0, (LSB)MR18= 0x8cc4, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6795 23:22:06.510941 CH1 RK0: MR19=C0C, MR18=8CC4
6796 23:22:06.517483 CH1_RK0: MR19=0xC0C, MR18=0x8CC4, DQSOSC=385, MR23=63, INC=398, DEC=265
6797 23:22:06.517573 ==
6798 23:22:06.520824 Dram Type= 6, Freq= 0, CH_1, rank 1
6799 23:22:06.524453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 23:22:06.524543 ==
6801 23:22:06.527680 [Gating] SW mode calibration
6802 23:22:06.534307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6803 23:22:06.537455 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6804 23:22:06.544402 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 23:22:06.547526 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 23:22:06.550784 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 23:22:06.557316 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 23:22:06.560427 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 23:22:06.563764 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 23:22:06.570558 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 23:22:06.573810 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 23:22:06.577310 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 23:22:06.580386 Total UI for P1: 0, mck2ui 16
6814 23:22:06.583651 best dqsien dly found for B0: ( 0, 14, 24)
6815 23:22:06.587374 Total UI for P1: 0, mck2ui 16
6816 23:22:06.590396 best dqsien dly found for B1: ( 0, 14, 24)
6817 23:22:06.593605 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6818 23:22:06.600469 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6819 23:22:06.600608
6820 23:22:06.603837 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 23:22:06.607144 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 23:22:06.610276 [Gating] SW calibration Done
6823 23:22:06.610406 ==
6824 23:22:06.613318 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 23:22:06.616808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 23:22:06.616936 ==
6827 23:22:06.620256 RX Vref Scan: 0
6828 23:22:06.620384
6829 23:22:06.620496 RX Vref 0 -> 0, step: 1
6830 23:22:06.620599
6831 23:22:06.623450 RX Delay -410 -> 252, step: 16
6832 23:22:06.626901 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6833 23:22:06.633400 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6834 23:22:06.636804 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6835 23:22:06.640167 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6836 23:22:06.643370 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6837 23:22:06.649904 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6838 23:22:06.653170 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6839 23:22:06.656413 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6840 23:22:06.659974 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6841 23:22:06.666384 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6842 23:22:06.670116 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6843 23:22:06.673199 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6844 23:22:06.676499 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6845 23:22:06.683254 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6846 23:22:06.686476 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6847 23:22:06.689766 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6848 23:22:06.689880 ==
6849 23:22:06.693040 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 23:22:06.699566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 23:22:06.699677 ==
6852 23:22:06.699784 DQS Delay:
6853 23:22:06.702951 DQS0 = 35, DQS1 = 35
6854 23:22:06.703053 DQM Delay:
6855 23:22:06.703145 DQM0 = 17, DQM1 = 13
6856 23:22:06.706401 DQ Delay:
6857 23:22:06.709776 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6858 23:22:06.712740 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6859 23:22:06.716106 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6860 23:22:06.719597 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6861 23:22:06.719712
6862 23:22:06.719806
6863 23:22:06.719899 ==
6864 23:22:06.722808 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 23:22:06.725980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 23:22:06.726057 ==
6867 23:22:06.726121
6868 23:22:06.726201
6869 23:22:06.729611 TX Vref Scan disable
6870 23:22:06.729720 == TX Byte 0 ==
6871 23:22:06.735942 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6872 23:22:06.739540 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6873 23:22:06.739651 == TX Byte 1 ==
6874 23:22:06.742709 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6875 23:22:06.749300 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6876 23:22:06.749422 ==
6877 23:22:06.752786 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 23:22:06.755970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 23:22:06.756071 ==
6880 23:22:06.756176
6881 23:22:06.756275
6882 23:22:06.759125 TX Vref Scan disable
6883 23:22:06.759232 == TX Byte 0 ==
6884 23:22:06.766107 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6885 23:22:06.769264 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6886 23:22:06.769375 == TX Byte 1 ==
6887 23:22:06.776081 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6888 23:22:06.779230 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6889 23:22:06.779339
6890 23:22:06.779436 [DATLAT]
6891 23:22:06.782744 Freq=400, CH1 RK1
6892 23:22:06.782849
6893 23:22:06.782954 DATLAT Default: 0xe
6894 23:22:06.785903 0, 0xFFFF, sum = 0
6895 23:22:06.786013 1, 0xFFFF, sum = 0
6896 23:22:06.789109 2, 0xFFFF, sum = 0
6897 23:22:06.789219 3, 0xFFFF, sum = 0
6898 23:22:06.792490 4, 0xFFFF, sum = 0
6899 23:22:06.792598 5, 0xFFFF, sum = 0
6900 23:22:06.796234 6, 0xFFFF, sum = 0
6901 23:22:06.796351 7, 0xFFFF, sum = 0
6902 23:22:06.799384 8, 0xFFFF, sum = 0
6903 23:22:06.799489 9, 0xFFFF, sum = 0
6904 23:22:06.802896 10, 0xFFFF, sum = 0
6905 23:22:06.803004 11, 0xFFFF, sum = 0
6906 23:22:06.805948 12, 0xFFFF, sum = 0
6907 23:22:06.806059 13, 0x0, sum = 1
6908 23:22:06.809188 14, 0x0, sum = 2
6909 23:22:06.809310 15, 0x0, sum = 3
6910 23:22:06.812839 16, 0x0, sum = 4
6911 23:22:06.812954 best_step = 14
6912 23:22:06.813060
6913 23:22:06.813161 ==
6914 23:22:06.815823 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 23:22:06.822744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 23:22:06.822859 ==
6917 23:22:06.822966 RX Vref Scan: 0
6918 23:22:06.823069
6919 23:22:06.826000 RX Vref 0 -> 0, step: 1
6920 23:22:06.826109
6921 23:22:06.829201 RX Delay -311 -> 252, step: 8
6922 23:22:06.836185 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6923 23:22:06.839384 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6924 23:22:06.842491 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6925 23:22:06.845798 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6926 23:22:06.852420 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6927 23:22:06.855752 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6928 23:22:06.858918 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6929 23:22:06.862469 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6930 23:22:06.865664 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6931 23:22:06.872542 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6932 23:22:06.875766 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6933 23:22:06.879099 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6934 23:22:06.885841 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6935 23:22:06.889080 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6936 23:22:06.892306 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6937 23:22:06.895661 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6938 23:22:06.895801 ==
6939 23:22:06.898947 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 23:22:06.905682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 23:22:06.905791 ==
6942 23:22:06.905903 DQS Delay:
6943 23:22:06.908969 DQS0 = 28, DQS1 = 32
6944 23:22:06.909156 DQM Delay:
6945 23:22:06.912210 DQM0 = 10, DQM1 = 11
6946 23:22:06.912342 DQ Delay:
6947 23:22:06.915424 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6948 23:22:06.918820 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6949 23:22:06.922336 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6950 23:22:06.925299 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6951 23:22:06.925406
6952 23:22:06.925513
6953 23:22:06.932060 [DQSOSCAuto] RK1, (LSB)MR18= 0xc558, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6954 23:22:06.935390 CH1 RK1: MR19=C0C, MR18=C558
6955 23:22:06.942139 CH1_RK1: MR19=0xC0C, MR18=0xC558, DQSOSC=385, MR23=63, INC=398, DEC=265
6956 23:22:06.945332 [RxdqsGatingPostProcess] freq 400
6957 23:22:06.948457 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6958 23:22:06.951989 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 23:22:06.955452 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 23:22:06.958404 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 23:22:06.961794 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 23:22:06.965220 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 23:22:06.968384 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 23:22:06.971800 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 23:22:06.975255 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 23:22:06.978409 Pre-setting of DQS Precalculation
6967 23:22:06.981794 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6968 23:22:06.991797 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6969 23:22:06.998327 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6970 23:22:06.998438
6971 23:22:06.998539
6972 23:22:07.001633 [Calibration Summary] 800 Mbps
6973 23:22:07.001748 CH 0, Rank 0
6974 23:22:07.004928 SW Impedance : PASS
6975 23:22:07.005076 DUTY Scan : NO K
6976 23:22:07.008635 ZQ Calibration : PASS
6977 23:22:07.011874 Jitter Meter : NO K
6978 23:22:07.011979 CBT Training : PASS
6979 23:22:07.015114 Write leveling : PASS
6980 23:22:07.018308 RX DQS gating : PASS
6981 23:22:07.018419 RX DQ/DQS(RDDQC) : PASS
6982 23:22:07.021781 TX DQ/DQS : PASS
6983 23:22:07.021893 RX DATLAT : PASS
6984 23:22:07.025209 RX DQ/DQS(Engine): PASS
6985 23:22:07.028449 TX OE : NO K
6986 23:22:07.028564 All Pass.
6987 23:22:07.028659
6988 23:22:07.028756 CH 0, Rank 1
6989 23:22:07.031784 SW Impedance : PASS
6990 23:22:07.034985 DUTY Scan : NO K
6991 23:22:07.035091 ZQ Calibration : PASS
6992 23:22:07.038639 Jitter Meter : NO K
6993 23:22:07.041562 CBT Training : PASS
6994 23:22:07.041670 Write leveling : NO K
6995 23:22:07.044844 RX DQS gating : PASS
6996 23:22:07.048346 RX DQ/DQS(RDDQC) : PASS
6997 23:22:07.048472 TX DQ/DQS : PASS
6998 23:22:07.051510 RX DATLAT : PASS
6999 23:22:07.055107 RX DQ/DQS(Engine): PASS
7000 23:22:07.055219 TX OE : NO K
7001 23:22:07.058267 All Pass.
7002 23:22:07.058379
7003 23:22:07.058479 CH 1, Rank 0
7004 23:22:07.061684 SW Impedance : PASS
7005 23:22:07.061792 DUTY Scan : NO K
7006 23:22:07.065181 ZQ Calibration : PASS
7007 23:22:07.068360 Jitter Meter : NO K
7008 23:22:07.068491 CBT Training : PASS
7009 23:22:07.071587 Write leveling : PASS
7010 23:22:07.071703 RX DQS gating : PASS
7011 23:22:07.075081 RX DQ/DQS(RDDQC) : PASS
7012 23:22:07.078401 TX DQ/DQS : PASS
7013 23:22:07.078523 RX DATLAT : PASS
7014 23:22:07.081674 RX DQ/DQS(Engine): PASS
7015 23:22:07.085255 TX OE : NO K
7016 23:22:07.085386 All Pass.
7017 23:22:07.085505
7018 23:22:07.085617 CH 1, Rank 1
7019 23:22:07.088362 SW Impedance : PASS
7020 23:22:07.091437 DUTY Scan : NO K
7021 23:22:07.091570 ZQ Calibration : PASS
7022 23:22:07.094844 Jitter Meter : NO K
7023 23:22:07.098197 CBT Training : PASS
7024 23:22:07.098324 Write leveling : NO K
7025 23:22:07.101472 RX DQS gating : PASS
7026 23:22:07.104618 RX DQ/DQS(RDDQC) : PASS
7027 23:22:07.104729 TX DQ/DQS : PASS
7028 23:22:07.108323 RX DATLAT : PASS
7029 23:22:07.111556 RX DQ/DQS(Engine): PASS
7030 23:22:07.111663 TX OE : NO K
7031 23:22:07.111763 All Pass.
7032 23:22:07.114769
7033 23:22:07.114874 DramC Write-DBI off
7034 23:22:07.117973 PER_BANK_REFRESH: Hybrid Mode
7035 23:22:07.118078 TX_TRACKING: ON
7036 23:22:07.128009 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7037 23:22:07.131463 [FAST_K] Save calibration result to emmc
7038 23:22:07.134711 dramc_set_vcore_voltage set vcore to 725000
7039 23:22:07.137898 Read voltage for 1600, 0
7040 23:22:07.138000 Vio18 = 0
7041 23:22:07.141483 Vcore = 725000
7042 23:22:07.141591 Vdram = 0
7043 23:22:07.141689 Vddq = 0
7044 23:22:07.141782 Vmddr = 0
7045 23:22:07.147942 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7046 23:22:07.154829 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7047 23:22:07.154939 MEM_TYPE=3, freq_sel=13
7048 23:22:07.158175 sv_algorithm_assistance_LP4_3733
7049 23:22:07.161438 ============ PULL DRAM RESETB DOWN ============
7050 23:22:07.168243 ========== PULL DRAM RESETB DOWN end =========
7051 23:22:07.171302 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7052 23:22:07.174603 ===================================
7053 23:22:07.178184 LPDDR4 DRAM CONFIGURATION
7054 23:22:07.181342 ===================================
7055 23:22:07.181454 EX_ROW_EN[0] = 0x0
7056 23:22:07.184395 EX_ROW_EN[1] = 0x0
7057 23:22:07.184507 LP4Y_EN = 0x0
7058 23:22:07.187759 WORK_FSP = 0x1
7059 23:22:07.187895 WL = 0x5
7060 23:22:07.191075 RL = 0x5
7061 23:22:07.194493 BL = 0x2
7062 23:22:07.194618 RPST = 0x0
7063 23:22:07.197644 RD_PRE = 0x0
7064 23:22:07.197768 WR_PRE = 0x1
7065 23:22:07.201244 WR_PST = 0x1
7066 23:22:07.201371 DBI_WR = 0x0
7067 23:22:07.204487 DBI_RD = 0x0
7068 23:22:07.204611 OTF = 0x1
7069 23:22:07.207812 ===================================
7070 23:22:07.211009 ===================================
7071 23:22:07.214236 ANA top config
7072 23:22:07.217592 ===================================
7073 23:22:07.217718 DLL_ASYNC_EN = 0
7074 23:22:07.220849 ALL_SLAVE_EN = 0
7075 23:22:07.224482 NEW_RANK_MODE = 1
7076 23:22:07.227677 DLL_IDLE_MODE = 1
7077 23:22:07.227807 LP45_APHY_COMB_EN = 1
7078 23:22:07.230875 TX_ODT_DIS = 0
7079 23:22:07.234396 NEW_8X_MODE = 1
7080 23:22:07.237488 ===================================
7081 23:22:07.240782 ===================================
7082 23:22:07.244427 data_rate = 3200
7083 23:22:07.247537 CKR = 1
7084 23:22:07.251151 DQ_P2S_RATIO = 8
7085 23:22:07.254138 ===================================
7086 23:22:07.254250 CA_P2S_RATIO = 8
7087 23:22:07.257473 DQ_CA_OPEN = 0
7088 23:22:07.260821 DQ_SEMI_OPEN = 0
7089 23:22:07.264057 CA_SEMI_OPEN = 0
7090 23:22:07.267137 CA_FULL_RATE = 0
7091 23:22:07.270865 DQ_CKDIV4_EN = 0
7092 23:22:07.270981 CA_CKDIV4_EN = 0
7093 23:22:07.274158 CA_PREDIV_EN = 0
7094 23:22:07.277321 PH8_DLY = 12
7095 23:22:07.280723 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7096 23:22:07.283911 DQ_AAMCK_DIV = 4
7097 23:22:07.287352 CA_AAMCK_DIV = 4
7098 23:22:07.287468 CA_ADMCK_DIV = 4
7099 23:22:07.290784 DQ_TRACK_CA_EN = 0
7100 23:22:07.293782 CA_PICK = 1600
7101 23:22:07.297176 CA_MCKIO = 1600
7102 23:22:07.300569 MCKIO_SEMI = 0
7103 23:22:07.303623 PLL_FREQ = 3068
7104 23:22:07.307131 DQ_UI_PI_RATIO = 32
7105 23:22:07.307239 CA_UI_PI_RATIO = 0
7106 23:22:07.310623 ===================================
7107 23:22:07.313955 ===================================
7108 23:22:07.317241 memory_type:LPDDR4
7109 23:22:07.320529 GP_NUM : 10
7110 23:22:07.320622 SRAM_EN : 1
7111 23:22:07.323691 MD32_EN : 0
7112 23:22:07.326928 ===================================
7113 23:22:07.330551 [ANA_INIT] >>>>>>>>>>>>>>
7114 23:22:07.333777 <<<<<< [CONFIGURE PHASE]: ANA_TX
7115 23:22:07.336940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7116 23:22:07.340374 ===================================
7117 23:22:07.340481 data_rate = 3200,PCW = 0X7600
7118 23:22:07.343584 ===================================
7119 23:22:07.347277 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7120 23:22:07.353824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 23:22:07.360096 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 23:22:07.363703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7123 23:22:07.366709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7124 23:22:07.370016 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7125 23:22:07.373559 [ANA_INIT] flow start
7126 23:22:07.376873 [ANA_INIT] PLL >>>>>>>>
7127 23:22:07.376987 [ANA_INIT] PLL <<<<<<<<
7128 23:22:07.380049 [ANA_INIT] MIDPI >>>>>>>>
7129 23:22:07.383312 [ANA_INIT] MIDPI <<<<<<<<
7130 23:22:07.383425 [ANA_INIT] DLL >>>>>>>>
7131 23:22:07.387032 [ANA_INIT] DLL <<<<<<<<
7132 23:22:07.390298 [ANA_INIT] flow end
7133 23:22:07.393456 ============ LP4 DIFF to SE enter ============
7134 23:22:07.396751 ============ LP4 DIFF to SE exit ============
7135 23:22:07.400275 [ANA_INIT] <<<<<<<<<<<<<
7136 23:22:07.403376 [Flow] Enable top DCM control >>>>>
7137 23:22:07.406699 [Flow] Enable top DCM control <<<<<
7138 23:22:07.410000 Enable DLL master slave shuffle
7139 23:22:07.413428 ==============================================================
7140 23:22:07.416868 Gating Mode config
7141 23:22:07.423413 ==============================================================
7142 23:22:07.423535 Config description:
7143 23:22:07.433085 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7144 23:22:07.439573 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7145 23:22:07.446194 SELPH_MODE 0: By rank 1: By Phase
7146 23:22:07.449377 ==============================================================
7147 23:22:07.452634 GAT_TRACK_EN = 1
7148 23:22:07.455845 RX_GATING_MODE = 2
7149 23:22:07.459520 RX_GATING_TRACK_MODE = 2
7150 23:22:07.462794 SELPH_MODE = 1
7151 23:22:07.465977 PICG_EARLY_EN = 1
7152 23:22:07.469292 VALID_LAT_VALUE = 1
7153 23:22:07.472787 ==============================================================
7154 23:22:07.475919 Enter into Gating configuration >>>>
7155 23:22:07.479205 Exit from Gating configuration <<<<
7156 23:22:07.482546 Enter into DVFS_PRE_config >>>>>
7157 23:22:07.496057 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7158 23:22:07.499556 Exit from DVFS_PRE_config <<<<<
7159 23:22:07.499651 Enter into PICG configuration >>>>
7160 23:22:07.502749 Exit from PICG configuration <<<<
7161 23:22:07.506003 [RX_INPUT] configuration >>>>>
7162 23:22:07.509301 [RX_INPUT] configuration <<<<<
7163 23:22:07.516043 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7164 23:22:07.519373 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7165 23:22:07.525802 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 23:22:07.532437 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 23:22:07.538874 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 23:22:07.545841 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 23:22:07.549038 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7170 23:22:07.552141 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7171 23:22:07.555486 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7172 23:22:07.562562 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7173 23:22:07.565769 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7174 23:22:07.569034 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 23:22:07.572182 ===================================
7176 23:22:07.575820 LPDDR4 DRAM CONFIGURATION
7177 23:22:07.579032 ===================================
7178 23:22:07.582596 EX_ROW_EN[0] = 0x0
7179 23:22:07.582711 EX_ROW_EN[1] = 0x0
7180 23:22:07.585797 LP4Y_EN = 0x0
7181 23:22:07.585912 WORK_FSP = 0x1
7182 23:22:07.588798 WL = 0x5
7183 23:22:07.588876 RL = 0x5
7184 23:22:07.592241 BL = 0x2
7185 23:22:07.592371 RPST = 0x0
7186 23:22:07.595871 RD_PRE = 0x0
7187 23:22:07.595981 WR_PRE = 0x1
7188 23:22:07.599043 WR_PST = 0x1
7189 23:22:07.599147 DBI_WR = 0x0
7190 23:22:07.602310 DBI_RD = 0x0
7191 23:22:07.602399 OTF = 0x1
7192 23:22:07.605813 ===================================
7193 23:22:07.609371 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7194 23:22:07.615772 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7195 23:22:07.618898 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 23:22:07.622419 ===================================
7197 23:22:07.625545 LPDDR4 DRAM CONFIGURATION
7198 23:22:07.629129 ===================================
7199 23:22:07.629207 EX_ROW_EN[0] = 0x10
7200 23:22:07.632476 EX_ROW_EN[1] = 0x0
7201 23:22:07.635400 LP4Y_EN = 0x0
7202 23:22:07.635512 WORK_FSP = 0x1
7203 23:22:07.638964 WL = 0x5
7204 23:22:07.639060 RL = 0x5
7205 23:22:07.642083 BL = 0x2
7206 23:22:07.642163 RPST = 0x0
7207 23:22:07.645623 RD_PRE = 0x0
7208 23:22:07.645730 WR_PRE = 0x1
7209 23:22:07.648845 WR_PST = 0x1
7210 23:22:07.648930 DBI_WR = 0x0
7211 23:22:07.652075 DBI_RD = 0x0
7212 23:22:07.652163 OTF = 0x1
7213 23:22:07.655698 ===================================
7214 23:22:07.662315 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7215 23:22:07.662437 ==
7216 23:22:07.665549 Dram Type= 6, Freq= 0, CH_0, rank 0
7217 23:22:07.668591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7218 23:22:07.668709 ==
7219 23:22:07.671981 [Duty_Offset_Calibration]
7220 23:22:07.675348 B0:2 B1:1 CA:1
7221 23:22:07.675437
7222 23:22:07.678540 [DutyScan_Calibration_Flow] k_type=0
7223 23:22:07.687253
7224 23:22:07.687340 ==CLK 0==
7225 23:22:07.690873 Final CLK duty delay cell = 0
7226 23:22:07.694231 [0] MAX Duty = 5156%(X100), DQS PI = 22
7227 23:22:07.697263 [0] MIN Duty = 4876%(X100), DQS PI = 48
7228 23:22:07.697369 [0] AVG Duty = 5016%(X100)
7229 23:22:07.700729
7230 23:22:07.704002 CH0 CLK Duty spec in!! Max-Min= 280%
7231 23:22:07.707259 [DutyScan_Calibration_Flow] ====Done====
7232 23:22:07.707343
7233 23:22:07.710608 [DutyScan_Calibration_Flow] k_type=1
7234 23:22:07.726373
7235 23:22:07.726465 ==DQS 0 ==
7236 23:22:07.729764 Final DQS duty delay cell = -4
7237 23:22:07.733262 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7238 23:22:07.736510 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7239 23:22:07.739914 [-4] AVG Duty = 4891%(X100)
7240 23:22:07.740025
7241 23:22:07.740123 ==DQS 1 ==
7242 23:22:07.743361 Final DQS duty delay cell = 0
7243 23:22:07.746588 [0] MAX Duty = 5187%(X100), DQS PI = 18
7244 23:22:07.749704 [0] MIN Duty = 5062%(X100), DQS PI = 30
7245 23:22:07.752842 [0] AVG Duty = 5124%(X100)
7246 23:22:07.752941
7247 23:22:07.756191 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7248 23:22:07.756332
7249 23:22:07.759820 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7250 23:22:07.763222 [DutyScan_Calibration_Flow] ====Done====
7251 23:22:07.763359
7252 23:22:07.766371 [DutyScan_Calibration_Flow] k_type=3
7253 23:22:07.783807
7254 23:22:07.783950 ==DQM 0 ==
7255 23:22:07.787424 Final DQM duty delay cell = 0
7256 23:22:07.790774 [0] MAX Duty = 5218%(X100), DQS PI = 34
7257 23:22:07.793816 [0] MIN Duty = 4907%(X100), DQS PI = 54
7258 23:22:07.793941 [0] AVG Duty = 5062%(X100)
7259 23:22:07.797339
7260 23:22:07.797419 ==DQM 1 ==
7261 23:22:07.800503 Final DQM duty delay cell = 0
7262 23:22:07.804104 [0] MAX Duty = 5187%(X100), DQS PI = 8
7263 23:22:07.807127 [0] MIN Duty = 5031%(X100), DQS PI = 50
7264 23:22:07.810659 [0] AVG Duty = 5109%(X100)
7265 23:22:07.810788
7266 23:22:07.814012 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7267 23:22:07.814141
7268 23:22:07.817310 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7269 23:22:07.820567 [DutyScan_Calibration_Flow] ====Done====
7270 23:22:07.820694
7271 23:22:07.823810 [DutyScan_Calibration_Flow] k_type=2
7272 23:22:07.840881
7273 23:22:07.841013 ==DQ 0 ==
7274 23:22:07.844459 Final DQ duty delay cell = 0
7275 23:22:07.847559 [0] MAX Duty = 5062%(X100), DQS PI = 26
7276 23:22:07.850821 [0] MIN Duty = 4907%(X100), DQS PI = 0
7277 23:22:07.850934 [0] AVG Duty = 4984%(X100)
7278 23:22:07.854502
7279 23:22:07.854609 ==DQ 1 ==
7280 23:22:07.857390 Final DQ duty delay cell = 0
7281 23:22:07.860820 [0] MAX Duty = 5125%(X100), DQS PI = 6
7282 23:22:07.864294 [0] MIN Duty = 4907%(X100), DQS PI = 34
7283 23:22:07.864430 [0] AVG Duty = 5016%(X100)
7284 23:22:07.864547
7285 23:22:07.867331 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7286 23:22:07.870658
7287 23:22:07.874306 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7288 23:22:07.877329 [DutyScan_Calibration_Flow] ====Done====
7289 23:22:07.877458 ==
7290 23:22:07.880949 Dram Type= 6, Freq= 0, CH_1, rank 0
7291 23:22:07.884245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 23:22:07.884377 ==
7293 23:22:07.887382 [Duty_Offset_Calibration]
7294 23:22:07.887507 B0:1 B1:0 CA:1
7295 23:22:07.887619
7296 23:22:07.890599 [DutyScan_Calibration_Flow] k_type=0
7297 23:22:07.900305
7298 23:22:07.900397 ==CLK 0==
7299 23:22:07.903852 Final CLK duty delay cell = -4
7300 23:22:07.906804 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7301 23:22:07.910122 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7302 23:22:07.913722 [-4] AVG Duty = 4922%(X100)
7303 23:22:07.913808
7304 23:22:07.916888 CH1 CLK Duty spec in!! Max-Min= 156%
7305 23:22:07.920354 [DutyScan_Calibration_Flow] ====Done====
7306 23:22:07.920436
7307 23:22:07.923493 [DutyScan_Calibration_Flow] k_type=1
7308 23:22:07.940383
7309 23:22:07.940486 ==DQS 0 ==
7310 23:22:07.943715 Final DQS duty delay cell = 0
7311 23:22:07.946838 [0] MAX Duty = 5125%(X100), DQS PI = 30
7312 23:22:07.949988 [0] MIN Duty = 4844%(X100), DQS PI = 48
7313 23:22:07.953635 [0] AVG Duty = 4984%(X100)
7314 23:22:07.953757
7315 23:22:07.953872 ==DQS 1 ==
7316 23:22:07.956859 Final DQS duty delay cell = 0
7317 23:22:07.960081 [0] MAX Duty = 5249%(X100), DQS PI = 16
7318 23:22:07.963624 [0] MIN Duty = 4969%(X100), DQS PI = 8
7319 23:22:07.966733 [0] AVG Duty = 5109%(X100)
7320 23:22:07.966849
7321 23:22:07.969900 CH1 DQS 0 Duty spec in!! Max-Min= 281%
7322 23:22:07.969986
7323 23:22:07.973341 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7324 23:22:07.976955 [DutyScan_Calibration_Flow] ====Done====
7325 23:22:07.977047
7326 23:22:07.980024 [DutyScan_Calibration_Flow] k_type=3
7327 23:22:07.997368
7328 23:22:07.997462 ==DQM 0 ==
7329 23:22:08.000547 Final DQM duty delay cell = 0
7330 23:22:08.003762 [0] MAX Duty = 5218%(X100), DQS PI = 16
7331 23:22:08.007074 [0] MIN Duty = 4969%(X100), DQS PI = 48
7332 23:22:08.010894 [0] AVG Duty = 5093%(X100)
7333 23:22:08.011012
7334 23:22:08.011112 ==DQM 1 ==
7335 23:22:08.013932 Final DQM duty delay cell = 0
7336 23:22:08.017201 [0] MAX Duty = 5093%(X100), DQS PI = 18
7337 23:22:08.020753 [0] MIN Duty = 4907%(X100), DQS PI = 34
7338 23:22:08.020866 [0] AVG Duty = 5000%(X100)
7339 23:22:08.023981
7340 23:22:08.027402 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7341 23:22:08.027509
7342 23:22:08.030711 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7343 23:22:08.034202 [DutyScan_Calibration_Flow] ====Done====
7344 23:22:08.034310
7345 23:22:08.037357 [DutyScan_Calibration_Flow] k_type=2
7346 23:22:08.053429
7347 23:22:08.053538 ==DQ 0 ==
7348 23:22:08.056647 Final DQ duty delay cell = -4
7349 23:22:08.060326 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7350 23:22:08.063566 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7351 23:22:08.066593 [-4] AVG Duty = 4953%(X100)
7352 23:22:08.066711
7353 23:22:08.066811 ==DQ 1 ==
7354 23:22:08.070140 Final DQ duty delay cell = 0
7355 23:22:08.073373 [0] MAX Duty = 5156%(X100), DQS PI = 18
7356 23:22:08.076317 [0] MIN Duty = 4938%(X100), DQS PI = 8
7357 23:22:08.079789 [0] AVG Duty = 5047%(X100)
7358 23:22:08.079912
7359 23:22:08.083349 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7360 23:22:08.083463
7361 23:22:08.086578 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7362 23:22:08.089778 [DutyScan_Calibration_Flow] ====Done====
7363 23:22:08.093312 nWR fixed to 30
7364 23:22:08.093425 [ModeRegInit_LP4] CH0 RK0
7365 23:22:08.096563 [ModeRegInit_LP4] CH0 RK1
7366 23:22:08.099741 [ModeRegInit_LP4] CH1 RK0
7367 23:22:08.103012 [ModeRegInit_LP4] CH1 RK1
7368 23:22:08.103128 match AC timing 5
7369 23:22:08.109464 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7370 23:22:08.113192 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7371 23:22:08.116424 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7372 23:22:08.122727 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7373 23:22:08.126456 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7374 23:22:08.126571 [MiockJmeterHQA]
7375 23:22:08.126666
7376 23:22:08.129635 [DramcMiockJmeter] u1RxGatingPI = 0
7377 23:22:08.133001 0 : 4255, 4029
7378 23:22:08.133107 4 : 4252, 4026
7379 23:22:08.136241 8 : 4252, 4027
7380 23:22:08.136340 12 : 4252, 4027
7381 23:22:08.136405 16 : 4252, 4027
7382 23:22:08.139662 20 : 4253, 4026
7383 23:22:08.139740 24 : 4255, 4029
7384 23:22:08.142808 28 : 4363, 4137
7385 23:22:08.142881 32 : 4252, 4027
7386 23:22:08.146230 36 : 4257, 4030
7387 23:22:08.146306 40 : 4252, 4027
7388 23:22:08.149381 44 : 4254, 4029
7389 23:22:08.149488 48 : 4252, 4027
7390 23:22:08.149594 52 : 4361, 4137
7391 23:22:08.153134 56 : 4363, 4138
7392 23:22:08.153211 60 : 4250, 4027
7393 23:22:08.156248 64 : 4250, 4026
7394 23:22:08.156343 68 : 4250, 4027
7395 23:22:08.159739 72 : 4250, 4026
7396 23:22:08.159814 76 : 4252, 4029
7397 23:22:08.159879 80 : 4360, 4137
7398 23:22:08.162995 84 : 4255, 4029
7399 23:22:08.163112 88 : 4250, 51
7400 23:22:08.166359 92 : 4250, 0
7401 23:22:08.166477 96 : 4363, 0
7402 23:22:08.166575 100 : 4252, 0
7403 23:22:08.169580 104 : 4254, 0
7404 23:22:08.169690 108 : 4250, 0
7405 23:22:08.173167 112 : 4250, 0
7406 23:22:08.173279 116 : 4252, 0
7407 23:22:08.173375 120 : 4255, 0
7408 23:22:08.176380 124 : 4361, 0
7409 23:22:08.176476 128 : 4360, 0
7410 23:22:08.179639 132 : 4363, 0
7411 23:22:08.179750 136 : 4250, 0
7412 23:22:08.179845 140 : 4250, 0
7413 23:22:08.183174 144 : 4249, 0
7414 23:22:08.183285 148 : 4250, 0
7415 23:22:08.183391 152 : 4250, 0
7416 23:22:08.186326 156 : 4250, 0
7417 23:22:08.186430 160 : 4252, 0
7418 23:22:08.189496 164 : 4252, 0
7419 23:22:08.189607 168 : 4360, 0
7420 23:22:08.189712 172 : 4250, 0
7421 23:22:08.193035 176 : 4363, 0
7422 23:22:08.193145 180 : 4250, 0
7423 23:22:08.196181 184 : 4361, 0
7424 23:22:08.196299 188 : 4250, 0
7425 23:22:08.196394 192 : 4361, 0
7426 23:22:08.199538 196 : 4250, 0
7427 23:22:08.199645 200 : 4250, 0
7428 23:22:08.202976 204 : 4250, 1479
7429 23:22:08.203089 208 : 4249, 3966
7430 23:22:08.206299 212 : 4252, 4029
7431 23:22:08.206405 216 : 4250, 4026
7432 23:22:08.206503 220 : 4252, 4029
7433 23:22:08.209550 224 : 4250, 4027
7434 23:22:08.209663 228 : 4250, 4026
7435 23:22:08.212819 232 : 4250, 4027
7436 23:22:08.212928 236 : 4360, 4137
7437 23:22:08.216085 240 : 4361, 4137
7438 23:22:08.216200 244 : 4248, 4024
7439 23:22:08.219656 248 : 4363, 4139
7440 23:22:08.219761 252 : 4249, 4027
7441 23:22:08.222842 256 : 4250, 4027
7442 23:22:08.222924 260 : 4250, 4027
7443 23:22:08.225960 264 : 4252, 4030
7444 23:22:08.226069 268 : 4250, 4027
7445 23:22:08.229640 272 : 4250, 4026
7446 23:22:08.229754 276 : 4250, 4027
7447 23:22:08.229849 280 : 4252, 4030
7448 23:22:08.232873 284 : 4250, 4027
7449 23:22:08.232990 288 : 4360, 4137
7450 23:22:08.236191 292 : 4361, 4137
7451 23:22:08.236303 296 : 4250, 4027
7452 23:22:08.239372 300 : 4360, 4138
7453 23:22:08.239487 304 : 4360, 4138
7454 23:22:08.242359 308 : 4250, 3932
7455 23:22:08.242492 312 : 4250, 1900
7456 23:22:08.242609
7457 23:22:08.245842 MIOCK jitter meter ch=0
7458 23:22:08.245970
7459 23:22:08.249339 1T = (312-88) = 224 dly cells
7460 23:22:08.255774 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7461 23:22:08.255902 ==
7462 23:22:08.259413 Dram Type= 6, Freq= 0, CH_0, rank 0
7463 23:22:08.262438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7464 23:22:08.262549 ==
7465 23:22:08.269304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7466 23:22:08.272511 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7467 23:22:08.275790 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7468 23:22:08.282304 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7469 23:22:08.290874 [CA 0] Center 42 (12~73) winsize 62
7470 23:22:08.294459 [CA 1] Center 42 (12~73) winsize 62
7471 23:22:08.297656 [CA 2] Center 38 (8~68) winsize 61
7472 23:22:08.300812 [CA 3] Center 37 (8~67) winsize 60
7473 23:22:08.304207 [CA 4] Center 36 (6~66) winsize 61
7474 23:22:08.307865 [CA 5] Center 35 (6~64) winsize 59
7475 23:22:08.307947
7476 23:22:08.310975 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7477 23:22:08.311054
7478 23:22:08.314164 [CATrainingPosCal] consider 1 rank data
7479 23:22:08.317908 u2DelayCellTimex100 = 290/100 ps
7480 23:22:08.321180 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7481 23:22:08.327564 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7482 23:22:08.330721 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7483 23:22:08.333941 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7484 23:22:08.337280 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7485 23:22:08.340449 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7486 23:22:08.340556
7487 23:22:08.344027 CA PerBit enable=1, Macro0, CA PI delay=35
7488 23:22:08.344136
7489 23:22:08.347155 [CBTSetCACLKResult] CA Dly = 35
7490 23:22:08.350854 CS Dly: 9 (0~40)
7491 23:22:08.353883 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7492 23:22:08.357351 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7493 23:22:08.357464 ==
7494 23:22:08.360669 Dram Type= 6, Freq= 0, CH_0, rank 1
7495 23:22:08.364077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7496 23:22:08.364203 ==
7497 23:22:08.370399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7498 23:22:08.373735 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7499 23:22:08.380397 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7500 23:22:08.383904 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7501 23:22:08.394184 [CA 0] Center 42 (12~73) winsize 62
7502 23:22:08.397468 [CA 1] Center 42 (12~73) winsize 62
7503 23:22:08.400874 [CA 2] Center 38 (8~68) winsize 61
7504 23:22:08.403976 [CA 3] Center 37 (7~67) winsize 61
7505 23:22:08.407509 [CA 4] Center 36 (6~66) winsize 61
7506 23:22:08.410967 [CA 5] Center 35 (5~65) winsize 61
7507 23:22:08.411080
7508 23:22:08.414200 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7509 23:22:08.414320
7510 23:22:08.417400 [CATrainingPosCal] consider 2 rank data
7511 23:22:08.420893 u2DelayCellTimex100 = 290/100 ps
7512 23:22:08.424022 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7513 23:22:08.430960 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7514 23:22:08.434195 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7515 23:22:08.437490 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7516 23:22:08.440663 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7517 23:22:08.444335 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7518 23:22:08.444442
7519 23:22:08.447575 CA PerBit enable=1, Macro0, CA PI delay=35
7520 23:22:08.447682
7521 23:22:08.450601 [CBTSetCACLKResult] CA Dly = 35
7522 23:22:08.453959 CS Dly: 10 (0~42)
7523 23:22:08.457139 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7524 23:22:08.460818 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7525 23:22:08.460931
7526 23:22:08.463985 ----->DramcWriteLeveling(PI) begin...
7527 23:22:08.464108 ==
7528 23:22:08.467418 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 23:22:08.470765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 23:22:08.473928 ==
7531 23:22:08.474038 Write leveling (Byte 0): 37 => 37
7532 23:22:08.477290 Write leveling (Byte 1): 28 => 28
7533 23:22:08.480491 DramcWriteLeveling(PI) end<-----
7534 23:22:08.480604
7535 23:22:08.480709 ==
7536 23:22:08.483776 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 23:22:08.490728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 23:22:08.490888 ==
7539 23:22:08.491005 [Gating] SW mode calibration
7540 23:22:08.500466 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7541 23:22:08.503998 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7542 23:22:08.510499 1 4 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7543 23:22:08.514130 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7544 23:22:08.517405 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7545 23:22:08.520633 1 4 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
7546 23:22:08.527422 1 4 16 | B1->B0 | 2323 3938 | 1 1 | (0 0) (1 1)
7547 23:22:08.530484 1 4 20 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)
7548 23:22:08.533960 1 4 24 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7549 23:22:08.540500 1 4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7550 23:22:08.543861 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7551 23:22:08.547485 1 5 4 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7552 23:22:08.554160 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7553 23:22:08.557316 1 5 12 | B1->B0 | 3434 2b2a | 1 1 | (1 1) (1 0)
7554 23:22:08.560484 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
7555 23:22:08.567365 1 5 20 | B1->B0 | 2525 2727 | 1 0 | (1 0) (0 0)
7556 23:22:08.570476 1 5 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7557 23:22:08.573879 1 5 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
7558 23:22:08.580650 1 6 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7559 23:22:08.584031 1 6 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 1)
7560 23:22:08.587265 1 6 8 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
7561 23:22:08.593694 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7562 23:22:08.597466 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7563 23:22:08.600572 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7564 23:22:08.607167 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 23:22:08.610565 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 23:22:08.613625 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 23:22:08.620647 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 23:22:08.623831 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 23:22:08.627016 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7570 23:22:08.630469 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 23:22:08.636908 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7572 23:22:08.640307 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 23:22:08.643542 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 23:22:08.650129 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 23:22:08.653420 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 23:22:08.657003 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 23:22:08.663365 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 23:22:08.666874 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 23:22:08.670013 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 23:22:08.676822 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 23:22:08.679925 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 23:22:08.683421 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 23:22:08.690304 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 23:22:08.693426 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 23:22:08.696619 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7586 23:22:08.703570 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7587 23:22:08.703710 Total UI for P1: 0, mck2ui 16
7588 23:22:08.710090 best dqsien dly found for B0: ( 1, 9, 12)
7589 23:22:08.713370 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7590 23:22:08.716834 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 23:22:08.719966 Total UI for P1: 0, mck2ui 16
7592 23:22:08.723333 best dqsien dly found for B1: ( 1, 9, 18)
7593 23:22:08.726434 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7594 23:22:08.729794 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7595 23:22:08.729883
7596 23:22:08.736453 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7597 23:22:08.740110 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7598 23:22:08.743368 [Gating] SW calibration Done
7599 23:22:08.743478 ==
7600 23:22:08.746546 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 23:22:08.750024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 23:22:08.750127 ==
7603 23:22:08.750219 RX Vref Scan: 0
7604 23:22:08.750308
7605 23:22:08.752976 RX Vref 0 -> 0, step: 1
7606 23:22:08.753066
7607 23:22:08.756682 RX Delay 0 -> 252, step: 8
7608 23:22:08.759845 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7609 23:22:08.763338 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7610 23:22:08.766471 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7611 23:22:08.773332 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7612 23:22:08.776404 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7613 23:22:08.779802 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7614 23:22:08.783189 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7615 23:22:08.786369 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7616 23:22:08.793315 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7617 23:22:08.796399 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7618 23:22:08.799873 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7619 23:22:08.803074 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7620 23:22:08.806353 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7621 23:22:08.813131 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7622 23:22:08.816348 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7623 23:22:08.819664 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7624 23:22:08.819779 ==
7625 23:22:08.822952 Dram Type= 6, Freq= 0, CH_0, rank 0
7626 23:22:08.826400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 23:22:08.826483 ==
7628 23:22:08.829664 DQS Delay:
7629 23:22:08.829740 DQS0 = 0, DQS1 = 0
7630 23:22:08.833148 DQM Delay:
7631 23:22:08.833237 DQM0 = 136, DQM1 = 129
7632 23:22:08.833334 DQ Delay:
7633 23:22:08.836330 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7634 23:22:08.842938 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7635 23:22:08.846232 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7636 23:22:08.849804 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7637 23:22:08.849888
7638 23:22:08.849956
7639 23:22:08.850023 ==
7640 23:22:08.853015 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 23:22:08.856335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 23:22:08.856451 ==
7643 23:22:08.856545
7644 23:22:08.856626
7645 23:22:08.859437 TX Vref Scan disable
7646 23:22:08.862857 == TX Byte 0 ==
7647 23:22:08.866435 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7648 23:22:08.869612 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7649 23:22:08.872900 == TX Byte 1 ==
7650 23:22:08.876083 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7651 23:22:08.879678 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7652 23:22:08.879793 ==
7653 23:22:08.882751 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 23:22:08.886336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 23:22:08.889469 ==
7656 23:22:08.901305
7657 23:22:08.904762 TX Vref early break, caculate TX vref
7658 23:22:08.908197 TX Vref=16, minBit 0, minWin=23, winSum=376
7659 23:22:08.911291 TX Vref=18, minBit 7, minWin=22, winSum=385
7660 23:22:08.914819 TX Vref=20, minBit 3, minWin=24, winSum=400
7661 23:22:08.917939 TX Vref=22, minBit 3, minWin=24, winSum=406
7662 23:22:08.921270 TX Vref=24, minBit 0, minWin=25, winSum=412
7663 23:22:08.928108 TX Vref=26, minBit 0, minWin=26, winSum=423
7664 23:22:08.931364 TX Vref=28, minBit 2, minWin=25, winSum=424
7665 23:22:08.934599 TX Vref=30, minBit 2, minWin=24, winSum=413
7666 23:22:08.938258 TX Vref=32, minBit 1, minWin=24, winSum=404
7667 23:22:08.941381 TX Vref=34, minBit 6, minWin=23, winSum=399
7668 23:22:08.947964 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 26
7669 23:22:08.948077
7670 23:22:08.951289 Final TX Range 0 Vref 26
7671 23:22:08.951396
7672 23:22:08.951488 ==
7673 23:22:08.954562 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 23:22:08.958260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 23:22:08.958373 ==
7676 23:22:08.958479
7677 23:22:08.958569
7678 23:22:08.961429 TX Vref Scan disable
7679 23:22:08.968042 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7680 23:22:08.968164 == TX Byte 0 ==
7681 23:22:08.971471 u2DelayCellOfst[0]=10 cells (3 PI)
7682 23:22:08.974486 u2DelayCellOfst[1]=13 cells (4 PI)
7683 23:22:08.978082 u2DelayCellOfst[2]=10 cells (3 PI)
7684 23:22:08.981272 u2DelayCellOfst[3]=6 cells (2 PI)
7685 23:22:08.984525 u2DelayCellOfst[4]=6 cells (2 PI)
7686 23:22:08.987797 u2DelayCellOfst[5]=0 cells (0 PI)
7687 23:22:08.991471 u2DelayCellOfst[6]=16 cells (5 PI)
7688 23:22:08.991580 u2DelayCellOfst[7]=13 cells (4 PI)
7689 23:22:08.998550 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7690 23:22:09.001187 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7691 23:22:09.001298 == TX Byte 1 ==
7692 23:22:09.004626 u2DelayCellOfst[8]=3 cells (1 PI)
7693 23:22:09.007949 u2DelayCellOfst[9]=0 cells (0 PI)
7694 23:22:09.011181 u2DelayCellOfst[10]=6 cells (2 PI)
7695 23:22:09.014535 u2DelayCellOfst[11]=6 cells (2 PI)
7696 23:22:09.017628 u2DelayCellOfst[12]=10 cells (3 PI)
7697 23:22:09.020882 u2DelayCellOfst[13]=10 cells (3 PI)
7698 23:22:09.024541 u2DelayCellOfst[14]=16 cells (5 PI)
7699 23:22:09.027690 u2DelayCellOfst[15]=10 cells (3 PI)
7700 23:22:09.030892 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7701 23:22:09.037768 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7702 23:22:09.037881 DramC Write-DBI on
7703 23:22:09.037953 ==
7704 23:22:09.040942 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 23:22:09.044459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 23:22:09.047501 ==
7707 23:22:09.047589
7708 23:22:09.047669
7709 23:22:09.047731 TX Vref Scan disable
7710 23:22:09.050850 == TX Byte 0 ==
7711 23:22:09.054227 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7712 23:22:09.057780 == TX Byte 1 ==
7713 23:22:09.060953 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7714 23:22:09.064244 DramC Write-DBI off
7715 23:22:09.064354
7716 23:22:09.064442 [DATLAT]
7717 23:22:09.064544 Freq=1600, CH0 RK0
7718 23:22:09.064636
7719 23:22:09.067458 DATLAT Default: 0xf
7720 23:22:09.067533 0, 0xFFFF, sum = 0
7721 23:22:09.070738 1, 0xFFFF, sum = 0
7722 23:22:09.074289 2, 0xFFFF, sum = 0
7723 23:22:09.074410 3, 0xFFFF, sum = 0
7724 23:22:09.077653 4, 0xFFFF, sum = 0
7725 23:22:09.077737 5, 0xFFFF, sum = 0
7726 23:22:09.080807 6, 0xFFFF, sum = 0
7727 23:22:09.080900 7, 0xFFFF, sum = 0
7728 23:22:09.084074 8, 0xFFFF, sum = 0
7729 23:22:09.084218 9, 0xFFFF, sum = 0
7730 23:22:09.087618 10, 0xFFFF, sum = 0
7731 23:22:09.087723 11, 0xFFFF, sum = 0
7732 23:22:09.090921 12, 0xFFFF, sum = 0
7733 23:22:09.091025 13, 0xFFFF, sum = 0
7734 23:22:09.094102 14, 0x0, sum = 1
7735 23:22:09.094181 15, 0x0, sum = 2
7736 23:22:09.097334 16, 0x0, sum = 3
7737 23:22:09.097416 17, 0x0, sum = 4
7738 23:22:09.100808 best_step = 15
7739 23:22:09.100884
7740 23:22:09.100958 ==
7741 23:22:09.103983 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 23:22:09.107228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 23:22:09.107304 ==
7744 23:22:09.110869 RX Vref Scan: 1
7745 23:22:09.110984
7746 23:22:09.111088 Set Vref Range= 24 -> 127
7747 23:22:09.111204
7748 23:22:09.114167 RX Vref 24 -> 127, step: 1
7749 23:22:09.114295
7750 23:22:09.117387 RX Delay 19 -> 252, step: 4
7751 23:22:09.117490
7752 23:22:09.120471 Set Vref, RX VrefLevel [Byte0]: 24
7753 23:22:09.124045 [Byte1]: 24
7754 23:22:09.124154
7755 23:22:09.127020 Set Vref, RX VrefLevel [Byte0]: 25
7756 23:22:09.130913 [Byte1]: 25
7757 23:22:09.131028
7758 23:22:09.133802 Set Vref, RX VrefLevel [Byte0]: 26
7759 23:22:09.137138 [Byte1]: 26
7760 23:22:09.141211
7761 23:22:09.141321 Set Vref, RX VrefLevel [Byte0]: 27
7762 23:22:09.144428 [Byte1]: 27
7763 23:22:09.148899
7764 23:22:09.148997 Set Vref, RX VrefLevel [Byte0]: 28
7765 23:22:09.152051 [Byte1]: 28
7766 23:22:09.156408
7767 23:22:09.156486 Set Vref, RX VrefLevel [Byte0]: 29
7768 23:22:09.159646 [Byte1]: 29
7769 23:22:09.163748
7770 23:22:09.163856 Set Vref, RX VrefLevel [Byte0]: 30
7771 23:22:09.167052 [Byte1]: 30
7772 23:22:09.171643
7773 23:22:09.171754 Set Vref, RX VrefLevel [Byte0]: 31
7774 23:22:09.174839 [Byte1]: 31
7775 23:22:09.178920
7776 23:22:09.179041 Set Vref, RX VrefLevel [Byte0]: 32
7777 23:22:09.182467 [Byte1]: 32
7778 23:22:09.186488
7779 23:22:09.186583 Set Vref, RX VrefLevel [Byte0]: 33
7780 23:22:09.189836 [Byte1]: 33
7781 23:22:09.194237
7782 23:22:09.194347 Set Vref, RX VrefLevel [Byte0]: 34
7783 23:22:09.197362 [Byte1]: 34
7784 23:22:09.201848
7785 23:22:09.201959 Set Vref, RX VrefLevel [Byte0]: 35
7786 23:22:09.204867 [Byte1]: 35
7787 23:22:09.209598
7788 23:22:09.209689 Set Vref, RX VrefLevel [Byte0]: 36
7789 23:22:09.212756 [Byte1]: 36
7790 23:22:09.216885
7791 23:22:09.217006 Set Vref, RX VrefLevel [Byte0]: 37
7792 23:22:09.220096 [Byte1]: 37
7793 23:22:09.224629
7794 23:22:09.224759 Set Vref, RX VrefLevel [Byte0]: 38
7795 23:22:09.227790 [Byte1]: 38
7796 23:22:09.232164
7797 23:22:09.232308 Set Vref, RX VrefLevel [Byte0]: 39
7798 23:22:09.235416 [Byte1]: 39
7799 23:22:09.239867
7800 23:22:09.239994 Set Vref, RX VrefLevel [Byte0]: 40
7801 23:22:09.242974 [Byte1]: 40
7802 23:22:09.247108
7803 23:22:09.247226 Set Vref, RX VrefLevel [Byte0]: 41
7804 23:22:09.250429 [Byte1]: 41
7805 23:22:09.254540
7806 23:22:09.254660 Set Vref, RX VrefLevel [Byte0]: 42
7807 23:22:09.258121 [Byte1]: 42
7808 23:22:09.262377
7809 23:22:09.262495 Set Vref, RX VrefLevel [Byte0]: 43
7810 23:22:09.265461 [Byte1]: 43
7811 23:22:09.270213
7812 23:22:09.270334 Set Vref, RX VrefLevel [Byte0]: 44
7813 23:22:09.273381 [Byte1]: 44
7814 23:22:09.277716
7815 23:22:09.277807 Set Vref, RX VrefLevel [Byte0]: 45
7816 23:22:09.280882 [Byte1]: 45
7817 23:22:09.285013
7818 23:22:09.285108 Set Vref, RX VrefLevel [Byte0]: 46
7819 23:22:09.288499 [Byte1]: 46
7820 23:22:09.292732
7821 23:22:09.292832 Set Vref, RX VrefLevel [Byte0]: 47
7822 23:22:09.295991 [Byte1]: 47
7823 23:22:09.300039
7824 23:22:09.300169 Set Vref, RX VrefLevel [Byte0]: 48
7825 23:22:09.303541 [Byte1]: 48
7826 23:22:09.307862
7827 23:22:09.307961 Set Vref, RX VrefLevel [Byte0]: 49
7828 23:22:09.310960 [Byte1]: 49
7829 23:22:09.315586
7830 23:22:09.315671 Set Vref, RX VrefLevel [Byte0]: 50
7831 23:22:09.318828 [Byte1]: 50
7832 23:22:09.322936
7833 23:22:09.323017 Set Vref, RX VrefLevel [Byte0]: 51
7834 23:22:09.326245 [Byte1]: 51
7835 23:22:09.330340
7836 23:22:09.330443 Set Vref, RX VrefLevel [Byte0]: 52
7837 23:22:09.333617 [Byte1]: 52
7838 23:22:09.338085
7839 23:22:09.338178 Set Vref, RX VrefLevel [Byte0]: 53
7840 23:22:09.341363 [Byte1]: 53
7841 23:22:09.345721
7842 23:22:09.345840 Set Vref, RX VrefLevel [Byte0]: 54
7843 23:22:09.348837 [Byte1]: 54
7844 23:22:09.353114
7845 23:22:09.353214 Set Vref, RX VrefLevel [Byte0]: 55
7846 23:22:09.356737 [Byte1]: 55
7847 23:22:09.360991
7848 23:22:09.361124 Set Vref, RX VrefLevel [Byte0]: 56
7849 23:22:09.364454 [Byte1]: 56
7850 23:22:09.368506
7851 23:22:09.368623 Set Vref, RX VrefLevel [Byte0]: 57
7852 23:22:09.371750 [Byte1]: 57
7853 23:22:09.376260
7854 23:22:09.376388 Set Vref, RX VrefLevel [Byte0]: 58
7855 23:22:09.379228 [Byte1]: 58
7856 23:22:09.383392
7857 23:22:09.383505 Set Vref, RX VrefLevel [Byte0]: 59
7858 23:22:09.386751 [Byte1]: 59
7859 23:22:09.391152
7860 23:22:09.391275 Set Vref, RX VrefLevel [Byte0]: 60
7861 23:22:09.394317 [Byte1]: 60
7862 23:22:09.398725
7863 23:22:09.398849 Set Vref, RX VrefLevel [Byte0]: 61
7864 23:22:09.401852 [Byte1]: 61
7865 23:22:09.406408
7866 23:22:09.406496 Set Vref, RX VrefLevel [Byte0]: 62
7867 23:22:09.409489 [Byte1]: 62
7868 23:22:09.413793
7869 23:22:09.413879 Set Vref, RX VrefLevel [Byte0]: 63
7870 23:22:09.417203 [Byte1]: 63
7871 23:22:09.421634
7872 23:22:09.421759 Set Vref, RX VrefLevel [Byte0]: 64
7873 23:22:09.424791 [Byte1]: 64
7874 23:22:09.428962
7875 23:22:09.429043 Set Vref, RX VrefLevel [Byte0]: 65
7876 23:22:09.432250 [Byte1]: 65
7877 23:22:09.436419
7878 23:22:09.436503 Set Vref, RX VrefLevel [Byte0]: 66
7879 23:22:09.439700 [Byte1]: 66
7880 23:22:09.444345
7881 23:22:09.444439 Set Vref, RX VrefLevel [Byte0]: 67
7882 23:22:09.447292 [Byte1]: 67
7883 23:22:09.451528
7884 23:22:09.451650 Set Vref, RX VrefLevel [Byte0]: 68
7885 23:22:09.454896 [Byte1]: 68
7886 23:22:09.459125
7887 23:22:09.459233 Set Vref, RX VrefLevel [Byte0]: 69
7888 23:22:09.462366 [Byte1]: 69
7889 23:22:09.466963
7890 23:22:09.467073 Set Vref, RX VrefLevel [Byte0]: 70
7891 23:22:09.470145 [Byte1]: 70
7892 23:22:09.474345
7893 23:22:09.474453 Set Vref, RX VrefLevel [Byte0]: 71
7894 23:22:09.477576 [Byte1]: 71
7895 23:22:09.481821
7896 23:22:09.481918 Set Vref, RX VrefLevel [Byte0]: 72
7897 23:22:09.485437 [Byte1]: 72
7898 23:22:09.489624
7899 23:22:09.489758 Set Vref, RX VrefLevel [Byte0]: 73
7900 23:22:09.493098 [Byte1]: 73
7901 23:22:09.497193
7902 23:22:09.497307 Set Vref, RX VrefLevel [Byte0]: 74
7903 23:22:09.500475 [Byte1]: 74
7904 23:22:09.504852
7905 23:22:09.504988 Final RX Vref Byte 0 = 61 to rank0
7906 23:22:09.507840 Final RX Vref Byte 1 = 60 to rank0
7907 23:22:09.511209 Final RX Vref Byte 0 = 61 to rank1
7908 23:22:09.514647 Final RX Vref Byte 1 = 60 to rank1==
7909 23:22:09.518105 Dram Type= 6, Freq= 0, CH_0, rank 0
7910 23:22:09.524741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7911 23:22:09.524861 ==
7912 23:22:09.524938 DQS Delay:
7913 23:22:09.525002 DQS0 = 0, DQS1 = 0
7914 23:22:09.528298 DQM Delay:
7915 23:22:09.528386 DQM0 = 134, DQM1 = 127
7916 23:22:09.531253 DQ Delay:
7917 23:22:09.534512 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7918 23:22:09.538122 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7919 23:22:09.541354 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7920 23:22:09.544612 DQ12 =130, DQ13 =134, DQ14 =138, DQ15 =134
7921 23:22:09.544722
7922 23:22:09.544818
7923 23:22:09.544910
7924 23:22:09.548240 [DramC_TX_OE_Calibration] TA2
7925 23:22:09.551480 Original DQ_B0 (3 6) =30, OEN = 27
7926 23:22:09.554607 Original DQ_B1 (3 6) =30, OEN = 27
7927 23:22:09.558225 24, 0x0, End_B0=24 End_B1=24
7928 23:22:09.558349 25, 0x0, End_B0=25 End_B1=25
7929 23:22:09.561451 26, 0x0, End_B0=26 End_B1=26
7930 23:22:09.564606 27, 0x0, End_B0=27 End_B1=27
7931 23:22:09.567842 28, 0x0, End_B0=28 End_B1=28
7932 23:22:09.567952 29, 0x0, End_B0=29 End_B1=29
7933 23:22:09.571222 30, 0x0, End_B0=30 End_B1=30
7934 23:22:09.574519 31, 0x4141, End_B0=30 End_B1=30
7935 23:22:09.577742 Byte0 end_step=30 best_step=27
7936 23:22:09.581497 Byte1 end_step=30 best_step=27
7937 23:22:09.584784 Byte0 TX OE(2T, 0.5T) = (3, 3)
7938 23:22:09.584894 Byte1 TX OE(2T, 0.5T) = (3, 3)
7939 23:22:09.587967
7940 23:22:09.588100
7941 23:22:09.594792 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7942 23:22:09.597908 CH0 RK0: MR19=303, MR18=2622
7943 23:22:09.604610 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
7944 23:22:09.604746
7945 23:22:09.607968 ----->DramcWriteLeveling(PI) begin...
7946 23:22:09.608056 ==
7947 23:22:09.611523 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 23:22:09.614720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 23:22:09.614813 ==
7950 23:22:09.618123 Write leveling (Byte 0): 37 => 37
7951 23:22:09.621251 Write leveling (Byte 1): 28 => 28
7952 23:22:09.624686 DramcWriteLeveling(PI) end<-----
7953 23:22:09.624774
7954 23:22:09.624839 ==
7955 23:22:09.627864 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 23:22:09.631097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 23:22:09.631187 ==
7958 23:22:09.634546 [Gating] SW mode calibration
7959 23:22:09.641291 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7960 23:22:09.647730 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7961 23:22:09.650968 1 4 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7962 23:22:09.654282 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7963 23:22:09.660769 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7964 23:22:09.664081 1 4 12 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
7965 23:22:09.667602 1 4 16 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
7966 23:22:09.674474 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7967 23:22:09.677760 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7968 23:22:09.680959 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7969 23:22:09.687740 1 5 0 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7970 23:22:09.690977 1 5 4 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7971 23:22:09.694317 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7972 23:22:09.700650 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
7973 23:22:09.704336 1 5 16 | B1->B0 | 2e2e 2929 | 0 0 | (0 1) (0 0)
7974 23:22:09.707427 1 5 20 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
7975 23:22:09.713927 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
7976 23:22:09.717548 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7977 23:22:09.720870 1 6 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
7978 23:22:09.727248 1 6 4 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7979 23:22:09.730847 1 6 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7980 23:22:09.734321 1 6 12 | B1->B0 | 2323 3534 | 0 1 | (0 0) (1 1)
7981 23:22:09.737680 1 6 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7982 23:22:09.744267 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7983 23:22:09.747573 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 23:22:09.751004 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 23:22:09.757427 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 23:22:09.760754 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 23:22:09.764492 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 23:22:09.770908 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7989 23:22:09.774166 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7990 23:22:09.777533 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 23:22:09.784091 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 23:22:09.787359 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 23:22:09.790689 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 23:22:09.797626 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 23:22:09.800884 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 23:22:09.803975 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 23:22:09.810772 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 23:22:09.813881 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 23:22:09.817219 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 23:22:09.823942 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 23:22:09.826949 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 23:22:09.830328 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 23:22:09.836947 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 23:22:09.840409 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8005 23:22:09.843579 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8006 23:22:09.850230 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 23:22:09.850316 Total UI for P1: 0, mck2ui 16
8008 23:22:09.857057 best dqsien dly found for B0: ( 1, 9, 14)
8009 23:22:09.857139 Total UI for P1: 0, mck2ui 16
8010 23:22:09.860357 best dqsien dly found for B1: ( 1, 9, 14)
8011 23:22:09.866829 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8012 23:22:09.870433 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8013 23:22:09.870520
8014 23:22:09.873672 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8015 23:22:09.876877 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8016 23:22:09.880119 [Gating] SW calibration Done
8017 23:22:09.880202 ==
8018 23:22:09.883590 Dram Type= 6, Freq= 0, CH_0, rank 1
8019 23:22:09.886848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 23:22:09.886927 ==
8021 23:22:09.890152 RX Vref Scan: 0
8022 23:22:09.890238
8023 23:22:09.890305 RX Vref 0 -> 0, step: 1
8024 23:22:09.890366
8025 23:22:09.893416 RX Delay 0 -> 252, step: 8
8026 23:22:09.896579 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8027 23:22:09.903518 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8028 23:22:09.906769 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8029 23:22:09.910132 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8030 23:22:09.913276 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8031 23:22:09.916762 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8032 23:22:09.923107 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8033 23:22:09.926560 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8034 23:22:09.930245 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8035 23:22:09.933400 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8036 23:22:09.936722 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8037 23:22:09.943291 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8038 23:22:09.946812 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8039 23:22:09.950138 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8040 23:22:09.953222 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8041 23:22:09.956330 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8042 23:22:09.959707 ==
8043 23:22:09.959814 Dram Type= 6, Freq= 0, CH_0, rank 1
8044 23:22:09.966641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8045 23:22:09.966729 ==
8046 23:22:09.966796 DQS Delay:
8047 23:22:09.969682 DQS0 = 0, DQS1 = 0
8048 23:22:09.969766 DQM Delay:
8049 23:22:09.973065 DQM0 = 137, DQM1 = 128
8050 23:22:09.973149 DQ Delay:
8051 23:22:09.976333 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8052 23:22:09.979805 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8053 23:22:09.983101 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8054 23:22:09.986354 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8055 23:22:09.986439
8056 23:22:09.986504
8057 23:22:09.986566 ==
8058 23:22:09.989681 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 23:22:09.996447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 23:22:09.996564 ==
8061 23:22:09.996659
8062 23:22:09.996756
8063 23:22:09.996846 TX Vref Scan disable
8064 23:22:09.999883 == TX Byte 0 ==
8065 23:22:10.002990 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8066 23:22:10.010049 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8067 23:22:10.010154 == TX Byte 1 ==
8068 23:22:10.012885 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8069 23:22:10.019715 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8070 23:22:10.019801 ==
8071 23:22:10.022839 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 23:22:10.026346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 23:22:10.026433 ==
8074 23:22:10.039946
8075 23:22:10.043041 TX Vref early break, caculate TX vref
8076 23:22:10.046416 TX Vref=16, minBit 1, minWin=23, winSum=381
8077 23:22:10.049717 TX Vref=18, minBit 1, minWin=23, winSum=396
8078 23:22:10.052866 TX Vref=20, minBit 3, minWin=24, winSum=404
8079 23:22:10.056145 TX Vref=22, minBit 0, minWin=24, winSum=407
8080 23:22:10.059468 TX Vref=24, minBit 1, minWin=25, winSum=419
8081 23:22:10.066022 TX Vref=26, minBit 1, minWin=25, winSum=426
8082 23:22:10.069651 TX Vref=28, minBit 3, minWin=25, winSum=424
8083 23:22:10.072735 TX Vref=30, minBit 3, minWin=25, winSum=417
8084 23:22:10.075950 TX Vref=32, minBit 2, minWin=25, winSum=410
8085 23:22:10.079123 TX Vref=34, minBit 4, minWin=23, winSum=400
8086 23:22:10.085751 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 26
8087 23:22:10.085855
8088 23:22:10.089042 Final TX Range 0 Vref 26
8089 23:22:10.089134
8090 23:22:10.089200 ==
8091 23:22:10.092568 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 23:22:10.095801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 23:22:10.095892 ==
8094 23:22:10.095961
8095 23:22:10.096026
8096 23:22:10.099267 TX Vref Scan disable
8097 23:22:10.105649 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8098 23:22:10.105745 == TX Byte 0 ==
8099 23:22:10.108996 u2DelayCellOfst[0]=10 cells (3 PI)
8100 23:22:10.112534 u2DelayCellOfst[1]=13 cells (4 PI)
8101 23:22:10.115714 u2DelayCellOfst[2]=6 cells (2 PI)
8102 23:22:10.119040 u2DelayCellOfst[3]=6 cells (2 PI)
8103 23:22:10.122339 u2DelayCellOfst[4]=6 cells (2 PI)
8104 23:22:10.125503 u2DelayCellOfst[5]=0 cells (0 PI)
8105 23:22:10.129017 u2DelayCellOfst[6]=13 cells (4 PI)
8106 23:22:10.132081 u2DelayCellOfst[7]=13 cells (4 PI)
8107 23:22:10.135633 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8108 23:22:10.138852 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8109 23:22:10.142193 == TX Byte 1 ==
8110 23:22:10.145486 u2DelayCellOfst[8]=3 cells (1 PI)
8111 23:22:10.145570 u2DelayCellOfst[9]=0 cells (0 PI)
8112 23:22:10.148707 u2DelayCellOfst[10]=6 cells (2 PI)
8113 23:22:10.152388 u2DelayCellOfst[11]=3 cells (1 PI)
8114 23:22:10.155536 u2DelayCellOfst[12]=10 cells (3 PI)
8115 23:22:10.158690 u2DelayCellOfst[13]=13 cells (4 PI)
8116 23:22:10.162107 u2DelayCellOfst[14]=16 cells (5 PI)
8117 23:22:10.165584 u2DelayCellOfst[15]=10 cells (3 PI)
8118 23:22:10.168660 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8119 23:22:10.175296 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8120 23:22:10.175428 DramC Write-DBI on
8121 23:22:10.175546 ==
8122 23:22:10.178545 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 23:22:10.185149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 23:22:10.185271 ==
8125 23:22:10.185371
8126 23:22:10.185472
8127 23:22:10.185567 TX Vref Scan disable
8128 23:22:10.188978 == TX Byte 0 ==
8129 23:22:10.192642 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8130 23:22:10.195773 == TX Byte 1 ==
8131 23:22:10.199054 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8132 23:22:10.202267 DramC Write-DBI off
8133 23:22:10.202410
8134 23:22:10.202538 [DATLAT]
8135 23:22:10.202660 Freq=1600, CH0 RK1
8136 23:22:10.202777
8137 23:22:10.205868 DATLAT Default: 0xf
8138 23:22:10.205998 0, 0xFFFF, sum = 0
8139 23:22:10.209374 1, 0xFFFF, sum = 0
8140 23:22:10.209497 2, 0xFFFF, sum = 0
8141 23:22:10.212438 3, 0xFFFF, sum = 0
8142 23:22:10.215864 4, 0xFFFF, sum = 0
8143 23:22:10.215942 5, 0xFFFF, sum = 0
8144 23:22:10.219219 6, 0xFFFF, sum = 0
8145 23:22:10.219299 7, 0xFFFF, sum = 0
8146 23:22:10.222474 8, 0xFFFF, sum = 0
8147 23:22:10.222550 9, 0xFFFF, sum = 0
8148 23:22:10.225832 10, 0xFFFF, sum = 0
8149 23:22:10.225907 11, 0xFFFF, sum = 0
8150 23:22:10.229159 12, 0xFFFF, sum = 0
8151 23:22:10.229243 13, 0xFFFF, sum = 0
8152 23:22:10.232403 14, 0x0, sum = 1
8153 23:22:10.232536 15, 0x0, sum = 2
8154 23:22:10.235908 16, 0x0, sum = 3
8155 23:22:10.236030 17, 0x0, sum = 4
8156 23:22:10.238945 best_step = 15
8157 23:22:10.239100
8158 23:22:10.239213 ==
8159 23:22:10.242159 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 23:22:10.245376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 23:22:10.245453 ==
8162 23:22:10.248760 RX Vref Scan: 0
8163 23:22:10.248902
8164 23:22:10.248978 RX Vref 0 -> 0, step: 1
8165 23:22:10.249069
8166 23:22:10.252419 RX Delay 19 -> 252, step: 4
8167 23:22:10.255657 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8168 23:22:10.262106 iDelay=195, Bit 1, Center 136 (91 ~ 182) 92
8169 23:22:10.265615 iDelay=195, Bit 2, Center 132 (83 ~ 182) 100
8170 23:22:10.268722 iDelay=195, Bit 3, Center 134 (83 ~ 186) 104
8171 23:22:10.272009 iDelay=195, Bit 4, Center 136 (87 ~ 186) 100
8172 23:22:10.275360 iDelay=195, Bit 5, Center 126 (75 ~ 178) 104
8173 23:22:10.282406 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
8174 23:22:10.285251 iDelay=195, Bit 7, Center 142 (91 ~ 194) 104
8175 23:22:10.288883 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8176 23:22:10.292117 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8177 23:22:10.295345 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8178 23:22:10.301818 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8179 23:22:10.305486 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8180 23:22:10.308893 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8181 23:22:10.312230 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8182 23:22:10.315324 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8183 23:22:10.318873 ==
8184 23:22:10.322272 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 23:22:10.325490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 23:22:10.325618 ==
8187 23:22:10.325763 DQS Delay:
8188 23:22:10.328603 DQS0 = 0, DQS1 = 0
8189 23:22:10.328741 DQM Delay:
8190 23:22:10.332115 DQM0 = 135, DQM1 = 127
8191 23:22:10.332242 DQ Delay:
8192 23:22:10.335302 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =134
8193 23:22:10.338605 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =142
8194 23:22:10.341838 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8195 23:22:10.345146 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8196 23:22:10.345282
8197 23:22:10.345399
8198 23:22:10.345523
8199 23:22:10.348468 [DramC_TX_OE_Calibration] TA2
8200 23:22:10.351773 Original DQ_B0 (3 6) =30, OEN = 27
8201 23:22:10.355225 Original DQ_B1 (3 6) =30, OEN = 27
8202 23:22:10.358399 24, 0x0, End_B0=24 End_B1=24
8203 23:22:10.361972 25, 0x0, End_B0=25 End_B1=25
8204 23:22:10.362100 26, 0x0, End_B0=26 End_B1=26
8205 23:22:10.365120 27, 0x0, End_B0=27 End_B1=27
8206 23:22:10.368653 28, 0x0, End_B0=28 End_B1=28
8207 23:22:10.372138 29, 0x0, End_B0=29 End_B1=29
8208 23:22:10.372222 30, 0x0, End_B0=30 End_B1=30
8209 23:22:10.375377 31, 0x4141, End_B0=30 End_B1=30
8210 23:22:10.378503 Byte0 end_step=30 best_step=27
8211 23:22:10.381703 Byte1 end_step=30 best_step=27
8212 23:22:10.385428 Byte0 TX OE(2T, 0.5T) = (3, 3)
8213 23:22:10.388720 Byte1 TX OE(2T, 0.5T) = (3, 3)
8214 23:22:10.388845
8215 23:22:10.388961
8216 23:22:10.395436 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8217 23:22:10.398436 CH0 RK1: MR19=303, MR18=2008
8218 23:22:10.405304 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8219 23:22:10.408434 [RxdqsGatingPostProcess] freq 1600
8220 23:22:10.411925 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8221 23:22:10.415174 best DQS0 dly(2T, 0.5T) = (1, 1)
8222 23:22:10.418852 best DQS1 dly(2T, 0.5T) = (1, 1)
8223 23:22:10.421580 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8224 23:22:10.425084 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8225 23:22:10.428447 best DQS0 dly(2T, 0.5T) = (1, 1)
8226 23:22:10.431729 best DQS1 dly(2T, 0.5T) = (1, 1)
8227 23:22:10.434835 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8228 23:22:10.438058 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8229 23:22:10.441589 Pre-setting of DQS Precalculation
8230 23:22:10.444958 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8231 23:22:10.445085 ==
8232 23:22:10.448326 Dram Type= 6, Freq= 0, CH_1, rank 0
8233 23:22:10.454889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 23:22:10.455019 ==
8235 23:22:10.457997 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8236 23:22:10.464855 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8237 23:22:10.467966 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8238 23:22:10.474529 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8239 23:22:10.482234 [CA 0] Center 41 (12~71) winsize 60
8240 23:22:10.485545 [CA 1] Center 41 (12~71) winsize 60
8241 23:22:10.488728 [CA 2] Center 38 (9~68) winsize 60
8242 23:22:10.492355 [CA 3] Center 37 (8~66) winsize 59
8243 23:22:10.495520 [CA 4] Center 37 (8~67) winsize 60
8244 23:22:10.498747 [CA 5] Center 36 (7~66) winsize 60
8245 23:22:10.498873
8246 23:22:10.502290 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8247 23:22:10.502416
8248 23:22:10.505468 [CATrainingPosCal] consider 1 rank data
8249 23:22:10.508612 u2DelayCellTimex100 = 290/100 ps
8250 23:22:10.512006 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8251 23:22:10.518995 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8252 23:22:10.522268 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8253 23:22:10.525543 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8254 23:22:10.528683 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8255 23:22:10.531886 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8256 23:22:10.531986
8257 23:22:10.535467 CA PerBit enable=1, Macro0, CA PI delay=36
8258 23:22:10.535569
8259 23:22:10.538542 [CBTSetCACLKResult] CA Dly = 36
8260 23:22:10.541922 CS Dly: 10 (0~41)
8261 23:22:10.545198 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8262 23:22:10.548841 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8263 23:22:10.548944 ==
8264 23:22:10.552129 Dram Type= 6, Freq= 0, CH_1, rank 1
8265 23:22:10.555172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 23:22:10.555300 ==
8267 23:22:10.562106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 23:22:10.565340 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 23:22:10.571913 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 23:22:10.575235 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 23:22:10.585536 [CA 0] Center 42 (12~72) winsize 61
8272 23:22:10.588813 [CA 1] Center 41 (12~71) winsize 60
8273 23:22:10.591951 [CA 2] Center 38 (9~68) winsize 60
8274 23:22:10.595607 [CA 3] Center 37 (8~67) winsize 60
8275 23:22:10.598846 [CA 4] Center 38 (8~68) winsize 61
8276 23:22:10.602160 [CA 5] Center 37 (8~67) winsize 60
8277 23:22:10.602275
8278 23:22:10.605383 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8279 23:22:10.605524
8280 23:22:10.608618 [CATrainingPosCal] consider 2 rank data
8281 23:22:10.612182 u2DelayCellTimex100 = 290/100 ps
8282 23:22:10.615507 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8283 23:22:10.622170 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8284 23:22:10.625211 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8285 23:22:10.628695 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8286 23:22:10.631963 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8287 23:22:10.635339 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8288 23:22:10.635494
8289 23:22:10.638349 CA PerBit enable=1, Macro0, CA PI delay=37
8290 23:22:10.638494
8291 23:22:10.641650 [CBTSetCACLKResult] CA Dly = 37
8292 23:22:10.645329 CS Dly: 11 (0~44)
8293 23:22:10.648754 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 23:22:10.652148 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 23:22:10.652282
8296 23:22:10.655099 ----->DramcWriteLeveling(PI) begin...
8297 23:22:10.655226 ==
8298 23:22:10.658448 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 23:22:10.661904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 23:22:10.665287 ==
8301 23:22:10.665410 Write leveling (Byte 0): 25 => 25
8302 23:22:10.668497 Write leveling (Byte 1): 26 => 26
8303 23:22:10.671625 DramcWriteLeveling(PI) end<-----
8304 23:22:10.671767
8305 23:22:10.671879 ==
8306 23:22:10.675012 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 23:22:10.681701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 23:22:10.681809 ==
8309 23:22:10.684800 [Gating] SW mode calibration
8310 23:22:10.691465 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8311 23:22:10.695175 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8312 23:22:10.701521 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 23:22:10.704757 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8314 23:22:10.708322 1 4 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
8315 23:22:10.714620 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
8316 23:22:10.717968 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 23:22:10.721204 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 23:22:10.728327 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 23:22:10.731468 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 23:22:10.734667 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 23:22:10.741116 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 23:22:10.744895 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)
8323 23:22:10.748190 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
8324 23:22:10.751317 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 23:22:10.757989 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 23:22:10.761062 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 23:22:10.764361 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 23:22:10.771122 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 23:22:10.774481 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 23:22:10.777780 1 6 8 | B1->B0 | 2525 4242 | 0 0 | (0 0) (0 0)
8331 23:22:10.784647 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8332 23:22:10.787687 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 23:22:10.790809 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 23:22:10.797849 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 23:22:10.800840 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 23:22:10.804236 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 23:22:10.810876 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 23:22:10.814045 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8339 23:22:10.817662 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8340 23:22:10.824120 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 23:22:10.827261 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 23:22:10.830775 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 23:22:10.837171 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 23:22:10.840866 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 23:22:10.843948 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 23:22:10.850688 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 23:22:10.853922 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 23:22:10.857332 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 23:22:10.863687 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 23:22:10.867222 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 23:22:10.870573 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 23:22:10.877173 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 23:22:10.880684 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 23:22:10.883629 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8355 23:22:10.890399 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8356 23:22:10.893963 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 23:22:10.897195 Total UI for P1: 0, mck2ui 16
8358 23:22:10.900183 best dqsien dly found for B0: ( 1, 9, 10)
8359 23:22:10.903676 Total UI for P1: 0, mck2ui 16
8360 23:22:10.906854 best dqsien dly found for B1: ( 1, 9, 10)
8361 23:22:10.910225 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8362 23:22:10.913691 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8363 23:22:10.913821
8364 23:22:10.917140 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8365 23:22:10.920549 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8366 23:22:10.923759 [Gating] SW calibration Done
8367 23:22:10.923871 ==
8368 23:22:10.926860 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 23:22:10.930339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 23:22:10.933568 ==
8371 23:22:10.933653 RX Vref Scan: 0
8372 23:22:10.933740
8373 23:22:11.010983 RX Vref 0 -> 0, step: 1
8374 23:22:11.011221
8375 23:22:11.011361 RX Delay 0 -> 252, step: 8
8376 23:22:11.011714 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8377 23:22:11.011845 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8378 23:22:11.011972 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8379 23:22:11.012095 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8380 23:22:11.012225 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8381 23:22:11.012363 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8382 23:22:11.012483 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8383 23:22:11.012609 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8384 23:22:11.012730 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8385 23:22:11.012862 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8386 23:22:11.012985 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8387 23:22:11.013095 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8388 23:22:11.013233 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8389 23:22:11.013345 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8390 23:22:11.013463 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8391 23:22:11.013596 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8392 23:22:11.013723 ==
8393 23:22:11.013839 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 23:22:11.013972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 23:22:11.014094 ==
8396 23:22:11.014222 DQS Delay:
8397 23:22:11.014354 DQS0 = 0, DQS1 = 0
8398 23:22:11.014477 DQM Delay:
8399 23:22:11.016443 DQM0 = 136, DQM1 = 132
8400 23:22:11.016584 DQ Delay:
8401 23:22:11.019729 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8402 23:22:11.023067 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8403 23:22:11.026199 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8404 23:22:11.032963 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8405 23:22:11.033061
8406 23:22:11.033127
8407 23:22:11.033196 ==
8408 23:22:11.036212 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 23:22:11.039450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 23:22:11.039543 ==
8411 23:22:11.039617
8412 23:22:11.039688
8413 23:22:11.042847 TX Vref Scan disable
8414 23:22:11.042930 == TX Byte 0 ==
8415 23:22:11.049508 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8416 23:22:11.052647 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8417 23:22:11.052751 == TX Byte 1 ==
8418 23:22:11.059547 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8419 23:22:11.062737 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8420 23:22:11.062819 ==
8421 23:22:11.065951 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 23:22:11.069230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 23:22:11.069320 ==
8424 23:22:11.082835
8425 23:22:11.086038 TX Vref early break, caculate TX vref
8426 23:22:11.089533 TX Vref=16, minBit 0, minWin=22, winSum=376
8427 23:22:11.092549 TX Vref=18, minBit 1, minWin=22, winSum=384
8428 23:22:11.096013 TX Vref=20, minBit 1, minWin=23, winSum=394
8429 23:22:11.099226 TX Vref=22, minBit 1, minWin=23, winSum=405
8430 23:22:11.102428 TX Vref=24, minBit 0, minWin=24, winSum=419
8431 23:22:11.109055 TX Vref=26, minBit 0, minWin=25, winSum=423
8432 23:22:11.112705 TX Vref=28, minBit 1, minWin=25, winSum=427
8433 23:22:11.115836 TX Vref=30, minBit 0, minWin=24, winSum=423
8434 23:22:11.118898 TX Vref=32, minBit 0, minWin=25, winSum=415
8435 23:22:11.122499 TX Vref=34, minBit 2, minWin=23, winSum=404
8436 23:22:11.128888 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 28
8437 23:22:11.128979
8438 23:22:11.132139 Final TX Range 0 Vref 28
8439 23:22:11.132215
8440 23:22:11.132298 ==
8441 23:22:11.135414 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 23:22:11.138974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 23:22:11.139068 ==
8444 23:22:11.139134
8445 23:22:11.139202
8446 23:22:11.142472 TX Vref Scan disable
8447 23:22:11.149213 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8448 23:22:11.149293 == TX Byte 0 ==
8449 23:22:11.152486 u2DelayCellOfst[0]=20 cells (6 PI)
8450 23:22:11.155878 u2DelayCellOfst[1]=10 cells (3 PI)
8451 23:22:11.159114 u2DelayCellOfst[2]=0 cells (0 PI)
8452 23:22:11.162295 u2DelayCellOfst[3]=6 cells (2 PI)
8453 23:22:11.165556 u2DelayCellOfst[4]=6 cells (2 PI)
8454 23:22:11.169251 u2DelayCellOfst[5]=20 cells (6 PI)
8455 23:22:11.172438 u2DelayCellOfst[6]=20 cells (6 PI)
8456 23:22:11.172516 u2DelayCellOfst[7]=6 cells (2 PI)
8457 23:22:11.178865 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8458 23:22:11.182520 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8459 23:22:11.182607 == TX Byte 1 ==
8460 23:22:11.185359 u2DelayCellOfst[8]=0 cells (0 PI)
8461 23:22:11.188838 u2DelayCellOfst[9]=3 cells (1 PI)
8462 23:22:11.192193 u2DelayCellOfst[10]=10 cells (3 PI)
8463 23:22:11.195465 u2DelayCellOfst[11]=6 cells (2 PI)
8464 23:22:11.198618 u2DelayCellOfst[12]=13 cells (4 PI)
8465 23:22:11.202105 u2DelayCellOfst[13]=16 cells (5 PI)
8466 23:22:11.205283 u2DelayCellOfst[14]=16 cells (5 PI)
8467 23:22:11.208826 u2DelayCellOfst[15]=16 cells (5 PI)
8468 23:22:11.211837 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8469 23:22:11.218402 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8470 23:22:11.218499 DramC Write-DBI on
8471 23:22:11.218588 ==
8472 23:22:11.221735 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 23:22:11.225153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 23:22:11.228277 ==
8475 23:22:11.228379
8476 23:22:11.228455
8477 23:22:11.228519 TX Vref Scan disable
8478 23:22:11.231998 == TX Byte 0 ==
8479 23:22:11.235382 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8480 23:22:11.238670 == TX Byte 1 ==
8481 23:22:11.241783 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8482 23:22:11.241876 DramC Write-DBI off
8483 23:22:11.245432
8484 23:22:11.245516 [DATLAT]
8485 23:22:11.245580 Freq=1600, CH1 RK0
8486 23:22:11.245641
8487 23:22:11.248881 DATLAT Default: 0xf
8488 23:22:11.248960 0, 0xFFFF, sum = 0
8489 23:22:11.252178 1, 0xFFFF, sum = 0
8490 23:22:11.252283 2, 0xFFFF, sum = 0
8491 23:22:11.255338 3, 0xFFFF, sum = 0
8492 23:22:11.255422 4, 0xFFFF, sum = 0
8493 23:22:11.258719 5, 0xFFFF, sum = 0
8494 23:22:11.261722 6, 0xFFFF, sum = 0
8495 23:22:11.261803 7, 0xFFFF, sum = 0
8496 23:22:11.265284 8, 0xFFFF, sum = 0
8497 23:22:11.265379 9, 0xFFFF, sum = 0
8498 23:22:11.268515 10, 0xFFFF, sum = 0
8499 23:22:11.268599 11, 0xFFFF, sum = 0
8500 23:22:11.271716 12, 0xFFFF, sum = 0
8501 23:22:11.271799 13, 0xFFFF, sum = 0
8502 23:22:11.275409 14, 0x0, sum = 1
8503 23:22:11.275492 15, 0x0, sum = 2
8504 23:22:11.278706 16, 0x0, sum = 3
8505 23:22:11.278802 17, 0x0, sum = 4
8506 23:22:11.281824 best_step = 15
8507 23:22:11.281931
8508 23:22:11.282023 ==
8509 23:22:11.285206 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 23:22:11.288739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 23:22:11.288842 ==
8512 23:22:11.288924 RX Vref Scan: 1
8513 23:22:11.288988
8514 23:22:11.291642 Set Vref Range= 24 -> 127
8515 23:22:11.291728
8516 23:22:11.295314 RX Vref 24 -> 127, step: 1
8517 23:22:11.295390
8518 23:22:11.298656 RX Delay 27 -> 252, step: 4
8519 23:22:11.298733
8520 23:22:11.301577 Set Vref, RX VrefLevel [Byte0]: 24
8521 23:22:11.304979 [Byte1]: 24
8522 23:22:11.305056
8523 23:22:11.308250 Set Vref, RX VrefLevel [Byte0]: 25
8524 23:22:11.311568 [Byte1]: 25
8525 23:22:11.311721
8526 23:22:11.315013 Set Vref, RX VrefLevel [Byte0]: 26
8527 23:22:11.318292 [Byte1]: 26
8528 23:22:11.321919
8529 23:22:11.322026 Set Vref, RX VrefLevel [Byte0]: 27
8530 23:22:11.325450 [Byte1]: 27
8531 23:22:11.329457
8532 23:22:11.329535 Set Vref, RX VrefLevel [Byte0]: 28
8533 23:22:11.332786 [Byte1]: 28
8534 23:22:11.336766
8535 23:22:11.340124 Set Vref, RX VrefLevel [Byte0]: 29
8536 23:22:11.343528 [Byte1]: 29
8537 23:22:11.343606
8538 23:22:11.346802 Set Vref, RX VrefLevel [Byte0]: 30
8539 23:22:11.350180 [Byte1]: 30
8540 23:22:11.350310
8541 23:22:11.353278 Set Vref, RX VrefLevel [Byte0]: 31
8542 23:22:11.356726 [Byte1]: 31
8543 23:22:11.356840
8544 23:22:11.360195 Set Vref, RX VrefLevel [Byte0]: 32
8545 23:22:11.363584 [Byte1]: 32
8546 23:22:11.367068
8547 23:22:11.367224 Set Vref, RX VrefLevel [Byte0]: 33
8548 23:22:11.370431 [Byte1]: 33
8549 23:22:11.374540
8550 23:22:11.374647 Set Vref, RX VrefLevel [Byte0]: 34
8551 23:22:11.378155 [Byte1]: 34
8552 23:22:11.382235
8553 23:22:11.382358 Set Vref, RX VrefLevel [Byte0]: 35
8554 23:22:11.385478 [Byte1]: 35
8555 23:22:11.389872
8556 23:22:11.389976 Set Vref, RX VrefLevel [Byte0]: 36
8557 23:22:11.393227 [Byte1]: 36
8558 23:22:11.397385
8559 23:22:11.397474 Set Vref, RX VrefLevel [Byte0]: 37
8560 23:22:11.400559 [Byte1]: 37
8561 23:22:11.404706
8562 23:22:11.404783 Set Vref, RX VrefLevel [Byte0]: 38
8563 23:22:11.408410 [Byte1]: 38
8564 23:22:11.412525
8565 23:22:11.412601 Set Vref, RX VrefLevel [Byte0]: 39
8566 23:22:11.415636 [Byte1]: 39
8567 23:22:11.419844
8568 23:22:11.420000 Set Vref, RX VrefLevel [Byte0]: 40
8569 23:22:11.423349 [Byte1]: 40
8570 23:22:11.427314
8571 23:22:11.427441 Set Vref, RX VrefLevel [Byte0]: 41
8572 23:22:11.430842 [Byte1]: 41
8573 23:22:11.435125
8574 23:22:11.435306 Set Vref, RX VrefLevel [Byte0]: 42
8575 23:22:11.438243 [Byte1]: 42
8576 23:22:11.442391
8577 23:22:11.442475 Set Vref, RX VrefLevel [Byte0]: 43
8578 23:22:11.445587 [Byte1]: 43
8579 23:22:11.450056
8580 23:22:11.450138 Set Vref, RX VrefLevel [Byte0]: 44
8581 23:22:11.453460 [Byte1]: 44
8582 23:22:11.457427
8583 23:22:11.457539 Set Vref, RX VrefLevel [Byte0]: 45
8584 23:22:11.460784 [Byte1]: 45
8585 23:22:11.465122
8586 23:22:11.465292 Set Vref, RX VrefLevel [Byte0]: 46
8587 23:22:11.468212 [Byte1]: 46
8588 23:22:11.472492
8589 23:22:11.472570 Set Vref, RX VrefLevel [Byte0]: 47
8590 23:22:11.475910 [Byte1]: 47
8591 23:22:11.480167
8592 23:22:11.480293 Set Vref, RX VrefLevel [Byte0]: 48
8593 23:22:11.483413 [Byte1]: 48
8594 23:22:11.487722
8595 23:22:11.487855 Set Vref, RX VrefLevel [Byte0]: 49
8596 23:22:11.491262 [Byte1]: 49
8597 23:22:11.495060
8598 23:22:11.495196 Set Vref, RX VrefLevel [Byte0]: 50
8599 23:22:11.498755 [Byte1]: 50
8600 23:22:11.502812
8601 23:22:11.502962 Set Vref, RX VrefLevel [Byte0]: 51
8602 23:22:11.505966 [Byte1]: 51
8603 23:22:11.510230
8604 23:22:11.510310 Set Vref, RX VrefLevel [Byte0]: 52
8605 23:22:11.513427 [Byte1]: 52
8606 23:22:11.518027
8607 23:22:11.518107 Set Vref, RX VrefLevel [Byte0]: 53
8608 23:22:11.521276 [Byte1]: 53
8609 23:22:11.525369
8610 23:22:11.525447 Set Vref, RX VrefLevel [Byte0]: 54
8611 23:22:11.528568 [Byte1]: 54
8612 23:22:11.532966
8613 23:22:11.533092 Set Vref, RX VrefLevel [Byte0]: 55
8614 23:22:11.536222 [Byte1]: 55
8615 23:22:11.540521
8616 23:22:11.540643 Set Vref, RX VrefLevel [Byte0]: 56
8617 23:22:11.543960 [Byte1]: 56
8618 23:22:11.548133
8619 23:22:11.548217 Set Vref, RX VrefLevel [Byte0]: 57
8620 23:22:11.551228 [Byte1]: 57
8621 23:22:11.555567
8622 23:22:11.555694 Set Vref, RX VrefLevel [Byte0]: 58
8623 23:22:11.558670 [Byte1]: 58
8624 23:22:11.563312
8625 23:22:11.563437 Set Vref, RX VrefLevel [Byte0]: 59
8626 23:22:11.566418 [Byte1]: 59
8627 23:22:11.570441
8628 23:22:11.570563 Set Vref, RX VrefLevel [Byte0]: 60
8629 23:22:11.573649 [Byte1]: 60
8630 23:22:11.578335
8631 23:22:11.578454 Set Vref, RX VrefLevel [Byte0]: 61
8632 23:22:11.581418 [Byte1]: 61
8633 23:22:11.585580
8634 23:22:11.585686 Set Vref, RX VrefLevel [Byte0]: 62
8635 23:22:11.588981 [Byte1]: 62
8636 23:22:11.593038
8637 23:22:11.593124 Set Vref, RX VrefLevel [Byte0]: 63
8638 23:22:11.596219 [Byte1]: 63
8639 23:22:11.600778
8640 23:22:11.600871 Set Vref, RX VrefLevel [Byte0]: 64
8641 23:22:11.603965 [Byte1]: 64
8642 23:22:11.608183
8643 23:22:11.608307 Set Vref, RX VrefLevel [Byte0]: 65
8644 23:22:11.611354 [Byte1]: 65
8645 23:22:11.615961
8646 23:22:11.616074 Set Vref, RX VrefLevel [Byte0]: 66
8647 23:22:11.619322 [Byte1]: 66
8648 23:22:11.623529
8649 23:22:11.623613 Set Vref, RX VrefLevel [Byte0]: 67
8650 23:22:11.626741 [Byte1]: 67
8651 23:22:11.630847
8652 23:22:11.630958 Set Vref, RX VrefLevel [Byte0]: 68
8653 23:22:11.634042 [Byte1]: 68
8654 23:22:11.638473
8655 23:22:11.638562 Set Vref, RX VrefLevel [Byte0]: 69
8656 23:22:11.641819 [Byte1]: 69
8657 23:22:11.645983
8658 23:22:11.646066 Set Vref, RX VrefLevel [Byte0]: 70
8659 23:22:11.649376 [Byte1]: 70
8660 23:22:11.653513
8661 23:22:11.653596 Set Vref, RX VrefLevel [Byte0]: 71
8662 23:22:11.656891 [Byte1]: 71
8663 23:22:11.661023
8664 23:22:11.661110 Set Vref, RX VrefLevel [Byte0]: 72
8665 23:22:11.664199 [Byte1]: 72
8666 23:22:11.668576
8667 23:22:11.668659 Set Vref, RX VrefLevel [Byte0]: 73
8668 23:22:11.671867 [Byte1]: 73
8669 23:22:11.676035
8670 23:22:11.676116 Set Vref, RX VrefLevel [Byte0]: 74
8671 23:22:11.679221 [Byte1]: 74
8672 23:22:11.683349
8673 23:22:11.683444 Set Vref, RX VrefLevel [Byte0]: 75
8674 23:22:11.686801 [Byte1]: 75
8675 23:22:11.690910
8676 23:22:11.690985 Final RX Vref Byte 0 = 60 to rank0
8677 23:22:11.694430 Final RX Vref Byte 1 = 56 to rank0
8678 23:22:11.697642 Final RX Vref Byte 0 = 60 to rank1
8679 23:22:11.700845 Final RX Vref Byte 1 = 56 to rank1==
8680 23:22:11.704268 Dram Type= 6, Freq= 0, CH_1, rank 0
8681 23:22:11.710907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8682 23:22:11.711035 ==
8683 23:22:11.711149 DQS Delay:
8684 23:22:11.711263 DQS0 = 0, DQS1 = 0
8685 23:22:11.714084 DQM Delay:
8686 23:22:11.714205 DQM0 = 134, DQM1 = 131
8687 23:22:11.717356 DQ Delay:
8688 23:22:11.720721 DQ0 =140, DQ1 =128, DQ2 =120, DQ3 =130
8689 23:22:11.724081 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8690 23:22:11.727401 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8691 23:22:11.730874 DQ12 =138, DQ13 =140, DQ14 =138, DQ15 =140
8692 23:22:11.730957
8693 23:22:11.731021
8694 23:22:11.731082
8695 23:22:11.734084 [DramC_TX_OE_Calibration] TA2
8696 23:22:11.737257 Original DQ_B0 (3 6) =30, OEN = 27
8697 23:22:11.740801 Original DQ_B1 (3 6) =30, OEN = 27
8698 23:22:11.744072 24, 0x0, End_B0=24 End_B1=24
8699 23:22:11.744175 25, 0x0, End_B0=25 End_B1=25
8700 23:22:11.747283 26, 0x0, End_B0=26 End_B1=26
8701 23:22:11.750523 27, 0x0, End_B0=27 End_B1=27
8702 23:22:11.754137 28, 0x0, End_B0=28 End_B1=28
8703 23:22:11.757359 29, 0x0, End_B0=29 End_B1=29
8704 23:22:11.757453 30, 0x0, End_B0=30 End_B1=30
8705 23:22:11.760635 31, 0x4141, End_B0=30 End_B1=30
8706 23:22:11.763835 Byte0 end_step=30 best_step=27
8707 23:22:11.767424 Byte1 end_step=30 best_step=27
8708 23:22:11.770545 Byte0 TX OE(2T, 0.5T) = (3, 3)
8709 23:22:11.773998 Byte1 TX OE(2T, 0.5T) = (3, 3)
8710 23:22:11.774113
8711 23:22:11.774214
8712 23:22:11.780738 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8713 23:22:11.783773 CH1 RK0: MR19=303, MR18=1624
8714 23:22:11.790270 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8715 23:22:11.790356
8716 23:22:11.793853 ----->DramcWriteLeveling(PI) begin...
8717 23:22:11.793965 ==
8718 23:22:11.797393 Dram Type= 6, Freq= 0, CH_1, rank 1
8719 23:22:11.800784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8720 23:22:11.800873 ==
8721 23:22:11.803918 Write leveling (Byte 0): 25 => 25
8722 23:22:11.807540 Write leveling (Byte 1): 29 => 29
8723 23:22:11.810739 DramcWriteLeveling(PI) end<-----
8724 23:22:11.810844
8725 23:22:11.810948 ==
8726 23:22:11.813807 Dram Type= 6, Freq= 0, CH_1, rank 1
8727 23:22:11.817029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8728 23:22:11.817136 ==
8729 23:22:11.820463 [Gating] SW mode calibration
8730 23:22:11.827167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8731 23:22:11.833497 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8732 23:22:11.836743 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8733 23:22:11.843589 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8734 23:22:11.847146 1 4 8 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8735 23:22:11.850235 1 4 12 | B1->B0 | 3434 2b2a | 1 1 | (1 1) (0 0)
8736 23:22:11.853504 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 23:22:11.860413 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 23:22:11.863240 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 23:22:11.866856 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 23:22:11.873358 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8741 23:22:11.876505 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8742 23:22:11.880296 1 5 8 | B1->B0 | 2727 3434 | 0 1 | (1 0) (1 0)
8743 23:22:11.886594 1 5 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
8744 23:22:11.890033 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 23:22:11.892998 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 23:22:11.899809 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 23:22:11.903291 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 23:22:11.906494 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 23:22:11.912965 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8750 23:22:11.916419 1 6 8 | B1->B0 | 4545 2626 | 0 0 | (0 0) (0 0)
8751 23:22:11.919954 1 6 12 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
8752 23:22:11.926389 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 23:22:11.929516 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 23:22:11.932803 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 23:22:11.939451 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 23:22:11.942672 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 23:22:11.946100 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8758 23:22:11.952610 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8759 23:22:11.955812 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8760 23:22:11.959161 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8761 23:22:11.965453 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 23:22:11.969185 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 23:22:11.972358 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 23:22:11.978795 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 23:22:11.982118 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 23:22:11.985306 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 23:22:11.992318 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 23:22:11.995557 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 23:22:11.998581 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 23:22:12.005181 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 23:22:12.008323 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 23:22:12.012027 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 23:22:12.018446 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8774 23:22:12.021747 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8775 23:22:12.024902 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8776 23:22:12.028241 Total UI for P1: 0, mck2ui 16
8777 23:22:12.031415 best dqsien dly found for B1: ( 1, 9, 6)
8778 23:22:12.038102 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 23:22:12.041735 Total UI for P1: 0, mck2ui 16
8780 23:22:12.044952 best dqsien dly found for B0: ( 1, 9, 10)
8781 23:22:12.048117 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8782 23:22:12.051460 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8783 23:22:12.051577
8784 23:22:12.054955 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8785 23:22:12.058251 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8786 23:22:12.061673 [Gating] SW calibration Done
8787 23:22:12.061802 ==
8788 23:22:12.064675 Dram Type= 6, Freq= 0, CH_1, rank 1
8789 23:22:12.068112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8790 23:22:12.068222 ==
8791 23:22:12.071302 RX Vref Scan: 0
8792 23:22:12.071409
8793 23:22:12.071517 RX Vref 0 -> 0, step: 1
8794 23:22:12.074580
8795 23:22:12.074662 RX Delay 0 -> 252, step: 8
8796 23:22:12.081404 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8797 23:22:12.084453 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8798 23:22:12.088173 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8799 23:22:12.091366 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8800 23:22:12.094602 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8801 23:22:12.101083 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8802 23:22:12.104296 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8803 23:22:12.107759 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8804 23:22:12.110933 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8805 23:22:12.114370 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8806 23:22:12.120816 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8807 23:22:12.124091 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8808 23:22:12.127341 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8809 23:22:12.130881 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8810 23:22:12.134310 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8811 23:22:12.140778 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8812 23:22:12.140872 ==
8813 23:22:12.144170 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 23:22:12.147319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 23:22:12.147452 ==
8816 23:22:12.147555 DQS Delay:
8817 23:22:12.150516 DQS0 = 0, DQS1 = 0
8818 23:22:12.150637 DQM Delay:
8819 23:22:12.154197 DQM0 = 136, DQM1 = 133
8820 23:22:12.154325 DQ Delay:
8821 23:22:12.157203 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8822 23:22:12.160602 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8823 23:22:12.164051 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8824 23:22:12.167167 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8825 23:22:12.170353
8826 23:22:12.170475
8827 23:22:12.170583 ==
8828 23:22:12.174005 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 23:22:12.177126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 23:22:12.177208 ==
8831 23:22:12.177273
8832 23:22:12.177333
8833 23:22:12.180741 TX Vref Scan disable
8834 23:22:12.180819 == TX Byte 0 ==
8835 23:22:12.187232 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8836 23:22:12.190456 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8837 23:22:12.190583 == TX Byte 1 ==
8838 23:22:12.197187 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8839 23:22:12.200425 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8840 23:22:12.200556 ==
8841 23:22:12.203501 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 23:22:12.206758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 23:22:12.206886 ==
8844 23:22:12.221765
8845 23:22:12.224943 TX Vref early break, caculate TX vref
8846 23:22:12.228346 TX Vref=16, minBit 1, minWin=22, winSum=379
8847 23:22:12.231613 TX Vref=18, minBit 2, minWin=23, winSum=393
8848 23:22:12.234804 TX Vref=20, minBit 1, minWin=23, winSum=400
8849 23:22:12.238097 TX Vref=22, minBit 2, minWin=23, winSum=407
8850 23:22:12.241448 TX Vref=24, minBit 0, minWin=24, winSum=413
8851 23:22:12.248321 TX Vref=26, minBit 0, minWin=25, winSum=421
8852 23:22:12.251549 TX Vref=28, minBit 0, minWin=25, winSum=425
8853 23:22:12.254877 TX Vref=30, minBit 0, minWin=25, winSum=422
8854 23:22:12.258422 TX Vref=32, minBit 0, minWin=25, winSum=412
8855 23:22:12.261388 TX Vref=34, minBit 0, minWin=24, winSum=405
8856 23:22:12.265136 TX Vref=36, minBit 0, minWin=23, winSum=396
8857 23:22:12.271454 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8858 23:22:12.271566
8859 23:22:12.274955 Final TX Range 0 Vref 28
8860 23:22:12.275034
8861 23:22:12.275096 ==
8862 23:22:12.278166 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 23:22:12.281402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 23:22:12.281518 ==
8865 23:22:12.281629
8866 23:22:12.281730
8867 23:22:12.284832 TX Vref Scan disable
8868 23:22:12.291619 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8869 23:22:12.291747 == TX Byte 0 ==
8870 23:22:12.294843 u2DelayCellOfst[0]=20 cells (6 PI)
8871 23:22:12.298169 u2DelayCellOfst[1]=10 cells (3 PI)
8872 23:22:12.301416 u2DelayCellOfst[2]=0 cells (0 PI)
8873 23:22:12.304969 u2DelayCellOfst[3]=6 cells (2 PI)
8874 23:22:12.307954 u2DelayCellOfst[4]=10 cells (3 PI)
8875 23:22:12.311321 u2DelayCellOfst[5]=20 cells (6 PI)
8876 23:22:12.315016 u2DelayCellOfst[6]=20 cells (6 PI)
8877 23:22:12.318321 u2DelayCellOfst[7]=6 cells (2 PI)
8878 23:22:12.321505 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8879 23:22:12.324562 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8880 23:22:12.327735 == TX Byte 1 ==
8881 23:22:12.331418 u2DelayCellOfst[8]=0 cells (0 PI)
8882 23:22:12.331501 u2DelayCellOfst[9]=6 cells (2 PI)
8883 23:22:12.334636 u2DelayCellOfst[10]=13 cells (4 PI)
8884 23:22:12.337816 u2DelayCellOfst[11]=6 cells (2 PI)
8885 23:22:12.341097 u2DelayCellOfst[12]=16 cells (5 PI)
8886 23:22:12.344359 u2DelayCellOfst[13]=16 cells (5 PI)
8887 23:22:12.347918 u2DelayCellOfst[14]=20 cells (6 PI)
8888 23:22:12.351143 u2DelayCellOfst[15]=20 cells (6 PI)
8889 23:22:12.354387 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8890 23:22:12.361301 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8891 23:22:12.361396 DramC Write-DBI on
8892 23:22:12.361462 ==
8893 23:22:12.364399 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 23:22:12.370847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 23:22:12.370963 ==
8896 23:22:12.371061
8897 23:22:12.371151
8898 23:22:12.371239 TX Vref Scan disable
8899 23:22:12.375068 == TX Byte 0 ==
8900 23:22:12.378387 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8901 23:22:12.381522 == TX Byte 1 ==
8902 23:22:12.384559 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8903 23:22:12.388113 DramC Write-DBI off
8904 23:22:12.388227
8905 23:22:12.388335 [DATLAT]
8906 23:22:12.388405 Freq=1600, CH1 RK1
8907 23:22:12.388468
8908 23:22:12.391242 DATLAT Default: 0xf
8909 23:22:12.391345 0, 0xFFFF, sum = 0
8910 23:22:12.394649 1, 0xFFFF, sum = 0
8911 23:22:12.398207 2, 0xFFFF, sum = 0
8912 23:22:12.398330 3, 0xFFFF, sum = 0
8913 23:22:12.401513 4, 0xFFFF, sum = 0
8914 23:22:12.401623 5, 0xFFFF, sum = 0
8915 23:22:12.404675 6, 0xFFFF, sum = 0
8916 23:22:12.404762 7, 0xFFFF, sum = 0
8917 23:22:12.407863 8, 0xFFFF, sum = 0
8918 23:22:12.407968 9, 0xFFFF, sum = 0
8919 23:22:12.411364 10, 0xFFFF, sum = 0
8920 23:22:12.411456 11, 0xFFFF, sum = 0
8921 23:22:12.414800 12, 0xFFFF, sum = 0
8922 23:22:12.414937 13, 0xFFFF, sum = 0
8923 23:22:12.417960 14, 0x0, sum = 1
8924 23:22:12.418064 15, 0x0, sum = 2
8925 23:22:12.421228 16, 0x0, sum = 3
8926 23:22:12.421320 17, 0x0, sum = 4
8927 23:22:12.424407 best_step = 15
8928 23:22:12.424487
8929 23:22:12.424552 ==
8930 23:22:12.427696 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 23:22:12.431189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 23:22:12.431293 ==
8933 23:22:12.434302 RX Vref Scan: 0
8934 23:22:12.434382
8935 23:22:12.434446 RX Vref 0 -> 0, step: 1
8936 23:22:12.434505
8937 23:22:12.437762 RX Delay 19 -> 252, step: 4
8938 23:22:12.440910 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8939 23:22:12.447748 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8940 23:22:12.450972 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8941 23:22:12.454282 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8942 23:22:12.457417 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8943 23:22:12.461214 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8944 23:22:12.467674 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8945 23:22:12.470866 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8946 23:22:12.474002 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8947 23:22:12.477518 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8948 23:22:12.480898 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8949 23:22:12.487473 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8950 23:22:12.490594 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8951 23:22:12.494059 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8952 23:22:12.497135 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8953 23:22:12.500748 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8954 23:22:12.504198 ==
8955 23:22:12.507583 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 23:22:12.510497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 23:22:12.510581 ==
8958 23:22:12.510682 DQS Delay:
8959 23:22:12.514231 DQS0 = 0, DQS1 = 0
8960 23:22:12.514333 DQM Delay:
8961 23:22:12.517546 DQM0 = 134, DQM1 = 130
8962 23:22:12.517651 DQ Delay:
8963 23:22:12.520714 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8964 23:22:12.524240 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8965 23:22:12.527296 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =126
8966 23:22:12.530658 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8967 23:22:12.530766
8968 23:22:12.530859
8969 23:22:12.530948
8970 23:22:12.533869 [DramC_TX_OE_Calibration] TA2
8971 23:22:12.537638 Original DQ_B0 (3 6) =30, OEN = 27
8972 23:22:12.540615 Original DQ_B1 (3 6) =30, OEN = 27
8973 23:22:12.544308 24, 0x0, End_B0=24 End_B1=24
8974 23:22:12.547143 25, 0x0, End_B0=25 End_B1=25
8975 23:22:12.547280 26, 0x0, End_B0=26 End_B1=26
8976 23:22:12.550867 27, 0x0, End_B0=27 End_B1=27
8977 23:22:12.554187 28, 0x0, End_B0=28 End_B1=28
8978 23:22:12.557409 29, 0x0, End_B0=29 End_B1=29
8979 23:22:12.557544 30, 0x0, End_B0=30 End_B1=30
8980 23:22:12.560672 31, 0x4141, End_B0=30 End_B1=30
8981 23:22:12.563809 Byte0 end_step=30 best_step=27
8982 23:22:12.567087 Byte1 end_step=30 best_step=27
8983 23:22:12.570674 Byte0 TX OE(2T, 0.5T) = (3, 3)
8984 23:22:12.573939 Byte1 TX OE(2T, 0.5T) = (3, 3)
8985 23:22:12.574067
8986 23:22:12.574193
8987 23:22:12.580375 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
8988 23:22:12.583806 CH1 RK1: MR19=303, MR18=2409
8989 23:22:12.590572 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
8990 23:22:12.593558 [RxdqsGatingPostProcess] freq 1600
8991 23:22:12.600374 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8992 23:22:12.600488 best DQS0 dly(2T, 0.5T) = (1, 1)
8993 23:22:12.603845 best DQS1 dly(2T, 0.5T) = (1, 1)
8994 23:22:12.607128 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8995 23:22:12.610264 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8996 23:22:12.613432 best DQS0 dly(2T, 0.5T) = (1, 1)
8997 23:22:12.617008 best DQS1 dly(2T, 0.5T) = (1, 1)
8998 23:22:12.620412 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8999 23:22:12.623779 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9000 23:22:12.626794 Pre-setting of DQS Precalculation
9001 23:22:12.630271 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9002 23:22:12.636875 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9003 23:22:12.646992 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9004 23:22:12.647128
9005 23:22:12.647240
9006 23:22:12.650499 [Calibration Summary] 3200 Mbps
9007 23:22:12.650620 CH 0, Rank 0
9008 23:22:12.653548 SW Impedance : PASS
9009 23:22:12.653674 DUTY Scan : NO K
9010 23:22:12.657205 ZQ Calibration : PASS
9011 23:22:12.660411 Jitter Meter : NO K
9012 23:22:12.660538 CBT Training : PASS
9013 23:22:12.663648 Write leveling : PASS
9014 23:22:12.663731 RX DQS gating : PASS
9015 23:22:12.666738 RX DQ/DQS(RDDQC) : PASS
9016 23:22:12.670382 TX DQ/DQS : PASS
9017 23:22:12.670462 RX DATLAT : PASS
9018 23:22:12.673629 RX DQ/DQS(Engine): PASS
9019 23:22:12.676779 TX OE : PASS
9020 23:22:12.676866 All Pass.
9021 23:22:12.676966
9022 23:22:12.677055 CH 0, Rank 1
9023 23:22:12.680006 SW Impedance : PASS
9024 23:22:12.683301 DUTY Scan : NO K
9025 23:22:12.683428 ZQ Calibration : PASS
9026 23:22:12.686880 Jitter Meter : NO K
9027 23:22:12.689911 CBT Training : PASS
9028 23:22:12.690033 Write leveling : PASS
9029 23:22:12.693224 RX DQS gating : PASS
9030 23:22:12.696870 RX DQ/DQS(RDDQC) : PASS
9031 23:22:12.696985 TX DQ/DQS : PASS
9032 23:22:12.700103 RX DATLAT : PASS
9033 23:22:12.703423 RX DQ/DQS(Engine): PASS
9034 23:22:12.703534 TX OE : PASS
9035 23:22:12.706419 All Pass.
9036 23:22:12.706531
9037 23:22:12.706634 CH 1, Rank 0
9038 23:22:12.709830 SW Impedance : PASS
9039 23:22:12.709941 DUTY Scan : NO K
9040 23:22:12.713145 ZQ Calibration : PASS
9041 23:22:12.716405 Jitter Meter : NO K
9042 23:22:12.716494 CBT Training : PASS
9043 23:22:12.719671 Write leveling : PASS
9044 23:22:12.722911 RX DQS gating : PASS
9045 23:22:12.723019 RX DQ/DQS(RDDQC) : PASS
9046 23:22:12.726536 TX DQ/DQS : PASS
9047 23:22:12.729613 RX DATLAT : PASS
9048 23:22:12.729724 RX DQ/DQS(Engine): PASS
9049 23:22:12.732801 TX OE : PASS
9050 23:22:12.732918 All Pass.
9051 23:22:12.733015
9052 23:22:12.736136 CH 1, Rank 1
9053 23:22:12.736241 SW Impedance : PASS
9054 23:22:12.739739 DUTY Scan : NO K
9055 23:22:12.739852 ZQ Calibration : PASS
9056 23:22:12.742853 Jitter Meter : NO K
9057 23:22:12.746407 CBT Training : PASS
9058 23:22:12.746509 Write leveling : PASS
9059 23:22:12.749429 RX DQS gating : PASS
9060 23:22:12.752738 RX DQ/DQS(RDDQC) : PASS
9061 23:22:12.752850 TX DQ/DQS : PASS
9062 23:22:12.756334 RX DATLAT : PASS
9063 23:22:12.759327 RX DQ/DQS(Engine): PASS
9064 23:22:12.759454 TX OE : PASS
9065 23:22:12.762931 All Pass.
9066 23:22:12.763054
9067 23:22:12.763168 DramC Write-DBI on
9068 23:22:12.765973 PER_BANK_REFRESH: Hybrid Mode
9069 23:22:12.766097 TX_TRACKING: ON
9070 23:22:12.776080 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9071 23:22:12.786070 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9072 23:22:12.792517 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9073 23:22:12.796084 [FAST_K] Save calibration result to emmc
9074 23:22:12.799109 sync common calibartion params.
9075 23:22:12.799226 sync cbt_mode0:1, 1:1
9076 23:22:12.802852 dram_init: ddr_geometry: 2
9077 23:22:12.806125 dram_init: ddr_geometry: 2
9078 23:22:12.806239 dram_init: ddr_geometry: 2
9079 23:22:12.809318 0:dram_rank_size:100000000
9080 23:22:12.812616 1:dram_rank_size:100000000
9081 23:22:12.819157 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9082 23:22:12.819276 DFS_SHUFFLE_HW_MODE: ON
9083 23:22:12.822604 dramc_set_vcore_voltage set vcore to 725000
9084 23:22:12.825930 Read voltage for 1600, 0
9085 23:22:12.826021 Vio18 = 0
9086 23:22:12.829120 Vcore = 725000
9087 23:22:12.829208 Vdram = 0
9088 23:22:12.829269 Vddq = 0
9089 23:22:12.832795 Vmddr = 0
9090 23:22:12.832902 switch to 3200 Mbps bootup
9091 23:22:12.835940 [DramcRunTimeConfig]
9092 23:22:12.836115 PHYPLL
9093 23:22:12.839203 DPM_CONTROL_AFTERK: ON
9094 23:22:12.839305 PER_BANK_REFRESH: ON
9095 23:22:12.842428 REFRESH_OVERHEAD_REDUCTION: ON
9096 23:22:12.845991 CMD_PICG_NEW_MODE: OFF
9097 23:22:12.846070 XRTWTW_NEW_MODE: ON
9098 23:22:12.849549 XRTRTR_NEW_MODE: ON
9099 23:22:12.849661 TX_TRACKING: ON
9100 23:22:12.852799 RDSEL_TRACKING: OFF
9101 23:22:12.856082 DQS Precalculation for DVFS: ON
9102 23:22:12.856205 RX_TRACKING: OFF
9103 23:22:12.859352 HW_GATING DBG: ON
9104 23:22:12.859444 ZQCS_ENABLE_LP4: ON
9105 23:22:12.862305 RX_PICG_NEW_MODE: ON
9106 23:22:12.862416 TX_PICG_NEW_MODE: ON
9107 23:22:12.865842 ENABLE_RX_DCM_DPHY: ON
9108 23:22:12.869082 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9109 23:22:12.872388 DUMMY_READ_FOR_TRACKING: OFF
9110 23:22:12.872517 !!! SPM_CONTROL_AFTERK: OFF
9111 23:22:12.875815 !!! SPM could not control APHY
9112 23:22:12.879340 IMPEDANCE_TRACKING: ON
9113 23:22:12.879446 TEMP_SENSOR: ON
9114 23:22:12.882254 HW_SAVE_FOR_SR: OFF
9115 23:22:12.885770 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9116 23:22:12.888870 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9117 23:22:12.889008 Read ODT Tracking: ON
9118 23:22:12.892371 Refresh Rate DeBounce: ON
9119 23:22:12.895627 DFS_NO_QUEUE_FLUSH: ON
9120 23:22:12.899360 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9121 23:22:12.899481 ENABLE_DFS_RUNTIME_MRW: OFF
9122 23:22:12.902489 DDR_RESERVE_NEW_MODE: ON
9123 23:22:12.905554 MR_CBT_SWITCH_FREQ: ON
9124 23:22:12.905678 =========================
9125 23:22:12.926016 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9126 23:22:12.929216 dram_init: ddr_geometry: 2
9127 23:22:12.947417 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9128 23:22:12.951118 dram_init: dram init end (result: 0)
9129 23:22:12.957807 DRAM-K: Full calibration passed in 24431 msecs
9130 23:22:12.961138 MRC: failed to locate region type 0.
9131 23:22:12.961222 DRAM rank0 size:0x100000000,
9132 23:22:12.964417 DRAM rank1 size=0x100000000
9133 23:22:12.974183 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9134 23:22:12.981177 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9135 23:22:12.987577 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9136 23:22:12.994319 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9137 23:22:12.997222 DRAM rank0 size:0x100000000,
9138 23:22:13.000575 DRAM rank1 size=0x100000000
9139 23:22:13.000659 CBMEM:
9140 23:22:13.004193 IMD: root @ 0xfffff000 254 entries.
9141 23:22:13.007273 IMD: root @ 0xffffec00 62 entries.
9142 23:22:13.010818 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9143 23:22:13.014112 WARNING: RO_VPD is uninitialized or empty.
9144 23:22:13.020707 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9145 23:22:13.027510 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9146 23:22:13.040272 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9147 23:22:13.051913 BS: romstage times (exec / console): total (unknown) / 23965 ms
9148 23:22:13.052003
9149 23:22:13.052070
9150 23:22:13.061860 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9151 23:22:13.064715 ARM64: Exception handlers installed.
9152 23:22:13.068428 ARM64: Testing exception
9153 23:22:13.071484 ARM64: Done test exception
9154 23:22:13.071568 Enumerating buses...
9155 23:22:13.074835 Show all devs... Before device enumeration.
9156 23:22:13.078024 Root Device: enabled 1
9157 23:22:13.081505 CPU_CLUSTER: 0: enabled 1
9158 23:22:13.081609 CPU: 00: enabled 1
9159 23:22:13.084488 Compare with tree...
9160 23:22:13.084593 Root Device: enabled 1
9161 23:22:13.088377 CPU_CLUSTER: 0: enabled 1
9162 23:22:13.091529 CPU: 00: enabled 1
9163 23:22:13.091615 Root Device scanning...
9164 23:22:13.094821 scan_static_bus for Root Device
9165 23:22:13.097999 CPU_CLUSTER: 0 enabled
9166 23:22:13.101329 scan_static_bus for Root Device done
9167 23:22:13.104431 scan_bus: bus Root Device finished in 8 msecs
9168 23:22:13.104517 done
9169 23:22:13.111243 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9170 23:22:13.114591 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9171 23:22:13.120935 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9172 23:22:13.124203 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9173 23:22:13.127738 Allocating resources...
9174 23:22:13.131107 Reading resources...
9175 23:22:13.134269 Root Device read_resources bus 0 link: 0
9176 23:22:13.137783 DRAM rank0 size:0x100000000,
9177 23:22:13.137880 DRAM rank1 size=0x100000000
9178 23:22:13.140849 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9179 23:22:13.144236 CPU: 00 missing read_resources
9180 23:22:13.151124 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9181 23:22:13.154291 Root Device read_resources bus 0 link: 0 done
9182 23:22:13.154382 Done reading resources.
9183 23:22:13.160867 Show resources in subtree (Root Device)...After reading.
9184 23:22:13.164112 Root Device child on link 0 CPU_CLUSTER: 0
9185 23:22:13.167400 CPU_CLUSTER: 0 child on link 0 CPU: 00
9186 23:22:13.177690 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9187 23:22:13.177811 CPU: 00
9188 23:22:13.180928 Root Device assign_resources, bus 0 link: 0
9189 23:22:13.184186 CPU_CLUSTER: 0 missing set_resources
9190 23:22:13.190505 Root Device assign_resources, bus 0 link: 0 done
9191 23:22:13.190629 Done setting resources.
9192 23:22:13.197363 Show resources in subtree (Root Device)...After assigning values.
9193 23:22:13.200639 Root Device child on link 0 CPU_CLUSTER: 0
9194 23:22:13.204469 CPU_CLUSTER: 0 child on link 0 CPU: 00
9195 23:22:13.214164 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9196 23:22:13.214283 CPU: 00
9197 23:22:13.217387 Done allocating resources.
9198 23:22:13.223821 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9199 23:22:13.223913 Enabling resources...
9200 23:22:13.224011 done.
9201 23:22:13.230806 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9202 23:22:13.230913 Initializing devices...
9203 23:22:13.234163 Root Device init
9204 23:22:13.234246 init hardware done!
9205 23:22:13.237408 0x00000018: ctrlr->caps
9206 23:22:13.240438 52.000 MHz: ctrlr->f_max
9207 23:22:13.240548 0.400 MHz: ctrlr->f_min
9208 23:22:13.243748 0x40ff8080: ctrlr->voltages
9209 23:22:13.246912 sclk: 390625
9210 23:22:13.247016 Bus Width = 1
9211 23:22:13.247110 sclk: 390625
9212 23:22:13.250287 Bus Width = 1
9213 23:22:13.250385 Early init status = 3
9214 23:22:13.256923 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9215 23:22:13.260169 in-header: 03 fc 00 00 01 00 00 00
9216 23:22:13.260277 in-data: 00
9217 23:22:13.267189 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9218 23:22:13.270630 in-header: 03 fd 00 00 00 00 00 00
9219 23:22:13.273591 in-data:
9220 23:22:13.277004 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9221 23:22:13.280612 in-header: 03 fc 00 00 01 00 00 00
9222 23:22:13.283801 in-data: 00
9223 23:22:13.287100 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9224 23:22:13.291783 in-header: 03 fd 00 00 00 00 00 00
9225 23:22:13.295085 in-data:
9226 23:22:13.298238 [SSUSB] Setting up USB HOST controller...
9227 23:22:13.301791 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9228 23:22:13.305027 [SSUSB] phy power-on done.
9229 23:22:13.308506 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9230 23:22:13.314997 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9231 23:22:13.318304 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9232 23:22:13.325206 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9233 23:22:13.331397 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9234 23:22:13.338175 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9235 23:22:13.344605 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9236 23:22:13.351445 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9237 23:22:13.354655 SPM: binary array size = 0x9dc
9238 23:22:13.358053 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9239 23:22:13.364644 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9240 23:22:13.371585 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9241 23:22:13.374882 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9242 23:22:13.381324 configure_display: Starting display init
9243 23:22:13.414953 anx7625_power_on_init: Init interface.
9244 23:22:13.418082 anx7625_disable_pd_protocol: Disabled PD feature.
9245 23:22:13.421656 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9246 23:22:13.449297 anx7625_start_dp_work: Secure OCM version=00
9247 23:22:13.452905 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9248 23:22:13.467344 sp_tx_get_edid_block: EDID Block = 1
9249 23:22:13.569907 Extracted contents:
9250 23:22:13.573233 header: 00 ff ff ff ff ff ff 00
9251 23:22:13.576909 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9252 23:22:13.580151 version: 01 04
9253 23:22:13.583257 basic params: 95 1f 11 78 0a
9254 23:22:13.586848 chroma info: 76 90 94 55 54 90 27 21 50 54
9255 23:22:13.589930 established: 00 00 00
9256 23:22:13.596793 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9257 23:22:13.600014 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9258 23:22:13.606563 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9259 23:22:13.613286 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9260 23:22:13.619738 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9261 23:22:13.623228 extensions: 00
9262 23:22:13.623343 checksum: fb
9263 23:22:13.623459
9264 23:22:13.626638 Manufacturer: IVO Model 57d Serial Number 0
9265 23:22:13.629786 Made week 0 of 2020
9266 23:22:13.629904 EDID version: 1.4
9267 23:22:13.633313 Digital display
9268 23:22:13.636257 6 bits per primary color channel
9269 23:22:13.636380 DisplayPort interface
9270 23:22:13.639661 Maximum image size: 31 cm x 17 cm
9271 23:22:13.643058 Gamma: 220%
9272 23:22:13.643164 Check DPMS levels
9273 23:22:13.646235 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9274 23:22:13.649406 First detailed timing is preferred timing
9275 23:22:13.652985 Established timings supported:
9276 23:22:13.656212 Standard timings supported:
9277 23:22:13.659406 Detailed timings
9278 23:22:13.662648 Hex of detail: 383680a07038204018303c0035ae10000019
9279 23:22:13.666270 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9280 23:22:13.672656 0780 0798 07c8 0820 hborder 0
9281 23:22:13.675914 0438 043b 0447 0458 vborder 0
9282 23:22:13.679633 -hsync -vsync
9283 23:22:13.679765 Did detailed timing
9284 23:22:13.686113 Hex of detail: 000000000000000000000000000000000000
9285 23:22:13.686199 Manufacturer-specified data, tag 0
9286 23:22:13.692611 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9287 23:22:13.696317 ASCII string: InfoVision
9288 23:22:13.699486 Hex of detail: 000000fe00523134304e574635205248200a
9289 23:22:13.702633 ASCII string: R140NWF5 RH
9290 23:22:13.702716 Checksum
9291 23:22:13.702781 Checksum: 0xfb (valid)
9292 23:22:13.709326 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9293 23:22:13.712522 DSI data_rate: 832800000 bps
9294 23:22:13.719356 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9295 23:22:13.722663 anx7625_parse_edid: pixelclock(138800).
9296 23:22:13.726335 hactive(1920), hsync(48), hfp(24), hbp(88)
9297 23:22:13.729520 vactive(1080), vsync(12), vfp(3), vbp(17)
9298 23:22:13.732804 anx7625_dsi_config: config dsi.
9299 23:22:13.739142 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9300 23:22:13.751992 anx7625_dsi_config: success to config DSI
9301 23:22:13.755473 anx7625_dp_start: MIPI phy setup OK.
9302 23:22:13.758757 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9303 23:22:13.762201 mtk_ddp_mode_set invalid vrefresh 60
9304 23:22:13.765192 main_disp_path_setup
9305 23:22:13.765273 ovl_layer_smi_id_en
9306 23:22:13.768601 ovl_layer_smi_id_en
9307 23:22:13.768682 ccorr_config
9308 23:22:13.768745 aal_config
9309 23:22:13.771957 gamma_config
9310 23:22:13.772037 postmask_config
9311 23:22:13.775216 dither_config
9312 23:22:13.778600 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9313 23:22:13.785400 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9314 23:22:13.788462 Root Device init finished in 551 msecs
9315 23:22:13.792102 CPU_CLUSTER: 0 init
9316 23:22:13.798725 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9317 23:22:13.801812 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9318 23:22:13.805594 APU_MBOX 0x190000b0 = 0x10001
9319 23:22:13.808737 APU_MBOX 0x190001b0 = 0x10001
9320 23:22:13.811970 APU_MBOX 0x190005b0 = 0x10001
9321 23:22:13.815467 APU_MBOX 0x190006b0 = 0x10001
9322 23:22:13.818502 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9323 23:22:13.830983 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9324 23:22:13.843539 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9325 23:22:13.849979 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9326 23:22:13.861740 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9327 23:22:13.870999 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9328 23:22:13.874552 CPU_CLUSTER: 0 init finished in 81 msecs
9329 23:22:13.877758 Devices initialized
9330 23:22:13.880953 Show all devs... After init.
9331 23:22:13.881030 Root Device: enabled 1
9332 23:22:13.884147 CPU_CLUSTER: 0: enabled 1
9333 23:22:13.887569 CPU: 00: enabled 1
9334 23:22:13.890750 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9335 23:22:13.894003 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9336 23:22:13.897412 ELOG: NV offset 0x57f000 size 0x1000
9337 23:22:13.904436 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9338 23:22:13.910763 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9339 23:22:13.914037 ELOG: Event(17) added with size 13 at 2024-04-03 23:19:19 UTC
9340 23:22:13.917686 out: cmd=0x121: 03 db 21 01 00 00 00 00
9341 23:22:13.921369 in-header: 03 f8 00 00 2c 00 00 00
9342 23:22:13.934303 in-data: 67 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9343 23:22:13.941066 ELOG: Event(A1) added with size 10 at 2024-04-03 23:19:19 UTC
9344 23:22:13.947392 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9345 23:22:13.954224 ELOG: Event(A0) added with size 9 at 2024-04-03 23:19:19 UTC
9346 23:22:13.957133 elog_add_boot_reason: Logged dev mode boot
9347 23:22:13.960723 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9348 23:22:13.964127 Finalize devices...
9349 23:22:13.964259 Devices finalized
9350 23:22:13.970549 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9351 23:22:13.973778 Writing coreboot table at 0xffe64000
9352 23:22:13.977538 0. 000000000010a000-0000000000113fff: RAMSTAGE
9353 23:22:13.980721 1. 0000000040000000-00000000400fffff: RAM
9354 23:22:13.987229 2. 0000000040100000-000000004032afff: RAMSTAGE
9355 23:22:13.990483 3. 000000004032b000-00000000545fffff: RAM
9356 23:22:13.993774 4. 0000000054600000-000000005465ffff: BL31
9357 23:22:13.997032 5. 0000000054660000-00000000ffe63fff: RAM
9358 23:22:14.004053 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9359 23:22:14.007100 7. 0000000100000000-000000023fffffff: RAM
9360 23:22:14.007226 Passing 5 GPIOs to payload:
9361 23:22:14.013863 NAME | PORT | POLARITY | VALUE
9362 23:22:14.016898 EC in RW | 0x000000aa | low | undefined
9363 23:22:14.023632 EC interrupt | 0x00000005 | low | undefined
9364 23:22:14.026825 TPM interrupt | 0x000000ab | high | undefined
9365 23:22:14.033523 SD card detect | 0x00000011 | high | undefined
9366 23:22:14.036941 speaker enable | 0x00000093 | high | undefined
9367 23:22:14.040487 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9368 23:22:14.043572 in-header: 03 f9 00 00 02 00 00 00
9369 23:22:14.047037 in-data: 02 00
9370 23:22:14.047162 ADC[4]: Raw value=905096 ID=7
9371 23:22:14.050135 ADC[3]: Raw value=213441 ID=1
9372 23:22:14.053577 RAM Code: 0x71
9373 23:22:14.053661 ADC[6]: Raw value=75332 ID=0
9374 23:22:14.056886 ADC[5]: Raw value=213072 ID=1
9375 23:22:14.060138 SKU Code: 0x1
9376 23:22:14.063389 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 6fab
9377 23:22:14.066828 coreboot table: 964 bytes.
9378 23:22:14.070106 IMD ROOT 0. 0xfffff000 0x00001000
9379 23:22:14.073309 IMD SMALL 1. 0xffffe000 0x00001000
9380 23:22:14.076699 RO MCACHE 2. 0xffffc000 0x00001104
9381 23:22:14.080375 CONSOLE 3. 0xfff7c000 0x00080000
9382 23:22:14.083442 FMAP 4. 0xfff7b000 0x00000452
9383 23:22:14.086755 TIME STAMP 5. 0xfff7a000 0x00000910
9384 23:22:14.090294 VBOOT WORK 6. 0xfff66000 0x00014000
9385 23:22:14.093554 RAMOOPS 7. 0xffe66000 0x00100000
9386 23:22:14.096824 COREBOOT 8. 0xffe64000 0x00002000
9387 23:22:14.096906 IMD small region:
9388 23:22:14.100055 IMD ROOT 0. 0xffffec00 0x00000400
9389 23:22:14.103233 VPD 1. 0xffffeb80 0x0000006c
9390 23:22:14.106414 MMC STATUS 2. 0xffffeb60 0x00000004
9391 23:22:14.113333 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9392 23:22:14.116815 Probing TPM: done!
9393 23:22:14.120109 Connected to device vid:did:rid of 1ae0:0028:00
9394 23:22:14.130111 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9395 23:22:14.133556 Initialized TPM device CR50 revision 0
9396 23:22:14.136854 Checking cr50 for pending updates
9397 23:22:14.140708 Reading cr50 TPM mode
9398 23:22:14.149346 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9399 23:22:14.155892 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9400 23:22:14.195875 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9401 23:22:14.199282 Checking segment from ROM address 0x40100000
9402 23:22:14.202614 Checking segment from ROM address 0x4010001c
9403 23:22:14.209419 Loading segment from ROM address 0x40100000
9404 23:22:14.209506 code (compression=0)
9405 23:22:14.216022 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9406 23:22:14.226191 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9407 23:22:14.226279 it's not compressed!
9408 23:22:14.232645 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9409 23:22:14.235867 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9410 23:22:14.256466 Loading segment from ROM address 0x4010001c
9411 23:22:14.256591 Entry Point 0x80000000
9412 23:22:14.259589 Loaded segments
9413 23:22:14.262923 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9414 23:22:14.269684 Jumping to boot code at 0x80000000(0xffe64000)
9415 23:22:14.276544 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9416 23:22:14.283337 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9417 23:22:14.291136 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9418 23:22:14.294346 Checking segment from ROM address 0x40100000
9419 23:22:14.297603 Checking segment from ROM address 0x4010001c
9420 23:22:14.304486 Loading segment from ROM address 0x40100000
9421 23:22:14.304581 code (compression=1)
9422 23:22:14.311082 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9423 23:22:14.320860 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9424 23:22:14.320955 using LZMA
9425 23:22:14.329094 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9426 23:22:14.336176 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9427 23:22:14.339383 Loading segment from ROM address 0x4010001c
9428 23:22:14.339510 Entry Point 0x54601000
9429 23:22:14.342728 Loaded segments
9430 23:22:14.345987 NOTICE: MT8192 bl31_setup
9431 23:22:14.352801 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9432 23:22:14.356187 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9433 23:22:14.359689 WARNING: region 0:
9434 23:22:14.362916 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9435 23:22:14.363045 WARNING: region 1:
9436 23:22:14.369344 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9437 23:22:14.372652 WARNING: region 2:
9438 23:22:14.376139 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9439 23:22:14.379411 WARNING: region 3:
9440 23:22:14.382637 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9441 23:22:14.386381 WARNING: region 4:
9442 23:22:14.392660 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9443 23:22:14.392772 WARNING: region 5:
9444 23:22:14.396152 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9445 23:22:14.399576 WARNING: region 6:
9446 23:22:14.402846 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 23:22:14.406074 WARNING: region 7:
9448 23:22:14.409761 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 23:22:14.416321 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9450 23:22:14.419724 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9451 23:22:14.422778 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9452 23:22:14.429953 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9453 23:22:14.433202 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9454 23:22:14.436437 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9455 23:22:14.443094 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9456 23:22:14.446312 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9457 23:22:14.449901 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9458 23:22:14.456357 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9459 23:22:14.460010 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9460 23:22:14.463444 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9461 23:22:14.469886 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9462 23:22:14.473169 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9463 23:22:14.479910 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9464 23:22:14.483386 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9465 23:22:14.486567 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9466 23:22:14.493514 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9467 23:22:14.496962 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9468 23:22:14.499955 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9469 23:22:14.506614 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9470 23:22:14.510180 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9471 23:22:14.516731 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9472 23:22:14.520123 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9473 23:22:14.523677 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9474 23:22:14.530254 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9475 23:22:14.533622 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9476 23:22:14.536858 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9477 23:22:14.543858 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9478 23:22:14.547282 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9479 23:22:14.553671 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9480 23:22:14.556926 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9481 23:22:14.560121 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9482 23:22:14.567118 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9483 23:22:14.570169 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9484 23:22:14.573511 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9485 23:22:14.576880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9486 23:22:14.580167 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9487 23:22:14.587092 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9488 23:22:14.590130 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9489 23:22:14.593357 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9490 23:22:14.600136 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9491 23:22:14.603378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9492 23:22:14.607070 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9493 23:22:14.610284 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9494 23:22:14.616607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9495 23:22:14.619955 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9496 23:22:14.623620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9497 23:22:14.630096 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9498 23:22:14.633553 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9499 23:22:14.636724 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9500 23:22:14.643566 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9501 23:22:14.646671 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9502 23:22:14.653577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9503 23:22:14.656838 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9504 23:22:14.660151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9505 23:22:14.667014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9506 23:22:14.670341 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9507 23:22:14.676769 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9508 23:22:14.680198 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9509 23:22:14.686665 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9510 23:22:14.690335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9511 23:22:14.696835 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9512 23:22:14.700254 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9513 23:22:14.703393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9514 23:22:14.710137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9515 23:22:14.713773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9516 23:22:14.720128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9517 23:22:14.723784 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9518 23:22:14.730354 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9519 23:22:14.733486 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9520 23:22:14.736687 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9521 23:22:14.743420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9522 23:22:14.746627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9523 23:22:14.753595 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9524 23:22:14.757054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9525 23:22:14.763651 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9526 23:22:14.766692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9527 23:22:14.770195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9528 23:22:14.776704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9529 23:22:14.780020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9530 23:22:14.787002 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9531 23:22:14.790070 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9532 23:22:14.796643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9533 23:22:14.799975 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9534 23:22:14.803523 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9535 23:22:14.809984 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9536 23:22:14.813399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9537 23:22:14.820399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9538 23:22:14.823544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9539 23:22:14.830619 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9540 23:22:14.833749 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9541 23:22:14.837145 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9542 23:22:14.843737 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9543 23:22:14.847447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9544 23:22:14.853869 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9545 23:22:14.857109 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9546 23:22:14.860361 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9547 23:22:14.863672 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9548 23:22:14.870249 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9549 23:22:14.873520 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9550 23:22:14.877295 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9551 23:22:14.883624 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9552 23:22:14.887137 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9553 23:22:14.893484 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9554 23:22:14.897205 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9555 23:22:14.900392 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9556 23:22:14.906814 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9557 23:22:14.910362 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9558 23:22:14.917143 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9559 23:22:14.920216 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9560 23:22:14.923457 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9561 23:22:14.930423 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9562 23:22:14.933545 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9563 23:22:14.940441 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9564 23:22:14.943533 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9565 23:22:14.947150 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9566 23:22:14.950377 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9567 23:22:14.957154 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9568 23:22:14.960587 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9569 23:22:14.963737 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9570 23:22:14.966838 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9571 23:22:14.973891 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9572 23:22:14.977233 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9573 23:22:14.980453 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9574 23:22:14.987164 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9575 23:22:14.990362 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9576 23:22:14.996898 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9577 23:22:15.000530 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9578 23:22:15.003742 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9579 23:22:15.010492 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9580 23:22:15.013853 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9581 23:22:15.017029 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9582 23:22:15.023912 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9583 23:22:15.027212 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9584 23:22:15.033654 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9585 23:22:15.036970 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9586 23:22:15.040568 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9587 23:22:15.046991 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9588 23:22:15.050571 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9589 23:22:15.057190 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9590 23:22:15.060387 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9591 23:22:15.063661 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9592 23:22:15.070391 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9593 23:22:15.074053 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9594 23:22:15.077262 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9595 23:22:15.083773 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9596 23:22:15.087164 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9597 23:22:15.094095 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9598 23:22:15.097409 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9599 23:22:15.100609 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9600 23:22:15.107493 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9601 23:22:15.110801 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9602 23:22:15.114055 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9603 23:22:15.120885 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9604 23:22:15.124121 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9605 23:22:15.130814 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9606 23:22:15.133968 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9607 23:22:15.137406 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9608 23:22:15.144128 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9609 23:22:15.147317 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9610 23:22:15.154171 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9611 23:22:15.157161 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9612 23:22:15.160383 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9613 23:22:15.167263 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9614 23:22:15.170377 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9615 23:22:15.173802 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9616 23:22:15.180630 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9617 23:22:15.183878 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9618 23:22:15.190471 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9619 23:22:15.194096 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9620 23:22:15.197270 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9621 23:22:15.203860 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9622 23:22:15.207286 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9623 23:22:15.213748 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9624 23:22:15.216991 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9625 23:22:15.220679 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9626 23:22:15.227322 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9627 23:22:15.230466 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9628 23:22:15.236839 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9629 23:22:15.240184 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9630 23:22:15.243751 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9631 23:22:15.250121 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9632 23:22:15.253426 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9633 23:22:15.260397 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9634 23:22:15.263574 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9635 23:22:15.266681 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9636 23:22:15.273496 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9637 23:22:15.276783 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9638 23:22:15.283384 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9639 23:22:15.287171 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9640 23:22:15.290277 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9641 23:22:15.296849 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9642 23:22:15.300155 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9643 23:22:15.306479 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9644 23:22:15.309827 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9645 23:22:15.313438 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9646 23:22:15.319932 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9647 23:22:15.323258 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9648 23:22:15.329816 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9649 23:22:15.333449 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9650 23:22:15.339971 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9651 23:22:15.343131 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9652 23:22:15.346718 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9653 23:22:15.353226 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9654 23:22:15.356506 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9655 23:22:15.362983 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9656 23:22:15.366323 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9657 23:22:15.369776 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9658 23:22:15.376208 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9659 23:22:15.379397 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9660 23:22:15.385945 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9661 23:22:15.389672 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9662 23:22:15.396119 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9663 23:22:15.399578 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9664 23:22:15.402794 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9665 23:22:15.409329 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9666 23:22:15.412444 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9667 23:22:15.419339 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9668 23:22:15.422512 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9669 23:22:15.429288 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9670 23:22:15.432539 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9671 23:22:15.435948 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9672 23:22:15.442482 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9673 23:22:15.445609 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9674 23:22:15.452221 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9675 23:22:15.455627 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9676 23:22:15.462602 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9677 23:22:15.465601 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9678 23:22:15.469355 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9679 23:22:15.472469 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9680 23:22:15.479136 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9681 23:22:15.482332 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9682 23:22:15.486053 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9683 23:22:15.489276 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9684 23:22:15.495938 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9685 23:22:15.499225 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9686 23:22:15.505601 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9687 23:22:15.509290 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9688 23:22:15.512521 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9689 23:22:15.518720 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9690 23:22:15.522209 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9691 23:22:15.525605 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9692 23:22:15.532204 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9693 23:22:15.535697 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9694 23:22:15.538843 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9695 23:22:15.545769 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9696 23:22:15.548721 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9697 23:22:15.552113 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9698 23:22:15.559011 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9699 23:22:15.562243 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9700 23:22:15.568432 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9701 23:22:15.571866 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9702 23:22:15.575410 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9703 23:22:15.582261 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9704 23:22:15.585479 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9705 23:22:15.588781 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9706 23:22:15.595106 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9707 23:22:15.598687 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9708 23:22:15.605236 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9709 23:22:15.608460 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9710 23:22:15.611895 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9711 23:22:15.618340 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9712 23:22:15.621961 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9713 23:22:15.625139 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9714 23:22:15.631659 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9715 23:22:15.634888 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9716 23:22:15.641799 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9717 23:22:15.644803 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9718 23:22:15.648005 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9719 23:22:15.651762 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9720 23:22:15.654933 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9721 23:22:15.661589 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9722 23:22:15.664763 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9723 23:22:15.668354 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9724 23:22:15.671635 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9725 23:22:15.678207 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9726 23:22:15.681333 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9727 23:22:15.684858 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9728 23:22:15.688240 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9729 23:22:15.694739 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9730 23:22:15.698200 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9731 23:22:15.701225 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9732 23:22:15.707955 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9733 23:22:15.711342 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9734 23:22:15.717878 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9735 23:22:15.721377 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9736 23:22:15.727792 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9737 23:22:15.731347 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9738 23:22:15.734676 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9739 23:22:15.741285 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9740 23:22:15.744489 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9741 23:22:15.750842 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9742 23:22:15.754092 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9743 23:22:15.757753 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9744 23:22:15.764276 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9745 23:22:15.767616 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9746 23:22:15.774038 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9747 23:22:15.777322 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9748 23:22:15.780946 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9749 23:22:15.787331 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9750 23:22:15.790601 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9751 23:22:15.797339 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9752 23:22:15.800475 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9753 23:22:15.807280 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9754 23:22:15.810340 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9755 23:22:15.813739 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9756 23:22:15.820294 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9757 23:22:15.823817 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9758 23:22:15.830296 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9759 23:22:15.833711 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9760 23:22:15.837087 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9761 23:22:15.843777 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9762 23:22:15.846910 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9763 23:22:15.853835 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9764 23:22:15.857295 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9765 23:22:15.860198 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9766 23:22:15.866939 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9767 23:22:15.870246 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9768 23:22:15.877122 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9769 23:22:15.880381 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9770 23:22:15.883594 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9771 23:22:15.890416 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9772 23:22:15.893494 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9773 23:22:15.900404 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9774 23:22:15.903534 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9775 23:22:15.909906 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9776 23:22:15.913578 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9777 23:22:15.916663 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9778 23:22:15.923520 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9779 23:22:15.926843 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9780 23:22:15.933336 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9781 23:22:15.936821 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9782 23:22:15.939829 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9783 23:22:15.946526 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9784 23:22:15.950170 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9785 23:22:15.956528 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9786 23:22:15.959950 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9787 23:22:15.963152 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9788 23:22:15.969533 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9789 23:22:15.973004 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9790 23:22:15.979739 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9791 23:22:15.982872 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9792 23:22:15.989837 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9793 23:22:15.993139 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9794 23:22:15.996671 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9795 23:22:16.003473 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9796 23:22:16.006678 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9797 23:22:16.009794 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9798 23:22:16.016203 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9799 23:22:16.019988 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9800 23:22:16.026350 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9801 23:22:16.029561 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9802 23:22:16.036280 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9803 23:22:16.039232 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9804 23:22:16.042534 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9805 23:22:16.049308 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9806 23:22:16.052366 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9807 23:22:16.059431 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9808 23:22:16.062615 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9809 23:22:16.069031 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9810 23:22:16.072257 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9811 23:22:16.079112 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9812 23:22:16.082230 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9813 23:22:16.085575 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9814 23:22:16.092408 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9815 23:22:16.095357 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9816 23:22:16.102354 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9817 23:22:16.105715 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9818 23:22:16.112395 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9819 23:22:16.115655 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9820 23:22:16.118902 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9821 23:22:16.125675 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9822 23:22:16.128829 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9823 23:22:16.135318 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9824 23:22:16.138917 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9825 23:22:16.145358 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9826 23:22:16.148685 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9827 23:22:16.151953 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9828 23:22:16.158936 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9829 23:22:16.162211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9830 23:22:16.168626 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9831 23:22:16.171825 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9832 23:22:16.178651 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9833 23:22:16.181902 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9834 23:22:16.185223 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9835 23:22:16.191681 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9836 23:22:16.195257 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9837 23:22:16.202165 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9838 23:22:16.205097 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9839 23:22:16.211588 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9840 23:22:16.215111 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9841 23:22:16.221930 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9842 23:22:16.224943 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9843 23:22:16.228171 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9844 23:22:16.234772 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9845 23:22:16.238382 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9846 23:22:16.244825 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9847 23:22:16.248029 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9848 23:22:16.254810 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9849 23:22:16.258334 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9850 23:22:16.264887 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9851 23:22:16.268199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9852 23:22:16.271231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9853 23:22:16.277680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9854 23:22:16.281451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9855 23:22:16.287907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9856 23:22:16.291207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9857 23:22:16.297696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9858 23:22:16.300911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9859 23:22:16.307821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9860 23:22:16.311127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9861 23:22:16.317692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9862 23:22:16.321055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9863 23:22:16.327695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9864 23:22:16.330751 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9865 23:22:16.337393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9866 23:22:16.340782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9867 23:22:16.347669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9868 23:22:16.350851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9869 23:22:16.354357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9870 23:22:16.360950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9871 23:22:16.364143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9872 23:22:16.370892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9873 23:22:16.374099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9874 23:22:16.380901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9875 23:22:16.387345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9876 23:22:16.390618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9877 23:22:16.394275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9878 23:22:16.400768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9879 23:22:16.407307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9880 23:22:16.410457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9881 23:22:16.416917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9882 23:22:16.420260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9883 23:22:16.423799 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9884 23:22:16.426988 INFO: [APUAPC] vio 0
9885 23:22:16.430202 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9886 23:22:16.437221 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9887 23:22:16.440696 INFO: [APUAPC] D0_APC_0: 0x400510
9888 23:22:16.443908 INFO: [APUAPC] D0_APC_1: 0x0
9889 23:22:16.447096 INFO: [APUAPC] D0_APC_2: 0x1540
9890 23:22:16.447179 INFO: [APUAPC] D0_APC_3: 0x0
9891 23:22:16.450750 INFO: [APUAPC] D1_APC_0: 0xffffffff
9892 23:22:16.453859 INFO: [APUAPC] D1_APC_1: 0xffffffff
9893 23:22:16.457320 INFO: [APUAPC] D1_APC_2: 0x3fffff
9894 23:22:16.460712 INFO: [APUAPC] D1_APC_3: 0x0
9895 23:22:16.463636 INFO: [APUAPC] D2_APC_0: 0xffffffff
9896 23:22:16.466983 INFO: [APUAPC] D2_APC_1: 0xffffffff
9897 23:22:16.470371 INFO: [APUAPC] D2_APC_2: 0x3fffff
9898 23:22:16.473983 INFO: [APUAPC] D2_APC_3: 0x0
9899 23:22:16.477250 INFO: [APUAPC] D3_APC_0: 0xffffffff
9900 23:22:16.480587 INFO: [APUAPC] D3_APC_1: 0xffffffff
9901 23:22:16.483714 INFO: [APUAPC] D3_APC_2: 0x3fffff
9902 23:22:16.487153 INFO: [APUAPC] D3_APC_3: 0x0
9903 23:22:16.490498 INFO: [APUAPC] D4_APC_0: 0xffffffff
9904 23:22:16.493877 INFO: [APUAPC] D4_APC_1: 0xffffffff
9905 23:22:16.497344 INFO: [APUAPC] D4_APC_2: 0x3fffff
9906 23:22:16.500660 INFO: [APUAPC] D4_APC_3: 0x0
9907 23:22:16.503946 INFO: [APUAPC] D5_APC_0: 0xffffffff
9908 23:22:16.507264 INFO: [APUAPC] D5_APC_1: 0xffffffff
9909 23:22:16.510456 INFO: [APUAPC] D5_APC_2: 0x3fffff
9910 23:22:16.513639 INFO: [APUAPC] D5_APC_3: 0x0
9911 23:22:16.517307 INFO: [APUAPC] D6_APC_0: 0xffffffff
9912 23:22:16.520515 INFO: [APUAPC] D6_APC_1: 0xffffffff
9913 23:22:16.523795 INFO: [APUAPC] D6_APC_2: 0x3fffff
9914 23:22:16.526858 INFO: [APUAPC] D6_APC_3: 0x0
9915 23:22:16.530196 INFO: [APUAPC] D7_APC_0: 0xffffffff
9916 23:22:16.533713 INFO: [APUAPC] D7_APC_1: 0xffffffff
9917 23:22:16.536799 INFO: [APUAPC] D7_APC_2: 0x3fffff
9918 23:22:16.540045 INFO: [APUAPC] D7_APC_3: 0x0
9919 23:22:16.543150 INFO: [APUAPC] D8_APC_0: 0xffffffff
9920 23:22:16.546534 INFO: [APUAPC] D8_APC_1: 0xffffffff
9921 23:22:16.549976 INFO: [APUAPC] D8_APC_2: 0x3fffff
9922 23:22:16.553345 INFO: [APUAPC] D8_APC_3: 0x0
9923 23:22:16.556446 INFO: [APUAPC] D9_APC_0: 0xffffffff
9924 23:22:16.559690 INFO: [APUAPC] D9_APC_1: 0xffffffff
9925 23:22:16.563297 INFO: [APUAPC] D9_APC_2: 0x3fffff
9926 23:22:16.566305 INFO: [APUAPC] D9_APC_3: 0x0
9927 23:22:16.569948 INFO: [APUAPC] D10_APC_0: 0xffffffff
9928 23:22:16.572939 INFO: [APUAPC] D10_APC_1: 0xffffffff
9929 23:22:16.576308 INFO: [APUAPC] D10_APC_2: 0x3fffff
9930 23:22:16.579714 INFO: [APUAPC] D10_APC_3: 0x0
9931 23:22:16.583038 INFO: [APUAPC] D11_APC_0: 0xffffffff
9932 23:22:16.586269 INFO: [APUAPC] D11_APC_1: 0xffffffff
9933 23:22:16.589362 INFO: [APUAPC] D11_APC_2: 0x3fffff
9934 23:22:16.592860 INFO: [APUAPC] D11_APC_3: 0x0
9935 23:22:16.596340 INFO: [APUAPC] D12_APC_0: 0xffffffff
9936 23:22:16.599352 INFO: [APUAPC] D12_APC_1: 0xffffffff
9937 23:22:16.602760 INFO: [APUAPC] D12_APC_2: 0x3fffff
9938 23:22:16.605934 INFO: [APUAPC] D12_APC_3: 0x0
9939 23:22:16.609422 INFO: [APUAPC] D13_APC_0: 0xffffffff
9940 23:22:16.612762 INFO: [APUAPC] D13_APC_1: 0xffffffff
9941 23:22:16.615967 INFO: [APUAPC] D13_APC_2: 0x3fffff
9942 23:22:16.619667 INFO: [APUAPC] D13_APC_3: 0x0
9943 23:22:16.622843 INFO: [APUAPC] D14_APC_0: 0xffffffff
9944 23:22:16.626087 INFO: [APUAPC] D14_APC_1: 0xffffffff
9945 23:22:16.629333 INFO: [APUAPC] D14_APC_2: 0x3fffff
9946 23:22:16.632626 INFO: [APUAPC] D14_APC_3: 0x0
9947 23:22:16.636263 INFO: [APUAPC] D15_APC_0: 0xffffffff
9948 23:22:16.639420 INFO: [APUAPC] D15_APC_1: 0xffffffff
9949 23:22:16.642921 INFO: [APUAPC] D15_APC_2: 0x3fffff
9950 23:22:16.646194 INFO: [APUAPC] D15_APC_3: 0x0
9951 23:22:16.649571 INFO: [APUAPC] APC_CON: 0x4
9952 23:22:16.652801 INFO: [NOCDAPC] D0_APC_0: 0x0
9953 23:22:16.656032 INFO: [NOCDAPC] D0_APC_1: 0x0
9954 23:22:16.656148 INFO: [NOCDAPC] D1_APC_0: 0x0
9955 23:22:16.659216 INFO: [NOCDAPC] D1_APC_1: 0xfff
9956 23:22:16.662528 INFO: [NOCDAPC] D2_APC_0: 0x0
9957 23:22:16.665991 INFO: [NOCDAPC] D2_APC_1: 0xfff
9958 23:22:16.669346 INFO: [NOCDAPC] D3_APC_0: 0x0
9959 23:22:16.672847 INFO: [NOCDAPC] D3_APC_1: 0xfff
9960 23:22:16.675946 INFO: [NOCDAPC] D4_APC_0: 0x0
9961 23:22:16.679406 INFO: [NOCDAPC] D4_APC_1: 0xfff
9962 23:22:16.682683 INFO: [NOCDAPC] D5_APC_0: 0x0
9963 23:22:16.685776 INFO: [NOCDAPC] D5_APC_1: 0xfff
9964 23:22:16.685861 INFO: [NOCDAPC] D6_APC_0: 0x0
9965 23:22:16.689374 INFO: [NOCDAPC] D6_APC_1: 0xfff
9966 23:22:16.692415 INFO: [NOCDAPC] D7_APC_0: 0x0
9967 23:22:16.695748 INFO: [NOCDAPC] D7_APC_1: 0xfff
9968 23:22:16.699136 INFO: [NOCDAPC] D8_APC_0: 0x0
9969 23:22:16.702347 INFO: [NOCDAPC] D8_APC_1: 0xfff
9970 23:22:16.705859 INFO: [NOCDAPC] D9_APC_0: 0x0
9971 23:22:16.709144 INFO: [NOCDAPC] D9_APC_1: 0xfff
9972 23:22:16.712502 INFO: [NOCDAPC] D10_APC_0: 0x0
9973 23:22:16.715761 INFO: [NOCDAPC] D10_APC_1: 0xfff
9974 23:22:16.719118 INFO: [NOCDAPC] D11_APC_0: 0x0
9975 23:22:16.722767 INFO: [NOCDAPC] D11_APC_1: 0xfff
9976 23:22:16.722900 INFO: [NOCDAPC] D12_APC_0: 0x0
9977 23:22:16.726006 INFO: [NOCDAPC] D12_APC_1: 0xfff
9978 23:22:16.729273 INFO: [NOCDAPC] D13_APC_0: 0x0
9979 23:22:16.732937 INFO: [NOCDAPC] D13_APC_1: 0xfff
9980 23:22:16.736232 INFO: [NOCDAPC] D14_APC_0: 0x0
9981 23:22:16.739469 INFO: [NOCDAPC] D14_APC_1: 0xfff
9982 23:22:16.742566 INFO: [NOCDAPC] D15_APC_0: 0x0
9983 23:22:16.745994 INFO: [NOCDAPC] D15_APC_1: 0xfff
9984 23:22:16.749184 INFO: [NOCDAPC] APC_CON: 0x4
9985 23:22:16.752714 INFO: [APUAPC] set_apusys_apc done
9986 23:22:16.755912 INFO: [DEVAPC] devapc_init done
9987 23:22:16.759155 INFO: GICv3 without legacy support detected.
9988 23:22:16.762318 INFO: ARM GICv3 driver initialized in EL3
9989 23:22:16.765854 INFO: Maximum SPI INTID supported: 639
9990 23:22:16.772258 INFO: BL31: Initializing runtime services
9991 23:22:16.775638 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9992 23:22:16.779309 INFO: SPM: enable CPC mode
9993 23:22:16.785791 INFO: mcdi ready for mcusys-off-idle and system suspend
9994 23:22:16.789086 INFO: BL31: Preparing for EL3 exit to normal world
9995 23:22:16.792340 INFO: Entry point address = 0x80000000
9996 23:22:16.795451 INFO: SPSR = 0x8
9997 23:22:16.800965
9998 23:22:16.801076
9999 23:22:16.801183
10000 23:22:16.804054 Starting depthcharge on Spherion...
10001 23:22:16.804162
10002 23:22:16.804266 Wipe memory regions:
10003 23:22:16.804373
10004 23:22:16.805313 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10005 23:22:16.805452 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10006 23:22:16.805572 Setting prompt string to ['asurada:']
10007 23:22:16.805681 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10008 23:22:16.807623 [0x00000040000000, 0x00000054600000)
10009 23:22:16.929596
10010 23:22:16.929811 [0x00000054660000, 0x00000080000000)
10011 23:22:17.190275
10012 23:22:17.190445 [0x000000821a7280, 0x000000ffe64000)
10013 23:22:17.934900
10014 23:22:17.935048 [0x00000100000000, 0x00000240000000)
10015 23:22:19.823465
10016 23:22:19.826751 Initializing XHCI USB controller at 0x11200000.
10017 23:22:20.864894
10018 23:22:20.868124 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10019 23:22:20.868237
10020 23:22:20.868346
10021 23:22:20.868410
10022 23:22:20.868697 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10024 23:22:20.968998 asurada: tftpboot 192.168.201.1 13248400/tftp-deploy-netd99_i/kernel/image.itb 13248400/tftp-deploy-netd99_i/kernel/cmdline
10025 23:22:20.969140 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10026 23:22:20.969232 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10027 23:22:20.973525 tftpboot 192.168.201.1 13248400/tftp-deploy-netd99_i/kernel/image.itp-deploy-netd99_i/kernel/cmdline
10028 23:22:20.973623
10029 23:22:20.973690 Waiting for link
10030 23:22:21.133817
10031 23:22:21.133951 R8152: Initializing
10032 23:22:21.134038
10033 23:22:21.137140 Version 9 (ocp_data = 6010)
10034 23:22:21.137261
10035 23:22:21.140276 R8152: Done initializing
10036 23:22:21.140413
10037 23:22:21.140537 Adding net device
10038 23:22:23.013424
10039 23:22:23.013635 done.
10040 23:22:23.013757
10041 23:22:23.013880 MAC: 00:e0:4c:78:7a:aa
10042 23:22:23.013990
10043 23:22:23.016623 Sending DHCP discover... done.
10044 23:22:23.016750
10045 23:22:26.716520 Waiting for reply... done.
10046 23:22:26.716734
10047 23:22:26.716873 Sending DHCP request... done.
10048 23:22:26.719777
10049 23:22:26.719857 Waiting for reply... done.
10050 23:22:26.719922
10051 23:22:26.723458 My ip is 192.168.201.12
10052 23:22:26.723541
10053 23:22:26.726640 The DHCP server ip is 192.168.201.1
10054 23:22:26.726722
10055 23:22:26.729861 TFTP server IP predefined by user: 192.168.201.1
10056 23:22:26.729935
10057 23:22:26.736355 Bootfile predefined by user: 13248400/tftp-deploy-netd99_i/kernel/image.itb
10058 23:22:26.736446
10059 23:22:26.739982 Sending tftp read request... done.
10060 23:22:26.740058
10061 23:22:26.742831 Waiting for the transfer...
10062 23:22:26.742921
10063 23:22:26.992178 00000000 ################################################################
10064 23:22:26.992377
10065 23:22:27.230791 00080000 ################################################################
10066 23:22:27.230987
10067 23:22:27.473217 00100000 ################################################################
10068 23:22:27.473362
10069 23:22:27.719729 00180000 ################################################################
10070 23:22:27.719883
10071 23:22:27.967017 00200000 ################################################################
10072 23:22:27.967159
10073 23:22:28.218283 00280000 ################################################################
10074 23:22:28.218451
10075 23:22:28.475905 00300000 ################################################################
10076 23:22:28.476040
10077 23:22:28.732835 00380000 ################################################################
10078 23:22:28.732971
10079 23:22:28.986204 00400000 ################################################################
10080 23:22:28.986367
10081 23:22:29.236397 00480000 ################################################################
10082 23:22:29.236578
10083 23:22:29.487442 00500000 ################################################################
10084 23:22:29.487587
10085 23:22:29.737774 00580000 ################################################################
10086 23:22:29.737944
10087 23:22:29.988772 00600000 ################################################################
10088 23:22:29.988904
10089 23:22:30.241576 00680000 ################################################################
10090 23:22:30.241735
10091 23:22:30.489388 00700000 ################################################################
10092 23:22:30.489522
10093 23:22:30.734950 00780000 ################################################################
10094 23:22:30.735089
10095 23:22:30.988270 00800000 ################################################################
10096 23:22:30.988408
10097 23:22:31.241517 00880000 ################################################################
10098 23:22:31.241649
10099 23:22:31.503817 00900000 ################################################################
10100 23:22:31.503954
10101 23:22:31.762901 00980000 ################################################################
10102 23:22:31.763042
10103 23:22:32.019314 00a00000 ################################################################
10104 23:22:32.019511
10105 23:22:32.272261 00a80000 ################################################################
10106 23:22:32.272407
10107 23:22:32.524733 00b00000 ################################################################
10108 23:22:32.524915
10109 23:22:32.775304 00b80000 ################################################################
10110 23:22:32.775465
10111 23:22:33.029949 00c00000 ################################################################
10112 23:22:33.030085
10113 23:22:33.280505 00c80000 ################################################################
10114 23:22:33.280646
10115 23:22:33.533938 00d00000 ################################################################
10116 23:22:33.534118
10117 23:22:33.781923 00d80000 ################################################################
10118 23:22:33.782056
10119 23:22:34.037418 00e00000 ################################################################
10120 23:22:34.037584
10121 23:22:34.291796 00e80000 ################################################################
10122 23:22:34.291963
10123 23:22:34.545121 00f00000 ################################################################
10124 23:22:34.545311
10125 23:22:34.803183 00f80000 ################################################################
10126 23:22:34.803313
10127 23:22:35.061112 01000000 ################################################################
10128 23:22:35.061244
10129 23:22:35.311751 01080000 ################################################################
10130 23:22:35.311912
10131 23:22:35.570993 01100000 ################################################################
10132 23:22:35.571188
10133 23:22:35.825615 01180000 ################################################################
10134 23:22:35.825825
10135 23:22:36.088303 01200000 ################################################################
10136 23:22:36.088436
10137 23:22:36.363504 01280000 ################################################################
10138 23:22:36.363660
10139 23:22:36.627998 01300000 ################################################################
10140 23:22:36.628189
10141 23:22:36.877501 01380000 ################################################################
10142 23:22:36.877661
10143 23:22:37.132308 01400000 ################################################################
10144 23:22:37.132512
10145 23:22:37.392727 01480000 ################################################################
10146 23:22:37.392858
10147 23:22:37.654785 01500000 ################################################################
10148 23:22:37.654938
10149 23:22:37.922061 01580000 ################################################################
10150 23:22:37.922204
10151 23:22:38.184590 01600000 ################################################################
10152 23:22:38.184794
10153 23:22:38.464500 01680000 ################################################################
10154 23:22:38.464658
10155 23:22:38.764882 01700000 ################################################################
10156 23:22:38.765089
10157 23:22:39.026435 01780000 ################################################################
10158 23:22:39.026585
10159 23:22:39.288493 01800000 ################################################################
10160 23:22:39.288705
10161 23:22:39.540220 01880000 ################################################################
10162 23:22:39.540443
10163 23:22:39.791215 01900000 ################################################################
10164 23:22:39.791422
10165 23:22:40.043459 01980000 ################################################################
10166 23:22:40.043608
10167 23:22:40.301705 01a00000 ################################################################
10168 23:22:40.301885
10169 23:22:40.558034 01a80000 ################################################################
10170 23:22:40.558242
10171 23:22:40.816299 01b00000 ################################################################
10172 23:22:40.816457
10173 23:22:41.089520 01b80000 ################################################################
10174 23:22:41.089671
10175 23:22:41.340044 01c00000 ################################################################
10176 23:22:41.340218
10177 23:22:41.588483 01c80000 ################################################################
10178 23:22:41.588659
10179 23:22:41.834905 01d00000 ################################################################
10180 23:22:41.835053
10181 23:22:42.084143 01d80000 ################################################################
10182 23:22:42.084308
10183 23:22:42.334153 01e00000 ################################################################
10184 23:22:42.334299
10185 23:22:42.605065 01e80000 ################################################################
10186 23:22:42.605285
10187 23:22:42.868734 01f00000 ################################################################
10188 23:22:42.868951
10189 23:22:43.119710 01f80000 ################################################################
10190 23:22:43.119888
10191 23:22:43.375659 02000000 ################################################################
10192 23:22:43.375810
10193 23:22:43.626559 02080000 ################################################################
10194 23:22:43.626697
10195 23:22:43.875311 02100000 ################################################################
10196 23:22:43.875459
10197 23:22:44.125311 02180000 ################################################################
10198 23:22:44.125455
10199 23:22:44.378187 02200000 ################################################################
10200 23:22:44.378370
10201 23:22:44.640074 02280000 ################################################################
10202 23:22:44.640222
10203 23:22:44.902387 02300000 ################################################################
10204 23:22:44.902564
10205 23:22:45.173187 02380000 ################################################################
10206 23:22:45.173347
10207 23:22:45.451372 02400000 ################################################################
10208 23:22:45.451536
10209 23:22:45.723162 02480000 ################################################################
10210 23:22:45.723333
10211 23:22:45.973619 02500000 ################################################################
10212 23:22:45.973753
10213 23:22:46.233960 02580000 ################################################################
10214 23:22:46.234100
10215 23:22:46.506659 02600000 ################################################################
10216 23:22:46.506801
10217 23:22:46.788824 02680000 ################################################################
10218 23:22:46.789027
10219 23:22:47.061143 02700000 ################################################################
10220 23:22:47.061334
10221 23:22:47.335829 02780000 ################################################################
10222 23:22:47.336050
10223 23:22:47.602510 02800000 ################################################################
10224 23:22:47.602648
10225 23:22:47.870197 02880000 ################################################################
10226 23:22:47.870341
10227 23:22:48.133322 02900000 ################################################################
10228 23:22:48.133525
10229 23:22:48.397793 02980000 ################################################################
10230 23:22:48.397941
10231 23:22:48.673485 02a00000 ################################################################
10232 23:22:48.673682
10233 23:22:48.930651 02a80000 ################################################################
10234 23:22:48.930797
10235 23:22:49.187707 02b00000 ################################################################
10236 23:22:49.187927
10237 23:22:49.451846 02b80000 ################################################################
10238 23:22:49.452003
10239 23:22:49.709742 02c00000 ################################################################
10240 23:22:49.709884
10241 23:22:49.969924 02c80000 ################################################################
10242 23:22:49.970059
10243 23:22:50.233346 02d00000 ################################################################
10244 23:22:50.233498
10245 23:22:50.493095 02d80000 ################################################################
10246 23:22:50.493230
10247 23:22:50.753210 02e00000 ################################################################
10248 23:22:50.753345
10249 23:22:51.017945 02e80000 ################################################################
10250 23:22:51.018114
10251 23:22:51.278731 02f00000 ################################################################
10252 23:22:51.278928
10253 23:22:51.530512 02f80000 ################################################################
10254 23:22:51.530644
10255 23:22:51.787730 03000000 ################################################################
10256 23:22:51.787902
10257 23:22:52.047323 03080000 ################################################################
10258 23:22:52.047484
10259 23:22:52.326491 03100000 ################################################################
10260 23:22:52.326621
10261 23:22:52.580508 03180000 ################################################################
10262 23:22:52.580642
10263 23:22:52.842269 03200000 ################################################################
10264 23:22:52.842488
10265 23:22:53.103072 03280000 ################################################################
10266 23:22:53.103235
10267 23:22:53.358484 03300000 ################################################################
10268 23:22:53.358622
10269 23:22:53.466604 03380000 ########################## done.
10270 23:22:53.466791
10271 23:22:53.470165 The bootfile was 54207310 bytes long.
10272 23:22:53.470294
10273 23:22:53.473266 Sending tftp read request... done.
10274 23:22:53.473392
10275 23:22:53.476778 Waiting for the transfer...
10276 23:22:53.476905
10277 23:22:53.477021 00000000 # done.
10278 23:22:53.477133
10279 23:22:53.483117 Command line loaded dynamically from TFTP file: 13248400/tftp-deploy-netd99_i/kernel/cmdline
10280 23:22:53.483243
10281 23:22:53.496463 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10282 23:22:53.499611
10283 23:22:53.499702 Loading FIT.
10284 23:22:53.499788
10285 23:22:53.503149 Image ramdisk-1 has 41250775 bytes.
10286 23:22:53.503272
10287 23:22:53.506258 Image fdt-1 has 47230 bytes.
10288 23:22:53.506379
10289 23:22:53.509727 Image kernel-1 has 12907270 bytes.
10290 23:22:53.509847
10291 23:22:53.516150 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10292 23:22:53.516272
10293 23:22:53.536282 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10294 23:22:53.536461
10295 23:22:53.539315 Choosing best match conf-1 for compat google,spherion-rev2.
10296 23:22:53.544240
10297 23:22:53.548901 Connected to device vid:did:rid of 1ae0:0028:00
10298 23:22:53.556970
10299 23:22:53.560038 tpm_get_response: command 0x17b, return code 0x0
10300 23:22:53.560161
10301 23:22:53.563063 ec_init: CrosEC protocol v3 supported (256, 248)
10302 23:22:53.567952
10303 23:22:53.571539 tpm_cleanup: add release locality here.
10304 23:22:53.571642
10305 23:22:53.571764 Shutting down all USB controllers.
10306 23:22:53.574898
10307 23:22:53.575017 Removing current net device
10308 23:22:53.575108
10309 23:22:53.581395 Exiting depthcharge with code 4 at timestamp: 66029421
10310 23:22:53.581522
10311 23:22:53.584899 LZMA decompressing kernel-1 to 0x821a6718
10312 23:22:53.585022
10313 23:22:53.588171 LZMA decompressing kernel-1 to 0x40000000
10314 23:22:55.181694
10315 23:22:55.181862 jumping to kernel
10316 23:22:55.182888 end: 2.2.4 bootloader-commands (duration 00:00:38) [common]
10317 23:22:55.183019 start: 2.2.5 auto-login-action (timeout 00:03:47) [common]
10318 23:22:55.183125 Setting prompt string to ['Linux version [0-9]']
10319 23:22:55.183222 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10320 23:22:55.183326 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10321 23:22:55.263253
10322 23:22:55.266353 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10323 23:22:55.269985 start: 2.2.5.1 login-action (timeout 00:03:47) [common]
10324 23:22:55.270088 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10325 23:22:55.270174 Setting prompt string to []
10326 23:22:55.270280 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10327 23:22:55.270374 Using line separator: #'\n'#
10328 23:22:55.270447 No login prompt set.
10329 23:22:55.270532 Parsing kernel messages
10330 23:22:55.270606 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10331 23:22:55.270791 [login-action] Waiting for messages, (timeout 00:03:47)
10332 23:22:55.270896 Waiting using forced prompt support (timeout 00:01:53)
10333 23:22:55.289707 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10334 23:22:55.292953 [ 0.000000] random: crng init done
10335 23:22:55.299648 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10336 23:22:55.302815 [ 0.000000] efi: UEFI not found.
10337 23:22:55.309301 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10338 23:22:55.319233 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10339 23:22:55.325862 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10340 23:22:55.336042 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10341 23:22:55.342460 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10342 23:22:55.349200 [ 0.000000] printk: bootconsole [mtk8250] enabled
10343 23:22:55.355861 [ 0.000000] NUMA: No NUMA configuration found
10344 23:22:55.362546 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10345 23:22:55.365536 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10346 23:22:55.368926 [ 0.000000] Zone ranges:
10347 23:22:55.375533 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10348 23:22:55.379025 [ 0.000000] DMA32 empty
10349 23:22:55.385686 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10350 23:22:55.388764 [ 0.000000] Movable zone start for each node
10351 23:22:55.392220 [ 0.000000] Early memory node ranges
10352 23:22:55.398872 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10353 23:22:55.405660 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10354 23:22:55.412409 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10355 23:22:55.419038 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10356 23:22:55.425636 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10357 23:22:55.432140 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10358 23:22:55.487851 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10359 23:22:55.494523 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10360 23:22:55.501215 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10361 23:22:55.504123 [ 0.000000] psci: probing for conduit method from DT.
10362 23:22:55.511159 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10363 23:22:55.514283 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10364 23:22:55.521107 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10365 23:22:55.524249 [ 0.000000] psci: SMC Calling Convention v1.2
10366 23:22:55.531123 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10367 23:22:55.534327 [ 0.000000] Detected VIPT I-cache on CPU0
10368 23:22:55.541060 [ 0.000000] CPU features: detected: GIC system register CPU interface
10369 23:22:55.547473 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10370 23:22:55.554026 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10371 23:22:55.560806 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10372 23:22:55.567628 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10373 23:22:55.577457 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10374 23:22:55.580676 [ 0.000000] alternatives: applying boot alternatives
10375 23:22:55.587095 [ 0.000000] Fallback order for Node 0: 0
10376 23:22:55.593872 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10377 23:22:55.597397 [ 0.000000] Policy zone: Normal
10378 23:22:55.610638 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10379 23:22:55.620776 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10380 23:22:55.631215 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10381 23:22:55.641234 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10382 23:22:55.647416 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10383 23:22:55.650904 <6>[ 0.000000] software IO TLB: area num 8.
10384 23:22:55.707398 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10385 23:22:55.856694 <6>[ 0.000000] Memory: 7924288K/8385536K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 428480K reserved, 32768K cma-reserved)
10386 23:22:55.863512 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10387 23:22:55.870222 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10388 23:22:55.873335 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10389 23:22:55.880238 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10390 23:22:55.886612 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10391 23:22:55.890140 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10392 23:22:55.899520 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10393 23:22:55.906202 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10394 23:22:55.912702 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10395 23:22:55.919286 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10396 23:22:55.922588 <6>[ 0.000000] GICv3: 608 SPIs implemented
10397 23:22:55.926011 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10398 23:22:55.932651 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10399 23:22:55.936166 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10400 23:22:55.942741 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10401 23:22:55.956118 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10402 23:22:55.968927 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10403 23:22:55.975633 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10404 23:22:55.983305 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10405 23:22:55.996684 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10406 23:22:56.003154 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10407 23:22:56.010019 <6>[ 0.009173] Console: colour dummy device 80x25
10408 23:22:56.019925 <6>[ 0.013930] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10409 23:22:56.023379 <6>[ 0.024372] pid_max: default: 32768 minimum: 301
10410 23:22:56.029636 <6>[ 0.029243] LSM: Security Framework initializing
10411 23:22:56.036160 <6>[ 0.034184] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10412 23:22:56.046094 <6>[ 0.041998] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10413 23:22:56.052699 <6>[ 0.051468] cblist_init_generic: Setting adjustable number of callback queues.
10414 23:22:56.059306 <6>[ 0.058912] cblist_init_generic: Setting shift to 3 and lim to 1.
10415 23:22:56.069495 <6>[ 0.065251] cblist_init_generic: Setting adjustable number of callback queues.
10416 23:22:56.076100 <6>[ 0.072724] cblist_init_generic: Setting shift to 3 and lim to 1.
10417 23:22:56.079282 <6>[ 0.079122] rcu: Hierarchical SRCU implementation.
10418 23:22:56.085962 <6>[ 0.084137] rcu: Max phase no-delay instances is 1000.
10419 23:22:56.092899 <6>[ 0.091192] EFI services will not be available.
10420 23:22:56.095993 <6>[ 0.096179] smp: Bringing up secondary CPUs ...
10421 23:22:56.104086 <6>[ 0.101229] Detected VIPT I-cache on CPU1
10422 23:22:56.110724 <6>[ 0.101301] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10423 23:22:56.117377 <6>[ 0.101332] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10424 23:22:56.120936 <6>[ 0.101669] Detected VIPT I-cache on CPU2
10425 23:22:56.127433 <6>[ 0.101724] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10426 23:22:56.133911 <6>[ 0.101742] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10427 23:22:56.140622 <6>[ 0.102002] Detected VIPT I-cache on CPU3
10428 23:22:56.147103 <6>[ 0.102050] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10429 23:22:56.153982 <6>[ 0.102066] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10430 23:22:56.157327 <6>[ 0.102371] CPU features: detected: Spectre-v4
10431 23:22:56.163731 <6>[ 0.102378] CPU features: detected: Spectre-BHB
10432 23:22:56.167294 <6>[ 0.102384] Detected PIPT I-cache on CPU4
10433 23:22:56.173937 <6>[ 0.102443] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10434 23:22:56.180125 <6>[ 0.102460] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10435 23:22:56.186845 <6>[ 0.102758] Detected PIPT I-cache on CPU5
10436 23:22:56.193760 <6>[ 0.102821] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10437 23:22:56.200316 <6>[ 0.102838] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10438 23:22:56.203535 <6>[ 0.103118] Detected PIPT I-cache on CPU6
10439 23:22:56.210269 <6>[ 0.103181] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10440 23:22:56.216788 <6>[ 0.103197] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10441 23:22:56.223742 <6>[ 0.103490] Detected PIPT I-cache on CPU7
10442 23:22:56.230350 <6>[ 0.103555] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10443 23:22:56.236943 <6>[ 0.103571] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10444 23:22:56.240124 <6>[ 0.103618] smp: Brought up 1 node, 8 CPUs
10445 23:22:56.246870 <6>[ 0.244976] SMP: Total of 8 processors activated.
10446 23:22:56.250021 <6>[ 0.249898] CPU features: detected: 32-bit EL0 Support
10447 23:22:56.260065 <6>[ 0.255294] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10448 23:22:56.266708 <6>[ 0.264150] CPU features: detected: Common not Private translations
10449 23:22:56.270079 <6>[ 0.270626] CPU features: detected: CRC32 instructions
10450 23:22:56.276769 <6>[ 0.275977] CPU features: detected: RCpc load-acquire (LDAPR)
10451 23:22:56.283465 <6>[ 0.281938] CPU features: detected: LSE atomic instructions
10452 23:22:56.290253 <6>[ 0.287719] CPU features: detected: Privileged Access Never
10453 23:22:56.293433 <6>[ 0.293535] CPU features: detected: RAS Extension Support
10454 23:22:56.303452 <6>[ 0.299179] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10455 23:22:56.306727 <6>[ 0.306400] CPU: All CPU(s) started at EL2
10456 23:22:56.313314 <6>[ 0.310717] alternatives: applying system-wide alternatives
10457 23:22:56.321960 <6>[ 0.321584] devtmpfs: initialized
10458 23:22:56.334031 <6>[ 0.330275] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10459 23:22:56.344178 <6>[ 0.340234] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10460 23:22:56.350515 <6>[ 0.348438] pinctrl core: initialized pinctrl subsystem
10461 23:22:56.353829 <6>[ 0.355099] DMI not present or invalid.
10462 23:22:56.360373 <6>[ 0.359509] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10463 23:22:56.370252 <6>[ 0.366388] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10464 23:22:56.377136 <6>[ 0.373973] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10465 23:22:56.386896 <6>[ 0.382197] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10466 23:22:56.389960 <6>[ 0.390436] audit: initializing netlink subsys (disabled)
10467 23:22:56.400186 <5>[ 0.396132] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10468 23:22:56.406535 <6>[ 0.396826] thermal_sys: Registered thermal governor 'step_wise'
10469 23:22:56.413199 <6>[ 0.404096] thermal_sys: Registered thermal governor 'power_allocator'
10470 23:22:56.416335 <6>[ 0.410351] cpuidle: using governor menu
10471 23:22:56.423027 <6>[ 0.421309] NET: Registered PF_QIPCRTR protocol family
10472 23:22:56.429749 <6>[ 0.426794] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10473 23:22:56.435898 <6>[ 0.433899] ASID allocator initialised with 32768 entries
10474 23:22:56.439232 <6>[ 0.440466] Serial: AMBA PL011 UART driver
10475 23:22:56.449692 <4>[ 0.449278] Trying to register duplicate clock ID: 134
10476 23:22:56.503885 <6>[ 0.506753] KASLR enabled
10477 23:22:56.518450 <6>[ 0.514440] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10478 23:22:56.525100 <6>[ 0.521453] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10479 23:22:56.531382 <6>[ 0.527942] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10480 23:22:56.538076 <6>[ 0.534945] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10481 23:22:56.544747 <6>[ 0.541430] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10482 23:22:56.551091 <6>[ 0.548435] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10483 23:22:56.557769 <6>[ 0.554921] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10484 23:22:56.564379 <6>[ 0.561926] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10485 23:22:56.567537 <6>[ 0.569461] ACPI: Interpreter disabled.
10486 23:22:56.576396 <6>[ 0.575952] iommu: Default domain type: Translated
10487 23:22:56.583238 <6>[ 0.581062] iommu: DMA domain TLB invalidation policy: strict mode
10488 23:22:56.586458 <5>[ 0.587721] SCSI subsystem initialized
10489 23:22:56.592818 <6>[ 0.591882] usbcore: registered new interface driver usbfs
10490 23:22:56.599424 <6>[ 0.597613] usbcore: registered new interface driver hub
10491 23:22:56.603017 <6>[ 0.603165] usbcore: registered new device driver usb
10492 23:22:56.609730 <6>[ 0.609264] pps_core: LinuxPPS API ver. 1 registered
10493 23:22:56.619722 <6>[ 0.614459] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10494 23:22:56.622781 <6>[ 0.623805] PTP clock support registered
10495 23:22:56.625979 <6>[ 0.628047] EDAC MC: Ver: 3.0.0
10496 23:22:56.633719 <6>[ 0.633193] FPGA manager framework
10497 23:22:56.637272 <6>[ 0.636871] Advanced Linux Sound Architecture Driver Initialized.
10498 23:22:56.640877 <6>[ 0.643650] vgaarb: loaded
10499 23:22:56.647265 <6>[ 0.646820] clocksource: Switched to clocksource arch_sys_counter
10500 23:22:56.654091 <5>[ 0.653261] VFS: Disk quotas dquot_6.6.0
10501 23:22:56.660675 <6>[ 0.657444] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10502 23:22:56.663836 <6>[ 0.664630] pnp: PnP ACPI: disabled
10503 23:22:56.671945 <6>[ 0.671258] NET: Registered PF_INET protocol family
10504 23:22:56.681713 <6>[ 0.676851] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10505 23:22:56.692798 <6>[ 0.689162] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10506 23:22:56.702689 <6>[ 0.697977] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10507 23:22:56.709441 <6>[ 0.705947] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10508 23:22:56.716374 <6>[ 0.714643] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10509 23:22:56.727991 <6>[ 0.724397] TCP: Hash tables configured (established 65536 bind 65536)
10510 23:22:56.734666 <6>[ 0.731257] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10511 23:22:56.741548 <6>[ 0.738453] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10512 23:22:56.747916 <6>[ 0.746154] NET: Registered PF_UNIX/PF_LOCAL protocol family
10513 23:22:56.754622 <6>[ 0.752302] RPC: Registered named UNIX socket transport module.
10514 23:22:56.758286 <6>[ 0.758454] RPC: Registered udp transport module.
10515 23:22:56.764749 <6>[ 0.763385] RPC: Registered tcp transport module.
10516 23:22:56.771372 <6>[ 0.768319] RPC: Registered tcp NFSv4.1 backchannel transport module.
10517 23:22:56.774523 <6>[ 0.774982] PCI: CLS 0 bytes, default 64
10518 23:22:56.777968 <6>[ 0.779317] Unpacking initramfs...
10519 23:22:56.795405 <6>[ 0.791428] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10520 23:22:56.805242 <6>[ 0.800094] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10521 23:22:56.808496 <6>[ 0.808943] kvm [1]: IPA Size Limit: 40 bits
10522 23:22:56.814873 <6>[ 0.813469] kvm [1]: GICv3: no GICV resource entry
10523 23:22:56.818245 <6>[ 0.818490] kvm [1]: disabling GICv2 emulation
10524 23:22:56.824891 <6>[ 0.823175] kvm [1]: GIC system register CPU interface enabled
10525 23:22:56.828111 <6>[ 0.829358] kvm [1]: vgic interrupt IRQ18
10526 23:22:56.835244 <6>[ 0.833726] kvm [1]: VHE mode initialized successfully
10527 23:22:56.841413 <5>[ 0.840260] Initialise system trusted keyrings
10528 23:22:56.848033 <6>[ 0.845055] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10529 23:22:56.855393 <6>[ 0.855091] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10530 23:22:56.862353 <5>[ 0.861488] NFS: Registering the id_resolver key type
10531 23:22:56.865603 <5>[ 0.866795] Key type id_resolver registered
10532 23:22:56.872169 <5>[ 0.871207] Key type id_legacy registered
10533 23:22:56.878488 <6>[ 0.875495] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10534 23:22:56.885269 <6>[ 0.882415] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10535 23:22:56.891899 <6>[ 0.890149] 9p: Installing v9fs 9p2000 file system support
10536 23:22:56.928221 <5>[ 0.927796] Key type asymmetric registered
10537 23:22:56.931730 <5>[ 0.932125] Asymmetric key parser 'x509' registered
10538 23:22:56.941142 <6>[ 0.937264] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10539 23:22:56.944528 <6>[ 0.944900] io scheduler mq-deadline registered
10540 23:22:56.947819 <6>[ 0.949681] io scheduler kyber registered
10541 23:22:56.966977 <6>[ 0.966895] EINJ: ACPI disabled.
10542 23:22:57.000186 <4>[ 0.993010] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10543 23:22:57.009966 <4>[ 1.003664] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10544 23:22:57.024893 <6>[ 1.024336] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10545 23:22:57.032899 <6>[ 1.032355] printk: console [ttyS0] disabled
10546 23:22:57.060819 <6>[ 1.056984] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10547 23:22:57.067246 <6>[ 1.066455] printk: console [ttyS0] enabled
10548 23:22:57.070625 <6>[ 1.066455] printk: console [ttyS0] enabled
10549 23:22:57.077212 <6>[ 1.075348] printk: bootconsole [mtk8250] disabled
10550 23:22:57.080744 <6>[ 1.075348] printk: bootconsole [mtk8250] disabled
10551 23:22:57.087007 <6>[ 1.086696] SuperH (H)SCI(F) driver initialized
10552 23:22:57.090637 <6>[ 1.091988] msm_serial: driver initialized
10553 23:22:57.104832 <6>[ 1.101091] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10554 23:22:57.114762 <6>[ 1.109639] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10555 23:22:57.121188 <6>[ 1.118182] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10556 23:22:57.131492 <6>[ 1.126814] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10557 23:22:57.138159 <6>[ 1.135519] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10558 23:22:57.147775 <6>[ 1.144233] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10559 23:22:57.158160 <6>[ 1.152787] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10560 23:22:57.164477 <6>[ 1.161622] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10561 23:22:57.174194 <6>[ 1.170167] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10562 23:22:57.186328 <6>[ 1.185986] loop: module loaded
10563 23:22:57.192993 <6>[ 1.191965] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10564 23:22:57.216120 <4>[ 1.215641] mtk-pmic-keys: Failed to locate of_node [id: -1]
10565 23:22:57.222892 <6>[ 1.222555] megasas: 07.719.03.00-rc1
10566 23:22:57.232579 <6>[ 1.232319] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10567 23:22:57.239208 <6>[ 1.238260] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10568 23:22:57.255258 <6>[ 1.254925] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10569 23:22:57.311376 <6>[ 1.304535] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10570 23:22:58.508596 <6>[ 2.508228] Freeing initrd memory: 40280K
10571 23:22:58.520232 <6>[ 2.520044] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10572 23:22:58.531648 <6>[ 2.531037] tun: Universal TUN/TAP device driver, 1.6
10573 23:22:58.534765 <6>[ 2.537113] thunder_xcv, ver 1.0
10574 23:22:58.538243 <6>[ 2.540620] thunder_bgx, ver 1.0
10575 23:22:58.541382 <6>[ 2.544118] nicpf, ver 1.0
10576 23:22:58.551794 <6>[ 2.548149] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10577 23:22:58.555146 <6>[ 2.555625] hns3: Copyright (c) 2017 Huawei Corporation.
10578 23:22:58.561691 <6>[ 2.561211] hclge is initializing
10579 23:22:58.564825 <6>[ 2.564791] e1000: Intel(R) PRO/1000 Network Driver
10580 23:22:58.571507 <6>[ 2.569920] e1000: Copyright (c) 1999-2006 Intel Corporation.
10581 23:22:58.575036 <6>[ 2.575934] e1000e: Intel(R) PRO/1000 Network Driver
10582 23:22:58.581532 <6>[ 2.581150] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10583 23:22:58.588387 <6>[ 2.587335] igb: Intel(R) Gigabit Ethernet Network Driver
10584 23:22:58.594724 <6>[ 2.592985] igb: Copyright (c) 2007-2014 Intel Corporation.
10585 23:22:58.601089 <6>[ 2.598828] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10586 23:22:58.607899 <6>[ 2.605346] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10587 23:22:58.611115 <6>[ 2.611831] sky2: driver version 1.30
10588 23:22:58.617723 <6>[ 2.616851] VFIO - User Level meta-driver version: 0.3
10589 23:22:58.625317 <6>[ 2.625149] usbcore: registered new interface driver usb-storage
10590 23:22:58.632079 <6>[ 2.631601] usbcore: registered new device driver onboard-usb-hub
10591 23:22:58.640991 <6>[ 2.640818] mt6397-rtc mt6359-rtc: registered as rtc0
10592 23:22:58.651031 <6>[ 2.646283] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:20:04 UTC (1712186404)
10593 23:22:58.654211 <6>[ 2.655853] i2c_dev: i2c /dev entries driver
10594 23:22:58.671423 <6>[ 2.667766] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10595 23:22:58.678067 <4>[ 2.676506] cpu cpu0: supply cpu not found, using dummy regulator
10596 23:22:58.684544 <4>[ 2.682938] cpu cpu1: supply cpu not found, using dummy regulator
10597 23:22:58.691265 <4>[ 2.689344] cpu cpu2: supply cpu not found, using dummy regulator
10598 23:22:58.697883 <4>[ 2.695764] cpu cpu3: supply cpu not found, using dummy regulator
10599 23:22:58.704578 <4>[ 2.702159] cpu cpu4: supply cpu not found, using dummy regulator
10600 23:22:58.711282 <4>[ 2.708554] cpu cpu5: supply cpu not found, using dummy regulator
10601 23:22:58.717713 <4>[ 2.714955] cpu cpu6: supply cpu not found, using dummy regulator
10602 23:22:58.724113 <4>[ 2.721350] cpu cpu7: supply cpu not found, using dummy regulator
10603 23:22:58.742244 <6>[ 2.742002] cpu cpu0: EM: created perf domain
10604 23:22:58.745400 <6>[ 2.746950] cpu cpu4: EM: created perf domain
10605 23:22:58.752665 <6>[ 2.752591] sdhci: Secure Digital Host Controller Interface driver
10606 23:22:58.759265 <6>[ 2.759025] sdhci: Copyright(c) Pierre Ossman
10607 23:22:58.766233 <6>[ 2.763992] Synopsys Designware Multimedia Card Interface Driver
10608 23:22:58.772591 <6>[ 2.770628] sdhci-pltfm: SDHCI platform and OF driver helper
10609 23:22:58.776182 <6>[ 2.770656] mmc0: CQHCI version 5.10
10610 23:22:58.782825 <6>[ 2.780872] ledtrig-cpu: registered to indicate activity on CPUs
10611 23:22:58.789532 <6>[ 2.787958] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10612 23:22:58.796073 <6>[ 2.795021] usbcore: registered new interface driver usbhid
10613 23:22:58.799190 <6>[ 2.800845] usbhid: USB HID core driver
10614 23:22:58.805781 <6>[ 2.805053] spi_master spi0: will run message pump with realtime priority
10615 23:22:58.851717 <6>[ 2.845042] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10616 23:22:58.871037 <6>[ 2.860774] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10617 23:22:58.877875 <6>[ 2.875789] cros-ec-spi spi0.0: Chrome EC device registered
10618 23:22:58.881529 <6>[ 2.881893] mmc0: Command Queue Engine enabled
10619 23:22:58.887831 <6>[ 2.886659] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10620 23:22:58.894373 <6>[ 2.894082] mmcblk0: mmc0:0001 DA4128 116 GiB
10621 23:22:58.904401 <6>[ 2.894506] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10622 23:22:58.907889 <6>[ 2.902799] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10623 23:22:58.914568 <6>[ 2.909263] NET: Registered PF_PACKET protocol family
10624 23:22:58.921318 <6>[ 2.915182] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10625 23:22:58.924435 <6>[ 2.919453] 9pnet: Installing 9P2000 support
10626 23:22:58.931123 <6>[ 2.925274] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10627 23:22:58.934199 <5>[ 2.929155] Key type dns_resolver registered
10628 23:22:58.940951 <6>[ 2.935093] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10629 23:22:58.944382 <6>[ 2.939408] registered taskstats version 1
10630 23:22:58.950849 <5>[ 2.949778] Loading compiled-in X.509 certificates
10631 23:22:58.978814 <4>[ 2.971946] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10632 23:22:58.988668 <4>[ 2.982700] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10633 23:22:58.995340 <3>[ 2.993234] debugfs: File 'uA_load' in directory '/' already present!
10634 23:22:59.002060 <3>[ 2.999933] debugfs: File 'min_uV' in directory '/' already present!
10635 23:22:59.008529 <3>[ 3.006544] debugfs: File 'max_uV' in directory '/' already present!
10636 23:22:59.015182 <3>[ 3.013212] debugfs: File 'constraint_flags' in directory '/' already present!
10637 23:22:59.026195 <3>[ 3.022851] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10638 23:22:59.036032 <6>[ 3.035998] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10639 23:22:59.043185 <6>[ 3.042752] xhci-mtk 11200000.usb: xHCI Host Controller
10640 23:22:59.049387 <6>[ 3.048259] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10641 23:22:59.059531 <6>[ 3.056095] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10642 23:22:59.066323 <6>[ 3.065520] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10643 23:22:59.072603 <6>[ 3.071593] xhci-mtk 11200000.usb: xHCI Host Controller
10644 23:22:59.079282 <6>[ 3.077067] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10645 23:22:59.085793 <6>[ 3.084713] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10646 23:22:59.092859 <6>[ 3.092532] hub 1-0:1.0: USB hub found
10647 23:22:59.096079 <6>[ 3.096559] hub 1-0:1.0: 1 port detected
10648 23:22:59.102743 <6>[ 3.100857] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10649 23:22:59.109870 <6>[ 3.109640] hub 2-0:1.0: USB hub found
10650 23:22:59.112885 <6>[ 3.113660] hub 2-0:1.0: 1 port detected
10651 23:22:59.121812 <6>[ 3.121756] mtk-msdc 11f70000.mmc: Got CD GPIO
10652 23:22:59.138623 <6>[ 3.134976] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10653 23:22:59.145014 <6>[ 3.142995] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10654 23:22:59.154935 <4>[ 3.150905] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10655 23:22:59.164866 <6>[ 3.160448] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10656 23:22:59.171541 <6>[ 3.168525] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10657 23:22:59.178158 <6>[ 3.176690] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10658 23:22:59.188267 <6>[ 3.184644] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10659 23:22:59.194827 <6>[ 3.192462] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10660 23:22:59.204665 <6>[ 3.200278] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10661 23:22:59.214686 <6>[ 3.210663] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10662 23:22:59.221191 <6>[ 3.219039] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10663 23:22:59.231432 <6>[ 3.227381] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10664 23:22:59.237934 <6>[ 3.235720] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10665 23:22:59.247744 <6>[ 3.244064] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10666 23:22:59.254361 <6>[ 3.252402] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10667 23:22:59.264155 <6>[ 3.260739] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10668 23:22:59.271153 <6>[ 3.269077] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10669 23:22:59.281066 <6>[ 3.277415] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10670 23:22:59.287356 <6>[ 3.285752] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10671 23:22:59.297399 <6>[ 3.294089] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10672 23:22:59.307643 <6>[ 3.302426] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10673 23:22:59.314785 <6>[ 3.310762] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10674 23:22:59.324264 <6>[ 3.319109] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10675 23:22:59.330716 <6>[ 3.327446] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10676 23:22:59.337433 <6>[ 3.336197] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10677 23:22:59.343960 <6>[ 3.343370] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10678 23:22:59.350784 <6>[ 3.350141] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10679 23:22:59.357119 <6>[ 3.356904] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10680 23:22:59.364038 <6>[ 3.363831] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10681 23:22:59.374042 <6>[ 3.370670] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10682 23:22:59.384228 <6>[ 3.379800] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10683 23:22:59.394336 <6>[ 3.388920] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10684 23:22:59.404213 <6>[ 3.398215] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10685 23:22:59.410807 <6>[ 3.407681] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10686 23:22:59.420612 <6>[ 3.417148] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10687 23:22:59.430541 <6>[ 3.426268] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10688 23:22:59.440360 <6>[ 3.435733] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10689 23:22:59.450064 <6>[ 3.444854] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10690 23:22:59.459928 <6>[ 3.454148] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10691 23:22:59.469692 <6>[ 3.464308] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10692 23:22:59.479465 <6>[ 3.476280] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10693 23:22:59.502548 <6>[ 3.499313] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10694 23:22:59.529871 <6>[ 3.529812] hub 2-1:1.0: USB hub found
10695 23:22:59.533081 <6>[ 3.534227] hub 2-1:1.0: 3 ports detected
10696 23:22:59.540970 <6>[ 3.540936] hub 2-1:1.0: USB hub found
10697 23:22:59.544117 <6>[ 3.545405] hub 2-1:1.0: 3 ports detected
10698 23:22:59.654459 <6>[ 3.651103] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10699 23:22:59.809394 <6>[ 3.809230] hub 1-1:1.0: USB hub found
10700 23:22:59.812683 <6>[ 3.813721] hub 1-1:1.0: 4 ports detected
10701 23:22:59.822256 <6>[ 3.822099] hub 1-1:1.0: USB hub found
10702 23:22:59.825159 <6>[ 3.826434] hub 1-1:1.0: 4 ports detected
10703 23:22:59.894643 <6>[ 3.891172] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10704 23:23:00.146505 <6>[ 4.143112] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10705 23:23:00.278653 <6>[ 4.278736] hub 1-1.4:1.0: USB hub found
10706 23:23:00.282222 <6>[ 4.283376] hub 1-1.4:1.0: 2 ports detected
10707 23:23:00.291463 <6>[ 4.291595] hub 1-1.4:1.0: USB hub found
10708 23:23:00.294806 <6>[ 4.296191] hub 1-1.4:1.0: 2 ports detected
10709 23:23:00.590451 <6>[ 4.587067] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10710 23:23:00.778406 <6>[ 4.775103] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10711 23:23:11.755842 <6>[ 15.760146] ALSA device list:
10712 23:23:11.762249 <6>[ 15.763433] No soundcards found.
10713 23:23:11.770459 <6>[ 15.771505] Freeing unused kernel memory: 8448K
10714 23:23:11.773791 <6>[ 15.776976] Run /init as init process
10715 23:23:11.804821 <6>[ 15.806343] NET: Registered PF_INET6 protocol family
10716 23:23:11.811714 <6>[ 15.812910] Segment Routing with IPv6
10717 23:23:11.815084 <6>[ 15.816863] In-situ OAM (IOAM) with IPv6
10718 23:23:11.857740 <30>[ 15.832158] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10719 23:23:11.864152 <30>[ 15.865301] systemd[1]: Detected architecture arm64.
10720 23:23:11.864281
10721 23:23:11.870483 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10722 23:23:11.870605
10723 23:23:11.870718
10724 23:23:11.890020 <30>[ 15.891214] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10725 23:23:12.002396 <30>[ 16.000172] systemd[1]: Queued start job for default target graphical.target.
10726 23:23:12.030739 <30>[ 16.028595] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10727 23:23:12.037240 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10728 23:23:12.037322
10729 23:23:12.057709 <30>[ 16.055827] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10730 23:23:12.067549 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10731 23:23:12.067668
10732 23:23:12.085791 <30>[ 16.083835] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10733 23:23:12.095882 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10734 23:23:12.095997
10735 23:23:12.114496 <30>[ 16.112457] systemd[1]: Created slice user.slice - User and Session Slice.
10736 23:23:12.121409 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10737 23:23:12.121523
10738 23:23:12.144320 <30>[ 16.139212] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10739 23:23:12.151409 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10740 23:23:12.151521
10741 23:23:12.173300 <30>[ 16.167792] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10742 23:23:12.179812 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10743 23:23:12.179929
10744 23:23:12.207505 <30>[ 16.195596] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10745 23:23:12.217452 <30>[ 16.215560] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10746 23:23:12.224124 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10747 23:23:12.224211
10748 23:23:12.241367 <30>[ 16.239439] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10749 23:23:12.251376 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10750 23:23:12.251461
10751 23:23:12.269785 <30>[ 16.267662] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10752 23:23:12.279645 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10753 23:23:12.279732
10754 23:23:12.294027 <30>[ 16.295212] systemd[1]: Reached target paths.target - Path Units.
10755 23:23:12.300469 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10756 23:23:12.303804
10757 23:23:12.321835 <30>[ 16.319611] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10758 23:23:12.328222 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10759 23:23:12.328347
10760 23:23:12.345287 <30>[ 16.343101] systemd[1]: Reached target slices.target - Slice Units.
10761 23:23:12.351630 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10762 23:23:12.351712
10763 23:23:12.366372 <30>[ 16.367637] systemd[1]: Reached target swap.target - Swaps.
10764 23:23:12.372908 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10765 23:23:12.372991
10766 23:23:12.393923 <30>[ 16.391620] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10767 23:23:12.403850 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10768 23:23:12.403935
10769 23:23:12.422216 <30>[ 16.420091] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10770 23:23:12.432008 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10771 23:23:12.432117
10772 23:23:12.451408 <30>[ 16.449365] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10773 23:23:12.461136 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10774 23:23:12.461224
10775 23:23:12.477713 <30>[ 16.475801] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10776 23:23:12.487608 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10777 23:23:12.487740
10778 23:23:12.505740 <30>[ 16.503818] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10779 23:23:12.512641 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10780 23:23:12.512751
10781 23:23:12.529861 <30>[ 16.527783] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10782 23:23:12.539609 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10783 23:23:12.539693
10784 23:23:12.558596 <30>[ 16.556508] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10785 23:23:12.568331 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10786 23:23:12.568417
10787 23:23:12.586151 <30>[ 16.584199] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10788 23:23:12.595935 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10789 23:23:12.596044
10790 23:23:12.649433 <30>[ 16.647219] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10791 23:23:12.655791 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10792 23:23:12.655878
10793 23:23:12.674921 <30>[ 16.672997] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10794 23:23:12.681784 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10795 23:23:12.681867
10796 23:23:12.703211 <30>[ 16.700938] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10797 23:23:12.709789 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10798 23:23:12.709872
10799 23:23:12.735781 <30>[ 16.727153] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10800 23:23:12.746559 <30>[ 16.744707] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10801 23:23:12.756468 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10802 23:23:12.756551
10803 23:23:12.805469 <30>[ 16.803471] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10804 23:23:12.812075 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10805 23:23:12.812165
10806 23:23:12.842021 <30>[ 16.839893] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10807 23:23:12.855195 Starting [0;1;39mmodprobe@dm_mod.s…[<6>[ 16.851748] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10808 23:23:12.858610 0m - Load Kernel Module dm_mod...
10809 23:23:12.858693
10810 23:23:12.883718 <30>[ 16.881839] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10811 23:23:12.890602 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10812 23:23:12.890685
10813 23:23:12.916225 <30>[ 16.914340] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10814 23:23:12.922770 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10815 23:23:12.926229
10816 23:23:12.969647 <30>[ 16.967910] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10817 23:23:12.976215 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10818 23:23:12.976368
10819 23:23:13.006263 <30>[ 17.004347] systemd[1]: Starting systemd-journald.service - Journal Service...
10820 23:23:13.012824 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10821 23:23:13.012950
10822 23:23:13.057667 <30>[ 17.055839] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10823 23:23:13.064104 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10824 23:23:13.064253
10825 23:23:13.091521 <30>[ 17.086236] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10826 23:23:13.097900 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10827 23:23:13.098025
10828 23:23:13.137662 <30>[ 17.135582] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10829 23:23:13.147436 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10830 23:23:13.147565
10831 23:23:13.168362 <30>[ 17.166521] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10832 23:23:13.178218 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10833 23:23:13.178347
10834 23:23:13.205345 <30>[ 17.203435] systemd[1]: Started systemd-journald.service - Journal Service.
10835 23:23:13.212176 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10836 23:23:13.212307
10837 23:23:13.233554 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10838 23:23:13.233679
10839 23:23:13.249658 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10840 23:23:13.249784
10841 23:23:13.270071 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10842 23:23:13.270198
10843 23:23:13.290060 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10844 23:23:13.290160
10845 23:23:13.313282 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10846 23:23:13.313372
10847 23:23:13.331610 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10848 23:23:13.331752
10849 23:23:13.357365 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10850 23:23:13.357451
10851 23:23:13.376082 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10852 23:23:13.376172
10853 23:23:13.400141 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10854 23:23:13.400228
10855 23:23:13.423637 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10856 23:23:13.423750
10857 23:23:13.442700 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10858 23:23:13.442830
10859 23:23:13.463681 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10860 23:23:13.463809
10861 23:23:13.477882 See 'systemctl status systemd-remount-fs.service' for details.
10862 23:23:13.478012
10863 23:23:13.498768 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10864 23:23:13.498895
10865 23:23:13.519854 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10866 23:23:13.519941
10867 23:23:13.577716 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10868 23:23:13.577817
10869 23:23:13.601543 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10870 23:23:13.601676
10871 23:23:13.624070 Starting [0;1;39msyste<46>[ 17.621105] systemd-journald[190]: Received client request to flush runtime journal.
10872 23:23:13.627124 md-random-se…ice[0m - Load/Save Random Seed...
10873 23:23:13.627247
10874 23:23:13.647893 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10875 23:23:13.647982
10876 23:23:13.668467 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10877 23:23:13.668595
10878 23:23:13.694322 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10879 23:23:13.694454
10880 23:23:13.714438 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10881 23:23:13.714569
10882 23:23:13.738305 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10883 23:23:13.738436
10884 23:23:13.758557 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10885 23:23:13.758688
10886 23:23:13.778255 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10887 23:23:13.778380
10888 23:23:13.837960 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10889 23:23:13.838063
10890 23:23:13.874950 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10891 23:23:13.875071
10892 23:23:13.894125 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10893 23:23:13.894210
10894 23:23:13.913451 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10895 23:23:13.913535
10896 23:23:13.961732 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10897 23:23:13.961832
10898 23:23:13.985627 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10899 23:23:13.985714
10900 23:23:14.009006 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10901 23:23:14.009093
10902 23:23:14.033229 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10903 23:23:14.033314
10904 23:23:14.052784 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10905 23:23:14.052867
10906 23:23:14.065349 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10907 23:23:14.065453
10908 23:23:14.152157 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10909 23:23:14.152266
10910 23:23:14.177560 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10911 23:23:14.177652
10912 23:23:14.203540 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10913 23:23:14.203671
10914 23:23:14.226188 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10915 23:23:14.226279
10916 23:23:14.263304 <5>[ 18.261701] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10917 23:23:14.290515 <5>[ 18.288938] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10918 23:23:14.297210 <5>[ 18.296489] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10919 23:23:14.307171 <4>[ 18.305251] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10920 23:23:14.313822 <6>[ 18.314410] cfg80211: failed to load regulatory.db
10921 23:23:14.336593 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10922 23:23:14.336682
10923 23:23:14.364279 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10924 23:23:14.364405
10925 23:23:14.386186 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10926 23:23:14.386273
10927 23:23:14.407566 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10928 23:23:14.407654
10929 23:23:14.422386 <6>[ 18.420633] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10930 23:23:14.433854 [[0;32m OK [0m] Reached targ<6>[ 18.433843] remoteproc remoteproc0: scp is available
10931 23:23:14.440456 et [0;1;39mtime<6>[ 18.440529] remoteproc remoteproc0: powering up scp
10932 23:23:14.450674 -set.target[0m <6>[ 18.446573] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10933 23:23:14.460463 - System Time Se<3>[ 18.450968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10934 23:23:14.466963 <6>[ 18.452429] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10935 23:23:14.467047 t.
10936 23:23:14.467208
10937 23:23:14.476864 <6>[ 18.452469] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10938 23:23:14.483587 <6>[ 18.452483] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10939 23:23:14.490091 <6>[ 18.456409] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10940 23:23:14.499917 <3>[ 18.466926] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10941 23:23:14.506412 <6>[ 18.474184] usbcore: registered new device driver r8152-cfgselector
10942 23:23:14.513049 <3>[ 18.484054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10943 23:23:14.516450 <6>[ 18.494563] mc: Linux media interface: v0.10
10944 23:23:14.526466 <4>[ 18.495307] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10945 23:23:14.532786 <4>[ 18.495415] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10946 23:23:14.539187 <3>[ 18.499681] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10947 23:23:14.549062 <6>[ 18.499862] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10948 23:23:14.555954 <3>[ 18.555006] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10949 23:23:14.565807 [[0;32m OK [<3>[ 18.563283] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10950 23:23:14.572477 <6>[ 18.572295] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10951 23:23:14.582192 <3>[ 18.572795] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10952 23:23:14.588937 <6>[ 18.579494] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10953 23:23:14.595735 <6>[ 18.579807] pci_bus 0000:00: root bus resource [bus 00-ff]
10954 23:23:14.605580 0m] Started [0;<3>[ 18.587712] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10955 23:23:14.611915 1;39mfstrim.time<6>[ 18.596051] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10956 23:23:14.618870 <6>[ 18.600116] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10957 23:23:14.628673 r[0m - Discard <6>[ 18.600136] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10958 23:23:14.635178 <6>[ 18.600144] remoteproc remoteproc0: remote processor scp is now up
10959 23:23:14.645310 <3>[ 18.601877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10960 23:23:14.651694 <3>[ 18.601936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10961 23:23:14.661728 <3>[ 18.601940] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10962 23:23:14.671477 unused blocks on<3>[ 18.601943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10963 23:23:14.678350 <3>[ 18.602021] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10964 23:23:14.678433 ce a week.
10965 23:23:14.678496
10966 23:23:14.688607 <3>[ 18.602026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10967 23:23:14.695671 <3>[ 18.602028] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10968 23:23:14.702469 <3>[ 18.602033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10969 23:23:14.712444 <6>[ 18.602737] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10970 23:23:14.722651 <4>[ 18.603968] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10971 23:23:14.729080 <4>[ 18.603973] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10972 23:23:14.738874 <6>[ 18.611732] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10973 23:23:14.748949 <6>[ 18.612825] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10974 23:23:14.755450 <6>[ 18.614540] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10975 23:23:14.765469 <3>[ 18.619816] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10976 23:23:14.771754 <6>[ 18.626982] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10977 23:23:14.778379 <3>[ 18.636798] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10978 23:23:14.785176 <6>[ 18.643193] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10979 23:23:14.798402 <6>[ 18.660390] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10980 23:23:14.801704 <6>[ 18.667483] pci 0000:00:00.0: supports D1 D2
10981 23:23:14.811552 <4>[ 18.669793] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10982 23:23:14.814871 <4>[ 18.669793] Fallback method does not support PEC.
10983 23:23:14.825580 <6>[ 18.677362] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10984 23:23:14.832559 <6>[ 18.684968] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10985 23:23:14.835970 <6>[ 18.685214] r8152 2-1.3:1.0 eth0: v1.12.13
10986 23:23:14.843320 <6>[ 18.685949] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10987 23:23:14.849800 <6>[ 18.686023] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10988 23:23:14.856425 <6>[ 18.686047] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10989 23:23:14.862936 <6>[ 18.686062] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10990 23:23:14.872888 <6>[ 18.686077] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10991 23:23:14.876259 <6>[ 18.686179] pci 0000:01:00.0: supports D1 D2
10992 23:23:14.882761 <6>[ 18.686180] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10993 23:23:14.889718 <6>[ 18.698976] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10994 23:23:14.896412 <6>[ 18.705478] usbcore: registered new interface driver r8152
10995 23:23:14.903490 <6>[ 18.710530] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10996 23:23:14.913395 <3>[ 18.711060] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 23:23:14.919930 <6>[ 18.711082] videodev: Linux video capture interface: v2.00
10998 23:23:14.923330 <6>[ 18.738076] Bluetooth: Core ver 2.22
10999 23:23:14.929922 <6>[ 18.746844] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11000 23:23:14.936453 <6>[ 18.747337] usbcore: registered new interface driver cdc_ether
11001 23:23:14.943254 <6>[ 18.755184] NET: Registered PF_BLUETOOTH protocol family
11002 23:23:14.949970 <6>[ 18.755617] usbcore: registered new interface driver r8153_ecm
11003 23:23:14.956518 <6>[ 18.763379] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11004 23:23:14.963140 <6>[ 18.763395] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11005 23:23:14.972968 <6>[ 18.763409] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11006 23:23:14.979562 <6>[ 18.771682] Bluetooth: HCI device and connection manager initialized
11007 23:23:14.986519 <6>[ 18.773127] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11008 23:23:14.999398 <6>[ 18.774220] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11009 23:23:15.005835 <6>[ 18.774340] usbcore: registered new interface driver uvcvideo
11010 23:23:15.009303 <6>[ 18.777750] pci 0000:00:00.0: PCI bridge to [bus 01]
11011 23:23:15.016237 <6>[ 18.782016] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11012 23:23:15.019416 <6>[ 18.785854] Bluetooth: HCI socket layer initialized
11013 23:23:15.029435 <6>[ 18.793292] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11014 23:23:15.035825 <6>[ 18.803369] Bluetooth: L2CAP socket layer initialized
11015 23:23:15.039333 <6>[ 18.808099] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11016 23:23:15.045993 <6>[ 18.808537] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11017 23:23:15.052467 <6>[ 18.821530] Bluetooth: SCO socket layer initialized
11018 23:23:15.059240 <6>[ 18.831098] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11019 23:23:15.065526 <3>[ 18.841952] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11020 23:23:15.072509 <6>[ 18.850339] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11021 23:23:15.082308 <3>[ 18.856920] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
11022 23:23:15.089100 <3>[ 18.857529] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11023 23:23:15.099166 <3>[ 18.858194] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
11024 23:23:15.102211 <6>[ 18.873073] usbcore: registered new interface driver btusb
11025 23:23:15.115416 <4>[ 18.874143] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11026 23:23:15.118558 <3>[ 18.874151] Bluetooth: hci0: Failed to load firmware file (-2)
11027 23:23:15.125370 <3>[ 18.874153] Bluetooth: hci0: Failed to set up firmware (-2)
11028 23:23:15.135116 <4>[ 18.874155] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11029 23:23:15.144983 <3>[ 18.908379] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11030 23:23:15.151854 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11031 23:23:15.151977
11032 23:23:15.177473 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message<3>[ 19.175782] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11033 23:23:15.180746 Bus Socket.
11034 23:23:15.180830
11035 23:23:15.193152 <6>[ 19.191318] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11036 23:23:15.200455 <6>[ 19.198847] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11037 23:23:15.213542 [[0;32m OK [0m] Reached target [0;1;39msock<3>[ 19.208554] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11038 23:23:15.213631 ets.target[0m - Socket Units.
11039 23:23:15.213696
11040 23:23:15.223846 <6>[ 19.225537] mt7921e 0000:01:00.0: ASIC revision: 79610010
11041 23:23:15.231220 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11042 23:23:15.231301
11043 23:23:15.241024 <3>[ 19.239333] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11044 23:23:15.273439 <3>[ 19.271670] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11045 23:23:15.279871 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11046 23:23:15.279955
11047 23:23:15.306023 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11048 23:23:15.306117
11049 23:23:15.330667 <6>[ 19.328707] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11050 23:23:15.334029 <6>[ 19.328707]
11051 23:23:15.340425 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11052 23:23:15.340508
11053 23:23:15.360207 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11054 23:23:15.360302
11055 23:23:15.388684 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11056 23:23:15.388778
11057 23:23:15.432144 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11058 23:23:15.432238
11059 23:23:15.455635 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11060 23:23:15.455719
11061 23:23:15.473580 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11062 23:23:15.473713
11063 23:23:15.493730 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11064 23:23:15.493860
11065 23:23:15.546435 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11066 23:23:15.546572
11067 23:23:15.568087 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11068 23:23:15.568178
11069 23:23:15.585984 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11070 23:23:15.586118
11071 23:23:15.600775 <6>[ 19.599000] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11072 23:23:15.607153 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11073 23:23:15.607277
11074 23:23:15.629967 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11075 23:23:15.630092
11076 23:23:15.682756 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11077 23:23:15.682876
11078 23:23:15.707799 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11079 23:23:15.707885
11080 23:23:15.732780 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11081 23:23:15.732865
11082 23:23:15.807082 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11083 23:23:15.807216
11084 23:23:15.826391 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11085 23:23:15.826502
11086 23:23:15.850332 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11087 23:23:15.850450
11088 23:23:15.913336
11089 23:23:15.913466
11090 23:23:15.916915 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11091 23:23:15.917027
11092 23:23:15.920130 debian-bookworm-arm64 login: root (automatic login)
11093 23:23:15.920240
11094 23:23:15.920341
11095 23:23:15.934138 Linux debian-bookworm-arm64 6.1.83-cip18 #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024 aarch64
11096 23:23:15.934253
11097 23:23:15.940559 The programs included with the Debian GNU/Linux system are free software;
11098 23:23:15.947145 the exact distribution terms for each program are described in the
11099 23:23:15.950712 individual files in /usr/share/doc/*/copyright.
11100 23:23:15.950818
11101 23:23:15.957124 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11102 23:23:15.960189 permitted by applicable law.
11103 23:23:15.960831 Matched prompt #10: / #
11105 23:23:15.961148 Setting prompt string to ['/ #']
11106 23:23:15.961280 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11108 23:23:15.961534 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11109 23:23:15.961661 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
11110 23:23:15.961767 Setting prompt string to ['/ #']
11111 23:23:15.961867 Forcing a shell prompt, looking for ['/ #']
11113 23:23:16.012131 / #
11114 23:23:16.012277 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11115 23:23:16.012425 Waiting using forced prompt support (timeout 00:02:30)
11116 23:23:16.017069
11117 23:23:16.017363 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11118 23:23:16.017472 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
11119 23:23:16.017606 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11120 23:23:16.017712 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
11121 23:23:16.017815 end: 2 depthcharge-action (duration 00:01:34) [common]
11122 23:23:16.017950 start: 3 lava-test-retry (timeout 00:08:00) [common]
11123 23:23:16.018079 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
11124 23:23:16.018191 Using namespace: common
11126 23:23:16.118538 / # #
11127 23:23:16.118696 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11128 23:23:16.123493 #
11129 23:23:16.123785 Using /lava-13248400
11131 23:23:16.224152 / # export SHELL=/bin/sh
11132 23:23:16.229252 export SHELL=/bin/sh
11134 23:23:16.329748 / # . /lava-13248400/environment
11135 23:23:16.329911 <6>[ 20.265552] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11136 23:23:16.330021 <6>[ 20.273402] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11137 23:23:16.334962 . /lava-13248400/environment
11139 23:23:16.435489 / # /lava-13248400/bin/lava-test-runner /lava-13248400/0
11140 23:23:16.435623 Test shell timeout: 10s (minimum of the action and connection timeout)
11141 23:23:16.440438 /lava-13248400/bin/lava-test-runner /lava-13248400/0
11142 23:23:16.465446 <6>[ 20.467255] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11143 23:23:16.472751 + export TESTRUN_ID=0_v4l2-compliance-uvc
11144 23:23:16.476188 + cd /lava-13248400/0/tests/0_v4l2-compliance-uvc
11145 23:23:16.476320 + cat uuid
11146 23:23:16.479399 + UUID=13248400_1.5.2.3.1
11147 23:23:16.479495 + set +x
11148 23:23:16.486211 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 13248400_1.5.2.3.1>
11149 23:23:16.486469 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 13248400_1.5.2.3.1
11150 23:23:16.486545 Starting test lava.0_v4l2-compliance-uvc (13248400_1.5.2.3.1)
11151 23:23:16.486625 Skipping test definition patterns.
11152 23:23:16.489264 + /usr/bin/v4l2-parser.sh -d uvcvideo
11153 23:23:16.495739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11154 23:23:16.495842 device: /dev/video0
11155 23:23:16.496078 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11157 23:23:22.989375 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11158 23:23:22.999807 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11159 23:23:23.008817
11160 23:23:23.026515 Compliance test for uvcvideo device /dev/video0:
11161 23:23:23.038091
11162 23:23:23.050596 Driver Info:
11163 23:23:23.063909 Driver name : uvcvideo
11164 23:23:23.082542 Card type : HD User Facing: HD User Facing
11165 23:23:23.094449 Bus info : usb-11200000.usb-1.4.1
11166 23:23:23.102690 Driver version : 6.1.83
11167 23:23:23.114777 Capabilities : 0x84a00001
11168 23:23:23.131098 Metadata Capture
11169 23:23:23.141212 Streaming
11170 23:23:23.151302 Extended Pix Format
11171 23:23:23.162655 Device Capabilities
11172 23:23:23.172175 Device Caps : 0x04200001
11173 23:23:23.185066 Streaming
11174 23:23:23.194910 Extended Pix Format
11175 23:23:23.204583 Media Driver Info:
11176 23:23:23.214363 Driver name : uvcvideo
11177 23:23:23.233626 Model : HD User Facing: HD User Facing
11178 23:23:23.242404 Serial : 200901010001
11179 23:23:23.255992 Bus info : usb-11200000.usb-1.4.1
11180 23:23:23.263304 Media version : 6.1.83
11181 23:23:23.282438 Hardware revision: 0x00009758 (38744)
11182 23:23:23.290793 Driver version : 6.1.83
11183 23:23:23.304924 Interface Info:
11184 23:23:23.319928 <LAVA_SIGNAL_TESTSET START Interface-Info>
11185 23:23:23.320054 ID : 0x03000002
11186 23:23:23.320351 Received signal: <TESTSET> START Interface-Info
11187 23:23:23.320476 Starting test_set Interface-Info
11188 23:23:23.331214 Type : V4L Video
11189 23:23:23.344823 Entity Info:
11190 23:23:23.351938 <LAVA_SIGNAL_TESTSET STOP>
11191 23:23:23.352237 Received signal: <TESTSET> STOP
11192 23:23:23.352405 Closing test_set Interface-Info
11193 23:23:23.362309 <LAVA_SIGNAL_TESTSET START Entity-Info>
11194 23:23:23.362594 Received signal: <TESTSET> START Entity-Info
11195 23:23:23.362690 Starting test_set Entity-Info
11196 23:23:23.365226 ID : 0x00000001 (1)
11197 23:23:23.377677 Name : HD User Facing: HD User Facing
11198 23:23:23.385878 Function : V4L2 I/O
11199 23:23:23.396691 Flags : default
11200 23:23:23.408440 Pad 0x01000007 : 0: Sink
11201 23:23:23.433533 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11202 23:23:23.433666
11203 23:23:23.445693 Required ioctls:
11204 23:23:23.453162 <LAVA_SIGNAL_TESTSET STOP>
11205 23:23:23.453467 Received signal: <TESTSET> STOP
11206 23:23:23.453587 Closing test_set Entity-Info
11207 23:23:23.464935 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11208 23:23:23.465238 Received signal: <TESTSET> START Required-ioctls
11209 23:23:23.465353 Starting test_set Required-ioctls
11210 23:23:23.468029 test MC information (see 'Media Driver Info' above): OK
11211 23:23:23.493318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11212 23:23:23.493627 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11214 23:23:23.496551 test VIDIOC_QUERYCAP: OK
11215 23:23:23.513929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11216 23:23:23.514233 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11218 23:23:23.516934 test invalid ioctls: OK
11219 23:23:23.540972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11220 23:23:23.541108
11221 23:23:23.541402 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11223 23:23:23.551729 Allow for multiple opens:
11224 23:23:23.559138 <LAVA_SIGNAL_TESTSET STOP>
11225 23:23:23.559441 Received signal: <TESTSET> STOP
11226 23:23:23.559558 Closing test_set Required-ioctls
11227 23:23:23.568262 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11228 23:23:23.568570 Received signal: <TESTSET> START Allow-for-multiple-opens
11229 23:23:23.568683 Starting test_set Allow-for-multiple-opens
11230 23:23:23.571318 test second /dev/video0 open: OK
11231 23:23:23.592920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11232 23:23:23.593221 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11234 23:23:23.596190 test VIDIOC_QUERYCAP: OK
11235 23:23:23.618079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11236 23:23:23.618376 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11238 23:23:23.621317 test VIDIOC_G/S_PRIORITY: OK
11239 23:23:23.644694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11240 23:23:23.645003 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11242 23:23:23.647625 test for unlimited opens: OK
11243 23:23:23.668622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11244 23:23:23.668749
11245 23:23:23.669035 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11247 23:23:23.680316 Debug ioctls:
11248 23:23:23.687396 <LAVA_SIGNAL_TESTSET STOP>
11249 23:23:23.687646 Received signal: <TESTSET> STOP
11250 23:23:23.687714 Closing test_set Allow-for-multiple-opens
11251 23:23:23.696818 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11252 23:23:23.697126 Received signal: <TESTSET> START Debug-ioctls
11253 23:23:23.697245 Starting test_set Debug-ioctls
11254 23:23:23.699918 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11255 23:23:23.722506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11256 23:23:23.722811 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11258 23:23:23.729225 test VIDIOC_LOG_STATUS: OK (Not Supported)
11259 23:23:23.747120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11260 23:23:23.747247
11261 23:23:23.747533 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11263 23:23:23.757823 Input ioctls:
11264 23:23:23.765459 <LAVA_SIGNAL_TESTSET STOP>
11265 23:23:23.765761 Received signal: <TESTSET> STOP
11266 23:23:23.765875 Closing test_set Debug-ioctls
11267 23:23:23.775297 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11268 23:23:23.775598 Received signal: <TESTSET> START Input-ioctls
11269 23:23:23.775715 Starting test_set Input-ioctls
11270 23:23:23.778359 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11271 23:23:23.807282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11272 23:23:23.807563 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11274 23:23:23.810584 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11275 23:23:23.830454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11276 23:23:23.830705 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11278 23:23:23.836850 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11279 23:23:23.856487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11280 23:23:23.856740 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11282 23:23:23.863007 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11283 23:23:23.879984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11284 23:23:23.880297 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11286 23:23:23.883262 test VIDIOC_G/S/ENUMINPUT: OK
11287 23:23:23.905276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11288 23:23:23.905584 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11290 23:23:23.908649 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11291 23:23:23.930653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11292 23:23:23.930958 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11294 23:23:23.934058 Inputs: 1 Audio Inputs: 0 Tuners: 0
11295 23:23:23.940784
11296 23:23:23.961193 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11297 23:23:23.983326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11298 23:23:23.983640 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11300 23:23:23.990080 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11301 23:23:24.006883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11302 23:23:24.007187 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11304 23:23:24.010311 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11305 23:23:24.039092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11306 23:23:24.039351 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11308 23:23:24.045870 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11309 23:23:24.064958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11310 23:23:24.065264 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11312 23:23:24.071208 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11313 23:23:24.090490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11314 23:23:24.090617
11315 23:23:24.090904 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11317 23:23:24.109552 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11318 23:23:24.131715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11319 23:23:24.132022 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11321 23:23:24.138434 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11322 23:23:24.163851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11323 23:23:24.164165 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11325 23:23:24.167381 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11326 23:23:24.185505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11327 23:23:24.185810 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11329 23:23:24.188654 test VIDIOC_G/S_EDID: OK (Not Supported)
11330 23:23:24.210286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11331 23:23:24.210415
11332 23:23:24.210706 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11334 23:23:24.220217 Control ioctls (Input 0):
11335 23:23:24.227627 <LAVA_SIGNAL_TESTSET STOP>
11336 23:23:24.227930 Received signal: <TESTSET> STOP
11337 23:23:24.228045 Closing test_set Input-ioctls
11338 23:23:24.236719 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11339 23:23:24.237016 Received signal: <TESTSET> START Control-ioctls-Input-0
11340 23:23:24.237129 Starting test_set Control-ioctls-Input-0
11341 23:23:24.240040 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11342 23:23:24.268714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11343 23:23:24.268845 test VIDIOC_QUERYCTRL: OK
11344 23:23:24.269136 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11346 23:23:24.289726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11347 23:23:24.290033 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11349 23:23:24.293355 test VIDIOC_G/S_CTRL: OK
11350 23:23:24.318446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11351 23:23:24.318751 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11353 23:23:24.321436 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11354 23:23:24.341917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11355 23:23:24.342218 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11357 23:23:24.348720 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11358 23:23:24.371763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11359 23:23:24.372077 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11361 23:23:24.374901 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11362 23:23:24.397562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11363 23:23:24.397870 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11365 23:23:24.400792 Standard Controls: 16 Private Controls: 0
11366 23:23:24.408851
11367 23:23:24.421183 Format ioctls (Input 0):
11368 23:23:24.427759 <LAVA_SIGNAL_TESTSET STOP>
11369 23:23:24.428058 Received signal: <TESTSET> STOP
11370 23:23:24.428177 Closing test_set Control-ioctls-Input-0
11371 23:23:24.437758 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11372 23:23:24.438052 Received signal: <TESTSET> START Format-ioctls-Input-0
11373 23:23:24.438170 Starting test_set Format-ioctls-Input-0
11374 23:23:24.440890 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11375 23:23:24.464247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11376 23:23:24.464644 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11378 23:23:24.467620 test VIDIOC_G/S_PARM: OK
11379 23:23:24.486168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11380 23:23:24.486529 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11382 23:23:24.489248 test VIDIOC_G_FBUF: OK (Not Supported)
11383 23:23:24.511285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11384 23:23:24.511663 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11386 23:23:24.514574 test VIDIOC_G_FMT: OK
11387 23:23:24.536849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11388 23:23:24.537236 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11390 23:23:24.539845 test VIDIOC_TRY_FMT: OK
11391 23:23:24.562342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11392 23:23:24.562717 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11394 23:23:24.568927 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11395 23:23:24.577902 test VIDIOC_S_FMT: OK
11396 23:23:24.602450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11397 23:23:24.602867 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11399 23:23:24.605921 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11400 23:23:24.629069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11401 23:23:24.629450 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11403 23:23:24.632106 test Cropping: OK (Not Supported)
11404 23:23:24.654463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11405 23:23:24.654816 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11407 23:23:24.657499 test Composing: OK (Not Supported)
11408 23:23:24.681505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11409 23:23:24.681823 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11411 23:23:24.684850 test Scaling: OK (Not Supported)
11412 23:23:24.705765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11413 23:23:24.705895
11414 23:23:24.706183 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11416 23:23:24.716269 Codec ioctls (Input 0):
11417 23:23:24.724658 <LAVA_SIGNAL_TESTSET STOP>
11418 23:23:24.724958 Received signal: <TESTSET> STOP
11419 23:23:24.725075 Closing test_set Format-ioctls-Input-0
11420 23:23:24.734775 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11421 23:23:24.735076 Received signal: <TESTSET> START Codec-ioctls-Input-0
11422 23:23:24.735191 Starting test_set Codec-ioctls-Input-0
11423 23:23:24.737969 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11424 23:23:24.760651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11425 23:23:24.760961 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11427 23:23:24.767480 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11428 23:23:24.787559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11429 23:23:24.787879 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11431 23:23:24.793953 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11432 23:23:24.811077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11433 23:23:24.811201
11434 23:23:24.811444 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11436 23:23:24.823425 Buffer ioctls (Input 0):
11437 23:23:24.831721 <LAVA_SIGNAL_TESTSET STOP>
11438 23:23:24.831981 Received signal: <TESTSET> STOP
11439 23:23:24.832052 Closing test_set Codec-ioctls-Input-0
11440 23:23:24.841136 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11441 23:23:24.841389 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11442 23:23:24.841458 Starting test_set Buffer-ioctls-Input-0
11443 23:23:24.844274 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11444 23:23:24.870785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11445 23:23:24.871083 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11447 23:23:24.873647 test CREATE_BUFS maximum buffers: OK
11448 23:23:24.893603 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11450 23:23:24.897000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11451 23:23:24.897091 test VIDIOC_EXPBUF: OK
11452 23:23:24.918769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11453 23:23:24.919022 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11455 23:23:24.922232 test Requests: OK (Not Supported)
11456 23:23:24.941726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11457 23:23:24.941840
11458 23:23:24.942105 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11460 23:23:24.953864 Test input 0:
11461 23:23:24.969446
11462 23:23:24.980105 Streaming ioctls:
11463 23:23:24.987422 <LAVA_SIGNAL_TESTSET STOP>
11464 23:23:24.987675 Received signal: <TESTSET> STOP
11465 23:23:24.987742 Closing test_set Buffer-ioctls-Input-0
11466 23:23:24.996831 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11467 23:23:24.997084 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11468 23:23:24.997152 Starting test_set Streaming-ioctls_Test-input-0
11469 23:23:25.000248 test read/write: OK (Not Supported)
11470 23:23:25.025615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11471 23:23:25.025867 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11473 23:23:25.028527 test blocking wait: OK
11474 23:23:25.050619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11475 23:23:25.050872 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11477 23:23:25.057114 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11478 23:23:25.062264 test MMAP (no poll): FAIL
11479 23:23:25.090467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11480 23:23:25.090758 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11482 23:23:25.096817 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11483 23:23:25.101510 test MMAP (select): FAIL
11484 23:23:25.127280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11485 23:23:25.127542 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11487 23:23:25.133544 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11488 23:23:25.138642 test MMAP (epoll): FAIL
11489 23:23:25.162093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11490 23:23:25.162176
11491 23:23:25.162410 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11493 23:23:25.174536
11494 23:23:25.355791
11495 23:23:25.364838 test USERPTR (no poll): OK
11496 23:23:25.390853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11497 23:23:25.390940
11498 23:23:25.391182 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11500 23:23:25.403134
11501 23:23:25.585277
11502 23:23:25.594060 test USERPTR (select): OK
11503 23:23:25.618914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11504 23:23:25.619174 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11506 23:23:25.625482 test DMABUF: Cannot test, specify --expbuf-device
11507 23:23:25.630122
11508 23:23:25.647168 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11509 23:23:25.651912 <LAVA_TEST_RUNNER EXIT>
11510 23:23:25.652164 ok: lava_test_shell seems to have completed
11511 23:23:25.652237 Marking unfinished test run as failed
11513 23:23:25.653218 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11514 23:23:25.653342 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11515 23:23:25.653427 end: 3 lava-test-retry (duration 00:00:10) [common]
11516 23:23:25.653510 start: 4 finalize (timeout 00:07:51) [common]
11517 23:23:25.653600 start: 4.1 power-off (timeout 00:00:30) [common]
11518 23:23:25.653751 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11519 23:23:25.733253 >> Command sent successfully.
11520 23:23:25.735757 Returned 0 in 0 seconds
11521 23:23:25.836325 end: 4.1 power-off (duration 00:00:00) [common]
11523 23:23:25.836776 start: 4.2 read-feedback (timeout 00:07:50) [common]
11524 23:23:25.837114 Listened to connection for namespace 'common' for up to 1s
11525 23:23:26.838053 Finalising connection for namespace 'common'
11526 23:23:26.838304 Disconnecting from shell: Finalise
11527 23:23:26.838442 / #
11528 23:23:26.938809 end: 4.2 read-feedback (duration 00:00:01) [common]
11529 23:23:26.938976 end: 4 finalize (duration 00:00:01) [common]
11530 23:23:26.939091 Cleaning after the job
11531 23:23:26.939193 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/ramdisk
11532 23:23:26.945197 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/kernel
11533 23:23:26.963054 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/dtb
11534 23:23:26.963314 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248400/tftp-deploy-netd99_i/modules
11535 23:23:26.971002 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248400
11536 23:23:27.046820 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248400
11537 23:23:27.046983 Job finished correctly