Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 27
- Boot result: PASS
1 01:18:06.041317 lava-dispatcher, installed at version: 2024.01
2 01:18:06.041522 start: 0 validate
3 01:18:06.041651 Start time: 2024-04-23 01:18:06.041643+00:00 (UTC)
4 01:18:06.041769 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:18:06.041903 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 01:18:06.313312 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:18:06.314035 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:18:06.572023 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:18:06.572769 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:18:06.832329 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:18:06.833113 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:18:07.342058 validate duration: 1.30
14 01:18:07.343466 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:18:07.344202 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:18:07.344821 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:18:07.345458 Not decompressing ramdisk as can be used compressed.
18 01:18:07.345979 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 01:18:07.346528 saving as /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/ramdisk/rootfs.cpio.gz
20 01:18:07.346965 total size: 8181887 (7 MB)
21 01:18:07.354216 progress 0 % (0 MB)
22 01:18:07.367185 progress 5 % (0 MB)
23 01:18:07.374143 progress 10 % (0 MB)
24 01:18:07.379852 progress 15 % (1 MB)
25 01:18:07.384160 progress 20 % (1 MB)
26 01:18:07.388137 progress 25 % (1 MB)
27 01:18:07.391387 progress 30 % (2 MB)
28 01:18:07.394709 progress 35 % (2 MB)
29 01:18:07.397540 progress 40 % (3 MB)
30 01:18:07.400308 progress 45 % (3 MB)
31 01:18:07.402861 progress 50 % (3 MB)
32 01:18:07.405296 progress 55 % (4 MB)
33 01:18:07.407631 progress 60 % (4 MB)
34 01:18:07.409858 progress 65 % (5 MB)
35 01:18:07.411909 progress 70 % (5 MB)
36 01:18:07.414121 progress 75 % (5 MB)
37 01:18:07.416210 progress 80 % (6 MB)
38 01:18:07.418422 progress 85 % (6 MB)
39 01:18:07.420488 progress 90 % (7 MB)
40 01:18:07.422696 progress 95 % (7 MB)
41 01:18:07.424706 progress 100 % (7 MB)
42 01:18:07.424908 7 MB downloaded in 0.08 s (100.08 MB/s)
43 01:18:07.425059 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:18:07.425299 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:18:07.425387 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:18:07.425470 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:18:07.425607 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:18:07.425680 saving as /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/kernel/Image
50 01:18:07.425741 total size: 54352384 (51 MB)
51 01:18:07.425802 No compression specified
52 01:18:07.426998 progress 0 % (0 MB)
53 01:18:07.440609 progress 5 % (2 MB)
54 01:18:07.454377 progress 10 % (5 MB)
55 01:18:07.468174 progress 15 % (7 MB)
56 01:18:07.482057 progress 20 % (10 MB)
57 01:18:07.495962 progress 25 % (12 MB)
58 01:18:07.509949 progress 30 % (15 MB)
59 01:18:07.523744 progress 35 % (18 MB)
60 01:18:07.537496 progress 40 % (20 MB)
61 01:18:07.551203 progress 45 % (23 MB)
62 01:18:07.564893 progress 50 % (25 MB)
63 01:18:07.578774 progress 55 % (28 MB)
64 01:18:07.592668 progress 60 % (31 MB)
65 01:18:07.606572 progress 65 % (33 MB)
66 01:18:07.620377 progress 70 % (36 MB)
67 01:18:07.634249 progress 75 % (38 MB)
68 01:18:07.647746 progress 80 % (41 MB)
69 01:18:07.661353 progress 85 % (44 MB)
70 01:18:07.675079 progress 90 % (46 MB)
71 01:18:07.688673 progress 95 % (49 MB)
72 01:18:07.702378 progress 100 % (51 MB)
73 01:18:07.702614 51 MB downloaded in 0.28 s (187.22 MB/s)
74 01:18:07.702768 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:18:07.703133 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:18:07.703226 start: 1.3 download-retry (timeout 00:10:00) [common]
78 01:18:07.703319 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 01:18:07.703458 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:18:07.703527 saving as /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/dtb/mt8192-asurada-spherion-r0.dtb
81 01:18:07.703588 total size: 47230 (0 MB)
82 01:18:07.703650 No compression specified
83 01:18:07.704757 progress 69 % (0 MB)
84 01:18:07.705028 progress 100 % (0 MB)
85 01:18:07.705184 0 MB downloaded in 0.00 s (28.28 MB/s)
86 01:18:07.705304 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:18:07.705524 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:18:07.705608 start: 1.4 download-retry (timeout 00:10:00) [common]
90 01:18:07.705690 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 01:18:07.705804 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:18:07.705872 saving as /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/modules/modules.tar
93 01:18:07.705932 total size: 8638160 (8 MB)
94 01:18:07.705993 Using unxz to decompress xz
95 01:18:07.710006 progress 0 % (0 MB)
96 01:18:07.728966 progress 5 % (0 MB)
97 01:18:07.753334 progress 10 % (0 MB)
98 01:18:07.777007 progress 15 % (1 MB)
99 01:18:07.799991 progress 20 % (1 MB)
100 01:18:07.824402 progress 25 % (2 MB)
101 01:18:07.849844 progress 30 % (2 MB)
102 01:18:07.873385 progress 35 % (2 MB)
103 01:18:07.898604 progress 40 % (3 MB)
104 01:18:07.922728 progress 45 % (3 MB)
105 01:18:07.947861 progress 50 % (4 MB)
106 01:18:07.972123 progress 55 % (4 MB)
107 01:18:07.999686 progress 60 % (4 MB)
108 01:18:08.024372 progress 65 % (5 MB)
109 01:18:08.049058 progress 70 % (5 MB)
110 01:18:08.073284 progress 75 % (6 MB)
111 01:18:08.098148 progress 80 % (6 MB)
112 01:18:08.125815 progress 85 % (7 MB)
113 01:18:08.151853 progress 90 % (7 MB)
114 01:18:08.190170 progress 95 % (7 MB)
115 01:18:08.223383 progress 100 % (8 MB)
116 01:18:08.229133 8 MB downloaded in 0.52 s (15.75 MB/s)
117 01:18:08.229389 end: 1.4.1 http-download (duration 00:00:01) [common]
119 01:18:08.229660 end: 1.4 download-retry (duration 00:00:01) [common]
120 01:18:08.229755 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:18:08.229849 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:18:08.229930 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:18:08.230019 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:18:08.230252 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd
125 01:18:08.230434 makedir: /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin
126 01:18:08.230544 makedir: /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/tests
127 01:18:08.230644 makedir: /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/results
128 01:18:08.230763 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-add-keys
129 01:18:08.230908 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-add-sources
130 01:18:08.231038 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-background-process-start
131 01:18:08.231168 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-background-process-stop
132 01:18:08.231291 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-common-functions
133 01:18:08.231413 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-echo-ipv4
134 01:18:08.231537 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-install-packages
135 01:18:08.231660 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-installed-packages
136 01:18:08.231781 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-os-build
137 01:18:08.231902 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-probe-channel
138 01:18:08.232022 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-probe-ip
139 01:18:08.232143 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-target-ip
140 01:18:08.232264 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-target-mac
141 01:18:08.232386 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-target-storage
142 01:18:08.232512 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-test-case
143 01:18:08.232636 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-test-event
144 01:18:08.232756 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-test-feedback
145 01:18:08.232879 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-test-raise
146 01:18:08.233002 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-test-reference
147 01:18:08.233136 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-test-runner
148 01:18:08.233262 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-test-set
149 01:18:08.233386 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-test-shell
150 01:18:08.233513 Updating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-install-packages (oe)
151 01:18:08.233661 Updating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/bin/lava-installed-packages (oe)
152 01:18:08.233778 Creating /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/environment
153 01:18:08.233876 LAVA metadata
154 01:18:08.233949 - LAVA_JOB_ID=13468730
155 01:18:08.234011 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:18:08.234114 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:18:08.234179 skipped lava-vland-overlay
158 01:18:08.234252 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:18:08.234360 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:18:08.234436 skipped lava-multinode-overlay
161 01:18:08.234509 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:18:08.234600 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:18:08.234673 Loading test definitions
164 01:18:08.234761 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:18:08.234831 Using /lava-13468730 at stage 0
166 01:18:08.235154 uuid=13468730_1.5.2.3.1 testdef=None
167 01:18:08.235243 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:18:08.235331 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:18:08.235861 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:18:08.236082 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:18:08.236715 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:18:08.236942 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:18:08.237552 runner path: /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/0/tests/0_dmesg test_uuid 13468730_1.5.2.3.1
176 01:18:08.237709 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:18:08.237912 Creating lava-test-runner.conf files
179 01:18:08.237973 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468730/lava-overlay-p95i11xd/lava-13468730/0 for stage 0
180 01:18:08.238059 - 0_dmesg
181 01:18:08.238153 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:18:08.238240 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 01:18:08.245454 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:18:08.245573 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 01:18:08.245660 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:18:08.245747 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:18:08.245830 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 01:18:08.485795 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 01:18:08.486199 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 01:18:08.486327 extracting modules file /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468730/extract-overlay-ramdisk-uoo76282/ramdisk
191 01:18:08.696397 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:18:08.696571 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
193 01:18:08.696661 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468730/compress-overlay-0x5_fz15/overlay-1.5.2.4.tar.gz to ramdisk
194 01:18:08.696732 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468730/compress-overlay-0x5_fz15/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468730/extract-overlay-ramdisk-uoo76282/ramdisk
195 01:18:08.703423 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:18:08.703536 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
197 01:18:08.703626 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:18:08.703712 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
199 01:18:08.703787 Building ramdisk /var/lib/lava/dispatcher/tmp/13468730/extract-overlay-ramdisk-uoo76282/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468730/extract-overlay-ramdisk-uoo76282/ramdisk
200 01:18:09.049387 >> 145406 blocks
201 01:18:11.364612 rename /var/lib/lava/dispatcher/tmp/13468730/extract-overlay-ramdisk-uoo76282/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/ramdisk/ramdisk.cpio.gz
202 01:18:11.365053 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 01:18:11.365176 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
204 01:18:11.365278 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
205 01:18:11.365390 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/kernel/Image'
206 01:18:24.475730 Returned 0 in 13 seconds
207 01:18:24.576646 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/kernel/image.itb
208 01:18:24.981220 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:18:24.981577 output: Created: Tue Apr 23 02:18:24 2024
210 01:18:24.981651 output: Image 0 (kernel-1)
211 01:18:24.981714 output: Description:
212 01:18:24.981775 output: Created: Tue Apr 23 02:18:24 2024
213 01:18:24.981834 output: Type: Kernel Image
214 01:18:24.981889 output: Compression: lzma compressed
215 01:18:24.981945 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
216 01:18:24.982001 output: Architecture: AArch64
217 01:18:24.982058 output: OS: Linux
218 01:18:24.982111 output: Load Address: 0x00000000
219 01:18:24.982164 output: Entry Point: 0x00000000
220 01:18:24.982222 output: Hash algo: crc32
221 01:18:24.982278 output: Hash value: 1126c3f9
222 01:18:24.982367 output: Image 1 (fdt-1)
223 01:18:24.982437 output: Description: mt8192-asurada-spherion-r0
224 01:18:24.982492 output: Created: Tue Apr 23 02:18:24 2024
225 01:18:24.982544 output: Type: Flat Device Tree
226 01:18:24.982596 output: Compression: uncompressed
227 01:18:24.982648 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 01:18:24.982700 output: Architecture: AArch64
229 01:18:24.982752 output: Hash algo: crc32
230 01:18:24.982804 output: Hash value: 4bf0d1ac
231 01:18:24.982856 output: Image 2 (ramdisk-1)
232 01:18:24.982908 output: Description: unavailable
233 01:18:24.982960 output: Created: Tue Apr 23 02:18:24 2024
234 01:18:24.983012 output: Type: RAMDisk Image
235 01:18:24.983065 output: Compression: Unknown Compression
236 01:18:24.983116 output: Data Size: 21418436 Bytes = 20916.44 KiB = 20.43 MiB
237 01:18:24.983168 output: Architecture: AArch64
238 01:18:24.983219 output: OS: Linux
239 01:18:24.983271 output: Load Address: unavailable
240 01:18:24.983323 output: Entry Point: unavailable
241 01:18:24.983375 output: Hash algo: crc32
242 01:18:24.983426 output: Hash value: 1a8b02f8
243 01:18:24.983478 output: Default Configuration: 'conf-1'
244 01:18:24.983530 output: Configuration 0 (conf-1)
245 01:18:24.983581 output: Description: mt8192-asurada-spherion-r0
246 01:18:24.983633 output: Kernel: kernel-1
247 01:18:24.983685 output: Init Ramdisk: ramdisk-1
248 01:18:24.983736 output: FDT: fdt-1
249 01:18:24.983787 output: Loadables: kernel-1
250 01:18:24.983839 output:
251 01:18:24.984041 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 01:18:24.984143 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 01:18:24.984247 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
254 01:18:24.984343 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
255 01:18:24.984424 No LXC device requested
256 01:18:24.984503 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:18:24.984584 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
258 01:18:24.984658 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:18:24.984724 Checking files for TFTP limit of 4294967296 bytes.
260 01:18:24.985220 end: 1 tftp-deploy (duration 00:00:18) [common]
261 01:18:24.985326 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:18:24.985417 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:18:24.985543 substitutions:
264 01:18:24.985610 - {DTB}: 13468730/tftp-deploy-xde3bg_r/dtb/mt8192-asurada-spherion-r0.dtb
265 01:18:24.985676 - {INITRD}: 13468730/tftp-deploy-xde3bg_r/ramdisk/ramdisk.cpio.gz
266 01:18:24.985735 - {KERNEL}: 13468730/tftp-deploy-xde3bg_r/kernel/Image
267 01:18:24.985792 - {LAVA_MAC}: None
268 01:18:24.985847 - {PRESEED_CONFIG}: None
269 01:18:24.985902 - {PRESEED_LOCAL}: None
270 01:18:24.985957 - {RAMDISK}: 13468730/tftp-deploy-xde3bg_r/ramdisk/ramdisk.cpio.gz
271 01:18:24.986011 - {ROOT_PART}: None
272 01:18:24.986064 - {ROOT}: None
273 01:18:24.986117 - {SERVER_IP}: 192.168.201.1
274 01:18:24.986170 - {TEE}: None
275 01:18:24.986224 Parsed boot commands:
276 01:18:24.986277 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:18:24.986493 Parsed boot commands: tftpboot 192.168.201.1 13468730/tftp-deploy-xde3bg_r/kernel/image.itb 13468730/tftp-deploy-xde3bg_r/kernel/cmdline
278 01:18:24.986632 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:18:24.986758 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:18:24.986854 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:18:24.986940 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:18:24.987009 Not connected, no need to disconnect.
283 01:18:24.987082 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:18:24.987160 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:18:24.987224 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 01:18:24.990974 Setting prompt string to ['lava-test: # ']
287 01:18:24.991337 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:18:24.991450 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:18:24.991547 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:18:24.991633 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:18:24.991825 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 01:18:30.139495 >> Command sent successfully.
293 01:18:30.145694 Returned 0 in 5 seconds
294 01:18:30.246438 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 01:18:30.247900 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 01:18:30.248413 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 01:18:30.248945 Setting prompt string to 'Starting depthcharge on Spherion...'
299 01:18:30.249577 Changing prompt to 'Starting depthcharge on Spherion...'
300 01:18:30.249976 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 01:18:30.251383 [Enter `^Ec?' for help]
302 01:18:30.644908
303 01:18:30.645543
304 01:18:30.645944 F0: 102B 0000
305 01:18:30.646351
306 01:18:30.646724 F3: 1001 0000 [0200]
307 01:18:30.647765
308 01:18:30.648236 F3: 1001 0000
309 01:18:30.648606
310 01:18:30.648948 F7: 102D 0000
311 01:18:30.649329
312 01:18:30.651377 F1: 0000 0000
313 01:18:30.651814
314 01:18:30.652180 V0: 0000 0000 [0001]
315 01:18:30.652517
316 01:18:30.654732 00: 0007 8000
317 01:18:30.655461
318 01:18:30.655948 01: 0000 0000
319 01:18:30.656414
320 01:18:30.657897 BP: 0C00 0209 [0000]
321 01:18:30.658408
322 01:18:30.658891 G0: 1182 0000
323 01:18:30.659346
324 01:18:30.661341 EC: 0000 0021 [4000]
325 01:18:30.661800
326 01:18:30.662239 S7: 0000 0000 [0000]
327 01:18:30.662700
328 01:18:30.664582 CC: 0000 0000 [0001]
329 01:18:30.665021
330 01:18:30.665460 T0: 0000 0040 [010F]
331 01:18:30.665888
332 01:18:30.667817 Jump to BL
333 01:18:30.668256
334 01:18:30.691386
335 01:18:30.691955
336 01:18:30.692453
337 01:18:30.702016 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 01:18:30.705239 ARM64: Exception handlers installed.
339 01:18:30.705823 ARM64: Testing exception
340 01:18:30.708590 ARM64: Done test exception
341 01:18:30.714952 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 01:18:30.725397 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 01:18:30.731824 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 01:18:30.742236 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 01:18:30.748817 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 01:18:30.759174 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 01:18:30.769589 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 01:18:30.775796 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 01:18:30.794889 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 01:18:30.798400 WDT: Last reset was cold boot
351 01:18:30.801596 SPI1(PAD0) initialized at 2873684 Hz
352 01:18:30.804879 SPI5(PAD0) initialized at 992727 Hz
353 01:18:30.808053 VBOOT: Loading verstage.
354 01:18:30.814868 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 01:18:30.818016 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 01:18:30.821410 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 01:18:30.824593 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 01:18:30.831881 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 01:18:30.838936 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 01:18:30.849564 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 01:18:30.850125
362 01:18:30.850560
363 01:18:30.859373 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 01:18:30.862986 ARM64: Exception handlers installed.
365 01:18:30.866204 ARM64: Testing exception
366 01:18:30.866836 ARM64: Done test exception
367 01:18:30.873095 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 01:18:30.876463 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 01:18:30.890256 Probing TPM: . done!
370 01:18:30.893998 TPM ready after 0 ms
371 01:18:30.897384 Connected to device vid:did:rid of 1ae0:0028:00
372 01:18:30.907334 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 01:18:30.991188 Initialized TPM device CR50 revision 0
374 01:18:31.011114 tlcl_send_startup: Startup return code is 0
375 01:18:31.017596 TPM: setup succeeded
376 01:18:31.032320 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 01:18:31.041851 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 01:18:31.053649 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 01:18:31.061825 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 01:18:31.066088 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 01:18:31.069033 in-header: 03 07 00 00 08 00 00 00
382 01:18:31.072330 in-data: aa e4 47 04 13 02 00 00
383 01:18:31.075503 Chrome EC: UHEPI supported
384 01:18:31.082065 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 01:18:31.085940 in-header: 03 ad 00 00 08 00 00 00
386 01:18:31.088649 in-data: 00 20 20 08 00 00 00 00
387 01:18:31.089113 Phase 1
388 01:18:31.092829 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 01:18:31.098950 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 01:18:31.106931 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 01:18:31.107491 Recovery requested (1009000e)
392 01:18:31.114765 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 01:18:31.120623 tlcl_extend: response is 0
394 01:18:31.129838 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 01:18:31.136039 tlcl_extend: response is 0
396 01:18:31.142948 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 01:18:31.162484 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 01:18:31.169540 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 01:18:31.170103
400 01:18:31.170547
401 01:18:31.179359 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 01:18:31.182835 ARM64: Exception handlers installed.
403 01:18:31.185883 ARM64: Testing exception
404 01:18:31.186489 ARM64: Done test exception
405 01:18:31.208336 pmic_efuse_setting: Set efuses in 11 msecs
406 01:18:31.211406 pmwrap_interface_init: Select PMIF_VLD_RDY
407 01:18:31.218454 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 01:18:31.221926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 01:18:31.227934 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 01:18:31.231751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 01:18:31.238161 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 01:18:31.241655 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 01:18:31.245609 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 01:18:31.252055 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 01:18:31.255146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 01:18:31.261527 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 01:18:31.264754 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 01:18:31.267987 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 01:18:31.275127 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 01:18:31.281513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 01:18:31.285314 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 01:18:31.292231 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 01:18:31.298718 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 01:18:31.301612 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 01:18:31.308531 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 01:18:31.315188 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 01:18:31.318282 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 01:18:31.325019 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 01:18:31.331419 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 01:18:31.335289 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 01:18:31.342370 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 01:18:31.348253 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 01:18:31.352129 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 01:18:31.358775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 01:18:31.361732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 01:18:31.368638 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 01:18:31.371951 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 01:18:31.378492 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 01:18:31.381834 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 01:18:31.388050 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 01:18:31.392178 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 01:18:31.398240 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 01:18:31.401962 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 01:18:31.408425 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 01:18:31.411976 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 01:18:31.415231 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 01:18:31.422036 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 01:18:31.425401 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 01:18:31.428715 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 01:18:31.431856 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 01:18:31.438675 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 01:18:31.441885 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 01:18:31.445118 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 01:18:31.451838 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 01:18:31.455514 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 01:18:31.458692 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 01:18:31.461858 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 01:18:31.472154 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 01:18:31.478457 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 01:18:31.485300 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 01:18:31.491668 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 01:18:31.502223 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 01:18:31.505424 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 01:18:31.508893 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 01:18:31.515206 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 01:18:31.521583 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde71, sec=0x26
467 01:18:31.528834 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
468 01:18:31.531458 [RTC]rtc_osc_init,62: osc32con val = 0xde71
469 01:18:31.535208 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 01:18:31.546030 [RTC]rtc_get_frequency_meter,154: input=15, output=761
471 01:18:31.555103 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 01:18:31.564671 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 01:18:31.574233 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 01:18:31.583713 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 01:18:31.593236 [RTC]rtc_get_frequency_meter,154: input=16, output=781
476 01:18:31.602710 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 01:18:31.605993 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 01:18:31.613402 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 01:18:31.616330 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 01:18:31.619580 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 01:18:31.626249 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 01:18:31.629716 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 01:18:31.633653 ADC[4]: Raw value=906573 ID=7
484 01:18:31.634225 ADC[3]: Raw value=213441 ID=1
485 01:18:31.636428 RAM Code: 0x71
486 01:18:31.639372 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 01:18:31.646543 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 01:18:31.653643 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 01:18:31.660099 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 01:18:31.663469 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 01:18:31.666278 in-header: 03 07 00 00 08 00 00 00
492 01:18:31.670072 in-data: aa e4 47 04 13 02 00 00
493 01:18:31.673101 Chrome EC: UHEPI supported
494 01:18:31.680252 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 01:18:31.683269 in-header: 03 ed 00 00 08 00 00 00
496 01:18:31.687209 in-data: 80 20 60 08 00 00 00 00
497 01:18:31.690363 MRC: failed to locate region type 0.
498 01:18:31.697706 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 01:18:31.698287 DRAM-K: Running full calibration
500 01:18:31.705219 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 01:18:31.708978 header.status = 0x0
502 01:18:31.709459 header.version = 0x6 (expected: 0x6)
503 01:18:31.712622 header.size = 0xd00 (expected: 0xd00)
504 01:18:31.715972 header.flags = 0x0
505 01:18:31.723141 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 01:18:31.739398 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 01:18:31.746048 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 01:18:31.749370 dram_init: ddr_geometry: 2
509 01:18:31.752494 [EMI] MDL number = 2
510 01:18:31.753063 [EMI] Get MDL freq = 0
511 01:18:31.755867 dram_init: ddr_type: 0
512 01:18:31.756352 is_discrete_lpddr4: 1
513 01:18:31.759323 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 01:18:31.759808
515 01:18:31.760290
516 01:18:31.762271 [Bian_co] ETT version 0.0.0.1
517 01:18:31.769432 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 01:18:31.770003
519 01:18:31.772401 dramc_set_vcore_voltage set vcore to 650000
520 01:18:31.772867 Read voltage for 800, 4
521 01:18:31.775611 Vio18 = 0
522 01:18:31.776073 Vcore = 650000
523 01:18:31.776495 Vdram = 0
524 01:18:31.778990 Vddq = 0
525 01:18:31.779453 Vmddr = 0
526 01:18:31.783050 dram_init: config_dvfs: 1
527 01:18:31.786107 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 01:18:31.792692 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 01:18:31.796067 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 01:18:31.799064 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 01:18:31.803217 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 01:18:31.805875 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 01:18:31.809458 MEM_TYPE=3, freq_sel=18
534 01:18:31.812887 sv_algorithm_assistance_LP4_1600
535 01:18:31.815902 ============ PULL DRAM RESETB DOWN ============
536 01:18:31.819199 ========== PULL DRAM RESETB DOWN end =========
537 01:18:31.825810 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 01:18:31.829258 ===================================
539 01:18:31.832954 LPDDR4 DRAM CONFIGURATION
540 01:18:31.835957 ===================================
541 01:18:31.836428 EX_ROW_EN[0] = 0x0
542 01:18:31.839275 EX_ROW_EN[1] = 0x0
543 01:18:31.839821 LP4Y_EN = 0x0
544 01:18:31.842692 WORK_FSP = 0x0
545 01:18:31.843252 WL = 0x2
546 01:18:31.846236 RL = 0x2
547 01:18:31.846841 BL = 0x2
548 01:18:31.849232 RPST = 0x0
549 01:18:31.849952 RD_PRE = 0x0
550 01:18:31.852775 WR_PRE = 0x1
551 01:18:31.853237 WR_PST = 0x0
552 01:18:31.855559 DBI_WR = 0x0
553 01:18:31.856102 DBI_RD = 0x0
554 01:18:31.858899 OTF = 0x1
555 01:18:31.862362 ===================================
556 01:18:31.865809 ===================================
557 01:18:31.866276 ANA top config
558 01:18:31.869444 ===================================
559 01:18:31.872374 DLL_ASYNC_EN = 0
560 01:18:31.875995 ALL_SLAVE_EN = 1
561 01:18:31.879504 NEW_RANK_MODE = 1
562 01:18:31.879973 DLL_IDLE_MODE = 1
563 01:18:31.882996 LP45_APHY_COMB_EN = 1
564 01:18:31.886198 TX_ODT_DIS = 1
565 01:18:31.889444 NEW_8X_MODE = 1
566 01:18:31.893330 ===================================
567 01:18:31.893910 ===================================
568 01:18:31.896787 data_rate = 1600
569 01:18:31.900698 CKR = 1
570 01:18:31.904753 DQ_P2S_RATIO = 8
571 01:18:31.908080 ===================================
572 01:18:31.908556 CA_P2S_RATIO = 8
573 01:18:31.911815 DQ_CA_OPEN = 0
574 01:18:31.915791 DQ_SEMI_OPEN = 0
575 01:18:31.919045 CA_SEMI_OPEN = 0
576 01:18:31.919525 CA_FULL_RATE = 0
577 01:18:31.923049 DQ_CKDIV4_EN = 1
578 01:18:31.927097 CA_CKDIV4_EN = 1
579 01:18:31.930388 CA_PREDIV_EN = 0
580 01:18:31.930968 PH8_DLY = 0
581 01:18:31.934130 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 01:18:31.936750 DQ_AAMCK_DIV = 4
583 01:18:31.940915 CA_AAMCK_DIV = 4
584 01:18:31.944148 CA_ADMCK_DIV = 4
585 01:18:31.944715 DQ_TRACK_CA_EN = 0
586 01:18:31.947473 CA_PICK = 800
587 01:18:31.950880 CA_MCKIO = 800
588 01:18:31.953944 MCKIO_SEMI = 0
589 01:18:31.956707 PLL_FREQ = 3068
590 01:18:31.960780 DQ_UI_PI_RATIO = 32
591 01:18:31.963910 CA_UI_PI_RATIO = 0
592 01:18:31.967625 ===================================
593 01:18:31.970091 ===================================
594 01:18:31.970597 memory_type:LPDDR4
595 01:18:31.973584 GP_NUM : 10
596 01:18:31.977519 SRAM_EN : 1
597 01:18:31.978240 MD32_EN : 0
598 01:18:31.980570 ===================================
599 01:18:31.983766 [ANA_INIT] >>>>>>>>>>>>>>
600 01:18:31.986811 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 01:18:31.990653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 01:18:31.994100 ===================================
603 01:18:31.994619 data_rate = 1600,PCW = 0X7600
604 01:18:31.998417 ===================================
605 01:18:32.001746 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 01:18:32.009448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 01:18:32.012293 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 01:18:32.019672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 01:18:32.020143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 01:18:32.023689 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 01:18:32.027061 [ANA_INIT] flow start
612 01:18:32.030800 [ANA_INIT] PLL >>>>>>>>
613 01:18:32.031267 [ANA_INIT] PLL <<<<<<<<
614 01:18:32.034454 [ANA_INIT] MIDPI >>>>>>>>
615 01:18:32.034878 [ANA_INIT] MIDPI <<<<<<<<
616 01:18:32.038339 [ANA_INIT] DLL >>>>>>>>
617 01:18:32.042102 [ANA_INIT] flow end
618 01:18:32.045855 ============ LP4 DIFF to SE enter ============
619 01:18:32.049485 ============ LP4 DIFF to SE exit ============
620 01:18:32.053149 [ANA_INIT] <<<<<<<<<<<<<
621 01:18:32.053731 [Flow] Enable top DCM control >>>>>
622 01:18:32.056301 [Flow] Enable top DCM control <<<<<
623 01:18:32.060254 Enable DLL master slave shuffle
624 01:18:32.067483 ==============================================================
625 01:18:32.067974 Gating Mode config
626 01:18:32.074998 ==============================================================
627 01:18:32.075479 Config description:
628 01:18:32.086618 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 01:18:32.090447 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 01:18:32.097922 SELPH_MODE 0: By rank 1: By Phase
631 01:18:32.101560 ==============================================================
632 01:18:32.104352 GAT_TRACK_EN = 1
633 01:18:32.107524 RX_GATING_MODE = 2
634 01:18:32.111419 RX_GATING_TRACK_MODE = 2
635 01:18:32.114420 SELPH_MODE = 1
636 01:18:32.118495 PICG_EARLY_EN = 1
637 01:18:32.119091 VALID_LAT_VALUE = 1
638 01:18:32.125594 ==============================================================
639 01:18:32.128940 Enter into Gating configuration >>>>
640 01:18:32.131684 Exit from Gating configuration <<<<
641 01:18:32.135358 Enter into DVFS_PRE_config >>>>>
642 01:18:32.145737 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 01:18:32.149074 Exit from DVFS_PRE_config <<<<<
644 01:18:32.152023 Enter into PICG configuration >>>>
645 01:18:32.155516 Exit from PICG configuration <<<<
646 01:18:32.158608 [RX_INPUT] configuration >>>>>
647 01:18:32.162035 [RX_INPUT] configuration <<<<<
648 01:18:32.165560 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 01:18:32.172402 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 01:18:32.179215 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 01:18:32.183196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 01:18:32.190220 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 01:18:32.197284 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 01:18:32.201216 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 01:18:32.205049 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 01:18:32.208741 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 01:18:32.212212 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 01:18:32.215980 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 01:18:32.223156 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 01:18:32.223716 ===================================
661 01:18:32.226814 LPDDR4 DRAM CONFIGURATION
662 01:18:32.230267 ===================================
663 01:18:32.230781 EX_ROW_EN[0] = 0x0
664 01:18:32.233977 EX_ROW_EN[1] = 0x0
665 01:18:32.237777 LP4Y_EN = 0x0
666 01:18:32.238245 WORK_FSP = 0x0
667 01:18:32.238670 WL = 0x2
668 01:18:32.241997 RL = 0x2
669 01:18:32.242642 BL = 0x2
670 01:18:32.245683 RPST = 0x0
671 01:18:32.246149 RD_PRE = 0x0
672 01:18:32.249942 WR_PRE = 0x1
673 01:18:32.250557 WR_PST = 0x0
674 01:18:32.252972 DBI_WR = 0x0
675 01:18:32.253529 DBI_RD = 0x0
676 01:18:32.256695 OTF = 0x1
677 01:18:32.257190 ===================================
678 01:18:32.260774 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 01:18:32.267728 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 01:18:32.271701 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 01:18:32.275217 ===================================
682 01:18:32.275656 LPDDR4 DRAM CONFIGURATION
683 01:18:32.279166 ===================================
684 01:18:32.282632 EX_ROW_EN[0] = 0x10
685 01:18:32.283051 EX_ROW_EN[1] = 0x0
686 01:18:32.286460 LP4Y_EN = 0x0
687 01:18:32.286978 WORK_FSP = 0x0
688 01:18:32.290028 WL = 0x2
689 01:18:32.290490 RL = 0x2
690 01:18:32.293336 BL = 0x2
691 01:18:32.293757 RPST = 0x0
692 01:18:32.297076 RD_PRE = 0x0
693 01:18:32.297632 WR_PRE = 0x1
694 01:18:32.300903 WR_PST = 0x0
695 01:18:32.301324 DBI_WR = 0x0
696 01:18:32.304082 DBI_RD = 0x0
697 01:18:32.304509 OTF = 0x1
698 01:18:32.307953 ===================================
699 01:18:32.314919 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 01:18:32.319108 nWR fixed to 40
701 01:18:32.319629 [ModeRegInit_LP4] CH0 RK0
702 01:18:32.322512 [ModeRegInit_LP4] CH0 RK1
703 01:18:32.325738 [ModeRegInit_LP4] CH1 RK0
704 01:18:32.326355 [ModeRegInit_LP4] CH1 RK1
705 01:18:32.329392 match AC timing 13
706 01:18:32.332700 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 01:18:32.336888 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 01:18:32.340434 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 01:18:32.348350 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 01:18:32.352073 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 01:18:32.352499 [EMI DOE] emi_dcm 0
712 01:18:32.355577 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 01:18:32.359243 ==
714 01:18:32.359664 Dram Type= 6, Freq= 0, CH_0, rank 0
715 01:18:32.366281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 01:18:32.366747 ==
717 01:18:32.369760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 01:18:32.376829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 01:18:32.385933 [CA 0] Center 36 (6~67) winsize 62
720 01:18:32.388769 [CA 1] Center 36 (6~67) winsize 62
721 01:18:32.392713 [CA 2] Center 34 (4~65) winsize 62
722 01:18:32.396748 [CA 3] Center 33 (3~64) winsize 62
723 01:18:32.400367 [CA 4] Center 33 (3~64) winsize 62
724 01:18:32.404552 [CA 5] Center 32 (3~62) winsize 60
725 01:18:32.405115
726 01:18:32.407589 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 01:18:32.408059
728 01:18:32.411179 [CATrainingPosCal] consider 1 rank data
729 01:18:32.411766 u2DelayCellTimex100 = 270/100 ps
730 01:18:32.414756 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 01:18:32.418462 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 01:18:32.422326 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 01:18:32.426101 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 01:18:32.429771 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 01:18:32.433705 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 01:18:32.434144
737 01:18:32.437722 CA PerBit enable=1, Macro0, CA PI delay=32
738 01:18:32.438160
739 01:18:32.441320 [CBTSetCACLKResult] CA Dly = 32
740 01:18:32.445346 CS Dly: 5 (0~36)
741 01:18:32.445880 ==
742 01:18:32.446359 Dram Type= 6, Freq= 0, CH_0, rank 1
743 01:18:32.452575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 01:18:32.453016 ==
745 01:18:32.455990 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 01:18:32.463330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 01:18:32.471643 [CA 0] Center 36 (6~67) winsize 62
748 01:18:32.475632 [CA 1] Center 36 (6~67) winsize 62
749 01:18:32.478926 [CA 2] Center 34 (3~65) winsize 63
750 01:18:32.482676 [CA 3] Center 33 (3~64) winsize 62
751 01:18:32.486632 [CA 4] Center 33 (3~63) winsize 61
752 01:18:32.487072 [CA 5] Center 32 (2~63) winsize 62
753 01:18:32.490042
754 01:18:32.493805 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 01:18:32.494241
756 01:18:32.497876 [CATrainingPosCal] consider 2 rank data
757 01:18:32.498350 u2DelayCellTimex100 = 270/100 ps
758 01:18:32.501093 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 01:18:32.505577 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 01:18:32.509533 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 01:18:32.513031 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 01:18:32.517049 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 01:18:32.520176 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 01:18:32.520606
765 01:18:32.524190 CA PerBit enable=1, Macro0, CA PI delay=32
766 01:18:32.524637
767 01:18:32.527716 [CBTSetCACLKResult] CA Dly = 32
768 01:18:32.528187 CS Dly: 5 (0~37)
769 01:18:32.528637
770 01:18:32.530975 ----->DramcWriteLeveling(PI) begin...
771 01:18:32.535135 ==
772 01:18:32.535694 Dram Type= 6, Freq= 0, CH_0, rank 0
773 01:18:32.539043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 01:18:32.542407 ==
775 01:18:32.542933 Write leveling (Byte 0): 33 => 33
776 01:18:32.546421 Write leveling (Byte 1): 31 => 31
777 01:18:32.550118 DramcWriteLeveling(PI) end<-----
778 01:18:32.550610
779 01:18:32.551067 ==
780 01:18:32.554180 Dram Type= 6, Freq= 0, CH_0, rank 0
781 01:18:32.557635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 01:18:32.558075 ==
783 01:18:32.561191 [Gating] SW mode calibration
784 01:18:32.569153 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 01:18:32.572751 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 01:18:32.576849 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 01:18:32.580851 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 01:18:32.587792 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 01:18:32.591665 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 01:18:32.595591 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 01:18:32.599396 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 01:18:32.603173 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 01:18:32.607024 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 01:18:32.614662 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 01:18:32.618574 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 01:18:32.622012 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 01:18:32.626190 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 01:18:32.629855 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 01:18:32.633980 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 01:18:32.637550 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 01:18:32.644486 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 01:18:32.647973 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 01:18:32.652052 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 01:18:32.655984 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 01:18:32.659471 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 01:18:32.663496 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 01:18:32.671058 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 01:18:32.674387 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 01:18:32.677882 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 01:18:32.681802 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 01:18:32.686151 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 01:18:32.692943 0 9 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
813 01:18:32.696809 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
814 01:18:32.701091 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 01:18:32.704314 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 01:18:32.708369 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 01:18:32.712374 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 01:18:32.719704 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 01:18:32.723376 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
820 01:18:32.727072 0 10 8 | B1->B0 | 3131 2828 | 0 0 | (1 0) (0 0)
821 01:18:32.729916 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 01:18:32.733915 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 01:18:32.741415 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 01:18:32.744594 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 01:18:32.747819 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 01:18:32.754440 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 01:18:32.757831 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 01:18:32.761263 0 11 8 | B1->B0 | 2828 3e3e | 1 1 | (0 0) (0 0)
829 01:18:32.764206 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
830 01:18:32.771436 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 01:18:32.774432 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 01:18:32.777458 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 01:18:32.784368 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 01:18:32.787996 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 01:18:32.791014 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 01:18:32.798132 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 01:18:32.801171 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 01:18:32.804624 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 01:18:32.811202 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 01:18:32.814465 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 01:18:32.817864 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 01:18:32.824274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 01:18:32.827366 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 01:18:32.830976 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 01:18:32.837563 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 01:18:32.841036 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 01:18:32.844285 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 01:18:32.851490 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 01:18:32.854970 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 01:18:32.857998 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 01:18:32.861300 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 01:18:32.867660 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
853 01:18:32.871550 Total UI for P1: 0, mck2ui 16
854 01:18:32.874999 best dqsien dly found for B0: ( 0, 14, 6)
855 01:18:32.877944 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 01:18:32.881269 Total UI for P1: 0, mck2ui 16
857 01:18:32.884875 best dqsien dly found for B1: ( 0, 14, 10)
858 01:18:32.887913 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 01:18:32.891600 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 01:18:32.892076
861 01:18:32.894747 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 01:18:32.897902 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 01:18:32.901347 [Gating] SW calibration Done
864 01:18:32.901997 ==
865 01:18:32.904997 Dram Type= 6, Freq= 0, CH_0, rank 0
866 01:18:32.907639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 01:18:32.911305 ==
868 01:18:32.911869 RX Vref Scan: 0
869 01:18:32.912247
870 01:18:32.914433 RX Vref 0 -> 0, step: 1
871 01:18:32.914903
872 01:18:32.918046 RX Delay -130 -> 252, step: 16
873 01:18:32.921836 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 01:18:32.924941 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 01:18:32.927867 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 01:18:32.931775 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 01:18:32.935952 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 01:18:32.939287 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 01:18:32.943516 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
880 01:18:32.946800 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 01:18:32.954012 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
882 01:18:32.958196 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 01:18:32.961521 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
884 01:18:32.965406 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 01:18:32.968593 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
886 01:18:32.972181 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 01:18:32.975549 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 01:18:32.982200 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
889 01:18:32.982826 ==
890 01:18:32.985753 Dram Type= 6, Freq= 0, CH_0, rank 0
891 01:18:32.988643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 01:18:32.989173 ==
893 01:18:32.989548 DQS Delay:
894 01:18:32.991695 DQS0 = 0, DQS1 = 0
895 01:18:32.992163 DQM Delay:
896 01:18:32.995251 DQM0 = 91, DQM1 = 84
897 01:18:32.995724 DQ Delay:
898 01:18:32.998707 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
899 01:18:33.001992 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
900 01:18:33.005368 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
901 01:18:33.009172 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 01:18:33.009697
903 01:18:33.010037
904 01:18:33.010403 ==
905 01:18:33.012330 Dram Type= 6, Freq= 0, CH_0, rank 0
906 01:18:33.015201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 01:18:33.015709 ==
908 01:18:33.016057
909 01:18:33.019095
910 01:18:33.019610 TX Vref Scan disable
911 01:18:33.022481 == TX Byte 0 ==
912 01:18:33.025856 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 01:18:33.028840 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 01:18:33.032213 == TX Byte 1 ==
915 01:18:33.035388 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 01:18:33.038901 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 01:18:33.039424 ==
918 01:18:33.042711 Dram Type= 6, Freq= 0, CH_0, rank 0
919 01:18:33.049146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 01:18:33.049709 ==
921 01:18:33.061083 TX Vref=22, minBit 7, minWin=27, winSum=447
922 01:18:33.063631 TX Vref=24, minBit 10, minWin=27, winSum=452
923 01:18:33.066997 TX Vref=26, minBit 0, minWin=28, winSum=455
924 01:18:33.070761 TX Vref=28, minBit 8, minWin=28, winSum=458
925 01:18:33.074089 TX Vref=30, minBit 8, minWin=28, winSum=458
926 01:18:33.080904 TX Vref=32, minBit 5, minWin=28, winSum=458
927 01:18:33.083979 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28
928 01:18:33.084484
929 01:18:33.087472 Final TX Range 1 Vref 28
930 01:18:33.087972
931 01:18:33.088339 ==
932 01:18:33.090368 Dram Type= 6, Freq= 0, CH_0, rank 0
933 01:18:33.094104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 01:18:33.094661 ==
935 01:18:33.095050
936 01:18:33.097446
937 01:18:33.098003 TX Vref Scan disable
938 01:18:33.100149 == TX Byte 0 ==
939 01:18:33.103709 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 01:18:33.107712 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 01:18:33.110921 == TX Byte 1 ==
942 01:18:33.114268 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 01:18:33.118020 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 01:18:33.118533
945 01:18:33.121293 [DATLAT]
946 01:18:33.121907 Freq=800, CH0 RK0
947 01:18:33.122284
948 01:18:33.124851 DATLAT Default: 0xa
949 01:18:33.125426 0, 0xFFFF, sum = 0
950 01:18:33.128013 1, 0xFFFF, sum = 0
951 01:18:33.128484 2, 0xFFFF, sum = 0
952 01:18:33.131574 3, 0xFFFF, sum = 0
953 01:18:33.132143 4, 0xFFFF, sum = 0
954 01:18:33.134269 5, 0xFFFF, sum = 0
955 01:18:33.134803 6, 0xFFFF, sum = 0
956 01:18:33.138121 7, 0xFFFF, sum = 0
957 01:18:33.138771 8, 0xFFFF, sum = 0
958 01:18:33.141186 9, 0x0, sum = 1
959 01:18:33.141679 10, 0x0, sum = 2
960 01:18:33.144810 11, 0x0, sum = 3
961 01:18:33.145393 12, 0x0, sum = 4
962 01:18:33.148064 best_step = 10
963 01:18:33.148529
964 01:18:33.148891 ==
965 01:18:33.151429 Dram Type= 6, Freq= 0, CH_0, rank 0
966 01:18:33.154688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 01:18:33.155310 ==
968 01:18:33.157806 RX Vref Scan: 1
969 01:18:33.158431
970 01:18:33.158815 Set Vref Range= 32 -> 127
971 01:18:33.159166
972 01:18:33.161014 RX Vref 32 -> 127, step: 1
973 01:18:33.161479
974 01:18:33.164380 RX Delay -95 -> 252, step: 8
975 01:18:33.164938
976 01:18:33.167648 Set Vref, RX VrefLevel [Byte0]: 32
977 01:18:33.170891 [Byte1]: 32
978 01:18:33.171392
979 01:18:33.174739 Set Vref, RX VrefLevel [Byte0]: 33
980 01:18:33.177721 [Byte1]: 33
981 01:18:33.178292
982 01:18:33.181515 Set Vref, RX VrefLevel [Byte0]: 34
983 01:18:33.184053 [Byte1]: 34
984 01:18:33.188578
985 01:18:33.189134 Set Vref, RX VrefLevel [Byte0]: 35
986 01:18:33.192023 [Byte1]: 35
987 01:18:33.196237
988 01:18:33.196804 Set Vref, RX VrefLevel [Byte0]: 36
989 01:18:33.199517 [Byte1]: 36
990 01:18:33.203997
991 01:18:33.204463 Set Vref, RX VrefLevel [Byte0]: 37
992 01:18:33.206694 [Byte1]: 37
993 01:18:33.211539
994 01:18:33.212087 Set Vref, RX VrefLevel [Byte0]: 38
995 01:18:33.214796 [Byte1]: 38
996 01:18:33.218810
997 01:18:33.219271 Set Vref, RX VrefLevel [Byte0]: 39
998 01:18:33.222348 [Byte1]: 39
999 01:18:33.226541
1000 01:18:33.227106 Set Vref, RX VrefLevel [Byte0]: 40
1001 01:18:33.229907 [Byte1]: 40
1002 01:18:33.234211
1003 01:18:33.234723 Set Vref, RX VrefLevel [Byte0]: 41
1004 01:18:33.237487 [Byte1]: 41
1005 01:18:33.241730
1006 01:18:33.242195 Set Vref, RX VrefLevel [Byte0]: 42
1007 01:18:33.244907 [Byte1]: 42
1008 01:18:33.249633
1009 01:18:33.250195 Set Vref, RX VrefLevel [Byte0]: 43
1010 01:18:33.252909 [Byte1]: 43
1011 01:18:33.256912
1012 01:18:33.257474 Set Vref, RX VrefLevel [Byte0]: 44
1013 01:18:33.259854 [Byte1]: 44
1014 01:18:33.264393
1015 01:18:33.264988 Set Vref, RX VrefLevel [Byte0]: 45
1016 01:18:33.268040 [Byte1]: 45
1017 01:18:33.271773
1018 01:18:33.272240 Set Vref, RX VrefLevel [Byte0]: 46
1019 01:18:33.274982 [Byte1]: 46
1020 01:18:33.279579
1021 01:18:33.280096 Set Vref, RX VrefLevel [Byte0]: 47
1022 01:18:33.282615 [Byte1]: 47
1023 01:18:33.287384
1024 01:18:33.287947 Set Vref, RX VrefLevel [Byte0]: 48
1025 01:18:33.290168 [Byte1]: 48
1026 01:18:33.294794
1027 01:18:33.295250 Set Vref, RX VrefLevel [Byte0]: 49
1028 01:18:33.298476 [Byte1]: 49
1029 01:18:33.302411
1030 01:18:33.302867 Set Vref, RX VrefLevel [Byte0]: 50
1031 01:18:33.305450 [Byte1]: 50
1032 01:18:33.310232
1033 01:18:33.310830 Set Vref, RX VrefLevel [Byte0]: 51
1034 01:18:33.313210 [Byte1]: 51
1035 01:18:33.317677
1036 01:18:33.318151 Set Vref, RX VrefLevel [Byte0]: 52
1037 01:18:33.321079 [Byte1]: 52
1038 01:18:33.325425
1039 01:18:33.325972 Set Vref, RX VrefLevel [Byte0]: 53
1040 01:18:33.328644 [Byte1]: 53
1041 01:18:33.332602
1042 01:18:33.333060 Set Vref, RX VrefLevel [Byte0]: 54
1043 01:18:33.335956 [Byte1]: 54
1044 01:18:33.340588
1045 01:18:33.341228 Set Vref, RX VrefLevel [Byte0]: 55
1046 01:18:33.343823 [Byte1]: 55
1047 01:18:33.348211
1048 01:18:33.348667 Set Vref, RX VrefLevel [Byte0]: 56
1049 01:18:33.351428 [Byte1]: 56
1050 01:18:33.355521
1051 01:18:33.356066 Set Vref, RX VrefLevel [Byte0]: 57
1052 01:18:33.359209 [Byte1]: 57
1053 01:18:33.363080
1054 01:18:33.363538 Set Vref, RX VrefLevel [Byte0]: 58
1055 01:18:33.366345 [Byte1]: 58
1056 01:18:33.370669
1057 01:18:33.371125 Set Vref, RX VrefLevel [Byte0]: 59
1058 01:18:33.373972 [Byte1]: 59
1059 01:18:33.378373
1060 01:18:33.378831 Set Vref, RX VrefLevel [Byte0]: 60
1061 01:18:33.381673 [Byte1]: 60
1062 01:18:33.386208
1063 01:18:33.386863 Set Vref, RX VrefLevel [Byte0]: 61
1064 01:18:33.389348 [Byte1]: 61
1065 01:18:33.393732
1066 01:18:33.394188 Set Vref, RX VrefLevel [Byte0]: 62
1067 01:18:33.397125 [Byte1]: 62
1068 01:18:33.400873
1069 01:18:33.401328 Set Vref, RX VrefLevel [Byte0]: 63
1070 01:18:33.404708 [Byte1]: 63
1071 01:18:33.409308
1072 01:18:33.409865 Set Vref, RX VrefLevel [Byte0]: 64
1073 01:18:33.412332 [Byte1]: 64
1074 01:18:33.416596
1075 01:18:33.417256 Set Vref, RX VrefLevel [Byte0]: 65
1076 01:18:33.419973 [Byte1]: 65
1077 01:18:33.423734
1078 01:18:33.424365 Set Vref, RX VrefLevel [Byte0]: 66
1079 01:18:33.427265 [Byte1]: 66
1080 01:18:33.431726
1081 01:18:33.432330 Set Vref, RX VrefLevel [Byte0]: 67
1082 01:18:33.434655 [Byte1]: 67
1083 01:18:33.439327
1084 01:18:33.439874 Set Vref, RX VrefLevel [Byte0]: 68
1085 01:18:33.443016 [Byte1]: 68
1086 01:18:33.446972
1087 01:18:33.447517 Set Vref, RX VrefLevel [Byte0]: 69
1088 01:18:33.450055 [Byte1]: 69
1089 01:18:33.454533
1090 01:18:33.455079 Set Vref, RX VrefLevel [Byte0]: 70
1091 01:18:33.458012 [Byte1]: 70
1092 01:18:33.462148
1093 01:18:33.462652 Set Vref, RX VrefLevel [Byte0]: 71
1094 01:18:33.465293 [Byte1]: 71
1095 01:18:33.469298
1096 01:18:33.469754 Set Vref, RX VrefLevel [Byte0]: 72
1097 01:18:33.473352 [Byte1]: 72
1098 01:18:33.477273
1099 01:18:33.477836 Set Vref, RX VrefLevel [Byte0]: 73
1100 01:18:33.480220 [Byte1]: 73
1101 01:18:33.485075
1102 01:18:33.485618 Set Vref, RX VrefLevel [Byte0]: 74
1103 01:18:33.488204 [Byte1]: 74
1104 01:18:33.492665
1105 01:18:33.493213 Set Vref, RX VrefLevel [Byte0]: 75
1106 01:18:33.495648 [Byte1]: 75
1107 01:18:33.499954
1108 01:18:33.500506 Set Vref, RX VrefLevel [Byte0]: 76
1109 01:18:33.503708 [Byte1]: 76
1110 01:18:33.508372
1111 01:18:33.508920 Set Vref, RX VrefLevel [Byte0]: 77
1112 01:18:33.511225 [Byte1]: 77
1113 01:18:33.515384
1114 01:18:33.515842 Final RX Vref Byte 0 = 49 to rank0
1115 01:18:33.518989 Final RX Vref Byte 1 = 58 to rank0
1116 01:18:33.522712 Final RX Vref Byte 0 = 49 to rank1
1117 01:18:33.526697 Final RX Vref Byte 1 = 58 to rank1==
1118 01:18:33.529694 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 01:18:33.532733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 01:18:33.533201 ==
1121 01:18:33.535995 DQS Delay:
1122 01:18:33.536456 DQS0 = 0, DQS1 = 0
1123 01:18:33.536820 DQM Delay:
1124 01:18:33.540655 DQM0 = 91, DQM1 = 85
1125 01:18:33.541116 DQ Delay:
1126 01:18:33.543886 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1127 01:18:33.546859 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1128 01:18:33.550802 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1129 01:18:33.553929 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1130 01:18:33.554519
1131 01:18:33.554948
1132 01:18:33.564093 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a40, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1133 01:18:33.564649 CH0 RK0: MR19=606, MR18=4A40
1134 01:18:33.570214 CH0_RK0: MR19=0x606, MR18=0x4A40, DQSOSC=391, MR23=63, INC=96, DEC=64
1135 01:18:33.570716
1136 01:18:33.573655 ----->DramcWriteLeveling(PI) begin...
1137 01:18:33.574120 ==
1138 01:18:33.577042 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 01:18:33.583626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 01:18:33.584089 ==
1141 01:18:33.587410 Write leveling (Byte 0): 33 => 33
1142 01:18:33.587960 Write leveling (Byte 1): 30 => 30
1143 01:18:33.590938 DramcWriteLeveling(PI) end<-----
1144 01:18:33.591491
1145 01:18:33.591852 ==
1146 01:18:33.593926 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 01:18:33.600327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 01:18:33.600883 ==
1149 01:18:33.603654 [Gating] SW mode calibration
1150 01:18:33.610536 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 01:18:33.613712 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 01:18:33.617024 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 01:18:33.624160 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 01:18:33.627127 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 01:18:33.630471 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 01:18:33.636979 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 01:18:33.640692 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 01:18:33.643728 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 01:18:33.650488 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 01:18:33.653800 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 01:18:33.657456 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 01:18:33.663730 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 01:18:33.666860 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 01:18:33.670687 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 01:18:33.677561 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 01:18:33.680484 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 01:18:33.683797 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 01:18:33.690593 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 01:18:33.693977 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 01:18:33.697437 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 01:18:33.700936 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 01:18:33.707443 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 01:18:33.710753 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 01:18:33.714098 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 01:18:33.721291 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 01:18:33.724112 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 01:18:33.727653 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 01:18:33.733826 0 9 8 | B1->B0 | 2b2b 2929 | 1 0 | (0 0) (0 0)
1179 01:18:33.737473 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 01:18:33.740218 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 01:18:33.747401 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 01:18:33.750784 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 01:18:33.754498 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 01:18:33.760964 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 01:18:33.763700 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1186 01:18:33.767384 0 10 8 | B1->B0 | 2a2a 2828 | 1 0 | (1 1) (0 0)
1187 01:18:33.773606 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 01:18:33.777795 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 01:18:33.780873 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 01:18:33.787279 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 01:18:33.790371 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 01:18:33.793850 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 01:18:33.797404 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1194 01:18:33.803793 0 11 8 | B1->B0 | 3c3c 3e3e | 0 0 | (0 0) (0 0)
1195 01:18:33.807523 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 01:18:33.810727 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 01:18:33.816923 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 01:18:33.821002 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 01:18:33.823946 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 01:18:33.830891 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 01:18:33.834276 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 01:18:33.837272 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 01:18:33.843739 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 01:18:33.847551 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 01:18:33.850426 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 01:18:33.857153 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 01:18:33.860310 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 01:18:33.863649 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 01:18:33.870939 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 01:18:33.873558 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 01:18:33.877177 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 01:18:33.883643 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 01:18:33.887271 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 01:18:33.890450 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 01:18:33.896837 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 01:18:33.900368 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 01:18:33.904248 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 01:18:33.907279 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 01:18:33.913525 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 01:18:33.916927 Total UI for P1: 0, mck2ui 16
1221 01:18:33.920361 best dqsien dly found for B0: ( 0, 14, 8)
1222 01:18:33.923732 Total UI for P1: 0, mck2ui 16
1223 01:18:33.927282 best dqsien dly found for B1: ( 0, 14, 8)
1224 01:18:33.930459 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1225 01:18:33.933685 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 01:18:33.934156
1227 01:18:33.937040 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 01:18:33.940211 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 01:18:33.944000 [Gating] SW calibration Done
1230 01:18:33.944565 ==
1231 01:18:33.947356 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 01:18:33.950719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 01:18:33.951288 ==
1234 01:18:33.953921 RX Vref Scan: 0
1235 01:18:33.954550
1236 01:18:33.955021 RX Vref 0 -> 0, step: 1
1237 01:18:33.955462
1238 01:18:33.956773 RX Delay -130 -> 252, step: 16
1239 01:18:33.960305 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1240 01:18:33.967070 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1241 01:18:33.971024 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1242 01:18:33.974017 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1243 01:18:33.977646 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1244 01:18:33.980547 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1245 01:18:33.987410 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1246 01:18:33.991027 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
1247 01:18:33.993787 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1248 01:18:33.997276 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1249 01:18:34.001108 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1250 01:18:34.007491 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1251 01:18:34.010661 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1252 01:18:34.013903 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1253 01:18:34.017405 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1254 01:18:34.020365 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1255 01:18:34.023630 ==
1256 01:18:34.027763 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 01:18:34.030819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 01:18:34.031296 ==
1259 01:18:34.031766 DQS Delay:
1260 01:18:34.034117 DQS0 = 0, DQS1 = 0
1261 01:18:34.034629 DQM Delay:
1262 01:18:34.037534 DQM0 = 90, DQM1 = 83
1263 01:18:34.038102 DQ Delay:
1264 01:18:34.040260 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1265 01:18:34.044063 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1266 01:18:34.047517 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1267 01:18:34.050088 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1268 01:18:34.050606
1269 01:18:34.051074
1270 01:18:34.051558 ==
1271 01:18:34.053761 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 01:18:34.057260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 01:18:34.057866 ==
1274 01:18:34.058366
1275 01:18:34.058817
1276 01:18:34.060492 TX Vref Scan disable
1277 01:18:34.063998 == TX Byte 0 ==
1278 01:18:34.067789 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1279 01:18:34.070514 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1280 01:18:34.074024 == TX Byte 1 ==
1281 01:18:34.076992 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1282 01:18:34.080363 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1283 01:18:34.080829 ==
1284 01:18:34.084208 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 01:18:34.087419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 01:18:34.090625 ==
1287 01:18:34.103371 TX Vref=22, minBit 10, minWin=27, winSum=447
1288 01:18:34.105627 TX Vref=24, minBit 13, minWin=27, winSum=451
1289 01:18:34.109304 TX Vref=26, minBit 1, minWin=28, winSum=455
1290 01:18:34.112490 TX Vref=28, minBit 14, minWin=28, winSum=464
1291 01:18:34.115928 TX Vref=30, minBit 7, minWin=28, winSum=459
1292 01:18:34.122159 TX Vref=32, minBit 12, minWin=27, winSum=455
1293 01:18:34.125740 [TxChooseVref] Worse bit 14, Min win 28, Win sum 464, Final Vref 28
1294 01:18:34.126199
1295 01:18:34.128973 Final TX Range 1 Vref 28
1296 01:18:34.129424
1297 01:18:34.129778 ==
1298 01:18:34.132260 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 01:18:34.135592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 01:18:34.138888 ==
1301 01:18:34.139341
1302 01:18:34.139692
1303 01:18:34.140023 TX Vref Scan disable
1304 01:18:34.142552 == TX Byte 0 ==
1305 01:18:34.146054 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1306 01:18:34.149303 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1307 01:18:34.152966 == TX Byte 1 ==
1308 01:18:34.155948 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1309 01:18:34.159025 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1310 01:18:34.162520
1311 01:18:34.162928 [DATLAT]
1312 01:18:34.163248 Freq=800, CH0 RK1
1313 01:18:34.163548
1314 01:18:34.166004 DATLAT Default: 0xa
1315 01:18:34.166508 0, 0xFFFF, sum = 0
1316 01:18:34.169233 1, 0xFFFF, sum = 0
1317 01:18:34.169650 2, 0xFFFF, sum = 0
1318 01:18:34.172654 3, 0xFFFF, sum = 0
1319 01:18:34.173261 4, 0xFFFF, sum = 0
1320 01:18:34.176615 5, 0xFFFF, sum = 0
1321 01:18:34.177031 6, 0xFFFF, sum = 0
1322 01:18:34.179741 7, 0xFFFF, sum = 0
1323 01:18:34.180250 8, 0xFFFF, sum = 0
1324 01:18:34.183583 9, 0x0, sum = 1
1325 01:18:34.183998 10, 0x0, sum = 2
1326 01:18:34.187329 11, 0x0, sum = 3
1327 01:18:34.187748 12, 0x0, sum = 4
1328 01:18:34.188093 best_step = 10
1329 01:18:34.188397
1330 01:18:34.188686 ==
1331 01:18:34.191043 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 01:18:34.194954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 01:18:34.198740 ==
1334 01:18:34.199147 RX Vref Scan: 0
1335 01:18:34.199467
1336 01:18:34.202136 RX Vref 0 -> 0, step: 1
1337 01:18:34.202588
1338 01:18:34.202912 RX Delay -79 -> 252, step: 8
1339 01:18:34.209825 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1340 01:18:34.213514 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1341 01:18:34.216646 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1342 01:18:34.220168 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1343 01:18:34.223298 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1344 01:18:34.226451 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1345 01:18:34.233454 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1346 01:18:34.236278 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1347 01:18:34.240327 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1348 01:18:34.243122 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1349 01:18:34.247205 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1350 01:18:34.253798 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1351 01:18:34.256994 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1352 01:18:34.260101 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1353 01:18:34.263623 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1354 01:18:34.266898 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1355 01:18:34.267450 ==
1356 01:18:34.270126 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 01:18:34.277243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 01:18:34.277801 ==
1359 01:18:34.278158 DQS Delay:
1360 01:18:34.280234 DQS0 = 0, DQS1 = 0
1361 01:18:34.280686 DQM Delay:
1362 01:18:34.281054 DQM0 = 92, DQM1 = 82
1363 01:18:34.283572 DQ Delay:
1364 01:18:34.286527 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =92
1365 01:18:34.290498 DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100
1366 01:18:34.293269 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1367 01:18:34.296505 DQ12 =84, DQ13 =88, DQ14 =88, DQ15 =88
1368 01:18:34.296977
1369 01:18:34.297328
1370 01:18:34.303284 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1371 01:18:34.306963 CH0 RK1: MR19=606, MR18=3F10
1372 01:18:34.313429 CH0_RK1: MR19=0x606, MR18=0x3F10, DQSOSC=393, MR23=63, INC=95, DEC=63
1373 01:18:34.316756 [RxdqsGatingPostProcess] freq 800
1374 01:18:34.320519 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 01:18:34.323461 Pre-setting of DQS Precalculation
1376 01:18:34.330471 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 01:18:34.331025 ==
1378 01:18:34.333897 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 01:18:34.337074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 01:18:34.337699 ==
1381 01:18:34.343582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 01:18:34.347013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 01:18:34.357418 [CA 0] Center 36 (6~67) winsize 62
1384 01:18:34.360737 [CA 1] Center 36 (6~67) winsize 62
1385 01:18:34.364498 [CA 2] Center 35 (4~66) winsize 63
1386 01:18:34.367532 [CA 3] Center 34 (4~65) winsize 62
1387 01:18:34.371191 [CA 4] Center 35 (5~65) winsize 61
1388 01:18:34.374039 [CA 5] Center 34 (4~65) winsize 62
1389 01:18:34.374630
1390 01:18:34.377603 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 01:18:34.378167
1392 01:18:34.380735 [CATrainingPosCal] consider 1 rank data
1393 01:18:34.383953 u2DelayCellTimex100 = 270/100 ps
1394 01:18:34.387198 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 01:18:34.390406 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 01:18:34.397046 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1397 01:18:34.400893 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 01:18:34.404093 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1399 01:18:34.407353 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 01:18:34.407905
1401 01:18:34.410786 CA PerBit enable=1, Macro0, CA PI delay=34
1402 01:18:34.411343
1403 01:18:34.414153 [CBTSetCACLKResult] CA Dly = 34
1404 01:18:34.414712 CS Dly: 5 (0~36)
1405 01:18:34.415329 ==
1406 01:18:34.417267 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 01:18:34.423795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 01:18:34.424304 ==
1409 01:18:34.427597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 01:18:34.433747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 01:18:34.443384 [CA 0] Center 36 (6~67) winsize 62
1412 01:18:34.446973 [CA 1] Center 37 (6~68) winsize 63
1413 01:18:34.450884 [CA 2] Center 35 (5~66) winsize 62
1414 01:18:34.454014 [CA 3] Center 34 (4~65) winsize 62
1415 01:18:34.456986 [CA 4] Center 35 (5~66) winsize 62
1416 01:18:34.460490 [CA 5] Center 34 (4~65) winsize 62
1417 01:18:34.460951
1418 01:18:34.464005 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 01:18:34.464566
1420 01:18:34.467171 [CATrainingPosCal] consider 2 rank data
1421 01:18:34.470711 u2DelayCellTimex100 = 270/100 ps
1422 01:18:34.473615 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 01:18:34.477042 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 01:18:34.483587 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1425 01:18:34.486950 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 01:18:34.490351 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 01:18:34.493613 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 01:18:34.494165
1429 01:18:34.496928 CA PerBit enable=1, Macro0, CA PI delay=34
1430 01:18:34.497480
1431 01:18:34.500325 [CBTSetCACLKResult] CA Dly = 34
1432 01:18:34.500878 CS Dly: 6 (0~38)
1433 01:18:34.501243
1434 01:18:34.503316 ----->DramcWriteLeveling(PI) begin...
1435 01:18:34.506643 ==
1436 01:18:34.507100 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 01:18:34.513424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 01:18:34.513979 ==
1439 01:18:34.516909 Write leveling (Byte 0): 28 => 28
1440 01:18:34.519803 Write leveling (Byte 1): 28 => 28
1441 01:18:34.523432 DramcWriteLeveling(PI) end<-----
1442 01:18:34.523890
1443 01:18:34.524246 ==
1444 01:18:34.527029 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 01:18:34.530243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 01:18:34.530844 ==
1447 01:18:34.533343 [Gating] SW mode calibration
1448 01:18:34.540328 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 01:18:34.543512 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 01:18:34.550455 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 01:18:34.553793 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1452 01:18:34.557138 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 01:18:34.563217 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 01:18:34.566861 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 01:18:34.570337 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 01:18:34.577317 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 01:18:34.579901 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 01:18:34.583261 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 01:18:34.590476 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 01:18:34.593764 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 01:18:34.597066 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 01:18:34.603252 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 01:18:34.606898 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 01:18:34.610111 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 01:18:34.617083 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 01:18:34.619790 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1467 01:18:34.623129 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1468 01:18:34.630240 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1469 01:18:34.633309 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 01:18:34.636313 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 01:18:34.640208 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 01:18:34.646657 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 01:18:34.649877 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 01:18:34.653286 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 01:18:34.660563 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1476 01:18:34.663392 0 9 8 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 1)
1477 01:18:34.666868 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 01:18:34.673708 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 01:18:34.676396 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 01:18:34.680221 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 01:18:34.686825 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 01:18:34.689823 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 01:18:34.693640 0 10 4 | B1->B0 | 3434 2f2f | 0 1 | (0 1) (1 1)
1484 01:18:34.699924 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
1485 01:18:34.702921 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 01:18:34.706734 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 01:18:34.713705 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 01:18:34.717093 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 01:18:34.720144 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 01:18:34.726917 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1491 01:18:34.730089 0 11 4 | B1->B0 | 2525 3535 | 0 1 | (0 0) (0 0)
1492 01:18:34.733093 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1493 01:18:34.737102 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 01:18:34.743485 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 01:18:34.746752 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 01:18:34.750534 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 01:18:34.757277 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 01:18:34.760718 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1499 01:18:34.764910 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1500 01:18:34.767917 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 01:18:34.774405 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 01:18:34.777664 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 01:18:34.780759 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 01:18:34.787716 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 01:18:34.791506 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 01:18:34.794377 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 01:18:34.801437 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 01:18:34.804856 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 01:18:34.807775 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 01:18:34.814382 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 01:18:34.817855 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 01:18:34.821175 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 01:18:34.828439 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 01:18:34.831398 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 01:18:34.834057 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 01:18:34.841119 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 01:18:34.841674 Total UI for P1: 0, mck2ui 16
1518 01:18:34.844617 best dqsien dly found for B0: ( 0, 14, 4)
1519 01:18:34.847513 Total UI for P1: 0, mck2ui 16
1520 01:18:34.851209 best dqsien dly found for B1: ( 0, 14, 4)
1521 01:18:34.854415 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1522 01:18:34.857723 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1523 01:18:34.861134
1524 01:18:34.864479 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1525 01:18:34.867787 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 01:18:34.871557 [Gating] SW calibration Done
1527 01:18:34.872104 ==
1528 01:18:34.874238 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 01:18:34.877670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 01:18:34.878124 ==
1531 01:18:34.878534 RX Vref Scan: 0
1532 01:18:34.878878
1533 01:18:34.880707 RX Vref 0 -> 0, step: 1
1534 01:18:34.881164
1535 01:18:34.884525 RX Delay -130 -> 252, step: 16
1536 01:18:34.887955 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1537 01:18:34.890964 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1538 01:18:34.897668 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1539 01:18:34.901585 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 01:18:34.904357 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1541 01:18:34.907431 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1542 01:18:34.910927 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1543 01:18:34.914291 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 01:18:34.921814 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1545 01:18:34.924986 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1546 01:18:34.927991 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1547 01:18:34.931489 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1548 01:18:34.937751 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1549 01:18:34.941565 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1550 01:18:34.944414 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1551 01:18:34.948071 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1552 01:18:34.948625 ==
1553 01:18:34.951018 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 01:18:34.955267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 01:18:34.958198 ==
1556 01:18:34.958682 DQS Delay:
1557 01:18:34.959036 DQS0 = 0, DQS1 = 0
1558 01:18:34.961592 DQM Delay:
1559 01:18:34.962258 DQM0 = 93, DQM1 = 87
1560 01:18:34.964606 DQ Delay:
1561 01:18:34.965155 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1562 01:18:34.967708 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1563 01:18:34.970997 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1564 01:18:34.975246 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1565 01:18:34.977675
1566 01:18:34.978123
1567 01:18:34.978529 ==
1568 01:18:34.981149 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 01:18:34.984221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 01:18:34.984677 ==
1571 01:18:34.985032
1572 01:18:34.985360
1573 01:18:34.987421 TX Vref Scan disable
1574 01:18:34.987900 == TX Byte 0 ==
1575 01:18:34.994080 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1576 01:18:34.997690 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1577 01:18:34.998200 == TX Byte 1 ==
1578 01:18:35.004356 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1579 01:18:35.007525 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1580 01:18:35.008037 ==
1581 01:18:35.010783 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 01:18:35.014494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 01:18:35.015006 ==
1584 01:18:35.027909 TX Vref=22, minBit 1, minWin=26, winSum=436
1585 01:18:35.031453 TX Vref=24, minBit 1, minWin=26, winSum=437
1586 01:18:35.034202 TX Vref=26, minBit 1, minWin=27, winSum=444
1587 01:18:35.038034 TX Vref=28, minBit 1, minWin=27, winSum=450
1588 01:18:35.041404 TX Vref=30, minBit 0, minWin=27, winSum=450
1589 01:18:35.048171 TX Vref=32, minBit 1, minWin=27, winSum=449
1590 01:18:35.050976 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 28
1591 01:18:35.051451
1592 01:18:35.054560 Final TX Range 1 Vref 28
1593 01:18:35.055027
1594 01:18:35.055494 ==
1595 01:18:35.057794 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 01:18:35.061329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 01:18:35.061916 ==
1598 01:18:35.064590
1599 01:18:35.065134
1600 01:18:35.065487 TX Vref Scan disable
1601 01:18:35.068426 == TX Byte 0 ==
1602 01:18:35.070999 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1603 01:18:35.074206 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1604 01:18:35.078035 == TX Byte 1 ==
1605 01:18:35.081474 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1606 01:18:35.084239 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1607 01:18:35.088087
1608 01:18:35.088534 [DATLAT]
1609 01:18:35.088889 Freq=800, CH1 RK0
1610 01:18:35.089220
1611 01:18:35.091590 DATLAT Default: 0xa
1612 01:18:35.092191 0, 0xFFFF, sum = 0
1613 01:18:35.094508 1, 0xFFFF, sum = 0
1614 01:18:35.094967 2, 0xFFFF, sum = 0
1615 01:18:35.097801 3, 0xFFFF, sum = 0
1616 01:18:35.098468 4, 0xFFFF, sum = 0
1617 01:18:35.101247 5, 0xFFFF, sum = 0
1618 01:18:35.101798 6, 0xFFFF, sum = 0
1619 01:18:35.104679 7, 0xFFFF, sum = 0
1620 01:18:35.105315 8, 0xFFFF, sum = 0
1621 01:18:35.108307 9, 0x0, sum = 1
1622 01:18:35.108866 10, 0x0, sum = 2
1623 01:18:35.111881 11, 0x0, sum = 3
1624 01:18:35.112445 12, 0x0, sum = 4
1625 01:18:35.114758 best_step = 10
1626 01:18:35.115209
1627 01:18:35.115559 ==
1628 01:18:35.118385 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 01:18:35.121454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 01:18:35.122004 ==
1631 01:18:35.124785 RX Vref Scan: 1
1632 01:18:35.125233
1633 01:18:35.125584 Set Vref Range= 32 -> 127
1634 01:18:35.125911
1635 01:18:35.127998 RX Vref 32 -> 127, step: 1
1636 01:18:35.128637
1637 01:18:35.131793 RX Delay -79 -> 252, step: 8
1638 01:18:35.132349
1639 01:18:35.134391 Set Vref, RX VrefLevel [Byte0]: 32
1640 01:18:35.137845 [Byte1]: 32
1641 01:18:35.138298
1642 01:18:35.141463 Set Vref, RX VrefLevel [Byte0]: 33
1643 01:18:35.144659 [Byte1]: 33
1644 01:18:35.148028
1645 01:18:35.148438 Set Vref, RX VrefLevel [Byte0]: 34
1646 01:18:35.151400 [Byte1]: 34
1647 01:18:35.155797
1648 01:18:35.156309 Set Vref, RX VrefLevel [Byte0]: 35
1649 01:18:35.159199 [Byte1]: 35
1650 01:18:35.162880
1651 01:18:35.163381 Set Vref, RX VrefLevel [Byte0]: 36
1652 01:18:35.166256 [Byte1]: 36
1653 01:18:35.170787
1654 01:18:35.171193 Set Vref, RX VrefLevel [Byte0]: 37
1655 01:18:35.173932 [Byte1]: 37
1656 01:18:35.178267
1657 01:18:35.178889 Set Vref, RX VrefLevel [Byte0]: 38
1658 01:18:35.181477 [Byte1]: 38
1659 01:18:35.185977
1660 01:18:35.186537 Set Vref, RX VrefLevel [Byte0]: 39
1661 01:18:35.189091 [Byte1]: 39
1662 01:18:35.193576
1663 01:18:35.194096 Set Vref, RX VrefLevel [Byte0]: 40
1664 01:18:35.196933 [Byte1]: 40
1665 01:18:35.200656
1666 01:18:35.201163 Set Vref, RX VrefLevel [Byte0]: 41
1667 01:18:35.203958 [Byte1]: 41
1668 01:18:35.208481
1669 01:18:35.209048 Set Vref, RX VrefLevel [Byte0]: 42
1670 01:18:35.212078 [Byte1]: 42
1671 01:18:35.215633
1672 01:18:35.216048 Set Vref, RX VrefLevel [Byte0]: 43
1673 01:18:35.219036 [Byte1]: 43
1674 01:18:35.223635
1675 01:18:35.224136 Set Vref, RX VrefLevel [Byte0]: 44
1676 01:18:35.226814 [Byte1]: 44
1677 01:18:35.230899
1678 01:18:35.231402 Set Vref, RX VrefLevel [Byte0]: 45
1679 01:18:35.234802 [Byte1]: 45
1680 01:18:35.238438
1681 01:18:35.239002 Set Vref, RX VrefLevel [Byte0]: 46
1682 01:18:35.241502 [Byte1]: 46
1683 01:18:35.246082
1684 01:18:35.246639 Set Vref, RX VrefLevel [Byte0]: 47
1685 01:18:35.249148 [Byte1]: 47
1686 01:18:35.253652
1687 01:18:35.254180 Set Vref, RX VrefLevel [Byte0]: 48
1688 01:18:35.256727 [Byte1]: 48
1689 01:18:35.261070
1690 01:18:35.261484 Set Vref, RX VrefLevel [Byte0]: 49
1691 01:18:35.264139 [Byte1]: 49
1692 01:18:35.268613
1693 01:18:35.269151 Set Vref, RX VrefLevel [Byte0]: 50
1694 01:18:35.272055 [Byte1]: 50
1695 01:18:35.276178
1696 01:18:35.276715 Set Vref, RX VrefLevel [Byte0]: 51
1697 01:18:35.279352 [Byte1]: 51
1698 01:18:35.283640
1699 01:18:35.284050 Set Vref, RX VrefLevel [Byte0]: 52
1700 01:18:35.286813 [Byte1]: 52
1701 01:18:35.291322
1702 01:18:35.291729 Set Vref, RX VrefLevel [Byte0]: 53
1703 01:18:35.294404 [Byte1]: 53
1704 01:18:35.298925
1705 01:18:35.299427 Set Vref, RX VrefLevel [Byte0]: 54
1706 01:18:35.302295 [Byte1]: 54
1707 01:18:35.306785
1708 01:18:35.307291 Set Vref, RX VrefLevel [Byte0]: 55
1709 01:18:35.310242 [Byte1]: 55
1710 01:18:35.314124
1711 01:18:35.314682 Set Vref, RX VrefLevel [Byte0]: 56
1712 01:18:35.317335 [Byte1]: 56
1713 01:18:35.321486
1714 01:18:35.321923 Set Vref, RX VrefLevel [Byte0]: 57
1715 01:18:35.325315 [Byte1]: 57
1716 01:18:35.329020
1717 01:18:35.329472 Set Vref, RX VrefLevel [Byte0]: 58
1718 01:18:35.332444 [Byte1]: 58
1719 01:18:35.336811
1720 01:18:35.337358 Set Vref, RX VrefLevel [Byte0]: 59
1721 01:18:35.339912 [Byte1]: 59
1722 01:18:35.344575
1723 01:18:35.345123 Set Vref, RX VrefLevel [Byte0]: 60
1724 01:18:35.347606 [Byte1]: 60
1725 01:18:35.351868
1726 01:18:35.352420 Set Vref, RX VrefLevel [Byte0]: 61
1727 01:18:35.355049 [Byte1]: 61
1728 01:18:35.359142
1729 01:18:35.359592 Set Vref, RX VrefLevel [Byte0]: 62
1730 01:18:35.362833 [Byte1]: 62
1731 01:18:35.366887
1732 01:18:35.367431 Set Vref, RX VrefLevel [Byte0]: 63
1733 01:18:35.370171 [Byte1]: 63
1734 01:18:35.374657
1735 01:18:35.375247 Set Vref, RX VrefLevel [Byte0]: 64
1736 01:18:35.377575 [Byte1]: 64
1737 01:18:35.382121
1738 01:18:35.382623 Set Vref, RX VrefLevel [Byte0]: 65
1739 01:18:35.385563 [Byte1]: 65
1740 01:18:35.389125
1741 01:18:35.389599 Set Vref, RX VrefLevel [Byte0]: 66
1742 01:18:35.392923 [Byte1]: 66
1743 01:18:35.397360
1744 01:18:35.397903 Set Vref, RX VrefLevel [Byte0]: 67
1745 01:18:35.400639 [Byte1]: 67
1746 01:18:35.404478
1747 01:18:35.405017 Set Vref, RX VrefLevel [Byte0]: 68
1748 01:18:35.407817 [Byte1]: 68
1749 01:18:35.412512
1750 01:18:35.413053 Set Vref, RX VrefLevel [Byte0]: 69
1751 01:18:35.415413 [Byte1]: 69
1752 01:18:35.419208
1753 01:18:35.419655 Set Vref, RX VrefLevel [Byte0]: 70
1754 01:18:35.422567 [Byte1]: 70
1755 01:18:35.427251
1756 01:18:35.427753 Set Vref, RX VrefLevel [Byte0]: 71
1757 01:18:35.430211 [Byte1]: 71
1758 01:18:35.434812
1759 01:18:35.435222 Final RX Vref Byte 0 = 55 to rank0
1760 01:18:35.437873 Final RX Vref Byte 1 = 54 to rank0
1761 01:18:35.441508 Final RX Vref Byte 0 = 55 to rank1
1762 01:18:35.444467 Final RX Vref Byte 1 = 54 to rank1==
1763 01:18:35.448062 Dram Type= 6, Freq= 0, CH_1, rank 0
1764 01:18:35.454497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1765 01:18:35.454791 ==
1766 01:18:35.455022 DQS Delay:
1767 01:18:35.455238 DQS0 = 0, DQS1 = 0
1768 01:18:35.457923 DQM Delay:
1769 01:18:35.458142 DQM0 = 94, DQM1 = 90
1770 01:18:35.461041 DQ Delay:
1771 01:18:35.464571 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1772 01:18:35.467657 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1773 01:18:35.467795 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1774 01:18:35.474543 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1775 01:18:35.474702
1776 01:18:35.474805
1777 01:18:35.480849 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1778 01:18:35.484605 CH1 RK0: MR19=606, MR18=2D4A
1779 01:18:35.490943 CH1_RK0: MR19=0x606, MR18=0x2D4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1780 01:18:35.491073
1781 01:18:35.494269 ----->DramcWriteLeveling(PI) begin...
1782 01:18:35.494507 ==
1783 01:18:35.498193 Dram Type= 6, Freq= 0, CH_1, rank 1
1784 01:18:35.501386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 01:18:35.501596 ==
1786 01:18:35.504566 Write leveling (Byte 0): 28 => 28
1787 01:18:35.508230 Write leveling (Byte 1): 28 => 28
1788 01:18:35.511277 DramcWriteLeveling(PI) end<-----
1789 01:18:35.511519
1790 01:18:35.511657 ==
1791 01:18:35.514519 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 01:18:35.518391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 01:18:35.518703 ==
1794 01:18:35.521148 [Gating] SW mode calibration
1795 01:18:35.528819 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1796 01:18:35.535081 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1797 01:18:35.538102 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1798 01:18:35.541773 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1799 01:18:35.548415 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 01:18:35.551538 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 01:18:35.555009 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 01:18:35.562173 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 01:18:35.565079 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 01:18:35.568121 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 01:18:35.575135 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 01:18:35.578715 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 01:18:35.581514 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 01:18:35.585461 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 01:18:35.591582 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 01:18:35.594893 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 01:18:35.598658 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 01:18:35.605423 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 01:18:35.608788 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1814 01:18:35.611855 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1815 01:18:35.618351 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 01:18:35.621589 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 01:18:35.624911 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 01:18:35.631778 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 01:18:35.635073 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 01:18:35.638369 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 01:18:35.645535 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 01:18:35.648500 0 9 4 | B1->B0 | 2828 2323 | 1 0 | (1 1) (0 0)
1823 01:18:35.651982 0 9 8 | B1->B0 | 3434 3231 | 1 1 | (1 1) (1 1)
1824 01:18:35.658220 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 01:18:35.661976 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 01:18:35.664727 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 01:18:35.671642 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 01:18:35.675143 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 01:18:35.678513 0 10 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 0)
1830 01:18:35.681551 0 10 4 | B1->B0 | 2b2b 3131 | 0 1 | (0 0) (1 0)
1831 01:18:35.688906 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1832 01:18:35.691939 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 01:18:35.695324 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 01:18:35.701773 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 01:18:35.705248 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 01:18:35.708672 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 01:18:35.715357 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 01:18:35.718605 0 11 4 | B1->B0 | 3838 2f2f | 1 0 | (0 0) (0 0)
1839 01:18:35.721609 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1840 01:18:35.728561 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 01:18:35.731891 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 01:18:35.734926 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 01:18:35.741589 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 01:18:35.745090 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 01:18:35.748028 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 01:18:35.754600 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1847 01:18:35.758464 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 01:18:35.761228 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 01:18:35.768065 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 01:18:35.772040 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 01:18:35.774987 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 01:18:35.781625 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 01:18:35.784571 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 01:18:35.788010 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 01:18:35.791325 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 01:18:35.798674 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 01:18:35.801940 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 01:18:35.804823 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 01:18:35.811657 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 01:18:35.815627 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 01:18:35.818376 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 01:18:35.824803 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1863 01:18:35.828252 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 01:18:35.831848 Total UI for P1: 0, mck2ui 16
1865 01:18:35.835110 best dqsien dly found for B0: ( 0, 14, 4)
1866 01:18:35.838364 Total UI for P1: 0, mck2ui 16
1867 01:18:35.841667 best dqsien dly found for B1: ( 0, 14, 4)
1868 01:18:35.845182 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1869 01:18:35.848013 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1870 01:18:35.848470
1871 01:18:35.851289 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1872 01:18:35.854722 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1873 01:18:35.858597 [Gating] SW calibration Done
1874 01:18:35.859155 ==
1875 01:18:35.861535 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 01:18:35.864737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 01:18:35.865314 ==
1878 01:18:35.868077 RX Vref Scan: 0
1879 01:18:35.868531
1880 01:18:35.871187 RX Vref 0 -> 0, step: 1
1881 01:18:35.871644
1882 01:18:35.871999 RX Delay -130 -> 252, step: 16
1883 01:18:35.878165 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1884 01:18:35.881805 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1885 01:18:35.885360 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1886 01:18:35.888268 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1887 01:18:35.891507 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1888 01:18:35.898088 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1889 01:18:35.901675 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1890 01:18:35.904972 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1891 01:18:35.908191 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1892 01:18:35.912045 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1893 01:18:35.918352 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1894 01:18:35.921347 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1895 01:18:35.924762 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1896 01:18:35.928776 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1897 01:18:35.931525 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1898 01:18:35.937878 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1899 01:18:35.938380 ==
1900 01:18:35.941272 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 01:18:35.944770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 01:18:35.945236 ==
1903 01:18:35.945593 DQS Delay:
1904 01:18:35.948160 DQS0 = 0, DQS1 = 0
1905 01:18:35.948616 DQM Delay:
1906 01:18:35.951823 DQM0 = 92, DQM1 = 87
1907 01:18:35.952283 DQ Delay:
1908 01:18:35.954643 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1909 01:18:35.958277 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1910 01:18:35.961563 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1911 01:18:35.964722 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1912 01:18:35.965309
1913 01:18:35.965651
1914 01:18:35.965954 ==
1915 01:18:35.968619 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 01:18:35.972041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 01:18:35.972572 ==
1918 01:18:35.975009
1919 01:18:35.975423
1920 01:18:35.975836 TX Vref Scan disable
1921 01:18:35.978067 == TX Byte 0 ==
1922 01:18:35.981583 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1923 01:18:35.985386 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1924 01:18:35.988743 == TX Byte 1 ==
1925 01:18:35.991464 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1926 01:18:35.995123 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1927 01:18:35.995542 ==
1928 01:18:35.998593 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 01:18:36.005367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 01:18:36.005891 ==
1931 01:18:36.017236 TX Vref=22, minBit 1, minWin=26, winSum=442
1932 01:18:36.020072 TX Vref=24, minBit 1, minWin=26, winSum=445
1933 01:18:36.023243 TX Vref=26, minBit 0, minWin=27, winSum=446
1934 01:18:36.027070 TX Vref=28, minBit 2, minWin=27, winSum=452
1935 01:18:36.030189 TX Vref=30, minBit 2, minWin=27, winSum=451
1936 01:18:36.033534 TX Vref=32, minBit 2, minWin=27, winSum=450
1937 01:18:36.040096 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 28
1938 01:18:36.040858
1939 01:18:36.043672 Final TX Range 1 Vref 28
1940 01:18:36.044131
1941 01:18:36.044485 ==
1942 01:18:36.047119 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 01:18:36.050626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 01:18:36.051192 ==
1945 01:18:36.051556
1946 01:18:36.053549
1947 01:18:36.054002 TX Vref Scan disable
1948 01:18:36.056859 == TX Byte 0 ==
1949 01:18:36.060447 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1950 01:18:36.063537 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1951 01:18:36.067525 == TX Byte 1 ==
1952 01:18:36.070365 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1953 01:18:36.073974 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1954 01:18:36.074600
1955 01:18:36.076842 [DATLAT]
1956 01:18:36.077297 Freq=800, CH1 RK1
1957 01:18:36.077697
1958 01:18:36.080251 DATLAT Default: 0xa
1959 01:18:36.080708 0, 0xFFFF, sum = 0
1960 01:18:36.084055 1, 0xFFFF, sum = 0
1961 01:18:36.084553 2, 0xFFFF, sum = 0
1962 01:18:36.087251 3, 0xFFFF, sum = 0
1963 01:18:36.087720 4, 0xFFFF, sum = 0
1964 01:18:36.090363 5, 0xFFFF, sum = 0
1965 01:18:36.090831 6, 0xFFFF, sum = 0
1966 01:18:36.093818 7, 0xFFFF, sum = 0
1967 01:18:36.094442 8, 0xFFFF, sum = 0
1968 01:18:36.097386 9, 0x0, sum = 1
1969 01:18:36.097850 10, 0x0, sum = 2
1970 01:18:36.100092 11, 0x0, sum = 3
1971 01:18:36.100557 12, 0x0, sum = 4
1972 01:18:36.103567 best_step = 10
1973 01:18:36.104083
1974 01:18:36.104408 ==
1975 01:18:36.106910 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 01:18:36.110276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 01:18:36.110735 ==
1978 01:18:36.114055 RX Vref Scan: 0
1979 01:18:36.114787
1980 01:18:36.115135 RX Vref 0 -> 0, step: 1
1981 01:18:36.115444
1982 01:18:36.116976 RX Delay -79 -> 252, step: 8
1983 01:18:36.123403 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1984 01:18:36.127535 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1985 01:18:36.130740 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1986 01:18:36.133570 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1987 01:18:36.136658 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1988 01:18:36.139980 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1989 01:18:36.146703 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1990 01:18:36.150235 iDelay=209, Bit 7, Center 92 (-7 ~ 192) 200
1991 01:18:36.153351 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1992 01:18:36.156968 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1993 01:18:36.160050 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
1994 01:18:36.166757 iDelay=209, Bit 11, Center 84 (-15 ~ 184) 200
1995 01:18:36.169970 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1996 01:18:36.173883 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1997 01:18:36.176996 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1998 01:18:36.180326 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1999 01:18:36.180785 ==
2000 01:18:36.183299 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 01:18:36.190520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 01:18:36.191070 ==
2003 01:18:36.191430 DQS Delay:
2004 01:18:36.193438 DQS0 = 0, DQS1 = 0
2005 01:18:36.193893 DQM Delay:
2006 01:18:36.194245 DQM0 = 96, DQM1 = 91
2007 01:18:36.196784 DQ Delay:
2008 01:18:36.200139 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2009 01:18:36.203637 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
2010 01:18:36.207155 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2011 01:18:36.210057 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2012 01:18:36.210694
2013 01:18:36.211027
2014 01:18:36.216773 [DQSOSCAuto] RK1, (LSB)MR18= 0x4712, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2015 01:18:36.220627 CH1 RK1: MR19=606, MR18=4712
2016 01:18:36.226943 CH1_RK1: MR19=0x606, MR18=0x4712, DQSOSC=392, MR23=63, INC=96, DEC=64
2017 01:18:36.230699 [RxdqsGatingPostProcess] freq 800
2018 01:18:36.233963 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2019 01:18:36.236930 Pre-setting of DQS Precalculation
2020 01:18:36.243203 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2021 01:18:36.250521 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2022 01:18:36.256922 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2023 01:18:36.257475
2024 01:18:36.257835
2025 01:18:36.260229 [Calibration Summary] 1600 Mbps
2026 01:18:36.260699 CH 0, Rank 0
2027 01:18:36.263189 SW Impedance : PASS
2028 01:18:36.266932 DUTY Scan : NO K
2029 01:18:36.267388 ZQ Calibration : PASS
2030 01:18:36.269972 Jitter Meter : NO K
2031 01:18:36.273575 CBT Training : PASS
2032 01:18:36.273987 Write leveling : PASS
2033 01:18:36.276768 RX DQS gating : PASS
2034 01:18:36.280012 RX DQ/DQS(RDDQC) : PASS
2035 01:18:36.280482 TX DQ/DQS : PASS
2036 01:18:36.283233 RX DATLAT : PASS
2037 01:18:36.286740 RX DQ/DQS(Engine): PASS
2038 01:18:36.287168 TX OE : NO K
2039 01:18:36.287496 All Pass.
2040 01:18:36.290590
2041 01:18:36.290999 CH 0, Rank 1
2042 01:18:36.293259 SW Impedance : PASS
2043 01:18:36.293670 DUTY Scan : NO K
2044 01:18:36.297021 ZQ Calibration : PASS
2045 01:18:36.297434 Jitter Meter : NO K
2046 01:18:36.299982 CBT Training : PASS
2047 01:18:36.303940 Write leveling : PASS
2048 01:18:36.304450 RX DQS gating : PASS
2049 01:18:36.307142 RX DQ/DQS(RDDQC) : PASS
2050 01:18:36.310462 TX DQ/DQS : PASS
2051 01:18:36.310989 RX DATLAT : PASS
2052 01:18:36.313553 RX DQ/DQS(Engine): PASS
2053 01:18:36.317315 TX OE : NO K
2054 01:18:36.317847 All Pass.
2055 01:18:36.318178
2056 01:18:36.318525 CH 1, Rank 0
2057 01:18:36.320099 SW Impedance : PASS
2058 01:18:36.323377 DUTY Scan : NO K
2059 01:18:36.323788 ZQ Calibration : PASS
2060 01:18:36.326895 Jitter Meter : NO K
2061 01:18:36.330887 CBT Training : PASS
2062 01:18:36.331419 Write leveling : PASS
2063 01:18:36.333735 RX DQS gating : PASS
2064 01:18:36.334257 RX DQ/DQS(RDDQC) : PASS
2065 01:18:36.337200 TX DQ/DQS : PASS
2066 01:18:36.340174 RX DATLAT : PASS
2067 01:18:36.340586 RX DQ/DQS(Engine): PASS
2068 01:18:36.343636 TX OE : NO K
2069 01:18:36.344158 All Pass.
2070 01:18:36.344489
2071 01:18:36.347040 CH 1, Rank 1
2072 01:18:36.347458 SW Impedance : PASS
2073 01:18:36.350418 DUTY Scan : NO K
2074 01:18:36.353596 ZQ Calibration : PASS
2075 01:18:36.354060 Jitter Meter : NO K
2076 01:18:36.356722 CBT Training : PASS
2077 01:18:36.359994 Write leveling : PASS
2078 01:18:36.360414 RX DQS gating : PASS
2079 01:18:36.363743 RX DQ/DQS(RDDQC) : PASS
2080 01:18:36.367062 TX DQ/DQS : PASS
2081 01:18:36.367632 RX DATLAT : PASS
2082 01:18:36.370042 RX DQ/DQS(Engine): PASS
2083 01:18:36.373883 TX OE : NO K
2084 01:18:36.374633 All Pass.
2085 01:18:36.375022
2086 01:18:36.375360 DramC Write-DBI off
2087 01:18:36.377197 PER_BANK_REFRESH: Hybrid Mode
2088 01:18:36.380218 TX_TRACKING: ON
2089 01:18:36.383762 [GetDramInforAfterCalByMRR] Vendor 6.
2090 01:18:36.386904 [GetDramInforAfterCalByMRR] Revision 606.
2091 01:18:36.390338 [GetDramInforAfterCalByMRR] Revision 2 0.
2092 01:18:36.390910 MR0 0x3b3b
2093 01:18:36.393523 MR8 0x5151
2094 01:18:36.396677 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2095 01:18:36.397152
2096 01:18:36.397512 MR0 0x3b3b
2097 01:18:36.397848 MR8 0x5151
2098 01:18:36.400353 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2099 01:18:36.403282
2100 01:18:36.409845 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2101 01:18:36.413696 [FAST_K] Save calibration result to emmc
2102 01:18:36.416594 [FAST_K] Save calibration result to emmc
2103 01:18:36.420135 dram_init: config_dvfs: 1
2104 01:18:36.423597 dramc_set_vcore_voltage set vcore to 662500
2105 01:18:36.426699 Read voltage for 1200, 2
2106 01:18:36.427283 Vio18 = 0
2107 01:18:36.430063 Vcore = 662500
2108 01:18:36.430558 Vdram = 0
2109 01:18:36.430919 Vddq = 0
2110 01:18:36.431269 Vmddr = 0
2111 01:18:36.436753 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2112 01:18:36.439969 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2113 01:18:36.443627 MEM_TYPE=3, freq_sel=15
2114 01:18:36.446959 sv_algorithm_assistance_LP4_1600
2115 01:18:36.450473 ============ PULL DRAM RESETB DOWN ============
2116 01:18:36.457074 ========== PULL DRAM RESETB DOWN end =========
2117 01:18:36.460322 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2118 01:18:36.463568 ===================================
2119 01:18:36.466673 LPDDR4 DRAM CONFIGURATION
2120 01:18:36.469901 ===================================
2121 01:18:36.470419 EX_ROW_EN[0] = 0x0
2122 01:18:36.474057 EX_ROW_EN[1] = 0x0
2123 01:18:36.474665 LP4Y_EN = 0x0
2124 01:18:36.477170 WORK_FSP = 0x0
2125 01:18:36.477733 WL = 0x4
2126 01:18:36.480337 RL = 0x4
2127 01:18:36.481101 BL = 0x2
2128 01:18:36.483833 RPST = 0x0
2129 01:18:36.484298 RD_PRE = 0x0
2130 01:18:36.486888 WR_PRE = 0x1
2131 01:18:36.487346 WR_PST = 0x0
2132 01:18:36.490604 DBI_WR = 0x0
2133 01:18:36.491061 DBI_RD = 0x0
2134 01:18:36.493424 OTF = 0x1
2135 01:18:36.496639 ===================================
2136 01:18:36.500346 ===================================
2137 01:18:36.500816 ANA top config
2138 01:18:36.503695 ===================================
2139 01:18:36.506771 DLL_ASYNC_EN = 0
2140 01:18:36.510834 ALL_SLAVE_EN = 0
2141 01:18:36.513900 NEW_RANK_MODE = 1
2142 01:18:36.514510 DLL_IDLE_MODE = 1
2143 01:18:36.516999 LP45_APHY_COMB_EN = 1
2144 01:18:36.520176 TX_ODT_DIS = 1
2145 01:18:36.523608 NEW_8X_MODE = 1
2146 01:18:36.527172 ===================================
2147 01:18:36.530486 ===================================
2148 01:18:36.533540 data_rate = 2400
2149 01:18:36.534114 CKR = 1
2150 01:18:36.537085 DQ_P2S_RATIO = 8
2151 01:18:36.540256 ===================================
2152 01:18:36.543653 CA_P2S_RATIO = 8
2153 01:18:36.546783 DQ_CA_OPEN = 0
2154 01:18:36.550419 DQ_SEMI_OPEN = 0
2155 01:18:36.553973 CA_SEMI_OPEN = 0
2156 01:18:36.554607 CA_FULL_RATE = 0
2157 01:18:36.557508 DQ_CKDIV4_EN = 0
2158 01:18:36.560250 CA_CKDIV4_EN = 0
2159 01:18:36.563856 CA_PREDIV_EN = 0
2160 01:18:36.567269 PH8_DLY = 17
2161 01:18:36.570803 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2162 01:18:36.571366 DQ_AAMCK_DIV = 4
2163 01:18:36.574066 CA_AAMCK_DIV = 4
2164 01:18:36.576904 CA_ADMCK_DIV = 4
2165 01:18:36.580374 DQ_TRACK_CA_EN = 0
2166 01:18:36.583979 CA_PICK = 1200
2167 01:18:36.587033 CA_MCKIO = 1200
2168 01:18:36.587694 MCKIO_SEMI = 0
2169 01:18:36.590246 PLL_FREQ = 2366
2170 01:18:36.594229 DQ_UI_PI_RATIO = 32
2171 01:18:36.597269 CA_UI_PI_RATIO = 0
2172 01:18:36.600593 ===================================
2173 01:18:36.603941 ===================================
2174 01:18:36.607220 memory_type:LPDDR4
2175 01:18:36.607782 GP_NUM : 10
2176 01:18:36.610217 SRAM_EN : 1
2177 01:18:36.613955 MD32_EN : 0
2178 01:18:36.617326 ===================================
2179 01:18:36.617884 [ANA_INIT] >>>>>>>>>>>>>>
2180 01:18:36.620408 <<<<<< [CONFIGURE PHASE]: ANA_TX
2181 01:18:36.623631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2182 01:18:36.626890 ===================================
2183 01:18:36.630279 data_rate = 2400,PCW = 0X5b00
2184 01:18:36.633507 ===================================
2185 01:18:36.636911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2186 01:18:36.643782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 01:18:36.647130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2188 01:18:36.653780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2189 01:18:36.656575 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2190 01:18:36.660018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2191 01:18:36.660482 [ANA_INIT] flow start
2192 01:18:36.663316 [ANA_INIT] PLL >>>>>>>>
2193 01:18:36.666919 [ANA_INIT] PLL <<<<<<<<
2194 01:18:36.667379 [ANA_INIT] MIDPI >>>>>>>>
2195 01:18:36.669949 [ANA_INIT] MIDPI <<<<<<<<
2196 01:18:36.673595 [ANA_INIT] DLL >>>>>>>>
2197 01:18:36.676779 [ANA_INIT] DLL <<<<<<<<
2198 01:18:36.677547 [ANA_INIT] flow end
2199 01:18:36.680559 ============ LP4 DIFF to SE enter ============
2200 01:18:36.686797 ============ LP4 DIFF to SE exit ============
2201 01:18:36.687347 [ANA_INIT] <<<<<<<<<<<<<
2202 01:18:36.690476 [Flow] Enable top DCM control >>>>>
2203 01:18:36.693952 [Flow] Enable top DCM control <<<<<
2204 01:18:36.696862 Enable DLL master slave shuffle
2205 01:18:36.703299 ==============================================================
2206 01:18:36.703842 Gating Mode config
2207 01:18:36.710671 ==============================================================
2208 01:18:36.714026 Config description:
2209 01:18:36.720049 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2210 01:18:36.726757 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2211 01:18:36.733998 SELPH_MODE 0: By rank 1: By Phase
2212 01:18:36.740186 ==============================================================
2213 01:18:36.740726 GAT_TRACK_EN = 1
2214 01:18:36.743780 RX_GATING_MODE = 2
2215 01:18:36.746803 RX_GATING_TRACK_MODE = 2
2216 01:18:36.750119 SELPH_MODE = 1
2217 01:18:36.753372 PICG_EARLY_EN = 1
2218 01:18:36.756919 VALID_LAT_VALUE = 1
2219 01:18:36.763081 ==============================================================
2220 01:18:36.767056 Enter into Gating configuration >>>>
2221 01:18:36.770826 Exit from Gating configuration <<<<
2222 01:18:36.773550 Enter into DVFS_PRE_config >>>>>
2223 01:18:36.783505 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2224 01:18:36.786899 Exit from DVFS_PRE_config <<<<<
2225 01:18:36.790350 Enter into PICG configuration >>>>
2226 01:18:36.793641 Exit from PICG configuration <<<<
2227 01:18:36.797035 [RX_INPUT] configuration >>>>>
2228 01:18:36.797600 [RX_INPUT] configuration <<<<<
2229 01:18:36.803920 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2230 01:18:36.809957 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2231 01:18:36.813972 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2232 01:18:36.820300 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2233 01:18:36.826861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 01:18:36.833205 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 01:18:36.836613 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2236 01:18:36.839970 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2237 01:18:36.847001 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2238 01:18:36.850172 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2239 01:18:36.853677 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2240 01:18:36.860045 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2241 01:18:36.863062 ===================================
2242 01:18:36.863529 LPDDR4 DRAM CONFIGURATION
2243 01:18:36.867025 ===================================
2244 01:18:36.869875 EX_ROW_EN[0] = 0x0
2245 01:18:36.870513 EX_ROW_EN[1] = 0x0
2246 01:18:36.873129 LP4Y_EN = 0x0
2247 01:18:36.873586 WORK_FSP = 0x0
2248 01:18:36.877217 WL = 0x4
2249 01:18:36.877934 RL = 0x4
2250 01:18:36.879975 BL = 0x2
2251 01:18:36.880429 RPST = 0x0
2252 01:18:36.883737 RD_PRE = 0x0
2253 01:18:36.886934 WR_PRE = 0x1
2254 01:18:36.887403 WR_PST = 0x0
2255 01:18:36.890290 DBI_WR = 0x0
2256 01:18:36.890772 DBI_RD = 0x0
2257 01:18:36.893708 OTF = 0x1
2258 01:18:36.896641 ===================================
2259 01:18:36.900375 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2260 01:18:36.903690 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2261 01:18:36.907010 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 01:18:36.910044 ===================================
2263 01:18:36.913442 LPDDR4 DRAM CONFIGURATION
2264 01:18:36.916829 ===================================
2265 01:18:36.920401 EX_ROW_EN[0] = 0x10
2266 01:18:36.920957 EX_ROW_EN[1] = 0x0
2267 01:18:36.923528 LP4Y_EN = 0x0
2268 01:18:36.924038 WORK_FSP = 0x0
2269 01:18:36.927057 WL = 0x4
2270 01:18:36.927607 RL = 0x4
2271 01:18:36.930406 BL = 0x2
2272 01:18:36.930962 RPST = 0x0
2273 01:18:36.933505 RD_PRE = 0x0
2274 01:18:36.934052 WR_PRE = 0x1
2275 01:18:36.936344 WR_PST = 0x0
2276 01:18:36.936799 DBI_WR = 0x0
2277 01:18:36.940002 DBI_RD = 0x0
2278 01:18:36.940459 OTF = 0x1
2279 01:18:36.943305 ===================================
2280 01:18:36.949797 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2281 01:18:36.950362 ==
2282 01:18:36.953501 Dram Type= 6, Freq= 0, CH_0, rank 0
2283 01:18:36.959554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2284 01:18:36.960048 ==
2285 01:18:36.960414 [Duty_Offset_Calibration]
2286 01:18:36.963659 B0:2 B1:1 CA:1
2287 01:18:36.964219
2288 01:18:36.966495 [DutyScan_Calibration_Flow] k_type=0
2289 01:18:36.975777
2290 01:18:36.976333 ==CLK 0==
2291 01:18:36.978612 Final CLK duty delay cell = 0
2292 01:18:36.982177 [0] MAX Duty = 5218%(X100), DQS PI = 24
2293 01:18:36.985656 [0] MIN Duty = 4844%(X100), DQS PI = 48
2294 01:18:36.986113 [0] AVG Duty = 5031%(X100)
2295 01:18:36.988972
2296 01:18:36.989493 CH0 CLK Duty spec in!! Max-Min= 374%
2297 01:18:36.995603 [DutyScan_Calibration_Flow] ====Done====
2298 01:18:36.996056
2299 01:18:36.998530 [DutyScan_Calibration_Flow] k_type=1
2300 01:18:37.014198
2301 01:18:37.014624 ==DQS 0 ==
2302 01:18:37.017439 Final DQS duty delay cell = -4
2303 01:18:37.020548 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2304 01:18:37.023875 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2305 01:18:37.027442 [-4] AVG Duty = 4953%(X100)
2306 01:18:37.027826
2307 01:18:37.028064 ==DQS 1 ==
2308 01:18:37.030392 Final DQS duty delay cell = 0
2309 01:18:37.033569 [0] MAX Duty = 5187%(X100), DQS PI = 62
2310 01:18:37.036826 [0] MIN Duty = 5000%(X100), DQS PI = 34
2311 01:18:37.041105 [0] AVG Duty = 5093%(X100)
2312 01:18:37.041482
2313 01:18:37.043782 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2314 01:18:37.044236
2315 01:18:37.047323 CH0 DQS 1 Duty spec in!! Max-Min= 187%
2316 01:18:37.050851 [DutyScan_Calibration_Flow] ====Done====
2317 01:18:37.051397
2318 01:18:37.053610 [DutyScan_Calibration_Flow] k_type=3
2319 01:18:37.071236
2320 01:18:37.071871 ==DQM 0 ==
2321 01:18:37.074278 Final DQM duty delay cell = 0
2322 01:18:37.078125 [0] MAX Duty = 5156%(X100), DQS PI = 30
2323 01:18:37.081486 [0] MIN Duty = 4875%(X100), DQS PI = 58
2324 01:18:37.084429 [0] AVG Duty = 5015%(X100)
2325 01:18:37.084882
2326 01:18:37.085231 ==DQM 1 ==
2327 01:18:37.087350 Final DQM duty delay cell = 0
2328 01:18:37.090671 [0] MAX Duty = 5093%(X100), DQS PI = 0
2329 01:18:37.094653 [0] MIN Duty = 5031%(X100), DQS PI = 14
2330 01:18:37.097442 [0] AVG Duty = 5062%(X100)
2331 01:18:37.097928
2332 01:18:37.101224 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2333 01:18:37.101773
2334 01:18:37.104312 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2335 01:18:37.108087 [DutyScan_Calibration_Flow] ====Done====
2336 01:18:37.108634
2337 01:18:37.111185 [DutyScan_Calibration_Flow] k_type=2
2338 01:18:37.127825
2339 01:18:37.128381 ==DQ 0 ==
2340 01:18:37.131182 Final DQ duty delay cell = 0
2341 01:18:37.134384 [0] MAX Duty = 5031%(X100), DQS PI = 26
2342 01:18:37.137148 [0] MIN Duty = 4844%(X100), DQS PI = 0
2343 01:18:37.137600 [0] AVG Duty = 4937%(X100)
2344 01:18:37.137954
2345 01:18:37.140813 ==DQ 1 ==
2346 01:18:37.144023 Final DQ duty delay cell = 0
2347 01:18:37.147202 [0] MAX Duty = 5093%(X100), DQS PI = 24
2348 01:18:37.150831 [0] MIN Duty = 4938%(X100), DQS PI = 36
2349 01:18:37.151421 [0] AVG Duty = 5015%(X100)
2350 01:18:37.151781
2351 01:18:37.153918 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2352 01:18:37.157350
2353 01:18:37.160227 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2354 01:18:37.164583 [DutyScan_Calibration_Flow] ====Done====
2355 01:18:37.165138 ==
2356 01:18:37.167667 Dram Type= 6, Freq= 0, CH_1, rank 0
2357 01:18:37.171220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 01:18:37.171809 ==
2359 01:18:37.173648 [Duty_Offset_Calibration]
2360 01:18:37.174100 B0:1 B1:0 CA:0
2361 01:18:37.174482
2362 01:18:37.177134 [DutyScan_Calibration_Flow] k_type=0
2363 01:18:37.186548
2364 01:18:37.187117 ==CLK 0==
2365 01:18:37.189362 Final CLK duty delay cell = -4
2366 01:18:37.193316 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2367 01:18:37.196718 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2368 01:18:37.199710 [-4] AVG Duty = 4953%(X100)
2369 01:18:37.200243
2370 01:18:37.202768 CH1 CLK Duty spec in!! Max-Min= 93%
2371 01:18:37.206402 [DutyScan_Calibration_Flow] ====Done====
2372 01:18:37.206856
2373 01:18:37.209804 [DutyScan_Calibration_Flow] k_type=1
2374 01:18:37.226387
2375 01:18:37.226933 ==DQS 0 ==
2376 01:18:37.229319 Final DQS duty delay cell = 0
2377 01:18:37.232717 [0] MAX Duty = 5094%(X100), DQS PI = 26
2378 01:18:37.235871 [0] MIN Duty = 4875%(X100), DQS PI = 0
2379 01:18:37.236329 [0] AVG Duty = 4984%(X100)
2380 01:18:37.239219
2381 01:18:37.239769 ==DQS 1 ==
2382 01:18:37.242583 Final DQS duty delay cell = 0
2383 01:18:37.246332 [0] MAX Duty = 5218%(X100), DQS PI = 20
2384 01:18:37.249577 [0] MIN Duty = 4969%(X100), DQS PI = 8
2385 01:18:37.250140 [0] AVG Duty = 5093%(X100)
2386 01:18:37.250566
2387 01:18:37.256149 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2388 01:18:37.256724
2389 01:18:37.259748 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2390 01:18:37.263028 [DutyScan_Calibration_Flow] ====Done====
2391 01:18:37.263487
2392 01:18:37.266638 [DutyScan_Calibration_Flow] k_type=3
2393 01:18:37.282555
2394 01:18:37.283119 ==DQM 0 ==
2395 01:18:37.286416 Final DQM duty delay cell = 0
2396 01:18:37.289409 [0] MAX Duty = 5156%(X100), DQS PI = 8
2397 01:18:37.292577 [0] MIN Duty = 5000%(X100), DQS PI = 0
2398 01:18:37.293039 [0] AVG Duty = 5078%(X100)
2399 01:18:37.295694
2400 01:18:37.296149 ==DQM 1 ==
2401 01:18:37.299294 Final DQM duty delay cell = 0
2402 01:18:37.302898 [0] MAX Duty = 5031%(X100), DQS PI = 16
2403 01:18:37.305658 [0] MIN Duty = 4907%(X100), DQS PI = 34
2404 01:18:37.306122 [0] AVG Duty = 4969%(X100)
2405 01:18:37.309228
2406 01:18:37.312185 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2407 01:18:37.312646
2408 01:18:37.315927 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2409 01:18:37.319480 [DutyScan_Calibration_Flow] ====Done====
2410 01:18:37.320058
2411 01:18:37.322140 [DutyScan_Calibration_Flow] k_type=2
2412 01:18:37.338152
2413 01:18:37.338771 ==DQ 0 ==
2414 01:18:37.341266 Final DQ duty delay cell = -4
2415 01:18:37.344605 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2416 01:18:37.347912 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2417 01:18:37.352102 [-4] AVG Duty = 4984%(X100)
2418 01:18:37.352660
2419 01:18:37.353024 ==DQ 1 ==
2420 01:18:37.355142 Final DQ duty delay cell = 0
2421 01:18:37.358651 [0] MAX Duty = 5125%(X100), DQS PI = 20
2422 01:18:37.361546 [0] MIN Duty = 4969%(X100), DQS PI = 10
2423 01:18:37.362115 [0] AVG Duty = 5047%(X100)
2424 01:18:37.364565
2425 01:18:37.368500 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2426 01:18:37.369139
2427 01:18:37.371474 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2428 01:18:37.374521 [DutyScan_Calibration_Flow] ====Done====
2429 01:18:37.378254 nWR fixed to 30
2430 01:18:37.378755 [ModeRegInit_LP4] CH0 RK0
2431 01:18:37.381842 [ModeRegInit_LP4] CH0 RK1
2432 01:18:37.385125 [ModeRegInit_LP4] CH1 RK0
2433 01:18:37.388690 [ModeRegInit_LP4] CH1 RK1
2434 01:18:37.389154 match AC timing 7
2435 01:18:37.394760 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2436 01:18:37.398017 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2437 01:18:37.401391 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2438 01:18:37.408291 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2439 01:18:37.411587 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2440 01:18:37.412153 ==
2441 01:18:37.414675 Dram Type= 6, Freq= 0, CH_0, rank 0
2442 01:18:37.418413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2443 01:18:37.418876 ==
2444 01:18:37.425033 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2445 01:18:37.431139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2446 01:18:37.438823 [CA 0] Center 39 (8~70) winsize 63
2447 01:18:37.441801 [CA 1] Center 39 (8~70) winsize 63
2448 01:18:37.445024 [CA 2] Center 35 (5~66) winsize 62
2449 01:18:37.448926 [CA 3] Center 34 (4~65) winsize 62
2450 01:18:37.452106 [CA 4] Center 33 (3~64) winsize 62
2451 01:18:37.455233 [CA 5] Center 32 (3~62) winsize 60
2452 01:18:37.455816
2453 01:18:37.458602 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2454 01:18:37.459164
2455 01:18:37.461549 [CATrainingPosCal] consider 1 rank data
2456 01:18:37.464939 u2DelayCellTimex100 = 270/100 ps
2457 01:18:37.468606 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2458 01:18:37.471403 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2459 01:18:37.478202 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2460 01:18:37.481922 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2461 01:18:37.485021 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2462 01:18:37.488458 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2463 01:18:37.488921
2464 01:18:37.492194 CA PerBit enable=1, Macro0, CA PI delay=32
2465 01:18:37.492762
2466 01:18:37.494882 [CBTSetCACLKResult] CA Dly = 32
2467 01:18:37.495340 CS Dly: 6 (0~37)
2468 01:18:37.498109 ==
2469 01:18:37.498678 Dram Type= 6, Freq= 0, CH_0, rank 1
2470 01:18:37.505372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2471 01:18:37.505936 ==
2472 01:18:37.508661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2473 01:18:37.514971 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2474 01:18:37.524022 [CA 0] Center 38 (8~69) winsize 62
2475 01:18:37.527935 [CA 1] Center 38 (8~69) winsize 62
2476 01:18:37.530908 [CA 2] Center 35 (4~66) winsize 63
2477 01:18:37.534499 [CA 3] Center 34 (4~65) winsize 62
2478 01:18:37.537472 [CA 4] Center 33 (3~64) winsize 62
2479 01:18:37.541033 [CA 5] Center 32 (3~62) winsize 60
2480 01:18:37.541495
2481 01:18:37.543960 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2482 01:18:37.544455
2483 01:18:37.547691 [CATrainingPosCal] consider 2 rank data
2484 01:18:37.551191 u2DelayCellTimex100 = 270/100 ps
2485 01:18:37.554475 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2486 01:18:37.557763 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2487 01:18:37.564199 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2488 01:18:37.567865 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2489 01:18:37.571016 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2490 01:18:37.574030 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2491 01:18:37.574553
2492 01:18:37.577433 CA PerBit enable=1, Macro0, CA PI delay=32
2493 01:18:37.577908
2494 01:18:37.581195 [CBTSetCACLKResult] CA Dly = 32
2495 01:18:37.581784 CS Dly: 7 (0~39)
2496 01:18:37.582382
2497 01:18:37.584276 ----->DramcWriteLeveling(PI) begin...
2498 01:18:37.584833 ==
2499 01:18:37.587597 Dram Type= 6, Freq= 0, CH_0, rank 0
2500 01:18:37.594182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2501 01:18:37.594798 ==
2502 01:18:37.598109 Write leveling (Byte 0): 32 => 32
2503 01:18:37.601218 Write leveling (Byte 1): 32 => 32
2504 01:18:37.601695 DramcWriteLeveling(PI) end<-----
2505 01:18:37.604310
2506 01:18:37.604779 ==
2507 01:18:37.607457 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 01:18:37.610809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 01:18:37.611351 ==
2510 01:18:37.614224 [Gating] SW mode calibration
2511 01:18:37.621055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2512 01:18:37.624289 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2513 01:18:37.630683 0 15 0 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
2514 01:18:37.634455 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
2515 01:18:37.637895 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 01:18:37.644251 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 01:18:37.647518 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 01:18:37.650646 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 01:18:37.657310 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 01:18:37.660719 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2521 01:18:37.664659 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2522 01:18:37.670643 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 01:18:37.674798 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 01:18:37.677580 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 01:18:37.684522 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 01:18:37.687622 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 01:18:37.691080 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2528 01:18:37.694392 1 0 28 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
2529 01:18:37.701119 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2530 01:18:37.704264 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 01:18:37.707833 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 01:18:37.714230 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 01:18:37.717884 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 01:18:37.721057 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 01:18:37.728162 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2536 01:18:37.731024 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2537 01:18:37.734829 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2538 01:18:37.741222 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 01:18:37.744459 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 01:18:37.747764 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 01:18:37.754335 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 01:18:37.758156 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 01:18:37.761419 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 01:18:37.767533 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 01:18:37.771158 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 01:18:37.774428 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 01:18:37.781223 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 01:18:37.784478 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 01:18:37.788109 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 01:18:37.791415 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 01:18:37.797946 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 01:18:37.801948 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2553 01:18:37.804715 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2554 01:18:37.810926 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 01:18:37.814285 Total UI for P1: 0, mck2ui 16
2556 01:18:37.817798 best dqsien dly found for B0: ( 1, 3, 30)
2557 01:18:37.818246 Total UI for P1: 0, mck2ui 16
2558 01:18:37.824856 best dqsien dly found for B1: ( 1, 4, 0)
2559 01:18:37.827797 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2560 01:18:37.831026 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2561 01:18:37.831577
2562 01:18:37.834885 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2563 01:18:37.838437 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2564 01:18:37.841643 [Gating] SW calibration Done
2565 01:18:37.842213 ==
2566 01:18:37.844611 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 01:18:37.848058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 01:18:37.848632 ==
2569 01:18:37.851132 RX Vref Scan: 0
2570 01:18:37.851582
2571 01:18:37.851935 RX Vref 0 -> 0, step: 1
2572 01:18:37.852267
2573 01:18:37.854557 RX Delay -40 -> 252, step: 8
2574 01:18:37.857648 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2575 01:18:37.864636 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2576 01:18:37.867924 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2577 01:18:37.871118 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2578 01:18:37.874692 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2579 01:18:37.878278 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2580 01:18:37.881344 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2581 01:18:37.888100 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2582 01:18:37.891515 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2583 01:18:37.894392 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2584 01:18:37.897787 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2585 01:18:37.901637 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2586 01:18:37.908446 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2587 01:18:37.911427 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2588 01:18:37.915041 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2589 01:18:37.918423 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2590 01:18:37.918975 ==
2591 01:18:37.921799 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 01:18:37.928009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 01:18:37.928479 ==
2594 01:18:37.928835 DQS Delay:
2595 01:18:37.931791 DQS0 = 0, DQS1 = 0
2596 01:18:37.932240 DQM Delay:
2597 01:18:37.932594 DQM0 = 121, DQM1 = 113
2598 01:18:37.934759 DQ Delay:
2599 01:18:37.938002 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2600 01:18:37.941231 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2601 01:18:37.944618 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2602 01:18:37.947803 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2603 01:18:37.948254
2604 01:18:37.948605
2605 01:18:37.948935 ==
2606 01:18:37.951656 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 01:18:37.954748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 01:18:37.955315 ==
2609 01:18:37.958382
2610 01:18:37.958928
2611 01:18:37.959281 TX Vref Scan disable
2612 01:18:37.961689 == TX Byte 0 ==
2613 01:18:37.964656 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2614 01:18:37.968141 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2615 01:18:37.971863 == TX Byte 1 ==
2616 01:18:37.975116 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2617 01:18:37.978487 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2618 01:18:37.979056 ==
2619 01:18:37.981396 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 01:18:37.988110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 01:18:37.988650 ==
2622 01:18:37.998765 TX Vref=22, minBit 13, minWin=24, winSum=403
2623 01:18:38.001820 TX Vref=24, minBit 1, minWin=25, winSum=410
2624 01:18:38.005325 TX Vref=26, minBit 1, minWin=25, winSum=418
2625 01:18:38.008687 TX Vref=28, minBit 0, minWin=26, winSum=424
2626 01:18:38.011934 TX Vref=30, minBit 10, minWin=25, winSum=424
2627 01:18:38.018701 TX Vref=32, minBit 12, minWin=25, winSum=420
2628 01:18:38.021969 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
2629 01:18:38.022558
2630 01:18:38.025223 Final TX Range 1 Vref 28
2631 01:18:38.025771
2632 01:18:38.026125 ==
2633 01:18:38.028734 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 01:18:38.031853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 01:18:38.034865 ==
2636 01:18:38.035353
2637 01:18:38.035703
2638 01:18:38.036030 TX Vref Scan disable
2639 01:18:38.038417 == TX Byte 0 ==
2640 01:18:38.041970 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2641 01:18:38.045097 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2642 01:18:38.048702 == TX Byte 1 ==
2643 01:18:38.052052 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2644 01:18:38.055944 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2645 01:18:38.056500
2646 01:18:38.058899 [DATLAT]
2647 01:18:38.059349 Freq=1200, CH0 RK0
2648 01:18:38.059704
2649 01:18:38.061878 DATLAT Default: 0xd
2650 01:18:38.062452 0, 0xFFFF, sum = 0
2651 01:18:38.065170 1, 0xFFFF, sum = 0
2652 01:18:38.065726 2, 0xFFFF, sum = 0
2653 01:18:38.068925 3, 0xFFFF, sum = 0
2654 01:18:38.069494 4, 0xFFFF, sum = 0
2655 01:18:38.071974 5, 0xFFFF, sum = 0
2656 01:18:38.072469 6, 0xFFFF, sum = 0
2657 01:18:38.075018 7, 0xFFFF, sum = 0
2658 01:18:38.078526 8, 0xFFFF, sum = 0
2659 01:18:38.079079 9, 0xFFFF, sum = 0
2660 01:18:38.081762 10, 0xFFFF, sum = 0
2661 01:18:38.082242 11, 0xFFFF, sum = 0
2662 01:18:38.085031 12, 0x0, sum = 1
2663 01:18:38.085528 13, 0x0, sum = 2
2664 01:18:38.086011 14, 0x0, sum = 3
2665 01:18:38.089153 15, 0x0, sum = 4
2666 01:18:38.089634 best_step = 13
2667 01:18:38.090114
2668 01:18:38.091950 ==
2669 01:18:38.092425 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 01:18:38.098649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 01:18:38.099129 ==
2672 01:18:38.099611 RX Vref Scan: 1
2673 01:18:38.100059
2674 01:18:38.101973 Set Vref Range= 32 -> 127
2675 01:18:38.102485
2676 01:18:38.105254 RX Vref 32 -> 127, step: 1
2677 01:18:38.105686
2678 01:18:38.108816 RX Delay -13 -> 252, step: 4
2679 01:18:38.109338
2680 01:18:38.111826 Set Vref, RX VrefLevel [Byte0]: 32
2681 01:18:38.114984 [Byte1]: 32
2682 01:18:38.115417
2683 01:18:38.118633 Set Vref, RX VrefLevel [Byte0]: 33
2684 01:18:38.122286 [Byte1]: 33
2685 01:18:38.122847
2686 01:18:38.125455 Set Vref, RX VrefLevel [Byte0]: 34
2687 01:18:38.129092 [Byte1]: 34
2688 01:18:38.132843
2689 01:18:38.133361 Set Vref, RX VrefLevel [Byte0]: 35
2690 01:18:38.136299 [Byte1]: 35
2691 01:18:38.141296
2692 01:18:38.141843 Set Vref, RX VrefLevel [Byte0]: 36
2693 01:18:38.143749 [Byte1]: 36
2694 01:18:38.148911
2695 01:18:38.149421 Set Vref, RX VrefLevel [Byte0]: 37
2696 01:18:38.151834 [Byte1]: 37
2697 01:18:38.156291
2698 01:18:38.156798 Set Vref, RX VrefLevel [Byte0]: 38
2699 01:18:38.159400 [Byte1]: 38
2700 01:18:38.164133
2701 01:18:38.164580 Set Vref, RX VrefLevel [Byte0]: 39
2702 01:18:38.167598 [Byte1]: 39
2703 01:18:38.172125
2704 01:18:38.172713 Set Vref, RX VrefLevel [Byte0]: 40
2705 01:18:38.175291 [Byte1]: 40
2706 01:18:38.179937
2707 01:18:38.180493 Set Vref, RX VrefLevel [Byte0]: 41
2708 01:18:38.183040 [Byte1]: 41
2709 01:18:38.187870
2710 01:18:38.188421 Set Vref, RX VrefLevel [Byte0]: 42
2711 01:18:38.191351 [Byte1]: 42
2712 01:18:38.196340
2713 01:18:38.196900 Set Vref, RX VrefLevel [Byte0]: 43
2714 01:18:38.199181 [Byte1]: 43
2715 01:18:38.203636
2716 01:18:38.204097 Set Vref, RX VrefLevel [Byte0]: 44
2717 01:18:38.210478 [Byte1]: 44
2718 01:18:38.211025
2719 01:18:38.213338 Set Vref, RX VrefLevel [Byte0]: 45
2720 01:18:38.217182 [Byte1]: 45
2721 01:18:38.217900
2722 01:18:38.220603 Set Vref, RX VrefLevel [Byte0]: 46
2723 01:18:38.223822 [Byte1]: 46
2724 01:18:38.227547
2725 01:18:38.228005 Set Vref, RX VrefLevel [Byte0]: 47
2726 01:18:38.230504 [Byte1]: 47
2727 01:18:38.235691
2728 01:18:38.236242 Set Vref, RX VrefLevel [Byte0]: 48
2729 01:18:38.238347 [Byte1]: 48
2730 01:18:38.243072
2731 01:18:38.243529 Set Vref, RX VrefLevel [Byte0]: 49
2732 01:18:38.246656 [Byte1]: 49
2733 01:18:38.251135
2734 01:18:38.251681 Set Vref, RX VrefLevel [Byte0]: 50
2735 01:18:38.254574 [Byte1]: 50
2736 01:18:38.259157
2737 01:18:38.259703 Set Vref, RX VrefLevel [Byte0]: 51
2738 01:18:38.262500 [Byte1]: 51
2739 01:18:38.267397
2740 01:18:38.267954 Set Vref, RX VrefLevel [Byte0]: 52
2741 01:18:38.269956 [Byte1]: 52
2742 01:18:38.274670
2743 01:18:38.275143 Set Vref, RX VrefLevel [Byte0]: 53
2744 01:18:38.278268 [Byte1]: 53
2745 01:18:38.282441
2746 01:18:38.282915 Set Vref, RX VrefLevel [Byte0]: 54
2747 01:18:38.285787 [Byte1]: 54
2748 01:18:38.290636
2749 01:18:38.291097 Set Vref, RX VrefLevel [Byte0]: 55
2750 01:18:38.294119 [Byte1]: 55
2751 01:18:38.298392
2752 01:18:38.298876 Set Vref, RX VrefLevel [Byte0]: 56
2753 01:18:38.302196 [Byte1]: 56
2754 01:18:38.306228
2755 01:18:38.306847 Set Vref, RX VrefLevel [Byte0]: 57
2756 01:18:38.310119 [Byte1]: 57
2757 01:18:38.314426
2758 01:18:38.314918 Set Vref, RX VrefLevel [Byte0]: 58
2759 01:18:38.317732 [Byte1]: 58
2760 01:18:38.321998
2761 01:18:38.322607 Set Vref, RX VrefLevel [Byte0]: 59
2762 01:18:38.325582 [Byte1]: 59
2763 01:18:38.329794
2764 01:18:38.330386 Set Vref, RX VrefLevel [Byte0]: 60
2765 01:18:38.333343 [Byte1]: 60
2766 01:18:38.338369
2767 01:18:38.338937 Set Vref, RX VrefLevel [Byte0]: 61
2768 01:18:38.341014 [Byte1]: 61
2769 01:18:38.345756
2770 01:18:38.346205 Set Vref, RX VrefLevel [Byte0]: 62
2771 01:18:38.349126 [Byte1]: 62
2772 01:18:38.353961
2773 01:18:38.354681 Set Vref, RX VrefLevel [Byte0]: 63
2774 01:18:38.357321 [Byte1]: 63
2775 01:18:38.362071
2776 01:18:38.362667 Set Vref, RX VrefLevel [Byte0]: 64
2777 01:18:38.364992 [Byte1]: 64
2778 01:18:38.369635
2779 01:18:38.370193 Set Vref, RX VrefLevel [Byte0]: 65
2780 01:18:38.373091 [Byte1]: 65
2781 01:18:38.377698
2782 01:18:38.378259 Set Vref, RX VrefLevel [Byte0]: 66
2783 01:18:38.380414 [Byte1]: 66
2784 01:18:38.384945
2785 01:18:38.385419 Set Vref, RX VrefLevel [Byte0]: 67
2786 01:18:38.388685 [Byte1]: 67
2787 01:18:38.393646
2788 01:18:38.394216 Set Vref, RX VrefLevel [Byte0]: 68
2789 01:18:38.396613 [Byte1]: 68
2790 01:18:38.401339
2791 01:18:38.401905 Set Vref, RX VrefLevel [Byte0]: 69
2792 01:18:38.404627 [Byte1]: 69
2793 01:18:38.409080
2794 01:18:38.409644 Final RX Vref Byte 0 = 54 to rank0
2795 01:18:38.412257 Final RX Vref Byte 1 = 46 to rank0
2796 01:18:38.415396 Final RX Vref Byte 0 = 54 to rank1
2797 01:18:38.418701 Final RX Vref Byte 1 = 46 to rank1==
2798 01:18:38.421947 Dram Type= 6, Freq= 0, CH_0, rank 0
2799 01:18:38.428943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2800 01:18:38.429511 ==
2801 01:18:38.429998 DQS Delay:
2802 01:18:38.430488 DQS0 = 0, DQS1 = 0
2803 01:18:38.432779 DQM Delay:
2804 01:18:38.433348 DQM0 = 120, DQM1 = 110
2805 01:18:38.435905 DQ Delay:
2806 01:18:38.438846 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2807 01:18:38.442535 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2808 01:18:38.445351 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =102
2809 01:18:38.449089 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2810 01:18:38.449647
2811 01:18:38.450006
2812 01:18:38.455704 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2813 01:18:38.458838 CH0 RK0: MR19=404, MR18=140D
2814 01:18:38.465347 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2815 01:18:38.465903
2816 01:18:38.469084 ----->DramcWriteLeveling(PI) begin...
2817 01:18:38.469648 ==
2818 01:18:38.472018 Dram Type= 6, Freq= 0, CH_0, rank 1
2819 01:18:38.475815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 01:18:38.476270 ==
2821 01:18:38.479294 Write leveling (Byte 0): 34 => 34
2822 01:18:38.482239 Write leveling (Byte 1): 27 => 27
2823 01:18:38.485582 DramcWriteLeveling(PI) end<-----
2824 01:18:38.486034
2825 01:18:38.486423 ==
2826 01:18:38.488859 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 01:18:38.495557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 01:18:38.496018 ==
2829 01:18:38.496376 [Gating] SW mode calibration
2830 01:18:38.505946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2831 01:18:38.508822 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2832 01:18:38.512409 0 15 0 | B1->B0 | 3232 2d2d | 0 0 | (0 0) (0 0)
2833 01:18:38.518815 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 01:18:38.522161 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 01:18:38.525924 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 01:18:38.532354 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 01:18:38.535745 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 01:18:38.538987 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
2839 01:18:38.545982 0 15 28 | B1->B0 | 3131 2f2f | 0 0 | (1 0) (0 0)
2840 01:18:38.549139 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 01:18:38.552325 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 01:18:38.559223 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 01:18:38.562706 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 01:18:38.566020 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 01:18:38.568921 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 01:18:38.575861 1 0 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
2847 01:18:38.579620 1 0 28 | B1->B0 | 3a3a 3a39 | 0 1 | (0 0) (0 0)
2848 01:18:38.582630 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 01:18:38.589175 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 01:18:38.592907 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 01:18:38.595648 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 01:18:38.602491 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 01:18:38.605912 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 01:18:38.609450 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 01:18:38.616165 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2856 01:18:38.619091 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2857 01:18:38.622245 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 01:18:38.629435 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 01:18:38.632331 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 01:18:38.635634 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 01:18:38.642657 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 01:18:38.645947 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 01:18:38.649405 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 01:18:38.656164 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 01:18:38.659072 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 01:18:38.662646 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 01:18:38.669167 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 01:18:38.672619 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 01:18:38.675636 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 01:18:38.679050 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 01:18:38.686193 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2872 01:18:38.689185 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 01:18:38.692736 Total UI for P1: 0, mck2ui 16
2874 01:18:38.695602 best dqsien dly found for B0: ( 1, 3, 28)
2875 01:18:38.699241 Total UI for P1: 0, mck2ui 16
2876 01:18:38.702201 best dqsien dly found for B1: ( 1, 3, 28)
2877 01:18:38.705819 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2878 01:18:38.709541 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2879 01:18:38.710091
2880 01:18:38.712445 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2881 01:18:38.716011 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2882 01:18:38.719292 [Gating] SW calibration Done
2883 01:18:38.719746 ==
2884 01:18:38.722682 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 01:18:38.726466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 01:18:38.729041 ==
2887 01:18:38.729655 RX Vref Scan: 0
2888 01:18:38.730020
2889 01:18:38.732280 RX Vref 0 -> 0, step: 1
2890 01:18:38.732733
2891 01:18:38.736257 RX Delay -40 -> 252, step: 8
2892 01:18:38.739470 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2893 01:18:38.742857 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2894 01:18:38.746164 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2895 01:18:38.749030 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2896 01:18:38.756102 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2897 01:18:38.758868 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2898 01:18:38.762996 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2899 01:18:38.766159 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2900 01:18:38.769631 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2901 01:18:38.772584 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2902 01:18:38.779230 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2903 01:18:38.783165 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2904 01:18:38.786258 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2905 01:18:38.789545 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2906 01:18:38.793093 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2907 01:18:38.799592 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2908 01:18:38.800051 ==
2909 01:18:38.802769 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 01:18:38.806272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 01:18:38.806761 ==
2912 01:18:38.807120 DQS Delay:
2913 01:18:38.809290 DQS0 = 0, DQS1 = 0
2914 01:18:38.809745 DQM Delay:
2915 01:18:38.812600 DQM0 = 121, DQM1 = 112
2916 01:18:38.813157 DQ Delay:
2917 01:18:38.815832 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2918 01:18:38.819414 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2919 01:18:38.822712 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2920 01:18:38.826014 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2921 01:18:38.826518
2922 01:18:38.826900
2923 01:18:38.829783 ==
2924 01:18:38.832696 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 01:18:38.835990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 01:18:38.836520 ==
2927 01:18:38.836877
2928 01:18:38.837203
2929 01:18:38.839222 TX Vref Scan disable
2930 01:18:38.839673 == TX Byte 0 ==
2931 01:18:38.842867 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2932 01:18:38.849553 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2933 01:18:38.850098 == TX Byte 1 ==
2934 01:18:38.852437 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2935 01:18:38.859442 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2936 01:18:38.859997 ==
2937 01:18:38.862997 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 01:18:38.865645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 01:18:38.866170 ==
2940 01:18:38.878881 TX Vref=22, minBit 3, minWin=25, winSum=418
2941 01:18:38.881856 TX Vref=24, minBit 1, minWin=25, winSum=417
2942 01:18:38.885531 TX Vref=26, minBit 1, minWin=26, winSum=421
2943 01:18:38.889316 TX Vref=28, minBit 1, minWin=26, winSum=429
2944 01:18:38.892312 TX Vref=30, minBit 1, minWin=26, winSum=429
2945 01:18:38.895652 TX Vref=32, minBit 0, minWin=26, winSum=429
2946 01:18:38.902285 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
2947 01:18:38.902871
2948 01:18:38.905711 Final TX Range 1 Vref 28
2949 01:18:38.906419
2950 01:18:38.906796 ==
2951 01:18:38.908567 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 01:18:38.912241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 01:18:38.912793 ==
2954 01:18:38.913153
2955 01:18:38.913481
2956 01:18:38.915779 TX Vref Scan disable
2957 01:18:38.918840 == TX Byte 0 ==
2958 01:18:38.922586 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2959 01:18:38.925684 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2960 01:18:38.929091 == TX Byte 1 ==
2961 01:18:38.932424 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2962 01:18:38.936011 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2963 01:18:38.936465
2964 01:18:38.939014 [DATLAT]
2965 01:18:38.939465 Freq=1200, CH0 RK1
2966 01:18:38.939818
2967 01:18:38.942387 DATLAT Default: 0xd
2968 01:18:38.942840 0, 0xFFFF, sum = 0
2969 01:18:38.945825 1, 0xFFFF, sum = 0
2970 01:18:38.946368 2, 0xFFFF, sum = 0
2971 01:18:38.949001 3, 0xFFFF, sum = 0
2972 01:18:38.949459 4, 0xFFFF, sum = 0
2973 01:18:38.952308 5, 0xFFFF, sum = 0
2974 01:18:38.952765 6, 0xFFFF, sum = 0
2975 01:18:38.956075 7, 0xFFFF, sum = 0
2976 01:18:38.956531 8, 0xFFFF, sum = 0
2977 01:18:38.959139 9, 0xFFFF, sum = 0
2978 01:18:38.959699 10, 0xFFFF, sum = 0
2979 01:18:38.962998 11, 0xFFFF, sum = 0
2980 01:18:38.963573 12, 0x0, sum = 1
2981 01:18:38.966050 13, 0x0, sum = 2
2982 01:18:38.966658 14, 0x0, sum = 3
2983 01:18:38.969179 15, 0x0, sum = 4
2984 01:18:38.969791 best_step = 13
2985 01:18:38.970156
2986 01:18:38.970544 ==
2987 01:18:38.972051 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 01:18:38.978987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 01:18:38.979564 ==
2990 01:18:38.979923 RX Vref Scan: 0
2991 01:18:38.980252
2992 01:18:38.982353 RX Vref 0 -> 0, step: 1
2993 01:18:38.982806
2994 01:18:38.985838 RX Delay -13 -> 252, step: 4
2995 01:18:38.989185 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
2996 01:18:38.992237 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
2997 01:18:38.999411 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2998 01:18:39.002819 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
2999 01:18:39.006136 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3000 01:18:39.009377 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3001 01:18:39.012483 iDelay=195, Bit 6, Center 126 (63 ~ 190) 128
3002 01:18:39.015902 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3003 01:18:39.022435 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3004 01:18:39.025561 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3005 01:18:39.029666 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3006 01:18:39.032828 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3007 01:18:39.036129 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3008 01:18:39.042911 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3009 01:18:39.045677 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3010 01:18:39.049378 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3011 01:18:39.049925 ==
3012 01:18:39.052647 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 01:18:39.056398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 01:18:39.059520 ==
3015 01:18:39.059971 DQS Delay:
3016 01:18:39.060324 DQS0 = 0, DQS1 = 0
3017 01:18:39.062775 DQM Delay:
3018 01:18:39.063224 DQM0 = 120, DQM1 = 109
3019 01:18:39.065827 DQ Delay:
3020 01:18:39.069438 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3021 01:18:39.072248 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3022 01:18:39.075691 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3023 01:18:39.078791 DQ12 =114, DQ13 =114, DQ14 =122, DQ15 =118
3024 01:18:39.079243
3025 01:18:39.079595
3026 01:18:39.085701 [DQSOSCAuto] RK1, (LSB)MR18= 0xff0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3027 01:18:39.089069 CH0 RK1: MR19=403, MR18=FF0
3028 01:18:39.095891 CH0_RK1: MR19=0x403, MR18=0xFF0, DQSOSC=404, MR23=63, INC=40, DEC=26
3029 01:18:39.099092 [RxdqsGatingPostProcess] freq 1200
3030 01:18:39.105870 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3031 01:18:39.106483 best DQS0 dly(2T, 0.5T) = (0, 11)
3032 01:18:39.109080 best DQS1 dly(2T, 0.5T) = (0, 12)
3033 01:18:39.113142 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3034 01:18:39.115452 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3035 01:18:39.119131 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 01:18:39.122159 best DQS1 dly(2T, 0.5T) = (0, 11)
3037 01:18:39.125833 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 01:18:39.128748 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3039 01:18:39.132655 Pre-setting of DQS Precalculation
3040 01:18:39.136022 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3041 01:18:39.139501 ==
3042 01:18:39.140053 Dram Type= 6, Freq= 0, CH_1, rank 0
3043 01:18:39.146079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 01:18:39.146726 ==
3045 01:18:39.149546 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3046 01:18:39.156408 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3047 01:18:39.165248 [CA 0] Center 37 (7~68) winsize 62
3048 01:18:39.168010 [CA 1] Center 37 (7~68) winsize 62
3049 01:18:39.171556 [CA 2] Center 35 (5~65) winsize 61
3050 01:18:39.174731 [CA 3] Center 34 (4~64) winsize 61
3051 01:18:39.178047 [CA 4] Center 34 (4~64) winsize 61
3052 01:18:39.182014 [CA 5] Center 33 (3~63) winsize 61
3053 01:18:39.182636
3054 01:18:39.185274 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3055 01:18:39.185736
3056 01:18:39.188301 [CATrainingPosCal] consider 1 rank data
3057 01:18:39.191387 u2DelayCellTimex100 = 270/100 ps
3058 01:18:39.194837 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3059 01:18:39.198012 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3060 01:18:39.205512 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3061 01:18:39.208517 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3062 01:18:39.211848 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3063 01:18:39.215065 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3064 01:18:39.215627
3065 01:18:39.218297 CA PerBit enable=1, Macro0, CA PI delay=33
3066 01:18:39.218897
3067 01:18:39.221319 [CBTSetCACLKResult] CA Dly = 33
3068 01:18:39.221769 CS Dly: 7 (0~38)
3069 01:18:39.222122 ==
3070 01:18:39.224636 Dram Type= 6, Freq= 0, CH_1, rank 1
3071 01:18:39.231166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 01:18:39.231623 ==
3073 01:18:39.235028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 01:18:39.241362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3075 01:18:39.250537 [CA 0] Center 37 (7~68) winsize 62
3076 01:18:39.253623 [CA 1] Center 38 (8~68) winsize 61
3077 01:18:39.257844 [CA 2] Center 35 (5~65) winsize 61
3078 01:18:39.260399 [CA 3] Center 34 (4~65) winsize 62
3079 01:18:39.263332 [CA 4] Center 34 (4~65) winsize 62
3080 01:18:39.267207 [CA 5] Center 34 (4~64) winsize 61
3081 01:18:39.267771
3082 01:18:39.270288 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3083 01:18:39.270833
3084 01:18:39.273821 [CATrainingPosCal] consider 2 rank data
3085 01:18:39.276630 u2DelayCellTimex100 = 270/100 ps
3086 01:18:39.280267 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 01:18:39.286996 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3088 01:18:39.290205 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3089 01:18:39.294051 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 01:18:39.297119 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 01:18:39.300316 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3092 01:18:39.300775
3093 01:18:39.303346 CA PerBit enable=1, Macro0, CA PI delay=33
3094 01:18:39.303799
3095 01:18:39.307006 [CBTSetCACLKResult] CA Dly = 33
3096 01:18:39.307460 CS Dly: 8 (0~41)
3097 01:18:39.309860
3098 01:18:39.313656 ----->DramcWriteLeveling(PI) begin...
3099 01:18:39.314213 ==
3100 01:18:39.316667 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 01:18:39.320266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 01:18:39.320815 ==
3103 01:18:39.323262 Write leveling (Byte 0): 26 => 26
3104 01:18:39.326756 Write leveling (Byte 1): 27 => 27
3105 01:18:39.330290 DramcWriteLeveling(PI) end<-----
3106 01:18:39.330906
3107 01:18:39.331261 ==
3108 01:18:39.333631 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 01:18:39.337457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 01:18:39.338058 ==
3111 01:18:39.339901 [Gating] SW mode calibration
3112 01:18:39.347036 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3113 01:18:39.350433 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3114 01:18:39.357141 0 15 0 | B1->B0 | 3433 3434 | 1 1 | (1 1) (1 1)
3115 01:18:39.360390 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 01:18:39.363917 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 01:18:39.370286 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 01:18:39.374047 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 01:18:39.377302 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 01:18:39.383613 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
3121 01:18:39.387188 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3122 01:18:39.390525 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 01:18:39.397521 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 01:18:39.400541 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 01:18:39.403601 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 01:18:39.410878 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 01:18:39.413683 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 01:18:39.416785 1 0 24 | B1->B0 | 2c2c 403f | 0 1 | (0 0) (0 0)
3129 01:18:39.423859 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 01:18:39.426979 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 01:18:39.430210 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 01:18:39.434112 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 01:18:39.440588 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 01:18:39.443767 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 01:18:39.447226 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 01:18:39.453787 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3137 01:18:39.457252 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3138 01:18:39.460324 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 01:18:39.467110 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 01:18:39.470457 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 01:18:39.473542 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 01:18:39.479954 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 01:18:39.483286 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 01:18:39.486889 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 01:18:39.493405 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 01:18:39.496582 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 01:18:39.500142 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 01:18:39.506808 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 01:18:39.510349 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 01:18:39.513949 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 01:18:39.520030 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 01:18:39.523675 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3153 01:18:39.526756 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 01:18:39.530029 Total UI for P1: 0, mck2ui 16
3155 01:18:39.533895 best dqsien dly found for B0: ( 1, 3, 24)
3156 01:18:39.537464 Total UI for P1: 0, mck2ui 16
3157 01:18:39.540103 best dqsien dly found for B1: ( 1, 3, 24)
3158 01:18:39.543593 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3159 01:18:39.546760 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3160 01:18:39.547192
3161 01:18:39.550172 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3162 01:18:39.556932 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3163 01:18:39.557497 [Gating] SW calibration Done
3164 01:18:39.557980 ==
3165 01:18:39.561314 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 01:18:39.567360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 01:18:39.567934 ==
3168 01:18:39.568419 RX Vref Scan: 0
3169 01:18:39.568867
3170 01:18:39.570420 RX Vref 0 -> 0, step: 1
3171 01:18:39.570840
3172 01:18:39.574065 RX Delay -40 -> 252, step: 8
3173 01:18:39.576957 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3174 01:18:39.580863 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3175 01:18:39.583614 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3176 01:18:39.587253 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3177 01:18:39.593874 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3178 01:18:39.597060 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3179 01:18:39.600500 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3180 01:18:39.603386 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3181 01:18:39.606809 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
3182 01:18:39.613678 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3183 01:18:39.617046 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3184 01:18:39.620382 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3185 01:18:39.623798 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3186 01:18:39.627393 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3187 01:18:39.633559 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3188 01:18:39.637101 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3189 01:18:39.637657 ==
3190 01:18:39.640719 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 01:18:39.644143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 01:18:39.644662 ==
3193 01:18:39.646964 DQS Delay:
3194 01:18:39.647381 DQS0 = 0, DQS1 = 0
3195 01:18:39.647710 DQM Delay:
3196 01:18:39.650515 DQM0 = 120, DQM1 = 117
3197 01:18:39.651020 DQ Delay:
3198 01:18:39.653986 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3199 01:18:39.657371 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3200 01:18:39.660975 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =111
3201 01:18:39.667454 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3202 01:18:39.667969
3203 01:18:39.668297
3204 01:18:39.668602 ==
3205 01:18:39.670887 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 01:18:39.673883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 01:18:39.674441 ==
3208 01:18:39.674875
3209 01:18:39.675281
3210 01:18:39.677068 TX Vref Scan disable
3211 01:18:39.677497 == TX Byte 0 ==
3212 01:18:39.683652 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3213 01:18:39.687204 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3214 01:18:39.687718 == TX Byte 1 ==
3215 01:18:39.694025 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3216 01:18:39.697359 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3217 01:18:39.697874 ==
3218 01:18:39.700690 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 01:18:39.703925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 01:18:39.704355 ==
3221 01:18:39.716241 TX Vref=22, minBit 9, minWin=24, winSum=408
3222 01:18:39.719534 TX Vref=24, minBit 1, minWin=25, winSum=413
3223 01:18:39.723097 TX Vref=26, minBit 1, minWin=26, winSum=424
3224 01:18:39.726182 TX Vref=28, minBit 1, minWin=26, winSum=426
3225 01:18:39.729294 TX Vref=30, minBit 1, minWin=26, winSum=432
3226 01:18:39.732697 TX Vref=32, minBit 2, minWin=26, winSum=433
3227 01:18:39.739669 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 32
3228 01:18:39.740289
3229 01:18:39.743453 Final TX Range 1 Vref 32
3230 01:18:39.744064
3231 01:18:39.744601 ==
3232 01:18:39.746120 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 01:18:39.749197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 01:18:39.749654 ==
3235 01:18:39.750008
3236 01:18:39.753475
3237 01:18:39.754083 TX Vref Scan disable
3238 01:18:39.756828 == TX Byte 0 ==
3239 01:18:39.759898 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3240 01:18:39.762557 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3241 01:18:39.766259 == TX Byte 1 ==
3242 01:18:39.769592 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3243 01:18:39.773284 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3244 01:18:39.773838
3245 01:18:39.776494 [DATLAT]
3246 01:18:39.776972 Freq=1200, CH1 RK0
3247 01:18:39.777330
3248 01:18:39.779752 DATLAT Default: 0xd
3249 01:18:39.780211 0, 0xFFFF, sum = 0
3250 01:18:39.783219 1, 0xFFFF, sum = 0
3251 01:18:39.783824 2, 0xFFFF, sum = 0
3252 01:18:39.786589 3, 0xFFFF, sum = 0
3253 01:18:39.787150 4, 0xFFFF, sum = 0
3254 01:18:39.789835 5, 0xFFFF, sum = 0
3255 01:18:39.790439 6, 0xFFFF, sum = 0
3256 01:18:39.793005 7, 0xFFFF, sum = 0
3257 01:18:39.793566 8, 0xFFFF, sum = 0
3258 01:18:39.796017 9, 0xFFFF, sum = 0
3259 01:18:39.799540 10, 0xFFFF, sum = 0
3260 01:18:39.800098 11, 0xFFFF, sum = 0
3261 01:18:39.802655 12, 0x0, sum = 1
3262 01:18:39.803211 13, 0x0, sum = 2
3263 01:18:39.803584 14, 0x0, sum = 3
3264 01:18:39.806666 15, 0x0, sum = 4
3265 01:18:39.807134 best_step = 13
3266 01:18:39.807494
3267 01:18:39.807829 ==
3268 01:18:39.809527 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 01:18:39.816477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 01:18:39.817041 ==
3271 01:18:39.817401 RX Vref Scan: 1
3272 01:18:39.817740
3273 01:18:39.819979 Set Vref Range= 32 -> 127
3274 01:18:39.820440
3275 01:18:39.822887 RX Vref 32 -> 127, step: 1
3276 01:18:39.823303
3277 01:18:39.823643 RX Delay -5 -> 252, step: 4
3278 01:18:39.826588
3279 01:18:39.827006 Set Vref, RX VrefLevel [Byte0]: 32
3280 01:18:39.829638 [Byte1]: 32
3281 01:18:39.834621
3282 01:18:39.835217 Set Vref, RX VrefLevel [Byte0]: 33
3283 01:18:39.837475 [Byte1]: 33
3284 01:18:39.842418
3285 01:18:39.842850 Set Vref, RX VrefLevel [Byte0]: 34
3286 01:18:39.845741 [Byte1]: 34
3287 01:18:39.850149
3288 01:18:39.850706 Set Vref, RX VrefLevel [Byte0]: 35
3289 01:18:39.853392 [Byte1]: 35
3290 01:18:39.857623
3291 01:18:39.858123 Set Vref, RX VrefLevel [Byte0]: 36
3292 01:18:39.861017 [Byte1]: 36
3293 01:18:39.865692
3294 01:18:39.866098 Set Vref, RX VrefLevel [Byte0]: 37
3295 01:18:39.868991 [Byte1]: 37
3296 01:18:39.873258
3297 01:18:39.873774 Set Vref, RX VrefLevel [Byte0]: 38
3298 01:18:39.876922 [Byte1]: 38
3299 01:18:39.881048
3300 01:18:39.881607 Set Vref, RX VrefLevel [Byte0]: 39
3301 01:18:39.884253 [Byte1]: 39
3302 01:18:39.889031
3303 01:18:39.889442 Set Vref, RX VrefLevel [Byte0]: 40
3304 01:18:39.892229 [Byte1]: 40
3305 01:18:39.897216
3306 01:18:39.897721 Set Vref, RX VrefLevel [Byte0]: 41
3307 01:18:39.900034 [Byte1]: 41
3308 01:18:39.904661
3309 01:18:39.905081 Set Vref, RX VrefLevel [Byte0]: 42
3310 01:18:39.908015 [Byte1]: 42
3311 01:18:39.912558
3312 01:18:39.912972 Set Vref, RX VrefLevel [Byte0]: 43
3313 01:18:39.915704 [Byte1]: 43
3314 01:18:39.920268
3315 01:18:39.920677 Set Vref, RX VrefLevel [Byte0]: 44
3316 01:18:39.924039 [Byte1]: 44
3317 01:18:39.928493
3318 01:18:39.928903 Set Vref, RX VrefLevel [Byte0]: 45
3319 01:18:39.931660 [Byte1]: 45
3320 01:18:39.936678
3321 01:18:39.937183 Set Vref, RX VrefLevel [Byte0]: 46
3322 01:18:39.939590 [Byte1]: 46
3323 01:18:39.944312
3324 01:18:39.944812 Set Vref, RX VrefLevel [Byte0]: 47
3325 01:18:39.947833 [Byte1]: 47
3326 01:18:39.952322
3327 01:18:39.952822 Set Vref, RX VrefLevel [Byte0]: 48
3328 01:18:39.955646 [Byte1]: 48
3329 01:18:39.959905
3330 01:18:39.960345 Set Vref, RX VrefLevel [Byte0]: 49
3331 01:18:39.963229 [Byte1]: 49
3332 01:18:39.967639
3333 01:18:39.968049 Set Vref, RX VrefLevel [Byte0]: 50
3334 01:18:39.971095 [Byte1]: 50
3335 01:18:39.975615
3336 01:18:39.976124 Set Vref, RX VrefLevel [Byte0]: 51
3337 01:18:39.978641 [Byte1]: 51
3338 01:18:39.983333
3339 01:18:39.983837 Set Vref, RX VrefLevel [Byte0]: 52
3340 01:18:39.986810 [Byte1]: 52
3341 01:18:39.991561
3342 01:18:39.992156 Set Vref, RX VrefLevel [Byte0]: 53
3343 01:18:39.994679 [Byte1]: 53
3344 01:18:39.999406
3345 01:18:39.999955 Set Vref, RX VrefLevel [Byte0]: 54
3346 01:18:40.002650 [Byte1]: 54
3347 01:18:40.007207
3348 01:18:40.007762 Set Vref, RX VrefLevel [Byte0]: 55
3349 01:18:40.010562 [Byte1]: 55
3350 01:18:40.015221
3351 01:18:40.015765 Set Vref, RX VrefLevel [Byte0]: 56
3352 01:18:40.018527 [Byte1]: 56
3353 01:18:40.023155
3354 01:18:40.023704 Set Vref, RX VrefLevel [Byte0]: 57
3355 01:18:40.026235 [Byte1]: 57
3356 01:18:40.030470
3357 01:18:40.030928 Set Vref, RX VrefLevel [Byte0]: 58
3358 01:18:40.033986 [Byte1]: 58
3359 01:18:40.038520
3360 01:18:40.039060 Set Vref, RX VrefLevel [Byte0]: 59
3361 01:18:40.041758 [Byte1]: 59
3362 01:18:40.046459
3363 01:18:40.047009 Set Vref, RX VrefLevel [Byte0]: 60
3364 01:18:40.049437 [Byte1]: 60
3365 01:18:40.053881
3366 01:18:40.054491 Set Vref, RX VrefLevel [Byte0]: 61
3367 01:18:40.057985 [Byte1]: 61
3368 01:18:40.062355
3369 01:18:40.062958 Set Vref, RX VrefLevel [Byte0]: 62
3370 01:18:40.065407 [Byte1]: 62
3371 01:18:40.069629
3372 01:18:40.070178 Set Vref, RX VrefLevel [Byte0]: 63
3373 01:18:40.072759 [Byte1]: 63
3374 01:18:40.077655
3375 01:18:40.078112 Set Vref, RX VrefLevel [Byte0]: 64
3376 01:18:40.080970 [Byte1]: 64
3377 01:18:40.085397
3378 01:18:40.085951 Set Vref, RX VrefLevel [Byte0]: 65
3379 01:18:40.088629 [Byte1]: 65
3380 01:18:40.093150
3381 01:18:40.093835 Set Vref, RX VrefLevel [Byte0]: 66
3382 01:18:40.096599 [Byte1]: 66
3383 01:18:40.101507
3384 01:18:40.102040 Set Vref, RX VrefLevel [Byte0]: 67
3385 01:18:40.104350 [Byte1]: 67
3386 01:18:40.109419
3387 01:18:40.109992 Set Vref, RX VrefLevel [Byte0]: 68
3388 01:18:40.112580 [Byte1]: 68
3389 01:18:40.116879
3390 01:18:40.117402 Set Vref, RX VrefLevel [Byte0]: 69
3391 01:18:40.120127 [Byte1]: 69
3392 01:18:40.124742
3393 01:18:40.125267 Set Vref, RX VrefLevel [Byte0]: 70
3394 01:18:40.127687 [Byte1]: 70
3395 01:18:40.132864
3396 01:18:40.133295 Set Vref, RX VrefLevel [Byte0]: 71
3397 01:18:40.135987 [Byte1]: 71
3398 01:18:40.140322
3399 01:18:40.140932 Final RX Vref Byte 0 = 53 to rank0
3400 01:18:40.143974 Final RX Vref Byte 1 = 53 to rank0
3401 01:18:40.147449 Final RX Vref Byte 0 = 53 to rank1
3402 01:18:40.150798 Final RX Vref Byte 1 = 53 to rank1==
3403 01:18:40.153996 Dram Type= 6, Freq= 0, CH_1, rank 0
3404 01:18:40.160378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3405 01:18:40.160950 ==
3406 01:18:40.161440 DQS Delay:
3407 01:18:40.161893 DQS0 = 0, DQS1 = 0
3408 01:18:40.163665 DQM Delay:
3409 01:18:40.164137 DQM0 = 120, DQM1 = 117
3410 01:18:40.167820 DQ Delay:
3411 01:18:40.170860 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =118
3412 01:18:40.174126 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3413 01:18:40.177002 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3414 01:18:40.180398 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =124
3415 01:18:40.180970
3416 01:18:40.181453
3417 01:18:40.187411 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3418 01:18:40.190489 CH1 RK0: MR19=404, MR18=114
3419 01:18:40.196783 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3420 01:18:40.197339
3421 01:18:40.200428 ----->DramcWriteLeveling(PI) begin...
3422 01:18:40.201042 ==
3423 01:18:40.203973 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 01:18:40.207050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 01:18:40.210399 ==
3426 01:18:40.210858 Write leveling (Byte 0): 26 => 26
3427 01:18:40.213361 Write leveling (Byte 1): 29 => 29
3428 01:18:40.217424 DramcWriteLeveling(PI) end<-----
3429 01:18:40.217995
3430 01:18:40.218404 ==
3431 01:18:40.220015 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 01:18:40.226705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 01:18:40.227122 ==
3434 01:18:40.227447 [Gating] SW mode calibration
3435 01:18:40.236858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3436 01:18:40.240175 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3437 01:18:40.244071 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 01:18:40.249961 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 01:18:40.253235 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 01:18:40.256540 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 01:18:40.263523 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 01:18:40.266674 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3443 01:18:40.269992 0 15 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 1) (1 0)
3444 01:18:40.277395 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3445 01:18:40.280593 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 01:18:40.283412 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 01:18:40.290258 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 01:18:40.293656 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 01:18:40.297427 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 01:18:40.303833 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3451 01:18:40.307029 1 0 24 | B1->B0 | 4040 2929 | 0 0 | (0 0) (0 0)
3452 01:18:40.310429 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3453 01:18:40.317016 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 01:18:40.320442 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 01:18:40.323315 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 01:18:40.330388 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 01:18:40.333782 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 01:18:40.336779 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 01:18:40.343623 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3460 01:18:40.346798 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3461 01:18:40.350197 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3462 01:18:40.353711 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 01:18:40.360597 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 01:18:40.363364 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 01:18:40.366625 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 01:18:40.373503 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 01:18:40.376833 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 01:18:40.380077 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 01:18:40.386368 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 01:18:40.389858 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 01:18:40.392940 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 01:18:40.399994 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 01:18:40.403334 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 01:18:40.406625 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3475 01:18:40.413290 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3476 01:18:40.416430 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3477 01:18:40.419519 Total UI for P1: 0, mck2ui 16
3478 01:18:40.422733 best dqsien dly found for B1: ( 1, 3, 22)
3479 01:18:40.426350 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 01:18:40.429919 Total UI for P1: 0, mck2ui 16
3481 01:18:40.432748 best dqsien dly found for B0: ( 1, 3, 26)
3482 01:18:40.436044 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3483 01:18:40.439492 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3484 01:18:40.440050
3485 01:18:40.446853 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3486 01:18:40.449988 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3487 01:18:40.450588 [Gating] SW calibration Done
3488 01:18:40.453066 ==
3489 01:18:40.455917 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 01:18:40.459625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 01:18:40.460184 ==
3492 01:18:40.460553 RX Vref Scan: 0
3493 01:18:40.460892
3494 01:18:40.462820 RX Vref 0 -> 0, step: 1
3495 01:18:40.463275
3496 01:18:40.466400 RX Delay -40 -> 252, step: 8
3497 01:18:40.469967 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3498 01:18:40.473229 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3499 01:18:40.479629 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3500 01:18:40.483390 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3501 01:18:40.486411 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3502 01:18:40.489670 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3503 01:18:40.492874 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3504 01:18:40.496608 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3505 01:18:40.502857 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3506 01:18:40.506063 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3507 01:18:40.509438 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3508 01:18:40.513143 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3509 01:18:40.516008 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3510 01:18:40.522912 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3511 01:18:40.526424 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3512 01:18:40.529740 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3513 01:18:40.530199 ==
3514 01:18:40.532992 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 01:18:40.536204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 01:18:40.539258 ==
3517 01:18:40.539673 DQS Delay:
3518 01:18:40.539998 DQS0 = 0, DQS1 = 0
3519 01:18:40.542297 DQM Delay:
3520 01:18:40.542744 DQM0 = 120, DQM1 = 118
3521 01:18:40.545968 DQ Delay:
3522 01:18:40.549680 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =119
3523 01:18:40.552844 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3524 01:18:40.555930 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =115
3525 01:18:40.559423 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3526 01:18:40.560117
3527 01:18:40.560653
3528 01:18:40.561169 ==
3529 01:18:40.562475 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 01:18:40.565862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 01:18:40.566421 ==
3532 01:18:40.569360
3533 01:18:40.569775
3534 01:18:40.570101 TX Vref Scan disable
3535 01:18:40.572593 == TX Byte 0 ==
3536 01:18:40.576020 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3537 01:18:40.579339 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3538 01:18:40.582425 == TX Byte 1 ==
3539 01:18:40.585604 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3540 01:18:40.589725 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3541 01:18:40.590239 ==
3542 01:18:40.592740 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 01:18:40.598869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 01:18:40.599377 ==
3545 01:18:40.610176 TX Vref=22, minBit 1, minWin=25, winSum=419
3546 01:18:40.613227 TX Vref=24, minBit 1, minWin=26, winSum=426
3547 01:18:40.616491 TX Vref=26, minBit 4, minWin=26, winSum=427
3548 01:18:40.619500 TX Vref=28, minBit 2, minWin=26, winSum=431
3549 01:18:40.623039 TX Vref=30, minBit 9, minWin=26, winSum=435
3550 01:18:40.629392 TX Vref=32, minBit 0, minWin=27, winSum=435
3551 01:18:40.633204 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 32
3552 01:18:40.633759
3553 01:18:40.636433 Final TX Range 1 Vref 32
3554 01:18:40.637050
3555 01:18:40.637418 ==
3556 01:18:40.639616 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 01:18:40.642867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 01:18:40.646285 ==
3559 01:18:40.646887
3560 01:18:40.647245
3561 01:18:40.647574 TX Vref Scan disable
3562 01:18:40.649990 == TX Byte 0 ==
3563 01:18:40.653225 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3564 01:18:40.659220 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3565 01:18:40.659681 == TX Byte 1 ==
3566 01:18:40.662958 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3567 01:18:40.669484 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3568 01:18:40.670038
3569 01:18:40.670457 [DATLAT]
3570 01:18:40.670799 Freq=1200, CH1 RK1
3571 01:18:40.671118
3572 01:18:40.672585 DATLAT Default: 0xd
3573 01:18:40.673084 0, 0xFFFF, sum = 0
3574 01:18:40.675748 1, 0xFFFF, sum = 0
3575 01:18:40.678827 2, 0xFFFF, sum = 0
3576 01:18:40.679286 3, 0xFFFF, sum = 0
3577 01:18:40.682823 4, 0xFFFF, sum = 0
3578 01:18:40.683380 5, 0xFFFF, sum = 0
3579 01:18:40.685667 6, 0xFFFF, sum = 0
3580 01:18:40.686142 7, 0xFFFF, sum = 0
3581 01:18:40.689196 8, 0xFFFF, sum = 0
3582 01:18:40.689759 9, 0xFFFF, sum = 0
3583 01:18:40.692944 10, 0xFFFF, sum = 0
3584 01:18:40.693413 11, 0xFFFF, sum = 0
3585 01:18:40.695681 12, 0x0, sum = 1
3586 01:18:40.696149 13, 0x0, sum = 2
3587 01:18:40.699016 14, 0x0, sum = 3
3588 01:18:40.699482 15, 0x0, sum = 4
3589 01:18:40.702132 best_step = 13
3590 01:18:40.702624
3591 01:18:40.702983 ==
3592 01:18:40.705605 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 01:18:40.708688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 01:18:40.709150 ==
3595 01:18:40.709518 RX Vref Scan: 0
3596 01:18:40.712003
3597 01:18:40.712420 RX Vref 0 -> 0, step: 1
3598 01:18:40.712746
3599 01:18:40.715177 RX Delay -5 -> 252, step: 4
3600 01:18:40.718713 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3601 01:18:40.725378 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3602 01:18:40.728440 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3603 01:18:40.731823 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3604 01:18:40.735328 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3605 01:18:40.739228 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3606 01:18:40.745585 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3607 01:18:40.748848 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3608 01:18:40.752140 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3609 01:18:40.755360 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3610 01:18:40.758661 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3611 01:18:40.765300 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3612 01:18:40.768532 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3613 01:18:40.772239 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3614 01:18:40.775250 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3615 01:18:40.782101 iDelay=195, Bit 15, Center 126 (63 ~ 190) 128
3616 01:18:40.782688 ==
3617 01:18:40.785229 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 01:18:40.788833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 01:18:40.789391 ==
3620 01:18:40.789755 DQS Delay:
3621 01:18:40.792128 DQS0 = 0, DQS1 = 0
3622 01:18:40.792684 DQM Delay:
3623 01:18:40.795278 DQM0 = 120, DQM1 = 118
3624 01:18:40.795738 DQ Delay:
3625 01:18:40.798628 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3626 01:18:40.801965 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3627 01:18:40.805228 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3628 01:18:40.808450 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3629 01:18:40.808913
3630 01:18:40.809271
3631 01:18:40.818413 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3632 01:18:40.821663 CH1 RK1: MR19=403, MR18=12EF
3633 01:18:40.825003 CH1_RK1: MR19=0x403, MR18=0x12EF, DQSOSC=403, MR23=63, INC=40, DEC=26
3634 01:18:40.828741 [RxdqsGatingPostProcess] freq 1200
3635 01:18:40.835132 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3636 01:18:40.838130 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 01:18:40.841863 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 01:18:40.844875 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 01:18:40.848284 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 01:18:40.851434 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 01:18:40.854847 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 01:18:40.858544 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 01:18:40.862020 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 01:18:40.865385 Pre-setting of DQS Precalculation
3645 01:18:40.868488 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3646 01:18:40.874815 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3647 01:18:40.881680 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3648 01:18:40.884888
3649 01:18:40.885440
3650 01:18:40.885795 [Calibration Summary] 2400 Mbps
3651 01:18:40.888201 CH 0, Rank 0
3652 01:18:40.888654 SW Impedance : PASS
3653 01:18:40.891578 DUTY Scan : NO K
3654 01:18:40.895034 ZQ Calibration : PASS
3655 01:18:40.895487 Jitter Meter : NO K
3656 01:18:40.898291 CBT Training : PASS
3657 01:18:40.901770 Write leveling : PASS
3658 01:18:40.902371 RX DQS gating : PASS
3659 01:18:40.904833 RX DQ/DQS(RDDQC) : PASS
3660 01:18:40.908037 TX DQ/DQS : PASS
3661 01:18:40.908490 RX DATLAT : PASS
3662 01:18:40.911221 RX DQ/DQS(Engine): PASS
3663 01:18:40.914728 TX OE : NO K
3664 01:18:40.915289 All Pass.
3665 01:18:40.915659
3666 01:18:40.916111 CH 0, Rank 1
3667 01:18:40.917881 SW Impedance : PASS
3668 01:18:40.921467 DUTY Scan : NO K
3669 01:18:40.922013 ZQ Calibration : PASS
3670 01:18:40.924800 Jitter Meter : NO K
3671 01:18:40.927394 CBT Training : PASS
3672 01:18:40.927848 Write leveling : PASS
3673 01:18:40.930665 RX DQS gating : PASS
3674 01:18:40.934448 RX DQ/DQS(RDDQC) : PASS
3675 01:18:40.935096 TX DQ/DQS : PASS
3676 01:18:40.937856 RX DATLAT : PASS
3677 01:18:40.940791 RX DQ/DQS(Engine): PASS
3678 01:18:40.941240 TX OE : NO K
3679 01:18:40.941598 All Pass.
3680 01:18:40.944380
3681 01:18:40.944834 CH 1, Rank 0
3682 01:18:40.947544 SW Impedance : PASS
3683 01:18:40.948008 DUTY Scan : NO K
3684 01:18:40.950898 ZQ Calibration : PASS
3685 01:18:40.951351 Jitter Meter : NO K
3686 01:18:40.954081 CBT Training : PASS
3687 01:18:40.957713 Write leveling : PASS
3688 01:18:40.958258 RX DQS gating : PASS
3689 01:18:40.961070 RX DQ/DQS(RDDQC) : PASS
3690 01:18:40.964313 TX DQ/DQS : PASS
3691 01:18:40.964767 RX DATLAT : PASS
3692 01:18:40.967606 RX DQ/DQS(Engine): PASS
3693 01:18:40.970943 TX OE : NO K
3694 01:18:40.971410 All Pass.
3695 01:18:40.971772
3696 01:18:40.972105 CH 1, Rank 1
3697 01:18:40.973943 SW Impedance : PASS
3698 01:18:40.977368 DUTY Scan : NO K
3699 01:18:40.977828 ZQ Calibration : PASS
3700 01:18:40.980938 Jitter Meter : NO K
3701 01:18:40.983983 CBT Training : PASS
3702 01:18:40.984446 Write leveling : PASS
3703 01:18:40.987261 RX DQS gating : PASS
3704 01:18:40.990749 RX DQ/DQS(RDDQC) : PASS
3705 01:18:40.991302 TX DQ/DQS : PASS
3706 01:18:40.993708 RX DATLAT : PASS
3707 01:18:40.996883 RX DQ/DQS(Engine): PASS
3708 01:18:40.997371 TX OE : NO K
3709 01:18:40.997740 All Pass.
3710 01:18:41.000869
3711 01:18:41.001419 DramC Write-DBI off
3712 01:18:41.004109 PER_BANK_REFRESH: Hybrid Mode
3713 01:18:41.004583 TX_TRACKING: ON
3714 01:18:41.014458 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3715 01:18:41.017379 [FAST_K] Save calibration result to emmc
3716 01:18:41.020452 dramc_set_vcore_voltage set vcore to 650000
3717 01:18:41.023939 Read voltage for 600, 5
3718 01:18:41.024488 Vio18 = 0
3719 01:18:41.027022 Vcore = 650000
3720 01:18:41.027473 Vdram = 0
3721 01:18:41.027826 Vddq = 0
3722 01:18:41.028157 Vmddr = 0
3723 01:18:41.033882 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3724 01:18:41.040387 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3725 01:18:41.040952 MEM_TYPE=3, freq_sel=19
3726 01:18:41.044149 sv_algorithm_assistance_LP4_1600
3727 01:18:41.046982 ============ PULL DRAM RESETB DOWN ============
3728 01:18:41.053921 ========== PULL DRAM RESETB DOWN end =========
3729 01:18:41.056710 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3730 01:18:41.060375 ===================================
3731 01:18:41.063996 LPDDR4 DRAM CONFIGURATION
3732 01:18:41.066867 ===================================
3733 01:18:41.067416 EX_ROW_EN[0] = 0x0
3734 01:18:41.070807 EX_ROW_EN[1] = 0x0
3735 01:18:41.071366 LP4Y_EN = 0x0
3736 01:18:41.074020 WORK_FSP = 0x0
3737 01:18:41.074600 WL = 0x2
3738 01:18:41.076628 RL = 0x2
3739 01:18:41.077073 BL = 0x2
3740 01:18:41.080559 RPST = 0x0
3741 01:18:41.083935 RD_PRE = 0x0
3742 01:18:41.084486 WR_PRE = 0x1
3743 01:18:41.086762 WR_PST = 0x0
3744 01:18:41.087216 DBI_WR = 0x0
3745 01:18:41.090268 DBI_RD = 0x0
3746 01:18:41.090761 OTF = 0x1
3747 01:18:41.093502 ===================================
3748 01:18:41.096814 ===================================
3749 01:18:41.100146 ANA top config
3750 01:18:41.103413 ===================================
3751 01:18:41.103864 DLL_ASYNC_EN = 0
3752 01:18:41.106637 ALL_SLAVE_EN = 1
3753 01:18:41.109749 NEW_RANK_MODE = 1
3754 01:18:41.113443 DLL_IDLE_MODE = 1
3755 01:18:41.113993 LP45_APHY_COMB_EN = 1
3756 01:18:41.117022 TX_ODT_DIS = 1
3757 01:18:41.119607 NEW_8X_MODE = 1
3758 01:18:41.123823 ===================================
3759 01:18:41.126814 ===================================
3760 01:18:41.130060 data_rate = 1200
3761 01:18:41.132786 CKR = 1
3762 01:18:41.136136 DQ_P2S_RATIO = 8
3763 01:18:41.139522 ===================================
3764 01:18:41.140077 CA_P2S_RATIO = 8
3765 01:18:41.142643 DQ_CA_OPEN = 0
3766 01:18:41.146439 DQ_SEMI_OPEN = 0
3767 01:18:41.149540 CA_SEMI_OPEN = 0
3768 01:18:41.153184 CA_FULL_RATE = 0
3769 01:18:41.156507 DQ_CKDIV4_EN = 1
3770 01:18:41.157064 CA_CKDIV4_EN = 1
3771 01:18:41.159294 CA_PREDIV_EN = 0
3772 01:18:41.162753 PH8_DLY = 0
3773 01:18:41.166132 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3774 01:18:41.169054 DQ_AAMCK_DIV = 4
3775 01:18:41.173011 CA_AAMCK_DIV = 4
3776 01:18:41.173648 CA_ADMCK_DIV = 4
3777 01:18:41.175654 DQ_TRACK_CA_EN = 0
3778 01:18:41.178985 CA_PICK = 600
3779 01:18:41.182637 CA_MCKIO = 600
3780 01:18:41.186337 MCKIO_SEMI = 0
3781 01:18:41.189202 PLL_FREQ = 2288
3782 01:18:41.192389 DQ_UI_PI_RATIO = 32
3783 01:18:41.192839 CA_UI_PI_RATIO = 0
3784 01:18:41.195630 ===================================
3785 01:18:41.199230 ===================================
3786 01:18:41.202953 memory_type:LPDDR4
3787 01:18:41.205867 GP_NUM : 10
3788 01:18:41.206457 SRAM_EN : 1
3789 01:18:41.208985 MD32_EN : 0
3790 01:18:41.212242 ===================================
3791 01:18:41.215582 [ANA_INIT] >>>>>>>>>>>>>>
3792 01:18:41.219028 <<<<<< [CONFIGURE PHASE]: ANA_TX
3793 01:18:41.222199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3794 01:18:41.225270 ===================================
3795 01:18:41.225721 data_rate = 1200,PCW = 0X5800
3796 01:18:41.229055 ===================================
3797 01:18:41.232114 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3798 01:18:41.238652 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 01:18:41.245558 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 01:18:41.249176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3801 01:18:41.252040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3802 01:18:41.255324 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3803 01:18:41.258433 [ANA_INIT] flow start
3804 01:18:41.262526 [ANA_INIT] PLL >>>>>>>>
3805 01:18:41.263071 [ANA_INIT] PLL <<<<<<<<
3806 01:18:41.265915 [ANA_INIT] MIDPI >>>>>>>>
3807 01:18:41.268965 [ANA_INIT] MIDPI <<<<<<<<
3808 01:18:41.269531 [ANA_INIT] DLL >>>>>>>>
3809 01:18:41.271943 [ANA_INIT] flow end
3810 01:18:41.275265 ============ LP4 DIFF to SE enter ============
3811 01:18:41.279001 ============ LP4 DIFF to SE exit ============
3812 01:18:41.281951 [ANA_INIT] <<<<<<<<<<<<<
3813 01:18:41.285602 [Flow] Enable top DCM control >>>>>
3814 01:18:41.288751 [Flow] Enable top DCM control <<<<<
3815 01:18:41.291555 Enable DLL master slave shuffle
3816 01:18:41.298962 ==============================================================
3817 01:18:41.299495 Gating Mode config
3818 01:18:41.305768 ==============================================================
3819 01:18:41.306373 Config description:
3820 01:18:41.314944 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3821 01:18:41.321569 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3822 01:18:41.328336 SELPH_MODE 0: By rank 1: By Phase
3823 01:18:41.331593 ==============================================================
3824 01:18:41.334775 GAT_TRACK_EN = 1
3825 01:18:41.338532 RX_GATING_MODE = 2
3826 01:18:41.341586 RX_GATING_TRACK_MODE = 2
3827 01:18:41.344911 SELPH_MODE = 1
3828 01:18:41.348518 PICG_EARLY_EN = 1
3829 01:18:41.351969 VALID_LAT_VALUE = 1
3830 01:18:41.358201 ==============================================================
3831 01:18:41.361366 Enter into Gating configuration >>>>
3832 01:18:41.364669 Exit from Gating configuration <<<<
3833 01:18:41.368935 Enter into DVFS_PRE_config >>>>>
3834 01:18:41.378549 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3835 01:18:41.381806 Exit from DVFS_PRE_config <<<<<
3836 01:18:41.385070 Enter into PICG configuration >>>>
3837 01:18:41.388027 Exit from PICG configuration <<<<
3838 01:18:41.391812 [RX_INPUT] configuration >>>>>
3839 01:18:41.392265 [RX_INPUT] configuration <<<<<
3840 01:18:41.397769 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3841 01:18:41.404612 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3842 01:18:41.408117 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 01:18:41.414585 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 01:18:41.421419 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 01:18:41.428017 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 01:18:41.431622 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3847 01:18:41.434834 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3848 01:18:41.441192 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3849 01:18:41.444673 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3850 01:18:41.448168 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3851 01:18:41.451263 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 01:18:41.454375 ===================================
3853 01:18:41.457946 LPDDR4 DRAM CONFIGURATION
3854 01:18:41.461333 ===================================
3855 01:18:41.464414 EX_ROW_EN[0] = 0x0
3856 01:18:41.464868 EX_ROW_EN[1] = 0x0
3857 01:18:41.467846 LP4Y_EN = 0x0
3858 01:18:41.468426 WORK_FSP = 0x0
3859 01:18:41.471323 WL = 0x2
3860 01:18:41.471776 RL = 0x2
3861 01:18:41.474918 BL = 0x2
3862 01:18:41.475468 RPST = 0x0
3863 01:18:41.477994 RD_PRE = 0x0
3864 01:18:41.481234 WR_PRE = 0x1
3865 01:18:41.481781 WR_PST = 0x0
3866 01:18:41.484545 DBI_WR = 0x0
3867 01:18:41.485095 DBI_RD = 0x0
3868 01:18:41.487629 OTF = 0x1
3869 01:18:41.491055 ===================================
3870 01:18:41.494274 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3871 01:18:41.498134 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3872 01:18:41.501062 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 01:18:41.504685 ===================================
3874 01:18:41.508013 LPDDR4 DRAM CONFIGURATION
3875 01:18:41.510979 ===================================
3876 01:18:41.514602 EX_ROW_EN[0] = 0x10
3877 01:18:41.515064 EX_ROW_EN[1] = 0x0
3878 01:18:41.517460 LP4Y_EN = 0x0
3879 01:18:41.517838 WORK_FSP = 0x0
3880 01:18:41.521029 WL = 0x2
3881 01:18:41.521486 RL = 0x2
3882 01:18:41.524972 BL = 0x2
3883 01:18:41.525524 RPST = 0x0
3884 01:18:41.527443 RD_PRE = 0x0
3885 01:18:41.527904 WR_PRE = 0x1
3886 01:18:41.530808 WR_PST = 0x0
3887 01:18:41.531270 DBI_WR = 0x0
3888 01:18:41.534533 DBI_RD = 0x0
3889 01:18:41.535011 OTF = 0x1
3890 01:18:41.537880 ===================================
3891 01:18:41.544560 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3892 01:18:41.549531 nWR fixed to 30
3893 01:18:41.552716 [ModeRegInit_LP4] CH0 RK0
3894 01:18:41.553170 [ModeRegInit_LP4] CH0 RK1
3895 01:18:41.555651 [ModeRegInit_LP4] CH1 RK0
3896 01:18:41.559317 [ModeRegInit_LP4] CH1 RK1
3897 01:18:41.559867 match AC timing 17
3898 01:18:41.566135 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3899 01:18:41.569053 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3900 01:18:41.572831 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3901 01:18:41.579479 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3902 01:18:41.582251 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3903 01:18:41.582767 ==
3904 01:18:41.586011 Dram Type= 6, Freq= 0, CH_0, rank 0
3905 01:18:41.589227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3906 01:18:41.589717 ==
3907 01:18:41.595639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3908 01:18:41.602261 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3909 01:18:41.605576 [CA 0] Center 36 (5~67) winsize 63
3910 01:18:41.608998 [CA 1] Center 36 (5~67) winsize 63
3911 01:18:41.612334 [CA 2] Center 33 (3~64) winsize 62
3912 01:18:41.615318 [CA 3] Center 33 (2~64) winsize 63
3913 01:18:41.618966 [CA 4] Center 33 (2~64) winsize 63
3914 01:18:41.622026 [CA 5] Center 32 (2~63) winsize 62
3915 01:18:41.622247
3916 01:18:41.625824 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3917 01:18:41.626048
3918 01:18:41.628939 [CATrainingPosCal] consider 1 rank data
3919 01:18:41.631976 u2DelayCellTimex100 = 270/100 ps
3920 01:18:41.635542 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3921 01:18:41.638661 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3922 01:18:41.642266 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3923 01:18:41.645656 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3924 01:18:41.648276 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3925 01:18:41.655448 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3926 01:18:41.655670
3927 01:18:41.658689 CA PerBit enable=1, Macro0, CA PI delay=32
3928 01:18:41.658910
3929 01:18:41.661779 [CBTSetCACLKResult] CA Dly = 32
3930 01:18:41.662001 CS Dly: 4 (0~35)
3931 01:18:41.662174 ==
3932 01:18:41.665179 Dram Type= 6, Freq= 0, CH_0, rank 1
3933 01:18:41.668566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 01:18:41.671477 ==
3935 01:18:41.674966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 01:18:41.682069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3937 01:18:41.685167 [CA 0] Center 35 (5~66) winsize 62
3938 01:18:41.688345 [CA 1] Center 35 (5~66) winsize 62
3939 01:18:41.691471 [CA 2] Center 34 (3~65) winsize 63
3940 01:18:41.694965 [CA 3] Center 33 (3~64) winsize 62
3941 01:18:41.697946 [CA 4] Center 33 (2~64) winsize 63
3942 01:18:41.701667 [CA 5] Center 32 (2~63) winsize 62
3943 01:18:41.701796
3944 01:18:41.704602 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3945 01:18:41.704716
3946 01:18:41.707862 [CATrainingPosCal] consider 2 rank data
3947 01:18:41.711113 u2DelayCellTimex100 = 270/100 ps
3948 01:18:41.714454 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3949 01:18:41.717783 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3950 01:18:41.721200 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3951 01:18:41.728263 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3952 01:18:41.731162 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3953 01:18:41.735009 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3954 01:18:41.735123
3955 01:18:41.738205 CA PerBit enable=1, Macro0, CA PI delay=32
3956 01:18:41.738329
3957 01:18:41.741170 [CBTSetCACLKResult] CA Dly = 32
3958 01:18:41.741282 CS Dly: 5 (0~37)
3959 01:18:41.741370
3960 01:18:41.744594 ----->DramcWriteLeveling(PI) begin...
3961 01:18:41.744713 ==
3962 01:18:41.747670 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 01:18:41.754665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 01:18:41.754780 ==
3965 01:18:41.757859 Write leveling (Byte 0): 36 => 36
3966 01:18:41.761289 Write leveling (Byte 1): 31 => 31
3967 01:18:41.761402 DramcWriteLeveling(PI) end<-----
3968 01:18:41.764599
3969 01:18:41.764717 ==
3970 01:18:41.767652 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 01:18:41.771050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 01:18:41.771163 ==
3973 01:18:41.774895 [Gating] SW mode calibration
3974 01:18:41.781346 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3975 01:18:41.784613 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3976 01:18:41.790941 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 01:18:41.794531 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 01:18:41.797798 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 01:18:41.804666 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
3980 01:18:41.807581 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (0 0) (0 0)
3981 01:18:41.811152 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 01:18:41.817281 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 01:18:41.821038 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 01:18:41.824581 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 01:18:41.831333 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 01:18:41.834211 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 01:18:41.837659 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
3988 01:18:41.844405 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
3989 01:18:41.848125 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3990 01:18:41.851345 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 01:18:41.857915 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 01:18:41.861573 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 01:18:41.864930 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 01:18:41.868209 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 01:18:41.875082 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 01:18:41.877951 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3997 01:18:41.881076 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 01:18:41.888088 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 01:18:41.890814 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 01:18:41.894282 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 01:18:41.901208 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 01:18:41.904255 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 01:18:41.907623 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 01:18:41.914499 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 01:18:41.917574 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 01:18:41.921113 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 01:18:41.927615 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 01:18:41.930975 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 01:18:41.934443 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 01:18:41.940939 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 01:18:41.944135 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4012 01:18:41.947625 Total UI for P1: 0, mck2ui 16
4013 01:18:41.950621 best dqsien dly found for B0: ( 0, 13, 10)
4014 01:18:41.954287 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4015 01:18:41.961232 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 01:18:41.961787 Total UI for P1: 0, mck2ui 16
4017 01:18:41.967589 best dqsien dly found for B1: ( 0, 13, 16)
4018 01:18:41.970772 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4019 01:18:41.974267 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4020 01:18:41.974885
4021 01:18:41.977317 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4022 01:18:41.980554 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4023 01:18:41.984117 [Gating] SW calibration Done
4024 01:18:41.984681 ==
4025 01:18:41.987148 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 01:18:41.990442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 01:18:41.991014 ==
4028 01:18:41.993871 RX Vref Scan: 0
4029 01:18:41.994494
4030 01:18:41.994980 RX Vref 0 -> 0, step: 1
4031 01:18:41.995464
4032 01:18:41.996889 RX Delay -230 -> 252, step: 16
4033 01:18:42.004233 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4034 01:18:42.007445 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4035 01:18:42.010483 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4036 01:18:42.013823 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4037 01:18:42.016748 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4038 01:18:42.024393 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4039 01:18:42.027263 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4040 01:18:42.030585 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4041 01:18:42.033753 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4042 01:18:42.040606 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4043 01:18:42.043277 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4044 01:18:42.047173 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4045 01:18:42.050295 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4046 01:18:42.056910 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4047 01:18:42.059938 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4048 01:18:42.063439 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4049 01:18:42.063950 ==
4050 01:18:42.067289 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 01:18:42.069989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 01:18:42.070588 ==
4053 01:18:42.073703 DQS Delay:
4054 01:18:42.074250 DQS0 = 0, DQS1 = 0
4055 01:18:42.076693 DQM Delay:
4056 01:18:42.077144 DQM0 = 53, DQM1 = 47
4057 01:18:42.077502 DQ Delay:
4058 01:18:42.080024 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4059 01:18:42.083242 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4060 01:18:42.086952 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =49
4061 01:18:42.089930 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4062 01:18:42.090419
4063 01:18:42.090788
4064 01:18:42.093054 ==
4065 01:18:42.097157 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 01:18:42.100749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 01:18:42.101324 ==
4068 01:18:42.101677
4069 01:18:42.102002
4070 01:18:42.103515 TX Vref Scan disable
4071 01:18:42.103966 == TX Byte 0 ==
4072 01:18:42.109822 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4073 01:18:42.112975 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4074 01:18:42.113640 == TX Byte 1 ==
4075 01:18:42.120232 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4076 01:18:42.123630 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4077 01:18:42.124087 ==
4078 01:18:42.126650 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 01:18:42.130731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 01:18:42.131288 ==
4081 01:18:42.131653
4082 01:18:42.131982
4083 01:18:42.133512 TX Vref Scan disable
4084 01:18:42.136557 == TX Byte 0 ==
4085 01:18:42.140337 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4086 01:18:42.143175 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4087 01:18:42.146350 == TX Byte 1 ==
4088 01:18:42.150092 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4089 01:18:42.152973 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4090 01:18:42.153388
4091 01:18:42.156240 [DATLAT]
4092 01:18:42.156753 Freq=600, CH0 RK0
4093 01:18:42.157094
4094 01:18:42.159635 DATLAT Default: 0x9
4095 01:18:42.160044 0, 0xFFFF, sum = 0
4096 01:18:42.162975 1, 0xFFFF, sum = 0
4097 01:18:42.163506 2, 0xFFFF, sum = 0
4098 01:18:42.166292 3, 0xFFFF, sum = 0
4099 01:18:42.166751 4, 0xFFFF, sum = 0
4100 01:18:42.169862 5, 0xFFFF, sum = 0
4101 01:18:42.170424 6, 0xFFFF, sum = 0
4102 01:18:42.172890 7, 0xFFFF, sum = 0
4103 01:18:42.173301 8, 0x0, sum = 1
4104 01:18:42.175931 9, 0x0, sum = 2
4105 01:18:42.176346 10, 0x0, sum = 3
4106 01:18:42.179424 11, 0x0, sum = 4
4107 01:18:42.179838 best_step = 9
4108 01:18:42.180157
4109 01:18:42.180516 ==
4110 01:18:42.182809 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 01:18:42.189246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 01:18:42.189774 ==
4113 01:18:42.190111 RX Vref Scan: 1
4114 01:18:42.190446
4115 01:18:42.192632 RX Vref 0 -> 0, step: 1
4116 01:18:42.193042
4117 01:18:42.196523 RX Delay -163 -> 252, step: 8
4118 01:18:42.196932
4119 01:18:42.199137 Set Vref, RX VrefLevel [Byte0]: 54
4120 01:18:42.202692 [Byte1]: 46
4121 01:18:42.203202
4122 01:18:42.206006 Final RX Vref Byte 0 = 54 to rank0
4123 01:18:42.210074 Final RX Vref Byte 1 = 46 to rank0
4124 01:18:42.213057 Final RX Vref Byte 0 = 54 to rank1
4125 01:18:42.216371 Final RX Vref Byte 1 = 46 to rank1==
4126 01:18:42.219462 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 01:18:42.222551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 01:18:42.222970 ==
4129 01:18:42.225620 DQS Delay:
4130 01:18:42.226029 DQS0 = 0, DQS1 = 0
4131 01:18:42.226373 DQM Delay:
4132 01:18:42.229737 DQM0 = 53, DQM1 = 46
4133 01:18:42.230253 DQ Delay:
4134 01:18:42.232410 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4135 01:18:42.235791 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4136 01:18:42.239122 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4137 01:18:42.242651 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4138 01:18:42.243201
4139 01:18:42.243659
4140 01:18:42.252615 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4141 01:18:42.255967 CH0 RK0: MR19=808, MR18=6E61
4142 01:18:42.259148 CH0_RK0: MR19=0x808, MR18=0x6E61, DQSOSC=389, MR23=63, INC=173, DEC=115
4143 01:18:42.259609
4144 01:18:42.265908 ----->DramcWriteLeveling(PI) begin...
4145 01:18:42.266508 ==
4146 01:18:42.269193 Dram Type= 6, Freq= 0, CH_0, rank 1
4147 01:18:42.272211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 01:18:42.272765 ==
4149 01:18:42.275481 Write leveling (Byte 0): 34 => 34
4150 01:18:42.278980 Write leveling (Byte 1): 34 => 34
4151 01:18:42.281892 DramcWriteLeveling(PI) end<-----
4152 01:18:42.282376
4153 01:18:42.282740 ==
4154 01:18:42.285525 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 01:18:42.288596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 01:18:42.289109 ==
4157 01:18:42.292134 [Gating] SW mode calibration
4158 01:18:42.298923 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4159 01:18:42.305010 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4160 01:18:42.308712 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 01:18:42.311567 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 01:18:42.318177 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 01:18:42.321794 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
4164 01:18:42.325160 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
4165 01:18:42.331738 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 01:18:42.334622 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 01:18:42.338200 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 01:18:42.345197 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 01:18:42.348303 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 01:18:42.355918 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 01:18:42.358177 0 10 12 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
4172 01:18:42.361471 0 10 16 | B1->B0 | 4040 3f3f | 0 0 | (0 0) (0 0)
4173 01:18:42.364601 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 01:18:42.371076 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 01:18:42.374943 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 01:18:42.378050 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 01:18:42.381379 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 01:18:42.387991 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 01:18:42.391179 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 01:18:42.394434 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 01:18:42.401657 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 01:18:42.404928 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 01:18:42.407676 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 01:18:42.414372 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 01:18:42.417667 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 01:18:42.421042 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 01:18:42.427625 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 01:18:42.431108 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 01:18:42.434036 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 01:18:42.441318 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 01:18:42.444402 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 01:18:42.447675 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 01:18:42.454047 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 01:18:42.457719 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 01:18:42.461303 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4196 01:18:42.468230 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 01:18:42.468798 Total UI for P1: 0, mck2ui 16
4198 01:18:42.474844 best dqsien dly found for B0: ( 0, 13, 12)
4199 01:18:42.475401 Total UI for P1: 0, mck2ui 16
4200 01:18:42.480623 best dqsien dly found for B1: ( 0, 13, 14)
4201 01:18:42.484290 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4202 01:18:42.488226 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4203 01:18:42.488781
4204 01:18:42.491303 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4205 01:18:42.494284 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4206 01:18:42.497882 [Gating] SW calibration Done
4207 01:18:42.498489 ==
4208 01:18:42.501083 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 01:18:42.504490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 01:18:42.505045 ==
4211 01:18:42.507603 RX Vref Scan: 0
4212 01:18:42.508070
4213 01:18:42.508422 RX Vref 0 -> 0, step: 1
4214 01:18:42.508748
4215 01:18:42.510602 RX Delay -230 -> 252, step: 16
4216 01:18:42.517621 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4217 01:18:42.520935 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4218 01:18:42.524154 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4219 01:18:42.527552 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4220 01:18:42.530620 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4221 01:18:42.537218 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4222 01:18:42.540359 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4223 01:18:42.543885 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4224 01:18:42.547153 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4225 01:18:42.550525 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4226 01:18:42.557535 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4227 01:18:42.560869 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4228 01:18:42.564137 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4229 01:18:42.567165 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4230 01:18:42.573742 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4231 01:18:42.577332 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4232 01:18:42.577889 ==
4233 01:18:42.580324 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 01:18:42.584073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 01:18:42.584628 ==
4236 01:18:42.587558 DQS Delay:
4237 01:18:42.588132 DQS0 = 0, DQS1 = 0
4238 01:18:42.588498 DQM Delay:
4239 01:18:42.590376 DQM0 = 54, DQM1 = 43
4240 01:18:42.590831 DQ Delay:
4241 01:18:42.593790 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4242 01:18:42.597731 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4243 01:18:42.600807 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4244 01:18:42.603792 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4245 01:18:42.604250
4246 01:18:42.604604
4247 01:18:42.604933 ==
4248 01:18:42.607189 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 01:18:42.613658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 01:18:42.614228 ==
4251 01:18:42.614653
4252 01:18:42.614999
4253 01:18:42.615343 TX Vref Scan disable
4254 01:18:42.617553 == TX Byte 0 ==
4255 01:18:42.620630 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4256 01:18:42.627596 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4257 01:18:42.628191 == TX Byte 1 ==
4258 01:18:42.630641 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4259 01:18:42.637546 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4260 01:18:42.638096 ==
4261 01:18:42.640418 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 01:18:42.643606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 01:18:42.644073 ==
4264 01:18:42.644433
4265 01:18:42.644771
4266 01:18:42.647120 TX Vref Scan disable
4267 01:18:42.650412 == TX Byte 0 ==
4268 01:18:42.653569 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4269 01:18:42.657377 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4270 01:18:42.660106 == TX Byte 1 ==
4271 01:18:42.663890 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4272 01:18:42.667194 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4273 01:18:42.667746
4274 01:18:42.668114 [DATLAT]
4275 01:18:42.670188 Freq=600, CH0 RK1
4276 01:18:42.670687
4277 01:18:42.673595 DATLAT Default: 0x9
4278 01:18:42.674150 0, 0xFFFF, sum = 0
4279 01:18:42.676702 1, 0xFFFF, sum = 0
4280 01:18:42.677196 2, 0xFFFF, sum = 0
4281 01:18:42.680628 3, 0xFFFF, sum = 0
4282 01:18:42.681187 4, 0xFFFF, sum = 0
4283 01:18:42.683887 5, 0xFFFF, sum = 0
4284 01:18:42.684445 6, 0xFFFF, sum = 0
4285 01:18:42.687267 7, 0xFFFF, sum = 0
4286 01:18:42.687732 8, 0x0, sum = 1
4287 01:18:42.690523 9, 0x0, sum = 2
4288 01:18:42.690990 10, 0x0, sum = 3
4289 01:18:42.691355 11, 0x0, sum = 4
4290 01:18:42.693601 best_step = 9
4291 01:18:42.694148
4292 01:18:42.694614 ==
4293 01:18:42.696777 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 01:18:42.700345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 01:18:42.700806 ==
4296 01:18:42.703645 RX Vref Scan: 0
4297 01:18:42.704057
4298 01:18:42.704379 RX Vref 0 -> 0, step: 1
4299 01:18:42.706657
4300 01:18:42.707069 RX Delay -163 -> 252, step: 8
4301 01:18:42.714097 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4302 01:18:42.717718 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4303 01:18:42.721085 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4304 01:18:42.724164 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4305 01:18:42.727397 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4306 01:18:42.734087 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4307 01:18:42.738115 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4308 01:18:42.741166 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4309 01:18:42.744444 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4310 01:18:42.747850 iDelay=197, Bit 9, Center 32 (-107 ~ 172) 280
4311 01:18:42.753982 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4312 01:18:42.757301 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4313 01:18:42.760559 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4314 01:18:42.764147 iDelay=197, Bit 13, Center 48 (-91 ~ 188) 280
4315 01:18:42.770849 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4316 01:18:42.774423 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4317 01:18:42.775019 ==
4318 01:18:42.777804 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 01:18:42.781129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 01:18:42.781691 ==
4321 01:18:42.784151 DQS Delay:
4322 01:18:42.784705 DQS0 = 0, DQS1 = 0
4323 01:18:42.785063 DQM Delay:
4324 01:18:42.787670 DQM0 = 54, DQM1 = 45
4325 01:18:42.788229 DQ Delay:
4326 01:18:42.790855 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4327 01:18:42.794285 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4328 01:18:42.797605 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40
4329 01:18:42.800644 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4330 01:18:42.801101
4331 01:18:42.801451
4332 01:18:42.810770 [DQSOSCAuto] RK1, (LSB)MR18= 0x6021, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4333 01:18:42.811330 CH0 RK1: MR19=808, MR18=6021
4334 01:18:42.817443 CH0_RK1: MR19=0x808, MR18=0x6021, DQSOSC=391, MR23=63, INC=171, DEC=114
4335 01:18:42.820772 [RxdqsGatingPostProcess] freq 600
4336 01:18:42.826961 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4337 01:18:42.830579 Pre-setting of DQS Precalculation
4338 01:18:42.833757 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4339 01:18:42.834391 ==
4340 01:18:42.837186 Dram Type= 6, Freq= 0, CH_1, rank 0
4341 01:18:42.840384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 01:18:42.843638 ==
4343 01:18:42.846877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4344 01:18:42.853635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4345 01:18:42.856957 [CA 0] Center 36 (5~67) winsize 63
4346 01:18:42.860833 [CA 1] Center 36 (5~67) winsize 63
4347 01:18:42.864068 [CA 2] Center 35 (4~66) winsize 63
4348 01:18:42.867477 [CA 3] Center 34 (4~65) winsize 62
4349 01:18:42.870525 [CA 4] Center 34 (4~65) winsize 62
4350 01:18:42.873706 [CA 5] Center 34 (3~65) winsize 63
4351 01:18:42.874161
4352 01:18:42.877267 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4353 01:18:42.877722
4354 01:18:42.880310 [CATrainingPosCal] consider 1 rank data
4355 01:18:42.884203 u2DelayCellTimex100 = 270/100 ps
4356 01:18:42.887404 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4357 01:18:42.890439 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4358 01:18:42.897242 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4359 01:18:42.900445 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4360 01:18:42.903949 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4361 01:18:42.906952 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4362 01:18:42.907406
4363 01:18:42.910265 CA PerBit enable=1, Macro0, CA PI delay=34
4364 01:18:42.910752
4365 01:18:42.913760 [CBTSetCACLKResult] CA Dly = 34
4366 01:18:42.914351 CS Dly: 6 (0~37)
4367 01:18:42.914818 ==
4368 01:18:42.916711 Dram Type= 6, Freq= 0, CH_1, rank 1
4369 01:18:42.923198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 01:18:42.923652 ==
4371 01:18:42.926437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 01:18:42.933154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4373 01:18:42.937159 [CA 0] Center 36 (5~67) winsize 63
4374 01:18:42.939939 [CA 1] Center 36 (5~67) winsize 63
4375 01:18:42.943691 [CA 2] Center 35 (4~66) winsize 63
4376 01:18:42.946994 [CA 3] Center 34 (4~65) winsize 62
4377 01:18:42.949937 [CA 4] Center 35 (4~66) winsize 63
4378 01:18:42.953628 [CA 5] Center 34 (3~65) winsize 63
4379 01:18:42.954175
4380 01:18:42.956685 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4381 01:18:42.957142
4382 01:18:42.959818 [CATrainingPosCal] consider 2 rank data
4383 01:18:42.963639 u2DelayCellTimex100 = 270/100 ps
4384 01:18:42.967019 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4385 01:18:42.969943 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4386 01:18:42.976915 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4387 01:18:42.979949 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4388 01:18:42.983648 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 01:18:42.986794 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4390 01:18:42.987254
4391 01:18:42.990058 CA PerBit enable=1, Macro0, CA PI delay=34
4392 01:18:42.990657
4393 01:18:42.993843 [CBTSetCACLKResult] CA Dly = 34
4394 01:18:42.994461 CS Dly: 6 (0~38)
4395 01:18:42.994840
4396 01:18:42.996619 ----->DramcWriteLeveling(PI) begin...
4397 01:18:43.000291 ==
4398 01:18:43.003232 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 01:18:43.006762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 01:18:43.007316 ==
4401 01:18:43.009956 Write leveling (Byte 0): 30 => 30
4402 01:18:43.013390 Write leveling (Byte 1): 30 => 30
4403 01:18:43.016692 DramcWriteLeveling(PI) end<-----
4404 01:18:43.017250
4405 01:18:43.017615 ==
4406 01:18:43.019818 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 01:18:43.023046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 01:18:43.023632 ==
4409 01:18:43.026535 [Gating] SW mode calibration
4410 01:18:43.033508 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4411 01:18:43.040282 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4412 01:18:43.043333 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 01:18:43.046403 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 01:18:43.049619 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 01:18:43.056709 0 9 12 | B1->B0 | 3232 2f2f | 1 0 | (0 1) (0 1)
4416 01:18:43.059757 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4417 01:18:43.063146 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 01:18:43.069824 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 01:18:43.072973 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 01:18:43.076250 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 01:18:43.082890 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 01:18:43.086578 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 01:18:43.089444 0 10 12 | B1->B0 | 3131 3535 | 0 0 | (0 0) (0 0)
4424 01:18:43.096184 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 01:18:43.099570 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 01:18:43.103086 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 01:18:43.109598 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 01:18:43.112739 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 01:18:43.116467 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 01:18:43.122860 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 01:18:43.126104 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4432 01:18:43.129403 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 01:18:43.135875 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 01:18:43.139183 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 01:18:43.143118 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 01:18:43.149384 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 01:18:43.152990 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 01:18:43.156294 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 01:18:43.162823 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 01:18:43.166094 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 01:18:43.169172 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 01:18:43.176204 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 01:18:43.179454 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 01:18:43.182728 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 01:18:43.189667 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 01:18:43.192830 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4447 01:18:43.196126 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4448 01:18:43.202371 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 01:18:43.202900 Total UI for P1: 0, mck2ui 16
4450 01:18:43.205435 best dqsien dly found for B0: ( 0, 13, 10)
4451 01:18:43.208880 Total UI for P1: 0, mck2ui 16
4452 01:18:43.212184 best dqsien dly found for B1: ( 0, 13, 14)
4453 01:18:43.215944 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4454 01:18:43.222704 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4455 01:18:43.223267
4456 01:18:43.225572 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4457 01:18:43.228890 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4458 01:18:43.232622 [Gating] SW calibration Done
4459 01:18:43.233139 ==
4460 01:18:43.235628 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 01:18:43.239105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 01:18:43.239565 ==
4463 01:18:43.239922 RX Vref Scan: 0
4464 01:18:43.242286
4465 01:18:43.242949 RX Vref 0 -> 0, step: 1
4466 01:18:43.243343
4467 01:18:43.245867 RX Delay -230 -> 252, step: 16
4468 01:18:43.249290 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4469 01:18:43.255709 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4470 01:18:43.259434 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4471 01:18:43.262443 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4472 01:18:43.265910 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4473 01:18:43.269495 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4474 01:18:43.275942 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4475 01:18:43.279185 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4476 01:18:43.282638 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4477 01:18:43.285931 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4478 01:18:43.289218 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4479 01:18:43.295983 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4480 01:18:43.299200 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4481 01:18:43.302242 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4482 01:18:43.305910 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4483 01:18:43.312106 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4484 01:18:43.312669 ==
4485 01:18:43.315329 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 01:18:43.319038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 01:18:43.319507 ==
4488 01:18:43.319863 DQS Delay:
4489 01:18:43.322284 DQS0 = 0, DQS1 = 0
4490 01:18:43.322769 DQM Delay:
4491 01:18:43.325644 DQM0 = 53, DQM1 = 51
4492 01:18:43.326130 DQ Delay:
4493 01:18:43.328952 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =49
4494 01:18:43.332549 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4495 01:18:43.335164 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =41
4496 01:18:43.339198 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4497 01:18:43.339749
4498 01:18:43.340107
4499 01:18:43.340440 ==
4500 01:18:43.341946 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 01:18:43.345695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 01:18:43.346251 ==
4503 01:18:43.346665
4504 01:18:43.347017
4505 01:18:43.348803 TX Vref Scan disable
4506 01:18:43.352414 == TX Byte 0 ==
4507 01:18:43.355427 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4508 01:18:43.358836 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4509 01:18:43.362290 == TX Byte 1 ==
4510 01:18:43.365627 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4511 01:18:43.368808 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4512 01:18:43.369477 ==
4513 01:18:43.372150 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 01:18:43.378765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 01:18:43.379423 ==
4516 01:18:43.379789
4517 01:18:43.380119
4518 01:18:43.380433 TX Vref Scan disable
4519 01:18:43.383023 == TX Byte 0 ==
4520 01:18:43.386209 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4521 01:18:43.393560 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4522 01:18:43.394112 == TX Byte 1 ==
4523 01:18:43.395922 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4524 01:18:43.402968 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4525 01:18:43.403521
4526 01:18:43.403877 [DATLAT]
4527 01:18:43.404208 Freq=600, CH1 RK0
4528 01:18:43.404557
4529 01:18:43.406206 DATLAT Default: 0x9
4530 01:18:43.406827 0, 0xFFFF, sum = 0
4531 01:18:43.409829 1, 0xFFFF, sum = 0
4532 01:18:43.410286 2, 0xFFFF, sum = 0
4533 01:18:43.413173 3, 0xFFFF, sum = 0
4534 01:18:43.416238 4, 0xFFFF, sum = 0
4535 01:18:43.416936 5, 0xFFFF, sum = 0
4536 01:18:43.418900 6, 0xFFFF, sum = 0
4537 01:18:43.419484 7, 0xFFFF, sum = 0
4538 01:18:43.422928 8, 0x0, sum = 1
4539 01:18:43.423389 9, 0x0, sum = 2
4540 01:18:43.423750 10, 0x0, sum = 3
4541 01:18:43.426472 11, 0x0, sum = 4
4542 01:18:43.427024 best_step = 9
4543 01:18:43.427382
4544 01:18:43.427711 ==
4545 01:18:43.429081 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 01:18:43.436208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 01:18:43.436758 ==
4548 01:18:43.437112 RX Vref Scan: 1
4549 01:18:43.437484
4550 01:18:43.439299 RX Vref 0 -> 0, step: 1
4551 01:18:43.440003
4552 01:18:43.442382 RX Delay -163 -> 252, step: 8
4553 01:18:43.442836
4554 01:18:43.445961 Set Vref, RX VrefLevel [Byte0]: 53
4555 01:18:43.449239 [Byte1]: 53
4556 01:18:43.449792
4557 01:18:43.452506 Final RX Vref Byte 0 = 53 to rank0
4558 01:18:43.455655 Final RX Vref Byte 1 = 53 to rank0
4559 01:18:43.459091 Final RX Vref Byte 0 = 53 to rank1
4560 01:18:43.462330 Final RX Vref Byte 1 = 53 to rank1==
4561 01:18:43.465755 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 01:18:43.469423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 01:18:43.470008 ==
4564 01:18:43.472491 DQS Delay:
4565 01:18:43.473044 DQS0 = 0, DQS1 = 0
4566 01:18:43.475758 DQM Delay:
4567 01:18:43.476281 DQM0 = 48, DQM1 = 45
4568 01:18:43.476645 DQ Delay:
4569 01:18:43.479069 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4570 01:18:43.482384 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4571 01:18:43.486078 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4572 01:18:43.488988 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4573 01:18:43.489599
4574 01:18:43.490007
4575 01:18:43.499105 [DQSOSCAuto] RK0, (LSB)MR18= 0x466c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4576 01:18:43.502505 CH1 RK0: MR19=808, MR18=466C
4577 01:18:43.506024 CH1_RK0: MR19=0x808, MR18=0x466C, DQSOSC=389, MR23=63, INC=173, DEC=115
4578 01:18:43.506516
4579 01:18:43.509131 ----->DramcWriteLeveling(PI) begin...
4580 01:18:43.512669 ==
4581 01:18:43.516033 Dram Type= 6, Freq= 0, CH_1, rank 1
4582 01:18:43.519039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 01:18:43.519502 ==
4584 01:18:43.522847 Write leveling (Byte 0): 28 => 28
4585 01:18:43.525801 Write leveling (Byte 1): 32 => 32
4586 01:18:43.529113 DramcWriteLeveling(PI) end<-----
4587 01:18:43.529567
4588 01:18:43.529918 ==
4589 01:18:43.533229 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 01:18:43.535600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 01:18:43.536059 ==
4592 01:18:43.539155 [Gating] SW mode calibration
4593 01:18:43.546056 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4594 01:18:43.552789 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4595 01:18:43.555844 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 01:18:43.559179 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 01:18:43.562686 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 01:18:43.569323 0 9 12 | B1->B0 | 2f2f 3131 | 0 0 | (1 1) (0 1)
4599 01:18:43.572019 0 9 16 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 0)
4600 01:18:43.579058 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 01:18:43.582408 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 01:18:43.585300 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 01:18:43.592320 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 01:18:43.595252 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 01:18:43.598538 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 01:18:43.602479 0 10 12 | B1->B0 | 3b3b 3636 | 1 0 | (0 0) (0 0)
4607 01:18:43.608777 0 10 16 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
4608 01:18:43.612115 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 01:18:43.614914 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 01:18:43.621690 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 01:18:43.624799 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 01:18:43.628706 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 01:18:43.635371 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 01:18:43.638186 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4615 01:18:43.641842 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 01:18:43.648610 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 01:18:43.651982 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 01:18:43.655147 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 01:18:43.661981 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 01:18:43.665149 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 01:18:43.668166 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 01:18:43.675041 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 01:18:43.678491 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 01:18:43.681659 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 01:18:43.688232 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 01:18:43.691589 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 01:18:43.695074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 01:18:43.701810 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 01:18:43.704423 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4630 01:18:43.708014 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4631 01:18:43.711106 Total UI for P1: 0, mck2ui 16
4632 01:18:43.714379 best dqsien dly found for B0: ( 0, 13, 10)
4633 01:18:43.721387 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 01:18:43.722167 Total UI for P1: 0, mck2ui 16
4635 01:18:43.728010 best dqsien dly found for B1: ( 0, 13, 10)
4636 01:18:43.730980 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4637 01:18:43.734350 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4638 01:18:43.734922
4639 01:18:43.737590 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4640 01:18:43.741233 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4641 01:18:43.744067 [Gating] SW calibration Done
4642 01:18:43.744528 ==
4643 01:18:43.747712 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 01:18:43.750583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 01:18:43.751047 ==
4646 01:18:43.754244 RX Vref Scan: 0
4647 01:18:43.754747
4648 01:18:43.755151 RX Vref 0 -> 0, step: 1
4649 01:18:43.755536
4650 01:18:43.757500 RX Delay -230 -> 252, step: 16
4651 01:18:43.764365 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4652 01:18:43.767567 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4653 01:18:43.770871 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4654 01:18:43.774440 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4655 01:18:43.777666 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4656 01:18:43.784191 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4657 01:18:43.787634 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4658 01:18:43.790829 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4659 01:18:43.794385 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4660 01:18:43.800846 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4661 01:18:43.804462 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4662 01:18:43.807463 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4663 01:18:43.810450 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4664 01:18:43.817110 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4665 01:18:43.820394 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4666 01:18:43.824233 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4667 01:18:43.824694 ==
4668 01:18:43.827013 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 01:18:43.831223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 01:18:43.831798 ==
4671 01:18:43.834413 DQS Delay:
4672 01:18:43.834988 DQS0 = 0, DQS1 = 0
4673 01:18:43.837235 DQM Delay:
4674 01:18:43.837693 DQM0 = 47, DQM1 = 47
4675 01:18:43.838057 DQ Delay:
4676 01:18:43.840481 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4677 01:18:43.844166 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4678 01:18:43.847523 DQ8 =33, DQ9 =41, DQ10 =41, DQ11 =41
4679 01:18:43.850819 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4680 01:18:43.851381
4681 01:18:43.851741
4682 01:18:43.853813 ==
4683 01:18:43.854284 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 01:18:43.860415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 01:18:43.860986 ==
4686 01:18:43.861355
4687 01:18:43.861692
4688 01:18:43.863964 TX Vref Scan disable
4689 01:18:43.864541 == TX Byte 0 ==
4690 01:18:43.870694 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4691 01:18:43.873689 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4692 01:18:43.874353 == TX Byte 1 ==
4693 01:18:43.877784 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4694 01:18:43.883837 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4695 01:18:43.884616 ==
4696 01:18:43.887250 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 01:18:43.890681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 01:18:43.891256 ==
4699 01:18:43.891624
4700 01:18:43.891959
4701 01:18:43.893835 TX Vref Scan disable
4702 01:18:43.897243 == TX Byte 0 ==
4703 01:18:43.900320 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4704 01:18:43.903567 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4705 01:18:43.906997 == TX Byte 1 ==
4706 01:18:43.910097 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4707 01:18:43.914085 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4708 01:18:43.914703
4709 01:18:43.917053 [DATLAT]
4710 01:18:43.917615 Freq=600, CH1 RK1
4711 01:18:43.917984
4712 01:18:43.920809 DATLAT Default: 0x9
4713 01:18:43.921384 0, 0xFFFF, sum = 0
4714 01:18:43.923645 1, 0xFFFF, sum = 0
4715 01:18:43.924113 2, 0xFFFF, sum = 0
4716 01:18:43.927468 3, 0xFFFF, sum = 0
4717 01:18:43.927932 4, 0xFFFF, sum = 0
4718 01:18:43.930367 5, 0xFFFF, sum = 0
4719 01:18:43.930832 6, 0xFFFF, sum = 0
4720 01:18:43.934017 7, 0xFFFF, sum = 0
4721 01:18:43.934599 8, 0x0, sum = 1
4722 01:18:43.937389 9, 0x0, sum = 2
4723 01:18:43.937955 10, 0x0, sum = 3
4724 01:18:43.940278 11, 0x0, sum = 4
4725 01:18:43.940747 best_step = 9
4726 01:18:43.941107
4727 01:18:43.941505 ==
4728 01:18:43.943556 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 01:18:43.947535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 01:18:43.948116 ==
4731 01:18:43.950551 RX Vref Scan: 0
4732 01:18:43.951009
4733 01:18:43.954121 RX Vref 0 -> 0, step: 1
4734 01:18:43.954719
4735 01:18:43.956496 RX Delay -163 -> 252, step: 8
4736 01:18:43.960371 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4737 01:18:43.963818 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4738 01:18:43.970600 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4739 01:18:43.973703 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4740 01:18:43.977085 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4741 01:18:43.980191 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4742 01:18:43.983366 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4743 01:18:43.990191 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4744 01:18:43.993537 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4745 01:18:43.997262 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4746 01:18:43.999774 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4747 01:18:44.003601 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4748 01:18:44.010115 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4749 01:18:44.013670 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4750 01:18:44.016642 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4751 01:18:44.019920 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4752 01:18:44.020382 ==
4753 01:18:44.022971 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 01:18:44.029559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 01:18:44.030129 ==
4756 01:18:44.030558 DQS Delay:
4757 01:18:44.033001 DQS0 = 0, DQS1 = 0
4758 01:18:44.033458 DQM Delay:
4759 01:18:44.036367 DQM0 = 49, DQM1 = 46
4760 01:18:44.036947 DQ Delay:
4761 01:18:44.039182 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4762 01:18:44.042971 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4763 01:18:44.045924 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4764 01:18:44.049891 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4765 01:18:44.050500
4766 01:18:44.050869
4767 01:18:44.055977 [DQSOSCAuto] RK1, (LSB)MR18= 0x6921, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
4768 01:18:44.059104 CH1 RK1: MR19=808, MR18=6921
4769 01:18:44.066262 CH1_RK1: MR19=0x808, MR18=0x6921, DQSOSC=390, MR23=63, INC=172, DEC=114
4770 01:18:44.069739 [RxdqsGatingPostProcess] freq 600
4771 01:18:44.075971 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4772 01:18:44.076536 Pre-setting of DQS Precalculation
4773 01:18:44.082372 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4774 01:18:44.089861 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4775 01:18:44.096336 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4776 01:18:44.096896
4777 01:18:44.097259
4778 01:18:44.099316 [Calibration Summary] 1200 Mbps
4779 01:18:44.102525 CH 0, Rank 0
4780 01:18:44.103086 SW Impedance : PASS
4781 01:18:44.105908 DUTY Scan : NO K
4782 01:18:44.106511 ZQ Calibration : PASS
4783 01:18:44.109641 Jitter Meter : NO K
4784 01:18:44.112771 CBT Training : PASS
4785 01:18:44.113332 Write leveling : PASS
4786 01:18:44.115718 RX DQS gating : PASS
4787 01:18:44.118959 RX DQ/DQS(RDDQC) : PASS
4788 01:18:44.119515 TX DQ/DQS : PASS
4789 01:18:44.122677 RX DATLAT : PASS
4790 01:18:44.125492 RX DQ/DQS(Engine): PASS
4791 01:18:44.125950 TX OE : NO K
4792 01:18:44.129292 All Pass.
4793 01:18:44.129843
4794 01:18:44.130204 CH 0, Rank 1
4795 01:18:44.132405 SW Impedance : PASS
4796 01:18:44.132861 DUTY Scan : NO K
4797 01:18:44.135818 ZQ Calibration : PASS
4798 01:18:44.138834 Jitter Meter : NO K
4799 01:18:44.139297 CBT Training : PASS
4800 01:18:44.142552 Write leveling : PASS
4801 01:18:44.145729 RX DQS gating : PASS
4802 01:18:44.146189 RX DQ/DQS(RDDQC) : PASS
4803 01:18:44.148942 TX DQ/DQS : PASS
4804 01:18:44.152366 RX DATLAT : PASS
4805 01:18:44.152828 RX DQ/DQS(Engine): PASS
4806 01:18:44.155235 TX OE : NO K
4807 01:18:44.155692 All Pass.
4808 01:18:44.156092
4809 01:18:44.158654 CH 1, Rank 0
4810 01:18:44.159111 SW Impedance : PASS
4811 01:18:44.162910 DUTY Scan : NO K
4812 01:18:44.163475 ZQ Calibration : PASS
4813 01:18:44.165479 Jitter Meter : NO K
4814 01:18:44.169102 CBT Training : PASS
4815 01:18:44.169565 Write leveling : PASS
4816 01:18:44.172723 RX DQS gating : PASS
4817 01:18:44.175900 RX DQ/DQS(RDDQC) : PASS
4818 01:18:44.176457 TX DQ/DQS : PASS
4819 01:18:44.179160 RX DATLAT : PASS
4820 01:18:44.182294 RX DQ/DQS(Engine): PASS
4821 01:18:44.182906 TX OE : NO K
4822 01:18:44.185610 All Pass.
4823 01:18:44.186066
4824 01:18:44.186497 CH 1, Rank 1
4825 01:18:44.188682 SW Impedance : PASS
4826 01:18:44.189403 DUTY Scan : NO K
4827 01:18:44.192327 ZQ Calibration : PASS
4828 01:18:44.195374 Jitter Meter : NO K
4829 01:18:44.195832 CBT Training : PASS
4830 01:18:44.199014 Write leveling : PASS
4831 01:18:44.202275 RX DQS gating : PASS
4832 01:18:44.202877 RX DQ/DQS(RDDQC) : PASS
4833 01:18:44.205523 TX DQ/DQS : PASS
4834 01:18:44.206084 RX DATLAT : PASS
4835 01:18:44.208729 RX DQ/DQS(Engine): PASS
4836 01:18:44.212415 TX OE : NO K
4837 01:18:44.212872 All Pass.
4838 01:18:44.213231
4839 01:18:44.215644 DramC Write-DBI off
4840 01:18:44.216159 PER_BANK_REFRESH: Hybrid Mode
4841 01:18:44.218807 TX_TRACKING: ON
4842 01:18:44.228836 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4843 01:18:44.232245 [FAST_K] Save calibration result to emmc
4844 01:18:44.235616 dramc_set_vcore_voltage set vcore to 662500
4845 01:18:44.236178 Read voltage for 933, 3
4846 01:18:44.238668 Vio18 = 0
4847 01:18:44.239129 Vcore = 662500
4848 01:18:44.239494 Vdram = 0
4849 01:18:44.241861 Vddq = 0
4850 01:18:44.242356 Vmddr = 0
4851 01:18:44.245091 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4852 01:18:44.252009 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4853 01:18:44.254932 MEM_TYPE=3, freq_sel=17
4854 01:18:44.258291 sv_algorithm_assistance_LP4_1600
4855 01:18:44.261976 ============ PULL DRAM RESETB DOWN ============
4856 01:18:44.264979 ========== PULL DRAM RESETB DOWN end =========
4857 01:18:44.272325 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4858 01:18:44.275142 ===================================
4859 01:18:44.275604 LPDDR4 DRAM CONFIGURATION
4860 01:18:44.278562 ===================================
4861 01:18:44.281869 EX_ROW_EN[0] = 0x0
4862 01:18:44.282477 EX_ROW_EN[1] = 0x0
4863 01:18:44.285034 LP4Y_EN = 0x0
4864 01:18:44.288473 WORK_FSP = 0x0
4865 01:18:44.289036 WL = 0x3
4866 01:18:44.291394 RL = 0x3
4867 01:18:44.291853 BL = 0x2
4868 01:18:44.295106 RPST = 0x0
4869 01:18:44.295656 RD_PRE = 0x0
4870 01:18:44.298114 WR_PRE = 0x1
4871 01:18:44.298762 WR_PST = 0x0
4872 01:18:44.301210 DBI_WR = 0x0
4873 01:18:44.301666 DBI_RD = 0x0
4874 01:18:44.304530 OTF = 0x1
4875 01:18:44.308701 ===================================
4876 01:18:44.311718 ===================================
4877 01:18:44.312178 ANA top config
4878 01:18:44.314982 ===================================
4879 01:18:44.318451 DLL_ASYNC_EN = 0
4880 01:18:44.321515 ALL_SLAVE_EN = 1
4881 01:18:44.322094 NEW_RANK_MODE = 1
4882 01:18:44.324600 DLL_IDLE_MODE = 1
4883 01:18:44.328439 LP45_APHY_COMB_EN = 1
4884 01:18:44.331653 TX_ODT_DIS = 1
4885 01:18:44.335028 NEW_8X_MODE = 1
4886 01:18:44.338122 ===================================
4887 01:18:44.341344 ===================================
4888 01:18:44.341912 data_rate = 1866
4889 01:18:44.344782 CKR = 1
4890 01:18:44.348276 DQ_P2S_RATIO = 8
4891 01:18:44.351227 ===================================
4892 01:18:44.354472 CA_P2S_RATIO = 8
4893 01:18:44.357644 DQ_CA_OPEN = 0
4894 01:18:44.360916 DQ_SEMI_OPEN = 0
4895 01:18:44.361379 CA_SEMI_OPEN = 0
4896 01:18:44.364792 CA_FULL_RATE = 0
4897 01:18:44.367582 DQ_CKDIV4_EN = 1
4898 01:18:44.370918 CA_CKDIV4_EN = 1
4899 01:18:44.374206 CA_PREDIV_EN = 0
4900 01:18:44.377677 PH8_DLY = 0
4901 01:18:44.378138 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4902 01:18:44.381165 DQ_AAMCK_DIV = 4
4903 01:18:44.384274 CA_AAMCK_DIV = 4
4904 01:18:44.387936 CA_ADMCK_DIV = 4
4905 01:18:44.390672 DQ_TRACK_CA_EN = 0
4906 01:18:44.394763 CA_PICK = 933
4907 01:18:44.397917 CA_MCKIO = 933
4908 01:18:44.398524 MCKIO_SEMI = 0
4909 01:18:44.400844 PLL_FREQ = 3732
4910 01:18:44.404253 DQ_UI_PI_RATIO = 32
4911 01:18:44.407391 CA_UI_PI_RATIO = 0
4912 01:18:44.410993 ===================================
4913 01:18:44.413835 ===================================
4914 01:18:44.417157 memory_type:LPDDR4
4915 01:18:44.417614 GP_NUM : 10
4916 01:18:44.420614 SRAM_EN : 1
4917 01:18:44.424321 MD32_EN : 0
4918 01:18:44.427684 ===================================
4919 01:18:44.428143 [ANA_INIT] >>>>>>>>>>>>>>
4920 01:18:44.430296 <<<<<< [CONFIGURE PHASE]: ANA_TX
4921 01:18:44.433599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4922 01:18:44.437336 ===================================
4923 01:18:44.440849 data_rate = 1866,PCW = 0X8f00
4924 01:18:44.444037 ===================================
4925 01:18:44.447508 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4926 01:18:44.454358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 01:18:44.457698 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 01:18:44.464289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4929 01:18:44.467444 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4930 01:18:44.470469 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4931 01:18:44.471030 [ANA_INIT] flow start
4932 01:18:44.474050 [ANA_INIT] PLL >>>>>>>>
4933 01:18:44.477046 [ANA_INIT] PLL <<<<<<<<
4934 01:18:44.477501 [ANA_INIT] MIDPI >>>>>>>>
4935 01:18:44.480141 [ANA_INIT] MIDPI <<<<<<<<
4936 01:18:44.483595 [ANA_INIT] DLL >>>>>>>>
4937 01:18:44.484048 [ANA_INIT] flow end
4938 01:18:44.490471 ============ LP4 DIFF to SE enter ============
4939 01:18:44.493795 ============ LP4 DIFF to SE exit ============
4940 01:18:44.497233 [ANA_INIT] <<<<<<<<<<<<<
4941 01:18:44.500627 [Flow] Enable top DCM control >>>>>
4942 01:18:44.503951 [Flow] Enable top DCM control <<<<<
4943 01:18:44.506811 Enable DLL master slave shuffle
4944 01:18:44.510413 ==============================================================
4945 01:18:44.513611 Gating Mode config
4946 01:18:44.516684 ==============================================================
4947 01:18:44.520004 Config description:
4948 01:18:44.530241 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4949 01:18:44.536803 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4950 01:18:44.540367 SELPH_MODE 0: By rank 1: By Phase
4951 01:18:44.546681 ==============================================================
4952 01:18:44.549906 GAT_TRACK_EN = 1
4953 01:18:44.553468 RX_GATING_MODE = 2
4954 01:18:44.556848 RX_GATING_TRACK_MODE = 2
4955 01:18:44.560115 SELPH_MODE = 1
4956 01:18:44.560529 PICG_EARLY_EN = 1
4957 01:18:44.563334 VALID_LAT_VALUE = 1
4958 01:18:44.570179 ==============================================================
4959 01:18:44.573518 Enter into Gating configuration >>>>
4960 01:18:44.576634 Exit from Gating configuration <<<<
4961 01:18:44.580324 Enter into DVFS_PRE_config >>>>>
4962 01:18:44.590491 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4963 01:18:44.593587 Exit from DVFS_PRE_config <<<<<
4964 01:18:44.597043 Enter into PICG configuration >>>>
4965 01:18:44.600229 Exit from PICG configuration <<<<
4966 01:18:44.603632 [RX_INPUT] configuration >>>>>
4967 01:18:44.606743 [RX_INPUT] configuration <<<<<
4968 01:18:44.610205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4969 01:18:44.616422 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4970 01:18:44.623087 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 01:18:44.629887 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 01:18:44.636294 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 01:18:44.642762 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 01:18:44.646286 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4975 01:18:44.649347 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4976 01:18:44.653020 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4977 01:18:44.656058 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4978 01:18:44.663105 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4979 01:18:44.666621 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4980 01:18:44.669816 ===================================
4981 01:18:44.673255 LPDDR4 DRAM CONFIGURATION
4982 01:18:44.676074 ===================================
4983 01:18:44.676491 EX_ROW_EN[0] = 0x0
4984 01:18:44.679338 EX_ROW_EN[1] = 0x0
4985 01:18:44.679748 LP4Y_EN = 0x0
4986 01:18:44.682915 WORK_FSP = 0x0
4987 01:18:44.683440 WL = 0x3
4988 01:18:44.686440 RL = 0x3
4989 01:18:44.689582 BL = 0x2
4990 01:18:44.690097 RPST = 0x0
4991 01:18:44.692565 RD_PRE = 0x0
4992 01:18:44.693080 WR_PRE = 0x1
4993 01:18:44.695609 WR_PST = 0x0
4994 01:18:44.696020 DBI_WR = 0x0
4995 01:18:44.699787 DBI_RD = 0x0
4996 01:18:44.700299 OTF = 0x1
4997 01:18:44.702996 ===================================
4998 01:18:44.705840 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4999 01:18:44.712288 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5000 01:18:44.716197 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 01:18:44.719431 ===================================
5002 01:18:44.722649 LPDDR4 DRAM CONFIGURATION
5003 01:18:44.726186 ===================================
5004 01:18:44.726782 EX_ROW_EN[0] = 0x10
5005 01:18:44.729530 EX_ROW_EN[1] = 0x0
5006 01:18:44.729943 LP4Y_EN = 0x0
5007 01:18:44.732650 WORK_FSP = 0x0
5008 01:18:44.733160 WL = 0x3
5009 01:18:44.735791 RL = 0x3
5010 01:18:44.736204 BL = 0x2
5011 01:18:44.739025 RPST = 0x0
5012 01:18:44.739437 RD_PRE = 0x0
5013 01:18:44.742775 WR_PRE = 0x1
5014 01:18:44.745985 WR_PST = 0x0
5015 01:18:44.746573 DBI_WR = 0x0
5016 01:18:44.749157 DBI_RD = 0x0
5017 01:18:44.749686 OTF = 0x1
5018 01:18:44.752816 ===================================
5019 01:18:44.758761 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5020 01:18:44.762490 nWR fixed to 30
5021 01:18:44.765866 [ModeRegInit_LP4] CH0 RK0
5022 01:18:44.766439 [ModeRegInit_LP4] CH0 RK1
5023 01:18:44.769208 [ModeRegInit_LP4] CH1 RK0
5024 01:18:44.772840 [ModeRegInit_LP4] CH1 RK1
5025 01:18:44.773357 match AC timing 9
5026 01:18:44.779311 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5027 01:18:44.782641 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5028 01:18:44.785863 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5029 01:18:44.792162 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5030 01:18:44.795990 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5031 01:18:44.796520 ==
5032 01:18:44.798942 Dram Type= 6, Freq= 0, CH_0, rank 0
5033 01:18:44.802945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5034 01:18:44.803464 ==
5035 01:18:44.808742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5036 01:18:44.815984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5037 01:18:44.819475 [CA 0] Center 37 (6~68) winsize 63
5038 01:18:44.822433 [CA 1] Center 37 (7~68) winsize 62
5039 01:18:44.825667 [CA 2] Center 34 (4~65) winsize 62
5040 01:18:44.828669 [CA 3] Center 34 (3~65) winsize 63
5041 01:18:44.832585 [CA 4] Center 33 (3~64) winsize 62
5042 01:18:44.835792 [CA 5] Center 32 (2~62) winsize 61
5043 01:18:44.836344
5044 01:18:44.838820 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5045 01:18:44.839234
5046 01:18:44.842383 [CATrainingPosCal] consider 1 rank data
5047 01:18:44.845537 u2DelayCellTimex100 = 270/100 ps
5048 01:18:44.848648 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5049 01:18:44.852321 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5050 01:18:44.855503 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5051 01:18:44.858707 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5052 01:18:44.861792 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5053 01:18:44.868616 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5054 01:18:44.869134
5055 01:18:44.871742 CA PerBit enable=1, Macro0, CA PI delay=32
5056 01:18:44.872155
5057 01:18:44.875242 [CBTSetCACLKResult] CA Dly = 32
5058 01:18:44.875755 CS Dly: 5 (0~36)
5059 01:18:44.876084 ==
5060 01:18:44.878230 Dram Type= 6, Freq= 0, CH_0, rank 1
5061 01:18:44.882187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 01:18:44.885488 ==
5063 01:18:44.888503 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 01:18:44.895160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5065 01:18:44.898286 [CA 0] Center 37 (6~68) winsize 63
5066 01:18:44.901966 [CA 1] Center 37 (6~68) winsize 63
5067 01:18:44.905341 [CA 2] Center 34 (4~65) winsize 62
5068 01:18:44.908584 [CA 3] Center 34 (4~65) winsize 62
5069 01:18:44.911865 [CA 4] Center 33 (3~63) winsize 61
5070 01:18:44.915150 [CA 5] Center 32 (2~62) winsize 61
5071 01:18:44.915608
5072 01:18:44.918060 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5073 01:18:44.918557
5074 01:18:44.921685 [CATrainingPosCal] consider 2 rank data
5075 01:18:44.924647 u2DelayCellTimex100 = 270/100 ps
5076 01:18:44.928357 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5077 01:18:44.931625 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5078 01:18:44.935062 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5079 01:18:44.941174 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5080 01:18:44.945272 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5081 01:18:44.948419 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5082 01:18:44.949002
5083 01:18:44.951220 CA PerBit enable=1, Macro0, CA PI delay=32
5084 01:18:44.951677
5085 01:18:44.954275 [CBTSetCACLKResult] CA Dly = 32
5086 01:18:44.954791 CS Dly: 5 (0~37)
5087 01:18:44.955330
5088 01:18:44.957825 ----->DramcWriteLeveling(PI) begin...
5089 01:18:44.961012 ==
5090 01:18:44.964106 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 01:18:44.968156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 01:18:44.968722 ==
5093 01:18:44.971076 Write leveling (Byte 0): 32 => 32
5094 01:18:44.974454 Write leveling (Byte 1): 30 => 30
5095 01:18:44.977833 DramcWriteLeveling(PI) end<-----
5096 01:18:44.978298
5097 01:18:44.978711 ==
5098 01:18:44.981137 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 01:18:44.984547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 01:18:44.985115 ==
5101 01:18:44.987603 [Gating] SW mode calibration
5102 01:18:44.994348 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5103 01:18:45.000998 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5104 01:18:45.004594 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5105 01:18:45.007843 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 01:18:45.014477 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 01:18:45.017727 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 01:18:45.021242 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 01:18:45.027642 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 01:18:45.030865 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5111 01:18:45.034215 0 14 28 | B1->B0 | 3333 2424 | 1 0 | (1 1) (0 0)
5112 01:18:45.037696 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5113 01:18:45.044136 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 01:18:45.047475 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 01:18:45.050883 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 01:18:45.057825 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 01:18:45.060720 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 01:18:45.063684 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 01:18:45.070844 0 15 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
5120 01:18:45.074207 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
5121 01:18:45.077208 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 01:18:45.083383 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 01:18:45.086604 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 01:18:45.090181 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 01:18:45.097273 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 01:18:45.100603 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 01:18:45.103600 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5128 01:18:45.110108 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5129 01:18:45.113892 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 01:18:45.117034 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 01:18:45.123800 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 01:18:45.127010 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 01:18:45.130357 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 01:18:45.137053 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 01:18:45.140119 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 01:18:45.143251 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 01:18:45.150151 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 01:18:45.153169 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 01:18:45.156489 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 01:18:45.162965 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 01:18:45.167028 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 01:18:45.170101 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5143 01:18:45.176359 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 01:18:45.176909 Total UI for P1: 0, mck2ui 16
5145 01:18:45.183128 best dqsien dly found for B0: ( 1, 2, 24)
5146 01:18:45.186280 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5147 01:18:45.189535 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 01:18:45.192885 Total UI for P1: 0, mck2ui 16
5149 01:18:45.196159 best dqsien dly found for B1: ( 1, 2, 30)
5150 01:18:45.199945 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5151 01:18:45.203039 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5152 01:18:45.203498
5153 01:18:45.209588 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5154 01:18:45.213151 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5155 01:18:45.215762 [Gating] SW calibration Done
5156 01:18:45.216220 ==
5157 01:18:45.219351 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 01:18:45.222832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 01:18:45.223292 ==
5160 01:18:45.223646 RX Vref Scan: 0
5161 01:18:45.223974
5162 01:18:45.226165 RX Vref 0 -> 0, step: 1
5163 01:18:45.226778
5164 01:18:45.229096 RX Delay -80 -> 252, step: 8
5165 01:18:45.232656 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5166 01:18:45.235957 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5167 01:18:45.238913 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5168 01:18:45.245822 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5169 01:18:45.249241 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5170 01:18:45.252223 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5171 01:18:45.256202 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5172 01:18:45.259204 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5173 01:18:45.262891 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5174 01:18:45.269112 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5175 01:18:45.272898 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5176 01:18:45.276465 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5177 01:18:45.279438 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5178 01:18:45.282548 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5179 01:18:45.289288 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5180 01:18:45.292700 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5181 01:18:45.293259 ==
5182 01:18:45.295805 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 01:18:45.298785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 01:18:45.299246 ==
5185 01:18:45.299602 DQS Delay:
5186 01:18:45.302567 DQS0 = 0, DQS1 = 0
5187 01:18:45.303180 DQM Delay:
5188 01:18:45.305799 DQM0 = 105, DQM1 = 95
5189 01:18:45.306252 DQ Delay:
5190 01:18:45.309035 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5191 01:18:45.312825 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5192 01:18:45.316110 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5193 01:18:45.318807 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5194 01:18:45.319266
5195 01:18:45.319622
5196 01:18:45.319954 ==
5197 01:18:45.322239 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 01:18:45.328641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 01:18:45.329206 ==
5200 01:18:45.329587
5201 01:18:45.329928
5202 01:18:45.330432 TX Vref Scan disable
5203 01:18:45.332436 == TX Byte 0 ==
5204 01:18:45.336010 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5205 01:18:45.342562 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5206 01:18:45.343115 == TX Byte 1 ==
5207 01:18:45.345675 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5208 01:18:45.349495 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5209 01:18:45.353080 ==
5210 01:18:45.355815 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 01:18:45.359672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 01:18:45.360224 ==
5213 01:18:45.360587
5214 01:18:45.360920
5215 01:18:45.362589 TX Vref Scan disable
5216 01:18:45.363048 == TX Byte 0 ==
5217 01:18:45.369136 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5218 01:18:45.373061 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5219 01:18:45.373611 == TX Byte 1 ==
5220 01:18:45.379455 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5221 01:18:45.382871 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5222 01:18:45.383426
5223 01:18:45.383787 [DATLAT]
5224 01:18:45.385941 Freq=933, CH0 RK0
5225 01:18:45.386450
5226 01:18:45.386829 DATLAT Default: 0xd
5227 01:18:45.389186 0, 0xFFFF, sum = 0
5228 01:18:45.389742 1, 0xFFFF, sum = 0
5229 01:18:45.392531 2, 0xFFFF, sum = 0
5230 01:18:45.393148 3, 0xFFFF, sum = 0
5231 01:18:45.395881 4, 0xFFFF, sum = 0
5232 01:18:45.396440 5, 0xFFFF, sum = 0
5233 01:18:45.399398 6, 0xFFFF, sum = 0
5234 01:18:45.402516 7, 0xFFFF, sum = 0
5235 01:18:45.402986 8, 0xFFFF, sum = 0
5236 01:18:45.406044 9, 0xFFFF, sum = 0
5237 01:18:45.406636 10, 0x0, sum = 1
5238 01:18:45.409093 11, 0x0, sum = 2
5239 01:18:45.409656 12, 0x0, sum = 3
5240 01:18:45.410027 13, 0x0, sum = 4
5241 01:18:45.411856 best_step = 11
5242 01:18:45.412314
5243 01:18:45.412671 ==
5244 01:18:45.415695 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 01:18:45.418803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 01:18:45.419278 ==
5247 01:18:45.422450 RX Vref Scan: 1
5248 01:18:45.423055
5249 01:18:45.423430 RX Vref 0 -> 0, step: 1
5250 01:18:45.425661
5251 01:18:45.426206 RX Delay -45 -> 252, step: 4
5252 01:18:45.426643
5253 01:18:45.428532 Set Vref, RX VrefLevel [Byte0]: 54
5254 01:18:45.432339 [Byte1]: 46
5255 01:18:45.436565
5256 01:18:45.437109 Final RX Vref Byte 0 = 54 to rank0
5257 01:18:45.440003 Final RX Vref Byte 1 = 46 to rank0
5258 01:18:45.442893 Final RX Vref Byte 0 = 54 to rank1
5259 01:18:45.446555 Final RX Vref Byte 1 = 46 to rank1==
5260 01:18:45.450077 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 01:18:45.456341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 01:18:45.456898 ==
5263 01:18:45.457262 DQS Delay:
5264 01:18:45.457598 DQS0 = 0, DQS1 = 0
5265 01:18:45.459561 DQM Delay:
5266 01:18:45.460072 DQM0 = 104, DQM1 = 94
5267 01:18:45.462845 DQ Delay:
5268 01:18:45.466095 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =104
5269 01:18:45.469670 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5270 01:18:45.473157 DQ8 =84, DQ9 =82, DQ10 =96, DQ11 =90
5271 01:18:45.476262 DQ12 =96, DQ13 =98, DQ14 =106, DQ15 =100
5272 01:18:45.476813
5273 01:18:45.477178
5274 01:18:45.483007 [DQSOSCAuto] RK0, (LSB)MR18= 0x3028, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5275 01:18:45.486169 CH0 RK0: MR19=505, MR18=3028
5276 01:18:45.492576 CH0_RK0: MR19=0x505, MR18=0x3028, DQSOSC=406, MR23=63, INC=65, DEC=43
5277 01:18:45.493034
5278 01:18:45.495797 ----->DramcWriteLeveling(PI) begin...
5279 01:18:45.496257 ==
5280 01:18:45.499107 Dram Type= 6, Freq= 0, CH_0, rank 1
5281 01:18:45.502379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 01:18:45.502792 ==
5283 01:18:45.505978 Write leveling (Byte 0): 34 => 34
5284 01:18:45.508991 Write leveling (Byte 1): 30 => 30
5285 01:18:45.512283 DramcWriteLeveling(PI) end<-----
5286 01:18:45.512504
5287 01:18:45.512675 ==
5288 01:18:45.515366 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 01:18:45.522336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 01:18:45.522485 ==
5291 01:18:45.522600 [Gating] SW mode calibration
5292 01:18:45.532646 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5293 01:18:45.535855 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5294 01:18:45.538776 0 14 0 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
5295 01:18:45.545958 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 01:18:45.549319 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 01:18:45.552158 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 01:18:45.558578 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 01:18:45.562484 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 01:18:45.565400 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 01:18:45.572112 0 14 28 | B1->B0 | 2e2e 2b2b | 0 0 | (0 0) (0 1)
5302 01:18:45.575947 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 01:18:45.579155 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 01:18:45.586014 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 01:18:45.588770 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 01:18:45.592505 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 01:18:45.598918 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 01:18:45.602420 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 01:18:45.605784 0 15 28 | B1->B0 | 3c3c 3636 | 0 1 | (0 0) (0 0)
5310 01:18:45.612207 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 01:18:45.616290 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 01:18:45.619479 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 01:18:45.625771 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 01:18:45.629221 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 01:18:45.632181 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 01:18:45.638991 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 01:18:45.642178 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5318 01:18:45.645518 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 01:18:45.651934 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 01:18:45.655679 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 01:18:45.658885 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 01:18:45.665736 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 01:18:45.668919 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 01:18:45.672492 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 01:18:45.675742 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 01:18:45.682059 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 01:18:45.684992 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 01:18:45.688312 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 01:18:45.695179 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 01:18:45.698518 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 01:18:45.701611 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 01:18:45.708154 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 01:18:45.711491 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5334 01:18:45.714624 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 01:18:45.718112 Total UI for P1: 0, mck2ui 16
5336 01:18:45.721583 best dqsien dly found for B0: ( 1, 2, 28)
5337 01:18:45.724720 Total UI for P1: 0, mck2ui 16
5338 01:18:45.727985 best dqsien dly found for B1: ( 1, 2, 30)
5339 01:18:45.731367 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5340 01:18:45.737801 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5341 01:18:45.738082
5342 01:18:45.741043 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5343 01:18:45.744335 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5344 01:18:45.747494 [Gating] SW calibration Done
5345 01:18:45.747679 ==
5346 01:18:45.750683 Dram Type= 6, Freq= 0, CH_0, rank 1
5347 01:18:45.753952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 01:18:45.754120 ==
5349 01:18:45.757164 RX Vref Scan: 0
5350 01:18:45.757307
5351 01:18:45.757431 RX Vref 0 -> 0, step: 1
5352 01:18:45.757557
5353 01:18:45.760826 RX Delay -80 -> 252, step: 8
5354 01:18:45.764181 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5355 01:18:45.767411 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5356 01:18:45.774387 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5357 01:18:45.777395 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5358 01:18:45.780557 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5359 01:18:45.783887 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5360 01:18:45.787591 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5361 01:18:45.794215 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5362 01:18:45.797467 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5363 01:18:45.800823 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5364 01:18:45.803928 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5365 01:18:45.807246 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5366 01:18:45.810274 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5367 01:18:45.817222 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5368 01:18:45.820649 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5369 01:18:45.823699 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5370 01:18:45.823840 ==
5371 01:18:45.826905 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 01:18:45.830485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 01:18:45.830599 ==
5374 01:18:45.834205 DQS Delay:
5375 01:18:45.834360 DQS0 = 0, DQS1 = 0
5376 01:18:45.837157 DQM Delay:
5377 01:18:45.837242 DQM0 = 104, DQM1 = 93
5378 01:18:45.837307 DQ Delay:
5379 01:18:45.840209 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5380 01:18:45.843883 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5381 01:18:45.846936 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5382 01:18:45.850254 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5383 01:18:45.853563
5384 01:18:45.853649
5385 01:18:45.853712 ==
5386 01:18:45.857161 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 01:18:45.860456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 01:18:45.860553 ==
5389 01:18:45.860618
5390 01:18:45.860677
5391 01:18:45.863381 TX Vref Scan disable
5392 01:18:45.863464 == TX Byte 0 ==
5393 01:18:45.870572 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5394 01:18:45.873698 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5395 01:18:45.873790 == TX Byte 1 ==
5396 01:18:45.880218 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5397 01:18:45.883884 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5398 01:18:45.883984 ==
5399 01:18:45.887204 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 01:18:45.890232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 01:18:45.890401 ==
5402 01:18:45.890513
5403 01:18:45.890622
5404 01:18:45.893387 TX Vref Scan disable
5405 01:18:45.896837 == TX Byte 0 ==
5406 01:18:45.899916 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5407 01:18:45.903247 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5408 01:18:45.906553 == TX Byte 1 ==
5409 01:18:45.910238 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5410 01:18:45.913608 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5411 01:18:45.913749
5412 01:18:45.916516 [DATLAT]
5413 01:18:45.916627 Freq=933, CH0 RK1
5414 01:18:45.916725
5415 01:18:45.920154 DATLAT Default: 0xb
5416 01:18:45.920262 0, 0xFFFF, sum = 0
5417 01:18:45.923359 1, 0xFFFF, sum = 0
5418 01:18:45.923468 2, 0xFFFF, sum = 0
5419 01:18:45.926567 3, 0xFFFF, sum = 0
5420 01:18:45.926674 4, 0xFFFF, sum = 0
5421 01:18:45.929696 5, 0xFFFF, sum = 0
5422 01:18:45.929803 6, 0xFFFF, sum = 0
5423 01:18:45.933425 7, 0xFFFF, sum = 0
5424 01:18:45.933548 8, 0xFFFF, sum = 0
5425 01:18:45.936408 9, 0xFFFF, sum = 0
5426 01:18:45.936597 10, 0x0, sum = 1
5427 01:18:45.940006 11, 0x0, sum = 2
5428 01:18:45.940134 12, 0x0, sum = 3
5429 01:18:45.943454 13, 0x0, sum = 4
5430 01:18:45.943540 best_step = 11
5431 01:18:45.943603
5432 01:18:45.943661 ==
5433 01:18:45.946607 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 01:18:45.953432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 01:18:45.953521 ==
5436 01:18:45.953584 RX Vref Scan: 0
5437 01:18:45.953645
5438 01:18:45.956603 RX Vref 0 -> 0, step: 1
5439 01:18:45.956683
5440 01:18:45.959867 RX Delay -53 -> 252, step: 4
5441 01:18:45.962956 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5442 01:18:45.966379 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5443 01:18:45.973099 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5444 01:18:45.976361 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5445 01:18:45.979459 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5446 01:18:45.983148 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5447 01:18:45.986075 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5448 01:18:45.992697 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5449 01:18:45.996794 iDelay=199, Bit 8, Center 84 (3 ~ 166) 164
5450 01:18:45.999817 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5451 01:18:46.003095 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5452 01:18:46.006252 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5453 01:18:46.009549 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5454 01:18:46.015885 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5455 01:18:46.019219 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5456 01:18:46.023073 iDelay=199, Bit 15, Center 100 (15 ~ 186) 172
5457 01:18:46.023166 ==
5458 01:18:46.026048 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 01:18:46.029206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 01:18:46.032524 ==
5461 01:18:46.032620 DQS Delay:
5462 01:18:46.032686 DQS0 = 0, DQS1 = 0
5463 01:18:46.036442 DQM Delay:
5464 01:18:46.036530 DQM0 = 104, DQM1 = 93
5465 01:18:46.039663 DQ Delay:
5466 01:18:46.042764 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5467 01:18:46.046284 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5468 01:18:46.049686 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5469 01:18:46.052801 DQ12 =98, DQ13 =98, DQ14 =104, DQ15 =100
5470 01:18:46.052885
5471 01:18:46.052949
5472 01:18:46.059115 [DQSOSCAuto] RK1, (LSB)MR18= 0x2902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5473 01:18:46.062958 CH0 RK1: MR19=505, MR18=2902
5474 01:18:46.069580 CH0_RK1: MR19=0x505, MR18=0x2902, DQSOSC=408, MR23=63, INC=65, DEC=43
5475 01:18:46.072918 [RxdqsGatingPostProcess] freq 933
5476 01:18:46.076077 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5477 01:18:46.079077 best DQS0 dly(2T, 0.5T) = (0, 10)
5478 01:18:46.082372 best DQS1 dly(2T, 0.5T) = (0, 10)
5479 01:18:46.085974 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5480 01:18:46.089294 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5481 01:18:46.092462 best DQS0 dly(2T, 0.5T) = (0, 10)
5482 01:18:46.095724 best DQS1 dly(2T, 0.5T) = (0, 10)
5483 01:18:46.098931 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5484 01:18:46.102674 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5485 01:18:46.105989 Pre-setting of DQS Precalculation
5486 01:18:46.109144 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5487 01:18:46.112183 ==
5488 01:18:46.112272 Dram Type= 6, Freq= 0, CH_1, rank 0
5489 01:18:46.119370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 01:18:46.119487 ==
5491 01:18:46.122556 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5492 01:18:46.129311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5493 01:18:46.132321 [CA 0] Center 36 (6~67) winsize 62
5494 01:18:46.136009 [CA 1] Center 37 (6~68) winsize 63
5495 01:18:46.139425 [CA 2] Center 34 (4~65) winsize 62
5496 01:18:46.142668 [CA 3] Center 34 (4~65) winsize 62
5497 01:18:46.146244 [CA 4] Center 34 (4~65) winsize 62
5498 01:18:46.149739 [CA 5] Center 33 (3~64) winsize 62
5499 01:18:46.150252
5500 01:18:46.152571 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5501 01:18:46.152989
5502 01:18:46.159373 [CATrainingPosCal] consider 1 rank data
5503 01:18:46.159794 u2DelayCellTimex100 = 270/100 ps
5504 01:18:46.165850 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5505 01:18:46.169615 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5506 01:18:46.172983 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5507 01:18:46.176368 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5508 01:18:46.179127 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5509 01:18:46.182461 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5510 01:18:46.183022
5511 01:18:46.186280 CA PerBit enable=1, Macro0, CA PI delay=33
5512 01:18:46.186850
5513 01:18:46.189191 [CBTSetCACLKResult] CA Dly = 33
5514 01:18:46.192490 CS Dly: 7 (0~38)
5515 01:18:46.192907 ==
5516 01:18:46.195735 Dram Type= 6, Freq= 0, CH_1, rank 1
5517 01:18:46.198999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 01:18:46.199576 ==
5519 01:18:46.206053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5520 01:18:46.208674 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5521 01:18:46.213397 [CA 0] Center 36 (6~67) winsize 62
5522 01:18:46.216219 [CA 1] Center 37 (7~68) winsize 62
5523 01:18:46.220022 [CA 2] Center 35 (4~66) winsize 63
5524 01:18:46.222715 [CA 3] Center 34 (4~65) winsize 62
5525 01:18:46.226295 [CA 4] Center 34 (4~65) winsize 62
5526 01:18:46.229444 [CA 5] Center 34 (4~64) winsize 61
5527 01:18:46.229876
5528 01:18:46.232703 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5529 01:18:46.233115
5530 01:18:46.236223 [CATrainingPosCal] consider 2 rank data
5531 01:18:46.239480 u2DelayCellTimex100 = 270/100 ps
5532 01:18:46.243181 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5533 01:18:46.249568 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5534 01:18:46.252853 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5535 01:18:46.256419 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5536 01:18:46.259195 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5537 01:18:46.262755 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5538 01:18:46.263175
5539 01:18:46.265934 CA PerBit enable=1, Macro0, CA PI delay=34
5540 01:18:46.266414
5541 01:18:46.269402 [CBTSetCACLKResult] CA Dly = 34
5542 01:18:46.269914 CS Dly: 8 (0~40)
5543 01:18:46.272586
5544 01:18:46.276136 ----->DramcWriteLeveling(PI) begin...
5545 01:18:46.276668 ==
5546 01:18:46.279258 Dram Type= 6, Freq= 0, CH_1, rank 0
5547 01:18:46.282893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 01:18:46.283451 ==
5549 01:18:46.286205 Write leveling (Byte 0): 29 => 29
5550 01:18:46.289076 Write leveling (Byte 1): 27 => 27
5551 01:18:46.292580 DramcWriteLeveling(PI) end<-----
5552 01:18:46.293140
5553 01:18:46.293505 ==
5554 01:18:46.295788 Dram Type= 6, Freq= 0, CH_1, rank 0
5555 01:18:46.299247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 01:18:46.299878 ==
5557 01:18:46.302996 [Gating] SW mode calibration
5558 01:18:46.309078 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5559 01:18:46.316262 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5560 01:18:46.319115 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 01:18:46.323011 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 01:18:46.329480 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 01:18:46.332447 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 01:18:46.335581 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 01:18:46.342653 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5566 01:18:46.345851 0 14 24 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
5567 01:18:46.349023 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5568 01:18:46.355500 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 01:18:46.358828 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 01:18:46.362112 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 01:18:46.365707 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 01:18:46.372290 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 01:18:46.375476 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 01:18:46.378769 0 15 24 | B1->B0 | 2424 2e2e | 1 1 | (0 0) (0 0)
5575 01:18:46.385375 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5576 01:18:46.388806 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 01:18:46.392196 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 01:18:46.399171 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 01:18:46.402148 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 01:18:46.405417 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 01:18:46.411960 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 01:18:46.415083 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5583 01:18:46.418490 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5584 01:18:46.425478 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 01:18:46.428309 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 01:18:46.431793 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 01:18:46.438658 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 01:18:46.442004 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 01:18:46.444959 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 01:18:46.451643 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 01:18:46.454913 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 01:18:46.458236 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 01:18:46.465511 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 01:18:46.468038 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 01:18:46.471801 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 01:18:46.478389 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 01:18:46.481595 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 01:18:46.484921 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5599 01:18:46.491668 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5600 01:18:46.492353 Total UI for P1: 0, mck2ui 16
5601 01:18:46.498587 best dqsien dly found for B0: ( 1, 2, 24)
5602 01:18:46.501664 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 01:18:46.505101 Total UI for P1: 0, mck2ui 16
5604 01:18:46.508063 best dqsien dly found for B1: ( 1, 2, 28)
5605 01:18:46.511402 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5606 01:18:46.514771 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5607 01:18:46.515400
5608 01:18:46.518138 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5609 01:18:46.521416 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5610 01:18:46.524735 [Gating] SW calibration Done
5611 01:18:46.525308 ==
5612 01:18:46.527946 Dram Type= 6, Freq= 0, CH_1, rank 0
5613 01:18:46.531599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5614 01:18:46.534688 ==
5615 01:18:46.535143 RX Vref Scan: 0
5616 01:18:46.535501
5617 01:18:46.538156 RX Vref 0 -> 0, step: 1
5618 01:18:46.538747
5619 01:18:46.539104 RX Delay -80 -> 252, step: 8
5620 01:18:46.544966 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5621 01:18:46.547865 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5622 01:18:46.551849 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5623 01:18:46.554564 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5624 01:18:46.558156 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5625 01:18:46.561424 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5626 01:18:46.567852 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5627 01:18:46.571497 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5628 01:18:46.574824 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5629 01:18:46.578495 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5630 01:18:46.581144 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5631 01:18:46.584808 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5632 01:18:46.591569 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5633 01:18:46.594818 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5634 01:18:46.597615 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5635 01:18:46.601177 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5636 01:18:46.601705 ==
5637 01:18:46.604969 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 01:18:46.610964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 01:18:46.611520 ==
5640 01:18:46.611877 DQS Delay:
5641 01:18:46.614884 DQS0 = 0, DQS1 = 0
5642 01:18:46.615438 DQM Delay:
5643 01:18:46.615796 DQM0 = 101, DQM1 = 99
5644 01:18:46.617873 DQ Delay:
5645 01:18:46.621234 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5646 01:18:46.624933 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5647 01:18:46.627875 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5648 01:18:46.631023 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5649 01:18:46.631497
5650 01:18:46.631969
5651 01:18:46.632413 ==
5652 01:18:46.634373 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 01:18:46.638103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 01:18:46.638720 ==
5655 01:18:46.639087
5656 01:18:46.639420
5657 01:18:46.641058 TX Vref Scan disable
5658 01:18:46.644135 == TX Byte 0 ==
5659 01:18:46.647772 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5660 01:18:46.650936 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5661 01:18:46.654819 == TX Byte 1 ==
5662 01:18:46.657654 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5663 01:18:46.661384 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5664 01:18:46.661937 ==
5665 01:18:46.664379 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 01:18:46.671142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 01:18:46.671733 ==
5668 01:18:46.672221
5669 01:18:46.672668
5670 01:18:46.673105 TX Vref Scan disable
5671 01:18:46.674792 == TX Byte 0 ==
5672 01:18:46.677996 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5673 01:18:46.684906 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5674 01:18:46.685370 == TX Byte 1 ==
5675 01:18:46.688453 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5676 01:18:46.694970 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5677 01:18:46.695522
5678 01:18:46.695883 [DATLAT]
5679 01:18:46.696214 Freq=933, CH1 RK0
5680 01:18:46.696534
5681 01:18:46.697940 DATLAT Default: 0xd
5682 01:18:46.698414 0, 0xFFFF, sum = 0
5683 01:18:46.701245 1, 0xFFFF, sum = 0
5684 01:18:46.701703 2, 0xFFFF, sum = 0
5685 01:18:46.704749 3, 0xFFFF, sum = 0
5686 01:18:46.707766 4, 0xFFFF, sum = 0
5687 01:18:46.708250 5, 0xFFFF, sum = 0
5688 01:18:46.710937 6, 0xFFFF, sum = 0
5689 01:18:46.711403 7, 0xFFFF, sum = 0
5690 01:18:46.715113 8, 0xFFFF, sum = 0
5691 01:18:46.715685 9, 0xFFFF, sum = 0
5692 01:18:46.717716 10, 0x0, sum = 1
5693 01:18:46.718178 11, 0x0, sum = 2
5694 01:18:46.721752 12, 0x0, sum = 3
5695 01:18:46.722430 13, 0x0, sum = 4
5696 01:18:46.722824 best_step = 11
5697 01:18:46.723197
5698 01:18:46.725028 ==
5699 01:18:46.727557 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 01:18:46.731109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 01:18:46.731587 ==
5702 01:18:46.732069 RX Vref Scan: 1
5703 01:18:46.732519
5704 01:18:46.734361 RX Vref 0 -> 0, step: 1
5705 01:18:46.734854
5706 01:18:46.737640 RX Delay -45 -> 252, step: 4
5707 01:18:46.738118
5708 01:18:46.741133 Set Vref, RX VrefLevel [Byte0]: 53
5709 01:18:46.744469 [Byte1]: 53
5710 01:18:46.744904
5711 01:18:46.748226 Final RX Vref Byte 0 = 53 to rank0
5712 01:18:46.751333 Final RX Vref Byte 1 = 53 to rank0
5713 01:18:46.754240 Final RX Vref Byte 0 = 53 to rank1
5714 01:18:46.757949 Final RX Vref Byte 1 = 53 to rank1==
5715 01:18:46.760984 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 01:18:46.763988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 01:18:46.767244 ==
5718 01:18:46.767700 DQS Delay:
5719 01:18:46.768024 DQS0 = 0, DQS1 = 0
5720 01:18:46.770791 DQM Delay:
5721 01:18:46.771200 DQM0 = 103, DQM1 = 99
5722 01:18:46.774553 DQ Delay:
5723 01:18:46.777625 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5724 01:18:46.781001 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5725 01:18:46.784159 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5726 01:18:46.787463 DQ12 =104, DQ13 =106, DQ14 =108, DQ15 =108
5727 01:18:46.787877
5728 01:18:46.788200
5729 01:18:46.794288 [DQSOSCAuto] RK0, (LSB)MR18= 0x1930, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5730 01:18:46.797561 CH1 RK0: MR19=505, MR18=1930
5731 01:18:46.804237 CH1_RK0: MR19=0x505, MR18=0x1930, DQSOSC=406, MR23=63, INC=65, DEC=43
5732 01:18:46.804789
5733 01:18:46.807174 ----->DramcWriteLeveling(PI) begin...
5734 01:18:46.807640 ==
5735 01:18:46.810798 Dram Type= 6, Freq= 0, CH_1, rank 1
5736 01:18:46.813991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 01:18:46.814602 ==
5738 01:18:46.817191 Write leveling (Byte 0): 24 => 24
5739 01:18:46.820224 Write leveling (Byte 1): 26 => 26
5740 01:18:46.824062 DramcWriteLeveling(PI) end<-----
5741 01:18:46.824519
5742 01:18:46.824873 ==
5743 01:18:46.827243 Dram Type= 6, Freq= 0, CH_1, rank 1
5744 01:18:46.830431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 01:18:46.833926 ==
5746 01:18:46.834531 [Gating] SW mode calibration
5747 01:18:46.840353 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5748 01:18:46.847022 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5749 01:18:46.850486 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 01:18:46.857333 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 01:18:46.860751 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 01:18:46.863888 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 01:18:46.870456 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 01:18:46.873444 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5755 01:18:46.877005 0 14 24 | B1->B0 | 2828 2f2f | 0 1 | (0 1) (0 0)
5756 01:18:46.883758 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
5757 01:18:46.886992 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 01:18:46.890175 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 01:18:46.896826 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 01:18:46.900067 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 01:18:46.903382 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 01:18:46.910173 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 01:18:46.913179 0 15 24 | B1->B0 | 3333 2323 | 1 0 | (0 0) (0 0)
5764 01:18:46.916839 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5765 01:18:46.923856 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 01:18:46.927004 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 01:18:46.930063 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 01:18:46.936659 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 01:18:46.940184 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 01:18:46.943238 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 01:18:46.949997 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5772 01:18:46.953037 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5773 01:18:46.956407 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 01:18:46.963529 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 01:18:46.966616 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 01:18:46.969689 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 01:18:46.973197 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 01:18:46.980011 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 01:18:46.983289 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 01:18:46.986287 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 01:18:46.992672 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 01:18:46.996293 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 01:18:46.999603 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 01:18:47.005785 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 01:18:47.009248 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 01:18:47.012830 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 01:18:47.019185 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5788 01:18:47.022248 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5789 01:18:47.025618 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 01:18:47.028894 Total UI for P1: 0, mck2ui 16
5791 01:18:47.032635 best dqsien dly found for B0: ( 1, 2, 28)
5792 01:18:47.035584 Total UI for P1: 0, mck2ui 16
5793 01:18:47.038729 best dqsien dly found for B1: ( 1, 2, 26)
5794 01:18:47.043109 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5795 01:18:47.045852 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5796 01:18:47.045935
5797 01:18:47.052411 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5798 01:18:47.055445 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5799 01:18:47.055527 [Gating] SW calibration Done
5800 01:18:47.058611 ==
5801 01:18:47.062571 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 01:18:47.065787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 01:18:47.065869 ==
5804 01:18:47.065933 RX Vref Scan: 0
5805 01:18:47.065993
5806 01:18:47.069136 RX Vref 0 -> 0, step: 1
5807 01:18:47.069218
5808 01:18:47.072392 RX Delay -80 -> 252, step: 8
5809 01:18:47.075382 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5810 01:18:47.078552 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5811 01:18:47.082415 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5812 01:18:47.088914 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5813 01:18:47.092219 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5814 01:18:47.095446 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5815 01:18:47.098492 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5816 01:18:47.101759 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5817 01:18:47.105614 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5818 01:18:47.111842 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5819 01:18:47.115223 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5820 01:18:47.118486 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5821 01:18:47.121732 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5822 01:18:47.125397 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5823 01:18:47.132150 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5824 01:18:47.134888 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5825 01:18:47.134971 ==
5826 01:18:47.138178 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 01:18:47.141620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 01:18:47.141714 ==
5829 01:18:47.145106 DQS Delay:
5830 01:18:47.145186 DQS0 = 0, DQS1 = 0
5831 01:18:47.145250 DQM Delay:
5832 01:18:47.148580 DQM0 = 102, DQM1 = 99
5833 01:18:47.148661 DQ Delay:
5834 01:18:47.151556 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5835 01:18:47.155130 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5836 01:18:47.158528 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5837 01:18:47.161577 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5838 01:18:47.161658
5839 01:18:47.161721
5840 01:18:47.164770 ==
5841 01:18:47.167855 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 01:18:47.171309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 01:18:47.171391 ==
5844 01:18:47.171454
5845 01:18:47.171513
5846 01:18:47.174587 TX Vref Scan disable
5847 01:18:47.174666 == TX Byte 0 ==
5848 01:18:47.177843 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5849 01:18:47.184708 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5850 01:18:47.184790 == TX Byte 1 ==
5851 01:18:47.188380 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5852 01:18:47.194773 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5853 01:18:47.194857 ==
5854 01:18:47.198155 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 01:18:47.201236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 01:18:47.201319 ==
5857 01:18:47.201382
5858 01:18:47.201442
5859 01:18:47.205203 TX Vref Scan disable
5860 01:18:47.207809 == TX Byte 0 ==
5861 01:18:47.211561 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5862 01:18:47.214932 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5863 01:18:47.217883 == TX Byte 1 ==
5864 01:18:47.221122 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5865 01:18:47.225121 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5866 01:18:47.225203
5867 01:18:47.225267 [DATLAT]
5868 01:18:47.228331 Freq=933, CH1 RK1
5869 01:18:47.228413
5870 01:18:47.231662 DATLAT Default: 0xb
5871 01:18:47.231744 0, 0xFFFF, sum = 0
5872 01:18:47.234934 1, 0xFFFF, sum = 0
5873 01:18:47.235017 2, 0xFFFF, sum = 0
5874 01:18:47.238210 3, 0xFFFF, sum = 0
5875 01:18:47.238357 4, 0xFFFF, sum = 0
5876 01:18:47.241564 5, 0xFFFF, sum = 0
5877 01:18:47.241647 6, 0xFFFF, sum = 0
5878 01:18:47.244941 7, 0xFFFF, sum = 0
5879 01:18:47.245024 8, 0xFFFF, sum = 0
5880 01:18:47.248123 9, 0xFFFF, sum = 0
5881 01:18:47.248236 10, 0x0, sum = 1
5882 01:18:47.251389 11, 0x0, sum = 2
5883 01:18:47.251472 12, 0x0, sum = 3
5884 01:18:47.254436 13, 0x0, sum = 4
5885 01:18:47.254518 best_step = 11
5886 01:18:47.254582
5887 01:18:47.254641 ==
5888 01:18:47.257758 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 01:18:47.261005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 01:18:47.264135 ==
5891 01:18:47.264247 RX Vref Scan: 0
5892 01:18:47.264331
5893 01:18:47.267941 RX Vref 0 -> 0, step: 1
5894 01:18:47.268023
5895 01:18:47.270962 RX Delay -45 -> 252, step: 4
5896 01:18:47.274294 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5897 01:18:47.277982 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5898 01:18:47.284230 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5899 01:18:47.287286 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5900 01:18:47.290543 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5901 01:18:47.294210 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5902 01:18:47.297157 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5903 01:18:47.300947 iDelay=203, Bit 7, Center 100 (15 ~ 186) 172
5904 01:18:47.307350 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5905 01:18:47.310488 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5906 01:18:47.313903 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5907 01:18:47.317135 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5908 01:18:47.320918 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5909 01:18:47.327709 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5910 01:18:47.330800 iDelay=203, Bit 14, Center 108 (27 ~ 190) 164
5911 01:18:47.333571 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5912 01:18:47.333659 ==
5913 01:18:47.337452 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 01:18:47.340650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 01:18:47.343929 ==
5916 01:18:47.344038 DQS Delay:
5917 01:18:47.344136 DQS0 = 0, DQS1 = 0
5918 01:18:47.347204 DQM Delay:
5919 01:18:47.347286 DQM0 = 103, DQM1 = 101
5920 01:18:47.350538 DQ Delay:
5921 01:18:47.353793 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =98
5922 01:18:47.356531 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =100
5923 01:18:47.360285 DQ8 =92, DQ9 =88, DQ10 =100, DQ11 =94
5924 01:18:47.363535 DQ12 =108, DQ13 =108, DQ14 =108, DQ15 =110
5925 01:18:47.363618
5926 01:18:47.363682
5927 01:18:47.369906 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5928 01:18:47.373511 CH1 RK1: MR19=505, MR18=2E01
5929 01:18:47.380202 CH1_RK1: MR19=0x505, MR18=0x2E01, DQSOSC=407, MR23=63, INC=65, DEC=43
5930 01:18:47.383357 [RxdqsGatingPostProcess] freq 933
5931 01:18:47.389931 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5932 01:18:47.393334 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 01:18:47.396440 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 01:18:47.399957 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 01:18:47.400041 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 01:18:47.403004 best DQS0 dly(2T, 0.5T) = (0, 10)
5937 01:18:47.406234 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 01:18:47.409803 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5939 01:18:47.412679 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 01:18:47.415993 Pre-setting of DQS Precalculation
5941 01:18:47.422924 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5942 01:18:47.429453 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5943 01:18:47.436216 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5944 01:18:47.436347
5945 01:18:47.436480
5946 01:18:47.439658 [Calibration Summary] 1866 Mbps
5947 01:18:47.439742 CH 0, Rank 0
5948 01:18:47.442795 SW Impedance : PASS
5949 01:18:47.446105 DUTY Scan : NO K
5950 01:18:47.446188 ZQ Calibration : PASS
5951 01:18:47.449354 Jitter Meter : NO K
5952 01:18:47.452743 CBT Training : PASS
5953 01:18:47.452838 Write leveling : PASS
5954 01:18:47.456163 RX DQS gating : PASS
5955 01:18:47.459405 RX DQ/DQS(RDDQC) : PASS
5956 01:18:47.459491 TX DQ/DQS : PASS
5957 01:18:47.462515 RX DATLAT : PASS
5958 01:18:47.462596 RX DQ/DQS(Engine): PASS
5959 01:18:47.465835 TX OE : NO K
5960 01:18:47.465916 All Pass.
5961 01:18:47.465980
5962 01:18:47.469143 CH 0, Rank 1
5963 01:18:47.469225 SW Impedance : PASS
5964 01:18:47.472474 DUTY Scan : NO K
5965 01:18:47.476293 ZQ Calibration : PASS
5966 01:18:47.476376 Jitter Meter : NO K
5967 01:18:47.479463 CBT Training : PASS
5968 01:18:47.482951 Write leveling : PASS
5969 01:18:47.483034 RX DQS gating : PASS
5970 01:18:47.485879 RX DQ/DQS(RDDQC) : PASS
5971 01:18:47.489383 TX DQ/DQS : PASS
5972 01:18:47.489466 RX DATLAT : PASS
5973 01:18:47.492426 RX DQ/DQS(Engine): PASS
5974 01:18:47.495668 TX OE : NO K
5975 01:18:47.495751 All Pass.
5976 01:18:47.495816
5977 01:18:47.495876 CH 1, Rank 0
5978 01:18:47.499507 SW Impedance : PASS
5979 01:18:47.502538 DUTY Scan : NO K
5980 01:18:47.502621 ZQ Calibration : PASS
5981 01:18:47.505738 Jitter Meter : NO K
5982 01:18:47.509189 CBT Training : PASS
5983 01:18:47.509274 Write leveling : PASS
5984 01:18:47.512290 RX DQS gating : PASS
5985 01:18:47.516050 RX DQ/DQS(RDDQC) : PASS
5986 01:18:47.516135 TX DQ/DQS : PASS
5987 01:18:47.519282 RX DATLAT : PASS
5988 01:18:47.519365 RX DQ/DQS(Engine): PASS
5989 01:18:47.522546 TX OE : NO K
5990 01:18:47.522628 All Pass.
5991 01:18:47.522692
5992 01:18:47.525678 CH 1, Rank 1
5993 01:18:47.525759 SW Impedance : PASS
5994 01:18:47.529438 DUTY Scan : NO K
5995 01:18:47.532597 ZQ Calibration : PASS
5996 01:18:47.532680 Jitter Meter : NO K
5997 01:18:47.535621 CBT Training : PASS
5998 01:18:47.539246 Write leveling : PASS
5999 01:18:47.539329 RX DQS gating : PASS
6000 01:18:47.542130 RX DQ/DQS(RDDQC) : PASS
6001 01:18:47.545506 TX DQ/DQS : PASS
6002 01:18:47.545591 RX DATLAT : PASS
6003 01:18:47.548715 RX DQ/DQS(Engine): PASS
6004 01:18:47.552104 TX OE : NO K
6005 01:18:47.552189 All Pass.
6006 01:18:47.552254
6007 01:18:47.555524 DramC Write-DBI off
6008 01:18:47.555607 PER_BANK_REFRESH: Hybrid Mode
6009 01:18:47.559236 TX_TRACKING: ON
6010 01:18:47.565959 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6011 01:18:47.568943 [FAST_K] Save calibration result to emmc
6012 01:18:47.575942 dramc_set_vcore_voltage set vcore to 650000
6013 01:18:47.576035 Read voltage for 400, 6
6014 01:18:47.579216 Vio18 = 0
6015 01:18:47.579297 Vcore = 650000
6016 01:18:47.579362 Vdram = 0
6017 01:18:47.582601 Vddq = 0
6018 01:18:47.582683 Vmddr = 0
6019 01:18:47.585770 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6020 01:18:47.592259 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6021 01:18:47.595824 MEM_TYPE=3, freq_sel=20
6022 01:18:47.595907 sv_algorithm_assistance_LP4_800
6023 01:18:47.602506 ============ PULL DRAM RESETB DOWN ============
6024 01:18:47.605423 ========== PULL DRAM RESETB DOWN end =========
6025 01:18:47.609064 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6026 01:18:47.612288 ===================================
6027 01:18:47.615590 LPDDR4 DRAM CONFIGURATION
6028 01:18:47.618714 ===================================
6029 01:18:47.622004 EX_ROW_EN[0] = 0x0
6030 01:18:47.622086 EX_ROW_EN[1] = 0x0
6031 01:18:47.625343 LP4Y_EN = 0x0
6032 01:18:47.625426 WORK_FSP = 0x0
6033 01:18:47.628608 WL = 0x2
6034 01:18:47.628689 RL = 0x2
6035 01:18:47.631934 BL = 0x2
6036 01:18:47.632015 RPST = 0x0
6037 01:18:47.635181 RD_PRE = 0x0
6038 01:18:47.635262 WR_PRE = 0x1
6039 01:18:47.638662 WR_PST = 0x0
6040 01:18:47.638744 DBI_WR = 0x0
6041 01:18:47.642175 DBI_RD = 0x0
6042 01:18:47.645449 OTF = 0x1
6043 01:18:47.648911 ===================================
6044 01:18:47.648993 ===================================
6045 01:18:47.652103 ANA top config
6046 01:18:47.655259 ===================================
6047 01:18:47.658519 DLL_ASYNC_EN = 0
6048 01:18:47.658614 ALL_SLAVE_EN = 1
6049 01:18:47.661804 NEW_RANK_MODE = 1
6050 01:18:47.665459 DLL_IDLE_MODE = 1
6051 01:18:47.668428 LP45_APHY_COMB_EN = 1
6052 01:18:47.671879 TX_ODT_DIS = 1
6053 01:18:47.671963 NEW_8X_MODE = 1
6054 01:18:47.675356 ===================================
6055 01:18:47.678541 ===================================
6056 01:18:47.681687 data_rate = 800
6057 01:18:47.685071 CKR = 1
6058 01:18:47.688402 DQ_P2S_RATIO = 4
6059 01:18:47.691639 ===================================
6060 01:18:47.695021 CA_P2S_RATIO = 4
6061 01:18:47.698784 DQ_CA_OPEN = 0
6062 01:18:47.698867 DQ_SEMI_OPEN = 1
6063 01:18:47.701908 CA_SEMI_OPEN = 1
6064 01:18:47.704833 CA_FULL_RATE = 0
6065 01:18:47.708613 DQ_CKDIV4_EN = 0
6066 01:18:47.711511 CA_CKDIV4_EN = 1
6067 01:18:47.714972 CA_PREDIV_EN = 0
6068 01:18:47.715058 PH8_DLY = 0
6069 01:18:47.718261 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6070 01:18:47.721867 DQ_AAMCK_DIV = 0
6071 01:18:47.724928 CA_AAMCK_DIV = 0
6072 01:18:47.728141 CA_ADMCK_DIV = 4
6073 01:18:47.731416 DQ_TRACK_CA_EN = 0
6074 01:18:47.731501 CA_PICK = 800
6075 01:18:47.735459 CA_MCKIO = 400
6076 01:18:47.738106 MCKIO_SEMI = 400
6077 01:18:47.741354 PLL_FREQ = 3016
6078 01:18:47.744684 DQ_UI_PI_RATIO = 32
6079 01:18:47.748525 CA_UI_PI_RATIO = 32
6080 01:18:47.751191 ===================================
6081 01:18:47.755184 ===================================
6082 01:18:47.758449 memory_type:LPDDR4
6083 01:18:47.758533 GP_NUM : 10
6084 01:18:47.761863 SRAM_EN : 1
6085 01:18:47.761945 MD32_EN : 0
6086 01:18:47.764986 ===================================
6087 01:18:47.768290 [ANA_INIT] >>>>>>>>>>>>>>
6088 01:18:47.771459 <<<<<< [CONFIGURE PHASE]: ANA_TX
6089 01:18:47.774672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6090 01:18:47.777840 ===================================
6091 01:18:47.781725 data_rate = 800,PCW = 0X7400
6092 01:18:47.784922 ===================================
6093 01:18:47.787589 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6094 01:18:47.794463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 01:18:47.803965 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 01:18:47.807526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6097 01:18:47.810867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6098 01:18:47.814182 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6099 01:18:47.817010 [ANA_INIT] flow start
6100 01:18:47.820348 [ANA_INIT] PLL >>>>>>>>
6101 01:18:47.823629 [ANA_INIT] PLL <<<<<<<<
6102 01:18:47.823712 [ANA_INIT] MIDPI >>>>>>>>
6103 01:18:47.826929 [ANA_INIT] MIDPI <<<<<<<<
6104 01:18:47.830538 [ANA_INIT] DLL >>>>>>>>
6105 01:18:47.830620 [ANA_INIT] flow end
6106 01:18:47.833498 ============ LP4 DIFF to SE enter ============
6107 01:18:47.840289 ============ LP4 DIFF to SE exit ============
6108 01:18:47.840380 [ANA_INIT] <<<<<<<<<<<<<
6109 01:18:47.843477 [Flow] Enable top DCM control >>>>>
6110 01:18:47.846780 [Flow] Enable top DCM control <<<<<
6111 01:18:47.850242 Enable DLL master slave shuffle
6112 01:18:47.857232 ==============================================================
6113 01:18:47.857346 Gating Mode config
6114 01:18:47.863874 ==============================================================
6115 01:18:47.867002 Config description:
6116 01:18:47.876801 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6117 01:18:47.883883 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6118 01:18:47.887253 SELPH_MODE 0: By rank 1: By Phase
6119 01:18:47.893696 ==============================================================
6120 01:18:47.896981 GAT_TRACK_EN = 0
6121 01:18:47.900233 RX_GATING_MODE = 2
6122 01:18:47.900320 RX_GATING_TRACK_MODE = 2
6123 01:18:47.903291 SELPH_MODE = 1
6124 01:18:47.906457 PICG_EARLY_EN = 1
6125 01:18:47.910262 VALID_LAT_VALUE = 1
6126 01:18:47.917042 ==============================================================
6127 01:18:47.920391 Enter into Gating configuration >>>>
6128 01:18:47.922945 Exit from Gating configuration <<<<
6129 01:18:47.926638 Enter into DVFS_PRE_config >>>>>
6130 01:18:47.936470 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6131 01:18:47.939926 Exit from DVFS_PRE_config <<<<<
6132 01:18:47.942960 Enter into PICG configuration >>>>
6133 01:18:47.946601 Exit from PICG configuration <<<<
6134 01:18:47.949711 [RX_INPUT] configuration >>>>>
6135 01:18:47.952844 [RX_INPUT] configuration <<<<<
6136 01:18:47.956626 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6137 01:18:47.963015 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6138 01:18:47.970193 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 01:18:47.976192 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 01:18:47.979984 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 01:18:47.986674 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 01:18:47.989837 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6143 01:18:47.996414 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6144 01:18:47.999735 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6145 01:18:48.003174 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6146 01:18:48.006216 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6147 01:18:48.013159 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 01:18:48.016359 ===================================
6149 01:18:48.016449 LPDDR4 DRAM CONFIGURATION
6150 01:18:48.019698 ===================================
6151 01:18:48.022911 EX_ROW_EN[0] = 0x0
6152 01:18:48.026231 EX_ROW_EN[1] = 0x0
6153 01:18:48.026336 LP4Y_EN = 0x0
6154 01:18:48.029625 WORK_FSP = 0x0
6155 01:18:48.029709 WL = 0x2
6156 01:18:48.032861 RL = 0x2
6157 01:18:48.032945 BL = 0x2
6158 01:18:48.036529 RPST = 0x0
6159 01:18:48.036612 RD_PRE = 0x0
6160 01:18:48.039423 WR_PRE = 0x1
6161 01:18:48.039507 WR_PST = 0x0
6162 01:18:48.042839 DBI_WR = 0x0
6163 01:18:48.042923 DBI_RD = 0x0
6164 01:18:48.046007 OTF = 0x1
6165 01:18:48.049887 ===================================
6166 01:18:48.053042 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6167 01:18:48.055934 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6168 01:18:48.062857 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6169 01:18:48.066289 ===================================
6170 01:18:48.066399 LPDDR4 DRAM CONFIGURATION
6171 01:18:48.069316 ===================================
6172 01:18:48.072895 EX_ROW_EN[0] = 0x10
6173 01:18:48.076451 EX_ROW_EN[1] = 0x0
6174 01:18:48.076534 LP4Y_EN = 0x0
6175 01:18:48.079444 WORK_FSP = 0x0
6176 01:18:48.079528 WL = 0x2
6177 01:18:48.082902 RL = 0x2
6178 01:18:48.082984 BL = 0x2
6179 01:18:48.086355 RPST = 0x0
6180 01:18:48.086438 RD_PRE = 0x0
6181 01:18:48.089451 WR_PRE = 0x1
6182 01:18:48.089532 WR_PST = 0x0
6183 01:18:48.092647 DBI_WR = 0x0
6184 01:18:48.092729 DBI_RD = 0x0
6185 01:18:48.096155 OTF = 0x1
6186 01:18:48.099085 ===================================
6187 01:18:48.106066 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6188 01:18:48.109192 nWR fixed to 30
6189 01:18:48.109277 [ModeRegInit_LP4] CH0 RK0
6190 01:18:48.112871 [ModeRegInit_LP4] CH0 RK1
6191 01:18:48.115965 [ModeRegInit_LP4] CH1 RK0
6192 01:18:48.119279 [ModeRegInit_LP4] CH1 RK1
6193 01:18:48.119361 match AC timing 19
6194 01:18:48.125779 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6195 01:18:48.128981 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6196 01:18:48.132275 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6197 01:18:48.138757 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6198 01:18:48.142630 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6199 01:18:48.142744 ==
6200 01:18:48.145638 Dram Type= 6, Freq= 0, CH_0, rank 0
6201 01:18:48.149026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6202 01:18:48.149111 ==
6203 01:18:48.155462 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6204 01:18:48.162199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6205 01:18:48.165683 [CA 0] Center 36 (8~64) winsize 57
6206 01:18:48.165769 [CA 1] Center 36 (8~64) winsize 57
6207 01:18:48.168837 [CA 2] Center 36 (8~64) winsize 57
6208 01:18:48.172178 [CA 3] Center 36 (8~64) winsize 57
6209 01:18:48.175387 [CA 4] Center 36 (8~64) winsize 57
6210 01:18:48.179179 [CA 5] Center 36 (8~64) winsize 57
6211 01:18:48.179267
6212 01:18:48.182398 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6213 01:18:48.182480
6214 01:18:48.188611 [CATrainingPosCal] consider 1 rank data
6215 01:18:48.188707 u2DelayCellTimex100 = 270/100 ps
6216 01:18:48.195645 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 01:18:48.198907 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 01:18:48.202099 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 01:18:48.205256 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 01:18:48.209058 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 01:18:48.212261 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 01:18:48.212344
6223 01:18:48.215278 CA PerBit enable=1, Macro0, CA PI delay=36
6224 01:18:48.215410
6225 01:18:48.218621 [CBTSetCACLKResult] CA Dly = 36
6226 01:18:48.218702 CS Dly: 1 (0~32)
6227 01:18:48.222621 ==
6228 01:18:48.225420 Dram Type= 6, Freq= 0, CH_0, rank 1
6229 01:18:48.228501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6230 01:18:48.228583 ==
6231 01:18:48.231929 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6232 01:18:48.238609 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6233 01:18:48.241922 [CA 0] Center 36 (8~64) winsize 57
6234 01:18:48.245197 [CA 1] Center 36 (8~64) winsize 57
6235 01:18:48.248274 [CA 2] Center 36 (8~64) winsize 57
6236 01:18:48.251832 [CA 3] Center 36 (8~64) winsize 57
6237 01:18:48.255092 [CA 4] Center 36 (8~64) winsize 57
6238 01:18:48.258590 [CA 5] Center 36 (8~64) winsize 57
6239 01:18:48.258676
6240 01:18:48.261759 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6241 01:18:48.261841
6242 01:18:48.264962 [CATrainingPosCal] consider 2 rank data
6243 01:18:48.268162 u2DelayCellTimex100 = 270/100 ps
6244 01:18:48.271570 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 01:18:48.275152 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 01:18:48.278179 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 01:18:48.281822 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 01:18:48.288373 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 01:18:48.291634 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 01:18:48.291716
6251 01:18:48.295122 CA PerBit enable=1, Macro0, CA PI delay=36
6252 01:18:48.295204
6253 01:18:48.298564 [CBTSetCACLKResult] CA Dly = 36
6254 01:18:48.298645 CS Dly: 1 (0~32)
6255 01:18:48.298709
6256 01:18:48.301518 ----->DramcWriteLeveling(PI) begin...
6257 01:18:48.301638 ==
6258 01:18:48.304607 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 01:18:48.311661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 01:18:48.311751 ==
6261 01:18:48.314458 Write leveling (Byte 0): 40 => 8
6262 01:18:48.318216 Write leveling (Byte 1): 40 => 8
6263 01:18:48.318366 DramcWriteLeveling(PI) end<-----
6264 01:18:48.318450
6265 01:18:48.321482 ==
6266 01:18:48.324609 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 01:18:48.327820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 01:18:48.327904 ==
6269 01:18:48.331509 [Gating] SW mode calibration
6270 01:18:48.338184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6271 01:18:48.341703 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6272 01:18:48.348076 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 01:18:48.350972 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 01:18:48.354282 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 01:18:48.361320 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 01:18:48.364194 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 01:18:48.367702 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 01:18:48.374107 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 01:18:48.377736 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 01:18:48.380811 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 01:18:48.384463 Total UI for P1: 0, mck2ui 16
6282 01:18:48.388034 best dqsien dly found for B0: ( 0, 14, 24)
6283 01:18:48.391137 Total UI for P1: 0, mck2ui 16
6284 01:18:48.394598 best dqsien dly found for B1: ( 0, 14, 24)
6285 01:18:48.397517 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6286 01:18:48.400653 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6287 01:18:48.400735
6288 01:18:48.407734 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 01:18:48.410780 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 01:18:48.410863 [Gating] SW calibration Done
6291 01:18:48.414529 ==
6292 01:18:48.417826 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 01:18:48.421130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 01:18:48.421217 ==
6295 01:18:48.421282 RX Vref Scan: 0
6296 01:18:48.421342
6297 01:18:48.424344 RX Vref 0 -> 0, step: 1
6298 01:18:48.424425
6299 01:18:48.427515 RX Delay -410 -> 252, step: 16
6300 01:18:48.430926 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6301 01:18:48.437477 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6302 01:18:48.440634 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6303 01:18:48.443906 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6304 01:18:48.447147 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6305 01:18:48.451014 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6306 01:18:48.457329 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6307 01:18:48.460723 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6308 01:18:48.464272 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6309 01:18:48.467353 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6310 01:18:48.473875 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6311 01:18:48.477118 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6312 01:18:48.480699 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6313 01:18:48.487171 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6314 01:18:48.490220 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6315 01:18:48.493836 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6316 01:18:48.493918 ==
6317 01:18:48.497315 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 01:18:48.500187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 01:18:48.503641 ==
6320 01:18:48.503722 DQS Delay:
6321 01:18:48.503786 DQS0 = 27, DQS1 = 35
6322 01:18:48.506900 DQM Delay:
6323 01:18:48.506979 DQM0 = 9, DQM1 = 11
6324 01:18:48.510248 DQ Delay:
6325 01:18:48.510379 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6326 01:18:48.513377 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6327 01:18:48.517136 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6328 01:18:48.520839 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6329 01:18:48.520923
6330 01:18:48.520987
6331 01:18:48.521045 ==
6332 01:18:48.523771 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 01:18:48.530486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 01:18:48.530593 ==
6335 01:18:48.530658
6336 01:18:48.530716
6337 01:18:48.530772 TX Vref Scan disable
6338 01:18:48.533685 == TX Byte 0 ==
6339 01:18:48.537085 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 01:18:48.540224 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 01:18:48.543492 == TX Byte 1 ==
6342 01:18:48.547191 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 01:18:48.549890 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 01:18:48.553579 ==
6345 01:18:48.556733 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 01:18:48.560036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 01:18:48.560120 ==
6348 01:18:48.560183
6349 01:18:48.560241
6350 01:18:48.563283 TX Vref Scan disable
6351 01:18:48.563363 == TX Byte 0 ==
6352 01:18:48.566923 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 01:18:48.573268 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 01:18:48.573363 == TX Byte 1 ==
6355 01:18:48.576463 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 01:18:48.582904 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 01:18:48.582995
6358 01:18:48.583060 [DATLAT]
6359 01:18:48.583119 Freq=400, CH0 RK0
6360 01:18:48.583177
6361 01:18:48.586637 DATLAT Default: 0xf
6362 01:18:48.586721 0, 0xFFFF, sum = 0
6363 01:18:48.589883 1, 0xFFFF, sum = 0
6364 01:18:48.590006 2, 0xFFFF, sum = 0
6365 01:18:48.593290 3, 0xFFFF, sum = 0
6366 01:18:48.596363 4, 0xFFFF, sum = 0
6367 01:18:48.596450 5, 0xFFFF, sum = 0
6368 01:18:48.599604 6, 0xFFFF, sum = 0
6369 01:18:48.599688 7, 0xFFFF, sum = 0
6370 01:18:48.603161 8, 0xFFFF, sum = 0
6371 01:18:48.603271 9, 0xFFFF, sum = 0
6372 01:18:48.606048 10, 0xFFFF, sum = 0
6373 01:18:48.606130 11, 0xFFFF, sum = 0
6374 01:18:48.609488 12, 0xFFFF, sum = 0
6375 01:18:48.609576 13, 0x0, sum = 1
6376 01:18:48.612853 14, 0x0, sum = 2
6377 01:18:48.612939 15, 0x0, sum = 3
6378 01:18:48.616128 16, 0x0, sum = 4
6379 01:18:48.616215 best_step = 14
6380 01:18:48.616278
6381 01:18:48.616336 ==
6382 01:18:48.619331 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 01:18:48.622566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 01:18:48.626498 ==
6385 01:18:48.626583 RX Vref Scan: 1
6386 01:18:48.626645
6387 01:18:48.629649 RX Vref 0 -> 0, step: 1
6388 01:18:48.629729
6389 01:18:48.632643 RX Delay -311 -> 252, step: 8
6390 01:18:48.632728
6391 01:18:48.635897 Set Vref, RX VrefLevel [Byte0]: 54
6392 01:18:48.639161 [Byte1]: 46
6393 01:18:48.639248
6394 01:18:48.642434 Final RX Vref Byte 0 = 54 to rank0
6395 01:18:48.646437 Final RX Vref Byte 1 = 46 to rank0
6396 01:18:48.649548 Final RX Vref Byte 0 = 54 to rank1
6397 01:18:48.652797 Final RX Vref Byte 1 = 46 to rank1==
6398 01:18:48.655882 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 01:18:48.659632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 01:18:48.659717 ==
6401 01:18:48.663021 DQS Delay:
6402 01:18:48.663103 DQS0 = 28, DQS1 = 36
6403 01:18:48.666194 DQM Delay:
6404 01:18:48.666307 DQM0 = 11, DQM1 = 13
6405 01:18:48.666376 DQ Delay:
6406 01:18:48.669415 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6407 01:18:48.672495 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6408 01:18:48.675554 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6409 01:18:48.679204 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6410 01:18:48.679287
6411 01:18:48.679350
6412 01:18:48.689256 [DQSOSCAuto] RK0, (LSB)MR18= 0xccba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6413 01:18:48.692431 CH0 RK0: MR19=C0C, MR18=CCBA
6414 01:18:48.695744 CH0_RK0: MR19=0xC0C, MR18=0xCCBA, DQSOSC=384, MR23=63, INC=400, DEC=267
6415 01:18:48.698947 ==
6416 01:18:48.699030 Dram Type= 6, Freq= 0, CH_0, rank 1
6417 01:18:48.706097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 01:18:48.706182 ==
6419 01:18:48.709268 [Gating] SW mode calibration
6420 01:18:48.715500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6421 01:18:48.719102 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6422 01:18:48.725534 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 01:18:48.728886 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 01:18:48.732126 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 01:18:48.738956 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 01:18:48.742224 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 01:18:48.745588 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 01:18:48.752392 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 01:18:48.755786 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 01:18:48.758852 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 01:18:48.762053 Total UI for P1: 0, mck2ui 16
6432 01:18:48.765234 best dqsien dly found for B0: ( 0, 14, 24)
6433 01:18:48.768554 Total UI for P1: 0, mck2ui 16
6434 01:18:48.771812 best dqsien dly found for B1: ( 0, 14, 24)
6435 01:18:48.775063 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6436 01:18:48.778273 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6437 01:18:48.778392
6438 01:18:48.784913 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 01:18:48.788720 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 01:18:48.788806 [Gating] SW calibration Done
6441 01:18:48.792206 ==
6442 01:18:48.795248 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 01:18:48.798549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 01:18:48.798633 ==
6445 01:18:48.798698 RX Vref Scan: 0
6446 01:18:48.798760
6447 01:18:48.801772 RX Vref 0 -> 0, step: 1
6448 01:18:48.801854
6449 01:18:48.805127 RX Delay -410 -> 252, step: 16
6450 01:18:48.808122 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6451 01:18:48.812053 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6452 01:18:48.818165 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6453 01:18:48.821423 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6454 01:18:48.824885 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6455 01:18:48.828144 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6456 01:18:48.835067 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6457 01:18:48.838216 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6458 01:18:48.841854 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6459 01:18:48.844720 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6460 01:18:48.851349 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6461 01:18:48.855068 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6462 01:18:48.858239 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6463 01:18:48.861613 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6464 01:18:48.868132 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6465 01:18:48.871461 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6466 01:18:48.871546 ==
6467 01:18:48.874492 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 01:18:48.878219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 01:18:48.878306 ==
6470 01:18:48.881110 DQS Delay:
6471 01:18:48.881192 DQS0 = 27, DQS1 = 35
6472 01:18:48.884397 DQM Delay:
6473 01:18:48.884478 DQM0 = 12, DQM1 = 12
6474 01:18:48.887645 DQ Delay:
6475 01:18:48.887727 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6476 01:18:48.891480 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6477 01:18:48.894665 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6478 01:18:48.897727 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6479 01:18:48.897809
6480 01:18:48.897872
6481 01:18:48.897931 ==
6482 01:18:48.900941 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 01:18:48.907586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 01:18:48.907669 ==
6485 01:18:48.907733
6486 01:18:48.907792
6487 01:18:48.907850 TX Vref Scan disable
6488 01:18:48.910810 == TX Byte 0 ==
6489 01:18:48.914607 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6490 01:18:48.917776 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6491 01:18:48.920969 == TX Byte 1 ==
6492 01:18:48.924123 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6493 01:18:48.927961 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6494 01:18:48.928043 ==
6495 01:18:48.931235 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 01:18:48.937667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 01:18:48.937753 ==
6498 01:18:48.937817
6499 01:18:48.937877
6500 01:18:48.937936 TX Vref Scan disable
6501 01:18:48.940968 == TX Byte 0 ==
6502 01:18:48.944199 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6503 01:18:48.947449 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6504 01:18:48.951088 == TX Byte 1 ==
6505 01:18:48.954212 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6506 01:18:48.957455 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6507 01:18:48.957536
6508 01:18:48.960684 [DATLAT]
6509 01:18:48.960766 Freq=400, CH0 RK1
6510 01:18:48.960831
6511 01:18:48.964047 DATLAT Default: 0xe
6512 01:18:48.964132 0, 0xFFFF, sum = 0
6513 01:18:48.967698 1, 0xFFFF, sum = 0
6514 01:18:48.967787 2, 0xFFFF, sum = 0
6515 01:18:48.970867 3, 0xFFFF, sum = 0
6516 01:18:48.970951 4, 0xFFFF, sum = 0
6517 01:18:48.973989 5, 0xFFFF, sum = 0
6518 01:18:48.974073 6, 0xFFFF, sum = 0
6519 01:18:48.977278 7, 0xFFFF, sum = 0
6520 01:18:48.977365 8, 0xFFFF, sum = 0
6521 01:18:48.980685 9, 0xFFFF, sum = 0
6522 01:18:48.984106 10, 0xFFFF, sum = 0
6523 01:18:48.984194 11, 0xFFFF, sum = 0
6524 01:18:48.987290 12, 0xFFFF, sum = 0
6525 01:18:48.987376 13, 0x0, sum = 1
6526 01:18:48.990590 14, 0x0, sum = 2
6527 01:18:48.990677 15, 0x0, sum = 3
6528 01:18:48.993972 16, 0x0, sum = 4
6529 01:18:48.994056 best_step = 14
6530 01:18:48.994119
6531 01:18:48.994178 ==
6532 01:18:48.997313 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 01:18:49.000540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 01:18:49.000626 ==
6535 01:18:49.003787 RX Vref Scan: 0
6536 01:18:49.003870
6537 01:18:49.007369 RX Vref 0 -> 0, step: 1
6538 01:18:49.007451
6539 01:18:49.007514 RX Delay -311 -> 252, step: 8
6540 01:18:49.015907 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6541 01:18:49.019034 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6542 01:18:49.022093 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6543 01:18:49.029184 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6544 01:18:49.032346 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6545 01:18:49.035632 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6546 01:18:49.038847 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6547 01:18:49.042142 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6548 01:18:49.048678 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6549 01:18:49.052496 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6550 01:18:49.055506 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432
6551 01:18:49.062502 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6552 01:18:49.065641 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6553 01:18:49.068957 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6554 01:18:49.072438 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6555 01:18:49.078952 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6556 01:18:49.079035 ==
6557 01:18:49.082219 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 01:18:49.085423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 01:18:49.085510 ==
6560 01:18:49.085594 DQS Delay:
6561 01:18:49.088707 DQS0 = 24, DQS1 = 36
6562 01:18:49.088793 DQM Delay:
6563 01:18:49.091904 DQM0 = 8, DQM1 = 13
6564 01:18:49.091988 DQ Delay:
6565 01:18:49.095138 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6566 01:18:49.098371 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6567 01:18:49.102232 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6568 01:18:49.104960 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6569 01:18:49.105045
6570 01:18:49.105129
6571 01:18:49.111919 [DQSOSCAuto] RK1, (LSB)MR18= 0xb655, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6572 01:18:49.114949 CH0 RK1: MR19=C0C, MR18=B655
6573 01:18:49.121749 CH0_RK1: MR19=0xC0C, MR18=0xB655, DQSOSC=387, MR23=63, INC=394, DEC=262
6574 01:18:49.124847 [RxdqsGatingPostProcess] freq 400
6575 01:18:49.131471 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6576 01:18:49.135212 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 01:18:49.135297 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 01:18:49.138514 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 01:18:49.141879 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 01:18:49.145041 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 01:18:49.148426 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 01:18:49.151745 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 01:18:49.154926 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 01:18:49.158207 Pre-setting of DQS Precalculation
6585 01:18:49.165099 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6586 01:18:49.165183 ==
6587 01:18:49.168193 Dram Type= 6, Freq= 0, CH_1, rank 0
6588 01:18:49.171575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 01:18:49.171657 ==
6590 01:18:49.178732 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6591 01:18:49.182182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6592 01:18:49.185223 [CA 0] Center 36 (8~64) winsize 57
6593 01:18:49.188401 [CA 1] Center 36 (8~64) winsize 57
6594 01:18:49.191698 [CA 2] Center 36 (8~64) winsize 57
6595 01:18:49.194987 [CA 3] Center 36 (8~64) winsize 57
6596 01:18:49.198256 [CA 4] Center 36 (8~64) winsize 57
6597 01:18:49.201490 [CA 5] Center 36 (8~64) winsize 57
6598 01:18:49.201572
6599 01:18:49.204770 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6600 01:18:49.204852
6601 01:18:49.208007 [CATrainingPosCal] consider 1 rank data
6602 01:18:49.211153 u2DelayCellTimex100 = 270/100 ps
6603 01:18:49.215164 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 01:18:49.218000 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 01:18:49.221164 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 01:18:49.228195 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 01:18:49.231429 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 01:18:49.234948 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 01:18:49.235029
6610 01:18:49.238220 CA PerBit enable=1, Macro0, CA PI delay=36
6611 01:18:49.238328
6612 01:18:49.241453 [CBTSetCACLKResult] CA Dly = 36
6613 01:18:49.241536 CS Dly: 1 (0~32)
6614 01:18:49.241600 ==
6615 01:18:49.244539 Dram Type= 6, Freq= 0, CH_1, rank 1
6616 01:18:49.251636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 01:18:49.251725 ==
6618 01:18:49.254566 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6619 01:18:49.261337 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6620 01:18:49.264746 [CA 0] Center 36 (8~64) winsize 57
6621 01:18:49.268125 [CA 1] Center 36 (8~64) winsize 57
6622 01:18:49.271545 [CA 2] Center 36 (8~64) winsize 57
6623 01:18:49.274536 [CA 3] Center 36 (8~64) winsize 57
6624 01:18:49.278154 [CA 4] Center 36 (8~64) winsize 57
6625 01:18:49.281265 [CA 5] Center 36 (8~64) winsize 57
6626 01:18:49.281347
6627 01:18:49.284688 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6628 01:18:49.284769
6629 01:18:49.287933 [CATrainingPosCal] consider 2 rank data
6630 01:18:49.291173 u2DelayCellTimex100 = 270/100 ps
6631 01:18:49.294416 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 01:18:49.297669 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 01:18:49.301019 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 01:18:49.304194 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 01:18:49.307534 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 01:18:49.310784 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 01:18:49.314091
6638 01:18:49.317866 CA PerBit enable=1, Macro0, CA PI delay=36
6639 01:18:49.317948
6640 01:18:49.320953 [CBTSetCACLKResult] CA Dly = 36
6641 01:18:49.321033 CS Dly: 1 (0~32)
6642 01:18:49.321097
6643 01:18:49.324254 ----->DramcWriteLeveling(PI) begin...
6644 01:18:49.324337 ==
6645 01:18:49.327345 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 01:18:49.330560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 01:18:49.334270 ==
6648 01:18:49.334360 Write leveling (Byte 0): 40 => 8
6649 01:18:49.337489 Write leveling (Byte 1): 40 => 8
6650 01:18:49.340817 DramcWriteLeveling(PI) end<-----
6651 01:18:49.340932
6652 01:18:49.340999 ==
6653 01:18:49.344399 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 01:18:49.350675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 01:18:49.350759 ==
6656 01:18:49.350823 [Gating] SW mode calibration
6657 01:18:49.360628 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6658 01:18:49.363768 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6659 01:18:49.367605 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 01:18:49.374203 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 01:18:49.377363 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 01:18:49.380524 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 01:18:49.387375 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 01:18:49.390268 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 01:18:49.393699 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 01:18:49.400884 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 01:18:49.404137 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 01:18:49.407218 Total UI for P1: 0, mck2ui 16
6669 01:18:49.410269 best dqsien dly found for B0: ( 0, 14, 24)
6670 01:18:49.414441 Total UI for P1: 0, mck2ui 16
6671 01:18:49.417652 best dqsien dly found for B1: ( 0, 14, 24)
6672 01:18:49.420281 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6673 01:18:49.423753 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6674 01:18:49.423836
6675 01:18:49.427055 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 01:18:49.430878 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 01:18:49.433801 [Gating] SW calibration Done
6678 01:18:49.433882 ==
6679 01:18:49.436801 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 01:18:49.443484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 01:18:49.443568 ==
6682 01:18:49.443632 RX Vref Scan: 0
6683 01:18:49.443693
6684 01:18:49.447381 RX Vref 0 -> 0, step: 1
6685 01:18:49.447464
6686 01:18:49.450268 RX Delay -410 -> 252, step: 16
6687 01:18:49.453847 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6688 01:18:49.457183 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6689 01:18:49.460156 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6690 01:18:49.466706 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6691 01:18:49.469943 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6692 01:18:49.473350 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6693 01:18:49.476976 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6694 01:18:49.483683 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6695 01:18:49.486978 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6696 01:18:49.489900 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6697 01:18:49.496250 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6698 01:18:49.499498 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6699 01:18:49.503208 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6700 01:18:49.506513 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6701 01:18:49.513018 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6702 01:18:49.516376 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6703 01:18:49.516460 ==
6704 01:18:49.519862 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 01:18:49.523023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 01:18:49.523106 ==
6707 01:18:49.526285 DQS Delay:
6708 01:18:49.526389 DQS0 = 35, DQS1 = 35
6709 01:18:49.526454 DQM Delay:
6710 01:18:49.529761 DQM0 = 17, DQM1 = 13
6711 01:18:49.529878 DQ Delay:
6712 01:18:49.532992 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6713 01:18:49.536664 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6714 01:18:49.539706 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6715 01:18:49.542762 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6716 01:18:49.542844
6717 01:18:49.542907
6718 01:18:49.542966 ==
6719 01:18:49.546119 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 01:18:49.549686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 01:18:49.552726 ==
6722 01:18:49.552807
6723 01:18:49.552871
6724 01:18:49.552930 TX Vref Scan disable
6725 01:18:49.556756 == TX Byte 0 ==
6726 01:18:49.559789 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 01:18:49.562750 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 01:18:49.566630 == TX Byte 1 ==
6729 01:18:49.569826 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 01:18:49.572814 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 01:18:49.572896 ==
6732 01:18:49.576713 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 01:18:49.583140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 01:18:49.583223 ==
6735 01:18:49.583287
6736 01:18:49.583345
6737 01:18:49.583401 TX Vref Scan disable
6738 01:18:49.586315 == TX Byte 0 ==
6739 01:18:49.589862 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 01:18:49.592956 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 01:18:49.596181 == TX Byte 1 ==
6742 01:18:49.599387 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 01:18:49.602986 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 01:18:49.603067
6745 01:18:49.606130 [DATLAT]
6746 01:18:49.606211 Freq=400, CH1 RK0
6747 01:18:49.606275
6748 01:18:49.609365 DATLAT Default: 0xf
6749 01:18:49.609446 0, 0xFFFF, sum = 0
6750 01:18:49.612635 1, 0xFFFF, sum = 0
6751 01:18:49.612718 2, 0xFFFF, sum = 0
6752 01:18:49.615902 3, 0xFFFF, sum = 0
6753 01:18:49.615985 4, 0xFFFF, sum = 0
6754 01:18:49.619178 5, 0xFFFF, sum = 0
6755 01:18:49.619261 6, 0xFFFF, sum = 0
6756 01:18:49.622682 7, 0xFFFF, sum = 0
6757 01:18:49.622765 8, 0xFFFF, sum = 0
6758 01:18:49.625749 9, 0xFFFF, sum = 0
6759 01:18:49.625831 10, 0xFFFF, sum = 0
6760 01:18:49.629405 11, 0xFFFF, sum = 0
6761 01:18:49.632471 12, 0xFFFF, sum = 0
6762 01:18:49.632554 13, 0x0, sum = 1
6763 01:18:49.635948 14, 0x0, sum = 2
6764 01:18:49.636030 15, 0x0, sum = 3
6765 01:18:49.636095 16, 0x0, sum = 4
6766 01:18:49.639271 best_step = 14
6767 01:18:49.639353
6768 01:18:49.639417 ==
6769 01:18:49.642105 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 01:18:49.645694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 01:18:49.645781 ==
6772 01:18:49.649119 RX Vref Scan: 1
6773 01:18:49.649201
6774 01:18:49.652559 RX Vref 0 -> 0, step: 1
6775 01:18:49.652641
6776 01:18:49.652705 RX Delay -311 -> 252, step: 8
6777 01:18:49.652765
6778 01:18:49.655660 Set Vref, RX VrefLevel [Byte0]: 53
6779 01:18:49.659022 [Byte1]: 53
6780 01:18:49.664263
6781 01:18:49.664343 Final RX Vref Byte 0 = 53 to rank0
6782 01:18:49.667287 Final RX Vref Byte 1 = 53 to rank0
6783 01:18:49.670776 Final RX Vref Byte 0 = 53 to rank1
6784 01:18:49.673949 Final RX Vref Byte 1 = 53 to rank1==
6785 01:18:49.677913 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 01:18:49.683874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 01:18:49.683957 ==
6788 01:18:49.684022 DQS Delay:
6789 01:18:49.687723 DQS0 = 32, DQS1 = 32
6790 01:18:49.687805 DQM Delay:
6791 01:18:49.687870 DQM0 = 13, DQM1 = 10
6792 01:18:49.690834 DQ Delay:
6793 01:18:49.694165 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6794 01:18:49.697484 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6795 01:18:49.697565 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6796 01:18:49.700651 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6797 01:18:49.703720
6798 01:18:49.703801
6799 01:18:49.710657 [DQSOSCAuto] RK0, (LSB)MR18= 0x88c1, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6800 01:18:49.713705 CH1 RK0: MR19=C0C, MR18=88C1
6801 01:18:49.720351 CH1_RK0: MR19=0xC0C, MR18=0x88C1, DQSOSC=385, MR23=63, INC=398, DEC=265
6802 01:18:49.720433 ==
6803 01:18:49.723642 Dram Type= 6, Freq= 0, CH_1, rank 1
6804 01:18:49.727391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 01:18:49.727474 ==
6806 01:18:49.730444 [Gating] SW mode calibration
6807 01:18:49.737061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6808 01:18:49.743886 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6809 01:18:49.746847 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6810 01:18:49.750278 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 01:18:49.753622 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 01:18:49.760585 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 01:18:49.763920 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 01:18:49.767097 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 01:18:49.773538 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 01:18:49.777345 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 01:18:49.780326 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 01:18:49.783502 Total UI for P1: 0, mck2ui 16
6819 01:18:49.787250 best dqsien dly found for B0: ( 0, 14, 24)
6820 01:18:49.790269 Total UI for P1: 0, mck2ui 16
6821 01:18:49.793307 best dqsien dly found for B1: ( 0, 14, 24)
6822 01:18:49.797024 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6823 01:18:49.803677 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6824 01:18:49.803759
6825 01:18:49.806851 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 01:18:49.809998 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 01:18:49.813826 [Gating] SW calibration Done
6828 01:18:49.813907 ==
6829 01:18:49.816917 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 01:18:49.820261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 01:18:49.820343 ==
6832 01:18:49.820408 RX Vref Scan: 0
6833 01:18:49.823419
6834 01:18:49.823500 RX Vref 0 -> 0, step: 1
6835 01:18:49.823563
6836 01:18:49.826756 RX Delay -410 -> 252, step: 16
6837 01:18:49.829963 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6838 01:18:49.836636 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6839 01:18:49.840299 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6840 01:18:49.843295 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6841 01:18:49.846928 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6842 01:18:49.853323 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6843 01:18:49.856882 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6844 01:18:49.859865 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6845 01:18:49.863060 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6846 01:18:49.870247 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6847 01:18:49.873174 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6848 01:18:49.876454 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6849 01:18:49.880292 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6850 01:18:49.886632 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6851 01:18:49.890260 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6852 01:18:49.893201 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6853 01:18:49.893282 ==
6854 01:18:49.896702 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 01:18:49.899745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 01:18:49.903283 ==
6857 01:18:49.903364 DQS Delay:
6858 01:18:49.903426 DQS0 = 35, DQS1 = 35
6859 01:18:49.906596 DQM Delay:
6860 01:18:49.906676 DQM0 = 19, DQM1 = 15
6861 01:18:49.909735 DQ Delay:
6862 01:18:49.913047 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6863 01:18:49.913127 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6864 01:18:49.916642 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6865 01:18:49.920298 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6866 01:18:49.920379
6867 01:18:49.920442
6868 01:18:49.923194 ==
6869 01:18:49.926489 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 01:18:49.929769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 01:18:49.929850 ==
6872 01:18:49.929914
6873 01:18:49.929973
6874 01:18:49.932996 TX Vref Scan disable
6875 01:18:49.933098 == TX Byte 0 ==
6876 01:18:49.936963 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6877 01:18:49.943493 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6878 01:18:49.943574 == TX Byte 1 ==
6879 01:18:49.946661 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6880 01:18:49.953186 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6881 01:18:49.953268 ==
6882 01:18:49.956358 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 01:18:49.959579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 01:18:49.959660 ==
6885 01:18:49.959724
6886 01:18:49.959782
6887 01:18:49.963206 TX Vref Scan disable
6888 01:18:49.963285 == TX Byte 0 ==
6889 01:18:49.966722 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6890 01:18:49.972813 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6891 01:18:49.972894 == TX Byte 1 ==
6892 01:18:49.976598 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6893 01:18:49.983354 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6894 01:18:49.983435
6895 01:18:49.983498 [DATLAT]
6896 01:18:49.983555 Freq=400, CH1 RK1
6897 01:18:49.983612
6898 01:18:49.986213 DATLAT Default: 0xe
6899 01:18:49.986328 0, 0xFFFF, sum = 0
6900 01:18:49.989654 1, 0xFFFF, sum = 0
6901 01:18:49.989763 2, 0xFFFF, sum = 0
6902 01:18:49.992986 3, 0xFFFF, sum = 0
6903 01:18:49.996230 4, 0xFFFF, sum = 0
6904 01:18:49.996312 5, 0xFFFF, sum = 0
6905 01:18:49.999768 6, 0xFFFF, sum = 0
6906 01:18:49.999851 7, 0xFFFF, sum = 0
6907 01:18:50.003045 8, 0xFFFF, sum = 0
6908 01:18:50.003128 9, 0xFFFF, sum = 0
6909 01:18:50.006275 10, 0xFFFF, sum = 0
6910 01:18:50.006400 11, 0xFFFF, sum = 0
6911 01:18:50.009822 12, 0xFFFF, sum = 0
6912 01:18:50.009905 13, 0x0, sum = 1
6913 01:18:50.012816 14, 0x0, sum = 2
6914 01:18:50.012899 15, 0x0, sum = 3
6915 01:18:50.016183 16, 0x0, sum = 4
6916 01:18:50.016265 best_step = 14
6917 01:18:50.016329
6918 01:18:50.016388 ==
6919 01:18:50.019357 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 01:18:50.022555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 01:18:50.026246 ==
6922 01:18:50.026349 RX Vref Scan: 0
6923 01:18:50.026414
6924 01:18:50.029236 RX Vref 0 -> 0, step: 1
6925 01:18:50.029317
6926 01:18:50.032481 RX Delay -311 -> 252, step: 8
6927 01:18:50.036272 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6928 01:18:50.042829 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6929 01:18:50.046209 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6930 01:18:50.049569 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6931 01:18:50.052708 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6932 01:18:50.059540 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6933 01:18:50.062597 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6934 01:18:50.066087 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6935 01:18:50.069139 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6936 01:18:50.075673 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6937 01:18:50.079183 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6938 01:18:50.082294 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6939 01:18:50.088789 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6940 01:18:50.092412 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6941 01:18:50.095387 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6942 01:18:50.099225 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6943 01:18:50.099307 ==
6944 01:18:50.102058 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 01:18:50.108741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 01:18:50.108823 ==
6947 01:18:50.108888 DQS Delay:
6948 01:18:50.112287 DQS0 = 28, DQS1 = 36
6949 01:18:50.112368 DQM Delay:
6950 01:18:50.115523 DQM0 = 10, DQM1 = 15
6951 01:18:50.115603 DQ Delay:
6952 01:18:50.118880 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6953 01:18:50.121708 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6954 01:18:50.125761 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =12
6955 01:18:50.128782 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6956 01:18:50.128863
6957 01:18:50.128926
6958 01:18:50.135286 [DQSOSCAuto] RK1, (LSB)MR18= 0xba4d, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6959 01:18:50.138618 CH1 RK1: MR19=C0C, MR18=BA4D
6960 01:18:50.145517 CH1_RK1: MR19=0xC0C, MR18=0xBA4D, DQSOSC=386, MR23=63, INC=396, DEC=264
6961 01:18:50.148737 [RxdqsGatingPostProcess] freq 400
6962 01:18:50.151957 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6963 01:18:50.155229 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 01:18:50.158360 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 01:18:50.162170 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 01:18:50.165316 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 01:18:50.168458 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 01:18:50.171819 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 01:18:50.175032 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 01:18:50.178827 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 01:18:50.181884 Pre-setting of DQS Precalculation
6972 01:18:50.185324 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6973 01:18:50.191781 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6974 01:18:50.201780 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6975 01:18:50.201862
6976 01:18:50.201925
6977 01:18:50.204779 [Calibration Summary] 800 Mbps
6978 01:18:50.204864 CH 0, Rank 0
6979 01:18:50.208635 SW Impedance : PASS
6980 01:18:50.208716 DUTY Scan : NO K
6981 01:18:50.212027 ZQ Calibration : PASS
6982 01:18:50.215144 Jitter Meter : NO K
6983 01:18:50.215226 CBT Training : PASS
6984 01:18:50.218046 Write leveling : PASS
6985 01:18:50.221728 RX DQS gating : PASS
6986 01:18:50.221810 RX DQ/DQS(RDDQC) : PASS
6987 01:18:50.224724 TX DQ/DQS : PASS
6988 01:18:50.224832 RX DATLAT : PASS
6989 01:18:50.227969 RX DQ/DQS(Engine): PASS
6990 01:18:50.231351 TX OE : NO K
6991 01:18:50.231432 All Pass.
6992 01:18:50.231496
6993 01:18:50.231554 CH 0, Rank 1
6994 01:18:50.234599 SW Impedance : PASS
6995 01:18:50.237906 DUTY Scan : NO K
6996 01:18:50.237988 ZQ Calibration : PASS
6997 01:18:50.241281 Jitter Meter : NO K
6998 01:18:50.244455 CBT Training : PASS
6999 01:18:50.244536 Write leveling : NO K
7000 01:18:50.247941 RX DQS gating : PASS
7001 01:18:50.251013 RX DQ/DQS(RDDQC) : PASS
7002 01:18:50.251093 TX DQ/DQS : PASS
7003 01:18:50.254464 RX DATLAT : PASS
7004 01:18:50.258212 RX DQ/DQS(Engine): PASS
7005 01:18:50.258342 TX OE : NO K
7006 01:18:50.261512 All Pass.
7007 01:18:50.261593
7008 01:18:50.261656 CH 1, Rank 0
7009 01:18:50.264578 SW Impedance : PASS
7010 01:18:50.264658 DUTY Scan : NO K
7011 01:18:50.267709 ZQ Calibration : PASS
7012 01:18:50.270957 Jitter Meter : NO K
7013 01:18:50.271038 CBT Training : PASS
7014 01:18:50.274758 Write leveling : PASS
7015 01:18:50.277843 RX DQS gating : PASS
7016 01:18:50.277923 RX DQ/DQS(RDDQC) : PASS
7017 01:18:50.281101 TX DQ/DQS : PASS
7018 01:18:50.281183 RX DATLAT : PASS
7019 01:18:50.284301 RX DQ/DQS(Engine): PASS
7020 01:18:50.287462 TX OE : NO K
7021 01:18:50.287543 All Pass.
7022 01:18:50.287606
7023 01:18:50.291323 CH 1, Rank 1
7024 01:18:50.291404 SW Impedance : PASS
7025 01:18:50.294417 DUTY Scan : NO K
7026 01:18:50.294498 ZQ Calibration : PASS
7027 01:18:50.297980 Jitter Meter : NO K
7028 01:18:50.300785 CBT Training : PASS
7029 01:18:50.300866 Write leveling : NO K
7030 01:18:50.304598 RX DQS gating : PASS
7031 01:18:50.307606 RX DQ/DQS(RDDQC) : PASS
7032 01:18:50.307688 TX DQ/DQS : PASS
7033 01:18:50.310685 RX DATLAT : PASS
7034 01:18:50.314181 RX DQ/DQS(Engine): PASS
7035 01:18:50.314288 TX OE : NO K
7036 01:18:50.317697 All Pass.
7037 01:18:50.317777
7038 01:18:50.317841 DramC Write-DBI off
7039 01:18:50.321036 PER_BANK_REFRESH: Hybrid Mode
7040 01:18:50.321117 TX_TRACKING: ON
7041 01:18:50.330837 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7042 01:18:50.334031 [FAST_K] Save calibration result to emmc
7043 01:18:50.337609 dramc_set_vcore_voltage set vcore to 725000
7044 01:18:50.340897 Read voltage for 1600, 0
7045 01:18:50.340979 Vio18 = 0
7046 01:18:50.343688 Vcore = 725000
7047 01:18:50.343769 Vdram = 0
7048 01:18:50.343833 Vddq = 0
7049 01:18:50.347372 Vmddr = 0
7050 01:18:50.350542 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7051 01:18:50.357307 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7052 01:18:50.357388 MEM_TYPE=3, freq_sel=13
7053 01:18:50.360463 sv_algorithm_assistance_LP4_3733
7054 01:18:50.367064 ============ PULL DRAM RESETB DOWN ============
7055 01:18:50.370206 ========== PULL DRAM RESETB DOWN end =========
7056 01:18:50.373406 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7057 01:18:50.377246 ===================================
7058 01:18:50.380471 LPDDR4 DRAM CONFIGURATION
7059 01:18:50.383686 ===================================
7060 01:18:50.386877 EX_ROW_EN[0] = 0x0
7061 01:18:50.386958 EX_ROW_EN[1] = 0x0
7062 01:18:50.390770 LP4Y_EN = 0x0
7063 01:18:50.390851 WORK_FSP = 0x1
7064 01:18:50.394023 WL = 0x5
7065 01:18:50.394104 RL = 0x5
7066 01:18:50.397177 BL = 0x2
7067 01:18:50.397258 RPST = 0x0
7068 01:18:50.400391 RD_PRE = 0x0
7069 01:18:50.400472 WR_PRE = 0x1
7070 01:18:50.403396 WR_PST = 0x1
7071 01:18:50.403477 DBI_WR = 0x0
7072 01:18:50.406943 DBI_RD = 0x0
7073 01:18:50.407024 OTF = 0x1
7074 01:18:50.410591 ===================================
7075 01:18:50.413787 ===================================
7076 01:18:50.416705 ANA top config
7077 01:18:50.420075 ===================================
7078 01:18:50.423406 DLL_ASYNC_EN = 0
7079 01:18:50.423486 ALL_SLAVE_EN = 0
7080 01:18:50.426996 NEW_RANK_MODE = 1
7081 01:18:50.430017 DLL_IDLE_MODE = 1
7082 01:18:50.433316 LP45_APHY_COMB_EN = 1
7083 01:18:50.433398 TX_ODT_DIS = 0
7084 01:18:50.436629 NEW_8X_MODE = 1
7085 01:18:50.439792 ===================================
7086 01:18:50.443637 ===================================
7087 01:18:50.446721 data_rate = 3200
7088 01:18:50.450024 CKR = 1
7089 01:18:50.453213 DQ_P2S_RATIO = 8
7090 01:18:50.456387 ===================================
7091 01:18:50.460082 CA_P2S_RATIO = 8
7092 01:18:50.460165 DQ_CA_OPEN = 0
7093 01:18:50.463289 DQ_SEMI_OPEN = 0
7094 01:18:50.466470 CA_SEMI_OPEN = 0
7095 01:18:50.469662 CA_FULL_RATE = 0
7096 01:18:50.473333 DQ_CKDIV4_EN = 0
7097 01:18:50.476645 CA_CKDIV4_EN = 0
7098 01:18:50.476727 CA_PREDIV_EN = 0
7099 01:18:50.479967 PH8_DLY = 12
7100 01:18:50.483155 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7101 01:18:50.486292 DQ_AAMCK_DIV = 4
7102 01:18:50.489473 CA_AAMCK_DIV = 4
7103 01:18:50.493221 CA_ADMCK_DIV = 4
7104 01:18:50.493302 DQ_TRACK_CA_EN = 0
7105 01:18:50.496537 CA_PICK = 1600
7106 01:18:50.500042 CA_MCKIO = 1600
7107 01:18:50.503590 MCKIO_SEMI = 0
7108 01:18:50.506894 PLL_FREQ = 3068
7109 01:18:50.510026 DQ_UI_PI_RATIO = 32
7110 01:18:50.513125 CA_UI_PI_RATIO = 0
7111 01:18:50.516758 ===================================
7112 01:18:50.519957 ===================================
7113 01:18:50.520039 memory_type:LPDDR4
7114 01:18:50.523125 GP_NUM : 10
7115 01:18:50.526243 SRAM_EN : 1
7116 01:18:50.526348 MD32_EN : 0
7117 01:18:50.529767 ===================================
7118 01:18:50.533596 [ANA_INIT] >>>>>>>>>>>>>>
7119 01:18:50.536186 <<<<<< [CONFIGURE PHASE]: ANA_TX
7120 01:18:50.540051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7121 01:18:50.543180 ===================================
7122 01:18:50.546514 data_rate = 3200,PCW = 0X7600
7123 01:18:50.549496 ===================================
7124 01:18:50.552598 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7125 01:18:50.556333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 01:18:50.562470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 01:18:50.565864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7128 01:18:50.569586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7129 01:18:50.572633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7130 01:18:50.576147 [ANA_INIT] flow start
7131 01:18:50.579296 [ANA_INIT] PLL >>>>>>>>
7132 01:18:50.579378 [ANA_INIT] PLL <<<<<<<<
7133 01:18:50.582709 [ANA_INIT] MIDPI >>>>>>>>
7134 01:18:50.585823 [ANA_INIT] MIDPI <<<<<<<<
7135 01:18:50.589518 [ANA_INIT] DLL >>>>>>>>
7136 01:18:50.589599 [ANA_INIT] DLL <<<<<<<<
7137 01:18:50.592603 [ANA_INIT] flow end
7138 01:18:50.596040 ============ LP4 DIFF to SE enter ============
7139 01:18:50.599214 ============ LP4 DIFF to SE exit ============
7140 01:18:50.602434 [ANA_INIT] <<<<<<<<<<<<<
7141 01:18:50.605779 [Flow] Enable top DCM control >>>>>
7142 01:18:50.609612 [Flow] Enable top DCM control <<<<<
7143 01:18:50.612935 Enable DLL master slave shuffle
7144 01:18:50.619147 ==============================================================
7145 01:18:50.619229 Gating Mode config
7146 01:18:50.625668 ==============================================================
7147 01:18:50.625750 Config description:
7148 01:18:50.636177 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7149 01:18:50.642522 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7150 01:18:50.648911 SELPH_MODE 0: By rank 1: By Phase
7151 01:18:50.652250 ==============================================================
7152 01:18:50.655540 GAT_TRACK_EN = 1
7153 01:18:50.659559 RX_GATING_MODE = 2
7154 01:18:50.662700 RX_GATING_TRACK_MODE = 2
7155 01:18:50.665837 SELPH_MODE = 1
7156 01:18:50.669030 PICG_EARLY_EN = 1
7157 01:18:50.672412 VALID_LAT_VALUE = 1
7158 01:18:50.675537 ==============================================================
7159 01:18:50.678898 Enter into Gating configuration >>>>
7160 01:18:50.682525 Exit from Gating configuration <<<<
7161 01:18:50.685440 Enter into DVFS_PRE_config >>>>>
7162 01:18:50.699213 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7163 01:18:50.702156 Exit from DVFS_PRE_config <<<<<
7164 01:18:50.705791 Enter into PICG configuration >>>>
7165 01:18:50.705873 Exit from PICG configuration <<<<
7166 01:18:50.709152 [RX_INPUT] configuration >>>>>
7167 01:18:50.712623 [RX_INPUT] configuration <<<<<
7168 01:18:50.719106 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7169 01:18:50.722527 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7170 01:18:50.728666 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 01:18:50.735250 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 01:18:50.742094 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 01:18:50.748525 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 01:18:50.751574 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7175 01:18:50.755477 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7176 01:18:50.761974 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7177 01:18:50.765219 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7178 01:18:50.768549 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7179 01:18:50.771856 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7180 01:18:50.774974 ===================================
7181 01:18:50.778197 LPDDR4 DRAM CONFIGURATION
7182 01:18:50.782101 ===================================
7183 01:18:50.785202 EX_ROW_EN[0] = 0x0
7184 01:18:50.785283 EX_ROW_EN[1] = 0x0
7185 01:18:50.788277 LP4Y_EN = 0x0
7186 01:18:50.788357 WORK_FSP = 0x1
7187 01:18:50.792278 WL = 0x5
7188 01:18:50.792359 RL = 0x5
7189 01:18:50.795356 BL = 0x2
7190 01:18:50.795436 RPST = 0x0
7191 01:18:50.798571 RD_PRE = 0x0
7192 01:18:50.798651 WR_PRE = 0x1
7193 01:18:50.801489 WR_PST = 0x1
7194 01:18:50.801577 DBI_WR = 0x0
7195 01:18:50.804813 DBI_RD = 0x0
7196 01:18:50.804893 OTF = 0x1
7197 01:18:50.808205 ===================================
7198 01:18:50.815203 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7199 01:18:50.817934 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7200 01:18:50.821644 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7201 01:18:50.824871 ===================================
7202 01:18:50.828306 LPDDR4 DRAM CONFIGURATION
7203 01:18:50.831426 ===================================
7204 01:18:50.834571 EX_ROW_EN[0] = 0x10
7205 01:18:50.834651 EX_ROW_EN[1] = 0x0
7206 01:18:50.838248 LP4Y_EN = 0x0
7207 01:18:50.838365 WORK_FSP = 0x1
7208 01:18:50.841570 WL = 0x5
7209 01:18:50.841651 RL = 0x5
7210 01:18:50.844745 BL = 0x2
7211 01:18:50.844826 RPST = 0x0
7212 01:18:50.847675 RD_PRE = 0x0
7213 01:18:50.847756 WR_PRE = 0x1
7214 01:18:50.851283 WR_PST = 0x1
7215 01:18:50.851397 DBI_WR = 0x0
7216 01:18:50.854465 DBI_RD = 0x0
7217 01:18:50.854545 OTF = 0x1
7218 01:18:50.857598 ===================================
7219 01:18:50.864155 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7220 01:18:50.864235 ==
7221 01:18:50.867903 Dram Type= 6, Freq= 0, CH_0, rank 0
7222 01:18:50.874583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7223 01:18:50.874664 ==
7224 01:18:50.874727 [Duty_Offset_Calibration]
7225 01:18:50.877856 B0:2 B1:1 CA:1
7226 01:18:50.877936
7227 01:18:50.880853 [DutyScan_Calibration_Flow] k_type=0
7228 01:18:50.890745
7229 01:18:50.890824 ==CLK 0==
7230 01:18:50.893822 Final CLK duty delay cell = 0
7231 01:18:50.896920 [0] MAX Duty = 5156%(X100), DQS PI = 22
7232 01:18:50.900560 [0] MIN Duty = 4876%(X100), DQS PI = 48
7233 01:18:50.900640 [0] AVG Duty = 5016%(X100)
7234 01:18:50.903852
7235 01:18:50.903932 CH0 CLK Duty spec in!! Max-Min= 280%
7236 01:18:50.910223 [DutyScan_Calibration_Flow] ====Done====
7237 01:18:50.910324
7238 01:18:50.913773 [DutyScan_Calibration_Flow] k_type=1
7239 01:18:50.929587
7240 01:18:50.929667 ==DQS 0 ==
7241 01:18:50.932799 Final DQS duty delay cell = -4
7242 01:18:50.936800 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7243 01:18:50.939815 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7244 01:18:50.943129 [-4] AVG Duty = 4891%(X100)
7245 01:18:50.943210
7246 01:18:50.943273 ==DQS 1 ==
7247 01:18:50.946178 Final DQS duty delay cell = 0
7248 01:18:50.949773 [0] MAX Duty = 5187%(X100), DQS PI = 4
7249 01:18:50.952979 [0] MIN Duty = 5031%(X100), DQS PI = 52
7250 01:18:50.956646 [0] AVG Duty = 5109%(X100)
7251 01:18:50.956726
7252 01:18:50.959669 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7253 01:18:50.959750
7254 01:18:50.963006 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7255 01:18:50.966202 [DutyScan_Calibration_Flow] ====Done====
7256 01:18:50.966297
7257 01:18:50.969445 [DutyScan_Calibration_Flow] k_type=3
7258 01:18:50.987050
7259 01:18:50.987130 ==DQM 0 ==
7260 01:18:50.990486 Final DQM duty delay cell = 0
7261 01:18:50.993663 [0] MAX Duty = 5187%(X100), DQS PI = 26
7262 01:18:50.996883 [0] MIN Duty = 4907%(X100), DQS PI = 0
7263 01:18:50.996963 [0] AVG Duty = 5047%(X100)
7264 01:18:51.000155
7265 01:18:51.000235 ==DQM 1 ==
7266 01:18:51.003401 Final DQM duty delay cell = 0
7267 01:18:51.006947 [0] MAX Duty = 5187%(X100), DQS PI = 2
7268 01:18:51.010244 [0] MIN Duty = 5031%(X100), DQS PI = 50
7269 01:18:51.010361 [0] AVG Duty = 5109%(X100)
7270 01:18:51.013884
7271 01:18:51.017156 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7272 01:18:51.017237
7273 01:18:51.020352 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7274 01:18:51.023503 [DutyScan_Calibration_Flow] ====Done====
7275 01:18:51.023584
7276 01:18:51.026554 [DutyScan_Calibration_Flow] k_type=2
7277 01:18:51.043753
7278 01:18:51.043835 ==DQ 0 ==
7279 01:18:51.047631 Final DQ duty delay cell = 0
7280 01:18:51.050545 [0] MAX Duty = 5062%(X100), DQS PI = 26
7281 01:18:51.053976 [0] MIN Duty = 4907%(X100), DQS PI = 0
7282 01:18:51.054059 [0] AVG Duty = 4984%(X100)
7283 01:18:51.054122
7284 01:18:51.057392 ==DQ 1 ==
7285 01:18:51.060945 Final DQ duty delay cell = 0
7286 01:18:51.064187 [0] MAX Duty = 5156%(X100), DQS PI = 22
7287 01:18:51.067329 [0] MIN Duty = 4907%(X100), DQS PI = 34
7288 01:18:51.067411 [0] AVG Duty = 5031%(X100)
7289 01:18:51.067474
7290 01:18:51.070813 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7291 01:18:51.070894
7292 01:18:51.073744 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7293 01:18:51.080452 [DutyScan_Calibration_Flow] ====Done====
7294 01:18:51.080535 ==
7295 01:18:51.084333 Dram Type= 6, Freq= 0, CH_1, rank 0
7296 01:18:51.087562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7297 01:18:51.087644 ==
7298 01:18:51.090723 [Duty_Offset_Calibration]
7299 01:18:51.090803 B0:1 B1:0 CA:0
7300 01:18:51.090866
7301 01:18:51.093877 [DutyScan_Calibration_Flow] k_type=0
7302 01:18:51.103123
7303 01:18:51.103203 ==CLK 0==
7304 01:18:51.107011 Final CLK duty delay cell = -4
7305 01:18:51.110219 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7306 01:18:51.113241 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7307 01:18:51.116872 [-4] AVG Duty = 4922%(X100)
7308 01:18:51.116952
7309 01:18:51.120003 CH1 CLK Duty spec in!! Max-Min= 156%
7310 01:18:51.123119 [DutyScan_Calibration_Flow] ====Done====
7311 01:18:51.123200
7312 01:18:51.126191 [DutyScan_Calibration_Flow] k_type=1
7313 01:18:51.143585
7314 01:18:51.143702 ==DQS 0 ==
7315 01:18:51.146906 Final DQS duty delay cell = 0
7316 01:18:51.150090 [0] MAX Duty = 5094%(X100), DQS PI = 30
7317 01:18:51.153210 [0] MIN Duty = 4844%(X100), DQS PI = 46
7318 01:18:51.156669 [0] AVG Duty = 4969%(X100)
7319 01:18:51.156750
7320 01:18:51.156812 ==DQS 1 ==
7321 01:18:51.160086 Final DQS duty delay cell = 0
7322 01:18:51.163506 [0] MAX Duty = 5249%(X100), DQS PI = 16
7323 01:18:51.166850 [0] MIN Duty = 4938%(X100), DQS PI = 8
7324 01:18:51.169905 [0] AVG Duty = 5093%(X100)
7325 01:18:51.169984
7326 01:18:51.173248 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7327 01:18:51.173327
7328 01:18:51.177106 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7329 01:18:51.180274 [DutyScan_Calibration_Flow] ====Done====
7330 01:18:51.180353
7331 01:18:51.183243 [DutyScan_Calibration_Flow] k_type=3
7332 01:18:51.200453
7333 01:18:51.200532 ==DQM 0 ==
7334 01:18:51.203730 Final DQM duty delay cell = 0
7335 01:18:51.207108 [0] MAX Duty = 5218%(X100), DQS PI = 18
7336 01:18:51.210289 [0] MIN Duty = 4969%(X100), DQS PI = 48
7337 01:18:51.213525 [0] AVG Duty = 5093%(X100)
7338 01:18:51.213604
7339 01:18:51.213666 ==DQM 1 ==
7340 01:18:51.216675 Final DQM duty delay cell = 0
7341 01:18:51.220328 [0] MAX Duty = 5093%(X100), DQS PI = 16
7342 01:18:51.223505 [0] MIN Duty = 4938%(X100), DQS PI = 6
7343 01:18:51.227079 [0] AVG Duty = 5015%(X100)
7344 01:18:51.227158
7345 01:18:51.230010 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7346 01:18:51.230089
7347 01:18:51.233811 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7348 01:18:51.236966 [DutyScan_Calibration_Flow] ====Done====
7349 01:18:51.237045
7350 01:18:51.239750 [DutyScan_Calibration_Flow] k_type=2
7351 01:18:51.256371
7352 01:18:51.256451 ==DQ 0 ==
7353 01:18:51.259698 Final DQ duty delay cell = -4
7354 01:18:51.262942 [-4] MAX Duty = 5031%(X100), DQS PI = 8
7355 01:18:51.266560 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7356 01:18:51.269643 [-4] AVG Duty = 4953%(X100)
7357 01:18:51.269722
7358 01:18:51.269784 ==DQ 1 ==
7359 01:18:51.273158 Final DQ duty delay cell = 0
7360 01:18:51.276180 [0] MAX Duty = 5124%(X100), DQS PI = 18
7361 01:18:51.279750 [0] MIN Duty = 4938%(X100), DQS PI = 10
7362 01:18:51.282706 [0] AVG Duty = 5031%(X100)
7363 01:18:51.282785
7364 01:18:51.286161 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7365 01:18:51.286242
7366 01:18:51.289426 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7367 01:18:51.292977 [DutyScan_Calibration_Flow] ====Done====
7368 01:18:51.295958 nWR fixed to 30
7369 01:18:51.299542 [ModeRegInit_LP4] CH0 RK0
7370 01:18:51.299665 [ModeRegInit_LP4] CH0 RK1
7371 01:18:51.303158 [ModeRegInit_LP4] CH1 RK0
7372 01:18:51.306101 [ModeRegInit_LP4] CH1 RK1
7373 01:18:51.306195 match AC timing 5
7374 01:18:51.312508 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7375 01:18:51.315875 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7376 01:18:51.319683 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7377 01:18:51.326216 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7378 01:18:51.329359 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7379 01:18:51.329441 [MiockJmeterHQA]
7380 01:18:51.329504
7381 01:18:51.332441 [DramcMiockJmeter] u1RxGatingPI = 0
7382 01:18:51.336305 0 : 4363, 4138
7383 01:18:51.336389 4 : 4252, 4027
7384 01:18:51.339088 8 : 4253, 4026
7385 01:18:51.339172 12 : 4252, 4026
7386 01:18:51.342239 16 : 4255, 4029
7387 01:18:51.342357 20 : 4253, 4027
7388 01:18:51.342423 24 : 4252, 4027
7389 01:18:51.346111 28 : 4365, 4140
7390 01:18:51.346195 32 : 4253, 4026
7391 01:18:51.349225 36 : 4255, 4030
7392 01:18:51.349312 40 : 4252, 4027
7393 01:18:51.352232 44 : 4363, 4137
7394 01:18:51.352314 48 : 4252, 4027
7395 01:18:51.355484 52 : 4360, 4137
7396 01:18:51.355565 56 : 4250, 4027
7397 01:18:51.355629 60 : 4249, 4027
7398 01:18:51.359385 64 : 4250, 4026
7399 01:18:51.359466 68 : 4252, 4030
7400 01:18:51.362162 72 : 4250, 4027
7401 01:18:51.362245 76 : 4253, 4029
7402 01:18:51.366071 80 : 4363, 4140
7403 01:18:51.366153 84 : 4250, 4026
7404 01:18:51.366216 88 : 4252, 173
7405 01:18:51.369306 92 : 4363, 0
7406 01:18:51.369387 96 : 4252, 0
7407 01:18:51.372609 100 : 4252, 0
7408 01:18:51.372690 104 : 4250, 0
7409 01:18:51.372753 108 : 4250, 0
7410 01:18:51.376041 112 : 4249, 0
7411 01:18:51.376122 116 : 4253, 0
7412 01:18:51.376198 120 : 4250, 0
7413 01:18:51.378976 124 : 4249, 0
7414 01:18:51.379057 128 : 4253, 0
7415 01:18:51.382268 132 : 4361, 0
7416 01:18:51.382403 136 : 4249, 0
7417 01:18:51.382482 140 : 4250, 0
7418 01:18:51.385525 144 : 4252, 0
7419 01:18:51.385606 148 : 4361, 0
7420 01:18:51.388931 152 : 4360, 0
7421 01:18:51.389012 156 : 4250, 0
7422 01:18:51.389076 160 : 4252, 0
7423 01:18:51.392430 164 : 4249, 0
7424 01:18:51.392511 168 : 4252, 0
7425 01:18:51.395901 172 : 4250, 0
7426 01:18:51.395987 176 : 4249, 0
7427 01:18:51.396051 180 : 4252, 0
7428 01:18:51.398709 184 : 4361, 0
7429 01:18:51.398790 188 : 4249, 0
7430 01:18:51.402005 192 : 4250, 0
7431 01:18:51.402087 196 : 4250, 0
7432 01:18:51.402157 200 : 4360, 0
7433 01:18:51.405359 204 : 4361, 1307
7434 01:18:51.405441 208 : 4361, 4109
7435 01:18:51.408889 212 : 4250, 4026
7436 01:18:51.408970 216 : 4250, 4027
7437 01:18:51.412261 220 : 4250, 4027
7438 01:18:51.412341 224 : 4249, 4027
7439 01:18:51.415243 228 : 4250, 4026
7440 01:18:51.415335 232 : 4250, 4027
7441 01:18:51.418742 236 : 4252, 4030
7442 01:18:51.418825 240 : 4249, 4027
7443 01:18:51.418890 244 : 4360, 4137
7444 01:18:51.422127 248 : 4361, 4137
7445 01:18:51.422208 252 : 4250, 4027
7446 01:18:51.425623 256 : 4363, 4140
7447 01:18:51.425705 260 : 4249, 4027
7448 01:18:51.428582 264 : 4250, 4026
7449 01:18:51.428663 268 : 4250, 4027
7450 01:18:51.431769 272 : 4252, 4030
7451 01:18:51.431851 276 : 4249, 4027
7452 01:18:51.435015 280 : 4250, 4026
7453 01:18:51.435096 284 : 4250, 4027
7454 01:18:51.438270 288 : 4252, 4030
7455 01:18:51.438387 292 : 4249, 4027
7456 01:18:51.441836 296 : 4360, 4137
7457 01:18:51.441919 300 : 4361, 4137
7458 01:18:51.445249 304 : 4250, 4027
7459 01:18:51.445332 308 : 4363, 4068
7460 01:18:51.445396 312 : 4361, 2216
7461 01:18:51.448859 316 : 4250, 6
7462 01:18:51.448942
7463 01:18:51.451892 MIOCK jitter meter ch=0
7464 01:18:51.451973
7465 01:18:51.452035 1T = (316-88) = 228 dly cells
7466 01:18:51.458274 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7467 01:18:51.458400 ==
7468 01:18:51.461611 Dram Type= 6, Freq= 0, CH_0, rank 0
7469 01:18:51.464996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7470 01:18:51.468167 ==
7471 01:18:51.471446 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7472 01:18:51.474860 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7473 01:18:51.481434 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7474 01:18:51.484721 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7475 01:18:51.495416 [CA 0] Center 43 (13~74) winsize 62
7476 01:18:51.498626 [CA 1] Center 43 (13~74) winsize 62
7477 01:18:51.501761 [CA 2] Center 38 (9~68) winsize 60
7478 01:18:51.505639 [CA 3] Center 38 (8~68) winsize 61
7479 01:18:51.508549 [CA 4] Center 37 (7~67) winsize 61
7480 01:18:51.512084 [CA 5] Center 36 (7~65) winsize 59
7481 01:18:51.512167
7482 01:18:51.515134 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7483 01:18:51.515216
7484 01:18:51.518894 [CATrainingPosCal] consider 1 rank data
7485 01:18:51.521903 u2DelayCellTimex100 = 285/100 ps
7486 01:18:51.525357 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7487 01:18:51.531765 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7488 01:18:51.535147 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7489 01:18:51.538526 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7490 01:18:51.541686 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7491 01:18:51.545528 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7492 01:18:51.545625
7493 01:18:51.548143 CA PerBit enable=1, Macro0, CA PI delay=36
7494 01:18:51.548226
7495 01:18:51.551992 [CBTSetCACLKResult] CA Dly = 36
7496 01:18:51.555309 CS Dly: 9 (0~40)
7497 01:18:51.558448 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7498 01:18:51.561958 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7499 01:18:51.562040 ==
7500 01:18:51.565445 Dram Type= 6, Freq= 0, CH_0, rank 1
7501 01:18:51.568677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7502 01:18:51.568762 ==
7503 01:18:51.575190 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7504 01:18:51.578363 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7505 01:18:51.584896 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7506 01:18:51.588754 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7507 01:18:51.598467 [CA 0] Center 42 (12~73) winsize 62
7508 01:18:51.601904 [CA 1] Center 42 (12~73) winsize 62
7509 01:18:51.605286 [CA 2] Center 38 (8~68) winsize 61
7510 01:18:51.608260 [CA 3] Center 37 (8~67) winsize 60
7511 01:18:51.612013 [CA 4] Center 36 (6~66) winsize 61
7512 01:18:51.615264 [CA 5] Center 35 (5~65) winsize 61
7513 01:18:51.615357
7514 01:18:51.618267 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7515 01:18:51.618385
7516 01:18:51.621728 [CATrainingPosCal] consider 2 rank data
7517 01:18:51.625329 u2DelayCellTimex100 = 285/100 ps
7518 01:18:51.628392 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7519 01:18:51.635429 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7520 01:18:51.638587 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7521 01:18:51.642205 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7522 01:18:51.645454 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7523 01:18:51.648524 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7524 01:18:51.648614
7525 01:18:51.651762 CA PerBit enable=1, Macro0, CA PI delay=36
7526 01:18:51.651845
7527 01:18:51.655194 [CBTSetCACLKResult] CA Dly = 36
7528 01:18:51.658439 CS Dly: 10 (0~42)
7529 01:18:51.661771 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7530 01:18:51.664988 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7531 01:18:51.665073
7532 01:18:51.668128 ----->DramcWriteLeveling(PI) begin...
7533 01:18:51.668212 ==
7534 01:18:51.671846 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 01:18:51.675399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 01:18:51.678319 ==
7537 01:18:51.678403 Write leveling (Byte 0): 35 => 35
7538 01:18:51.681572 Write leveling (Byte 1): 29 => 29
7539 01:18:51.684989 DramcWriteLeveling(PI) end<-----
7540 01:18:51.685074
7541 01:18:51.685137 ==
7542 01:18:51.688299 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 01:18:51.694834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 01:18:51.694927 ==
7545 01:18:51.694991 [Gating] SW mode calibration
7546 01:18:51.704612 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7547 01:18:51.707885 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7548 01:18:51.714982 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7549 01:18:51.717817 1 4 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7550 01:18:51.721266 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7551 01:18:51.728236 1 4 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (1 1)
7552 01:18:51.731210 1 4 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
7553 01:18:51.734583 1 4 20 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7554 01:18:51.741648 1 4 24 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7555 01:18:51.744812 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7556 01:18:51.748120 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7557 01:18:51.751274 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7558 01:18:51.757715 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7559 01:18:51.761220 1 5 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7560 01:18:51.764748 1 5 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
7561 01:18:51.771158 1 5 20 | B1->B0 | 2626 2626 | 0 0 | (0 1) (0 0)
7562 01:18:51.774430 1 5 24 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7563 01:18:51.777712 1 5 28 | B1->B0 | 2323 2222 | 0 1 | (0 0) (0 0)
7564 01:18:51.784723 1 6 0 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7565 01:18:51.787763 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
7566 01:18:51.791351 1 6 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7567 01:18:51.797811 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7568 01:18:51.801192 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7569 01:18:51.804442 1 6 20 | B1->B0 | 4040 4645 | 0 1 | (0 0) (0 0)
7570 01:18:51.810993 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7571 01:18:51.814265 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 01:18:51.817558 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 01:18:51.824476 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 01:18:51.827865 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 01:18:51.831146 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7576 01:18:51.837394 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 01:18:51.841098 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7578 01:18:51.844004 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 01:18:51.851070 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 01:18:51.854086 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 01:18:51.857907 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 01:18:51.864261 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 01:18:51.867245 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 01:18:51.870665 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 01:18:51.877415 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 01:18:51.880636 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 01:18:51.884297 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 01:18:51.887500 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 01:18:51.894326 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 01:18:51.897724 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 01:18:51.900822 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7592 01:18:51.907419 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7593 01:18:51.910728 Total UI for P1: 0, mck2ui 16
7594 01:18:51.913970 best dqsien dly found for B0: ( 1, 9, 12)
7595 01:18:51.917299 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7596 01:18:51.920579 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 01:18:51.923867 Total UI for P1: 0, mck2ui 16
7598 01:18:51.927181 best dqsien dly found for B1: ( 1, 9, 18)
7599 01:18:51.930488 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7600 01:18:51.934173 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7601 01:18:51.937221
7602 01:18:51.940675 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7603 01:18:51.943600 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7604 01:18:51.947211 [Gating] SW calibration Done
7605 01:18:51.947308 ==
7606 01:18:51.950238 Dram Type= 6, Freq= 0, CH_0, rank 0
7607 01:18:51.954177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 01:18:51.954293 ==
7609 01:18:51.954401 RX Vref Scan: 0
7610 01:18:51.957240
7611 01:18:51.957321 RX Vref 0 -> 0, step: 1
7612 01:18:51.957385
7613 01:18:51.960493 RX Delay 0 -> 252, step: 8
7614 01:18:51.963921 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7615 01:18:51.967418 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7616 01:18:51.974128 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7617 01:18:51.977546 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7618 01:18:51.980660 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7619 01:18:51.983745 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7620 01:18:51.987316 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7621 01:18:51.990672 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7622 01:18:51.997130 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7623 01:18:52.001085 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7624 01:18:52.003825 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7625 01:18:52.007343 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7626 01:18:52.010703 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7627 01:18:52.017415 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7628 01:18:52.020538 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7629 01:18:52.023894 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7630 01:18:52.023986 ==
7631 01:18:52.027197 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 01:18:52.030517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 01:18:52.030603 ==
7634 01:18:52.033672 DQS Delay:
7635 01:18:52.033755 DQS0 = 0, DQS1 = 0
7636 01:18:52.036959 DQM Delay:
7637 01:18:52.037043 DQM0 = 136, DQM1 = 129
7638 01:18:52.040321 DQ Delay:
7639 01:18:52.043715 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7640 01:18:52.046772 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7641 01:18:52.050294 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7642 01:18:52.053825 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7643 01:18:52.053917
7644 01:18:52.053981
7645 01:18:52.054041 ==
7646 01:18:52.056777 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 01:18:52.060048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 01:18:52.060136 ==
7649 01:18:52.060201
7650 01:18:52.060260
7651 01:18:52.063926 TX Vref Scan disable
7652 01:18:52.066930 == TX Byte 0 ==
7653 01:18:52.070057 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7654 01:18:52.073807 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7655 01:18:52.076655 == TX Byte 1 ==
7656 01:18:52.079986 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7657 01:18:52.083659 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7658 01:18:52.083760 ==
7659 01:18:52.086623 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 01:18:52.093475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 01:18:52.093581 ==
7662 01:18:52.104369
7663 01:18:52.107450 TX Vref early break, caculate TX vref
7664 01:18:52.110968 TX Vref=16, minBit 0, minWin=23, winSum=381
7665 01:18:52.114034 TX Vref=18, minBit 0, minWin=23, winSum=387
7666 01:18:52.117777 TX Vref=20, minBit 7, minWin=23, winSum=397
7667 01:18:52.121213 TX Vref=22, minBit 0, minWin=24, winSum=406
7668 01:18:52.124501 TX Vref=24, minBit 0, minWin=25, winSum=414
7669 01:18:52.130993 TX Vref=26, minBit 1, minWin=25, winSum=429
7670 01:18:52.134296 TX Vref=28, minBit 1, minWin=25, winSum=426
7671 01:18:52.137551 TX Vref=30, minBit 1, minWin=24, winSum=414
7672 01:18:52.140873 TX Vref=32, minBit 0, minWin=23, winSum=401
7673 01:18:52.147462 [TxChooseVref] Worse bit 1, Min win 25, Win sum 429, Final Vref 26
7674 01:18:52.147576
7675 01:18:52.150744 Final TX Range 0 Vref 26
7676 01:18:52.150835
7677 01:18:52.150900 ==
7678 01:18:52.154372 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 01:18:52.157380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 01:18:52.157465 ==
7681 01:18:52.157528
7682 01:18:52.157586
7683 01:18:52.161091 TX Vref Scan disable
7684 01:18:52.164118 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7685 01:18:52.167378 == TX Byte 0 ==
7686 01:18:52.170830 u2DelayCellOfst[0]=10 cells (3 PI)
7687 01:18:52.173959 u2DelayCellOfst[1]=13 cells (4 PI)
7688 01:18:52.177272 u2DelayCellOfst[2]=10 cells (3 PI)
7689 01:18:52.180387 u2DelayCellOfst[3]=6 cells (2 PI)
7690 01:18:52.184199 u2DelayCellOfst[4]=6 cells (2 PI)
7691 01:18:52.184292 u2DelayCellOfst[5]=0 cells (0 PI)
7692 01:18:52.187256 u2DelayCellOfst[6]=17 cells (5 PI)
7693 01:18:52.190532 u2DelayCellOfst[7]=17 cells (5 PI)
7694 01:18:52.197213 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7695 01:18:52.200573 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7696 01:18:52.200672 == TX Byte 1 ==
7697 01:18:52.203717 u2DelayCellOfst[8]=3 cells (1 PI)
7698 01:18:52.207324 u2DelayCellOfst[9]=0 cells (0 PI)
7699 01:18:52.210802 u2DelayCellOfst[10]=6 cells (2 PI)
7700 01:18:52.213823 u2DelayCellOfst[11]=6 cells (2 PI)
7701 01:18:52.217266 u2DelayCellOfst[12]=10 cells (3 PI)
7702 01:18:52.220456 u2DelayCellOfst[13]=10 cells (3 PI)
7703 01:18:52.224175 u2DelayCellOfst[14]=13 cells (4 PI)
7704 01:18:52.226925 u2DelayCellOfst[15]=10 cells (3 PI)
7705 01:18:52.230462 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7706 01:18:52.233887 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7707 01:18:52.237167 DramC Write-DBI on
7708 01:18:52.237256 ==
7709 01:18:52.240587 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 01:18:52.243911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 01:18:52.244003 ==
7712 01:18:52.244068
7713 01:18:52.244127
7714 01:18:52.247100 TX Vref Scan disable
7715 01:18:52.250277 == TX Byte 0 ==
7716 01:18:52.253631 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7717 01:18:52.256802 == TX Byte 1 ==
7718 01:18:52.260013 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7719 01:18:52.260102 DramC Write-DBI off
7720 01:18:52.260167
7721 01:18:52.263224 [DATLAT]
7722 01:18:52.263309 Freq=1600, CH0 RK0
7723 01:18:52.263373
7724 01:18:52.266837 DATLAT Default: 0xf
7725 01:18:52.266938 0, 0xFFFF, sum = 0
7726 01:18:52.270006 1, 0xFFFF, sum = 0
7727 01:18:52.270094 2, 0xFFFF, sum = 0
7728 01:18:52.273119 3, 0xFFFF, sum = 0
7729 01:18:52.273207 4, 0xFFFF, sum = 0
7730 01:18:52.276711 5, 0xFFFF, sum = 0
7731 01:18:52.276801 6, 0xFFFF, sum = 0
7732 01:18:52.280340 7, 0xFFFF, sum = 0
7733 01:18:52.283553 8, 0xFFFF, sum = 0
7734 01:18:52.283643 9, 0xFFFF, sum = 0
7735 01:18:52.286694 10, 0xFFFF, sum = 0
7736 01:18:52.286779 11, 0xFFFF, sum = 0
7737 01:18:52.290021 12, 0xFFFF, sum = 0
7738 01:18:52.290107 13, 0xFFFF, sum = 0
7739 01:18:52.293330 14, 0x0, sum = 1
7740 01:18:52.293415 15, 0x0, sum = 2
7741 01:18:52.296795 16, 0x0, sum = 3
7742 01:18:52.296884 17, 0x0, sum = 4
7743 01:18:52.299717 best_step = 15
7744 01:18:52.299801
7745 01:18:52.299865 ==
7746 01:18:52.303512 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 01:18:52.306514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 01:18:52.306603 ==
7749 01:18:52.306667 RX Vref Scan: 1
7750 01:18:52.306727
7751 01:18:52.309686 Set Vref Range= 24 -> 127
7752 01:18:52.309769
7753 01:18:52.312952 RX Vref 24 -> 127, step: 1
7754 01:18:52.313037
7755 01:18:52.316721 RX Delay 19 -> 252, step: 4
7756 01:18:52.316806
7757 01:18:52.319694 Set Vref, RX VrefLevel [Byte0]: 24
7758 01:18:52.322880 [Byte1]: 24
7759 01:18:52.322971
7760 01:18:52.326712 Set Vref, RX VrefLevel [Byte0]: 25
7761 01:18:52.329958 [Byte1]: 25
7762 01:18:52.330050
7763 01:18:52.333478 Set Vref, RX VrefLevel [Byte0]: 26
7764 01:18:52.336911 [Byte1]: 26
7765 01:18:52.339873
7766 01:18:52.339963 Set Vref, RX VrefLevel [Byte0]: 27
7767 01:18:52.343549 [Byte1]: 27
7768 01:18:52.347645
7769 01:18:52.347744 Set Vref, RX VrefLevel [Byte0]: 28
7770 01:18:52.350936 [Byte1]: 28
7771 01:18:52.355452
7772 01:18:52.355551 Set Vref, RX VrefLevel [Byte0]: 29
7773 01:18:52.358851 [Byte1]: 29
7774 01:18:52.362676
7775 01:18:52.362767 Set Vref, RX VrefLevel [Byte0]: 30
7776 01:18:52.365938 [Byte1]: 30
7777 01:18:52.370275
7778 01:18:52.370408 Set Vref, RX VrefLevel [Byte0]: 31
7779 01:18:52.373974 [Byte1]: 31
7780 01:18:52.377767
7781 01:18:52.377855 Set Vref, RX VrefLevel [Byte0]: 32
7782 01:18:52.381022 [Byte1]: 32
7783 01:18:52.385349
7784 01:18:52.385436 Set Vref, RX VrefLevel [Byte0]: 33
7785 01:18:52.388758 [Byte1]: 33
7786 01:18:52.393346
7787 01:18:52.393439 Set Vref, RX VrefLevel [Byte0]: 34
7788 01:18:52.396635 [Byte1]: 34
7789 01:18:52.400422
7790 01:18:52.400510 Set Vref, RX VrefLevel [Byte0]: 35
7791 01:18:52.403768 [Byte1]: 35
7792 01:18:52.408154
7793 01:18:52.408247 Set Vref, RX VrefLevel [Byte0]: 36
7794 01:18:52.411436 [Byte1]: 36
7795 01:18:52.415479
7796 01:18:52.415566 Set Vref, RX VrefLevel [Byte0]: 37
7797 01:18:52.419379 [Byte1]: 37
7798 01:18:52.423158
7799 01:18:52.423244 Set Vref, RX VrefLevel [Byte0]: 38
7800 01:18:52.426614 [Byte1]: 38
7801 01:18:52.430817
7802 01:18:52.430907 Set Vref, RX VrefLevel [Byte0]: 39
7803 01:18:52.434401 [Byte1]: 39
7804 01:18:52.438246
7805 01:18:52.438386 Set Vref, RX VrefLevel [Byte0]: 40
7806 01:18:52.442005 [Byte1]: 40
7807 01:18:52.446254
7808 01:18:52.446411 Set Vref, RX VrefLevel [Byte0]: 41
7809 01:18:52.449283 [Byte1]: 41
7810 01:18:52.453921
7811 01:18:52.454008 Set Vref, RX VrefLevel [Byte0]: 42
7812 01:18:52.457064 [Byte1]: 42
7813 01:18:52.461238
7814 01:18:52.461331 Set Vref, RX VrefLevel [Byte0]: 43
7815 01:18:52.464611 [Byte1]: 43
7816 01:18:52.469051
7817 01:18:52.469150 Set Vref, RX VrefLevel [Byte0]: 44
7818 01:18:52.472328 [Byte1]: 44
7819 01:18:52.476153
7820 01:18:52.476243 Set Vref, RX VrefLevel [Byte0]: 45
7821 01:18:52.479701 [Byte1]: 45
7822 01:18:52.484236
7823 01:18:52.484333 Set Vref, RX VrefLevel [Byte0]: 46
7824 01:18:52.487530 [Byte1]: 46
7825 01:18:52.491923
7826 01:18:52.492016 Set Vref, RX VrefLevel [Byte0]: 47
7827 01:18:52.494820 [Byte1]: 47
7828 01:18:52.499313
7829 01:18:52.499405 Set Vref, RX VrefLevel [Byte0]: 48
7830 01:18:52.502641 [Byte1]: 48
7831 01:18:52.506489
7832 01:18:52.506577 Set Vref, RX VrefLevel [Byte0]: 49
7833 01:18:52.509742 [Byte1]: 49
7834 01:18:52.514082
7835 01:18:52.514171 Set Vref, RX VrefLevel [Byte0]: 50
7836 01:18:52.517438 [Byte1]: 50
7837 01:18:52.521997
7838 01:18:52.522091 Set Vref, RX VrefLevel [Byte0]: 51
7839 01:18:52.525309 [Byte1]: 51
7840 01:18:52.529332
7841 01:18:52.529423 Set Vref, RX VrefLevel [Byte0]: 52
7842 01:18:52.532974 [Byte1]: 52
7843 01:18:52.537189
7844 01:18:52.537285 Set Vref, RX VrefLevel [Byte0]: 53
7845 01:18:52.540604 [Byte1]: 53
7846 01:18:52.544261
7847 01:18:52.544355 Set Vref, RX VrefLevel [Byte0]: 54
7848 01:18:52.547859 [Byte1]: 54
7849 01:18:52.551866
7850 01:18:52.552023 Set Vref, RX VrefLevel [Byte0]: 55
7851 01:18:52.555329 [Byte1]: 55
7852 01:18:52.559605
7853 01:18:52.559698 Set Vref, RX VrefLevel [Byte0]: 56
7854 01:18:52.562744 [Byte1]: 56
7855 01:18:52.567679
7856 01:18:52.567772 Set Vref, RX VrefLevel [Byte0]: 57
7857 01:18:52.570803 [Byte1]: 57
7858 01:18:52.574775
7859 01:18:52.574870 Set Vref, RX VrefLevel [Byte0]: 58
7860 01:18:52.578618 [Byte1]: 58
7861 01:18:52.582440
7862 01:18:52.582530 Set Vref, RX VrefLevel [Byte0]: 59
7863 01:18:52.585753 [Byte1]: 59
7864 01:18:52.589789
7865 01:18:52.593476 Set Vref, RX VrefLevel [Byte0]: 60
7866 01:18:52.596205 [Byte1]: 60
7867 01:18:52.596295
7868 01:18:52.599732 Set Vref, RX VrefLevel [Byte0]: 61
7869 01:18:52.603143 [Byte1]: 61
7870 01:18:52.603232
7871 01:18:52.606120 Set Vref, RX VrefLevel [Byte0]: 62
7872 01:18:52.610135 [Byte1]: 62
7873 01:18:52.610224
7874 01:18:52.612800 Set Vref, RX VrefLevel [Byte0]: 63
7875 01:18:52.616634 [Byte1]: 63
7876 01:18:52.620217
7877 01:18:52.620308 Set Vref, RX VrefLevel [Byte0]: 64
7878 01:18:52.623586 [Byte1]: 64
7879 01:18:52.628156
7880 01:18:52.628247 Set Vref, RX VrefLevel [Byte0]: 65
7881 01:18:52.631495 [Byte1]: 65
7882 01:18:52.635503
7883 01:18:52.635595 Set Vref, RX VrefLevel [Byte0]: 66
7884 01:18:52.638546 [Byte1]: 66
7885 01:18:52.642869
7886 01:18:52.642963 Set Vref, RX VrefLevel [Byte0]: 67
7887 01:18:52.645999 [Byte1]: 67
7888 01:18:52.650612
7889 01:18:52.650737 Set Vref, RX VrefLevel [Byte0]: 68
7890 01:18:52.653812 [Byte1]: 68
7891 01:18:52.658186
7892 01:18:52.658283 Set Vref, RX VrefLevel [Byte0]: 69
7893 01:18:52.661152 [Byte1]: 69
7894 01:18:52.665810
7895 01:18:52.665905 Set Vref, RX VrefLevel [Byte0]: 70
7896 01:18:52.668780 [Byte1]: 70
7897 01:18:52.673540
7898 01:18:52.673637 Set Vref, RX VrefLevel [Byte0]: 71
7899 01:18:52.676758 [Byte1]: 71
7900 01:18:52.680584
7901 01:18:52.680675 Set Vref, RX VrefLevel [Byte0]: 72
7902 01:18:52.683867 [Byte1]: 72
7903 01:18:52.688185
7904 01:18:52.688278 Set Vref, RX VrefLevel [Byte0]: 73
7905 01:18:52.691493 [Byte1]: 73
7906 01:18:52.696377
7907 01:18:52.696475 Set Vref, RX VrefLevel [Byte0]: 74
7908 01:18:52.699168 [Byte1]: 74
7909 01:18:52.703784
7910 01:18:52.703878 Set Vref, RX VrefLevel [Byte0]: 75
7911 01:18:52.706524 [Byte1]: 75
7912 01:18:52.711507
7913 01:18:52.711601 Final RX Vref Byte 0 = 59 to rank0
7914 01:18:52.714477 Final RX Vref Byte 1 = 61 to rank0
7915 01:18:52.717656 Final RX Vref Byte 0 = 59 to rank1
7916 01:18:52.721626 Final RX Vref Byte 1 = 61 to rank1==
7917 01:18:52.724572 Dram Type= 6, Freq= 0, CH_0, rank 0
7918 01:18:52.727720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7919 01:18:52.731197 ==
7920 01:18:52.731288 DQS Delay:
7921 01:18:52.731353 DQS0 = 0, DQS1 = 0
7922 01:18:52.734990 DQM Delay:
7923 01:18:52.735073 DQM0 = 134, DQM1 = 127
7924 01:18:52.738276 DQ Delay:
7925 01:18:52.741492 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7926 01:18:52.744365 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =140
7927 01:18:52.748091 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7928 01:18:52.751080 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7929 01:18:52.751171
7930 01:18:52.751237
7931 01:18:52.751295
7932 01:18:52.754240 [DramC_TX_OE_Calibration] TA2
7933 01:18:52.757473 Original DQ_B0 (3 6) =30, OEN = 27
7934 01:18:52.761243 Original DQ_B1 (3 6) =30, OEN = 27
7935 01:18:52.764413 24, 0x0, End_B0=24 End_B1=24
7936 01:18:52.764502 25, 0x0, End_B0=25 End_B1=25
7937 01:18:52.767553 26, 0x0, End_B0=26 End_B1=26
7938 01:18:52.771200 27, 0x0, End_B0=27 End_B1=27
7939 01:18:52.774216 28, 0x0, End_B0=28 End_B1=28
7940 01:18:52.774335 29, 0x0, End_B0=29 End_B1=29
7941 01:18:52.777249 30, 0x0, End_B0=30 End_B1=30
7942 01:18:52.781025 31, 0x4141, End_B0=30 End_B1=30
7943 01:18:52.784206 Byte0 end_step=30 best_step=27
7944 01:18:52.787657 Byte1 end_step=30 best_step=27
7945 01:18:52.790950 Byte0 TX OE(2T, 0.5T) = (3, 3)
7946 01:18:52.791038 Byte1 TX OE(2T, 0.5T) = (3, 3)
7947 01:18:52.794212
7948 01:18:52.794320
7949 01:18:52.800659 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7950 01:18:52.803935 CH0 RK0: MR19=303, MR18=2622
7951 01:18:52.810839 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
7952 01:18:52.810943
7953 01:18:52.814306 ----->DramcWriteLeveling(PI) begin...
7954 01:18:52.814420 ==
7955 01:18:52.817725 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 01:18:52.820878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 01:18:52.820972 ==
7958 01:18:52.823824 Write leveling (Byte 0): 36 => 36
7959 01:18:52.827544 Write leveling (Byte 1): 26 => 26
7960 01:18:52.830311 DramcWriteLeveling(PI) end<-----
7961 01:18:52.830415
7962 01:18:52.830479 ==
7963 01:18:52.833735 Dram Type= 6, Freq= 0, CH_0, rank 1
7964 01:18:52.837017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7965 01:18:52.837104 ==
7966 01:18:52.840420 [Gating] SW mode calibration
7967 01:18:52.846953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7968 01:18:52.853497 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7969 01:18:52.857307 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7970 01:18:52.863297 1 4 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7971 01:18:52.867134 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7972 01:18:52.870237 1 4 12 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7973 01:18:52.876712 1 4 16 | B1->B0 | 2e2e 3b3a | 1 1 | (1 1) (1 1)
7974 01:18:52.880048 1 4 20 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7975 01:18:52.883160 1 4 24 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
7976 01:18:52.889981 1 4 28 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7977 01:18:52.893252 1 5 0 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
7978 01:18:52.896444 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7979 01:18:52.900298 1 5 8 | B1->B0 | 3434 3837 | 1 1 | (1 0) (0 0)
7980 01:18:52.906405 1 5 12 | B1->B0 | 3434 3635 | 1 1 | (1 0) (0 1)
7981 01:18:52.909647 1 5 16 | B1->B0 | 2e2e 3131 | 0 0 | (0 1) (0 1)
7982 01:18:52.912946 1 5 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7983 01:18:52.919584 1 5 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7984 01:18:52.922996 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7985 01:18:52.926276 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7986 01:18:52.933149 1 6 4 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (1 1)
7987 01:18:52.936157 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7988 01:18:52.939649 1 6 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7989 01:18:52.946308 1 6 16 | B1->B0 | 3c3b 4545 | 1 0 | (0 0) (0 0)
7990 01:18:52.949683 1 6 20 | B1->B0 | 4646 4646 | 0 1 | (0 0) (0 0)
7991 01:18:52.953016 1 6 24 | B1->B0 | 4646 4646 | 0 1 | (0 0) (0 0)
7992 01:18:52.959519 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7993 01:18:52.962810 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 01:18:52.966034 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 01:18:52.972914 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 01:18:52.976237 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 01:18:52.979510 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7998 01:18:52.986019 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 01:18:52.989179 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 01:18:52.992788 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 01:18:52.999143 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 01:18:53.002285 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 01:18:53.005724 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 01:18:53.012762 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 01:18:53.016209 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 01:18:53.019331 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 01:18:53.025849 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 01:18:53.029095 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 01:18:53.032533 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 01:18:53.039460 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 01:18:53.042618 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 01:18:53.045823 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8013 01:18:53.052355 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8014 01:18:53.055551 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 01:18:53.059040 Total UI for P1: 0, mck2ui 16
8016 01:18:53.062436 best dqsien dly found for B0: ( 1, 9, 14)
8017 01:18:53.066194 Total UI for P1: 0, mck2ui 16
8018 01:18:53.069180 best dqsien dly found for B1: ( 1, 9, 14)
8019 01:18:53.072112 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8020 01:18:53.075414 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8021 01:18:53.075500
8022 01:18:53.079288 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8023 01:18:53.082252 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8024 01:18:53.085258 [Gating] SW calibration Done
8025 01:18:53.085344 ==
8026 01:18:53.088876 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 01:18:53.092157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 01:18:53.092244 ==
8029 01:18:53.095401 RX Vref Scan: 0
8030 01:18:53.095486
8031 01:18:53.099040 RX Vref 0 -> 0, step: 1
8032 01:18:53.099136
8033 01:18:53.099200 RX Delay 0 -> 252, step: 8
8034 01:18:53.105776 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8035 01:18:53.108636 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8036 01:18:53.112221 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8037 01:18:53.115769 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8038 01:18:53.118617 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8039 01:18:53.125136 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8040 01:18:53.129188 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8041 01:18:53.131720 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8042 01:18:53.135610 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8043 01:18:53.138756 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8044 01:18:53.145103 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8045 01:18:53.148171 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8046 01:18:53.151931 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8047 01:18:53.155220 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8048 01:18:53.161704 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8049 01:18:53.164932 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8050 01:18:53.165023 ==
8051 01:18:53.168528 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 01:18:53.171475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 01:18:53.171565 ==
8054 01:18:53.174717 DQS Delay:
8055 01:18:53.174829 DQS0 = 0, DQS1 = 0
8056 01:18:53.174917 DQM Delay:
8057 01:18:53.178343 DQM0 = 137, DQM1 = 130
8058 01:18:53.178441 DQ Delay:
8059 01:18:53.181748 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8060 01:18:53.185076 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8061 01:18:53.188244 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8062 01:18:53.195041 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8063 01:18:53.195157
8064 01:18:53.195222
8065 01:18:53.195282 ==
8066 01:18:53.197832 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 01:18:53.201910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 01:18:53.201999 ==
8069 01:18:53.202064
8070 01:18:53.202124
8071 01:18:53.205000 TX Vref Scan disable
8072 01:18:53.205084 == TX Byte 0 ==
8073 01:18:53.211208 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8074 01:18:53.214623 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8075 01:18:53.214748 == TX Byte 1 ==
8076 01:18:53.221475 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8077 01:18:53.224382 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8078 01:18:53.224502 ==
8079 01:18:53.228153 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 01:18:53.231214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 01:18:53.231304 ==
8082 01:18:53.246215
8083 01:18:53.249962 TX Vref early break, caculate TX vref
8084 01:18:53.253180 TX Vref=16, minBit 1, minWin=23, winSum=385
8085 01:18:53.256263 TX Vref=18, minBit 1, minWin=23, winSum=394
8086 01:18:53.259562 TX Vref=20, minBit 1, minWin=24, winSum=402
8087 01:18:53.263480 TX Vref=22, minBit 3, minWin=24, winSum=414
8088 01:18:53.266739 TX Vref=24, minBit 1, minWin=25, winSum=419
8089 01:18:53.273360 TX Vref=26, minBit 3, minWin=25, winSum=425
8090 01:18:53.276498 TX Vref=28, minBit 3, minWin=25, winSum=423
8091 01:18:53.279494 TX Vref=30, minBit 0, minWin=25, winSum=417
8092 01:18:53.282783 TX Vref=32, minBit 0, minWin=24, winSum=414
8093 01:18:53.286227 TX Vref=34, minBit 0, minWin=23, winSum=401
8094 01:18:53.292823 [TxChooseVref] Worse bit 3, Min win 25, Win sum 425, Final Vref 26
8095 01:18:53.292941
8096 01:18:53.296291 Final TX Range 0 Vref 26
8097 01:18:53.296383
8098 01:18:53.296448 ==
8099 01:18:53.299349 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 01:18:53.302844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 01:18:53.302932 ==
8102 01:18:53.302997
8103 01:18:53.303056
8104 01:18:53.306055 TX Vref Scan disable
8105 01:18:53.312698 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8106 01:18:53.312806 == TX Byte 0 ==
8107 01:18:53.316534 u2DelayCellOfst[0]=13 cells (4 PI)
8108 01:18:53.319756 u2DelayCellOfst[1]=17 cells (5 PI)
8109 01:18:53.323267 u2DelayCellOfst[2]=13 cells (4 PI)
8110 01:18:53.326307 u2DelayCellOfst[3]=10 cells (3 PI)
8111 01:18:53.329525 u2DelayCellOfst[4]=10 cells (3 PI)
8112 01:18:53.332625 u2DelayCellOfst[5]=0 cells (0 PI)
8113 01:18:53.336136 u2DelayCellOfst[6]=17 cells (5 PI)
8114 01:18:53.339517 u2DelayCellOfst[7]=17 cells (5 PI)
8115 01:18:53.342872 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8116 01:18:53.345784 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8117 01:18:53.349284 == TX Byte 1 ==
8118 01:18:53.349378 u2DelayCellOfst[8]=3 cells (1 PI)
8119 01:18:53.352617 u2DelayCellOfst[9]=0 cells (0 PI)
8120 01:18:53.356514 u2DelayCellOfst[10]=6 cells (2 PI)
8121 01:18:53.359240 u2DelayCellOfst[11]=6 cells (2 PI)
8122 01:18:53.362539 u2DelayCellOfst[12]=10 cells (3 PI)
8123 01:18:53.365678 u2DelayCellOfst[13]=13 cells (4 PI)
8124 01:18:53.369173 u2DelayCellOfst[14]=17 cells (5 PI)
8125 01:18:53.372355 u2DelayCellOfst[15]=10 cells (3 PI)
8126 01:18:53.375630 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8127 01:18:53.382525 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8128 01:18:53.382638 DramC Write-DBI on
8129 01:18:53.382706 ==
8130 01:18:53.385688 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 01:18:53.389211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 01:18:53.392215 ==
8133 01:18:53.392364
8134 01:18:53.392482
8135 01:18:53.392594 TX Vref Scan disable
8136 01:18:53.395769 == TX Byte 0 ==
8137 01:18:53.399105 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8138 01:18:53.402944 == TX Byte 1 ==
8139 01:18:53.406242 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8140 01:18:53.409360 DramC Write-DBI off
8141 01:18:53.409451
8142 01:18:53.409516 [DATLAT]
8143 01:18:53.409575 Freq=1600, CH0 RK1
8144 01:18:53.409633
8145 01:18:53.412673 DATLAT Default: 0xf
8146 01:18:53.416071 0, 0xFFFF, sum = 0
8147 01:18:53.416161 1, 0xFFFF, sum = 0
8148 01:18:53.419393 2, 0xFFFF, sum = 0
8149 01:18:53.419479 3, 0xFFFF, sum = 0
8150 01:18:53.422409 4, 0xFFFF, sum = 0
8151 01:18:53.422495 5, 0xFFFF, sum = 0
8152 01:18:53.425425 6, 0xFFFF, sum = 0
8153 01:18:53.425512 7, 0xFFFF, sum = 0
8154 01:18:53.428901 8, 0xFFFF, sum = 0
8155 01:18:53.428988 9, 0xFFFF, sum = 0
8156 01:18:53.432096 10, 0xFFFF, sum = 0
8157 01:18:53.432181 11, 0xFFFF, sum = 0
8158 01:18:53.435451 12, 0xFFFF, sum = 0
8159 01:18:53.435537 13, 0xFFFF, sum = 0
8160 01:18:53.438723 14, 0x0, sum = 1
8161 01:18:53.438808 15, 0x0, sum = 2
8162 01:18:53.442534 16, 0x0, sum = 3
8163 01:18:53.442621 17, 0x0, sum = 4
8164 01:18:53.445770 best_step = 15
8165 01:18:53.445856
8166 01:18:53.445920 ==
8167 01:18:53.449180 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 01:18:53.452304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 01:18:53.452396 ==
8170 01:18:53.455547 RX Vref Scan: 0
8171 01:18:53.455634
8172 01:18:53.455698 RX Vref 0 -> 0, step: 1
8173 01:18:53.455758
8174 01:18:53.458943 RX Delay 19 -> 252, step: 4
8175 01:18:53.465272 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8176 01:18:53.469099 iDelay=191, Bit 1, Center 136 (91 ~ 182) 92
8177 01:18:53.472263 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8178 01:18:53.475612 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8179 01:18:53.478870 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8180 01:18:53.482222 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8181 01:18:53.488570 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8182 01:18:53.492176 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8183 01:18:53.495186 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8184 01:18:53.498500 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8185 01:18:53.502157 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8186 01:18:53.508691 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8187 01:18:53.511965 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8188 01:18:53.515211 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8189 01:18:53.518524 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8190 01:18:53.525600 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8191 01:18:53.525707 ==
8192 01:18:53.528582 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 01:18:53.531723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 01:18:53.531811 ==
8195 01:18:53.531876 DQS Delay:
8196 01:18:53.535138 DQS0 = 0, DQS1 = 0
8197 01:18:53.535222 DQM Delay:
8198 01:18:53.538252 DQM0 = 134, DQM1 = 127
8199 01:18:53.538402 DQ Delay:
8200 01:18:53.541643 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8201 01:18:53.544891 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8202 01:18:53.548173 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8203 01:18:53.551403 DQ12 =134, DQ13 =132, DQ14 =136, DQ15 =134
8204 01:18:53.551494
8205 01:18:53.551559
8206 01:18:53.555458
8207 01:18:53.555546 [DramC_TX_OE_Calibration] TA2
8208 01:18:53.558576 Original DQ_B0 (3 6) =30, OEN = 27
8209 01:18:53.561922 Original DQ_B1 (3 6) =30, OEN = 27
8210 01:18:53.565117 24, 0x0, End_B0=24 End_B1=24
8211 01:18:53.568286 25, 0x0, End_B0=25 End_B1=25
8212 01:18:53.568377 26, 0x0, End_B0=26 End_B1=26
8213 01:18:53.571373 27, 0x0, End_B0=27 End_B1=27
8214 01:18:53.574610 28, 0x0, End_B0=28 End_B1=28
8215 01:18:53.578177 29, 0x0, End_B0=29 End_B1=29
8216 01:18:53.581268 30, 0x0, End_B0=30 End_B1=30
8217 01:18:53.584423 31, 0x4141, End_B0=30 End_B1=30
8218 01:18:53.584513 Byte0 end_step=30 best_step=27
8219 01:18:53.587985 Byte1 end_step=30 best_step=27
8220 01:18:53.591148 Byte0 TX OE(2T, 0.5T) = (3, 3)
8221 01:18:53.594292 Byte1 TX OE(2T, 0.5T) = (3, 3)
8222 01:18:53.594387
8223 01:18:53.594453
8224 01:18:53.601486 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8225 01:18:53.604343 CH0 RK1: MR19=303, MR18=1E07
8226 01:18:53.611428 CH0_RK1: MR19=0x303, MR18=0x1E07, DQSOSC=394, MR23=63, INC=23, DEC=15
8227 01:18:53.614679 [RxdqsGatingPostProcess] freq 1600
8228 01:18:53.621014 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8229 01:18:53.624279 best DQS0 dly(2T, 0.5T) = (1, 1)
8230 01:18:53.624370 best DQS1 dly(2T, 0.5T) = (1, 1)
8231 01:18:53.627641 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8232 01:18:53.630841 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8233 01:18:53.634147 best DQS0 dly(2T, 0.5T) = (1, 1)
8234 01:18:53.637862 best DQS1 dly(2T, 0.5T) = (1, 1)
8235 01:18:53.640985 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8236 01:18:53.644349 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8237 01:18:53.647683 Pre-setting of DQS Precalculation
8238 01:18:53.654294 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8239 01:18:53.654440 ==
8240 01:18:53.657145 Dram Type= 6, Freq= 0, CH_1, rank 0
8241 01:18:53.660903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 01:18:53.660990 ==
8243 01:18:53.667273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8244 01:18:53.670338 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8245 01:18:53.673815 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8246 01:18:53.680797 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8247 01:18:53.689381 [CA 0] Center 42 (13~72) winsize 60
8248 01:18:53.692599 [CA 1] Center 42 (13~72) winsize 60
8249 01:18:53.695565 [CA 2] Center 39 (10~68) winsize 59
8250 01:18:53.699020 [CA 3] Center 38 (9~67) winsize 59
8251 01:18:53.702513 [CA 4] Center 38 (9~68) winsize 60
8252 01:18:53.705706 [CA 5] Center 37 (8~67) winsize 60
8253 01:18:53.705791
8254 01:18:53.708794 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8255 01:18:53.708877
8256 01:18:53.711993 [CATrainingPosCal] consider 1 rank data
8257 01:18:53.715483 u2DelayCellTimex100 = 285/100 ps
8258 01:18:53.718775 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8259 01:18:53.725898 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8260 01:18:53.728873 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8261 01:18:53.731954 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8262 01:18:53.735441 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8263 01:18:53.738907 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8264 01:18:53.738996
8265 01:18:53.742069 CA PerBit enable=1, Macro0, CA PI delay=37
8266 01:18:53.742154
8267 01:18:53.745609 [CBTSetCACLKResult] CA Dly = 37
8268 01:18:53.748830 CS Dly: 11 (0~42)
8269 01:18:53.752550 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8270 01:18:53.755776 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8271 01:18:53.755868 ==
8272 01:18:53.758591 Dram Type= 6, Freq= 0, CH_1, rank 1
8273 01:18:53.762260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 01:18:53.765709 ==
8275 01:18:53.768907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8276 01:18:53.772121 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8277 01:18:53.778590 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8278 01:18:53.785289 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8279 01:18:53.792295 [CA 0] Center 41 (12~71) winsize 60
8280 01:18:53.795821 [CA 1] Center 42 (12~72) winsize 61
8281 01:18:53.799179 [CA 2] Center 38 (9~68) winsize 60
8282 01:18:53.802264 [CA 3] Center 38 (8~68) winsize 61
8283 01:18:53.805915 [CA 4] Center 38 (8~68) winsize 61
8284 01:18:53.809224 [CA 5] Center 37 (7~67) winsize 61
8285 01:18:53.809314
8286 01:18:53.812420 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8287 01:18:53.812504
8288 01:18:53.815794 [CATrainingPosCal] consider 2 rank data
8289 01:18:53.818915 u2DelayCellTimex100 = 285/100 ps
8290 01:18:53.822107 CA0 delay=42 (13~71),Diff = 5 PI (17 cell)
8291 01:18:53.828915 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8292 01:18:53.832526 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8293 01:18:53.835853 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8294 01:18:53.839094 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8295 01:18:53.842271 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8296 01:18:53.842392
8297 01:18:53.845442 CA PerBit enable=1, Macro0, CA PI delay=37
8298 01:18:53.845527
8299 01:18:53.848779 [CBTSetCACLKResult] CA Dly = 37
8300 01:18:53.852455 CS Dly: 12 (0~45)
8301 01:18:53.855750 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8302 01:18:53.859209 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8303 01:18:53.859302
8304 01:18:53.861851 ----->DramcWriteLeveling(PI) begin...
8305 01:18:53.861935 ==
8306 01:18:53.865394 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 01:18:53.868599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 01:18:53.872169 ==
8309 01:18:53.872265 Write leveling (Byte 0): 25 => 25
8310 01:18:53.875417 Write leveling (Byte 1): 26 => 26
8311 01:18:53.878446 DramcWriteLeveling(PI) end<-----
8312 01:18:53.878540
8313 01:18:53.878605 ==
8314 01:18:53.882328 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 01:18:53.888999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 01:18:53.889135 ==
8317 01:18:53.892276 [Gating] SW mode calibration
8318 01:18:53.898693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8319 01:18:53.902329 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8320 01:18:53.908646 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 01:18:53.912268 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 01:18:53.915391 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8323 01:18:53.921786 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8324 01:18:53.925555 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 01:18:53.928786 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 01:18:53.931912 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 01:18:53.938658 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 01:18:53.941979 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 01:18:53.945331 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 01:18:53.951612 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8331 01:18:53.955110 1 5 12 | B1->B0 | 2d2d 2323 | 1 0 | (0 1) (1 0)
8332 01:18:53.958233 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 01:18:53.965126 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 01:18:53.968678 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 01:18:53.971477 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 01:18:53.978457 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 01:18:53.981291 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 01:18:53.984757 1 6 8 | B1->B0 | 2525 3737 | 0 1 | (0 0) (0 0)
8339 01:18:53.991346 1 6 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
8340 01:18:53.994752 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 01:18:53.997933 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 01:18:54.004511 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 01:18:54.008154 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 01:18:54.011137 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 01:18:54.018123 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 01:18:54.021124 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8347 01:18:54.024937 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8348 01:18:54.031260 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8349 01:18:54.034474 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 01:18:54.037657 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 01:18:54.044411 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 01:18:54.047537 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 01:18:54.051516 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 01:18:54.057819 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 01:18:54.060965 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 01:18:54.064639 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 01:18:54.071198 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 01:18:54.074476 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 01:18:54.077376 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 01:18:54.084484 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 01:18:54.087893 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 01:18:54.090926 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8363 01:18:54.097237 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8364 01:18:54.100947 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 01:18:54.104355 Total UI for P1: 0, mck2ui 16
8366 01:18:54.107244 best dqsien dly found for B0: ( 1, 9, 10)
8367 01:18:54.110573 Total UI for P1: 0, mck2ui 16
8368 01:18:54.113832 best dqsien dly found for B1: ( 1, 9, 10)
8369 01:18:54.117536 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8370 01:18:54.120435 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8371 01:18:54.120562
8372 01:18:54.124472 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8373 01:18:54.127631 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8374 01:18:54.130502 [Gating] SW calibration Done
8375 01:18:54.130598 ==
8376 01:18:54.134199 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 01:18:54.137171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 01:18:54.141186 ==
8379 01:18:54.141303 RX Vref Scan: 0
8380 01:18:54.141372
8381 01:18:54.144285 RX Vref 0 -> 0, step: 1
8382 01:18:54.144374
8383 01:18:54.144438 RX Delay 0 -> 252, step: 8
8384 01:18:54.150498 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8385 01:18:54.153776 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8386 01:18:54.156946 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8387 01:18:54.160553 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8388 01:18:54.164195 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8389 01:18:54.170584 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8390 01:18:54.173834 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8391 01:18:54.177186 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8392 01:18:54.180375 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8393 01:18:54.183680 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8394 01:18:54.190288 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8395 01:18:54.193943 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8396 01:18:54.196893 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8397 01:18:54.199967 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8398 01:18:54.206606 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8399 01:18:54.209984 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8400 01:18:54.210099 ==
8401 01:18:54.213774 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 01:18:54.216865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 01:18:54.216973 ==
8404 01:18:54.217038 DQS Delay:
8405 01:18:54.220198 DQS0 = 0, DQS1 = 0
8406 01:18:54.220301 DQM Delay:
8407 01:18:54.223415 DQM0 = 136, DQM1 = 132
8408 01:18:54.223511 DQ Delay:
8409 01:18:54.227256 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8410 01:18:54.230201 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8411 01:18:54.233618 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8412 01:18:54.240289 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8413 01:18:54.240428
8414 01:18:54.240492
8415 01:18:54.240551 ==
8416 01:18:54.243465 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 01:18:54.246739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 01:18:54.246846 ==
8419 01:18:54.246911
8420 01:18:54.246970
8421 01:18:54.249774 TX Vref Scan disable
8422 01:18:54.249871 == TX Byte 0 ==
8423 01:18:54.256689 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8424 01:18:54.259869 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8425 01:18:54.259989 == TX Byte 1 ==
8426 01:18:54.266579 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8427 01:18:54.269772 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8428 01:18:54.269880 ==
8429 01:18:54.272944 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 01:18:54.276563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 01:18:54.276673 ==
8432 01:18:54.289770
8433 01:18:54.292931 TX Vref early break, caculate TX vref
8434 01:18:54.296889 TX Vref=16, minBit 0, minWin=23, winSum=382
8435 01:18:54.299622 TX Vref=18, minBit 1, minWin=23, winSum=389
8436 01:18:54.303024 TX Vref=20, minBit 0, minWin=23, winSum=397
8437 01:18:54.306120 TX Vref=22, minBit 6, minWin=23, winSum=407
8438 01:18:54.309975 TX Vref=24, minBit 0, minWin=25, winSum=416
8439 01:18:54.316488 TX Vref=26, minBit 0, minWin=25, winSum=423
8440 01:18:54.319593 TX Vref=28, minBit 2, minWin=25, winSum=429
8441 01:18:54.322787 TX Vref=30, minBit 0, minWin=25, winSum=423
8442 01:18:54.326359 TX Vref=32, minBit 2, minWin=24, winSum=414
8443 01:18:54.330098 TX Vref=34, minBit 0, minWin=24, winSum=405
8444 01:18:54.336188 [TxChooseVref] Worse bit 2, Min win 25, Win sum 429, Final Vref 28
8445 01:18:54.336369
8446 01:18:54.339775 Final TX Range 0 Vref 28
8447 01:18:54.339877
8448 01:18:54.339940 ==
8449 01:18:54.342666 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 01:18:54.346177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 01:18:54.346362 ==
8452 01:18:54.346435
8453 01:18:54.346495
8454 01:18:54.349386 TX Vref Scan disable
8455 01:18:54.356636 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8456 01:18:54.356782 == TX Byte 0 ==
8457 01:18:54.359568 u2DelayCellOfst[0]=20 cells (6 PI)
8458 01:18:54.362691 u2DelayCellOfst[1]=13 cells (4 PI)
8459 01:18:54.366109 u2DelayCellOfst[2]=0 cells (0 PI)
8460 01:18:54.369460 u2DelayCellOfst[3]=10 cells (3 PI)
8461 01:18:54.372773 u2DelayCellOfst[4]=10 cells (3 PI)
8462 01:18:54.376126 u2DelayCellOfst[5]=20 cells (6 PI)
8463 01:18:54.379196 u2DelayCellOfst[6]=23 cells (7 PI)
8464 01:18:54.382880 u2DelayCellOfst[7]=10 cells (3 PI)
8465 01:18:54.386161 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8466 01:18:54.389541 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8467 01:18:54.392850 == TX Byte 1 ==
8468 01:18:54.392960 u2DelayCellOfst[8]=0 cells (0 PI)
8469 01:18:54.396135 u2DelayCellOfst[9]=3 cells (1 PI)
8470 01:18:54.399355 u2DelayCellOfst[10]=13 cells (4 PI)
8471 01:18:54.402656 u2DelayCellOfst[11]=6 cells (2 PI)
8472 01:18:54.405820 u2DelayCellOfst[12]=17 cells (5 PI)
8473 01:18:54.409085 u2DelayCellOfst[13]=17 cells (5 PI)
8474 01:18:54.413204 u2DelayCellOfst[14]=20 cells (6 PI)
8475 01:18:54.415890 u2DelayCellOfst[15]=17 cells (5 PI)
8476 01:18:54.419110 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8477 01:18:54.425875 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8478 01:18:54.426014 DramC Write-DBI on
8479 01:18:54.426083 ==
8480 01:18:54.428981 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 01:18:54.432624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 01:18:54.435967 ==
8483 01:18:54.436076
8484 01:18:54.436142
8485 01:18:54.436202 TX Vref Scan disable
8486 01:18:54.439020 == TX Byte 0 ==
8487 01:18:54.442508 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8488 01:18:54.446015 == TX Byte 1 ==
8489 01:18:54.449380 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8490 01:18:54.452605 DramC Write-DBI off
8491 01:18:54.452719
8492 01:18:54.452783 [DATLAT]
8493 01:18:54.452842 Freq=1600, CH1 RK0
8494 01:18:54.452899
8495 01:18:54.455898 DATLAT Default: 0xf
8496 01:18:54.455988 0, 0xFFFF, sum = 0
8497 01:18:54.459069 1, 0xFFFF, sum = 0
8498 01:18:54.462490 2, 0xFFFF, sum = 0
8499 01:18:54.462599 3, 0xFFFF, sum = 0
8500 01:18:54.465638 4, 0xFFFF, sum = 0
8501 01:18:54.465731 5, 0xFFFF, sum = 0
8502 01:18:54.469120 6, 0xFFFF, sum = 0
8503 01:18:54.469218 7, 0xFFFF, sum = 0
8504 01:18:54.472225 8, 0xFFFF, sum = 0
8505 01:18:54.472324 9, 0xFFFF, sum = 0
8506 01:18:54.475674 10, 0xFFFF, sum = 0
8507 01:18:54.475792 11, 0xFFFF, sum = 0
8508 01:18:54.478921 12, 0xFFFF, sum = 0
8509 01:18:54.479018 13, 0xFFFF, sum = 0
8510 01:18:54.482299 14, 0x0, sum = 1
8511 01:18:54.482412 15, 0x0, sum = 2
8512 01:18:54.485743 16, 0x0, sum = 3
8513 01:18:54.485842 17, 0x0, sum = 4
8514 01:18:54.488775 best_step = 15
8515 01:18:54.488871
8516 01:18:54.488935 ==
8517 01:18:54.492136 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 01:18:54.495525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 01:18:54.495626 ==
8520 01:18:54.498825 RX Vref Scan: 1
8521 01:18:54.498917
8522 01:18:54.498983 Set Vref Range= 24 -> 127
8523 01:18:54.499042
8524 01:18:54.502243 RX Vref 24 -> 127, step: 1
8525 01:18:54.502371
8526 01:18:54.505285 RX Delay 27 -> 252, step: 4
8527 01:18:54.505372
8528 01:18:54.508650 Set Vref, RX VrefLevel [Byte0]: 24
8529 01:18:54.512519 [Byte1]: 24
8530 01:18:54.512625
8531 01:18:54.515819 Set Vref, RX VrefLevel [Byte0]: 25
8532 01:18:54.518986 [Byte1]: 25
8533 01:18:54.519087
8534 01:18:54.522163 Set Vref, RX VrefLevel [Byte0]: 26
8535 01:18:54.525520 [Byte1]: 26
8536 01:18:54.529592
8537 01:18:54.529705 Set Vref, RX VrefLevel [Byte0]: 27
8538 01:18:54.532573 [Byte1]: 27
8539 01:18:54.536822
8540 01:18:54.536934 Set Vref, RX VrefLevel [Byte0]: 28
8541 01:18:54.540295 [Byte1]: 28
8542 01:18:54.544226
8543 01:18:54.544339 Set Vref, RX VrefLevel [Byte0]: 29
8544 01:18:54.547459 [Byte1]: 29
8545 01:18:54.552228
8546 01:18:54.552358 Set Vref, RX VrefLevel [Byte0]: 30
8547 01:18:54.555454 [Byte1]: 30
8548 01:18:54.559299
8549 01:18:54.559423 Set Vref, RX VrefLevel [Byte0]: 31
8550 01:18:54.562964 [Byte1]: 31
8551 01:18:54.566732
8552 01:18:54.566844 Set Vref, RX VrefLevel [Byte0]: 32
8553 01:18:54.570368 [Byte1]: 32
8554 01:18:54.574587
8555 01:18:54.574704 Set Vref, RX VrefLevel [Byte0]: 33
8556 01:18:54.577485 [Byte1]: 33
8557 01:18:54.581994
8558 01:18:54.582111 Set Vref, RX VrefLevel [Byte0]: 34
8559 01:18:54.585137 [Byte1]: 34
8560 01:18:54.589452
8561 01:18:54.589566 Set Vref, RX VrefLevel [Byte0]: 35
8562 01:18:54.592854 [Byte1]: 35
8563 01:18:54.597241
8564 01:18:54.597363 Set Vref, RX VrefLevel [Byte0]: 36
8565 01:18:54.600429 [Byte1]: 36
8566 01:18:54.604356
8567 01:18:54.604472 Set Vref, RX VrefLevel [Byte0]: 37
8568 01:18:54.607844 [Byte1]: 37
8569 01:18:54.612465
8570 01:18:54.612600 Set Vref, RX VrefLevel [Byte0]: 38
8571 01:18:54.615768 [Byte1]: 38
8572 01:18:54.619884
8573 01:18:54.620000 Set Vref, RX VrefLevel [Byte0]: 39
8574 01:18:54.622989 [Byte1]: 39
8575 01:18:54.627662
8576 01:18:54.627782 Set Vref, RX VrefLevel [Byte0]: 40
8577 01:18:54.630326 [Byte1]: 40
8578 01:18:54.634954
8579 01:18:54.635066 Set Vref, RX VrefLevel [Byte0]: 41
8580 01:18:54.638120 [Byte1]: 41
8581 01:18:54.642095
8582 01:18:54.642202 Set Vref, RX VrefLevel [Byte0]: 42
8583 01:18:54.645338 [Byte1]: 42
8584 01:18:54.649916
8585 01:18:54.650056 Set Vref, RX VrefLevel [Byte0]: 43
8586 01:18:54.652973 [Byte1]: 43
8587 01:18:54.657485
8588 01:18:54.657608 Set Vref, RX VrefLevel [Byte0]: 44
8589 01:18:54.660828 [Byte1]: 44
8590 01:18:54.664743
8591 01:18:54.664856 Set Vref, RX VrefLevel [Byte0]: 45
8592 01:18:54.668073 [Byte1]: 45
8593 01:18:54.672340
8594 01:18:54.672454 Set Vref, RX VrefLevel [Byte0]: 46
8595 01:18:54.675405 [Byte1]: 46
8596 01:18:54.679974
8597 01:18:54.680094 Set Vref, RX VrefLevel [Byte0]: 47
8598 01:18:54.683633 [Byte1]: 47
8599 01:18:54.687476
8600 01:18:54.687585 Set Vref, RX VrefLevel [Byte0]: 48
8601 01:18:54.690554 [Byte1]: 48
8602 01:18:54.694891
8603 01:18:54.695014 Set Vref, RX VrefLevel [Byte0]: 49
8604 01:18:54.698101 [Byte1]: 49
8605 01:18:54.702737
8606 01:18:54.702863 Set Vref, RX VrefLevel [Byte0]: 50
8607 01:18:54.706008 [Byte1]: 50
8608 01:18:54.710389
8609 01:18:54.710501 Set Vref, RX VrefLevel [Byte0]: 51
8610 01:18:54.713224 [Byte1]: 51
8611 01:18:54.717509
8612 01:18:54.717624 Set Vref, RX VrefLevel [Byte0]: 52
8613 01:18:54.721177 [Byte1]: 52
8614 01:18:54.725282
8615 01:18:54.725403 Set Vref, RX VrefLevel [Byte0]: 53
8616 01:18:54.728377 [Byte1]: 53
8617 01:18:54.732916
8618 01:18:54.733036 Set Vref, RX VrefLevel [Byte0]: 54
8619 01:18:54.736204 [Byte1]: 54
8620 01:18:54.740179
8621 01:18:54.740301 Set Vref, RX VrefLevel [Byte0]: 55
8622 01:18:54.743333 [Byte1]: 55
8623 01:18:54.747876
8624 01:18:54.747997 Set Vref, RX VrefLevel [Byte0]: 56
8625 01:18:54.751033 [Byte1]: 56
8626 01:18:54.755579
8627 01:18:54.755741 Set Vref, RX VrefLevel [Byte0]: 57
8628 01:18:54.758735 [Byte1]: 57
8629 01:18:54.762821
8630 01:18:54.762942 Set Vref, RX VrefLevel [Byte0]: 58
8631 01:18:54.766024 [Byte1]: 58
8632 01:18:54.770092
8633 01:18:54.770205 Set Vref, RX VrefLevel [Byte0]: 59
8634 01:18:54.773712 [Byte1]: 59
8635 01:18:54.778122
8636 01:18:54.778276 Set Vref, RX VrefLevel [Byte0]: 60
8637 01:18:54.780987 [Byte1]: 60
8638 01:18:54.785860
8639 01:18:54.786018 Set Vref, RX VrefLevel [Byte0]: 61
8640 01:18:54.788581 [Byte1]: 61
8641 01:18:54.792928
8642 01:18:54.793080 Set Vref, RX VrefLevel [Byte0]: 62
8643 01:18:54.796072 [Byte1]: 62
8644 01:18:54.800513
8645 01:18:54.800660 Set Vref, RX VrefLevel [Byte0]: 63
8646 01:18:54.803598 [Byte1]: 63
8647 01:18:54.807768
8648 01:18:54.807914 Set Vref, RX VrefLevel [Byte0]: 64
8649 01:18:54.811764 [Byte1]: 64
8650 01:18:54.815501
8651 01:18:54.815639 Set Vref, RX VrefLevel [Byte0]: 65
8652 01:18:54.818657 [Byte1]: 65
8653 01:18:54.823383
8654 01:18:54.823528 Set Vref, RX VrefLevel [Byte0]: 66
8655 01:18:54.826441 [Byte1]: 66
8656 01:18:54.830564
8657 01:18:54.830709 Set Vref, RX VrefLevel [Byte0]: 67
8658 01:18:54.834105 [Byte1]: 67
8659 01:18:54.837900
8660 01:18:54.838048 Set Vref, RX VrefLevel [Byte0]: 68
8661 01:18:54.841699 [Byte1]: 68
8662 01:18:54.845582
8663 01:18:54.845725 Set Vref, RX VrefLevel [Byte0]: 69
8664 01:18:54.848880 [Byte1]: 69
8665 01:18:54.853297
8666 01:18:54.853452 Set Vref, RX VrefLevel [Byte0]: 70
8667 01:18:54.856371 [Byte1]: 70
8668 01:18:54.861137
8669 01:18:54.864166 Set Vref, RX VrefLevel [Byte0]: 71
8670 01:18:54.864299 [Byte1]: 71
8671 01:18:54.868167
8672 01:18:54.868299 Set Vref, RX VrefLevel [Byte0]: 72
8673 01:18:54.871280 [Byte1]: 72
8674 01:18:54.875947
8675 01:18:54.876094 Set Vref, RX VrefLevel [Byte0]: 73
8676 01:18:54.879252 [Byte1]: 73
8677 01:18:54.883640
8678 01:18:54.883783 Set Vref, RX VrefLevel [Byte0]: 74
8679 01:18:54.886579 [Byte1]: 74
8680 01:18:54.890802
8681 01:18:54.890936 Set Vref, RX VrefLevel [Byte0]: 75
8682 01:18:54.894305 [Byte1]: 75
8683 01:18:54.898542
8684 01:18:54.898660 Set Vref, RX VrefLevel [Byte0]: 76
8685 01:18:54.901602 [Byte1]: 76
8686 01:18:54.905957
8687 01:18:54.906077 Set Vref, RX VrefLevel [Byte0]: 77
8688 01:18:54.908900 [Byte1]: 77
8689 01:18:54.913611
8690 01:18:54.913739 Final RX Vref Byte 0 = 58 to rank0
8691 01:18:54.916636 Final RX Vref Byte 1 = 57 to rank0
8692 01:18:54.920134 Final RX Vref Byte 0 = 58 to rank1
8693 01:18:54.923496 Final RX Vref Byte 1 = 57 to rank1==
8694 01:18:54.926718 Dram Type= 6, Freq= 0, CH_1, rank 0
8695 01:18:54.933223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8696 01:18:54.933366 ==
8697 01:18:54.933436 DQS Delay:
8698 01:18:54.933496 DQS0 = 0, DQS1 = 0
8699 01:18:54.936508 DQM Delay:
8700 01:18:54.936612 DQM0 = 134, DQM1 = 131
8701 01:18:54.939761 DQ Delay:
8702 01:18:54.943490 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8703 01:18:54.946486 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =134
8704 01:18:54.949974 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8705 01:18:54.953221 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8706 01:18:54.953334
8707 01:18:54.953400
8708 01:18:54.953459
8709 01:18:54.956409 [DramC_TX_OE_Calibration] TA2
8710 01:18:54.959949 Original DQ_B0 (3 6) =30, OEN = 27
8711 01:18:54.962761 Original DQ_B1 (3 6) =30, OEN = 27
8712 01:18:54.966292 24, 0x0, End_B0=24 End_B1=24
8713 01:18:54.966452 25, 0x0, End_B0=25 End_B1=25
8714 01:18:54.969461 26, 0x0, End_B0=26 End_B1=26
8715 01:18:54.972769 27, 0x0, End_B0=27 End_B1=27
8716 01:18:54.976085 28, 0x0, End_B0=28 End_B1=28
8717 01:18:54.979322 29, 0x0, End_B0=29 End_B1=29
8718 01:18:54.979431 30, 0x0, End_B0=30 End_B1=30
8719 01:18:54.982648 31, 0x4545, End_B0=30 End_B1=30
8720 01:18:54.986510 Byte0 end_step=30 best_step=27
8721 01:18:54.989917 Byte1 end_step=30 best_step=27
8722 01:18:54.993261 Byte0 TX OE(2T, 0.5T) = (3, 3)
8723 01:18:54.996638 Byte1 TX OE(2T, 0.5T) = (3, 3)
8724 01:18:54.996780
8725 01:18:54.996863
8726 01:18:55.003131 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8727 01:18:55.006148 CH1 RK0: MR19=303, MR18=1623
8728 01:18:55.012704 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8729 01:18:55.012874
8730 01:18:55.016183 ----->DramcWriteLeveling(PI) begin...
8731 01:18:55.016287 ==
8732 01:18:55.019473 Dram Type= 6, Freq= 0, CH_1, rank 1
8733 01:18:55.023061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8734 01:18:55.023174 ==
8735 01:18:55.026214 Write leveling (Byte 0): 25 => 25
8736 01:18:55.029420 Write leveling (Byte 1): 27 => 27
8737 01:18:55.032720 DramcWriteLeveling(PI) end<-----
8738 01:18:55.032885
8739 01:18:55.033085 ==
8740 01:18:55.036416 Dram Type= 6, Freq= 0, CH_1, rank 1
8741 01:18:55.039620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8742 01:18:55.039723 ==
8743 01:18:55.042976 [Gating] SW mode calibration
8744 01:18:55.049319 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8745 01:18:55.056047 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8746 01:18:55.059658 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 01:18:55.062518 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 01:18:55.069153 1 4 8 | B1->B0 | 2525 2323 | 1 0 | (1 1) (0 0)
8749 01:18:55.072881 1 4 12 | B1->B0 | 3434 2e2d | 1 1 | (1 1) (0 0)
8750 01:18:55.075971 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 01:18:55.082829 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 01:18:55.086237 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 01:18:55.089452 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 01:18:55.096185 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 01:18:55.099495 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 01:18:55.102750 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)
8757 01:18:55.109475 1 5 12 | B1->B0 | 2424 2727 | 0 1 | (0 0) (1 0)
8758 01:18:55.112589 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 01:18:55.115988 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 01:18:55.122884 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 01:18:55.126428 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 01:18:55.129479 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 01:18:55.135785 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 01:18:55.139419 1 6 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8765 01:18:55.142856 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8766 01:18:55.149054 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 01:18:55.152435 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 01:18:55.155600 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 01:18:55.162086 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 01:18:55.165594 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 01:18:55.168661 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8772 01:18:55.175480 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8773 01:18:55.178890 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8774 01:18:55.181876 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8775 01:18:55.188732 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 01:18:55.192169 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 01:18:55.195146 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 01:18:55.202115 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 01:18:55.205449 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 01:18:55.208898 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 01:18:55.215201 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 01:18:55.218805 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 01:18:55.221877 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 01:18:55.228382 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 01:18:55.231721 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 01:18:55.235093 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 01:18:55.238824 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8788 01:18:55.245177 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8789 01:18:55.248957 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8790 01:18:55.252048 Total UI for P1: 0, mck2ui 16
8791 01:18:55.255619 best dqsien dly found for B1: ( 1, 9, 6)
8792 01:18:55.258588 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 01:18:55.262033 Total UI for P1: 0, mck2ui 16
8794 01:18:55.265646 best dqsien dly found for B0: ( 1, 9, 10)
8795 01:18:55.268812 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8796 01:18:55.272271 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8797 01:18:55.272382
8798 01:18:55.278773 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8799 01:18:55.281881 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8800 01:18:55.285096 [Gating] SW calibration Done
8801 01:18:55.285208 ==
8802 01:18:55.288185 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 01:18:55.291739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 01:18:55.291847 ==
8805 01:18:55.291914 RX Vref Scan: 0
8806 01:18:55.291974
8807 01:18:55.295260 RX Vref 0 -> 0, step: 1
8808 01:18:55.295360
8809 01:18:55.298800 RX Delay 0 -> 252, step: 8
8810 01:18:55.301565 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8811 01:18:55.305131 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8812 01:18:55.311806 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8813 01:18:55.315140 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8814 01:18:55.318349 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8815 01:18:55.321551 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8816 01:18:55.325210 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8817 01:18:55.328153 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8818 01:18:55.335403 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8819 01:18:55.338686 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8820 01:18:55.341849 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8821 01:18:55.344989 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8822 01:18:55.351447 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8823 01:18:55.355553 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8824 01:18:55.358297 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8825 01:18:55.361562 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8826 01:18:55.361700 ==
8827 01:18:55.364572 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 01:18:55.368156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 01:18:55.371394 ==
8830 01:18:55.371535 DQS Delay:
8831 01:18:55.371631 DQS0 = 0, DQS1 = 0
8832 01:18:55.375278 DQM Delay:
8833 01:18:55.375406 DQM0 = 136, DQM1 = 133
8834 01:18:55.378186 DQ Delay:
8835 01:18:55.381477 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8836 01:18:55.384534 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8837 01:18:55.388379 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8838 01:18:55.391701 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8839 01:18:55.391855
8840 01:18:55.391953
8841 01:18:55.392041 ==
8842 01:18:55.394919 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 01:18:55.398086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 01:18:55.398221 ==
8845 01:18:55.401321
8846 01:18:55.401438
8847 01:18:55.401531 TX Vref Scan disable
8848 01:18:55.404466 == TX Byte 0 ==
8849 01:18:55.408069 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8850 01:18:55.411329 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8851 01:18:55.414903 == TX Byte 1 ==
8852 01:18:55.417995 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8853 01:18:55.421508 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8854 01:18:55.421649 ==
8855 01:18:55.424647 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 01:18:55.431378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 01:18:55.431564 ==
8858 01:18:55.442755
8859 01:18:55.445925 TX Vref early break, caculate TX vref
8860 01:18:55.448980 TX Vref=16, minBit 0, minWin=23, winSum=381
8861 01:18:55.453068 TX Vref=18, minBit 1, minWin=24, winSum=396
8862 01:18:55.456288 TX Vref=20, minBit 0, minWin=23, winSum=398
8863 01:18:55.459382 TX Vref=22, minBit 0, minWin=25, winSum=410
8864 01:18:55.462438 TX Vref=24, minBit 0, minWin=25, winSum=419
8865 01:18:55.468897 TX Vref=26, minBit 0, minWin=25, winSum=426
8866 01:18:55.472718 TX Vref=28, minBit 0, minWin=26, winSum=429
8867 01:18:55.475873 TX Vref=30, minBit 0, minWin=25, winSum=425
8868 01:18:55.479231 TX Vref=32, minBit 0, minWin=25, winSum=416
8869 01:18:55.482873 TX Vref=34, minBit 0, minWin=24, winSum=406
8870 01:18:55.489132 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8871 01:18:55.489275
8872 01:18:55.492735 Final TX Range 0 Vref 28
8873 01:18:55.492843
8874 01:18:55.492906 ==
8875 01:18:55.495980 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 01:18:55.499202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 01:18:55.499308 ==
8878 01:18:55.499375
8879 01:18:55.499434
8880 01:18:55.502909 TX Vref Scan disable
8881 01:18:55.509720 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8882 01:18:55.509861 == TX Byte 0 ==
8883 01:18:55.512684 u2DelayCellOfst[0]=20 cells (6 PI)
8884 01:18:55.515753 u2DelayCellOfst[1]=10 cells (3 PI)
8885 01:18:55.519163 u2DelayCellOfst[2]=0 cells (0 PI)
8886 01:18:55.522226 u2DelayCellOfst[3]=6 cells (2 PI)
8887 01:18:55.525487 u2DelayCellOfst[4]=10 cells (3 PI)
8888 01:18:55.529372 u2DelayCellOfst[5]=17 cells (5 PI)
8889 01:18:55.532208 u2DelayCellOfst[6]=20 cells (6 PI)
8890 01:18:55.532306 u2DelayCellOfst[7]=3 cells (1 PI)
8891 01:18:55.539097 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8892 01:18:55.542882 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8893 01:18:55.543004 == TX Byte 1 ==
8894 01:18:55.545808 u2DelayCellOfst[8]=0 cells (0 PI)
8895 01:18:55.549094 u2DelayCellOfst[9]=6 cells (2 PI)
8896 01:18:55.552330 u2DelayCellOfst[10]=13 cells (4 PI)
8897 01:18:55.555423 u2DelayCellOfst[11]=6 cells (2 PI)
8898 01:18:55.558889 u2DelayCellOfst[12]=17 cells (5 PI)
8899 01:18:55.562119 u2DelayCellOfst[13]=17 cells (5 PI)
8900 01:18:55.565263 u2DelayCellOfst[14]=20 cells (6 PI)
8901 01:18:55.568438 u2DelayCellOfst[15]=20 cells (6 PI)
8902 01:18:55.571763 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8903 01:18:55.578427 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8904 01:18:55.578573 DramC Write-DBI on
8905 01:18:55.578639 ==
8906 01:18:55.581639 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 01:18:55.588396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 01:18:55.588539 ==
8909 01:18:55.588605
8910 01:18:55.588664
8911 01:18:55.588721 TX Vref Scan disable
8912 01:18:55.592079 == TX Byte 0 ==
8913 01:18:55.595106 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8914 01:18:55.598647 == TX Byte 1 ==
8915 01:18:55.601894 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8916 01:18:55.605340 DramC Write-DBI off
8917 01:18:55.605453
8918 01:18:55.605518 [DATLAT]
8919 01:18:55.605577 Freq=1600, CH1 RK1
8920 01:18:55.605635
8921 01:18:55.608587 DATLAT Default: 0xf
8922 01:18:55.608676 0, 0xFFFF, sum = 0
8923 01:18:55.611768 1, 0xFFFF, sum = 0
8924 01:18:55.615083 2, 0xFFFF, sum = 0
8925 01:18:55.615185 3, 0xFFFF, sum = 0
8926 01:18:55.618561 4, 0xFFFF, sum = 0
8927 01:18:55.618655 5, 0xFFFF, sum = 0
8928 01:18:55.621692 6, 0xFFFF, sum = 0
8929 01:18:55.621785 7, 0xFFFF, sum = 0
8930 01:18:55.625217 8, 0xFFFF, sum = 0
8931 01:18:55.625312 9, 0xFFFF, sum = 0
8932 01:18:55.628225 10, 0xFFFF, sum = 0
8933 01:18:55.628318 11, 0xFFFF, sum = 0
8934 01:18:55.632174 12, 0xFFFF, sum = 0
8935 01:18:55.632282 13, 0xFFFF, sum = 0
8936 01:18:55.635398 14, 0x0, sum = 1
8937 01:18:55.635513 15, 0x0, sum = 2
8938 01:18:55.638400 16, 0x0, sum = 3
8939 01:18:55.638491 17, 0x0, sum = 4
8940 01:18:55.641456 best_step = 15
8941 01:18:55.641550
8942 01:18:55.641615 ==
8943 01:18:55.645092 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 01:18:55.648280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 01:18:55.648383 ==
8946 01:18:55.651704 RX Vref Scan: 0
8947 01:18:55.651836
8948 01:18:55.651931 RX Vref 0 -> 0, step: 1
8949 01:18:55.652019
8950 01:18:55.655221 RX Delay 19 -> 252, step: 4
8951 01:18:55.658188 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8952 01:18:55.664792 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8953 01:18:55.667969 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8954 01:18:55.671815 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8955 01:18:55.674951 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8956 01:18:55.678237 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8957 01:18:55.684735 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8958 01:18:55.687955 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8959 01:18:55.691146 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8960 01:18:55.694946 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8961 01:18:55.697913 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8962 01:18:55.704656 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8963 01:18:55.708117 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8964 01:18:55.711530 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8965 01:18:55.714392 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8966 01:18:55.718448 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8967 01:18:55.721573 ==
8968 01:18:55.721684 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 01:18:55.728118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 01:18:55.728276 ==
8971 01:18:55.728376 DQS Delay:
8972 01:18:55.731326 DQS0 = 0, DQS1 = 0
8973 01:18:55.731419 DQM Delay:
8974 01:18:55.734456 DQM0 = 134, DQM1 = 130
8975 01:18:55.734550 DQ Delay:
8976 01:18:55.737932 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8977 01:18:55.740983 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8978 01:18:55.744242 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8979 01:18:55.747953 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8980 01:18:55.748070
8981 01:18:55.748135
8982 01:18:55.748194
8983 01:18:55.751238 [DramC_TX_OE_Calibration] TA2
8984 01:18:55.754370 Original DQ_B0 (3 6) =30, OEN = 27
8985 01:18:55.757802 Original DQ_B1 (3 6) =30, OEN = 27
8986 01:18:55.761283 24, 0x0, End_B0=24 End_B1=24
8987 01:18:55.764098 25, 0x0, End_B0=25 End_B1=25
8988 01:18:55.764201 26, 0x0, End_B0=26 End_B1=26
8989 01:18:55.767900 27, 0x0, End_B0=27 End_B1=27
8990 01:18:55.770784 28, 0x0, End_B0=28 End_B1=28
8991 01:18:55.774115 29, 0x0, End_B0=29 End_B1=29
8992 01:18:55.777750 30, 0x0, End_B0=30 End_B1=30
8993 01:18:55.777860 31, 0x4141, End_B0=30 End_B1=30
8994 01:18:55.780826 Byte0 end_step=30 best_step=27
8995 01:18:55.784302 Byte1 end_step=30 best_step=27
8996 01:18:55.787442 Byte0 TX OE(2T, 0.5T) = (3, 3)
8997 01:18:55.790601 Byte1 TX OE(2T, 0.5T) = (3, 3)
8998 01:18:55.790711
8999 01:18:55.790777
9000 01:18:55.797848 [DQSOSCAuto] RK1, (LSB)MR18= 0x2308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9001 01:18:55.801121 CH1 RK1: MR19=303, MR18=2308
9002 01:18:55.807142 CH1_RK1: MR19=0x303, MR18=0x2308, DQSOSC=392, MR23=63, INC=24, DEC=16
9003 01:18:55.810548 [RxdqsGatingPostProcess] freq 1600
9004 01:18:55.817132 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9005 01:18:55.817268 best DQS0 dly(2T, 0.5T) = (1, 1)
9006 01:18:55.820615 best DQS1 dly(2T, 0.5T) = (1, 1)
9007 01:18:55.823913 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9008 01:18:55.827807 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9009 01:18:55.830949 best DQS0 dly(2T, 0.5T) = (1, 1)
9010 01:18:55.834211 best DQS1 dly(2T, 0.5T) = (1, 1)
9011 01:18:55.837671 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9012 01:18:55.840555 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9013 01:18:55.844211 Pre-setting of DQS Precalculation
9014 01:18:55.847369 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9015 01:18:55.854362 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9016 01:18:55.863981 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9017 01:18:55.864132
9018 01:18:55.864201
9019 01:18:55.867141 [Calibration Summary] 3200 Mbps
9020 01:18:55.867233 CH 0, Rank 0
9021 01:18:55.870786 SW Impedance : PASS
9022 01:18:55.870886 DUTY Scan : NO K
9023 01:18:55.873938 ZQ Calibration : PASS
9024 01:18:55.877542 Jitter Meter : NO K
9025 01:18:55.877653 CBT Training : PASS
9026 01:18:55.880983 Write leveling : PASS
9027 01:18:55.881080 RX DQS gating : PASS
9028 01:18:55.884451 RX DQ/DQS(RDDQC) : PASS
9029 01:18:55.887570 TX DQ/DQS : PASS
9030 01:18:55.887679 RX DATLAT : PASS
9031 01:18:55.890558 RX DQ/DQS(Engine): PASS
9032 01:18:55.894081 TX OE : PASS
9033 01:18:55.894192 All Pass.
9034 01:18:55.894257
9035 01:18:55.894366 CH 0, Rank 1
9036 01:18:55.897385 SW Impedance : PASS
9037 01:18:55.900604 DUTY Scan : NO K
9038 01:18:55.900704 ZQ Calibration : PASS
9039 01:18:55.903921 Jitter Meter : NO K
9040 01:18:55.907142 CBT Training : PASS
9041 01:18:55.907247 Write leveling : PASS
9042 01:18:55.910358 RX DQS gating : PASS
9043 01:18:55.913768 RX DQ/DQS(RDDQC) : PASS
9044 01:18:55.913873 TX DQ/DQS : PASS
9045 01:18:55.916855 RX DATLAT : PASS
9046 01:18:55.920142 RX DQ/DQS(Engine): PASS
9047 01:18:55.920274 TX OE : PASS
9048 01:18:55.923805 All Pass.
9049 01:18:55.923905
9050 01:18:55.923972 CH 1, Rank 0
9051 01:18:55.926828 SW Impedance : PASS
9052 01:18:55.926922 DUTY Scan : NO K
9053 01:18:55.930586 ZQ Calibration : PASS
9054 01:18:55.933985 Jitter Meter : NO K
9055 01:18:55.934096 CBT Training : PASS
9056 01:18:55.937121 Write leveling : PASS
9057 01:18:55.937232 RX DQS gating : PASS
9058 01:18:55.941527 RX DQ/DQS(RDDQC) : PASS
9059 01:18:55.943835 TX DQ/DQS : PASS
9060 01:18:55.944164 RX DATLAT : PASS
9061 01:18:55.947313 RX DQ/DQS(Engine): PASS
9062 01:18:55.950437 TX OE : PASS
9063 01:18:55.950628 All Pass.
9064 01:18:55.950777
9065 01:18:55.950914 CH 1, Rank 1
9066 01:18:55.953477 SW Impedance : PASS
9067 01:18:55.957211 DUTY Scan : NO K
9068 01:18:55.957379 ZQ Calibration : PASS
9069 01:18:55.960538 Jitter Meter : NO K
9070 01:18:55.963762 CBT Training : PASS
9071 01:18:55.963908 Write leveling : PASS
9072 01:18:55.967109 RX DQS gating : PASS
9073 01:18:55.970282 RX DQ/DQS(RDDQC) : PASS
9074 01:18:55.970428 TX DQ/DQS : PASS
9075 01:18:55.973712 RX DATLAT : PASS
9076 01:18:55.976995 RX DQ/DQS(Engine): PASS
9077 01:18:55.977106 TX OE : PASS
9078 01:18:55.977183 All Pass.
9079 01:18:55.980243
9080 01:18:55.980353 DramC Write-DBI on
9081 01:18:55.983492 PER_BANK_REFRESH: Hybrid Mode
9082 01:18:55.983591 TX_TRACKING: ON
9083 01:18:55.993517 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9084 01:18:56.000007 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9085 01:18:56.009669 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9086 01:18:56.013399 [FAST_K] Save calibration result to emmc
9087 01:18:56.016669 sync common calibartion params.
9088 01:18:56.016779 sync cbt_mode0:1, 1:1
9089 01:18:56.019734 dram_init: ddr_geometry: 2
9090 01:18:56.023222 dram_init: ddr_geometry: 2
9091 01:18:56.023334 dram_init: ddr_geometry: 2
9092 01:18:56.026415 0:dram_rank_size:100000000
9093 01:18:56.030137 1:dram_rank_size:100000000
9094 01:18:56.033445 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9095 01:18:56.036539 DFS_SHUFFLE_HW_MODE: ON
9096 01:18:56.039607 dramc_set_vcore_voltage set vcore to 725000
9097 01:18:56.043533 Read voltage for 1600, 0
9098 01:18:56.043654 Vio18 = 0
9099 01:18:56.046759 Vcore = 725000
9100 01:18:56.046855 Vdram = 0
9101 01:18:56.046919 Vddq = 0
9102 01:18:56.046978 Vmddr = 0
9103 01:18:56.049868 switch to 3200 Mbps bootup
9104 01:18:56.052947 [DramcRunTimeConfig]
9105 01:18:56.053059 PHYPLL
9106 01:18:56.056764 DPM_CONTROL_AFTERK: ON
9107 01:18:56.056882 PER_BANK_REFRESH: ON
9108 01:18:56.059869 REFRESH_OVERHEAD_REDUCTION: ON
9109 01:18:56.063307 CMD_PICG_NEW_MODE: OFF
9110 01:18:56.063421 XRTWTW_NEW_MODE: ON
9111 01:18:56.066408 XRTRTR_NEW_MODE: ON
9112 01:18:56.066501 TX_TRACKING: ON
9113 01:18:56.069638 RDSEL_TRACKING: OFF
9114 01:18:56.073063 DQS Precalculation for DVFS: ON
9115 01:18:56.073170 RX_TRACKING: OFF
9116 01:18:56.076252 HW_GATING DBG: ON
9117 01:18:56.076354 ZQCS_ENABLE_LP4: ON
9118 01:18:56.079860 RX_PICG_NEW_MODE: ON
9119 01:18:56.079964 TX_PICG_NEW_MODE: ON
9120 01:18:56.082932 ENABLE_RX_DCM_DPHY: ON
9121 01:18:56.086280 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9122 01:18:56.090118 DUMMY_READ_FOR_TRACKING: OFF
9123 01:18:56.090228 !!! SPM_CONTROL_AFTERK: OFF
9124 01:18:56.093501 !!! SPM could not control APHY
9125 01:18:56.096596 IMPEDANCE_TRACKING: ON
9126 01:18:56.096711 TEMP_SENSOR: ON
9127 01:18:56.099732 HW_SAVE_FOR_SR: OFF
9128 01:18:56.102986 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9129 01:18:56.106161 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9130 01:18:56.106271 Read ODT Tracking: ON
9131 01:18:56.109837 Refresh Rate DeBounce: ON
9132 01:18:56.113360 DFS_NO_QUEUE_FLUSH: ON
9133 01:18:56.116187 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9134 01:18:56.116299 ENABLE_DFS_RUNTIME_MRW: OFF
9135 01:18:56.119702 DDR_RESERVE_NEW_MODE: ON
9136 01:18:56.122613 MR_CBT_SWITCH_FREQ: ON
9137 01:18:56.122722 =========================
9138 01:18:56.143596 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9139 01:18:56.146525 dram_init: ddr_geometry: 2
9140 01:18:56.164444 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9141 01:18:56.168100 dram_init: dram init end (result: 0)
9142 01:18:56.174747 DRAM-K: Full calibration passed in 24464 msecs
9143 01:18:56.178059 MRC: failed to locate region type 0.
9144 01:18:56.178176 DRAM rank0 size:0x100000000,
9145 01:18:56.181238 DRAM rank1 size=0x100000000
9146 01:18:56.191270 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9147 01:18:56.197747 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9148 01:18:56.204626 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9149 01:18:56.211291 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9150 01:18:56.214727 DRAM rank0 size:0x100000000,
9151 01:18:56.217593 DRAM rank1 size=0x100000000
9152 01:18:56.217701 CBMEM:
9153 01:18:56.221364 IMD: root @ 0xfffff000 254 entries.
9154 01:18:56.224509 IMD: root @ 0xffffec00 62 entries.
9155 01:18:56.227510 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9156 01:18:56.231158 WARNING: RO_VPD is uninitialized or empty.
9157 01:18:56.237405 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9158 01:18:56.244652 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9159 01:18:56.257643 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9160 01:18:56.268933 BS: romstage times (exec / console): total (unknown) / 23992 ms
9161 01:18:56.269086
9162 01:18:56.269155
9163 01:18:56.279172 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9164 01:18:56.282513 ARM64: Exception handlers installed.
9165 01:18:56.285639 ARM64: Testing exception
9166 01:18:56.288963 ARM64: Done test exception
9167 01:18:56.289073 Enumerating buses...
9168 01:18:56.292065 Show all devs... Before device enumeration.
9169 01:18:56.295206 Root Device: enabled 1
9170 01:18:56.299148 CPU_CLUSTER: 0: enabled 1
9171 01:18:56.299263 CPU: 00: enabled 1
9172 01:18:56.302514 Compare with tree...
9173 01:18:56.302609 Root Device: enabled 1
9174 01:18:56.305674 CPU_CLUSTER: 0: enabled 1
9175 01:18:56.308856 CPU: 00: enabled 1
9176 01:18:56.308958 Root Device scanning...
9177 01:18:56.312245 scan_static_bus for Root Device
9178 01:18:56.315573 CPU_CLUSTER: 0 enabled
9179 01:18:56.318791 scan_static_bus for Root Device done
9180 01:18:56.321978 scan_bus: bus Root Device finished in 8 msecs
9181 01:18:56.322083 done
9182 01:18:56.328789 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9183 01:18:56.332066 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9184 01:18:56.338582 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9185 01:18:56.341800 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9186 01:18:56.344784 Allocating resources...
9187 01:18:56.348637 Reading resources...
9188 01:18:56.351689 Root Device read_resources bus 0 link: 0
9189 01:18:56.351805 DRAM rank0 size:0x100000000,
9190 01:18:56.354796 DRAM rank1 size=0x100000000
9191 01:18:56.358512 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9192 01:18:56.361732 CPU: 00 missing read_resources
9193 01:18:56.365161 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9194 01:18:56.371927 Root Device read_resources bus 0 link: 0 done
9195 01:18:56.372071 Done reading resources.
9196 01:18:56.378397 Show resources in subtree (Root Device)...After reading.
9197 01:18:56.381276 Root Device child on link 0 CPU_CLUSTER: 0
9198 01:18:56.384824 CPU_CLUSTER: 0 child on link 0 CPU: 00
9199 01:18:56.394573 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9200 01:18:56.394726 CPU: 00
9201 01:18:56.398225 Root Device assign_resources, bus 0 link: 0
9202 01:18:56.401212 CPU_CLUSTER: 0 missing set_resources
9203 01:18:56.408347 Root Device assign_resources, bus 0 link: 0 done
9204 01:18:56.408487 Done setting resources.
9205 01:18:56.414787 Show resources in subtree (Root Device)...After assigning values.
9206 01:18:56.417999 Root Device child on link 0 CPU_CLUSTER: 0
9207 01:18:56.421300 CPU_CLUSTER: 0 child on link 0 CPU: 00
9208 01:18:56.431096 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9209 01:18:56.431247 CPU: 00
9210 01:18:56.434867 Done allocating resources.
9211 01:18:56.438117 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9212 01:18:56.441343 Enabling resources...
9213 01:18:56.441450 done.
9214 01:18:56.448150 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9215 01:18:56.448287 Initializing devices...
9216 01:18:56.451356 Root Device init
9217 01:18:56.451451 init hardware done!
9218 01:18:56.454954 0x00000018: ctrlr->caps
9219 01:18:56.457880 52.000 MHz: ctrlr->f_max
9220 01:18:56.457986 0.400 MHz: ctrlr->f_min
9221 01:18:56.461102 0x40ff8080: ctrlr->voltages
9222 01:18:56.461202 sclk: 390625
9223 01:18:56.464144 Bus Width = 1
9224 01:18:56.464240 sclk: 390625
9225 01:18:56.468012 Bus Width = 1
9226 01:18:56.468130 Early init status = 3
9227 01:18:56.474600 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9228 01:18:56.477512 in-header: 03 fc 00 00 01 00 00 00
9229 01:18:56.477623 in-data: 00
9230 01:18:56.484056 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9231 01:18:56.487472 in-header: 03 fd 00 00 00 00 00 00
9232 01:18:56.490647 in-data:
9233 01:18:56.494051 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9234 01:18:56.497830 in-header: 03 fc 00 00 01 00 00 00
9235 01:18:56.501014 in-data: 00
9236 01:18:56.504069 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9237 01:18:56.509852 in-header: 03 fd 00 00 00 00 00 00
9238 01:18:56.513006 in-data:
9239 01:18:56.516085 [SSUSB] Setting up USB HOST controller...
9240 01:18:56.519254 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9241 01:18:56.522807 [SSUSB] phy power-on done.
9242 01:18:56.526209 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9243 01:18:56.532725 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9244 01:18:56.536067 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9245 01:18:56.542625 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9246 01:18:56.549154 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9247 01:18:56.555699 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9248 01:18:56.562136 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9249 01:18:56.568998 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9250 01:18:56.572428 SPM: binary array size = 0x9dc
9251 01:18:56.575165 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9252 01:18:56.582264 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9253 01:18:56.588772 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9254 01:18:56.595315 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9255 01:18:56.598630 configure_display: Starting display init
9256 01:18:56.632719 anx7625_power_on_init: Init interface.
9257 01:18:56.636102 anx7625_disable_pd_protocol: Disabled PD feature.
9258 01:18:56.639124 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9259 01:18:56.666983 anx7625_start_dp_work: Secure OCM version=00
9260 01:18:56.670202 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9261 01:18:56.685426 sp_tx_get_edid_block: EDID Block = 1
9262 01:18:56.788041 Extracted contents:
9263 01:18:56.790958 header: 00 ff ff ff ff ff ff 00
9264 01:18:56.794347 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9265 01:18:56.797514 version: 01 04
9266 01:18:56.800988 basic params: 95 1f 11 78 0a
9267 01:18:56.804222 chroma info: 76 90 94 55 54 90 27 21 50 54
9268 01:18:56.807529 established: 00 00 00
9269 01:18:56.814100 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9270 01:18:56.817335 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9271 01:18:56.824274 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9272 01:18:56.830876 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9273 01:18:56.837502 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9274 01:18:56.840658 extensions: 00
9275 01:18:56.840772 checksum: fb
9276 01:18:56.840841
9277 01:18:56.843895 Manufacturer: IVO Model 57d Serial Number 0
9278 01:18:56.847683 Made week 0 of 2020
9279 01:18:56.847820 EDID version: 1.4
9280 01:18:56.850727 Digital display
9281 01:18:56.854125 6 bits per primary color channel
9282 01:18:56.854264 DisplayPort interface
9283 01:18:56.857240 Maximum image size: 31 cm x 17 cm
9284 01:18:56.861101 Gamma: 220%
9285 01:18:56.861213 Check DPMS levels
9286 01:18:56.864462 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9287 01:18:56.867110 First detailed timing is preferred timing
9288 01:18:56.870422 Established timings supported:
9289 01:18:56.874164 Standard timings supported:
9290 01:18:56.877254 Detailed timings
9291 01:18:56.880538 Hex of detail: 383680a07038204018303c0035ae10000019
9292 01:18:56.883776 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9293 01:18:56.890951 0780 0798 07c8 0820 hborder 0
9294 01:18:56.894112 0438 043b 0447 0458 vborder 0
9295 01:18:56.897468 -hsync -vsync
9296 01:18:56.897570 Did detailed timing
9297 01:18:56.900685 Hex of detail: 000000000000000000000000000000000000
9298 01:18:56.904376 Manufacturer-specified data, tag 0
9299 01:18:56.911047 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9300 01:18:56.911188 ASCII string: InfoVision
9301 01:18:56.917284 Hex of detail: 000000fe00523134304e574635205248200a
9302 01:18:56.920681 ASCII string: R140NWF5 RH
9303 01:18:56.920795 Checksum
9304 01:18:56.920862 Checksum: 0xfb (valid)
9305 01:18:56.927346 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9306 01:18:56.930911 DSI data_rate: 832800000 bps
9307 01:18:56.933932 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9308 01:18:56.940783 anx7625_parse_edid: pixelclock(138800).
9309 01:18:56.943682 hactive(1920), hsync(48), hfp(24), hbp(88)
9310 01:18:56.947354 vactive(1080), vsync(12), vfp(3), vbp(17)
9311 01:18:56.950578 anx7625_dsi_config: config dsi.
9312 01:18:56.956830 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9313 01:18:56.969817 anx7625_dsi_config: success to config DSI
9314 01:18:56.972930 anx7625_dp_start: MIPI phy setup OK.
9315 01:18:56.976494 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9316 01:18:56.979955 mtk_ddp_mode_set invalid vrefresh 60
9317 01:18:56.983314 main_disp_path_setup
9318 01:18:56.983422 ovl_layer_smi_id_en
9319 01:18:56.986257 ovl_layer_smi_id_en
9320 01:18:56.986369 ccorr_config
9321 01:18:56.986435 aal_config
9322 01:18:56.990025 gamma_config
9323 01:18:56.990122 postmask_config
9324 01:18:56.993121 dither_config
9325 01:18:56.996435 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9326 01:18:57.002959 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9327 01:18:57.006234 Root Device init finished in 552 msecs
9328 01:18:57.009456 CPU_CLUSTER: 0 init
9329 01:18:57.016496 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9330 01:18:57.019571 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9331 01:18:57.022915 APU_MBOX 0x190000b0 = 0x10001
9332 01:18:57.026093 APU_MBOX 0x190001b0 = 0x10001
9333 01:18:57.029997 APU_MBOX 0x190005b0 = 0x10001
9334 01:18:57.032867 APU_MBOX 0x190006b0 = 0x10001
9335 01:18:57.036124 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9336 01:18:57.048788 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9337 01:18:57.061102 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9338 01:18:57.068093 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9339 01:18:57.079506 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9340 01:18:57.089158 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9341 01:18:57.091739 CPU_CLUSTER: 0 init finished in 81 msecs
9342 01:18:57.095144 Devices initialized
9343 01:18:57.098563 Show all devs... After init.
9344 01:18:57.098704 Root Device: enabled 1
9345 01:18:57.101870 CPU_CLUSTER: 0: enabled 1
9346 01:18:57.105233 CPU: 00: enabled 1
9347 01:18:57.108307 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9348 01:18:57.111501 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9349 01:18:57.115440 ELOG: NV offset 0x57f000 size 0x1000
9350 01:18:57.121856 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9351 01:18:57.128586 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9352 01:18:57.131230 ELOG: Event(17) added with size 13 at 2024-04-23 01:14:45 UTC
9353 01:18:57.138472 out: cmd=0x121: 03 db 21 01 00 00 00 00
9354 01:18:57.141311 in-header: 03 c8 00 00 2c 00 00 00
9355 01:18:57.151772 in-data: 96 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9356 01:18:57.158204 ELOG: Event(A1) added with size 10 at 2024-04-23 01:14:45 UTC
9357 01:18:57.164673 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9358 01:18:57.171217 ELOG: Event(A0) added with size 9 at 2024-04-23 01:14:45 UTC
9359 01:18:57.174542 elog_add_boot_reason: Logged dev mode boot
9360 01:18:57.177848 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9361 01:18:57.181629 Finalize devices...
9362 01:18:57.184742 Devices finalized
9363 01:18:57.188053 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9364 01:18:57.191319 Writing coreboot table at 0xffe64000
9365 01:18:57.194590 0. 000000000010a000-0000000000113fff: RAMSTAGE
9366 01:18:57.197891 1. 0000000040000000-00000000400fffff: RAM
9367 01:18:57.204413 2. 0000000040100000-000000004032afff: RAMSTAGE
9368 01:18:57.207974 3. 000000004032b000-00000000545fffff: RAM
9369 01:18:57.211122 4. 0000000054600000-000000005465ffff: BL31
9370 01:18:57.214564 5. 0000000054660000-00000000ffe63fff: RAM
9371 01:18:57.221059 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9372 01:18:57.224688 7. 0000000100000000-000000023fffffff: RAM
9373 01:18:57.227782 Passing 5 GPIOs to payload:
9374 01:18:57.230829 NAME | PORT | POLARITY | VALUE
9375 01:18:57.234604 EC in RW | 0x000000aa | low | undefined
9376 01:18:57.241204 EC interrupt | 0x00000005 | low | undefined
9377 01:18:57.244365 TPM interrupt | 0x000000ab | high | undefined
9378 01:18:57.250662 SD card detect | 0x00000011 | high | undefined
9379 01:18:57.254230 speaker enable | 0x00000093 | high | undefined
9380 01:18:57.257514 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9381 01:18:57.261325 in-header: 03 f9 00 00 02 00 00 00
9382 01:18:57.264465 in-data: 02 00
9383 01:18:57.264577 ADC[4]: Raw value=904726 ID=7
9384 01:18:57.267744 ADC[3]: Raw value=213441 ID=1
9385 01:18:57.271016 RAM Code: 0x71
9386 01:18:57.271122 ADC[6]: Raw value=75332 ID=0
9387 01:18:57.274244 ADC[5]: Raw value=213072 ID=1
9388 01:18:57.277398 SKU Code: 0x1
9389 01:18:57.280516 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cac8
9390 01:18:57.284323 coreboot table: 964 bytes.
9391 01:18:57.287412 IMD ROOT 0. 0xfffff000 0x00001000
9392 01:18:57.290406 IMD SMALL 1. 0xffffe000 0x00001000
9393 01:18:57.293655 RO MCACHE 2. 0xffffc000 0x00001104
9394 01:18:57.297202 CONSOLE 3. 0xfff7c000 0x00080000
9395 01:18:57.300583 FMAP 4. 0xfff7b000 0x00000452
9396 01:18:57.303867 TIME STAMP 5. 0xfff7a000 0x00000910
9397 01:18:57.307172 VBOOT WORK 6. 0xfff66000 0x00014000
9398 01:18:57.310475 RAMOOPS 7. 0xffe66000 0x00100000
9399 01:18:57.313801 COREBOOT 8. 0xffe64000 0x00002000
9400 01:18:57.317108 IMD small region:
9401 01:18:57.320136 IMD ROOT 0. 0xffffec00 0x00000400
9402 01:18:57.324036 VPD 1. 0xffffeb80 0x0000006c
9403 01:18:57.327245 MMC STATUS 2. 0xffffeb60 0x00000004
9404 01:18:57.330327 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9405 01:18:57.333888 Probing TPM: done!
9406 01:18:57.337255 Connected to device vid:did:rid of 1ae0:0028:00
9407 01:18:57.347711 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9408 01:18:57.350706 Initialized TPM device CR50 revision 0
9409 01:18:57.355000 Checking cr50 for pending updates
9410 01:18:57.358112 Reading cr50 TPM mode
9411 01:18:57.366840 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9412 01:18:57.373746 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9413 01:18:57.413522 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9414 01:18:57.416905 Checking segment from ROM address 0x40100000
9415 01:18:57.420724 Checking segment from ROM address 0x4010001c
9416 01:18:57.427115 Loading segment from ROM address 0x40100000
9417 01:18:57.427265 code (compression=0)
9418 01:18:57.437409 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9419 01:18:57.443764 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9420 01:18:57.443910 it's not compressed!
9421 01:18:57.450086 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9422 01:18:57.453711 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9423 01:18:57.473986 Loading segment from ROM address 0x4010001c
9424 01:18:57.474136 Entry Point 0x80000000
9425 01:18:57.477731 Loaded segments
9426 01:18:57.480585 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9427 01:18:57.487718 Jumping to boot code at 0x80000000(0xffe64000)
9428 01:18:57.494142 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9429 01:18:57.500735 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9430 01:18:57.508617 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9431 01:18:57.511905 Checking segment from ROM address 0x40100000
9432 01:18:57.515559 Checking segment from ROM address 0x4010001c
9433 01:18:57.518483 Loading segment from ROM address 0x40100000
9434 01:18:57.521965 code (compression=1)
9435 01:18:57.528736 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9436 01:18:57.538563 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9437 01:18:57.538714 using LZMA
9438 01:18:57.547176 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9439 01:18:57.553444 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9440 01:18:57.556697 Loading segment from ROM address 0x4010001c
9441 01:18:57.556822 Entry Point 0x54601000
9442 01:18:57.560585 Loaded segments
9443 01:18:57.563771 NOTICE: MT8192 bl31_setup
9444 01:18:57.570933 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9445 01:18:57.573916 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9446 01:18:57.577283 WARNING: region 0:
9447 01:18:57.580537 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9448 01:18:57.580648 WARNING: region 1:
9449 01:18:57.586981 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9450 01:18:57.590787 WARNING: region 2:
9451 01:18:57.593884 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9452 01:18:57.597142 WARNING: region 3:
9453 01:18:57.600788 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9454 01:18:57.603888 WARNING: region 4:
9455 01:18:57.610484 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9456 01:18:57.610630 WARNING: region 5:
9457 01:18:57.613895 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 01:18:57.617178 WARNING: region 6:
9459 01:18:57.620281 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 01:18:57.623639 WARNING: region 7:
9461 01:18:57.626957 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 01:18:57.633737 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9463 01:18:57.637300 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9464 01:18:57.640316 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9465 01:18:57.647041 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9466 01:18:57.650331 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9467 01:18:57.653964 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9468 01:18:57.660264 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9469 01:18:57.664160 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9470 01:18:57.670735 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9471 01:18:57.674071 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9472 01:18:57.677298 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9473 01:18:57.683823 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9474 01:18:57.687558 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9475 01:18:57.690587 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9476 01:18:57.697049 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9477 01:18:57.700834 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9478 01:18:57.703839 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9479 01:18:57.710763 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9480 01:18:57.714054 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9481 01:18:57.720846 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9482 01:18:57.724148 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9483 01:18:57.727934 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9484 01:18:57.734238 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9485 01:18:57.737522 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9486 01:18:57.743924 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9487 01:18:57.747135 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9488 01:18:57.750576 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9489 01:18:57.757593 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9490 01:18:57.760439 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9491 01:18:57.763862 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9492 01:18:57.770877 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9493 01:18:57.773724 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9494 01:18:57.777156 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9495 01:18:57.783652 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9496 01:18:57.787516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9497 01:18:57.790756 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9498 01:18:57.793773 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9499 01:18:57.800489 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9500 01:18:57.804457 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9501 01:18:57.806979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9502 01:18:57.810363 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9503 01:18:57.817516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9504 01:18:57.820521 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9505 01:18:57.823967 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9506 01:18:57.827402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9507 01:18:57.833891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9508 01:18:57.837109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9509 01:18:57.840913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9510 01:18:57.847746 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9511 01:18:57.850899 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9512 01:18:57.857530 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9513 01:18:57.860830 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9514 01:18:57.863952 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9515 01:18:57.871081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9516 01:18:57.873867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9517 01:18:57.880738 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9518 01:18:57.884052 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9519 01:18:57.887101 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9520 01:18:57.894053 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9521 01:18:57.897314 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9522 01:18:57.904498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9523 01:18:57.907296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9524 01:18:57.913845 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9525 01:18:57.917139 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9526 01:18:57.924082 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9527 01:18:57.927236 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9528 01:18:57.931123 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9529 01:18:57.937246 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9530 01:18:57.940608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9531 01:18:57.947594 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9532 01:18:57.950679 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9533 01:18:57.954178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9534 01:18:57.960999 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9535 01:18:57.964268 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9536 01:18:57.971029 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9537 01:18:57.974282 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9538 01:18:57.980595 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9539 01:18:57.984441 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9540 01:18:57.987635 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9541 01:18:57.994800 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9542 01:18:57.997891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9543 01:18:58.004405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9544 01:18:58.007745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9545 01:18:58.014232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9546 01:18:58.017445 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9547 01:18:58.020684 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9548 01:18:58.027794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9549 01:18:58.030970 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9550 01:18:58.038089 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9551 01:18:58.041232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9552 01:18:58.047769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9553 01:18:58.051082 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9554 01:18:58.054948 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9555 01:18:58.061973 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9556 01:18:58.064423 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9557 01:18:58.071382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9558 01:18:58.074714 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9559 01:18:58.078104 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9560 01:18:58.081383 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9561 01:18:58.088433 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9562 01:18:58.091618 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9563 01:18:58.094648 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9564 01:18:58.101787 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9565 01:18:58.104888 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9566 01:18:58.111450 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9567 01:18:58.115218 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9568 01:18:58.118199 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9569 01:18:58.125098 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9570 01:18:58.128189 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9571 01:18:58.135312 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9572 01:18:58.138431 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9573 01:18:58.141749 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9574 01:18:58.148274 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9575 01:18:58.151546 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9576 01:18:58.155330 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9577 01:18:58.161870 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9578 01:18:58.165029 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9579 01:18:58.168339 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9580 01:18:58.175431 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9581 01:18:58.178266 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9582 01:18:58.181935 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9583 01:18:58.185231 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9584 01:18:58.191431 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9585 01:18:58.195374 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9586 01:18:58.198430 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9587 01:18:58.205272 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9588 01:18:58.208571 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9589 01:18:58.211701 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9590 01:18:58.218713 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9591 01:18:58.222240 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9592 01:18:58.225240 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9593 01:18:58.232137 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9594 01:18:58.235372 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9595 01:18:58.242351 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9596 01:18:58.245330 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9597 01:18:58.248585 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9598 01:18:58.255157 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9599 01:18:58.258498 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9600 01:18:58.265382 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9601 01:18:58.268280 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9602 01:18:58.271851 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9603 01:18:58.278862 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9604 01:18:58.282111 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9605 01:18:58.288459 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9606 01:18:58.291898 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9607 01:18:58.295308 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9608 01:18:58.302150 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9609 01:18:58.305591 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9610 01:18:58.308585 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9611 01:18:58.315153 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9612 01:18:58.319279 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9613 01:18:58.325259 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9614 01:18:58.328891 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9615 01:18:58.331871 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9616 01:18:58.338847 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9617 01:18:58.342096 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9618 01:18:58.348464 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9619 01:18:58.352281 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9620 01:18:58.355370 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9621 01:18:58.361932 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9622 01:18:58.365138 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9623 01:18:58.368424 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9624 01:18:58.375516 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9625 01:18:58.378355 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9626 01:18:58.385362 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9627 01:18:58.388606 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9628 01:18:58.391912 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9629 01:18:58.398247 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9630 01:18:58.401673 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9631 01:18:58.408240 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9632 01:18:58.411474 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9633 01:18:58.414738 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9634 01:18:58.421526 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9635 01:18:58.424749 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9636 01:18:58.431426 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9637 01:18:58.434765 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9638 01:18:58.438249 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9639 01:18:58.444695 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9640 01:18:58.447983 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9641 01:18:58.454832 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9642 01:18:58.457779 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9643 01:18:58.461553 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9644 01:18:58.468041 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9645 01:18:58.471362 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9646 01:18:58.477995 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9647 01:18:58.481174 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9648 01:18:58.484816 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9649 01:18:58.491370 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9650 01:18:58.494826 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9651 01:18:58.501173 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9652 01:18:58.504449 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9653 01:18:58.507803 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9654 01:18:58.514411 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9655 01:18:58.517650 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9656 01:18:58.524377 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9657 01:18:58.528188 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9658 01:18:58.531072 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9659 01:18:58.537816 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9660 01:18:58.541098 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9661 01:18:58.548001 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9662 01:18:58.551356 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9663 01:18:58.554261 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9664 01:18:58.561259 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9665 01:18:58.564720 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9666 01:18:58.571429 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9667 01:18:58.574846 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9668 01:18:58.581299 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9669 01:18:58.584505 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9670 01:18:58.587675 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9671 01:18:58.594080 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9672 01:18:58.597628 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9673 01:18:58.603948 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9674 01:18:58.607740 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9675 01:18:58.614175 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9676 01:18:58.617532 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9677 01:18:58.620857 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9678 01:18:58.627886 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9679 01:18:58.631166 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9680 01:18:58.637520 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9681 01:18:58.640644 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9682 01:18:58.643860 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9683 01:18:58.650433 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9684 01:18:58.653813 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9685 01:18:58.660499 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9686 01:18:58.663536 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9687 01:18:58.670509 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9688 01:18:58.673541 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9689 01:18:58.676804 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9690 01:18:58.683350 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9691 01:18:58.687260 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9692 01:18:58.690217 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9693 01:18:58.693474 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9694 01:18:58.700612 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9695 01:18:58.703734 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9696 01:18:58.706926 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9697 01:18:58.713456 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9698 01:18:58.716974 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9699 01:18:58.720233 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9700 01:18:58.726731 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9701 01:18:58.730794 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9702 01:18:58.733773 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9703 01:18:58.740401 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9704 01:18:58.743480 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9705 01:18:58.749985 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9706 01:18:58.753197 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9707 01:18:58.756464 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9708 01:18:58.763167 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9709 01:18:58.766494 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9710 01:18:58.770103 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9711 01:18:58.776566 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9712 01:18:58.780102 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9713 01:18:58.786575 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9714 01:18:58.790179 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9715 01:18:58.793247 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9716 01:18:58.799778 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9717 01:18:58.803130 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9718 01:18:58.806251 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9719 01:18:58.812838 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9720 01:18:58.816668 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9721 01:18:58.819758 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9722 01:18:58.826178 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9723 01:18:58.829601 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9724 01:18:58.836744 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9725 01:18:58.839596 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9726 01:18:58.842897 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9727 01:18:58.849404 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9728 01:18:58.853262 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9729 01:18:58.856500 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9730 01:18:58.862985 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9731 01:18:58.866293 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9732 01:18:58.869739 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9733 01:18:58.873055 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9734 01:18:58.879478 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9735 01:18:58.882492 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9736 01:18:58.886051 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9737 01:18:58.889439 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9738 01:18:58.896107 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9739 01:18:58.899343 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9740 01:18:58.903160 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9741 01:18:58.906410 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9742 01:18:58.913099 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9743 01:18:58.916100 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9744 01:18:58.919169 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9745 01:18:58.926284 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9746 01:18:58.929352 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9747 01:18:58.936090 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9748 01:18:58.939578 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9749 01:18:58.942548 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9750 01:18:58.949112 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9751 01:18:58.952388 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9752 01:18:58.959307 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9753 01:18:58.962695 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9754 01:18:58.965986 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9755 01:18:58.972471 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9756 01:18:58.976487 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9757 01:18:58.983072 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9758 01:18:58.986436 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9759 01:18:58.989621 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9760 01:18:58.995802 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9761 01:18:58.999469 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9762 01:18:59.005886 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9763 01:18:59.009550 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9764 01:18:59.012439 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9765 01:18:59.019042 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9766 01:18:59.022248 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9767 01:18:59.029008 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9768 01:18:59.032597 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9769 01:18:59.035804 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9770 01:18:59.042517 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9771 01:18:59.045242 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9772 01:18:59.052140 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9773 01:18:59.055294 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9774 01:18:59.061916 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9775 01:18:59.065197 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9776 01:18:59.069056 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9777 01:18:59.075525 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9778 01:18:59.078175 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9779 01:18:59.085549 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9780 01:18:59.088775 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9781 01:18:59.094951 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9782 01:18:59.098157 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9783 01:18:59.101447 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9784 01:18:59.108630 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9785 01:18:59.111766 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9786 01:18:59.118047 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9787 01:18:59.121496 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9788 01:18:59.125042 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9789 01:18:59.131313 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9790 01:18:59.135085 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9791 01:18:59.141086 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9792 01:18:59.144799 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9793 01:18:59.148124 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9794 01:18:59.155056 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9795 01:18:59.158067 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9796 01:18:59.164640 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9797 01:18:59.167872 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9798 01:18:59.174484 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9799 01:18:59.177599 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9800 01:18:59.180972 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9801 01:18:59.188144 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9802 01:18:59.191448 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9803 01:18:59.197917 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9804 01:18:59.200978 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9805 01:18:59.204190 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9806 01:18:59.211386 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9807 01:18:59.214464 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9808 01:18:59.221045 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9809 01:18:59.224217 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9810 01:18:59.228004 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9811 01:18:59.234479 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9812 01:18:59.237550 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9813 01:18:59.244500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9814 01:18:59.247403 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9815 01:18:59.250975 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9816 01:18:59.257629 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9817 01:18:59.261347 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9818 01:18:59.267733 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9819 01:18:59.270962 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9820 01:18:59.277439 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9821 01:18:59.280952 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9822 01:18:59.287346 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9823 01:18:59.291051 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9824 01:18:59.293883 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9825 01:18:59.300849 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9826 01:18:59.304100 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9827 01:18:59.310781 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9828 01:18:59.314108 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9829 01:18:59.321141 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9830 01:18:59.324383 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9831 01:18:59.327657 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9832 01:18:59.334133 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9833 01:18:59.337287 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9834 01:18:59.344279 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9835 01:18:59.347691 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9836 01:18:59.350836 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9837 01:18:59.357442 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9838 01:18:59.360565 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9839 01:18:59.367402 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9840 01:18:59.370504 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9841 01:18:59.377665 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9842 01:18:59.380840 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9843 01:18:59.387466 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9844 01:18:59.390514 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9845 01:18:59.393919 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9846 01:18:59.400511 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9847 01:18:59.403964 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9848 01:18:59.410665 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9849 01:18:59.413810 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9850 01:18:59.420184 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9851 01:18:59.423422 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9852 01:18:59.427044 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9853 01:18:59.433610 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9854 01:18:59.436858 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9855 01:18:59.443330 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9856 01:18:59.446467 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9857 01:18:59.453234 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9858 01:18:59.456546 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9859 01:18:59.463296 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9860 01:18:59.466935 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9861 01:18:59.470021 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9862 01:18:59.476342 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9863 01:18:59.479573 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9864 01:18:59.486508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9865 01:18:59.489967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9866 01:18:59.493073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9867 01:18:59.499923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9868 01:18:59.502935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9869 01:18:59.510321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9870 01:18:59.513275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9871 01:18:59.519732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9872 01:18:59.522991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9873 01:18:59.529647 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9874 01:18:59.533205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9875 01:18:59.539506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9876 01:18:59.543098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9877 01:18:59.549671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9878 01:18:59.553265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9879 01:18:59.559683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9880 01:18:59.563224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9881 01:18:59.569759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9882 01:18:59.573290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9883 01:18:59.579787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9884 01:18:59.583047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9885 01:18:59.589383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9886 01:18:59.592692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9887 01:18:59.599793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9888 01:18:59.602411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9889 01:18:59.609203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9890 01:18:59.613070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9891 01:18:59.619304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9892 01:18:59.622700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9893 01:18:59.629192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9894 01:18:59.632426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9895 01:18:59.638911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9896 01:18:59.642367 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9897 01:18:59.645462 INFO: [APUAPC] vio 0
9898 01:18:59.648798 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9899 01:18:59.655906 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9900 01:18:59.656062 INFO: [APUAPC] D0_APC_0: 0x400510
9901 01:18:59.658988 INFO: [APUAPC] D0_APC_1: 0x0
9902 01:18:59.662015 INFO: [APUAPC] D0_APC_2: 0x1540
9903 01:18:59.665868 INFO: [APUAPC] D0_APC_3: 0x0
9904 01:18:59.668640 INFO: [APUAPC] D1_APC_0: 0xffffffff
9905 01:18:59.671849 INFO: [APUAPC] D1_APC_1: 0xffffffff
9906 01:18:59.675300 INFO: [APUAPC] D1_APC_2: 0x3fffff
9907 01:18:59.678841 INFO: [APUAPC] D1_APC_3: 0x0
9908 01:18:59.682218 INFO: [APUAPC] D2_APC_0: 0xffffffff
9909 01:18:59.685391 INFO: [APUAPC] D2_APC_1: 0xffffffff
9910 01:18:59.688686 INFO: [APUAPC] D2_APC_2: 0x3fffff
9911 01:18:59.691841 INFO: [APUAPC] D2_APC_3: 0x0
9912 01:18:59.695410 INFO: [APUAPC] D3_APC_0: 0xffffffff
9913 01:18:59.698482 INFO: [APUAPC] D3_APC_1: 0xffffffff
9914 01:18:59.702094 INFO: [APUAPC] D3_APC_2: 0x3fffff
9915 01:18:59.705025 INFO: [APUAPC] D3_APC_3: 0x0
9916 01:18:59.708503 INFO: [APUAPC] D4_APC_0: 0xffffffff
9917 01:18:59.712379 INFO: [APUAPC] D4_APC_1: 0xffffffff
9918 01:18:59.715496 INFO: [APUAPC] D4_APC_2: 0x3fffff
9919 01:18:59.718857 INFO: [APUAPC] D4_APC_3: 0x0
9920 01:18:59.721783 INFO: [APUAPC] D5_APC_0: 0xffffffff
9921 01:18:59.725650 INFO: [APUAPC] D5_APC_1: 0xffffffff
9922 01:18:59.728275 INFO: [APUAPC] D5_APC_2: 0x3fffff
9923 01:18:59.731702 INFO: [APUAPC] D5_APC_3: 0x0
9924 01:18:59.734863 INFO: [APUAPC] D6_APC_0: 0xffffffff
9925 01:18:59.738094 INFO: [APUAPC] D6_APC_1: 0xffffffff
9926 01:18:59.741394 INFO: [APUAPC] D6_APC_2: 0x3fffff
9927 01:18:59.745254 INFO: [APUAPC] D6_APC_3: 0x0
9928 01:18:59.748466 INFO: [APUAPC] D7_APC_0: 0xffffffff
9929 01:18:59.751850 INFO: [APUAPC] D7_APC_1: 0xffffffff
9930 01:18:59.754999 INFO: [APUAPC] D7_APC_2: 0x3fffff
9931 01:18:59.758694 INFO: [APUAPC] D7_APC_3: 0x0
9932 01:18:59.761875 INFO: [APUAPC] D8_APC_0: 0xffffffff
9933 01:18:59.765118 INFO: [APUAPC] D8_APC_1: 0xffffffff
9934 01:18:59.768289 INFO: [APUAPC] D8_APC_2: 0x3fffff
9935 01:18:59.771706 INFO: [APUAPC] D8_APC_3: 0x0
9936 01:18:59.774896 INFO: [APUAPC] D9_APC_0: 0xffffffff
9937 01:18:59.778193 INFO: [APUAPC] D9_APC_1: 0xffffffff
9938 01:18:59.781366 INFO: [APUAPC] D9_APC_2: 0x3fffff
9939 01:18:59.784606 INFO: [APUAPC] D9_APC_3: 0x0
9940 01:18:59.788340 INFO: [APUAPC] D10_APC_0: 0xffffffff
9941 01:18:59.791587 INFO: [APUAPC] D10_APC_1: 0xffffffff
9942 01:18:59.795074 INFO: [APUAPC] D10_APC_2: 0x3fffff
9943 01:18:59.798113 INFO: [APUAPC] D10_APC_3: 0x0
9944 01:18:59.801276 INFO: [APUAPC] D11_APC_0: 0xffffffff
9945 01:18:59.804947 INFO: [APUAPC] D11_APC_1: 0xffffffff
9946 01:18:59.808131 INFO: [APUAPC] D11_APC_2: 0x3fffff
9947 01:18:59.811639 INFO: [APUAPC] D11_APC_3: 0x0
9948 01:18:59.814705 INFO: [APUAPC] D12_APC_0: 0xffffffff
9949 01:18:59.817939 INFO: [APUAPC] D12_APC_1: 0xffffffff
9950 01:18:59.821397 INFO: [APUAPC] D12_APC_2: 0x3fffff
9951 01:18:59.824854 INFO: [APUAPC] D12_APC_3: 0x0
9952 01:18:59.827988 INFO: [APUAPC] D13_APC_0: 0xffffffff
9953 01:18:59.832079 INFO: [APUAPC] D13_APC_1: 0xffffffff
9954 01:18:59.835123 INFO: [APUAPC] D13_APC_2: 0x3fffff
9955 01:18:59.838498 INFO: [APUAPC] D13_APC_3: 0x0
9956 01:18:59.841239 INFO: [APUAPC] D14_APC_0: 0xffffffff
9957 01:18:59.844464 INFO: [APUAPC] D14_APC_1: 0xffffffff
9958 01:18:59.847756 INFO: [APUAPC] D14_APC_2: 0x3fffff
9959 01:18:59.851111 INFO: [APUAPC] D14_APC_3: 0x0
9960 01:18:59.854774 INFO: [APUAPC] D15_APC_0: 0xffffffff
9961 01:18:59.858414 INFO: [APUAPC] D15_APC_1: 0xffffffff
9962 01:18:59.861476 INFO: [APUAPC] D15_APC_2: 0x3fffff
9963 01:18:59.864690 INFO: [APUAPC] D15_APC_3: 0x0
9964 01:18:59.864818 INFO: [APUAPC] APC_CON: 0x4
9965 01:18:59.867964 INFO: [NOCDAPC] D0_APC_0: 0x0
9966 01:18:59.871199 INFO: [NOCDAPC] D0_APC_1: 0x0
9967 01:18:59.874581 INFO: [NOCDAPC] D1_APC_0: 0x0
9968 01:18:59.877825 INFO: [NOCDAPC] D1_APC_1: 0xfff
9969 01:18:59.880985 INFO: [NOCDAPC] D2_APC_0: 0x0
9970 01:18:59.884218 INFO: [NOCDAPC] D2_APC_1: 0xfff
9971 01:18:59.888147 INFO: [NOCDAPC] D3_APC_0: 0x0
9972 01:18:59.891339 INFO: [NOCDAPC] D3_APC_1: 0xfff
9973 01:18:59.894647 INFO: [NOCDAPC] D4_APC_0: 0x0
9974 01:18:59.894767 INFO: [NOCDAPC] D4_APC_1: 0xfff
9975 01:18:59.898041 INFO: [NOCDAPC] D5_APC_0: 0x0
9976 01:18:59.901233 INFO: [NOCDAPC] D5_APC_1: 0xfff
9977 01:18:59.904447 INFO: [NOCDAPC] D6_APC_0: 0x0
9978 01:18:59.907826 INFO: [NOCDAPC] D6_APC_1: 0xfff
9979 01:18:59.911023 INFO: [NOCDAPC] D7_APC_0: 0x0
9980 01:18:59.914229 INFO: [NOCDAPC] D7_APC_1: 0xfff
9981 01:18:59.917660 INFO: [NOCDAPC] D8_APC_0: 0x0
9982 01:18:59.921058 INFO: [NOCDAPC] D8_APC_1: 0xfff
9983 01:18:59.924977 INFO: [NOCDAPC] D9_APC_0: 0x0
9984 01:18:59.928109 INFO: [NOCDAPC] D9_APC_1: 0xfff
9985 01:18:59.928230 INFO: [NOCDAPC] D10_APC_0: 0x0
9986 01:18:59.931264 INFO: [NOCDAPC] D10_APC_1: 0xfff
9987 01:18:59.934471 INFO: [NOCDAPC] D11_APC_0: 0x0
9988 01:18:59.937691 INFO: [NOCDAPC] D11_APC_1: 0xfff
9989 01:18:59.941089 INFO: [NOCDAPC] D12_APC_0: 0x0
9990 01:18:59.944099 INFO: [NOCDAPC] D12_APC_1: 0xfff
9991 01:18:59.947746 INFO: [NOCDAPC] D13_APC_0: 0x0
9992 01:18:59.950732 INFO: [NOCDAPC] D13_APC_1: 0xfff
9993 01:18:59.954267 INFO: [NOCDAPC] D14_APC_0: 0x0
9994 01:18:59.957341 INFO: [NOCDAPC] D14_APC_1: 0xfff
9995 01:18:59.960918 INFO: [NOCDAPC] D15_APC_0: 0x0
9996 01:18:59.964218 INFO: [NOCDAPC] D15_APC_1: 0xfff
9997 01:18:59.967328 INFO: [NOCDAPC] APC_CON: 0x4
9998 01:18:59.970765 INFO: [APUAPC] set_apusys_apc done
9999 01:18:59.974020 INFO: [DEVAPC] devapc_init done
10000 01:18:59.977702 INFO: GICv3 without legacy support detected.
10001 01:18:59.980501 INFO: ARM GICv3 driver initialized in EL3
10002 01:18:59.984024 INFO: Maximum SPI INTID supported: 639
10003 01:18:59.987253 INFO: BL31: Initializing runtime services
10004 01:18:59.994030 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10005 01:18:59.997214 INFO: SPM: enable CPC mode
10006 01:19:00.000632 INFO: mcdi ready for mcusys-off-idle and system suspend
10007 01:19:00.007143 INFO: BL31: Preparing for EL3 exit to normal world
10008 01:19:00.010483 INFO: Entry point address = 0x80000000
10009 01:19:00.013674 INFO: SPSR = 0x8
10010 01:19:00.018569
10011 01:19:00.018694
10012 01:19:00.018764
10013 01:19:00.021626 Starting depthcharge on Spherion...
10014 01:19:00.021713
10015 01:19:00.021779 Wipe memory regions:
10016 01:19:00.021838
10017 01:19:00.022585 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10018 01:19:00.022690 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10019 01:19:00.022774 Setting prompt string to ['asurada:']
10020 01:19:00.022854 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10021 01:19:00.024945 [0x00000040000000, 0x00000054600000)
10022 01:19:00.147281
10023 01:19:00.147441 [0x00000054660000, 0x00000080000000)
10024 01:19:00.408022
10025 01:19:00.408182 [0x000000821a7280, 0x000000ffe64000)
10026 01:19:01.152573
10027 01:19:01.152728 [0x00000100000000, 0x00000240000000)
10028 01:19:03.043237
10029 01:19:03.046323 Initializing XHCI USB controller at 0x11200000.
10030 01:19:04.084693
10031 01:19:04.087721 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10032 01:19:04.087826
10033 01:19:04.087893
10034 01:19:04.087953
10035 01:19:04.088231 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10037 01:19:04.188586 asurada: tftpboot 192.168.201.1 13468730/tftp-deploy-xde3bg_r/kernel/image.itb 13468730/tftp-deploy-xde3bg_r/kernel/cmdline
10038 01:19:04.188761 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10039 01:19:04.188879 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10040 01:19:04.193296 tftpboot 192.168.201.1 13468730/tftp-deploy-xde3bg_r/kernel/image.ittp-deploy-xde3bg_r/kernel/cmdline
10041 01:19:04.193395
10042 01:19:04.193458 Waiting for link
10043 01:19:04.351713
10044 01:19:04.351849 R8152: Initializing
10045 01:19:04.351915
10046 01:19:04.354790 Version 9 (ocp_data = 6010)
10047 01:19:04.354904
10048 01:19:04.358057 R8152: Done initializing
10049 01:19:04.358169
10050 01:19:04.358262 Adding net device
10051 01:19:06.232711
10052 01:19:06.232850 done.
10053 01:19:06.232941
10054 01:19:06.233021 MAC: 00:e0:4c:78:7a:aa
10055 01:19:06.233099
10056 01:19:06.236090 Sending DHCP discover... done.
10057 01:19:06.236176
10058 01:19:06.239399 Waiting for reply... done.
10059 01:19:06.239484
10060 01:19:06.242775 Sending DHCP request... done.
10061 01:19:06.242860
10062 01:19:06.242944 Waiting for reply... done.
10063 01:19:06.243024
10064 01:19:06.246191 My ip is 192.168.201.12
10065 01:19:06.246307
10066 01:19:06.249275 The DHCP server ip is 192.168.201.1
10067 01:19:06.249385
10068 01:19:06.252744 TFTP server IP predefined by user: 192.168.201.1
10069 01:19:06.252830
10070 01:19:06.259281 Bootfile predefined by user: 13468730/tftp-deploy-xde3bg_r/kernel/image.itb
10071 01:19:06.259364
10072 01:19:06.262323 Sending tftp read request... done.
10073 01:19:06.262417
10074 01:19:06.265693 Waiting for the transfer...
10075 01:19:06.265776
10076 01:19:06.538396 00000000 ################################################################
10077 01:19:06.538538
10078 01:19:06.812072 00080000 ################################################################
10079 01:19:06.812208
10080 01:19:07.087920 00100000 ################################################################
10081 01:19:07.088064
10082 01:19:07.357098 00180000 ################################################################
10083 01:19:07.357240
10084 01:19:07.622550 00200000 ################################################################
10085 01:19:07.622709
10086 01:19:07.892442 00280000 ################################################################
10087 01:19:07.892577
10088 01:19:08.159625 00300000 ################################################################
10089 01:19:08.159771
10090 01:19:08.429771 00380000 ################################################################
10091 01:19:08.429914
10092 01:19:08.701328 00400000 ################################################################
10093 01:19:08.701460
10094 01:19:08.953044 00480000 ################################################################
10095 01:19:08.953182
10096 01:19:09.243304 00500000 ################################################################
10097 01:19:09.243455
10098 01:19:09.515702 00580000 ################################################################
10099 01:19:09.515845
10100 01:19:09.788764 00600000 ################################################################
10101 01:19:09.788897
10102 01:19:10.059160 00680000 ################################################################
10103 01:19:10.059296
10104 01:19:10.316607 00700000 ################################################################
10105 01:19:10.316754
10106 01:19:10.578125 00780000 ################################################################
10107 01:19:10.578270
10108 01:19:10.831639 00800000 ################################################################
10109 01:19:10.831784
10110 01:19:11.082009 00880000 ################################################################
10111 01:19:11.082144
10112 01:19:11.346128 00900000 ################################################################
10113 01:19:11.346263
10114 01:19:11.608604 00980000 ################################################################
10115 01:19:11.608749
10116 01:19:11.861463 00a00000 ################################################################
10117 01:19:11.861596
10118 01:19:12.115105 00a80000 ################################################################
10119 01:19:12.115235
10120 01:19:12.367238 00b00000 ################################################################
10121 01:19:12.367397
10122 01:19:12.625086 00b80000 ################################################################
10123 01:19:12.625245
10124 01:19:12.897495 00c00000 ################################################################
10125 01:19:12.897650
10126 01:19:13.183654 00c80000 ################################################################
10127 01:19:13.183785
10128 01:19:13.452645 00d00000 ################################################################
10129 01:19:13.452782
10130 01:19:13.729693 00d80000 ################################################################
10131 01:19:13.729850
10132 01:19:14.005677 00e00000 ################################################################
10133 01:19:14.005833
10134 01:19:14.270990 00e80000 ################################################################
10135 01:19:14.271145
10136 01:19:14.558222 00f00000 ################################################################
10137 01:19:14.558402
10138 01:19:14.822869 00f80000 ################################################################
10139 01:19:14.823007
10140 01:19:15.100482 01000000 ################################################################
10141 01:19:15.100621
10142 01:19:15.376054 01080000 ################################################################
10143 01:19:15.376213
10144 01:19:15.657009 01100000 ################################################################
10145 01:19:15.657140
10146 01:19:15.918586 01180000 ################################################################
10147 01:19:15.918721
10148 01:19:16.198336 01200000 ################################################################
10149 01:19:16.198486
10150 01:19:16.486046 01280000 ################################################################
10151 01:19:16.486172
10152 01:19:16.775315 01300000 ################################################################
10153 01:19:16.775459
10154 01:19:17.047191 01380000 ################################################################
10155 01:19:17.047323
10156 01:19:17.342320 01400000 ################################################################
10157 01:19:17.342466
10158 01:19:17.600590 01480000 ################################################################
10159 01:19:17.600746
10160 01:19:17.850324 01500000 ################################################################
10161 01:19:17.850473
10162 01:19:18.105938 01580000 ################################################################
10163 01:19:18.106079
10164 01:19:18.361125 01600000 ################################################################
10165 01:19:18.361256
10166 01:19:18.612137 01680000 ################################################################
10167 01:19:18.612272
10168 01:19:18.866452 01700000 ################################################################
10169 01:19:18.866598
10170 01:19:19.118802 01780000 ################################################################
10171 01:19:19.118946
10172 01:19:19.370200 01800000 ################################################################
10173 01:19:19.370385
10174 01:19:19.622261 01880000 ################################################################
10175 01:19:19.622446
10176 01:19:19.880125 01900000 ################################################################
10177 01:19:19.880264
10178 01:19:20.142946 01980000 ################################################################
10179 01:19:20.143088
10180 01:19:20.410738 01a00000 ################################################################
10181 01:19:20.410908
10182 01:19:20.665747 01a80000 ################################################################
10183 01:19:20.665885
10184 01:19:20.921344 01b00000 ################################################################
10185 01:19:20.921490
10186 01:19:21.182260 01b80000 ################################################################
10187 01:19:21.182397
10188 01:19:21.445077 01c00000 ################################################################
10189 01:19:21.445211
10190 01:19:21.711629 01c80000 ################################################################
10191 01:19:21.711759
10192 01:19:21.981530 01d00000 ################################################################
10193 01:19:21.981687
10194 01:19:22.242365 01d80000 ################################################################
10195 01:19:22.242522
10196 01:19:22.508584 01e00000 ################################################################
10197 01:19:22.508833
10198 01:19:22.770554 01e80000 ################################################################
10199 01:19:22.770704
10200 01:19:23.012944 01f00000 ################################################################
10201 01:19:23.013116
10202 01:19:23.262702 01f80000 ################################################################
10203 01:19:23.262838
10204 01:19:23.515970 02000000 ################################################################
10205 01:19:23.516103
10206 01:19:23.657240 02080000 ##################################### done.
10207 01:19:23.657368
10208 01:19:23.660542 The bootfile was 34377750 bytes long.
10209 01:19:23.660615
10210 01:19:23.663974 Sending tftp read request... done.
10211 01:19:23.664067
10212 01:19:23.667345 Waiting for the transfer...
10213 01:19:23.667426
10214 01:19:23.667490 00000000 # done.
10215 01:19:23.670895
10216 01:19:23.677127 Command line loaded dynamically from TFTP file: 13468730/tftp-deploy-xde3bg_r/kernel/cmdline
10217 01:19:23.677209
10218 01:19:23.690573 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10219 01:19:23.690660
10220 01:19:23.690723 Loading FIT.
10221 01:19:23.690783
10222 01:19:23.693802 Image ramdisk-1 has 21418436 bytes.
10223 01:19:23.693883
10224 01:19:23.697160 Image fdt-1 has 47230 bytes.
10225 01:19:23.697240
10226 01:19:23.700401 Image kernel-1 has 12910050 bytes.
10227 01:19:23.700481
10228 01:19:23.710486 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10229 01:19:23.710567
10230 01:19:23.726798 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10231 01:19:23.726884
10232 01:19:23.733383 Choosing best match conf-1 for compat google,spherion-rev2.
10233 01:19:23.733465
10234 01:19:23.741719 Connected to device vid:did:rid of 1ae0:0028:00
10235 01:19:23.749825
10236 01:19:23.752792 tpm_get_response: command 0x17b, return code 0x0
10237 01:19:23.752873
10238 01:19:23.755954 ec_init: CrosEC protocol v3 supported (256, 248)
10239 01:19:23.759997
10240 01:19:23.763335 tpm_cleanup: add release locality here.
10241 01:19:23.763416
10242 01:19:23.763479 Shutting down all USB controllers.
10243 01:19:23.766580
10244 01:19:23.766660 Removing current net device
10245 01:19:23.766724
10246 01:19:23.773233 Exiting depthcharge with code 4 at timestamp: 53078361
10247 01:19:23.773314
10248 01:19:23.776943 LZMA decompressing kernel-1 to 0x821a6718
10249 01:19:23.777024
10250 01:19:23.779674 LZMA decompressing kernel-1 to 0x40000000
10251 01:19:25.374619
10252 01:19:25.374762 jumping to kernel
10253 01:19:25.375222 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10254 01:19:25.375317 start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
10255 01:19:25.375392 Setting prompt string to ['Linux version [0-9]']
10256 01:19:25.375462 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10257 01:19:25.375528 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10258 01:19:25.456344
10259 01:19:25.459597 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10260 01:19:25.463591 start: 2.2.5.1 login-action (timeout 00:04:00) [common]
10261 01:19:25.463685 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10262 01:19:25.463754 Setting prompt string to []
10263 01:19:25.463830 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10264 01:19:25.463904 Using line separator: #'\n'#
10265 01:19:25.463962 No login prompt set.
10266 01:19:25.464022 Parsing kernel messages
10267 01:19:25.464076 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10268 01:19:25.464175 [login-action] Waiting for messages, (timeout 00:04:00)
10269 01:19:25.464238 Waiting using forced prompt support (timeout 00:02:00)
10270 01:19:25.482610 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10271 01:19:25.485976 [ 0.000000] random: crng init done
10272 01:19:25.492648 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10273 01:19:25.496216 [ 0.000000] efi: UEFI not found.
10274 01:19:25.502509 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10275 01:19:25.512705 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10276 01:19:25.519708 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10277 01:19:25.529437 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10278 01:19:25.536088 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10279 01:19:25.542810 [ 0.000000] printk: bootconsole [mtk8250] enabled
10280 01:19:25.549492 [ 0.000000] NUMA: No NUMA configuration found
10281 01:19:25.556070 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10282 01:19:25.559344 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10283 01:19:25.562752 [ 0.000000] Zone ranges:
10284 01:19:25.569348 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10285 01:19:25.572719 [ 0.000000] DMA32 empty
10286 01:19:25.579260 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10287 01:19:25.582001 [ 0.000000] Movable zone start for each node
10288 01:19:25.585848 [ 0.000000] Early memory node ranges
10289 01:19:25.592675 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10290 01:19:25.599127 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10291 01:19:25.605789 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10292 01:19:25.612345 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10293 01:19:25.615274 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10294 01:19:25.625410 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10295 01:19:25.681466 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10296 01:19:25.687518 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10297 01:19:25.694594 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10298 01:19:25.697708 [ 0.000000] psci: probing for conduit method from DT.
10299 01:19:25.704771 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10300 01:19:25.707970 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10301 01:19:25.714634 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10302 01:19:25.717748 [ 0.000000] psci: SMC Calling Convention v1.2
10303 01:19:25.724502 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10304 01:19:25.728123 [ 0.000000] Detected VIPT I-cache on CPU0
10305 01:19:25.734289 [ 0.000000] CPU features: detected: GIC system register CPU interface
10306 01:19:25.741011 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10307 01:19:25.747517 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10308 01:19:25.754071 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10309 01:19:25.760810 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10310 01:19:25.767472 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10311 01:19:25.774278 [ 0.000000] alternatives: applying boot alternatives
10312 01:19:25.780574 [ 0.000000] Fallback order for Node 0: 0
10313 01:19:25.787082 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10314 01:19:25.790420 [ 0.000000] Policy zone: Normal
10315 01:19:25.804278 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10316 01:19:25.813519 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10317 01:19:25.825559 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10318 01:19:25.835731 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10319 01:19:25.842258 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10320 01:19:25.845418 <6>[ 0.000000] software IO TLB: area num 8.
10321 01:19:25.902375 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10322 01:19:26.052009 <6>[ 0.000000] Memory: 7943592K/8385536K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 409176K reserved, 32768K cma-reserved)
10323 01:19:26.058644 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10324 01:19:26.065409 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10325 01:19:26.068240 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10326 01:19:26.074960 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10327 01:19:26.081895 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10328 01:19:26.085324 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10329 01:19:26.094611 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10330 01:19:26.101422 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10331 01:19:26.108044 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10332 01:19:26.114693 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10333 01:19:26.117981 <6>[ 0.000000] GICv3: 608 SPIs implemented
10334 01:19:26.121680 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10335 01:19:26.128327 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10336 01:19:26.131453 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10337 01:19:26.137692 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10338 01:19:26.151453 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10339 01:19:26.160913 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10340 01:19:26.171257 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10341 01:19:26.178856 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10342 01:19:26.192166 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10343 01:19:26.198493 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10344 01:19:26.205332 <6>[ 0.009236] Console: colour dummy device 80x25
10345 01:19:26.215197 <6>[ 0.013955] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10346 01:19:26.221487 <6>[ 0.024397] pid_max: default: 32768 minimum: 301
10347 01:19:26.224592 <6>[ 0.029298] LSM: Security Framework initializing
10348 01:19:26.231655 <6>[ 0.034235] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10349 01:19:26.241464 <6>[ 0.042049] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10350 01:19:26.248120 <6>[ 0.051472] cblist_init_generic: Setting adjustable number of callback queues.
10351 01:19:26.254914 <6>[ 0.058960] cblist_init_generic: Setting shift to 3 and lim to 1.
10352 01:19:26.264748 <6>[ 0.065299] cblist_init_generic: Setting adjustable number of callback queues.
10353 01:19:26.271172 <6>[ 0.072771] cblist_init_generic: Setting shift to 3 and lim to 1.
10354 01:19:26.274783 <6>[ 0.079170] rcu: Hierarchical SRCU implementation.
10355 01:19:26.281174 <6>[ 0.084186] rcu: Max phase no-delay instances is 1000.
10356 01:19:26.287917 <6>[ 0.091211] EFI services will not be available.
10357 01:19:26.290825 <6>[ 0.096165] smp: Bringing up secondary CPUs ...
10358 01:19:26.299441 <6>[ 0.101245] Detected VIPT I-cache on CPU1
10359 01:19:26.305810 <6>[ 0.101314] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10360 01:19:26.312434 <6>[ 0.101346] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10361 01:19:26.315757 <6>[ 0.101677] Detected VIPT I-cache on CPU2
10362 01:19:26.322900 <6>[ 0.101724] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10363 01:19:26.329062 <6>[ 0.101739] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10364 01:19:26.335603 <6>[ 0.101993] Detected VIPT I-cache on CPU3
10365 01:19:26.342411 <6>[ 0.102039] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10366 01:19:26.348949 <6>[ 0.102052] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10367 01:19:26.352320 <6>[ 0.102357] CPU features: detected: Spectre-v4
10368 01:19:26.359042 <6>[ 0.102363] CPU features: detected: Spectre-BHB
10369 01:19:26.362486 <6>[ 0.102369] Detected PIPT I-cache on CPU4
10370 01:19:26.368960 <6>[ 0.102426] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10371 01:19:26.375671 <6>[ 0.102443] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10372 01:19:26.381947 <6>[ 0.102739] Detected PIPT I-cache on CPU5
10373 01:19:26.388524 <6>[ 0.102802] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10374 01:19:26.395110 <6>[ 0.102818] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10375 01:19:26.398596 <6>[ 0.103099] Detected PIPT I-cache on CPU6
10376 01:19:26.405133 <6>[ 0.103164] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10377 01:19:26.411776 <6>[ 0.103180] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10378 01:19:26.418513 <6>[ 0.103476] Detected PIPT I-cache on CPU7
10379 01:19:26.424813 <6>[ 0.103542] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10380 01:19:26.431564 <6>[ 0.103558] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10381 01:19:26.434887 <6>[ 0.103606] smp: Brought up 1 node, 8 CPUs
10382 01:19:26.441607 <6>[ 0.245057] SMP: Total of 8 processors activated.
10383 01:19:26.444767 <6>[ 0.249978] CPU features: detected: 32-bit EL0 Support
10384 01:19:26.454798 <6>[ 0.255374] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10385 01:19:26.461550 <6>[ 0.264174] CPU features: detected: Common not Private translations
10386 01:19:26.467704 <6>[ 0.270650] CPU features: detected: CRC32 instructions
10387 01:19:26.470978 <6>[ 0.276002] CPU features: detected: RCpc load-acquire (LDAPR)
10388 01:19:26.477536 <6>[ 0.281962] CPU features: detected: LSE atomic instructions
10389 01:19:26.484138 <6>[ 0.287744] CPU features: detected: Privileged Access Never
10390 01:19:26.491229 <6>[ 0.293524] CPU features: detected: RAS Extension Support
10391 01:19:26.497649 <6>[ 0.299167] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10392 01:19:26.501004 <6>[ 0.306389] CPU: All CPU(s) started at EL2
10393 01:19:26.507459 <6>[ 0.310706] alternatives: applying system-wide alternatives
10394 01:19:26.517369 <6>[ 0.321521] devtmpfs: initialized
10395 01:19:26.532818 <6>[ 0.330515] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10396 01:19:26.539624 <6>[ 0.340478] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10397 01:19:26.546359 <6>[ 0.348703] pinctrl core: initialized pinctrl subsystem
10398 01:19:26.549691 <6>[ 0.355343] DMI not present or invalid.
10399 01:19:26.555896 <6>[ 0.359756] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10400 01:19:26.566029 <6>[ 0.366588] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10401 01:19:26.572633 <6>[ 0.374172] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10402 01:19:26.582447 <6>[ 0.382403] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10403 01:19:26.585904 <6>[ 0.390648] audit: initializing netlink subsys (disabled)
10404 01:19:26.595993 <5>[ 0.396347] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10405 01:19:26.602416 <6>[ 0.397064] thermal_sys: Registered thermal governor 'step_wise'
10406 01:19:26.608978 <6>[ 0.404313] thermal_sys: Registered thermal governor 'power_allocator'
10407 01:19:26.612172 <6>[ 0.410566] cpuidle: using governor menu
10408 01:19:26.618617 <6>[ 0.421524] NET: Registered PF_QIPCRTR protocol family
10409 01:19:26.625554 <6>[ 0.427026] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10410 01:19:26.632012 <6>[ 0.434133] ASID allocator initialised with 32768 entries
10411 01:19:26.635371 <6>[ 0.440707] Serial: AMBA PL011 UART driver
10412 01:19:26.644840 <4>[ 0.449465] Trying to register duplicate clock ID: 134
10413 01:19:26.701432 <6>[ 0.509057] KASLR enabled
10414 01:19:26.715652 <6>[ 0.516690] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10415 01:19:26.722689 <6>[ 0.523703] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10416 01:19:26.728649 <6>[ 0.530188] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10417 01:19:26.735299 <6>[ 0.537192] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10418 01:19:26.741961 <6>[ 0.543679] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10419 01:19:26.748565 <6>[ 0.550683] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10420 01:19:26.755047 <6>[ 0.557173] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10421 01:19:26.761885 <6>[ 0.564177] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10422 01:19:26.764900 <6>[ 0.571644] ACPI: Interpreter disabled.
10423 01:19:26.774005 <6>[ 0.578059] iommu: Default domain type: Translated
10424 01:19:26.780027 <6>[ 0.583206] iommu: DMA domain TLB invalidation policy: strict mode
10425 01:19:26.783846 <5>[ 0.589864] SCSI subsystem initialized
10426 01:19:26.790289 <6>[ 0.594119] usbcore: registered new interface driver usbfs
10427 01:19:26.796972 <6>[ 0.599851] usbcore: registered new interface driver hub
10428 01:19:26.800002 <6>[ 0.605404] usbcore: registered new device driver usb
10429 01:19:26.807546 <6>[ 0.611527] pps_core: LinuxPPS API ver. 1 registered
10430 01:19:26.817345 <6>[ 0.616718] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10431 01:19:26.820430 <6>[ 0.626062] PTP clock support registered
10432 01:19:26.823465 <6>[ 0.630301] EDAC MC: Ver: 3.0.0
10433 01:19:26.830937 <6>[ 0.635461] FPGA manager framework
10434 01:19:26.834378 <6>[ 0.639136] Advanced Linux Sound Architecture Driver Initialized.
10435 01:19:26.838313 <6>[ 0.645917] vgaarb: loaded
10436 01:19:26.844913 <6>[ 0.649074] clocksource: Switched to clocksource arch_sys_counter
10437 01:19:26.851602 <5>[ 0.655517] VFS: Disk quotas dquot_6.6.0
10438 01:19:26.858101 <6>[ 0.659705] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10439 01:19:26.861357 <6>[ 0.666897] pnp: PnP ACPI: disabled
10440 01:19:26.869274 <6>[ 0.673597] NET: Registered PF_INET protocol family
10441 01:19:26.879087 <6>[ 0.679188] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10442 01:19:26.890256 <6>[ 0.691509] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10443 01:19:26.900760 <6>[ 0.700321] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10444 01:19:26.907196 <6>[ 0.708293] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10445 01:19:26.913605 <6>[ 0.716998] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10446 01:19:26.925751 <6>[ 0.726754] TCP: Hash tables configured (established 65536 bind 65536)
10447 01:19:26.932621 <6>[ 0.733627] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10448 01:19:26.939467 <6>[ 0.740826] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10449 01:19:26.945392 <6>[ 0.748531] NET: Registered PF_UNIX/PF_LOCAL protocol family
10450 01:19:26.951981 <6>[ 0.754671] RPC: Registered named UNIX socket transport module.
10451 01:19:26.955228 <6>[ 0.760823] RPC: Registered udp transport module.
10452 01:19:26.961871 <6>[ 0.765755] RPC: Registered tcp transport module.
10453 01:19:26.968854 <6>[ 0.770688] RPC: Registered tcp NFSv4.1 backchannel transport module.
10454 01:19:26.972136 <6>[ 0.777353] PCI: CLS 0 bytes, default 64
10455 01:19:26.975564 <6>[ 0.781700] Unpacking initramfs...
10456 01:19:26.996778 <6>[ 0.797656] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10457 01:19:27.006963 <6>[ 0.806289] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10458 01:19:27.009804 <6>[ 0.815131] kvm [1]: IPA Size Limit: 40 bits
10459 01:19:27.016495 <6>[ 0.819674] kvm [1]: GICv3: no GICV resource entry
10460 01:19:27.020023 <6>[ 0.824695] kvm [1]: disabling GICv2 emulation
10461 01:19:27.026414 <6>[ 0.829379] kvm [1]: GIC system register CPU interface enabled
10462 01:19:27.029974 <6>[ 0.835542] kvm [1]: vgic interrupt IRQ18
10463 01:19:27.036436 <6>[ 0.839901] kvm [1]: VHE mode initialized successfully
10464 01:19:27.043034 <5>[ 0.846390] Initialise system trusted keyrings
10465 01:19:27.049419 <6>[ 0.851192] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10466 01:19:27.057072 <6>[ 0.861250] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10467 01:19:27.063958 <5>[ 0.867649] NFS: Registering the id_resolver key type
10468 01:19:27.067178 <5>[ 0.872970] Key type id_resolver registered
10469 01:19:27.073968 <5>[ 0.877384] Key type id_legacy registered
10470 01:19:27.080695 <6>[ 0.881664] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10471 01:19:27.087066 <6>[ 0.888587] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10472 01:19:27.093134 <6>[ 0.896303] 9p: Installing v9fs 9p2000 file system support
10473 01:19:27.130640 <5>[ 0.934848] Key type asymmetric registered
10474 01:19:27.133983 <5>[ 0.939178] Asymmetric key parser 'x509' registered
10475 01:19:27.143837 <6>[ 0.944319] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10476 01:19:27.147102 <6>[ 0.951934] io scheduler mq-deadline registered
10477 01:19:27.150247 <6>[ 0.956712] io scheduler kyber registered
10478 01:19:27.169106 <6>[ 0.973768] EINJ: ACPI disabled.
10479 01:19:27.202257 <4>[ 0.999582] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10480 01:19:27.211635 <4>[ 1.010192] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10481 01:19:27.226473 <6>[ 1.030870] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10482 01:19:27.234407 <6>[ 1.038801] printk: console [ttyS0] disabled
10483 01:19:27.262443 <6>[ 1.063427] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10484 01:19:27.269038 <6>[ 1.072899] printk: console [ttyS0] enabled
10485 01:19:27.272504 <6>[ 1.072899] printk: console [ttyS0] enabled
10486 01:19:27.278887 <6>[ 1.081793] printk: bootconsole [mtk8250] disabled
10487 01:19:27.282240 <6>[ 1.081793] printk: bootconsole [mtk8250] disabled
10488 01:19:27.289027 <6>[ 1.092822] SuperH (H)SCI(F) driver initialized
10489 01:19:27.292388 <6>[ 1.098100] msm_serial: driver initialized
10490 01:19:27.306419 <6>[ 1.106945] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10491 01:19:27.315712 <6>[ 1.115492] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10492 01:19:27.322400 <6>[ 1.124034] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10493 01:19:27.332370 <6>[ 1.132660] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10494 01:19:27.342060 <6>[ 1.141366] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10495 01:19:27.348799 <6>[ 1.150087] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10496 01:19:27.358703 <6>[ 1.158629] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10497 01:19:27.365274 <6>[ 1.167425] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10498 01:19:27.374991 <6>[ 1.175967] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10499 01:19:27.387293 <6>[ 1.191481] loop: module loaded
10500 01:19:27.393473 <6>[ 1.197370] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10501 01:19:27.416073 <4>[ 1.220486] mtk-pmic-keys: Failed to locate of_node [id: -1]
10502 01:19:27.422633 <6>[ 1.227342] megasas: 07.719.03.00-rc1
10503 01:19:27.432623 <6>[ 1.237017] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10504 01:19:27.439927 <6>[ 1.244465] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10505 01:19:27.457044 <6>[ 1.261320] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10506 01:19:27.514004 <6>[ 1.311573] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10507 01:19:27.906131 <6>[ 1.710432] Freeing initrd memory: 20912K
10508 01:19:27.921703 <6>[ 1.726296] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10509 01:19:27.933497 <6>[ 1.737519] tun: Universal TUN/TAP device driver, 1.6
10510 01:19:27.936331 <6>[ 1.743593] thunder_xcv, ver 1.0
10511 01:19:27.939692 <6>[ 1.747098] thunder_bgx, ver 1.0
10512 01:19:27.942968 <6>[ 1.750592] nicpf, ver 1.0
10513 01:19:27.953619 <6>[ 1.754628] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10514 01:19:27.956960 <6>[ 1.762105] hns3: Copyright (c) 2017 Huawei Corporation.
10515 01:19:27.960052 <6>[ 1.767693] hclge is initializing
10516 01:19:27.967089 <6>[ 1.771274] e1000: Intel(R) PRO/1000 Network Driver
10517 01:19:27.973308 <6>[ 1.776404] e1000: Copyright (c) 1999-2006 Intel Corporation.
10518 01:19:27.977285 <6>[ 1.782417] e1000e: Intel(R) PRO/1000 Network Driver
10519 01:19:27.983858 <6>[ 1.787632] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10520 01:19:27.990269 <6>[ 1.793820] igb: Intel(R) Gigabit Ethernet Network Driver
10521 01:19:27.996940 <6>[ 1.799471] igb: Copyright (c) 2007-2014 Intel Corporation.
10522 01:19:28.003575 <6>[ 1.805308] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10523 01:19:28.010289 <6>[ 1.811825] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10524 01:19:28.013341 <6>[ 1.818287] sky2: driver version 1.30
10525 01:19:28.020044 <6>[ 1.823284] VFIO - User Level meta-driver version: 0.3
10526 01:19:28.027523 <6>[ 1.831520] usbcore: registered new interface driver usb-storage
10527 01:19:28.033687 <6>[ 1.837961] usbcore: registered new device driver onboard-usb-hub
10528 01:19:28.042722 <6>[ 1.847141] mt6397-rtc mt6359-rtc: registered as rtc0
10529 01:19:28.052898 <6>[ 1.852609] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:15:16 UTC (1713834916)
10530 01:19:28.056129 <6>[ 1.862175] i2c_dev: i2c /dev entries driver
10531 01:19:28.072844 <6>[ 1.874072] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10532 01:19:28.079585 <4>[ 1.882801] cpu cpu0: supply cpu not found, using dummy regulator
10533 01:19:28.086192 <4>[ 1.889223] cpu cpu1: supply cpu not found, using dummy regulator
10534 01:19:28.092989 <4>[ 1.895647] cpu cpu2: supply cpu not found, using dummy regulator
10535 01:19:28.099702 <4>[ 1.902044] cpu cpu3: supply cpu not found, using dummy regulator
10536 01:19:28.106425 <4>[ 1.908439] cpu cpu4: supply cpu not found, using dummy regulator
10537 01:19:28.113134 <4>[ 1.914837] cpu cpu5: supply cpu not found, using dummy regulator
10538 01:19:28.119664 <4>[ 1.921235] cpu cpu6: supply cpu not found, using dummy regulator
10539 01:19:28.123036 <4>[ 1.927651] cpu cpu7: supply cpu not found, using dummy regulator
10540 01:19:28.144016 <6>[ 1.948294] cpu cpu0: EM: created perf domain
10541 01:19:28.147328 <6>[ 1.953234] cpu cpu4: EM: created perf domain
10542 01:19:28.154685 <6>[ 1.958793] sdhci: Secure Digital Host Controller Interface driver
10543 01:19:28.160864 <6>[ 1.965228] sdhci: Copyright(c) Pierre Ossman
10544 01:19:28.167760 <6>[ 1.970179] Synopsys Designware Multimedia Card Interface Driver
10545 01:19:28.174386 <6>[ 1.976809] sdhci-pltfm: SDHCI platform and OF driver helper
10546 01:19:28.177937 <6>[ 1.976921] mmc0: CQHCI version 5.10
10547 01:19:28.184570 <6>[ 1.986782] ledtrig-cpu: registered to indicate activity on CPUs
10548 01:19:28.191313 <6>[ 1.993929] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10549 01:19:28.197925 <6>[ 2.000986] usbcore: registered new interface driver usbhid
10550 01:19:28.201071 <6>[ 2.006811] usbhid: USB HID core driver
10551 01:19:28.207600 <6>[ 2.011007] spi_master spi0: will run message pump with realtime priority
10552 01:19:28.252172 <6>[ 2.049862] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10553 01:19:28.271547 <6>[ 2.065806] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10554 01:19:28.275157 <6>[ 2.080074] mmc0: Command Queue Engine enabled
10555 01:19:28.281403 <6>[ 2.084856] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10556 01:19:28.288511 <6>[ 2.091625] cros-ec-spi spi0.0: Chrome EC device registered
10557 01:19:28.291085 <6>[ 2.092063] mmcblk0: mmc0:0001 DA4128 116 GiB
10558 01:19:28.309058 <6>[ 2.113388] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10559 01:19:28.318875 <6>[ 2.115363] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10560 01:19:28.325730 <6>[ 2.120585] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10561 01:19:28.328713 <6>[ 2.129913] NET: Registered PF_PACKET protocol family
10562 01:19:28.335216 <6>[ 2.134477] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10563 01:19:28.338554 <6>[ 2.139219] 9pnet: Installing 9P2000 support
10564 01:19:28.345187 <6>[ 2.144994] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10565 01:19:28.352118 <5>[ 2.148927] Key type dns_resolver registered
10566 01:19:28.355163 <6>[ 2.160367] registered taskstats version 1
10567 01:19:28.358846 <5>[ 2.164746] Loading compiled-in X.509 certificates
10568 01:19:28.390504 <4>[ 2.188326] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10569 01:19:28.400678 <4>[ 2.199050] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10570 01:19:28.406868 <3>[ 2.209584] debugfs: File 'uA_load' in directory '/' already present!
10571 01:19:28.413855 <3>[ 2.216287] debugfs: File 'min_uV' in directory '/' already present!
10572 01:19:28.420621 <3>[ 2.222952] debugfs: File 'max_uV' in directory '/' already present!
10573 01:19:28.427235 <3>[ 2.229574] debugfs: File 'constraint_flags' in directory '/' already present!
10574 01:19:28.438240 <3>[ 2.239263] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10575 01:19:28.447799 <6>[ 2.251956] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10576 01:19:28.454248 <6>[ 2.258819] xhci-mtk 11200000.usb: xHCI Host Controller
10577 01:19:28.460751 <6>[ 2.264323] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10578 01:19:28.471359 <6>[ 2.272164] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10579 01:19:28.478056 <6>[ 2.281600] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10580 01:19:28.484506 <6>[ 2.287669] xhci-mtk 11200000.usb: xHCI Host Controller
10581 01:19:28.491078 <6>[ 2.293151] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10582 01:19:28.497582 <6>[ 2.300796] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10583 01:19:28.504179 <6>[ 2.308670] hub 1-0:1.0: USB hub found
10584 01:19:28.507463 <6>[ 2.312690] hub 1-0:1.0: 1 port detected
10585 01:19:28.514078 <6>[ 2.316954] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10586 01:19:28.521321 <6>[ 2.325687] hub 2-0:1.0: USB hub found
10587 01:19:28.524572 <6>[ 2.329706] hub 2-0:1.0: 1 port detected
10588 01:19:28.532744 <6>[ 2.337505] mtk-msdc 11f70000.mmc: Got CD GPIO
10589 01:19:28.543499 <6>[ 2.344556] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10590 01:19:28.550184 <6>[ 2.352588] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10591 01:19:28.559911 <4>[ 2.360561] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10592 01:19:28.569753 <6>[ 2.370094] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10593 01:19:28.576392 <6>[ 2.378173] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10594 01:19:28.586196 <6>[ 2.386338] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10595 01:19:28.593460 <6>[ 2.394291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10596 01:19:28.599434 <6>[ 2.402110] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10597 01:19:28.610036 <6>[ 2.409929] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10598 01:19:28.619625 <6>[ 2.420357] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10599 01:19:28.626447 <6>[ 2.428720] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10600 01:19:28.636486 <6>[ 2.437060] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10601 01:19:28.642627 <6>[ 2.445400] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10602 01:19:28.652636 <6>[ 2.453738] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10603 01:19:28.659390 <6>[ 2.462076] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10604 01:19:28.669423 <6>[ 2.470413] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10605 01:19:28.678957 <6>[ 2.478753] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10606 01:19:28.685958 <6>[ 2.487091] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10607 01:19:28.695985 <6>[ 2.495429] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10608 01:19:28.702337 <6>[ 2.503776] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10609 01:19:28.712504 <6>[ 2.512114] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10610 01:19:28.719027 <6>[ 2.520454] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10611 01:19:28.729066 <6>[ 2.528792] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10612 01:19:28.735364 <6>[ 2.537130] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10613 01:19:28.742224 <6>[ 2.545957] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10614 01:19:28.748723 <6>[ 2.553285] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10615 01:19:28.755601 <6>[ 2.560220] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10616 01:19:28.765589 <6>[ 2.567123] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10617 01:19:28.772295 <6>[ 2.574179] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10618 01:19:28.779285 <6>[ 2.581052] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10619 01:19:28.789208 <6>[ 2.590185] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10620 01:19:28.799179 <6>[ 2.599304] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10621 01:19:28.809093 <6>[ 2.608597] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10622 01:19:28.818920 <6>[ 2.618080] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10623 01:19:28.825775 <6>[ 2.627547] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10624 01:19:28.835378 <6>[ 2.636666] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10625 01:19:28.845276 <6>[ 2.646134] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10626 01:19:28.855730 <6>[ 2.655254] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10627 01:19:28.865218 <6>[ 2.664548] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10628 01:19:28.874982 <6>[ 2.674708] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10629 01:19:28.885106 <6>[ 2.686454] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10630 01:19:28.931983 <6>[ 2.733346] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10631 01:19:29.086908 <6>[ 2.891320] hub 1-1:1.0: USB hub found
10632 01:19:29.090036 <6>[ 2.895847] hub 1-1:1.0: 4 ports detected
10633 01:19:29.100019 <6>[ 2.904679] hub 1-1:1.0: USB hub found
10634 01:19:29.103547 <6>[ 2.909011] hub 1-1:1.0: 4 ports detected
10635 01:19:29.212378 <6>[ 3.013679] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10636 01:19:29.238022 <6>[ 3.042856] hub 2-1:1.0: USB hub found
10637 01:19:29.241826 <6>[ 3.047329] hub 2-1:1.0: 3 ports detected
10638 01:19:29.250904 <6>[ 3.055329] hub 2-1:1.0: USB hub found
10639 01:19:29.254264 <6>[ 3.059842] hub 2-1:1.0: 3 ports detected
10640 01:19:29.427933 <6>[ 3.229386] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10641 01:19:29.560132 <6>[ 3.365003] hub 1-1.4:1.0: USB hub found
10642 01:19:29.563836 <6>[ 3.369663] hub 1-1.4:1.0: 2 ports detected
10643 01:19:29.572236 <6>[ 3.376858] hub 1-1.4:1.0: USB hub found
10644 01:19:29.575642 <6>[ 3.381370] hub 1-1.4:1.0: 2 ports detected
10645 01:19:29.644208 <6>[ 3.445478] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10646 01:19:29.872049 <6>[ 3.673390] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10647 01:19:30.063843 <6>[ 3.865373] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10648 01:19:41.181354 <6>[ 14.990404] ALSA device list:
10649 01:19:41.187582 <6>[ 14.993693] No soundcards found.
10650 01:19:41.195659 <6>[ 15.001646] Freeing unused kernel memory: 8448K
10651 01:19:41.198883 <6>[ 15.007118] Run /init as init process
10652 01:19:41.221398 Starting syslogd: OK
10653 01:19:41.224649 Starting klogd: OK
10654 01:19:41.232384 Running sysctl: OK
10655 01:19:41.242600 Populating /dev using udev: <30>[ 15.047141] udevd[196]: starting version 3.2.9
10656 01:19:41.250425 <27>[ 15.056321] udevd[196]: specified user 'tss' unknown
10657 01:19:41.257014 <27>[ 15.061712] udevd[196]: specified group 'tss' unknown
10658 01:19:41.263679 <30>[ 15.068311] udevd[197]: starting eudev-3.2.9
10659 01:19:41.418254 <6>[ 15.220762] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10660 01:19:41.424897 <6>[ 15.228485] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10661 01:19:41.434890 <6>[ 15.237332] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10662 01:19:41.450871 <6>[ 15.256937] usbcore: registered new device driver r8152-cfgselector
10663 01:19:41.460809 <6>[ 15.259519] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10664 01:19:41.471107 <3>[ 15.273606] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 01:19:41.477542 <4>[ 15.273872] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10666 01:19:41.484494 <6>[ 15.278049] remoteproc remoteproc0: scp is available
10667 01:19:41.487867 <6>[ 15.278561] remoteproc remoteproc0: powering up scp
10668 01:19:41.497617 <6>[ 15.278567] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10669 01:19:41.503993 <6>[ 15.278585] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10670 01:19:41.510498 <3>[ 15.281780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 01:19:41.517169 <3>[ 15.281793] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 01:19:41.527416 <3>[ 15.281874] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 01:19:41.530814 <6>[ 15.288010] mc: Linux media interface: v0.10
10674 01:19:41.537575 <4>[ 15.289275] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10675 01:19:41.547016 <3>[ 15.294418] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 01:19:41.554021 <6>[ 15.338481] videodev: Linux video capture interface: v2.00
10677 01:19:41.560372 <3>[ 15.343244] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 01:19:41.567232 <6>[ 15.371673] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10679 01:19:41.576916 <3>[ 15.372054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 01:19:41.580451 <6>[ 15.378888] pci_bus 0000:00: root bus resource [bus 00-ff]
10681 01:19:41.590203 <6>[ 15.386994] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10682 01:19:41.596855 <3>[ 15.387038] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 01:19:41.606903 <6>[ 15.387610] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10684 01:19:41.613354 <6>[ 15.392950] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10685 01:19:41.619926 <3>[ 15.401300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 01:19:41.629850 <6>[ 15.409412] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10687 01:19:41.636700 <6>[ 15.409414] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10688 01:19:41.646852 <6>[ 15.409722] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10689 01:19:41.653631 <6>[ 15.409788] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10690 01:19:41.660161 <6>[ 15.409805] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10691 01:19:41.667151 <6>[ 15.409876] pci 0000:00:00.0: supports D1 D2
10692 01:19:41.670863 <6>[ 15.409878] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10693 01:19:41.680804 <6>[ 15.410896] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10694 01:19:41.687328 <6>[ 15.410977] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10695 01:19:41.694186 <6>[ 15.411002] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10696 01:19:41.700993 <6>[ 15.411017] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10697 01:19:41.708004 <6>[ 15.411032] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10698 01:19:41.714040 <6>[ 15.411134] pci 0000:01:00.0: supports D1 D2
10699 01:19:41.720916 <6>[ 15.411136] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10700 01:19:41.730912 <6>[ 15.412327] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10701 01:19:41.740844 <6>[ 15.412674] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10702 01:19:41.747662 <4>[ 15.412791] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10703 01:19:41.757224 <4>[ 15.412799] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10704 01:19:41.767297 <6>[ 15.415105] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10705 01:19:41.773722 <3>[ 15.417388] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 01:19:41.783970 <4>[ 15.419039] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10707 01:19:41.787406 <4>[ 15.419039] Fallback method does not support PEC.
10708 01:19:41.793929 <6>[ 15.424371] remoteproc remoteproc0: remote processor scp is now up
10709 01:19:41.800308 <6>[ 15.427460] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10710 01:19:41.810692 <6>[ 15.427519] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10711 01:19:41.817041 <6>[ 15.427526] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10712 01:19:41.826980 <6>[ 15.427542] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10713 01:19:41.833673 <6>[ 15.427558] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10714 01:19:41.840285 <6>[ 15.427575] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10715 01:19:41.846905 <6>[ 15.427591] pci 0000:00:00.0: PCI bridge to [bus 01]
10716 01:19:41.853031 <6>[ 15.427601] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10717 01:19:41.859577 <6>[ 15.427859] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10718 01:19:41.866491 <6>[ 15.432055] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10719 01:19:41.872932 <6>[ 15.432335] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10720 01:19:41.879624 <3>[ 15.432556] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 01:19:41.889674 <3>[ 15.432568] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 01:19:41.895852 <3>[ 15.432678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 01:19:41.906002 <3>[ 15.432682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 01:19:41.912667 <3>[ 15.432685] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 01:19:41.922481 <3>[ 15.432691] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 01:19:41.929203 <3>[ 15.432694] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 01:19:41.939328 <3>[ 15.432722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 01:19:41.942484 <6>[ 15.442137] Bluetooth: Core ver 2.22
10729 01:19:41.948559 <6>[ 15.443093] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10730 01:19:41.958593 <6>[ 15.444412] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10731 01:19:41.961954 <6>[ 15.465525] r8152 2-1.3:1.0 eth0: v1.12.13
10732 01:19:41.968768 <5>[ 15.466155] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10733 01:19:41.974995 <6>[ 15.471726] NET: Registered PF_BLUETOOTH protocol family
10734 01:19:41.981459 <6>[ 15.474480] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10735 01:19:41.994538 <6>[ 15.475489] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10736 01:19:42.001542 <6>[ 15.475595] usbcore: registered new interface driver uvcvideo
10737 01:19:42.008121 <6>[ 15.476621] usbcore: registered new interface driver r8152
10738 01:19:42.015230 <6>[ 15.477608] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10739 01:19:42.021245 <3>[ 15.481767] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10740 01:19:42.027902 <6>[ 15.483087] Bluetooth: HCI device and connection manager initialized
10741 01:19:42.034836 <6>[ 15.483130] Bluetooth: HCI socket layer initialized
10742 01:19:42.038185 <6>[ 15.483154] Bluetooth: L2CAP socket layer initialized
10743 01:19:42.044345 <6>[ 15.483177] Bluetooth: SCO socket layer initialized
10744 01:19:42.051003 <5>[ 15.488693] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10745 01:19:42.057990 <5>[ 15.488926] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10746 01:19:42.068042 <4>[ 15.488982] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10747 01:19:42.074382 <6>[ 15.488988] cfg80211: failed to load regulatory.db
10748 01:19:42.081205 <3>[ 15.504234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10749 01:19:42.087703 <6>[ 15.513683] usbcore: registered new interface driver cdc_ether
10750 01:19:42.093831 <6>[ 15.551445] usbcore: registered new interface driver btusb
10751 01:19:42.104195 <4>[ 15.552980] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10752 01:19:42.110952 <3>[ 15.552998] Bluetooth: hci0: Failed to load firmware file (-2)
10753 01:19:42.117525 <3>[ 15.553001] Bluetooth: hci0: Failed to set up firmware (-2)
10754 01:19:42.127531 <4>[ 15.553003] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10755 01:19:42.133537 <6>[ 15.568359] usbcore: registered new interface driver r8153_ecm
10756 01:19:42.140245 <6>[ 15.578495] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10757 01:19:42.146961 <6>[ 15.951343] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10758 01:19:42.171437 <6>[ 15.977467] mt7921e 0000:01:00.0: ASIC revision: 79610010
10759 01:19:42.274218 <6>[ 16.076892] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10760 01:19:42.277405 <6>[ 16.076892]
10761 01:19:42.285065 done
10762 01:19:42.295024 Saving random seed: OK
10763 01:19:42.311802 Starting network: OK
10764 01:19:42.342309 Starting dropbear sshd: <6>[ 16.148537] NET: Registered PF_INET6 protocol family
10765 01:19:42.348836 <6>[ 16.154958] Segment Routing with IPv6
10766 01:19:42.352147 <6>[ 16.158926] In-situ OAM (IOAM) with IPv6
10767 01:19:42.355493 OK
10768 01:19:42.364855 /bin/sh: can't access tty; job control turned off
10769 01:19:42.365391 Matched prompt #10: / #
10771 01:19:42.365704 Setting prompt string to ['/ #']
10772 01:19:42.365832 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10774 01:19:42.366141 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10775 01:19:42.366257 start: 2.2.6 expect-shell-connection (timeout 00:03:43) [common]
10776 01:19:42.366402 Setting prompt string to ['/ #']
10777 01:19:42.366489 Forcing a shell prompt, looking for ['/ #']
10779 01:19:42.416736 / #
10780 01:19:42.416841 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10781 01:19:42.416937 Waiting using forced prompt support (timeout 00:02:30)
10782 01:19:42.421796
10783 01:19:42.422091 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10784 01:19:42.422206 start: 2.2.7 export-device-env (timeout 00:03:43) [common]
10785 01:19:42.422367 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10786 01:19:42.422453 end: 2.2 depthcharge-retry (duration 00:01:17) [common]
10787 01:19:42.422538 end: 2 depthcharge-action (duration 00:01:17) [common]
10788 01:19:42.422622 start: 3 lava-test-retry (timeout 00:01:00) [common]
10789 01:19:42.422701 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10790 01:19:42.422777 Using namespace: common
10792 01:19:42.523049 / # #
10793 01:19:42.523198 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10794 01:19:42.528236 #
10795 01:19:42.528527 Using /lava-13468730
10797 01:19:42.628857 / # export SHELL=/bin/sh
10798 01:19:42.629050 <6>[ 16.346977] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10799 01:19:42.635075 export SHELL=/bin/sh
10801 01:19:42.735525 / # . /lava-13468730/environment
10802 01:19:42.740779 . /lava-13468730/environment
10804 01:19:42.841284 / # /lava-13468730/bin/lava-test-runner /lava-13468730/0
10805 01:19:42.841409 Test shell timeout: 10s (minimum of the action and connection timeout)
10806 01:19:42.847020 /lava-13468730/bin/lava-test-runner /lava-13468730/0
10807 01:19:42.865104 + export 'TESTRUN_ID=0_dmesg'
10808 01:19:42.871715 +<8>[ 16.676086] <LAVA_SIGNAL_STARTRUN 0_dmesg 13468730_1.5.2.3.1>
10809 01:19:42.871993 Received signal: <STARTRUN> 0_dmesg 13468730_1.5.2.3.1
10810 01:19:42.872091 Starting test lava.0_dmesg (13468730_1.5.2.3.1)
10811 01:19:42.872215 Skipping test definition patterns.
10812 01:19:42.874791 cd /lava-13468730/0/tests/0_dmesg
10813 01:19:42.874867 + cat uuid
10814 01:19:42.877917 + UUID=13468730_1.5.2.3.1
10815 01:19:42.878017 + set +x
10816 01:19:42.884737 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10817 01:19:42.894602 <8>[ 16.695818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10818 01:19:42.894882 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10820 01:19:42.911917 <8>[ 16.714846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10821 01:19:42.912191 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10823 01:19:42.932195 <8>[ 16.735066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10824 01:19:42.932486 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10826 01:19:42.935913 + set +x
10827 01:19:42.939072 <8>[ 16.744505] <LAVA_SIGNAL_ENDRUN 0_dmesg 13468730_1.5.2.3.1>
10828 01:19:42.939319 Received signal: <ENDRUN> 0_dmesg 13468730_1.5.2.3.1
10829 01:19:42.939398 Ending use of test pattern.
10830 01:19:42.939458 Ending test lava.0_dmesg (13468730_1.5.2.3.1), duration 0.07
10832 01:19:42.942272 <LAVA_TEST_RUNNER EXIT>
10833 01:19:42.942636 ok: lava_test_shell seems to have completed
10834 01:19:42.942740 alert: pass
crit: pass
emerg: pass
10835 01:19:42.942827 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10836 01:19:42.942907 end: 3 lava-test-retry (duration 00:00:01) [common]
10837 01:19:42.942987 start: 4 finalize (timeout 00:08:24) [common]
10838 01:19:42.943074 start: 4.1 power-off (timeout 00:00:30) [common]
10839 01:19:42.943225 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
10840 01:19:43.024862 >> Command sent successfully.
10841 01:19:43.027668 Returned 0 in 0 seconds
10842 01:19:43.128079 end: 4.1 power-off (duration 00:00:00) [common]
10844 01:19:43.128397 start: 4.2 read-feedback (timeout 00:08:24) [common]
10845 01:19:43.128653 Listened to connection for namespace 'common' for up to 1s
10846 01:19:44.129581 Finalising connection for namespace 'common'
10847 01:19:44.129740 Disconnecting from shell: Finalise
10848 01:19:44.129817 / #
10849 01:19:44.230133 end: 4.2 read-feedback (duration 00:00:01) [common]
10850 01:19:44.230341 end: 4 finalize (duration 00:00:01) [common]
10851 01:19:44.230465 Cleaning after the job
10852 01:19:44.230559 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/ramdisk
10853 01:19:44.233120 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/kernel
10854 01:19:44.240495 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/dtb
10855 01:19:44.240667 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468730/tftp-deploy-xde3bg_r/modules
10856 01:19:44.246174 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468730
10857 01:19:44.287327 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468730
10858 01:19:44.287480 Job finished correctly