Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 23
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
1 01:18:17.917341 lava-dispatcher, installed at version: 2024.01
2 01:18:17.917643 start: 0 validate
3 01:18:17.917804 Start time: 2024-04-23 01:18:17.917795+00:00 (UTC)
4 01:18:17.917980 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:18:17.918121 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:18:18.178720 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:18:18.178984 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:18:18.433694 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:18:18.433980 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:18:18.688440 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:18:18.688671 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:18:18.945789 validate duration: 1.03
14 01:18:18.946415 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:18:18.946662 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:18:18.946887 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:18:18.947255 Not decompressing ramdisk as can be used compressed.
18 01:18:18.947545 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 01:18:18.947775 saving as /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/ramdisk/rootfs.cpio.gz
20 01:18:18.948030 total size: 39026414 (37 MB)
21 01:18:18.954593 progress 0 % (0 MB)
22 01:18:18.978738 progress 5 % (1 MB)
23 01:18:18.995397 progress 10 % (3 MB)
24 01:18:19.006933 progress 15 % (5 MB)
25 01:18:19.017276 progress 20 % (7 MB)
26 01:18:19.027389 progress 25 % (9 MB)
27 01:18:19.037364 progress 30 % (11 MB)
28 01:18:19.047363 progress 35 % (13 MB)
29 01:18:19.057606 progress 40 % (14 MB)
30 01:18:19.068038 progress 45 % (16 MB)
31 01:18:19.078398 progress 50 % (18 MB)
32 01:18:19.088787 progress 55 % (20 MB)
33 01:18:19.098652 progress 60 % (22 MB)
34 01:18:19.108729 progress 65 % (24 MB)
35 01:18:19.118911 progress 70 % (26 MB)
36 01:18:19.129103 progress 75 % (27 MB)
37 01:18:19.138935 progress 80 % (29 MB)
38 01:18:19.149168 progress 85 % (31 MB)
39 01:18:19.159261 progress 90 % (33 MB)
40 01:18:19.169173 progress 95 % (35 MB)
41 01:18:19.179097 progress 100 % (37 MB)
42 01:18:19.179419 37 MB downloaded in 0.23 s (160.84 MB/s)
43 01:18:19.179621 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:18:19.179997 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:18:19.180118 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:18:19.180235 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:18:19.180403 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:18:19.180502 saving as /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/kernel/Image
50 01:18:19.180591 total size: 54352384 (51 MB)
51 01:18:19.180684 No compression specified
52 01:18:19.182264 progress 0 % (0 MB)
53 01:18:19.196504 progress 5 % (2 MB)
54 01:18:19.211052 progress 10 % (5 MB)
55 01:18:19.225543 progress 15 % (7 MB)
56 01:18:19.239811 progress 20 % (10 MB)
57 01:18:19.253900 progress 25 % (12 MB)
58 01:18:19.267596 progress 30 % (15 MB)
59 01:18:19.281258 progress 35 % (18 MB)
60 01:18:19.294935 progress 40 % (20 MB)
61 01:18:19.308691 progress 45 % (23 MB)
62 01:18:19.322775 progress 50 % (25 MB)
63 01:18:19.336749 progress 55 % (28 MB)
64 01:18:19.350721 progress 60 % (31 MB)
65 01:18:19.364462 progress 65 % (33 MB)
66 01:18:19.378177 progress 70 % (36 MB)
67 01:18:19.391830 progress 75 % (38 MB)
68 01:18:19.405318 progress 80 % (41 MB)
69 01:18:19.419018 progress 85 % (44 MB)
70 01:18:19.432797 progress 90 % (46 MB)
71 01:18:19.446693 progress 95 % (49 MB)
72 01:18:19.460645 progress 100 % (51 MB)
73 01:18:19.460928 51 MB downloaded in 0.28 s (184.90 MB/s)
74 01:18:19.461077 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:18:19.461352 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:18:19.461440 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:18:19.461550 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:18:19.461723 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:18:19.461793 saving as /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/dtb/mt8192-asurada-spherion-r0.dtb
81 01:18:19.461854 total size: 47230 (0 MB)
82 01:18:19.461916 No compression specified
83 01:18:19.463092 progress 69 % (0 MB)
84 01:18:19.463463 progress 100 % (0 MB)
85 01:18:19.463631 0 MB downloaded in 0.00 s (25.39 MB/s)
86 01:18:19.463751 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:18:19.464032 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:18:19.464130 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:18:19.464212 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:18:19.464359 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:18:19.464440 saving as /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/modules/modules.tar
93 01:18:19.464501 total size: 8638160 (8 MB)
94 01:18:19.464576 Using unxz to decompress xz
95 01:18:19.468915 progress 0 % (0 MB)
96 01:18:19.487882 progress 5 % (0 MB)
97 01:18:19.512004 progress 10 % (0 MB)
98 01:18:19.535903 progress 15 % (1 MB)
99 01:18:19.558800 progress 20 % (1 MB)
100 01:18:19.583053 progress 25 % (2 MB)
101 01:18:19.608352 progress 30 % (2 MB)
102 01:18:19.631921 progress 35 % (2 MB)
103 01:18:19.656365 progress 40 % (3 MB)
104 01:18:19.680229 progress 45 % (3 MB)
105 01:18:19.705887 progress 50 % (4 MB)
106 01:18:19.730251 progress 55 % (4 MB)
107 01:18:19.757167 progress 60 % (4 MB)
108 01:18:19.781696 progress 65 % (5 MB)
109 01:18:19.805926 progress 70 % (5 MB)
110 01:18:19.829724 progress 75 % (6 MB)
111 01:18:19.854685 progress 80 % (6 MB)
112 01:18:19.882329 progress 85 % (7 MB)
113 01:18:19.908034 progress 90 % (7 MB)
114 01:18:19.936398 progress 95 % (7 MB)
115 01:18:19.962572 progress 100 % (8 MB)
116 01:18:19.968266 8 MB downloaded in 0.50 s (16.35 MB/s)
117 01:18:19.968593 end: 1.4.1 http-download (duration 00:00:01) [common]
119 01:18:19.968858 end: 1.4 download-retry (duration 00:00:01) [common]
120 01:18:19.968948 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:18:19.969041 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:18:19.969118 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:18:19.969203 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:18:19.969428 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays
125 01:18:19.969597 makedir: /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin
126 01:18:19.969700 makedir: /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/tests
127 01:18:19.969795 makedir: /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/results
128 01:18:19.969908 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-add-keys
129 01:18:19.970050 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-add-sources
130 01:18:19.970175 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-background-process-start
131 01:18:19.970311 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-background-process-stop
132 01:18:19.970435 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-common-functions
133 01:18:19.970555 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-echo-ipv4
134 01:18:19.970674 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-install-packages
135 01:18:19.970793 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-installed-packages
136 01:18:19.970913 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-os-build
137 01:18:19.971032 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-probe-channel
138 01:18:19.971153 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-probe-ip
139 01:18:19.971272 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-target-ip
140 01:18:19.971391 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-target-mac
141 01:18:19.971508 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-target-storage
142 01:18:19.971630 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-test-case
143 01:18:19.971748 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-test-event
144 01:18:19.971867 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-test-feedback
145 01:18:19.971985 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-test-raise
146 01:18:19.972107 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-test-reference
147 01:18:19.972225 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-test-runner
148 01:18:19.972350 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-test-set
149 01:18:19.972471 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-test-shell
150 01:18:19.972594 Updating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-install-packages (oe)
151 01:18:19.972739 Updating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/bin/lava-installed-packages (oe)
152 01:18:19.972855 Creating /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/environment
153 01:18:19.972951 LAVA metadata
154 01:18:19.973024 - LAVA_JOB_ID=13468751
155 01:18:19.973086 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:18:19.973185 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:18:19.973252 skipped lava-vland-overlay
158 01:18:19.973323 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:18:19.973401 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:18:19.973462 skipped lava-multinode-overlay
161 01:18:19.973544 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:18:19.973673 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:18:19.973747 Loading test definitions
164 01:18:19.973834 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:18:19.973908 Using /lava-13468751 at stage 0
166 01:18:19.974222 uuid=13468751_1.5.2.3.1 testdef=None
167 01:18:19.974310 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:18:19.974398 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:18:19.974895 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:18:19.975110 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:18:19.975728 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:18:19.975953 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:18:19.976737 runner path: /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/0/tests/0_cros-ec test_uuid 13468751_1.5.2.3.1
176 01:18:19.976928 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:18:19.977258 Creating lava-test-runner.conf files
179 01:18:19.977347 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468751/lava-overlay-trs93ays/lava-13468751/0 for stage 0
180 01:18:19.977463 - 0_cros-ec
181 01:18:19.977637 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:18:19.977733 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 01:18:19.985335 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:18:19.985435 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 01:18:19.985529 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:18:19.985613 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:18:19.985698 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 01:18:21.185163 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 01:18:21.185579 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 01:18:21.185705 extracting modules file /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468751/extract-overlay-ramdisk-9ja2etyo/ramdisk
191 01:18:21.427064 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:18:21.427225 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 01:18:21.427316 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468751/compress-overlay-kd_kx9d_/overlay-1.5.2.4.tar.gz to ramdisk
194 01:18:21.427385 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468751/compress-overlay-kd_kx9d_/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468751/extract-overlay-ramdisk-9ja2etyo/ramdisk
195 01:18:21.433956 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:18:21.434063 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 01:18:21.434151 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:18:21.434238 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 01:18:21.434312 Building ramdisk /var/lib/lava/dispatcher/tmp/13468751/extract-overlay-ramdisk-9ja2etyo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468751/extract-overlay-ramdisk-9ja2etyo/ramdisk
200 01:18:22.324266 >> 336160 blocks
201 01:18:27.606891 rename /var/lib/lava/dispatcher/tmp/13468751/extract-overlay-ramdisk-9ja2etyo/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/ramdisk/ramdisk.cpio.gz
202 01:18:27.607346 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 01:18:27.607470 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 01:18:27.607571 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 01:18:27.607680 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/kernel/Image'
206 01:18:40.724931 Returned 0 in 13 seconds
207 01:18:40.825554 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/kernel/image.itb
208 01:18:41.585359 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:18:41.585837 output: Created: Tue Apr 23 02:18:41 2024
210 01:18:41.585916 output: Image 0 (kernel-1)
211 01:18:41.585981 output: Description:
212 01:18:41.586042 output: Created: Tue Apr 23 02:18:41 2024
213 01:18:41.586100 output: Type: Kernel Image
214 01:18:41.586159 output: Compression: lzma compressed
215 01:18:41.586215 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
216 01:18:41.586271 output: Architecture: AArch64
217 01:18:41.586326 output: OS: Linux
218 01:18:41.586380 output: Load Address: 0x00000000
219 01:18:41.586436 output: Entry Point: 0x00000000
220 01:18:41.586490 output: Hash algo: crc32
221 01:18:41.586547 output: Hash value: 1126c3f9
222 01:18:41.586603 output: Image 1 (fdt-1)
223 01:18:41.586659 output: Description: mt8192-asurada-spherion-r0
224 01:18:41.586711 output: Created: Tue Apr 23 02:18:41 2024
225 01:18:41.586763 output: Type: Flat Device Tree
226 01:18:41.586815 output: Compression: uncompressed
227 01:18:41.586866 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 01:18:41.586918 output: Architecture: AArch64
229 01:18:41.586969 output: Hash algo: crc32
230 01:18:41.587020 output: Hash value: 4bf0d1ac
231 01:18:41.587071 output: Image 2 (ramdisk-1)
232 01:18:41.587121 output: Description: unavailable
233 01:18:41.587172 output: Created: Tue Apr 23 02:18:41 2024
234 01:18:41.587223 output: Type: RAMDisk Image
235 01:18:41.587274 output: Compression: Unknown Compression
236 01:18:41.587325 output: Data Size: 52181228 Bytes = 50958.23 KiB = 49.76 MiB
237 01:18:41.587376 output: Architecture: AArch64
238 01:18:41.587427 output: OS: Linux
239 01:18:41.587478 output: Load Address: unavailable
240 01:18:41.587528 output: Entry Point: unavailable
241 01:18:41.587579 output: Hash algo: crc32
242 01:18:41.587630 output: Hash value: c1bdff87
243 01:18:41.587681 output: Default Configuration: 'conf-1'
244 01:18:41.587732 output: Configuration 0 (conf-1)
245 01:18:41.587783 output: Description: mt8192-asurada-spherion-r0
246 01:18:41.587835 output: Kernel: kernel-1
247 01:18:41.587886 output: Init Ramdisk: ramdisk-1
248 01:18:41.587936 output: FDT: fdt-1
249 01:18:41.587987 output: Loadables: kernel-1
250 01:18:41.588039 output:
251 01:18:41.588272 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 01:18:41.588371 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 01:18:41.588483 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 01:18:41.588590 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 01:18:41.588682 No LXC device requested
256 01:18:41.588781 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:18:41.588890 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 01:18:41.589009 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:18:41.589121 Checking files for TFTP limit of 4294967296 bytes.
260 01:18:41.589816 end: 1 tftp-deploy (duration 00:00:23) [common]
261 01:18:41.589956 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:18:41.590087 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:18:41.590228 substitutions:
264 01:18:41.590301 - {DTB}: 13468751/tftp-deploy-efs9j2v9/dtb/mt8192-asurada-spherion-r0.dtb
265 01:18:41.590403 - {INITRD}: 13468751/tftp-deploy-efs9j2v9/ramdisk/ramdisk.cpio.gz
266 01:18:41.590500 - {KERNEL}: 13468751/tftp-deploy-efs9j2v9/kernel/Image
267 01:18:41.590597 - {LAVA_MAC}: None
268 01:18:41.590692 - {PRESEED_CONFIG}: None
269 01:18:41.590786 - {PRESEED_LOCAL}: None
270 01:18:41.590879 - {RAMDISK}: 13468751/tftp-deploy-efs9j2v9/ramdisk/ramdisk.cpio.gz
271 01:18:41.590972 - {ROOT_PART}: None
272 01:18:41.591065 - {ROOT}: None
273 01:18:41.591157 - {SERVER_IP}: 192.168.201.1
274 01:18:41.591249 - {TEE}: None
275 01:18:41.591341 Parsed boot commands:
276 01:18:41.591433 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:18:41.591664 Parsed boot commands: tftpboot 192.168.201.1 13468751/tftp-deploy-efs9j2v9/kernel/image.itb 13468751/tftp-deploy-efs9j2v9/kernel/cmdline
278 01:18:41.591788 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:18:41.591917 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:18:41.592051 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:18:41.592179 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:18:41.592287 Not connected, no need to disconnect.
283 01:18:41.592403 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:18:41.592526 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:18:41.592626 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 01:18:41.596485 Setting prompt string to ['lava-test: # ']
287 01:18:41.596882 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:18:41.597027 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:18:41.597163 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:18:41.597295 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:18:41.597613 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 01:18:46.744649 >> Command sent successfully.
293 01:18:46.754866 Returned 0 in 5 seconds
294 01:18:46.856128 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 01:18:46.857921 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 01:18:46.858536 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 01:18:46.859185 Setting prompt string to 'Starting depthcharge on Spherion...'
299 01:18:46.859697 Changing prompt to 'Starting depthcharge on Spherion...'
300 01:18:46.860326 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 01:18:46.862271 [Enter `^Ec?' for help]
302 01:18:47.019211
303 01:18:47.019392
304 01:18:47.019497 F0: 102B 0000
305 01:18:47.019595
306 01:18:47.019687 F3: 1001 0000 [0200]
307 01:18:47.019783
308 01:18:47.022636 F3: 1001 0000
309 01:18:47.022737
310 01:18:47.022833 F7: 102D 0000
311 01:18:47.022923
312 01:18:47.023018 F1: 0000 0000
313 01:18:47.026155
314 01:18:47.026271 V0: 0000 0000 [0001]
315 01:18:47.026378
316 01:18:47.026478 00: 0007 8000
317 01:18:47.026565
318 01:18:47.030405 01: 0000 0000
319 01:18:47.030509
320 01:18:47.030606 BP: 0C00 0209 [0000]
321 01:18:47.030700
322 01:18:47.030788 G0: 1182 0000
323 01:18:47.033974
324 01:18:47.034084 EC: 0000 0021 [4000]
325 01:18:47.034177
326 01:18:47.034276 S7: 0000 0000 [0000]
327 01:18:47.037846
328 01:18:47.037961 CC: 0000 0000 [0001]
329 01:18:47.038058
330 01:18:47.041267 T0: 0000 0040 [010F]
331 01:18:47.041366
332 01:18:47.041457 Jump to BL
333 01:18:47.041558
334 01:18:47.066027
335 01:18:47.066119
336 01:18:47.066187
337 01:18:47.073378 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 01:18:47.076175 ARM64: Exception handlers installed.
339 01:18:47.080266 ARM64: Testing exception
340 01:18:47.084001 ARM64: Done test exception
341 01:18:47.091184 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 01:18:47.102193 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 01:18:47.105938 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 01:18:47.116554 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 01:18:47.122938 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 01:18:47.133451 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 01:18:47.144371 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 01:18:47.150661 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 01:18:47.168559 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 01:18:47.172093 WDT: Last reset was cold boot
351 01:18:47.175161 SPI1(PAD0) initialized at 2873684 Hz
352 01:18:47.178599 SPI5(PAD0) initialized at 992727 Hz
353 01:18:47.181628 VBOOT: Loading verstage.
354 01:18:47.188899 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 01:18:47.191680 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 01:18:47.195319 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 01:18:47.198337 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 01:18:47.206118 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 01:18:47.212876 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 01:18:47.223891 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 01:18:47.223983
362 01:18:47.224065
363 01:18:47.233787 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 01:18:47.236765 ARM64: Exception handlers installed.
365 01:18:47.240136 ARM64: Testing exception
366 01:18:47.240217 ARM64: Done test exception
367 01:18:47.247676 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 01:18:47.251102 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 01:18:47.264579 Probing TPM: . done!
370 01:18:47.264674 TPM ready after 0 ms
371 01:18:47.270914 Connected to device vid:did:rid of 1ae0:0028:00
372 01:18:47.319074 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 01:18:47.319232 Initialized TPM device CR50 revision 0
374 01:18:47.331277 tlcl_send_startup: Startup return code is 0
375 01:18:47.331389 TPM: setup succeeded
376 01:18:47.342466 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 01:18:47.351555 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 01:18:47.364106 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 01:18:47.372676 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 01:18:47.376083 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 01:18:47.379207 in-header: 03 07 00 00 08 00 00 00
382 01:18:47.382975 in-data: aa e4 47 04 13 02 00 00
383 01:18:47.386459 Chrome EC: UHEPI supported
384 01:18:47.393284 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 01:18:47.396849 in-header: 03 9d 00 00 08 00 00 00
386 01:18:47.400349 in-data: 10 20 20 08 00 00 00 00
387 01:18:47.400513 Phase 1
388 01:18:47.404402 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 01:18:47.412087 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 01:18:47.419203 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 01:18:47.419337 Recovery requested (1009000e)
392 01:18:47.428156 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 01:18:47.433673 tlcl_extend: response is 0
394 01:18:47.441410 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 01:18:47.447321 tlcl_extend: response is 0
396 01:18:47.453460 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 01:18:47.474642 read SPI 0x210d4 0x2173b: 15148 us, 9045 KB/s, 72.360 Mbps
398 01:18:47.481475 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 01:18:47.481629
400 01:18:47.481701
401 01:18:47.489329 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 01:18:47.492994 ARM64: Exception handlers installed.
403 01:18:47.496546 ARM64: Testing exception
404 01:18:47.500020 ARM64: Done test exception
405 01:18:47.520075 pmic_efuse_setting: Set efuses in 11 msecs
406 01:18:47.523756 pmwrap_interface_init: Select PMIF_VLD_RDY
407 01:18:47.527324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 01:18:47.534726 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 01:18:47.538885 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 01:18:47.542542 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 01:18:47.550115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 01:18:47.553381 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 01:18:47.557276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 01:18:47.564214 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 01:18:47.567538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 01:18:47.571204 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 01:18:47.577642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 01:18:47.580763 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 01:18:47.584124 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 01:18:47.591850 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 01:18:47.598325 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 01:18:47.604841 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 01:18:47.608347 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 01:18:47.614730 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 01:18:47.621592 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 01:18:47.625792 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 01:18:47.633040 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 01:18:47.636470 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 01:18:47.643015 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 01:18:47.650290 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 01:18:47.653726 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 01:18:47.660658 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 01:18:47.664327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 01:18:47.670478 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 01:18:47.673860 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 01:18:47.677325 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 01:18:47.684484 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 01:18:47.688031 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 01:18:47.695487 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 01:18:47.699221 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 01:18:47.703033 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 01:18:47.710426 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 01:18:47.713883 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 01:18:47.717322 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 01:18:47.724037 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 01:18:47.727422 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 01:18:47.730785 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 01:18:47.737368 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 01:18:47.740894 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 01:18:47.744254 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 01:18:47.750343 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 01:18:47.753624 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 01:18:47.757364 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 01:18:47.763754 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 01:18:47.767258 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 01:18:47.770183 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 01:18:47.773972 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 01:18:47.783443 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 01:18:47.790699 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 01:18:47.796847 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 01:18:47.803359 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 01:18:47.813861 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 01:18:47.817015 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 01:18:47.820485 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 01:18:47.826844 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 01:18:47.833600 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x15
467 01:18:47.836996 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 01:18:47.844373 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 01:18:47.847810 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 01:18:47.857237 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 01:18:47.860551 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 01:18:47.867644 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 01:18:47.870802 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
474 01:18:47.874114 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 01:18:47.877680 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
476 01:18:47.880580 ADC[4]: Raw value=898150 ID=7
477 01:18:47.884067 ADC[3]: Raw value=213440 ID=1
478 01:18:47.884696 RAM Code: 0x71
479 01:18:47.890889 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 01:18:47.893924 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 01:18:47.904740 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 01:18:47.910834 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 01:18:47.914510 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 01:18:47.918027 in-header: 03 07 00 00 08 00 00 00
485 01:18:47.920984 in-data: aa e4 47 04 13 02 00 00
486 01:18:47.924690 Chrome EC: UHEPI supported
487 01:18:47.927634 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 01:18:47.932368 in-header: 03 d5 00 00 08 00 00 00
489 01:18:47.935881 in-data: 98 20 60 08 00 00 00 00
490 01:18:47.939344 MRC: failed to locate region type 0.
491 01:18:47.946091 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 01:18:47.949367 DRAM-K: Running full calibration
493 01:18:47.956194 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 01:18:47.956620 header.status = 0x0
495 01:18:47.959659 header.version = 0x6 (expected: 0x6)
496 01:18:47.963841 header.size = 0xd00 (expected: 0xd00)
497 01:18:47.966593 header.flags = 0x0
498 01:18:47.973226 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 01:18:47.989625 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
500 01:18:47.996580 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 01:18:47.999926 dram_init: ddr_geometry: 2
502 01:18:48.002654 [EMI] MDL number = 2
503 01:18:48.003144 [EMI] Get MDL freq = 0
504 01:18:48.006381 dram_init: ddr_type: 0
505 01:18:48.006850 is_discrete_lpddr4: 1
506 01:18:48.009443 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 01:18:48.009989
508 01:18:48.010380
509 01:18:48.012918 [Bian_co] ETT version 0.0.0.1
510 01:18:48.019306 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 01:18:48.019793
512 01:18:48.023105 dramc_set_vcore_voltage set vcore to 650000
513 01:18:48.023607 Read voltage for 800, 4
514 01:18:48.026310 Vio18 = 0
515 01:18:48.027108 Vcore = 650000
516 01:18:48.027681 Vdram = 0
517 01:18:48.029169 Vddq = 0
518 01:18:48.029838 Vmddr = 0
519 01:18:48.032889 dram_init: config_dvfs: 1
520 01:18:48.036085 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 01:18:48.042893 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 01:18:48.046183 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 01:18:48.049450 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 01:18:48.052771 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 01:18:48.056383 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 01:18:48.059678 MEM_TYPE=3, freq_sel=18
527 01:18:48.062574 sv_algorithm_assistance_LP4_1600
528 01:18:48.066209 ============ PULL DRAM RESETB DOWN ============
529 01:18:48.069430 ========== PULL DRAM RESETB DOWN end =========
530 01:18:48.076103 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 01:18:48.079339 ===================================
532 01:18:48.082792 LPDDR4 DRAM CONFIGURATION
533 01:18:48.085879 ===================================
534 01:18:48.086311 EX_ROW_EN[0] = 0x0
535 01:18:48.089260 EX_ROW_EN[1] = 0x0
536 01:18:48.089867 LP4Y_EN = 0x0
537 01:18:48.092779 WORK_FSP = 0x0
538 01:18:48.093334 WL = 0x2
539 01:18:48.096266 RL = 0x2
540 01:18:48.096821 BL = 0x2
541 01:18:48.099379 RPST = 0x0
542 01:18:48.099936 RD_PRE = 0x0
543 01:18:48.102798 WR_PRE = 0x1
544 01:18:48.103352 WR_PST = 0x0
545 01:18:48.105734 DBI_WR = 0x0
546 01:18:48.106296 DBI_RD = 0x0
547 01:18:48.110351 OTF = 0x1
548 01:18:48.113201 ===================================
549 01:18:48.116159 ===================================
550 01:18:48.116609 ANA top config
551 01:18:48.119299 ===================================
552 01:18:48.123206 DLL_ASYNC_EN = 0
553 01:18:48.126309 ALL_SLAVE_EN = 1
554 01:18:48.129240 NEW_RANK_MODE = 1
555 01:18:48.129783 DLL_IDLE_MODE = 1
556 01:18:48.132516 LP45_APHY_COMB_EN = 1
557 01:18:48.135897 TX_ODT_DIS = 1
558 01:18:48.139563 NEW_8X_MODE = 1
559 01:18:48.142622 ===================================
560 01:18:48.145991 ===================================
561 01:18:48.149350 data_rate = 1600
562 01:18:48.149826 CKR = 1
563 01:18:48.152880 DQ_P2S_RATIO = 8
564 01:18:48.155793 ===================================
565 01:18:48.159449 CA_P2S_RATIO = 8
566 01:18:48.162484 DQ_CA_OPEN = 0
567 01:18:48.165953 DQ_SEMI_OPEN = 0
568 01:18:48.169315 CA_SEMI_OPEN = 0
569 01:18:48.169782 CA_FULL_RATE = 0
570 01:18:48.172728 DQ_CKDIV4_EN = 1
571 01:18:48.176163 CA_CKDIV4_EN = 1
572 01:18:48.178874 CA_PREDIV_EN = 0
573 01:18:48.182378 PH8_DLY = 0
574 01:18:48.185779 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 01:18:48.186216 DQ_AAMCK_DIV = 4
576 01:18:48.189028 CA_AAMCK_DIV = 4
577 01:18:48.192500 CA_ADMCK_DIV = 4
578 01:18:48.195978 DQ_TRACK_CA_EN = 0
579 01:18:48.198902 CA_PICK = 800
580 01:18:48.202365 CA_MCKIO = 800
581 01:18:48.202793 MCKIO_SEMI = 0
582 01:18:48.206417 PLL_FREQ = 3068
583 01:18:48.209935 DQ_UI_PI_RATIO = 32
584 01:18:48.213429 CA_UI_PI_RATIO = 0
585 01:18:48.216927 ===================================
586 01:18:48.220791 ===================================
587 01:18:48.221098 memory_type:LPDDR4
588 01:18:48.224336 GP_NUM : 10
589 01:18:48.224758 SRAM_EN : 1
590 01:18:48.227337 MD32_EN : 0
591 01:18:48.231486 ===================================
592 01:18:48.235271 [ANA_INIT] >>>>>>>>>>>>>>
593 01:18:48.235576 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 01:18:48.238669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 01:18:48.242815 ===================================
596 01:18:48.245901 data_rate = 1600,PCW = 0X7600
597 01:18:48.249698 ===================================
598 01:18:48.253333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 01:18:48.257061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 01:18:48.264464 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 01:18:48.267742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 01:18:48.271484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 01:18:48.274835 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 01:18:48.278968 [ANA_INIT] flow start
605 01:18:48.279268 [ANA_INIT] PLL >>>>>>>>
606 01:18:48.282653 [ANA_INIT] PLL <<<<<<<<
607 01:18:48.282950 [ANA_INIT] MIDPI >>>>>>>>
608 01:18:48.286048 [ANA_INIT] MIDPI <<<<<<<<
609 01:18:48.289851 [ANA_INIT] DLL >>>>>>>>
610 01:18:48.290262 [ANA_INIT] flow end
611 01:18:48.293533 ============ LP4 DIFF to SE enter ============
612 01:18:48.297096 ============ LP4 DIFF to SE exit ============
613 01:18:48.300912 [ANA_INIT] <<<<<<<<<<<<<
614 01:18:48.304466 [Flow] Enable top DCM control >>>>>
615 01:18:48.308325 [Flow] Enable top DCM control <<<<<
616 01:18:48.312288 Enable DLL master slave shuffle
617 01:18:48.315794 ==============================================================
618 01:18:48.319388 Gating Mode config
619 01:18:48.323474 ==============================================================
620 01:18:48.326960 Config description:
621 01:18:48.334034 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 01:18:48.341015 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 01:18:48.344491 SELPH_MODE 0: By rank 1: By Phase
624 01:18:48.351034 ==============================================================
625 01:18:48.354527 GAT_TRACK_EN = 1
626 01:18:48.357842 RX_GATING_MODE = 2
627 01:18:48.361058 RX_GATING_TRACK_MODE = 2
628 01:18:48.364401 SELPH_MODE = 1
629 01:18:48.367848 PICG_EARLY_EN = 1
630 01:18:48.370840 VALID_LAT_VALUE = 1
631 01:18:48.374204 ==============================================================
632 01:18:48.377851 Enter into Gating configuration >>>>
633 01:18:48.380585 Exit from Gating configuration <<<<
634 01:18:48.384019 Enter into DVFS_PRE_config >>>>>
635 01:18:48.397557 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 01:18:48.397655 Exit from DVFS_PRE_config <<<<<
637 01:18:48.400679 Enter into PICG configuration >>>>
638 01:18:48.404203 Exit from PICG configuration <<<<
639 01:18:48.407678 [RX_INPUT] configuration >>>>>
640 01:18:48.411251 [RX_INPUT] configuration <<<<<
641 01:18:48.417445 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 01:18:48.421097 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 01:18:48.427355 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 01:18:48.434050 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 01:18:48.441095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 01:18:48.447288 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 01:18:48.450405 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 01:18:48.453966 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 01:18:48.457168 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 01:18:48.463942 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 01:18:48.467772 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 01:18:48.471341 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 01:18:48.474803 ===================================
654 01:18:48.478940 LPDDR4 DRAM CONFIGURATION
655 01:18:48.479030 ===================================
656 01:18:48.482373 EX_ROW_EN[0] = 0x0
657 01:18:48.485779 EX_ROW_EN[1] = 0x0
658 01:18:48.485886 LP4Y_EN = 0x0
659 01:18:48.486040 WORK_FSP = 0x0
660 01:18:48.489121 WL = 0x2
661 01:18:48.489225 RL = 0x2
662 01:18:48.493318 BL = 0x2
663 01:18:48.493423 RPST = 0x0
664 01:18:48.496320 RD_PRE = 0x0
665 01:18:48.496424 WR_PRE = 0x1
666 01:18:48.500099 WR_PST = 0x0
667 01:18:48.500207 DBI_WR = 0x0
668 01:18:48.503921 DBI_RD = 0x0
669 01:18:48.504029 OTF = 0x1
670 01:18:48.507425 ===================================
671 01:18:48.511174 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 01:18:48.514759 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 01:18:48.522096 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 01:18:48.526070 ===================================
675 01:18:48.526272 LPDDR4 DRAM CONFIGURATION
676 01:18:48.529503 ===================================
677 01:18:48.532936 EX_ROW_EN[0] = 0x10
678 01:18:48.533060 EX_ROW_EN[1] = 0x0
679 01:18:48.537092 LP4Y_EN = 0x0
680 01:18:48.537194 WORK_FSP = 0x0
681 01:18:48.540797 WL = 0x2
682 01:18:48.540880 RL = 0x2
683 01:18:48.540946 BL = 0x2
684 01:18:48.544437 RPST = 0x0
685 01:18:48.544519 RD_PRE = 0x0
686 01:18:48.547964 WR_PRE = 0x1
687 01:18:48.548047 WR_PST = 0x0
688 01:18:48.551638 DBI_WR = 0x0
689 01:18:48.551721 DBI_RD = 0x0
690 01:18:48.554997 OTF = 0x1
691 01:18:48.559254 ===================================
692 01:18:48.562477 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 01:18:48.568296 nWR fixed to 40
694 01:18:48.568728 [ModeRegInit_LP4] CH0 RK0
695 01:18:48.571889 [ModeRegInit_LP4] CH0 RK1
696 01:18:48.575692 [ModeRegInit_LP4] CH1 RK0
697 01:18:48.576129 [ModeRegInit_LP4] CH1 RK1
698 01:18:48.579522 match AC timing 13
699 01:18:48.583050 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 01:18:48.587044 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 01:18:48.590578 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 01:18:48.598188 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 01:18:48.602352 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 01:18:48.602805 [EMI DOE] emi_dcm 0
705 01:18:48.605972 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 01:18:48.606570 ==
707 01:18:48.609451 Dram Type= 6, Freq= 0, CH_0, rank 0
708 01:18:48.613035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 01:18:48.616707 ==
710 01:18:48.620402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 01:18:48.627534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 01:18:48.636071 [CA 0] Center 38 (7~69) winsize 63
713 01:18:48.639275 [CA 1] Center 37 (7~68) winsize 62
714 01:18:48.643036 [CA 2] Center 35 (5~66) winsize 62
715 01:18:48.647080 [CA 3] Center 35 (5~66) winsize 62
716 01:18:48.650704 [CA 4] Center 34 (4~65) winsize 62
717 01:18:48.654589 [CA 5] Center 34 (4~65) winsize 62
718 01:18:48.655187
719 01:18:48.655655 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 01:18:48.658282
721 01:18:48.658813 [CATrainingPosCal] consider 1 rank data
722 01:18:48.662470 u2DelayCellTimex100 = 270/100 ps
723 01:18:48.665807 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 01:18:48.669784 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 01:18:48.672985 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 01:18:48.677167 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 01:18:48.680712 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 01:18:48.684681 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 01:18:48.685110
730 01:18:48.688272 CA PerBit enable=1, Macro0, CA PI delay=34
731 01:18:48.688865
732 01:18:48.692532 [CBTSetCACLKResult] CA Dly = 34
733 01:18:48.693004 CS Dly: 6 (0~37)
734 01:18:48.693575 ==
735 01:18:48.695814 Dram Type= 6, Freq= 0, CH_0, rank 1
736 01:18:48.699417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 01:18:48.703424 ==
738 01:18:48.706810 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 01:18:48.713707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 01:18:48.721972 [CA 0] Center 38 (7~69) winsize 63
741 01:18:48.725458 [CA 1] Center 38 (7~69) winsize 63
742 01:18:48.729233 [CA 2] Center 35 (5~66) winsize 62
743 01:18:48.733087 [CA 3] Center 35 (5~66) winsize 62
744 01:18:48.736606 [CA 4] Center 34 (4~65) winsize 62
745 01:18:48.740343 [CA 5] Center 34 (4~65) winsize 62
746 01:18:48.740900
747 01:18:48.744928 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 01:18:48.745345
749 01:18:48.748230 [CATrainingPosCal] consider 2 rank data
750 01:18:48.748800 u2DelayCellTimex100 = 270/100 ps
751 01:18:48.751659 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 01:18:48.757980 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 01:18:48.761562 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 01:18:48.764409 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 01:18:48.768115 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 01:18:48.771543 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 01:18:48.772002
758 01:18:48.774250 CA PerBit enable=1, Macro0, CA PI delay=34
759 01:18:48.774694
760 01:18:48.777915 [CBTSetCACLKResult] CA Dly = 34
761 01:18:48.781313 CS Dly: 6 (0~38)
762 01:18:48.781787
763 01:18:48.784674 ----->DramcWriteLeveling(PI) begin...
764 01:18:48.785152 ==
765 01:18:48.788062 Dram Type= 6, Freq= 0, CH_0, rank 0
766 01:18:48.791287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 01:18:48.791734 ==
768 01:18:48.794719 Write leveling (Byte 0): 31 => 31
769 01:18:48.797734 Write leveling (Byte 1): 31 => 31
770 01:18:48.801224 DramcWriteLeveling(PI) end<-----
771 01:18:48.801690
772 01:18:48.802071 ==
773 01:18:48.804621 Dram Type= 6, Freq= 0, CH_0, rank 0
774 01:18:48.807732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 01:18:48.808168 ==
776 01:18:48.811079 [Gating] SW mode calibration
777 01:18:48.817807 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 01:18:48.824708 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 01:18:48.828229 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 01:18:48.831123 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 01:18:48.837917 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
782 01:18:48.841043 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 01:18:48.844466 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 01:18:48.847650 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 01:18:48.854451 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 01:18:48.857416 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 01:18:48.861016 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 01:18:48.865292 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 01:18:48.872918 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 01:18:48.876092 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 01:18:48.879478 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 01:18:48.883150 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 01:18:48.890526 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 01:18:48.894107 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 01:18:48.897501 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 01:18:48.900794 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 01:18:48.907034 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
798 01:18:48.910489 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 01:18:48.914100 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 01:18:48.920874 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 01:18:48.923813 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 01:18:48.927142 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 01:18:48.933878 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 01:18:48.937458 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 01:18:48.940408 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 01:18:48.947265 0 9 12 | B1->B0 | 2424 3333 | 0 0 | (1 1) (0 0)
807 01:18:48.950496 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 01:18:48.954201 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 01:18:48.960961 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 01:18:48.963952 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 01:18:48.967443 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 01:18:48.974102 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 01:18:48.977671 0 10 8 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
814 01:18:48.981148 0 10 12 | B1->B0 | 2e2e 2525 | 1 0 | (1 0) (0 0)
815 01:18:48.987463 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 01:18:48.990921 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 01:18:48.994171 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 01:18:49.000638 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 01:18:49.004148 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 01:18:49.007049 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 01:18:49.010662 0 11 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
822 01:18:49.017062 0 11 12 | B1->B0 | 3030 4040 | 0 1 | (0 0) (0 0)
823 01:18:49.020519 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 01:18:49.023986 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 01:18:49.030916 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 01:18:49.033875 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 01:18:49.037128 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 01:18:49.043792 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
829 01:18:49.046721 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 01:18:49.050533 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 01:18:49.057030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 01:18:49.060249 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 01:18:49.063845 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 01:18:49.070158 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 01:18:49.074099 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 01:18:49.076976 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 01:18:49.084131 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 01:18:49.086956 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 01:18:49.090884 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 01:18:49.097087 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 01:18:49.100634 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 01:18:49.103382 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 01:18:49.109967 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 01:18:49.113434 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 01:18:49.116984 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 01:18:49.123681 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 01:18:49.124118 Total UI for P1: 0, mck2ui 16
848 01:18:49.126524 best dqsien dly found for B0: ( 0, 14, 8)
849 01:18:49.130290 Total UI for P1: 0, mck2ui 16
850 01:18:49.133454 best dqsien dly found for B1: ( 0, 14, 10)
851 01:18:49.136835 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
852 01:18:49.143716 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
853 01:18:49.144421
854 01:18:49.146624 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
855 01:18:49.150134 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 01:18:49.153630 [Gating] SW calibration Done
857 01:18:49.154093 ==
858 01:18:49.156668 Dram Type= 6, Freq= 0, CH_0, rank 0
859 01:18:49.160061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 01:18:49.160776 ==
861 01:18:49.162889 RX Vref Scan: 0
862 01:18:49.163206
863 01:18:49.163529 RX Vref 0 -> 0, step: 1
864 01:18:49.163839
865 01:18:49.166310 RX Delay -130 -> 252, step: 16
866 01:18:49.169507 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
867 01:18:49.173217 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 01:18:49.179609 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 01:18:49.183034 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
870 01:18:49.186558 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 01:18:49.190118 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
872 01:18:49.193100 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 01:18:49.200037 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 01:18:49.202975 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 01:18:49.206746 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
876 01:18:49.209937 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 01:18:49.212944 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 01:18:49.220379 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 01:18:49.223373 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 01:18:49.226325 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 01:18:49.229853 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 01:18:49.229986 ==
883 01:18:49.233012 Dram Type= 6, Freq= 0, CH_0, rank 0
884 01:18:49.239967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 01:18:49.240085 ==
886 01:18:49.240179 DQS Delay:
887 01:18:49.243036 DQS0 = 0, DQS1 = 0
888 01:18:49.243159 DQM Delay:
889 01:18:49.243256 DQM0 = 82, DQM1 = 69
890 01:18:49.246310 DQ Delay:
891 01:18:49.250073 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =85
892 01:18:49.253047 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
893 01:18:49.256821 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
894 01:18:49.259638 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 01:18:49.259721
896 01:18:49.259786
897 01:18:49.259855 ==
898 01:18:49.263227 Dram Type= 6, Freq= 0, CH_0, rank 0
899 01:18:49.267142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 01:18:49.267283 ==
901 01:18:49.267408
902 01:18:49.267541
903 01:18:49.270711 TX Vref Scan disable
904 01:18:49.270850 == TX Byte 0 ==
905 01:18:49.273762 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
906 01:18:49.280672 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
907 01:18:49.280803 == TX Byte 1 ==
908 01:18:49.283862 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
909 01:18:49.290407 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
910 01:18:49.290543 ==
911 01:18:49.293763 Dram Type= 6, Freq= 0, CH_0, rank 0
912 01:18:49.297499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 01:18:49.297695 ==
914 01:18:49.310563 TX Vref=22, minBit 14, minWin=26, winSum=436
915 01:18:49.313502 TX Vref=24, minBit 7, minWin=26, winSum=439
916 01:18:49.316918 TX Vref=26, minBit 1, minWin=27, winSum=438
917 01:18:49.320088 TX Vref=28, minBit 9, minWin=27, winSum=444
918 01:18:49.323624 TX Vref=30, minBit 9, minWin=27, winSum=441
919 01:18:49.330043 TX Vref=32, minBit 10, minWin=26, winSum=439
920 01:18:49.333601 [TxChooseVref] Worse bit 9, Min win 27, Win sum 444, Final Vref 28
921 01:18:49.334007
922 01:18:49.337227 Final TX Range 1 Vref 28
923 01:18:49.337712
924 01:18:49.338053 ==
925 01:18:49.340125 Dram Type= 6, Freq= 0, CH_0, rank 0
926 01:18:49.343567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 01:18:49.344011 ==
928 01:18:49.346856
929 01:18:49.347285
930 01:18:49.347640 TX Vref Scan disable
931 01:18:49.350655 == TX Byte 0 ==
932 01:18:49.353868 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
933 01:18:49.360545 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
934 01:18:49.360965 == TX Byte 1 ==
935 01:18:49.363910 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
936 01:18:49.370325 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
937 01:18:49.370788
938 01:18:49.371120 [DATLAT]
939 01:18:49.371428 Freq=800, CH0 RK0
940 01:18:49.371722
941 01:18:49.373557 DATLAT Default: 0xa
942 01:18:49.373978 0, 0xFFFF, sum = 0
943 01:18:49.377541 1, 0xFFFF, sum = 0
944 01:18:49.377971 2, 0xFFFF, sum = 0
945 01:18:49.380192 3, 0xFFFF, sum = 0
946 01:18:49.383572 4, 0xFFFF, sum = 0
947 01:18:49.384078 5, 0xFFFF, sum = 0
948 01:18:49.387260 6, 0xFFFF, sum = 0
949 01:18:49.387685 7, 0xFFFF, sum = 0
950 01:18:49.390203 8, 0xFFFF, sum = 0
951 01:18:49.390641 9, 0x0, sum = 1
952 01:18:49.390976 10, 0x0, sum = 2
953 01:18:49.393990 11, 0x0, sum = 3
954 01:18:49.394412 12, 0x0, sum = 4
955 01:18:49.396953 best_step = 10
956 01:18:49.397380
957 01:18:49.397834 ==
958 01:18:49.400442 Dram Type= 6, Freq= 0, CH_0, rank 0
959 01:18:49.404011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 01:18:49.404430 ==
961 01:18:49.407496 RX Vref Scan: 1
962 01:18:49.407912
963 01:18:49.408239 Set Vref Range= 32 -> 127
964 01:18:49.408545
965 01:18:49.410479 RX Vref 32 -> 127, step: 1
966 01:18:49.410891
967 01:18:49.413984 RX Delay -111 -> 252, step: 8
968 01:18:49.414397
969 01:18:49.417430 Set Vref, RX VrefLevel [Byte0]: 32
970 01:18:49.420409 [Byte1]: 32
971 01:18:49.420820
972 01:18:49.423658 Set Vref, RX VrefLevel [Byte0]: 33
973 01:18:49.427304 [Byte1]: 33
974 01:18:49.430854
975 01:18:49.431086 Set Vref, RX VrefLevel [Byte0]: 34
976 01:18:49.434300 [Byte1]: 34
977 01:18:49.438240
978 01:18:49.438426 Set Vref, RX VrefLevel [Byte0]: 35
979 01:18:49.441530 [Byte1]: 35
980 01:18:49.446323
981 01:18:49.446479 Set Vref, RX VrefLevel [Byte0]: 36
982 01:18:49.449030 [Byte1]: 36
983 01:18:49.453507
984 01:18:49.453661 Set Vref, RX VrefLevel [Byte0]: 37
985 01:18:49.456736 [Byte1]: 37
986 01:18:49.461179
987 01:18:49.461783 Set Vref, RX VrefLevel [Byte0]: 38
988 01:18:49.464601 [Byte1]: 38
989 01:18:49.469289
990 01:18:49.469809 Set Vref, RX VrefLevel [Byte0]: 39
991 01:18:49.472647 [Byte1]: 39
992 01:18:49.476853
993 01:18:49.477403 Set Vref, RX VrefLevel [Byte0]: 40
994 01:18:49.480091 [Byte1]: 40
995 01:18:49.484528
996 01:18:49.485047 Set Vref, RX VrefLevel [Byte0]: 41
997 01:18:49.487476 [Byte1]: 41
998 01:18:49.492223
999 01:18:49.492691 Set Vref, RX VrefLevel [Byte0]: 42
1000 01:18:49.495370 [Byte1]: 42
1001 01:18:49.499557
1002 01:18:49.500004 Set Vref, RX VrefLevel [Byte0]: 43
1003 01:18:49.506079 [Byte1]: 43
1004 01:18:49.506496
1005 01:18:49.509658 Set Vref, RX VrefLevel [Byte0]: 44
1006 01:18:49.512627 [Byte1]: 44
1007 01:18:49.513041
1008 01:18:49.516141 Set Vref, RX VrefLevel [Byte0]: 45
1009 01:18:49.519679 [Byte1]: 45
1010 01:18:49.520092
1011 01:18:49.523218 Set Vref, RX VrefLevel [Byte0]: 46
1012 01:18:49.527180 [Byte1]: 46
1013 01:18:49.530763
1014 01:18:49.531247 Set Vref, RX VrefLevel [Byte0]: 47
1015 01:18:49.533787 [Byte1]: 47
1016 01:18:49.538420
1017 01:18:49.538902 Set Vref, RX VrefLevel [Byte0]: 48
1018 01:18:49.541469 [Byte1]: 48
1019 01:18:49.546004
1020 01:18:49.546435 Set Vref, RX VrefLevel [Byte0]: 49
1021 01:18:49.549268 [Byte1]: 49
1022 01:18:49.553569
1023 01:18:49.554006 Set Vref, RX VrefLevel [Byte0]: 50
1024 01:18:49.556890 [Byte1]: 50
1025 01:18:49.561108
1026 01:18:49.561608 Set Vref, RX VrefLevel [Byte0]: 51
1027 01:18:49.564338 [Byte1]: 51
1028 01:18:49.568883
1029 01:18:49.569349 Set Vref, RX VrefLevel [Byte0]: 52
1030 01:18:49.571882 [Byte1]: 52
1031 01:18:49.576182
1032 01:18:49.576661 Set Vref, RX VrefLevel [Byte0]: 53
1033 01:18:49.579617 [Byte1]: 53
1034 01:18:49.583638
1035 01:18:49.584084 Set Vref, RX VrefLevel [Byte0]: 54
1036 01:18:49.586849 [Byte1]: 54
1037 01:18:49.591427
1038 01:18:49.591837 Set Vref, RX VrefLevel [Byte0]: 55
1039 01:18:49.594588 [Byte1]: 55
1040 01:18:49.599020
1041 01:18:49.599529 Set Vref, RX VrefLevel [Byte0]: 56
1042 01:18:49.602180 [Byte1]: 56
1043 01:18:49.606924
1044 01:18:49.607385 Set Vref, RX VrefLevel [Byte0]: 57
1045 01:18:49.609809 [Byte1]: 57
1046 01:18:49.614281
1047 01:18:49.614695 Set Vref, RX VrefLevel [Byte0]: 58
1048 01:18:49.617827 [Byte1]: 58
1049 01:18:49.622049
1050 01:18:49.622464 Set Vref, RX VrefLevel [Byte0]: 59
1051 01:18:49.625397 [Byte1]: 59
1052 01:18:49.629583
1053 01:18:49.630065 Set Vref, RX VrefLevel [Byte0]: 60
1054 01:18:49.632956 [Byte1]: 60
1055 01:18:49.637579
1056 01:18:49.637993 Set Vref, RX VrefLevel [Byte0]: 61
1057 01:18:49.640495 [Byte1]: 61
1058 01:18:49.645035
1059 01:18:49.645448 Set Vref, RX VrefLevel [Byte0]: 62
1060 01:18:49.648578 [Byte1]: 62
1061 01:18:49.652557
1062 01:18:49.653068 Set Vref, RX VrefLevel [Byte0]: 63
1063 01:18:49.656015 [Byte1]: 63
1064 01:18:49.660161
1065 01:18:49.660574 Set Vref, RX VrefLevel [Byte0]: 64
1066 01:18:49.663316 [Byte1]: 64
1067 01:18:49.667854
1068 01:18:49.668454 Set Vref, RX VrefLevel [Byte0]: 65
1069 01:18:49.671068 [Byte1]: 65
1070 01:18:49.675524
1071 01:18:49.676066 Set Vref, RX VrefLevel [Byte0]: 66
1072 01:18:49.678946 [Byte1]: 66
1073 01:18:49.683284
1074 01:18:49.683706 Set Vref, RX VrefLevel [Byte0]: 67
1075 01:18:49.686279 [Byte1]: 67
1076 01:18:49.690704
1077 01:18:49.691111 Set Vref, RX VrefLevel [Byte0]: 68
1078 01:18:49.693929 [Byte1]: 68
1079 01:18:49.698784
1080 01:18:49.699194 Set Vref, RX VrefLevel [Byte0]: 69
1081 01:18:49.701453 [Byte1]: 69
1082 01:18:49.706051
1083 01:18:49.706459 Set Vref, RX VrefLevel [Byte0]: 70
1084 01:18:49.709329 [Byte1]: 70
1085 01:18:49.713659
1086 01:18:49.714067 Set Vref, RX VrefLevel [Byte0]: 71
1087 01:18:49.716995 [Byte1]: 71
1088 01:18:49.721291
1089 01:18:49.721944 Set Vref, RX VrefLevel [Byte0]: 72
1090 01:18:49.724893 [Byte1]: 72
1091 01:18:49.729055
1092 01:18:49.729465 Set Vref, RX VrefLevel [Byte0]: 73
1093 01:18:49.732500 [Byte1]: 73
1094 01:18:49.736630
1095 01:18:49.737051 Set Vref, RX VrefLevel [Byte0]: 74
1096 01:18:49.739973 [Byte1]: 74
1097 01:18:49.744607
1098 01:18:49.745016 Set Vref, RX VrefLevel [Byte0]: 75
1099 01:18:49.747691 [Byte1]: 75
1100 01:18:49.752059
1101 01:18:49.752477 Set Vref, RX VrefLevel [Byte0]: 76
1102 01:18:49.755584 [Byte1]: 76
1103 01:18:49.759579
1104 01:18:49.760005 Set Vref, RX VrefLevel [Byte0]: 77
1105 01:18:49.763072 [Byte1]: 77
1106 01:18:49.767219
1107 01:18:49.770689 Set Vref, RX VrefLevel [Byte0]: 78
1108 01:18:49.771105 [Byte1]: 78
1109 01:18:49.774838
1110 01:18:49.775250 Set Vref, RX VrefLevel [Byte0]: 79
1111 01:18:49.778304 [Byte1]: 79
1112 01:18:49.782497
1113 01:18:49.783223 Set Vref, RX VrefLevel [Byte0]: 80
1114 01:18:49.785852 [Byte1]: 80
1115 01:18:49.790347
1116 01:18:49.790914 Final RX Vref Byte 0 = 57 to rank0
1117 01:18:49.793505 Final RX Vref Byte 1 = 59 to rank0
1118 01:18:49.796935 Final RX Vref Byte 0 = 57 to rank1
1119 01:18:49.800147 Final RX Vref Byte 1 = 59 to rank1==
1120 01:18:49.803374 Dram Type= 6, Freq= 0, CH_0, rank 0
1121 01:18:49.809986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1122 01:18:49.810401 ==
1123 01:18:49.810729 DQS Delay:
1124 01:18:49.811031 DQS0 = 0, DQS1 = 0
1125 01:18:49.813665 DQM Delay:
1126 01:18:49.814122 DQM0 = 82, DQM1 = 68
1127 01:18:49.816505 DQ Delay:
1128 01:18:49.820175 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1129 01:18:49.823499 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1130 01:18:49.823950 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =64
1131 01:18:49.829845 DQ12 =72, DQ13 =76, DQ14 =76, DQ15 =76
1132 01:18:49.830285
1133 01:18:49.830625
1134 01:18:49.836640 [DQSOSCAuto] RK0, (LSB)MR18= 0x2221, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1135 01:18:49.839958 CH0 RK0: MR19=606, MR18=2221
1136 01:18:49.846301 CH0_RK0: MR19=0x606, MR18=0x2221, DQSOSC=401, MR23=63, INC=91, DEC=61
1137 01:18:49.846736
1138 01:18:49.849815 ----->DramcWriteLeveling(PI) begin...
1139 01:18:49.850251 ==
1140 01:18:49.853395 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 01:18:49.856459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 01:18:49.856892 ==
1143 01:18:49.860010 Write leveling (Byte 0): 32 => 32
1144 01:18:49.862957 Write leveling (Byte 1): 30 => 30
1145 01:18:49.866610 DramcWriteLeveling(PI) end<-----
1146 01:18:49.867139
1147 01:18:49.867568 ==
1148 01:18:49.869557 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 01:18:49.873127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 01:18:49.873589 ==
1151 01:18:49.876626 [Gating] SW mode calibration
1152 01:18:49.883743 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1153 01:18:49.889927 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1154 01:18:49.893083 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 01:18:49.896464 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1156 01:18:49.903182 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1157 01:18:49.906164 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 01:18:49.909562 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 01:18:49.916069 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 01:18:49.919667 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 01:18:49.923024 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 01:18:49.929462 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 01:18:49.932613 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 01:18:49.936432 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 01:18:49.983607 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 01:18:49.984056 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 01:18:49.984498 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 01:18:49.984916 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 01:18:49.985323 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 01:18:49.986121 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 01:18:49.986493 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1172 01:18:49.986897 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1173 01:18:49.987290 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 01:18:49.987677 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 01:18:50.014957 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 01:18:50.015391 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 01:18:50.016183 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 01:18:50.016556 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 01:18:50.016973 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 01:18:50.017376 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
1181 01:18:50.017808 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1182 01:18:50.019566 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 01:18:50.023961 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 01:18:50.026128 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 01:18:50.029474 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 01:18:50.033029 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 01:18:50.039061 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
1188 01:18:50.042697 0 10 8 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 0)
1189 01:18:50.045967 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1190 01:18:50.052485 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 01:18:50.056052 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 01:18:50.059453 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 01:18:50.065998 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 01:18:50.069214 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 01:18:50.072889 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 01:18:50.079574 0 11 8 | B1->B0 | 2d2d 3d3d | 0 0 | (0 0) (0 0)
1197 01:18:50.082981 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 01:18:50.086499 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 01:18:50.092881 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 01:18:50.095867 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 01:18:50.099481 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 01:18:50.103552 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 01:18:50.107152 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1204 01:18:50.114259 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 01:18:50.117587 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 01:18:50.121289 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 01:18:50.128207 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 01:18:50.132176 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 01:18:50.135039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 01:18:50.138712 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 01:18:50.145028 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 01:18:50.148551 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 01:18:50.152061 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 01:18:50.158693 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 01:18:50.161901 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 01:18:50.165310 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 01:18:50.171973 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 01:18:50.175232 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 01:18:50.178237 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 01:18:50.182053 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1221 01:18:50.188858 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 01:18:50.191726 Total UI for P1: 0, mck2ui 16
1223 01:18:50.195398 best dqsien dly found for B0: ( 0, 14, 8)
1224 01:18:50.198558 Total UI for P1: 0, mck2ui 16
1225 01:18:50.202108 best dqsien dly found for B1: ( 0, 14, 8)
1226 01:18:50.205459 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1227 01:18:50.208407 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1228 01:18:50.209000
1229 01:18:50.212025 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1230 01:18:50.215413 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 01:18:50.218327 [Gating] SW calibration Done
1232 01:18:50.218760 ==
1233 01:18:50.221500 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 01:18:50.224789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 01:18:50.225345 ==
1236 01:18:50.228181 RX Vref Scan: 0
1237 01:18:50.228634
1238 01:18:50.228887 RX Vref 0 -> 0, step: 1
1239 01:18:50.231427
1240 01:18:50.231720 RX Delay -130 -> 252, step: 16
1241 01:18:50.237899 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1242 01:18:50.241348 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1243 01:18:50.244317 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1244 01:18:50.248109 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1245 01:18:50.251199 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1246 01:18:50.258409 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1247 01:18:50.261390 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1248 01:18:50.265404 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1249 01:18:50.268515 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1250 01:18:50.271772 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1251 01:18:50.275131 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1252 01:18:50.281953 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1253 01:18:50.285369 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1254 01:18:50.288037 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1255 01:18:50.291702 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1256 01:18:50.298022 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1257 01:18:50.298106 ==
1258 01:18:50.300977 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 01:18:50.304596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 01:18:50.304681 ==
1261 01:18:50.304765 DQS Delay:
1262 01:18:50.307879 DQS0 = 0, DQS1 = 0
1263 01:18:50.307962 DQM Delay:
1264 01:18:50.310906 DQM0 = 79, DQM1 = 69
1265 01:18:50.310989 DQ Delay:
1266 01:18:50.314665 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1267 01:18:50.317593 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =85
1268 01:18:50.321129 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1269 01:18:50.324652 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1270 01:18:50.324741
1271 01:18:50.324831
1272 01:18:50.324916 ==
1273 01:18:50.327899 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 01:18:50.331385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 01:18:50.331490 ==
1276 01:18:50.331597
1277 01:18:50.334252
1278 01:18:50.334355 TX Vref Scan disable
1279 01:18:50.338367 == TX Byte 0 ==
1280 01:18:50.340948 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1281 01:18:50.344668 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1282 01:18:50.348088 == TX Byte 1 ==
1283 01:18:50.351032 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1284 01:18:50.354379 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1285 01:18:50.354534 ==
1286 01:18:50.358090 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 01:18:50.364764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 01:18:50.365187 ==
1289 01:18:50.376299 TX Vref=22, minBit 9, minWin=26, winSum=437
1290 01:18:50.380080 TX Vref=24, minBit 1, minWin=27, winSum=440
1291 01:18:50.383435 TX Vref=26, minBit 1, minWin=27, winSum=441
1292 01:18:50.386238 TX Vref=28, minBit 1, minWin=27, winSum=443
1293 01:18:50.389726 TX Vref=30, minBit 1, minWin=27, winSum=443
1294 01:18:50.393377 TX Vref=32, minBit 8, minWin=27, winSum=442
1295 01:18:50.399814 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 28
1296 01:18:50.400231
1297 01:18:50.403180 Final TX Range 1 Vref 28
1298 01:18:50.403597
1299 01:18:50.403926 ==
1300 01:18:50.406336 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 01:18:50.410069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 01:18:50.410610 ==
1303 01:18:50.410950
1304 01:18:50.412851
1305 01:18:50.413336 TX Vref Scan disable
1306 01:18:50.416065 == TX Byte 0 ==
1307 01:18:50.419894 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1308 01:18:50.426306 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1309 01:18:50.426753 == TX Byte 1 ==
1310 01:18:50.429483 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1311 01:18:50.436263 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1312 01:18:50.436683
1313 01:18:50.437048 [DATLAT]
1314 01:18:50.437374 Freq=800, CH0 RK1
1315 01:18:50.437753
1316 01:18:50.439581 DATLAT Default: 0xa
1317 01:18:50.439996 0, 0xFFFF, sum = 0
1318 01:18:50.443104 1, 0xFFFF, sum = 0
1319 01:18:50.443524 2, 0xFFFF, sum = 0
1320 01:18:50.446381 3, 0xFFFF, sum = 0
1321 01:18:50.446799 4, 0xFFFF, sum = 0
1322 01:18:50.449978 5, 0xFFFF, sum = 0
1323 01:18:50.453127 6, 0xFFFF, sum = 0
1324 01:18:50.453588 7, 0xFFFF, sum = 0
1325 01:18:50.456534 8, 0xFFFF, sum = 0
1326 01:18:50.456955 9, 0x0, sum = 1
1327 01:18:50.457288 10, 0x0, sum = 2
1328 01:18:50.459964 11, 0x0, sum = 3
1329 01:18:50.460383 12, 0x0, sum = 4
1330 01:18:50.462919 best_step = 10
1331 01:18:50.463331
1332 01:18:50.463655 ==
1333 01:18:50.466348 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 01:18:50.469672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 01:18:50.470091 ==
1336 01:18:50.473153 RX Vref Scan: 0
1337 01:18:50.473612
1338 01:18:50.473947 RX Vref 0 -> 0, step: 1
1339 01:18:50.474253
1340 01:18:50.476141 RX Delay -111 -> 252, step: 8
1341 01:18:50.482951 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1342 01:18:50.486336 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1343 01:18:50.489693 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1344 01:18:50.493590 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1345 01:18:50.496652 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1346 01:18:50.503198 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1347 01:18:50.506517 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1348 01:18:50.509719 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1349 01:18:50.512854 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1350 01:18:50.516395 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1351 01:18:50.523146 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1352 01:18:50.526327 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1353 01:18:50.529410 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1354 01:18:50.532867 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1355 01:18:50.536334 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1356 01:18:50.542466 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1357 01:18:50.542559 ==
1358 01:18:50.546457 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 01:18:50.549254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 01:18:50.549337 ==
1361 01:18:50.549403 DQS Delay:
1362 01:18:50.552604 DQS0 = 0, DQS1 = 0
1363 01:18:50.552687 DQM Delay:
1364 01:18:50.556012 DQM0 = 79, DQM1 = 70
1365 01:18:50.556111 DQ Delay:
1366 01:18:50.559743 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1367 01:18:50.563344 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1368 01:18:50.566220 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1369 01:18:50.569666 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1370 01:18:50.569747
1371 01:18:50.569811
1372 01:18:50.575920 [DQSOSCAuto] RK1, (LSB)MR18= 0x4621, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1373 01:18:50.579317 CH0 RK1: MR19=606, MR18=4621
1374 01:18:50.586172 CH0_RK1: MR19=0x606, MR18=0x4621, DQSOSC=392, MR23=63, INC=96, DEC=64
1375 01:18:50.589478 [RxdqsGatingPostProcess] freq 800
1376 01:18:50.596500 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 01:18:50.599671 Pre-setting of DQS Precalculation
1378 01:18:50.603001 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 01:18:50.603084 ==
1380 01:18:50.606319 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 01:18:50.609553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 01:18:50.609650 ==
1383 01:18:50.616018 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 01:18:50.622745 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 01:18:50.631502 [CA 0] Center 36 (6~67) winsize 62
1386 01:18:50.634648 [CA 1] Center 36 (6~67) winsize 62
1387 01:18:50.637927 [CA 2] Center 34 (4~64) winsize 61
1388 01:18:50.640920 [CA 3] Center 34 (4~64) winsize 61
1389 01:18:50.644304 [CA 4] Center 34 (4~64) winsize 61
1390 01:18:50.647646 [CA 5] Center 34 (4~64) winsize 61
1391 01:18:50.647728
1392 01:18:50.651318 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1393 01:18:50.651400
1394 01:18:50.654378 [CATrainingPosCal] consider 1 rank data
1395 01:18:50.657686 u2DelayCellTimex100 = 270/100 ps
1396 01:18:50.661169 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 01:18:50.664514 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 01:18:50.670828 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1399 01:18:50.674491 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 01:18:50.677926 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1401 01:18:50.681300 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1402 01:18:50.681382
1403 01:18:50.684144 CA PerBit enable=1, Macro0, CA PI delay=34
1404 01:18:50.684225
1405 01:18:50.687589 [CBTSetCACLKResult] CA Dly = 34
1406 01:18:50.687670 CS Dly: 5 (0~36)
1407 01:18:50.690986 ==
1408 01:18:50.691071 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 01:18:50.698034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 01:18:50.698119 ==
1411 01:18:50.700786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 01:18:50.707373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 01:18:50.717239 [CA 0] Center 37 (7~67) winsize 61
1414 01:18:50.720512 [CA 1] Center 36 (6~67) winsize 62
1415 01:18:50.723748 [CA 2] Center 34 (4~65) winsize 62
1416 01:18:50.727254 [CA 3] Center 34 (4~64) winsize 61
1417 01:18:50.730697 [CA 4] Center 34 (4~65) winsize 62
1418 01:18:50.733828 [CA 5] Center 33 (3~64) winsize 62
1419 01:18:50.733911
1420 01:18:50.736919 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1421 01:18:50.737000
1422 01:18:50.740760 [CATrainingPosCal] consider 2 rank data
1423 01:18:50.744015 u2DelayCellTimex100 = 270/100 ps
1424 01:18:50.747142 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1425 01:18:50.751003 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 01:18:50.757001 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 01:18:50.760744 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 01:18:50.764419 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 01:18:50.768318 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1430 01:18:50.768403
1431 01:18:50.772211 CA PerBit enable=1, Macro0, CA PI delay=34
1432 01:18:50.772289
1433 01:18:50.772352 [CBTSetCACLKResult] CA Dly = 34
1434 01:18:50.775995 CS Dly: 5 (0~37)
1435 01:18:50.776076
1436 01:18:50.779417 ----->DramcWriteLeveling(PI) begin...
1437 01:18:50.779500 ==
1438 01:18:50.783415 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 01:18:50.786745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 01:18:50.786836 ==
1441 01:18:50.790721 Write leveling (Byte 0): 29 => 29
1442 01:18:50.794086 Write leveling (Byte 1): 30 => 30
1443 01:18:50.794167 DramcWriteLeveling(PI) end<-----
1444 01:18:50.794232
1445 01:18:50.797851 ==
1446 01:18:50.797931 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 01:18:50.804289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 01:18:50.804370 ==
1449 01:18:50.807632 [Gating] SW mode calibration
1450 01:18:50.814483 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 01:18:50.817823 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 01:18:50.824362 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 01:18:50.827795 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 01:18:50.831171 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1455 01:18:50.837705 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 01:18:50.841157 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 01:18:50.844466 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 01:18:50.851280 0 6 24 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1459 01:18:50.854494 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 01:18:50.857919 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 01:18:50.861200 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 01:18:50.868097 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 01:18:50.871430 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 01:18:50.874418 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 01:18:50.881228 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 01:18:50.884977 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 01:18:50.888390 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 01:18:50.894789 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 01:18:50.898066 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1470 01:18:50.901219 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1471 01:18:50.907949 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 01:18:50.911278 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 01:18:50.914585 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 01:18:50.921082 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 01:18:50.924610 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 01:18:50.928059 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 01:18:50.934140 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 01:18:50.937545 0 9 8 | B1->B0 | 2727 2928 | 0 1 | (0 0) (0 0)
1479 01:18:50.941111 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 01:18:50.947809 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 01:18:50.951188 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 01:18:50.954195 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 01:18:50.961013 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 01:18:50.964130 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 01:18:50.967330 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1486 01:18:50.970846 0 10 8 | B1->B0 | 2d2d 2e2e | 0 0 | (1 0) (1 0)
1487 01:18:50.977637 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 01:18:50.980759 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 01:18:50.983985 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 01:18:50.990791 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 01:18:50.994543 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 01:18:50.997979 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 01:18:51.004371 0 11 4 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
1494 01:18:51.008028 0 11 8 | B1->B0 | 3837 3737 | 1 0 | (0 0) (0 0)
1495 01:18:51.011359 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 01:18:51.017495 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 01:18:51.020922 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 01:18:51.024443 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 01:18:51.031551 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 01:18:51.034962 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 01:18:51.038108 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1502 01:18:51.044465 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1503 01:18:51.047759 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 01:18:51.051243 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 01:18:51.057842 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 01:18:51.061363 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 01:18:51.064727 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 01:18:51.068072 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 01:18:51.074806 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 01:18:51.078037 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 01:18:51.081254 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 01:18:51.087879 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 01:18:51.091318 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 01:18:51.094499 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 01:18:51.101162 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 01:18:51.104399 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 01:18:51.107530 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 01:18:51.114990 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1519 01:18:51.115488 Total UI for P1: 0, mck2ui 16
1520 01:18:51.121278 best dqsien dly found for B0: ( 0, 14, 6)
1521 01:18:51.124531 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 01:18:51.128093 Total UI for P1: 0, mck2ui 16
1523 01:18:51.131632 best dqsien dly found for B1: ( 0, 14, 8)
1524 01:18:51.134562 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1525 01:18:51.138005 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1526 01:18:51.138427
1527 01:18:51.140940 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1528 01:18:51.144648 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1529 01:18:51.148091 [Gating] SW calibration Done
1530 01:18:51.148511 ==
1531 01:18:51.151026 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 01:18:51.154594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 01:18:51.155129 ==
1534 01:18:51.157857 RX Vref Scan: 0
1535 01:18:51.158276
1536 01:18:51.161162 RX Vref 0 -> 0, step: 1
1537 01:18:51.161617
1538 01:18:51.161964 RX Delay -130 -> 252, step: 16
1539 01:18:51.167574 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1540 01:18:51.170862 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1541 01:18:51.174685 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1542 01:18:51.178068 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1543 01:18:51.181040 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1544 01:18:51.187760 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1545 01:18:51.191147 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1546 01:18:51.194211 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1547 01:18:51.197594 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1548 01:18:51.201156 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1549 01:18:51.207687 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1550 01:18:51.211004 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1551 01:18:51.214427 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1552 01:18:51.217991 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1553 01:18:51.224094 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1554 01:18:51.227591 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1555 01:18:51.228006 ==
1556 01:18:51.231277 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 01:18:51.234264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 01:18:51.234686 ==
1559 01:18:51.235026 DQS Delay:
1560 01:18:51.237608 DQS0 = 0, DQS1 = 0
1561 01:18:51.238098 DQM Delay:
1562 01:18:51.241081 DQM0 = 80, DQM1 = 72
1563 01:18:51.241657 DQ Delay:
1564 01:18:51.244070 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1565 01:18:51.247343 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1566 01:18:51.250776 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1567 01:18:51.254308 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1568 01:18:51.254723
1569 01:18:51.255091
1570 01:18:51.255452 ==
1571 01:18:51.257775 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 01:18:51.260575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 01:18:51.263975 ==
1574 01:18:51.264521
1575 01:18:51.264946
1576 01:18:51.265258 TX Vref Scan disable
1577 01:18:51.267451 == TX Byte 0 ==
1578 01:18:51.270999 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1579 01:18:51.274371 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1580 01:18:51.277774 == TX Byte 1 ==
1581 01:18:51.280935 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1582 01:18:51.284324 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1583 01:18:51.287867 ==
1584 01:18:51.288292 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 01:18:51.293737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 01:18:51.294149 ==
1587 01:18:51.306097 TX Vref=22, minBit 0, minWin=27, winSum=440
1588 01:18:51.309480 TX Vref=24, minBit 0, minWin=27, winSum=443
1589 01:18:51.313096 TX Vref=26, minBit 0, minWin=27, winSum=444
1590 01:18:51.316138 TX Vref=28, minBit 1, minWin=28, winSum=454
1591 01:18:51.319259 TX Vref=30, minBit 4, minWin=27, winSum=450
1592 01:18:51.322450 TX Vref=32, minBit 4, minWin=27, winSum=449
1593 01:18:51.329281 [TxChooseVref] Worse bit 1, Min win 28, Win sum 454, Final Vref 28
1594 01:18:51.330024
1595 01:18:51.332834 Final TX Range 1 Vref 28
1596 01:18:51.333367
1597 01:18:51.333841 ==
1598 01:18:51.336197 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 01:18:51.339887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 01:18:51.340307 ==
1601 01:18:51.340640
1602 01:18:51.341039
1603 01:18:51.343366 TX Vref Scan disable
1604 01:18:51.346570 == TX Byte 0 ==
1605 01:18:51.350498 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1606 01:18:51.353329 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1607 01:18:51.356381 == TX Byte 1 ==
1608 01:18:51.359871 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1609 01:18:51.363599 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1610 01:18:51.364010
1611 01:18:51.366696 [DATLAT]
1612 01:18:51.367110 Freq=800, CH1 RK0
1613 01:18:51.367440
1614 01:18:51.369880 DATLAT Default: 0xa
1615 01:18:51.370363 0, 0xFFFF, sum = 0
1616 01:18:51.373322 1, 0xFFFF, sum = 0
1617 01:18:51.373786 2, 0xFFFF, sum = 0
1618 01:18:51.376897 3, 0xFFFF, sum = 0
1619 01:18:51.377314 4, 0xFFFF, sum = 0
1620 01:18:51.379809 5, 0xFFFF, sum = 0
1621 01:18:51.380227 6, 0xFFFF, sum = 0
1622 01:18:51.383126 7, 0xFFFF, sum = 0
1623 01:18:51.383545 8, 0xFFFF, sum = 0
1624 01:18:51.386352 9, 0x0, sum = 1
1625 01:18:51.386783 10, 0x0, sum = 2
1626 01:18:51.389894 11, 0x0, sum = 3
1627 01:18:51.390319 12, 0x0, sum = 4
1628 01:18:51.393376 best_step = 10
1629 01:18:51.393823
1630 01:18:51.394151 ==
1631 01:18:51.396823 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 01:18:51.399758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 01:18:51.400179 ==
1634 01:18:51.400509 RX Vref Scan: 1
1635 01:18:51.402898
1636 01:18:51.402978 Set Vref Range= 32 -> 127
1637 01:18:51.403042
1638 01:18:51.406493 RX Vref 32 -> 127, step: 1
1639 01:18:51.406654
1640 01:18:51.409764 RX Delay -111 -> 252, step: 8
1641 01:18:51.409914
1642 01:18:51.413081 Set Vref, RX VrefLevel [Byte0]: 32
1643 01:18:51.416478 [Byte1]: 32
1644 01:18:51.416653
1645 01:18:51.419787 Set Vref, RX VrefLevel [Byte0]: 33
1646 01:18:51.423523 [Byte1]: 33
1647 01:18:51.426129
1648 01:18:51.426210 Set Vref, RX VrefLevel [Byte0]: 34
1649 01:18:51.429655 [Byte1]: 34
1650 01:18:51.433647
1651 01:18:51.433741 Set Vref, RX VrefLevel [Byte0]: 35
1652 01:18:51.436934 [Byte1]: 35
1653 01:18:51.441759
1654 01:18:51.441840 Set Vref, RX VrefLevel [Byte0]: 36
1655 01:18:51.444825 [Byte1]: 36
1656 01:18:51.449146
1657 01:18:51.449226 Set Vref, RX VrefLevel [Byte0]: 37
1658 01:18:51.452192 [Byte1]: 37
1659 01:18:51.456661
1660 01:18:51.456742 Set Vref, RX VrefLevel [Byte0]: 38
1661 01:18:51.460039 [Byte1]: 38
1662 01:18:51.464523
1663 01:18:51.464612 Set Vref, RX VrefLevel [Byte0]: 39
1664 01:18:51.467557 [Byte1]: 39
1665 01:18:51.471952
1666 01:18:51.472044 Set Vref, RX VrefLevel [Byte0]: 40
1667 01:18:51.475892 [Byte1]: 40
1668 01:18:51.479691
1669 01:18:51.479865 Set Vref, RX VrefLevel [Byte0]: 41
1670 01:18:51.483083 [Byte1]: 41
1671 01:18:51.487535
1672 01:18:51.487655 Set Vref, RX VrefLevel [Byte0]: 42
1673 01:18:51.490730 [Byte1]: 42
1674 01:18:51.495529
1675 01:18:51.495662 Set Vref, RX VrefLevel [Byte0]: 43
1676 01:18:51.498312 [Byte1]: 43
1677 01:18:51.503001
1678 01:18:51.503082 Set Vref, RX VrefLevel [Byte0]: 44
1679 01:18:51.505783 [Byte1]: 44
1680 01:18:51.510412
1681 01:18:51.510492 Set Vref, RX VrefLevel [Byte0]: 45
1682 01:18:51.513615 [Byte1]: 45
1683 01:18:51.517728
1684 01:18:51.517814 Set Vref, RX VrefLevel [Byte0]: 46
1685 01:18:51.521367 [Byte1]: 46
1686 01:18:51.526105
1687 01:18:51.526185 Set Vref, RX VrefLevel [Byte0]: 47
1688 01:18:51.529298 [Byte1]: 47
1689 01:18:51.533293
1690 01:18:51.533380 Set Vref, RX VrefLevel [Byte0]: 48
1691 01:18:51.537102 [Byte1]: 48
1692 01:18:51.541027
1693 01:18:51.541119 Set Vref, RX VrefLevel [Byte0]: 49
1694 01:18:51.544493 [Byte1]: 49
1695 01:18:51.548876
1696 01:18:51.549014 Set Vref, RX VrefLevel [Byte0]: 50
1697 01:18:51.551684 [Byte1]: 50
1698 01:18:51.556052
1699 01:18:51.556138 Set Vref, RX VrefLevel [Byte0]: 51
1700 01:18:51.559515 [Byte1]: 51
1701 01:18:51.563824
1702 01:18:51.563924 Set Vref, RX VrefLevel [Byte0]: 52
1703 01:18:51.566918 [Byte1]: 52
1704 01:18:51.571759
1705 01:18:51.571880 Set Vref, RX VrefLevel [Byte0]: 53
1706 01:18:51.574761 [Byte1]: 53
1707 01:18:51.579454
1708 01:18:51.579592 Set Vref, RX VrefLevel [Byte0]: 54
1709 01:18:51.582721 [Byte1]: 54
1710 01:18:51.586716
1711 01:18:51.586898 Set Vref, RX VrefLevel [Byte0]: 55
1712 01:18:51.590421 [Byte1]: 55
1713 01:18:51.594663
1714 01:18:51.594860 Set Vref, RX VrefLevel [Byte0]: 56
1715 01:18:51.597712 [Byte1]: 56
1716 01:18:51.602401
1717 01:18:51.602726 Set Vref, RX VrefLevel [Byte0]: 57
1718 01:18:51.605891 [Byte1]: 57
1719 01:18:51.610101
1720 01:18:51.610478 Set Vref, RX VrefLevel [Byte0]: 58
1721 01:18:51.613559 [Byte1]: 58
1722 01:18:51.618036
1723 01:18:51.618499 Set Vref, RX VrefLevel [Byte0]: 59
1724 01:18:51.620868 [Byte1]: 59
1725 01:18:51.625396
1726 01:18:51.625884 Set Vref, RX VrefLevel [Byte0]: 60
1727 01:18:51.628806 [Byte1]: 60
1728 01:18:51.633010
1729 01:18:51.633435 Set Vref, RX VrefLevel [Byte0]: 61
1730 01:18:51.636449 [Byte1]: 61
1731 01:18:51.640501
1732 01:18:51.640917 Set Vref, RX VrefLevel [Byte0]: 62
1733 01:18:51.644360 [Byte1]: 62
1734 01:18:51.648313
1735 01:18:51.648798 Set Vref, RX VrefLevel [Byte0]: 63
1736 01:18:51.651643 [Byte1]: 63
1737 01:18:51.655782
1738 01:18:51.656242 Set Vref, RX VrefLevel [Byte0]: 64
1739 01:18:51.659208 [Byte1]: 64
1740 01:18:51.663637
1741 01:18:51.664136 Set Vref, RX VrefLevel [Byte0]: 65
1742 01:18:51.666859 [Byte1]: 65
1743 01:18:51.671401
1744 01:18:51.671814 Set Vref, RX VrefLevel [Byte0]: 66
1745 01:18:51.674397 [Byte1]: 66
1746 01:18:51.679201
1747 01:18:51.679627 Set Vref, RX VrefLevel [Byte0]: 67
1748 01:18:51.682163 [Byte1]: 67
1749 01:18:51.686566
1750 01:18:51.686975 Set Vref, RX VrefLevel [Byte0]: 68
1751 01:18:51.689880 [Byte1]: 68
1752 01:18:51.694482
1753 01:18:51.694892 Set Vref, RX VrefLevel [Byte0]: 69
1754 01:18:51.697486 [Byte1]: 69
1755 01:18:51.701622
1756 01:18:51.702036 Set Vref, RX VrefLevel [Byte0]: 70
1757 01:18:51.704952 [Byte1]: 70
1758 01:18:51.709429
1759 01:18:51.709887 Set Vref, RX VrefLevel [Byte0]: 71
1760 01:18:51.712895 [Byte1]: 71
1761 01:18:51.717341
1762 01:18:51.717814 Set Vref, RX VrefLevel [Byte0]: 72
1763 01:18:51.720583 [Byte1]: 72
1764 01:18:51.725275
1765 01:18:51.725831 Set Vref, RX VrefLevel [Byte0]: 73
1766 01:18:51.727941 [Byte1]: 73
1767 01:18:51.732468
1768 01:18:51.732924 Set Vref, RX VrefLevel [Byte0]: 74
1769 01:18:51.735895 [Byte1]: 74
1770 01:18:51.739931
1771 01:18:51.740398 Set Vref, RX VrefLevel [Byte0]: 75
1772 01:18:51.743293 [Byte1]: 75
1773 01:18:51.747545
1774 01:18:51.748073 Set Vref, RX VrefLevel [Byte0]: 76
1775 01:18:51.751369 [Byte1]: 76
1776 01:18:51.755746
1777 01:18:51.756159 Final RX Vref Byte 0 = 61 to rank0
1778 01:18:51.758544 Final RX Vref Byte 1 = 58 to rank0
1779 01:18:51.762004 Final RX Vref Byte 0 = 61 to rank1
1780 01:18:51.765313 Final RX Vref Byte 1 = 58 to rank1==
1781 01:18:51.768654 Dram Type= 6, Freq= 0, CH_1, rank 0
1782 01:18:51.775298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 01:18:51.775717 ==
1784 01:18:51.776045 DQS Delay:
1785 01:18:51.776353 DQS0 = 0, DQS1 = 0
1786 01:18:51.778580 DQM Delay:
1787 01:18:51.778989 DQM0 = 81, DQM1 = 70
1788 01:18:51.782012 DQ Delay:
1789 01:18:51.785549 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1790 01:18:51.785967 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1791 01:18:51.788594 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1792 01:18:51.795463 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1793 01:18:51.795915
1794 01:18:51.796251
1795 01:18:51.802071 [DQSOSCAuto] RK0, (LSB)MR18= 0xb15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 407 ps
1796 01:18:51.805154 CH1 RK0: MR19=606, MR18=B15
1797 01:18:51.812038 CH1_RK0: MR19=0x606, MR18=0xB15, DQSOSC=404, MR23=63, INC=90, DEC=60
1798 01:18:51.812538
1799 01:18:51.815480 ----->DramcWriteLeveling(PI) begin...
1800 01:18:51.815985 ==
1801 01:18:51.818486 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 01:18:51.821977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 01:18:51.822396 ==
1804 01:18:51.825134 Write leveling (Byte 0): 28 => 28
1805 01:18:51.828333 Write leveling (Byte 1): 29 => 29
1806 01:18:51.832015 DramcWriteLeveling(PI) end<-----
1807 01:18:51.832433
1808 01:18:51.832897 ==
1809 01:18:51.835185 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 01:18:51.838613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 01:18:51.839068 ==
1812 01:18:51.842059 [Gating] SW mode calibration
1813 01:18:51.848404 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1814 01:18:51.855459 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1815 01:18:51.858401 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1816 01:18:51.861965 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 01:18:51.868175 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 01:18:51.871784 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 01:18:51.874983 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 01:18:51.881567 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 01:18:51.885475 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 01:18:51.888469 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 01:18:51.894676 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 01:18:51.898462 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 01:18:51.901876 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 01:18:51.908605 0 7 12 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1827 01:18:51.911490 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 01:18:51.914755 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 01:18:51.918386 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 01:18:51.925078 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 01:18:51.928388 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 01:18:51.931573 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1833 01:18:51.938386 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 01:18:51.941641 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 01:18:51.944955 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 01:18:51.951542 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 01:18:51.954830 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 01:18:51.958405 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 01:18:51.964967 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 01:18:51.967974 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1841 01:18:51.971534 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1842 01:18:51.978214 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 01:18:51.981659 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 01:18:51.985067 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 01:18:51.991467 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 01:18:51.994991 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 01:18:51.998354 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1848 01:18:52.004644 0 10 4 | B1->B0 | 3030 2a2a | 0 0 | (0 1) (1 0)
1849 01:18:52.008419 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
1850 01:18:52.011393 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 01:18:52.017730 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 01:18:52.021471 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 01:18:52.025124 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 01:18:52.031550 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 01:18:52.034645 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1856 01:18:52.037868 0 11 4 | B1->B0 | 2727 3838 | 0 0 | (0 0) (0 0)
1857 01:18:52.041386 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1858 01:18:52.048003 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 01:18:52.051315 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 01:18:52.055191 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 01:18:52.061449 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 01:18:52.064909 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 01:18:52.068309 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 01:18:52.075045 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 01:18:52.078511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 01:18:52.081396 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 01:18:52.088135 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 01:18:52.091732 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 01:18:52.095291 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 01:18:52.101703 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 01:18:52.104552 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 01:18:52.108048 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 01:18:52.114526 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 01:18:52.117928 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 01:18:52.121416 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 01:18:52.124900 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 01:18:52.131711 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 01:18:52.134752 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 01:18:52.138019 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1880 01:18:52.144822 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1881 01:18:52.148017 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1882 01:18:52.151528 Total UI for P1: 0, mck2ui 16
1883 01:18:52.155144 best dqsien dly found for B0: ( 0, 14, 2)
1884 01:18:52.158072 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 01:18:52.161662 Total UI for P1: 0, mck2ui 16
1886 01:18:52.164670 best dqsien dly found for B1: ( 0, 14, 8)
1887 01:18:52.168513 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1888 01:18:52.171789 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1889 01:18:52.172224
1890 01:18:52.178212 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1891 01:18:52.181559 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1892 01:18:52.182044 [Gating] SW calibration Done
1893 01:18:52.184756 ==
1894 01:18:52.188284 Dram Type= 6, Freq= 0, CH_1, rank 1
1895 01:18:52.191705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1896 01:18:52.192184 ==
1897 01:18:52.192665 RX Vref Scan: 0
1898 01:18:52.193121
1899 01:18:52.194853 RX Vref 0 -> 0, step: 1
1900 01:18:52.195327
1901 01:18:52.198403 RX Delay -130 -> 252, step: 16
1902 01:18:52.201305 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1903 01:18:52.204620 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1904 01:18:52.208025 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1905 01:18:52.214664 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1906 01:18:52.218072 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1907 01:18:52.221721 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1908 01:18:52.224943 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1909 01:18:52.228283 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1910 01:18:52.235371 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1911 01:18:52.238070 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1912 01:18:52.241459 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1913 01:18:52.245057 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1914 01:18:52.248447 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1915 01:18:52.254831 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1916 01:18:52.257967 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1917 01:18:52.261476 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1918 01:18:52.261977 ==
1919 01:18:52.264785 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 01:18:52.267885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 01:18:52.271244 ==
1922 01:18:52.271753 DQS Delay:
1923 01:18:52.272190 DQS0 = 0, DQS1 = 0
1924 01:18:52.274620 DQM Delay:
1925 01:18:52.275051 DQM0 = 78, DQM1 = 76
1926 01:18:52.278461 DQ Delay:
1927 01:18:52.278891 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1928 01:18:52.281318 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1929 01:18:52.284662 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =61
1930 01:18:52.288219 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1931 01:18:52.288649
1932 01:18:52.289084
1933 01:18:52.291382 ==
1934 01:18:52.294617 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 01:18:52.298229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 01:18:52.298668 ==
1937 01:18:52.299104
1938 01:18:52.299517
1939 01:18:52.301361 TX Vref Scan disable
1940 01:18:52.301827 == TX Byte 0 ==
1941 01:18:52.304648 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1942 01:18:52.311515 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1943 01:18:52.311948 == TX Byte 1 ==
1944 01:18:52.314980 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1945 01:18:52.321306 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1946 01:18:52.321799 ==
1947 01:18:52.324785 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 01:18:52.328068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 01:18:52.328502 ==
1950 01:18:52.341591 TX Vref=22, minBit 1, minWin=27, winSum=448
1951 01:18:52.344405 TX Vref=24, minBit 7, minWin=27, winSum=450
1952 01:18:52.347888 TX Vref=26, minBit 0, minWin=28, winSum=455
1953 01:18:52.351342 TX Vref=28, minBit 1, minWin=27, winSum=459
1954 01:18:52.354784 TX Vref=30, minBit 5, minWin=27, winSum=459
1955 01:18:52.357792 TX Vref=32, minBit 1, minWin=27, winSum=457
1956 01:18:52.364634 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 26
1957 01:18:52.365067
1958 01:18:52.368102 Final TX Range 1 Vref 26
1959 01:18:52.368532
1960 01:18:52.368966 ==
1961 01:18:52.371491 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 01:18:52.374696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 01:18:52.375129 ==
1964 01:18:52.375566
1965 01:18:52.377548
1966 01:18:52.377979 TX Vref Scan disable
1967 01:18:52.381200 == TX Byte 0 ==
1968 01:18:52.384704 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1969 01:18:52.387998 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1970 01:18:52.391194 == TX Byte 1 ==
1971 01:18:52.394146 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1972 01:18:52.397683 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1973 01:18:52.401389
1974 01:18:52.401902 [DATLAT]
1975 01:18:52.402280 Freq=800, CH1 RK1
1976 01:18:52.402684
1977 01:18:52.404485 DATLAT Default: 0xa
1978 01:18:52.405026 0, 0xFFFF, sum = 0
1979 01:18:52.407770 1, 0xFFFF, sum = 0
1980 01:18:52.408287 2, 0xFFFF, sum = 0
1981 01:18:52.411242 3, 0xFFFF, sum = 0
1982 01:18:52.411669 4, 0xFFFF, sum = 0
1983 01:18:52.414666 5, 0xFFFF, sum = 0
1984 01:18:52.415089 6, 0xFFFF, sum = 0
1985 01:18:52.417619 7, 0xFFFF, sum = 0
1986 01:18:52.421213 8, 0xFFFF, sum = 0
1987 01:18:52.421710 9, 0x0, sum = 1
1988 01:18:52.422144 10, 0x0, sum = 2
1989 01:18:52.424499 11, 0x0, sum = 3
1990 01:18:52.424928 12, 0x0, sum = 4
1991 01:18:52.427971 best_step = 10
1992 01:18:52.428391
1993 01:18:52.428829 ==
1994 01:18:52.431403 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 01:18:52.434332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 01:18:52.434943 ==
1997 01:18:52.437696 RX Vref Scan: 0
1998 01:18:52.438130
1999 01:18:52.438478 RX Vref 0 -> 0, step: 1
2000 01:18:52.438796
2001 01:18:52.440960 RX Delay -111 -> 252, step: 8
2002 01:18:52.447869 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2003 01:18:52.451358 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2004 01:18:52.454897 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2005 01:18:52.457713 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2006 01:18:52.461151 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2007 01:18:52.467876 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2008 01:18:52.471446 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2009 01:18:52.474823 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2010 01:18:52.478062 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2011 01:18:52.481591 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2012 01:18:52.488011 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2013 01:18:52.491394 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2014 01:18:52.494496 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2015 01:18:52.497646 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2016 01:18:52.501242 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2017 01:18:52.507776 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2018 01:18:52.508391 ==
2019 01:18:52.510991 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 01:18:52.514364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 01:18:52.514796 ==
2022 01:18:52.515234 DQS Delay:
2023 01:18:52.517729 DQS0 = 0, DQS1 = 0
2024 01:18:52.518159 DQM Delay:
2025 01:18:52.521114 DQM0 = 77, DQM1 = 73
2026 01:18:52.521574 DQ Delay:
2027 01:18:52.524325 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2028 01:18:52.527875 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2029 01:18:52.531686 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2030 01:18:52.534395 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2031 01:18:52.534828
2032 01:18:52.535259
2033 01:18:52.541239 [DQSOSCAuto] RK1, (LSB)MR18= 0x223a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2034 01:18:52.544281 CH1 RK1: MR19=606, MR18=223A
2035 01:18:52.551202 CH1_RK1: MR19=0x606, MR18=0x223A, DQSOSC=395, MR23=63, INC=94, DEC=63
2036 01:18:52.554267 [RxdqsGatingPostProcess] freq 800
2037 01:18:52.561219 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2038 01:18:52.564842 Pre-setting of DQS Precalculation
2039 01:18:52.568233 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2040 01:18:52.574664 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2041 01:18:52.581434 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2042 01:18:52.582074
2043 01:18:52.582561
2044 01:18:52.584806 [Calibration Summary] 1600 Mbps
2045 01:18:52.587515 CH 0, Rank 0
2046 01:18:52.587984 SW Impedance : PASS
2047 01:18:52.591030 DUTY Scan : NO K
2048 01:18:52.594416 ZQ Calibration : PASS
2049 01:18:52.594833 Jitter Meter : NO K
2050 01:18:52.597762 CBT Training : PASS
2051 01:18:52.600972 Write leveling : PASS
2052 01:18:52.601474 RX DQS gating : PASS
2053 01:18:52.604257 RX DQ/DQS(RDDQC) : PASS
2054 01:18:52.607648 TX DQ/DQS : PASS
2055 01:18:52.608246 RX DATLAT : PASS
2056 01:18:52.610968 RX DQ/DQS(Engine): PASS
2057 01:18:52.614161 TX OE : NO K
2058 01:18:52.614628 All Pass.
2059 01:18:52.614955
2060 01:18:52.615258 CH 0, Rank 1
2061 01:18:52.617326 SW Impedance : PASS
2062 01:18:52.620622 DUTY Scan : NO K
2063 01:18:52.621077 ZQ Calibration : PASS
2064 01:18:52.624054 Jitter Meter : NO K
2065 01:18:52.624518 CBT Training : PASS
2066 01:18:52.627288 Write leveling : PASS
2067 01:18:52.630848 RX DQS gating : PASS
2068 01:18:52.631261 RX DQ/DQS(RDDQC) : PASS
2069 01:18:52.634122 TX DQ/DQS : PASS
2070 01:18:52.637560 RX DATLAT : PASS
2071 01:18:52.638029 RX DQ/DQS(Engine): PASS
2072 01:18:52.641104 TX OE : NO K
2073 01:18:52.641572 All Pass.
2074 01:18:52.641957
2075 01:18:52.644027 CH 1, Rank 0
2076 01:18:52.644489 SW Impedance : PASS
2077 01:18:52.647298 DUTY Scan : NO K
2078 01:18:52.650491 ZQ Calibration : PASS
2079 01:18:52.650907 Jitter Meter : NO K
2080 01:18:52.653930 CBT Training : PASS
2081 01:18:52.657281 Write leveling : PASS
2082 01:18:52.657838 RX DQS gating : PASS
2083 01:18:52.660415 RX DQ/DQS(RDDQC) : PASS
2084 01:18:52.663652 TX DQ/DQS : PASS
2085 01:18:52.664086 RX DATLAT : PASS
2086 01:18:52.667047 RX DQ/DQS(Engine): PASS
2087 01:18:52.670333 TX OE : NO K
2088 01:18:52.670765 All Pass.
2089 01:18:52.671199
2090 01:18:52.671692 CH 1, Rank 1
2091 01:18:52.673760 SW Impedance : PASS
2092 01:18:52.677093 DUTY Scan : NO K
2093 01:18:52.677505 ZQ Calibration : PASS
2094 01:18:52.680677 Jitter Meter : NO K
2095 01:18:52.681139 CBT Training : PASS
2096 01:18:52.683970 Write leveling : PASS
2097 01:18:52.687393 RX DQS gating : PASS
2098 01:18:52.687806 RX DQ/DQS(RDDQC) : PASS
2099 01:18:52.690724 TX DQ/DQS : PASS
2100 01:18:52.693660 RX DATLAT : PASS
2101 01:18:52.694073 RX DQ/DQS(Engine): PASS
2102 01:18:52.697132 TX OE : NO K
2103 01:18:52.697622 All Pass.
2104 01:18:52.697952
2105 01:18:52.700638 DramC Write-DBI off
2106 01:18:52.703989 PER_BANK_REFRESH: Hybrid Mode
2107 01:18:52.704451 TX_TRACKING: ON
2108 01:18:52.707364 [GetDramInforAfterCalByMRR] Vendor 6.
2109 01:18:52.710717 [GetDramInforAfterCalByMRR] Revision 606.
2110 01:18:52.713709 [GetDramInforAfterCalByMRR] Revision 2 0.
2111 01:18:52.716937 MR0 0x3b3b
2112 01:18:52.717390 MR8 0x5151
2113 01:18:52.720451 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 01:18:52.720863
2115 01:18:52.721233 MR0 0x3b3b
2116 01:18:52.723736 MR8 0x5151
2117 01:18:52.727009 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 01:18:52.727513
2119 01:18:52.737033 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2120 01:18:52.740482 [FAST_K] Save calibration result to emmc
2121 01:18:52.743496 [FAST_K] Save calibration result to emmc
2122 01:18:52.744047 dram_init: config_dvfs: 1
2123 01:18:52.750491 dramc_set_vcore_voltage set vcore to 662500
2124 01:18:52.751042 Read voltage for 1200, 2
2125 01:18:52.753863 Vio18 = 0
2126 01:18:52.754401 Vcore = 662500
2127 01:18:52.754876 Vdram = 0
2128 01:18:52.756754 Vddq = 0
2129 01:18:52.757141 Vmddr = 0
2130 01:18:52.759913 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2131 01:18:52.766935 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2132 01:18:52.770385 MEM_TYPE=3, freq_sel=15
2133 01:18:52.773291 sv_algorithm_assistance_LP4_1600
2134 01:18:52.776569 ============ PULL DRAM RESETB DOWN ============
2135 01:18:52.780074 ========== PULL DRAM RESETB DOWN end =========
2136 01:18:52.783455 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2137 01:18:52.786772 ===================================
2138 01:18:52.790274 LPDDR4 DRAM CONFIGURATION
2139 01:18:52.793180 ===================================
2140 01:18:52.796910 EX_ROW_EN[0] = 0x0
2141 01:18:52.797041 EX_ROW_EN[1] = 0x0
2142 01:18:52.800269 LP4Y_EN = 0x0
2143 01:18:52.800399 WORK_FSP = 0x0
2144 01:18:52.803148 WL = 0x4
2145 01:18:52.803272 RL = 0x4
2146 01:18:52.806598 BL = 0x2
2147 01:18:52.806711 RPST = 0x0
2148 01:18:52.810106 RD_PRE = 0x0
2149 01:18:52.810293 WR_PRE = 0x1
2150 01:18:52.813224 WR_PST = 0x0
2151 01:18:52.813389 DBI_WR = 0x0
2152 01:18:52.816843 DBI_RD = 0x0
2153 01:18:52.819859 OTF = 0x1
2154 01:18:52.823320 ===================================
2155 01:18:52.826568 ===================================
2156 01:18:52.826726 ANA top config
2157 01:18:52.829950 ===================================
2158 01:18:52.833505 DLL_ASYNC_EN = 0
2159 01:18:52.833723 ALL_SLAVE_EN = 0
2160 01:18:52.836880 NEW_RANK_MODE = 1
2161 01:18:52.840058 DLL_IDLE_MODE = 1
2162 01:18:52.843090 LP45_APHY_COMB_EN = 1
2163 01:18:52.846713 TX_ODT_DIS = 1
2164 01:18:52.846931 NEW_8X_MODE = 1
2165 01:18:52.850112 ===================================
2166 01:18:52.853270 ===================================
2167 01:18:52.856769 data_rate = 2400
2168 01:18:52.859771 CKR = 1
2169 01:18:52.863648 DQ_P2S_RATIO = 8
2170 01:18:52.866425 ===================================
2171 01:18:52.870018 CA_P2S_RATIO = 8
2172 01:18:52.870435 DQ_CA_OPEN = 0
2173 01:18:52.873449 DQ_SEMI_OPEN = 0
2174 01:18:52.877203 CA_SEMI_OPEN = 0
2175 01:18:52.880547 CA_FULL_RATE = 0
2176 01:18:52.883567 DQ_CKDIV4_EN = 0
2177 01:18:52.887237 CA_CKDIV4_EN = 0
2178 01:18:52.887695 CA_PREDIV_EN = 0
2179 01:18:52.890401 PH8_DLY = 17
2180 01:18:52.893633 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2181 01:18:52.896994 DQ_AAMCK_DIV = 4
2182 01:18:52.900514 CA_AAMCK_DIV = 4
2183 01:18:52.903811 CA_ADMCK_DIV = 4
2184 01:18:52.904359 DQ_TRACK_CA_EN = 0
2185 01:18:52.906969 CA_PICK = 1200
2186 01:18:52.910262 CA_MCKIO = 1200
2187 01:18:52.913199 MCKIO_SEMI = 0
2188 01:18:52.917129 PLL_FREQ = 2366
2189 01:18:52.920552 DQ_UI_PI_RATIO = 32
2190 01:18:52.923574 CA_UI_PI_RATIO = 0
2191 01:18:52.926952 ===================================
2192 01:18:52.930614 ===================================
2193 01:18:52.931220 memory_type:LPDDR4
2194 01:18:52.933656 GP_NUM : 10
2195 01:18:52.937197 SRAM_EN : 1
2196 01:18:52.937688 MD32_EN : 0
2197 01:18:52.940384 ===================================
2198 01:18:52.943619 [ANA_INIT] >>>>>>>>>>>>>>
2199 01:18:52.946709 <<<<<< [CONFIGURE PHASE]: ANA_TX
2200 01:18:52.949935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2201 01:18:52.953625 ===================================
2202 01:18:52.956626 data_rate = 2400,PCW = 0X5b00
2203 01:18:52.960180 ===================================
2204 01:18:52.963636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2205 01:18:52.966752 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 01:18:52.973603 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 01:18:52.977157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2208 01:18:52.980202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2209 01:18:52.984076 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2210 01:18:52.987033 [ANA_INIT] flow start
2211 01:18:52.990380 [ANA_INIT] PLL >>>>>>>>
2212 01:18:52.990926 [ANA_INIT] PLL <<<<<<<<
2213 01:18:52.993865 [ANA_INIT] MIDPI >>>>>>>>
2214 01:18:52.997036 [ANA_INIT] MIDPI <<<<<<<<
2215 01:18:52.997492 [ANA_INIT] DLL >>>>>>>>
2216 01:18:53.000733 [ANA_INIT] DLL <<<<<<<<
2217 01:18:53.003988 [ANA_INIT] flow end
2218 01:18:53.007152 ============ LP4 DIFF to SE enter ============
2219 01:18:53.010490 ============ LP4 DIFF to SE exit ============
2220 01:18:53.013667 [ANA_INIT] <<<<<<<<<<<<<
2221 01:18:53.017295 [Flow] Enable top DCM control >>>>>
2222 01:18:53.020503 [Flow] Enable top DCM control <<<<<
2223 01:18:53.023858 Enable DLL master slave shuffle
2224 01:18:53.027302 ==============================================================
2225 01:18:53.030440 Gating Mode config
2226 01:18:53.036630 ==============================================================
2227 01:18:53.037085 Config description:
2228 01:18:53.046872 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2229 01:18:53.053319 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2230 01:18:53.056691 SELPH_MODE 0: By rank 1: By Phase
2231 01:18:53.063926 ==============================================================
2232 01:18:53.066582 GAT_TRACK_EN = 1
2233 01:18:53.070197 RX_GATING_MODE = 2
2234 01:18:53.073201 RX_GATING_TRACK_MODE = 2
2235 01:18:53.076794 SELPH_MODE = 1
2236 01:18:53.080515 PICG_EARLY_EN = 1
2237 01:18:53.083683 VALID_LAT_VALUE = 1
2238 01:18:53.086954 ==============================================================
2239 01:18:53.090128 Enter into Gating configuration >>>>
2240 01:18:53.093276 Exit from Gating configuration <<<<
2241 01:18:53.096541 Enter into DVFS_PRE_config >>>>>
2242 01:18:53.109878 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2243 01:18:53.110433 Exit from DVFS_PRE_config <<<<<
2244 01:18:53.113364 Enter into PICG configuration >>>>
2245 01:18:53.116667 Exit from PICG configuration <<<<
2246 01:18:53.120014 [RX_INPUT] configuration >>>>>
2247 01:18:53.123083 [RX_INPUT] configuration <<<<<
2248 01:18:53.130138 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2249 01:18:53.132849 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2250 01:18:53.140124 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 01:18:53.146472 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 01:18:53.153552 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 01:18:53.159780 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 01:18:53.163038 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2255 01:18:53.166450 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2256 01:18:53.170192 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2257 01:18:53.176763 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2258 01:18:53.180137 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2259 01:18:53.183288 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 01:18:53.186802 ===================================
2261 01:18:53.189762 LPDDR4 DRAM CONFIGURATION
2262 01:18:53.193040 ===================================
2263 01:18:53.193659 EX_ROW_EN[0] = 0x0
2264 01:18:53.196772 EX_ROW_EN[1] = 0x0
2265 01:18:53.200009 LP4Y_EN = 0x0
2266 01:18:53.200574 WORK_FSP = 0x0
2267 01:18:53.203067 WL = 0x4
2268 01:18:53.203624 RL = 0x4
2269 01:18:53.206419 BL = 0x2
2270 01:18:53.206955 RPST = 0x0
2271 01:18:53.209854 RD_PRE = 0x0
2272 01:18:53.210517 WR_PRE = 0x1
2273 01:18:53.213255 WR_PST = 0x0
2274 01:18:53.213773 DBI_WR = 0x0
2275 01:18:53.216711 DBI_RD = 0x0
2276 01:18:53.217278 OTF = 0x1
2277 01:18:53.219629 ===================================
2278 01:18:53.222740 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2279 01:18:53.229843 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2280 01:18:53.233182 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2281 01:18:53.236495 ===================================
2282 01:18:53.239356 LPDDR4 DRAM CONFIGURATION
2283 01:18:53.242650 ===================================
2284 01:18:53.243104 EX_ROW_EN[0] = 0x10
2285 01:18:53.246036 EX_ROW_EN[1] = 0x0
2286 01:18:53.246488 LP4Y_EN = 0x0
2287 01:18:53.249539 WORK_FSP = 0x0
2288 01:18:53.250005 WL = 0x4
2289 01:18:53.253113 RL = 0x4
2290 01:18:53.253729 BL = 0x2
2291 01:18:53.256793 RPST = 0x0
2292 01:18:53.259525 RD_PRE = 0x0
2293 01:18:53.259973 WR_PRE = 0x1
2294 01:18:53.262922 WR_PST = 0x0
2295 01:18:53.263377 DBI_WR = 0x0
2296 01:18:53.266009 DBI_RD = 0x0
2297 01:18:53.266460 OTF = 0x1
2298 01:18:53.269565 ===================================
2299 01:18:53.276009 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2300 01:18:53.276455 ==
2301 01:18:53.279342 Dram Type= 6, Freq= 0, CH_0, rank 0
2302 01:18:53.282573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2303 01:18:53.283067 ==
2304 01:18:53.286083 [Duty_Offset_Calibration]
2305 01:18:53.286536 B0:2 B1:0 CA:3
2306 01:18:53.289378
2307 01:18:53.293145 [DutyScan_Calibration_Flow] k_type=0
2308 01:18:53.300965
2309 01:18:53.301379 ==CLK 0==
2310 01:18:53.303946 Final CLK duty delay cell = 0
2311 01:18:53.307070 [0] MAX Duty = 5031%(X100), DQS PI = 12
2312 01:18:53.310575 [0] MIN Duty = 4906%(X100), DQS PI = 54
2313 01:18:53.314049 [0] AVG Duty = 4968%(X100)
2314 01:18:53.314467
2315 01:18:53.316948 CH0 CLK Duty spec in!! Max-Min= 125%
2316 01:18:53.320316 [DutyScan_Calibration_Flow] ====Done====
2317 01:18:53.320629
2318 01:18:53.323469 [DutyScan_Calibration_Flow] k_type=1
2319 01:18:53.339299
2320 01:18:53.339861 ==DQS 0 ==
2321 01:18:53.342430 Final DQS duty delay cell = 0
2322 01:18:53.346007 [0] MAX Duty = 5062%(X100), DQS PI = 12
2323 01:18:53.348967 [0] MIN Duty = 4907%(X100), DQS PI = 2
2324 01:18:53.349574 [0] AVG Duty = 4984%(X100)
2325 01:18:53.352514
2326 01:18:53.353057 ==DQS 1 ==
2327 01:18:53.355581 Final DQS duty delay cell = -4
2328 01:18:53.359216 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2329 01:18:53.362544 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2330 01:18:53.365952 [-4] AVG Duty = 4937%(X100)
2331 01:18:53.366504
2332 01:18:53.369154 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2333 01:18:53.369723
2334 01:18:53.372439 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2335 01:18:53.376156 [DutyScan_Calibration_Flow] ====Done====
2336 01:18:53.376613
2337 01:18:53.379043 [DutyScan_Calibration_Flow] k_type=3
2338 01:18:53.396915
2339 01:18:53.397562 ==DQM 0 ==
2340 01:18:53.400158 Final DQM duty delay cell = 0
2341 01:18:53.403480 [0] MAX Duty = 5124%(X100), DQS PI = 28
2342 01:18:53.406924 [0] MIN Duty = 4876%(X100), DQS PI = 0
2343 01:18:53.407480 [0] AVG Duty = 5000%(X100)
2344 01:18:53.410467
2345 01:18:53.411015 ==DQM 1 ==
2346 01:18:53.413717 Final DQM duty delay cell = 4
2347 01:18:53.416852 [4] MAX Duty = 5124%(X100), DQS PI = 50
2348 01:18:53.420216 [4] MIN Duty = 5000%(X100), DQS PI = 12
2349 01:18:53.420770 [4] AVG Duty = 5062%(X100)
2350 01:18:53.423874
2351 01:18:53.426673 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2352 01:18:53.427226
2353 01:18:53.429967 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2354 01:18:53.433402 [DutyScan_Calibration_Flow] ====Done====
2355 01:18:53.434003
2356 01:18:53.436796 [DutyScan_Calibration_Flow] k_type=2
2357 01:18:53.451964
2358 01:18:53.452600 ==DQ 0 ==
2359 01:18:53.455131 Final DQ duty delay cell = -4
2360 01:18:53.458218 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2361 01:18:53.461473 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2362 01:18:53.464581 [-4] AVG Duty = 4969%(X100)
2363 01:18:53.464660
2364 01:18:53.464723 ==DQ 1 ==
2365 01:18:53.467845 Final DQ duty delay cell = -4
2366 01:18:53.471325 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2367 01:18:53.474516 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2368 01:18:53.478057 [-4] AVG Duty = 4922%(X100)
2369 01:18:53.478222
2370 01:18:53.481525 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2371 01:18:53.481657
2372 01:18:53.485146 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2373 01:18:53.487917 [DutyScan_Calibration_Flow] ====Done====
2374 01:18:53.488065 ==
2375 01:18:53.491864 Dram Type= 6, Freq= 0, CH_1, rank 0
2376 01:18:53.494652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2377 01:18:53.494852 ==
2378 01:18:53.498208 [Duty_Offset_Calibration]
2379 01:18:53.498415 B0:1 B1:-2 CA:0
2380 01:18:53.498529
2381 01:18:53.501383 [DutyScan_Calibration_Flow] k_type=0
2382 01:18:53.511956
2383 01:18:53.512237 ==CLK 0==
2384 01:18:53.514694 Final CLK duty delay cell = 0
2385 01:18:53.518139 [0] MAX Duty = 5062%(X100), DQS PI = 30
2386 01:18:53.521670 [0] MIN Duty = 4876%(X100), DQS PI = 58
2387 01:18:53.522124 [0] AVG Duty = 4969%(X100)
2388 01:18:53.525109
2389 01:18:53.528867 CH1 CLK Duty spec in!! Max-Min= 186%
2390 01:18:53.532211 [DutyScan_Calibration_Flow] ====Done====
2391 01:18:53.532769
2392 01:18:53.535466 [DutyScan_Calibration_Flow] k_type=1
2393 01:18:53.550427
2394 01:18:53.550973 ==DQS 0 ==
2395 01:18:53.554034 Final DQS duty delay cell = -4
2396 01:18:53.556797 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2397 01:18:53.560304 [-4] MIN Duty = 4876%(X100), DQS PI = 52
2398 01:18:53.563642 [-4] AVG Duty = 4953%(X100)
2399 01:18:53.564098
2400 01:18:53.564455 ==DQS 1 ==
2401 01:18:53.566735 Final DQS duty delay cell = 0
2402 01:18:53.570159 [0] MAX Duty = 5062%(X100), DQS PI = 0
2403 01:18:53.573580 [0] MIN Duty = 4875%(X100), DQS PI = 26
2404 01:18:53.577133 [0] AVG Duty = 4968%(X100)
2405 01:18:53.577622
2406 01:18:53.580320 CH1 DQS 0 Duty spec in!! Max-Min= 155%
2407 01:18:53.580781
2408 01:18:53.583793 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2409 01:18:53.587130 [DutyScan_Calibration_Flow] ====Done====
2410 01:18:53.587726
2411 01:18:53.589986 [DutyScan_Calibration_Flow] k_type=3
2412 01:18:53.607409
2413 01:18:53.607988 ==DQM 0 ==
2414 01:18:53.610297 Final DQM duty delay cell = 0
2415 01:18:53.614014 [0] MAX Duty = 5000%(X100), DQS PI = 22
2416 01:18:53.616821 [0] MIN Duty = 4844%(X100), DQS PI = 52
2417 01:18:53.620261 [0] AVG Duty = 4922%(X100)
2418 01:18:53.620810
2419 01:18:53.621250 ==DQM 1 ==
2420 01:18:53.623847 Final DQM duty delay cell = 0
2421 01:18:53.626884 [0] MAX Duty = 5031%(X100), DQS PI = 36
2422 01:18:53.630034 [0] MIN Duty = 4907%(X100), DQS PI = 2
2423 01:18:53.633647 [0] AVG Duty = 4969%(X100)
2424 01:18:53.634106
2425 01:18:53.636595 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2426 01:18:53.637053
2427 01:18:53.640542 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2428 01:18:53.643321 [DutyScan_Calibration_Flow] ====Done====
2429 01:18:53.643778
2430 01:18:53.646593 [DutyScan_Calibration_Flow] k_type=2
2431 01:18:53.663497
2432 01:18:53.664074 ==DQ 0 ==
2433 01:18:53.667280 Final DQ duty delay cell = 0
2434 01:18:53.670420 [0] MAX Duty = 5062%(X100), DQS PI = 12
2435 01:18:53.673691 [0] MIN Duty = 4938%(X100), DQS PI = 54
2436 01:18:53.674244 [0] AVG Duty = 5000%(X100)
2437 01:18:53.676987
2438 01:18:53.677595 ==DQ 1 ==
2439 01:18:53.680286 Final DQ duty delay cell = 0
2440 01:18:53.683511 [0] MAX Duty = 5125%(X100), DQS PI = 36
2441 01:18:53.686815 [0] MIN Duty = 4969%(X100), DQS PI = 26
2442 01:18:53.687276 [0] AVG Duty = 5047%(X100)
2443 01:18:53.687641
2444 01:18:53.693564 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2445 01:18:53.694280
2446 01:18:53.696842 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2447 01:18:53.700227 [DutyScan_Calibration_Flow] ====Done====
2448 01:18:53.703496 nWR fixed to 30
2449 01:18:53.703960 [ModeRegInit_LP4] CH0 RK0
2450 01:18:53.707179 [ModeRegInit_LP4] CH0 RK1
2451 01:18:53.710518 [ModeRegInit_LP4] CH1 RK0
2452 01:18:53.711073 [ModeRegInit_LP4] CH1 RK1
2453 01:18:53.713425 match AC timing 7
2454 01:18:53.716657 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2455 01:18:53.723967 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2456 01:18:53.726891 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2457 01:18:53.733284 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2458 01:18:53.736846 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2459 01:18:53.737389 ==
2460 01:18:53.739755 Dram Type= 6, Freq= 0, CH_0, rank 0
2461 01:18:53.743143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2462 01:18:53.743606 ==
2463 01:18:53.750145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2464 01:18:53.756722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2465 01:18:53.763396 [CA 0] Center 40 (10~71) winsize 62
2466 01:18:53.766850 [CA 1] Center 39 (9~70) winsize 62
2467 01:18:53.770482 [CA 2] Center 36 (6~66) winsize 61
2468 01:18:53.773311 [CA 3] Center 35 (5~66) winsize 62
2469 01:18:53.776688 [CA 4] Center 34 (4~65) winsize 62
2470 01:18:53.780344 [CA 5] Center 33 (3~63) winsize 61
2471 01:18:53.780894
2472 01:18:53.783635 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2473 01:18:53.784191
2474 01:18:53.786858 [CATrainingPosCal] consider 1 rank data
2475 01:18:53.790191 u2DelayCellTimex100 = 270/100 ps
2476 01:18:53.794035 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2477 01:18:53.800295 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2478 01:18:53.803438 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2479 01:18:53.806972 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2480 01:18:53.810222 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2481 01:18:53.813636 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2482 01:18:53.814196
2483 01:18:53.816852 CA PerBit enable=1, Macro0, CA PI delay=33
2484 01:18:53.817310
2485 01:18:53.819841 [CBTSetCACLKResult] CA Dly = 33
2486 01:18:53.823752 CS Dly: 7 (0~38)
2487 01:18:53.824298 ==
2488 01:18:53.827219 Dram Type= 6, Freq= 0, CH_0, rank 1
2489 01:18:53.830099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 01:18:53.830658 ==
2491 01:18:53.836738 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 01:18:53.839743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2493 01:18:53.850066 [CA 0] Center 40 (10~70) winsize 61
2494 01:18:53.852681 [CA 1] Center 40 (10~70) winsize 61
2495 01:18:53.856001 [CA 2] Center 36 (6~66) winsize 61
2496 01:18:53.859819 [CA 3] Center 35 (5~66) winsize 62
2497 01:18:53.862674 [CA 4] Center 34 (4~65) winsize 62
2498 01:18:53.866159 [CA 5] Center 33 (3~64) winsize 62
2499 01:18:53.866615
2500 01:18:53.869907 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2501 01:18:53.870461
2502 01:18:53.873213 [CATrainingPosCal] consider 2 rank data
2503 01:18:53.876225 u2DelayCellTimex100 = 270/100 ps
2504 01:18:53.879651 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2505 01:18:53.886207 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2506 01:18:53.889782 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2507 01:18:53.893148 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2508 01:18:53.896121 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2509 01:18:53.899758 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2510 01:18:53.900313
2511 01:18:53.902655 CA PerBit enable=1, Macro0, CA PI delay=33
2512 01:18:53.903215
2513 01:18:53.906230 [CBTSetCACLKResult] CA Dly = 33
2514 01:18:53.909420 CS Dly: 8 (0~40)
2515 01:18:53.910019
2516 01:18:53.913337 ----->DramcWriteLeveling(PI) begin...
2517 01:18:53.913951 ==
2518 01:18:53.915975 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 01:18:53.919088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 01:18:53.919544 ==
2521 01:18:53.922474 Write leveling (Byte 0): 33 => 33
2522 01:18:53.926020 Write leveling (Byte 1): 29 => 29
2523 01:18:53.929489 DramcWriteLeveling(PI) end<-----
2524 01:18:53.929998
2525 01:18:53.930359 ==
2526 01:18:53.932390 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 01:18:53.935783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 01:18:53.936242 ==
2529 01:18:53.939211 [Gating] SW mode calibration
2530 01:18:53.945863 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2531 01:18:53.952425 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2532 01:18:53.955796 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 01:18:53.959702 0 15 4 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
2534 01:18:53.965812 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 01:18:53.969344 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 01:18:53.972918 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 01:18:53.979775 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 01:18:53.982953 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 01:18:53.986100 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2540 01:18:53.992692 1 0 0 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (0 0)
2541 01:18:53.996013 1 0 4 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2542 01:18:53.999089 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 01:18:54.006378 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 01:18:54.009038 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 01:18:54.012476 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 01:18:54.019233 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 01:18:54.022122 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2548 01:18:54.025628 1 1 0 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
2549 01:18:54.032055 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2550 01:18:54.035400 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 01:18:54.038942 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 01:18:54.042073 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 01:18:54.048463 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 01:18:54.052080 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 01:18:54.055436 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2556 01:18:54.062199 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2557 01:18:54.065654 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2558 01:18:54.068266 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 01:18:54.075117 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 01:18:54.078368 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 01:18:54.081464 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 01:18:54.088691 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 01:18:54.091961 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 01:18:54.095114 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 01:18:54.101499 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 01:18:54.104987 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 01:18:54.108478 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 01:18:54.114818 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 01:18:54.118417 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 01:18:54.121865 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 01:18:54.128375 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2572 01:18:54.131573 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2573 01:18:54.135117 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2574 01:18:54.138487 Total UI for P1: 0, mck2ui 16
2575 01:18:54.141521 best dqsien dly found for B0: ( 1, 3, 30)
2576 01:18:54.144985 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 01:18:54.148343 Total UI for P1: 0, mck2ui 16
2578 01:18:54.151693 best dqsien dly found for B1: ( 1, 4, 4)
2579 01:18:54.154910 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2580 01:18:54.161856 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2581 01:18:54.161939
2582 01:18:54.164676 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2583 01:18:54.168136 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2584 01:18:54.171564 [Gating] SW calibration Done
2585 01:18:54.171646 ==
2586 01:18:54.175027 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 01:18:54.178509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 01:18:54.178591 ==
2589 01:18:54.178655 RX Vref Scan: 0
2590 01:18:54.181207
2591 01:18:54.181287 RX Vref 0 -> 0, step: 1
2592 01:18:54.181351
2593 01:18:54.184702 RX Delay -40 -> 252, step: 8
2594 01:18:54.188483 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2595 01:18:54.192056 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2596 01:18:54.197900 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2597 01:18:54.201145 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2598 01:18:54.204831 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2599 01:18:54.207932 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2600 01:18:54.211688 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2601 01:18:54.218106 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2602 01:18:54.221684 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2603 01:18:54.224715 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2604 01:18:54.228200 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2605 01:18:54.231489 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2606 01:18:54.234694 iDelay=200, Bit 12, Center 107 (40 ~ 175) 136
2607 01:18:54.241457 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2608 01:18:54.245150 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2609 01:18:54.247978 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2610 01:18:54.248112 ==
2611 01:18:54.251641 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 01:18:54.254658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 01:18:54.258025 ==
2614 01:18:54.258157 DQS Delay:
2615 01:18:54.258277 DQS0 = 0, DQS1 = 0
2616 01:18:54.261250 DQM Delay:
2617 01:18:54.261381 DQM0 = 112, DQM1 = 102
2618 01:18:54.264647 DQ Delay:
2619 01:18:54.267983 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2620 01:18:54.271552 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2621 01:18:54.274947 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2622 01:18:54.277808 DQ12 =107, DQ13 =107, DQ14 =119, DQ15 =111
2623 01:18:54.277941
2624 01:18:54.278064
2625 01:18:54.278184 ==
2626 01:18:54.281205 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 01:18:54.284581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 01:18:54.284721 ==
2629 01:18:54.284844
2630 01:18:54.284963
2631 01:18:54.287999 TX Vref Scan disable
2632 01:18:54.291277 == TX Byte 0 ==
2633 01:18:54.294506 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2634 01:18:54.298411 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2635 01:18:54.301694 == TX Byte 1 ==
2636 01:18:54.305091 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2637 01:18:54.308458 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2638 01:18:54.308590 ==
2639 01:18:54.311382 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 01:18:54.314748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 01:18:54.314880 ==
2642 01:18:54.328557 TX Vref=22, minBit 7, minWin=25, winSum=417
2643 01:18:54.331762 TX Vref=24, minBit 7, minWin=25, winSum=423
2644 01:18:54.334847 TX Vref=26, minBit 7, minWin=26, winSum=428
2645 01:18:54.338179 TX Vref=28, minBit 4, minWin=26, winSum=431
2646 01:18:54.341718 TX Vref=30, minBit 14, minWin=26, winSum=433
2647 01:18:54.348104 TX Vref=32, minBit 2, minWin=26, winSum=428
2648 01:18:54.351487 [TxChooseVref] Worse bit 14, Min win 26, Win sum 433, Final Vref 30
2649 01:18:54.351619
2650 01:18:54.354670 Final TX Range 1 Vref 30
2651 01:18:54.354801
2652 01:18:54.354920 ==
2653 01:18:54.358180 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 01:18:54.361487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 01:18:54.361659 ==
2656 01:18:54.364800
2657 01:18:54.364929
2658 01:18:54.365051 TX Vref Scan disable
2659 01:18:54.367915 == TX Byte 0 ==
2660 01:18:54.371553 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2661 01:18:54.378130 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2662 01:18:54.378263 == TX Byte 1 ==
2663 01:18:54.381433 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2664 01:18:54.388162 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2665 01:18:54.388296
2666 01:18:54.388418 [DATLAT]
2667 01:18:54.388537 Freq=1200, CH0 RK0
2668 01:18:54.388653
2669 01:18:54.391561 DATLAT Default: 0xd
2670 01:18:54.391690 0, 0xFFFF, sum = 0
2671 01:18:54.394867 1, 0xFFFF, sum = 0
2672 01:18:54.398043 2, 0xFFFF, sum = 0
2673 01:18:54.398180 3, 0xFFFF, sum = 0
2674 01:18:54.401322 4, 0xFFFF, sum = 0
2675 01:18:54.401456 5, 0xFFFF, sum = 0
2676 01:18:54.404233 6, 0xFFFF, sum = 0
2677 01:18:54.404367 7, 0xFFFF, sum = 0
2678 01:18:54.408255 8, 0xFFFF, sum = 0
2679 01:18:54.408388 9, 0xFFFF, sum = 0
2680 01:18:54.411054 10, 0xFFFF, sum = 0
2681 01:18:54.411185 11, 0xFFFF, sum = 0
2682 01:18:54.414383 12, 0x0, sum = 1
2683 01:18:54.414515 13, 0x0, sum = 2
2684 01:18:54.417648 14, 0x0, sum = 3
2685 01:18:54.417780 15, 0x0, sum = 4
2686 01:18:54.421058 best_step = 13
2687 01:18:54.421188
2688 01:18:54.421306 ==
2689 01:18:54.424470 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 01:18:54.427906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 01:18:54.428039 ==
2692 01:18:54.428161 RX Vref Scan: 1
2693 01:18:54.431147
2694 01:18:54.431276 Set Vref Range= 32 -> 127
2695 01:18:54.431394
2696 01:18:54.434390 RX Vref 32 -> 127, step: 1
2697 01:18:54.434517
2698 01:18:54.437941 RX Delay -37 -> 252, step: 4
2699 01:18:54.438066
2700 01:18:54.440948 Set Vref, RX VrefLevel [Byte0]: 32
2701 01:18:54.444662 [Byte1]: 32
2702 01:18:54.444784
2703 01:18:54.447554 Set Vref, RX VrefLevel [Byte0]: 33
2704 01:18:54.450816 [Byte1]: 33
2705 01:18:54.454831
2706 01:18:54.454962 Set Vref, RX VrefLevel [Byte0]: 34
2707 01:18:54.458302 [Byte1]: 34
2708 01:18:54.463114
2709 01:18:54.463245 Set Vref, RX VrefLevel [Byte0]: 35
2710 01:18:54.466438 [Byte1]: 35
2711 01:18:54.470588
2712 01:18:54.470716 Set Vref, RX VrefLevel [Byte0]: 36
2713 01:18:54.473915 [Byte1]: 36
2714 01:18:54.478658
2715 01:18:54.478790 Set Vref, RX VrefLevel [Byte0]: 37
2716 01:18:54.482067 [Byte1]: 37
2717 01:18:54.487342
2718 01:18:54.487470 Set Vref, RX VrefLevel [Byte0]: 38
2719 01:18:54.490079 [Byte1]: 38
2720 01:18:54.495016
2721 01:18:54.495140 Set Vref, RX VrefLevel [Byte0]: 39
2722 01:18:54.498297 [Byte1]: 39
2723 01:18:54.502789
2724 01:18:54.502921 Set Vref, RX VrefLevel [Byte0]: 40
2725 01:18:54.506116 [Byte1]: 40
2726 01:18:54.510683
2727 01:18:54.510808 Set Vref, RX VrefLevel [Byte0]: 41
2728 01:18:54.514351 [Byte1]: 41
2729 01:18:54.518656
2730 01:18:54.518789 Set Vref, RX VrefLevel [Byte0]: 42
2731 01:18:54.522420 [Byte1]: 42
2732 01:18:54.526973
2733 01:18:54.527107 Set Vref, RX VrefLevel [Byte0]: 43
2734 01:18:54.530248 [Byte1]: 43
2735 01:18:54.534678
2736 01:18:54.534807 Set Vref, RX VrefLevel [Byte0]: 44
2737 01:18:54.538031 [Byte1]: 44
2738 01:18:54.542849
2739 01:18:54.543009 Set Vref, RX VrefLevel [Byte0]: 45
2740 01:18:54.546299 [Byte1]: 45
2741 01:18:54.550689
2742 01:18:54.550820 Set Vref, RX VrefLevel [Byte0]: 46
2743 01:18:54.553879 [Byte1]: 46
2744 01:18:54.559080
2745 01:18:54.559210 Set Vref, RX VrefLevel [Byte0]: 47
2746 01:18:54.562220 [Byte1]: 47
2747 01:18:54.567094
2748 01:18:54.567228 Set Vref, RX VrefLevel [Byte0]: 48
2749 01:18:54.569975 [Byte1]: 48
2750 01:18:54.574889
2751 01:18:54.575016 Set Vref, RX VrefLevel [Byte0]: 49
2752 01:18:54.578263 [Byte1]: 49
2753 01:18:54.583003
2754 01:18:54.583137 Set Vref, RX VrefLevel [Byte0]: 50
2755 01:18:54.586135 [Byte1]: 50
2756 01:18:54.590590
2757 01:18:54.590714 Set Vref, RX VrefLevel [Byte0]: 51
2758 01:18:54.593905 [Byte1]: 51
2759 01:18:54.598962
2760 01:18:54.599095 Set Vref, RX VrefLevel [Byte0]: 52
2761 01:18:54.602431 [Byte1]: 52
2762 01:18:54.606748
2763 01:18:54.606877 Set Vref, RX VrefLevel [Byte0]: 53
2764 01:18:54.610155 [Byte1]: 53
2765 01:18:54.614685
2766 01:18:54.614814 Set Vref, RX VrefLevel [Byte0]: 54
2767 01:18:54.618176 [Byte1]: 54
2768 01:18:54.622874
2769 01:18:54.623006 Set Vref, RX VrefLevel [Byte0]: 55
2770 01:18:54.625984 [Byte1]: 55
2771 01:18:54.630528
2772 01:18:54.630660 Set Vref, RX VrefLevel [Byte0]: 56
2773 01:18:54.634017 [Byte1]: 56
2774 01:18:54.638979
2775 01:18:54.639060 Set Vref, RX VrefLevel [Byte0]: 57
2776 01:18:54.642408 [Byte1]: 57
2777 01:18:54.646719
2778 01:18:54.646800 Set Vref, RX VrefLevel [Byte0]: 58
2779 01:18:54.650337 [Byte1]: 58
2780 01:18:54.655024
2781 01:18:54.655106 Set Vref, RX VrefLevel [Byte0]: 59
2782 01:18:54.658007 [Byte1]: 59
2783 01:18:54.663145
2784 01:18:54.663227 Set Vref, RX VrefLevel [Byte0]: 60
2785 01:18:54.665925 [Byte1]: 60
2786 01:18:54.670828
2787 01:18:54.670909 Set Vref, RX VrefLevel [Byte0]: 61
2788 01:18:54.674006 [Byte1]: 61
2789 01:18:54.679039
2790 01:18:54.679228 Set Vref, RX VrefLevel [Byte0]: 62
2791 01:18:54.682384 [Byte1]: 62
2792 01:18:54.686771
2793 01:18:54.686855 Set Vref, RX VrefLevel [Byte0]: 63
2794 01:18:54.690158 [Byte1]: 63
2795 01:18:54.694944
2796 01:18:54.695034 Set Vref, RX VrefLevel [Byte0]: 64
2797 01:18:54.701052 [Byte1]: 64
2798 01:18:54.701138
2799 01:18:54.704600 Set Vref, RX VrefLevel [Byte0]: 65
2800 01:18:54.708004 [Byte1]: 65
2801 01:18:54.708089
2802 01:18:54.711184 Set Vref, RX VrefLevel [Byte0]: 66
2803 01:18:54.714396 [Byte1]: 66
2804 01:18:54.718613
2805 01:18:54.718696 Set Vref, RX VrefLevel [Byte0]: 67
2806 01:18:54.722104 [Byte1]: 67
2807 01:18:54.727227
2808 01:18:54.727549 Set Vref, RX VrefLevel [Byte0]: 68
2809 01:18:54.730174 [Byte1]: 68
2810 01:18:54.735226
2811 01:18:54.735463 Set Vref, RX VrefLevel [Byte0]: 69
2812 01:18:54.738313 [Byte1]: 69
2813 01:18:54.743337
2814 01:18:54.743750 Set Vref, RX VrefLevel [Byte0]: 70
2815 01:18:54.746890 [Byte1]: 70
2816 01:18:54.751304
2817 01:18:54.751721 Set Vref, RX VrefLevel [Byte0]: 71
2818 01:18:54.754568 [Byte1]: 71
2819 01:18:54.759288
2820 01:18:54.759697 Set Vref, RX VrefLevel [Byte0]: 72
2821 01:18:54.762321 [Byte1]: 72
2822 01:18:54.767154
2823 01:18:54.767565 Set Vref, RX VrefLevel [Byte0]: 73
2824 01:18:54.770540 [Byte1]: 73
2825 01:18:54.775354
2826 01:18:54.775818 Set Vref, RX VrefLevel [Byte0]: 74
2827 01:18:54.778959 [Byte1]: 74
2828 01:18:54.783538
2829 01:18:54.783999 Set Vref, RX VrefLevel [Byte0]: 75
2830 01:18:54.786666 [Byte1]: 75
2831 01:18:54.791253
2832 01:18:54.791710 Final RX Vref Byte 0 = 61 to rank0
2833 01:18:54.794906 Final RX Vref Byte 1 = 57 to rank0
2834 01:18:54.798234 Final RX Vref Byte 0 = 61 to rank1
2835 01:18:54.800653 Final RX Vref Byte 1 = 57 to rank1==
2836 01:18:54.804530 Dram Type= 6, Freq= 0, CH_0, rank 0
2837 01:18:54.807849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 01:18:54.811264 ==
2839 01:18:54.811413 DQS Delay:
2840 01:18:54.811487 DQS0 = 0, DQS1 = 0
2841 01:18:54.814491 DQM Delay:
2842 01:18:54.814605 DQM0 = 112, DQM1 = 102
2843 01:18:54.817363 DQ Delay:
2844 01:18:54.821268 DQ0 =112, DQ1 =114, DQ2 =112, DQ3 =108
2845 01:18:54.824172 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2846 01:18:54.827387 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2847 01:18:54.831107 DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =110
2848 01:18:54.831200
2849 01:18:54.831268
2850 01:18:54.837702 [DQSOSCAuto] RK0, (LSB)MR18= 0xf9f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
2851 01:18:54.840889 CH0 RK0: MR19=303, MR18=F9F8
2852 01:18:54.847665 CH0_RK0: MR19=0x303, MR18=0xF9F8, DQSOSC=412, MR23=63, INC=38, DEC=25
2853 01:18:54.847832
2854 01:18:54.851132 ----->DramcWriteLeveling(PI) begin...
2855 01:18:54.851272 ==
2856 01:18:54.854354 Dram Type= 6, Freq= 0, CH_0, rank 1
2857 01:18:54.857765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2858 01:18:54.861230 ==
2859 01:18:54.861408 Write leveling (Byte 0): 31 => 31
2860 01:18:54.864403 Write leveling (Byte 1): 29 => 29
2861 01:18:54.867588 DramcWriteLeveling(PI) end<-----
2862 01:18:54.867792
2863 01:18:54.867899 ==
2864 01:18:54.871101 Dram Type= 6, Freq= 0, CH_0, rank 1
2865 01:18:54.877736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2866 01:18:54.877979 ==
2867 01:18:54.878116 [Gating] SW mode calibration
2868 01:18:54.887822 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2869 01:18:54.891199 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2870 01:18:54.894600 0 15 0 | B1->B0 | 2828 3333 | 1 1 | (0 0) (1 1)
2871 01:18:54.901034 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 01:18:54.904714 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 01:18:54.908189 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2874 01:18:54.914651 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2875 01:18:54.918102 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2876 01:18:54.921873 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2877 01:18:54.927753 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
2878 01:18:54.931508 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2879 01:18:54.934614 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 01:18:54.941549 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 01:18:54.944822 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2882 01:18:54.948146 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2883 01:18:54.954949 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2884 01:18:54.958454 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2885 01:18:54.961787 1 0 28 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
2886 01:18:54.967992 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
2887 01:18:54.971861 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 01:18:54.975026 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 01:18:54.977970 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 01:18:54.984816 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 01:18:54.988171 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 01:18:54.991431 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 01:18:54.998029 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2894 01:18:55.001576 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2895 01:18:55.004648 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 01:18:55.011248 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 01:18:55.014346 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 01:18:55.018068 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 01:18:55.024832 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 01:18:55.030142 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 01:18:55.030737 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 01:18:55.037503 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 01:18:55.040662 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 01:18:55.043930 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 01:18:55.051074 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 01:18:55.054618 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 01:18:55.057644 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 01:18:55.064437 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2909 01:18:55.067905 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2910 01:18:55.071279 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2911 01:18:55.074109 Total UI for P1: 0, mck2ui 16
2912 01:18:55.077440 best dqsien dly found for B0: ( 1, 3, 26)
2913 01:18:55.080851 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 01:18:55.084293 Total UI for P1: 0, mck2ui 16
2915 01:18:55.087810 best dqsien dly found for B1: ( 1, 4, 0)
2916 01:18:55.091056 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2917 01:18:55.094849 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2918 01:18:55.097579
2919 01:18:55.100944 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2920 01:18:55.104281 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2921 01:18:55.107696 [Gating] SW calibration Done
2922 01:18:55.108055 ==
2923 01:18:55.110779 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 01:18:55.114998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 01:18:55.115567 ==
2926 01:18:55.115937 RX Vref Scan: 0
2927 01:18:55.116276
2928 01:18:55.117583 RX Vref 0 -> 0, step: 1
2929 01:18:55.118049
2930 01:18:55.121245 RX Delay -40 -> 252, step: 8
2931 01:18:55.124590 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2932 01:18:55.127940 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2933 01:18:55.134921 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2934 01:18:55.137857 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2935 01:18:55.141271 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2936 01:18:55.144613 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2937 01:18:55.148073 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2938 01:18:55.150953 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2939 01:18:55.157581 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2940 01:18:55.161572 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
2941 01:18:55.164578 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2942 01:18:55.168434 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2943 01:18:55.171557 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2944 01:18:55.177783 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2945 01:18:55.181351 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2946 01:18:55.184565 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2947 01:18:55.185122 ==
2948 01:18:55.187970 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 01:18:55.191321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 01:18:55.191883 ==
2951 01:18:55.194285 DQS Delay:
2952 01:18:55.194740 DQS0 = 0, DQS1 = 0
2953 01:18:55.197913 DQM Delay:
2954 01:18:55.198482 DQM0 = 112, DQM1 = 102
2955 01:18:55.198854 DQ Delay:
2956 01:18:55.204713 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2957 01:18:55.208176 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2958 01:18:55.211216 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2959 01:18:55.215135 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2960 01:18:55.215696
2961 01:18:55.216059
2962 01:18:55.216394 ==
2963 01:18:55.217967 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 01:18:55.221660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 01:18:55.222223 ==
2966 01:18:55.222588
2967 01:18:55.222920
2968 01:18:55.225097 TX Vref Scan disable
2969 01:18:55.225700 == TX Byte 0 ==
2970 01:18:55.231814 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2971 01:18:55.234606 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2972 01:18:55.235189 == TX Byte 1 ==
2973 01:18:55.241594 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2974 01:18:55.244591 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2975 01:18:55.245055 ==
2976 01:18:55.248338 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 01:18:55.251265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 01:18:55.251733 ==
2979 01:18:55.264376 TX Vref=22, minBit 0, minWin=26, winSum=426
2980 01:18:55.267944 TX Vref=24, minBit 5, minWin=26, winSum=432
2981 01:18:55.271117 TX Vref=26, minBit 1, minWin=26, winSum=437
2982 01:18:55.274441 TX Vref=28, minBit 1, minWin=27, winSum=443
2983 01:18:55.277437 TX Vref=30, minBit 8, minWin=27, winSum=447
2984 01:18:55.284603 TX Vref=32, minBit 8, minWin=26, winSum=437
2985 01:18:55.287658 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 30
2986 01:18:55.288121
2987 01:18:55.291267 Final TX Range 1 Vref 30
2988 01:18:55.291833
2989 01:18:55.292199 ==
2990 01:18:55.294685 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 01:18:55.298143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 01:18:55.298713 ==
2993 01:18:55.300794
2994 01:18:55.301356
2995 01:18:55.301769 TX Vref Scan disable
2996 01:18:55.304146 == TX Byte 0 ==
2997 01:18:55.307714 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2998 01:18:55.310988 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2999 01:18:55.314594 == TX Byte 1 ==
3000 01:18:55.317590 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3001 01:18:55.324630 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3002 01:18:55.325208
3003 01:18:55.325600 [DATLAT]
3004 01:18:55.325947 Freq=1200, CH0 RK1
3005 01:18:55.326276
3006 01:18:55.327465 DATLAT Default: 0xd
3007 01:18:55.327921 0, 0xFFFF, sum = 0
3008 01:18:55.330688 1, 0xFFFF, sum = 0
3009 01:18:55.331262 2, 0xFFFF, sum = 0
3010 01:18:55.334551 3, 0xFFFF, sum = 0
3011 01:18:55.337668 4, 0xFFFF, sum = 0
3012 01:18:55.338237 5, 0xFFFF, sum = 0
3013 01:18:55.340624 6, 0xFFFF, sum = 0
3014 01:18:55.341088 7, 0xFFFF, sum = 0
3015 01:18:55.344172 8, 0xFFFF, sum = 0
3016 01:18:55.344649 9, 0xFFFF, sum = 0
3017 01:18:55.347367 10, 0xFFFF, sum = 0
3018 01:18:55.347826 11, 0xFFFF, sum = 0
3019 01:18:55.350428 12, 0x0, sum = 1
3020 01:18:55.350882 13, 0x0, sum = 2
3021 01:18:55.354038 14, 0x0, sum = 3
3022 01:18:55.354632 15, 0x0, sum = 4
3023 01:18:55.355065 best_step = 13
3024 01:18:55.357138
3025 01:18:55.357621 ==
3026 01:18:55.360552 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 01:18:55.363972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 01:18:55.364529 ==
3029 01:18:55.364888 RX Vref Scan: 0
3030 01:18:55.365222
3031 01:18:55.367027 RX Vref 0 -> 0, step: 1
3032 01:18:55.367480
3033 01:18:55.370905 RX Delay -29 -> 252, step: 4
3034 01:18:55.373774 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3035 01:18:55.380563 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3036 01:18:55.383868 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3037 01:18:55.386953 iDelay=195, Bit 3, Center 110 (39 ~ 182) 144
3038 01:18:55.391130 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3039 01:18:55.393987 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3040 01:18:55.400681 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3041 01:18:55.404165 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3042 01:18:55.407579 iDelay=195, Bit 8, Center 92 (23 ~ 162) 140
3043 01:18:55.410314 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3044 01:18:55.414213 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3045 01:18:55.420732 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3046 01:18:55.423804 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3047 01:18:55.426965 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3048 01:18:55.430458 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3049 01:18:55.433601 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3050 01:18:55.437289 ==
3051 01:18:55.440648 Dram Type= 6, Freq= 0, CH_0, rank 1
3052 01:18:55.443307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 01:18:55.443771 ==
3054 01:18:55.444137 DQS Delay:
3055 01:18:55.446617 DQS0 = 0, DQS1 = 0
3056 01:18:55.447077 DQM Delay:
3057 01:18:55.450215 DQM0 = 111, DQM1 = 102
3058 01:18:55.450673 DQ Delay:
3059 01:18:55.453777 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =110
3060 01:18:55.456687 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =118
3061 01:18:55.460094 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
3062 01:18:55.463450 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =110
3063 01:18:55.464019
3064 01:18:55.464387
3065 01:18:55.473691 [DQSOSCAuto] RK1, (LSB)MR18= 0x11fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3066 01:18:55.474159 CH0 RK1: MR19=403, MR18=11FA
3067 01:18:55.480489 CH0_RK1: MR19=0x403, MR18=0x11FA, DQSOSC=403, MR23=63, INC=40, DEC=26
3068 01:18:55.483616 [RxdqsGatingPostProcess] freq 1200
3069 01:18:55.490324 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3070 01:18:55.493621 best DQS0 dly(2T, 0.5T) = (0, 11)
3071 01:18:55.496711 best DQS1 dly(2T, 0.5T) = (0, 12)
3072 01:18:55.500532 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3073 01:18:55.503210 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3074 01:18:55.506550 best DQS0 dly(2T, 0.5T) = (0, 11)
3075 01:18:55.509877 best DQS1 dly(2T, 0.5T) = (0, 12)
3076 01:18:55.510339 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3077 01:18:55.513325 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3078 01:18:55.516927 Pre-setting of DQS Precalculation
3079 01:18:55.523325 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3080 01:18:55.523889 ==
3081 01:18:55.526703 Dram Type= 6, Freq= 0, CH_1, rank 0
3082 01:18:55.529868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 01:18:55.530438 ==
3084 01:18:55.536804 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3085 01:18:55.543029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3086 01:18:55.550229 [CA 0] Center 37 (8~67) winsize 60
3087 01:18:55.553465 [CA 1] Center 37 (7~68) winsize 62
3088 01:18:55.557147 [CA 2] Center 34 (4~64) winsize 61
3089 01:18:55.560420 [CA 3] Center 34 (4~64) winsize 61
3090 01:18:55.563721 [CA 4] Center 34 (4~64) winsize 61
3091 01:18:55.566979 [CA 5] Center 33 (3~63) winsize 61
3092 01:18:55.567444
3093 01:18:55.570223 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3094 01:18:55.570792
3095 01:18:55.574002 [CATrainingPosCal] consider 1 rank data
3096 01:18:55.576792 u2DelayCellTimex100 = 270/100 ps
3097 01:18:55.580566 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3098 01:18:55.583686 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3099 01:18:55.590231 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3100 01:18:55.593693 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3101 01:18:55.596823 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3102 01:18:55.600370 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3103 01:18:55.600940
3104 01:18:55.603461 CA PerBit enable=1, Macro0, CA PI delay=33
3105 01:18:55.604010
3106 01:18:55.607192 [CBTSetCACLKResult] CA Dly = 33
3107 01:18:55.607747 CS Dly: 5 (0~36)
3108 01:18:55.609989 ==
3109 01:18:55.613882 Dram Type= 6, Freq= 0, CH_1, rank 1
3110 01:18:55.617230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 01:18:55.617835 ==
3112 01:18:55.620293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3113 01:18:55.626915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3114 01:18:55.635892 [CA 0] Center 37 (7~67) winsize 61
3115 01:18:55.639425 [CA 1] Center 37 (7~68) winsize 62
3116 01:18:55.643002 [CA 2] Center 34 (4~65) winsize 62
3117 01:18:55.646280 [CA 3] Center 33 (3~64) winsize 62
3118 01:18:55.649263 [CA 4] Center 34 (4~65) winsize 62
3119 01:18:55.652320 [CA 5] Center 33 (3~63) winsize 61
3120 01:18:55.652769
3121 01:18:55.656054 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3122 01:18:55.656511
3123 01:18:55.659620 [CATrainingPosCal] consider 2 rank data
3124 01:18:55.662467 u2DelayCellTimex100 = 270/100 ps
3125 01:18:55.665920 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3126 01:18:55.669287 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3127 01:18:55.676269 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3128 01:18:55.679503 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3129 01:18:55.682716 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3130 01:18:55.686342 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3131 01:18:55.686901
3132 01:18:55.689074 CA PerBit enable=1, Macro0, CA PI delay=33
3133 01:18:55.689568
3134 01:18:55.692740 [CBTSetCACLKResult] CA Dly = 33
3135 01:18:55.693326 CS Dly: 7 (0~40)
3136 01:18:55.693760
3137 01:18:55.695961 ----->DramcWriteLeveling(PI) begin...
3138 01:18:55.699311 ==
3139 01:18:55.699881 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 01:18:55.705981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 01:18:55.706542 ==
3142 01:18:55.709645 Write leveling (Byte 0): 26 => 26
3143 01:18:55.712519 Write leveling (Byte 1): 27 => 27
3144 01:18:55.716238 DramcWriteLeveling(PI) end<-----
3145 01:18:55.716790
3146 01:18:55.717150 ==
3147 01:18:55.719634 Dram Type= 6, Freq= 0, CH_1, rank 0
3148 01:18:55.722506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3149 01:18:55.723064 ==
3150 01:18:55.725906 [Gating] SW mode calibration
3151 01:18:55.733086 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3152 01:18:55.735741 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3153 01:18:55.742305 0 15 0 | B1->B0 | 3030 2827 | 1 1 | (1 1) (1 1)
3154 01:18:55.745919 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 01:18:55.749124 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3156 01:18:55.755416 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3157 01:18:55.759310 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 01:18:55.762553 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3159 01:18:55.769163 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 01:18:55.772327 0 15 28 | B1->B0 | 2e2e 3131 | 1 1 | (1 0) (1 0)
3161 01:18:55.775675 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 01:18:55.782413 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 01:18:55.785890 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 01:18:55.789059 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 01:18:55.795600 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 01:18:55.798847 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 01:18:55.802009 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3168 01:18:55.809125 1 0 28 | B1->B0 | 3939 3434 | 1 1 | (1 1) (0 0)
3169 01:18:55.812327 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 01:18:55.815417 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 01:18:55.822183 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 01:18:55.825300 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 01:18:55.828615 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 01:18:55.835707 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 01:18:55.838953 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 01:18:55.842521 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3177 01:18:55.848926 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 01:18:55.852263 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 01:18:55.855392 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 01:18:55.858480 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 01:18:55.865478 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 01:18:55.868580 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 01:18:55.871999 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 01:18:55.878815 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 01:18:55.881872 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 01:18:55.885717 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 01:18:55.892074 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 01:18:55.895484 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 01:18:55.898781 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 01:18:55.905490 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 01:18:55.908886 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 01:18:55.912319 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3193 01:18:55.918710 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3194 01:18:55.919265 Total UI for P1: 0, mck2ui 16
3195 01:18:55.925419 best dqsien dly found for B1: ( 1, 3, 28)
3196 01:18:55.928830 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 01:18:55.932028 Total UI for P1: 0, mck2ui 16
3198 01:18:55.935333 best dqsien dly found for B0: ( 1, 3, 30)
3199 01:18:55.939176 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3200 01:18:55.942413 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3201 01:18:55.942985
3202 01:18:55.945752 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3203 01:18:55.948838 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3204 01:18:55.952052 [Gating] SW calibration Done
3205 01:18:55.952605 ==
3206 01:18:55.955531 Dram Type= 6, Freq= 0, CH_1, rank 0
3207 01:18:55.958936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3208 01:18:55.959405 ==
3209 01:18:55.962071 RX Vref Scan: 0
3210 01:18:55.962527
3211 01:18:55.965446 RX Vref 0 -> 0, step: 1
3212 01:18:55.966054
3213 01:18:55.966416 RX Delay -40 -> 252, step: 8
3214 01:18:55.972144 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3215 01:18:55.975507 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3216 01:18:55.978776 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3217 01:18:55.982156 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3218 01:18:55.985711 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3219 01:18:55.992120 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3220 01:18:55.995671 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3221 01:18:55.998706 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3222 01:18:56.002419 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3223 01:18:56.005435 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3224 01:18:56.011970 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3225 01:18:56.015572 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3226 01:18:56.018946 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3227 01:18:56.021930 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3228 01:18:56.025345 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3229 01:18:56.031993 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3230 01:18:56.032547 ==
3231 01:18:56.035129 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 01:18:56.038855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 01:18:56.039319 ==
3234 01:18:56.039686 DQS Delay:
3235 01:18:56.041910 DQS0 = 0, DQS1 = 0
3236 01:18:56.042368 DQM Delay:
3237 01:18:56.045632 DQM0 = 113, DQM1 = 106
3238 01:18:56.046201 DQ Delay:
3239 01:18:56.048566 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =115
3240 01:18:56.052229 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3241 01:18:56.054996 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3242 01:18:56.058920 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3243 01:18:56.059384
3244 01:18:56.059746
3245 01:18:56.060085 ==
3246 01:18:56.062119 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 01:18:56.068529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 01:18:56.069094 ==
3249 01:18:56.069462
3250 01:18:56.069862
3251 01:18:56.070203 TX Vref Scan disable
3252 01:18:56.072427 == TX Byte 0 ==
3253 01:18:56.075785 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3254 01:18:56.079106 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3255 01:18:56.082685 == TX Byte 1 ==
3256 01:18:56.086158 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3257 01:18:56.088994 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3258 01:18:56.092547 ==
3259 01:18:56.095943 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 01:18:56.099024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 01:18:56.099491 ==
3262 01:18:56.110466 TX Vref=22, minBit 11, minWin=23, winSum=402
3263 01:18:56.113204 TX Vref=24, minBit 8, minWin=24, winSum=407
3264 01:18:56.116978 TX Vref=26, minBit 10, minWin=24, winSum=418
3265 01:18:56.119849 TX Vref=28, minBit 9, minWin=25, winSum=419
3266 01:18:56.123579 TX Vref=30, minBit 9, minWin=24, winSum=417
3267 01:18:56.130399 TX Vref=32, minBit 9, minWin=24, winSum=418
3268 01:18:56.133480 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 28
3269 01:18:56.134093
3270 01:18:56.136880 Final TX Range 1 Vref 28
3271 01:18:56.137447
3272 01:18:56.137878 ==
3273 01:18:56.140091 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 01:18:56.143415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 01:18:56.146674 ==
3276 01:18:56.147235
3277 01:18:56.147602
3278 01:18:56.147944 TX Vref Scan disable
3279 01:18:56.149812 == TX Byte 0 ==
3280 01:18:56.153488 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3281 01:18:56.160375 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3282 01:18:56.160943 == TX Byte 1 ==
3283 01:18:56.163571 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3284 01:18:56.166840 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3285 01:18:56.170422
3286 01:18:56.170983 [DATLAT]
3287 01:18:56.171349 Freq=1200, CH1 RK0
3288 01:18:56.171691
3289 01:18:56.173174 DATLAT Default: 0xd
3290 01:18:56.173655 0, 0xFFFF, sum = 0
3291 01:18:56.177293 1, 0xFFFF, sum = 0
3292 01:18:56.177929 2, 0xFFFF, sum = 0
3293 01:18:56.179892 3, 0xFFFF, sum = 0
3294 01:18:56.183654 4, 0xFFFF, sum = 0
3295 01:18:56.184116 5, 0xFFFF, sum = 0
3296 01:18:56.186529 6, 0xFFFF, sum = 0
3297 01:18:56.186994 7, 0xFFFF, sum = 0
3298 01:18:56.189708 8, 0xFFFF, sum = 0
3299 01:18:56.190174 9, 0xFFFF, sum = 0
3300 01:18:56.193550 10, 0xFFFF, sum = 0
3301 01:18:56.194015 11, 0xFFFF, sum = 0
3302 01:18:56.196315 12, 0x0, sum = 1
3303 01:18:56.196778 13, 0x0, sum = 2
3304 01:18:56.199900 14, 0x0, sum = 3
3305 01:18:56.200605 15, 0x0, sum = 4
3306 01:18:56.200989 best_step = 13
3307 01:18:56.203187
3308 01:18:56.203640 ==
3309 01:18:56.206537 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 01:18:56.209898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 01:18:56.210458 ==
3312 01:18:56.210824 RX Vref Scan: 1
3313 01:18:56.211163
3314 01:18:56.213008 Set Vref Range= 32 -> 127
3315 01:18:56.213644
3316 01:18:56.216828 RX Vref 32 -> 127, step: 1
3317 01:18:56.217383
3318 01:18:56.220177 RX Delay -21 -> 252, step: 4
3319 01:18:56.220735
3320 01:18:56.223242 Set Vref, RX VrefLevel [Byte0]: 32
3321 01:18:56.226993 [Byte1]: 32
3322 01:18:56.227753
3323 01:18:56.229870 Set Vref, RX VrefLevel [Byte0]: 33
3324 01:18:56.233279 [Byte1]: 33
3325 01:18:56.236301
3326 01:18:56.236751 Set Vref, RX VrefLevel [Byte0]: 34
3327 01:18:56.239864 [Byte1]: 34
3328 01:18:56.244265
3329 01:18:56.244718 Set Vref, RX VrefLevel [Byte0]: 35
3330 01:18:56.247677 [Byte1]: 35
3331 01:18:56.252460
3332 01:18:56.253025 Set Vref, RX VrefLevel [Byte0]: 36
3333 01:18:56.255550 [Byte1]: 36
3334 01:18:56.260531
3335 01:18:56.261086 Set Vref, RX VrefLevel [Byte0]: 37
3336 01:18:56.263503 [Byte1]: 37
3337 01:18:56.268401
3338 01:18:56.268957 Set Vref, RX VrefLevel [Byte0]: 38
3339 01:18:56.271414 [Byte1]: 38
3340 01:18:56.276220
3341 01:18:56.276779 Set Vref, RX VrefLevel [Byte0]: 39
3342 01:18:56.279656 [Byte1]: 39
3343 01:18:56.284324
3344 01:18:56.284888 Set Vref, RX VrefLevel [Byte0]: 40
3345 01:18:56.287397 [Byte1]: 40
3346 01:18:56.291893
3347 01:18:56.292446 Set Vref, RX VrefLevel [Byte0]: 41
3348 01:18:56.295318 [Byte1]: 41
3349 01:18:56.300148
3350 01:18:56.300707 Set Vref, RX VrefLevel [Byte0]: 42
3351 01:18:56.303405 [Byte1]: 42
3352 01:18:56.308210
3353 01:18:56.308763 Set Vref, RX VrefLevel [Byte0]: 43
3354 01:18:56.311544 [Byte1]: 43
3355 01:18:56.316097
3356 01:18:56.316653 Set Vref, RX VrefLevel [Byte0]: 44
3357 01:18:56.319295 [Byte1]: 44
3358 01:18:56.323989
3359 01:18:56.324550 Set Vref, RX VrefLevel [Byte0]: 45
3360 01:18:56.326891 [Byte1]: 45
3361 01:18:56.331653
3362 01:18:56.332181 Set Vref, RX VrefLevel [Byte0]: 46
3363 01:18:56.334791 [Byte1]: 46
3364 01:18:56.339946
3365 01:18:56.340504 Set Vref, RX VrefLevel [Byte0]: 47
3366 01:18:56.342630 [Byte1]: 47
3367 01:18:56.348095
3368 01:18:56.348733 Set Vref, RX VrefLevel [Byte0]: 48
3369 01:18:56.350841 [Byte1]: 48
3370 01:18:56.355214
3371 01:18:56.355702 Set Vref, RX VrefLevel [Byte0]: 49
3372 01:18:56.358840 [Byte1]: 49
3373 01:18:56.363006
3374 01:18:56.363463 Set Vref, RX VrefLevel [Byte0]: 50
3375 01:18:56.366547 [Byte1]: 50
3376 01:18:56.371198
3377 01:18:56.371748 Set Vref, RX VrefLevel [Byte0]: 51
3378 01:18:56.374169 [Byte1]: 51
3379 01:18:56.379174
3380 01:18:56.379726 Set Vref, RX VrefLevel [Byte0]: 52
3381 01:18:56.382320 [Byte1]: 52
3382 01:18:56.386964
3383 01:18:56.387519 Set Vref, RX VrefLevel [Byte0]: 53
3384 01:18:56.390339 [Byte1]: 53
3385 01:18:56.395170
3386 01:18:56.395733 Set Vref, RX VrefLevel [Byte0]: 54
3387 01:18:56.398639 [Byte1]: 54
3388 01:18:56.403172
3389 01:18:56.403740 Set Vref, RX VrefLevel [Byte0]: 55
3390 01:18:56.406199 [Byte1]: 55
3391 01:18:56.411022
3392 01:18:56.411578 Set Vref, RX VrefLevel [Byte0]: 56
3393 01:18:56.414234 [Byte1]: 56
3394 01:18:56.418766
3395 01:18:56.419320 Set Vref, RX VrefLevel [Byte0]: 57
3396 01:18:56.421982 [Byte1]: 57
3397 01:18:56.426662
3398 01:18:56.427212 Set Vref, RX VrefLevel [Byte0]: 58
3399 01:18:56.429780 [Byte1]: 58
3400 01:18:56.434659
3401 01:18:56.435215 Set Vref, RX VrefLevel [Byte0]: 59
3402 01:18:56.437901 [Byte1]: 59
3403 01:18:56.442765
3404 01:18:56.443315 Set Vref, RX VrefLevel [Byte0]: 60
3405 01:18:56.446170 [Byte1]: 60
3406 01:18:56.450361
3407 01:18:56.450833 Set Vref, RX VrefLevel [Byte0]: 61
3408 01:18:56.453876 [Byte1]: 61
3409 01:18:56.458021
3410 01:18:56.458476 Set Vref, RX VrefLevel [Byte0]: 62
3411 01:18:56.461922 [Byte1]: 62
3412 01:18:56.466210
3413 01:18:56.466775 Set Vref, RX VrefLevel [Byte0]: 63
3414 01:18:56.469334 [Byte1]: 63
3415 01:18:56.473962
3416 01:18:56.474421 Set Vref, RX VrefLevel [Byte0]: 64
3417 01:18:56.478078 [Byte1]: 64
3418 01:18:56.481982
3419 01:18:56.482540 Set Vref, RX VrefLevel [Byte0]: 65
3420 01:18:56.485402 [Byte1]: 65
3421 01:18:56.490483
3422 01:18:56.491047 Set Vref, RX VrefLevel [Byte0]: 66
3423 01:18:56.493607 [Byte1]: 66
3424 01:18:56.498308
3425 01:18:56.498868 Set Vref, RX VrefLevel [Byte0]: 67
3426 01:18:56.501467 [Byte1]: 67
3427 01:18:56.505616
3428 01:18:56.506080 Set Vref, RX VrefLevel [Byte0]: 68
3429 01:18:56.509117 [Byte1]: 68
3430 01:18:56.513501
3431 01:18:56.514000 Final RX Vref Byte 0 = 55 to rank0
3432 01:18:56.517670 Final RX Vref Byte 1 = 47 to rank0
3433 01:18:56.520210 Final RX Vref Byte 0 = 55 to rank1
3434 01:18:56.524356 Final RX Vref Byte 1 = 47 to rank1==
3435 01:18:56.527474 Dram Type= 6, Freq= 0, CH_1, rank 0
3436 01:18:56.533551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 01:18:56.534116 ==
3438 01:18:56.534482 DQS Delay:
3439 01:18:56.534825 DQS0 = 0, DQS1 = 0
3440 01:18:56.537060 DQM Delay:
3441 01:18:56.537557 DQM0 = 114, DQM1 = 105
3442 01:18:56.540475 DQ Delay:
3443 01:18:56.543958 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =110
3444 01:18:56.546998 DQ4 =112, DQ5 =122, DQ6 =128, DQ7 =110
3445 01:18:56.550646 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =100
3446 01:18:56.553450 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3447 01:18:56.554010
3448 01:18:56.554379
3449 01:18:56.560720 [DQSOSCAuto] RK0, (LSB)MR18= 0xedf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
3450 01:18:56.563491 CH1 RK0: MR19=303, MR18=EDF4
3451 01:18:56.570324 CH1_RK0: MR19=0x303, MR18=0xEDF4, DQSOSC=415, MR23=63, INC=38, DEC=25
3452 01:18:56.570893
3453 01:18:56.573563 ----->DramcWriteLeveling(PI) begin...
3454 01:18:56.574039 ==
3455 01:18:56.576936 Dram Type= 6, Freq= 0, CH_1, rank 1
3456 01:18:56.580572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3457 01:18:56.583913 ==
3458 01:18:56.584481 Write leveling (Byte 0): 23 => 23
3459 01:18:56.587195 Write leveling (Byte 1): 27 => 27
3460 01:18:56.590155 DramcWriteLeveling(PI) end<-----
3461 01:18:56.590616
3462 01:18:56.590978 ==
3463 01:18:56.593710 Dram Type= 6, Freq= 0, CH_1, rank 1
3464 01:18:56.600487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 01:18:56.601058 ==
3466 01:18:56.601429 [Gating] SW mode calibration
3467 01:18:56.610312 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3468 01:18:56.614061 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3469 01:18:56.617887 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 01:18:56.623857 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 01:18:56.627413 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 01:18:56.630668 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 01:18:56.636718 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 01:18:56.640624 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3475 01:18:56.643773 0 15 24 | B1->B0 | 3434 2727 | 1 1 | (1 0) (1 0)
3476 01:18:56.650448 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
3477 01:18:56.653592 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 01:18:56.656975 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 01:18:56.663735 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 01:18:56.667306 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 01:18:56.670134 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 01:18:56.677139 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3483 01:18:56.679873 1 0 24 | B1->B0 | 2929 4545 | 1 0 | (0 0) (0 0)
3484 01:18:56.683017 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 01:18:56.689588 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 01:18:56.693451 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 01:18:56.696236 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 01:18:56.703257 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 01:18:56.706642 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 01:18:56.710084 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 01:18:56.716426 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 01:18:56.719660 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3493 01:18:56.722926 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 01:18:56.729592 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 01:18:56.733264 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 01:18:56.736543 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 01:18:56.742932 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 01:18:56.746035 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 01:18:56.749895 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 01:18:56.756669 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 01:18:56.759225 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 01:18:56.762772 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 01:18:56.769808 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 01:18:56.772998 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 01:18:56.776146 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 01:18:56.782406 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 01:18:56.786414 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3508 01:18:56.789117 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3509 01:18:56.792176 Total UI for P1: 0, mck2ui 16
3510 01:18:56.795647 best dqsien dly found for B0: ( 1, 3, 24)
3511 01:18:56.802391 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 01:18:56.802959 Total UI for P1: 0, mck2ui 16
3513 01:18:56.809542 best dqsien dly found for B1: ( 1, 3, 26)
3514 01:18:56.812663 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3515 01:18:56.815382 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3516 01:18:56.815846
3517 01:18:56.818995 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3518 01:18:56.822055 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3519 01:18:56.825371 [Gating] SW calibration Done
3520 01:18:56.825874 ==
3521 01:18:56.829176 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 01:18:56.832284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 01:18:56.832852 ==
3524 01:18:56.835481 RX Vref Scan: 0
3525 01:18:56.835943
3526 01:18:56.836307 RX Vref 0 -> 0, step: 1
3527 01:18:56.836643
3528 01:18:56.838347 RX Delay -40 -> 252, step: 8
3529 01:18:56.842123 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3530 01:18:56.848862 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3531 01:18:56.851687 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3532 01:18:56.855176 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3533 01:18:56.858429 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3534 01:18:56.861660 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3535 01:18:56.868252 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3536 01:18:56.871947 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3537 01:18:56.874690 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3538 01:18:56.878265 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3539 01:18:56.881787 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3540 01:18:56.888550 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3541 01:18:56.891766 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3542 01:18:56.895185 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3543 01:18:56.898210 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3544 01:18:56.901711 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3545 01:18:56.904722 ==
3546 01:18:56.908047 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 01:18:56.911403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 01:18:56.911868 ==
3549 01:18:56.912232 DQS Delay:
3550 01:18:56.914316 DQS0 = 0, DQS1 = 0
3551 01:18:56.914774 DQM Delay:
3552 01:18:56.917756 DQM0 = 110, DQM1 = 106
3553 01:18:56.918215 DQ Delay:
3554 01:18:56.921223 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3555 01:18:56.924145 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3556 01:18:56.927645 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =95
3557 01:18:56.931167 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =115
3558 01:18:56.931782
3559 01:18:56.932157
3560 01:18:56.932498 ==
3561 01:18:56.934201 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 01:18:56.940587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 01:18:56.941055 ==
3564 01:18:56.941423
3565 01:18:56.941827
3566 01:18:56.942314 TX Vref Scan disable
3567 01:18:56.944212 == TX Byte 0 ==
3568 01:18:56.947773 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3569 01:18:56.954563 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3570 01:18:56.955025 == TX Byte 1 ==
3571 01:18:56.957820 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3572 01:18:56.964299 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3573 01:18:56.964848 ==
3574 01:18:56.967661 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 01:18:56.970991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 01:18:56.971472 ==
3577 01:18:56.982379 TX Vref=22, minBit 8, minWin=25, winSum=419
3578 01:18:56.986221 TX Vref=24, minBit 0, minWin=25, winSum=423
3579 01:18:56.989270 TX Vref=26, minBit 0, minWin=25, winSum=428
3580 01:18:56.992726 TX Vref=28, minBit 9, minWin=26, winSum=432
3581 01:18:56.995824 TX Vref=30, minBit 9, minWin=26, winSum=432
3582 01:18:57.002393 TX Vref=32, minBit 8, minWin=26, winSum=430
3583 01:18:57.005618 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28
3584 01:18:57.006081
3585 01:18:57.008923 Final TX Range 1 Vref 28
3586 01:18:57.009382
3587 01:18:57.009789 ==
3588 01:18:57.012438 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 01:18:57.015682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 01:18:57.016141 ==
3591 01:18:57.019308
3592 01:18:57.019861
3593 01:18:57.020226 TX Vref Scan disable
3594 01:18:57.022336 == TX Byte 0 ==
3595 01:18:57.025738 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3596 01:18:57.032628 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3597 01:18:57.033184 == TX Byte 1 ==
3598 01:18:57.035418 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3599 01:18:57.041976 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3600 01:18:57.042433
3601 01:18:57.042794 [DATLAT]
3602 01:18:57.043381 Freq=1200, CH1 RK1
3603 01:18:57.043761
3604 01:18:57.045107 DATLAT Default: 0xd
3605 01:18:57.045633 0, 0xFFFF, sum = 0
3606 01:18:57.048451 1, 0xFFFF, sum = 0
3607 01:18:57.051926 2, 0xFFFF, sum = 0
3608 01:18:57.052627 3, 0xFFFF, sum = 0
3609 01:18:57.055247 4, 0xFFFF, sum = 0
3610 01:18:57.055714 5, 0xFFFF, sum = 0
3611 01:18:57.058756 6, 0xFFFF, sum = 0
3612 01:18:57.059604 7, 0xFFFF, sum = 0
3613 01:18:57.062179 8, 0xFFFF, sum = 0
3614 01:18:57.062886 9, 0xFFFF, sum = 0
3615 01:18:57.064954 10, 0xFFFF, sum = 0
3616 01:18:57.065772 11, 0xFFFF, sum = 0
3617 01:18:57.068056 12, 0x0, sum = 1
3618 01:18:57.068560 13, 0x0, sum = 2
3619 01:18:57.071804 14, 0x0, sum = 3
3620 01:18:57.072273 15, 0x0, sum = 4
3621 01:18:57.075048 best_step = 13
3622 01:18:57.075549
3623 01:18:57.075917 ==
3624 01:18:57.078181 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 01:18:57.081656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 01:18:57.082221 ==
3627 01:18:57.082733 RX Vref Scan: 0
3628 01:18:57.085043
3629 01:18:57.085604 RX Vref 0 -> 0, step: 1
3630 01:18:57.085954
3631 01:18:57.088322 RX Delay -21 -> 252, step: 4
3632 01:18:57.095169 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3633 01:18:57.098515 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3634 01:18:57.101776 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3635 01:18:57.104756 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3636 01:18:57.108331 iDelay=195, Bit 4, Center 108 (35 ~ 182) 148
3637 01:18:57.115070 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3638 01:18:57.118545 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3639 01:18:57.121465 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3640 01:18:57.125222 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3641 01:18:57.128584 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3642 01:18:57.135070 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3643 01:18:57.137911 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3644 01:18:57.141568 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3645 01:18:57.144966 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3646 01:18:57.148172 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3647 01:18:57.154694 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3648 01:18:57.155163 ==
3649 01:18:57.157991 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 01:18:57.161357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 01:18:57.161862 ==
3652 01:18:57.162230 DQS Delay:
3653 01:18:57.164502 DQS0 = 0, DQS1 = 0
3654 01:18:57.164957 DQM Delay:
3655 01:18:57.167835 DQM0 = 111, DQM1 = 108
3656 01:18:57.168291 DQ Delay:
3657 01:18:57.171436 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3658 01:18:57.174935 DQ4 =108, DQ5 =122, DQ6 =122, DQ7 =108
3659 01:18:57.177913 DQ8 =94, DQ9 =100, DQ10 =110, DQ11 =100
3660 01:18:57.181141 DQ12 =116, DQ13 =114, DQ14 =114, DQ15 =116
3661 01:18:57.181882
3662 01:18:57.185051
3663 01:18:57.191159 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa09, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3664 01:18:57.194145 CH1 RK1: MR19=304, MR18=FA09
3665 01:18:57.201205 CH1_RK1: MR19=0x304, MR18=0xFA09, DQSOSC=406, MR23=63, INC=39, DEC=26
3666 01:18:57.204405 [RxdqsGatingPostProcess] freq 1200
3667 01:18:57.207812 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3668 01:18:57.211189 best DQS0 dly(2T, 0.5T) = (0, 11)
3669 01:18:57.214194 best DQS1 dly(2T, 0.5T) = (0, 11)
3670 01:18:57.217399 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3671 01:18:57.221258 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3672 01:18:57.224325 best DQS0 dly(2T, 0.5T) = (0, 11)
3673 01:18:57.227457 best DQS1 dly(2T, 0.5T) = (0, 11)
3674 01:18:57.231120 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3675 01:18:57.234108 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3676 01:18:57.237487 Pre-setting of DQS Precalculation
3677 01:18:57.241186 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3678 01:18:57.247904 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3679 01:18:57.257737 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3680 01:18:57.258282
3681 01:18:57.258642
3682 01:18:57.260759 [Calibration Summary] 2400 Mbps
3683 01:18:57.261214 CH 0, Rank 0
3684 01:18:57.264020 SW Impedance : PASS
3685 01:18:57.264494 DUTY Scan : NO K
3686 01:18:57.267433 ZQ Calibration : PASS
3687 01:18:57.268004 Jitter Meter : NO K
3688 01:18:57.270315 CBT Training : PASS
3689 01:18:57.273553 Write leveling : PASS
3690 01:18:57.274040 RX DQS gating : PASS
3691 01:18:57.277111 RX DQ/DQS(RDDQC) : PASS
3692 01:18:57.280710 TX DQ/DQS : PASS
3693 01:18:57.281440 RX DATLAT : PASS
3694 01:18:57.283832 RX DQ/DQS(Engine): PASS
3695 01:18:57.287190 TX OE : NO K
3696 01:18:57.287649 All Pass.
3697 01:18:57.288008
3698 01:18:57.288341 CH 0, Rank 1
3699 01:18:57.290119 SW Impedance : PASS
3700 01:18:57.293404 DUTY Scan : NO K
3701 01:18:57.293917 ZQ Calibration : PASS
3702 01:18:57.297097 Jitter Meter : NO K
3703 01:18:57.300388 CBT Training : PASS
3704 01:18:57.300938 Write leveling : PASS
3705 01:18:57.303832 RX DQS gating : PASS
3706 01:18:57.306763 RX DQ/DQS(RDDQC) : PASS
3707 01:18:57.307219 TX DQ/DQS : PASS
3708 01:18:57.309898 RX DATLAT : PASS
3709 01:18:57.314005 RX DQ/DQS(Engine): PASS
3710 01:18:57.314553 TX OE : NO K
3711 01:18:57.316729 All Pass.
3712 01:18:57.317184
3713 01:18:57.317565 CH 1, Rank 0
3714 01:18:57.320173 SW Impedance : PASS
3715 01:18:57.320629 DUTY Scan : NO K
3716 01:18:57.323440 ZQ Calibration : PASS
3717 01:18:57.326947 Jitter Meter : NO K
3718 01:18:57.327496 CBT Training : PASS
3719 01:18:57.330186 Write leveling : PASS
3720 01:18:57.333570 RX DQS gating : PASS
3721 01:18:57.334127 RX DQ/DQS(RDDQC) : PASS
3722 01:18:57.336914 TX DQ/DQS : PASS
3723 01:18:57.340199 RX DATLAT : PASS
3724 01:18:57.340761 RX DQ/DQS(Engine): PASS
3725 01:18:57.343164 TX OE : NO K
3726 01:18:57.343621 All Pass.
3727 01:18:57.343976
3728 01:18:57.346676 CH 1, Rank 1
3729 01:18:57.347225 SW Impedance : PASS
3730 01:18:57.350025 DUTY Scan : NO K
3731 01:18:57.350533 ZQ Calibration : PASS
3732 01:18:57.352784 Jitter Meter : NO K
3733 01:18:57.356311 CBT Training : PASS
3734 01:18:57.356768 Write leveling : PASS
3735 01:18:57.359704 RX DQS gating : PASS
3736 01:18:57.362908 RX DQ/DQS(RDDQC) : PASS
3737 01:18:57.363363 TX DQ/DQS : PASS
3738 01:18:57.365885 RX DATLAT : PASS
3739 01:18:57.369600 RX DQ/DQS(Engine): PASS
3740 01:18:57.370059 TX OE : NO K
3741 01:18:57.372739 All Pass.
3742 01:18:57.373194
3743 01:18:57.373585 DramC Write-DBI off
3744 01:18:57.375932 PER_BANK_REFRESH: Hybrid Mode
3745 01:18:57.379209 TX_TRACKING: ON
3746 01:18:57.385836 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3747 01:18:57.389155 [FAST_K] Save calibration result to emmc
3748 01:18:57.392587 dramc_set_vcore_voltage set vcore to 650000
3749 01:18:57.396120 Read voltage for 600, 5
3750 01:18:57.396630 Vio18 = 0
3751 01:18:57.399578 Vcore = 650000
3752 01:18:57.400090 Vdram = 0
3753 01:18:57.400422 Vddq = 0
3754 01:18:57.402181 Vmddr = 0
3755 01:18:57.405627 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3756 01:18:57.412398 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3757 01:18:57.412817 MEM_TYPE=3, freq_sel=19
3758 01:18:57.415498 sv_algorithm_assistance_LP4_1600
3759 01:18:57.422123 ============ PULL DRAM RESETB DOWN ============
3760 01:18:57.425712 ========== PULL DRAM RESETB DOWN end =========
3761 01:18:57.429277 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3762 01:18:57.432489 ===================================
3763 01:18:57.435778 LPDDR4 DRAM CONFIGURATION
3764 01:18:57.438985 ===================================
3765 01:18:57.442064 EX_ROW_EN[0] = 0x0
3766 01:18:57.442579 EX_ROW_EN[1] = 0x0
3767 01:18:57.445403 LP4Y_EN = 0x0
3768 01:18:57.445854 WORK_FSP = 0x0
3769 01:18:57.448859 WL = 0x2
3770 01:18:57.449271 RL = 0x2
3771 01:18:57.451660 BL = 0x2
3772 01:18:57.452073 RPST = 0x0
3773 01:18:57.455169 RD_PRE = 0x0
3774 01:18:57.455584 WR_PRE = 0x1
3775 01:18:57.458395 WR_PST = 0x0
3776 01:18:57.458807 DBI_WR = 0x0
3777 01:18:57.461847 DBI_RD = 0x0
3778 01:18:57.465316 OTF = 0x1
3779 01:18:57.465868 ===================================
3780 01:18:57.468815 ===================================
3781 01:18:57.471854 ANA top config
3782 01:18:57.475200 ===================================
3783 01:18:57.478165 DLL_ASYNC_EN = 0
3784 01:18:57.478579 ALL_SLAVE_EN = 1
3785 01:18:57.481575 NEW_RANK_MODE = 1
3786 01:18:57.485128 DLL_IDLE_MODE = 1
3787 01:18:57.488341 LP45_APHY_COMB_EN = 1
3788 01:18:57.491489 TX_ODT_DIS = 1
3789 01:18:57.491905 NEW_8X_MODE = 1
3790 01:18:57.495200 ===================================
3791 01:18:57.498451 ===================================
3792 01:18:57.501784 data_rate = 1200
3793 01:18:57.504716 CKR = 1
3794 01:18:57.507881 DQ_P2S_RATIO = 8
3795 01:18:57.511331 ===================================
3796 01:18:57.515119 CA_P2S_RATIO = 8
3797 01:18:57.517963 DQ_CA_OPEN = 0
3798 01:18:57.518382 DQ_SEMI_OPEN = 0
3799 01:18:57.521921 CA_SEMI_OPEN = 0
3800 01:18:57.524420 CA_FULL_RATE = 0
3801 01:18:57.527847 DQ_CKDIV4_EN = 1
3802 01:18:57.531440 CA_CKDIV4_EN = 1
3803 01:18:57.534547 CA_PREDIV_EN = 0
3804 01:18:57.535054 PH8_DLY = 0
3805 01:18:57.537736 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3806 01:18:57.541586 DQ_AAMCK_DIV = 4
3807 01:18:57.544953 CA_AAMCK_DIV = 4
3808 01:18:57.548213 CA_ADMCK_DIV = 4
3809 01:18:57.551499 DQ_TRACK_CA_EN = 0
3810 01:18:57.551918 CA_PICK = 600
3811 01:18:57.554373 CA_MCKIO = 600
3812 01:18:57.557639 MCKIO_SEMI = 0
3813 01:18:57.561003 PLL_FREQ = 2288
3814 01:18:57.564636 DQ_UI_PI_RATIO = 32
3815 01:18:57.567511 CA_UI_PI_RATIO = 0
3816 01:18:57.570722 ===================================
3817 01:18:57.573948 ===================================
3818 01:18:57.577839 memory_type:LPDDR4
3819 01:18:57.578251 GP_NUM : 10
3820 01:18:57.580827 SRAM_EN : 1
3821 01:18:57.581243 MD32_EN : 0
3822 01:18:57.584099 ===================================
3823 01:18:57.587423 [ANA_INIT] >>>>>>>>>>>>>>
3824 01:18:57.590986 <<<<<< [CONFIGURE PHASE]: ANA_TX
3825 01:18:57.594026 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3826 01:18:57.597548 ===================================
3827 01:18:57.600767 data_rate = 1200,PCW = 0X5800
3828 01:18:57.604550 ===================================
3829 01:18:57.607775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3830 01:18:57.611052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3831 01:18:57.617558 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3832 01:18:57.620786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3833 01:18:57.627648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3834 01:18:57.631066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3835 01:18:57.631530 [ANA_INIT] flow start
3836 01:18:57.633825 [ANA_INIT] PLL >>>>>>>>
3837 01:18:57.637560 [ANA_INIT] PLL <<<<<<<<
3838 01:18:57.638124 [ANA_INIT] MIDPI >>>>>>>>
3839 01:18:57.640457 [ANA_INIT] MIDPI <<<<<<<<
3840 01:18:57.643931 [ANA_INIT] DLL >>>>>>>>
3841 01:18:57.644399 [ANA_INIT] flow end
3842 01:18:57.650851 ============ LP4 DIFF to SE enter ============
3843 01:18:57.654075 ============ LP4 DIFF to SE exit ============
3844 01:18:57.656722 [ANA_INIT] <<<<<<<<<<<<<
3845 01:18:57.657179 [Flow] Enable top DCM control >>>>>
3846 01:18:57.660190 [Flow] Enable top DCM control <<<<<
3847 01:18:57.663563 Enable DLL master slave shuffle
3848 01:18:57.669896 ==============================================================
3849 01:18:57.673398 Gating Mode config
3850 01:18:57.677046 ==============================================================
3851 01:18:57.680324 Config description:
3852 01:18:57.690096 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3853 01:18:57.696780 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3854 01:18:57.699938 SELPH_MODE 0: By rank 1: By Phase
3855 01:18:57.706568 ==============================================================
3856 01:18:57.710147 GAT_TRACK_EN = 1
3857 01:18:57.713290 RX_GATING_MODE = 2
3858 01:18:57.716601 RX_GATING_TRACK_MODE = 2
3859 01:18:57.719620 SELPH_MODE = 1
3860 01:18:57.720073 PICG_EARLY_EN = 1
3861 01:18:57.722964 VALID_LAT_VALUE = 1
3862 01:18:57.729820 ==============================================================
3863 01:18:57.732784 Enter into Gating configuration >>>>
3864 01:18:57.736275 Exit from Gating configuration <<<<
3865 01:18:57.739623 Enter into DVFS_PRE_config >>>>>
3866 01:18:57.749304 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3867 01:18:57.752553 Exit from DVFS_PRE_config <<<<<
3868 01:18:57.756074 Enter into PICG configuration >>>>
3869 01:18:57.759336 Exit from PICG configuration <<<<
3870 01:18:57.762165 [RX_INPUT] configuration >>>>>
3871 01:18:57.765681 [RX_INPUT] configuration <<<<<
3872 01:18:57.769130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3873 01:18:57.775267 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3874 01:18:57.782186 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 01:18:57.788442 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 01:18:57.795240 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3877 01:18:57.801732 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3878 01:18:57.805059 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3879 01:18:57.808282 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3880 01:18:57.811679 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3881 01:18:57.818363 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3882 01:18:57.821834 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3883 01:18:57.825081 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3884 01:18:57.828615 ===================================
3885 01:18:57.831785 LPDDR4 DRAM CONFIGURATION
3886 01:18:57.835117 ===================================
3887 01:18:57.835201 EX_ROW_EN[0] = 0x0
3888 01:18:57.838346 EX_ROW_EN[1] = 0x0
3889 01:18:57.838428 LP4Y_EN = 0x0
3890 01:18:57.841906 WORK_FSP = 0x0
3891 01:18:57.844804 WL = 0x2
3892 01:18:57.844889 RL = 0x2
3893 01:18:57.848129 BL = 0x2
3894 01:18:57.848211 RPST = 0x0
3895 01:18:57.851645 RD_PRE = 0x0
3896 01:18:57.851731 WR_PRE = 0x1
3897 01:18:57.854729 WR_PST = 0x0
3898 01:18:57.854814 DBI_WR = 0x0
3899 01:18:57.858342 DBI_RD = 0x0
3900 01:18:57.858436 OTF = 0x1
3901 01:18:57.861601 ===================================
3902 01:18:57.864943 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3903 01:18:57.871866 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3904 01:18:57.874604 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3905 01:18:57.878282 ===================================
3906 01:18:57.881430 LPDDR4 DRAM CONFIGURATION
3907 01:18:57.884827 ===================================
3908 01:18:57.884931 EX_ROW_EN[0] = 0x10
3909 01:18:57.887765 EX_ROW_EN[1] = 0x0
3910 01:18:57.887850 LP4Y_EN = 0x0
3911 01:18:57.891575 WORK_FSP = 0x0
3912 01:18:57.894530 WL = 0x2
3913 01:18:57.894624 RL = 0x2
3914 01:18:57.897674 BL = 0x2
3915 01:18:57.897759 RPST = 0x0
3916 01:18:57.901207 RD_PRE = 0x0
3917 01:18:57.901291 WR_PRE = 0x1
3918 01:18:57.904258 WR_PST = 0x0
3919 01:18:57.904349 DBI_WR = 0x0
3920 01:18:57.907701 DBI_RD = 0x0
3921 01:18:57.907787 OTF = 0x1
3922 01:18:57.911052 ===================================
3923 01:18:57.917911 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3924 01:18:57.922028 nWR fixed to 30
3925 01:18:57.925218 [ModeRegInit_LP4] CH0 RK0
3926 01:18:57.925330 [ModeRegInit_LP4] CH0 RK1
3927 01:18:57.928631 [ModeRegInit_LP4] CH1 RK0
3928 01:18:57.931978 [ModeRegInit_LP4] CH1 RK1
3929 01:18:57.932085 match AC timing 17
3930 01:18:57.938379 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3931 01:18:57.941792 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3932 01:18:57.944962 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3933 01:18:57.951903 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3934 01:18:57.954722 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3935 01:18:57.954835 ==
3936 01:18:57.958109 Dram Type= 6, Freq= 0, CH_0, rank 0
3937 01:18:57.961427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3938 01:18:57.961518 ==
3939 01:18:57.968026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3940 01:18:57.974652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3941 01:18:57.978059 [CA 0] Center 37 (7~67) winsize 61
3942 01:18:57.981234 [CA 1] Center 37 (7~67) winsize 61
3943 01:18:57.984453 [CA 2] Center 35 (5~65) winsize 61
3944 01:18:57.988017 [CA 3] Center 35 (5~65) winsize 61
3945 01:18:57.991268 [CA 4] Center 34 (4~65) winsize 62
3946 01:18:57.994744 [CA 5] Center 34 (4~64) winsize 61
3947 01:18:57.994826
3948 01:18:57.998033 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3949 01:18:57.998121
3950 01:18:58.001425 [CATrainingPosCal] consider 1 rank data
3951 01:18:58.004810 u2DelayCellTimex100 = 270/100 ps
3952 01:18:58.008012 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3953 01:18:58.011205 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3954 01:18:58.014716 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3955 01:18:58.017666 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3956 01:18:58.024559 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3957 01:18:58.027742 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3958 01:18:58.027842
3959 01:18:58.031158 CA PerBit enable=1, Macro0, CA PI delay=34
3960 01:18:58.031267
3961 01:18:58.034075 [CBTSetCACLKResult] CA Dly = 34
3962 01:18:58.034158 CS Dly: 6 (0~37)
3963 01:18:58.034222 ==
3964 01:18:58.037372 Dram Type= 6, Freq= 0, CH_0, rank 1
3965 01:18:58.044285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 01:18:58.044519 ==
3967 01:18:58.047369 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3968 01:18:58.054141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3969 01:18:58.057485 [CA 0] Center 37 (7~67) winsize 61
3970 01:18:58.060739 [CA 1] Center 37 (7~67) winsize 61
3971 01:18:58.064205 [CA 2] Center 35 (5~65) winsize 61
3972 01:18:58.067468 [CA 3] Center 34 (4~65) winsize 62
3973 01:18:58.070925 [CA 4] Center 34 (4~65) winsize 62
3974 01:18:58.073911 [CA 5] Center 33 (3~64) winsize 62
3975 01:18:58.074000
3976 01:18:58.077043 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3977 01:18:58.077145
3978 01:18:58.081065 [CATrainingPosCal] consider 2 rank data
3979 01:18:58.084179 u2DelayCellTimex100 = 270/100 ps
3980 01:18:58.087287 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3981 01:18:58.090632 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3982 01:18:58.097040 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3983 01:18:58.100359 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3984 01:18:58.103706 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3985 01:18:58.106929 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3986 01:18:58.107016
3987 01:18:58.110396 CA PerBit enable=1, Macro0, CA PI delay=34
3988 01:18:58.110520
3989 01:18:58.113883 [CBTSetCACLKResult] CA Dly = 34
3990 01:18:58.113978 CS Dly: 5 (0~36)
3991 01:18:58.114044
3992 01:18:58.117097 ----->DramcWriteLeveling(PI) begin...
3993 01:18:58.120631 ==
3994 01:18:58.123951 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 01:18:58.127045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 01:18:58.127134 ==
3997 01:18:58.130270 Write leveling (Byte 0): 33 => 33
3998 01:18:58.133460 Write leveling (Byte 1): 33 => 33
3999 01:18:58.136521 DramcWriteLeveling(PI) end<-----
4000 01:18:58.136603
4001 01:18:58.136666 ==
4002 01:18:58.140183 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 01:18:58.143373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 01:18:58.143455 ==
4005 01:18:58.146949 [Gating] SW mode calibration
4006 01:18:58.153316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4007 01:18:58.159996 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4008 01:18:58.163052 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 01:18:58.166425 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4010 01:18:58.173251 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4011 01:18:58.176440 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4012 01:18:58.179776 0 9 16 | B1->B0 | 3333 2a2a | 1 0 | (1 0) (1 1)
4013 01:18:58.186364 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 01:18:58.189891 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 01:18:58.192826 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 01:18:58.199496 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 01:18:58.202933 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 01:18:58.206200 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 01:18:58.212959 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4020 01:18:58.216198 0 10 16 | B1->B0 | 2f2f 3f3f | 1 0 | (0 0) (1 1)
4021 01:18:58.219562 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 01:18:58.225906 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 01:18:58.229403 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 01:18:58.232470 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 01:18:58.238972 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 01:18:58.242369 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 01:18:58.245672 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4028 01:18:58.252243 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4029 01:18:58.255646 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 01:18:58.258761 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 01:18:58.265461 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 01:18:58.268308 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 01:18:58.271776 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 01:18:58.278501 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 01:18:58.281872 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 01:18:58.285438 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 01:18:58.291893 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 01:18:58.295322 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 01:18:58.298680 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 01:18:58.304910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 01:18:58.308288 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 01:18:58.311522 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 01:18:58.314980 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4044 01:18:58.321625 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4045 01:18:58.324991 Total UI for P1: 0, mck2ui 16
4046 01:18:58.328332 best dqsien dly found for B0: ( 0, 13, 12)
4047 01:18:58.331306 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 01:18:58.334775 Total UI for P1: 0, mck2ui 16
4049 01:18:58.338144 best dqsien dly found for B1: ( 0, 13, 16)
4050 01:18:58.341245 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4051 01:18:58.344960 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4052 01:18:58.345050
4053 01:18:58.348224 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4054 01:18:58.354663 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4055 01:18:58.354749 [Gating] SW calibration Done
4056 01:18:58.358037 ==
4057 01:18:58.358126 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 01:18:58.364812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 01:18:58.364905 ==
4060 01:18:58.364971 RX Vref Scan: 0
4061 01:18:58.365031
4062 01:18:58.367984 RX Vref 0 -> 0, step: 1
4063 01:18:58.368070
4064 01:18:58.371198 RX Delay -230 -> 252, step: 16
4065 01:18:58.374354 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4066 01:18:58.377496 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4067 01:18:58.384538 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4068 01:18:58.387531 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4069 01:18:58.390792 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4070 01:18:58.393963 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4071 01:18:58.400645 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4072 01:18:58.403943 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4073 01:18:58.407315 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4074 01:18:58.410851 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4075 01:18:58.414186 iDelay=218, Bit 10, Center 25 (-150 ~ 201) 352
4076 01:18:58.421068 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4077 01:18:58.423855 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4078 01:18:58.427227 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4079 01:18:58.433726 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4080 01:18:58.437207 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4081 01:18:58.437296 ==
4082 01:18:58.440291 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 01:18:58.443802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 01:18:58.443885 ==
4085 01:18:58.443950 DQS Delay:
4086 01:18:58.447101 DQS0 = 0, DQS1 = 0
4087 01:18:58.447184 DQM Delay:
4088 01:18:58.450467 DQM0 = 37, DQM1 = 28
4089 01:18:58.450550 DQ Delay:
4090 01:18:58.453720 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4091 01:18:58.456991 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4092 01:18:58.460410 DQ8 =17, DQ9 =17, DQ10 =25, DQ11 =17
4093 01:18:58.463875 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4094 01:18:58.463985
4095 01:18:58.464051
4096 01:18:58.464112 ==
4097 01:18:58.466964 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 01:18:58.473150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 01:18:58.473259 ==
4100 01:18:58.473329
4101 01:18:58.473389
4102 01:18:58.473446 TX Vref Scan disable
4103 01:18:58.476626 == TX Byte 0 ==
4104 01:18:58.480044 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4105 01:18:58.486645 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4106 01:18:58.486742 == TX Byte 1 ==
4107 01:18:58.489747 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4108 01:18:58.496478 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4109 01:18:58.496570 ==
4110 01:18:58.499487 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 01:18:58.503172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 01:18:58.503388 ==
4113 01:18:58.503475
4114 01:18:58.503537
4115 01:18:58.506223 TX Vref Scan disable
4116 01:18:58.509664 == TX Byte 0 ==
4117 01:18:58.513243 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4118 01:18:58.516600 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4119 01:18:58.519488 == TX Byte 1 ==
4120 01:18:58.522747 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4121 01:18:58.526424 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4122 01:18:58.526526
4123 01:18:58.526593 [DATLAT]
4124 01:18:58.529250 Freq=600, CH0 RK0
4125 01:18:58.529336
4126 01:18:58.532570 DATLAT Default: 0x9
4127 01:18:58.532653 0, 0xFFFF, sum = 0
4128 01:18:58.536208 1, 0xFFFF, sum = 0
4129 01:18:58.536293 2, 0xFFFF, sum = 0
4130 01:18:58.539769 3, 0xFFFF, sum = 0
4131 01:18:58.539852 4, 0xFFFF, sum = 0
4132 01:18:58.542927 5, 0xFFFF, sum = 0
4133 01:18:58.543009 6, 0xFFFF, sum = 0
4134 01:18:58.546395 7, 0xFFFF, sum = 0
4135 01:18:58.546478 8, 0x0, sum = 1
4136 01:18:58.549627 9, 0x0, sum = 2
4137 01:18:58.549711 10, 0x0, sum = 3
4138 01:18:58.552481 11, 0x0, sum = 4
4139 01:18:58.552563 best_step = 9
4140 01:18:58.552626
4141 01:18:58.552685 ==
4142 01:18:58.556145 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 01:18:58.559273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 01:18:58.559367 ==
4145 01:18:58.562306 RX Vref Scan: 1
4146 01:18:58.562387
4147 01:18:58.565709 RX Vref 0 -> 0, step: 1
4148 01:18:58.565791
4149 01:18:58.565855 RX Delay -195 -> 252, step: 8
4150 01:18:58.565914
4151 01:18:58.569438 Set Vref, RX VrefLevel [Byte0]: 61
4152 01:18:58.572741 [Byte1]: 57
4153 01:18:58.577237
4154 01:18:58.577322 Final RX Vref Byte 0 = 61 to rank0
4155 01:18:58.580269 Final RX Vref Byte 1 = 57 to rank0
4156 01:18:58.583769 Final RX Vref Byte 0 = 61 to rank1
4157 01:18:58.586983 Final RX Vref Byte 1 = 57 to rank1==
4158 01:18:58.590426 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 01:18:58.597233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 01:18:58.597328 ==
4161 01:18:58.597395 DQS Delay:
4162 01:18:58.600546 DQS0 = 0, DQS1 = 0
4163 01:18:58.600632 DQM Delay:
4164 01:18:58.600696 DQM0 = 34, DQM1 = 28
4165 01:18:58.603684 DQ Delay:
4166 01:18:58.607132 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =32
4167 01:18:58.610184 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =48
4168 01:18:58.613937 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4169 01:18:58.616894 DQ12 =32, DQ13 =32, DQ14 =44, DQ15 =36
4170 01:18:58.617004
4171 01:18:58.617082
4172 01:18:58.623572 [DQSOSCAuto] RK0, (LSB)MR18= 0x403f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4173 01:18:58.626610 CH0 RK0: MR19=808, MR18=403F
4174 01:18:58.633631 CH0_RK0: MR19=0x808, MR18=0x403F, DQSOSC=397, MR23=63, INC=166, DEC=110
4175 01:18:58.633726
4176 01:18:58.637043 ----->DramcWriteLeveling(PI) begin...
4177 01:18:58.637127 ==
4178 01:18:58.640271 Dram Type= 6, Freq= 0, CH_0, rank 1
4179 01:18:58.643412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 01:18:58.643510 ==
4181 01:18:58.646718 Write leveling (Byte 0): 32 => 32
4182 01:18:58.649912 Write leveling (Byte 1): 30 => 30
4183 01:18:58.653622 DramcWriteLeveling(PI) end<-----
4184 01:18:58.653746
4185 01:18:58.653815 ==
4186 01:18:58.657015 Dram Type= 6, Freq= 0, CH_0, rank 1
4187 01:18:58.659715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 01:18:58.659806 ==
4189 01:18:58.663508 [Gating] SW mode calibration
4190 01:18:58.670025 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4191 01:18:58.676288 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4192 01:18:58.679605 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 01:18:58.686367 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4194 01:18:58.689280 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4195 01:18:58.693216 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4196 01:18:58.699534 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
4197 01:18:58.702853 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 01:18:58.706198 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 01:18:58.712809 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 01:18:58.716449 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 01:18:58.719303 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 01:18:58.726088 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 01:18:58.729204 0 10 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
4204 01:18:58.732373 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4205 01:18:58.739098 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 01:18:58.742554 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 01:18:58.746110 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 01:18:58.752661 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 01:18:58.755761 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 01:18:58.759134 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 01:18:58.765710 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4212 01:18:58.768684 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4213 01:18:58.772446 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 01:18:58.778653 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 01:18:58.781952 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 01:18:58.785307 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 01:18:58.791747 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 01:18:58.795134 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 01:18:58.798628 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 01:18:58.805235 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 01:18:58.808671 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 01:18:58.812044 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 01:18:58.818386 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 01:18:58.821786 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 01:18:58.824955 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 01:18:58.831515 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 01:18:58.834960 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4228 01:18:58.838430 Total UI for P1: 0, mck2ui 16
4229 01:18:58.841717 best dqsien dly found for B0: ( 0, 13, 10)
4230 01:18:58.844830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 01:18:58.847984 Total UI for P1: 0, mck2ui 16
4232 01:18:58.851496 best dqsien dly found for B1: ( 0, 13, 12)
4233 01:18:58.854720 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4234 01:18:58.857900 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4235 01:18:58.857985
4236 01:18:58.861298 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4237 01:18:58.867901 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4238 01:18:58.868019 [Gating] SW calibration Done
4239 01:18:58.871325 ==
4240 01:18:58.874401 Dram Type= 6, Freq= 0, CH_0, rank 1
4241 01:18:58.877922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 01:18:58.878004 ==
4243 01:18:58.878068 RX Vref Scan: 0
4244 01:18:58.878127
4245 01:18:58.881467 RX Vref 0 -> 0, step: 1
4246 01:18:58.881592
4247 01:18:58.884328 RX Delay -230 -> 252, step: 16
4248 01:18:58.887812 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4249 01:18:58.890987 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4250 01:18:58.897697 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4251 01:18:58.901447 iDelay=218, Bit 3, Center 25 (-150 ~ 201) 352
4252 01:18:58.904802 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4253 01:18:58.908073 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4254 01:18:58.914365 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4255 01:18:58.917704 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4256 01:18:58.921065 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4257 01:18:58.924500 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4258 01:18:58.927909 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4259 01:18:58.934250 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4260 01:18:58.937426 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4261 01:18:58.940923 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4262 01:18:58.944759 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4263 01:18:58.951236 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4264 01:18:58.951436 ==
4265 01:18:58.954056 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 01:18:58.957404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 01:18:58.957664 ==
4268 01:18:58.957815 DQS Delay:
4269 01:18:58.960416 DQS0 = 0, DQS1 = 0
4270 01:18:58.960572 DQM Delay:
4271 01:18:58.963750 DQM0 = 34, DQM1 = 28
4272 01:18:58.963932 DQ Delay:
4273 01:18:58.967247 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =25
4274 01:18:58.970836 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4275 01:18:58.973715 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4276 01:18:58.977441 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4277 01:18:58.977556
4278 01:18:58.977626
4279 01:18:58.977706 ==
4280 01:18:58.980924 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 01:18:58.983826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 01:18:58.987088 ==
4283 01:18:58.987268
4284 01:18:58.987358
4285 01:18:58.987439 TX Vref Scan disable
4286 01:18:58.990925 == TX Byte 0 ==
4287 01:18:58.993921 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4288 01:18:59.000565 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4289 01:18:59.000787 == TX Byte 1 ==
4290 01:18:59.003944 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4291 01:18:59.010616 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4292 01:18:59.010871 ==
4293 01:18:59.013802 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 01:18:59.016927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 01:18:59.017007 ==
4296 01:18:59.017070
4297 01:18:59.017129
4298 01:18:59.020240 TX Vref Scan disable
4299 01:18:59.023524 == TX Byte 0 ==
4300 01:18:59.027162 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4301 01:18:59.030435 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4302 01:18:59.033828 == TX Byte 1 ==
4303 01:18:59.037168 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4304 01:18:59.040850 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4305 01:18:59.041361
4306 01:18:59.041755 [DATLAT]
4307 01:18:59.043455 Freq=600, CH0 RK1
4308 01:18:59.043866
4309 01:18:59.044245 DATLAT Default: 0x9
4310 01:18:59.047110 0, 0xFFFF, sum = 0
4311 01:18:59.050317 1, 0xFFFF, sum = 0
4312 01:18:59.050399 2, 0xFFFF, sum = 0
4313 01:18:59.053429 3, 0xFFFF, sum = 0
4314 01:18:59.053548 4, 0xFFFF, sum = 0
4315 01:18:59.057035 5, 0xFFFF, sum = 0
4316 01:18:59.057122 6, 0xFFFF, sum = 0
4317 01:18:59.060334 7, 0xFFFF, sum = 0
4318 01:18:59.060427 8, 0x0, sum = 1
4319 01:18:59.060502 9, 0x0, sum = 2
4320 01:18:59.063850 10, 0x0, sum = 3
4321 01:18:59.064030 11, 0x0, sum = 4
4322 01:18:59.067221 best_step = 9
4323 01:18:59.067396
4324 01:18:59.067481 ==
4325 01:18:59.070100 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 01:18:59.073380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 01:18:59.073583 ==
4328 01:18:59.076596 RX Vref Scan: 0
4329 01:18:59.076765
4330 01:18:59.076871 RX Vref 0 -> 0, step: 1
4331 01:18:59.076961
4332 01:18:59.080049 RX Delay -195 -> 252, step: 8
4333 01:18:59.087588 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4334 01:18:59.090808 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4335 01:18:59.094027 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4336 01:18:59.097425 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4337 01:18:59.103852 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4338 01:18:59.107671 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4339 01:18:59.110915 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4340 01:18:59.115283 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4341 01:18:59.121054 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4342 01:18:59.124884 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4343 01:18:59.127368 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4344 01:18:59.131144 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4345 01:18:59.134416 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4346 01:18:59.140977 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4347 01:18:59.143841 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4348 01:18:59.146939 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4349 01:18:59.147355 ==
4350 01:18:59.150405 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 01:18:59.157246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 01:18:59.157802 ==
4353 01:18:59.158134 DQS Delay:
4354 01:18:59.158438 DQS0 = 0, DQS1 = 0
4355 01:18:59.160873 DQM Delay:
4356 01:18:59.161284 DQM0 = 33, DQM1 = 27
4357 01:18:59.164198 DQ Delay:
4358 01:18:59.167465 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4359 01:18:59.167896 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4360 01:18:59.170281 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4361 01:18:59.176980 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4362 01:18:59.177474
4363 01:18:59.177838
4364 01:18:59.183705 [DQSOSCAuto] RK1, (LSB)MR18= 0x6535, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4365 01:18:59.187078 CH0 RK1: MR19=808, MR18=6535
4366 01:18:59.193887 CH0_RK1: MR19=0x808, MR18=0x6535, DQSOSC=390, MR23=63, INC=172, DEC=114
4367 01:18:59.197300 [RxdqsGatingPostProcess] freq 600
4368 01:18:59.200442 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4369 01:18:59.203816 Pre-setting of DQS Precalculation
4370 01:18:59.210664 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4371 01:18:59.211259 ==
4372 01:18:59.213421 Dram Type= 6, Freq= 0, CH_1, rank 0
4373 01:18:59.217053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 01:18:59.217623 ==
4375 01:18:59.223444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 01:18:59.226357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4377 01:18:59.231429 [CA 0] Center 35 (5~66) winsize 62
4378 01:18:59.234736 [CA 1] Center 36 (6~66) winsize 61
4379 01:18:59.238139 [CA 2] Center 34 (4~65) winsize 62
4380 01:18:59.240691 [CA 3] Center 34 (3~65) winsize 63
4381 01:18:59.244434 [CA 4] Center 34 (4~65) winsize 62
4382 01:18:59.247445 [CA 5] Center 33 (3~64) winsize 62
4383 01:18:59.247588
4384 01:18:59.251258 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4385 01:18:59.251475
4386 01:18:59.254054 [CATrainingPosCal] consider 1 rank data
4387 01:18:59.257531 u2DelayCellTimex100 = 270/100 ps
4388 01:18:59.261110 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4389 01:18:59.267532 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4390 01:18:59.270790 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4391 01:18:59.274137 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4392 01:18:59.277248 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4393 01:18:59.280747 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4394 01:18:59.281041
4395 01:18:59.284315 CA PerBit enable=1, Macro0, CA PI delay=33
4396 01:18:59.284771
4397 01:18:59.287039 [CBTSetCACLKResult] CA Dly = 33
4398 01:18:59.290977 CS Dly: 4 (0~35)
4399 01:18:59.291389 ==
4400 01:18:59.294082 Dram Type= 6, Freq= 0, CH_1, rank 1
4401 01:18:59.297460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 01:18:59.297906 ==
4403 01:18:59.304399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4404 01:18:59.307419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4405 01:18:59.311308 [CA 0] Center 36 (6~66) winsize 61
4406 01:18:59.315075 [CA 1] Center 36 (6~67) winsize 62
4407 01:18:59.318244 [CA 2] Center 34 (4~65) winsize 62
4408 01:18:59.321042 [CA 3] Center 34 (4~65) winsize 62
4409 01:18:59.324636 [CA 4] Center 34 (4~65) winsize 62
4410 01:18:59.328507 [CA 5] Center 34 (3~65) winsize 63
4411 01:18:59.329020
4412 01:18:59.331327 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4413 01:18:59.331839
4414 01:18:59.334473 [CATrainingPosCal] consider 2 rank data
4415 01:18:59.338121 u2DelayCellTimex100 = 270/100 ps
4416 01:18:59.341591 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4417 01:18:59.347976 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4418 01:18:59.350909 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4419 01:18:59.354658 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4420 01:18:59.357556 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4421 01:18:59.360970 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4422 01:18:59.361613
4423 01:18:59.364597 CA PerBit enable=1, Macro0, CA PI delay=33
4424 01:18:59.365107
4425 01:18:59.367741 [CBTSetCACLKResult] CA Dly = 33
4426 01:18:59.370859 CS Dly: 4 (0~36)
4427 01:18:59.371270
4428 01:18:59.374304 ----->DramcWriteLeveling(PI) begin...
4429 01:18:59.374723 ==
4430 01:18:59.377489 Dram Type= 6, Freq= 0, CH_1, rank 0
4431 01:18:59.380728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 01:18:59.381240 ==
4433 01:18:59.383896 Write leveling (Byte 0): 28 => 28
4434 01:18:59.387092 Write leveling (Byte 1): 29 => 29
4435 01:18:59.390429 DramcWriteLeveling(PI) end<-----
4436 01:18:59.390842
4437 01:18:59.391163 ==
4438 01:18:59.393876 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 01:18:59.397299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 01:18:59.397857 ==
4441 01:18:59.400337 [Gating] SW mode calibration
4442 01:18:59.407112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4443 01:18:59.414204 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4444 01:18:59.416921 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 01:18:59.420397 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4446 01:18:59.427101 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4447 01:18:59.430443 0 9 12 | B1->B0 | 3333 3333 | 1 1 | (0 1) (0 1)
4448 01:18:59.434127 0 9 16 | B1->B0 | 2929 2424 | 1 0 | (1 0) (1 0)
4449 01:18:59.440726 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 01:18:59.443479 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 01:18:59.446647 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 01:18:59.452977 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 01:18:59.456242 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 01:18:59.459639 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 01:18:59.466342 0 10 12 | B1->B0 | 2b2b 2f2f | 1 0 | (0 0) (0 0)
4456 01:18:59.469613 0 10 16 | B1->B0 | 4242 4242 | 0 0 | (0 0) (0 0)
4457 01:18:59.472667 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 01:18:59.479636 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 01:18:59.482694 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 01:18:59.485817 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 01:18:59.492451 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 01:18:59.496055 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 01:18:59.499340 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 01:18:59.506298 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4465 01:18:59.509046 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 01:18:59.512698 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 01:18:59.519038 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 01:18:59.522436 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 01:18:59.525986 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 01:18:59.532296 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 01:18:59.535683 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 01:18:59.539018 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 01:18:59.545578 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 01:18:59.549137 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 01:18:59.552438 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 01:18:59.558905 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 01:18:59.561917 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 01:18:59.565768 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 01:18:59.571882 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 01:18:59.575181 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 01:18:59.578568 Total UI for P1: 0, mck2ui 16
4482 01:18:59.582270 best dqsien dly found for B0: ( 0, 13, 14)
4483 01:18:59.585387 Total UI for P1: 0, mck2ui 16
4484 01:18:59.589069 best dqsien dly found for B1: ( 0, 13, 14)
4485 01:18:59.592100 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4486 01:18:59.595450 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4487 01:18:59.595868
4488 01:18:59.598401 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4489 01:18:59.601952 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4490 01:18:59.605168 [Gating] SW calibration Done
4491 01:18:59.605616 ==
4492 01:18:59.608927 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 01:18:59.615445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 01:18:59.615973 ==
4495 01:18:59.616313 RX Vref Scan: 0
4496 01:18:59.616625
4497 01:18:59.618908 RX Vref 0 -> 0, step: 1
4498 01:18:59.619445
4499 01:18:59.621584 RX Delay -230 -> 252, step: 16
4500 01:18:59.624987 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4501 01:18:59.628282 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4502 01:18:59.631901 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4503 01:18:59.638716 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4504 01:18:59.641408 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4505 01:18:59.645246 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4506 01:18:59.648131 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4507 01:18:59.655024 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4508 01:18:59.658205 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4509 01:18:59.661928 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4510 01:18:59.664891 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4511 01:18:59.668269 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4512 01:18:59.674758 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4513 01:18:59.678070 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4514 01:18:59.681027 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4515 01:18:59.685017 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4516 01:18:59.688132 ==
4517 01:18:59.691189 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 01:18:59.694336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 01:18:59.694757 ==
4520 01:18:59.695086 DQS Delay:
4521 01:18:59.698119 DQS0 = 0, DQS1 = 0
4522 01:18:59.698535 DQM Delay:
4523 01:18:59.701547 DQM0 = 38, DQM1 = 28
4524 01:18:59.702055 DQ Delay:
4525 01:18:59.704382 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4526 01:18:59.708306 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4527 01:18:59.711731 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4528 01:18:59.714682 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4529 01:18:59.715189
4530 01:18:59.715521
4531 01:18:59.715825 ==
4532 01:18:59.717403 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 01:18:59.721086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 01:18:59.721503 ==
4535 01:18:59.721899
4536 01:18:59.722205
4537 01:18:59.723940 TX Vref Scan disable
4538 01:18:59.727314 == TX Byte 0 ==
4539 01:18:59.730627 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4540 01:18:59.734461 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4541 01:18:59.737699 == TX Byte 1 ==
4542 01:18:59.740732 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4543 01:18:59.744424 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4544 01:18:59.744938 ==
4545 01:18:59.747313 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 01:18:59.754386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 01:18:59.754902 ==
4548 01:18:59.755236
4549 01:18:59.755540
4550 01:18:59.755833 TX Vref Scan disable
4551 01:18:59.758443 == TX Byte 0 ==
4552 01:18:59.761864 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4553 01:18:59.768747 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4554 01:18:59.769170 == TX Byte 1 ==
4555 01:18:59.772206 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4556 01:18:59.778281 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4557 01:18:59.778822
4558 01:18:59.779160 [DATLAT]
4559 01:18:59.779463 Freq=600, CH1 RK0
4560 01:18:59.779758
4561 01:18:59.781687 DATLAT Default: 0x9
4562 01:18:59.782101 0, 0xFFFF, sum = 0
4563 01:18:59.785100 1, 0xFFFF, sum = 0
4564 01:18:59.785555 2, 0xFFFF, sum = 0
4565 01:18:59.788482 3, 0xFFFF, sum = 0
4566 01:18:59.791682 4, 0xFFFF, sum = 0
4567 01:18:59.792198 5, 0xFFFF, sum = 0
4568 01:18:59.794778 6, 0xFFFF, sum = 0
4569 01:18:59.795201 7, 0xFFFF, sum = 0
4570 01:18:59.797922 8, 0x0, sum = 1
4571 01:18:59.798345 9, 0x0, sum = 2
4572 01:18:59.798675 10, 0x0, sum = 3
4573 01:18:59.800910 11, 0x0, sum = 4
4574 01:18:59.800992 best_step = 9
4575 01:18:59.801057
4576 01:18:59.801116 ==
4577 01:18:59.804450 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 01:18:59.810995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 01:18:59.811153 ==
4580 01:18:59.811234 RX Vref Scan: 1
4581 01:18:59.811308
4582 01:18:59.814645 RX Vref 0 -> 0, step: 1
4583 01:18:59.814812
4584 01:18:59.818024 RX Delay -195 -> 252, step: 8
4585 01:18:59.818194
4586 01:18:59.821165 Set Vref, RX VrefLevel [Byte0]: 55
4587 01:18:59.824387 [Byte1]: 47
4588 01:18:59.824539
4589 01:18:59.827870 Final RX Vref Byte 0 = 55 to rank0
4590 01:18:59.830922 Final RX Vref Byte 1 = 47 to rank0
4591 01:18:59.834359 Final RX Vref Byte 0 = 55 to rank1
4592 01:18:59.838314 Final RX Vref Byte 1 = 47 to rank1==
4593 01:18:59.841100 Dram Type= 6, Freq= 0, CH_1, rank 0
4594 01:18:59.844828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 01:18:59.845089 ==
4596 01:18:59.847376 DQS Delay:
4597 01:18:59.847572 DQS0 = 0, DQS1 = 0
4598 01:18:59.850724 DQM Delay:
4599 01:18:59.850924 DQM0 = 38, DQM1 = 30
4600 01:18:59.851085 DQ Delay:
4601 01:18:59.853864 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4602 01:18:59.857207 DQ4 =36, DQ5 =44, DQ6 =52, DQ7 =36
4603 01:18:59.860736 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =24
4604 01:18:59.864079 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =40
4605 01:18:59.864378
4606 01:18:59.864612
4607 01:18:59.874090 [DQSOSCAuto] RK0, (LSB)MR18= 0x222f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4608 01:18:59.877764 CH1 RK0: MR19=808, MR18=222F
4609 01:18:59.884050 CH1_RK0: MR19=0x808, MR18=0x222F, DQSOSC=400, MR23=63, INC=163, DEC=109
4610 01:18:59.884583
4611 01:18:59.887712 ----->DramcWriteLeveling(PI) begin...
4612 01:18:59.888136 ==
4613 01:18:59.890871 Dram Type= 6, Freq= 0, CH_1, rank 1
4614 01:18:59.894128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 01:18:59.894647 ==
4616 01:18:59.897368 Write leveling (Byte 0): 28 => 28
4617 01:18:59.901026 Write leveling (Byte 1): 31 => 31
4618 01:18:59.904149 DramcWriteLeveling(PI) end<-----
4619 01:18:59.904667
4620 01:18:59.905000 ==
4621 01:18:59.907260 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 01:18:59.910504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 01:18:59.910983 ==
4624 01:18:59.914043 [Gating] SW mode calibration
4625 01:18:59.920269 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4626 01:18:59.927471 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4627 01:18:59.930332 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 01:18:59.933485 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4629 01:18:59.940586 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4630 01:18:59.943991 0 9 12 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
4631 01:18:59.947040 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4632 01:18:59.954012 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 01:18:59.957241 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 01:18:59.960131 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 01:18:59.966472 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 01:18:59.969888 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 01:18:59.973284 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4638 01:18:59.979550 0 10 12 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (0 0)
4639 01:18:59.983242 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4640 01:18:59.986625 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 01:18:59.993007 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 01:18:59.996370 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 01:18:59.999674 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 01:19:00.006416 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 01:19:00.010155 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 01:19:00.013567 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4647 01:19:00.019675 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 01:19:00.023161 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 01:19:00.026021 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 01:19:00.032905 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 01:19:00.036099 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 01:19:00.039542 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 01:19:00.046144 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 01:19:00.049440 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 01:19:00.052748 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 01:19:00.059843 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 01:19:00.062502 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 01:19:00.066048 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 01:19:00.072366 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 01:19:00.075716 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 01:19:00.079221 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 01:19:00.085804 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4663 01:19:00.086323 Total UI for P1: 0, mck2ui 16
4664 01:19:00.092426 best dqsien dly found for B0: ( 0, 13, 10)
4665 01:19:00.096018 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 01:19:00.099261 Total UI for P1: 0, mck2ui 16
4667 01:19:00.101915 best dqsien dly found for B1: ( 0, 13, 12)
4668 01:19:00.104983 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4669 01:19:00.108379 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4670 01:19:00.108460
4671 01:19:00.111838 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4672 01:19:00.115373 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4673 01:19:00.118535 [Gating] SW calibration Done
4674 01:19:00.118703 ==
4675 01:19:00.121928 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 01:19:00.128712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 01:19:00.128900 ==
4678 01:19:00.128998 RX Vref Scan: 0
4679 01:19:00.129087
4680 01:19:00.131508 RX Vref 0 -> 0, step: 1
4681 01:19:00.131643
4682 01:19:00.134618 RX Delay -230 -> 252, step: 16
4683 01:19:00.138724 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4684 01:19:00.141409 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4685 01:19:00.144933 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4686 01:19:00.151263 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4687 01:19:00.154860 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4688 01:19:00.158111 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4689 01:19:00.162063 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4690 01:19:00.168499 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4691 01:19:00.171285 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4692 01:19:00.175078 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4693 01:19:00.178213 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4694 01:19:00.181471 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4695 01:19:00.188004 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4696 01:19:00.191620 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4697 01:19:00.194789 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4698 01:19:00.197993 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4699 01:19:00.201702 ==
4700 01:19:00.205064 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 01:19:00.207799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 01:19:00.208312 ==
4703 01:19:00.208638 DQS Delay:
4704 01:19:00.210953 DQS0 = 0, DQS1 = 0
4705 01:19:00.211359 DQM Delay:
4706 01:19:00.214448 DQM0 = 35, DQM1 = 28
4707 01:19:00.214958 DQ Delay:
4708 01:19:00.217680 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4709 01:19:00.220759 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4710 01:19:00.224447 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =17
4711 01:19:00.227655 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4712 01:19:00.228068
4713 01:19:00.228388
4714 01:19:00.228685 ==
4715 01:19:00.230786 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 01:19:00.234067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 01:19:00.234479 ==
4718 01:19:00.234805
4719 01:19:00.237282
4720 01:19:00.237708 TX Vref Scan disable
4721 01:19:00.240586 == TX Byte 0 ==
4722 01:19:00.244042 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4723 01:19:00.247632 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4724 01:19:00.250351 == TX Byte 1 ==
4725 01:19:00.253893 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4726 01:19:00.257003 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4727 01:19:00.257414 ==
4728 01:19:00.260623 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 01:19:00.266916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 01:19:00.267331 ==
4731 01:19:00.267656
4732 01:19:00.267959
4733 01:19:00.270096 TX Vref Scan disable
4734 01:19:00.270506 == TX Byte 0 ==
4735 01:19:00.277077 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4736 01:19:00.279976 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4737 01:19:00.280389 == TX Byte 1 ==
4738 01:19:00.286729 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4739 01:19:00.290219 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4740 01:19:00.290636
4741 01:19:00.290962 [DATLAT]
4742 01:19:00.293366 Freq=600, CH1 RK1
4743 01:19:00.293807
4744 01:19:00.294197 DATLAT Default: 0x9
4745 01:19:00.296858 0, 0xFFFF, sum = 0
4746 01:19:00.297389 1, 0xFFFF, sum = 0
4747 01:19:00.300150 2, 0xFFFF, sum = 0
4748 01:19:00.303494 3, 0xFFFF, sum = 0
4749 01:19:00.303913 4, 0xFFFF, sum = 0
4750 01:19:00.305879 5, 0xFFFF, sum = 0
4751 01:19:00.305960 6, 0xFFFF, sum = 0
4752 01:19:00.309403 7, 0xFFFF, sum = 0
4753 01:19:00.309495 8, 0x0, sum = 1
4754 01:19:00.313038 9, 0x0, sum = 2
4755 01:19:00.313197 10, 0x0, sum = 3
4756 01:19:00.313271 11, 0x0, sum = 4
4757 01:19:00.316250 best_step = 9
4758 01:19:00.316366
4759 01:19:00.316442 ==
4760 01:19:00.319986 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 01:19:00.323022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 01:19:00.323163 ==
4763 01:19:00.325826 RX Vref Scan: 0
4764 01:19:00.326030
4765 01:19:00.326157 RX Vref 0 -> 0, step: 1
4766 01:19:00.329326
4767 01:19:00.329457 RX Delay -195 -> 252, step: 8
4768 01:19:00.337221 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4769 01:19:00.340347 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4770 01:19:00.343602 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4771 01:19:00.346745 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4772 01:19:00.353449 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4773 01:19:00.357238 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4774 01:19:00.360284 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4775 01:19:00.363083 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4776 01:19:00.370297 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4777 01:19:00.373181 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4778 01:19:00.377174 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4779 01:19:00.380125 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4780 01:19:00.386312 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4781 01:19:00.389558 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4782 01:19:00.393540 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4783 01:19:00.396840 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4784 01:19:00.397009 ==
4785 01:19:00.400096 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 01:19:00.406524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 01:19:00.406939 ==
4788 01:19:00.407267 DQS Delay:
4789 01:19:00.410244 DQS0 = 0, DQS1 = 0
4790 01:19:00.410759 DQM Delay:
4791 01:19:00.411086 DQM0 = 35, DQM1 = 30
4792 01:19:00.413342 DQ Delay:
4793 01:19:00.416716 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4794 01:19:00.420463 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4795 01:19:00.423406 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4796 01:19:00.426831 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4797 01:19:00.427242
4798 01:19:00.427564
4799 01:19:00.433012 [DQSOSCAuto] RK1, (LSB)MR18= 0x3758, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4800 01:19:00.436262 CH1 RK1: MR19=808, MR18=3758
4801 01:19:00.443218 CH1_RK1: MR19=0x808, MR18=0x3758, DQSOSC=393, MR23=63, INC=169, DEC=113
4802 01:19:00.446532 [RxdqsGatingPostProcess] freq 600
4803 01:19:00.449767 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4804 01:19:00.452843 Pre-setting of DQS Precalculation
4805 01:19:00.459467 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4806 01:19:00.466045 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4807 01:19:00.472685 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4808 01:19:00.473104
4809 01:19:00.473430
4810 01:19:00.475969 [Calibration Summary] 1200 Mbps
4811 01:19:00.476381 CH 0, Rank 0
4812 01:19:00.479381 SW Impedance : PASS
4813 01:19:00.482668 DUTY Scan : NO K
4814 01:19:00.483077 ZQ Calibration : PASS
4815 01:19:00.486108 Jitter Meter : NO K
4816 01:19:00.489630 CBT Training : PASS
4817 01:19:00.490054 Write leveling : PASS
4818 01:19:00.492904 RX DQS gating : PASS
4819 01:19:00.496016 RX DQ/DQS(RDDQC) : PASS
4820 01:19:00.496473 TX DQ/DQS : PASS
4821 01:19:00.500110 RX DATLAT : PASS
4822 01:19:00.502888 RX DQ/DQS(Engine): PASS
4823 01:19:00.503598 TX OE : NO K
4824 01:19:00.505796 All Pass.
4825 01:19:00.506237
4826 01:19:00.506560 CH 0, Rank 1
4827 01:19:00.509152 SW Impedance : PASS
4828 01:19:00.509586 DUTY Scan : NO K
4829 01:19:00.512668 ZQ Calibration : PASS
4830 01:19:00.516280 Jitter Meter : NO K
4831 01:19:00.516794 CBT Training : PASS
4832 01:19:00.519158 Write leveling : PASS
4833 01:19:00.522455 RX DQS gating : PASS
4834 01:19:00.522866 RX DQ/DQS(RDDQC) : PASS
4835 01:19:00.525639 TX DQ/DQS : PASS
4836 01:19:00.526052 RX DATLAT : PASS
4837 01:19:00.529374 RX DQ/DQS(Engine): PASS
4838 01:19:00.532787 TX OE : NO K
4839 01:19:00.533300 All Pass.
4840 01:19:00.533662
4841 01:19:00.533968 CH 1, Rank 0
4842 01:19:00.536072 SW Impedance : PASS
4843 01:19:00.539180 DUTY Scan : NO K
4844 01:19:00.539592 ZQ Calibration : PASS
4845 01:19:00.542650 Jitter Meter : NO K
4846 01:19:00.545814 CBT Training : PASS
4847 01:19:00.546368 Write leveling : PASS
4848 01:19:00.548828 RX DQS gating : PASS
4849 01:19:00.552095 RX DQ/DQS(RDDQC) : PASS
4850 01:19:00.552514 TX DQ/DQS : PASS
4851 01:19:00.555405 RX DATLAT : PASS
4852 01:19:00.558977 RX DQ/DQS(Engine): PASS
4853 01:19:00.559434 TX OE : NO K
4854 01:19:00.562436 All Pass.
4855 01:19:00.562843
4856 01:19:00.563185 CH 1, Rank 1
4857 01:19:00.565326 SW Impedance : PASS
4858 01:19:00.565891 DUTY Scan : NO K
4859 01:19:00.568694 ZQ Calibration : PASS
4860 01:19:00.572347 Jitter Meter : NO K
4861 01:19:00.572822 CBT Training : PASS
4862 01:19:00.575366 Write leveling : PASS
4863 01:19:00.578725 RX DQS gating : PASS
4864 01:19:00.579134 RX DQ/DQS(RDDQC) : PASS
4865 01:19:00.581988 TX DQ/DQS : PASS
4866 01:19:00.582399 RX DATLAT : PASS
4867 01:19:00.585705 RX DQ/DQS(Engine): PASS
4868 01:19:00.588852 TX OE : NO K
4869 01:19:00.589364 All Pass.
4870 01:19:00.589854
4871 01:19:00.592377 DramC Write-DBI off
4872 01:19:00.592895 PER_BANK_REFRESH: Hybrid Mode
4873 01:19:00.595359 TX_TRACKING: ON
4874 01:19:00.604957 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4875 01:19:00.608517 [FAST_K] Save calibration result to emmc
4876 01:19:00.612145 dramc_set_vcore_voltage set vcore to 662500
4877 01:19:00.612577 Read voltage for 933, 3
4878 01:19:00.615635 Vio18 = 0
4879 01:19:00.616144 Vcore = 662500
4880 01:19:00.616469 Vdram = 0
4881 01:19:00.618297 Vddq = 0
4882 01:19:00.618704 Vmddr = 0
4883 01:19:00.625344 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4884 01:19:00.628542 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4885 01:19:00.632082 MEM_TYPE=3, freq_sel=17
4886 01:19:00.634953 sv_algorithm_assistance_LP4_1600
4887 01:19:00.638841 ============ PULL DRAM RESETB DOWN ============
4888 01:19:00.642211 ========== PULL DRAM RESETB DOWN end =========
4889 01:19:00.648382 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4890 01:19:00.651774 ===================================
4891 01:19:00.652294 LPDDR4 DRAM CONFIGURATION
4892 01:19:00.655079 ===================================
4893 01:19:00.658492 EX_ROW_EN[0] = 0x0
4894 01:19:00.661967 EX_ROW_EN[1] = 0x0
4895 01:19:00.662487 LP4Y_EN = 0x0
4896 01:19:00.665000 WORK_FSP = 0x0
4897 01:19:00.665408 WL = 0x3
4898 01:19:00.668461 RL = 0x3
4899 01:19:00.668874 BL = 0x2
4900 01:19:00.671343 RPST = 0x0
4901 01:19:00.671770 RD_PRE = 0x0
4902 01:19:00.675016 WR_PRE = 0x1
4903 01:19:00.675424 WR_PST = 0x0
4904 01:19:00.678057 DBI_WR = 0x0
4905 01:19:00.678589 DBI_RD = 0x0
4906 01:19:00.681415 OTF = 0x1
4907 01:19:00.684582 ===================================
4908 01:19:00.687837 ===================================
4909 01:19:00.688295 ANA top config
4910 01:19:00.691414 ===================================
4911 01:19:00.694487 DLL_ASYNC_EN = 0
4912 01:19:00.698428 ALL_SLAVE_EN = 1
4913 01:19:00.698944 NEW_RANK_MODE = 1
4914 01:19:00.701465 DLL_IDLE_MODE = 1
4915 01:19:00.704631 LP45_APHY_COMB_EN = 1
4916 01:19:00.708334 TX_ODT_DIS = 1
4917 01:19:00.711015 NEW_8X_MODE = 1
4918 01:19:00.714352 ===================================
4919 01:19:00.718305 ===================================
4920 01:19:00.718830 data_rate = 1866
4921 01:19:00.721577 CKR = 1
4922 01:19:00.724272 DQ_P2S_RATIO = 8
4923 01:19:00.727754 ===================================
4924 01:19:00.730945 CA_P2S_RATIO = 8
4925 01:19:00.734816 DQ_CA_OPEN = 0
4926 01:19:00.737618 DQ_SEMI_OPEN = 0
4927 01:19:00.738029 CA_SEMI_OPEN = 0
4928 01:19:00.741024 CA_FULL_RATE = 0
4929 01:19:00.744699 DQ_CKDIV4_EN = 1
4930 01:19:00.747750 CA_CKDIV4_EN = 1
4931 01:19:00.751291 CA_PREDIV_EN = 0
4932 01:19:00.754762 PH8_DLY = 0
4933 01:19:00.755274 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4934 01:19:00.758054 DQ_AAMCK_DIV = 4
4935 01:19:00.760971 CA_AAMCK_DIV = 4
4936 01:19:00.764456 CA_ADMCK_DIV = 4
4937 01:19:00.767665 DQ_TRACK_CA_EN = 0
4938 01:19:00.770803 CA_PICK = 933
4939 01:19:00.774641 CA_MCKIO = 933
4940 01:19:00.775157 MCKIO_SEMI = 0
4941 01:19:00.777418 PLL_FREQ = 3732
4942 01:19:00.780718 DQ_UI_PI_RATIO = 32
4943 01:19:00.783774 CA_UI_PI_RATIO = 0
4944 01:19:00.787196 ===================================
4945 01:19:00.790836 ===================================
4946 01:19:00.793967 memory_type:LPDDR4
4947 01:19:00.794375 GP_NUM : 10
4948 01:19:00.797674 SRAM_EN : 1
4949 01:19:00.800781 MD32_EN : 0
4950 01:19:00.803464 ===================================
4951 01:19:00.803897 [ANA_INIT] >>>>>>>>>>>>>>
4952 01:19:00.807295 <<<<<< [CONFIGURE PHASE]: ANA_TX
4953 01:19:00.810168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4954 01:19:00.813460 ===================================
4955 01:19:00.816942 data_rate = 1866,PCW = 0X8f00
4956 01:19:00.820276 ===================================
4957 01:19:00.823635 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4958 01:19:00.830391 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4959 01:19:00.834049 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4960 01:19:00.840276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4961 01:19:00.843665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4962 01:19:00.846597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4963 01:19:00.847029 [ANA_INIT] flow start
4964 01:19:00.850417 [ANA_INIT] PLL >>>>>>>>
4965 01:19:00.853356 [ANA_INIT] PLL <<<<<<<<
4966 01:19:00.856577 [ANA_INIT] MIDPI >>>>>>>>
4967 01:19:00.857114 [ANA_INIT] MIDPI <<<<<<<<
4968 01:19:00.859922 [ANA_INIT] DLL >>>>>>>>
4969 01:19:00.863632 [ANA_INIT] flow end
4970 01:19:00.867028 ============ LP4 DIFF to SE enter ============
4971 01:19:00.869836 ============ LP4 DIFF to SE exit ============
4972 01:19:00.873354 [ANA_INIT] <<<<<<<<<<<<<
4973 01:19:00.876780 [Flow] Enable top DCM control >>>>>
4974 01:19:00.880213 [Flow] Enable top DCM control <<<<<
4975 01:19:00.883776 Enable DLL master slave shuffle
4976 01:19:00.886537 ==============================================================
4977 01:19:00.890098 Gating Mode config
4978 01:19:00.896508 ==============================================================
4979 01:19:00.897040 Config description:
4980 01:19:00.906745 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4981 01:19:00.913102 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4982 01:19:00.916962 SELPH_MODE 0: By rank 1: By Phase
4983 01:19:00.923304 ==============================================================
4984 01:19:00.926493 GAT_TRACK_EN = 1
4985 01:19:00.929344 RX_GATING_MODE = 2
4986 01:19:00.932917 RX_GATING_TRACK_MODE = 2
4987 01:19:00.936231 SELPH_MODE = 1
4988 01:19:00.939676 PICG_EARLY_EN = 1
4989 01:19:00.942737 VALID_LAT_VALUE = 1
4990 01:19:00.945978 ==============================================================
4991 01:19:00.949363 Enter into Gating configuration >>>>
4992 01:19:00.952633 Exit from Gating configuration <<<<
4993 01:19:00.956268 Enter into DVFS_PRE_config >>>>>
4994 01:19:00.969343 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4995 01:19:00.969894 Exit from DVFS_PRE_config <<<<<
4996 01:19:00.972638 Enter into PICG configuration >>>>
4997 01:19:00.976045 Exit from PICG configuration <<<<
4998 01:19:00.979317 [RX_INPUT] configuration >>>>>
4999 01:19:00.982462 [RX_INPUT] configuration <<<<<
5000 01:19:00.989211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5001 01:19:00.992601 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5002 01:19:00.999431 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 01:19:01.005665 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 01:19:01.012183 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5005 01:19:01.018964 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5006 01:19:01.022392 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5007 01:19:01.025591 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5008 01:19:01.028998 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5009 01:19:01.035376 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5010 01:19:01.038622 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5011 01:19:01.042187 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5012 01:19:01.045467 ===================================
5013 01:19:01.048305 LPDDR4 DRAM CONFIGURATION
5014 01:19:01.051811 ===================================
5015 01:19:01.055460 EX_ROW_EN[0] = 0x0
5016 01:19:01.055974 EX_ROW_EN[1] = 0x0
5017 01:19:01.058537 LP4Y_EN = 0x0
5018 01:19:01.059113 WORK_FSP = 0x0
5019 01:19:01.061591 WL = 0x3
5020 01:19:01.062119 RL = 0x3
5021 01:19:01.065241 BL = 0x2
5022 01:19:01.065778 RPST = 0x0
5023 01:19:01.068297 RD_PRE = 0x0
5024 01:19:01.068754 WR_PRE = 0x1
5025 01:19:01.071849 WR_PST = 0x0
5026 01:19:01.072435 DBI_WR = 0x0
5027 01:19:01.075233 DBI_RD = 0x0
5028 01:19:01.075649 OTF = 0x1
5029 01:19:01.078572 ===================================
5030 01:19:01.085292 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5031 01:19:01.088474 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5032 01:19:01.091604 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5033 01:19:01.095459 ===================================
5034 01:19:01.098136 LPDDR4 DRAM CONFIGURATION
5035 01:19:01.101737 ===================================
5036 01:19:01.104792 EX_ROW_EN[0] = 0x10
5037 01:19:01.105355 EX_ROW_EN[1] = 0x0
5038 01:19:01.108247 LP4Y_EN = 0x0
5039 01:19:01.108993 WORK_FSP = 0x0
5040 01:19:01.111517 WL = 0x3
5041 01:19:01.112075 RL = 0x3
5042 01:19:01.115108 BL = 0x2
5043 01:19:01.115568 RPST = 0x0
5044 01:19:01.117961 RD_PRE = 0x0
5045 01:19:01.118419 WR_PRE = 0x1
5046 01:19:01.121834 WR_PST = 0x0
5047 01:19:01.122388 DBI_WR = 0x0
5048 01:19:01.124833 DBI_RD = 0x0
5049 01:19:01.125393 OTF = 0x1
5050 01:19:01.128390 ===================================
5051 01:19:01.134602 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5052 01:19:01.139691 nWR fixed to 30
5053 01:19:01.142856 [ModeRegInit_LP4] CH0 RK0
5054 01:19:01.143411 [ModeRegInit_LP4] CH0 RK1
5055 01:19:01.145812 [ModeRegInit_LP4] CH1 RK0
5056 01:19:01.149616 [ModeRegInit_LP4] CH1 RK1
5057 01:19:01.150171 match AC timing 9
5058 01:19:01.156245 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5059 01:19:01.159590 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5060 01:19:01.162549 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5061 01:19:01.169263 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5062 01:19:01.172646 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5063 01:19:01.173108 ==
5064 01:19:01.175995 Dram Type= 6, Freq= 0, CH_0, rank 0
5065 01:19:01.179376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 01:19:01.179892 ==
5067 01:19:01.185540 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 01:19:01.192616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5069 01:19:01.195463 [CA 0] Center 38 (8~69) winsize 62
5070 01:19:01.198931 [CA 1] Center 38 (7~69) winsize 63
5071 01:19:01.202263 [CA 2] Center 35 (5~66) winsize 62
5072 01:19:01.205280 [CA 3] Center 35 (4~66) winsize 63
5073 01:19:01.209221 [CA 4] Center 34 (4~65) winsize 62
5074 01:19:01.212576 [CA 5] Center 33 (3~64) winsize 62
5075 01:19:01.213101
5076 01:19:01.215835 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5077 01:19:01.216360
5078 01:19:01.219284 [CATrainingPosCal] consider 1 rank data
5079 01:19:01.222195 u2DelayCellTimex100 = 270/100 ps
5080 01:19:01.225933 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5081 01:19:01.229079 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5082 01:19:01.232384 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5083 01:19:01.235427 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5084 01:19:01.242028 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5085 01:19:01.245595 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5086 01:19:01.246160
5087 01:19:01.248730 CA PerBit enable=1, Macro0, CA PI delay=33
5088 01:19:01.249294
5089 01:19:01.252410 [CBTSetCACLKResult] CA Dly = 33
5090 01:19:01.252974 CS Dly: 7 (0~38)
5091 01:19:01.253341 ==
5092 01:19:01.255514 Dram Type= 6, Freq= 0, CH_0, rank 1
5093 01:19:01.261970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 01:19:01.262553 ==
5095 01:19:01.265266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5096 01:19:01.271766 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5097 01:19:01.275413 [CA 0] Center 38 (8~69) winsize 62
5098 01:19:01.278120 [CA 1] Center 38 (8~69) winsize 62
5099 01:19:01.281558 [CA 2] Center 35 (5~66) winsize 62
5100 01:19:01.284679 [CA 3] Center 35 (4~66) winsize 63
5101 01:19:01.288389 [CA 4] Center 34 (4~65) winsize 62
5102 01:19:01.291772 [CA 5] Center 34 (4~64) winsize 61
5103 01:19:01.292228
5104 01:19:01.294989 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5105 01:19:01.295543
5106 01:19:01.298024 [CATrainingPosCal] consider 2 rank data
5107 01:19:01.301712 u2DelayCellTimex100 = 270/100 ps
5108 01:19:01.304766 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5109 01:19:01.308173 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5110 01:19:01.314596 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5111 01:19:01.318025 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5112 01:19:01.321647 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5113 01:19:01.324955 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5114 01:19:01.325568
5115 01:19:01.328384 CA PerBit enable=1, Macro0, CA PI delay=34
5116 01:19:01.328938
5117 01:19:01.331429 [CBTSetCACLKResult] CA Dly = 34
5118 01:19:01.331987 CS Dly: 7 (0~38)
5119 01:19:01.332351
5120 01:19:01.334331 ----->DramcWriteLeveling(PI) begin...
5121 01:19:01.338224 ==
5122 01:19:01.341041 Dram Type= 6, Freq= 0, CH_0, rank 0
5123 01:19:01.344934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5124 01:19:01.345549 ==
5125 01:19:01.347832 Write leveling (Byte 0): 31 => 31
5126 01:19:01.350758 Write leveling (Byte 1): 30 => 30
5127 01:19:01.354256 DramcWriteLeveling(PI) end<-----
5128 01:19:01.354811
5129 01:19:01.355172 ==
5130 01:19:01.357697 Dram Type= 6, Freq= 0, CH_0, rank 0
5131 01:19:01.360696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 01:19:01.361155 ==
5133 01:19:01.364216 [Gating] SW mode calibration
5134 01:19:01.370849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5135 01:19:01.377300 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5136 01:19:01.380735 0 14 0 | B1->B0 | 2323 2c2c | 1 1 | (0 0) (1 1)
5137 01:19:01.383621 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5138 01:19:01.390355 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 01:19:01.393677 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 01:19:01.397314 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 01:19:01.403646 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 01:19:01.407786 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 01:19:01.411044 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5144 01:19:01.417165 0 15 0 | B1->B0 | 3434 2828 | 0 0 | (0 0) (1 1)
5145 01:19:01.420340 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5146 01:19:01.423982 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 01:19:01.430473 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 01:19:01.433862 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 01:19:01.437023 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 01:19:01.443538 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 01:19:01.447026 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 01:19:01.450128 1 0 0 | B1->B0 | 2626 3f3f | 1 0 | (0 0) (0 0)
5153 01:19:01.456666 1 0 4 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5154 01:19:01.459842 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 01:19:01.463536 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 01:19:01.470432 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 01:19:01.473402 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 01:19:01.476265 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 01:19:01.483487 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5160 01:19:01.486495 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5161 01:19:01.489361 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 01:19:01.495997 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 01:19:01.499389 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 01:19:01.503096 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 01:19:01.509898 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 01:19:01.513075 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 01:19:01.516415 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 01:19:01.522591 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 01:19:01.525776 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 01:19:01.529063 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 01:19:01.535884 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 01:19:01.539033 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 01:19:01.542504 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 01:19:01.549118 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 01:19:01.552482 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 01:19:01.555626 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5177 01:19:01.559052 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 01:19:01.562337 Total UI for P1: 0, mck2ui 16
5179 01:19:01.565768 best dqsien dly found for B0: ( 1, 3, 0)
5180 01:19:01.569082 Total UI for P1: 0, mck2ui 16
5181 01:19:01.572576 best dqsien dly found for B1: ( 1, 3, 0)
5182 01:19:01.575870 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5183 01:19:01.578772 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5184 01:19:01.579191
5185 01:19:01.585613 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5186 01:19:01.588858 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5187 01:19:01.592220 [Gating] SW calibration Done
5188 01:19:01.592629 ==
5189 01:19:01.596013 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 01:19:01.598763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 01:19:01.599308 ==
5192 01:19:01.599778 RX Vref Scan: 0
5193 01:19:01.600222
5194 01:19:01.602379 RX Vref 0 -> 0, step: 1
5195 01:19:01.602788
5196 01:19:01.605378 RX Delay -80 -> 252, step: 8
5197 01:19:01.608967 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5198 01:19:01.612190 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5199 01:19:01.615359 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5200 01:19:01.622522 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5201 01:19:01.625641 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5202 01:19:01.628983 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5203 01:19:01.632425 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5204 01:19:01.635737 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5205 01:19:01.638967 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5206 01:19:01.645491 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5207 01:19:01.648615 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5208 01:19:01.651647 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5209 01:19:01.655188 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5210 01:19:01.661870 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5211 01:19:01.665359 iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208
5212 01:19:01.668474 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5213 01:19:01.668985 ==
5214 01:19:01.671648 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 01:19:01.675067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 01:19:01.675479 ==
5217 01:19:01.678424 DQS Delay:
5218 01:19:01.678831 DQS0 = 0, DQS1 = 0
5219 01:19:01.681683 DQM Delay:
5220 01:19:01.682270 DQM0 = 95, DQM1 = 83
5221 01:19:01.682725 DQ Delay:
5222 01:19:01.685162 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5223 01:19:01.688046 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =111
5224 01:19:01.691798 DQ8 =79, DQ9 =67, DQ10 =83, DQ11 =75
5225 01:19:01.694840 DQ12 =91, DQ13 =87, DQ14 =95, DQ15 =91
5226 01:19:01.695327
5227 01:19:01.695663
5228 01:19:01.698154 ==
5229 01:19:01.701463 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 01:19:01.704792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 01:19:01.705310 ==
5232 01:19:01.705688
5233 01:19:01.705998
5234 01:19:01.707730 TX Vref Scan disable
5235 01:19:01.708138 == TX Byte 0 ==
5236 01:19:01.711601 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5237 01:19:01.717911 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5238 01:19:01.718431 == TX Byte 1 ==
5239 01:19:01.721480 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5240 01:19:01.727837 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5241 01:19:01.728368 ==
5242 01:19:01.731120 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 01:19:01.734658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 01:19:01.735313 ==
5245 01:19:01.735654
5246 01:19:01.735960
5247 01:19:01.737620 TX Vref Scan disable
5248 01:19:01.741914 == TX Byte 0 ==
5249 01:19:01.744245 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5250 01:19:01.747886 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5251 01:19:01.751272 == TX Byte 1 ==
5252 01:19:01.754103 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5253 01:19:01.758192 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5254 01:19:01.758764
5255 01:19:01.760904 [DATLAT]
5256 01:19:01.761356 Freq=933, CH0 RK0
5257 01:19:01.761783
5258 01:19:01.764245 DATLAT Default: 0xd
5259 01:19:01.764650 0, 0xFFFF, sum = 0
5260 01:19:01.767785 1, 0xFFFF, sum = 0
5261 01:19:01.768463 2, 0xFFFF, sum = 0
5262 01:19:01.770742 3, 0xFFFF, sum = 0
5263 01:19:01.771155 4, 0xFFFF, sum = 0
5264 01:19:01.773986 5, 0xFFFF, sum = 0
5265 01:19:01.774406 6, 0xFFFF, sum = 0
5266 01:19:01.777393 7, 0xFFFF, sum = 0
5267 01:19:01.777853 8, 0xFFFF, sum = 0
5268 01:19:01.780995 9, 0xFFFF, sum = 0
5269 01:19:01.781551 10, 0x0, sum = 1
5270 01:19:01.784433 11, 0x0, sum = 2
5271 01:19:01.784983 12, 0x0, sum = 3
5272 01:19:01.787670 13, 0x0, sum = 4
5273 01:19:01.788087 best_step = 11
5274 01:19:01.788410
5275 01:19:01.788714 ==
5276 01:19:01.790968 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 01:19:01.797404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 01:19:01.797957 ==
5279 01:19:01.798290 RX Vref Scan: 1
5280 01:19:01.798597
5281 01:19:01.800694 RX Vref 0 -> 0, step: 1
5282 01:19:01.801041
5283 01:19:01.804186 RX Delay -77 -> 252, step: 4
5284 01:19:01.804704
5285 01:19:01.807494 Set Vref, RX VrefLevel [Byte0]: 61
5286 01:19:01.810685 [Byte1]: 57
5287 01:19:01.811110
5288 01:19:01.813537 Final RX Vref Byte 0 = 61 to rank0
5289 01:19:01.817027 Final RX Vref Byte 1 = 57 to rank0
5290 01:19:01.819950 Final RX Vref Byte 0 = 61 to rank1
5291 01:19:01.823264 Final RX Vref Byte 1 = 57 to rank1==
5292 01:19:01.827065 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 01:19:01.830024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 01:19:01.830432 ==
5295 01:19:01.833600 DQS Delay:
5296 01:19:01.834008 DQS0 = 0, DQS1 = 0
5297 01:19:01.836841 DQM Delay:
5298 01:19:01.837245 DQM0 = 95, DQM1 = 84
5299 01:19:01.837595 DQ Delay:
5300 01:19:01.840298 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =92
5301 01:19:01.843383 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =108
5302 01:19:01.846373 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
5303 01:19:01.849609 DQ12 =90, DQ13 =88, DQ14 =92, DQ15 =90
5304 01:19:01.850018
5305 01:19:01.853034
5306 01:19:01.860023 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5307 01:19:01.863294 CH0 RK0: MR19=505, MR18=1414
5308 01:19:01.869941 CH0_RK0: MR19=0x505, MR18=0x1414, DQSOSC=415, MR23=63, INC=62, DEC=41
5309 01:19:01.870491
5310 01:19:01.873158 ----->DramcWriteLeveling(PI) begin...
5311 01:19:01.873656 ==
5312 01:19:01.876052 Dram Type= 6, Freq= 0, CH_0, rank 1
5313 01:19:01.880066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 01:19:01.880526 ==
5315 01:19:01.883269 Write leveling (Byte 0): 34 => 34
5316 01:19:01.886478 Write leveling (Byte 1): 28 => 28
5317 01:19:01.889637 DramcWriteLeveling(PI) end<-----
5318 01:19:01.890042
5319 01:19:01.890361 ==
5320 01:19:01.893029 Dram Type= 6, Freq= 0, CH_0, rank 1
5321 01:19:01.896849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 01:19:01.897362 ==
5323 01:19:01.900113 [Gating] SW mode calibration
5324 01:19:01.906362 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5325 01:19:01.913221 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5326 01:19:01.916194 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
5327 01:19:01.919831 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 01:19:01.925829 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 01:19:01.929309 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 01:19:01.932620 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 01:19:01.939506 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 01:19:01.942251 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 01:19:01.945468 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5334 01:19:01.952285 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5335 01:19:01.955362 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 01:19:01.958701 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 01:19:01.965410 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 01:19:01.968859 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 01:19:01.972418 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 01:19:01.979018 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 01:19:01.982283 0 15 28 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
5342 01:19:01.985177 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5343 01:19:01.991738 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 01:19:01.995392 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 01:19:01.998703 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 01:19:02.004948 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 01:19:02.008509 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 01:19:02.012069 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5349 01:19:02.018522 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5350 01:19:02.022089 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5351 01:19:02.025383 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5352 01:19:02.031691 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 01:19:02.034648 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 01:19:02.038158 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 01:19:02.044553 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 01:19:02.047740 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 01:19:02.051240 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 01:19:02.058165 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 01:19:02.061030 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 01:19:02.064697 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 01:19:02.071229 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 01:19:02.074168 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 01:19:02.077449 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 01:19:02.084365 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 01:19:02.087598 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5366 01:19:02.091054 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 01:19:02.094116 Total UI for P1: 0, mck2ui 16
5368 01:19:02.097946 best dqsien dly found for B0: ( 1, 2, 28)
5369 01:19:02.101320 Total UI for P1: 0, mck2ui 16
5370 01:19:02.104143 best dqsien dly found for B1: ( 1, 2, 30)
5371 01:19:02.107731 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5372 01:19:02.110874 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5373 01:19:02.111425
5374 01:19:02.117462 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5375 01:19:02.120562 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5376 01:19:02.124148 [Gating] SW calibration Done
5377 01:19:02.124596 ==
5378 01:19:02.126895 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 01:19:02.130712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 01:19:02.131163 ==
5381 01:19:02.131518 RX Vref Scan: 0
5382 01:19:02.134189
5383 01:19:02.134734 RX Vref 0 -> 0, step: 1
5384 01:19:02.135094
5385 01:19:02.137429 RX Delay -80 -> 252, step: 8
5386 01:19:02.140679 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5387 01:19:02.143899 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5388 01:19:02.150534 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5389 01:19:02.153471 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5390 01:19:02.156870 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5391 01:19:02.160591 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5392 01:19:02.163219 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5393 01:19:02.166638 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5394 01:19:02.173540 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5395 01:19:02.176788 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5396 01:19:02.180251 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5397 01:19:02.183537 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5398 01:19:02.190142 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5399 01:19:02.193038 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5400 01:19:02.196596 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5401 01:19:02.199765 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5402 01:19:02.200216 ==
5403 01:19:02.203502 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 01:19:02.207015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 01:19:02.209619 ==
5406 01:19:02.210072 DQS Delay:
5407 01:19:02.210425 DQS0 = 0, DQS1 = 0
5408 01:19:02.212815 DQM Delay:
5409 01:19:02.213262 DQM0 = 92, DQM1 = 83
5410 01:19:02.216498 DQ Delay:
5411 01:19:02.219839 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5412 01:19:02.223025 DQ4 =91, DQ5 =79, DQ6 =107, DQ7 =107
5413 01:19:02.226315 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5414 01:19:02.229630 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5415 01:19:02.230183
5416 01:19:02.230541
5417 01:19:02.230867 ==
5418 01:19:02.233462 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 01:19:02.236617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 01:19:02.237282 ==
5421 01:19:02.237706
5422 01:19:02.238047
5423 01:19:02.239765 TX Vref Scan disable
5424 01:19:02.240385 == TX Byte 0 ==
5425 01:19:02.245789 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5426 01:19:02.249010 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5427 01:19:02.249465 == TX Byte 1 ==
5428 01:19:02.255810 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5429 01:19:02.259317 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5430 01:19:02.259772 ==
5431 01:19:02.262634 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 01:19:02.265942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 01:19:02.266400 ==
5434 01:19:02.268837
5435 01:19:02.269285
5436 01:19:02.269668 TX Vref Scan disable
5437 01:19:02.272774 == TX Byte 0 ==
5438 01:19:02.275777 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5439 01:19:02.282501 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5440 01:19:02.282958 == TX Byte 1 ==
5441 01:19:02.285389 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5442 01:19:02.292206 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5443 01:19:02.292838
5444 01:19:02.293203 [DATLAT]
5445 01:19:02.293573 Freq=933, CH0 RK1
5446 01:19:02.293920
5447 01:19:02.295567 DATLAT Default: 0xb
5448 01:19:02.299084 0, 0xFFFF, sum = 0
5449 01:19:02.299543 1, 0xFFFF, sum = 0
5450 01:19:02.302127 2, 0xFFFF, sum = 0
5451 01:19:02.302595 3, 0xFFFF, sum = 0
5452 01:19:02.305753 4, 0xFFFF, sum = 0
5453 01:19:02.306337 5, 0xFFFF, sum = 0
5454 01:19:02.308938 6, 0xFFFF, sum = 0
5455 01:19:02.309393 7, 0xFFFF, sum = 0
5456 01:19:02.311774 8, 0xFFFF, sum = 0
5457 01:19:02.312328 9, 0xFFFF, sum = 0
5458 01:19:02.315448 10, 0x0, sum = 1
5459 01:19:02.315960 11, 0x0, sum = 2
5460 01:19:02.318571 12, 0x0, sum = 3
5461 01:19:02.319153 13, 0x0, sum = 4
5462 01:19:02.321971 best_step = 11
5463 01:19:02.322524
5464 01:19:02.323020 ==
5465 01:19:02.325337 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 01:19:02.328634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 01:19:02.329042 ==
5468 01:19:02.329381 RX Vref Scan: 0
5469 01:19:02.329728
5470 01:19:02.332124 RX Vref 0 -> 0, step: 1
5471 01:19:02.332629
5472 01:19:02.335109 RX Delay -77 -> 252, step: 4
5473 01:19:02.342187 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5474 01:19:02.345133 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5475 01:19:02.348397 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5476 01:19:02.351403 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5477 01:19:02.355109 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5478 01:19:02.361566 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5479 01:19:02.365080 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5480 01:19:02.368398 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5481 01:19:02.371267 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5482 01:19:02.374420 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5483 01:19:02.381049 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5484 01:19:02.384667 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5485 01:19:02.388136 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5486 01:19:02.391288 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5487 01:19:02.394212 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5488 01:19:02.401105 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5489 01:19:02.401656 ==
5490 01:19:02.404473 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 01:19:02.408107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 01:19:02.408630 ==
5493 01:19:02.408964 DQS Delay:
5494 01:19:02.410782 DQS0 = 0, DQS1 = 0
5495 01:19:02.411189 DQM Delay:
5496 01:19:02.414527 DQM0 = 92, DQM1 = 84
5497 01:19:02.415063 DQ Delay:
5498 01:19:02.417469 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =90
5499 01:19:02.421293 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5500 01:19:02.424643 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5501 01:19:02.428023 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =92
5502 01:19:02.428598
5503 01:19:02.428928
5504 01:19:02.434819 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5505 01:19:02.437649 CH0 RK1: MR19=505, MR18=2B0E
5506 01:19:02.444154 CH0_RK1: MR19=0x505, MR18=0x2B0E, DQSOSC=408, MR23=63, INC=65, DEC=43
5507 01:19:02.447444 [RxdqsGatingPostProcess] freq 933
5508 01:19:02.453937 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5509 01:19:02.457169 best DQS0 dly(2T, 0.5T) = (0, 11)
5510 01:19:02.461024 best DQS1 dly(2T, 0.5T) = (0, 11)
5511 01:19:02.463877 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5512 01:19:02.467075 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5513 01:19:02.467487 best DQS0 dly(2T, 0.5T) = (0, 10)
5514 01:19:02.470408 best DQS1 dly(2T, 0.5T) = (0, 10)
5515 01:19:02.473968 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5516 01:19:02.476912 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5517 01:19:02.480483 Pre-setting of DQS Precalculation
5518 01:19:02.486724 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5519 01:19:02.487139 ==
5520 01:19:02.490028 Dram Type= 6, Freq= 0, CH_1, rank 0
5521 01:19:02.493288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 01:19:02.493753 ==
5523 01:19:02.500477 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5524 01:19:02.506367 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5525 01:19:02.509825 [CA 0] Center 37 (7~68) winsize 62
5526 01:19:02.513278 [CA 1] Center 37 (7~68) winsize 62
5527 01:19:02.516510 [CA 2] Center 34 (5~64) winsize 60
5528 01:19:02.520034 [CA 3] Center 34 (4~64) winsize 61
5529 01:19:02.523444 [CA 4] Center 34 (5~64) winsize 60
5530 01:19:02.526153 [CA 5] Center 34 (4~64) winsize 61
5531 01:19:02.526566
5532 01:19:02.530195 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5533 01:19:02.530732
5534 01:19:02.533581 [CATrainingPosCal] consider 1 rank data
5535 01:19:02.537048 u2DelayCellTimex100 = 270/100 ps
5536 01:19:02.539848 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5537 01:19:02.543189 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5538 01:19:02.546190 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5539 01:19:02.549451 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5540 01:19:02.553332 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5541 01:19:02.556373 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5542 01:19:02.557072
5543 01:19:02.562684 CA PerBit enable=1, Macro0, CA PI delay=34
5544 01:19:02.563264
5545 01:19:02.563629 [CBTSetCACLKResult] CA Dly = 34
5546 01:19:02.566076 CS Dly: 6 (0~37)
5547 01:19:02.566527 ==
5548 01:19:02.569436 Dram Type= 6, Freq= 0, CH_1, rank 1
5549 01:19:02.572621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 01:19:02.573080 ==
5551 01:19:02.579960 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5552 01:19:02.586223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5553 01:19:02.589402 [CA 0] Center 38 (8~68) winsize 61
5554 01:19:02.593117 [CA 1] Center 37 (7~68) winsize 62
5555 01:19:02.596202 [CA 2] Center 35 (5~65) winsize 61
5556 01:19:02.599109 [CA 3] Center 34 (4~65) winsize 62
5557 01:19:02.602504 [CA 4] Center 35 (5~65) winsize 61
5558 01:19:02.605992 [CA 5] Center 33 (3~64) winsize 62
5559 01:19:02.606445
5560 01:19:02.609456 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5561 01:19:02.609909
5562 01:19:02.613048 [CATrainingPosCal] consider 2 rank data
5563 01:19:02.616121 u2DelayCellTimex100 = 270/100 ps
5564 01:19:02.619243 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5565 01:19:02.622683 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5566 01:19:02.625796 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5567 01:19:02.628976 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5568 01:19:02.632398 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5569 01:19:02.638728 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5570 01:19:02.639245
5571 01:19:02.641998 CA PerBit enable=1, Macro0, CA PI delay=34
5572 01:19:02.642407
5573 01:19:02.645615 [CBTSetCACLKResult] CA Dly = 34
5574 01:19:02.646134 CS Dly: 7 (0~39)
5575 01:19:02.646463
5576 01:19:02.648946 ----->DramcWriteLeveling(PI) begin...
5577 01:19:02.649464 ==
5578 01:19:02.652194 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 01:19:02.658689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 01:19:02.659208 ==
5581 01:19:02.661660 Write leveling (Byte 0): 26 => 26
5582 01:19:02.662075 Write leveling (Byte 1): 27 => 27
5583 01:19:02.665066 DramcWriteLeveling(PI) end<-----
5584 01:19:02.665686
5585 01:19:02.668249 ==
5586 01:19:02.668822 Dram Type= 6, Freq= 0, CH_1, rank 0
5587 01:19:02.674977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 01:19:02.675434 ==
5589 01:19:02.678327 [Gating] SW mode calibration
5590 01:19:02.685142 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5591 01:19:02.688287 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5592 01:19:02.694755 0 14 0 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 1)
5593 01:19:02.697953 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 01:19:02.701506 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 01:19:02.708342 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 01:19:02.711021 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 01:19:02.714268 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 01:19:02.721018 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 01:19:02.724228 0 14 28 | B1->B0 | 3030 3030 | 1 1 | (1 0) (0 0)
5600 01:19:02.727849 0 15 0 | B1->B0 | 2626 2727 | 0 0 | (0 0) (1 0)
5601 01:19:02.734039 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 01:19:02.737448 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 01:19:02.740818 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 01:19:02.747166 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 01:19:02.750729 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 01:19:02.754102 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 01:19:02.760222 0 15 28 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (1 1)
5608 01:19:02.763608 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5609 01:19:02.766874 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 01:19:02.773834 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 01:19:02.777069 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 01:19:02.780191 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 01:19:02.786941 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 01:19:02.790474 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 01:19:02.793271 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5616 01:19:02.800822 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 01:19:02.803544 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 01:19:02.807197 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 01:19:02.813331 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 01:19:02.816377 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 01:19:02.820126 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 01:19:02.826493 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 01:19:02.829836 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 01:19:02.833204 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 01:19:02.840066 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 01:19:02.843393 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 01:19:02.846094 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 01:19:02.853287 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 01:19:02.856421 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 01:19:02.859526 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 01:19:02.866252 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5632 01:19:02.869603 Total UI for P1: 0, mck2ui 16
5633 01:19:02.873153 best dqsien dly found for B1: ( 1, 2, 26)
5634 01:19:02.876048 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 01:19:02.879383 Total UI for P1: 0, mck2ui 16
5636 01:19:02.882722 best dqsien dly found for B0: ( 1, 2, 28)
5637 01:19:02.885938 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5638 01:19:02.889646 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5639 01:19:02.890175
5640 01:19:02.892837 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5641 01:19:02.895698 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5642 01:19:02.898912 [Gating] SW calibration Done
5643 01:19:02.899322 ==
5644 01:19:02.902230 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 01:19:02.909507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 01:19:02.910060 ==
5647 01:19:02.910386 RX Vref Scan: 0
5648 01:19:02.910687
5649 01:19:02.911968 RX Vref 0 -> 0, step: 1
5650 01:19:02.912377
5651 01:19:02.915685 RX Delay -80 -> 252, step: 8
5652 01:19:02.918764 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5653 01:19:02.922066 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5654 01:19:02.925591 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5655 01:19:02.928479 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5656 01:19:02.935439 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5657 01:19:02.938571 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5658 01:19:02.942141 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5659 01:19:02.945260 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5660 01:19:02.948576 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5661 01:19:02.955611 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5662 01:19:02.958372 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5663 01:19:02.961710 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5664 01:19:02.965196 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5665 01:19:02.968525 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5666 01:19:02.975021 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5667 01:19:02.978461 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5668 01:19:02.979256 ==
5669 01:19:02.981574 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 01:19:02.984954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 01:19:02.985411 ==
5672 01:19:02.988173 DQS Delay:
5673 01:19:02.988622 DQS0 = 0, DQS1 = 0
5674 01:19:02.988978 DQM Delay:
5675 01:19:02.991095 DQM0 = 94, DQM1 = 86
5676 01:19:02.991651 DQ Delay:
5677 01:19:02.994279 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5678 01:19:02.997500 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5679 01:19:03.001383 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5680 01:19:03.004699 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5681 01:19:03.005160
5682 01:19:03.005541
5683 01:19:03.005880 ==
5684 01:19:03.007507 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 01:19:03.014299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 01:19:03.014716 ==
5687 01:19:03.015040
5688 01:19:03.015340
5689 01:19:03.017635 TX Vref Scan disable
5690 01:19:03.018060 == TX Byte 0 ==
5691 01:19:03.021021 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5692 01:19:03.027568 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5693 01:19:03.028091 == TX Byte 1 ==
5694 01:19:03.030676 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5695 01:19:03.037796 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5696 01:19:03.038330 ==
5697 01:19:03.040782 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 01:19:03.044321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 01:19:03.044926 ==
5700 01:19:03.045457
5701 01:19:03.045828
5702 01:19:03.047373 TX Vref Scan disable
5703 01:19:03.050790 == TX Byte 0 ==
5704 01:19:03.054123 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5705 01:19:03.057142 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5706 01:19:03.060576 == TX Byte 1 ==
5707 01:19:03.063786 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5708 01:19:03.067515 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5709 01:19:03.068030
5710 01:19:03.070580 [DATLAT]
5711 01:19:03.071140 Freq=933, CH1 RK0
5712 01:19:03.071672
5713 01:19:03.073792 DATLAT Default: 0xd
5714 01:19:03.074223 0, 0xFFFF, sum = 0
5715 01:19:03.077264 1, 0xFFFF, sum = 0
5716 01:19:03.077719 2, 0xFFFF, sum = 0
5717 01:19:03.080726 3, 0xFFFF, sum = 0
5718 01:19:03.081313 4, 0xFFFF, sum = 0
5719 01:19:03.083674 5, 0xFFFF, sum = 0
5720 01:19:03.084264 6, 0xFFFF, sum = 0
5721 01:19:03.087268 7, 0xFFFF, sum = 0
5722 01:19:03.087698 8, 0xFFFF, sum = 0
5723 01:19:03.090540 9, 0xFFFF, sum = 0
5724 01:19:03.090954 10, 0x0, sum = 1
5725 01:19:03.094064 11, 0x0, sum = 2
5726 01:19:03.094479 12, 0x0, sum = 3
5727 01:19:03.097268 13, 0x0, sum = 4
5728 01:19:03.097726 best_step = 11
5729 01:19:03.098070
5730 01:19:03.098369 ==
5731 01:19:03.100260 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 01:19:03.104266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 01:19:03.107188 ==
5734 01:19:03.107601 RX Vref Scan: 1
5735 01:19:03.107923
5736 01:19:03.110560 RX Vref 0 -> 0, step: 1
5737 01:19:03.111069
5738 01:19:03.113676 RX Delay -69 -> 252, step: 4
5739 01:19:03.114187
5740 01:19:03.116790 Set Vref, RX VrefLevel [Byte0]: 55
5741 01:19:03.120318 [Byte1]: 47
5742 01:19:03.120749
5743 01:19:03.123992 Final RX Vref Byte 0 = 55 to rank0
5744 01:19:03.126864 Final RX Vref Byte 1 = 47 to rank0
5745 01:19:03.129812 Final RX Vref Byte 0 = 55 to rank1
5746 01:19:03.133313 Final RX Vref Byte 1 = 47 to rank1==
5747 01:19:03.136407 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 01:19:03.140112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 01:19:03.140624 ==
5750 01:19:03.143538 DQS Delay:
5751 01:19:03.144051 DQS0 = 0, DQS1 = 0
5752 01:19:03.144377 DQM Delay:
5753 01:19:03.146234 DQM0 = 96, DQM1 = 87
5754 01:19:03.146643 DQ Delay:
5755 01:19:03.149679 DQ0 =100, DQ1 =94, DQ2 =84, DQ3 =94
5756 01:19:03.153577 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =94
5757 01:19:03.156390 DQ8 =74, DQ9 =78, DQ10 =90, DQ11 =82
5758 01:19:03.159948 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5759 01:19:03.160458
5760 01:19:03.160782
5761 01:19:03.170103 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5762 01:19:03.173300 CH1 RK0: MR19=405, MR18=FE07
5763 01:19:03.179204 CH1_RK0: MR19=0x405, MR18=0xFE07, DQSOSC=419, MR23=63, INC=61, DEC=41
5764 01:19:03.179662
5765 01:19:03.182720 ----->DramcWriteLeveling(PI) begin...
5766 01:19:03.183136 ==
5767 01:19:03.185867 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 01:19:03.189368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 01:19:03.190001 ==
5770 01:19:03.192419 Write leveling (Byte 0): 23 => 23
5771 01:19:03.195671 Write leveling (Byte 1): 26 => 26
5772 01:19:03.199288 DramcWriteLeveling(PI) end<-----
5773 01:19:03.199753
5774 01:19:03.200076 ==
5775 01:19:03.202718 Dram Type= 6, Freq= 0, CH_1, rank 1
5776 01:19:03.205687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 01:19:03.206104 ==
5778 01:19:03.208921 [Gating] SW mode calibration
5779 01:19:03.215595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5780 01:19:03.222375 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5781 01:19:03.225287 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 01:19:03.228738 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 01:19:03.235706 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 01:19:03.238540 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 01:19:03.241923 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 01:19:03.248467 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 01:19:03.251765 0 14 24 | B1->B0 | 3333 3030 | 1 0 | (1 1) (0 1)
5788 01:19:03.255120 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5789 01:19:03.261723 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5790 01:19:03.265311 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 01:19:03.268477 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 01:19:03.275128 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 01:19:03.278352 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 01:19:03.281610 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 01:19:03.288646 0 15 24 | B1->B0 | 2424 3232 | 0 1 | (0 0) (0 0)
5796 01:19:03.291660 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5797 01:19:03.294721 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 01:19:03.301135 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 01:19:03.304675 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 01:19:03.307766 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 01:19:03.314602 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 01:19:03.317689 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 01:19:03.321319 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5804 01:19:03.328190 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5805 01:19:03.331049 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 01:19:03.334616 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 01:19:03.340901 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 01:19:03.344121 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 01:19:03.347465 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 01:19:03.354368 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 01:19:03.357617 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 01:19:03.360892 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 01:19:03.367608 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 01:19:03.370358 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 01:19:03.374092 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 01:19:03.380227 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 01:19:03.383573 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 01:19:03.386930 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5819 01:19:03.393251 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5820 01:19:03.396592 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5821 01:19:03.400440 Total UI for P1: 0, mck2ui 16
5822 01:19:03.403503 best dqsien dly found for B0: ( 1, 2, 22)
5823 01:19:03.406630 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 01:19:03.409858 Total UI for P1: 0, mck2ui 16
5825 01:19:03.413301 best dqsien dly found for B1: ( 1, 2, 28)
5826 01:19:03.416771 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5827 01:19:03.419720 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5828 01:19:03.423302
5829 01:19:03.426604 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5830 01:19:03.429857 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5831 01:19:03.433123 [Gating] SW calibration Done
5832 01:19:03.433359 ==
5833 01:19:03.436448 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 01:19:03.440067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 01:19:03.440343 ==
5836 01:19:03.440557 RX Vref Scan: 0
5837 01:19:03.442688
5838 01:19:03.442890 RX Vref 0 -> 0, step: 1
5839 01:19:03.443084
5840 01:19:03.446137 RX Delay -80 -> 252, step: 8
5841 01:19:03.449584 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5842 01:19:03.453282 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5843 01:19:03.459608 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5844 01:19:03.463026 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5845 01:19:03.466449 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5846 01:19:03.469493 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5847 01:19:03.472529 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5848 01:19:03.479090 iDelay=208, Bit 7, Center 87 (-16 ~ 191) 208
5849 01:19:03.482490 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5850 01:19:03.485683 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5851 01:19:03.489036 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5852 01:19:03.492763 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5853 01:19:03.499627 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5854 01:19:03.502582 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5855 01:19:03.505625 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5856 01:19:03.509209 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5857 01:19:03.509399 ==
5858 01:19:03.512181 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 01:19:03.515680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 01:19:03.515927 ==
5861 01:19:03.518769 DQS Delay:
5862 01:19:03.518965 DQS0 = 0, DQS1 = 0
5863 01:19:03.522465 DQM Delay:
5864 01:19:03.522749 DQM0 = 92, DQM1 = 88
5865 01:19:03.526221 DQ Delay:
5866 01:19:03.526558 DQ0 =99, DQ1 =87, DQ2 =79, DQ3 =87
5867 01:19:03.529260 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5868 01:19:03.532645 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5869 01:19:03.535851 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5870 01:19:03.539602
5871 01:19:03.540147
5872 01:19:03.540506 ==
5873 01:19:03.542196 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 01:19:03.545637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 01:19:03.546096 ==
5876 01:19:03.546455
5877 01:19:03.546784
5878 01:19:03.549241 TX Vref Scan disable
5879 01:19:03.549848 == TX Byte 0 ==
5880 01:19:03.555980 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5881 01:19:03.558760 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5882 01:19:03.559217 == TX Byte 1 ==
5883 01:19:03.565531 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5884 01:19:03.568536 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5885 01:19:03.568998 ==
5886 01:19:03.571846 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 01:19:03.575622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 01:19:03.576179 ==
5889 01:19:03.576538
5890 01:19:03.576868
5891 01:19:03.578843 TX Vref Scan disable
5892 01:19:03.581640 == TX Byte 0 ==
5893 01:19:03.584835 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5894 01:19:03.588706 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5895 01:19:03.592017 == TX Byte 1 ==
5896 01:19:03.595431 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5897 01:19:03.598260 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5898 01:19:03.601541
5899 01:19:03.602028 [DATLAT]
5900 01:19:03.602388 Freq=933, CH1 RK1
5901 01:19:03.602722
5902 01:19:03.604857 DATLAT Default: 0xb
5903 01:19:03.605310 0, 0xFFFF, sum = 0
5904 01:19:03.608398 1, 0xFFFF, sum = 0
5905 01:19:03.608858 2, 0xFFFF, sum = 0
5906 01:19:03.611297 3, 0xFFFF, sum = 0
5907 01:19:03.611891 4, 0xFFFF, sum = 0
5908 01:19:03.614755 5, 0xFFFF, sum = 0
5909 01:19:03.615214 6, 0xFFFF, sum = 0
5910 01:19:03.618408 7, 0xFFFF, sum = 0
5911 01:19:03.621954 8, 0xFFFF, sum = 0
5912 01:19:03.622415 9, 0xFFFF, sum = 0
5913 01:19:03.624589 10, 0x0, sum = 1
5914 01:19:03.625003 11, 0x0, sum = 2
5915 01:19:03.625333 12, 0x0, sum = 3
5916 01:19:03.627989 13, 0x0, sum = 4
5917 01:19:03.628448 best_step = 11
5918 01:19:03.628773
5919 01:19:03.629073 ==
5920 01:19:03.631474 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 01:19:03.638071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 01:19:03.638389 ==
5923 01:19:03.638623 RX Vref Scan: 0
5924 01:19:03.638807
5925 01:19:03.640759 RX Vref 0 -> 0, step: 1
5926 01:19:03.640979
5927 01:19:03.644449 RX Delay -69 -> 252, step: 4
5928 01:19:03.647624 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5929 01:19:03.654594 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5930 01:19:03.657357 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5931 01:19:03.661247 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5932 01:19:03.664538 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5933 01:19:03.667679 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5934 01:19:03.673774 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5935 01:19:03.677688 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5936 01:19:03.680616 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5937 01:19:03.684476 iDelay=203, Bit 9, Center 84 (-9 ~ 178) 188
5938 01:19:03.687406 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5939 01:19:03.690727 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5940 01:19:03.697429 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5941 01:19:03.700717 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5942 01:19:03.704181 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5943 01:19:03.707215 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5944 01:19:03.707675 ==
5945 01:19:03.710894 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 01:19:03.717574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 01:19:03.718137 ==
5948 01:19:03.718520 DQS Delay:
5949 01:19:03.718857 DQS0 = 0, DQS1 = 0
5950 01:19:03.720279 DQM Delay:
5951 01:19:03.720734 DQM0 = 91, DQM1 = 91
5952 01:19:03.723575 DQ Delay:
5953 01:19:03.727114 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5954 01:19:03.730195 DQ4 =90, DQ5 =102, DQ6 =102, DQ7 =88
5955 01:19:03.733368 DQ8 =78, DQ9 =84, DQ10 =94, DQ11 =82
5956 01:19:03.737068 DQ12 =98, DQ13 =98, DQ14 =100, DQ15 =96
5957 01:19:03.737548
5958 01:19:03.737914
5959 01:19:03.743454 [DQSOSCAuto] RK1, (LSB)MR18= 0x91c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 419 ps
5960 01:19:03.746692 CH1 RK1: MR19=505, MR18=91C
5961 01:19:03.753704 CH1_RK1: MR19=0x505, MR18=0x91C, DQSOSC=412, MR23=63, INC=63, DEC=42
5962 01:19:03.756521 [RxdqsGatingPostProcess] freq 933
5963 01:19:03.759920 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5964 01:19:03.763500 best DQS0 dly(2T, 0.5T) = (0, 10)
5965 01:19:03.766423 best DQS1 dly(2T, 0.5T) = (0, 10)
5966 01:19:03.770139 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5967 01:19:03.773576 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5968 01:19:03.776615 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 01:19:03.779774 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 01:19:03.783032 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 01:19:03.786257 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 01:19:03.789715 Pre-setting of DQS Precalculation
5973 01:19:03.793143 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5974 01:19:03.802942 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5975 01:19:03.809637 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5976 01:19:03.810187
5977 01:19:03.810547
5978 01:19:03.812831 [Calibration Summary] 1866 Mbps
5979 01:19:03.813386 CH 0, Rank 0
5980 01:19:03.816058 SW Impedance : PASS
5981 01:19:03.816526 DUTY Scan : NO K
5982 01:19:03.819223 ZQ Calibration : PASS
5983 01:19:03.822721 Jitter Meter : NO K
5984 01:19:03.823392 CBT Training : PASS
5985 01:19:03.826068 Write leveling : PASS
5986 01:19:03.829141 RX DQS gating : PASS
5987 01:19:03.829634 RX DQ/DQS(RDDQC) : PASS
5988 01:19:03.832301 TX DQ/DQS : PASS
5989 01:19:03.835661 RX DATLAT : PASS
5990 01:19:03.836084 RX DQ/DQS(Engine): PASS
5991 01:19:03.838960 TX OE : NO K
5992 01:19:03.839387 All Pass.
5993 01:19:03.839810
5994 01:19:03.842590 CH 0, Rank 1
5995 01:19:03.843141 SW Impedance : PASS
5996 01:19:03.845504 DUTY Scan : NO K
5997 01:19:03.848873 ZQ Calibration : PASS
5998 01:19:03.849308 Jitter Meter : NO K
5999 01:19:03.852500 CBT Training : PASS
6000 01:19:03.855456 Write leveling : PASS
6001 01:19:03.855898 RX DQS gating : PASS
6002 01:19:03.859098 RX DQ/DQS(RDDQC) : PASS
6003 01:19:03.862657 TX DQ/DQS : PASS
6004 01:19:03.863180 RX DATLAT : PASS
6005 01:19:03.866112 RX DQ/DQS(Engine): PASS
6006 01:19:03.868612 TX OE : NO K
6007 01:19:03.869154 All Pass.
6008 01:19:03.869721
6009 01:19:03.870134 CH 1, Rank 0
6010 01:19:03.871739 SW Impedance : PASS
6011 01:19:03.875617 DUTY Scan : NO K
6012 01:19:03.876170 ZQ Calibration : PASS
6013 01:19:03.878376 Jitter Meter : NO K
6014 01:19:03.882224 CBT Training : PASS
6015 01:19:03.882650 Write leveling : PASS
6016 01:19:03.885040 RX DQS gating : PASS
6017 01:19:03.885477 RX DQ/DQS(RDDQC) : PASS
6018 01:19:03.888377 TX DQ/DQS : PASS
6019 01:19:03.891828 RX DATLAT : PASS
6020 01:19:03.892271 RX DQ/DQS(Engine): PASS
6021 01:19:03.895516 TX OE : NO K
6022 01:19:03.895934 All Pass.
6023 01:19:03.896260
6024 01:19:03.898195 CH 1, Rank 1
6025 01:19:03.898787 SW Impedance : PASS
6026 01:19:03.902024 DUTY Scan : NO K
6027 01:19:03.905283 ZQ Calibration : PASS
6028 01:19:03.905809 Jitter Meter : NO K
6029 01:19:03.908449 CBT Training : PASS
6030 01:19:03.912035 Write leveling : PASS
6031 01:19:03.912572 RX DQS gating : PASS
6032 01:19:03.915226 RX DQ/DQS(RDDQC) : PASS
6033 01:19:03.918599 TX DQ/DQS : PASS
6034 01:19:03.919037 RX DATLAT : PASS
6035 01:19:03.922030 RX DQ/DQS(Engine): PASS
6036 01:19:03.925355 TX OE : NO K
6037 01:19:03.925831 All Pass.
6038 01:19:03.926257
6039 01:19:03.926658 DramC Write-DBI off
6040 01:19:03.928529 PER_BANK_REFRESH: Hybrid Mode
6041 01:19:03.932078 TX_TRACKING: ON
6042 01:19:03.938130 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6043 01:19:03.941688 [FAST_K] Save calibration result to emmc
6044 01:19:03.948006 dramc_set_vcore_voltage set vcore to 650000
6045 01:19:03.948552 Read voltage for 400, 6
6046 01:19:03.951807 Vio18 = 0
6047 01:19:03.952249 Vcore = 650000
6048 01:19:03.952705 Vdram = 0
6049 01:19:03.954733 Vddq = 0
6050 01:19:03.955193 Vmddr = 0
6051 01:19:03.958249 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6052 01:19:03.965111 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6053 01:19:03.967979 MEM_TYPE=3, freq_sel=20
6054 01:19:03.971022 sv_algorithm_assistance_LP4_800
6055 01:19:03.974516 ============ PULL DRAM RESETB DOWN ============
6056 01:19:03.977622 ========== PULL DRAM RESETB DOWN end =========
6057 01:19:03.984273 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6058 01:19:03.987772 ===================================
6059 01:19:03.988187 LPDDR4 DRAM CONFIGURATION
6060 01:19:03.991109 ===================================
6061 01:19:03.994599 EX_ROW_EN[0] = 0x0
6062 01:19:03.995014 EX_ROW_EN[1] = 0x0
6063 01:19:03.997386 LP4Y_EN = 0x0
6064 01:19:04.000779 WORK_FSP = 0x0
6065 01:19:04.001193 WL = 0x2
6066 01:19:04.003858 RL = 0x2
6067 01:19:04.004269 BL = 0x2
6068 01:19:04.007274 RPST = 0x0
6069 01:19:04.007688 RD_PRE = 0x0
6070 01:19:04.010694 WR_PRE = 0x1
6071 01:19:04.011107 WR_PST = 0x0
6072 01:19:04.014203 DBI_WR = 0x0
6073 01:19:04.014496 DBI_RD = 0x0
6074 01:19:04.016961 OTF = 0x1
6075 01:19:04.020514 ===================================
6076 01:19:04.024022 ===================================
6077 01:19:04.024568 ANA top config
6078 01:19:04.027712 ===================================
6079 01:19:04.030358 DLL_ASYNC_EN = 0
6080 01:19:04.034103 ALL_SLAVE_EN = 1
6081 01:19:04.034410 NEW_RANK_MODE = 1
6082 01:19:04.037160 DLL_IDLE_MODE = 1
6083 01:19:04.040487 LP45_APHY_COMB_EN = 1
6084 01:19:04.043856 TX_ODT_DIS = 1
6085 01:19:04.047133 NEW_8X_MODE = 1
6086 01:19:04.050403 ===================================
6087 01:19:04.053619 ===================================
6088 01:19:04.054168 data_rate = 800
6089 01:19:04.056791 CKR = 1
6090 01:19:04.060338 DQ_P2S_RATIO = 4
6091 01:19:04.063923 ===================================
6092 01:19:04.066548 CA_P2S_RATIO = 4
6093 01:19:04.069871 DQ_CA_OPEN = 0
6094 01:19:04.073362 DQ_SEMI_OPEN = 1
6095 01:19:04.076563 CA_SEMI_OPEN = 1
6096 01:19:04.077014 CA_FULL_RATE = 0
6097 01:19:04.080034 DQ_CKDIV4_EN = 0
6098 01:19:04.083326 CA_CKDIV4_EN = 1
6099 01:19:04.086485 CA_PREDIV_EN = 0
6100 01:19:04.090012 PH8_DLY = 0
6101 01:19:04.092979 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6102 01:19:04.093443 DQ_AAMCK_DIV = 0
6103 01:19:04.096146 CA_AAMCK_DIV = 0
6104 01:19:04.099386 CA_ADMCK_DIV = 4
6105 01:19:04.102742 DQ_TRACK_CA_EN = 0
6106 01:19:04.106096 CA_PICK = 800
6107 01:19:04.109450 CA_MCKIO = 400
6108 01:19:04.112757 MCKIO_SEMI = 400
6109 01:19:04.113039 PLL_FREQ = 3016
6110 01:19:04.116233 DQ_UI_PI_RATIO = 32
6111 01:19:04.119717 CA_UI_PI_RATIO = 32
6112 01:19:04.122496 ===================================
6113 01:19:04.125875 ===================================
6114 01:19:04.129080 memory_type:LPDDR4
6115 01:19:04.132573 GP_NUM : 10
6116 01:19:04.132847 SRAM_EN : 1
6117 01:19:04.135669 MD32_EN : 0
6118 01:19:04.139173 ===================================
6119 01:19:04.139677 [ANA_INIT] >>>>>>>>>>>>>>
6120 01:19:04.142883 <<<<<< [CONFIGURE PHASE]: ANA_TX
6121 01:19:04.146050 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6122 01:19:04.149383 ===================================
6123 01:19:04.152345 data_rate = 800,PCW = 0X7400
6124 01:19:04.156071 ===================================
6125 01:19:04.159129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6126 01:19:04.166139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 01:19:04.175824 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6128 01:19:04.182562 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6129 01:19:04.185421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6130 01:19:04.188907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6131 01:19:04.189223 [ANA_INIT] flow start
6132 01:19:04.192213 [ANA_INIT] PLL >>>>>>>>
6133 01:19:04.195946 [ANA_INIT] PLL <<<<<<<<
6134 01:19:04.196191 [ANA_INIT] MIDPI >>>>>>>>
6135 01:19:04.198454 [ANA_INIT] MIDPI <<<<<<<<
6136 01:19:04.201667 [ANA_INIT] DLL >>>>>>>>
6137 01:19:04.201852 [ANA_INIT] flow end
6138 01:19:04.208533 ============ LP4 DIFF to SE enter ============
6139 01:19:04.211821 ============ LP4 DIFF to SE exit ============
6140 01:19:04.215510 [ANA_INIT] <<<<<<<<<<<<<
6141 01:19:04.218371 [Flow] Enable top DCM control >>>>>
6142 01:19:04.221683 [Flow] Enable top DCM control <<<<<
6143 01:19:04.225118 Enable DLL master slave shuffle
6144 01:19:04.229060 ==============================================================
6145 01:19:04.231812 Gating Mode config
6146 01:19:04.235287 ==============================================================
6147 01:19:04.238708 Config description:
6148 01:19:04.248585 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6149 01:19:04.255086 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6150 01:19:04.258654 SELPH_MODE 0: By rank 1: By Phase
6151 01:19:04.265331 ==============================================================
6152 01:19:04.268516 GAT_TRACK_EN = 0
6153 01:19:04.272030 RX_GATING_MODE = 2
6154 01:19:04.275223 RX_GATING_TRACK_MODE = 2
6155 01:19:04.278561 SELPH_MODE = 1
6156 01:19:04.281863 PICG_EARLY_EN = 1
6157 01:19:04.282314 VALID_LAT_VALUE = 1
6158 01:19:04.288876 ==============================================================
6159 01:19:04.292240 Enter into Gating configuration >>>>
6160 01:19:04.294770 Exit from Gating configuration <<<<
6161 01:19:04.298329 Enter into DVFS_PRE_config >>>>>
6162 01:19:04.308610 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6163 01:19:04.311759 Exit from DVFS_PRE_config <<<<<
6164 01:19:04.314433 Enter into PICG configuration >>>>
6165 01:19:04.318082 Exit from PICG configuration <<<<
6166 01:19:04.321120 [RX_INPUT] configuration >>>>>
6167 01:19:04.324389 [RX_INPUT] configuration <<<<<
6168 01:19:04.331147 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6169 01:19:04.334935 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6170 01:19:04.341033 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6171 01:19:04.347987 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6172 01:19:04.354710 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6173 01:19:04.360925 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6174 01:19:04.364647 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6175 01:19:04.367770 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6176 01:19:04.370908 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6177 01:19:04.377704 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6178 01:19:04.381091 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6179 01:19:04.384337 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 01:19:04.387508 ===================================
6181 01:19:04.390815 LPDDR4 DRAM CONFIGURATION
6182 01:19:04.394109 ===================================
6183 01:19:04.394571 EX_ROW_EN[0] = 0x0
6184 01:19:04.397363 EX_ROW_EN[1] = 0x0
6185 01:19:04.401153 LP4Y_EN = 0x0
6186 01:19:04.401762 WORK_FSP = 0x0
6187 01:19:04.404421 WL = 0x2
6188 01:19:04.404981 RL = 0x2
6189 01:19:04.407444 BL = 0x2
6190 01:19:04.408018 RPST = 0x0
6191 01:19:04.410558 RD_PRE = 0x0
6192 01:19:04.411022 WR_PRE = 0x1
6193 01:19:04.414079 WR_PST = 0x0
6194 01:19:04.414542 DBI_WR = 0x0
6195 01:19:04.417685 DBI_RD = 0x0
6196 01:19:04.418249 OTF = 0x1
6197 01:19:04.420758 ===================================
6198 01:19:04.424284 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6199 01:19:04.431039 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6200 01:19:04.433859 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6201 01:19:04.437238 ===================================
6202 01:19:04.440647 LPDDR4 DRAM CONFIGURATION
6203 01:19:04.443572 ===================================
6204 01:19:04.444048 EX_ROW_EN[0] = 0x10
6205 01:19:04.447261 EX_ROW_EN[1] = 0x0
6206 01:19:04.450133 LP4Y_EN = 0x0
6207 01:19:04.450594 WORK_FSP = 0x0
6208 01:19:04.454014 WL = 0x2
6209 01:19:04.454567 RL = 0x2
6210 01:19:04.456832 BL = 0x2
6211 01:19:04.457291 RPST = 0x0
6212 01:19:04.460412 RD_PRE = 0x0
6213 01:19:04.461014 WR_PRE = 0x1
6214 01:19:04.463614 WR_PST = 0x0
6215 01:19:04.464077 DBI_WR = 0x0
6216 01:19:04.466754 DBI_RD = 0x0
6217 01:19:04.467212 OTF = 0x1
6218 01:19:04.470531 ===================================
6219 01:19:04.476743 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6220 01:19:04.481193 nWR fixed to 30
6221 01:19:04.484819 [ModeRegInit_LP4] CH0 RK0
6222 01:19:04.485359 [ModeRegInit_LP4] CH0 RK1
6223 01:19:04.487811 [ModeRegInit_LP4] CH1 RK0
6224 01:19:04.491046 [ModeRegInit_LP4] CH1 RK1
6225 01:19:04.491499 match AC timing 19
6226 01:19:04.497691 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6227 01:19:04.500833 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6228 01:19:04.504376 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6229 01:19:04.511124 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6230 01:19:04.514423 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6231 01:19:04.514879 ==
6232 01:19:04.517693 Dram Type= 6, Freq= 0, CH_0, rank 0
6233 01:19:04.521342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6234 01:19:04.521837 ==
6235 01:19:04.527865 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6236 01:19:04.534651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6237 01:19:04.537264 [CA 0] Center 36 (8~64) winsize 57
6238 01:19:04.541432 [CA 1] Center 36 (8~64) winsize 57
6239 01:19:04.544202 [CA 2] Center 36 (8~64) winsize 57
6240 01:19:04.548131 [CA 3] Center 36 (8~64) winsize 57
6241 01:19:04.548687 [CA 4] Center 36 (8~64) winsize 57
6242 01:19:04.550868 [CA 5] Center 36 (8~64) winsize 57
6243 01:19:04.551417
6244 01:19:04.557607 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6245 01:19:04.558159
6246 01:19:04.561238 [CATrainingPosCal] consider 1 rank data
6247 01:19:04.563852 u2DelayCellTimex100 = 270/100 ps
6248 01:19:04.567335 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 01:19:04.570707 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 01:19:04.574106 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 01:19:04.577311 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 01:19:04.580469 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 01:19:04.584020 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 01:19:04.584473
6255 01:19:04.587019 CA PerBit enable=1, Macro0, CA PI delay=36
6256 01:19:04.587499
6257 01:19:04.590415 [CBTSetCACLKResult] CA Dly = 36
6258 01:19:04.593627 CS Dly: 1 (0~32)
6259 01:19:04.594120 ==
6260 01:19:04.596893 Dram Type= 6, Freq= 0, CH_0, rank 1
6261 01:19:04.600103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 01:19:04.600566 ==
6263 01:19:04.606748 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6264 01:19:04.613900 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6265 01:19:04.616937 [CA 0] Center 36 (8~64) winsize 57
6266 01:19:04.617400 [CA 1] Center 36 (8~64) winsize 57
6267 01:19:04.620258 [CA 2] Center 36 (8~64) winsize 57
6268 01:19:04.623668 [CA 3] Center 36 (8~64) winsize 57
6269 01:19:04.627152 [CA 4] Center 36 (8~64) winsize 57
6270 01:19:04.630111 [CA 5] Center 36 (8~64) winsize 57
6271 01:19:04.630672
6272 01:19:04.633368 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6273 01:19:04.633866
6274 01:19:04.639853 [CATrainingPosCal] consider 2 rank data
6275 01:19:04.640317 u2DelayCellTimex100 = 270/100 ps
6276 01:19:04.646735 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 01:19:04.650062 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 01:19:04.653617 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 01:19:04.656938 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 01:19:04.660229 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 01:19:04.663676 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 01:19:04.664231
6283 01:19:04.666444 CA PerBit enable=1, Macro0, CA PI delay=36
6284 01:19:04.667004
6285 01:19:04.669993 [CBTSetCACLKResult] CA Dly = 36
6286 01:19:04.673337 CS Dly: 1 (0~32)
6287 01:19:04.673879
6288 01:19:04.676313 ----->DramcWriteLeveling(PI) begin...
6289 01:19:04.676781 ==
6290 01:19:04.679536 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 01:19:04.682627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 01:19:04.683092 ==
6293 01:19:04.686158 Write leveling (Byte 0): 40 => 8
6294 01:19:04.689576 Write leveling (Byte 1): 40 => 8
6295 01:19:04.692747 DramcWriteLeveling(PI) end<-----
6296 01:19:04.693202
6297 01:19:04.693640 ==
6298 01:19:04.696139 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 01:19:04.699577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 01:19:04.700071 ==
6301 01:19:04.702930 [Gating] SW mode calibration
6302 01:19:04.709613 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6303 01:19:04.716010 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6304 01:19:04.719092 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 01:19:04.722604 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6306 01:19:04.728780 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 01:19:04.732004 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 01:19:04.735804 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 01:19:04.742252 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 01:19:04.746057 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 01:19:04.749043 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 01:19:04.755661 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 01:19:04.759117 Total UI for P1: 0, mck2ui 16
6314 01:19:04.761978 best dqsien dly found for B0: ( 0, 14, 24)
6315 01:19:04.762397 Total UI for P1: 0, mck2ui 16
6316 01:19:04.768821 best dqsien dly found for B1: ( 0, 14, 24)
6317 01:19:04.772102 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6318 01:19:04.775432 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6319 01:19:04.775942
6320 01:19:04.778758 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 01:19:04.781716 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6322 01:19:04.785393 [Gating] SW calibration Done
6323 01:19:04.785953 ==
6324 01:19:04.788260 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 01:19:04.791687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 01:19:04.792103 ==
6327 01:19:04.794930 RX Vref Scan: 0
6328 01:19:04.795342
6329 01:19:04.798370 RX Vref 0 -> 0, step: 1
6330 01:19:04.798784
6331 01:19:04.799109 RX Delay -410 -> 252, step: 16
6332 01:19:04.805175 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6333 01:19:04.808415 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6334 01:19:04.811806 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6335 01:19:04.818458 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6336 01:19:04.821339 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6337 01:19:04.824393 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6338 01:19:04.827771 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6339 01:19:04.834514 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6340 01:19:04.837692 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6341 01:19:04.841274 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6342 01:19:04.844279 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6343 01:19:04.851477 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6344 01:19:04.854587 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6345 01:19:04.857728 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6346 01:19:04.861334 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6347 01:19:04.868175 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6348 01:19:04.868727 ==
6349 01:19:04.870781 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 01:19:04.874421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 01:19:04.874974 ==
6352 01:19:04.875661 DQS Delay:
6353 01:19:04.878099 DQS0 = 59, DQS1 = 59
6354 01:19:04.878646 DQM Delay:
6355 01:19:04.881340 DQM0 = 17, DQM1 = 10
6356 01:19:04.881944 DQ Delay:
6357 01:19:04.884125 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6358 01:19:04.887616 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6359 01:19:04.890999 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6360 01:19:04.894265 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6361 01:19:04.894924
6362 01:19:04.895508
6363 01:19:04.895874 ==
6364 01:19:04.897636 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 01:19:04.901017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 01:19:04.903898 ==
6367 01:19:04.904353
6368 01:19:04.904711
6369 01:19:04.905047 TX Vref Scan disable
6370 01:19:04.907264 == TX Byte 0 ==
6371 01:19:04.911018 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 01:19:04.914319 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 01:19:04.917152 == TX Byte 1 ==
6374 01:19:04.920435 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 01:19:04.923780 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 01:19:04.924306 ==
6377 01:19:04.927355 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 01:19:04.933645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 01:19:04.934110 ==
6380 01:19:04.934472
6381 01:19:04.934806
6382 01:19:04.935123 TX Vref Scan disable
6383 01:19:04.937008 == TX Byte 0 ==
6384 01:19:04.940756 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 01:19:04.943597 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 01:19:04.947158 == TX Byte 1 ==
6387 01:19:04.950350 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 01:19:04.953442 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 01:19:04.954059
6390 01:19:04.956875 [DATLAT]
6391 01:19:04.957572 Freq=400, CH0 RK0
6392 01:19:04.958009
6393 01:19:04.959882 DATLAT Default: 0xf
6394 01:19:04.960434 0, 0xFFFF, sum = 0
6395 01:19:04.963227 1, 0xFFFF, sum = 0
6396 01:19:04.963720 2, 0xFFFF, sum = 0
6397 01:19:04.966484 3, 0xFFFF, sum = 0
6398 01:19:04.966946 4, 0xFFFF, sum = 0
6399 01:19:04.969872 5, 0xFFFF, sum = 0
6400 01:19:04.970404 6, 0xFFFF, sum = 0
6401 01:19:04.973152 7, 0xFFFF, sum = 0
6402 01:19:04.973890 8, 0xFFFF, sum = 0
6403 01:19:04.976800 9, 0xFFFF, sum = 0
6404 01:19:04.977449 10, 0xFFFF, sum = 0
6405 01:19:04.980079 11, 0xFFFF, sum = 0
6406 01:19:04.983375 12, 0xFFFF, sum = 0
6407 01:19:04.983795 13, 0x0, sum = 1
6408 01:19:04.986916 14, 0x0, sum = 2
6409 01:19:04.987445 15, 0x0, sum = 3
6410 01:19:04.987786 16, 0x0, sum = 4
6411 01:19:04.990037 best_step = 14
6412 01:19:04.990450
6413 01:19:04.990777 ==
6414 01:19:04.992849 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 01:19:04.996592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 01:19:04.997015 ==
6417 01:19:04.999705 RX Vref Scan: 1
6418 01:19:05.000187
6419 01:19:05.000526 RX Vref 0 -> 0, step: 1
6420 01:19:05.003072
6421 01:19:05.003558 RX Delay -359 -> 252, step: 8
6422 01:19:05.003896
6423 01:19:05.006361 Set Vref, RX VrefLevel [Byte0]: 61
6424 01:19:05.009773 [Byte1]: 57
6425 01:19:05.014870
6426 01:19:05.015460 Final RX Vref Byte 0 = 61 to rank0
6427 01:19:05.018417 Final RX Vref Byte 1 = 57 to rank0
6428 01:19:05.021947 Final RX Vref Byte 0 = 61 to rank1
6429 01:19:05.025036 Final RX Vref Byte 1 = 57 to rank1==
6430 01:19:05.028184 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 01:19:05.034619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 01:19:05.035117 ==
6433 01:19:05.035452 DQS Delay:
6434 01:19:05.037816 DQS0 = 60, DQS1 = 68
6435 01:19:05.038217 DQM Delay:
6436 01:19:05.038544 DQM0 = 14, DQM1 = 14
6437 01:19:05.041750 DQ Delay:
6438 01:19:05.044742 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6439 01:19:05.048137 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6440 01:19:05.048553 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6441 01:19:05.054658 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6442 01:19:05.055290
6443 01:19:05.055850
6444 01:19:05.061235 [DQSOSCAuto] RK0, (LSB)MR18= 0x7d7b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
6445 01:19:05.064565 CH0 RK0: MR19=C0C, MR18=7D7B
6446 01:19:05.071391 CH0_RK0: MR19=0xC0C, MR18=0x7D7B, DQSOSC=394, MR23=63, INC=380, DEC=253
6447 01:19:05.071948 ==
6448 01:19:05.074532 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 01:19:05.077896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 01:19:05.078439 ==
6451 01:19:05.080865 [Gating] SW mode calibration
6452 01:19:05.087746 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6453 01:19:05.094130 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6454 01:19:05.097899 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 01:19:05.101141 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6456 01:19:05.107669 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 01:19:05.111419 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 01:19:05.114685 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 01:19:05.121469 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 01:19:05.124918 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 01:19:05.127794 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 01:19:05.130835 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 01:19:05.134283 Total UI for P1: 0, mck2ui 16
6464 01:19:05.137998 best dqsien dly found for B0: ( 0, 14, 24)
6465 01:19:05.141401 Total UI for P1: 0, mck2ui 16
6466 01:19:05.144544 best dqsien dly found for B1: ( 0, 14, 24)
6467 01:19:05.147882 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6468 01:19:05.154229 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6469 01:19:05.154646
6470 01:19:05.157552 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 01:19:05.160844 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6472 01:19:05.164211 [Gating] SW calibration Done
6473 01:19:05.164633 ==
6474 01:19:05.167241 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 01:19:05.170989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 01:19:05.171411 ==
6477 01:19:05.174000 RX Vref Scan: 0
6478 01:19:05.174429
6479 01:19:05.175080 RX Vref 0 -> 0, step: 1
6480 01:19:05.175542
6481 01:19:05.177342 RX Delay -410 -> 252, step: 16
6482 01:19:05.180873 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6483 01:19:05.187240 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6484 01:19:05.190627 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6485 01:19:05.194027 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6486 01:19:05.197558 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6487 01:19:05.203841 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6488 01:19:05.207344 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6489 01:19:05.210679 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6490 01:19:05.213975 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6491 01:19:05.220802 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6492 01:19:05.223838 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6493 01:19:05.227342 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6494 01:19:05.234144 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6495 01:19:05.237306 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6496 01:19:05.240936 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6497 01:19:05.243801 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6498 01:19:05.244264 ==
6499 01:19:05.247362 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 01:19:05.253636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 01:19:05.254178 ==
6502 01:19:05.254543 DQS Delay:
6503 01:19:05.257424 DQS0 = 59, DQS1 = 59
6504 01:19:05.258015 DQM Delay:
6505 01:19:05.260722 DQM0 = 16, DQM1 = 10
6506 01:19:05.261443 DQ Delay:
6507 01:19:05.263875 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6508 01:19:05.267457 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6509 01:19:05.270503 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6510 01:19:05.273596 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6511 01:19:05.274216
6512 01:19:05.274596
6513 01:19:05.274942 ==
6514 01:19:05.277238 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 01:19:05.280570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 01:19:05.281042 ==
6517 01:19:05.281403
6518 01:19:05.281801
6519 01:19:05.283378 TX Vref Scan disable
6520 01:19:05.283838 == TX Byte 0 ==
6521 01:19:05.290115 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6522 01:19:05.293498 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6523 01:19:05.293992 == TX Byte 1 ==
6524 01:19:05.300499 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6525 01:19:05.303716 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6526 01:19:05.304183 ==
6527 01:19:05.306700 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 01:19:05.310081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 01:19:05.310548 ==
6530 01:19:05.310917
6531 01:19:05.311255
6532 01:19:05.313167 TX Vref Scan disable
6533 01:19:05.316679 == TX Byte 0 ==
6534 01:19:05.320036 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6535 01:19:05.323309 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6536 01:19:05.326660 == TX Byte 1 ==
6537 01:19:05.329824 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6538 01:19:05.333016 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6539 01:19:05.333577
6540 01:19:05.333969 [DATLAT]
6541 01:19:05.336493 Freq=400, CH0 RK1
6542 01:19:05.336951
6543 01:19:05.339797 DATLAT Default: 0xe
6544 01:19:05.340353 0, 0xFFFF, sum = 0
6545 01:19:05.343172 1, 0xFFFF, sum = 0
6546 01:19:05.343791 2, 0xFFFF, sum = 0
6547 01:19:05.346293 3, 0xFFFF, sum = 0
6548 01:19:05.346857 4, 0xFFFF, sum = 0
6549 01:19:05.349900 5, 0xFFFF, sum = 0
6550 01:19:05.350515 6, 0xFFFF, sum = 0
6551 01:19:05.353016 7, 0xFFFF, sum = 0
6552 01:19:05.353672 8, 0xFFFF, sum = 0
6553 01:19:05.356560 9, 0xFFFF, sum = 0
6554 01:19:05.357128 10, 0xFFFF, sum = 0
6555 01:19:05.359546 11, 0xFFFF, sum = 0
6556 01:19:05.360012 12, 0xFFFF, sum = 0
6557 01:19:05.362696 13, 0x0, sum = 1
6558 01:19:05.363165 14, 0x0, sum = 2
6559 01:19:05.366073 15, 0x0, sum = 3
6560 01:19:05.366540 16, 0x0, sum = 4
6561 01:19:05.369343 best_step = 14
6562 01:19:05.369835
6563 01:19:05.370199 ==
6564 01:19:05.373045 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 01:19:05.376427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 01:19:05.376987 ==
6567 01:19:05.379313 RX Vref Scan: 0
6568 01:19:05.379775
6569 01:19:05.380136 RX Vref 0 -> 0, step: 1
6570 01:19:05.380475
6571 01:19:05.382475 RX Delay -359 -> 252, step: 8
6572 01:19:05.390576 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6573 01:19:05.394096 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6574 01:19:05.397051 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6575 01:19:05.400848 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6576 01:19:05.407627 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6577 01:19:05.410934 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6578 01:19:05.413867 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6579 01:19:05.417022 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6580 01:19:05.423983 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6581 01:19:05.426998 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6582 01:19:05.430938 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6583 01:19:05.436889 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6584 01:19:05.440467 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6585 01:19:05.443573 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6586 01:19:05.447323 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6587 01:19:05.453569 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6588 01:19:05.454161 ==
6589 01:19:05.456906 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 01:19:05.460490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 01:19:05.461001 ==
6592 01:19:05.461463 DQS Delay:
6593 01:19:05.463517 DQS0 = 60, DQS1 = 68
6594 01:19:05.464071 DQM Delay:
6595 01:19:05.466664 DQM0 = 11, DQM1 = 14
6596 01:19:05.467121 DQ Delay:
6597 01:19:05.470262 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6598 01:19:05.473881 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6599 01:19:05.476746 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6600 01:19:05.480634 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6601 01:19:05.481188
6602 01:19:05.481593
6603 01:19:05.486697 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6604 01:19:05.490069 CH0 RK1: MR19=C0C, MR18=BE73
6605 01:19:05.496474 CH0_RK1: MR19=0xC0C, MR18=0xBE73, DQSOSC=386, MR23=63, INC=396, DEC=264
6606 01:19:05.500239 [RxdqsGatingPostProcess] freq 400
6607 01:19:05.506655 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6608 01:19:05.509981 best DQS0 dly(2T, 0.5T) = (0, 10)
6609 01:19:05.510442 best DQS1 dly(2T, 0.5T) = (0, 10)
6610 01:19:05.513552 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6611 01:19:05.517008 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6612 01:19:05.519560 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 01:19:05.523442 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 01:19:05.526533 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 01:19:05.529912 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 01:19:05.533722 Pre-setting of DQS Precalculation
6617 01:19:05.539480 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6618 01:19:05.540026 ==
6619 01:19:05.543004 Dram Type= 6, Freq= 0, CH_1, rank 0
6620 01:19:05.546384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 01:19:05.546850 ==
6622 01:19:05.553089 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6623 01:19:05.556537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6624 01:19:05.559919 [CA 0] Center 36 (8~64) winsize 57
6625 01:19:05.563085 [CA 1] Center 36 (8~64) winsize 57
6626 01:19:05.566029 [CA 2] Center 36 (8~64) winsize 57
6627 01:19:05.569553 [CA 3] Center 36 (8~64) winsize 57
6628 01:19:05.573027 [CA 4] Center 36 (8~64) winsize 57
6629 01:19:05.576179 [CA 5] Center 36 (8~64) winsize 57
6630 01:19:05.576809
6631 01:19:05.579203 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6632 01:19:05.579714
6633 01:19:05.582674 [CATrainingPosCal] consider 1 rank data
6634 01:19:05.585997 u2DelayCellTimex100 = 270/100 ps
6635 01:19:05.589230 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 01:19:05.592472 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 01:19:05.599328 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 01:19:05.602565 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 01:19:05.605937 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 01:19:05.609656 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 01:19:05.610128
6642 01:19:05.612631 CA PerBit enable=1, Macro0, CA PI delay=36
6643 01:19:05.613093
6644 01:19:05.616190 [CBTSetCACLKResult] CA Dly = 36
6645 01:19:05.616746 CS Dly: 1 (0~32)
6646 01:19:05.617130 ==
6647 01:19:05.619515 Dram Type= 6, Freq= 0, CH_1, rank 1
6648 01:19:05.626160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 01:19:05.626716 ==
6650 01:19:05.629419 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6651 01:19:05.635956 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6652 01:19:05.638813 [CA 0] Center 36 (8~64) winsize 57
6653 01:19:05.642642 [CA 1] Center 36 (8~64) winsize 57
6654 01:19:05.646071 [CA 2] Center 36 (8~64) winsize 57
6655 01:19:05.649559 [CA 3] Center 36 (8~64) winsize 57
6656 01:19:05.652327 [CA 4] Center 36 (8~64) winsize 57
6657 01:19:05.656330 [CA 5] Center 36 (8~64) winsize 57
6658 01:19:05.656885
6659 01:19:05.659047 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6660 01:19:05.659600
6661 01:19:05.662547 [CATrainingPosCal] consider 2 rank data
6662 01:19:05.665956 u2DelayCellTimex100 = 270/100 ps
6663 01:19:05.669084 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 01:19:05.672242 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 01:19:05.675712 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 01:19:05.678718 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 01:19:05.682141 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 01:19:05.688751 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 01:19:05.689219
6670 01:19:05.691941 CA PerBit enable=1, Macro0, CA PI delay=36
6671 01:19:05.692402
6672 01:19:05.695226 [CBTSetCACLKResult] CA Dly = 36
6673 01:19:05.695688 CS Dly: 1 (0~32)
6674 01:19:05.696074
6675 01:19:05.699358 ----->DramcWriteLeveling(PI) begin...
6676 01:19:05.699901 ==
6677 01:19:05.701912 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 01:19:05.705325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 01:19:05.708417 ==
6680 01:19:05.709029 Write leveling (Byte 0): 40 => 8
6681 01:19:05.711773 Write leveling (Byte 1): 40 => 8
6682 01:19:05.715182 DramcWriteLeveling(PI) end<-----
6683 01:19:05.715643
6684 01:19:05.716005 ==
6685 01:19:05.718865 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 01:19:05.724838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 01:19:05.725319 ==
6688 01:19:05.728483 [Gating] SW mode calibration
6689 01:19:05.735334 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6690 01:19:05.738586 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6691 01:19:05.745210 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6692 01:19:05.748220 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6693 01:19:05.751718 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 01:19:05.758397 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 01:19:05.761549 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 01:19:05.764897 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 01:19:05.771407 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 01:19:05.774540 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 01:19:05.777825 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 01:19:05.781195 Total UI for P1: 0, mck2ui 16
6701 01:19:05.784672 best dqsien dly found for B0: ( 0, 14, 24)
6702 01:19:05.788301 Total UI for P1: 0, mck2ui 16
6703 01:19:05.790850 best dqsien dly found for B1: ( 0, 14, 24)
6704 01:19:05.794373 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6705 01:19:05.797832 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6706 01:19:05.798292
6707 01:19:05.804221 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 01:19:05.807921 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6709 01:19:05.810856 [Gating] SW calibration Done
6710 01:19:05.811336 ==
6711 01:19:05.814303 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 01:19:05.817604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 01:19:05.818319 ==
6714 01:19:05.818763 RX Vref Scan: 0
6715 01:19:05.819292
6716 01:19:05.821081 RX Vref 0 -> 0, step: 1
6717 01:19:05.821576
6718 01:19:05.823873 RX Delay -410 -> 252, step: 16
6719 01:19:05.827682 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6720 01:19:05.834123 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6721 01:19:05.837255 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6722 01:19:05.840864 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6723 01:19:05.844460 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6724 01:19:05.850912 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6725 01:19:05.853720 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6726 01:19:05.857222 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6727 01:19:05.860603 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6728 01:19:05.867507 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6729 01:19:05.870565 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6730 01:19:05.873786 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6731 01:19:05.877080 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6732 01:19:05.883633 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6733 01:19:05.887114 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6734 01:19:05.890469 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6735 01:19:05.891025 ==
6736 01:19:05.893980 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 01:19:05.897025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 01:19:05.900426 ==
6739 01:19:05.900975 DQS Delay:
6740 01:19:05.901569 DQS0 = 51, DQS1 = 67
6741 01:19:05.903646 DQM Delay:
6742 01:19:05.904104 DQM0 = 13, DQM1 = 16
6743 01:19:05.907155 DQ Delay:
6744 01:19:05.907708 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6745 01:19:05.910483 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6746 01:19:05.913640 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6747 01:19:05.917355 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6748 01:19:05.917966
6749 01:19:05.918333
6750 01:19:05.920394 ==
6751 01:19:05.924364 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 01:19:05.926657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 01:19:05.927231 ==
6754 01:19:05.927607
6755 01:19:05.927948
6756 01:19:05.930226 TX Vref Scan disable
6757 01:19:05.930686 == TX Byte 0 ==
6758 01:19:05.933108 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 01:19:05.940082 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 01:19:05.940623 == TX Byte 1 ==
6761 01:19:05.943232 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 01:19:05.950060 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 01:19:05.950644 ==
6764 01:19:05.953232 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 01:19:05.956473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 01:19:05.957029 ==
6767 01:19:05.957469
6768 01:19:05.957903
6769 01:19:05.959960 TX Vref Scan disable
6770 01:19:05.960483 == TX Byte 0 ==
6771 01:19:05.963147 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 01:19:05.970171 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 01:19:05.970728 == TX Byte 1 ==
6774 01:19:05.973453 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 01:19:05.979807 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 01:19:05.980383
6777 01:19:05.980744 [DATLAT]
6778 01:19:05.981078 Freq=400, CH1 RK0
6779 01:19:05.983163
6780 01:19:05.983768 DATLAT Default: 0xf
6781 01:19:05.986409 0, 0xFFFF, sum = 0
6782 01:19:05.986898 1, 0xFFFF, sum = 0
6783 01:19:05.989597 2, 0xFFFF, sum = 0
6784 01:19:05.990065 3, 0xFFFF, sum = 0
6785 01:19:05.992878 4, 0xFFFF, sum = 0
6786 01:19:05.993345 5, 0xFFFF, sum = 0
6787 01:19:05.996683 6, 0xFFFF, sum = 0
6788 01:19:05.997249 7, 0xFFFF, sum = 0
6789 01:19:05.999616 8, 0xFFFF, sum = 0
6790 01:19:06.000081 9, 0xFFFF, sum = 0
6791 01:19:06.002899 10, 0xFFFF, sum = 0
6792 01:19:06.003370 11, 0xFFFF, sum = 0
6793 01:19:06.005996 12, 0xFFFF, sum = 0
6794 01:19:06.006464 13, 0x0, sum = 1
6795 01:19:06.009581 14, 0x0, sum = 2
6796 01:19:06.010051 15, 0x0, sum = 3
6797 01:19:06.012776 16, 0x0, sum = 4
6798 01:19:06.013242 best_step = 14
6799 01:19:06.013651
6800 01:19:06.014048 ==
6801 01:19:06.016174 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 01:19:06.022834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 01:19:06.023520 ==
6804 01:19:06.024090 RX Vref Scan: 1
6805 01:19:06.024599
6806 01:19:06.026323 RX Vref 0 -> 0, step: 1
6807 01:19:06.026986
6808 01:19:06.029296 RX Delay -375 -> 252, step: 8
6809 01:19:06.029872
6810 01:19:06.033070 Set Vref, RX VrefLevel [Byte0]: 55
6811 01:19:06.036070 [Byte1]: 47
6812 01:19:06.036537
6813 01:19:06.039699 Final RX Vref Byte 0 = 55 to rank0
6814 01:19:06.042876 Final RX Vref Byte 1 = 47 to rank0
6815 01:19:06.046792 Final RX Vref Byte 0 = 55 to rank1
6816 01:19:06.049098 Final RX Vref Byte 1 = 47 to rank1==
6817 01:19:06.052707 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 01:19:06.055564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 01:19:06.059032 ==
6820 01:19:06.059609 DQS Delay:
6821 01:19:06.059982 DQS0 = 52, DQS1 = 68
6822 01:19:06.062691 DQM Delay:
6823 01:19:06.063152 DQM0 = 9, DQM1 = 14
6824 01:19:06.066041 DQ Delay:
6825 01:19:06.066500 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6826 01:19:06.069291 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6827 01:19:06.072303 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6828 01:19:06.076205 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =24
6829 01:19:06.076785
6830 01:19:06.077386
6831 01:19:06.086098 [DQSOSCAuto] RK0, (LSB)MR18= 0x596d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6832 01:19:06.088852 CH1 RK0: MR19=C0C, MR18=596D
6833 01:19:06.095720 CH1_RK0: MR19=0xC0C, MR18=0x596D, DQSOSC=396, MR23=63, INC=376, DEC=251
6834 01:19:06.096186 ==
6835 01:19:06.098580 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 01:19:06.102620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 01:19:06.103176 ==
6838 01:19:06.105250 [Gating] SW mode calibration
6839 01:19:06.111855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6840 01:19:06.115586 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6841 01:19:06.121709 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6842 01:19:06.125703 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6843 01:19:06.129231 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 01:19:06.135291 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 01:19:06.138543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 01:19:06.141997 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 01:19:06.148599 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 01:19:06.151869 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 01:19:06.155058 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 01:19:06.158648 Total UI for P1: 0, mck2ui 16
6851 01:19:06.162114 best dqsien dly found for B0: ( 0, 14, 24)
6852 01:19:06.165337 Total UI for P1: 0, mck2ui 16
6853 01:19:06.168645 best dqsien dly found for B1: ( 0, 14, 24)
6854 01:19:06.171744 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6855 01:19:06.175840 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6856 01:19:06.178082
6857 01:19:06.181752 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 01:19:06.184925 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6859 01:19:06.188548 [Gating] SW calibration Done
6860 01:19:06.189008 ==
6861 01:19:06.192182 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 01:19:06.194989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 01:19:06.195519 ==
6864 01:19:06.196090 RX Vref Scan: 0
6865 01:19:06.198305
6866 01:19:06.198765 RX Vref 0 -> 0, step: 1
6867 01:19:06.199131
6868 01:19:06.201581 RX Delay -410 -> 252, step: 16
6869 01:19:06.204749 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6870 01:19:06.211873 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6871 01:19:06.214673 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6872 01:19:06.218101 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6873 01:19:06.221277 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6874 01:19:06.228110 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6875 01:19:06.231322 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6876 01:19:06.234937 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6877 01:19:06.238064 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6878 01:19:06.245066 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6879 01:19:06.248465 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6880 01:19:06.251846 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6881 01:19:06.254890 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6882 01:19:06.261481 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6883 01:19:06.264675 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6884 01:19:06.268003 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6885 01:19:06.268492 ==
6886 01:19:06.271283 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 01:19:06.277616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 01:19:06.278192 ==
6889 01:19:06.278762 DQS Delay:
6890 01:19:06.281333 DQS0 = 59, DQS1 = 59
6891 01:19:06.281838 DQM Delay:
6892 01:19:06.282191 DQM0 = 19, DQM1 = 12
6893 01:19:06.284349 DQ Delay:
6894 01:19:06.288310 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6895 01:19:06.291242 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6896 01:19:06.291787 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6897 01:19:06.297879 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6898 01:19:06.298342
6899 01:19:06.298757
6900 01:19:06.299103 ==
6901 01:19:06.301222 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 01:19:06.304063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 01:19:06.304529 ==
6904 01:19:06.304897
6905 01:19:06.305233
6906 01:19:06.307504 TX Vref Scan disable
6907 01:19:06.308035 == TX Byte 0 ==
6908 01:19:06.311044 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6909 01:19:06.317691 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6910 01:19:06.318173 == TX Byte 1 ==
6911 01:19:06.323911 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6912 01:19:06.327695 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6913 01:19:06.328278 ==
6914 01:19:06.330886 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 01:19:06.334154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 01:19:06.334755 ==
6917 01:19:06.335136
6918 01:19:06.335504
6919 01:19:06.337297 TX Vref Scan disable
6920 01:19:06.338019 == TX Byte 0 ==
6921 01:19:06.344002 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6922 01:19:06.347463 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6923 01:19:06.347926 == TX Byte 1 ==
6924 01:19:06.354134 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6925 01:19:06.356890 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6926 01:19:06.357354
6927 01:19:06.357754 [DATLAT]
6928 01:19:06.360534 Freq=400, CH1 RK1
6929 01:19:06.361162
6930 01:19:06.361753 DATLAT Default: 0xe
6931 01:19:06.363698 0, 0xFFFF, sum = 0
6932 01:19:06.364168 1, 0xFFFF, sum = 0
6933 01:19:06.367288 2, 0xFFFF, sum = 0
6934 01:19:06.370079 3, 0xFFFF, sum = 0
6935 01:19:06.370563 4, 0xFFFF, sum = 0
6936 01:19:06.373679 5, 0xFFFF, sum = 0
6937 01:19:06.374235 6, 0xFFFF, sum = 0
6938 01:19:06.377033 7, 0xFFFF, sum = 0
6939 01:19:06.377637 8, 0xFFFF, sum = 0
6940 01:19:06.379965 9, 0xFFFF, sum = 0
6941 01:19:06.380433 10, 0xFFFF, sum = 0
6942 01:19:06.383278 11, 0xFFFF, sum = 0
6943 01:19:06.383745 12, 0xFFFF, sum = 0
6944 01:19:06.386798 13, 0x0, sum = 1
6945 01:19:06.387274 14, 0x0, sum = 2
6946 01:19:06.390390 15, 0x0, sum = 3
6947 01:19:06.390964 16, 0x0, sum = 4
6948 01:19:06.393206 best_step = 14
6949 01:19:06.393791
6950 01:19:06.394156 ==
6951 01:19:06.396272 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 01:19:06.399761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 01:19:06.400289 ==
6954 01:19:06.403241 RX Vref Scan: 0
6955 01:19:06.403863
6956 01:19:06.404290 RX Vref 0 -> 0, step: 1
6957 01:19:06.404680
6958 01:19:06.406556 RX Delay -359 -> 252, step: 8
6959 01:19:06.414194 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6960 01:19:06.417907 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6961 01:19:06.420969 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6962 01:19:06.424118 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6963 01:19:06.431181 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6964 01:19:06.434437 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6965 01:19:06.437628 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6966 01:19:06.444415 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6967 01:19:06.447267 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6968 01:19:06.450625 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6969 01:19:06.454003 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6970 01:19:06.460438 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6971 01:19:06.463809 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6972 01:19:06.467219 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6973 01:19:06.470677 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6974 01:19:06.477351 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6975 01:19:06.477945 ==
6976 01:19:06.480610 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 01:19:06.483734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 01:19:06.484205 ==
6979 01:19:06.484571 DQS Delay:
6980 01:19:06.487074 DQS0 = 60, DQS1 = 64
6981 01:19:06.487535 DQM Delay:
6982 01:19:06.490507 DQM0 = 13, DQM1 = 10
6983 01:19:06.490970 DQ Delay:
6984 01:19:06.493478 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6985 01:19:06.496893 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6986 01:19:06.500361 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6987 01:19:06.503484 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6988 01:19:06.503981
6989 01:19:06.504546
6990 01:19:06.510128 [DQSOSCAuto] RK1, (LSB)MR18= 0x77a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6991 01:19:06.513652 CH1 RK1: MR19=C0C, MR18=77A8
6992 01:19:06.519972 CH1_RK1: MR19=0xC0C, MR18=0x77A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6993 01:19:06.523652 [RxdqsGatingPostProcess] freq 400
6994 01:19:06.530001 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6995 01:19:06.533709 best DQS0 dly(2T, 0.5T) = (0, 10)
6996 01:19:06.536797 best DQS1 dly(2T, 0.5T) = (0, 10)
6997 01:19:06.539886 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6998 01:19:06.542889 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6999 01:19:06.543351 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 01:19:06.546622 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 01:19:06.550390 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 01:19:06.553087 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 01:19:06.556267 Pre-setting of DQS Precalculation
7004 01:19:06.563386 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7005 01:19:06.569895 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7006 01:19:06.576420 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7007 01:19:06.576946
7008 01:19:06.577320
7009 01:19:06.579799 [Calibration Summary] 800 Mbps
7010 01:19:06.580412 CH 0, Rank 0
7011 01:19:06.582834 SW Impedance : PASS
7012 01:19:06.586461 DUTY Scan : NO K
7013 01:19:06.586931 ZQ Calibration : PASS
7014 01:19:06.589844 Jitter Meter : NO K
7015 01:19:06.593235 CBT Training : PASS
7016 01:19:06.593857 Write leveling : PASS
7017 01:19:06.596312 RX DQS gating : PASS
7018 01:19:06.599355 RX DQ/DQS(RDDQC) : PASS
7019 01:19:06.599976 TX DQ/DQS : PASS
7020 01:19:06.602506 RX DATLAT : PASS
7021 01:19:06.606103 RX DQ/DQS(Engine): PASS
7022 01:19:06.606611 TX OE : NO K
7023 01:19:06.607008 All Pass.
7024 01:19:06.609421
7025 01:19:06.609862 CH 0, Rank 1
7026 01:19:06.612782 SW Impedance : PASS
7027 01:19:06.613239 DUTY Scan : NO K
7028 01:19:06.616319 ZQ Calibration : PASS
7029 01:19:06.619240 Jitter Meter : NO K
7030 01:19:06.619804 CBT Training : PASS
7031 01:19:06.622555 Write leveling : NO K
7032 01:19:06.626141 RX DQS gating : PASS
7033 01:19:06.626726 RX DQ/DQS(RDDQC) : PASS
7034 01:19:06.629107 TX DQ/DQS : PASS
7035 01:19:06.629705 RX DATLAT : PASS
7036 01:19:06.633010 RX DQ/DQS(Engine): PASS
7037 01:19:06.635974 TX OE : NO K
7038 01:19:06.636531 All Pass.
7039 01:19:06.636897
7040 01:19:06.637235 CH 1, Rank 0
7041 01:19:06.639291 SW Impedance : PASS
7042 01:19:06.642186 DUTY Scan : NO K
7043 01:19:06.642732 ZQ Calibration : PASS
7044 01:19:06.646135 Jitter Meter : NO K
7045 01:19:06.649546 CBT Training : PASS
7046 01:19:06.650040 Write leveling : PASS
7047 01:19:06.652799 RX DQS gating : PASS
7048 01:19:06.655375 RX DQ/DQS(RDDQC) : PASS
7049 01:19:06.655911 TX DQ/DQS : PASS
7050 01:19:06.658606 RX DATLAT : PASS
7051 01:19:06.662616 RX DQ/DQS(Engine): PASS
7052 01:19:06.663318 TX OE : NO K
7053 01:19:06.665657 All Pass.
7054 01:19:06.666116
7055 01:19:06.666484 CH 1, Rank 1
7056 01:19:06.669093 SW Impedance : PASS
7057 01:19:06.669591 DUTY Scan : NO K
7058 01:19:06.672560 ZQ Calibration : PASS
7059 01:19:06.675364 Jitter Meter : NO K
7060 01:19:06.675894 CBT Training : PASS
7061 01:19:06.678793 Write leveling : NO K
7062 01:19:06.682479 RX DQS gating : PASS
7063 01:19:06.683031 RX DQ/DQS(RDDQC) : PASS
7064 01:19:06.685272 TX DQ/DQS : PASS
7065 01:19:06.685779 RX DATLAT : PASS
7066 01:19:06.689041 RX DQ/DQS(Engine): PASS
7067 01:19:06.691856 TX OE : NO K
7068 01:19:06.692319 All Pass.
7069 01:19:06.692684
7070 01:19:06.695651 DramC Write-DBI off
7071 01:19:06.696111 PER_BANK_REFRESH: Hybrid Mode
7072 01:19:06.699032 TX_TRACKING: ON
7073 01:19:06.708637 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7074 01:19:06.712518 [FAST_K] Save calibration result to emmc
7075 01:19:06.715622 dramc_set_vcore_voltage set vcore to 725000
7076 01:19:06.718311 Read voltage for 1600, 0
7077 01:19:06.718771 Vio18 = 0
7078 01:19:06.719136 Vcore = 725000
7079 01:19:06.719474 Vdram = 0
7080 01:19:06.721633 Vddq = 0
7081 01:19:06.722092 Vmddr = 0
7082 01:19:06.729148 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7083 01:19:06.731890 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7084 01:19:06.735087 MEM_TYPE=3, freq_sel=13
7085 01:19:06.738412 sv_algorithm_assistance_LP4_3733
7086 01:19:06.741978 ============ PULL DRAM RESETB DOWN ============
7087 01:19:06.745138 ========== PULL DRAM RESETB DOWN end =========
7088 01:19:06.751890 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7089 01:19:06.755076 ===================================
7090 01:19:06.755632 LPDDR4 DRAM CONFIGURATION
7091 01:19:06.758196 ===================================
7092 01:19:06.761962 EX_ROW_EN[0] = 0x0
7093 01:19:06.764816 EX_ROW_EN[1] = 0x0
7094 01:19:06.765278 LP4Y_EN = 0x0
7095 01:19:06.768311 WORK_FSP = 0x1
7096 01:19:06.768768 WL = 0x5
7097 01:19:06.772163 RL = 0x5
7098 01:19:06.772716 BL = 0x2
7099 01:19:06.775012 RPST = 0x0
7100 01:19:06.775572 RD_PRE = 0x0
7101 01:19:06.778459 WR_PRE = 0x1
7102 01:19:06.778884 WR_PST = 0x1
7103 01:19:06.781570 DBI_WR = 0x0
7104 01:19:06.782122 DBI_RD = 0x0
7105 01:19:06.784659 OTF = 0x1
7106 01:19:06.787846 ===================================
7107 01:19:06.791383 ===================================
7108 01:19:06.791848 ANA top config
7109 01:19:06.795014 ===================================
7110 01:19:06.797953 DLL_ASYNC_EN = 0
7111 01:19:06.801071 ALL_SLAVE_EN = 0
7112 01:19:06.804535 NEW_RANK_MODE = 1
7113 01:19:06.805001 DLL_IDLE_MODE = 1
7114 01:19:06.807850 LP45_APHY_COMB_EN = 1
7115 01:19:06.811387 TX_ODT_DIS = 0
7116 01:19:06.815051 NEW_8X_MODE = 1
7117 01:19:06.818246 ===================================
7118 01:19:06.821571 ===================================
7119 01:19:06.824409 data_rate = 3200
7120 01:19:06.824958 CKR = 1
7121 01:19:06.828128 DQ_P2S_RATIO = 8
7122 01:19:06.831772 ===================================
7123 01:19:06.834439 CA_P2S_RATIO = 8
7124 01:19:06.837671 DQ_CA_OPEN = 0
7125 01:19:06.841040 DQ_SEMI_OPEN = 0
7126 01:19:06.844300 CA_SEMI_OPEN = 0
7127 01:19:06.844763 CA_FULL_RATE = 0
7128 01:19:06.847905 DQ_CKDIV4_EN = 0
7129 01:19:06.850856 CA_CKDIV4_EN = 0
7130 01:19:06.854844 CA_PREDIV_EN = 0
7131 01:19:06.857934 PH8_DLY = 12
7132 01:19:06.861305 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7133 01:19:06.861796 DQ_AAMCK_DIV = 4
7134 01:19:06.864456 CA_AAMCK_DIV = 4
7135 01:19:06.867544 CA_ADMCK_DIV = 4
7136 01:19:06.871272 DQ_TRACK_CA_EN = 0
7137 01:19:06.874240 CA_PICK = 1600
7138 01:19:06.877962 CA_MCKIO = 1600
7139 01:19:06.880832 MCKIO_SEMI = 0
7140 01:19:06.881297 PLL_FREQ = 3068
7141 01:19:06.884346 DQ_UI_PI_RATIO = 32
7142 01:19:06.887634 CA_UI_PI_RATIO = 0
7143 01:19:06.891177 ===================================
7144 01:19:06.894168 ===================================
7145 01:19:06.897609 memory_type:LPDDR4
7146 01:19:06.898143 GP_NUM : 10
7147 01:19:06.900719 SRAM_EN : 1
7148 01:19:06.904193 MD32_EN : 0
7149 01:19:06.907403 ===================================
7150 01:19:06.907875 [ANA_INIT] >>>>>>>>>>>>>>
7151 01:19:06.910712 <<<<<< [CONFIGURE PHASE]: ANA_TX
7152 01:19:06.914079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7153 01:19:06.917162 ===================================
7154 01:19:06.920559 data_rate = 3200,PCW = 0X7600
7155 01:19:06.924353 ===================================
7156 01:19:06.927330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7157 01:19:06.934025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 01:19:06.937358 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7159 01:19:06.944304 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7160 01:19:06.947615 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7161 01:19:06.950300 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7162 01:19:06.953398 [ANA_INIT] flow start
7163 01:19:06.953915 [ANA_INIT] PLL >>>>>>>>
7164 01:19:06.956702 [ANA_INIT] PLL <<<<<<<<
7165 01:19:06.960442 [ANA_INIT] MIDPI >>>>>>>>
7166 01:19:06.960943 [ANA_INIT] MIDPI <<<<<<<<
7167 01:19:06.963269 [ANA_INIT] DLL >>>>>>>>
7168 01:19:06.966642 [ANA_INIT] DLL <<<<<<<<
7169 01:19:06.967153 [ANA_INIT] flow end
7170 01:19:06.973344 ============ LP4 DIFF to SE enter ============
7171 01:19:06.976761 ============ LP4 DIFF to SE exit ============
7172 01:19:06.980349 [ANA_INIT] <<<<<<<<<<<<<
7173 01:19:06.983907 [Flow] Enable top DCM control >>>>>
7174 01:19:06.986553 [Flow] Enable top DCM control <<<<<
7175 01:19:06.987033 Enable DLL master slave shuffle
7176 01:19:06.993681 ==============================================================
7177 01:19:06.996280 Gating Mode config
7178 01:19:06.999787 ==============================================================
7179 01:19:07.003015 Config description:
7180 01:19:07.013310 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7181 01:19:07.019708 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7182 01:19:07.023414 SELPH_MODE 0: By rank 1: By Phase
7183 01:19:07.029320 ==============================================================
7184 01:19:07.032897 GAT_TRACK_EN = 1
7185 01:19:07.036642 RX_GATING_MODE = 2
7186 01:19:07.039449 RX_GATING_TRACK_MODE = 2
7187 01:19:07.042996 SELPH_MODE = 1
7188 01:19:07.043465 PICG_EARLY_EN = 1
7189 01:19:07.046134 VALID_LAT_VALUE = 1
7190 01:19:07.052834 ==============================================================
7191 01:19:07.056598 Enter into Gating configuration >>>>
7192 01:19:07.059491 Exit from Gating configuration <<<<
7193 01:19:07.062955 Enter into DVFS_PRE_config >>>>>
7194 01:19:07.072829 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7195 01:19:07.075979 Exit from DVFS_PRE_config <<<<<
7196 01:19:07.079179 Enter into PICG configuration >>>>
7197 01:19:07.082587 Exit from PICG configuration <<<<
7198 01:19:07.085915 [RX_INPUT] configuration >>>>>
7199 01:19:07.088926 [RX_INPUT] configuration <<<<<
7200 01:19:07.092479 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7201 01:19:07.099332 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7202 01:19:07.105604 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7203 01:19:07.112185 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7204 01:19:07.119259 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7205 01:19:07.126028 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7206 01:19:07.128871 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7207 01:19:07.132145 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7208 01:19:07.135251 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7209 01:19:07.141713 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7210 01:19:07.145143 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7211 01:19:07.148697 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 01:19:07.152178 ===================================
7213 01:19:07.155042 LPDDR4 DRAM CONFIGURATION
7214 01:19:07.158377 ===================================
7215 01:19:07.158859 EX_ROW_EN[0] = 0x0
7216 01:19:07.162141 EX_ROW_EN[1] = 0x0
7217 01:19:07.165607 LP4Y_EN = 0x0
7218 01:19:07.166156 WORK_FSP = 0x1
7219 01:19:07.168809 WL = 0x5
7220 01:19:07.169275 RL = 0x5
7221 01:19:07.171640 BL = 0x2
7222 01:19:07.172210 RPST = 0x0
7223 01:19:07.175715 RD_PRE = 0x0
7224 01:19:07.176287 WR_PRE = 0x1
7225 01:19:07.178738 WR_PST = 0x1
7226 01:19:07.179205 DBI_WR = 0x0
7227 01:19:07.181499 DBI_RD = 0x0
7228 01:19:07.182008 OTF = 0x1
7229 01:19:07.185208 ===================================
7230 01:19:07.188537 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7231 01:19:07.195180 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7232 01:19:07.198107 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7233 01:19:07.201799 ===================================
7234 01:19:07.204911 LPDDR4 DRAM CONFIGURATION
7235 01:19:07.208016 ===================================
7236 01:19:07.208495 EX_ROW_EN[0] = 0x10
7237 01:19:07.211294 EX_ROW_EN[1] = 0x0
7238 01:19:07.211770 LP4Y_EN = 0x0
7239 01:19:07.214660 WORK_FSP = 0x1
7240 01:19:07.218022 WL = 0x5
7241 01:19:07.218539 RL = 0x5
7242 01:19:07.221313 BL = 0x2
7243 01:19:07.221815 RPST = 0x0
7244 01:19:07.225444 RD_PRE = 0x0
7245 01:19:07.226049 WR_PRE = 0x1
7246 01:19:07.228292 WR_PST = 0x1
7247 01:19:07.228916 DBI_WR = 0x0
7248 01:19:07.231467 DBI_RD = 0x0
7249 01:19:07.232022 OTF = 0x1
7250 01:19:07.234559 ===================================
7251 01:19:07.241051 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7252 01:19:07.241542 ==
7253 01:19:07.245175 Dram Type= 6, Freq= 0, CH_0, rank 0
7254 01:19:07.248495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7255 01:19:07.249053 ==
7256 01:19:07.251450 [Duty_Offset_Calibration]
7257 01:19:07.254761 B0:2 B1:0 CA:3
7258 01:19:07.255396
7259 01:19:07.258175 [DutyScan_Calibration_Flow] k_type=0
7260 01:19:07.266362
7261 01:19:07.266912 ==CLK 0==
7262 01:19:07.269564 Final CLK duty delay cell = 0
7263 01:19:07.273318 [0] MAX Duty = 5031%(X100), DQS PI = 12
7264 01:19:07.276285 [0] MIN Duty = 4907%(X100), DQS PI = 6
7265 01:19:07.276888 [0] AVG Duty = 4969%(X100)
7266 01:19:07.279384
7267 01:19:07.283182 CH0 CLK Duty spec in!! Max-Min= 124%
7268 01:19:07.286309 [DutyScan_Calibration_Flow] ====Done====
7269 01:19:07.286765
7270 01:19:07.289459 [DutyScan_Calibration_Flow] k_type=1
7271 01:19:07.306213
7272 01:19:07.306771 ==DQS 0 ==
7273 01:19:07.309469 Final DQS duty delay cell = 0
7274 01:19:07.313144 [0] MAX Duty = 5094%(X100), DQS PI = 14
7275 01:19:07.316454 [0] MIN Duty = 4875%(X100), DQS PI = 48
7276 01:19:07.319674 [0] AVG Duty = 4984%(X100)
7277 01:19:07.320223
7278 01:19:07.320599 ==DQS 1 ==
7279 01:19:07.322773 Final DQS duty delay cell = 0
7280 01:19:07.326054 [0] MAX Duty = 5156%(X100), DQS PI = 30
7281 01:19:07.329007 [0] MIN Duty = 5031%(X100), DQS PI = 12
7282 01:19:07.332984 [0] AVG Duty = 5093%(X100)
7283 01:19:07.333573
7284 01:19:07.336120 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7285 01:19:07.336671
7286 01:19:07.339275 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7287 01:19:07.342770 [DutyScan_Calibration_Flow] ====Done====
7288 01:19:07.343287
7289 01:19:07.346188 [DutyScan_Calibration_Flow] k_type=3
7290 01:19:07.363883
7291 01:19:07.364487 ==DQM 0 ==
7292 01:19:07.367222 Final DQM duty delay cell = 0
7293 01:19:07.370459 [0] MAX Duty = 5187%(X100), DQS PI = 32
7294 01:19:07.374018 [0] MIN Duty = 4844%(X100), DQS PI = 52
7295 01:19:07.377136 [0] AVG Duty = 5015%(X100)
7296 01:19:07.377786
7297 01:19:07.378248 ==DQM 1 ==
7298 01:19:07.380724 Final DQM duty delay cell = 4
7299 01:19:07.384071 [4] MAX Duty = 5187%(X100), DQS PI = 62
7300 01:19:07.387071 [4] MIN Duty = 5031%(X100), DQS PI = 12
7301 01:19:07.390524 [4] AVG Duty = 5109%(X100)
7302 01:19:07.391008
7303 01:19:07.393947 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7304 01:19:07.394481
7305 01:19:07.397609 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7306 01:19:07.400646 [DutyScan_Calibration_Flow] ====Done====
7307 01:19:07.401102
7308 01:19:07.403542 [DutyScan_Calibration_Flow] k_type=2
7309 01:19:07.419866
7310 01:19:07.420320 ==DQ 0 ==
7311 01:19:07.423326 Final DQ duty delay cell = -4
7312 01:19:07.426694 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7313 01:19:07.429857 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7314 01:19:07.433357 [-4] AVG Duty = 4938%(X100)
7315 01:19:07.434036
7316 01:19:07.434411 ==DQ 1 ==
7317 01:19:07.436411 Final DQ duty delay cell = 0
7318 01:19:07.440168 [0] MAX Duty = 5156%(X100), DQS PI = 60
7319 01:19:07.443501 [0] MIN Duty = 4969%(X100), DQS PI = 22
7320 01:19:07.446573 [0] AVG Duty = 5062%(X100)
7321 01:19:07.447027
7322 01:19:07.449809 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7323 01:19:07.450307
7324 01:19:07.452933 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7325 01:19:07.456441 [DutyScan_Calibration_Flow] ====Done====
7326 01:19:07.456905 ==
7327 01:19:07.460372 Dram Type= 6, Freq= 0, CH_1, rank 0
7328 01:19:07.463217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7329 01:19:07.463675 ==
7330 01:19:07.466454 [Duty_Offset_Calibration]
7331 01:19:07.466904 B0:1 B1:-2 CA:0
7332 01:19:07.467271
7333 01:19:07.469810 [DutyScan_Calibration_Flow] k_type=0
7334 01:19:07.480769
7335 01:19:07.481184 ==CLK 0==
7336 01:19:07.484153 Final CLK duty delay cell = 0
7337 01:19:07.487435 [0] MAX Duty = 5062%(X100), DQS PI = 20
7338 01:19:07.490811 [0] MIN Duty = 4844%(X100), DQS PI = 0
7339 01:19:07.494363 [0] AVG Duty = 4953%(X100)
7340 01:19:07.494910
7341 01:19:07.496814 CH1 CLK Duty spec in!! Max-Min= 218%
7342 01:19:07.500619 [DutyScan_Calibration_Flow] ====Done====
7343 01:19:07.501197
7344 01:19:07.504075 [DutyScan_Calibration_Flow] k_type=1
7345 01:19:07.520727
7346 01:19:07.521272 ==DQS 0 ==
7347 01:19:07.524078 Final DQS duty delay cell = 0
7348 01:19:07.527472 [0] MAX Duty = 5187%(X100), DQS PI = 24
7349 01:19:07.530021 [0] MIN Duty = 5062%(X100), DQS PI = 0
7350 01:19:07.530515 [0] AVG Duty = 5124%(X100)
7351 01:19:07.533714
7352 01:19:07.534375 ==DQS 1 ==
7353 01:19:07.536605 Final DQS duty delay cell = 0
7354 01:19:07.540016 [0] MAX Duty = 5093%(X100), DQS PI = 60
7355 01:19:07.543335 [0] MIN Duty = 4844%(X100), DQS PI = 24
7356 01:19:07.546644 [0] AVG Duty = 4968%(X100)
7357 01:19:07.547101
7358 01:19:07.550150 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7359 01:19:07.550613
7360 01:19:07.553112 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7361 01:19:07.556728 [DutyScan_Calibration_Flow] ====Done====
7362 01:19:07.557180
7363 01:19:07.560068 [DutyScan_Calibration_Flow] k_type=3
7364 01:19:07.577262
7365 01:19:07.577861 ==DQM 0 ==
7366 01:19:07.580712 Final DQM duty delay cell = 0
7367 01:19:07.583596 [0] MAX Duty = 5031%(X100), DQS PI = 24
7368 01:19:07.586772 [0] MIN Duty = 4782%(X100), DQS PI = 56
7369 01:19:07.590584 [0] AVG Duty = 4906%(X100)
7370 01:19:07.591173
7371 01:19:07.591607 ==DQM 1 ==
7372 01:19:07.593382 Final DQM duty delay cell = 0
7373 01:19:07.596598 [0] MAX Duty = 5062%(X100), DQS PI = 34
7374 01:19:07.600060 [0] MIN Duty = 4875%(X100), DQS PI = 24
7375 01:19:07.603302 [0] AVG Duty = 4968%(X100)
7376 01:19:07.603768
7377 01:19:07.606579 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7378 01:19:07.607044
7379 01:19:07.610300 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7380 01:19:07.613404 [DutyScan_Calibration_Flow] ====Done====
7381 01:19:07.613900
7382 01:19:07.616821 [DutyScan_Calibration_Flow] k_type=2
7383 01:19:07.633897
7384 01:19:07.634448 ==DQ 0 ==
7385 01:19:07.637398 Final DQ duty delay cell = 0
7386 01:19:07.640758 [0] MAX Duty = 5093%(X100), DQS PI = 20
7387 01:19:07.643772 [0] MIN Duty = 4907%(X100), DQS PI = 46
7388 01:19:07.644242 [0] AVG Duty = 5000%(X100)
7389 01:19:07.644613
7390 01:19:07.647652 ==DQ 1 ==
7391 01:19:07.650761 Final DQ duty delay cell = 0
7392 01:19:07.653702 [0] MAX Duty = 5125%(X100), DQS PI = 34
7393 01:19:07.657179 [0] MIN Duty = 4969%(X100), DQS PI = 24
7394 01:19:07.657865 [0] AVG Duty = 5047%(X100)
7395 01:19:07.658246
7396 01:19:07.663683 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7397 01:19:07.664233
7398 01:19:07.667124 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7399 01:19:07.670099 [DutyScan_Calibration_Flow] ====Done====
7400 01:19:07.673833 nWR fixed to 30
7401 01:19:07.674297 [ModeRegInit_LP4] CH0 RK0
7402 01:19:07.676972 [ModeRegInit_LP4] CH0 RK1
7403 01:19:07.679883 [ModeRegInit_LP4] CH1 RK0
7404 01:19:07.683463 [ModeRegInit_LP4] CH1 RK1
7405 01:19:07.684015 match AC timing 5
7406 01:19:07.690145 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7407 01:19:07.693623 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7408 01:19:07.696928 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7409 01:19:07.703425 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7410 01:19:07.706678 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7411 01:19:07.707138 [MiockJmeterHQA]
7412 01:19:07.707503
7413 01:19:07.710115 [DramcMiockJmeter] u1RxGatingPI = 0
7414 01:19:07.713420 0 : 4257, 4030
7415 01:19:07.714004 4 : 4366, 4140
7416 01:19:07.716451 8 : 4368, 4140
7417 01:19:07.717044 12 : 4254, 4029
7418 01:19:07.717421 16 : 4255, 4029
7419 01:19:07.719817 20 : 4255, 4029
7420 01:19:07.720457 24 : 4255, 4029
7421 01:19:07.722870 28 : 4253, 4029
7422 01:19:07.723337 32 : 4255, 4030
7423 01:19:07.726348 36 : 4254, 4029
7424 01:19:07.726824 40 : 4366, 4140
7425 01:19:07.729751 44 : 4366, 4140
7426 01:19:07.730219 48 : 4252, 4027
7427 01:19:07.730590 52 : 4254, 4029
7428 01:19:07.732939 56 : 4252, 4029
7429 01:19:07.733407 60 : 4255, 4030
7430 01:19:07.736414 64 : 4252, 4030
7431 01:19:07.737050 68 : 4257, 4031
7432 01:19:07.739895 72 : 4255, 4029
7433 01:19:07.740362 76 : 4254, 4029
7434 01:19:07.742866 80 : 4252, 4030
7435 01:19:07.743376 84 : 4252, 4029
7436 01:19:07.743747 88 : 4255, 4029
7437 01:19:07.746018 92 : 4360, 4138
7438 01:19:07.746512 96 : 4252, 4030
7439 01:19:07.750113 100 : 4250, 4027
7440 01:19:07.750688 104 : 4250, 3449
7441 01:19:07.752568 108 : 4253, 0
7442 01:19:07.753033 112 : 4255, 0
7443 01:19:07.753401 116 : 4255, 0
7444 01:19:07.755836 120 : 4366, 0
7445 01:19:07.756305 124 : 4363, 0
7446 01:19:07.759191 128 : 4366, 0
7447 01:19:07.759770 132 : 4253, 0
7448 01:19:07.760147 136 : 4364, 0
7449 01:19:07.762626 140 : 4363, 0
7450 01:19:07.763094 144 : 4252, 0
7451 01:19:07.765952 148 : 4252, 0
7452 01:19:07.766436 152 : 4368, 0
7453 01:19:07.766803 156 : 4254, 0
7454 01:19:07.769443 160 : 4252, 0
7455 01:19:07.769953 164 : 4252, 0
7456 01:19:07.772460 168 : 4255, 0
7457 01:19:07.772924 172 : 4253, 0
7458 01:19:07.773314 176 : 4252, 0
7459 01:19:07.776027 180 : 4257, 0
7460 01:19:07.776492 184 : 4253, 0
7461 01:19:07.779478 188 : 4253, 0
7462 01:19:07.780122 192 : 4257, 0
7463 01:19:07.780540 196 : 4255, 0
7464 01:19:07.782406 200 : 4250, 0
7465 01:19:07.782876 204 : 4255, 0
7466 01:19:07.783248 208 : 4255, 0
7467 01:19:07.786069 212 : 4252, 0
7468 01:19:07.786534 216 : 4252, 0
7469 01:19:07.788790 220 : 4258, 0
7470 01:19:07.789254 224 : 4363, 0
7471 01:19:07.789674 228 : 4252, 0
7472 01:19:07.792703 232 : 4365, 3
7473 01:19:07.793172 236 : 4252, 1244
7474 01:19:07.796009 240 : 4255, 4029
7475 01:19:07.796572 244 : 4255, 4029
7476 01:19:07.799142 248 : 4360, 4137
7477 01:19:07.799610 252 : 4363, 4140
7478 01:19:07.802427 256 : 4252, 4026
7479 01:19:07.802890 260 : 4253, 4027
7480 01:19:07.805547 264 : 4366, 4140
7481 01:19:07.806016 268 : 4252, 4030
7482 01:19:07.808712 272 : 4365, 4140
7483 01:19:07.809177 276 : 4255, 4029
7484 01:19:07.809592 280 : 4366, 4140
7485 01:19:07.812146 284 : 4252, 4029
7486 01:19:07.812611 288 : 4253, 4029
7487 01:19:07.815326 292 : 4255, 4029
7488 01:19:07.815791 296 : 4252, 4030
7489 01:19:07.818835 300 : 4363, 4140
7490 01:19:07.819396 304 : 4363, 4140
7491 01:19:07.821963 308 : 4255, 4029
7492 01:19:07.822433 312 : 4255, 4030
7493 01:19:07.825389 316 : 4366, 4140
7494 01:19:07.825897 320 : 4255, 4030
7495 01:19:07.829188 324 : 4253, 4029
7496 01:19:07.829697 328 : 4258, 4031
7497 01:19:07.832416 332 : 4252, 4030
7498 01:19:07.832884 336 : 4365, 4140
7499 01:19:07.833254 340 : 4253, 4029
7500 01:19:07.835606 344 : 4253, 4029
7501 01:19:07.836166 348 : 4252, 4030
7502 01:19:07.838750 352 : 4363, 4093
7503 01:19:07.839313 356 : 4363, 2608
7504 01:19:07.842033 360 : 4252, 0
7505 01:19:07.842501
7506 01:19:07.842862 MIOCK jitter meter ch=0
7507 01:19:07.845435
7508 01:19:07.845920 1T = (360-108) = 252 dly cells
7509 01:19:07.852046 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7510 01:19:07.852602 ==
7511 01:19:07.855351 Dram Type= 6, Freq= 0, CH_0, rank 0
7512 01:19:07.858646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7513 01:19:07.859259 ==
7514 01:19:07.864833 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7515 01:19:07.868549 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7516 01:19:07.874732 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7517 01:19:07.878415 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7518 01:19:07.888949 [CA 0] Center 44 (14~75) winsize 62
7519 01:19:07.892389 [CA 1] Center 43 (13~74) winsize 62
7520 01:19:07.895701 [CA 2] Center 40 (11~69) winsize 59
7521 01:19:07.898963 [CA 3] Center 39 (10~69) winsize 60
7522 01:19:07.902332 [CA 4] Center 37 (8~67) winsize 60
7523 01:19:07.905243 [CA 5] Center 37 (8~66) winsize 59
7524 01:19:07.905736
7525 01:19:07.908794 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7526 01:19:07.909256
7527 01:19:07.915466 [CATrainingPosCal] consider 1 rank data
7528 01:19:07.915928 u2DelayCellTimex100 = 258/100 ps
7529 01:19:07.922364 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7530 01:19:07.925386 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7531 01:19:07.928798 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7532 01:19:07.932101 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7533 01:19:07.935474 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7534 01:19:07.938852 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7535 01:19:07.939415
7536 01:19:07.942108 CA PerBit enable=1, Macro0, CA PI delay=37
7537 01:19:07.942567
7538 01:19:07.945667 [CBTSetCACLKResult] CA Dly = 37
7539 01:19:07.948938 CS Dly: 11 (0~42)
7540 01:19:07.952319 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7541 01:19:07.955241 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7542 01:19:07.955802 ==
7543 01:19:07.958411 Dram Type= 6, Freq= 0, CH_0, rank 1
7544 01:19:07.965162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 01:19:07.965801 ==
7546 01:19:07.968332 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7547 01:19:07.974659 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7548 01:19:07.977984 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7549 01:19:07.984765 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7550 01:19:07.992725 [CA 0] Center 43 (13~74) winsize 62
7551 01:19:07.995842 [CA 1] Center 43 (13~74) winsize 62
7552 01:19:07.999027 [CA 2] Center 39 (10~68) winsize 59
7553 01:19:08.002762 [CA 3] Center 39 (10~68) winsize 59
7554 01:19:08.006027 [CA 4] Center 36 (7~66) winsize 60
7555 01:19:08.009413 [CA 5] Center 36 (6~66) winsize 61
7556 01:19:08.009912
7557 01:19:08.012761 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7558 01:19:08.013236
7559 01:19:08.019296 [CATrainingPosCal] consider 2 rank data
7560 01:19:08.019860 u2DelayCellTimex100 = 258/100 ps
7561 01:19:08.025875 CA0 delay=44 (14~74),Diff = 7 PI (26 cell)
7562 01:19:08.029093 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7563 01:19:08.032705 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7564 01:19:08.035370 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7565 01:19:08.038870 CA4 delay=37 (8~66),Diff = 0 PI (0 cell)
7566 01:19:08.042121 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7567 01:19:08.042580
7568 01:19:08.045635 CA PerBit enable=1, Macro0, CA PI delay=37
7569 01:19:08.046097
7570 01:19:08.049097 [CBTSetCACLKResult] CA Dly = 37
7571 01:19:08.052034 CS Dly: 11 (0~43)
7572 01:19:08.055342 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7573 01:19:08.058724 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7574 01:19:08.059187
7575 01:19:08.062147 ----->DramcWriteLeveling(PI) begin...
7576 01:19:08.062715 ==
7577 01:19:08.065590 Dram Type= 6, Freq= 0, CH_0, rank 0
7578 01:19:08.072290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 01:19:08.072849 ==
7580 01:19:08.075316 Write leveling (Byte 0): 35 => 35
7581 01:19:08.078528 Write leveling (Byte 1): 30 => 30
7582 01:19:08.081766 DramcWriteLeveling(PI) end<-----
7583 01:19:08.082316
7584 01:19:08.082681 ==
7585 01:19:08.085366 Dram Type= 6, Freq= 0, CH_0, rank 0
7586 01:19:08.088533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 01:19:08.088995 ==
7588 01:19:08.091712 [Gating] SW mode calibration
7589 01:19:08.098496 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7590 01:19:08.104843 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7591 01:19:08.108818 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 01:19:08.111801 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 01:19:08.117932 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 01:19:08.121363 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 01:19:08.124710 1 4 16 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7596 01:19:08.131075 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
7597 01:19:08.135084 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7598 01:19:08.137902 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 01:19:08.144729 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 01:19:08.147965 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 01:19:08.151283 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 01:19:08.157629 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7603 01:19:08.161069 1 5 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7604 01:19:08.164631 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7605 01:19:08.171058 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7606 01:19:08.174328 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7607 01:19:08.177499 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 01:19:08.183754 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 01:19:08.187740 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 01:19:08.191032 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7611 01:19:08.194586 1 6 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (1 1)
7612 01:19:08.200822 1 6 20 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7613 01:19:08.204165 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7614 01:19:08.207292 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 01:19:08.214057 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 01:19:08.216841 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 01:19:08.220578 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 01:19:08.226944 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 01:19:08.230281 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7620 01:19:08.234003 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7621 01:19:08.240828 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7622 01:19:08.243263 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 01:19:08.246569 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 01:19:08.253758 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 01:19:08.256599 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 01:19:08.260110 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 01:19:08.266842 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 01:19:08.270091 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 01:19:08.273675 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 01:19:08.279972 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 01:19:08.283127 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 01:19:08.286477 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 01:19:08.293052 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 01:19:08.296459 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7635 01:19:08.299450 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7636 01:19:08.306314 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7637 01:19:08.309674 Total UI for P1: 0, mck2ui 16
7638 01:19:08.313059 best dqsien dly found for B0: ( 1, 9, 14)
7639 01:19:08.316652 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7640 01:19:08.319993 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 01:19:08.323040 Total UI for P1: 0, mck2ui 16
7642 01:19:08.326260 best dqsien dly found for B1: ( 1, 9, 22)
7643 01:19:08.329365 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7644 01:19:08.332911 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7645 01:19:08.333384
7646 01:19:08.339785 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7647 01:19:08.342778 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7648 01:19:08.346211 [Gating] SW calibration Done
7649 01:19:08.346688 ==
7650 01:19:08.349905 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 01:19:08.352884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 01:19:08.353361 ==
7653 01:19:08.353868 RX Vref Scan: 0
7654 01:19:08.354351
7655 01:19:08.356053 RX Vref 0 -> 0, step: 1
7656 01:19:08.356528
7657 01:19:08.359305 RX Delay 0 -> 252, step: 8
7658 01:19:08.362893 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7659 01:19:08.365732 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7660 01:19:08.373000 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7661 01:19:08.376172 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7662 01:19:08.379415 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7663 01:19:08.382382 iDelay=192, Bit 5, Center 115 (64 ~ 167) 104
7664 01:19:08.385945 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7665 01:19:08.393007 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7666 01:19:08.395531 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7667 01:19:08.399031 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7668 01:19:08.402235 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7669 01:19:08.405892 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7670 01:19:08.412387 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7671 01:19:08.415737 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7672 01:19:08.418917 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7673 01:19:08.422293 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7674 01:19:08.422753 ==
7675 01:19:08.425637 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 01:19:08.432458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 01:19:08.433014 ==
7678 01:19:08.433385 DQS Delay:
7679 01:19:08.436126 DQS0 = 0, DQS1 = 0
7680 01:19:08.436679 DQM Delay:
7681 01:19:08.437046 DQM0 = 128, DQM1 = 124
7682 01:19:08.438994 DQ Delay:
7683 01:19:08.442081 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7684 01:19:08.445580 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
7685 01:19:08.448830 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7686 01:19:08.452071 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7687 01:19:08.452543
7688 01:19:08.452905
7689 01:19:08.453239 ==
7690 01:19:08.455401 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 01:19:08.462120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 01:19:08.462585 ==
7693 01:19:08.462954
7694 01:19:08.463291
7695 01:19:08.463615 TX Vref Scan disable
7696 01:19:08.464941 == TX Byte 0 ==
7697 01:19:08.468847 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7698 01:19:08.471474 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7699 01:19:08.475595 == TX Byte 1 ==
7700 01:19:08.478758 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7701 01:19:08.485446 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7702 01:19:08.486058 ==
7703 01:19:08.488356 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 01:19:08.491807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 01:19:08.492309 ==
7706 01:19:08.504297
7707 01:19:08.507479 TX Vref early break, caculate TX vref
7708 01:19:08.511081 TX Vref=16, minBit 13, minWin=21, winSum=366
7709 01:19:08.514395 TX Vref=18, minBit 0, minWin=23, winSum=380
7710 01:19:08.517330 TX Vref=20, minBit 0, minWin=23, winSum=386
7711 01:19:08.521265 TX Vref=22, minBit 2, minWin=24, winSum=393
7712 01:19:08.524506 TX Vref=24, minBit 0, minWin=24, winSum=402
7713 01:19:08.530950 TX Vref=26, minBit 2, minWin=25, winSum=416
7714 01:19:08.534424 TX Vref=28, minBit 2, minWin=25, winSum=416
7715 01:19:08.537706 TX Vref=30, minBit 4, minWin=24, winSum=406
7716 01:19:08.541052 TX Vref=32, minBit 0, minWin=24, winSum=398
7717 01:19:08.544200 TX Vref=34, minBit 11, minWin=23, winSum=389
7718 01:19:08.551267 [TxChooseVref] Worse bit 2, Min win 25, Win sum 416, Final Vref 26
7719 01:19:08.551828
7720 01:19:08.553976 Final TX Range 0 Vref 26
7721 01:19:08.554438
7722 01:19:08.554803 ==
7723 01:19:08.557399 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 01:19:08.560867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 01:19:08.561418 ==
7726 01:19:08.561838
7727 01:19:08.562179
7728 01:19:08.564039 TX Vref Scan disable
7729 01:19:08.570386 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7730 01:19:08.570864 == TX Byte 0 ==
7731 01:19:08.573828 u2DelayCellOfst[0]=15 cells (4 PI)
7732 01:19:08.577301 u2DelayCellOfst[1]=18 cells (5 PI)
7733 01:19:08.580831 u2DelayCellOfst[2]=15 cells (4 PI)
7734 01:19:08.583445 u2DelayCellOfst[3]=15 cells (4 PI)
7735 01:19:08.587196 u2DelayCellOfst[4]=11 cells (3 PI)
7736 01:19:08.590271 u2DelayCellOfst[5]=0 cells (0 PI)
7737 01:19:08.593427 u2DelayCellOfst[6]=18 cells (5 PI)
7738 01:19:08.596853 u2DelayCellOfst[7]=18 cells (5 PI)
7739 01:19:08.600424 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7740 01:19:08.603400 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7741 01:19:08.606989 == TX Byte 1 ==
7742 01:19:08.610137 u2DelayCellOfst[8]=0 cells (0 PI)
7743 01:19:08.613550 u2DelayCellOfst[9]=3 cells (1 PI)
7744 01:19:08.614031 u2DelayCellOfst[10]=7 cells (2 PI)
7745 01:19:08.616706 u2DelayCellOfst[11]=3 cells (1 PI)
7746 01:19:08.620092 u2DelayCellOfst[12]=15 cells (4 PI)
7747 01:19:08.623534 u2DelayCellOfst[13]=11 cells (3 PI)
7748 01:19:08.626720 u2DelayCellOfst[14]=18 cells (5 PI)
7749 01:19:08.630170 u2DelayCellOfst[15]=11 cells (3 PI)
7750 01:19:08.636633 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7751 01:19:08.640024 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7752 01:19:08.640492 DramC Write-DBI on
7753 01:19:08.640860 ==
7754 01:19:08.643212 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 01:19:08.650160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 01:19:08.650769 ==
7757 01:19:08.651147
7758 01:19:08.651484
7759 01:19:08.651810 TX Vref Scan disable
7760 01:19:08.654562 == TX Byte 0 ==
7761 01:19:08.657860 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7762 01:19:08.660583 == TX Byte 1 ==
7763 01:19:08.663952 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7764 01:19:08.667836 DramC Write-DBI off
7765 01:19:08.668388
7766 01:19:08.668757 [DATLAT]
7767 01:19:08.669093 Freq=1600, CH0 RK0
7768 01:19:08.669423
7769 01:19:08.670628 DATLAT Default: 0xf
7770 01:19:08.671089 0, 0xFFFF, sum = 0
7771 01:19:08.674296 1, 0xFFFF, sum = 0
7772 01:19:08.677335 2, 0xFFFF, sum = 0
7773 01:19:08.677851 3, 0xFFFF, sum = 0
7774 01:19:08.680306 4, 0xFFFF, sum = 0
7775 01:19:08.680773 5, 0xFFFF, sum = 0
7776 01:19:08.684390 6, 0xFFFF, sum = 0
7777 01:19:08.684955 7, 0xFFFF, sum = 0
7778 01:19:08.687687 8, 0xFFFF, sum = 0
7779 01:19:08.688249 9, 0xFFFF, sum = 0
7780 01:19:08.690361 10, 0xFFFF, sum = 0
7781 01:19:08.690830 11, 0xFFFF, sum = 0
7782 01:19:08.693816 12, 0xFFFF, sum = 0
7783 01:19:08.694379 13, 0xFFFF, sum = 0
7784 01:19:08.697059 14, 0x0, sum = 1
7785 01:19:08.697672 15, 0x0, sum = 2
7786 01:19:08.700160 16, 0x0, sum = 3
7787 01:19:08.700630 17, 0x0, sum = 4
7788 01:19:08.703520 best_step = 15
7789 01:19:08.704029
7790 01:19:08.704400 ==
7791 01:19:08.707138 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 01:19:08.710241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 01:19:08.710827 ==
7794 01:19:08.713327 RX Vref Scan: 1
7795 01:19:08.713863
7796 01:19:08.714234 Set Vref Range= 24 -> 127
7797 01:19:08.714577
7798 01:19:08.717074 RX Vref 24 -> 127, step: 1
7799 01:19:08.717573
7800 01:19:08.720323 RX Delay 11 -> 252, step: 4
7801 01:19:08.720924
7802 01:19:08.723559 Set Vref, RX VrefLevel [Byte0]: 24
7803 01:19:08.727077 [Byte1]: 24
7804 01:19:08.727630
7805 01:19:08.729925 Set Vref, RX VrefLevel [Byte0]: 25
7806 01:19:08.733169 [Byte1]: 25
7807 01:19:08.737267
7808 01:19:08.737761 Set Vref, RX VrefLevel [Byte0]: 26
7809 01:19:08.740513 [Byte1]: 26
7810 01:19:08.744269
7811 01:19:08.747591 Set Vref, RX VrefLevel [Byte0]: 27
7812 01:19:08.750947 [Byte1]: 27
7813 01:19:08.751501
7814 01:19:08.754897 Set Vref, RX VrefLevel [Byte0]: 28
7815 01:19:08.757563 [Byte1]: 28
7816 01:19:08.758122
7817 01:19:08.760818 Set Vref, RX VrefLevel [Byte0]: 29
7818 01:19:08.764180 [Byte1]: 29
7819 01:19:08.767852
7820 01:19:08.768403 Set Vref, RX VrefLevel [Byte0]: 30
7821 01:19:08.770689 [Byte1]: 30
7822 01:19:08.774914
7823 01:19:08.775499 Set Vref, RX VrefLevel [Byte0]: 31
7824 01:19:08.778374 [Byte1]: 31
7825 01:19:08.782532
7826 01:19:08.783097 Set Vref, RX VrefLevel [Byte0]: 32
7827 01:19:08.785554 [Byte1]: 32
7828 01:19:08.790142
7829 01:19:08.790795 Set Vref, RX VrefLevel [Byte0]: 33
7830 01:19:08.793871 [Byte1]: 33
7831 01:19:08.797893
7832 01:19:08.798440 Set Vref, RX VrefLevel [Byte0]: 34
7833 01:19:08.801155 [Byte1]: 34
7834 01:19:08.805771
7835 01:19:08.806321 Set Vref, RX VrefLevel [Byte0]: 35
7836 01:19:08.808901 [Byte1]: 35
7837 01:19:08.813219
7838 01:19:08.813815 Set Vref, RX VrefLevel [Byte0]: 36
7839 01:19:08.816425 [Byte1]: 36
7840 01:19:08.821007
7841 01:19:08.821606 Set Vref, RX VrefLevel [Byte0]: 37
7842 01:19:08.823813 [Byte1]: 37
7843 01:19:08.828845
7844 01:19:08.829394 Set Vref, RX VrefLevel [Byte0]: 38
7845 01:19:08.831330 [Byte1]: 38
7846 01:19:08.836354
7847 01:19:08.836904 Set Vref, RX VrefLevel [Byte0]: 39
7848 01:19:08.839193 [Byte1]: 39
7849 01:19:08.843694
7850 01:19:08.844308 Set Vref, RX VrefLevel [Byte0]: 40
7851 01:19:08.846940 [Byte1]: 40
7852 01:19:08.851551
7853 01:19:08.852397 Set Vref, RX VrefLevel [Byte0]: 41
7854 01:19:08.854757 [Byte1]: 41
7855 01:19:08.858803
7856 01:19:08.859380 Set Vref, RX VrefLevel [Byte0]: 42
7857 01:19:08.862051 [Byte1]: 42
7858 01:19:08.866823
7859 01:19:08.867669 Set Vref, RX VrefLevel [Byte0]: 43
7860 01:19:08.870415 [Byte1]: 43
7861 01:19:08.873898
7862 01:19:08.874449 Set Vref, RX VrefLevel [Byte0]: 44
7863 01:19:08.877381 [Byte1]: 44
7864 01:19:08.881690
7865 01:19:08.882239 Set Vref, RX VrefLevel [Byte0]: 45
7866 01:19:08.884906 [Byte1]: 45
7867 01:19:08.889181
7868 01:19:08.889785 Set Vref, RX VrefLevel [Byte0]: 46
7869 01:19:08.892542 [Byte1]: 46
7870 01:19:08.897007
7871 01:19:08.897584 Set Vref, RX VrefLevel [Byte0]: 47
7872 01:19:08.900431 [Byte1]: 47
7873 01:19:08.904857
7874 01:19:08.905408 Set Vref, RX VrefLevel [Byte0]: 48
7875 01:19:08.907413 [Byte1]: 48
7876 01:19:08.912079
7877 01:19:08.912779 Set Vref, RX VrefLevel [Byte0]: 49
7878 01:19:08.915900 [Byte1]: 49
7879 01:19:08.919593
7880 01:19:08.920053 Set Vref, RX VrefLevel [Byte0]: 50
7881 01:19:08.922717 [Byte1]: 50
7882 01:19:08.927751
7883 01:19:08.928300 Set Vref, RX VrefLevel [Byte0]: 51
7884 01:19:08.930670 [Byte1]: 51
7885 01:19:08.934686
7886 01:19:08.935146 Set Vref, RX VrefLevel [Byte0]: 52
7887 01:19:08.938175 [Byte1]: 52
7888 01:19:08.942668
7889 01:19:08.943217 Set Vref, RX VrefLevel [Byte0]: 53
7890 01:19:08.946143 [Byte1]: 53
7891 01:19:08.949951
7892 01:19:08.950503 Set Vref, RX VrefLevel [Byte0]: 54
7893 01:19:08.953367 [Byte1]: 54
7894 01:19:08.957838
7895 01:19:08.958416 Set Vref, RX VrefLevel [Byte0]: 55
7896 01:19:08.960962 [Byte1]: 55
7897 01:19:08.965150
7898 01:19:08.965636 Set Vref, RX VrefLevel [Byte0]: 56
7899 01:19:08.968664 [Byte1]: 56
7900 01:19:08.972982
7901 01:19:08.973454 Set Vref, RX VrefLevel [Byte0]: 57
7902 01:19:08.976178 [Byte1]: 57
7903 01:19:08.980446
7904 01:19:08.980905 Set Vref, RX VrefLevel [Byte0]: 58
7905 01:19:08.984845 [Byte1]: 58
7906 01:19:08.988364
7907 01:19:08.988915 Set Vref, RX VrefLevel [Byte0]: 59
7908 01:19:08.992046 [Byte1]: 59
7909 01:19:08.995720
7910 01:19:08.996303 Set Vref, RX VrefLevel [Byte0]: 60
7911 01:19:08.999051 [Byte1]: 60
7912 01:19:09.003411
7913 01:19:09.003872 Set Vref, RX VrefLevel [Byte0]: 61
7914 01:19:09.006415 [Byte1]: 61
7915 01:19:09.010818
7916 01:19:09.011280 Set Vref, RX VrefLevel [Byte0]: 62
7917 01:19:09.014437 [Byte1]: 62
7918 01:19:09.018518
7919 01:19:09.019070 Set Vref, RX VrefLevel [Byte0]: 63
7920 01:19:09.022108 [Byte1]: 63
7921 01:19:09.026268
7922 01:19:09.026870 Set Vref, RX VrefLevel [Byte0]: 64
7923 01:19:09.029643 [Byte1]: 64
7924 01:19:09.033766
7925 01:19:09.034330 Set Vref, RX VrefLevel [Byte0]: 65
7926 01:19:09.037074 [Byte1]: 65
7927 01:19:09.041292
7928 01:19:09.041920 Set Vref, RX VrefLevel [Byte0]: 66
7929 01:19:09.044696 [Byte1]: 66
7930 01:19:09.049342
7931 01:19:09.049970 Set Vref, RX VrefLevel [Byte0]: 67
7932 01:19:09.052256 [Byte1]: 67
7933 01:19:09.056749
7934 01:19:09.057299 Set Vref, RX VrefLevel [Byte0]: 68
7935 01:19:09.060095 [Byte1]: 68
7936 01:19:09.064097
7937 01:19:09.064660 Set Vref, RX VrefLevel [Byte0]: 69
7938 01:19:09.067649 [Byte1]: 69
7939 01:19:09.072231
7940 01:19:09.072785 Set Vref, RX VrefLevel [Byte0]: 70
7941 01:19:09.075387 [Byte1]: 70
7942 01:19:09.079556
7943 01:19:09.080018 Set Vref, RX VrefLevel [Byte0]: 71
7944 01:19:09.083019 [Byte1]: 71
7945 01:19:09.087346
7946 01:19:09.087981 Set Vref, RX VrefLevel [Byte0]: 72
7947 01:19:09.090640 [Byte1]: 72
7948 01:19:09.094707
7949 01:19:09.095257 Set Vref, RX VrefLevel [Byte0]: 73
7950 01:19:09.098163 [Byte1]: 73
7951 01:19:09.102326
7952 01:19:09.102840 Set Vref, RX VrefLevel [Byte0]: 74
7953 01:19:09.105381 [Byte1]: 74
7954 01:19:09.110049
7955 01:19:09.110543 Set Vref, RX VrefLevel [Byte0]: 75
7956 01:19:09.113108 [Byte1]: 75
7957 01:19:09.117756
7958 01:19:09.118348 Set Vref, RX VrefLevel [Byte0]: 76
7959 01:19:09.120994 [Byte1]: 76
7960 01:19:09.125289
7961 01:19:09.125799 Final RX Vref Byte 0 = 64 to rank0
7962 01:19:09.128782 Final RX Vref Byte 1 = 63 to rank0
7963 01:19:09.131701 Final RX Vref Byte 0 = 64 to rank1
7964 01:19:09.134941 Final RX Vref Byte 1 = 63 to rank1==
7965 01:19:09.138362 Dram Type= 6, Freq= 0, CH_0, rank 0
7966 01:19:09.144837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 01:19:09.145421 ==
7968 01:19:09.145845 DQS Delay:
7969 01:19:09.148592 DQS0 = 0, DQS1 = 0
7970 01:19:09.149153 DQM Delay:
7971 01:19:09.149574 DQM0 = 126, DQM1 = 120
7972 01:19:09.151951 DQ Delay:
7973 01:19:09.154720 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7974 01:19:09.158100 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7975 01:19:09.161692 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7976 01:19:09.164840 DQ12 =124, DQ13 =126, DQ14 =132, DQ15 =126
7977 01:19:09.165303
7978 01:19:09.165703
7979 01:19:09.166044
7980 01:19:09.168171 [DramC_TX_OE_Calibration] TA2
7981 01:19:09.171745 Original DQ_B0 (3 6) =30, OEN = 27
7982 01:19:09.175044 Original DQ_B1 (3 6) =30, OEN = 27
7983 01:19:09.178097 24, 0x0, End_B0=24 End_B1=24
7984 01:19:09.178569 25, 0x0, End_B0=25 End_B1=25
7985 01:19:09.181507 26, 0x0, End_B0=26 End_B1=26
7986 01:19:09.184953 27, 0x0, End_B0=27 End_B1=27
7987 01:19:09.188205 28, 0x0, End_B0=28 End_B1=28
7988 01:19:09.191513 29, 0x0, End_B0=29 End_B1=29
7989 01:19:09.191978 30, 0x0, End_B0=30 End_B1=30
7990 01:19:09.194843 31, 0x4141, End_B0=30 End_B1=30
7991 01:19:09.198458 Byte0 end_step=30 best_step=27
7992 01:19:09.201069 Byte1 end_step=30 best_step=27
7993 01:19:09.204480 Byte0 TX OE(2T, 0.5T) = (3, 3)
7994 01:19:09.208145 Byte1 TX OE(2T, 0.5T) = (3, 3)
7995 01:19:09.208701
7996 01:19:09.209065
7997 01:19:09.214547 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
7998 01:19:09.217830 CH0 RK0: MR19=303, MR18=1010
7999 01:19:09.224456 CH0_RK0: MR19=0x303, MR18=0x1010, DQSOSC=401, MR23=63, INC=22, DEC=15
8000 01:19:09.224923
8001 01:19:09.228051 ----->DramcWriteLeveling(PI) begin...
8002 01:19:09.228627 ==
8003 01:19:09.231298 Dram Type= 6, Freq= 0, CH_0, rank 1
8004 01:19:09.234101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8005 01:19:09.234570 ==
8006 01:19:09.237831 Write leveling (Byte 0): 35 => 35
8007 01:19:09.241697 Write leveling (Byte 1): 27 => 27
8008 01:19:09.244596 DramcWriteLeveling(PI) end<-----
8009 01:19:09.245055
8010 01:19:09.245417 ==
8011 01:19:09.248125 Dram Type= 6, Freq= 0, CH_0, rank 1
8012 01:19:09.251082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 01:19:09.251549 ==
8014 01:19:09.254365 [Gating] SW mode calibration
8015 01:19:09.261340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8016 01:19:09.267434 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8017 01:19:09.270562 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 01:19:09.277604 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 01:19:09.280654 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 01:19:09.283846 1 4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8021 01:19:09.290879 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8022 01:19:09.293493 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 01:19:09.297758 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8024 01:19:09.303815 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 01:19:09.307386 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 01:19:09.310616 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 01:19:09.317558 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8028 01:19:09.320039 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8029 01:19:09.324184 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8030 01:19:09.330794 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8031 01:19:09.334061 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 01:19:09.336889 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 01:19:09.340599 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 01:19:09.346935 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 01:19:09.350349 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8036 01:19:09.353686 1 6 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8037 01:19:09.360879 1 6 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8038 01:19:09.364145 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 01:19:09.367544 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 01:19:09.373278 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 01:19:09.377008 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 01:19:09.380010 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 01:19:09.387223 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 01:19:09.389952 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8045 01:19:09.393361 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8046 01:19:09.400023 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8047 01:19:09.403001 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 01:19:09.406584 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 01:19:09.412892 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 01:19:09.416134 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 01:19:09.419813 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 01:19:09.426614 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 01:19:09.430232 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 01:19:09.433078 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 01:19:09.439943 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 01:19:09.442938 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 01:19:09.446483 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 01:19:09.453064 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 01:19:09.456678 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8060 01:19:09.459504 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8061 01:19:09.462783 Total UI for P1: 0, mck2ui 16
8062 01:19:09.466102 best dqsien dly found for B0: ( 1, 9, 8)
8063 01:19:09.472344 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8064 01:19:09.475981 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8065 01:19:09.479468 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 01:19:09.482176 Total UI for P1: 0, mck2ui 16
8067 01:19:09.485864 best dqsien dly found for B1: ( 1, 9, 18)
8068 01:19:09.489286 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8069 01:19:09.492615 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8070 01:19:09.493166
8071 01:19:09.498761 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8072 01:19:09.502241 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8073 01:19:09.505230 [Gating] SW calibration Done
8074 01:19:09.505771 ==
8075 01:19:09.508380 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 01:19:09.512055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 01:19:09.512517 ==
8078 01:19:09.512998 RX Vref Scan: 0
8079 01:19:09.515898
8080 01:19:09.516389 RX Vref 0 -> 0, step: 1
8081 01:19:09.516780
8082 01:19:09.518358 RX Delay 0 -> 252, step: 8
8083 01:19:09.521683 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8084 01:19:09.525198 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8085 01:19:09.531661 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8086 01:19:09.535042 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8087 01:19:09.538302 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8088 01:19:09.541439 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8089 01:19:09.544823 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8090 01:19:09.551560 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8091 01:19:09.554910 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8092 01:19:09.558072 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8093 01:19:09.561375 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8094 01:19:09.564838 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8095 01:19:09.571316 iDelay=200, Bit 12, Center 123 (64 ~ 183) 120
8096 01:19:09.574352 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8097 01:19:09.577903 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8098 01:19:09.581572 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8099 01:19:09.581859 ==
8100 01:19:09.584321 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 01:19:09.591431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 01:19:09.591755 ==
8103 01:19:09.592011 DQS Delay:
8104 01:19:09.594270 DQS0 = 0, DQS1 = 0
8105 01:19:09.594682 DQM Delay:
8106 01:19:09.597686 DQM0 = 127, DQM1 = 120
8107 01:19:09.598103 DQ Delay:
8108 01:19:09.600992 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8109 01:19:09.604753 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8110 01:19:09.607492 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8111 01:19:09.610977 DQ12 =123, DQ13 =127, DQ14 =131, DQ15 =127
8112 01:19:09.611439
8113 01:19:09.611981
8114 01:19:09.612493 ==
8115 01:19:09.614186 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 01:19:09.621064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 01:19:09.621567 ==
8118 01:19:09.621942
8119 01:19:09.622277
8120 01:19:09.622600 TX Vref Scan disable
8121 01:19:09.624517 == TX Byte 0 ==
8122 01:19:09.628139 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8123 01:19:09.634249 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8124 01:19:09.634689 == TX Byte 1 ==
8125 01:19:09.637507 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8126 01:19:09.644315 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8127 01:19:09.644753 ==
8128 01:19:09.647660 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 01:19:09.650890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 01:19:09.651307 ==
8131 01:19:09.664292
8132 01:19:09.667552 TX Vref early break, caculate TX vref
8133 01:19:09.670836 TX Vref=16, minBit 8, minWin=21, winSum=367
8134 01:19:09.674144 TX Vref=18, minBit 8, minWin=22, winSum=375
8135 01:19:09.677681 TX Vref=20, minBit 8, minWin=22, winSum=382
8136 01:19:09.680942 TX Vref=22, minBit 8, minWin=22, winSum=388
8137 01:19:09.684181 TX Vref=24, minBit 8, minWin=24, winSum=402
8138 01:19:09.690964 TX Vref=26, minBit 8, minWin=24, winSum=406
8139 01:19:09.694000 TX Vref=28, minBit 8, minWin=24, winSum=412
8140 01:19:09.697099 TX Vref=30, minBit 8, minWin=24, winSum=411
8141 01:19:09.700557 TX Vref=32, minBit 8, minWin=23, winSum=393
8142 01:19:09.704081 TX Vref=34, minBit 8, minWin=22, winSum=390
8143 01:19:09.710784 [TxChooseVref] Worse bit 8, Min win 24, Win sum 412, Final Vref 28
8144 01:19:09.711204
8145 01:19:09.713958 Final TX Range 0 Vref 28
8146 01:19:09.714523
8147 01:19:09.714862 ==
8148 01:19:09.717564 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 01:19:09.720625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 01:19:09.721150 ==
8151 01:19:09.721487
8152 01:19:09.721839
8153 01:19:09.723762 TX Vref Scan disable
8154 01:19:09.730235 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8155 01:19:09.730738 == TX Byte 0 ==
8156 01:19:09.733626 u2DelayCellOfst[0]=15 cells (4 PI)
8157 01:19:09.736993 u2DelayCellOfst[1]=18 cells (5 PI)
8158 01:19:09.740294 u2DelayCellOfst[2]=11 cells (3 PI)
8159 01:19:09.743776 u2DelayCellOfst[3]=11 cells (3 PI)
8160 01:19:09.746790 u2DelayCellOfst[4]=7 cells (2 PI)
8161 01:19:09.750193 u2DelayCellOfst[5]=0 cells (0 PI)
8162 01:19:09.753557 u2DelayCellOfst[6]=18 cells (5 PI)
8163 01:19:09.757187 u2DelayCellOfst[7]=15 cells (4 PI)
8164 01:19:09.760574 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8165 01:19:09.763676 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8166 01:19:09.766989 == TX Byte 1 ==
8167 01:19:09.770127 u2DelayCellOfst[8]=0 cells (0 PI)
8168 01:19:09.770682 u2DelayCellOfst[9]=0 cells (0 PI)
8169 01:19:09.773464 u2DelayCellOfst[10]=11 cells (3 PI)
8170 01:19:09.776736 u2DelayCellOfst[11]=7 cells (2 PI)
8171 01:19:09.780269 u2DelayCellOfst[12]=15 cells (4 PI)
8172 01:19:09.783369 u2DelayCellOfst[13]=15 cells (4 PI)
8173 01:19:09.786499 u2DelayCellOfst[14]=15 cells (4 PI)
8174 01:19:09.790240 u2DelayCellOfst[15]=11 cells (3 PI)
8175 01:19:09.793352 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8176 01:19:09.799746 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8177 01:19:09.800223 DramC Write-DBI on
8178 01:19:09.800589 ==
8179 01:19:09.803633 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 01:19:09.809818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 01:19:09.810382 ==
8182 01:19:09.810756
8183 01:19:09.811097
8184 01:19:09.811422 TX Vref Scan disable
8185 01:19:09.813809 == TX Byte 0 ==
8186 01:19:09.817341 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8187 01:19:09.820943 == TX Byte 1 ==
8188 01:19:09.824008 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8189 01:19:09.827546 DramC Write-DBI off
8190 01:19:09.828202
8191 01:19:09.828714 [DATLAT]
8192 01:19:09.829069 Freq=1600, CH0 RK1
8193 01:19:09.829403
8194 01:19:09.830416 DATLAT Default: 0xf
8195 01:19:09.830880 0, 0xFFFF, sum = 0
8196 01:19:09.833634 1, 0xFFFF, sum = 0
8197 01:19:09.837003 2, 0xFFFF, sum = 0
8198 01:19:09.837473 3, 0xFFFF, sum = 0
8199 01:19:09.840926 4, 0xFFFF, sum = 0
8200 01:19:09.841562 5, 0xFFFF, sum = 0
8201 01:19:09.843906 6, 0xFFFF, sum = 0
8202 01:19:09.844376 7, 0xFFFF, sum = 0
8203 01:19:09.847361 8, 0xFFFF, sum = 0
8204 01:19:09.847831 9, 0xFFFF, sum = 0
8205 01:19:09.850454 10, 0xFFFF, sum = 0
8206 01:19:09.850923 11, 0xFFFF, sum = 0
8207 01:19:09.853677 12, 0xFFFF, sum = 0
8208 01:19:09.854174 13, 0xCFFF, sum = 0
8209 01:19:09.856675 14, 0x0, sum = 1
8210 01:19:09.857143 15, 0x0, sum = 2
8211 01:19:09.860112 16, 0x0, sum = 3
8212 01:19:09.860583 17, 0x0, sum = 4
8213 01:19:09.863825 best_step = 15
8214 01:19:09.864389
8215 01:19:09.864758 ==
8216 01:19:09.866948 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 01:19:09.870512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 01:19:09.871078 ==
8219 01:19:09.873558 RX Vref Scan: 0
8220 01:19:09.874043
8221 01:19:09.874592 RX Vref 0 -> 0, step: 1
8222 01:19:09.875013
8223 01:19:09.876939 RX Delay 3 -> 252, step: 4
8224 01:19:09.880106 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8225 01:19:09.886882 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8226 01:19:09.890415 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8227 01:19:09.893362 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8228 01:19:09.897014 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8229 01:19:09.900358 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8230 01:19:09.906774 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8231 01:19:09.909842 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8232 01:19:09.913233 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8233 01:19:09.916393 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8234 01:19:09.919838 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8235 01:19:09.926922 iDelay=191, Bit 11, Center 110 (55 ~ 166) 112
8236 01:19:09.929697 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8237 01:19:09.933026 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8238 01:19:09.936518 iDelay=191, Bit 14, Center 126 (67 ~ 186) 120
8239 01:19:09.943325 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8240 01:19:09.943880 ==
8241 01:19:09.946540 Dram Type= 6, Freq= 0, CH_0, rank 1
8242 01:19:09.949584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 01:19:09.950048 ==
8244 01:19:09.950409 DQS Delay:
8245 01:19:09.953137 DQS0 = 0, DQS1 = 0
8246 01:19:09.953735 DQM Delay:
8247 01:19:09.956547 DQM0 = 124, DQM1 = 117
8248 01:19:09.957097 DQ Delay:
8249 01:19:09.959771 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8250 01:19:09.963003 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8251 01:19:09.966364 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =110
8252 01:19:09.969777 DQ12 =124, DQ13 =122, DQ14 =126, DQ15 =124
8253 01:19:09.970333
8254 01:19:09.970694
8255 01:19:09.972799
8256 01:19:09.973485 [DramC_TX_OE_Calibration] TA2
8257 01:19:09.976554 Original DQ_B0 (3 6) =30, OEN = 27
8258 01:19:09.979524 Original DQ_B1 (3 6) =30, OEN = 27
8259 01:19:09.982876 24, 0x0, End_B0=24 End_B1=24
8260 01:19:09.985894 25, 0x0, End_B0=25 End_B1=25
8261 01:19:09.989293 26, 0x0, End_B0=26 End_B1=26
8262 01:19:09.989828 27, 0x0, End_B0=27 End_B1=27
8263 01:19:09.992563 28, 0x0, End_B0=28 End_B1=28
8264 01:19:09.996232 29, 0x0, End_B0=29 End_B1=29
8265 01:19:09.999304 30, 0x0, End_B0=30 End_B1=30
8266 01:19:10.002911 31, 0x4545, End_B0=30 End_B1=30
8267 01:19:10.003484 Byte0 end_step=30 best_step=27
8268 01:19:10.006194 Byte1 end_step=30 best_step=27
8269 01:19:10.009497 Byte0 TX OE(2T, 0.5T) = (3, 3)
8270 01:19:10.012414 Byte1 TX OE(2T, 0.5T) = (3, 3)
8271 01:19:10.012909
8272 01:19:10.013450
8273 01:19:10.019823 [DQSOSCAuto] RK1, (LSB)MR18= 0x2410, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
8274 01:19:10.023144 CH0 RK1: MR19=303, MR18=2410
8275 01:19:10.029567 CH0_RK1: MR19=0x303, MR18=0x2410, DQSOSC=391, MR23=63, INC=24, DEC=16
8276 01:19:10.032529 [RxdqsGatingPostProcess] freq 1600
8277 01:19:10.040042 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8278 01:19:10.042785 best DQS0 dly(2T, 0.5T) = (1, 1)
8279 01:19:10.043243 best DQS1 dly(2T, 0.5T) = (1, 1)
8280 01:19:10.045962 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8281 01:19:10.049163 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8282 01:19:10.052871 best DQS0 dly(2T, 0.5T) = (1, 1)
8283 01:19:10.055894 best DQS1 dly(2T, 0.5T) = (1, 1)
8284 01:19:10.059284 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8285 01:19:10.062527 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8286 01:19:10.066043 Pre-setting of DQS Precalculation
8287 01:19:10.069455 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8288 01:19:10.072376 ==
8289 01:19:10.072837 Dram Type= 6, Freq= 0, CH_1, rank 0
8290 01:19:10.079502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8291 01:19:10.080026 ==
8292 01:19:10.082260 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8293 01:19:10.089320 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8294 01:19:10.092435 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8295 01:19:10.099028 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8296 01:19:10.106981 [CA 0] Center 41 (13~70) winsize 58
8297 01:19:10.110115 [CA 1] Center 42 (12~72) winsize 61
8298 01:19:10.113702 [CA 2] Center 37 (9~66) winsize 58
8299 01:19:10.116696 [CA 3] Center 37 (8~66) winsize 59
8300 01:19:10.120741 [CA 4] Center 37 (8~67) winsize 60
8301 01:19:10.123668 [CA 5] Center 36 (7~65) winsize 59
8302 01:19:10.124271
8303 01:19:10.127409 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8304 01:19:10.127964
8305 01:19:10.130302 [CATrainingPosCal] consider 1 rank data
8306 01:19:10.133612 u2DelayCellTimex100 = 258/100 ps
8307 01:19:10.136905 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8308 01:19:10.143289 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8309 01:19:10.146920 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8310 01:19:10.150112 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8311 01:19:10.153383 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8312 01:19:10.157016 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8313 01:19:10.157593
8314 01:19:10.159972 CA PerBit enable=1, Macro0, CA PI delay=36
8315 01:19:10.160525
8316 01:19:10.163406 [CBTSetCACLKResult] CA Dly = 36
8317 01:19:10.166638 CS Dly: 9 (0~40)
8318 01:19:10.170036 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8319 01:19:10.173416 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8320 01:19:10.173905 ==
8321 01:19:10.176912 Dram Type= 6, Freq= 0, CH_1, rank 1
8322 01:19:10.179883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8323 01:19:10.183267 ==
8324 01:19:10.186478 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8325 01:19:10.189822 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8326 01:19:10.196746 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8327 01:19:10.202769 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8328 01:19:10.210419 [CA 0] Center 42 (12~72) winsize 61
8329 01:19:10.213843 [CA 1] Center 42 (12~72) winsize 61
8330 01:19:10.216732 [CA 2] Center 38 (9~67) winsize 59
8331 01:19:10.220501 [CA 3] Center 36 (7~66) winsize 60
8332 01:19:10.223707 [CA 4] Center 38 (8~68) winsize 61
8333 01:19:10.226724 [CA 5] Center 36 (6~66) winsize 61
8334 01:19:10.227174
8335 01:19:10.230472 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8336 01:19:10.231024
8337 01:19:10.233561 [CATrainingPosCal] consider 2 rank data
8338 01:19:10.236670 u2DelayCellTimex100 = 258/100 ps
8339 01:19:10.240062 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8340 01:19:10.246401 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8341 01:19:10.249894 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8342 01:19:10.253389 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8343 01:19:10.256428 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8344 01:19:10.260110 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8345 01:19:10.260668
8346 01:19:10.263524 CA PerBit enable=1, Macro0, CA PI delay=36
8347 01:19:10.264084
8348 01:19:10.266591 [CBTSetCACLKResult] CA Dly = 36
8349 01:19:10.270332 CS Dly: 11 (0~44)
8350 01:19:10.273408 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8351 01:19:10.276397 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8352 01:19:10.277011
8353 01:19:10.279504 ----->DramcWriteLeveling(PI) begin...
8354 01:19:10.279967 ==
8355 01:19:10.283075 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 01:19:10.289445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 01:19:10.290028 ==
8358 01:19:10.293008 Write leveling (Byte 0): 25 => 25
8359 01:19:10.295807 Write leveling (Byte 1): 28 => 28
8360 01:19:10.296278 DramcWriteLeveling(PI) end<-----
8361 01:19:10.296755
8362 01:19:10.299287 ==
8363 01:19:10.302872 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 01:19:10.306218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 01:19:10.306696 ==
8366 01:19:10.309636 [Gating] SW mode calibration
8367 01:19:10.316107 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8368 01:19:10.319569 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8369 01:19:10.326095 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 01:19:10.329667 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 01:19:10.332548 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 01:19:10.339615 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 01:19:10.343047 1 4 16 | B1->B0 | 3333 3232 | 0 1 | (0 0) (1 1)
8374 01:19:10.346365 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 01:19:10.352714 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 01:19:10.355824 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 01:19:10.359577 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 01:19:10.365946 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 01:19:10.369280 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 01:19:10.372528 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8381 01:19:10.379062 1 5 16 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (1 0)
8382 01:19:10.382338 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 01:19:10.385751 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 01:19:10.392584 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 01:19:10.395334 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 01:19:10.398624 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 01:19:10.405493 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 01:19:10.409046 1 6 12 | B1->B0 | 2323 2424 | 1 0 | (0 0) (0 0)
8389 01:19:10.412123 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8390 01:19:10.418179 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 01:19:10.421656 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 01:19:10.425352 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 01:19:10.431570 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 01:19:10.434870 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 01:19:10.438506 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 01:19:10.445123 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 01:19:10.448384 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8398 01:19:10.451975 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8399 01:19:10.458433 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 01:19:10.461553 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 01:19:10.465102 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 01:19:10.471407 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 01:19:10.474822 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 01:19:10.478231 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 01:19:10.485090 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 01:19:10.487706 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 01:19:10.491230 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 01:19:10.497989 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 01:19:10.501065 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 01:19:10.504264 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 01:19:10.511649 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 01:19:10.513905 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8413 01:19:10.517375 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8414 01:19:10.524749 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 01:19:10.525304 Total UI for P1: 0, mck2ui 16
8416 01:19:10.531307 best dqsien dly found for B0: ( 1, 9, 14)
8417 01:19:10.531867 Total UI for P1: 0, mck2ui 16
8418 01:19:10.534011 best dqsien dly found for B1: ( 1, 9, 16)
8419 01:19:10.540654 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8420 01:19:10.544056 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8421 01:19:10.544516
8422 01:19:10.547158 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8423 01:19:10.550743 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8424 01:19:10.553872 [Gating] SW calibration Done
8425 01:19:10.554427 ==
8426 01:19:10.556901 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 01:19:10.560359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 01:19:10.560947 ==
8429 01:19:10.564010 RX Vref Scan: 0
8430 01:19:10.564460
8431 01:19:10.564817 RX Vref 0 -> 0, step: 1
8432 01:19:10.565150
8433 01:19:10.566764 RX Delay 0 -> 252, step: 8
8434 01:19:10.570269 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8435 01:19:10.576672 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8436 01:19:10.580402 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8437 01:19:10.583347 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8438 01:19:10.587110 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8439 01:19:10.590168 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8440 01:19:10.596603 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8441 01:19:10.600301 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8442 01:19:10.603538 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8443 01:19:10.606697 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8444 01:19:10.609721 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8445 01:19:10.616372 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8446 01:19:10.619736 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8447 01:19:10.623151 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8448 01:19:10.626451 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8449 01:19:10.633141 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8450 01:19:10.633799 ==
8451 01:19:10.636436 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 01:19:10.639710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 01:19:10.640273 ==
8454 01:19:10.640640 DQS Delay:
8455 01:19:10.642704 DQS0 = 0, DQS1 = 0
8456 01:19:10.643220 DQM Delay:
8457 01:19:10.645967 DQM0 = 131, DQM1 = 125
8458 01:19:10.646425 DQ Delay:
8459 01:19:10.649747 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8460 01:19:10.652510 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8461 01:19:10.655888 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8462 01:19:10.658987 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8463 01:19:10.662516
8464 01:19:10.662969
8465 01:19:10.663328 ==
8466 01:19:10.665677 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 01:19:10.669446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 01:19:10.669984 ==
8469 01:19:10.670444
8470 01:19:10.670793
8471 01:19:10.672634 TX Vref Scan disable
8472 01:19:10.673090 == TX Byte 0 ==
8473 01:19:10.679306 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8474 01:19:10.682657 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8475 01:19:10.683219 == TX Byte 1 ==
8476 01:19:10.689104 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8477 01:19:10.692931 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8478 01:19:10.693486 ==
8479 01:19:10.696112 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 01:19:10.699160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 01:19:10.699620 ==
8482 01:19:10.712504
8483 01:19:10.715791 TX Vref early break, caculate TX vref
8484 01:19:10.718785 TX Vref=16, minBit 10, minWin=21, winSum=362
8485 01:19:10.721966 TX Vref=18, minBit 11, minWin=22, winSum=378
8486 01:19:10.725480 TX Vref=20, minBit 11, minWin=21, winSum=380
8487 01:19:10.728882 TX Vref=22, minBit 11, minWin=23, winSum=393
8488 01:19:10.735968 TX Vref=24, minBit 11, minWin=24, winSum=407
8489 01:19:10.739078 TX Vref=26, minBit 1, minWin=25, winSum=414
8490 01:19:10.742098 TX Vref=28, minBit 1, minWin=25, winSum=421
8491 01:19:10.745723 TX Vref=30, minBit 1, minWin=25, winSum=415
8492 01:19:10.748509 TX Vref=32, minBit 5, minWin=24, winSum=409
8493 01:19:10.751945 TX Vref=34, minBit 0, minWin=24, winSum=396
8494 01:19:10.758473 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
8495 01:19:10.759020
8496 01:19:10.761874 Final TX Range 0 Vref 28
8497 01:19:10.762386
8498 01:19:10.762755 ==
8499 01:19:10.765214 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 01:19:10.768338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 01:19:10.768798 ==
8502 01:19:10.769163
8503 01:19:10.771544
8504 01:19:10.771998 TX Vref Scan disable
8505 01:19:10.778065 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8506 01:19:10.778550 == TX Byte 0 ==
8507 01:19:10.781574 u2DelayCellOfst[0]=18 cells (5 PI)
8508 01:19:10.784808 u2DelayCellOfst[1]=15 cells (4 PI)
8509 01:19:10.788135 u2DelayCellOfst[2]=0 cells (0 PI)
8510 01:19:10.791435 u2DelayCellOfst[3]=7 cells (2 PI)
8511 01:19:10.794723 u2DelayCellOfst[4]=7 cells (2 PI)
8512 01:19:10.798042 u2DelayCellOfst[5]=22 cells (6 PI)
8513 01:19:10.801029 u2DelayCellOfst[6]=22 cells (6 PI)
8514 01:19:10.804489 u2DelayCellOfst[7]=7 cells (2 PI)
8515 01:19:10.807748 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8516 01:19:10.811262 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8517 01:19:10.814634 == TX Byte 1 ==
8518 01:19:10.817717 u2DelayCellOfst[8]=0 cells (0 PI)
8519 01:19:10.821082 u2DelayCellOfst[9]=11 cells (3 PI)
8520 01:19:10.824216 u2DelayCellOfst[10]=15 cells (4 PI)
8521 01:19:10.827802 u2DelayCellOfst[11]=7 cells (2 PI)
8522 01:19:10.831005 u2DelayCellOfst[12]=18 cells (5 PI)
8523 01:19:10.834460 u2DelayCellOfst[13]=22 cells (6 PI)
8524 01:19:10.834919 u2DelayCellOfst[14]=22 cells (6 PI)
8525 01:19:10.837277 u2DelayCellOfst[15]=22 cells (6 PI)
8526 01:19:10.844120 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8527 01:19:10.847847 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8528 01:19:10.850845 DramC Write-DBI on
8529 01:19:10.851301 ==
8530 01:19:10.853949 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 01:19:10.857111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 01:19:10.857623 ==
8533 01:19:10.857995
8534 01:19:10.858329
8535 01:19:10.860331 TX Vref Scan disable
8536 01:19:10.860787 == TX Byte 0 ==
8537 01:19:10.866988 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8538 01:19:10.867448 == TX Byte 1 ==
8539 01:19:10.870518 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8540 01:19:10.873789 DramC Write-DBI off
8541 01:19:10.874200
8542 01:19:10.874530 [DATLAT]
8543 01:19:10.877169 Freq=1600, CH1 RK0
8544 01:19:10.877676
8545 01:19:10.878009 DATLAT Default: 0xf
8546 01:19:10.880408 0, 0xFFFF, sum = 0
8547 01:19:10.880827 1, 0xFFFF, sum = 0
8548 01:19:10.883561 2, 0xFFFF, sum = 0
8549 01:19:10.884095 3, 0xFFFF, sum = 0
8550 01:19:10.887384 4, 0xFFFF, sum = 0
8551 01:19:10.890394 5, 0xFFFF, sum = 0
8552 01:19:10.890816 6, 0xFFFF, sum = 0
8553 01:19:10.893731 7, 0xFFFF, sum = 0
8554 01:19:10.894269 8, 0xFFFF, sum = 0
8555 01:19:10.896964 9, 0xFFFF, sum = 0
8556 01:19:10.897711 10, 0xFFFF, sum = 0
8557 01:19:10.900628 11, 0xFFFF, sum = 0
8558 01:19:10.901156 12, 0xFFFF, sum = 0
8559 01:19:10.903668 13, 0x8FFF, sum = 0
8560 01:19:10.904086 14, 0x0, sum = 1
8561 01:19:10.906495 15, 0x0, sum = 2
8562 01:19:10.906915 16, 0x0, sum = 3
8563 01:19:10.910292 17, 0x0, sum = 4
8564 01:19:10.910721 best_step = 15
8565 01:19:10.911053
8566 01:19:10.911360 ==
8567 01:19:10.913245 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 01:19:10.916791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 01:19:10.919853 ==
8570 01:19:10.920265 RX Vref Scan: 1
8571 01:19:10.920723
8572 01:19:10.923526 Set Vref Range= 24 -> 127
8573 01:19:10.923937
8574 01:19:10.926404 RX Vref 24 -> 127, step: 1
8575 01:19:10.926816
8576 01:19:10.927143 RX Delay 11 -> 252, step: 4
8577 01:19:10.927449
8578 01:19:10.929798 Set Vref, RX VrefLevel [Byte0]: 24
8579 01:19:10.933095 [Byte1]: 24
8580 01:19:10.937683
8581 01:19:10.938193 Set Vref, RX VrefLevel [Byte0]: 25
8582 01:19:10.940998 [Byte1]: 25
8583 01:19:10.945422
8584 01:19:10.945987 Set Vref, RX VrefLevel [Byte0]: 26
8585 01:19:10.948137 [Byte1]: 26
8586 01:19:10.952585
8587 01:19:10.953120 Set Vref, RX VrefLevel [Byte0]: 27
8588 01:19:10.956085 [Byte1]: 27
8589 01:19:10.960343
8590 01:19:10.960858 Set Vref, RX VrefLevel [Byte0]: 28
8591 01:19:10.963248 [Byte1]: 28
8592 01:19:10.968108
8593 01:19:10.968627 Set Vref, RX VrefLevel [Byte0]: 29
8594 01:19:10.971405 [Byte1]: 29
8595 01:19:10.975173
8596 01:19:10.975689 Set Vref, RX VrefLevel [Byte0]: 30
8597 01:19:10.978233 [Byte1]: 30
8598 01:19:10.982751
8599 01:19:10.983280 Set Vref, RX VrefLevel [Byte0]: 31
8600 01:19:10.985850 [Byte1]: 31
8601 01:19:10.990717
8602 01:19:10.991184 Set Vref, RX VrefLevel [Byte0]: 32
8603 01:19:10.994052 [Byte1]: 32
8604 01:19:10.998124
8605 01:19:10.998694 Set Vref, RX VrefLevel [Byte0]: 33
8606 01:19:11.001588 [Byte1]: 33
8607 01:19:11.005564
8608 01:19:11.006037 Set Vref, RX VrefLevel [Byte0]: 34
8609 01:19:11.008824 [Byte1]: 34
8610 01:19:11.013410
8611 01:19:11.014018 Set Vref, RX VrefLevel [Byte0]: 35
8612 01:19:11.016797 [Byte1]: 35
8613 01:19:11.020728
8614 01:19:11.021232 Set Vref, RX VrefLevel [Byte0]: 36
8615 01:19:11.024152 [Byte1]: 36
8616 01:19:11.028544
8617 01:19:11.029010 Set Vref, RX VrefLevel [Byte0]: 37
8618 01:19:11.031966 [Byte1]: 37
8619 01:19:11.036329
8620 01:19:11.036910 Set Vref, RX VrefLevel [Byte0]: 38
8621 01:19:11.039466 [Byte1]: 38
8622 01:19:11.043911
8623 01:19:11.044475 Set Vref, RX VrefLevel [Byte0]: 39
8624 01:19:11.046818 [Byte1]: 39
8625 01:19:11.051411
8626 01:19:11.051876 Set Vref, RX VrefLevel [Byte0]: 40
8627 01:19:11.054882 [Byte1]: 40
8628 01:19:11.058722
8629 01:19:11.059190 Set Vref, RX VrefLevel [Byte0]: 41
8630 01:19:11.062710 [Byte1]: 41
8631 01:19:11.066542
8632 01:19:11.067029 Set Vref, RX VrefLevel [Byte0]: 42
8633 01:19:11.069564 [Byte1]: 42
8634 01:19:11.074228
8635 01:19:11.074795 Set Vref, RX VrefLevel [Byte0]: 43
8636 01:19:11.077289 [Byte1]: 43
8637 01:19:11.082117
8638 01:19:11.082679 Set Vref, RX VrefLevel [Byte0]: 44
8639 01:19:11.085163 [Byte1]: 44
8640 01:19:11.089894
8641 01:19:11.090466 Set Vref, RX VrefLevel [Byte0]: 45
8642 01:19:11.092851 [Byte1]: 45
8643 01:19:11.097057
8644 01:19:11.097672 Set Vref, RX VrefLevel [Byte0]: 46
8645 01:19:11.100345 [Byte1]: 46
8646 01:19:11.104586
8647 01:19:11.105057 Set Vref, RX VrefLevel [Byte0]: 47
8648 01:19:11.107998 [Byte1]: 47
8649 01:19:11.112435
8650 01:19:11.113020 Set Vref, RX VrefLevel [Byte0]: 48
8651 01:19:11.115197 [Byte1]: 48
8652 01:19:11.119611
8653 01:19:11.120078 Set Vref, RX VrefLevel [Byte0]: 49
8654 01:19:11.123101 [Byte1]: 49
8655 01:19:11.127367
8656 01:19:11.127833 Set Vref, RX VrefLevel [Byte0]: 50
8657 01:19:11.130935 [Byte1]: 50
8658 01:19:11.135276
8659 01:19:11.135841 Set Vref, RX VrefLevel [Byte0]: 51
8660 01:19:11.138539 [Byte1]: 51
8661 01:19:11.142618
8662 01:19:11.143186 Set Vref, RX VrefLevel [Byte0]: 52
8663 01:19:11.146009 [Byte1]: 52
8664 01:19:11.150448
8665 01:19:11.151015 Set Vref, RX VrefLevel [Byte0]: 53
8666 01:19:11.153828 [Byte1]: 53
8667 01:19:11.158247
8668 01:19:11.158812 Set Vref, RX VrefLevel [Byte0]: 54
8669 01:19:11.161563 [Byte1]: 54
8670 01:19:11.165766
8671 01:19:11.166240 Set Vref, RX VrefLevel [Byte0]: 55
8672 01:19:11.168968 [Byte1]: 55
8673 01:19:11.173005
8674 01:19:11.173630 Set Vref, RX VrefLevel [Byte0]: 56
8675 01:19:11.176214 [Byte1]: 56
8676 01:19:11.180820
8677 01:19:11.181288 Set Vref, RX VrefLevel [Byte0]: 57
8678 01:19:11.184042 [Byte1]: 57
8679 01:19:11.188850
8680 01:19:11.189426 Set Vref, RX VrefLevel [Byte0]: 58
8681 01:19:11.192036 [Byte1]: 58
8682 01:19:11.196506
8683 01:19:11.197072 Set Vref, RX VrefLevel [Byte0]: 59
8684 01:19:11.199161 [Byte1]: 59
8685 01:19:11.203652
8686 01:19:11.204118 Set Vref, RX VrefLevel [Byte0]: 60
8687 01:19:11.206859 [Byte1]: 60
8688 01:19:11.211506
8689 01:19:11.212079 Set Vref, RX VrefLevel [Byte0]: 61
8690 01:19:11.214705 [Byte1]: 61
8691 01:19:11.218881
8692 01:19:11.219350 Set Vref, RX VrefLevel [Byte0]: 62
8693 01:19:11.222043 [Byte1]: 62
8694 01:19:11.226435
8695 01:19:11.227001 Set Vref, RX VrefLevel [Byte0]: 63
8696 01:19:11.229954 [Byte1]: 63
8697 01:19:11.233928
8698 01:19:11.234395 Set Vref, RX VrefLevel [Byte0]: 64
8699 01:19:11.237306 [Byte1]: 64
8700 01:19:11.241902
8701 01:19:11.242464 Set Vref, RX VrefLevel [Byte0]: 65
8702 01:19:11.245226 [Byte1]: 65
8703 01:19:11.249235
8704 01:19:11.249732 Set Vref, RX VrefLevel [Byte0]: 66
8705 01:19:11.252510 [Byte1]: 66
8706 01:19:11.257212
8707 01:19:11.257840 Set Vref, RX VrefLevel [Byte0]: 67
8708 01:19:11.260208 [Byte1]: 67
8709 01:19:11.264852
8710 01:19:11.265416 Set Vref, RX VrefLevel [Byte0]: 68
8711 01:19:11.268000 [Byte1]: 68
8712 01:19:11.272128
8713 01:19:11.272708 Set Vref, RX VrefLevel [Byte0]: 69
8714 01:19:11.275404 [Byte1]: 69
8715 01:19:11.280072
8716 01:19:11.280636 Set Vref, RX VrefLevel [Byte0]: 70
8717 01:19:11.283410 [Byte1]: 70
8718 01:19:11.287754
8719 01:19:11.288353 Final RX Vref Byte 0 = 56 to rank0
8720 01:19:11.290822 Final RX Vref Byte 1 = 52 to rank0
8721 01:19:11.294158 Final RX Vref Byte 0 = 56 to rank1
8722 01:19:11.297302 Final RX Vref Byte 1 = 52 to rank1==
8723 01:19:11.300513 Dram Type= 6, Freq= 0, CH_1, rank 0
8724 01:19:11.307156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8725 01:19:11.307633 ==
8726 01:19:11.308108 DQS Delay:
8727 01:19:11.308553 DQS0 = 0, DQS1 = 0
8728 01:19:11.310567 DQM Delay:
8729 01:19:11.311035 DQM0 = 131, DQM1 = 123
8730 01:19:11.314083 DQ Delay:
8731 01:19:11.317277 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =128
8732 01:19:11.320561 DQ4 =126, DQ5 =142, DQ6 =140, DQ7 =128
8733 01:19:11.324092 DQ8 =108, DQ9 =112, DQ10 =124, DQ11 =116
8734 01:19:11.327632 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8735 01:19:11.328216
8736 01:19:11.328698
8737 01:19:11.329139
8738 01:19:11.330591 [DramC_TX_OE_Calibration] TA2
8739 01:19:11.333553 Original DQ_B0 (3 6) =30, OEN = 27
8740 01:19:11.337544 Original DQ_B1 (3 6) =30, OEN = 27
8741 01:19:11.340467 24, 0x0, End_B0=24 End_B1=24
8742 01:19:11.340945 25, 0x0, End_B0=25 End_B1=25
8743 01:19:11.344278 26, 0x0, End_B0=26 End_B1=26
8744 01:19:11.347178 27, 0x0, End_B0=27 End_B1=27
8745 01:19:11.350328 28, 0x0, End_B0=28 End_B1=28
8746 01:19:11.353353 29, 0x0, End_B0=29 End_B1=29
8747 01:19:11.353975 30, 0x0, End_B0=30 End_B1=30
8748 01:19:11.356626 31, 0x4141, End_B0=30 End_B1=30
8749 01:19:11.360165 Byte0 end_step=30 best_step=27
8750 01:19:11.363770 Byte1 end_step=30 best_step=27
8751 01:19:11.366938 Byte0 TX OE(2T, 0.5T) = (3, 3)
8752 01:19:11.369878 Byte1 TX OE(2T, 0.5T) = (3, 3)
8753 01:19:11.370344
8754 01:19:11.370814
8755 01:19:11.376666 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8756 01:19:11.380372 CH1 RK0: MR19=303, MR18=80D
8757 01:19:11.386828 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8758 01:19:11.387300
8759 01:19:11.390172 ----->DramcWriteLeveling(PI) begin...
8760 01:19:11.390647 ==
8761 01:19:11.393295 Dram Type= 6, Freq= 0, CH_1, rank 1
8762 01:19:11.396739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 01:19:11.397327 ==
8764 01:19:11.399803 Write leveling (Byte 0): 26 => 26
8765 01:19:11.403479 Write leveling (Byte 1): 26 => 26
8766 01:19:11.406889 DramcWriteLeveling(PI) end<-----
8767 01:19:11.407454
8768 01:19:11.407933 ==
8769 01:19:11.409748 Dram Type= 6, Freq= 0, CH_1, rank 1
8770 01:19:11.413163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 01:19:11.413791 ==
8772 01:19:11.416227 [Gating] SW mode calibration
8773 01:19:11.422943 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8774 01:19:11.429505 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8775 01:19:11.432490 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 01:19:11.439579 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 01:19:11.442924 1 4 8 | B1->B0 | 2323 3130 | 0 1 | (0 0) (1 1)
8778 01:19:11.445703 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8779 01:19:11.452983 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 01:19:11.455921 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 01:19:11.459397 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 01:19:11.465932 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 01:19:11.469277 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 01:19:11.472337 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 01:19:11.479298 1 5 8 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8786 01:19:11.482761 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
8787 01:19:11.485442 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 01:19:11.492298 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 01:19:11.495937 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 01:19:11.499112 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 01:19:11.505498 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 01:19:11.508707 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8793 01:19:11.512188 1 6 8 | B1->B0 | 2727 4141 | 0 1 | (0 0) (0 0)
8794 01:19:11.518648 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8795 01:19:11.522138 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 01:19:11.525293 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 01:19:11.528835 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 01:19:11.535726 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 01:19:11.538922 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 01:19:11.542132 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 01:19:11.548411 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8802 01:19:11.551708 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8803 01:19:11.555015 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8804 01:19:11.562085 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 01:19:11.565166 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 01:19:11.568311 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 01:19:11.575036 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 01:19:11.578279 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 01:19:11.581542 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 01:19:11.588456 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 01:19:11.591662 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 01:19:11.595075 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 01:19:11.601546 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 01:19:11.604845 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 01:19:11.607802 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 01:19:11.614567 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8817 01:19:11.617692 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8818 01:19:11.621354 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8819 01:19:11.624159 Total UI for P1: 0, mck2ui 16
8820 01:19:11.627509 best dqsien dly found for B1: ( 1, 9, 10)
8821 01:19:11.634254 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 01:19:11.637611 Total UI for P1: 0, mck2ui 16
8823 01:19:11.641083 best dqsien dly found for B0: ( 1, 9, 8)
8824 01:19:11.644494 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8825 01:19:11.647156 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8826 01:19:11.647610
8827 01:19:11.651001 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8828 01:19:11.654284 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8829 01:19:11.657235 [Gating] SW calibration Done
8830 01:19:11.657844 ==
8831 01:19:11.660813 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 01:19:11.664043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 01:19:11.664639 ==
8834 01:19:11.667055 RX Vref Scan: 0
8835 01:19:11.667512
8836 01:19:11.670468 RX Vref 0 -> 0, step: 1
8837 01:19:11.670923
8838 01:19:11.671283 RX Delay 0 -> 252, step: 8
8839 01:19:11.677122 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8840 01:19:11.680680 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8841 01:19:11.684001 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8842 01:19:11.686973 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8843 01:19:11.690245 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8844 01:19:11.697034 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8845 01:19:11.700758 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8846 01:19:11.704252 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8847 01:19:11.706880 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8848 01:19:11.710138 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8849 01:19:11.716524 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8850 01:19:11.720345 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8851 01:19:11.723603 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8852 01:19:11.726795 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8853 01:19:11.729912 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8854 01:19:11.736808 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8855 01:19:11.737282 ==
8856 01:19:11.739941 Dram Type= 6, Freq= 0, CH_1, rank 1
8857 01:19:11.743195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8858 01:19:11.743668 ==
8859 01:19:11.744140 DQS Delay:
8860 01:19:11.746747 DQS0 = 0, DQS1 = 0
8861 01:19:11.747200 DQM Delay:
8862 01:19:11.749707 DQM0 = 129, DQM1 = 128
8863 01:19:11.750163 DQ Delay:
8864 01:19:11.753255 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =127
8865 01:19:11.756740 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =127
8866 01:19:11.760031 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8867 01:19:11.763509 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8868 01:19:11.766688
8869 01:19:11.767144
8870 01:19:11.767504 ==
8871 01:19:11.769732 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 01:19:11.773195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 01:19:11.773801 ==
8874 01:19:11.774173
8875 01:19:11.774509
8876 01:19:11.776267 TX Vref Scan disable
8877 01:19:11.776860 == TX Byte 0 ==
8878 01:19:11.783275 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8879 01:19:11.786358 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8880 01:19:11.786964 == TX Byte 1 ==
8881 01:19:11.793420 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8882 01:19:11.796623 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8883 01:19:11.797083 ==
8884 01:19:11.799848 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 01:19:11.802584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 01:19:11.803041 ==
8887 01:19:11.816665
8888 01:19:11.819962 TX Vref early break, caculate TX vref
8889 01:19:11.823291 TX Vref=16, minBit 0, minWin=23, winSum=385
8890 01:19:11.826308 TX Vref=18, minBit 0, minWin=23, winSum=400
8891 01:19:11.829475 TX Vref=20, minBit 0, minWin=24, winSum=405
8892 01:19:11.833293 TX Vref=22, minBit 0, minWin=23, winSum=407
8893 01:19:11.836445 TX Vref=24, minBit 0, minWin=25, winSum=418
8894 01:19:11.843156 TX Vref=26, minBit 0, minWin=25, winSum=428
8895 01:19:11.846097 TX Vref=28, minBit 6, minWin=25, winSum=429
8896 01:19:11.849504 TX Vref=30, minBit 0, minWin=24, winSum=425
8897 01:19:11.852657 TX Vref=32, minBit 1, minWin=25, winSum=417
8898 01:19:11.856228 TX Vref=34, minBit 5, minWin=23, winSum=404
8899 01:19:11.862835 [TxChooseVref] Worse bit 6, Min win 25, Win sum 429, Final Vref 28
8900 01:19:11.863296
8901 01:19:11.866095 Final TX Range 0 Vref 28
8902 01:19:11.866566
8903 01:19:11.866971 ==
8904 01:19:11.869482 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 01:19:11.872400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 01:19:11.872873 ==
8907 01:19:11.873444
8908 01:19:11.873931
8909 01:19:11.875738 TX Vref Scan disable
8910 01:19:11.882159 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8911 01:19:11.882630 == TX Byte 0 ==
8912 01:19:11.885867 u2DelayCellOfst[0]=18 cells (5 PI)
8913 01:19:11.888734 u2DelayCellOfst[1]=15 cells (4 PI)
8914 01:19:11.892170 u2DelayCellOfst[2]=0 cells (0 PI)
8915 01:19:11.895726 u2DelayCellOfst[3]=7 cells (2 PI)
8916 01:19:11.899047 u2DelayCellOfst[4]=11 cells (3 PI)
8917 01:19:11.902471 u2DelayCellOfst[5]=22 cells (6 PI)
8918 01:19:11.905289 u2DelayCellOfst[6]=18 cells (5 PI)
8919 01:19:11.908730 u2DelayCellOfst[7]=7 cells (2 PI)
8920 01:19:11.912204 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8921 01:19:11.915417 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8922 01:19:11.918668 == TX Byte 1 ==
8923 01:19:11.921778 u2DelayCellOfst[8]=0 cells (0 PI)
8924 01:19:11.922232 u2DelayCellOfst[9]=7 cells (2 PI)
8925 01:19:11.925348 u2DelayCellOfst[10]=15 cells (4 PI)
8926 01:19:11.928568 u2DelayCellOfst[11]=7 cells (2 PI)
8927 01:19:11.931969 u2DelayCellOfst[12]=15 cells (4 PI)
8928 01:19:11.935224 u2DelayCellOfst[13]=18 cells (5 PI)
8929 01:19:11.938548 u2DelayCellOfst[14]=18 cells (5 PI)
8930 01:19:11.941600 u2DelayCellOfst[15]=22 cells (6 PI)
8931 01:19:11.948856 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8932 01:19:11.952001 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8933 01:19:11.952454 DramC Write-DBI on
8934 01:19:11.952867 ==
8935 01:19:11.955389 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 01:19:11.961414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 01:19:11.961903 ==
8938 01:19:11.962261
8939 01:19:11.962590
8940 01:19:11.962904 TX Vref Scan disable
8941 01:19:11.965602 == TX Byte 0 ==
8942 01:19:11.969617 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8943 01:19:11.972883 == TX Byte 1 ==
8944 01:19:11.976237 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8945 01:19:11.978879 DramC Write-DBI off
8946 01:19:11.979351
8947 01:19:11.979821 [DATLAT]
8948 01:19:11.980267 Freq=1600, CH1 RK1
8949 01:19:11.980708
8950 01:19:11.982585 DATLAT Default: 0xf
8951 01:19:11.983053 0, 0xFFFF, sum = 0
8952 01:19:11.985993 1, 0xFFFF, sum = 0
8953 01:19:11.986452 2, 0xFFFF, sum = 0
8954 01:19:11.989216 3, 0xFFFF, sum = 0
8955 01:19:11.992176 4, 0xFFFF, sum = 0
8956 01:19:11.992640 5, 0xFFFF, sum = 0
8957 01:19:11.995608 6, 0xFFFF, sum = 0
8958 01:19:11.996069 7, 0xFFFF, sum = 0
8959 01:19:11.999237 8, 0xFFFF, sum = 0
8960 01:19:11.999799 9, 0xFFFF, sum = 0
8961 01:19:12.002153 10, 0xFFFF, sum = 0
8962 01:19:12.002634 11, 0xFFFF, sum = 0
8963 01:19:12.005663 12, 0xFFFF, sum = 0
8964 01:19:12.006155 13, 0x8FFF, sum = 0
8965 01:19:12.008862 14, 0x0, sum = 1
8966 01:19:12.009339 15, 0x0, sum = 2
8967 01:19:12.012009 16, 0x0, sum = 3
8968 01:19:12.012482 17, 0x0, sum = 4
8969 01:19:12.015481 best_step = 15
8970 01:19:12.015945
8971 01:19:12.016415 ==
8972 01:19:12.019116 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 01:19:12.022290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 01:19:12.022762 ==
8975 01:19:12.025569 RX Vref Scan: 0
8976 01:19:12.026063
8977 01:19:12.026436 RX Vref 0 -> 0, step: 1
8978 01:19:12.026778
8979 01:19:12.028723 RX Delay 3 -> 252, step: 4
8980 01:19:12.032188 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8981 01:19:12.038908 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8982 01:19:12.042122 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8983 01:19:12.045056 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8984 01:19:12.048598 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8985 01:19:12.051681 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8986 01:19:12.058513 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8987 01:19:12.061889 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
8988 01:19:12.065208 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8989 01:19:12.068493 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8990 01:19:12.071767 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8991 01:19:12.078411 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8992 01:19:12.081823 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8993 01:19:12.085194 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8994 01:19:12.088419 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8995 01:19:12.095242 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8996 01:19:12.095793 ==
8997 01:19:12.098513 Dram Type= 6, Freq= 0, CH_1, rank 1
8998 01:19:12.101697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8999 01:19:12.102251 ==
9000 01:19:12.102672 DQS Delay:
9001 01:19:12.105123 DQS0 = 0, DQS1 = 0
9002 01:19:12.105637 DQM Delay:
9003 01:19:12.108225 DQM0 = 127, DQM1 = 125
9004 01:19:12.108735 DQ Delay:
9005 01:19:12.111207 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =126
9006 01:19:12.114889 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =122
9007 01:19:12.118267 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
9008 01:19:12.121860 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =134
9009 01:19:12.122414
9010 01:19:12.122773
9011 01:19:12.125041
9012 01:19:12.125493 [DramC_TX_OE_Calibration] TA2
9013 01:19:12.128144 Original DQ_B0 (3 6) =30, OEN = 27
9014 01:19:12.131169 Original DQ_B1 (3 6) =30, OEN = 27
9015 01:19:12.135227 24, 0x0, End_B0=24 End_B1=24
9016 01:19:12.138181 25, 0x0, End_B0=25 End_B1=25
9017 01:19:12.138648 26, 0x0, End_B0=26 End_B1=26
9018 01:19:12.141356 27, 0x0, End_B0=27 End_B1=27
9019 01:19:12.145175 28, 0x0, End_B0=28 End_B1=28
9020 01:19:12.148623 29, 0x0, End_B0=29 End_B1=29
9021 01:19:12.151407 30, 0x0, End_B0=30 End_B1=30
9022 01:19:12.151871 31, 0x4545, End_B0=30 End_B1=30
9023 01:19:12.154595 Byte0 end_step=30 best_step=27
9024 01:19:12.158036 Byte1 end_step=30 best_step=27
9025 01:19:12.161321 Byte0 TX OE(2T, 0.5T) = (3, 3)
9026 01:19:12.164389 Byte1 TX OE(2T, 0.5T) = (3, 3)
9027 01:19:12.164873
9028 01:19:12.165251
9029 01:19:12.171100 [DQSOSCAuto] RK1, (LSB)MR18= 0x101c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9030 01:19:12.174623 CH1 RK1: MR19=303, MR18=101C
9031 01:19:12.181578 CH1_RK1: MR19=0x303, MR18=0x101C, DQSOSC=395, MR23=63, INC=23, DEC=15
9032 01:19:12.184786 [RxdqsGatingPostProcess] freq 1600
9033 01:19:12.191416 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9034 01:19:12.194819 best DQS0 dly(2T, 0.5T) = (1, 1)
9035 01:19:12.195379 best DQS1 dly(2T, 0.5T) = (1, 1)
9036 01:19:12.198188 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9037 01:19:12.201009 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9038 01:19:12.204556 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 01:19:12.207770 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 01:19:12.211089 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 01:19:12.214067 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 01:19:12.217779 Pre-setting of DQS Precalculation
9043 01:19:12.220905 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9044 01:19:12.230822 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9045 01:19:12.237468 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9046 01:19:12.238094
9047 01:19:12.238452
9048 01:19:12.240272 [Calibration Summary] 3200 Mbps
9049 01:19:12.240727 CH 0, Rank 0
9050 01:19:12.244521 SW Impedance : PASS
9051 01:19:12.247407 DUTY Scan : NO K
9052 01:19:12.247888 ZQ Calibration : PASS
9053 01:19:12.250898 Jitter Meter : NO K
9054 01:19:12.251350 CBT Training : PASS
9055 01:19:12.254081 Write leveling : PASS
9056 01:19:12.257256 RX DQS gating : PASS
9057 01:19:12.257856 RX DQ/DQS(RDDQC) : PASS
9058 01:19:12.260704 TX DQ/DQS : PASS
9059 01:19:12.264148 RX DATLAT : PASS
9060 01:19:12.264602 RX DQ/DQS(Engine): PASS
9061 01:19:12.267205 TX OE : PASS
9062 01:19:12.267659 All Pass.
9063 01:19:12.268073
9064 01:19:12.270211 CH 0, Rank 1
9065 01:19:12.270662 SW Impedance : PASS
9066 01:19:12.274217 DUTY Scan : NO K
9067 01:19:12.276905 ZQ Calibration : PASS
9068 01:19:12.277359 Jitter Meter : NO K
9069 01:19:12.280360 CBT Training : PASS
9070 01:19:12.284008 Write leveling : PASS
9071 01:19:12.284567 RX DQS gating : PASS
9072 01:19:12.287326 RX DQ/DQS(RDDQC) : PASS
9073 01:19:12.290466 TX DQ/DQS : PASS
9074 01:19:12.291025 RX DATLAT : PASS
9075 01:19:12.293364 RX DQ/DQS(Engine): PASS
9076 01:19:12.296478 TX OE : PASS
9077 01:19:12.296936 All Pass.
9078 01:19:12.297312
9079 01:19:12.297738 CH 1, Rank 0
9080 01:19:12.300055 SW Impedance : PASS
9081 01:19:12.303411 DUTY Scan : NO K
9082 01:19:12.303867 ZQ Calibration : PASS
9083 01:19:12.306659 Jitter Meter : NO K
9084 01:19:12.310002 CBT Training : PASS
9085 01:19:12.310464 Write leveling : PASS
9086 01:19:12.313484 RX DQS gating : PASS
9087 01:19:12.316751 RX DQ/DQS(RDDQC) : PASS
9088 01:19:12.317311 TX DQ/DQS : PASS
9089 01:19:12.320239 RX DATLAT : PASS
9090 01:19:12.320929 RX DQ/DQS(Engine): PASS
9091 01:19:12.323278 TX OE : PASS
9092 01:19:12.323739 All Pass.
9093 01:19:12.324101
9094 01:19:12.326362 CH 1, Rank 1
9095 01:19:12.326821 SW Impedance : PASS
9096 01:19:12.329600 DUTY Scan : NO K
9097 01:19:12.333325 ZQ Calibration : PASS
9098 01:19:12.333951 Jitter Meter : NO K
9099 01:19:12.336591 CBT Training : PASS
9100 01:19:12.340091 Write leveling : PASS
9101 01:19:12.340738 RX DQS gating : PASS
9102 01:19:12.343202 RX DQ/DQS(RDDQC) : PASS
9103 01:19:12.345999 TX DQ/DQS : PASS
9104 01:19:12.346457 RX DATLAT : PASS
9105 01:19:12.349621 RX DQ/DQS(Engine): PASS
9106 01:19:12.353209 TX OE : PASS
9107 01:19:12.353807 All Pass.
9108 01:19:12.354169
9109 01:19:12.356593 DramC Write-DBI on
9110 01:19:12.357322 PER_BANK_REFRESH: Hybrid Mode
9111 01:19:12.359440 TX_TRACKING: ON
9112 01:19:12.369100 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9113 01:19:12.375938 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9114 01:19:12.382488 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9115 01:19:12.386211 [FAST_K] Save calibration result to emmc
9116 01:19:12.389320 sync common calibartion params.
9117 01:19:12.392686 sync cbt_mode0:1, 1:1
9118 01:19:12.393230 dram_init: ddr_geometry: 2
9119 01:19:12.396263 dram_init: ddr_geometry: 2
9120 01:19:12.399110 dram_init: ddr_geometry: 2
9121 01:19:12.402608 0:dram_rank_size:100000000
9122 01:19:12.403158 1:dram_rank_size:100000000
9123 01:19:12.409035 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9124 01:19:12.412681 DFS_SHUFFLE_HW_MODE: ON
9125 01:19:12.416167 dramc_set_vcore_voltage set vcore to 725000
9126 01:19:12.418555 Read voltage for 1600, 0
9127 01:19:12.419014 Vio18 = 0
9128 01:19:12.419372 Vcore = 725000
9129 01:19:12.422500 Vdram = 0
9130 01:19:12.423063 Vddq = 0
9131 01:19:12.423431 Vmddr = 0
9132 01:19:12.425430 switch to 3200 Mbps bootup
9133 01:19:12.425933 [DramcRunTimeConfig]
9134 01:19:12.428544 PHYPLL
9135 01:19:12.429001 DPM_CONTROL_AFTERK: ON
9136 01:19:12.432152 PER_BANK_REFRESH: ON
9137 01:19:12.435583 REFRESH_OVERHEAD_REDUCTION: ON
9138 01:19:12.436041 CMD_PICG_NEW_MODE: OFF
9139 01:19:12.438678 XRTWTW_NEW_MODE: ON
9140 01:19:12.439133 XRTRTR_NEW_MODE: ON
9141 01:19:12.442098 TX_TRACKING: ON
9142 01:19:12.442557 RDSEL_TRACKING: OFF
9143 01:19:12.445404 DQS Precalculation for DVFS: ON
9144 01:19:12.449133 RX_TRACKING: OFF
9145 01:19:12.449746 HW_GATING DBG: ON
9146 01:19:12.452391 ZQCS_ENABLE_LP4: ON
9147 01:19:12.452844 RX_PICG_NEW_MODE: ON
9148 01:19:12.455051 TX_PICG_NEW_MODE: ON
9149 01:19:12.455509 ENABLE_RX_DCM_DPHY: ON
9150 01:19:12.458370 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9151 01:19:12.461924 DUMMY_READ_FOR_TRACKING: OFF
9152 01:19:12.465464 !!! SPM_CONTROL_AFTERK: OFF
9153 01:19:12.469076 !!! SPM could not control APHY
9154 01:19:12.469777 IMPEDANCE_TRACKING: ON
9155 01:19:12.472150 TEMP_SENSOR: ON
9156 01:19:12.472717 HW_SAVE_FOR_SR: OFF
9157 01:19:12.475632 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9158 01:19:12.478535 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9159 01:19:12.481677 Read ODT Tracking: ON
9160 01:19:12.485433 Refresh Rate DeBounce: ON
9161 01:19:12.485922 DFS_NO_QUEUE_FLUSH: ON
9162 01:19:12.488734 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9163 01:19:12.491995 ENABLE_DFS_RUNTIME_MRW: OFF
9164 01:19:12.495601 DDR_RESERVE_NEW_MODE: ON
9165 01:19:12.496149 MR_CBT_SWITCH_FREQ: ON
9166 01:19:12.498603 =========================
9167 01:19:12.517397 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9168 01:19:12.520647 dram_init: ddr_geometry: 2
9169 01:19:12.538728 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9170 01:19:12.542060 dram_init: dram init end (result: 0)
9171 01:19:12.548801 DRAM-K: Full calibration passed in 24587 msecs
9172 01:19:12.552594 MRC: failed to locate region type 0.
9173 01:19:12.553145 DRAM rank0 size:0x100000000,
9174 01:19:12.555409 DRAM rank1 size=0x100000000
9175 01:19:12.565568 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9176 01:19:12.571876 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9177 01:19:12.578560 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9178 01:19:12.588817 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9179 01:19:12.589369 DRAM rank0 size:0x100000000,
9180 01:19:12.591748 DRAM rank1 size=0x100000000
9181 01:19:12.592293 CBMEM:
9182 01:19:12.595186 IMD: root @ 0xfffff000 254 entries.
9183 01:19:12.597927 IMD: root @ 0xffffec00 62 entries.
9184 01:19:12.601950 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9185 01:19:12.608629 WARNING: RO_VPD is uninitialized or empty.
9186 01:19:12.611103 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9187 01:19:12.619006 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9188 01:19:12.631601 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9189 01:19:12.643456 BS: romstage times (exec / console): total (unknown) / 24049 ms
9190 01:19:12.644012
9191 01:19:12.644376
9192 01:19:12.653154 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9193 01:19:12.656319 ARM64: Exception handlers installed.
9194 01:19:12.659888 ARM64: Testing exception
9195 01:19:12.663436 ARM64: Done test exception
9196 01:19:12.663994 Enumerating buses...
9197 01:19:12.665983 Show all devs... Before device enumeration.
9198 01:19:12.669226 Root Device: enabled 1
9199 01:19:12.672807 CPU_CLUSTER: 0: enabled 1
9200 01:19:12.673370 CPU: 00: enabled 1
9201 01:19:12.676160 Compare with tree...
9202 01:19:12.676723 Root Device: enabled 1
9203 01:19:12.679181 CPU_CLUSTER: 0: enabled 1
9204 01:19:12.682538 CPU: 00: enabled 1
9205 01:19:12.682993 Root Device scanning...
9206 01:19:12.685784 scan_static_bus for Root Device
9207 01:19:12.689349 CPU_CLUSTER: 0 enabled
9208 01:19:12.692446 scan_static_bus for Root Device done
9209 01:19:12.695748 scan_bus: bus Root Device finished in 8 msecs
9210 01:19:12.696206 done
9211 01:19:12.702390 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9212 01:19:12.705886 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9213 01:19:12.712543 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9214 01:19:12.715734 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9215 01:19:12.719201 Allocating resources...
9216 01:19:12.722092 Reading resources...
9217 01:19:12.725838 Root Device read_resources bus 0 link: 0
9218 01:19:12.729076 DRAM rank0 size:0x100000000,
9219 01:19:12.729907 DRAM rank1 size=0x100000000
9220 01:19:12.732012 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9221 01:19:12.735666 CPU: 00 missing read_resources
9222 01:19:12.742022 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9223 01:19:12.745328 Root Device read_resources bus 0 link: 0 done
9224 01:19:12.745863 Done reading resources.
9225 01:19:12.752364 Show resources in subtree (Root Device)...After reading.
9226 01:19:12.755330 Root Device child on link 0 CPU_CLUSTER: 0
9227 01:19:12.758805 CPU_CLUSTER: 0 child on link 0 CPU: 00
9228 01:19:12.768818 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9229 01:19:12.769390 CPU: 00
9230 01:19:12.772077 Root Device assign_resources, bus 0 link: 0
9231 01:19:12.775793 CPU_CLUSTER: 0 missing set_resources
9232 01:19:12.782264 Root Device assign_resources, bus 0 link: 0 done
9233 01:19:12.782728 Done setting resources.
9234 01:19:12.788784 Show resources in subtree (Root Device)...After assigning values.
9235 01:19:12.792153 Root Device child on link 0 CPU_CLUSTER: 0
9236 01:19:12.795798 CPU_CLUSTER: 0 child on link 0 CPU: 00
9237 01:19:12.805239 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9238 01:19:12.805844 CPU: 00
9239 01:19:12.808458 Done allocating resources.
9240 01:19:12.815099 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9241 01:19:12.815582 Enabling resources...
9242 01:19:12.815945 done.
9243 01:19:12.821830 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9244 01:19:12.822290 Initializing devices...
9245 01:19:12.825244 Root Device init
9246 01:19:12.825844 init hardware done!
9247 01:19:12.828407 0x00000018: ctrlr->caps
9248 01:19:12.831471 52.000 MHz: ctrlr->f_max
9249 01:19:12.831943 0.400 MHz: ctrlr->f_min
9250 01:19:12.834751 0x40ff8080: ctrlr->voltages
9251 01:19:12.838031 sclk: 390625
9252 01:19:12.838488 Bus Width = 1
9253 01:19:12.838850 sclk: 390625
9254 01:19:12.841663 Bus Width = 1
9255 01:19:12.842121 Early init status = 3
9256 01:19:12.848167 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9257 01:19:12.851846 in-header: 03 fc 00 00 01 00 00 00
9258 01:19:12.854903 in-data: 00
9259 01:19:12.858269 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9260 01:19:12.863407 in-header: 03 fd 00 00 00 00 00 00
9261 01:19:12.867168 in-data:
9262 01:19:12.869931 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9263 01:19:12.874803 in-header: 03 fc 00 00 01 00 00 00
9264 01:19:12.877710 in-data: 00
9265 01:19:12.881338 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9266 01:19:12.886938 in-header: 03 fd 00 00 00 00 00 00
9267 01:19:12.890233 in-data:
9268 01:19:12.893411 [SSUSB] Setting up USB HOST controller...
9269 01:19:12.896873 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9270 01:19:12.899858 [SSUSB] phy power-on done.
9271 01:19:12.903345 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9272 01:19:12.909876 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9273 01:19:12.913039 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9274 01:19:12.919411 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9275 01:19:12.926253 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9276 01:19:12.932781 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9277 01:19:12.939664 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9278 01:19:12.945891 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9279 01:19:12.949327 SPM: binary array size = 0x9dc
9280 01:19:12.953180 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9281 01:19:12.959576 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9282 01:19:12.966271 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9283 01:19:12.972862 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9284 01:19:12.975577 configure_display: Starting display init
9285 01:19:13.009840 anx7625_power_on_init: Init interface.
9286 01:19:13.013333 anx7625_disable_pd_protocol: Disabled PD feature.
9287 01:19:13.016176 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9288 01:19:13.044359 anx7625_start_dp_work: Secure OCM version=00
9289 01:19:13.047389 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9290 01:19:13.062079 sp_tx_get_edid_block: EDID Block = 1
9291 01:19:13.164957 Extracted contents:
9292 01:19:13.168197 header: 00 ff ff ff ff ff ff 00
9293 01:19:13.171764 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9294 01:19:13.174682 version: 01 04
9295 01:19:13.178254 basic params: 95 1f 11 78 0a
9296 01:19:13.181480 chroma info: 76 90 94 55 54 90 27 21 50 54
9297 01:19:13.184475 established: 00 00 00
9298 01:19:13.191187 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9299 01:19:13.194529 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9300 01:19:13.201217 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9301 01:19:13.208290 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9302 01:19:13.214720 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9303 01:19:13.218001 extensions: 00
9304 01:19:13.218683 checksum: fb
9305 01:19:13.219200
9306 01:19:13.221274 Manufacturer: IVO Model 57d Serial Number 0
9307 01:19:13.224701 Made week 0 of 2020
9308 01:19:13.225255 EDID version: 1.4
9309 01:19:13.227964 Digital display
9310 01:19:13.230719 6 bits per primary color channel
9311 01:19:13.231184 DisplayPort interface
9312 01:19:13.234590 Maximum image size: 31 cm x 17 cm
9313 01:19:13.237416 Gamma: 220%
9314 01:19:13.237936 Check DPMS levels
9315 01:19:13.240679 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9316 01:19:13.247575 First detailed timing is preferred timing
9317 01:19:13.248331 Established timings supported:
9318 01:19:13.250644 Standard timings supported:
9319 01:19:13.253991 Detailed timings
9320 01:19:13.257204 Hex of detail: 383680a07038204018303c0035ae10000019
9321 01:19:13.263909 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9322 01:19:13.267011 0780 0798 07c8 0820 hborder 0
9323 01:19:13.270387 0438 043b 0447 0458 vborder 0
9324 01:19:13.273468 -hsync -vsync
9325 01:19:13.273637 Did detailed timing
9326 01:19:13.280483 Hex of detail: 000000000000000000000000000000000000
9327 01:19:13.283700 Manufacturer-specified data, tag 0
9328 01:19:13.287051 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9329 01:19:13.290626 ASCII string: InfoVision
9330 01:19:13.293454 Hex of detail: 000000fe00523134304e574635205248200a
9331 01:19:13.297103 ASCII string: R140NWF5 RH
9332 01:19:13.297365 Checksum
9333 01:19:13.300283 Checksum: 0xfb (valid)
9334 01:19:13.303345 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9335 01:19:13.306724 DSI data_rate: 832800000 bps
9336 01:19:13.313275 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9337 01:19:13.316772 anx7625_parse_edid: pixelclock(138800).
9338 01:19:13.320135 hactive(1920), hsync(48), hfp(24), hbp(88)
9339 01:19:13.323333 vactive(1080), vsync(12), vfp(3), vbp(17)
9340 01:19:13.326804 anx7625_dsi_config: config dsi.
9341 01:19:13.333101 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9342 01:19:13.347376 anx7625_dsi_config: success to config DSI
9343 01:19:13.349985 anx7625_dp_start: MIPI phy setup OK.
9344 01:19:13.353555 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9345 01:19:13.357037 mtk_ddp_mode_set invalid vrefresh 60
9346 01:19:13.360811 main_disp_path_setup
9347 01:19:13.361355 ovl_layer_smi_id_en
9348 01:19:13.363761 ovl_layer_smi_id_en
9349 01:19:13.364347 ccorr_config
9350 01:19:13.364702 aal_config
9351 01:19:13.366979 gamma_config
9352 01:19:13.367433 postmask_config
9353 01:19:13.370327 dither_config
9354 01:19:13.373417 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9355 01:19:13.380028 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9356 01:19:13.383679 Root Device init finished in 555 msecs
9357 01:19:13.386582 CPU_CLUSTER: 0 init
9358 01:19:13.393405 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9359 01:19:13.396668 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9360 01:19:13.399865 APU_MBOX 0x190000b0 = 0x10001
9361 01:19:13.403394 APU_MBOX 0x190001b0 = 0x10001
9362 01:19:13.406967 APU_MBOX 0x190005b0 = 0x10001
9363 01:19:13.409910 APU_MBOX 0x190006b0 = 0x10001
9364 01:19:13.412801 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9365 01:19:13.425740 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9366 01:19:13.438353 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9367 01:19:13.445021 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9368 01:19:13.456810 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9369 01:19:13.466278 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9370 01:19:13.469374 CPU_CLUSTER: 0 init finished in 81 msecs
9371 01:19:13.472518 Devices initialized
9372 01:19:13.475467 Show all devs... After init.
9373 01:19:13.475926 Root Device: enabled 1
9374 01:19:13.479509 CPU_CLUSTER: 0: enabled 1
9375 01:19:13.482541 CPU: 00: enabled 1
9376 01:19:13.486332 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9377 01:19:13.489151 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9378 01:19:13.491937 ELOG: NV offset 0x57f000 size 0x1000
9379 01:19:13.498850 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9380 01:19:13.505536 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9381 01:19:13.508864 ELOG: Event(17) added with size 13 at 2024-04-23 01:19:13 UTC
9382 01:19:13.515503 out: cmd=0x121: 03 db 21 01 00 00 00 00
9383 01:19:13.518536 in-header: 03 49 00 00 2c 00 00 00
9384 01:19:13.528360 in-data: 15 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9385 01:19:13.535332 ELOG: Event(A1) added with size 10 at 2024-04-23 01:19:13 UTC
9386 01:19:13.541967 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9387 01:19:13.548372 ELOG: Event(A0) added with size 9 at 2024-04-23 01:19:13 UTC
9388 01:19:13.551966 elog_add_boot_reason: Logged dev mode boot
9389 01:19:13.558200 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9390 01:19:13.558737 Finalize devices...
9391 01:19:13.561716 Devices finalized
9392 01:19:13.565127 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9393 01:19:13.568372 Writing coreboot table at 0xffe64000
9394 01:19:13.571872 0. 000000000010a000-0000000000113fff: RAMSTAGE
9395 01:19:13.575133 1. 0000000040000000-00000000400fffff: RAM
9396 01:19:13.581446 2. 0000000040100000-000000004032afff: RAMSTAGE
9397 01:19:13.585003 3. 000000004032b000-00000000545fffff: RAM
9398 01:19:13.588203 4. 0000000054600000-000000005465ffff: BL31
9399 01:19:13.591186 5. 0000000054660000-00000000ffe63fff: RAM
9400 01:19:13.598233 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9401 01:19:13.601708 7. 0000000100000000-000000023fffffff: RAM
9402 01:19:13.605217 Passing 5 GPIOs to payload:
9403 01:19:13.608306 NAME | PORT | POLARITY | VALUE
9404 01:19:13.614591 EC in RW | 0x000000aa | low | undefined
9405 01:19:13.618083 EC interrupt | 0x00000005 | low | undefined
9406 01:19:13.621121 TPM interrupt | 0x000000ab | high | undefined
9407 01:19:13.627788 SD card detect | 0x00000011 | high | undefined
9408 01:19:13.631128 speaker enable | 0x00000093 | high | undefined
9409 01:19:13.634574 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9410 01:19:13.637566 in-header: 03 f9 00 00 02 00 00 00
9411 01:19:13.640823 in-data: 02 00
9412 01:19:13.644077 ADC[4]: Raw value=896300 ID=7
9413 01:19:13.644538 ADC[3]: Raw value=213810 ID=1
9414 01:19:13.647604 RAM Code: 0x71
9415 01:19:13.650828 ADC[6]: Raw value=74722 ID=0
9416 01:19:13.651378 ADC[5]: Raw value=211960 ID=1
9417 01:19:13.654117 SKU Code: 0x1
9418 01:19:13.660957 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9a05
9419 01:19:13.661560 coreboot table: 964 bytes.
9420 01:19:13.664388 IMD ROOT 0. 0xfffff000 0x00001000
9421 01:19:13.667470 IMD SMALL 1. 0xffffe000 0x00001000
9422 01:19:13.671022 RO MCACHE 2. 0xffffc000 0x00001104
9423 01:19:13.674450 CONSOLE 3. 0xfff7c000 0x00080000
9424 01:19:13.677378 FMAP 4. 0xfff7b000 0x00000452
9425 01:19:13.680867 TIME STAMP 5. 0xfff7a000 0x00000910
9426 01:19:13.683698 VBOOT WORK 6. 0xfff66000 0x00014000
9427 01:19:13.687356 RAMOOPS 7. 0xffe66000 0x00100000
9428 01:19:13.690419 COREBOOT 8. 0xffe64000 0x00002000
9429 01:19:13.693911 IMD small region:
9430 01:19:13.696921 IMD ROOT 0. 0xffffec00 0x00000400
9431 01:19:13.700622 VPD 1. 0xffffeb80 0x0000006c
9432 01:19:13.703346 MMC STATUS 2. 0xffffeb60 0x00000004
9433 01:19:13.706691 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9434 01:19:13.710312 Probing TPM: done!
9435 01:19:13.714102 Connected to device vid:did:rid of 1ae0:0028:00
9436 01:19:13.724888 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9437 01:19:13.727880 Initialized TPM device CR50 revision 0
9438 01:19:13.731725 Checking cr50 for pending updates
9439 01:19:13.735415 Reading cr50 TPM mode
9440 01:19:13.744366 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9441 01:19:13.750654 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9442 01:19:13.790890 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9443 01:19:13.794448 Checking segment from ROM address 0x40100000
9444 01:19:13.797257 Checking segment from ROM address 0x4010001c
9445 01:19:13.804557 Loading segment from ROM address 0x40100000
9446 01:19:13.805164 code (compression=0)
9447 01:19:13.814107 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9448 01:19:13.820642 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9449 01:19:13.821102 it's not compressed!
9450 01:19:13.827577 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9451 01:19:13.830898 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9452 01:19:13.851836 Loading segment from ROM address 0x4010001c
9453 01:19:13.852395 Entry Point 0x80000000
9454 01:19:13.854408 Loaded segments
9455 01:19:13.857985 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9456 01:19:13.864968 Jumping to boot code at 0x80000000(0xffe64000)
9457 01:19:13.871317 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9458 01:19:13.878050 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9459 01:19:13.885494 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9460 01:19:13.889321 Checking segment from ROM address 0x40100000
9461 01:19:13.892659 Checking segment from ROM address 0x4010001c
9462 01:19:13.899508 Loading segment from ROM address 0x40100000
9463 01:19:13.900064 code (compression=1)
9464 01:19:13.905704 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9465 01:19:13.915828 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9466 01:19:13.916404 using LZMA
9467 01:19:13.924534 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9468 01:19:13.930765 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9469 01:19:13.934074 Loading segment from ROM address 0x4010001c
9470 01:19:13.934541 Entry Point 0x54601000
9471 01:19:13.937320 Loaded segments
9472 01:19:13.940720 NOTICE: MT8192 bl31_setup
9473 01:19:13.947790 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9474 01:19:13.951557 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9475 01:19:13.954351 WARNING: region 0:
9476 01:19:13.957568 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 01:19:13.958025 WARNING: region 1:
9478 01:19:13.964463 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9479 01:19:13.967596 WARNING: region 2:
9480 01:19:13.970873 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9481 01:19:13.974685 WARNING: region 3:
9482 01:19:13.977418 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9483 01:19:13.981116 WARNING: region 4:
9484 01:19:13.988001 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 01:19:13.988558 WARNING: region 5:
9486 01:19:13.991279 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 01:19:13.994370 WARNING: region 6:
9488 01:19:13.997676 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 01:19:14.001117 WARNING: region 7:
9490 01:19:14.004669 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 01:19:14.011380 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9492 01:19:14.014160 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9493 01:19:14.017665 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9494 01:19:14.024786 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9495 01:19:14.027541 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9496 01:19:14.031421 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9497 01:19:14.037416 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9498 01:19:14.041383 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9499 01:19:14.047776 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9500 01:19:14.051049 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9501 01:19:14.054544 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9502 01:19:14.061020 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9503 01:19:14.064572 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9504 01:19:14.067553 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9505 01:19:14.074338 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9506 01:19:14.077888 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9507 01:19:14.084159 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9508 01:19:14.087501 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9509 01:19:14.090965 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9510 01:19:14.097865 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9511 01:19:14.101079 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9512 01:19:14.104503 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9513 01:19:14.110934 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9514 01:19:14.114056 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9515 01:19:14.121342 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9516 01:19:14.124846 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9517 01:19:14.127698 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9518 01:19:14.134582 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9519 01:19:14.137957 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9520 01:19:14.144427 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9521 01:19:14.147760 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9522 01:19:14.151061 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9523 01:19:14.157162 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9524 01:19:14.160947 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9525 01:19:14.164064 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9526 01:19:14.167157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9527 01:19:14.173966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9528 01:19:14.177104 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9529 01:19:14.180366 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9530 01:19:14.183827 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9531 01:19:14.190734 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9532 01:19:14.194114 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9533 01:19:14.197401 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9534 01:19:14.200316 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9535 01:19:14.207043 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9536 01:19:14.210607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9537 01:19:14.213784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9538 01:19:14.220315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9539 01:19:14.223479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9540 01:19:14.226689 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9541 01:19:14.233832 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9542 01:19:14.236962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9543 01:19:14.243776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9544 01:19:14.246849 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9545 01:19:14.250070 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9546 01:19:14.256928 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9547 01:19:14.260452 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9548 01:19:14.267159 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9549 01:19:14.270286 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9550 01:19:14.277118 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9551 01:19:14.280074 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9552 01:19:14.286736 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9553 01:19:14.290451 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9554 01:19:14.293708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9555 01:19:14.300719 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9556 01:19:14.303761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9557 01:19:14.310580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9558 01:19:14.313817 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9559 01:19:14.320568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9560 01:19:14.324086 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9561 01:19:14.326840 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9562 01:19:14.333587 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9563 01:19:14.336899 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9564 01:19:14.343719 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9565 01:19:14.347315 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9566 01:19:14.353548 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9567 01:19:14.356985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9568 01:19:14.360402 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9569 01:19:14.367005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9570 01:19:14.369973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9571 01:19:14.376751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9572 01:19:14.380637 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9573 01:19:14.386701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9574 01:19:14.390407 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9575 01:19:14.397229 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9576 01:19:14.400292 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9577 01:19:14.403785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9578 01:19:14.410047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9579 01:19:14.413353 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9580 01:19:14.419906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9581 01:19:14.423575 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9582 01:19:14.430023 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9583 01:19:14.433214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9584 01:19:14.436546 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9585 01:19:14.443274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9586 01:19:14.446977 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9587 01:19:14.453553 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9588 01:19:14.456816 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9589 01:19:14.460202 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9590 01:19:14.463941 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9591 01:19:14.469960 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9592 01:19:14.473422 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9593 01:19:14.476643 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9594 01:19:14.483305 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9595 01:19:14.486747 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9596 01:19:14.490013 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9597 01:19:14.496874 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9598 01:19:14.500581 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9599 01:19:14.506506 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9600 01:19:14.509999 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9601 01:19:14.516770 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9602 01:19:14.520360 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9603 01:19:14.523377 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9604 01:19:14.530138 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9605 01:19:14.533306 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9606 01:19:14.536835 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9607 01:19:14.543813 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9608 01:19:14.547133 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9609 01:19:14.550277 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9610 01:19:14.556422 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9611 01:19:14.559935 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9612 01:19:14.563494 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9613 01:19:14.566924 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9614 01:19:14.573576 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9615 01:19:14.576927 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9616 01:19:14.580111 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9617 01:19:14.586667 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9618 01:19:14.589866 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9619 01:19:14.596945 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9620 01:19:14.600236 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9621 01:19:14.603647 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9622 01:19:14.609643 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9623 01:19:14.613274 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9624 01:19:14.620284 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9625 01:19:14.622942 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9626 01:19:14.626212 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9627 01:19:14.633091 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9628 01:19:14.636404 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9629 01:19:14.639882 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9630 01:19:14.646544 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9631 01:19:14.649937 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9632 01:19:14.656565 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9633 01:19:14.659635 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9634 01:19:14.663119 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9635 01:19:14.669835 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9636 01:19:14.672841 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9637 01:19:14.680145 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9638 01:19:14.682883 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9639 01:19:14.686861 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9640 01:19:14.693261 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9641 01:19:14.696548 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9642 01:19:14.699470 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9643 01:19:14.706332 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9644 01:19:14.710284 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9645 01:19:14.716144 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9646 01:19:14.719928 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9647 01:19:14.722925 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9648 01:19:14.729959 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9649 01:19:14.732591 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9650 01:19:14.740055 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9651 01:19:14.742914 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9652 01:19:14.746142 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9653 01:19:14.752739 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9654 01:19:14.756136 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9655 01:19:14.762973 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9656 01:19:14.765903 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9657 01:19:14.769850 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9658 01:19:14.776384 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9659 01:19:14.779364 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9660 01:19:14.782541 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9661 01:19:14.789152 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9662 01:19:14.792536 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9663 01:19:14.799244 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9664 01:19:14.802822 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9665 01:19:14.805993 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9666 01:19:14.812576 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9667 01:19:14.815815 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9668 01:19:14.822629 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9669 01:19:14.825875 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9670 01:19:14.829193 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9671 01:19:14.835883 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9672 01:19:14.839507 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9673 01:19:14.846438 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9674 01:19:14.848945 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9675 01:19:14.853051 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9676 01:19:14.859081 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9677 01:19:14.862455 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9678 01:19:14.869604 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9679 01:19:14.872539 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9680 01:19:14.875336 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9681 01:19:14.881951 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9682 01:19:14.885617 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9683 01:19:14.891818 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9684 01:19:14.895473 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9685 01:19:14.902058 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9686 01:19:14.905431 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9687 01:19:14.908184 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9688 01:19:14.915249 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9689 01:19:14.918577 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9690 01:19:14.925012 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9691 01:19:14.928252 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9692 01:19:14.935025 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9693 01:19:14.938460 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9694 01:19:14.941731 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9695 01:19:14.948375 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9696 01:19:14.951921 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9697 01:19:14.958118 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9698 01:19:14.961604 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9699 01:19:14.968792 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9700 01:19:14.971062 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9701 01:19:14.974328 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9702 01:19:14.981099 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9703 01:19:14.984437 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9704 01:19:14.991272 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9705 01:19:14.994285 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9706 01:19:14.998049 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9707 01:19:15.004134 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9708 01:19:15.007655 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9709 01:19:15.014264 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9710 01:19:15.017232 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9711 01:19:15.023960 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9712 01:19:15.027180 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9713 01:19:15.030690 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9714 01:19:15.037268 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9715 01:19:15.040570 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9716 01:19:15.047282 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9717 01:19:15.050454 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9718 01:19:15.057294 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9719 01:19:15.060230 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9720 01:19:15.063446 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9721 01:19:15.067213 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9722 01:19:15.073177 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9723 01:19:15.077126 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9724 01:19:15.080876 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9725 01:19:15.086479 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9726 01:19:15.090009 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9727 01:19:15.093067 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9728 01:19:15.099917 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9729 01:19:15.103075 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9730 01:19:15.106312 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9731 01:19:15.113095 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9732 01:19:15.116029 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9733 01:19:15.122966 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9734 01:19:15.126206 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9735 01:19:15.129610 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9736 01:19:15.136217 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9737 01:19:15.139428 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9738 01:19:15.145827 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9739 01:19:15.149404 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9740 01:19:15.152864 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9741 01:19:15.159135 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9742 01:19:15.162745 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9743 01:19:15.166075 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9744 01:19:15.172525 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9745 01:19:15.175958 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9746 01:19:15.179382 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9747 01:19:15.185808 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9748 01:19:15.189387 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9749 01:19:15.192170 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9750 01:19:15.199226 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9751 01:19:15.202621 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9752 01:19:15.208786 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9753 01:19:15.212418 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9754 01:19:15.215497 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9755 01:19:15.222168 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9756 01:19:15.225160 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9757 01:19:15.232091 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9758 01:19:15.235484 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9759 01:19:15.238665 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9760 01:19:15.241822 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9761 01:19:15.248657 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9762 01:19:15.251978 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9763 01:19:15.255466 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9764 01:19:15.258441 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9765 01:19:15.265080 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9766 01:19:15.268835 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9767 01:19:15.271571 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9768 01:19:15.274900 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9769 01:19:15.282019 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9770 01:19:15.285216 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9771 01:19:15.288858 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9772 01:19:15.291818 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9773 01:19:15.298523 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9774 01:19:15.301897 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9775 01:19:15.308850 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9776 01:19:15.311654 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9777 01:19:15.318724 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9778 01:19:15.321709 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9779 01:19:15.324637 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9780 01:19:15.331535 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9781 01:19:15.334511 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9782 01:19:15.341286 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9783 01:19:15.344463 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9784 01:19:15.347640 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9785 01:19:15.355109 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9786 01:19:15.357899 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9787 01:19:15.364596 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9788 01:19:15.367925 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9789 01:19:15.371389 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9790 01:19:15.377772 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9791 01:19:15.381003 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9792 01:19:15.387785 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9793 01:19:15.391020 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9794 01:19:15.398117 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9795 01:19:15.401147 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9796 01:19:15.404514 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9797 01:19:15.410636 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9798 01:19:15.413923 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9799 01:19:15.420563 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9800 01:19:15.424023 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9801 01:19:15.427730 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9802 01:19:15.434093 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9803 01:19:15.437079 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9804 01:19:15.444064 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9805 01:19:15.447163 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9806 01:19:15.450346 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9807 01:19:15.456739 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9808 01:19:15.460012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9809 01:19:15.466535 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9810 01:19:15.469630 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9811 01:19:15.476397 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9812 01:19:15.479931 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9813 01:19:15.482742 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9814 01:19:15.489884 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9815 01:19:15.492896 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9816 01:19:15.499564 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9817 01:19:15.502912 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9818 01:19:15.509657 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9819 01:19:15.512569 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9820 01:19:15.516374 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9821 01:19:15.522644 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9822 01:19:15.526251 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9823 01:19:15.532519 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9824 01:19:15.535860 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9825 01:19:15.539177 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9826 01:19:15.546299 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9827 01:19:15.549465 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9828 01:19:15.555501 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9829 01:19:15.558947 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9830 01:19:15.562058 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9831 01:19:15.568559 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9832 01:19:15.572126 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9833 01:19:15.578984 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9834 01:19:15.581981 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9835 01:19:15.588569 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9836 01:19:15.591879 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9837 01:19:15.595071 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9838 01:19:15.601777 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9839 01:19:15.605206 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9840 01:19:15.611512 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9841 01:19:15.614732 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9842 01:19:15.621609 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9843 01:19:15.624818 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9844 01:19:15.628038 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9845 01:19:15.634896 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9846 01:19:15.638372 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9847 01:19:15.645053 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9848 01:19:15.648047 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9849 01:19:15.654781 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9850 01:19:15.657853 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9851 01:19:15.664675 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9852 01:19:15.667974 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9853 01:19:15.670816 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9854 01:19:15.677430 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9855 01:19:15.681180 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9856 01:19:15.687258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9857 01:19:15.691090 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9858 01:19:15.697498 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9859 01:19:15.700623 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9860 01:19:15.704299 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9861 01:19:15.710535 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9862 01:19:15.713847 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9863 01:19:15.720349 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9864 01:19:15.723819 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9865 01:19:15.730547 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9866 01:19:15.733853 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9867 01:19:15.740529 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9868 01:19:15.743713 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9869 01:19:15.746891 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9870 01:19:15.753538 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9871 01:19:15.756948 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9872 01:19:15.763740 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9873 01:19:15.767043 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9874 01:19:15.773751 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9875 01:19:15.776869 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9876 01:19:15.779925 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9877 01:19:15.786845 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9878 01:19:15.789800 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9879 01:19:15.796645 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9880 01:19:15.799853 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9881 01:19:15.806448 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9882 01:19:15.810021 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9883 01:19:15.816285 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9884 01:19:15.819905 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9885 01:19:15.823320 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9886 01:19:15.830034 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9887 01:19:15.833306 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9888 01:19:15.839612 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9889 01:19:15.842847 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9890 01:19:15.849374 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9891 01:19:15.852634 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9892 01:19:15.856069 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9893 01:19:15.862778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9894 01:19:15.866081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9895 01:19:15.872350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9896 01:19:15.875766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9897 01:19:15.882201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9898 01:19:15.885806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9899 01:19:15.892405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9900 01:19:15.895831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9901 01:19:15.902210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9902 01:19:15.905531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9903 01:19:15.912488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9904 01:19:15.915284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9905 01:19:15.922166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9906 01:19:15.925254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9907 01:19:15.932029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9908 01:19:15.935516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9909 01:19:15.938848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9910 01:19:15.945454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9911 01:19:15.948693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9912 01:19:15.955517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9913 01:19:15.958849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9914 01:19:15.965472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9915 01:19:15.968469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9916 01:19:15.975183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9917 01:19:15.982067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9918 01:19:15.985359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9919 01:19:15.991917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9920 01:19:15.995181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9921 01:19:16.002102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9922 01:19:16.005060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9923 01:19:16.011453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9924 01:19:16.014944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9925 01:19:16.018072 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9926 01:19:16.021944 INFO: [APUAPC] vio 0
9927 01:19:16.024997 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9928 01:19:16.031637 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9929 01:19:16.035312 INFO: [APUAPC] D0_APC_0: 0x400510
9930 01:19:16.038326 INFO: [APUAPC] D0_APC_1: 0x0
9931 01:19:16.041598 INFO: [APUAPC] D0_APC_2: 0x1540
9932 01:19:16.041728 INFO: [APUAPC] D0_APC_3: 0x0
9933 01:19:16.044869 INFO: [APUAPC] D1_APC_0: 0xffffffff
9934 01:19:16.051859 INFO: [APUAPC] D1_APC_1: 0xffffffff
9935 01:19:16.054650 INFO: [APUAPC] D1_APC_2: 0x3fffff
9936 01:19:16.054754 INFO: [APUAPC] D1_APC_3: 0x0
9937 01:19:16.058283 INFO: [APUAPC] D2_APC_0: 0xffffffff
9938 01:19:16.061701 INFO: [APUAPC] D2_APC_1: 0xffffffff
9939 01:19:16.064535 INFO: [APUAPC] D2_APC_2: 0x3fffff
9940 01:19:16.067936 INFO: [APUAPC] D2_APC_3: 0x0
9941 01:19:16.071223 INFO: [APUAPC] D3_APC_0: 0xffffffff
9942 01:19:16.074975 INFO: [APUAPC] D3_APC_1: 0xffffffff
9943 01:19:16.077816 INFO: [APUAPC] D3_APC_2: 0x3fffff
9944 01:19:16.081277 INFO: [APUAPC] D3_APC_3: 0x0
9945 01:19:16.084829 INFO: [APUAPC] D4_APC_0: 0xffffffff
9946 01:19:16.088052 INFO: [APUAPC] D4_APC_1: 0xffffffff
9947 01:19:16.091277 INFO: [APUAPC] D4_APC_2: 0x3fffff
9948 01:19:16.094699 INFO: [APUAPC] D4_APC_3: 0x0
9949 01:19:16.098041 INFO: [APUAPC] D5_APC_0: 0xffffffff
9950 01:19:16.100929 INFO: [APUAPC] D5_APC_1: 0xffffffff
9951 01:19:16.104307 INFO: [APUAPC] D5_APC_2: 0x3fffff
9952 01:19:16.107642 INFO: [APUAPC] D5_APC_3: 0x0
9953 01:19:16.111390 INFO: [APUAPC] D6_APC_0: 0xffffffff
9954 01:19:16.114391 INFO: [APUAPC] D6_APC_1: 0xffffffff
9955 01:19:16.117662 INFO: [APUAPC] D6_APC_2: 0x3fffff
9956 01:19:16.120841 INFO: [APUAPC] D6_APC_3: 0x0
9957 01:19:16.124348 INFO: [APUAPC] D7_APC_0: 0xffffffff
9958 01:19:16.127631 INFO: [APUAPC] D7_APC_1: 0xffffffff
9959 01:19:16.131014 INFO: [APUAPC] D7_APC_2: 0x3fffff
9960 01:19:16.134181 INFO: [APUAPC] D7_APC_3: 0x0
9961 01:19:16.137319 INFO: [APUAPC] D8_APC_0: 0xffffffff
9962 01:19:16.140839 INFO: [APUAPC] D8_APC_1: 0xffffffff
9963 01:19:16.143970 INFO: [APUAPC] D8_APC_2: 0x3fffff
9964 01:19:16.147488 INFO: [APUAPC] D8_APC_3: 0x0
9965 01:19:16.150429 INFO: [APUAPC] D9_APC_0: 0xffffffff
9966 01:19:16.154260 INFO: [APUAPC] D9_APC_1: 0xffffffff
9967 01:19:16.157665 INFO: [APUAPC] D9_APC_2: 0x3fffff
9968 01:19:16.160969 INFO: [APUAPC] D9_APC_3: 0x0
9969 01:19:16.163794 INFO: [APUAPC] D10_APC_0: 0xffffffff
9970 01:19:16.167158 INFO: [APUAPC] D10_APC_1: 0xffffffff
9971 01:19:16.170898 INFO: [APUAPC] D10_APC_2: 0x3fffff
9972 01:19:16.173971 INFO: [APUAPC] D10_APC_3: 0x0
9973 01:19:16.177259 INFO: [APUAPC] D11_APC_0: 0xffffffff
9974 01:19:16.180754 INFO: [APUAPC] D11_APC_1: 0xffffffff
9975 01:19:16.184074 INFO: [APUAPC] D11_APC_2: 0x3fffff
9976 01:19:16.187495 INFO: [APUAPC] D11_APC_3: 0x0
9977 01:19:16.190251 INFO: [APUAPC] D12_APC_0: 0xffffffff
9978 01:19:16.193485 INFO: [APUAPC] D12_APC_1: 0xffffffff
9979 01:19:16.197002 INFO: [APUAPC] D12_APC_2: 0x3fffff
9980 01:19:16.200331 INFO: [APUAPC] D12_APC_3: 0x0
9981 01:19:16.203724 INFO: [APUAPC] D13_APC_0: 0xffffffff
9982 01:19:16.207033 INFO: [APUAPC] D13_APC_1: 0xffffffff
9983 01:19:16.210300 INFO: [APUAPC] D13_APC_2: 0x3fffff
9984 01:19:16.213706 INFO: [APUAPC] D13_APC_3: 0x0
9985 01:19:16.217041 INFO: [APUAPC] D14_APC_0: 0xffffffff
9986 01:19:16.220601 INFO: [APUAPC] D14_APC_1: 0xffffffff
9987 01:19:16.223617 INFO: [APUAPC] D14_APC_2: 0x3fffff
9988 01:19:16.226901 INFO: [APUAPC] D14_APC_3: 0x0
9989 01:19:16.230363 INFO: [APUAPC] D15_APC_0: 0xffffffff
9990 01:19:16.233500 INFO: [APUAPC] D15_APC_1: 0xffffffff
9991 01:19:16.237035 INFO: [APUAPC] D15_APC_2: 0x3fffff
9992 01:19:16.240256 INFO: [APUAPC] D15_APC_3: 0x0
9993 01:19:16.243119 INFO: [APUAPC] APC_CON: 0x4
9994 01:19:16.246580 INFO: [NOCDAPC] D0_APC_0: 0x0
9995 01:19:16.250059 INFO: [NOCDAPC] D0_APC_1: 0x0
9996 01:19:16.253396 INFO: [NOCDAPC] D1_APC_0: 0x0
9997 01:19:16.253553 INFO: [NOCDAPC] D1_APC_1: 0xfff
9998 01:19:16.256834 INFO: [NOCDAPC] D2_APC_0: 0x0
9999 01:19:16.260229 INFO: [NOCDAPC] D2_APC_1: 0xfff
10000 01:19:16.263411 INFO: [NOCDAPC] D3_APC_0: 0x0
10001 01:19:16.266295 INFO: [NOCDAPC] D3_APC_1: 0xfff
10002 01:19:16.269584 INFO: [NOCDAPC] D4_APC_0: 0x0
10003 01:19:16.272990 INFO: [NOCDAPC] D4_APC_1: 0xfff
10004 01:19:16.276211 INFO: [NOCDAPC] D5_APC_0: 0x0
10005 01:19:16.279877 INFO: [NOCDAPC] D5_APC_1: 0xfff
10006 01:19:16.283200 INFO: [NOCDAPC] D6_APC_0: 0x0
10007 01:19:16.286463 INFO: [NOCDAPC] D6_APC_1: 0xfff
10008 01:19:16.286607 INFO: [NOCDAPC] D7_APC_0: 0x0
10009 01:19:16.289568 INFO: [NOCDAPC] D7_APC_1: 0xfff
10010 01:19:16.293063 INFO: [NOCDAPC] D8_APC_0: 0x0
10011 01:19:16.296454 INFO: [NOCDAPC] D8_APC_1: 0xfff
10012 01:19:16.299577 INFO: [NOCDAPC] D9_APC_0: 0x0
10013 01:19:16.302908 INFO: [NOCDAPC] D9_APC_1: 0xfff
10014 01:19:16.306324 INFO: [NOCDAPC] D10_APC_0: 0x0
10015 01:19:16.309677 INFO: [NOCDAPC] D10_APC_1: 0xfff
10016 01:19:16.313077 INFO: [NOCDAPC] D11_APC_0: 0x0
10017 01:19:16.316511 INFO: [NOCDAPC] D11_APC_1: 0xfff
10018 01:19:16.319789 INFO: [NOCDAPC] D12_APC_0: 0x0
10019 01:19:16.322641 INFO: [NOCDAPC] D12_APC_1: 0xfff
10020 01:19:16.326603 INFO: [NOCDAPC] D13_APC_0: 0x0
10021 01:19:16.329551 INFO: [NOCDAPC] D13_APC_1: 0xfff
10022 01:19:16.329700 INFO: [NOCDAPC] D14_APC_0: 0x0
10023 01:19:16.332799 INFO: [NOCDAPC] D14_APC_1: 0xfff
10024 01:19:16.336094 INFO: [NOCDAPC] D15_APC_0: 0x0
10025 01:19:16.339589 INFO: [NOCDAPC] D15_APC_1: 0xfff
10026 01:19:16.342580 INFO: [NOCDAPC] APC_CON: 0x4
10027 01:19:16.345776 INFO: [APUAPC] set_apusys_apc done
10028 01:19:16.349347 INFO: [DEVAPC] devapc_init done
10029 01:19:16.352452 INFO: GICv3 without legacy support detected.
10030 01:19:16.359162 INFO: ARM GICv3 driver initialized in EL3
10031 01:19:16.362563 INFO: Maximum SPI INTID supported: 639
10032 01:19:16.365906 INFO: BL31: Initializing runtime services
10033 01:19:16.372736 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10034 01:19:16.372964 INFO: SPM: enable CPC mode
10035 01:19:16.379340 INFO: mcdi ready for mcusys-off-idle and system suspend
10036 01:19:16.382651 INFO: BL31: Preparing for EL3 exit to normal world
10037 01:19:16.389211 INFO: Entry point address = 0x80000000
10038 01:19:16.389430 INFO: SPSR = 0x8
10039 01:19:16.395553
10040 01:19:16.395689
10041 01:19:16.395787
10042 01:19:16.398369 Starting depthcharge on Spherion...
10043 01:19:16.398502
10044 01:19:16.398617 Wipe memory regions:
10045 01:19:16.398728
10046 01:19:16.399638 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10047 01:19:16.399772 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10048 01:19:16.399882 Setting prompt string to ['asurada:']
10049 01:19:16.399989 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10050 01:19:16.401731 [0x00000040000000, 0x00000054600000)
10051 01:19:16.524267
10052 01:19:16.524458 [0x00000054660000, 0x00000080000000)
10053 01:19:16.785256
10054 01:19:16.785460 [0x000000821a7280, 0x000000ffe64000)
10055 01:19:17.530173
10056 01:19:17.530349 [0x00000100000000, 0x00000240000000)
10057 01:19:19.420360
10058 01:19:19.423310 Initializing XHCI USB controller at 0x11200000.
10059 01:19:20.461743
10060 01:19:20.464470 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10061 01:19:20.464594
10062 01:19:20.464694
10063 01:19:20.464789
10064 01:19:20.465124 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10066 01:19:20.565541 asurada: tftpboot 192.168.201.1 13468751/tftp-deploy-efs9j2v9/kernel/image.itb 13468751/tftp-deploy-efs9j2v9/kernel/cmdline
10067 01:19:20.565698 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 01:19:20.565785 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10069 01:19:20.569617 tftpboot 192.168.201.1 13468751/tftp-deploy-efs9j2v9/kernel/image.itp-deploy-efs9j2v9/kernel/cmdline
10070 01:19:20.569706
10071 01:19:20.569772 Waiting for link
10072 01:19:20.730233
10073 01:19:20.730416 R8152: Initializing
10074 01:19:20.730511
10075 01:19:20.733875 Version 6 (ocp_data = 5c30)
10076 01:19:20.733959
10077 01:19:20.736631 R8152: Done initializing
10078 01:19:20.736789
10079 01:19:20.736932 Adding net device
10080 01:19:22.766642
10081 01:19:22.766774 done.
10082 01:19:22.766840
10083 01:19:22.766899 MAC: 00:24:32:30:78:ff
10084 01:19:22.766957
10085 01:19:22.770202 Sending DHCP discover... done.
10086 01:19:22.770333
10087 01:19:22.772816 Waiting for reply... done.
10088 01:19:22.772908
10089 01:19:22.776377 Sending DHCP request... done.
10090 01:19:22.776460
10091 01:19:22.776525 Waiting for reply... done.
10092 01:19:22.776586
10093 01:19:22.779677 My ip is 192.168.201.21
10094 01:19:22.779758
10095 01:19:22.783085 The DHCP server ip is 192.168.201.1
10096 01:19:22.783201
10097 01:19:22.786459 TFTP server IP predefined by user: 192.168.201.1
10098 01:19:22.786607
10099 01:19:22.792546 Bootfile predefined by user: 13468751/tftp-deploy-efs9j2v9/kernel/image.itb
10100 01:19:22.792643
10101 01:19:22.795889 Sending tftp read request... done.
10102 01:19:22.795974
10103 01:19:22.802407 Waiting for the transfer...
10104 01:19:22.802577
10105 01:19:23.355665 00000000 ################################################################
10106 01:19:23.355811
10107 01:19:23.920816 00080000 ################################################################
10108 01:19:23.920963
10109 01:19:24.498235 00100000 ################################################################
10110 01:19:24.498398
10111 01:19:25.062983 00180000 ################################################################
10112 01:19:25.063200
10113 01:19:25.608688 00200000 ################################################################
10114 01:19:25.608841
10115 01:19:26.173056 00280000 ################################################################
10116 01:19:26.173193
10117 01:19:26.814951 00300000 ################################################################
10118 01:19:26.815080
10119 01:19:27.398477 00380000 ################################################################
10120 01:19:27.398693
10121 01:19:27.965963 00400000 ################################################################
10122 01:19:27.966100
10123 01:19:28.513679 00480000 ################################################################
10124 01:19:28.513817
10125 01:19:29.056185 00500000 ################################################################
10126 01:19:29.056322
10127 01:19:29.615917 00580000 ################################################################
10128 01:19:29.616049
10129 01:19:30.174956 00600000 ################################################################
10130 01:19:30.175142
10131 01:19:30.722096 00680000 ################################################################
10132 01:19:30.722232
10133 01:19:31.269166 00700000 ################################################################
10134 01:19:31.269319
10135 01:19:31.814018 00780000 ################################################################
10136 01:19:31.814154
10137 01:19:32.350902 00800000 ################################################################
10138 01:19:32.351061
10139 01:19:32.930514 00880000 ################################################################
10140 01:19:32.930649
10141 01:19:33.463250 00900000 ################################################################
10142 01:19:33.463393
10143 01:19:33.997530 00980000 ################################################################
10144 01:19:33.997722
10145 01:19:34.536523 00a00000 ################################################################
10146 01:19:34.536662
10147 01:19:35.071001 00a80000 ################################################################
10148 01:19:35.071148
10149 01:19:35.592226 00b00000 ################################################################
10150 01:19:35.592367
10151 01:19:36.119844 00b80000 ################################################################
10152 01:19:36.119984
10153 01:19:36.653857 00c00000 ################################################################
10154 01:19:36.653996
10155 01:19:37.177520 00c80000 ################################################################
10156 01:19:37.177681
10157 01:19:37.703265 00d00000 ################################################################
10158 01:19:37.703397
10159 01:19:38.229375 00d80000 ################################################################
10160 01:19:38.229574
10161 01:19:38.749747 00e00000 ################################################################
10162 01:19:38.749884
10163 01:19:39.278822 00e80000 ################################################################
10164 01:19:39.278984
10165 01:19:39.804854 00f00000 ################################################################
10166 01:19:39.804993
10167 01:19:40.327667 00f80000 ################################################################
10168 01:19:40.327801
10169 01:19:40.848221 01000000 ################################################################
10170 01:19:40.848364
10171 01:19:41.369624 01080000 ################################################################
10172 01:19:41.369761
10173 01:19:41.900982 01100000 ################################################################
10174 01:19:41.901121
10175 01:19:42.426643 01180000 ################################################################
10176 01:19:42.426789
10177 01:19:42.945081 01200000 ################################################################
10178 01:19:42.945223
10179 01:19:43.460844 01280000 ################################################################
10180 01:19:43.461052
10181 01:19:43.979309 01300000 ################################################################
10182 01:19:43.979447
10183 01:19:44.501584 01380000 ################################################################
10184 01:19:44.501764
10185 01:19:45.021318 01400000 ################################################################
10186 01:19:45.021482
10187 01:19:45.546852 01480000 ################################################################
10188 01:19:45.547018
10189 01:19:46.067950 01500000 ################################################################
10190 01:19:46.068109
10191 01:19:46.596446 01580000 ################################################################
10192 01:19:46.596620
10193 01:19:47.118500 01600000 ################################################################
10194 01:19:47.118695
10195 01:19:47.640364 01680000 ################################################################
10196 01:19:47.640531
10197 01:19:48.158392 01700000 ################################################################
10198 01:19:48.158548
10199 01:19:48.677161 01780000 ################################################################
10200 01:19:48.677310
10201 01:19:49.191662 01800000 ################################################################
10202 01:19:49.191801
10203 01:19:49.706113 01880000 ################################################################
10204 01:19:49.706337
10205 01:19:50.218558 01900000 ################################################################
10206 01:19:50.218727
10207 01:19:50.731989 01980000 ################################################################
10208 01:19:50.732136
10209 01:19:51.245196 01a00000 ################################################################
10210 01:19:51.245374
10211 01:19:51.813044 01a80000 ################################################################
10212 01:19:51.813222
10213 01:19:52.400976 01b00000 ################################################################
10214 01:19:52.401146
10215 01:19:53.004651 01b80000 ################################################################
10216 01:19:53.004815
10217 01:19:53.533197 01c00000 ################################################################
10218 01:19:53.533361
10219 01:19:54.058467 01c80000 ################################################################
10220 01:19:54.058656
10221 01:19:54.578293 01d00000 ################################################################
10222 01:19:54.578454
10223 01:19:55.105056 01d80000 ################################################################
10224 01:19:55.105216
10225 01:19:55.621715 01e00000 ################################################################
10226 01:19:55.621878
10227 01:19:56.150173 01e80000 ################################################################
10228 01:19:56.150339
10229 01:19:56.675929 01f00000 ################################################################
10230 01:19:56.676100
10231 01:19:57.201570 01f80000 ################################################################
10232 01:19:57.201713
10233 01:19:57.724512 02000000 ################################################################
10234 01:19:57.724690
10235 01:19:58.247829 02080000 ################################################################
10236 01:19:58.248002
10237 01:19:58.775639 02100000 ################################################################
10238 01:19:58.775786
10239 01:19:59.299558 02180000 ################################################################
10240 01:19:59.299703
10241 01:19:59.828235 02200000 ################################################################
10242 01:19:59.828414
10243 01:20:00.351778 02280000 ################################################################
10244 01:20:00.351972
10245 01:20:00.883434 02300000 ################################################################
10246 01:20:00.883587
10247 01:20:01.415623 02380000 ################################################################
10248 01:20:01.415782
10249 01:20:01.943693 02400000 ################################################################
10250 01:20:01.943880
10251 01:20:02.466251 02480000 ################################################################
10252 01:20:02.466447
10253 01:20:02.992026 02500000 ################################################################
10254 01:20:02.992165
10255 01:20:03.517203 02580000 ################################################################
10256 01:20:03.517449
10257 01:20:04.040220 02600000 ################################################################
10258 01:20:04.040360
10259 01:20:04.571313 02680000 ################################################################
10260 01:20:04.571447
10261 01:20:05.091504 02700000 ################################################################
10262 01:20:05.091654
10263 01:20:05.613798 02780000 ################################################################
10264 01:20:05.613974
10265 01:20:06.135165 02800000 ################################################################
10266 01:20:06.135359
10267 01:20:06.656534 02880000 ################################################################
10268 01:20:06.656730
10269 01:20:07.175381 02900000 ################################################################
10270 01:20:07.175536
10271 01:20:07.701968 02980000 ################################################################
10272 01:20:07.702117
10273 01:20:08.228993 02a00000 ################################################################
10274 01:20:08.229155
10275 01:20:08.752851 02a80000 ################################################################
10276 01:20:08.752990
10277 01:20:09.279799 02b00000 ################################################################
10278 01:20:09.279971
10279 01:20:09.805546 02b80000 ################################################################
10280 01:20:09.805686
10281 01:20:10.329998 02c00000 ################################################################
10282 01:20:10.330165
10283 01:20:10.858628 02c80000 ################################################################
10284 01:20:10.858796
10285 01:20:11.383877 02d00000 ################################################################
10286 01:20:11.384048
10287 01:20:11.913846 02d80000 ################################################################
10288 01:20:11.914002
10289 01:20:12.441929 02e00000 ################################################################
10290 01:20:12.442088
10291 01:20:12.969129 02e80000 ################################################################
10292 01:20:12.969307
10293 01:20:13.493038 02f00000 ################################################################
10294 01:20:13.493206
10295 01:20:14.011381 02f80000 ################################################################
10296 01:20:14.011557
10297 01:20:14.533577 03000000 ################################################################
10298 01:20:14.533712
10299 01:20:15.058373 03080000 ################################################################
10300 01:20:15.058672
10301 01:20:15.579516 03100000 ################################################################
10302 01:20:15.579677
10303 01:20:16.095190 03180000 ################################################################
10304 01:20:16.095362
10305 01:20:16.611636 03200000 ################################################################
10306 01:20:16.611804
10307 01:20:17.136144 03280000 ################################################################
10308 01:20:17.136294
10309 01:20:17.669483 03300000 ################################################################
10310 01:20:17.669659
10311 01:20:18.196846 03380000 ################################################################
10312 01:20:18.196992
10313 01:20:18.725951 03400000 ################################################################
10314 01:20:18.726119
10315 01:20:19.258887 03480000 ################################################################
10316 01:20:19.259060
10317 01:20:19.811946 03500000 ################################################################
10318 01:20:19.812104
10319 01:20:20.364639 03580000 ################################################################
10320 01:20:20.364836
10321 01:20:20.986394 03600000 ################################################################
10322 01:20:20.986893
10323 01:20:21.640460 03680000 ################################################################
10324 01:20:21.640953
10325 01:20:22.240013 03700000 ################################################################
10326 01:20:22.240174
10327 01:20:22.836581 03780000 ################################################################
10328 01:20:22.836722
10329 01:20:23.377798 03800000 ################################################################
10330 01:20:23.377939
10331 01:20:23.928151 03880000 ################################################################
10332 01:20:23.928310
10333 01:20:24.506163 03900000 ################################################################
10334 01:20:24.506300
10335 01:20:25.092709 03980000 ################################################################
10336 01:20:25.092849
10337 01:20:25.657240 03a00000 ################################################################
10338 01:20:25.657413
10339 01:20:26.219597 03a80000 ################################################################
10340 01:20:26.219731
10341 01:20:26.758406 03b00000 ################################################################
10342 01:20:26.758565
10343 01:20:27.345185 03b80000 ################################################################
10344 01:20:27.345803
10345 01:20:27.899054 03c00000 ################################################################
10346 01:20:27.899198
10347 01:20:28.595966 03c80000 ################################################################
10348 01:20:28.596594
10349 01:20:29.202270 03d00000 ################################################################
10350 01:20:29.202411
10351 01:20:29.768827 03d80000 ################################################################
10352 01:20:29.768965
10353 01:20:29.905254 03e00000 ################ done.
10354 01:20:29.905425
10355 01:20:29.908333 The bootfile was 65140542 bytes long.
10356 01:20:29.908417
10357 01:20:29.911404 Sending tftp read request... done.
10358 01:20:29.911485
10359 01:20:29.911549 Waiting for the transfer...
10360 01:20:29.911609
10361 01:20:29.914486 00000000 # done.
10362 01:20:29.914570
10363 01:20:29.921503 Command line loaded dynamically from TFTP file: 13468751/tftp-deploy-efs9j2v9/kernel/cmdline
10364 01:20:29.921625
10365 01:20:29.934955 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10366 01:20:29.935044
10367 01:20:29.937849 Loading FIT.
10368 01:20:29.937930
10369 01:20:29.941719 Image ramdisk-1 has 52181228 bytes.
10370 01:20:29.941800
10371 01:20:29.941865 Image fdt-1 has 47230 bytes.
10372 01:20:29.944777
10373 01:20:29.944857 Image kernel-1 has 12910050 bytes.
10374 01:20:29.944921
10375 01:20:29.954649 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10376 01:20:29.954739
10377 01:20:29.971221 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10378 01:20:29.971311
10379 01:20:29.977695 Choosing best match conf-1 for compat google,spherion-rev2.
10380 01:20:29.982012
10381 01:20:29.986527 Connected to device vid:did:rid of 1ae0:0028:00
10382 01:20:29.994632
10383 01:20:29.998414 tpm_get_response: command 0x17b, return code 0x0
10384 01:20:29.998497
10385 01:20:30.001392 ec_init: CrosEC protocol v3 supported (256, 248)
10386 01:20:30.005689
10387 01:20:30.008781 tpm_cleanup: add release locality here.
10388 01:20:30.008862
10389 01:20:30.008926 Shutting down all USB controllers.
10390 01:20:30.011682
10391 01:20:30.011763 Removing current net device
10392 01:20:30.011828
10393 01:20:30.018445 Exiting depthcharge with code 4 at timestamp: 102948932
10394 01:20:30.018527
10395 01:20:30.022026 LZMA decompressing kernel-1 to 0x821a6718
10396 01:20:30.022108
10397 01:20:30.024984 LZMA decompressing kernel-1 to 0x40000000
10398 01:20:31.619573
10399 01:20:31.619708 jumping to kernel
10400 01:20:31.620268 end: 2.2.4 bootloader-commands (duration 00:01:15) [common]
10401 01:20:31.620405 start: 2.2.5 auto-login-action (timeout 00:03:10) [common]
10402 01:20:31.620513 Setting prompt string to ['Linux version [0-9]']
10403 01:20:31.620617 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10404 01:20:31.620716 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10405 01:20:31.701584
10406 01:20:31.704683 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10407 01:20:31.708439 start: 2.2.5.1 login-action (timeout 00:03:10) [common]
10408 01:20:31.708541 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10409 01:20:31.708618 Setting prompt string to []
10410 01:20:31.708707 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10411 01:20:31.708819 Using line separator: #'\n'#
10412 01:20:31.708908 No login prompt set.
10413 01:20:31.709007 Parsing kernel messages
10414 01:20:31.709093 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10415 01:20:31.709266 [login-action] Waiting for messages, (timeout 00:03:10)
10416 01:20:31.709359 Waiting using forced prompt support (timeout 00:01:35)
10417 01:20:31.728111 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10418 01:20:31.731620 [ 0.000000] random: crng init done
10419 01:20:31.738180 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10420 01:20:31.741300 [ 0.000000] efi: UEFI not found.
10421 01:20:31.748070 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10422 01:20:31.754290 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10423 01:20:31.764204 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10424 01:20:31.774153 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10425 01:20:31.780809 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10426 01:20:31.787196 [ 0.000000] printk: bootconsole [mtk8250] enabled
10427 01:20:31.793789 [ 0.000000] NUMA: No NUMA configuration found
10428 01:20:31.800631 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10429 01:20:31.806769 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10430 01:20:31.806852 [ 0.000000] Zone ranges:
10431 01:20:31.813655 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10432 01:20:31.816796 [ 0.000000] DMA32 empty
10433 01:20:31.823642 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10434 01:20:31.826695 [ 0.000000] Movable zone start for each node
10435 01:20:31.829663 [ 0.000000] Early memory node ranges
10436 01:20:31.836815 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10437 01:20:31.843051 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10438 01:20:31.849337 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10439 01:20:31.856129 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10440 01:20:31.863148 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10441 01:20:31.869302 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10442 01:20:31.926468 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10443 01:20:31.932751 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10444 01:20:31.939611 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10445 01:20:31.942610 [ 0.000000] psci: probing for conduit method from DT.
10446 01:20:31.949513 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10447 01:20:31.952519 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10448 01:20:31.959130 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10449 01:20:31.962638 [ 0.000000] psci: SMC Calling Convention v1.2
10450 01:20:31.969266 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10451 01:20:31.972451 [ 0.000000] Detected VIPT I-cache on CPU0
10452 01:20:31.979093 [ 0.000000] CPU features: detected: GIC system register CPU interface
10453 01:20:31.985530 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10454 01:20:31.992655 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10455 01:20:31.998936 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10456 01:20:32.008811 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10457 01:20:32.015343 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10458 01:20:32.018955 [ 0.000000] alternatives: applying boot alternatives
10459 01:20:32.025335 [ 0.000000] Fallback order for Node 0: 0
10460 01:20:32.032266 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10461 01:20:32.035351 [ 0.000000] Policy zone: Normal
10462 01:20:32.048590 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10463 01:20:32.058690 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10464 01:20:32.070737 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10465 01:20:32.080275 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10466 01:20:32.086987 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10467 01:20:32.090548 <6>[ 0.000000] software IO TLB: area num 8.
10468 01:20:32.147173 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10469 01:20:32.296543 <6>[ 0.000000] Memory: 7913548K/8385536K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 439220K reserved, 32768K cma-reserved)
10470 01:20:32.303339 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10471 01:20:32.310249 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10472 01:20:32.313452 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10473 01:20:32.320104 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10474 01:20:32.326307 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10475 01:20:32.329630 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10476 01:20:32.339733 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10477 01:20:32.346182 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10478 01:20:32.353118 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10479 01:20:32.359448 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10480 01:20:32.363283 <6>[ 0.000000] GICv3: 608 SPIs implemented
10481 01:20:32.366295 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10482 01:20:32.372959 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10483 01:20:32.376035 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10484 01:20:32.382872 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10485 01:20:32.395643 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10486 01:20:32.409262 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10487 01:20:32.415847 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10488 01:20:32.423214 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10489 01:20:32.436460 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10490 01:20:32.442869 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10491 01:20:32.449944 <6>[ 0.009186] Console: colour dummy device 80x25
10492 01:20:32.459888 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10493 01:20:32.466202 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10494 01:20:32.469831 <6>[ 0.029217] LSM: Security Framework initializing
10495 01:20:32.476591 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10496 01:20:32.486441 <6>[ 0.042017] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10497 01:20:32.492728 <6>[ 0.051437] cblist_init_generic: Setting adjustable number of callback queues.
10498 01:20:32.499474 <6>[ 0.058914] cblist_init_generic: Setting shift to 3 and lim to 1.
10499 01:20:32.509929 <6>[ 0.065253] cblist_init_generic: Setting adjustable number of callback queues.
10500 01:20:32.515873 <6>[ 0.072680] cblist_init_generic: Setting shift to 3 and lim to 1.
10501 01:20:32.519705 <6>[ 0.079121] rcu: Hierarchical SRCU implementation.
10502 01:20:32.525881 <6>[ 0.084136] rcu: Max phase no-delay instances is 1000.
10503 01:20:32.532575 <6>[ 0.091163] EFI services will not be available.
10504 01:20:32.535790 <6>[ 0.096149] smp: Bringing up secondary CPUs ...
10505 01:20:32.544396 <6>[ 0.101196] Detected VIPT I-cache on CPU1
10506 01:20:32.551061 <6>[ 0.101266] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10507 01:20:32.557263 <6>[ 0.101297] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10508 01:20:32.560621 <6>[ 0.101626] Detected VIPT I-cache on CPU2
10509 01:20:32.567396 <6>[ 0.101671] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10510 01:20:32.577032 <6>[ 0.101687] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10511 01:20:32.580405 <6>[ 0.101942] Detected VIPT I-cache on CPU3
10512 01:20:32.587083 <6>[ 0.101988] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10513 01:20:32.593309 <6>[ 0.102002] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10514 01:20:32.597047 <6>[ 0.102303] CPU features: detected: Spectre-v4
10515 01:20:32.603550 <6>[ 0.102309] CPU features: detected: Spectre-BHB
10516 01:20:32.606673 <6>[ 0.102314] Detected PIPT I-cache on CPU4
10517 01:20:32.613322 <6>[ 0.102370] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10518 01:20:32.620029 <6>[ 0.102387] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10519 01:20:32.626845 <6>[ 0.102678] Detected PIPT I-cache on CPU5
10520 01:20:32.633103 <6>[ 0.102740] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10521 01:20:32.639899 <6>[ 0.102756] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10522 01:20:32.643661 <6>[ 0.103034] Detected PIPT I-cache on CPU6
10523 01:20:32.649955 <6>[ 0.103099] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10524 01:20:32.656781 <6>[ 0.103115] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10525 01:20:32.663339 <6>[ 0.103407] Detected PIPT I-cache on CPU7
10526 01:20:32.669791 <6>[ 0.103472] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10527 01:20:32.676330 <6>[ 0.103488] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10528 01:20:32.679752 <6>[ 0.103535] smp: Brought up 1 node, 8 CPUs
10529 01:20:32.686111 <6>[ 0.244763] SMP: Total of 8 processors activated.
10530 01:20:32.690022 <6>[ 0.249685] CPU features: detected: 32-bit EL0 Support
10531 01:20:32.699633 <6>[ 0.255082] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10532 01:20:32.705746 <6>[ 0.263937] CPU features: detected: Common not Private translations
10533 01:20:32.712481 <6>[ 0.270413] CPU features: detected: CRC32 instructions
10534 01:20:32.716188 <6>[ 0.275764] CPU features: detected: RCpc load-acquire (LDAPR)
10535 01:20:32.722213 <6>[ 0.281724] CPU features: detected: LSE atomic instructions
10536 01:20:32.729045 <6>[ 0.287506] CPU features: detected: Privileged Access Never
10537 01:20:32.735755 <6>[ 0.293286] CPU features: detected: RAS Extension Support
10538 01:20:32.742432 <6>[ 0.298929] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10539 01:20:32.745475 <6>[ 0.306155] CPU: All CPU(s) started at EL2
10540 01:20:32.752275 <6>[ 0.310471] alternatives: applying system-wide alternatives
10541 01:20:32.761758 <6>[ 0.321327] devtmpfs: initialized
10542 01:20:32.777694 <6>[ 0.330253] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10543 01:20:32.784626 <6>[ 0.340215] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10544 01:20:32.790815 <6>[ 0.348463] pinctrl core: initialized pinctrl subsystem
10545 01:20:32.794133 <6>[ 0.355096] DMI not present or invalid.
10546 01:20:32.800692 <6>[ 0.359508] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10547 01:20:32.810471 <6>[ 0.366268] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10548 01:20:32.816931 <6>[ 0.373856] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10549 01:20:32.826905 <6>[ 0.382093] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10550 01:20:32.830032 <6>[ 0.390333] audit: initializing netlink subsys (disabled)
10551 01:20:32.840279 <5>[ 0.396026] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10552 01:20:32.846554 <6>[ 0.396724] thermal_sys: Registered thermal governor 'step_wise'
10553 01:20:32.853278 <6>[ 0.403990] thermal_sys: Registered thermal governor 'power_allocator'
10554 01:20:32.857021 <6>[ 0.410248] cpuidle: using governor menu
10555 01:20:32.863217 <6>[ 0.421209] NET: Registered PF_QIPCRTR protocol family
10556 01:20:32.869919 <6>[ 0.426700] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10557 01:20:32.876724 <6>[ 0.433801] ASID allocator initialised with 32768 entries
10558 01:20:32.879777 <6>[ 0.440369] Serial: AMBA PL011 UART driver
10559 01:20:32.889633 <4>[ 0.449103] Trying to register duplicate clock ID: 134
10560 01:20:32.944082 <6>[ 0.506544] KASLR enabled
10561 01:20:32.958228 <6>[ 0.514252] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10562 01:20:32.964522 <6>[ 0.521265] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10563 01:20:32.971494 <6>[ 0.527755] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10564 01:20:32.978167 <6>[ 0.534757] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10565 01:20:32.984480 <6>[ 0.541247] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10566 01:20:32.991362 <6>[ 0.548248] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10567 01:20:32.997718 <6>[ 0.554732] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10568 01:20:33.004505 <6>[ 0.561736] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10569 01:20:33.007681 <6>[ 0.569260] ACPI: Interpreter disabled.
10570 01:20:33.016261 <6>[ 0.575690] iommu: Default domain type: Translated
10571 01:20:33.022946 <6>[ 0.580803] iommu: DMA domain TLB invalidation policy: strict mode
10572 01:20:33.026075 <5>[ 0.587464] SCSI subsystem initialized
10573 01:20:33.032583 <6>[ 0.591626] usbcore: registered new interface driver usbfs
10574 01:20:33.039561 <6>[ 0.597357] usbcore: registered new interface driver hub
10575 01:20:33.042543 <6>[ 0.602905] usbcore: registered new device driver usb
10576 01:20:33.049675 <6>[ 0.608997] pps_core: LinuxPPS API ver. 1 registered
10577 01:20:33.059797 <6>[ 0.614191] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10578 01:20:33.062555 <6>[ 0.623535] PTP clock support registered
10579 01:20:33.066056 <6>[ 0.627778] EDAC MC: Ver: 3.0.0
10580 01:20:33.073986 <6>[ 0.632930] FPGA manager framework
10581 01:20:33.080248 <6>[ 0.636612] Advanced Linux Sound Architecture Driver Initialized.
10582 01:20:33.083365 <6>[ 0.643391] vgaarb: loaded
10583 01:20:33.090223 <6>[ 0.646558] clocksource: Switched to clocksource arch_sys_counter
10584 01:20:33.093469 <5>[ 0.653002] VFS: Disk quotas dquot_6.6.0
10585 01:20:33.100167 <6>[ 0.657187] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10586 01:20:33.103273 <6>[ 0.664375] pnp: PnP ACPI: disabled
10587 01:20:33.111711 <6>[ 0.671054] NET: Registered PF_INET protocol family
10588 01:20:33.121415 <6>[ 0.676646] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10589 01:20:33.133400 <6>[ 0.688965] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10590 01:20:33.142431 <6>[ 0.697775] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10591 01:20:33.149234 <6>[ 0.705745] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10592 01:20:33.159258 <6>[ 0.714445] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10593 01:20:33.165789 <6>[ 0.724194] TCP: Hash tables configured (established 65536 bind 65536)
10594 01:20:33.172461 <6>[ 0.731054] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10595 01:20:33.182069 <6>[ 0.738256] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10596 01:20:33.188938 <6>[ 0.745955] NET: Registered PF_UNIX/PF_LOCAL protocol family
10597 01:20:33.192045 <6>[ 0.752102] RPC: Registered named UNIX socket transport module.
10598 01:20:33.198840 <6>[ 0.758255] RPC: Registered udp transport module.
10599 01:20:33.201996 <6>[ 0.763186] RPC: Registered tcp transport module.
10600 01:20:33.208817 <6>[ 0.768119] RPC: Registered tcp NFSv4.1 backchannel transport module.
10601 01:20:33.215113 <6>[ 0.774782] PCI: CLS 0 bytes, default 64
10602 01:20:33.218719 <6>[ 0.779189] Unpacking initramfs...
10603 01:20:33.225451 <6>[ 0.782915] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10604 01:20:33.235506 <6>[ 0.791533] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10605 01:20:33.242240 <6>[ 0.800335] kvm [1]: IPA Size Limit: 40 bits
10606 01:20:33.245423 <6>[ 0.804864] kvm [1]: GICv3: no GICV resource entry
10607 01:20:33.248347 <6>[ 0.809882] kvm [1]: disabling GICv2 emulation
10608 01:20:33.255057 <6>[ 0.814564] kvm [1]: GIC system register CPU interface enabled
10609 01:20:33.261924 <6>[ 0.820723] kvm [1]: vgic interrupt IRQ18
10610 01:20:33.268791 <6>[ 0.826625] kvm [1]: VHE mode initialized successfully
10611 01:20:33.271834 <5>[ 0.833021] Initialise system trusted keyrings
10612 01:20:33.281631 <6>[ 0.837831] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10613 01:20:33.288342 <6>[ 0.847777] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10614 01:20:33.295104 <5>[ 0.854157] NFS: Registering the id_resolver key type
10615 01:20:33.298321 <5>[ 0.859455] Key type id_resolver registered
10616 01:20:33.305031 <5>[ 0.863869] Key type id_legacy registered
10617 01:20:33.311406 <6>[ 0.868146] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10618 01:20:33.318193 <6>[ 0.875067] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10619 01:20:33.324858 <6>[ 0.882773] 9p: Installing v9fs 9p2000 file system support
10620 01:20:33.361128 <5>[ 0.920329] Key type asymmetric registered
10621 01:20:33.364022 <5>[ 0.924659] Asymmetric key parser 'x509' registered
10622 01:20:33.374064 <6>[ 0.929806] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10623 01:20:33.377417 <6>[ 0.937420] io scheduler mq-deadline registered
10624 01:20:33.380769 <6>[ 0.942180] io scheduler kyber registered
10625 01:20:33.399920 <6>[ 0.959180] EINJ: ACPI disabled.
10626 01:20:33.432002 <4>[ 0.984702] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10627 01:20:33.441469 <4>[ 0.995323] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10628 01:20:33.456471 <6>[ 1.015893] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10629 01:20:33.464615 <6>[ 1.023938] printk: console [ttyS0] disabled
10630 01:20:33.492212 <6>[ 1.048569] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10631 01:20:33.499423 <6>[ 1.058039] printk: console [ttyS0] enabled
10632 01:20:33.502267 <6>[ 1.058039] printk: console [ttyS0] enabled
10633 01:20:33.509018 <6>[ 1.066932] printk: bootconsole [mtk8250] disabled
10634 01:20:33.512304 <6>[ 1.066932] printk: bootconsole [mtk8250] disabled
10635 01:20:33.518746 <6>[ 1.077978] SuperH (H)SCI(F) driver initialized
10636 01:20:33.522160 <6>[ 1.083258] msm_serial: driver initialized
10637 01:20:33.535988 <6>[ 1.092148] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10638 01:20:33.545658 <6>[ 1.100693] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10639 01:20:33.552454 <6>[ 1.109235] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10640 01:20:33.562481 <6>[ 1.117862] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10641 01:20:33.569384 <6>[ 1.126569] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10642 01:20:33.579335 <6>[ 1.135284] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10643 01:20:33.589194 <6>[ 1.143824] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10644 01:20:33.595833 <6>[ 1.152619] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10645 01:20:33.605527 <6>[ 1.161159] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10646 01:20:33.617191 <6>[ 1.176782] loop: module loaded
10647 01:20:33.623908 <6>[ 1.182796] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10648 01:20:33.646541 <4>[ 1.206125] mtk-pmic-keys: Failed to locate of_node [id: -1]
10649 01:20:33.653419 <6>[ 1.212948] megasas: 07.719.03.00-rc1
10650 01:20:33.663032 <6>[ 1.222539] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10651 01:20:33.670573 <6>[ 1.229959] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10652 01:20:33.686866 <6>[ 1.246465] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10653 01:20:33.743438 <6>[ 1.296253] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10654 01:20:35.437048 <6>[ 2.996752] Freeing initrd memory: 50956K
10655 01:20:35.449024 <6>[ 3.008589] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10656 01:20:35.460155 <6>[ 3.019775] tun: Universal TUN/TAP device driver, 1.6
10657 01:20:35.463172 <6>[ 3.025851] thunder_xcv, ver 1.0
10658 01:20:35.466766 <6>[ 3.029353] thunder_bgx, ver 1.0
10659 01:20:35.469749 <6>[ 3.032852] nicpf, ver 1.0
10660 01:20:35.480782 <6>[ 3.036883] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10661 01:20:35.483905 <6>[ 3.044359] hns3: Copyright (c) 2017 Huawei Corporation.
10662 01:20:35.490651 <6>[ 3.049952] hclge is initializing
10663 01:20:35.493700 <6>[ 3.053534] e1000: Intel(R) PRO/1000 Network Driver
10664 01:20:35.500596 <6>[ 3.058663] e1000: Copyright (c) 1999-2006 Intel Corporation.
10665 01:20:35.503559 <6>[ 3.064677] e1000e: Intel(R) PRO/1000 Network Driver
10666 01:20:35.510176 <6>[ 3.069893] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10667 01:20:35.517040 <6>[ 3.076077] igb: Intel(R) Gigabit Ethernet Network Driver
10668 01:20:35.523494 <6>[ 3.081728] igb: Copyright (c) 2007-2014 Intel Corporation.
10669 01:20:35.530222 <6>[ 3.087564] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10670 01:20:35.537174 <6>[ 3.094081] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10671 01:20:35.540191 <6>[ 3.100547] sky2: driver version 1.30
10672 01:20:35.546620 <6>[ 3.105551] VFIO - User Level meta-driver version: 0.3
10673 01:20:35.553924 <6>[ 3.113834] usbcore: registered new interface driver usb-storage
10674 01:20:35.560578 <6>[ 3.120286] usbcore: registered new device driver onboard-usb-hub
10675 01:20:35.570080 <6>[ 3.129468] mt6397-rtc mt6359-rtc: registered as rtc0
10676 01:20:35.579994 <6>[ 3.134936] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:20:35 UTC (1713835235)
10677 01:20:35.583243 <6>[ 3.144501] i2c_dev: i2c /dev entries driver
10678 01:20:35.600328 <6>[ 3.156353] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10679 01:20:35.606756 <4>[ 3.165080] cpu cpu0: supply cpu not found, using dummy regulator
10680 01:20:35.613388 <4>[ 3.171529] cpu cpu1: supply cpu not found, using dummy regulator
10681 01:20:35.619586 <4>[ 3.177938] cpu cpu2: supply cpu not found, using dummy regulator
10682 01:20:35.626429 <4>[ 3.184343] cpu cpu3: supply cpu not found, using dummy regulator
10683 01:20:35.633327 <4>[ 3.190736] cpu cpu4: supply cpu not found, using dummy regulator
10684 01:20:35.639563 <4>[ 3.197132] cpu cpu5: supply cpu not found, using dummy regulator
10685 01:20:35.646112 <4>[ 3.203549] cpu cpu6: supply cpu not found, using dummy regulator
10686 01:20:35.652907 <4>[ 3.209945] cpu cpu7: supply cpu not found, using dummy regulator
10687 01:20:35.670966 <6>[ 3.230581] cpu cpu0: EM: created perf domain
10688 01:20:35.674240 <6>[ 3.235510] cpu cpu4: EM: created perf domain
10689 01:20:35.681727 <6>[ 3.241116] sdhci: Secure Digital Host Controller Interface driver
10690 01:20:35.687809 <6>[ 3.247546] sdhci: Copyright(c) Pierre Ossman
10691 01:20:35.694695 <6>[ 3.252510] Synopsys Designware Multimedia Card Interface Driver
10692 01:20:35.701108 <6>[ 3.259154] sdhci-pltfm: SDHCI platform and OF driver helper
10693 01:20:35.704801 <6>[ 3.259165] mmc0: CQHCI version 5.10
10694 01:20:35.711658 <6>[ 3.269319] ledtrig-cpu: registered to indicate activity on CPUs
10695 01:20:35.717658 <6>[ 3.276439] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10696 01:20:35.724403 <6>[ 3.283498] usbcore: registered new interface driver usbhid
10697 01:20:35.727544 <6>[ 3.289324] usbhid: USB HID core driver
10698 01:20:35.734367 <6>[ 3.293531] spi_master spi0: will run message pump with realtime priority
10699 01:20:35.777197 <6>[ 3.330051] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10700 01:20:35.795495 <6>[ 3.345286] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10701 01:20:35.803186 <6>[ 3.360194] cros-ec-spi spi0.0: Chrome EC device registered
10702 01:20:35.806010 <6>[ 3.366286] mmc0: Command Queue Engine enabled
10703 01:20:35.812551 <6>[ 3.371041] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10704 01:20:35.819362 <6>[ 3.378715] mmcblk0: mmc0:0001 DA4128 116 GiB
10705 01:20:35.828454 <6>[ 3.388285] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10706 01:20:35.836515 <6>[ 3.395966] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10707 01:20:35.846510 <6>[ 3.399628] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10708 01:20:35.849759 <6>[ 3.401922] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10709 01:20:35.856187 <6>[ 3.411680] NET: Registered PF_PACKET protocol family
10710 01:20:35.863095 <6>[ 3.416414] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10711 01:20:35.866218 <6>[ 3.421090] 9pnet: Installing 9P2000 support
10712 01:20:35.872908 <5>[ 3.432107] Key type dns_resolver registered
10713 01:20:35.875918 <6>[ 3.437077] registered taskstats version 1
10714 01:20:35.882597 <5>[ 3.441462] Loading compiled-in X.509 certificates
10715 01:20:35.911333 <4>[ 3.464375] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10716 01:20:35.921433 <4>[ 3.475318] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10717 01:20:35.927977 <3>[ 3.485871] debugfs: File 'uA_load' in directory '/' already present!
10718 01:20:35.934536 <3>[ 3.492629] debugfs: File 'min_uV' in directory '/' already present!
10719 01:20:35.941354 <3>[ 3.499263] debugfs: File 'max_uV' in directory '/' already present!
10720 01:20:35.947715 <3>[ 3.505968] debugfs: File 'constraint_flags' in directory '/' already present!
10721 01:20:35.959451 <3>[ 3.515642] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10722 01:20:35.968814 <6>[ 3.528471] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10723 01:20:35.975572 <6>[ 3.535345] xhci-mtk 11200000.usb: xHCI Host Controller
10724 01:20:35.982203 <6>[ 3.540836] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10725 01:20:35.992598 <6>[ 3.548745] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10726 01:20:35.998920 <6>[ 3.558192] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10727 01:20:36.005614 <6>[ 3.564253] xhci-mtk 11200000.usb: xHCI Host Controller
10728 01:20:36.012189 <6>[ 3.569728] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10729 01:20:36.018811 <6>[ 3.577374] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10730 01:20:36.025685 <6>[ 3.584987] hub 1-0:1.0: USB hub found
10731 01:20:36.028355 <6>[ 3.588996] hub 1-0:1.0: 1 port detected
10732 01:20:36.038651 <6>[ 3.593249] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10733 01:20:36.042080 <6>[ 3.601902] hub 2-0:1.0: USB hub found
10734 01:20:36.045229 <6>[ 3.605919] hub 2-0:1.0: 1 port detected
10735 01:20:36.053941 <6>[ 3.613737] mtk-msdc 11f70000.mmc: Got CD GPIO
10736 01:20:36.071369 <6>[ 3.627895] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10737 01:20:36.078260 <6>[ 3.635930] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10738 01:20:36.087939 <4>[ 3.643826] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10739 01:20:36.097895 <6>[ 3.653352] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10740 01:20:36.104413 <6>[ 3.661429] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10741 01:20:36.111004 <6>[ 3.669534] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10742 01:20:36.120779 <6>[ 3.677461] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10743 01:20:36.127375 <6>[ 3.685281] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10744 01:20:36.137424 <6>[ 3.693098] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10745 01:20:36.147548 <6>[ 3.703683] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10746 01:20:36.153894 <6>[ 3.712041] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10747 01:20:36.164090 <6>[ 3.720380] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10748 01:20:36.174115 <6>[ 3.728718] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10749 01:20:36.180321 <6>[ 3.737056] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10750 01:20:36.190116 <6>[ 3.745395] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10751 01:20:36.196885 <6>[ 3.753732] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10752 01:20:36.206744 <6>[ 3.762070] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10753 01:20:36.213250 <6>[ 3.770408] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10754 01:20:36.223233 <6>[ 3.778745] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10755 01:20:36.230062 <6>[ 3.787082] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10756 01:20:36.239684 <6>[ 3.795421] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10757 01:20:36.246566 <6>[ 3.803758] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10758 01:20:36.256766 <6>[ 3.812097] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10759 01:20:36.263095 <6>[ 3.820434] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10760 01:20:36.269748 <6>[ 3.829214] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10761 01:20:36.276372 <6>[ 3.836422] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10762 01:20:36.283836 <6>[ 3.843194] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10763 01:20:36.293844 <6>[ 3.849960] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10764 01:20:36.300012 <6>[ 3.856888] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10765 01:20:36.306874 <6>[ 3.863733] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10766 01:20:36.316943 <6>[ 3.872869] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10767 01:20:36.326387 <6>[ 3.881989] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10768 01:20:36.336364 <6>[ 3.891315] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10769 01:20:36.346116 <6>[ 3.900789] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10770 01:20:36.356046 <6>[ 3.910258] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10771 01:20:36.362972 <6>[ 3.919377] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10772 01:20:36.372863 <6>[ 3.928843] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10773 01:20:36.382702 <6>[ 3.937962] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10774 01:20:36.392686 <6>[ 3.947256] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10775 01:20:36.402472 <6>[ 3.957417] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10776 01:20:36.412178 <6>[ 3.968907] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10777 01:20:36.434564 <6>[ 3.990864] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10778 01:20:36.462145 <6>[ 4.021552] hub 2-1:1.0: USB hub found
10779 01:20:36.465370 <6>[ 4.025978] hub 2-1:1.0: 3 ports detected
10780 01:20:36.473267 <6>[ 4.032803] hub 2-1:1.0: USB hub found
10781 01:20:36.476352 <6>[ 4.037286] hub 2-1:1.0: 3 ports detected
10782 01:20:36.586199 <6>[ 4.142856] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10783 01:20:36.744861 <6>[ 4.304860] hub 1-1:1.0: USB hub found
10784 01:20:36.748751 <6>[ 4.309342] hub 1-1:1.0: 4 ports detected
10785 01:20:36.757409 <6>[ 4.317341] hub 1-1:1.0: USB hub found
10786 01:20:36.761054 <6>[ 4.321878] hub 1-1:1.0: 4 ports detected
10787 01:20:36.830252 <6>[ 4.386948] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10788 01:20:37.082031 <6>[ 4.638876] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10789 01:20:37.214763 <6>[ 4.774769] hub 1-1.4:1.0: USB hub found
10790 01:20:37.218229 <6>[ 4.779445] hub 1-1.4:1.0: 2 ports detected
10791 01:20:37.228471 <6>[ 4.788419] hub 1-1.4:1.0: USB hub found
10792 01:20:37.231678 <6>[ 4.793079] hub 1-1.4:1.0: 2 ports detected
10793 01:20:37.530150 <6>[ 5.086856] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10794 01:20:37.721971 <6>[ 5.278858] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10795 01:20:48.707494 <6>[ 16.271879] ALSA device list:
10796 01:20:48.713834 <6>[ 16.275168] No soundcards found.
10797 01:20:48.722750 <6>[ 16.283737] Freeing unused kernel memory: 8448K
10798 01:20:48.726232 <6>[ 16.288719] Run /init as init process
10799 01:20:48.761699 <6>[ 16.323028] NET: Registered PF_INET6 protocol family
10800 01:20:48.768425 <6>[ 16.329447] Segment Routing with IPv6
10801 01:20:48.771944 <6>[ 16.333412] In-situ OAM (IOAM) with IPv6
10802 01:20:48.814790 <30>[ 16.349213] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10803 01:20:48.821120 <30>[ 16.382257] systemd[1]: Detected architecture arm64.
10804 01:20:48.821239
10805 01:20:48.827953 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10806 01:20:48.828038
10807 01:20:48.828101
10808 01:20:48.841439 <30>[ 16.402887] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10809 01:20:48.972121 <30>[ 16.530029] systemd[1]: Queued start job for default target graphical.target.
10810 01:20:49.007124 <30>[ 16.564770] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10811 01:20:49.013454 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10812 01:20:49.013587
10813 01:20:49.034044 <30>[ 16.591887] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10814 01:20:49.040698 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10815 01:20:49.043743
10816 01:20:49.065890 <30>[ 16.623633] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10817 01:20:49.075666 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10818 01:20:49.075751
10819 01:20:49.094464 <30>[ 16.652483] systemd[1]: Created slice user.slice - User and Session Slice.
10820 01:20:49.101285 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10821 01:20:49.101424
10822 01:20:49.125147 <30>[ 16.679675] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10823 01:20:49.134838 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10824 01:20:49.135012
10825 01:20:49.152698 <30>[ 16.707055] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10826 01:20:49.159209 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10827 01:20:49.159291
10828 01:20:49.187485 <30>[ 16.735418] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10829 01:20:49.197520 <30>[ 16.755319] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10830 01:20:49.203871 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10831 01:20:49.203990
10832 01:20:49.221292 <30>[ 16.779242] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10833 01:20:49.228008 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10834 01:20:49.230963
10835 01:20:49.250113 <30>[ 16.807373] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10836 01:20:49.259310 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10837 01:20:49.259427
10838 01:20:49.274753 <30>[ 16.835382] systemd[1]: Reached target paths.target - Path Units.
10839 01:20:49.281275 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10840 01:20:49.284307
10841 01:20:49.301825 <30>[ 16.859322] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10842 01:20:49.308471 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10843 01:20:49.308936
10844 01:20:49.321991 <30>[ 16.882833] systemd[1]: Reached target slices.target - Slice Units.
10845 01:20:49.332124 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10846 01:20:49.332552
10847 01:20:49.346246 <30>[ 16.907340] systemd[1]: Reached target swap.target - Swaps.
10848 01:20:49.352724 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10849 01:20:49.353151
10850 01:20:49.373876 <30>[ 16.931356] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10851 01:20:49.383800 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10852 01:20:49.384223
10853 01:20:49.402078 <30>[ 16.959336] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10854 01:20:49.411793 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10855 01:20:49.412273
10856 01:20:49.430876 <30>[ 16.988685] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10857 01:20:49.441124 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10858 01:20:49.441567
10859 01:20:49.457772 <30>[ 17.015531] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10860 01:20:49.467859 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10861 01:20:49.468274
10862 01:20:49.485897 <30>[ 17.043500] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10863 01:20:49.492629 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10864 01:20:49.493036
10865 01:20:49.510125 <30>[ 17.067530] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10866 01:20:49.519912 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10867 01:20:49.520231
10868 01:20:49.538335 <30>[ 17.096246] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10869 01:20:49.548444 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10870 01:20:49.548683
10871 01:20:49.566585 <30>[ 17.123964] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10872 01:20:49.576357 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10873 01:20:49.576533
10874 01:20:49.633244 <30>[ 17.191109] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10875 01:20:49.640236 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10876 01:20:49.640851
10877 01:20:49.652897 <30>[ 17.210437] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10878 01:20:49.659851 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10879 01:20:49.660320
10880 01:20:49.681211 <30>[ 17.238639] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10881 01:20:49.687541 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10882 01:20:49.687785
10883 01:20:49.711104 <30>[ 17.262976] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10884 01:20:49.749157 <30>[ 17.307181] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10885 01:20:49.759035 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10886 01:20:49.759153
10887 01:20:49.781899 <30>[ 17.339863] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10888 01:20:49.788566 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10889 01:20:49.788649
10890 01:20:49.813835 <30>[ 17.371796] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10891 01:20:49.826917 Starting [0;1;39mmodprobe@dm_mod.s…[<6>[ 17.384255] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10892 01:20:49.830700 0m - Load Kernel Module dm_mod...
10893 01:20:49.830786
10894 01:20:49.885120 <30>[ 17.443214] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10895 01:20:49.891911 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10896 01:20:49.892002
10897 01:20:49.913439 <30>[ 17.471459] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10898 01:20:49.919705 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10899 01:20:49.922961
10900 01:20:49.945823 <30>[ 17.503906] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10901 01:20:49.952629 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10902 01:20:49.952739
10903 01:20:49.996978 <30>[ 17.555174] systemd[1]: Starting systemd-journald.service - Journal Service...
10904 01:20:50.003749 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10905 01:20:50.003842
10906 01:20:50.023757 <30>[ 17.581871] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10907 01:20:50.030683 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10908 01:20:50.030780
10909 01:20:50.054936 <30>[ 17.609620] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10910 01:20:50.061575 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10911 01:20:50.061681
10912 01:20:50.085339 <30>[ 17.643335] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10913 01:20:50.095343 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10914 01:20:50.095461
10915 01:20:50.133317 <30>[ 17.691550] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10916 01:20:50.140335 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10917 01:20:50.140455
10918 01:20:50.165694 <30>[ 17.724021] systemd[1]: Started systemd-journald.service - Journal Service.
10919 01:20:50.172759 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10920 01:20:50.172874
10921 01:20:50.191426 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10922 01:20:50.191535
10923 01:20:50.209345 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10924 01:20:50.209456
10925 01:20:50.229427 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10926 01:20:50.229557
10927 01:20:50.249887 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10928 01:20:50.249983
10929 01:20:50.271826 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10930 01:20:50.271946
10931 01:20:50.291765 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10932 01:20:50.291854
10933 01:20:50.315980 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10934 01:20:50.316094
10935 01:20:50.339945 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10936 01:20:50.340087
10937 01:20:50.363267 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10938 01:20:50.363378
10939 01:20:50.387116 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10940 01:20:50.387267
10941 01:20:50.406052 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10942 01:20:50.406160
10943 01:20:50.431789 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10944 01:20:50.431921
10945 01:20:50.438294 See 'systemctl status systemd-remount-fs.service' for details.
10946 01:20:50.438371
10947 01:20:50.447893 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10948 01:20:50.447996
10949 01:20:50.471304 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10950 01:20:50.471420
10951 01:20:50.517728 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10952 01:20:50.517949
10953 01:20:50.546662 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10954 01:20:50.546818
10955 01:20:50.557028 <46>[ 18.115283] systemd-journald[182]: Received client request to flush runtime journal.
10956 01:20:50.574863 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10957 01:20:50.574978
10958 01:20:50.638066 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10959 01:20:50.638283
10960 01:20:50.662583 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10961 01:20:50.662748
10962 01:20:50.691864 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10963 01:20:50.692011
10964 01:20:50.710206 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10965 01:20:50.710326
10966 01:20:50.730160 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10967 01:20:50.730259
10968 01:20:50.750121 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10969 01:20:50.750241
10970 01:20:50.770603 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10971 01:20:50.770708
10972 01:20:50.829737 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10973 01:20:50.829865
10974 01:20:50.851761 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10975 01:20:50.851888
10976 01:20:50.869361 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10977 01:20:50.869462
10978 01:20:50.888356 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10979 01:20:50.888461
10980 01:20:50.933686 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10981 01:20:50.933832
10982 01:20:50.958677 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10983 01:20:50.958829
10984 01:20:50.983585 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10985 01:20:50.983702
10986 01:20:51.003903 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10987 01:20:51.003993
10988 01:20:51.037966 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10989 01:20:51.038128
10990 01:20:51.065871 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10991 01:20:51.065982
10992 01:20:51.098855 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10993 01:20:51.098983
10994 01:20:51.127486 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10995 01:20:51.127614
10996 01:20:51.169780 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10997 01:20:51.169899
10998 01:20:51.190433 <5>[ 18.748369] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10999 01:20:51.204740 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11000 01:20:51.204839
11001 01:20:51.225351 <5>[ 18.783392] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11002 01:20:51.232147 <5>[ 18.790938] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11003 01:20:51.242116 <4>[ 18.799413] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11004 01:20:51.248063 <6>[ 18.808362] cfg80211: failed to load regulatory.db
11005 01:20:51.267777 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11006 01:20:51.267908
11007 01:20:51.316947 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11008 01:20:51.317077
11009 01:20:51.337816 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11010 01:20:51.337922
11011 01:20:51.357962 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11012 01:20:51.358050
11013 01:20:51.380811 [[0;32m OK [0m] Reached target [0;1;39mtime<6>[ 18.939124] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11014 01:20:51.390648 -set.target[0m <6>[ 18.947825] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11015 01:20:51.400680 - System Time Se<6>[ 18.957949] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11016 01:20:51.400774 t.
11017 01:20:51.400842
11018 01:20:51.419958 <3>[ 18.977808] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11019 01:20:51.426570 <6>[ 18.978665] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11020 01:20:51.436557 <3>[ 18.986001] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11021 01:20:51.442750 <3>[ 19.001597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11022 01:20:51.455729 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks on<6>[ 19.015951] remoteproc remoteproc0: scp is available
11023 01:20:51.455835 ce a week.
11024 01:20:51.455940
11025 01:20:51.466036 <3>[ 19.020776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11026 01:20:51.468971 <6>[ 19.022135] remoteproc remoteproc0: powering up scp
11027 01:20:51.479453 <3>[ 19.031274] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11028 01:20:51.485586 <6>[ 19.036420] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11029 01:20:51.495669 <3>[ 19.044487] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11030 01:20:51.498727 <6>[ 19.052979] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11031 01:20:51.509030 <3>[ 19.061159] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11032 01:20:51.515373 <4>[ 19.062266] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11033 01:20:51.519117 <6>[ 19.062770] mc: Linux media interface: v0.10
11034 01:20:51.528906 <4>[ 19.084116] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11035 01:20:51.535438 <3>[ 19.086613] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11036 01:20:51.541794 <6>[ 19.089127] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11037 01:20:51.551787 <3>[ 19.094785] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11038 01:20:51.558773 <6>[ 19.114639] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11039 01:20:51.564919 <6>[ 19.124651] pci_bus 0000:00: root bus resource [bus 00-ff]
11040 01:20:51.571942 <6>[ 19.124659] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11041 01:20:51.578680 <3>[ 19.127113] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11042 01:20:51.585320 <3>[ 19.127141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11043 01:20:51.595519 <3>[ 19.127147] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11044 01:20:51.602187 <3>[ 19.131910] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11045 01:20:51.612261 [[0;32m OK [<4>[ 19.132219] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11046 01:20:51.618605 <4>[ 19.132219] Fallback method does not support PEC.
11047 01:20:51.629277 0m] Reached targ<6>[ 19.137528] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11048 01:20:51.636178 et [0;1;39mtime<6>[ 19.137630] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11049 01:20:51.642797 <6>[ 19.138466] usbcore: registered new device driver r8152-cfgselector
11050 01:20:51.649444 rs.target[0m - <6>[ 19.142226] videodev: Linux video capture interface: v2.00
11051 01:20:51.652876 Timer Units.
11052 01:20:51.652954
11053 01:20:51.659899 <3>[ 19.145682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11054 01:20:51.670151 <3>[ 19.149319] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11055 01:20:51.676282 <6>[ 19.153770] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11056 01:20:51.686490 <3>[ 19.161835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11057 01:20:51.690006 <6>[ 19.169979] pci 0000:00:00.0: supports D1 D2
11058 01:20:51.696599 <3>[ 19.184930] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11059 01:20:51.702777 <6>[ 19.191952] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11060 01:20:51.712625 <3>[ 19.195452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11061 01:20:51.722789 <6>[ 19.196239] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11062 01:20:51.729273 <6>[ 19.196251] remoteproc remoteproc0: remote processor scp is now up
11063 01:20:51.736101 <3>[ 19.196357] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11064 01:20:51.742860 <6>[ 19.196394] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11065 01:20:51.752482 <6>[ 19.197311] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11066 01:20:51.759358 <6>[ 19.197388] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11067 01:20:51.766007 <6>[ 19.197413] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11068 01:20:51.773347 <6>[ 19.197429] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11069 01:20:51.780658 <6>[ 19.197443] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11070 01:20:51.784318 <6>[ 19.197546] pci 0000:01:00.0: supports D1 D2
11071 01:20:51.791036 <6>[ 19.197547] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11072 01:20:51.801394 <3>[ 19.203915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11073 01:20:51.808252 <6>[ 19.210710] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11074 01:20:51.814811 <3>[ 19.217713] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11075 01:20:51.824519 <6>[ 19.222838] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11076 01:20:51.834289 <6>[ 19.227024] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11077 01:20:51.844616 <6>[ 19.227489] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11078 01:20:51.851755 <6>[ 19.227882] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11079 01:20:51.862173 <3>[ 19.232131] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11080 01:20:51.869328 <6>[ 19.242083] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11081 01:20:51.879252 <6>[ 19.243319] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11082 01:20:51.885381 <6>[ 19.243356] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11083 01:20:51.892269 <6>[ 19.243374] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11084 01:20:51.899019 <6>[ 19.244828] Bluetooth: Core ver 2.22
11085 01:20:51.902239 <6>[ 19.244949] NET: Registered PF_BLUETOOTH protocol family
11086 01:20:51.908690 <6>[ 19.244952] Bluetooth: HCI device and connection manager initialized
11087 01:20:51.915349 <6>[ 19.244974] Bluetooth: HCI socket layer initialized
11088 01:20:51.918481 <6>[ 19.244993] Bluetooth: L2CAP socket layer initialized
11089 01:20:51.925394 <6>[ 19.245009] Bluetooth: SCO socket layer initialized
11090 01:20:51.931587 <6>[ 19.257403] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11091 01:20:51.941395 <6>[ 19.264059] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11092 01:20:51.945151 <6>[ 19.264073] pci 0000:00:00.0: PCI bridge to [bus 01]
11093 01:20:51.955011 <6>[ 19.274638] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11094 01:20:51.965003 <4>[ 19.274638] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11095 01:20:51.971575 <4>[ 19.274649] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11096 01:20:51.977911 <6>[ 19.279883] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11097 01:20:51.984578 <6>[ 19.280110] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11098 01:20:51.995082 <6>[ 19.296969] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11099 01:20:51.998074 <6>[ 19.304741] usbcore: registered new interface driver btusb
11100 01:20:52.005367 <6>[ 19.304788] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11101 01:20:52.012122 <6>[ 19.304963] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11102 01:20:52.021789 <4>[ 19.305642] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11103 01:20:52.028224 <3>[ 19.305683] Bluetooth: hci0: Failed to load firmware file (-2)
11104 01:20:52.031657 <3>[ 19.305690] Bluetooth: hci0: Failed to set up firmware (-2)
11105 01:20:52.045141 <4>[ 19.305698] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11106 01:20:52.055421 <6>[ 19.313433] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11107 01:20:52.062519 <6>[ 19.320058] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11108 01:20:52.068931 <6>[ 19.325522] usbcore: registered new interface driver uvcvideo
11109 01:20:52.072341 <6>[ 19.342730] r8152 2-1.3:1.0 eth0: v1.12.13
11110 01:20:52.082546 <3>[ 19.349668] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11111 01:20:52.089346 <6>[ 19.352712] usbcore: registered new interface driver r8152
11112 01:20:52.096136 <3>[ 19.364862] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11113 01:20:52.102980 <6>[ 19.381818] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11114 01:20:52.109816 <6>[ 19.399933] usbcore: registered new interface driver cdc_ether
11115 01:20:52.116427 <6>[ 19.409852] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11116 01:20:52.124039 <3>[ 19.426573] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11117 01:20:52.130293 <6>[ 19.427818] usbcore: registered new interface driver r8153_ecm
11118 01:20:52.141177 <3>[ 19.436204] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11119 01:20:52.144049 <6>[ 19.448029] mt7921e 0000:01:00.0: ASIC revision: 79610010
11120 01:20:52.150844 <6>[ 19.462911] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
11121 01:20:52.161414 <6>[ 19.557746] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11122 01:20:52.161496 <6>[ 19.557746]
11123 01:20:52.171188 <3>[ 19.578180] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11124 01:20:52.180911 <3>[ 19.600096] power_supply sbs-5-000b: driver failed to report `constant_charge_current_max' property: -6
11125 01:20:52.187455 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11126 01:20:52.187645
11127 01:20:52.204615 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11128 01:20:52.204744
11129 01:20:52.225186 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11130 01:20:52.225290
11131 01:20:52.274358 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11132 01:20:52.274488
11133 01:20:52.300998 <6>[ 19.859111] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11134 01:20:52.307446 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11135 01:20:52.307550
11136 01:20:52.334909 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11137 01:20:52.335067
11138 01:20:52.354394 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11139 01:20:52.354482
11140 01:20:52.379677 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11141 01:20:52.379793
11142 01:20:52.446199 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11143 01:20:52.446317
11144 01:20:52.468741 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11145 01:20:52.468840
11146 01:20:52.485417 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11147 01:20:52.485506
11148 01:20:52.505459 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11149 01:20:52.505594
11150 01:20:52.558681 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11151 01:20:52.558823
11152 01:20:52.579768 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11153 01:20:52.579857
11154 01:20:52.597876 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11155 01:20:52.597981
11156 01:20:52.613485 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11157 01:20:52.613609
11158 01:20:52.633654 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11159 01:20:52.633746
11160 01:20:52.694619 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11161 01:20:52.694792
11162 01:20:52.719582 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11163 01:20:52.719674
11164 01:20:52.743852 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11165 01:20:52.744049
11166 01:20:52.807306 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11167 01:20:52.807431
11168 01:20:52.826788 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11169 01:20:52.826892
11170 01:20:52.853943 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11171 01:20:52.854047
11172 01:20:52.894155
11173 01:20:52.894254
11174 01:20:52.897455 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11175 01:20:52.897591
11176 01:20:52.900720 debian-bookworm-arm64 login: root (automatic login)
11177 01:20:52.900801
11178 01:20:52.900864
11179 01:20:52.913040 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024 aarch64
11180 01:20:52.913128
11181 01:20:52.919671 The programs included with the Debian GNU/Linux system are free software;
11182 01:20:52.926220 the exact distribution terms for each program are described in the
11183 01:20:52.929533 individual files in /usr/share/doc/*/copyright.
11184 01:20:52.929642
11185 01:20:52.936095 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11186 01:20:52.939068 permitted by applicable law.
11187 01:20:52.939605 Matched prompt #10: / #
11189 01:20:52.939937 Setting prompt string to ['/ #']
11190 01:20:52.940077 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11192 01:20:52.940388 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11193 01:20:52.940522 start: 2.2.6 expect-shell-connection (timeout 00:02:49) [common]
11194 01:20:52.940636 Setting prompt string to ['/ #']
11195 01:20:52.940731 Forcing a shell prompt, looking for ['/ #']
11197 01:20:52.991003 / #
11198 01:20:52.991140 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11199 01:20:52.991226 Waiting using forced prompt support (timeout 00:02:30)
11200 01:20:52.996257
11201 01:20:52.996541 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11202 01:20:52.996630 start: 2.2.7 export-device-env (timeout 00:02:49) [common]
11203 01:20:52.996719 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11204 01:20:52.996818 end: 2.2 depthcharge-retry (duration 00:02:11) [common]
11205 01:20:52.996903 end: 2 depthcharge-action (duration 00:02:11) [common]
11206 01:20:52.996995 start: 3 lava-test-retry (timeout 00:05:00) [common]
11207 01:20:52.997082 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11208 01:20:52.997158 Using namespace: common
11210 01:20:53.097469 / # #
11211 01:20:53.097733 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11212 01:20:53.103410 #
11213 01:20:53.103824 Using /lava-13468751
11215 01:20:53.204468 / # export SHELL=/bin/sh
11216 01:20:53.204644 <6>[ 20.722986] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11217 01:20:53.209539 export SHELL=/bin/sh
11219 01:20:53.310099 / # . /lava-13468751/environment
11220 01:20:53.315403 . /lava-13468751/environment
11222 01:20:53.416064 / # /lava-13468751/bin/lava-test-runner /lava-13468751/0
11223 01:20:53.416245 Test shell timeout: 10s (minimum of the action and connection timeout)
11224 01:20:53.416755 <6>[ 20.900716] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11225 01:20:53.421469 /lava-13468751/bin/lava-test-runner /lava-13468751/0
11226 01:20:53.461772 + export TESTRUN_ID=0_cros-ec
11227 01:20:53.462057 +<8>[ 21.006666] <LAVA_SIGNAL_STARTRUN 0_cros-ec 13468751_1.5.2.3.1>
11228 01:20:53.462274 cd /lava-13468751/0/tests/0_cros-ec
11229 01:20:53.462465 + cat uuid
11230 01:20:53.462667 + UUID=13468751_1.5.2.3.1
11231 01:20:53.462933 + set +x
11232 01:20:53.463185 + python3 -m cros.runners.lava_runner -v
11233 01:20:53.463680 Received signal: <STARTRUN> 0_cros-ec 13468751_1.5.2.3.1
11234 01:20:53.463951 Starting test lava.0_cros-ec (13468751_1.5.2.3.1)
11235 01:20:53.464268 Skipping test definition patterns.
11236 01:20:53.876673 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11237 01:20:53.883101 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11238 01:20:53.883197
11239 01:20:53.889188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11240 01:20:53.889450 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11242 01:20:53.899630 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11243 01:20:53.909322 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11244 01:20:53.909442
11245 01:20:53.919158 <LAVA_SIGNAL_TESTC<6>[ 21.477088] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11246 01:20:53.925586 ASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11247 01:20:53.925951 Received signal: <TESTC<6>[> 21.477088] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
ASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11248 01:20:53.932582 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11249 01:20:53.939063 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11250 01:20:53.939703
11251 01:20:53.945817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11252 01:20:53.946694 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11254 01:20:53.952614 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11255 01:20:53.959023 Checks the standard ABI for the main Embedded Controller. ... ok
11256 01:20:53.959478
11257 01:20:53.962824 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11259 01:20:53.965951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11260 01:20:53.972401 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11261 01:20:53.975923 Checks the main Embedded controller character device. ... ok
11262 01:20:53.976600
11263 01:20:53.982296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11264 01:20:53.983070 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11266 01:20:53.988775 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11267 01:20:53.995487 Checks basic comunication with the main Embedded controller. ... ok
11268 01:20:53.996130
11269 01:20:54.001902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11270 01:20:54.002829 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11272 01:20:54.008594 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11273 01:20:54.015460 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11274 01:20:54.016019
11275 01:20:54.021930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11276 01:20:54.022892 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11278 01:20:54.028477 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11279 01:20:54.038091 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11280 01:20:54.038757
11281 01:20:54.041574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11282 01:20:54.042332 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11284 01:20:54.048539 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11285 01:20:54.058088 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11286 01:20:54.058809
11287 01:20:54.061547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11288 01:20:54.062364 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11290 01:20:54.068064 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11291 01:20:54.077834 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11292 01:20:54.078384
11293 01:20:54.081684 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11295 01:20:54.084946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11296 01:20:54.090976 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11297 01:20:54.097948 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11298 01:20:54.098586
11299 01:20:54.104223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11300 01:20:54.105269 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11302 01:20:54.111118 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11303 01:20:54.117408 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11304 01:20:54.117538
11305 01:20:54.123954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11306 01:20:54.124231 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11308 01:20:54.130569 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11309 01:20:54.137032 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11310 01:20:54.140837
11311 01:20:54.143788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11312 01:20:54.144036 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11314 01:20:54.154111 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11315 01:20:54.163748 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11316 01:20:54.163827
11317 01:20:54.169983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11318 01:20:54.170230 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11320 01:20:54.177183 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11321 01:20:54.184070 Check the cros battery ABI. ... skipped 'No BAT found'
11322 01:20:54.184657
11323 01:20:54.187033 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11325 01:20:54.190213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11326 01:20:54.197027 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11327 01:20:54.203294 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11328 01:20:54.203403
11329 01:20:54.209858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11330 01:20:54.210108 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11332 01:20:54.219519 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11333 01:20:54.226274 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11334 01:20:54.226355
11335 01:20:54.232892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11336 01:20:54.233133 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11338 01:20:54.239371 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11339 01:20:54.246120 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11340 01:20:54.246199
11341 01:20:54.252801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11342 01:20:54.252884
11343 01:20:54.253138 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11345 01:20:54.259605 ----------<8>[ 21.820182] <LAVA_SIGNAL_ENDRUN 0_cros-ec 13468751_1.5.2.3.1>
11346 01:20:54.259876 Received signal: <ENDRUN> 0_cros-ec 13468751_1.5.2.3.1
11347 01:20:54.259978 Ending use of test pattern.
11348 01:20:54.260068 Ending test lava.0_cros-ec (13468751_1.5.2.3.1), duration 0.80
11350 01:20:54.266088 ------------------------------------------------------------
11351 01:20:54.269099 Ran 18 tests in 0.346s
11352 01:20:54.269256
11353 01:20:54.269399 OK (skipped=15)
11354 01:20:54.269545 + set +x
11355 01:20:54.272328 <LAVA_TEST_RUNNER EXIT>
11356 01:20:54.272670 ok: lava_test_shell seems to have completed
11357 01:20:54.273045 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11358 01:20:54.273198 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11359 01:20:54.273335 end: 3 lava-test-retry (duration 00:00:01) [common]
11360 01:20:54.273471 start: 4 finalize (timeout 00:07:25) [common]
11361 01:20:54.273629 start: 4.1 power-off (timeout 00:00:30) [common]
11362 01:20:54.273880 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11363 01:20:54.362014 >> Command sent successfully.
11364 01:20:54.374003 Returned 0 in 0 seconds
11365 01:20:54.475080 end: 4.1 power-off (duration 00:00:00) [common]
11367 01:20:54.475680 start: 4.2 read-feedback (timeout 00:07:24) [common]
11368 01:20:54.476152 Listened to connection for namespace 'common' for up to 1s
11369 01:20:55.477126 Finalising connection for namespace 'common'
11370 01:20:55.477329 Disconnecting from shell: Finalise
11371 01:20:55.477408 / #
11372 01:20:55.577665 end: 4.2 read-feedback (duration 00:00:01) [common]
11373 01:20:55.577828 end: 4 finalize (duration 00:00:01) [common]
11374 01:20:55.577945 Cleaning after the job
11375 01:20:55.578040 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/ramdisk
11376 01:20:55.584218 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/kernel
11377 01:20:55.591947 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/dtb
11378 01:20:55.592120 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468751/tftp-deploy-efs9j2v9/modules
11379 01:20:55.597915 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468751
11380 01:20:55.686899 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468751
11381 01:20:55.687084 Job finished correctly