Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
1 01:14:37.778883 lava-dispatcher, installed at version: 2024.01
2 01:14:37.779122 start: 0 validate
3 01:14:37.779309 Start time: 2024-04-23 01:14:37.779300+00:00 (UTC)
4 01:14:37.779479 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:14:37.779672 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:14:38.035237 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:14:38.035405 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:14:38.290438 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:14:38.291060 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:14:38.548474 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:14:38.549186 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:14:39.054312 validate duration: 1.28
14 01:14:39.054585 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:14:39.054685 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:14:39.054774 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:14:39.054887 Not decompressing ramdisk as can be used compressed.
18 01:14:39.054972 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 01:14:39.055036 saving as /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/ramdisk/rootfs.cpio.gz
20 01:14:39.055099 total size: 47897469 (45 MB)
21 01:14:39.056125 progress 0 % (0 MB)
22 01:14:39.068638 progress 5 % (2 MB)
23 01:14:39.080761 progress 10 % (4 MB)
24 01:14:39.092889 progress 15 % (6 MB)
25 01:14:39.105018 progress 20 % (9 MB)
26 01:14:39.117288 progress 25 % (11 MB)
27 01:14:39.129799 progress 30 % (13 MB)
28 01:14:39.142440 progress 35 % (16 MB)
29 01:14:39.154558 progress 40 % (18 MB)
30 01:14:39.167266 progress 45 % (20 MB)
31 01:14:39.179408 progress 50 % (22 MB)
32 01:14:39.191791 progress 55 % (25 MB)
33 01:14:39.204288 progress 60 % (27 MB)
34 01:14:39.216437 progress 65 % (29 MB)
35 01:14:39.228644 progress 70 % (32 MB)
36 01:14:39.241233 progress 75 % (34 MB)
37 01:14:39.253378 progress 80 % (36 MB)
38 01:14:39.265571 progress 85 % (38 MB)
39 01:14:39.277740 progress 90 % (41 MB)
40 01:14:39.289905 progress 95 % (43 MB)
41 01:14:39.301967 progress 100 % (45 MB)
42 01:14:39.302181 45 MB downloaded in 0.25 s (184.87 MB/s)
43 01:14:39.302336 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:14:39.302575 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:14:39.302662 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:14:39.302746 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:14:39.302878 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:14:39.302951 saving as /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/kernel/Image
50 01:14:39.303011 total size: 54352384 (51 MB)
51 01:14:39.303072 No compression specified
52 01:14:39.304155 progress 0 % (0 MB)
53 01:14:39.317725 progress 5 % (2 MB)
54 01:14:39.334083 progress 10 % (5 MB)
55 01:14:39.350149 progress 15 % (7 MB)
56 01:14:39.364351 progress 20 % (10 MB)
57 01:14:39.378610 progress 25 % (12 MB)
58 01:14:39.392964 progress 30 % (15 MB)
59 01:14:39.407240 progress 35 % (18 MB)
60 01:14:39.420991 progress 40 % (20 MB)
61 01:14:39.434838 progress 45 % (23 MB)
62 01:14:39.449457 progress 50 % (25 MB)
63 01:14:39.464255 progress 55 % (28 MB)
64 01:14:39.480969 progress 60 % (31 MB)
65 01:14:39.496894 progress 65 % (33 MB)
66 01:14:39.512460 progress 70 % (36 MB)
67 01:14:39.528001 progress 75 % (38 MB)
68 01:14:39.543039 progress 80 % (41 MB)
69 01:14:39.557196 progress 85 % (44 MB)
70 01:14:39.571542 progress 90 % (46 MB)
71 01:14:39.585983 progress 95 % (49 MB)
72 01:14:39.600551 progress 100 % (51 MB)
73 01:14:39.600797 51 MB downloaded in 0.30 s (174.07 MB/s)
74 01:14:39.600950 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:14:39.601189 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:14:39.601276 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:14:39.601366 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:14:39.601503 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:14:39.601585 saving as /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/dtb/mt8192-asurada-spherion-r0.dtb
81 01:14:39.601648 total size: 47230 (0 MB)
82 01:14:39.601709 No compression specified
83 01:14:39.602833 progress 69 % (0 MB)
84 01:14:39.603112 progress 100 % (0 MB)
85 01:14:39.603296 0 MB downloaded in 0.00 s (27.37 MB/s)
86 01:14:39.603422 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:14:39.603648 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:14:39.603732 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:14:39.603815 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:14:39.603930 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:14:39.603998 saving as /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/modules/modules.tar
93 01:14:39.604059 total size: 8638160 (8 MB)
94 01:14:39.604121 Using unxz to decompress xz
95 01:14:39.608182 progress 0 % (0 MB)
96 01:14:39.627995 progress 5 % (0 MB)
97 01:14:39.652885 progress 10 % (0 MB)
98 01:14:39.677637 progress 15 % (1 MB)
99 01:14:39.703149 progress 20 % (1 MB)
100 01:14:39.730974 progress 25 % (2 MB)
101 01:14:39.766390 progress 30 % (2 MB)
102 01:14:39.793012 progress 35 % (2 MB)
103 01:14:39.819368 progress 40 % (3 MB)
104 01:14:39.843637 progress 45 % (3 MB)
105 01:14:39.869828 progress 50 % (4 MB)
106 01:14:39.896736 progress 55 % (4 MB)
107 01:14:39.927218 progress 60 % (4 MB)
108 01:14:39.952459 progress 65 % (5 MB)
109 01:14:39.980704 progress 70 % (5 MB)
110 01:14:40.007772 progress 75 % (6 MB)
111 01:14:40.034521 progress 80 % (6 MB)
112 01:14:40.064297 progress 85 % (7 MB)
113 01:14:40.091796 progress 90 % (7 MB)
114 01:14:40.121851 progress 95 % (7 MB)
115 01:14:40.150521 progress 100 % (8 MB)
116 01:14:40.156668 8 MB downloaded in 0.55 s (14.91 MB/s)
117 01:14:40.156922 end: 1.4.1 http-download (duration 00:00:01) [common]
119 01:14:40.157184 end: 1.4 download-retry (duration 00:00:01) [common]
120 01:14:40.157275 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:14:40.157368 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:14:40.157448 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:14:40.157566 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:14:40.157804 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k
125 01:14:40.157939 makedir: /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin
126 01:14:40.158041 makedir: /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/tests
127 01:14:40.158138 makedir: /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/results
128 01:14:40.158251 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-add-keys
129 01:14:40.158396 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-add-sources
130 01:14:40.158525 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-background-process-start
131 01:14:40.158658 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-background-process-stop
132 01:14:40.158782 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-common-functions
133 01:14:40.158906 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-echo-ipv4
134 01:14:40.159029 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-install-packages
135 01:14:40.159154 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-installed-packages
136 01:14:40.159276 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-os-build
137 01:14:40.159398 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-probe-channel
138 01:14:40.159519 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-probe-ip
139 01:14:40.159641 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-target-ip
140 01:14:40.159763 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-target-mac
141 01:14:40.159884 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-target-storage
142 01:14:40.160010 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-test-case
143 01:14:40.160134 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-test-event
144 01:14:40.160255 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-test-feedback
145 01:14:40.160376 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-test-raise
146 01:14:40.160503 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-test-reference
147 01:14:40.160624 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-test-runner
148 01:14:40.160746 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-test-set
149 01:14:40.160870 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-test-shell
150 01:14:40.160997 Updating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-install-packages (oe)
151 01:14:40.161145 Updating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/bin/lava-installed-packages (oe)
152 01:14:40.161337 Creating /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/environment
153 01:14:40.161476 LAVA metadata
154 01:14:40.161589 - LAVA_JOB_ID=13468726
155 01:14:40.161655 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:14:40.161760 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:14:40.161828 skipped lava-vland-overlay
158 01:14:40.161900 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:14:40.161979 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:14:40.162041 skipped lava-multinode-overlay
161 01:14:40.162115 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:14:40.162199 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:14:40.162276 Loading test definitions
164 01:14:40.162368 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:14:40.162450 Using /lava-13468726 at stage 0
166 01:14:40.162773 uuid=13468726_1.5.2.3.1 testdef=None
167 01:14:40.162862 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:14:40.162944 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:14:40.163461 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:14:40.163680 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:14:40.164294 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:14:40.164523 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:14:40.165130 runner path: /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/0/tests/0_igt-kms-mediatek test_uuid 13468726_1.5.2.3.1
176 01:14:40.165311 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:14:40.165525 Creating lava-test-runner.conf files
179 01:14:40.165603 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468726/lava-overlay-jcvfk07k/lava-13468726/0 for stage 0
180 01:14:40.165725 - 0_igt-kms-mediatek
181 01:14:40.165820 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:14:40.165904 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 01:14:40.173374 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:14:40.173484 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 01:14:40.173597 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:14:40.173682 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:14:40.173770 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 01:14:41.935422 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 01:14:41.935803 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 01:14:41.935914 extracting modules file /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468726/extract-overlay-ramdisk-0sl11mjs/ramdisk
191 01:14:42.173991 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:14:42.174159 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 01:14:42.174256 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468726/compress-overlay-09j79ohu/overlay-1.5.2.4.tar.gz to ramdisk
194 01:14:42.174327 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468726/compress-overlay-09j79ohu/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468726/extract-overlay-ramdisk-0sl11mjs/ramdisk
195 01:14:42.181840 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:14:42.182018 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 01:14:42.182172 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:14:42.182320 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 01:14:42.182457 Building ramdisk /var/lib/lava/dispatcher/tmp/13468726/extract-overlay-ramdisk-0sl11mjs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468726/extract-overlay-ramdisk-0sl11mjs/ramdisk
200 01:14:43.421907 >> 466207 blocks
201 01:14:49.577755 rename /var/lib/lava/dispatcher/tmp/13468726/extract-overlay-ramdisk-0sl11mjs/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/ramdisk/ramdisk.cpio.gz
202 01:14:49.578192 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 01:14:49.578312 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 01:14:49.578416 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 01:14:49.578525 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/kernel/Image'
206 01:15:02.357887 Returned 0 in 12 seconds
207 01:15:02.458923 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/kernel/image.itb
208 01:15:03.324295 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:15:03.324665 output: Created: Tue Apr 23 02:15:03 2024
210 01:15:03.324740 output: Image 0 (kernel-1)
211 01:15:03.324803 output: Description:
212 01:15:03.324864 output: Created: Tue Apr 23 02:15:03 2024
213 01:15:03.324925 output: Type: Kernel Image
214 01:15:03.324983 output: Compression: lzma compressed
215 01:15:03.325040 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
216 01:15:03.325096 output: Architecture: AArch64
217 01:15:03.325152 output: OS: Linux
218 01:15:03.325209 output: Load Address: 0x00000000
219 01:15:03.325266 output: Entry Point: 0x00000000
220 01:15:03.325323 output: Hash algo: crc32
221 01:15:03.325380 output: Hash value: 1126c3f9
222 01:15:03.325438 output: Image 1 (fdt-1)
223 01:15:03.325497 output: Description: mt8192-asurada-spherion-r0
224 01:15:03.325615 output: Created: Tue Apr 23 02:15:03 2024
225 01:15:03.325669 output: Type: Flat Device Tree
226 01:15:03.325722 output: Compression: uncompressed
227 01:15:03.325775 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 01:15:03.325827 output: Architecture: AArch64
229 01:15:03.325879 output: Hash algo: crc32
230 01:15:03.326012 output: Hash value: 4bf0d1ac
231 01:15:03.326066 output: Image 2 (ramdisk-1)
232 01:15:03.326119 output: Description: unavailable
233 01:15:03.326172 output: Created: Tue Apr 23 02:15:03 2024
234 01:15:03.326225 output: Type: RAMDisk Image
235 01:15:03.326277 output: Compression: Unknown Compression
236 01:15:03.326330 output: Data Size: 61038434 Bytes = 59607.85 KiB = 58.21 MiB
237 01:15:03.326383 output: Architecture: AArch64
238 01:15:03.326435 output: OS: Linux
239 01:15:03.326488 output: Load Address: unavailable
240 01:15:03.326540 output: Entry Point: unavailable
241 01:15:03.326623 output: Hash algo: crc32
242 01:15:03.326675 output: Hash value: 58246b5c
243 01:15:03.326727 output: Default Configuration: 'conf-1'
244 01:15:03.326780 output: Configuration 0 (conf-1)
245 01:15:03.326832 output: Description: mt8192-asurada-spherion-r0
246 01:15:03.326884 output: Kernel: kernel-1
247 01:15:03.326935 output: Init Ramdisk: ramdisk-1
248 01:15:03.326987 output: FDT: fdt-1
249 01:15:03.327039 output: Loadables: kernel-1
250 01:15:03.327090 output:
251 01:15:03.327294 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 01:15:03.327390 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 01:15:03.327490 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 01:15:03.327582 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 01:15:03.327662 No LXC device requested
256 01:15:03.327742 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:15:03.327826 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 01:15:03.327901 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:15:03.327970 Checking files for TFTP limit of 4294967296 bytes.
260 01:15:03.328462 end: 1 tftp-deploy (duration 00:00:24) [common]
261 01:15:03.328562 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:15:03.328656 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:15:03.328783 substitutions:
264 01:15:03.328848 - {DTB}: 13468726/tftp-deploy-o740h9ux/dtb/mt8192-asurada-spherion-r0.dtb
265 01:15:03.328913 - {INITRD}: 13468726/tftp-deploy-o740h9ux/ramdisk/ramdisk.cpio.gz
266 01:15:03.328972 - {KERNEL}: 13468726/tftp-deploy-o740h9ux/kernel/Image
267 01:15:03.329029 - {LAVA_MAC}: None
268 01:15:03.329084 - {PRESEED_CONFIG}: None
269 01:15:03.329138 - {PRESEED_LOCAL}: None
270 01:15:03.329192 - {RAMDISK}: 13468726/tftp-deploy-o740h9ux/ramdisk/ramdisk.cpio.gz
271 01:15:03.329247 - {ROOT_PART}: None
272 01:15:03.329300 - {ROOT}: None
273 01:15:03.329353 - {SERVER_IP}: 192.168.201.1
274 01:15:03.329406 - {TEE}: None
275 01:15:03.329459 Parsed boot commands:
276 01:15:03.329517 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:15:03.329724 Parsed boot commands: tftpboot 192.168.201.1 13468726/tftp-deploy-o740h9ux/kernel/image.itb 13468726/tftp-deploy-o740h9ux/kernel/cmdline
278 01:15:03.329812 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:15:03.329949 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:15:03.330058 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:15:03.330143 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:15:03.330214 Not connected, no need to disconnect.
283 01:15:03.330285 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:15:03.330362 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:15:03.330428 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 01:15:03.334319 Setting prompt string to ['lava-test: # ']
287 01:15:03.334666 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:15:03.334772 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:15:03.334869 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:15:03.335011 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:15:03.335210 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 01:15:08.485172 >> Command sent successfully.
293 01:15:08.495311 Returned 0 in 5 seconds
294 01:15:08.596488 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 01:15:08.597883 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 01:15:08.598367 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 01:15:08.598816 Setting prompt string to 'Starting depthcharge on Spherion...'
299 01:15:08.599148 Changing prompt to 'Starting depthcharge on Spherion...'
300 01:15:08.599476 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 01:15:08.600672 [Enter `^Ec?' for help]
302 01:15:08.760381
303 01:15:08.760919
304 01:15:08.761276 F0: 102B 0000
305 01:15:08.761660
306 01:15:08.762008 F3: 1001 0000 [0200]
307 01:15:08.763621
308 01:15:08.764130 F3: 1001 0000
309 01:15:08.764602
310 01:15:08.764929 F7: 102D 0000
311 01:15:08.765238
312 01:15:08.767312 F1: 0000 0000
313 01:15:08.767733
314 01:15:08.768069 V0: 0000 0000 [0001]
315 01:15:08.768395
316 01:15:08.770503 00: 0007 8000
317 01:15:08.770943
318 01:15:08.771280 01: 0000 0000
319 01:15:08.771599
320 01:15:08.773900 BP: 0C00 0209 [0000]
321 01:15:08.774320
322 01:15:08.774655 G0: 1182 0000
323 01:15:08.774969
324 01:15:08.777082 EC: 0000 0021 [4000]
325 01:15:08.777499
326 01:15:08.777855 S7: 0000 0000 [0000]
327 01:15:08.778164
328 01:15:08.781216 CC: 0000 0000 [0001]
329 01:15:08.781684
330 01:15:08.782030 T0: 0000 0040 [010F]
331 01:15:08.782351
332 01:15:08.782659 Jump to BL
333 01:15:08.782959
334 01:15:08.807293
335 01:15:08.807817
336 01:15:08.808155
337 01:15:08.814103 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 01:15:08.817777 ARM64: Exception handlers installed.
339 01:15:08.821116 ARM64: Testing exception
340 01:15:08.824422 ARM64: Done test exception
341 01:15:08.831227 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 01:15:08.842227 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 01:15:08.849108 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 01:15:08.858766 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 01:15:08.865023 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 01:15:08.875121 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 01:15:08.885503 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 01:15:08.892666 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 01:15:08.910207 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 01:15:08.913543 WDT: Last reset was cold boot
351 01:15:08.916696 SPI1(PAD0) initialized at 2873684 Hz
352 01:15:08.920287 SPI5(PAD0) initialized at 992727 Hz
353 01:15:08.923836 VBOOT: Loading verstage.
354 01:15:08.930432 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 01:15:08.933473 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 01:15:08.936588 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 01:15:08.940181 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 01:15:08.948297 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 01:15:08.954529 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 01:15:08.965644 read SPI 0x96554 0xa1eb: 4593 us, 9024 KB/s, 72.192 Mbps
361 01:15:08.966216
362 01:15:08.966591
363 01:15:08.975323 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 01:15:08.978568 ARM64: Exception handlers installed.
365 01:15:08.981842 ARM64: Testing exception
366 01:15:08.982415 ARM64: Done test exception
367 01:15:08.988909 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 01:15:08.992182 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 01:15:09.006452 Probing TPM: . done!
370 01:15:09.007030 TPM ready after 0 ms
371 01:15:09.013207 Connected to device vid:did:rid of 1ae0:0028:00
372 01:15:09.020184 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 01:15:09.060388 Initialized TPM device CR50 revision 0
374 01:15:09.071875 tlcl_send_startup: Startup return code is 0
375 01:15:09.072413 TPM: setup succeeded
376 01:15:09.083397 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 01:15:09.092108 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 01:15:09.104851 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 01:15:09.112604 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 01:15:09.115611 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 01:15:09.121564 in-header: 03 07 00 00 08 00 00 00
382 01:15:09.125291 in-data: aa e4 47 04 13 02 00 00
383 01:15:09.129239 Chrome EC: UHEPI supported
384 01:15:09.135654 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 01:15:09.139405 in-header: 03 9d 00 00 08 00 00 00
386 01:15:09.143191 in-data: 10 20 20 08 00 00 00 00
387 01:15:09.143616 Phase 1
388 01:15:09.146442 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 01:15:09.154098 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 01:15:09.161731 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 01:15:09.162267 Recovery requested (1009000e)
392 01:15:09.170167 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 01:15:09.175773 tlcl_extend: response is 0
394 01:15:09.183652 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 01:15:09.189588 tlcl_extend: response is 0
396 01:15:09.196130 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 01:15:09.217294 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
398 01:15:09.224832 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 01:15:09.225364
400 01:15:09.225741
401 01:15:09.231937 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 01:15:09.235385 ARM64: Exception handlers installed.
403 01:15:09.239310 ARM64: Testing exception
404 01:15:09.239741 ARM64: Done test exception
405 01:15:09.261613 pmic_efuse_setting: Set efuses in 11 msecs
406 01:15:09.265623 pmwrap_interface_init: Select PMIF_VLD_RDY
407 01:15:09.269353 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 01:15:09.276507 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 01:15:09.280418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 01:15:09.284588 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 01:15:09.292454 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 01:15:09.296026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 01:15:09.299802 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 01:15:09.303081 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 01:15:09.309883 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 01:15:09.313231 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 01:15:09.320157 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 01:15:09.323002 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 01:15:09.326441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 01:15:09.333555 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 01:15:09.340004 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 01:15:09.347187 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 01:15:09.349869 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 01:15:09.356871 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 01:15:09.363665 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 01:15:09.368095 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 01:15:09.375185 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 01:15:09.378780 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 01:15:09.385377 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 01:15:09.389647 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 01:15:09.396952 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 01:15:09.399575 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 01:15:09.406953 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 01:15:09.410876 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 01:15:09.414309 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 01:15:09.421181 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 01:15:09.424724 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 01:15:09.431818 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 01:15:09.435725 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 01:15:09.439098 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 01:15:09.446611 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 01:15:09.450566 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 01:15:09.456828 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 01:15:09.460620 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 01:15:09.463747 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 01:15:09.470328 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 01:15:09.473622 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 01:15:09.476931 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 01:15:09.483474 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 01:15:09.486947 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 01:15:09.490081 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 01:15:09.497485 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 01:15:09.501001 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 01:15:09.503569 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 01:15:09.507495 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 01:15:09.514014 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 01:15:09.516760 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 01:15:09.523590 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 01:15:09.533736 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 01:15:09.536501 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 01:15:09.547075 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 01:15:09.553287 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 01:15:09.560818 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 01:15:09.563667 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 01:15:09.566898 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 01:15:09.574400 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x15
467 01:15:09.581048 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 01:15:09.584688 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 01:15:09.590698 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 01:15:09.599079 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 01:15:09.602445 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 01:15:09.608928 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 01:15:09.612185 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
474 01:15:09.615254 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 01:15:09.618515 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
476 01:15:09.622038 ADC[4]: Raw value=897780 ID=7
477 01:15:09.625824 ADC[3]: Raw value=213440 ID=1
478 01:15:09.626297 RAM Code: 0x71
479 01:15:09.632706 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 01:15:09.636171 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 01:15:09.646290 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 01:15:09.653582 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 01:15:09.656221 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 01:15:09.659795 in-header: 03 07 00 00 08 00 00 00
485 01:15:09.663271 in-data: aa e4 47 04 13 02 00 00
486 01:15:09.666729 Chrome EC: UHEPI supported
487 01:15:09.670508 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 01:15:09.675112 in-header: 03 d5 00 00 08 00 00 00
489 01:15:09.678663 in-data: 98 20 60 08 00 00 00 00
490 01:15:09.682327 MRC: failed to locate region type 0.
491 01:15:09.688716 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 01:15:09.692408 DRAM-K: Running full calibration
493 01:15:09.699520 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 01:15:09.700048 header.status = 0x0
495 01:15:09.702670 header.version = 0x6 (expected: 0x6)
496 01:15:09.706248 header.size = 0xd00 (expected: 0xd00)
497 01:15:09.709313 header.flags = 0x0
498 01:15:09.715996 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 01:15:09.732136 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
500 01:15:09.738578 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 01:15:09.741836 dram_init: ddr_geometry: 2
502 01:15:09.744981 [EMI] MDL number = 2
503 01:15:09.745407 [EMI] Get MDL freq = 0
504 01:15:09.748596 dram_init: ddr_type: 0
505 01:15:09.749021 is_discrete_lpddr4: 1
506 01:15:09.752003 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 01:15:09.752428
508 01:15:09.752763
509 01:15:09.754989 [Bian_co] ETT version 0.0.0.1
510 01:15:09.762348 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 01:15:09.762883
512 01:15:09.764923 dramc_set_vcore_voltage set vcore to 650000
513 01:15:09.769314 Read voltage for 800, 4
514 01:15:09.769881 Vio18 = 0
515 01:15:09.770223 Vcore = 650000
516 01:15:09.770541 Vdram = 0
517 01:15:09.771910 Vddq = 0
518 01:15:09.772334 Vmddr = 0
519 01:15:09.775259 dram_init: config_dvfs: 1
520 01:15:09.778904 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 01:15:09.785672 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 01:15:09.788531 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 01:15:09.792141 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 01:15:09.795669 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
525 01:15:09.798520 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
526 01:15:09.802142 MEM_TYPE=3, freq_sel=18
527 01:15:09.805140 sv_algorithm_assistance_LP4_1600
528 01:15:09.808880 ============ PULL DRAM RESETB DOWN ============
529 01:15:09.811636 ========== PULL DRAM RESETB DOWN end =========
530 01:15:09.818263 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 01:15:09.821788 ===================================
532 01:15:09.825462 LPDDR4 DRAM CONFIGURATION
533 01:15:09.828801 ===================================
534 01:15:09.829340 EX_ROW_EN[0] = 0x0
535 01:15:09.832188 EX_ROW_EN[1] = 0x0
536 01:15:09.832614 LP4Y_EN = 0x0
537 01:15:09.835400 WORK_FSP = 0x0
538 01:15:09.835957 WL = 0x2
539 01:15:09.838319 RL = 0x2
540 01:15:09.838786 BL = 0x2
541 01:15:09.841843 RPST = 0x0
542 01:15:09.842284 RD_PRE = 0x0
543 01:15:09.845278 WR_PRE = 0x1
544 01:15:09.845966 WR_PST = 0x0
545 01:15:09.848649 DBI_WR = 0x0
546 01:15:09.849180 DBI_RD = 0x0
547 01:15:09.852362 OTF = 0x1
548 01:15:09.855780 ===================================
549 01:15:09.858888 ===================================
550 01:15:09.859426 ANA top config
551 01:15:09.861693 ===================================
552 01:15:09.865249 DLL_ASYNC_EN = 0
553 01:15:09.868559 ALL_SLAVE_EN = 1
554 01:15:09.871895 NEW_RANK_MODE = 1
555 01:15:09.872440 DLL_IDLE_MODE = 1
556 01:15:09.875404 LP45_APHY_COMB_EN = 1
557 01:15:09.878586 TX_ODT_DIS = 1
558 01:15:09.881864 NEW_8X_MODE = 1
559 01:15:09.885589 ===================================
560 01:15:09.889014 ===================================
561 01:15:09.892047 data_rate = 1600
562 01:15:09.892584 CKR = 1
563 01:15:09.895524 DQ_P2S_RATIO = 8
564 01:15:09.898754 ===================================
565 01:15:09.902412 CA_P2S_RATIO = 8
566 01:15:09.906423 DQ_CA_OPEN = 0
567 01:15:09.907022 DQ_SEMI_OPEN = 0
568 01:15:09.910010 CA_SEMI_OPEN = 0
569 01:15:09.913806 CA_FULL_RATE = 0
570 01:15:09.917134 DQ_CKDIV4_EN = 1
571 01:15:09.917713 CA_CKDIV4_EN = 1
572 01:15:09.921154 CA_PREDIV_EN = 0
573 01:15:09.924570 PH8_DLY = 0
574 01:15:09.928153 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 01:15:09.928715 DQ_AAMCK_DIV = 4
576 01:15:09.932016 CA_AAMCK_DIV = 4
577 01:15:09.935574 CA_ADMCK_DIV = 4
578 01:15:09.939212 DQ_TRACK_CA_EN = 0
579 01:15:09.942875 CA_PICK = 800
580 01:15:09.943328 CA_MCKIO = 800
581 01:15:09.947104 MCKIO_SEMI = 0
582 01:15:09.950196 PLL_FREQ = 3068
583 01:15:09.953387 DQ_UI_PI_RATIO = 32
584 01:15:09.953905 CA_UI_PI_RATIO = 0
585 01:15:09.957178 ===================================
586 01:15:09.961110 ===================================
587 01:15:09.964948 memory_type:LPDDR4
588 01:15:09.965634 GP_NUM : 10
589 01:15:09.968687 SRAM_EN : 1
590 01:15:09.969413 MD32_EN : 0
591 01:15:09.972369 ===================================
592 01:15:09.976616 [ANA_INIT] >>>>>>>>>>>>>>
593 01:15:09.979987 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 01:15:09.983631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 01:15:09.984146 ===================================
596 01:15:09.987395 data_rate = 1600,PCW = 0X7600
597 01:15:09.990829 ===================================
598 01:15:09.994242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 01:15:10.001272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 01:15:10.004833 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 01:15:10.011270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 01:15:10.014503 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 01:15:10.018673 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 01:15:10.019391 [ANA_INIT] flow start
605 01:15:10.021874 [ANA_INIT] PLL >>>>>>>>
606 01:15:10.025364 [ANA_INIT] PLL <<<<<<<<
607 01:15:10.025986 [ANA_INIT] MIDPI >>>>>>>>
608 01:15:10.029100 [ANA_INIT] MIDPI <<<<<<<<
609 01:15:10.032661 [ANA_INIT] DLL >>>>>>>>
610 01:15:10.033085 [ANA_INIT] flow end
611 01:15:10.036141 ============ LP4 DIFF to SE enter ============
612 01:15:10.040122 ============ LP4 DIFF to SE exit ============
613 01:15:10.043335 [ANA_INIT] <<<<<<<<<<<<<
614 01:15:10.046995 [Flow] Enable top DCM control >>>>>
615 01:15:10.050610 [Flow] Enable top DCM control <<<<<
616 01:15:10.054119 Enable DLL master slave shuffle
617 01:15:10.057455 ==============================================================
618 01:15:10.060946 Gating Mode config
619 01:15:10.067153 ==============================================================
620 01:15:10.067621 Config description:
621 01:15:10.077411 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 01:15:10.084611 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 01:15:10.087838 SELPH_MODE 0: By rank 1: By Phase
624 01:15:10.094378 ==============================================================
625 01:15:10.097902 GAT_TRACK_EN = 1
626 01:15:10.101140 RX_GATING_MODE = 2
627 01:15:10.103815 RX_GATING_TRACK_MODE = 2
628 01:15:10.107563 SELPH_MODE = 1
629 01:15:10.111052 PICG_EARLY_EN = 1
630 01:15:10.114404 VALID_LAT_VALUE = 1
631 01:15:10.117116 ==============================================================
632 01:15:10.120775 Enter into Gating configuration >>>>
633 01:15:10.124275 Exit from Gating configuration <<<<
634 01:15:10.127574 Enter into DVFS_PRE_config >>>>>
635 01:15:10.137801 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 01:15:10.140658 Exit from DVFS_PRE_config <<<<<
637 01:15:10.144342 Enter into PICG configuration >>>>
638 01:15:10.147268 Exit from PICG configuration <<<<
639 01:15:10.151113 [RX_INPUT] configuration >>>>>
640 01:15:10.153710 [RX_INPUT] configuration <<<<<
641 01:15:10.160824 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 01:15:10.164272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 01:15:10.170837 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 01:15:10.177118 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 01:15:10.183963 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 01:15:10.190942 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 01:15:10.193953 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 01:15:10.197542 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 01:15:10.200564 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 01:15:10.207380 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 01:15:10.210956 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 01:15:10.214201 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 01:15:10.217422 ===================================
654 01:15:10.220134 LPDDR4 DRAM CONFIGURATION
655 01:15:10.223674 ===================================
656 01:15:10.224104 EX_ROW_EN[0] = 0x0
657 01:15:10.227479 EX_ROW_EN[1] = 0x0
658 01:15:10.228010 LP4Y_EN = 0x0
659 01:15:10.230832 WORK_FSP = 0x0
660 01:15:10.231366 WL = 0x2
661 01:15:10.233778 RL = 0x2
662 01:15:10.237308 BL = 0x2
663 01:15:10.237893 RPST = 0x0
664 01:15:10.240490 RD_PRE = 0x0
665 01:15:10.241021 WR_PRE = 0x1
666 01:15:10.243873 WR_PST = 0x0
667 01:15:10.244399 DBI_WR = 0x0
668 01:15:10.247012 DBI_RD = 0x0
669 01:15:10.247603 OTF = 0x1
670 01:15:10.250739 ===================================
671 01:15:10.253821 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 01:15:10.257230 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 01:15:10.263615 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 01:15:10.267259 ===================================
675 01:15:10.270675 LPDDR4 DRAM CONFIGURATION
676 01:15:10.274465 ===================================
677 01:15:10.274996 EX_ROW_EN[0] = 0x10
678 01:15:10.277083 EX_ROW_EN[1] = 0x0
679 01:15:10.277658 LP4Y_EN = 0x0
680 01:15:10.280395 WORK_FSP = 0x0
681 01:15:10.280823 WL = 0x2
682 01:15:10.284225 RL = 0x2
683 01:15:10.284762 BL = 0x2
684 01:15:10.287075 RPST = 0x0
685 01:15:10.287612 RD_PRE = 0x0
686 01:15:10.290216 WR_PRE = 0x1
687 01:15:10.290748 WR_PST = 0x0
688 01:15:10.293716 DBI_WR = 0x0
689 01:15:10.297232 DBI_RD = 0x0
690 01:15:10.297680 OTF = 0x1
691 01:15:10.300573 ===================================
692 01:15:10.307090 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 01:15:10.311093 nWR fixed to 40
694 01:15:10.314090 [ModeRegInit_LP4] CH0 RK0
695 01:15:10.314626 [ModeRegInit_LP4] CH0 RK1
696 01:15:10.316958 [ModeRegInit_LP4] CH1 RK0
697 01:15:10.319988 [ModeRegInit_LP4] CH1 RK1
698 01:15:10.320422 match AC timing 13
699 01:15:10.327120 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 01:15:10.331056 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 01:15:10.333769 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 01:15:10.339919 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 01:15:10.343622 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 01:15:10.347048 [EMI DOE] emi_dcm 0
705 01:15:10.349881 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 01:15:10.350311 ==
707 01:15:10.353746 Dram Type= 6, Freq= 0, CH_0, rank 0
708 01:15:10.356655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 01:15:10.357189 ==
710 01:15:10.363433 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 01:15:10.369879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 01:15:10.378382 [CA 0] Center 38 (7~69) winsize 63
713 01:15:10.381871 [CA 1] Center 37 (7~68) winsize 62
714 01:15:10.384553 [CA 2] Center 35 (5~66) winsize 62
715 01:15:10.387908 [CA 3] Center 35 (5~66) winsize 62
716 01:15:10.392164 [CA 4] Center 34 (4~65) winsize 62
717 01:15:10.395377 [CA 5] Center 34 (4~65) winsize 62
718 01:15:10.395951
719 01:15:10.398779 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 01:15:10.399207
721 01:15:10.402892 [CATrainingPosCal] consider 1 rank data
722 01:15:10.406172 u2DelayCellTimex100 = 270/100 ps
723 01:15:10.410038 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 01:15:10.414074 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 01:15:10.417535 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 01:15:10.421249 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 01:15:10.424737 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 01:15:10.427957 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 01:15:10.428386
730 01:15:10.432006 CA PerBit enable=1, Macro0, CA PI delay=34
731 01:15:10.432540
732 01:15:10.435382 [CBTSetCACLKResult] CA Dly = 34
733 01:15:10.435809 CS Dly: 6 (0~37)
734 01:15:10.436150 ==
735 01:15:10.439310 Dram Type= 6, Freq= 0, CH_0, rank 1
736 01:15:10.442620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 01:15:10.443070 ==
738 01:15:10.449886 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 01:15:10.455957 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 01:15:10.464681 [CA 0] Center 37 (7~68) winsize 62
741 01:15:10.467971 [CA 1] Center 38 (7~69) winsize 63
742 01:15:10.471787 [CA 2] Center 35 (5~66) winsize 62
743 01:15:10.475372 [CA 3] Center 35 (5~66) winsize 62
744 01:15:10.479078 [CA 4] Center 34 (4~65) winsize 62
745 01:15:10.483068 [CA 5] Center 34 (3~65) winsize 63
746 01:15:10.483493
747 01:15:10.486885 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 01:15:10.487429
749 01:15:10.490548 [CATrainingPosCal] consider 2 rank data
750 01:15:10.490970 u2DelayCellTimex100 = 270/100 ps
751 01:15:10.494606 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
752 01:15:10.498283 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 01:15:10.502314 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 01:15:10.505814 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 01:15:10.509386 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 01:15:10.512700 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 01:15:10.513130
758 01:15:10.516821 CA PerBit enable=1, Macro0, CA PI delay=34
759 01:15:10.517342
760 01:15:10.520368 [CBTSetCACLKResult] CA Dly = 34
761 01:15:10.523692 CS Dly: 6 (0~38)
762 01:15:10.524116
763 01:15:10.527417 ----->DramcWriteLeveling(PI) begin...
764 01:15:10.527978 ==
765 01:15:10.528325 Dram Type= 6, Freq= 0, CH_0, rank 0
766 01:15:10.534985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 01:15:10.535505 ==
768 01:15:10.538165 Write leveling (Byte 0): 32 => 32
769 01:15:10.538591 Write leveling (Byte 1): 30 => 30
770 01:15:10.541960 DramcWriteLeveling(PI) end<-----
771 01:15:10.542638
772 01:15:10.543106 ==
773 01:15:10.545679 Dram Type= 6, Freq= 0, CH_0, rank 0
774 01:15:10.549879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 01:15:10.550449 ==
776 01:15:10.553189 [Gating] SW mode calibration
777 01:15:10.560419 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 01:15:10.563890 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 01:15:10.571615 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 01:15:10.575443 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 01:15:10.578810 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 01:15:10.582431 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
783 01:15:10.586014 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 01:15:10.593320 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 01:15:10.597833 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 01:15:10.601046 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 01:15:10.604590 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 01:15:10.608520 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 01:15:10.612582 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 01:15:10.619524 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 01:15:10.623590 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 01:15:10.627310 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 01:15:10.630650 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 01:15:10.634610 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 01:15:10.642310 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 01:15:10.645712 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 01:15:10.649452 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
798 01:15:10.653027 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 01:15:10.657220 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
800 01:15:10.660770 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 01:15:10.667685 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 01:15:10.671611 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 01:15:10.675278 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 01:15:10.678949 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 01:15:10.682891 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 01:15:10.690018 0 9 12 | B1->B0 | 2626 2d2d | 1 1 | (1 1) (1 1)
807 01:15:10.693598 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 01:15:10.697418 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 01:15:10.701235 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 01:15:10.704872 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 01:15:10.712162 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 01:15:10.716048 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 01:15:10.719683 0 10 8 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
814 01:15:10.722621 0 10 12 | B1->B0 | 2d2d 2424 | 0 0 | (1 0) (0 0)
815 01:15:10.729231 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 01:15:10.732528 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 01:15:10.736029 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 01:15:10.742489 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 01:15:10.745954 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 01:15:10.749368 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 01:15:10.756197 0 11 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
822 01:15:10.759406 0 11 12 | B1->B0 | 3636 3e3e | 0 0 | (0 0) (0 0)
823 01:15:10.762584 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 01:15:10.766138 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 01:15:10.772604 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 01:15:10.775806 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 01:15:10.779625 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 01:15:10.786181 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 01:15:10.789621 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 01:15:10.792984 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 01:15:10.799230 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
832 01:15:10.802700 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 01:15:10.806068 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 01:15:10.813144 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 01:15:10.816221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 01:15:10.819190 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 01:15:10.826004 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 01:15:10.829215 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 01:15:10.832675 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 01:15:10.839189 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 01:15:10.842763 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 01:15:10.845891 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 01:15:10.852604 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 01:15:10.855869 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 01:15:10.859407 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 01:15:10.862645 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 01:15:10.865942 Total UI for P1: 0, mck2ui 16
848 01:15:10.869115 best dqsien dly found for B0: ( 0, 14, 8)
849 01:15:10.876047 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 01:15:10.879584 Total UI for P1: 0, mck2ui 16
851 01:15:10.882749 best dqsien dly found for B1: ( 0, 14, 12)
852 01:15:10.886773 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
853 01:15:10.889664 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 01:15:10.890195
855 01:15:10.892949 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 01:15:10.895904 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 01:15:10.900104 [Gating] SW calibration Done
858 01:15:10.900625 ==
859 01:15:10.903043 Dram Type= 6, Freq= 0, CH_0, rank 0
860 01:15:10.906221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 01:15:10.906651 ==
862 01:15:10.909615 RX Vref Scan: 0
863 01:15:10.910037
864 01:15:10.910368 RX Vref 0 -> 0, step: 1
865 01:15:10.910681
866 01:15:10.912923 RX Delay -130 -> 252, step: 16
867 01:15:10.916627 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 01:15:10.923261 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 01:15:10.926347 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 01:15:10.929933 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 01:15:10.932909 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 01:15:10.936089 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 01:15:10.942967 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 01:15:10.946733 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 01:15:10.949828 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 01:15:10.953211 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 01:15:10.956550 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 01:15:10.963127 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 01:15:10.966766 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 01:15:10.970072 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 01:15:10.973503 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 01:15:10.976469 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 01:15:10.979859 ==
884 01:15:10.980386 Dram Type= 6, Freq= 0, CH_0, rank 0
885 01:15:10.986398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 01:15:10.986925 ==
887 01:15:10.987261 DQS Delay:
888 01:15:10.989819 DQS0 = 0, DQS1 = 0
889 01:15:10.990339 DQM Delay:
890 01:15:10.993481 DQM0 = 81, DQM1 = 69
891 01:15:10.994042 DQ Delay:
892 01:15:10.996847 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
893 01:15:10.999866 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 01:15:11.002985 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 01:15:11.006914 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 01:15:11.007441
897 01:15:11.007779
898 01:15:11.008148 ==
899 01:15:11.010659 Dram Type= 6, Freq= 0, CH_0, rank 0
900 01:15:11.013861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 01:15:11.014285 ==
902 01:15:11.014621
903 01:15:11.014930
904 01:15:11.017650 TX Vref Scan disable
905 01:15:11.018176 == TX Byte 0 ==
906 01:15:11.024129 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
907 01:15:11.026945 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
908 01:15:11.027404 == TX Byte 1 ==
909 01:15:11.033934 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
910 01:15:11.037391 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
911 01:15:11.037956 ==
912 01:15:11.040875 Dram Type= 6, Freq= 0, CH_0, rank 0
913 01:15:11.043582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 01:15:11.044007 ==
915 01:15:11.057681 TX Vref=22, minBit 0, minWin=26, winSum=428
916 01:15:11.061394 TX Vref=24, minBit 14, minWin=26, winSum=438
917 01:15:11.063949 TX Vref=26, minBit 14, minWin=26, winSum=440
918 01:15:11.067129 TX Vref=28, minBit 5, minWin=27, winSum=446
919 01:15:11.070878 TX Vref=30, minBit 10, minWin=26, winSum=442
920 01:15:11.077728 TX Vref=32, minBit 10, minWin=26, winSum=439
921 01:15:11.080784 [TxChooseVref] Worse bit 5, Min win 27, Win sum 446, Final Vref 28
922 01:15:11.081234
923 01:15:11.083856 Final TX Range 1 Vref 28
924 01:15:11.084278
925 01:15:11.084611 ==
926 01:15:11.087753 Dram Type= 6, Freq= 0, CH_0, rank 0
927 01:15:11.090580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 01:15:11.094027 ==
929 01:15:11.094552
930 01:15:11.094883
931 01:15:11.095185 TX Vref Scan disable
932 01:15:11.097755 == TX Byte 0 ==
933 01:15:11.101271 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
934 01:15:11.107648 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
935 01:15:11.108077 == TX Byte 1 ==
936 01:15:11.111510 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
937 01:15:11.115087 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
938 01:15:11.117796
939 01:15:11.118212 [DATLAT]
940 01:15:11.118546 Freq=800, CH0 RK0
941 01:15:11.118860
942 01:15:11.120966 DATLAT Default: 0xa
943 01:15:11.121398 0, 0xFFFF, sum = 0
944 01:15:11.124564 1, 0xFFFF, sum = 0
945 01:15:11.125049 2, 0xFFFF, sum = 0
946 01:15:11.128254 3, 0xFFFF, sum = 0
947 01:15:11.128780 4, 0xFFFF, sum = 0
948 01:15:11.130869 5, 0xFFFF, sum = 0
949 01:15:11.131304 6, 0xFFFF, sum = 0
950 01:15:11.134433 7, 0xFFFF, sum = 0
951 01:15:11.137748 8, 0xFFFF, sum = 0
952 01:15:11.138392 9, 0x0, sum = 1
953 01:15:11.138872 10, 0x0, sum = 2
954 01:15:11.141260 11, 0x0, sum = 3
955 01:15:11.141830 12, 0x0, sum = 4
956 01:15:11.144071 best_step = 10
957 01:15:11.144487
958 01:15:11.144816 ==
959 01:15:11.147620 Dram Type= 6, Freq= 0, CH_0, rank 0
960 01:15:11.150528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 01:15:11.150951 ==
962 01:15:11.154016 RX Vref Scan: 1
963 01:15:11.154429
964 01:15:11.154760 Set Vref Range= 32 -> 127
965 01:15:11.157573
966 01:15:11.157992 RX Vref 32 -> 127, step: 1
967 01:15:11.158323
968 01:15:11.161189 RX Delay -111 -> 252, step: 8
969 01:15:11.161640
970 01:15:11.163973 Set Vref, RX VrefLevel [Byte0]: 32
971 01:15:11.167578 [Byte1]: 32
972 01:15:11.167995
973 01:15:11.171212 Set Vref, RX VrefLevel [Byte0]: 33
974 01:15:11.174089 [Byte1]: 33
975 01:15:11.178040
976 01:15:11.178470 Set Vref, RX VrefLevel [Byte0]: 34
977 01:15:11.181468 [Byte1]: 34
978 01:15:11.185936
979 01:15:11.186492 Set Vref, RX VrefLevel [Byte0]: 35
980 01:15:11.189692 [Byte1]: 35
981 01:15:11.193761
982 01:15:11.194279 Set Vref, RX VrefLevel [Byte0]: 36
983 01:15:11.196787 [Byte1]: 36
984 01:15:11.201617
985 01:15:11.202035 Set Vref, RX VrefLevel [Byte0]: 37
986 01:15:11.204814 [Byte1]: 37
987 01:15:11.208997
988 01:15:11.209542 Set Vref, RX VrefLevel [Byte0]: 38
989 01:15:11.212437 [Byte1]: 38
990 01:15:11.216448
991 01:15:11.216967 Set Vref, RX VrefLevel [Byte0]: 39
992 01:15:11.219984 [Byte1]: 39
993 01:15:11.224222
994 01:15:11.224799 Set Vref, RX VrefLevel [Byte0]: 40
995 01:15:11.227775 [Byte1]: 40
996 01:15:11.231740
997 01:15:11.232205 Set Vref, RX VrefLevel [Byte0]: 41
998 01:15:11.234822 [Byte1]: 41
999 01:15:11.239544
1000 01:15:11.240064 Set Vref, RX VrefLevel [Byte0]: 42
1001 01:15:11.242659 [Byte1]: 42
1002 01:15:11.246782
1003 01:15:11.247259 Set Vref, RX VrefLevel [Byte0]: 43
1004 01:15:11.250265 [Byte1]: 43
1005 01:15:11.255068
1006 01:15:11.255581 Set Vref, RX VrefLevel [Byte0]: 44
1007 01:15:11.257979 [Byte1]: 44
1008 01:15:11.262896
1009 01:15:11.263528 Set Vref, RX VrefLevel [Byte0]: 45
1010 01:15:11.266070 [Byte1]: 45
1011 01:15:11.270365
1012 01:15:11.270784 Set Vref, RX VrefLevel [Byte0]: 46
1013 01:15:11.273542 [Byte1]: 46
1014 01:15:11.278270
1015 01:15:11.278784 Set Vref, RX VrefLevel [Byte0]: 47
1016 01:15:11.281108 [Byte1]: 47
1017 01:15:11.285794
1018 01:15:11.286216 Set Vref, RX VrefLevel [Byte0]: 48
1019 01:15:11.288788 [Byte1]: 48
1020 01:15:11.293405
1021 01:15:11.293955 Set Vref, RX VrefLevel [Byte0]: 49
1022 01:15:11.296258 [Byte1]: 49
1023 01:15:11.300735
1024 01:15:11.301258 Set Vref, RX VrefLevel [Byte0]: 50
1025 01:15:11.303861 [Byte1]: 50
1026 01:15:11.308313
1027 01:15:11.308817 Set Vref, RX VrefLevel [Byte0]: 51
1028 01:15:11.311938 [Byte1]: 51
1029 01:15:11.316019
1030 01:15:11.316527 Set Vref, RX VrefLevel [Byte0]: 52
1031 01:15:11.319187 [Byte1]: 52
1032 01:15:11.323159
1033 01:15:11.323661 Set Vref, RX VrefLevel [Byte0]: 53
1034 01:15:11.326980 [Byte1]: 53
1035 01:15:11.331401
1036 01:15:11.331913 Set Vref, RX VrefLevel [Byte0]: 54
1037 01:15:11.334403 [Byte1]: 54
1038 01:15:11.338849
1039 01:15:11.339359 Set Vref, RX VrefLevel [Byte0]: 55
1040 01:15:11.342042 [Byte1]: 55
1041 01:15:11.346108
1042 01:15:11.346635 Set Vref, RX VrefLevel [Byte0]: 56
1043 01:15:11.349779 [Byte1]: 56
1044 01:15:11.354145
1045 01:15:11.354653 Set Vref, RX VrefLevel [Byte0]: 57
1046 01:15:11.357425 [Byte1]: 57
1047 01:15:11.361866
1048 01:15:11.362369 Set Vref, RX VrefLevel [Byte0]: 58
1049 01:15:11.365118 [Byte1]: 58
1050 01:15:11.370099
1051 01:15:11.370609 Set Vref, RX VrefLevel [Byte0]: 59
1052 01:15:11.372996 [Byte1]: 59
1053 01:15:11.377820
1054 01:15:11.378375 Set Vref, RX VrefLevel [Byte0]: 60
1055 01:15:11.380605 [Byte1]: 60
1056 01:15:11.385405
1057 01:15:11.385994 Set Vref, RX VrefLevel [Byte0]: 61
1058 01:15:11.388224 [Byte1]: 61
1059 01:15:11.392391
1060 01:15:11.392944 Set Vref, RX VrefLevel [Byte0]: 62
1061 01:15:11.395833 [Byte1]: 62
1062 01:15:11.399964
1063 01:15:11.400419 Set Vref, RX VrefLevel [Byte0]: 63
1064 01:15:11.402960 [Byte1]: 63
1065 01:15:11.407367
1066 01:15:11.407775 Set Vref, RX VrefLevel [Byte0]: 64
1067 01:15:11.411336 [Byte1]: 64
1068 01:15:11.415075
1069 01:15:11.415588 Set Vref, RX VrefLevel [Byte0]: 65
1070 01:15:11.418702 [Byte1]: 65
1071 01:15:11.423056
1072 01:15:11.423502 Set Vref, RX VrefLevel [Byte0]: 66
1073 01:15:11.425879 [Byte1]: 66
1074 01:15:11.430384
1075 01:15:11.430887 Set Vref, RX VrefLevel [Byte0]: 67
1076 01:15:11.433671 [Byte1]: 67
1077 01:15:11.438369
1078 01:15:11.438891 Set Vref, RX VrefLevel [Byte0]: 68
1079 01:15:11.444941 [Byte1]: 68
1080 01:15:11.445355
1081 01:15:11.447586 Set Vref, RX VrefLevel [Byte0]: 69
1082 01:15:11.451007 [Byte1]: 69
1083 01:15:11.451416
1084 01:15:11.454879 Set Vref, RX VrefLevel [Byte0]: 70
1085 01:15:11.457685 [Byte1]: 70
1086 01:15:11.461430
1087 01:15:11.461999 Set Vref, RX VrefLevel [Byte0]: 71
1088 01:15:11.464431 [Byte1]: 71
1089 01:15:11.468448
1090 01:15:11.468889 Set Vref, RX VrefLevel [Byte0]: 72
1091 01:15:11.472371 [Byte1]: 72
1092 01:15:11.476299
1093 01:15:11.476932 Set Vref, RX VrefLevel [Byte0]: 73
1094 01:15:11.479585 [Byte1]: 73
1095 01:15:11.484143
1096 01:15:11.484558 Set Vref, RX VrefLevel [Byte0]: 74
1097 01:15:11.487612 [Byte1]: 74
1098 01:15:11.492169
1099 01:15:11.492679 Set Vref, RX VrefLevel [Byte0]: 75
1100 01:15:11.495526 [Byte1]: 75
1101 01:15:11.499530
1102 01:15:11.500041 Set Vref, RX VrefLevel [Byte0]: 76
1103 01:15:11.502720 [Byte1]: 76
1104 01:15:11.507507
1105 01:15:11.508047 Set Vref, RX VrefLevel [Byte0]: 77
1106 01:15:11.510091 [Byte1]: 77
1107 01:15:11.514694
1108 01:15:11.515203 Set Vref, RX VrefLevel [Byte0]: 78
1109 01:15:11.517817 [Byte1]: 78
1110 01:15:11.522419
1111 01:15:11.522968 Final RX Vref Byte 0 = 59 to rank0
1112 01:15:11.525885 Final RX Vref Byte 1 = 60 to rank0
1113 01:15:11.529289 Final RX Vref Byte 0 = 59 to rank1
1114 01:15:11.532323 Final RX Vref Byte 1 = 60 to rank1==
1115 01:15:11.535854 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 01:15:11.542327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 01:15:11.542741 ==
1118 01:15:11.543069 DQS Delay:
1119 01:15:11.543376 DQS0 = 0, DQS1 = 0
1120 01:15:11.545677 DQM Delay:
1121 01:15:11.546087 DQM0 = 82, DQM1 = 68
1122 01:15:11.548694 DQ Delay:
1123 01:15:11.552330 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1124 01:15:11.555851 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1125 01:15:11.556361 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1126 01:15:11.562441 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =76
1127 01:15:11.562962
1128 01:15:11.563291
1129 01:15:11.569151 [DQSOSCAuto] RK0, (LSB)MR18= 0x2120, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1130 01:15:11.572186 CH0 RK0: MR19=606, MR18=2120
1131 01:15:11.578851 CH0_RK0: MR19=0x606, MR18=0x2120, DQSOSC=401, MR23=63, INC=91, DEC=61
1132 01:15:11.579358
1133 01:15:11.582179 ----->DramcWriteLeveling(PI) begin...
1134 01:15:11.582609 ==
1135 01:15:11.585368 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 01:15:11.589125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 01:15:11.589683 ==
1138 01:15:11.592204 Write leveling (Byte 0): 30 => 30
1139 01:15:11.595302 Write leveling (Byte 1): 30 => 30
1140 01:15:11.598859 DramcWriteLeveling(PI) end<-----
1141 01:15:11.599558
1142 01:15:11.599927 ==
1143 01:15:11.602012 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 01:15:11.605692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 01:15:11.606115 ==
1146 01:15:11.609430 [Gating] SW mode calibration
1147 01:15:11.615556 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 01:15:11.622481 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 01:15:11.625823 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 01:15:11.629305 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 01:15:11.635568 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 01:15:11.639094 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 01:15:11.642423 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 01:15:11.648777 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 01:15:11.652034 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 01:15:11.655580 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 01:15:11.662462 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 01:15:11.666028 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 01:15:11.668750 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 01:15:11.675536 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 01:15:11.678842 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 01:15:11.682248 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 01:15:11.726232 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 01:15:11.726947 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 01:15:11.727828 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 01:15:11.728366 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 01:15:11.728739 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1168 01:15:11.729077 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 01:15:11.729472 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 01:15:11.729881 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 01:15:11.730204 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 01:15:11.730518 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 01:15:11.756248 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 01:15:11.756954 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 01:15:11.757421 0 9 8 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
1176 01:15:11.757841 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1177 01:15:11.758537 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 01:15:11.758901 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 01:15:11.759871 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 01:15:11.763599 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 01:15:11.766831 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 01:15:11.770051 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1183 01:15:11.773851 0 10 8 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (1 0)
1184 01:15:11.780192 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
1185 01:15:11.783749 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 01:15:11.787025 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 01:15:11.793334 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 01:15:11.796814 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 01:15:11.800582 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 01:15:11.806806 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
1191 01:15:11.810204 0 11 8 | B1->B0 | 2c2c 3837 | 0 1 | (0 0) (0 0)
1192 01:15:11.813898 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1193 01:15:11.820187 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 01:15:11.823350 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 01:15:11.826501 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 01:15:11.833143 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 01:15:11.837059 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 01:15:11.839888 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 01:15:11.843692 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1200 01:15:11.851562 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1201 01:15:11.854702 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 01:15:11.858356 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 01:15:11.861370 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 01:15:11.868438 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 01:15:11.872378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 01:15:11.875747 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 01:15:11.879469 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 01:15:11.885941 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 01:15:11.889193 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 01:15:11.892695 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 01:15:11.899042 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 01:15:11.902307 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 01:15:11.905871 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 01:15:11.912689 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 01:15:11.915745 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1216 01:15:11.919242 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 01:15:11.922045 Total UI for P1: 0, mck2ui 16
1218 01:15:11.925794 best dqsien dly found for B0: ( 0, 14, 8)
1219 01:15:11.929413 Total UI for P1: 0, mck2ui 16
1220 01:15:11.932724 best dqsien dly found for B1: ( 0, 14, 8)
1221 01:15:11.935460 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1222 01:15:11.939284 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 01:15:11.939701
1224 01:15:11.942057 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 01:15:11.949262 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 01:15:11.950277 [Gating] SW calibration Done
1227 01:15:11.950658 ==
1228 01:15:11.952365 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 01:15:11.958839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 01:15:11.959262 ==
1231 01:15:11.959593 RX Vref Scan: 0
1232 01:15:11.959906
1233 01:15:11.962143 RX Vref 0 -> 0, step: 1
1234 01:15:11.962560
1235 01:15:11.965791 RX Delay -130 -> 252, step: 16
1236 01:15:11.968721 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1237 01:15:11.972547 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1238 01:15:11.975315 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1239 01:15:11.982130 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1240 01:15:11.985355 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1241 01:15:11.988641 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1242 01:15:11.992366 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1243 01:15:11.995493 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1244 01:15:11.998937 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1245 01:15:12.005569 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1246 01:15:12.009236 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1247 01:15:12.012339 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1248 01:15:12.015620 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1249 01:15:12.022503 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1250 01:15:12.025765 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1251 01:15:12.029361 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1252 01:15:12.029910 ==
1253 01:15:12.032378 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 01:15:12.035838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 01:15:12.036360 ==
1256 01:15:12.039282 DQS Delay:
1257 01:15:12.039797 DQS0 = 0, DQS1 = 0
1258 01:15:12.042356 DQM Delay:
1259 01:15:12.042871 DQM0 = 81, DQM1 = 71
1260 01:15:12.043204 DQ Delay:
1261 01:15:12.045638 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1262 01:15:12.048956 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1263 01:15:12.052280 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1264 01:15:12.055579 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
1265 01:15:12.055993
1266 01:15:12.056323
1267 01:15:12.056628 ==
1268 01:15:12.058815 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 01:15:12.065426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 01:15:12.065877 ==
1271 01:15:12.066207
1272 01:15:12.066515
1273 01:15:12.066811 TX Vref Scan disable
1274 01:15:12.069296 == TX Byte 0 ==
1275 01:15:12.072598 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1276 01:15:12.076455 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1277 01:15:12.079353 == TX Byte 1 ==
1278 01:15:12.082724 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1279 01:15:12.089640 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1280 01:15:12.090164 ==
1281 01:15:12.093070 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 01:15:12.096114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 01:15:12.096539 ==
1284 01:15:12.108051 TX Vref=22, minBit 11, minWin=26, winSum=432
1285 01:15:12.112017 TX Vref=24, minBit 1, minWin=26, winSum=436
1286 01:15:12.114877 TX Vref=26, minBit 8, minWin=27, winSum=442
1287 01:15:12.118279 TX Vref=28, minBit 7, minWin=27, winSum=440
1288 01:15:12.121892 TX Vref=30, minBit 2, minWin=27, winSum=443
1289 01:15:12.125475 TX Vref=32, minBit 0, minWin=27, winSum=447
1290 01:15:12.131811 [TxChooseVref] Worse bit 0, Min win 27, Win sum 447, Final Vref 32
1291 01:15:12.132329
1292 01:15:12.134835 Final TX Range 1 Vref 32
1293 01:15:12.135251
1294 01:15:12.135578 ==
1295 01:15:12.138225 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 01:15:12.141557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 01:15:12.141976 ==
1298 01:15:12.142302
1299 01:15:12.145038
1300 01:15:12.145448 TX Vref Scan disable
1301 01:15:12.148303 == TX Byte 0 ==
1302 01:15:12.151626 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1303 01:15:12.155055 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1304 01:15:12.158082 == TX Byte 1 ==
1305 01:15:12.161869 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1306 01:15:12.164931 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1307 01:15:12.168653
1308 01:15:12.169173 [DATLAT]
1309 01:15:12.169506 Freq=800, CH0 RK1
1310 01:15:12.169880
1311 01:15:12.171361 DATLAT Default: 0xa
1312 01:15:12.171841 0, 0xFFFF, sum = 0
1313 01:15:12.174933 1, 0xFFFF, sum = 0
1314 01:15:12.175354 2, 0xFFFF, sum = 0
1315 01:15:12.178196 3, 0xFFFF, sum = 0
1316 01:15:12.178615 4, 0xFFFF, sum = 0
1317 01:15:12.181932 5, 0xFFFF, sum = 0
1318 01:15:12.182455 6, 0xFFFF, sum = 0
1319 01:15:12.185610 7, 0xFFFF, sum = 0
1320 01:15:12.188482 8, 0xFFFF, sum = 0
1321 01:15:12.189016 9, 0x0, sum = 1
1322 01:15:12.189356 10, 0x0, sum = 2
1323 01:15:12.192118 11, 0x0, sum = 3
1324 01:15:12.192639 12, 0x0, sum = 4
1325 01:15:12.195020 best_step = 10
1326 01:15:12.195534
1327 01:15:12.195868 ==
1328 01:15:12.198269 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 01:15:12.201461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 01:15:12.201908 ==
1331 01:15:12.205228 RX Vref Scan: 0
1332 01:15:12.205788
1333 01:15:12.206122 RX Vref 0 -> 0, step: 1
1334 01:15:12.206431
1335 01:15:12.208315 RX Delay -111 -> 252, step: 8
1336 01:15:12.215254 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1337 01:15:12.218147 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1338 01:15:12.221571 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1339 01:15:12.224489 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1340 01:15:12.228481 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1341 01:15:12.234793 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1342 01:15:12.237973 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1343 01:15:12.241421 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1344 01:15:12.245202 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1345 01:15:12.248352 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1346 01:15:12.255046 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1347 01:15:12.257829 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1348 01:15:12.261590 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1349 01:15:12.264992 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1350 01:15:12.271944 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1351 01:15:12.274867 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1352 01:15:12.275344 ==
1353 01:15:12.277819 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 01:15:12.281263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 01:15:12.281846 ==
1356 01:15:12.282188 DQS Delay:
1357 01:15:12.284798 DQS0 = 0, DQS1 = 0
1358 01:15:12.285344 DQM Delay:
1359 01:15:12.288114 DQM0 = 78, DQM1 = 70
1360 01:15:12.288568 DQ Delay:
1361 01:15:12.291566 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1362 01:15:12.294726 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1363 01:15:12.298085 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1364 01:15:12.301802 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =80
1365 01:15:12.302315
1366 01:15:12.302639
1367 01:15:12.311231 [DQSOSCAuto] RK1, (LSB)MR18= 0x4824, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1368 01:15:12.311794 CH0 RK1: MR19=606, MR18=4824
1369 01:15:12.318156 CH0_RK1: MR19=0x606, MR18=0x4824, DQSOSC=391, MR23=63, INC=96, DEC=64
1370 01:15:12.321650 [RxdqsGatingPostProcess] freq 800
1371 01:15:12.327996 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 01:15:12.331361 Pre-setting of DQS Precalculation
1373 01:15:12.335026 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 01:15:12.335585 ==
1375 01:15:12.338113 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 01:15:12.341570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 01:15:12.345484 ==
1378 01:15:12.348278 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 01:15:12.354793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 01:15:12.363281 [CA 0] Center 36 (6~67) winsize 62
1381 01:15:12.366310 [CA 1] Center 36 (6~67) winsize 62
1382 01:15:12.369974 [CA 2] Center 34 (4~64) winsize 61
1383 01:15:12.373391 [CA 3] Center 34 (4~64) winsize 61
1384 01:15:12.376815 [CA 4] Center 34 (4~65) winsize 62
1385 01:15:12.380237 [CA 5] Center 34 (4~64) winsize 61
1386 01:15:12.380857
1387 01:15:12.383269 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1388 01:15:12.383725
1389 01:15:12.386525 [CATrainingPosCal] consider 1 rank data
1390 01:15:12.389797 u2DelayCellTimex100 = 270/100 ps
1391 01:15:12.393464 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1392 01:15:12.396628 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1393 01:15:12.403289 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1394 01:15:12.406823 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1395 01:15:12.410061 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 01:15:12.413635 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 01:15:12.414194
1398 01:15:12.416848 CA PerBit enable=1, Macro0, CA PI delay=34
1399 01:15:12.417402
1400 01:15:12.420032 [CBTSetCACLKResult] CA Dly = 34
1401 01:15:12.420584 CS Dly: 5 (0~36)
1402 01:15:12.422858 ==
1403 01:15:12.426481 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 01:15:12.429696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 01:15:12.430213 ==
1406 01:15:12.433303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 01:15:12.439586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 01:15:12.449593 [CA 0] Center 37 (7~67) winsize 61
1409 01:15:12.452913 [CA 1] Center 37 (7~67) winsize 61
1410 01:15:12.456029 [CA 2] Center 34 (4~65) winsize 62
1411 01:15:12.460087 [CA 3] Center 33 (3~64) winsize 62
1412 01:15:12.462972 [CA 4] Center 34 (4~65) winsize 62
1413 01:15:12.465865 [CA 5] Center 33 (3~64) winsize 62
1414 01:15:12.466325
1415 01:15:12.469159 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1416 01:15:12.469651
1417 01:15:12.472646 [CATrainingPosCal] consider 2 rank data
1418 01:15:12.475596 u2DelayCellTimex100 = 270/100 ps
1419 01:15:12.479237 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1420 01:15:12.485714 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1421 01:15:12.489571 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1422 01:15:12.492698 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1423 01:15:12.496285 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 01:15:12.499009 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 01:15:12.499523
1426 01:15:12.502708 CA PerBit enable=1, Macro0, CA PI delay=34
1427 01:15:12.503229
1428 01:15:12.506225 [CBTSetCACLKResult] CA Dly = 34
1429 01:15:12.506733 CS Dly: 6 (0~38)
1430 01:15:12.507068
1431 01:15:12.509907 ----->DramcWriteLeveling(PI) begin...
1432 01:15:12.510426 ==
1433 01:15:12.513386 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 01:15:12.517605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 01:15:12.518020 ==
1436 01:15:12.520754 Write leveling (Byte 0): 29 => 29
1437 01:15:12.524240 Write leveling (Byte 1): 30 => 30
1438 01:15:12.528201 DramcWriteLeveling(PI) end<-----
1439 01:15:12.528704
1440 01:15:12.529044 ==
1441 01:15:12.531915 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 01:15:12.535181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 01:15:12.535605 ==
1444 01:15:12.539379 [Gating] SW mode calibration
1445 01:15:12.545724 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 01:15:12.552446 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 01:15:12.556075 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 01:15:12.558959 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 01:15:12.562206 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 01:15:12.569185 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1451 01:15:12.572327 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 01:15:12.575968 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 01:15:12.582543 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 01:15:12.585405 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 01:15:12.588865 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 01:15:12.595612 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 01:15:12.598939 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 01:15:12.602359 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 01:15:12.609465 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 01:15:12.611918 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 01:15:12.615240 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 01:15:12.622227 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 01:15:12.625598 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 01:15:12.628587 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1465 01:15:12.635140 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1466 01:15:12.638558 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 01:15:12.642419 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 01:15:12.648997 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 01:15:12.651693 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 01:15:12.655524 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 01:15:12.662435 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 01:15:12.665180 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 01:15:12.668905 0 9 8 | B1->B0 | 2a2a 2525 | 0 0 | (0 0) (0 0)
1474 01:15:12.675813 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 01:15:12.678803 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 01:15:12.682030 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 01:15:12.688995 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 01:15:12.692049 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 01:15:12.695718 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 01:15:12.698273 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1481 01:15:12.705747 0 10 8 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 1)
1482 01:15:12.708811 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 01:15:12.711891 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 01:15:12.718876 0 10 20 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
1485 01:15:12.722232 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 01:15:12.725386 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 01:15:12.732188 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 01:15:12.734835 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 01:15:12.738535 0 11 8 | B1->B0 | 3939 3b3b | 1 0 | (0 0) (1 1)
1490 01:15:12.745045 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 01:15:12.748490 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 01:15:12.751583 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 01:15:12.758263 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 01:15:12.761572 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 01:15:12.765061 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 01:15:12.771656 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 01:15:12.774957 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 01:15:12.778666 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 01:15:12.785028 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 01:15:12.788517 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 01:15:12.792020 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 01:15:12.798204 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 01:15:12.802107 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 01:15:12.805192 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 01:15:12.808640 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 01:15:12.815624 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 01:15:12.818386 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 01:15:12.821969 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 01:15:12.828503 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 01:15:12.831955 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 01:15:12.834819 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 01:15:12.841827 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 01:15:12.845007 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 01:15:12.848478 Total UI for P1: 0, mck2ui 16
1515 01:15:12.851910 best dqsien dly found for B0: ( 0, 14, 6)
1516 01:15:12.854959 Total UI for P1: 0, mck2ui 16
1517 01:15:12.858215 best dqsien dly found for B1: ( 0, 14, 6)
1518 01:15:12.861838 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1519 01:15:12.865159 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1520 01:15:12.865788
1521 01:15:12.868356 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 01:15:12.871538 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1523 01:15:12.874856 [Gating] SW calibration Done
1524 01:15:12.875268 ==
1525 01:15:12.878034 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 01:15:12.881668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 01:15:12.885318 ==
1528 01:15:12.885867 RX Vref Scan: 0
1529 01:15:12.886199
1530 01:15:12.888499 RX Vref 0 -> 0, step: 1
1531 01:15:12.888908
1532 01:15:12.891355 RX Delay -130 -> 252, step: 16
1533 01:15:12.895239 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1534 01:15:12.898467 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1535 01:15:12.901655 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1536 01:15:12.905547 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1537 01:15:12.908201 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1538 01:15:12.915254 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1539 01:15:12.918668 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1540 01:15:12.921634 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1541 01:15:12.925161 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1542 01:15:12.928546 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1543 01:15:12.935154 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1544 01:15:12.938762 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1545 01:15:12.941371 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1546 01:15:12.944998 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1547 01:15:12.951565 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1548 01:15:12.954529 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1549 01:15:12.955033 ==
1550 01:15:12.958224 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 01:15:12.961267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 01:15:12.961766 ==
1553 01:15:12.965198 DQS Delay:
1554 01:15:12.965894 DQS0 = 0, DQS1 = 0
1555 01:15:12.966277 DQM Delay:
1556 01:15:12.968301 DQM0 = 81, DQM1 = 73
1557 01:15:12.968850 DQ Delay:
1558 01:15:12.971573 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1559 01:15:12.974392 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1560 01:15:12.978015 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1561 01:15:12.981494 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1562 01:15:12.982091
1563 01:15:12.982464
1564 01:15:12.982805 ==
1565 01:15:12.984797 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 01:15:12.990957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 01:15:12.991511 ==
1568 01:15:12.991881
1569 01:15:12.992218
1570 01:15:12.992545 TX Vref Scan disable
1571 01:15:12.995150 == TX Byte 0 ==
1572 01:15:12.998018 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1573 01:15:13.001486 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1574 01:15:13.004938 == TX Byte 1 ==
1575 01:15:13.007774 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1576 01:15:13.011639 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1577 01:15:13.014584 ==
1578 01:15:13.018232 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 01:15:13.021213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 01:15:13.021679 ==
1581 01:15:13.033750 TX Vref=22, minBit 1, minWin=26, winSum=437
1582 01:15:13.036569 TX Vref=24, minBit 0, minWin=27, winSum=440
1583 01:15:13.040002 TX Vref=26, minBit 5, minWin=27, winSum=444
1584 01:15:13.043523 TX Vref=28, minBit 11, minWin=27, winSum=448
1585 01:15:13.046826 TX Vref=30, minBit 11, minWin=27, winSum=448
1586 01:15:13.053040 TX Vref=32, minBit 0, minWin=27, winSum=448
1587 01:15:13.057123 [TxChooseVref] Worse bit 11, Min win 27, Win sum 448, Final Vref 28
1588 01:15:13.057729
1589 01:15:13.059998 Final TX Range 1 Vref 28
1590 01:15:13.060615
1591 01:15:13.060969 ==
1592 01:15:13.063453 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 01:15:13.066600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 01:15:13.070242 ==
1595 01:15:13.070661
1596 01:15:13.070997
1597 01:15:13.071494 TX Vref Scan disable
1598 01:15:13.073463 == TX Byte 0 ==
1599 01:15:13.077140 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1600 01:15:13.080838 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1601 01:15:13.084270 == TX Byte 1 ==
1602 01:15:13.087679 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1603 01:15:13.091149 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1604 01:15:13.091552
1605 01:15:13.094791 [DATLAT]
1606 01:15:13.095305 Freq=800, CH1 RK0
1607 01:15:13.095642
1608 01:15:13.097653 DATLAT Default: 0xa
1609 01:15:13.098080 0, 0xFFFF, sum = 0
1610 01:15:13.100776 1, 0xFFFF, sum = 0
1611 01:15:13.101193 2, 0xFFFF, sum = 0
1612 01:15:13.104328 3, 0xFFFF, sum = 0
1613 01:15:13.104859 4, 0xFFFF, sum = 0
1614 01:15:13.107721 5, 0xFFFF, sum = 0
1615 01:15:13.108582 6, 0xFFFF, sum = 0
1616 01:15:13.110882 7, 0xFFFF, sum = 0
1617 01:15:13.111438 8, 0xFFFF, sum = 0
1618 01:15:13.114484 9, 0x0, sum = 1
1619 01:15:13.114900 10, 0x0, sum = 2
1620 01:15:13.117848 11, 0x0, sum = 3
1621 01:15:13.118298 12, 0x0, sum = 4
1622 01:15:13.120615 best_step = 10
1623 01:15:13.121025
1624 01:15:13.121349 ==
1625 01:15:13.124347 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 01:15:13.127563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 01:15:13.128079 ==
1628 01:15:13.131207 RX Vref Scan: 1
1629 01:15:13.131722
1630 01:15:13.132077 Set Vref Range= 32 -> 127
1631 01:15:13.132426
1632 01:15:13.134163 RX Vref 32 -> 127, step: 1
1633 01:15:13.134630
1634 01:15:13.137597 RX Delay -95 -> 252, step: 8
1635 01:15:13.138011
1636 01:15:13.141145 Set Vref, RX VrefLevel [Byte0]: 32
1637 01:15:13.144663 [Byte1]: 32
1638 01:15:13.145167
1639 01:15:13.147466 Set Vref, RX VrefLevel [Byte0]: 33
1640 01:15:13.151063 [Byte1]: 33
1641 01:15:13.151619
1642 01:15:13.154023 Set Vref, RX VrefLevel [Byte0]: 34
1643 01:15:13.157678 [Byte1]: 34
1644 01:15:13.161656
1645 01:15:13.162064 Set Vref, RX VrefLevel [Byte0]: 35
1646 01:15:13.164719 [Byte1]: 35
1647 01:15:13.169244
1648 01:15:13.169812 Set Vref, RX VrefLevel [Byte0]: 36
1649 01:15:13.172603 [Byte1]: 36
1650 01:15:13.176491
1651 01:15:13.177093 Set Vref, RX VrefLevel [Byte0]: 37
1652 01:15:13.180138 [Byte1]: 37
1653 01:15:13.184205
1654 01:15:13.184614 Set Vref, RX VrefLevel [Byte0]: 38
1655 01:15:13.187498 [Byte1]: 38
1656 01:15:13.191637
1657 01:15:13.192056 Set Vref, RX VrefLevel [Byte0]: 39
1658 01:15:13.195433 [Byte1]: 39
1659 01:15:13.199552
1660 01:15:13.199964 Set Vref, RX VrefLevel [Byte0]: 40
1661 01:15:13.202581 [Byte1]: 40
1662 01:15:13.207078
1663 01:15:13.210067 Set Vref, RX VrefLevel [Byte0]: 41
1664 01:15:13.210481 [Byte1]: 41
1665 01:15:13.214336
1666 01:15:13.214776 Set Vref, RX VrefLevel [Byte0]: 42
1667 01:15:13.217998 [Byte1]: 42
1668 01:15:13.222276
1669 01:15:13.222683 Set Vref, RX VrefLevel [Byte0]: 43
1670 01:15:13.225384 [Byte1]: 43
1671 01:15:13.230142
1672 01:15:13.230649 Set Vref, RX VrefLevel [Byte0]: 44
1673 01:15:13.233279 [Byte1]: 44
1674 01:15:13.237542
1675 01:15:13.237975 Set Vref, RX VrefLevel [Byte0]: 45
1676 01:15:13.240969 [Byte1]: 45
1677 01:15:13.245359
1678 01:15:13.245901 Set Vref, RX VrefLevel [Byte0]: 46
1679 01:15:13.248317 [Byte1]: 46
1680 01:15:13.252862
1681 01:15:13.253271 Set Vref, RX VrefLevel [Byte0]: 47
1682 01:15:13.256344 [Byte1]: 47
1683 01:15:13.260435
1684 01:15:13.261118 Set Vref, RX VrefLevel [Byte0]: 48
1685 01:15:13.264470 [Byte1]: 48
1686 01:15:13.268239
1687 01:15:13.268744 Set Vref, RX VrefLevel [Byte0]: 49
1688 01:15:13.271189 [Byte1]: 49
1689 01:15:13.275694
1690 01:15:13.276194 Set Vref, RX VrefLevel [Byte0]: 50
1691 01:15:13.278728 [Byte1]: 50
1692 01:15:13.283004
1693 01:15:13.283415 Set Vref, RX VrefLevel [Byte0]: 51
1694 01:15:13.286189 [Byte1]: 51
1695 01:15:13.291083
1696 01:15:13.291596 Set Vref, RX VrefLevel [Byte0]: 52
1697 01:15:13.293695 [Byte1]: 52
1698 01:15:13.298405
1699 01:15:13.298961 Set Vref, RX VrefLevel [Byte0]: 53
1700 01:15:13.301581 [Byte1]: 53
1701 01:15:13.305866
1702 01:15:13.306375 Set Vref, RX VrefLevel [Byte0]: 54
1703 01:15:13.308941 [Byte1]: 54
1704 01:15:13.313614
1705 01:15:13.314024 Set Vref, RX VrefLevel [Byte0]: 55
1706 01:15:13.317347 [Byte1]: 55
1707 01:15:13.321449
1708 01:15:13.322007 Set Vref, RX VrefLevel [Byte0]: 56
1709 01:15:13.324140 [Byte1]: 56
1710 01:15:13.328961
1711 01:15:13.329552 Set Vref, RX VrefLevel [Byte0]: 57
1712 01:15:13.332154 [Byte1]: 57
1713 01:15:13.336139
1714 01:15:13.336577 Set Vref, RX VrefLevel [Byte0]: 58
1715 01:15:13.339752 [Byte1]: 58
1716 01:15:13.343737
1717 01:15:13.344237 Set Vref, RX VrefLevel [Byte0]: 59
1718 01:15:13.347208 [Byte1]: 59
1719 01:15:13.351348
1720 01:15:13.351858 Set Vref, RX VrefLevel [Byte0]: 60
1721 01:15:13.354684 [Byte1]: 60
1722 01:15:13.359226
1723 01:15:13.359739 Set Vref, RX VrefLevel [Byte0]: 61
1724 01:15:13.362153 [Byte1]: 61
1725 01:15:13.366615
1726 01:15:13.367024 Set Vref, RX VrefLevel [Byte0]: 62
1727 01:15:13.370054 [Byte1]: 62
1728 01:15:13.374619
1729 01:15:13.375274 Set Vref, RX VrefLevel [Byte0]: 63
1730 01:15:13.377812 [Byte1]: 63
1731 01:15:13.381935
1732 01:15:13.382443 Set Vref, RX VrefLevel [Byte0]: 64
1733 01:15:13.385139 [Byte1]: 64
1734 01:15:13.389725
1735 01:15:13.390146 Set Vref, RX VrefLevel [Byte0]: 65
1736 01:15:13.393032 [Byte1]: 65
1737 01:15:13.397301
1738 01:15:13.397870 Set Vref, RX VrefLevel [Byte0]: 66
1739 01:15:13.400735 [Byte1]: 66
1740 01:15:13.404742
1741 01:15:13.405257 Set Vref, RX VrefLevel [Byte0]: 67
1742 01:15:13.408147 [Byte1]: 67
1743 01:15:13.412485
1744 01:15:13.413002 Set Vref, RX VrefLevel [Byte0]: 68
1745 01:15:13.415902 [Byte1]: 68
1746 01:15:13.420330
1747 01:15:13.420849 Set Vref, RX VrefLevel [Byte0]: 69
1748 01:15:13.423287 [Byte1]: 69
1749 01:15:13.427451
1750 01:15:13.427975 Set Vref, RX VrefLevel [Byte0]: 70
1751 01:15:13.430850 [Byte1]: 70
1752 01:15:13.435455
1753 01:15:13.435984 Set Vref, RX VrefLevel [Byte0]: 71
1754 01:15:13.438626 [Byte1]: 71
1755 01:15:13.442799
1756 01:15:13.443319 Set Vref, RX VrefLevel [Byte0]: 72
1757 01:15:13.446155 [Byte1]: 72
1758 01:15:13.450195
1759 01:15:13.450617 Set Vref, RX VrefLevel [Byte0]: 73
1760 01:15:13.453390 [Byte1]: 73
1761 01:15:13.457941
1762 01:15:13.458666 Set Vref, RX VrefLevel [Byte0]: 74
1763 01:15:13.461123 [Byte1]: 74
1764 01:15:13.465543
1765 01:15:13.466083 Set Vref, RX VrefLevel [Byte0]: 75
1766 01:15:13.468474 [Byte1]: 75
1767 01:15:13.472865
1768 01:15:13.473306 Final RX Vref Byte 0 = 57 to rank0
1769 01:15:13.476235 Final RX Vref Byte 1 = 57 to rank0
1770 01:15:13.479810 Final RX Vref Byte 0 = 57 to rank1
1771 01:15:13.483163 Final RX Vref Byte 1 = 57 to rank1==
1772 01:15:13.486435 Dram Type= 6, Freq= 0, CH_1, rank 0
1773 01:15:13.492863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1774 01:15:13.493289 ==
1775 01:15:13.493784 DQS Delay:
1776 01:15:13.494207 DQS0 = 0, DQS1 = 0
1777 01:15:13.496203 DQM Delay:
1778 01:15:13.496628 DQM0 = 81, DQM1 = 71
1779 01:15:13.500305 DQ Delay:
1780 01:15:13.503199 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =76
1781 01:15:13.503727 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1782 01:15:13.506437 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1783 01:15:13.509971 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1784 01:15:13.513465
1785 01:15:13.514022
1786 01:15:13.519659 [DQSOSCAuto] RK0, (LSB)MR18= 0x111b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1787 01:15:13.523536 CH1 RK0: MR19=606, MR18=111B
1788 01:15:13.530045 CH1_RK0: MR19=0x606, MR18=0x111B, DQSOSC=403, MR23=63, INC=90, DEC=60
1789 01:15:13.530565
1790 01:15:13.532820 ----->DramcWriteLeveling(PI) begin...
1791 01:15:13.533382 ==
1792 01:15:13.536622 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 01:15:13.540250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 01:15:13.540785 ==
1795 01:15:13.543476 Write leveling (Byte 0): 25 => 25
1796 01:15:13.546315 Write leveling (Byte 1): 30 => 30
1797 01:15:13.550099 DramcWriteLeveling(PI) end<-----
1798 01:15:13.550632
1799 01:15:13.551067 ==
1800 01:15:13.553458 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 01:15:13.556711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 01:15:13.557143 ==
1803 01:15:13.559726 [Gating] SW mode calibration
1804 01:15:13.566674 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1805 01:15:13.572898 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1806 01:15:13.576653 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1807 01:15:13.579873 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1808 01:15:13.586071 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 01:15:13.589438 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 01:15:13.592998 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 01:15:13.599725 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 01:15:13.602876 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 01:15:13.606115 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 01:15:13.612216 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 01:15:13.615795 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 01:15:13.619129 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 01:15:13.626019 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 01:15:13.629290 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 01:15:13.632756 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 01:15:13.639445 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 01:15:13.642637 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 01:15:13.646050 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1823 01:15:13.653008 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1824 01:15:13.655832 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1825 01:15:13.659035 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 01:15:13.666496 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 01:15:13.669146 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 01:15:13.672658 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 01:15:13.679016 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 01:15:13.682441 0 9 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1831 01:15:13.686233 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1832 01:15:13.692604 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1833 01:15:13.695749 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 01:15:13.698766 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 01:15:13.702465 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 01:15:13.708798 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 01:15:13.712192 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 01:15:13.715631 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 01:15:13.723076 0 10 4 | B1->B0 | 3232 2d2d | 1 0 | (1 1) (1 0)
1840 01:15:13.725370 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
1841 01:15:13.728913 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 01:15:13.735394 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 01:15:13.738851 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 01:15:13.742360 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 01:15:13.749249 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 01:15:13.752229 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 01:15:13.755841 0 11 4 | B1->B0 | 2828 3b3b | 1 0 | (0 0) (0 0)
1848 01:15:13.762451 0 11 8 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
1849 01:15:13.765408 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 01:15:13.769071 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 01:15:13.775511 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 01:15:13.778967 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 01:15:13.782195 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 01:15:13.788892 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 01:15:13.792347 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1856 01:15:13.795870 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 01:15:13.802151 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 01:15:13.805765 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 01:15:13.808795 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 01:15:13.812168 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 01:15:13.818822 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 01:15:13.822149 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 01:15:13.825778 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 01:15:13.832093 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 01:15:13.835629 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 01:15:13.838515 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 01:15:13.845283 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 01:15:13.848650 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 01:15:13.851969 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 01:15:13.858589 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 01:15:13.861836 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 01:15:13.865398 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1873 01:15:13.868768 Total UI for P1: 0, mck2ui 16
1874 01:15:13.871984 best dqsien dly found for B0: ( 0, 14, 6)
1875 01:15:13.878693 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 01:15:13.879205 Total UI for P1: 0, mck2ui 16
1877 01:15:13.885168 best dqsien dly found for B1: ( 0, 14, 8)
1878 01:15:13.888549 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1879 01:15:13.892033 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1880 01:15:13.892585
1881 01:15:13.895675 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1882 01:15:13.898521 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1883 01:15:13.902240 [Gating] SW calibration Done
1884 01:15:13.902792 ==
1885 01:15:13.905661 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 01:15:13.909190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 01:15:13.909786 ==
1888 01:15:13.912066 RX Vref Scan: 0
1889 01:15:13.912617
1890 01:15:13.912981 RX Vref 0 -> 0, step: 1
1891 01:15:13.913323
1892 01:15:13.915443 RX Delay -130 -> 252, step: 16
1893 01:15:13.918788 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1894 01:15:13.925300 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1895 01:15:13.928947 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1896 01:15:13.931948 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1897 01:15:13.935299 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1898 01:15:13.938596 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1899 01:15:13.945209 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1900 01:15:13.948722 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1901 01:15:13.952146 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1902 01:15:13.955253 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1903 01:15:13.958226 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1904 01:15:13.965302 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1905 01:15:13.968570 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1906 01:15:13.972271 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1907 01:15:13.975295 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1908 01:15:13.978412 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1909 01:15:13.978866 ==
1910 01:15:13.981573 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 01:15:13.988593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1912 01:15:13.989004 ==
1913 01:15:13.989332 DQS Delay:
1914 01:15:13.991963 DQS0 = 0, DQS1 = 0
1915 01:15:13.992371 DQM Delay:
1916 01:15:13.992697 DQM0 = 78, DQM1 = 71
1917 01:15:13.995871 DQ Delay:
1918 01:15:13.998567 DQ0 =77, DQ1 =69, DQ2 =61, DQ3 =77
1919 01:15:14.002333 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1920 01:15:14.005348 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1921 01:15:14.008943 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1922 01:15:14.009451
1923 01:15:14.009819
1924 01:15:14.010124 ==
1925 01:15:14.011456 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 01:15:14.015151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 01:15:14.015668 ==
1928 01:15:14.016001
1929 01:15:14.016306
1930 01:15:14.018486 TX Vref Scan disable
1931 01:15:14.021747 == TX Byte 0 ==
1932 01:15:14.025335 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1933 01:15:14.028484 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1934 01:15:14.031833 == TX Byte 1 ==
1935 01:15:14.034880 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1936 01:15:14.038122 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1937 01:15:14.038642 ==
1938 01:15:14.041414 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 01:15:14.044939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 01:15:14.047737 ==
1941 01:15:14.059865 TX Vref=22, minBit 9, minWin=27, winSum=453
1942 01:15:14.062866 TX Vref=24, minBit 1, minWin=28, winSum=458
1943 01:15:14.066618 TX Vref=26, minBit 1, minWin=28, winSum=462
1944 01:15:14.069888 TX Vref=28, minBit 1, minWin=28, winSum=463
1945 01:15:14.073448 TX Vref=30, minBit 1, minWin=28, winSum=463
1946 01:15:14.076805 TX Vref=32, minBit 1, minWin=28, winSum=464
1947 01:15:14.082983 [TxChooseVref] Worse bit 1, Min win 28, Win sum 464, Final Vref 32
1948 01:15:14.083552
1949 01:15:14.086626 Final TX Range 1 Vref 32
1950 01:15:14.087086
1951 01:15:14.087447 ==
1952 01:15:14.089733 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 01:15:14.092939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 01:15:14.093352 ==
1955 01:15:14.093710
1956 01:15:14.096240
1957 01:15:14.096750 TX Vref Scan disable
1958 01:15:14.100000 == TX Byte 0 ==
1959 01:15:14.103056 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1960 01:15:14.109448 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1961 01:15:14.109981 == TX Byte 1 ==
1962 01:15:14.113103 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1963 01:15:14.116532 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1964 01:15:14.119789
1965 01:15:14.120236 [DATLAT]
1966 01:15:14.120573 Freq=800, CH1 RK1
1967 01:15:14.120879
1968 01:15:14.123155 DATLAT Default: 0xa
1969 01:15:14.123564 0, 0xFFFF, sum = 0
1970 01:15:14.126055 1, 0xFFFF, sum = 0
1971 01:15:14.126475 2, 0xFFFF, sum = 0
1972 01:15:14.129688 3, 0xFFFF, sum = 0
1973 01:15:14.130206 4, 0xFFFF, sum = 0
1974 01:15:14.133175 5, 0xFFFF, sum = 0
1975 01:15:14.136173 6, 0xFFFF, sum = 0
1976 01:15:14.136686 7, 0xFFFF, sum = 0
1977 01:15:14.139579 8, 0xFFFF, sum = 0
1978 01:15:14.139996 9, 0x0, sum = 1
1979 01:15:14.140329 10, 0x0, sum = 2
1980 01:15:14.143105 11, 0x0, sum = 3
1981 01:15:14.143518 12, 0x0, sum = 4
1982 01:15:14.146715 best_step = 10
1983 01:15:14.147228
1984 01:15:14.147561 ==
1985 01:15:14.149642 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 01:15:14.153084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 01:15:14.153648 ==
1988 01:15:14.156658 RX Vref Scan: 0
1989 01:15:14.157175
1990 01:15:14.157507 RX Vref 0 -> 0, step: 1
1991 01:15:14.157888
1992 01:15:14.159403 RX Delay -111 -> 252, step: 8
1993 01:15:14.166514 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1994 01:15:14.169684 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1995 01:15:14.173303 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
1996 01:15:14.176463 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1997 01:15:14.180087 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1998 01:15:14.186253 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1999 01:15:14.189879 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2000 01:15:14.193061 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2001 01:15:14.196309 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2002 01:15:14.200067 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2003 01:15:14.206108 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2004 01:15:14.209733 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2005 01:15:14.212803 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2006 01:15:14.216239 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2007 01:15:14.223050 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2008 01:15:14.226309 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2009 01:15:14.226877 ==
2010 01:15:14.229776 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 01:15:14.233236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 01:15:14.233839 ==
2013 01:15:14.234213 DQS Delay:
2014 01:15:14.236026 DQS0 = 0, DQS1 = 0
2015 01:15:14.236572 DQM Delay:
2016 01:15:14.239158 DQM0 = 77, DQM1 = 74
2017 01:15:14.239612 DQ Delay:
2018 01:15:14.242914 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2019 01:15:14.246130 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2020 01:15:14.249733 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2021 01:15:14.253094 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2022 01:15:14.253690
2023 01:15:14.254064
2024 01:15:14.262317 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b33, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2025 01:15:14.262863 CH1 RK1: MR19=606, MR18=1B33
2026 01:15:14.269670 CH1_RK1: MR19=0x606, MR18=0x1B33, DQSOSC=396, MR23=63, INC=94, DEC=62
2027 01:15:14.272866 [RxdqsGatingPostProcess] freq 800
2028 01:15:14.279718 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2029 01:15:14.282987 Pre-setting of DQS Precalculation
2030 01:15:14.286421 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2031 01:15:14.292815 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2032 01:15:14.302511 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2033 01:15:14.303050
2034 01:15:14.303413
2035 01:15:14.303770 [Calibration Summary] 1600 Mbps
2036 01:15:14.305729 CH 0, Rank 0
2037 01:15:14.306202 SW Impedance : PASS
2038 01:15:14.309318 DUTY Scan : NO K
2039 01:15:14.312242 ZQ Calibration : PASS
2040 01:15:14.312659 Jitter Meter : NO K
2041 01:15:14.315670 CBT Training : PASS
2042 01:15:14.319277 Write leveling : PASS
2043 01:15:14.319791 RX DQS gating : PASS
2044 01:15:14.322517 RX DQ/DQS(RDDQC) : PASS
2045 01:15:14.325782 TX DQ/DQS : PASS
2046 01:15:14.326221 RX DATLAT : PASS
2047 01:15:14.329043 RX DQ/DQS(Engine): PASS
2048 01:15:14.332516 TX OE : NO K
2049 01:15:14.332928 All Pass.
2050 01:15:14.333255
2051 01:15:14.333600 CH 0, Rank 1
2052 01:15:14.335972 SW Impedance : PASS
2053 01:15:14.339543 DUTY Scan : NO K
2054 01:15:14.339953 ZQ Calibration : PASS
2055 01:15:14.342339 Jitter Meter : NO K
2056 01:15:14.345807 CBT Training : PASS
2057 01:15:14.346227 Write leveling : PASS
2058 01:15:14.349610 RX DQS gating : PASS
2059 01:15:14.350107 RX DQ/DQS(RDDQC) : PASS
2060 01:15:14.352932 TX DQ/DQS : PASS
2061 01:15:14.355805 RX DATLAT : PASS
2062 01:15:14.356213 RX DQ/DQS(Engine): PASS
2063 01:15:14.359236 TX OE : NO K
2064 01:15:14.359649 All Pass.
2065 01:15:14.359971
2066 01:15:14.362745 CH 1, Rank 0
2067 01:15:14.363203 SW Impedance : PASS
2068 01:15:14.366140 DUTY Scan : NO K
2069 01:15:14.369240 ZQ Calibration : PASS
2070 01:15:14.369743 Jitter Meter : NO K
2071 01:15:14.372440 CBT Training : PASS
2072 01:15:14.376233 Write leveling : PASS
2073 01:15:14.376754 RX DQS gating : PASS
2074 01:15:14.378994 RX DQ/DQS(RDDQC) : PASS
2075 01:15:14.382454 TX DQ/DQS : PASS
2076 01:15:14.382867 RX DATLAT : PASS
2077 01:15:14.385946 RX DQ/DQS(Engine): PASS
2078 01:15:14.389346 TX OE : NO K
2079 01:15:14.389839 All Pass.
2080 01:15:14.390269
2081 01:15:14.390722 CH 1, Rank 1
2082 01:15:14.392186 SW Impedance : PASS
2083 01:15:14.395785 DUTY Scan : NO K
2084 01:15:14.396193 ZQ Calibration : PASS
2085 01:15:14.399041 Jitter Meter : NO K
2086 01:15:14.399451 CBT Training : PASS
2087 01:15:14.402675 Write leveling : PASS
2088 01:15:14.405814 RX DQS gating : PASS
2089 01:15:14.406226 RX DQ/DQS(RDDQC) : PASS
2090 01:15:14.409150 TX DQ/DQS : PASS
2091 01:15:14.412409 RX DATLAT : PASS
2092 01:15:14.412825 RX DQ/DQS(Engine): PASS
2093 01:15:14.415590 TX OE : NO K
2094 01:15:14.416009 All Pass.
2095 01:15:14.416336
2096 01:15:14.418775 DramC Write-DBI off
2097 01:15:14.422724 PER_BANK_REFRESH: Hybrid Mode
2098 01:15:14.423230 TX_TRACKING: ON
2099 01:15:14.425496 [GetDramInforAfterCalByMRR] Vendor 6.
2100 01:15:14.428787 [GetDramInforAfterCalByMRR] Revision 606.
2101 01:15:14.432547 [GetDramInforAfterCalByMRR] Revision 2 0.
2102 01:15:14.435585 MR0 0x3b3b
2103 01:15:14.436000 MR8 0x5151
2104 01:15:14.439068 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 01:15:14.439481
2106 01:15:14.439807 MR0 0x3b3b
2107 01:15:14.442196 MR8 0x5151
2108 01:15:14.445815 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 01:15:14.446340
2110 01:15:14.455560 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2111 01:15:14.459099 [FAST_K] Save calibration result to emmc
2112 01:15:14.462519 [FAST_K] Save calibration result to emmc
2113 01:15:14.462987 dram_init: config_dvfs: 1
2114 01:15:14.469333 dramc_set_vcore_voltage set vcore to 662500
2115 01:15:14.469953 Read voltage for 1200, 2
2116 01:15:14.472989 Vio18 = 0
2117 01:15:14.473590 Vcore = 662500
2118 01:15:14.474042 Vdram = 0
2119 01:15:14.475782 Vddq = 0
2120 01:15:14.476331 Vmddr = 0
2121 01:15:14.479025 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2122 01:15:14.486229 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2123 01:15:14.489460 MEM_TYPE=3, freq_sel=15
2124 01:15:14.492458 sv_algorithm_assistance_LP4_1600
2125 01:15:14.495861 ============ PULL DRAM RESETB DOWN ============
2126 01:15:14.499264 ========== PULL DRAM RESETB DOWN end =========
2127 01:15:14.502303 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2128 01:15:14.505700 ===================================
2129 01:15:14.509150 LPDDR4 DRAM CONFIGURATION
2130 01:15:14.512751 ===================================
2131 01:15:14.516206 EX_ROW_EN[0] = 0x0
2132 01:15:14.516760 EX_ROW_EN[1] = 0x0
2133 01:15:14.519712 LP4Y_EN = 0x0
2134 01:15:14.520263 WORK_FSP = 0x0
2135 01:15:14.522406 WL = 0x4
2136 01:15:14.522912 RL = 0x4
2137 01:15:14.526144 BL = 0x2
2138 01:15:14.526699 RPST = 0x0
2139 01:15:14.528999 RD_PRE = 0x0
2140 01:15:14.529582 WR_PRE = 0x1
2141 01:15:14.532016 WR_PST = 0x0
2142 01:15:14.532469 DBI_WR = 0x0
2143 01:15:14.535759 DBI_RD = 0x0
2144 01:15:14.536313 OTF = 0x1
2145 01:15:14.539270 ===================================
2146 01:15:14.542242 ===================================
2147 01:15:14.545759 ANA top config
2148 01:15:14.549141 ===================================
2149 01:15:14.552350 DLL_ASYNC_EN = 0
2150 01:15:14.552806 ALL_SLAVE_EN = 0
2151 01:15:14.555649 NEW_RANK_MODE = 1
2152 01:15:14.559087 DLL_IDLE_MODE = 1
2153 01:15:14.562324 LP45_APHY_COMB_EN = 1
2154 01:15:14.565814 TX_ODT_DIS = 1
2155 01:15:14.566270 NEW_8X_MODE = 1
2156 01:15:14.568960 ===================================
2157 01:15:14.572366 ===================================
2158 01:15:14.575626 data_rate = 2400
2159 01:15:14.579337 CKR = 1
2160 01:15:14.582259 DQ_P2S_RATIO = 8
2161 01:15:14.585727 ===================================
2162 01:15:14.588615 CA_P2S_RATIO = 8
2163 01:15:14.589070 DQ_CA_OPEN = 0
2164 01:15:14.591922 DQ_SEMI_OPEN = 0
2165 01:15:14.595718 CA_SEMI_OPEN = 0
2166 01:15:14.599122 CA_FULL_RATE = 0
2167 01:15:14.602382 DQ_CKDIV4_EN = 0
2168 01:15:14.605456 CA_CKDIV4_EN = 0
2169 01:15:14.606014 CA_PREDIV_EN = 0
2170 01:15:14.609125 PH8_DLY = 17
2171 01:15:14.612413 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2172 01:15:14.615427 DQ_AAMCK_DIV = 4
2173 01:15:14.619205 CA_AAMCK_DIV = 4
2174 01:15:14.621820 CA_ADMCK_DIV = 4
2175 01:15:14.622246 DQ_TRACK_CA_EN = 0
2176 01:15:14.625616 CA_PICK = 1200
2177 01:15:14.628541 CA_MCKIO = 1200
2178 01:15:14.631822 MCKIO_SEMI = 0
2179 01:15:14.635567 PLL_FREQ = 2366
2180 01:15:14.638820 DQ_UI_PI_RATIO = 32
2181 01:15:14.642142 CA_UI_PI_RATIO = 0
2182 01:15:14.645134 ===================================
2183 01:15:14.648262 ===================================
2184 01:15:14.648678 memory_type:LPDDR4
2185 01:15:14.652185 GP_NUM : 10
2186 01:15:14.655399 SRAM_EN : 1
2187 01:15:14.655976 MD32_EN : 0
2188 01:15:14.658333 ===================================
2189 01:15:14.661949 [ANA_INIT] >>>>>>>>>>>>>>
2190 01:15:14.665059 <<<<<< [CONFIGURE PHASE]: ANA_TX
2191 01:15:14.668429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2192 01:15:14.671809 ===================================
2193 01:15:14.675421 data_rate = 2400,PCW = 0X5b00
2194 01:15:14.678703 ===================================
2195 01:15:14.681930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2196 01:15:14.685272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 01:15:14.691768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 01:15:14.695086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2199 01:15:14.698602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2200 01:15:14.701365 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2201 01:15:14.705326 [ANA_INIT] flow start
2202 01:15:14.708685 [ANA_INIT] PLL >>>>>>>>
2203 01:15:14.709198 [ANA_INIT] PLL <<<<<<<<
2204 01:15:14.712199 [ANA_INIT] MIDPI >>>>>>>>
2205 01:15:14.715762 [ANA_INIT] MIDPI <<<<<<<<
2206 01:15:14.718322 [ANA_INIT] DLL >>>>>>>>
2207 01:15:14.718735 [ANA_INIT] DLL <<<<<<<<
2208 01:15:14.722108 [ANA_INIT] flow end
2209 01:15:14.725618 ============ LP4 DIFF to SE enter ============
2210 01:15:14.728756 ============ LP4 DIFF to SE exit ============
2211 01:15:14.731634 [ANA_INIT] <<<<<<<<<<<<<
2212 01:15:14.735285 [Flow] Enable top DCM control >>>>>
2213 01:15:14.738710 [Flow] Enable top DCM control <<<<<
2214 01:15:14.741392 Enable DLL master slave shuffle
2215 01:15:14.748549 ==============================================================
2216 01:15:14.749060 Gating Mode config
2217 01:15:14.755362 ==============================================================
2218 01:15:14.755886 Config description:
2219 01:15:14.764899 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2220 01:15:14.771416 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2221 01:15:14.778252 SELPH_MODE 0: By rank 1: By Phase
2222 01:15:14.781313 ==============================================================
2223 01:15:14.785284 GAT_TRACK_EN = 1
2224 01:15:14.788479 RX_GATING_MODE = 2
2225 01:15:14.791628 RX_GATING_TRACK_MODE = 2
2226 01:15:14.794917 SELPH_MODE = 1
2227 01:15:14.798272 PICG_EARLY_EN = 1
2228 01:15:14.802035 VALID_LAT_VALUE = 1
2229 01:15:14.805243 ==============================================================
2230 01:15:14.808606 Enter into Gating configuration >>>>
2231 01:15:14.811274 Exit from Gating configuration <<<<
2232 01:15:14.815341 Enter into DVFS_PRE_config >>>>>
2233 01:15:14.828382 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2234 01:15:14.831612 Exit from DVFS_PRE_config <<<<<
2235 01:15:14.834727 Enter into PICG configuration >>>>
2236 01:15:14.835281 Exit from PICG configuration <<<<
2237 01:15:14.838202 [RX_INPUT] configuration >>>>>
2238 01:15:14.841241 [RX_INPUT] configuration <<<<<
2239 01:15:14.848450 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2240 01:15:14.851489 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2241 01:15:14.857893 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2242 01:15:14.865072 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2243 01:15:14.871644 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 01:15:14.878266 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 01:15:14.881770 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2246 01:15:14.885005 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2247 01:15:14.888212 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2248 01:15:14.894585 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2249 01:15:14.897899 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2250 01:15:14.901610 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2251 01:15:14.904872 ===================================
2252 01:15:14.908059 LPDDR4 DRAM CONFIGURATION
2253 01:15:14.911338 ===================================
2254 01:15:14.911756 EX_ROW_EN[0] = 0x0
2255 01:15:14.914947 EX_ROW_EN[1] = 0x0
2256 01:15:14.917859 LP4Y_EN = 0x0
2257 01:15:14.918271 WORK_FSP = 0x0
2258 01:15:14.921190 WL = 0x4
2259 01:15:14.921657 RL = 0x4
2260 01:15:14.924777 BL = 0x2
2261 01:15:14.925299 RPST = 0x0
2262 01:15:14.928098 RD_PRE = 0x0
2263 01:15:14.928617 WR_PRE = 0x1
2264 01:15:14.931575 WR_PST = 0x0
2265 01:15:14.931991 DBI_WR = 0x0
2266 01:15:14.934674 DBI_RD = 0x0
2267 01:15:14.935187 OTF = 0x1
2268 01:15:14.937828 ===================================
2269 01:15:14.941238 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2270 01:15:14.948232 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2271 01:15:14.951071 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2272 01:15:14.954878 ===================================
2273 01:15:14.958412 LPDDR4 DRAM CONFIGURATION
2274 01:15:14.961930 ===================================
2275 01:15:14.962454 EX_ROW_EN[0] = 0x10
2276 01:15:14.964791 EX_ROW_EN[1] = 0x0
2277 01:15:14.965334 LP4Y_EN = 0x0
2278 01:15:14.968297 WORK_FSP = 0x0
2279 01:15:14.968814 WL = 0x4
2280 01:15:14.971597 RL = 0x4
2281 01:15:14.974663 BL = 0x2
2282 01:15:14.975084 RPST = 0x0
2283 01:15:14.978012 RD_PRE = 0x0
2284 01:15:14.978531 WR_PRE = 0x1
2285 01:15:14.981358 WR_PST = 0x0
2286 01:15:14.981918 DBI_WR = 0x0
2287 01:15:14.984941 DBI_RD = 0x0
2288 01:15:14.985457 OTF = 0x1
2289 01:15:14.987903 ===================================
2290 01:15:14.994633 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2291 01:15:14.995156 ==
2292 01:15:14.997619 Dram Type= 6, Freq= 0, CH_0, rank 0
2293 01:15:15.001189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2294 01:15:15.001640 ==
2295 01:15:15.004626 [Duty_Offset_Calibration]
2296 01:15:15.007500 B0:2 B1:0 CA:3
2297 01:15:15.007909
2298 01:15:15.010895 [DutyScan_Calibration_Flow] k_type=0
2299 01:15:15.019299
2300 01:15:15.019722 ==CLK 0==
2301 01:15:15.022514 Final CLK duty delay cell = 0
2302 01:15:15.025412 [0] MAX Duty = 5062%(X100), DQS PI = 20
2303 01:15:15.029132 [0] MIN Duty = 4906%(X100), DQS PI = 54
2304 01:15:15.029779 [0] AVG Duty = 4984%(X100)
2305 01:15:15.032206
2306 01:15:15.035624 CH0 CLK Duty spec in!! Max-Min= 156%
2307 01:15:15.039200 [DutyScan_Calibration_Flow] ====Done====
2308 01:15:15.039739
2309 01:15:15.042175 [DutyScan_Calibration_Flow] k_type=1
2310 01:15:15.058141
2311 01:15:15.058653 ==DQS 0 ==
2312 01:15:15.061184 Final DQS duty delay cell = 0
2313 01:15:15.064639 [0] MAX Duty = 5062%(X100), DQS PI = 16
2314 01:15:15.067475 [0] MIN Duty = 4907%(X100), DQS PI = 2
2315 01:15:15.067888 [0] AVG Duty = 4984%(X100)
2316 01:15:15.071185
2317 01:15:15.071706 ==DQS 1 ==
2318 01:15:15.074044 Final DQS duty delay cell = -4
2319 01:15:15.077992 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2320 01:15:15.080566 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2321 01:15:15.084770 [-4] AVG Duty = 4922%(X100)
2322 01:15:15.085441
2323 01:15:15.087500 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2324 01:15:15.088020
2325 01:15:15.090725 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2326 01:15:15.094241 [DutyScan_Calibration_Flow] ====Done====
2327 01:15:15.094697
2328 01:15:15.097677 [DutyScan_Calibration_Flow] k_type=3
2329 01:15:15.115420
2330 01:15:15.115995 ==DQM 0 ==
2331 01:15:15.118254 Final DQM duty delay cell = 0
2332 01:15:15.121675 [0] MAX Duty = 5124%(X100), DQS PI = 28
2333 01:15:15.125264 [0] MIN Duty = 4876%(X100), DQS PI = 0
2334 01:15:15.128598 [0] AVG Duty = 5000%(X100)
2335 01:15:15.129164
2336 01:15:15.129589 ==DQM 1 ==
2337 01:15:15.131852 Final DQM duty delay cell = 4
2338 01:15:15.134835 [4] MAX Duty = 5124%(X100), DQS PI = 50
2339 01:15:15.138709 [4] MIN Duty = 5000%(X100), DQS PI = 12
2340 01:15:15.141389 [4] AVG Duty = 5062%(X100)
2341 01:15:15.141879
2342 01:15:15.144782 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2343 01:15:15.145238
2344 01:15:15.148330 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2345 01:15:15.151513 [DutyScan_Calibration_Flow] ====Done====
2346 01:15:15.152080
2347 01:15:15.154523 [DutyScan_Calibration_Flow] k_type=2
2348 01:15:15.170153
2349 01:15:15.170726 ==DQ 0 ==
2350 01:15:15.173303 Final DQ duty delay cell = -4
2351 01:15:15.176815 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2352 01:15:15.180190 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2353 01:15:15.183322 [-4] AVG Duty = 4969%(X100)
2354 01:15:15.183901
2355 01:15:15.184269 ==DQ 1 ==
2356 01:15:15.186700 Final DQ duty delay cell = -4
2357 01:15:15.189792 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2358 01:15:15.193677 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2359 01:15:15.196960 [-4] AVG Duty = 4938%(X100)
2360 01:15:15.197559
2361 01:15:15.200543 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2362 01:15:15.201105
2363 01:15:15.203002 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2364 01:15:15.206408 [DutyScan_Calibration_Flow] ====Done====
2365 01:15:15.206976 ==
2366 01:15:15.210046 Dram Type= 6, Freq= 0, CH_1, rank 0
2367 01:15:15.213449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 01:15:15.214058 ==
2369 01:15:15.216953 [Duty_Offset_Calibration]
2370 01:15:15.217548 B0:1 B1:-2 CA:0
2371 01:15:15.217937
2372 01:15:15.220457 [DutyScan_Calibration_Flow] k_type=0
2373 01:15:15.230657
2374 01:15:15.231210 ==CLK 0==
2375 01:15:15.234041 Final CLK duty delay cell = 0
2376 01:15:15.237688 [0] MAX Duty = 5031%(X100), DQS PI = 18
2377 01:15:15.240291 [0] MIN Duty = 4844%(X100), DQS PI = 58
2378 01:15:15.243972 [0] AVG Duty = 4937%(X100)
2379 01:15:15.244538
2380 01:15:15.247010 CH1 CLK Duty spec in!! Max-Min= 187%
2381 01:15:15.250499 [DutyScan_Calibration_Flow] ====Done====
2382 01:15:15.251050
2383 01:15:15.254039 [DutyScan_Calibration_Flow] k_type=1
2384 01:15:15.269090
2385 01:15:15.269711 ==DQS 0 ==
2386 01:15:15.272282 Final DQS duty delay cell = -4
2387 01:15:15.275369 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2388 01:15:15.278948 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2389 01:15:15.282502 [-4] AVG Duty = 4953%(X100)
2390 01:15:15.282960
2391 01:15:15.283323 ==DQS 1 ==
2392 01:15:15.285477 Final DQS duty delay cell = 0
2393 01:15:15.289064 [0] MAX Duty = 5093%(X100), DQS PI = 0
2394 01:15:15.292278 [0] MIN Duty = 4875%(X100), DQS PI = 26
2395 01:15:15.295471 [0] AVG Duty = 4984%(X100)
2396 01:15:15.296042
2397 01:15:15.298941 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2398 01:15:15.299453
2399 01:15:15.302073 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2400 01:15:15.305845 [DutyScan_Calibration_Flow] ====Done====
2401 01:15:15.306355
2402 01:15:15.309107 [DutyScan_Calibration_Flow] k_type=3
2403 01:15:15.325655
2404 01:15:15.326201 ==DQM 0 ==
2405 01:15:15.329049 Final DQM duty delay cell = 0
2406 01:15:15.332510 [0] MAX Duty = 5000%(X100), DQS PI = 22
2407 01:15:15.335498 [0] MIN Duty = 4844%(X100), DQS PI = 56
2408 01:15:15.338568 [0] AVG Duty = 4922%(X100)
2409 01:15:15.339022
2410 01:15:15.339382 ==DQM 1 ==
2411 01:15:15.342041 Final DQM duty delay cell = 0
2412 01:15:15.345249 [0] MAX Duty = 5031%(X100), DQS PI = 36
2413 01:15:15.349121 [0] MIN Duty = 4907%(X100), DQS PI = 2
2414 01:15:15.349744 [0] AVG Duty = 4969%(X100)
2415 01:15:15.352121
2416 01:15:15.355577 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2417 01:15:15.356032
2418 01:15:15.359173 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2419 01:15:15.362816 [DutyScan_Calibration_Flow] ====Done====
2420 01:15:15.363391
2421 01:15:15.365227 [DutyScan_Calibration_Flow] k_type=2
2422 01:15:15.382118
2423 01:15:15.382671 ==DQ 0 ==
2424 01:15:15.385226 Final DQ duty delay cell = 0
2425 01:15:15.388777 [0] MAX Duty = 5093%(X100), DQS PI = 20
2426 01:15:15.392127 [0] MIN Duty = 4938%(X100), DQS PI = 54
2427 01:15:15.392584 [0] AVG Duty = 5015%(X100)
2428 01:15:15.392945
2429 01:15:15.395043 ==DQ 1 ==
2430 01:15:15.398239 Final DQ duty delay cell = 0
2431 01:15:15.401696 [0] MAX Duty = 5093%(X100), DQS PI = 18
2432 01:15:15.405173 [0] MIN Duty = 4969%(X100), DQS PI = 26
2433 01:15:15.405639 [0] AVG Duty = 5031%(X100)
2434 01:15:15.405980
2435 01:15:15.408664 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2436 01:15:15.411707
2437 01:15:15.415548 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2438 01:15:15.418374 [DutyScan_Calibration_Flow] ====Done====
2439 01:15:15.421802 nWR fixed to 30
2440 01:15:15.422220 [ModeRegInit_LP4] CH0 RK0
2441 01:15:15.425326 [ModeRegInit_LP4] CH0 RK1
2442 01:15:15.428252 [ModeRegInit_LP4] CH1 RK0
2443 01:15:15.428673 [ModeRegInit_LP4] CH1 RK1
2444 01:15:15.432065 match AC timing 7
2445 01:15:15.435494 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2446 01:15:15.438738 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2447 01:15:15.445420 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2448 01:15:15.448934 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2449 01:15:15.455653 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2450 01:15:15.456070 ==
2451 01:15:15.458940 Dram Type= 6, Freq= 0, CH_0, rank 0
2452 01:15:15.461932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2453 01:15:15.462350 ==
2454 01:15:15.468615 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2455 01:15:15.471952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2456 01:15:15.482034 [CA 0] Center 40 (10~71) winsize 62
2457 01:15:15.485266 [CA 1] Center 39 (9~70) winsize 62
2458 01:15:15.488764 [CA 2] Center 36 (6~66) winsize 61
2459 01:15:15.491716 [CA 3] Center 35 (5~66) winsize 62
2460 01:15:15.495033 [CA 4] Center 34 (4~65) winsize 62
2461 01:15:15.498463 [CA 5] Center 33 (3~63) winsize 61
2462 01:15:15.498878
2463 01:15:15.501832 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2464 01:15:15.502372
2465 01:15:15.505467 [CATrainingPosCal] consider 1 rank data
2466 01:15:15.508324 u2DelayCellTimex100 = 270/100 ps
2467 01:15:15.511710 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2468 01:15:15.515114 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2469 01:15:15.522101 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2470 01:15:15.525413 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2471 01:15:15.529025 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2472 01:15:15.532182 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2473 01:15:15.532709
2474 01:15:15.535441 CA PerBit enable=1, Macro0, CA PI delay=33
2475 01:15:15.535965
2476 01:15:15.538741 [CBTSetCACLKResult] CA Dly = 33
2477 01:15:15.539154 CS Dly: 7 (0~38)
2478 01:15:15.542178 ==
2479 01:15:15.545279 Dram Type= 6, Freq= 0, CH_0, rank 1
2480 01:15:15.548391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2481 01:15:15.548909 ==
2482 01:15:15.555512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2483 01:15:15.558191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2484 01:15:15.568597 [CA 0] Center 40 (10~71) winsize 62
2485 01:15:15.571270 [CA 1] Center 39 (9~70) winsize 62
2486 01:15:15.574860 [CA 2] Center 35 (5~66) winsize 62
2487 01:15:15.577845 [CA 3] Center 35 (5~66) winsize 62
2488 01:15:15.581619 [CA 4] Center 34 (4~65) winsize 62
2489 01:15:15.585178 [CA 5] Center 33 (3~63) winsize 61
2490 01:15:15.585788
2491 01:15:15.588503 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2492 01:15:15.589061
2493 01:15:15.591319 [CATrainingPosCal] consider 2 rank data
2494 01:15:15.594699 u2DelayCellTimex100 = 270/100 ps
2495 01:15:15.598243 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2496 01:15:15.601804 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2497 01:15:15.608385 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2498 01:15:15.611813 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2499 01:15:15.614570 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2500 01:15:15.618096 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2501 01:15:15.618601
2502 01:15:15.621607 CA PerBit enable=1, Macro0, CA PI delay=33
2503 01:15:15.622069
2504 01:15:15.624895 [CBTSetCACLKResult] CA Dly = 33
2505 01:15:15.625453 CS Dly: 8 (0~40)
2506 01:15:15.628284
2507 01:15:15.631320 ----->DramcWriteLeveling(PI) begin...
2508 01:15:15.631786 ==
2509 01:15:15.634357 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 01:15:15.637998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 01:15:15.638567 ==
2512 01:15:15.640981 Write leveling (Byte 0): 33 => 33
2513 01:15:15.645018 Write leveling (Byte 1): 30 => 30
2514 01:15:15.648218 DramcWriteLeveling(PI) end<-----
2515 01:15:15.648777
2516 01:15:15.649141 ==
2517 01:15:15.651065 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 01:15:15.654457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 01:15:15.655037 ==
2520 01:15:15.658099 [Gating] SW mode calibration
2521 01:15:15.664821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2522 01:15:15.671274 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2523 01:15:15.674687 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 01:15:15.678047 0 15 4 | B1->B0 | 2828 3333 | 1 1 | (1 1) (1 1)
2525 01:15:15.684743 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 01:15:15.688226 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 01:15:15.690965 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 01:15:15.697805 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 01:15:15.701444 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 01:15:15.704767 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2531 01:15:15.711056 1 0 0 | B1->B0 | 3333 2a2a | 0 1 | (0 0) (1 0)
2532 01:15:15.714493 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2533 01:15:15.717744 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 01:15:15.721012 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 01:15:15.728526 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 01:15:15.730671 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 01:15:15.734297 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 01:15:15.740922 1 0 28 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2539 01:15:15.744398 1 1 0 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
2540 01:15:15.747773 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2541 01:15:15.754447 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 01:15:15.758008 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 01:15:15.761290 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 01:15:15.767465 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 01:15:15.770914 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 01:15:15.773958 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 01:15:15.780820 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2548 01:15:15.784361 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2549 01:15:15.787733 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 01:15:15.793860 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 01:15:15.797599 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 01:15:15.800724 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 01:15:15.807815 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 01:15:15.810756 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 01:15:15.814331 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 01:15:15.820887 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 01:15:15.823842 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 01:15:15.827533 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 01:15:15.833937 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 01:15:15.837780 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 01:15:15.840819 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 01:15:15.843962 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 01:15:15.850615 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2564 01:15:15.853736 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2565 01:15:15.857943 Total UI for P1: 0, mck2ui 16
2566 01:15:15.860982 best dqsien dly found for B0: ( 1, 4, 0)
2567 01:15:15.864476 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 01:15:15.867447 Total UI for P1: 0, mck2ui 16
2569 01:15:15.870463 best dqsien dly found for B1: ( 1, 4, 4)
2570 01:15:15.874035 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2571 01:15:15.877238 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2572 01:15:15.877740
2573 01:15:15.884321 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2574 01:15:15.887730 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2575 01:15:15.888286 [Gating] SW calibration Done
2576 01:15:15.890525 ==
2577 01:15:15.893701 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 01:15:15.897474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 01:15:15.897975 ==
2580 01:15:15.898336 RX Vref Scan: 0
2581 01:15:15.898673
2582 01:15:15.901149 RX Vref 0 -> 0, step: 1
2583 01:15:15.901757
2584 01:15:15.904262 RX Delay -40 -> 252, step: 8
2585 01:15:15.907744 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2586 01:15:15.910858 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2587 01:15:15.914011 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2588 01:15:15.920946 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2589 01:15:15.924413 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2590 01:15:15.927928 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2591 01:15:15.930510 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2592 01:15:15.934014 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2593 01:15:15.940445 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2594 01:15:15.944362 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2595 01:15:15.947186 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2596 01:15:15.950563 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2597 01:15:15.953829 iDelay=200, Bit 12, Center 103 (32 ~ 175) 144
2598 01:15:15.960852 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2599 01:15:15.963994 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2600 01:15:15.967005 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2601 01:15:15.967519 ==
2602 01:15:15.970622 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 01:15:15.974177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 01:15:15.974636 ==
2605 01:15:15.977303 DQS Delay:
2606 01:15:15.977977 DQS0 = 0, DQS1 = 0
2607 01:15:15.978347 DQM Delay:
2608 01:15:15.980500 DQM0 = 112, DQM1 = 102
2609 01:15:15.981056 DQ Delay:
2610 01:15:15.983876 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2611 01:15:15.987445 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2612 01:15:15.990713 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =95
2613 01:15:15.997810 DQ12 =103, DQ13 =107, DQ14 =115, DQ15 =111
2614 01:15:15.998366
2615 01:15:15.998723
2616 01:15:15.999052 ==
2617 01:15:16.000605 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 01:15:16.003790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 01:15:16.004246 ==
2620 01:15:16.004622
2621 01:15:16.004925
2622 01:15:16.007593 TX Vref Scan disable
2623 01:15:16.008120 == TX Byte 0 ==
2624 01:15:16.014233 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2625 01:15:16.017119 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2626 01:15:16.017571 == TX Byte 1 ==
2627 01:15:16.023981 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2628 01:15:16.027314 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2629 01:15:16.027832 ==
2630 01:15:16.030739 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 01:15:16.034360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 01:15:16.034881 ==
2633 01:15:16.046466 TX Vref=22, minBit 1, minWin=25, winSum=414
2634 01:15:16.049771 TX Vref=24, minBit 1, minWin=25, winSum=418
2635 01:15:16.053231 TX Vref=26, minBit 7, minWin=25, winSum=426
2636 01:15:16.056694 TX Vref=28, minBit 13, minWin=26, winSum=435
2637 01:15:16.060028 TX Vref=30, minBit 10, minWin=26, winSum=434
2638 01:15:16.066786 TX Vref=32, minBit 10, minWin=26, winSum=429
2639 01:15:16.069944 [TxChooseVref] Worse bit 13, Min win 26, Win sum 435, Final Vref 28
2640 01:15:16.070360
2641 01:15:16.073268 Final TX Range 1 Vref 28
2642 01:15:16.073717
2643 01:15:16.074055 ==
2644 01:15:16.076479 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 01:15:16.079461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 01:15:16.083174 ==
2647 01:15:16.083582
2648 01:15:16.083905
2649 01:15:16.084206 TX Vref Scan disable
2650 01:15:16.086832 == TX Byte 0 ==
2651 01:15:16.090132 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2652 01:15:16.096367 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2653 01:15:16.096782 == TX Byte 1 ==
2654 01:15:16.099856 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2655 01:15:16.106947 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2656 01:15:16.107454
2657 01:15:16.107783 [DATLAT]
2658 01:15:16.108089 Freq=1200, CH0 RK0
2659 01:15:16.108383
2660 01:15:16.109718 DATLAT Default: 0xd
2661 01:15:16.110126 0, 0xFFFF, sum = 0
2662 01:15:16.113313 1, 0xFFFF, sum = 0
2663 01:15:16.116414 2, 0xFFFF, sum = 0
2664 01:15:16.116929 3, 0xFFFF, sum = 0
2665 01:15:16.119702 4, 0xFFFF, sum = 0
2666 01:15:16.120121 5, 0xFFFF, sum = 0
2667 01:15:16.123183 6, 0xFFFF, sum = 0
2668 01:15:16.123657 7, 0xFFFF, sum = 0
2669 01:15:16.126611 8, 0xFFFF, sum = 0
2670 01:15:16.127128 9, 0xFFFF, sum = 0
2671 01:15:16.130202 10, 0xFFFF, sum = 0
2672 01:15:16.130811 11, 0xFFFF, sum = 0
2673 01:15:16.133310 12, 0x0, sum = 1
2674 01:15:16.133917 13, 0x0, sum = 2
2675 01:15:16.136716 14, 0x0, sum = 3
2676 01:15:16.137132 15, 0x0, sum = 4
2677 01:15:16.137464 best_step = 13
2678 01:15:16.140320
2679 01:15:16.140821 ==
2680 01:15:16.143006 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 01:15:16.146700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 01:15:16.147217 ==
2683 01:15:16.147556 RX Vref Scan: 1
2684 01:15:16.147861
2685 01:15:16.150138 Set Vref Range= 32 -> 127
2686 01:15:16.150645
2687 01:15:16.153406 RX Vref 32 -> 127, step: 1
2688 01:15:16.153878
2689 01:15:16.156393 RX Delay -37 -> 252, step: 4
2690 01:15:16.156917
2691 01:15:16.159505 Set Vref, RX VrefLevel [Byte0]: 32
2692 01:15:16.163482 [Byte1]: 32
2693 01:15:16.163995
2694 01:15:16.166604 Set Vref, RX VrefLevel [Byte0]: 33
2695 01:15:16.169626 [Byte1]: 33
2696 01:15:16.173317
2697 01:15:16.173814 Set Vref, RX VrefLevel [Byte0]: 34
2698 01:15:16.177078 [Byte1]: 34
2699 01:15:16.181188
2700 01:15:16.181642 Set Vref, RX VrefLevel [Byte0]: 35
2701 01:15:16.184661 [Byte1]: 35
2702 01:15:16.189307
2703 01:15:16.189932 Set Vref, RX VrefLevel [Byte0]: 36
2704 01:15:16.192615 [Byte1]: 36
2705 01:15:16.197204
2706 01:15:16.197639 Set Vref, RX VrefLevel [Byte0]: 37
2707 01:15:16.200763 [Byte1]: 37
2708 01:15:16.205542
2709 01:15:16.206067 Set Vref, RX VrefLevel [Byte0]: 38
2710 01:15:16.211867 [Byte1]: 38
2711 01:15:16.212376
2712 01:15:16.215378 Set Vref, RX VrefLevel [Byte0]: 39
2713 01:15:16.218332 [Byte1]: 39
2714 01:15:16.218842
2715 01:15:16.221853 Set Vref, RX VrefLevel [Byte0]: 40
2716 01:15:16.225025 [Byte1]: 40
2717 01:15:16.229206
2718 01:15:16.229757 Set Vref, RX VrefLevel [Byte0]: 41
2719 01:15:16.232427 [Byte1]: 41
2720 01:15:16.237586
2721 01:15:16.238099 Set Vref, RX VrefLevel [Byte0]: 42
2722 01:15:16.240568 [Byte1]: 42
2723 01:15:16.245289
2724 01:15:16.245883 Set Vref, RX VrefLevel [Byte0]: 43
2725 01:15:16.248249 [Byte1]: 43
2726 01:15:16.252935
2727 01:15:16.253342 Set Vref, RX VrefLevel [Byte0]: 44
2728 01:15:16.256666 [Byte1]: 44
2729 01:15:16.261187
2730 01:15:16.261737 Set Vref, RX VrefLevel [Byte0]: 45
2731 01:15:16.264833 [Byte1]: 45
2732 01:15:16.269091
2733 01:15:16.269622 Set Vref, RX VrefLevel [Byte0]: 46
2734 01:15:16.272274 [Byte1]: 46
2735 01:15:16.277306
2736 01:15:16.278059 Set Vref, RX VrefLevel [Byte0]: 47
2737 01:15:16.280730 [Byte1]: 47
2738 01:15:16.285458
2739 01:15:16.286032 Set Vref, RX VrefLevel [Byte0]: 48
2740 01:15:16.288784 [Byte1]: 48
2741 01:15:16.293021
2742 01:15:16.293628 Set Vref, RX VrefLevel [Byte0]: 49
2743 01:15:16.297065 [Byte1]: 49
2744 01:15:16.301433
2745 01:15:16.301985 Set Vref, RX VrefLevel [Byte0]: 50
2746 01:15:16.304453 [Byte1]: 50
2747 01:15:16.309711
2748 01:15:16.310374 Set Vref, RX VrefLevel [Byte0]: 51
2749 01:15:16.312577 [Byte1]: 51
2750 01:15:16.317228
2751 01:15:16.317788 Set Vref, RX VrefLevel [Byte0]: 52
2752 01:15:16.320611 [Byte1]: 52
2753 01:15:16.325232
2754 01:15:16.325677 Set Vref, RX VrefLevel [Byte0]: 53
2755 01:15:16.329016 [Byte1]: 53
2756 01:15:16.333632
2757 01:15:16.334143 Set Vref, RX VrefLevel [Byte0]: 54
2758 01:15:16.337023 [Byte1]: 54
2759 01:15:16.341496
2760 01:15:16.342107 Set Vref, RX VrefLevel [Byte0]: 55
2761 01:15:16.344676 [Byte1]: 55
2762 01:15:16.349660
2763 01:15:16.350235 Set Vref, RX VrefLevel [Byte0]: 56
2764 01:15:16.352719 [Byte1]: 56
2765 01:15:16.357209
2766 01:15:16.357810 Set Vref, RX VrefLevel [Byte0]: 57
2767 01:15:16.361149 [Byte1]: 57
2768 01:15:16.365816
2769 01:15:16.366370 Set Vref, RX VrefLevel [Byte0]: 58
2770 01:15:16.369065 [Byte1]: 58
2771 01:15:16.373155
2772 01:15:16.376592 Set Vref, RX VrefLevel [Byte0]: 59
2773 01:15:16.379984 [Byte1]: 59
2774 01:15:16.380535
2775 01:15:16.383006 Set Vref, RX VrefLevel [Byte0]: 60
2776 01:15:16.386847 [Byte1]: 60
2777 01:15:16.387405
2778 01:15:16.389618 Set Vref, RX VrefLevel [Byte0]: 61
2779 01:15:16.393055 [Byte1]: 61
2780 01:15:16.397319
2781 01:15:16.397773 Set Vref, RX VrefLevel [Byte0]: 62
2782 01:15:16.400920 [Byte1]: 62
2783 01:15:16.405087
2784 01:15:16.405504 Set Vref, RX VrefLevel [Byte0]: 63
2785 01:15:16.408659 [Byte1]: 63
2786 01:15:16.413276
2787 01:15:16.413843 Set Vref, RX VrefLevel [Byte0]: 64
2788 01:15:16.416735 [Byte1]: 64
2789 01:15:16.421404
2790 01:15:16.421872 Set Vref, RX VrefLevel [Byte0]: 65
2791 01:15:16.424746 [Byte1]: 65
2792 01:15:16.429854
2793 01:15:16.430380 Set Vref, RX VrefLevel [Byte0]: 66
2794 01:15:16.432335 [Byte1]: 66
2795 01:15:16.437288
2796 01:15:16.437868 Set Vref, RX VrefLevel [Byte0]: 67
2797 01:15:16.440776 [Byte1]: 67
2798 01:15:16.445042
2799 01:15:16.445458 Set Vref, RX VrefLevel [Byte0]: 68
2800 01:15:16.448844 [Byte1]: 68
2801 01:15:16.453272
2802 01:15:16.453769 Set Vref, RX VrefLevel [Byte0]: 69
2803 01:15:16.456556 [Byte1]: 69
2804 01:15:16.461862
2805 01:15:16.462380 Set Vref, RX VrefLevel [Byte0]: 70
2806 01:15:16.465173 [Byte1]: 70
2807 01:15:16.469332
2808 01:15:16.469901 Set Vref, RX VrefLevel [Byte0]: 71
2809 01:15:16.472384 [Byte1]: 71
2810 01:15:16.477372
2811 01:15:16.477846 Set Vref, RX VrefLevel [Byte0]: 72
2812 01:15:16.480916 [Byte1]: 72
2813 01:15:16.485471
2814 01:15:16.485926 Set Vref, RX VrefLevel [Byte0]: 73
2815 01:15:16.488902 [Byte1]: 73
2816 01:15:16.493572
2817 01:15:16.493988 Set Vref, RX VrefLevel [Byte0]: 74
2818 01:15:16.496762 [Byte1]: 74
2819 01:15:16.501678
2820 01:15:16.502196 Final RX Vref Byte 0 = 61 to rank0
2821 01:15:16.505008 Final RX Vref Byte 1 = 47 to rank0
2822 01:15:16.508239 Final RX Vref Byte 0 = 61 to rank1
2823 01:15:16.511206 Final RX Vref Byte 1 = 47 to rank1==
2824 01:15:16.515490 Dram Type= 6, Freq= 0, CH_0, rank 0
2825 01:15:16.517876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 01:15:16.521618 ==
2827 01:15:16.522136 DQS Delay:
2828 01:15:16.522474 DQS0 = 0, DQS1 = 0
2829 01:15:16.524735 DQM Delay:
2830 01:15:16.525152 DQM0 = 112, DQM1 = 98
2831 01:15:16.528001 DQ Delay:
2832 01:15:16.531513 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2833 01:15:16.534511 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2834 01:15:16.537947 DQ8 =90, DQ9 =82, DQ10 =98, DQ11 =90
2835 01:15:16.540824 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2836 01:15:16.541245
2837 01:15:16.541606
2838 01:15:16.547759 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2839 01:15:16.551285 CH0 RK0: MR19=303, MR18=FDFC
2840 01:15:16.557972 CH0_RK0: MR19=0x303, MR18=0xFDFC, DQSOSC=411, MR23=63, INC=38, DEC=25
2841 01:15:16.558494
2842 01:15:16.561479 ----->DramcWriteLeveling(PI) begin...
2843 01:15:16.562078 ==
2844 01:15:16.564422 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 01:15:16.568072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 01:15:16.568498 ==
2847 01:15:16.570884 Write leveling (Byte 0): 31 => 31
2848 01:15:16.574535 Write leveling (Byte 1): 29 => 29
2849 01:15:16.577965 DramcWriteLeveling(PI) end<-----
2850 01:15:16.578386
2851 01:15:16.578806 ==
2852 01:15:16.580867 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 01:15:16.587971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 01:15:16.588484 ==
2855 01:15:16.588957 [Gating] SW mode calibration
2856 01:15:16.597598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2857 01:15:16.600870 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2858 01:15:16.604326 0 15 0 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
2859 01:15:16.611195 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 01:15:16.614101 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 01:15:16.617358 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 01:15:16.624014 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 01:15:16.627770 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 01:15:16.630944 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2865 01:15:16.637504 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
2866 01:15:16.640826 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2867 01:15:16.644265 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 01:15:16.651071 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 01:15:16.654176 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 01:15:16.657942 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 01:15:16.664049 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 01:15:16.667515 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
2873 01:15:16.671160 1 0 28 | B1->B0 | 2525 3f3f | 0 0 | (0 0) (0 0)
2874 01:15:16.677612 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2875 01:15:16.681143 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 01:15:16.684527 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 01:15:16.690628 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 01:15:16.694495 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 01:15:16.697112 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 01:15:16.704375 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 01:15:16.707924 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 01:15:16.710649 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2883 01:15:16.717398 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 01:15:16.720678 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 01:15:16.724186 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 01:15:16.727663 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 01:15:16.733971 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 01:15:16.737318 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 01:15:16.740676 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 01:15:16.747066 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 01:15:16.750490 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 01:15:16.754196 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 01:15:16.760331 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 01:15:16.764040 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 01:15:16.767609 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 01:15:16.773721 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2897 01:15:16.777009 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 01:15:16.780779 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2899 01:15:16.783909 Total UI for P1: 0, mck2ui 16
2900 01:15:16.787198 best dqsien dly found for B0: ( 1, 3, 26)
2901 01:15:16.793975 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 01:15:16.794504 Total UI for P1: 0, mck2ui 16
2903 01:15:16.800485 best dqsien dly found for B1: ( 1, 4, 0)
2904 01:15:16.804023 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2905 01:15:16.807698 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2906 01:15:16.808221
2907 01:15:16.810320 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2908 01:15:16.813828 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2909 01:15:16.817036 [Gating] SW calibration Done
2910 01:15:16.817495 ==
2911 01:15:16.820451 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 01:15:16.823434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 01:15:16.823865 ==
2914 01:15:16.827255 RX Vref Scan: 0
2915 01:15:16.827776
2916 01:15:16.828108 RX Vref 0 -> 0, step: 1
2917 01:15:16.828421
2918 01:15:16.830423 RX Delay -40 -> 252, step: 8
2919 01:15:16.833999 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2920 01:15:16.840926 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2921 01:15:16.844305 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2922 01:15:16.847595 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2923 01:15:16.850631 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2924 01:15:16.853625 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2925 01:15:16.857412 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2926 01:15:16.863926 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2927 01:15:16.866987 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2928 01:15:16.870684 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2929 01:15:16.873590 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2930 01:15:16.877006 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
2931 01:15:16.884031 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2932 01:15:16.887290 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2933 01:15:16.890371 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2934 01:15:16.893351 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2935 01:15:16.893937 ==
2936 01:15:16.897497 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 01:15:16.903860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 01:15:16.904382 ==
2939 01:15:16.904722 DQS Delay:
2940 01:15:16.905038 DQS0 = 0, DQS1 = 0
2941 01:15:16.907154 DQM Delay:
2942 01:15:16.907676 DQM0 = 112, DQM1 = 100
2943 01:15:16.910444 DQ Delay:
2944 01:15:16.913628 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2945 01:15:16.917284 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2946 01:15:16.920888 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =91
2947 01:15:16.923963 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2948 01:15:16.924489
2949 01:15:16.924829
2950 01:15:16.925142 ==
2951 01:15:16.926987 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 01:15:16.930728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 01:15:16.931412 ==
2954 01:15:16.931776
2955 01:15:16.932092
2956 01:15:16.933616 TX Vref Scan disable
2957 01:15:16.937021 == TX Byte 0 ==
2958 01:15:16.940891 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2959 01:15:16.944212 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2960 01:15:16.947237 == TX Byte 1 ==
2961 01:15:16.950280 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2962 01:15:16.953604 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2963 01:15:16.954032 ==
2964 01:15:16.957434 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 01:15:16.964020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 01:15:16.964552 ==
2967 01:15:16.974373 TX Vref=22, minBit 1, minWin=25, winSum=428
2968 01:15:16.977318 TX Vref=24, minBit 1, minWin=26, winSum=432
2969 01:15:16.980995 TX Vref=26, minBit 8, minWin=26, winSum=438
2970 01:15:16.984397 TX Vref=28, minBit 1, minWin=27, winSum=442
2971 01:15:16.987791 TX Vref=30, minBit 8, minWin=26, winSum=442
2972 01:15:16.991058 TX Vref=32, minBit 8, minWin=26, winSum=443
2973 01:15:16.997376 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 28
2974 01:15:16.997949
2975 01:15:17.000832 Final TX Range 1 Vref 28
2976 01:15:17.001354
2977 01:15:17.001747 ==
2978 01:15:17.004510 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 01:15:17.007762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 01:15:17.008286 ==
2981 01:15:17.008623
2982 01:15:17.011308
2983 01:15:17.011825 TX Vref Scan disable
2984 01:15:17.013914 == TX Byte 0 ==
2985 01:15:17.017598 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2986 01:15:17.020744 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2987 01:15:17.024569 == TX Byte 1 ==
2988 01:15:17.027504 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2989 01:15:17.030900 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2990 01:15:17.031427
2991 01:15:17.034034 [DATLAT]
2992 01:15:17.034451 Freq=1200, CH0 RK1
2993 01:15:17.034789
2994 01:15:17.037296 DATLAT Default: 0xd
2995 01:15:17.037758 0, 0xFFFF, sum = 0
2996 01:15:17.040940 1, 0xFFFF, sum = 0
2997 01:15:17.041468 2, 0xFFFF, sum = 0
2998 01:15:17.044241 3, 0xFFFF, sum = 0
2999 01:15:17.044654 4, 0xFFFF, sum = 0
3000 01:15:17.047461 5, 0xFFFF, sum = 0
3001 01:15:17.047980 6, 0xFFFF, sum = 0
3002 01:15:17.050718 7, 0xFFFF, sum = 0
3003 01:15:17.054112 8, 0xFFFF, sum = 0
3004 01:15:17.054530 9, 0xFFFF, sum = 0
3005 01:15:17.057606 10, 0xFFFF, sum = 0
3006 01:15:17.058026 11, 0xFFFF, sum = 0
3007 01:15:17.060598 12, 0x0, sum = 1
3008 01:15:17.061015 13, 0x0, sum = 2
3009 01:15:17.063975 14, 0x0, sum = 3
3010 01:15:17.064398 15, 0x0, sum = 4
3011 01:15:17.064732 best_step = 13
3012 01:15:17.065039
3013 01:15:17.067546 ==
3014 01:15:17.070505 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 01:15:17.074135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 01:15:17.074672 ==
3017 01:15:17.075008 RX Vref Scan: 0
3018 01:15:17.075314
3019 01:15:17.076930 RX Vref 0 -> 0, step: 1
3020 01:15:17.077339
3021 01:15:17.080912 RX Delay -37 -> 252, step: 4
3022 01:15:17.083780 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3023 01:15:17.091001 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3024 01:15:17.093696 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3025 01:15:17.096983 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3026 01:15:17.100742 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3027 01:15:17.103976 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3028 01:15:17.110702 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3029 01:15:17.114011 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3030 01:15:17.117448 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3031 01:15:17.120747 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3032 01:15:17.123799 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3033 01:15:17.126972 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3034 01:15:17.134273 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3035 01:15:17.137097 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3036 01:15:17.140843 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3037 01:15:17.143856 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3038 01:15:17.144412 ==
3039 01:15:17.147005 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 01:15:17.153746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 01:15:17.154305 ==
3042 01:15:17.154673 DQS Delay:
3043 01:15:17.157070 DQS0 = 0, DQS1 = 0
3044 01:15:17.157574 DQM Delay:
3045 01:15:17.160930 DQM0 = 110, DQM1 = 100
3046 01:15:17.161540 DQ Delay:
3047 01:15:17.163511 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3048 01:15:17.166894 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3049 01:15:17.170089 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =92
3050 01:15:17.173670 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3051 01:15:17.174217
3052 01:15:17.174580
3053 01:15:17.184032 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3054 01:15:17.184604 CH0 RK1: MR19=403, MR18=12F9
3055 01:15:17.190111 CH0_RK1: MR19=0x403, MR18=0x12F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3056 01:15:17.193423 [RxdqsGatingPostProcess] freq 1200
3057 01:15:17.200730 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3058 01:15:17.203932 best DQS0 dly(2T, 0.5T) = (0, 12)
3059 01:15:17.207415 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 01:15:17.210475 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3061 01:15:17.214149 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 01:15:17.214709 best DQS0 dly(2T, 0.5T) = (0, 11)
3063 01:15:17.217389 best DQS1 dly(2T, 0.5T) = (0, 12)
3064 01:15:17.220511 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3065 01:15:17.223795 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3066 01:15:17.227177 Pre-setting of DQS Precalculation
3067 01:15:17.234140 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3068 01:15:17.234696 ==
3069 01:15:17.237235 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 01:15:17.240507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 01:15:17.241060 ==
3072 01:15:17.247126 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 01:15:17.250806 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3074 01:15:17.260268 [CA 0] Center 37 (7~67) winsize 61
3075 01:15:17.263709 [CA 1] Center 38 (8~68) winsize 61
3076 01:15:17.266415 [CA 2] Center 34 (4~64) winsize 61
3077 01:15:17.269733 [CA 3] Center 33 (3~64) winsize 62
3078 01:15:17.273419 [CA 4] Center 34 (4~64) winsize 61
3079 01:15:17.276355 [CA 5] Center 33 (3~63) winsize 61
3080 01:15:17.276833
3081 01:15:17.280139 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3082 01:15:17.280599
3083 01:15:17.283269 [CATrainingPosCal] consider 1 rank data
3084 01:15:17.286499 u2DelayCellTimex100 = 270/100 ps
3085 01:15:17.290160 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3086 01:15:17.293376 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3087 01:15:17.299666 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3088 01:15:17.303393 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3089 01:15:17.306624 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 01:15:17.310059 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3091 01:15:17.310579
3092 01:15:17.313323 CA PerBit enable=1, Macro0, CA PI delay=33
3093 01:15:17.313776
3094 01:15:17.316685 [CBTSetCACLKResult] CA Dly = 33
3095 01:15:17.317219 CS Dly: 5 (0~36)
3096 01:15:17.319873 ==
3097 01:15:17.320332 Dram Type= 6, Freq= 0, CH_1, rank 1
3098 01:15:17.326544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 01:15:17.327078 ==
3100 01:15:17.330279 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3101 01:15:17.336442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3102 01:15:17.345980 [CA 0] Center 38 (8~68) winsize 61
3103 01:15:17.349321 [CA 1] Center 37 (7~68) winsize 62
3104 01:15:17.352722 [CA 2] Center 34 (4~65) winsize 62
3105 01:15:17.356269 [CA 3] Center 33 (3~64) winsize 62
3106 01:15:17.359188 [CA 4] Center 34 (4~65) winsize 62
3107 01:15:17.362578 [CA 5] Center 33 (3~63) winsize 61
3108 01:15:17.363045
3109 01:15:17.365625 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3110 01:15:17.366186
3111 01:15:17.369237 [CATrainingPosCal] consider 2 rank data
3112 01:15:17.372278 u2DelayCellTimex100 = 270/100 ps
3113 01:15:17.375616 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3114 01:15:17.382009 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3115 01:15:17.385689 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3116 01:15:17.389082 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3117 01:15:17.391994 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3118 01:15:17.395371 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3119 01:15:17.395835
3120 01:15:17.398889 CA PerBit enable=1, Macro0, CA PI delay=33
3121 01:15:17.399535
3122 01:15:17.402143 [CBTSetCACLKResult] CA Dly = 33
3123 01:15:17.402840 CS Dly: 7 (0~40)
3124 01:15:17.405495
3125 01:15:17.408982 ----->DramcWriteLeveling(PI) begin...
3126 01:15:17.409609 ==
3127 01:15:17.411781 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 01:15:17.415251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 01:15:17.415724 ==
3130 01:15:17.418323 Write leveling (Byte 0): 25 => 25
3131 01:15:17.421871 Write leveling (Byte 1): 28 => 28
3132 01:15:17.425173 DramcWriteLeveling(PI) end<-----
3133 01:15:17.425739
3134 01:15:17.426080 ==
3135 01:15:17.428422 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 01:15:17.431757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 01:15:17.432282 ==
3138 01:15:17.435093 [Gating] SW mode calibration
3139 01:15:17.441890 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3140 01:15:17.448776 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3141 01:15:17.452197 0 15 0 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (0 0)
3142 01:15:17.455394 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 01:15:17.461722 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 01:15:17.465186 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 01:15:17.468764 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 01:15:17.475375 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 01:15:17.478531 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 01:15:17.482035 0 15 28 | B1->B0 | 2a2a 2d2d | 1 0 | (1 0) (0 0)
3149 01:15:17.485188 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 01:15:17.491786 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 01:15:17.495261 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 01:15:17.498651 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 01:15:17.505081 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 01:15:17.508569 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 01:15:17.512217 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3156 01:15:17.518138 1 0 28 | B1->B0 | 3b3b 3e3e | 1 0 | (0 0) (0 0)
3157 01:15:17.521863 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 01:15:17.524868 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 01:15:17.531692 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 01:15:17.534725 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 01:15:17.538344 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 01:15:17.545265 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 01:15:17.548721 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 01:15:17.551771 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3165 01:15:17.558388 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3166 01:15:17.561305 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 01:15:17.564823 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 01:15:17.571426 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 01:15:17.575146 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 01:15:17.578198 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 01:15:17.584985 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 01:15:17.588431 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 01:15:17.592096 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 01:15:17.595114 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 01:15:17.601364 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 01:15:17.605137 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 01:15:17.608641 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 01:15:17.614690 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 01:15:17.618390 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 01:15:17.621645 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3181 01:15:17.628390 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3182 01:15:17.631451 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 01:15:17.634573 Total UI for P1: 0, mck2ui 16
3184 01:15:17.638123 best dqsien dly found for B0: ( 1, 3, 30)
3185 01:15:17.641381 Total UI for P1: 0, mck2ui 16
3186 01:15:17.644472 best dqsien dly found for B1: ( 1, 3, 30)
3187 01:15:17.647859 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3188 01:15:17.651493 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3189 01:15:17.651932
3190 01:15:17.655012 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3191 01:15:17.657701 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3192 01:15:17.661656 [Gating] SW calibration Done
3193 01:15:17.662070 ==
3194 01:15:17.664423 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 01:15:17.668013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 01:15:17.671573 ==
3197 01:15:17.672024 RX Vref Scan: 0
3198 01:15:17.672361
3199 01:15:17.674766 RX Vref 0 -> 0, step: 1
3200 01:15:17.675190
3201 01:15:17.678159 RX Delay -40 -> 252, step: 8
3202 01:15:17.681341 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3203 01:15:17.684650 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3204 01:15:17.688134 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3205 01:15:17.691420 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3206 01:15:17.697868 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3207 01:15:17.701233 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3208 01:15:17.704587 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3209 01:15:17.707969 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3210 01:15:17.711284 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3211 01:15:17.714368 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3212 01:15:17.721122 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3213 01:15:17.724592 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3214 01:15:17.728042 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3215 01:15:17.731570 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3216 01:15:17.737897 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3217 01:15:17.741013 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3218 01:15:17.741571 ==
3219 01:15:17.744697 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 01:15:17.747817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 01:15:17.748271 ==
3222 01:15:17.748603 DQS Delay:
3223 01:15:17.751006 DQS0 = 0, DQS1 = 0
3224 01:15:17.751425 DQM Delay:
3225 01:15:17.754189 DQM0 = 114, DQM1 = 106
3226 01:15:17.754607 DQ Delay:
3227 01:15:17.757649 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3228 01:15:17.761207 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3229 01:15:17.764583 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3230 01:15:17.767799 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3231 01:15:17.768320
3232 01:15:17.771405
3233 01:15:17.771930 ==
3234 01:15:17.774904 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 01:15:17.777908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 01:15:17.778448 ==
3237 01:15:17.778795
3238 01:15:17.779142
3239 01:15:17.781120 TX Vref Scan disable
3240 01:15:17.781575 == TX Byte 0 ==
3241 01:15:17.787578 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3242 01:15:17.791389 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3243 01:15:17.791932 == TX Byte 1 ==
3244 01:15:17.797700 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3245 01:15:17.801069 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3246 01:15:17.801486 ==
3247 01:15:17.804481 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 01:15:17.807374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 01:15:17.807796 ==
3250 01:15:17.819988 TX Vref=22, minBit 8, minWin=24, winSum=408
3251 01:15:17.823805 TX Vref=24, minBit 8, minWin=24, winSum=410
3252 01:15:17.827167 TX Vref=26, minBit 8, minWin=24, winSum=417
3253 01:15:17.830457 TX Vref=28, minBit 9, minWin=25, winSum=422
3254 01:15:17.833809 TX Vref=30, minBit 9, minWin=24, winSum=425
3255 01:15:17.836960 TX Vref=32, minBit 9, minWin=25, winSum=423
3256 01:15:17.843606 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 32
3257 01:15:17.844161
3258 01:15:17.847015 Final TX Range 1 Vref 32
3259 01:15:17.847639
3260 01:15:17.848018 ==
3261 01:15:17.850874 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 01:15:17.853843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 01:15:17.854311 ==
3264 01:15:17.854679
3265 01:15:17.855015
3266 01:15:17.856907 TX Vref Scan disable
3267 01:15:17.860676 == TX Byte 0 ==
3268 01:15:17.863631 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3269 01:15:17.866612 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3270 01:15:17.870341 == TX Byte 1 ==
3271 01:15:17.873827 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3272 01:15:17.876878 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3273 01:15:17.877443
3274 01:15:17.880225 [DATLAT]
3275 01:15:17.880689 Freq=1200, CH1 RK0
3276 01:15:17.881058
3277 01:15:17.883954 DATLAT Default: 0xd
3278 01:15:17.884564 0, 0xFFFF, sum = 0
3279 01:15:17.887173 1, 0xFFFF, sum = 0
3280 01:15:17.887602 2, 0xFFFF, sum = 0
3281 01:15:17.889935 3, 0xFFFF, sum = 0
3282 01:15:17.890361 4, 0xFFFF, sum = 0
3283 01:15:17.893208 5, 0xFFFF, sum = 0
3284 01:15:17.893683 6, 0xFFFF, sum = 0
3285 01:15:17.896923 7, 0xFFFF, sum = 0
3286 01:15:17.897345 8, 0xFFFF, sum = 0
3287 01:15:17.900697 9, 0xFFFF, sum = 0
3288 01:15:17.903686 10, 0xFFFF, sum = 0
3289 01:15:17.904325 11, 0xFFFF, sum = 0
3290 01:15:17.906567 12, 0x0, sum = 1
3291 01:15:17.906995 13, 0x0, sum = 2
3292 01:15:17.907335 14, 0x0, sum = 3
3293 01:15:17.909684 15, 0x0, sum = 4
3294 01:15:17.910108 best_step = 13
3295 01:15:17.910439
3296 01:15:17.913258 ==
3297 01:15:17.913707 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 01:15:17.919781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 01:15:17.920201 ==
3300 01:15:17.920532 RX Vref Scan: 1
3301 01:15:17.920847
3302 01:15:17.923093 Set Vref Range= 32 -> 127
3303 01:15:17.923508
3304 01:15:17.926518 RX Vref 32 -> 127, step: 1
3305 01:15:17.926935
3306 01:15:17.929815 RX Delay -21 -> 252, step: 4
3307 01:15:17.930230
3308 01:15:17.933239 Set Vref, RX VrefLevel [Byte0]: 32
3309 01:15:17.936711 [Byte1]: 32
3310 01:15:17.937228
3311 01:15:17.940307 Set Vref, RX VrefLevel [Byte0]: 33
3312 01:15:17.943694 [Byte1]: 33
3313 01:15:17.944214
3314 01:15:17.946896 Set Vref, RX VrefLevel [Byte0]: 34
3315 01:15:17.949945 [Byte1]: 34
3316 01:15:17.954411
3317 01:15:17.954944 Set Vref, RX VrefLevel [Byte0]: 35
3318 01:15:17.957229 [Byte1]: 35
3319 01:15:17.961983
3320 01:15:17.962399 Set Vref, RX VrefLevel [Byte0]: 36
3321 01:15:17.965872 [Byte1]: 36
3322 01:15:17.970365
3323 01:15:17.970889 Set Vref, RX VrefLevel [Byte0]: 37
3324 01:15:17.973351 [Byte1]: 37
3325 01:15:17.978425
3326 01:15:17.978959 Set Vref, RX VrefLevel [Byte0]: 38
3327 01:15:17.980847 [Byte1]: 38
3328 01:15:17.985888
3329 01:15:17.986424 Set Vref, RX VrefLevel [Byte0]: 39
3330 01:15:17.992488 [Byte1]: 39
3331 01:15:17.993039
3332 01:15:17.995794 Set Vref, RX VrefLevel [Byte0]: 40
3333 01:15:17.999167 [Byte1]: 40
3334 01:15:17.999716
3335 01:15:18.002145 Set Vref, RX VrefLevel [Byte0]: 41
3336 01:15:18.005711 [Byte1]: 41
3337 01:15:18.009740
3338 01:15:18.010288 Set Vref, RX VrefLevel [Byte0]: 42
3339 01:15:18.013192 [Byte1]: 42
3340 01:15:18.017858
3341 01:15:18.018404 Set Vref, RX VrefLevel [Byte0]: 43
3342 01:15:18.020708 [Byte1]: 43
3343 01:15:18.025813
3344 01:15:18.026358 Set Vref, RX VrefLevel [Byte0]: 44
3345 01:15:18.028935 [Byte1]: 44
3346 01:15:18.033296
3347 01:15:18.033892 Set Vref, RX VrefLevel [Byte0]: 45
3348 01:15:18.037314 [Byte1]: 45
3349 01:15:18.041489
3350 01:15:18.042120 Set Vref, RX VrefLevel [Byte0]: 46
3351 01:15:18.044745 [Byte1]: 46
3352 01:15:18.049182
3353 01:15:18.049721 Set Vref, RX VrefLevel [Byte0]: 47
3354 01:15:18.052645 [Byte1]: 47
3355 01:15:18.057407
3356 01:15:18.057964 Set Vref, RX VrefLevel [Byte0]: 48
3357 01:15:18.060878 [Byte1]: 48
3358 01:15:18.065034
3359 01:15:18.065489 Set Vref, RX VrefLevel [Byte0]: 49
3360 01:15:18.068683 [Byte1]: 49
3361 01:15:18.073294
3362 01:15:18.073896 Set Vref, RX VrefLevel [Byte0]: 50
3363 01:15:18.076768 [Byte1]: 50
3364 01:15:18.081040
3365 01:15:18.081505 Set Vref, RX VrefLevel [Byte0]: 51
3366 01:15:18.084499 [Byte1]: 51
3367 01:15:18.089151
3368 01:15:18.089752 Set Vref, RX VrefLevel [Byte0]: 52
3369 01:15:18.092211 [Byte1]: 52
3370 01:15:18.096482
3371 01:15:18.097130 Set Vref, RX VrefLevel [Byte0]: 53
3372 01:15:18.100388 [Byte1]: 53
3373 01:15:18.105219
3374 01:15:18.105843 Set Vref, RX VrefLevel [Byte0]: 54
3375 01:15:18.108360 [Byte1]: 54
3376 01:15:18.112915
3377 01:15:18.113484 Set Vref, RX VrefLevel [Byte0]: 55
3378 01:15:18.116336 [Byte1]: 55
3379 01:15:18.120808
3380 01:15:18.121369 Set Vref, RX VrefLevel [Byte0]: 56
3381 01:15:18.124380 [Byte1]: 56
3382 01:15:18.128950
3383 01:15:18.129572 Set Vref, RX VrefLevel [Byte0]: 57
3384 01:15:18.131861 [Byte1]: 57
3385 01:15:18.136357
3386 01:15:18.136919 Set Vref, RX VrefLevel [Byte0]: 58
3387 01:15:18.140289 [Byte1]: 58
3388 01:15:18.144105
3389 01:15:18.144669 Set Vref, RX VrefLevel [Byte0]: 59
3390 01:15:18.147633 [Byte1]: 59
3391 01:15:18.152249
3392 01:15:18.152818 Set Vref, RX VrefLevel [Byte0]: 60
3393 01:15:18.155608 [Byte1]: 60
3394 01:15:18.160825
3395 01:15:18.161397 Set Vref, RX VrefLevel [Byte0]: 61
3396 01:15:18.163750 [Byte1]: 61
3397 01:15:18.168536
3398 01:15:18.169094 Set Vref, RX VrefLevel [Byte0]: 62
3399 01:15:18.171458 [Byte1]: 62
3400 01:15:18.176417
3401 01:15:18.176975 Set Vref, RX VrefLevel [Byte0]: 63
3402 01:15:18.179473 [Byte1]: 63
3403 01:15:18.184079
3404 01:15:18.184554 Set Vref, RX VrefLevel [Byte0]: 64
3405 01:15:18.187057 [Byte1]: 64
3406 01:15:18.192137
3407 01:15:18.192702 Set Vref, RX VrefLevel [Byte0]: 65
3408 01:15:18.195190 [Byte1]: 65
3409 01:15:18.199965
3410 01:15:18.200439 Set Vref, RX VrefLevel [Byte0]: 66
3411 01:15:18.203354 [Byte1]: 66
3412 01:15:18.208192
3413 01:15:18.208761 Set Vref, RX VrefLevel [Byte0]: 67
3414 01:15:18.211089 [Byte1]: 67
3415 01:15:18.215519
3416 01:15:18.216093 Set Vref, RX VrefLevel [Byte0]: 68
3417 01:15:18.218497 [Byte1]: 68
3418 01:15:18.223714
3419 01:15:18.224287 Set Vref, RX VrefLevel [Byte0]: 69
3420 01:15:18.227084 [Byte1]: 69
3421 01:15:18.231929
3422 01:15:18.232490 Final RX Vref Byte 0 = 59 to rank0
3423 01:15:18.234451 Final RX Vref Byte 1 = 43 to rank0
3424 01:15:18.238247 Final RX Vref Byte 0 = 59 to rank1
3425 01:15:18.241429 Final RX Vref Byte 1 = 43 to rank1==
3426 01:15:18.245008 Dram Type= 6, Freq= 0, CH_1, rank 0
3427 01:15:18.251461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 01:15:18.252042 ==
3429 01:15:18.252531 DQS Delay:
3430 01:15:18.252982 DQS0 = 0, DQS1 = 0
3431 01:15:18.254651 DQM Delay:
3432 01:15:18.255195 DQM0 = 115, DQM1 = 104
3433 01:15:18.258224 DQ Delay:
3434 01:15:18.261488 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =112
3435 01:15:18.264635 DQ4 =112, DQ5 =126, DQ6 =128, DQ7 =112
3436 01:15:18.268415 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =96
3437 01:15:18.271649 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3438 01:15:18.272211
3439 01:15:18.272576
3440 01:15:18.277834 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3441 01:15:18.281217 CH1 RK0: MR19=303, MR18=F0F8
3442 01:15:18.288221 CH1_RK0: MR19=0x303, MR18=0xF0F8, DQSOSC=413, MR23=63, INC=38, DEC=25
3443 01:15:18.288791
3444 01:15:18.291340 ----->DramcWriteLeveling(PI) begin...
3445 01:15:18.291908 ==
3446 01:15:18.294876 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 01:15:18.297591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 01:15:18.301464 ==
3449 01:15:18.302126 Write leveling (Byte 0): 26 => 26
3450 01:15:18.304888 Write leveling (Byte 1): 27 => 27
3451 01:15:18.307585 DramcWriteLeveling(PI) end<-----
3452 01:15:18.308063
3453 01:15:18.308432 ==
3454 01:15:18.311363 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 01:15:18.317988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 01:15:18.318592 ==
3457 01:15:18.318970 [Gating] SW mode calibration
3458 01:15:18.327874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3459 01:15:18.331158 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3460 01:15:18.334488 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3461 01:15:18.341242 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 01:15:18.345034 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 01:15:18.347742 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 01:15:18.354344 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 01:15:18.357882 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3466 01:15:18.361092 0 15 24 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
3467 01:15:18.367879 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3468 01:15:18.371369 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 01:15:18.374781 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 01:15:18.381391 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 01:15:18.384207 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 01:15:18.387817 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 01:15:18.394505 1 0 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3474 01:15:18.397448 1 0 24 | B1->B0 | 2727 4343 | 0 0 | (0 0) (0 0)
3475 01:15:18.401357 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3476 01:15:18.407880 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 01:15:18.410530 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 01:15:18.414363 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 01:15:18.421079 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 01:15:18.424208 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 01:15:18.426804 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 01:15:18.433678 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3483 01:15:18.437063 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 01:15:18.440742 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 01:15:18.447190 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 01:15:18.451019 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 01:15:18.453543 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 01:15:18.460854 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 01:15:18.463336 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 01:15:18.467004 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 01:15:18.474066 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 01:15:18.476618 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 01:15:18.480425 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 01:15:18.486610 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 01:15:18.489971 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 01:15:18.493253 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 01:15:18.500082 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 01:15:18.503554 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3499 01:15:18.507128 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3500 01:15:18.510135 Total UI for P1: 0, mck2ui 16
3501 01:15:18.513918 best dqsien dly found for B0: ( 1, 3, 24)
3502 01:15:18.520196 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 01:15:18.520766 Total UI for P1: 0, mck2ui 16
3504 01:15:18.523525 best dqsien dly found for B1: ( 1, 3, 26)
3505 01:15:18.530091 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3506 01:15:18.533259 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3507 01:15:18.533767
3508 01:15:18.536522 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3509 01:15:18.539897 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3510 01:15:18.543712 [Gating] SW calibration Done
3511 01:15:18.544293 ==
3512 01:15:18.546271 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 01:15:18.549464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 01:15:18.549974 ==
3515 01:15:18.553078 RX Vref Scan: 0
3516 01:15:18.553687
3517 01:15:18.554066 RX Vref 0 -> 0, step: 1
3518 01:15:18.554414
3519 01:15:18.556116 RX Delay -40 -> 252, step: 8
3520 01:15:18.559750 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3521 01:15:18.566009 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3522 01:15:18.569111 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3523 01:15:18.573074 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3524 01:15:18.576194 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3525 01:15:18.579775 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3526 01:15:18.586066 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3527 01:15:18.589242 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3528 01:15:18.592675 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3529 01:15:18.595925 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3530 01:15:18.598694 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3531 01:15:18.605802 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3532 01:15:18.609014 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3533 01:15:18.612252 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3534 01:15:18.615573 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3535 01:15:18.622027 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3536 01:15:18.622649 ==
3537 01:15:18.625600 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 01:15:18.629385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 01:15:18.629977 ==
3540 01:15:18.630323 DQS Delay:
3541 01:15:18.632224 DQS0 = 0, DQS1 = 0
3542 01:15:18.632742 DQM Delay:
3543 01:15:18.635822 DQM0 = 110, DQM1 = 105
3544 01:15:18.636343 DQ Delay:
3545 01:15:18.638317 DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =107
3546 01:15:18.641975 DQ4 =107, DQ5 =123, DQ6 =123, DQ7 =107
3547 01:15:18.645456 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
3548 01:15:18.648667 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =115
3549 01:15:18.649212
3550 01:15:18.649621
3551 01:15:18.649939 ==
3552 01:15:18.651868 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 01:15:18.658605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 01:15:18.659025 ==
3555 01:15:18.659353
3556 01:15:18.659660
3557 01:15:18.659958 TX Vref Scan disable
3558 01:15:18.662304 == TX Byte 0 ==
3559 01:15:18.665419 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3560 01:15:18.672072 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3561 01:15:18.672592 == TX Byte 1 ==
3562 01:15:18.675369 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3563 01:15:18.681856 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3564 01:15:18.682436 ==
3565 01:15:18.685237 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 01:15:18.688975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 01:15:18.689589 ==
3568 01:15:18.700247 TX Vref=22, minBit 9, minWin=25, winSum=420
3569 01:15:18.703057 TX Vref=24, minBit 0, minWin=26, winSum=422
3570 01:15:18.706623 TX Vref=26, minBit 3, minWin=26, winSum=429
3571 01:15:18.710047 TX Vref=28, minBit 9, minWin=26, winSum=432
3572 01:15:18.713495 TX Vref=30, minBit 9, minWin=26, winSum=433
3573 01:15:18.719964 TX Vref=32, minBit 1, minWin=26, winSum=431
3574 01:15:18.723075 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3575 01:15:18.723589
3576 01:15:18.726101 Final TX Range 1 Vref 30
3577 01:15:18.726593
3578 01:15:18.726976 ==
3579 01:15:18.729766 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 01:15:18.733108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 01:15:18.735953 ==
3582 01:15:18.736371
3583 01:15:18.736704
3584 01:15:18.737024 TX Vref Scan disable
3585 01:15:18.739332 == TX Byte 0 ==
3586 01:15:18.743210 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3587 01:15:18.749350 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3588 01:15:18.749959 == TX Byte 1 ==
3589 01:15:18.752603 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3590 01:15:18.759511 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3591 01:15:18.760030
3592 01:15:18.760364 [DATLAT]
3593 01:15:18.760682 Freq=1200, CH1 RK1
3594 01:15:18.760985
3595 01:15:18.762704 DATLAT Default: 0xd
3596 01:15:18.763183 0, 0xFFFF, sum = 0
3597 01:15:18.765608 1, 0xFFFF, sum = 0
3598 01:15:18.768903 2, 0xFFFF, sum = 0
3599 01:15:18.769505 3, 0xFFFF, sum = 0
3600 01:15:18.772405 4, 0xFFFF, sum = 0
3601 01:15:18.772830 5, 0xFFFF, sum = 0
3602 01:15:18.776295 6, 0xFFFF, sum = 0
3603 01:15:18.776828 7, 0xFFFF, sum = 0
3604 01:15:18.779145 8, 0xFFFF, sum = 0
3605 01:15:18.779569 9, 0xFFFF, sum = 0
3606 01:15:18.782374 10, 0xFFFF, sum = 0
3607 01:15:18.782800 11, 0xFFFF, sum = 0
3608 01:15:18.785609 12, 0x0, sum = 1
3609 01:15:18.786067 13, 0x0, sum = 2
3610 01:15:18.789309 14, 0x0, sum = 3
3611 01:15:18.789779 15, 0x0, sum = 4
3612 01:15:18.792421 best_step = 13
3613 01:15:18.792838
3614 01:15:18.793169 ==
3615 01:15:18.795671 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 01:15:18.798786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 01:15:18.799238 ==
3618 01:15:18.799578 RX Vref Scan: 0
3619 01:15:18.802425
3620 01:15:18.802863 RX Vref 0 -> 0, step: 1
3621 01:15:18.803255
3622 01:15:18.806001 RX Delay -21 -> 252, step: 4
3623 01:15:18.812410 iDelay=195, Bit 0, Center 116 (43 ~ 190) 148
3624 01:15:18.816053 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3625 01:15:18.819474 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3626 01:15:18.822070 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3627 01:15:18.825394 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3628 01:15:18.832875 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3629 01:15:18.835476 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3630 01:15:18.838701 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3631 01:15:18.842032 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3632 01:15:18.845370 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3633 01:15:18.851955 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3634 01:15:18.855329 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3635 01:15:18.858933 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3636 01:15:18.861591 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3637 01:15:18.865070 iDelay=195, Bit 14, Center 118 (59 ~ 178) 120
3638 01:15:18.872168 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3639 01:15:18.872589 ==
3640 01:15:18.875321 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 01:15:18.878441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 01:15:18.878972 ==
3643 01:15:18.879309 DQS Delay:
3644 01:15:18.881688 DQS0 = 0, DQS1 = 0
3645 01:15:18.882107 DQM Delay:
3646 01:15:18.885198 DQM0 = 112, DQM1 = 108
3647 01:15:18.885771 DQ Delay:
3648 01:15:18.888713 DQ0 =116, DQ1 =108, DQ2 =102, DQ3 =108
3649 01:15:18.891816 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3650 01:15:18.894869 DQ8 =94, DQ9 =100, DQ10 =110, DQ11 =100
3651 01:15:18.898379 DQ12 =116, DQ13 =114, DQ14 =118, DQ15 =114
3652 01:15:18.898801
3653 01:15:18.901593
3654 01:15:18.908259 [DQSOSCAuto] RK1, (LSB)MR18= 0xf808, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3655 01:15:18.911913 CH1 RK1: MR19=304, MR18=F808
3656 01:15:18.918153 CH1_RK1: MR19=0x304, MR18=0xF808, DQSOSC=406, MR23=63, INC=39, DEC=26
3657 01:15:18.921876 [RxdqsGatingPostProcess] freq 1200
3658 01:15:18.924620 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3659 01:15:18.928385 best DQS0 dly(2T, 0.5T) = (0, 11)
3660 01:15:18.931418 best DQS1 dly(2T, 0.5T) = (0, 11)
3661 01:15:18.934816 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3662 01:15:18.938171 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3663 01:15:18.942005 best DQS0 dly(2T, 0.5T) = (0, 11)
3664 01:15:18.945074 best DQS1 dly(2T, 0.5T) = (0, 11)
3665 01:15:18.947807 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3666 01:15:18.951652 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3667 01:15:18.954862 Pre-setting of DQS Precalculation
3668 01:15:18.958590 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3669 01:15:18.964727 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3670 01:15:18.974452 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3671 01:15:18.974981
3672 01:15:18.975315
3673 01:15:18.977851 [Calibration Summary] 2400 Mbps
3674 01:15:18.978272 CH 0, Rank 0
3675 01:15:18.981623 SW Impedance : PASS
3676 01:15:18.982141 DUTY Scan : NO K
3677 01:15:18.984575 ZQ Calibration : PASS
3678 01:15:18.987842 Jitter Meter : NO K
3679 01:15:18.988261 CBT Training : PASS
3680 01:15:18.990798 Write leveling : PASS
3681 01:15:18.991226 RX DQS gating : PASS
3682 01:15:18.994332 RX DQ/DQS(RDDQC) : PASS
3683 01:15:18.997598 TX DQ/DQS : PASS
3684 01:15:18.998025 RX DATLAT : PASS
3685 01:15:19.000828 RX DQ/DQS(Engine): PASS
3686 01:15:19.004651 TX OE : NO K
3687 01:15:19.005162 All Pass.
3688 01:15:19.005494
3689 01:15:19.005853 CH 0, Rank 1
3690 01:15:19.007289 SW Impedance : PASS
3691 01:15:19.010742 DUTY Scan : NO K
3692 01:15:19.011260 ZQ Calibration : PASS
3693 01:15:19.014077 Jitter Meter : NO K
3694 01:15:19.017087 CBT Training : PASS
3695 01:15:19.017498 Write leveling : PASS
3696 01:15:19.020977 RX DQS gating : PASS
3697 01:15:19.024482 RX DQ/DQS(RDDQC) : PASS
3698 01:15:19.024997 TX DQ/DQS : PASS
3699 01:15:19.027531 RX DATLAT : PASS
3700 01:15:19.030734 RX DQ/DQS(Engine): PASS
3701 01:15:19.031154 TX OE : NO K
3702 01:15:19.033603 All Pass.
3703 01:15:19.034018
3704 01:15:19.034347 CH 1, Rank 0
3705 01:15:19.037696 SW Impedance : PASS
3706 01:15:19.038202 DUTY Scan : NO K
3707 01:15:19.040375 ZQ Calibration : PASS
3708 01:15:19.044148 Jitter Meter : NO K
3709 01:15:19.044658 CBT Training : PASS
3710 01:15:19.047499 Write leveling : PASS
3711 01:15:19.050095 RX DQS gating : PASS
3712 01:15:19.050676 RX DQ/DQS(RDDQC) : PASS
3713 01:15:19.053733 TX DQ/DQS : PASS
3714 01:15:19.057097 RX DATLAT : PASS
3715 01:15:19.057628 RX DQ/DQS(Engine): PASS
3716 01:15:19.060342 TX OE : NO K
3717 01:15:19.060855 All Pass.
3718 01:15:19.061187
3719 01:15:19.063784 CH 1, Rank 1
3720 01:15:19.064198 SW Impedance : PASS
3721 01:15:19.066654 DUTY Scan : NO K
3722 01:15:19.067072 ZQ Calibration : PASS
3723 01:15:19.070122 Jitter Meter : NO K
3724 01:15:19.074016 CBT Training : PASS
3725 01:15:19.074529 Write leveling : PASS
3726 01:15:19.076960 RX DQS gating : PASS
3727 01:15:19.080448 RX DQ/DQS(RDDQC) : PASS
3728 01:15:19.080969 TX DQ/DQS : PASS
3729 01:15:19.083653 RX DATLAT : PASS
3730 01:15:19.087077 RX DQ/DQS(Engine): PASS
3731 01:15:19.087516 TX OE : NO K
3732 01:15:19.089856 All Pass.
3733 01:15:19.090279
3734 01:15:19.090612 DramC Write-DBI off
3735 01:15:19.093484 PER_BANK_REFRESH: Hybrid Mode
3736 01:15:19.094050 TX_TRACKING: ON
3737 01:15:19.103577 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3738 01:15:19.106924 [FAST_K] Save calibration result to emmc
3739 01:15:19.110036 dramc_set_vcore_voltage set vcore to 650000
3740 01:15:19.113435 Read voltage for 600, 5
3741 01:15:19.113908 Vio18 = 0
3742 01:15:19.116659 Vcore = 650000
3743 01:15:19.117369 Vdram = 0
3744 01:15:19.117780 Vddq = 0
3745 01:15:19.120006 Vmddr = 0
3746 01:15:19.123272 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3747 01:15:19.129909 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3748 01:15:19.130425 MEM_TYPE=3, freq_sel=19
3749 01:15:19.133478 sv_algorithm_assistance_LP4_1600
3750 01:15:19.139785 ============ PULL DRAM RESETB DOWN ============
3751 01:15:19.143100 ========== PULL DRAM RESETB DOWN end =========
3752 01:15:19.146181 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3753 01:15:19.149414 ===================================
3754 01:15:19.153049 LPDDR4 DRAM CONFIGURATION
3755 01:15:19.156684 ===================================
3756 01:15:19.159351 EX_ROW_EN[0] = 0x0
3757 01:15:19.159771 EX_ROW_EN[1] = 0x0
3758 01:15:19.162757 LP4Y_EN = 0x0
3759 01:15:19.163278 WORK_FSP = 0x0
3760 01:15:19.166049 WL = 0x2
3761 01:15:19.166540 RL = 0x2
3762 01:15:19.169259 BL = 0x2
3763 01:15:19.169708 RPST = 0x0
3764 01:15:19.173070 RD_PRE = 0x0
3765 01:15:19.173633 WR_PRE = 0x1
3766 01:15:19.175681 WR_PST = 0x0
3767 01:15:19.176099 DBI_WR = 0x0
3768 01:15:19.179662 DBI_RD = 0x0
3769 01:15:19.180179 OTF = 0x1
3770 01:15:19.182467 ===================================
3771 01:15:19.186068 ===================================
3772 01:15:19.189441 ANA top config
3773 01:15:19.193028 ===================================
3774 01:15:19.196059 DLL_ASYNC_EN = 0
3775 01:15:19.196579 ALL_SLAVE_EN = 1
3776 01:15:19.199143 NEW_RANK_MODE = 1
3777 01:15:19.202676 DLL_IDLE_MODE = 1
3778 01:15:19.205802 LP45_APHY_COMB_EN = 1
3779 01:15:19.206225 TX_ODT_DIS = 1
3780 01:15:19.208924 NEW_8X_MODE = 1
3781 01:15:19.212434 ===================================
3782 01:15:19.216176 ===================================
3783 01:15:19.219596 data_rate = 1200
3784 01:15:19.222621 CKR = 1
3785 01:15:19.226096 DQ_P2S_RATIO = 8
3786 01:15:19.228731 ===================================
3787 01:15:19.232765 CA_P2S_RATIO = 8
3788 01:15:19.235530 DQ_CA_OPEN = 0
3789 01:15:19.235950 DQ_SEMI_OPEN = 0
3790 01:15:19.238605 CA_SEMI_OPEN = 0
3791 01:15:19.241840 CA_FULL_RATE = 0
3792 01:15:19.245452 DQ_CKDIV4_EN = 1
3793 01:15:19.248918 CA_CKDIV4_EN = 1
3794 01:15:19.252121 CA_PREDIV_EN = 0
3795 01:15:19.252649 PH8_DLY = 0
3796 01:15:19.255396 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3797 01:15:19.258871 DQ_AAMCK_DIV = 4
3798 01:15:19.261756 CA_AAMCK_DIV = 4
3799 01:15:19.265574 CA_ADMCK_DIV = 4
3800 01:15:19.268739 DQ_TRACK_CA_EN = 0
3801 01:15:19.269173 CA_PICK = 600
3802 01:15:19.271640 CA_MCKIO = 600
3803 01:15:19.275228 MCKIO_SEMI = 0
3804 01:15:19.278311 PLL_FREQ = 2288
3805 01:15:19.281739 DQ_UI_PI_RATIO = 32
3806 01:15:19.284976 CA_UI_PI_RATIO = 0
3807 01:15:19.288175 ===================================
3808 01:15:19.291726 ===================================
3809 01:15:19.292282 memory_type:LPDDR4
3810 01:15:19.295321 GP_NUM : 10
3811 01:15:19.298511 SRAM_EN : 1
3812 01:15:19.298929 MD32_EN : 0
3813 01:15:19.301645 ===================================
3814 01:15:19.304854 [ANA_INIT] >>>>>>>>>>>>>>
3815 01:15:19.307757 <<<<<< [CONFIGURE PHASE]: ANA_TX
3816 01:15:19.311411 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3817 01:15:19.314827 ===================================
3818 01:15:19.317799 data_rate = 1200,PCW = 0X5800
3819 01:15:19.321673 ===================================
3820 01:15:19.325000 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3821 01:15:19.331202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 01:15:19.334168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3823 01:15:19.341132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3824 01:15:19.344440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3825 01:15:19.347688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3826 01:15:19.348243 [ANA_INIT] flow start
3827 01:15:19.350935 [ANA_INIT] PLL >>>>>>>>
3828 01:15:19.354438 [ANA_INIT] PLL <<<<<<<<
3829 01:15:19.354963 [ANA_INIT] MIDPI >>>>>>>>
3830 01:15:19.357628 [ANA_INIT] MIDPI <<<<<<<<
3831 01:15:19.360773 [ANA_INIT] DLL >>>>>>>>
3832 01:15:19.361192 [ANA_INIT] flow end
3833 01:15:19.367240 ============ LP4 DIFF to SE enter ============
3834 01:15:19.371030 ============ LP4 DIFF to SE exit ============
3835 01:15:19.374398 [ANA_INIT] <<<<<<<<<<<<<
3836 01:15:19.377571 [Flow] Enable top DCM control >>>>>
3837 01:15:19.380919 [Flow] Enable top DCM control <<<<<
3838 01:15:19.381446 Enable DLL master slave shuffle
3839 01:15:19.387091 ==============================================================
3840 01:15:19.390896 Gating Mode config
3841 01:15:19.394068 ==============================================================
3842 01:15:19.397385 Config description:
3843 01:15:19.407527 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3844 01:15:19.414379 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3845 01:15:19.417241 SELPH_MODE 0: By rank 1: By Phase
3846 01:15:19.423731 ==============================================================
3847 01:15:19.427089 GAT_TRACK_EN = 1
3848 01:15:19.430191 RX_GATING_MODE = 2
3849 01:15:19.433784 RX_GATING_TRACK_MODE = 2
3850 01:15:19.437157 SELPH_MODE = 1
3851 01:15:19.437762 PICG_EARLY_EN = 1
3852 01:15:19.440585 VALID_LAT_VALUE = 1
3853 01:15:19.446885 ==============================================================
3854 01:15:19.450111 Enter into Gating configuration >>>>
3855 01:15:19.453358 Exit from Gating configuration <<<<
3856 01:15:19.457205 Enter into DVFS_PRE_config >>>>>
3857 01:15:19.467067 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3858 01:15:19.470173 Exit from DVFS_PRE_config <<<<<
3859 01:15:19.473466 Enter into PICG configuration >>>>
3860 01:15:19.476441 Exit from PICG configuration <<<<
3861 01:15:19.479763 [RX_INPUT] configuration >>>>>
3862 01:15:19.483116 [RX_INPUT] configuration <<<<<
3863 01:15:19.490016 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3864 01:15:19.492979 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3865 01:15:19.499460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 01:15:19.506088 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 01:15:19.512712 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3868 01:15:19.519290 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3869 01:15:19.522244 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3870 01:15:19.525924 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3871 01:15:19.529278 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3872 01:15:19.535900 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3873 01:15:19.539040 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3874 01:15:19.542351 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3875 01:15:19.546236 ===================================
3876 01:15:19.549469 LPDDR4 DRAM CONFIGURATION
3877 01:15:19.552085 ===================================
3878 01:15:19.555826 EX_ROW_EN[0] = 0x0
3879 01:15:19.556349 EX_ROW_EN[1] = 0x0
3880 01:15:19.559092 LP4Y_EN = 0x0
3881 01:15:19.559511 WORK_FSP = 0x0
3882 01:15:19.562101 WL = 0x2
3883 01:15:19.562631 RL = 0x2
3884 01:15:19.565974 BL = 0x2
3885 01:15:19.566497 RPST = 0x0
3886 01:15:19.568541 RD_PRE = 0x0
3887 01:15:19.568958 WR_PRE = 0x1
3888 01:15:19.572314 WR_PST = 0x0
3889 01:15:19.572833 DBI_WR = 0x0
3890 01:15:19.575568 DBI_RD = 0x0
3891 01:15:19.576092 OTF = 0x1
3892 01:15:19.578818 ===================================
3893 01:15:19.585340 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3894 01:15:19.588240 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3895 01:15:19.591889 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3896 01:15:19.595419 ===================================
3897 01:15:19.598087 LPDDR4 DRAM CONFIGURATION
3898 01:15:19.601610 ===================================
3899 01:15:19.604723 EX_ROW_EN[0] = 0x10
3900 01:15:19.605221 EX_ROW_EN[1] = 0x0
3901 01:15:19.608599 LP4Y_EN = 0x0
3902 01:15:19.609118 WORK_FSP = 0x0
3903 01:15:19.611290 WL = 0x2
3904 01:15:19.611831 RL = 0x2
3905 01:15:19.614570 BL = 0x2
3906 01:15:19.614988 RPST = 0x0
3907 01:15:19.617821 RD_PRE = 0x0
3908 01:15:19.618241 WR_PRE = 0x1
3909 01:15:19.621749 WR_PST = 0x0
3910 01:15:19.622266 DBI_WR = 0x0
3911 01:15:19.624860 DBI_RD = 0x0
3912 01:15:19.625278 OTF = 0x1
3913 01:15:19.627922 ===================================
3914 01:15:19.634341 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3915 01:15:19.639502 nWR fixed to 30
3916 01:15:19.642734 [ModeRegInit_LP4] CH0 RK0
3917 01:15:19.643259 [ModeRegInit_LP4] CH0 RK1
3918 01:15:19.646414 [ModeRegInit_LP4] CH1 RK0
3919 01:15:19.649499 [ModeRegInit_LP4] CH1 RK1
3920 01:15:19.650047 match AC timing 17
3921 01:15:19.655903 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3922 01:15:19.659261 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3923 01:15:19.662394 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3924 01:15:19.669385 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3925 01:15:19.672585 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3926 01:15:19.673108 ==
3927 01:15:19.675561 Dram Type= 6, Freq= 0, CH_0, rank 0
3928 01:15:19.679105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3929 01:15:19.679681 ==
3930 01:15:19.685490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3931 01:15:19.692399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3932 01:15:19.695718 [CA 0] Center 37 (7~67) winsize 61
3933 01:15:19.698577 [CA 1] Center 37 (7~67) winsize 61
3934 01:15:19.702106 [CA 2] Center 35 (5~65) winsize 61
3935 01:15:19.705692 [CA 3] Center 35 (5~65) winsize 61
3936 01:15:19.709098 [CA 4] Center 34 (4~65) winsize 62
3937 01:15:19.712511 [CA 5] Center 34 (4~65) winsize 62
3938 01:15:19.713050
3939 01:15:19.715574 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3940 01:15:19.715998
3941 01:15:19.718739 [CATrainingPosCal] consider 1 rank data
3942 01:15:19.722344 u2DelayCellTimex100 = 270/100 ps
3943 01:15:19.725662 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3944 01:15:19.728555 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3945 01:15:19.732169 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3946 01:15:19.735499 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3947 01:15:19.742193 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3948 01:15:19.745750 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
3949 01:15:19.746276
3950 01:15:19.748918 CA PerBit enable=1, Macro0, CA PI delay=34
3951 01:15:19.749579
3952 01:15:19.751906 [CBTSetCACLKResult] CA Dly = 34
3953 01:15:19.752326 CS Dly: 6 (0~37)
3954 01:15:19.752661 ==
3955 01:15:19.755227 Dram Type= 6, Freq= 0, CH_0, rank 1
3956 01:15:19.761616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 01:15:19.762042 ==
3958 01:15:19.765475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3959 01:15:19.771858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3960 01:15:19.775316 [CA 0] Center 37 (7~67) winsize 61
3961 01:15:19.778091 [CA 1] Center 36 (6~67) winsize 62
3962 01:15:19.781583 [CA 2] Center 35 (5~65) winsize 61
3963 01:15:19.784603 [CA 3] Center 35 (5~65) winsize 61
3964 01:15:19.788144 [CA 4] Center 34 (4~65) winsize 62
3965 01:15:19.791578 [CA 5] Center 33 (3~64) winsize 62
3966 01:15:19.792000
3967 01:15:19.795309 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3968 01:15:19.795836
3969 01:15:19.798559 [CATrainingPosCal] consider 2 rank data
3970 01:15:19.801710 u2DelayCellTimex100 = 270/100 ps
3971 01:15:19.805118 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3972 01:15:19.808360 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3973 01:15:19.814813 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3974 01:15:19.817937 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3975 01:15:19.821925 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3976 01:15:19.824543 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3977 01:15:19.825070
3978 01:15:19.827946 CA PerBit enable=1, Macro0, CA PI delay=34
3979 01:15:19.828483
3980 01:15:19.831834 [CBTSetCACLKResult] CA Dly = 34
3981 01:15:19.832358 CS Dly: 6 (0~37)
3982 01:15:19.834619
3983 01:15:19.838080 ----->DramcWriteLeveling(PI) begin...
3984 01:15:19.838611 ==
3985 01:15:19.841588 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 01:15:19.844517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 01:15:19.845044 ==
3988 01:15:19.848034 Write leveling (Byte 0): 32 => 32
3989 01:15:19.851136 Write leveling (Byte 1): 32 => 32
3990 01:15:19.854468 DramcWriteLeveling(PI) end<-----
3991 01:15:19.854992
3992 01:15:19.855324 ==
3993 01:15:19.858093 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 01:15:19.860902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 01:15:19.861429 ==
3996 01:15:19.864708 [Gating] SW mode calibration
3997 01:15:19.870829 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3998 01:15:19.877290 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3999 01:15:19.880810 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 01:15:19.883819 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 01:15:19.890872 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 01:15:19.893992 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
4003 01:15:19.897015 0 9 16 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
4004 01:15:19.903655 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 01:15:19.906952 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 01:15:19.910404 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 01:15:19.916947 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 01:15:19.920330 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 01:15:19.923971 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 01:15:19.930052 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4011 01:15:19.933693 0 10 16 | B1->B0 | 3030 3939 | 0 0 | (0 0) (0 0)
4012 01:15:19.936762 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 01:15:19.943394 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 01:15:19.946971 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 01:15:19.950083 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 01:15:19.957131 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 01:15:19.960323 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 01:15:19.963589 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 01:15:19.970194 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4020 01:15:19.973483 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 01:15:19.976648 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 01:15:19.983575 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 01:15:19.986530 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 01:15:19.990144 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 01:15:19.996392 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 01:15:19.999983 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 01:15:20.003445 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 01:15:20.009653 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 01:15:20.013086 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 01:15:20.016248 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 01:15:20.020117 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 01:15:20.026025 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 01:15:20.029805 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 01:15:20.033243 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 01:15:20.039483 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 01:15:20.042947 Total UI for P1: 0, mck2ui 16
4037 01:15:20.046412 best dqsien dly found for B0: ( 0, 13, 14)
4038 01:15:20.049284 Total UI for P1: 0, mck2ui 16
4039 01:15:20.052637 best dqsien dly found for B1: ( 0, 13, 14)
4040 01:15:20.055839 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4041 01:15:20.059460 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4042 01:15:20.059881
4043 01:15:20.062777 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4044 01:15:20.066265 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4045 01:15:20.069360 [Gating] SW calibration Done
4046 01:15:20.069916 ==
4047 01:15:20.073102 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 01:15:20.076600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 01:15:20.077123 ==
4050 01:15:20.079332 RX Vref Scan: 0
4051 01:15:20.079860
4052 01:15:20.082255 RX Vref 0 -> 0, step: 1
4053 01:15:20.082676
4054 01:15:20.083008 RX Delay -230 -> 252, step: 16
4055 01:15:20.089782 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4056 01:15:20.092337 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4057 01:15:20.095993 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4058 01:15:20.099557 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4059 01:15:20.105860 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4060 01:15:20.109270 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4061 01:15:20.112780 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4062 01:15:20.115676 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4063 01:15:20.122507 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4064 01:15:20.125670 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4065 01:15:20.128639 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4066 01:15:20.131997 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4067 01:15:20.138514 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4068 01:15:20.141817 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4069 01:15:20.145389 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4070 01:15:20.148817 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4071 01:15:20.149350 ==
4072 01:15:20.152160 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 01:15:20.158540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 01:15:20.159071 ==
4075 01:15:20.159410 DQS Delay:
4076 01:15:20.161882 DQS0 = 0, DQS1 = 0
4077 01:15:20.162406 DQM Delay:
4078 01:15:20.162807 DQM0 = 37, DQM1 = 27
4079 01:15:20.165292 DQ Delay:
4080 01:15:20.168753 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4081 01:15:20.171503 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4082 01:15:20.175160 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4083 01:15:20.178702 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4084 01:15:20.179224
4085 01:15:20.179555
4086 01:15:20.179865 ==
4087 01:15:20.181669 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 01:15:20.185055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 01:15:20.185479 ==
4090 01:15:20.185852
4091 01:15:20.186167
4092 01:15:20.188469 TX Vref Scan disable
4093 01:15:20.191431 == TX Byte 0 ==
4094 01:15:20.194489 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4095 01:15:20.198212 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4096 01:15:20.201585 == TX Byte 1 ==
4097 01:15:20.204583 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4098 01:15:20.207958 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4099 01:15:20.208481 ==
4100 01:15:20.211623 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 01:15:20.214432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 01:15:20.218094 ==
4103 01:15:20.218615
4104 01:15:20.218948
4105 01:15:20.219259 TX Vref Scan disable
4106 01:15:20.222210 == TX Byte 0 ==
4107 01:15:20.225070 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4108 01:15:20.231665 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4109 01:15:20.232177 == TX Byte 1 ==
4110 01:15:20.235094 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4111 01:15:20.241778 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4112 01:15:20.242318
4113 01:15:20.242726 [DATLAT]
4114 01:15:20.243047 Freq=600, CH0 RK0
4115 01:15:20.243355
4116 01:15:20.245051 DATLAT Default: 0x9
4117 01:15:20.245466 0, 0xFFFF, sum = 0
4118 01:15:20.248597 1, 0xFFFF, sum = 0
4119 01:15:20.249124 2, 0xFFFF, sum = 0
4120 01:15:20.251545 3, 0xFFFF, sum = 0
4121 01:15:20.255013 4, 0xFFFF, sum = 0
4122 01:15:20.255541 5, 0xFFFF, sum = 0
4123 01:15:20.258338 6, 0xFFFF, sum = 0
4124 01:15:20.258867 7, 0xFFFF, sum = 0
4125 01:15:20.261744 8, 0x0, sum = 1
4126 01:15:20.262171 9, 0x0, sum = 2
4127 01:15:20.262512 10, 0x0, sum = 3
4128 01:15:20.264944 11, 0x0, sum = 4
4129 01:15:20.265559 best_step = 9
4130 01:15:20.265916
4131 01:15:20.266230 ==
4132 01:15:20.268378 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 01:15:20.274762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 01:15:20.275285 ==
4135 01:15:20.275622 RX Vref Scan: 1
4136 01:15:20.275936
4137 01:15:20.278262 RX Vref 0 -> 0, step: 1
4138 01:15:20.278787
4139 01:15:20.281827 RX Delay -195 -> 252, step: 8
4140 01:15:20.282249
4141 01:15:20.284900 Set Vref, RX VrefLevel [Byte0]: 61
4142 01:15:20.288033 [Byte1]: 47
4143 01:15:20.288570
4144 01:15:20.291041 Final RX Vref Byte 0 = 61 to rank0
4145 01:15:20.294614 Final RX Vref Byte 1 = 47 to rank0
4146 01:15:20.298032 Final RX Vref Byte 0 = 61 to rank1
4147 01:15:20.301048 Final RX Vref Byte 1 = 47 to rank1==
4148 01:15:20.304686 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 01:15:20.308136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 01:15:20.308664 ==
4151 01:15:20.311752 DQS Delay:
4152 01:15:20.312277 DQS0 = 0, DQS1 = 0
4153 01:15:20.314387 DQM Delay:
4154 01:15:20.314813 DQM0 = 34, DQM1 = 28
4155 01:15:20.315147 DQ Delay:
4156 01:15:20.318048 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4157 01:15:20.321270 DQ4 =36, DQ5 =24, DQ6 =40, DQ7 =48
4158 01:15:20.324598 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4159 01:15:20.328177 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4160 01:15:20.328704
4161 01:15:20.329037
4162 01:15:20.337929 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4163 01:15:20.341209 CH0 RK0: MR19=808, MR18=3E3D
4164 01:15:20.347564 CH0_RK0: MR19=0x808, MR18=0x3E3D, DQSOSC=398, MR23=63, INC=165, DEC=110
4165 01:15:20.348079
4166 01:15:20.350674 ----->DramcWriteLeveling(PI) begin...
4167 01:15:20.351098 ==
4168 01:15:20.354001 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 01:15:20.357239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 01:15:20.357844 ==
4171 01:15:20.360577 Write leveling (Byte 0): 32 => 32
4172 01:15:20.363625 Write leveling (Byte 1): 32 => 32
4173 01:15:20.367253 DramcWriteLeveling(PI) end<-----
4174 01:15:20.367822
4175 01:15:20.368161 ==
4176 01:15:20.370468 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 01:15:20.374129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 01:15:20.374655 ==
4179 01:15:20.377662 [Gating] SW mode calibration
4180 01:15:20.384352 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4181 01:15:20.390475 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4182 01:15:20.393812 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 01:15:20.397372 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 01:15:20.403744 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 01:15:20.407052 0 9 12 | B1->B0 | 3333 3131 | 1 0 | (1 0) (0 0)
4186 01:15:20.410336 0 9 16 | B1->B0 | 3030 2525 | 1 0 | (1 1) (0 0)
4187 01:15:20.416811 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 01:15:20.420602 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 01:15:20.424019 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 01:15:20.430768 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 01:15:20.434006 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 01:15:20.437382 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 01:15:20.443406 0 10 12 | B1->B0 | 2525 3636 | 0 0 | (0 0) (1 1)
4194 01:15:20.447250 0 10 16 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
4195 01:15:20.450416 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 01:15:20.456958 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 01:15:20.459852 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 01:15:20.463262 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 01:15:20.469900 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 01:15:20.473337 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 01:15:20.476660 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 01:15:20.482830 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 01:15:20.486163 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 01:15:20.490019 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 01:15:20.496392 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 01:15:20.500341 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 01:15:20.502866 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 01:15:20.509614 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 01:15:20.513112 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 01:15:20.516090 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 01:15:20.523204 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 01:15:20.526043 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 01:15:20.529347 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 01:15:20.536311 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 01:15:20.539733 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 01:15:20.542435 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 01:15:20.549777 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4218 01:15:20.550308 Total UI for P1: 0, mck2ui 16
4219 01:15:20.556038 best dqsien dly found for B0: ( 0, 13, 10)
4220 01:15:20.559257 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4221 01:15:20.562168 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 01:15:20.565934 Total UI for P1: 0, mck2ui 16
4223 01:15:20.568957 best dqsien dly found for B1: ( 0, 13, 14)
4224 01:15:20.572605 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4225 01:15:20.575969 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4226 01:15:20.576507
4227 01:15:20.582323 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4228 01:15:20.585608 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4229 01:15:20.589091 [Gating] SW calibration Done
4230 01:15:20.589536 ==
4231 01:15:20.592174 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 01:15:20.595472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 01:15:20.595896 ==
4234 01:15:20.596231 RX Vref Scan: 0
4235 01:15:20.596546
4236 01:15:20.598924 RX Vref 0 -> 0, step: 1
4237 01:15:20.599455
4238 01:15:20.602342 RX Delay -230 -> 252, step: 16
4239 01:15:20.605607 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4240 01:15:20.608815 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4241 01:15:20.615564 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4242 01:15:20.618672 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4243 01:15:20.622207 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4244 01:15:20.625634 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4245 01:15:20.631935 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4246 01:15:20.635549 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4247 01:15:20.638406 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4248 01:15:20.641784 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4249 01:15:20.645273 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4250 01:15:20.652086 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4251 01:15:20.654812 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4252 01:15:20.658394 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4253 01:15:20.661931 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4254 01:15:20.668562 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4255 01:15:20.669072 ==
4256 01:15:20.671780 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 01:15:20.675251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 01:15:20.675770 ==
4259 01:15:20.676107 DQS Delay:
4260 01:15:20.678550 DQS0 = 0, DQS1 = 0
4261 01:15:20.679073 DQM Delay:
4262 01:15:20.681834 DQM0 = 36, DQM1 = 29
4263 01:15:20.682346 DQ Delay:
4264 01:15:20.684991 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4265 01:15:20.687998 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4266 01:15:20.691611 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4267 01:15:20.694389 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4268 01:15:20.694823
4269 01:15:20.695172
4270 01:15:20.695489 ==
4271 01:15:20.697616 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 01:15:20.701582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 01:15:20.704605 ==
4274 01:15:20.705126
4275 01:15:20.705460
4276 01:15:20.705827 TX Vref Scan disable
4277 01:15:20.707748 == TX Byte 0 ==
4278 01:15:20.711828 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4279 01:15:20.714836 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4280 01:15:20.718304 == TX Byte 1 ==
4281 01:15:20.720943 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4282 01:15:20.724919 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4283 01:15:20.727847 ==
4284 01:15:20.731475 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 01:15:20.734430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 01:15:20.734962 ==
4287 01:15:20.735301
4288 01:15:20.735609
4289 01:15:20.737788 TX Vref Scan disable
4290 01:15:20.738313 == TX Byte 0 ==
4291 01:15:20.744197 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4292 01:15:20.747370 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4293 01:15:20.747792 == TX Byte 1 ==
4294 01:15:20.754377 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4295 01:15:20.757752 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4296 01:15:20.758167
4297 01:15:20.758493 [DATLAT]
4298 01:15:20.761158 Freq=600, CH0 RK1
4299 01:15:20.761602
4300 01:15:20.761967 DATLAT Default: 0x9
4301 01:15:20.764164 0, 0xFFFF, sum = 0
4302 01:15:20.764585 1, 0xFFFF, sum = 0
4303 01:15:20.767464 2, 0xFFFF, sum = 0
4304 01:15:20.771217 3, 0xFFFF, sum = 0
4305 01:15:20.771740 4, 0xFFFF, sum = 0
4306 01:15:20.774737 5, 0xFFFF, sum = 0
4307 01:15:20.775264 6, 0xFFFF, sum = 0
4308 01:15:20.777669 7, 0xFFFF, sum = 0
4309 01:15:20.778249 8, 0x0, sum = 1
4310 01:15:20.778595 9, 0x0, sum = 2
4311 01:15:20.780808 10, 0x0, sum = 3
4312 01:15:20.781232 11, 0x0, sum = 4
4313 01:15:20.784369 best_step = 9
4314 01:15:20.784886
4315 01:15:20.785215 ==
4316 01:15:20.787548 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 01:15:20.791401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 01:15:20.791929 ==
4319 01:15:20.794108 RX Vref Scan: 0
4320 01:15:20.794647
4321 01:15:20.795005 RX Vref 0 -> 0, step: 1
4322 01:15:20.795324
4323 01:15:20.797331 RX Delay -195 -> 252, step: 8
4324 01:15:20.804714 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4325 01:15:20.807822 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4326 01:15:20.811048 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4327 01:15:20.814944 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4328 01:15:20.821354 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4329 01:15:20.824726 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4330 01:15:20.828566 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4331 01:15:20.832052 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4332 01:15:20.834751 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4333 01:15:20.841304 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4334 01:15:20.844286 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4335 01:15:20.848422 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4336 01:15:20.851263 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4337 01:15:20.858056 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4338 01:15:20.860911 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4339 01:15:20.864407 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4340 01:15:20.864933 ==
4341 01:15:20.867833 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 01:15:20.874245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 01:15:20.874771 ==
4344 01:15:20.875103 DQS Delay:
4345 01:15:20.878121 DQS0 = 0, DQS1 = 0
4346 01:15:20.878638 DQM Delay:
4347 01:15:20.878973 DQM0 = 34, DQM1 = 28
4348 01:15:20.881179 DQ Delay:
4349 01:15:20.883911 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4350 01:15:20.887665 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4351 01:15:20.890911 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4352 01:15:20.894379 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4353 01:15:20.895102
4354 01:15:20.895453
4355 01:15:20.900857 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4356 01:15:20.904134 CH0 RK1: MR19=808, MR18=6C3B
4357 01:15:20.910702 CH0_RK1: MR19=0x808, MR18=0x6C3B, DQSOSC=389, MR23=63, INC=173, DEC=115
4358 01:15:20.913828 [RxdqsGatingPostProcess] freq 600
4359 01:15:20.917179 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4360 01:15:20.920843 Pre-setting of DQS Precalculation
4361 01:15:20.926972 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4362 01:15:20.927393 ==
4363 01:15:20.931082 Dram Type= 6, Freq= 0, CH_1, rank 0
4364 01:15:20.933852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 01:15:20.934277 ==
4366 01:15:20.940167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4367 01:15:20.947207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4368 01:15:20.950609 [CA 0] Center 36 (6~66) winsize 61
4369 01:15:20.953593 [CA 1] Center 36 (6~66) winsize 61
4370 01:15:20.957034 [CA 2] Center 34 (4~65) winsize 62
4371 01:15:20.960221 [CA 3] Center 34 (4~65) winsize 62
4372 01:15:20.963445 [CA 4] Center 34 (4~65) winsize 62
4373 01:15:20.966932 [CA 5] Center 33 (3~64) winsize 62
4374 01:15:20.967458
4375 01:15:20.970147 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4376 01:15:20.970616
4377 01:15:20.973427 [CATrainingPosCal] consider 1 rank data
4378 01:15:20.976995 u2DelayCellTimex100 = 270/100 ps
4379 01:15:20.979856 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4380 01:15:20.983591 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4381 01:15:20.986971 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 01:15:20.989598 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4383 01:15:20.993078 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4384 01:15:20.996206 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4385 01:15:20.996628
4386 01:15:21.003341 CA PerBit enable=1, Macro0, CA PI delay=33
4387 01:15:21.003762
4388 01:15:21.004097 [CBTSetCACLKResult] CA Dly = 33
4389 01:15:21.006654 CS Dly: 4 (0~35)
4390 01:15:21.007175 ==
4391 01:15:21.009414 Dram Type= 6, Freq= 0, CH_1, rank 1
4392 01:15:21.012823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 01:15:21.013359 ==
4394 01:15:21.019985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4395 01:15:21.026275 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4396 01:15:21.029578 [CA 0] Center 36 (6~66) winsize 61
4397 01:15:21.032946 [CA 1] Center 35 (5~66) winsize 62
4398 01:15:21.036311 [CA 2] Center 34 (4~65) winsize 62
4399 01:15:21.039705 [CA 3] Center 34 (3~65) winsize 63
4400 01:15:21.043145 [CA 4] Center 34 (4~65) winsize 62
4401 01:15:21.046123 [CA 5] Center 33 (3~64) winsize 62
4402 01:15:21.046549
4403 01:15:21.049690 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4404 01:15:21.050437
4405 01:15:21.052492 [CATrainingPosCal] consider 2 rank data
4406 01:15:21.056663 u2DelayCellTimex100 = 270/100 ps
4407 01:15:21.059765 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4408 01:15:21.062741 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4409 01:15:21.066151 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 01:15:21.069451 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4411 01:15:21.072689 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4412 01:15:21.079260 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4413 01:15:21.079777
4414 01:15:21.082918 CA PerBit enable=1, Macro0, CA PI delay=33
4415 01:15:21.083445
4416 01:15:21.086173 [CBTSetCACLKResult] CA Dly = 33
4417 01:15:21.086594 CS Dly: 4 (0~36)
4418 01:15:21.086930
4419 01:15:21.089061 ----->DramcWriteLeveling(PI) begin...
4420 01:15:21.089488 ==
4421 01:15:21.092353 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 01:15:21.095723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 01:15:21.099192 ==
4424 01:15:21.099616 Write leveling (Byte 0): 31 => 31
4425 01:15:21.102453 Write leveling (Byte 1): 31 => 31
4426 01:15:21.105990 DramcWriteLeveling(PI) end<-----
4427 01:15:21.106409
4428 01:15:21.106741 ==
4429 01:15:21.109610 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 01:15:21.115867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 01:15:21.116296 ==
4432 01:15:21.119342 [Gating] SW mode calibration
4433 01:15:21.125829 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4434 01:15:21.128955 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4435 01:15:21.135736 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 01:15:21.138934 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 01:15:21.142548 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 01:15:21.149093 0 9 12 | B1->B0 | 3232 3030 | 1 1 | (1 0) (1 0)
4439 01:15:21.152523 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4440 01:15:21.155855 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 01:15:21.162057 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 01:15:21.165476 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 01:15:21.169234 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 01:15:21.175317 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 01:15:21.178668 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 01:15:21.182171 0 10 12 | B1->B0 | 2d2d 2f2f | 0 0 | (0 0) (0 0)
4447 01:15:21.188623 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 01:15:21.191725 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 01:15:21.194977 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 01:15:21.198342 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 01:15:21.205138 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 01:15:21.208566 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 01:15:21.215075 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 01:15:21.218534 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4455 01:15:21.221453 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4456 01:15:21.228476 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 01:15:21.231254 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 01:15:21.234849 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 01:15:21.241032 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 01:15:21.244563 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 01:15:21.248202 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 01:15:21.251851 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 01:15:21.258105 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 01:15:21.261555 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 01:15:21.264821 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 01:15:21.271527 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 01:15:21.274372 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 01:15:21.277798 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 01:15:21.284712 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 01:15:21.287436 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 01:15:21.290732 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 01:15:21.294360 Total UI for P1: 0, mck2ui 16
4473 01:15:21.297548 best dqsien dly found for B0: ( 0, 13, 14)
4474 01:15:21.300464 Total UI for P1: 0, mck2ui 16
4475 01:15:21.304284 best dqsien dly found for B1: ( 0, 13, 14)
4476 01:15:21.307622 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4477 01:15:21.314020 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4478 01:15:21.314539
4479 01:15:21.317410 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4480 01:15:21.320740 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4481 01:15:21.324182 [Gating] SW calibration Done
4482 01:15:21.324702 ==
4483 01:15:21.327652 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 01:15:21.331202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 01:15:21.331722 ==
4486 01:15:21.334326 RX Vref Scan: 0
4487 01:15:21.334744
4488 01:15:21.335079 RX Vref 0 -> 0, step: 1
4489 01:15:21.335391
4490 01:15:21.337159 RX Delay -230 -> 252, step: 16
4491 01:15:21.341028 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4492 01:15:21.347729 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4493 01:15:21.350217 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4494 01:15:21.354134 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4495 01:15:21.357116 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4496 01:15:21.363642 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4497 01:15:21.367072 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4498 01:15:21.370413 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4499 01:15:21.374051 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4500 01:15:21.377162 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4501 01:15:21.383799 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4502 01:15:21.386566 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4503 01:15:21.390172 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4504 01:15:21.393620 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4505 01:15:21.399931 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4506 01:15:21.403306 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4507 01:15:21.403730 ==
4508 01:15:21.406707 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 01:15:21.410220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 01:15:21.410643 ==
4511 01:15:21.413544 DQS Delay:
4512 01:15:21.413962 DQS0 = 0, DQS1 = 0
4513 01:15:21.414300 DQM Delay:
4514 01:15:21.416702 DQM0 = 38, DQM1 = 29
4515 01:15:21.417118 DQ Delay:
4516 01:15:21.420350 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4517 01:15:21.423147 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4518 01:15:21.426504 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4519 01:15:21.430043 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4520 01:15:21.430462
4521 01:15:21.430795
4522 01:15:21.431102 ==
4523 01:15:21.433609 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 01:15:21.440314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 01:15:21.440844 ==
4526 01:15:21.441182
4527 01:15:21.441499
4528 01:15:21.441844 TX Vref Scan disable
4529 01:15:21.443954 == TX Byte 0 ==
4530 01:15:21.447241 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4531 01:15:21.454151 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4532 01:15:21.454672 == TX Byte 1 ==
4533 01:15:21.457095 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4534 01:15:21.463764 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4535 01:15:21.464289 ==
4536 01:15:21.467054 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 01:15:21.470155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 01:15:21.470677 ==
4539 01:15:21.471014
4540 01:15:21.471477
4541 01:15:21.473352 TX Vref Scan disable
4542 01:15:21.476785 == TX Byte 0 ==
4543 01:15:21.480227 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4544 01:15:21.483753 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4545 01:15:21.487127 == TX Byte 1 ==
4546 01:15:21.490411 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4547 01:15:21.493667 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4548 01:15:21.494190
4549 01:15:21.494589 [DATLAT]
4550 01:15:21.496674 Freq=600, CH1 RK0
4551 01:15:21.497181
4552 01:15:21.497567 DATLAT Default: 0x9
4553 01:15:21.499881 0, 0xFFFF, sum = 0
4554 01:15:21.503111 1, 0xFFFF, sum = 0
4555 01:15:21.503641 2, 0xFFFF, sum = 0
4556 01:15:21.507005 3, 0xFFFF, sum = 0
4557 01:15:21.507534 4, 0xFFFF, sum = 0
4558 01:15:21.510264 5, 0xFFFF, sum = 0
4559 01:15:21.510691 6, 0xFFFF, sum = 0
4560 01:15:21.513033 7, 0xFFFF, sum = 0
4561 01:15:21.513457 8, 0x0, sum = 1
4562 01:15:21.516641 9, 0x0, sum = 2
4563 01:15:21.517066 10, 0x0, sum = 3
4564 01:15:21.517404 11, 0x0, sum = 4
4565 01:15:21.519659 best_step = 9
4566 01:15:21.520077
4567 01:15:21.520406 ==
4568 01:15:21.522955 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 01:15:21.526454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 01:15:21.526981 ==
4571 01:15:21.529864 RX Vref Scan: 1
4572 01:15:21.530419
4573 01:15:21.530764 RX Vref 0 -> 0, step: 1
4574 01:15:21.533082
4575 01:15:21.533639 RX Delay -195 -> 252, step: 8
4576 01:15:21.533983
4577 01:15:21.536642 Set Vref, RX VrefLevel [Byte0]: 59
4578 01:15:21.539892 [Byte1]: 43
4579 01:15:21.544158
4580 01:15:21.544679 Final RX Vref Byte 0 = 59 to rank0
4581 01:15:21.547708 Final RX Vref Byte 1 = 43 to rank0
4582 01:15:21.551214 Final RX Vref Byte 0 = 59 to rank1
4583 01:15:21.554566 Final RX Vref Byte 1 = 43 to rank1==
4584 01:15:21.557559 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 01:15:21.564491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 01:15:21.565019 ==
4587 01:15:21.565357 DQS Delay:
4588 01:15:21.567456 DQS0 = 0, DQS1 = 0
4589 01:15:21.567976 DQM Delay:
4590 01:15:21.568316 DQM0 = 38, DQM1 = 30
4591 01:15:21.570681 DQ Delay:
4592 01:15:21.574042 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4593 01:15:21.576964 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4594 01:15:21.580594 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =24
4595 01:15:21.584139 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4596 01:15:21.584788
4597 01:15:21.585132
4598 01:15:21.590416 [DQSOSCAuto] RK0, (LSB)MR18= 0x222f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4599 01:15:21.593599 CH1 RK0: MR19=808, MR18=222F
4600 01:15:21.600244 CH1_RK0: MR19=0x808, MR18=0x222F, DQSOSC=400, MR23=63, INC=163, DEC=109
4601 01:15:21.600670
4602 01:15:21.603234 ----->DramcWriteLeveling(PI) begin...
4603 01:15:21.603793 ==
4604 01:15:21.607118 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 01:15:21.610270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 01:15:21.610692 ==
4607 01:15:21.613568 Write leveling (Byte 0): 29 => 29
4608 01:15:21.616874 Write leveling (Byte 1): 29 => 29
4609 01:15:21.620364 DramcWriteLeveling(PI) end<-----
4610 01:15:21.620786
4611 01:15:21.621118 ==
4612 01:15:21.623512 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 01:15:21.626975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 01:15:21.630199 ==
4615 01:15:21.630625 [Gating] SW mode calibration
4616 01:15:21.636598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4617 01:15:21.644001 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4618 01:15:21.646454 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 01:15:21.653775 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4620 01:15:21.656619 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4621 01:15:21.659952 0 9 12 | B1->B0 | 3434 2d2d | 0 1 | (0 0) (1 1)
4622 01:15:21.666462 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4623 01:15:21.669944 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 01:15:21.673088 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 01:15:21.679353 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 01:15:21.682783 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 01:15:21.686179 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 01:15:21.692901 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4629 01:15:21.695999 0 10 12 | B1->B0 | 2f2f 3a3a | 0 0 | (0 0) (0 0)
4630 01:15:21.699590 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 01:15:21.705608 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 01:15:21.709224 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 01:15:21.712443 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 01:15:21.719242 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 01:15:21.722542 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 01:15:21.726256 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 01:15:21.732745 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4638 01:15:21.735826 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 01:15:21.738993 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 01:15:21.746198 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 01:15:21.748977 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 01:15:21.752274 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 01:15:21.758320 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 01:15:21.762030 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 01:15:21.765390 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 01:15:21.771939 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 01:15:21.775230 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 01:15:21.778892 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 01:15:21.785290 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 01:15:21.788435 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 01:15:21.791537 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 01:15:21.798225 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4653 01:15:21.801304 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 01:15:21.804516 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 01:15:21.808061 Total UI for P1: 0, mck2ui 16
4656 01:15:21.811378 best dqsien dly found for B0: ( 0, 13, 14)
4657 01:15:21.814626 Total UI for P1: 0, mck2ui 16
4658 01:15:21.817906 best dqsien dly found for B1: ( 0, 13, 14)
4659 01:15:21.821016 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4660 01:15:21.824440 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4661 01:15:21.827855
4662 01:15:21.831069 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4663 01:15:21.834427 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4664 01:15:21.838169 [Gating] SW calibration Done
4665 01:15:21.838697 ==
4666 01:15:21.840984 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 01:15:21.844098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 01:15:21.844520 ==
4669 01:15:21.847773 RX Vref Scan: 0
4670 01:15:21.848296
4671 01:15:21.848631 RX Vref 0 -> 0, step: 1
4672 01:15:21.848944
4673 01:15:21.850893 RX Delay -230 -> 252, step: 16
4674 01:15:21.854129 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4675 01:15:21.860959 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4676 01:15:21.864077 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4677 01:15:21.867093 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4678 01:15:21.871083 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4679 01:15:21.877594 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4680 01:15:21.880528 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4681 01:15:21.884160 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4682 01:15:21.887318 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4683 01:15:21.890847 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4684 01:15:21.896964 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4685 01:15:21.900179 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4686 01:15:21.903758 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4687 01:15:21.907306 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4688 01:15:21.913833 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4689 01:15:21.917456 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4690 01:15:21.918027 ==
4691 01:15:21.920671 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 01:15:21.923705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 01:15:21.924237 ==
4694 01:15:21.926915 DQS Delay:
4695 01:15:21.927443 DQS0 = 0, DQS1 = 0
4696 01:15:21.927830 DQM Delay:
4697 01:15:21.930001 DQM0 = 36, DQM1 = 27
4698 01:15:21.930420 DQ Delay:
4699 01:15:21.933843 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4700 01:15:21.936641 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4701 01:15:21.940319 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4702 01:15:21.943486 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4703 01:15:21.943908
4704 01:15:21.944240
4705 01:15:21.944550 ==
4706 01:15:21.947324 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 01:15:21.953828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 01:15:21.954355 ==
4709 01:15:21.954694
4710 01:15:21.955007
4711 01:15:21.955305 TX Vref Scan disable
4712 01:15:21.957297 == TX Byte 0 ==
4713 01:15:21.960441 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4714 01:15:21.967219 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4715 01:15:21.967750 == TX Byte 1 ==
4716 01:15:21.970415 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4717 01:15:21.977090 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4718 01:15:21.977641 ==
4719 01:15:21.980226 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 01:15:21.983940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 01:15:21.984465 ==
4722 01:15:21.984800
4723 01:15:21.985110
4724 01:15:21.986926 TX Vref Scan disable
4725 01:15:21.990435 == TX Byte 0 ==
4726 01:15:21.993903 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4727 01:15:21.997078 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4728 01:15:22.000454 == TX Byte 1 ==
4729 01:15:22.003668 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4730 01:15:22.006568 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4731 01:15:22.006990
4732 01:15:22.007323 [DATLAT]
4733 01:15:22.010153 Freq=600, CH1 RK1
4734 01:15:22.010702
4735 01:15:22.013206 DATLAT Default: 0x9
4736 01:15:22.013660 0, 0xFFFF, sum = 0
4737 01:15:22.016830 1, 0xFFFF, sum = 0
4738 01:15:22.017357 2, 0xFFFF, sum = 0
4739 01:15:22.020214 3, 0xFFFF, sum = 0
4740 01:15:22.020745 4, 0xFFFF, sum = 0
4741 01:15:22.023727 5, 0xFFFF, sum = 0
4742 01:15:22.024261 6, 0xFFFF, sum = 0
4743 01:15:22.026740 7, 0xFFFF, sum = 0
4744 01:15:22.027166 8, 0x0, sum = 1
4745 01:15:22.030144 9, 0x0, sum = 2
4746 01:15:22.030569 10, 0x0, sum = 3
4747 01:15:22.033310 11, 0x0, sum = 4
4748 01:15:22.033877 best_step = 9
4749 01:15:22.034225
4750 01:15:22.034538 ==
4751 01:15:22.036245 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 01:15:22.040199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 01:15:22.040727 ==
4754 01:15:22.042758 RX Vref Scan: 0
4755 01:15:22.043177
4756 01:15:22.046000 RX Vref 0 -> 0, step: 1
4757 01:15:22.046419
4758 01:15:22.046752 RX Delay -195 -> 252, step: 8
4759 01:15:22.054110 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4760 01:15:22.057474 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4761 01:15:22.060641 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4762 01:15:22.063990 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4763 01:15:22.071030 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4764 01:15:22.074007 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4765 01:15:22.077502 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4766 01:15:22.080555 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4767 01:15:22.087652 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4768 01:15:22.091155 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4769 01:15:22.093921 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4770 01:15:22.097073 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4771 01:15:22.103570 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4772 01:15:22.107151 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4773 01:15:22.110496 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4774 01:15:22.113995 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4775 01:15:22.114415 ==
4776 01:15:22.117374 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 01:15:22.123438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 01:15:22.123966 ==
4779 01:15:22.124304 DQS Delay:
4780 01:15:22.127006 DQS0 = 0, DQS1 = 0
4781 01:15:22.127531 DQM Delay:
4782 01:15:22.127870 DQM0 = 36, DQM1 = 30
4783 01:15:22.130232 DQ Delay:
4784 01:15:22.133925 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4785 01:15:22.136514 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =36
4786 01:15:22.139998 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4787 01:15:22.143523 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4788 01:15:22.144050
4789 01:15:22.144384
4790 01:15:22.150086 [DQSOSCAuto] RK1, (LSB)MR18= 0x3454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4791 01:15:22.153263 CH1 RK1: MR19=808, MR18=3454
4792 01:15:22.160022 CH1_RK1: MR19=0x808, MR18=0x3454, DQSOSC=393, MR23=63, INC=169, DEC=113
4793 01:15:22.163332 [RxdqsGatingPostProcess] freq 600
4794 01:15:22.166751 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4795 01:15:22.169944 Pre-setting of DQS Precalculation
4796 01:15:22.176618 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4797 01:15:22.183116 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4798 01:15:22.189650 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4799 01:15:22.190169
4800 01:15:22.190504
4801 01:15:22.193041 [Calibration Summary] 1200 Mbps
4802 01:15:22.193749 CH 0, Rank 0
4803 01:15:22.196213 SW Impedance : PASS
4804 01:15:22.199379 DUTY Scan : NO K
4805 01:15:22.199801 ZQ Calibration : PASS
4806 01:15:22.202559 Jitter Meter : NO K
4807 01:15:22.206033 CBT Training : PASS
4808 01:15:22.206454 Write leveling : PASS
4809 01:15:22.209626 RX DQS gating : PASS
4810 01:15:22.212654 RX DQ/DQS(RDDQC) : PASS
4811 01:15:22.213181 TX DQ/DQS : PASS
4812 01:15:22.216254 RX DATLAT : PASS
4813 01:15:22.219612 RX DQ/DQS(Engine): PASS
4814 01:15:22.220136 TX OE : NO K
4815 01:15:22.222932 All Pass.
4816 01:15:22.223445
4817 01:15:22.223781 CH 0, Rank 1
4818 01:15:22.226056 SW Impedance : PASS
4819 01:15:22.226474 DUTY Scan : NO K
4820 01:15:22.229497 ZQ Calibration : PASS
4821 01:15:22.232456 Jitter Meter : NO K
4822 01:15:22.232874 CBT Training : PASS
4823 01:15:22.235820 Write leveling : PASS
4824 01:15:22.239400 RX DQS gating : PASS
4825 01:15:22.239925 RX DQ/DQS(RDDQC) : PASS
4826 01:15:22.242877 TX DQ/DQS : PASS
4827 01:15:22.245880 RX DATLAT : PASS
4828 01:15:22.246407 RX DQ/DQS(Engine): PASS
4829 01:15:22.249485 TX OE : NO K
4830 01:15:22.250044 All Pass.
4831 01:15:22.250380
4832 01:15:22.252984 CH 1, Rank 0
4833 01:15:22.253535 SW Impedance : PASS
4834 01:15:22.255826 DUTY Scan : NO K
4835 01:15:22.256345 ZQ Calibration : PASS
4836 01:15:22.259345 Jitter Meter : NO K
4837 01:15:22.262628 CBT Training : PASS
4838 01:15:22.263152 Write leveling : PASS
4839 01:15:22.266112 RX DQS gating : PASS
4840 01:15:22.269295 RX DQ/DQS(RDDQC) : PASS
4841 01:15:22.269825 TX DQ/DQS : PASS
4842 01:15:22.272489 RX DATLAT : PASS
4843 01:15:22.275739 RX DQ/DQS(Engine): PASS
4844 01:15:22.276269 TX OE : NO K
4845 01:15:22.278792 All Pass.
4846 01:15:22.279231
4847 01:15:22.279579 CH 1, Rank 1
4848 01:15:22.282468 SW Impedance : PASS
4849 01:15:22.282889 DUTY Scan : NO K
4850 01:15:22.285749 ZQ Calibration : PASS
4851 01:15:22.289124 Jitter Meter : NO K
4852 01:15:22.289578 CBT Training : PASS
4853 01:15:22.292336 Write leveling : PASS
4854 01:15:22.295736 RX DQS gating : PASS
4855 01:15:22.296327 RX DQ/DQS(RDDQC) : PASS
4856 01:15:22.298808 TX DQ/DQS : PASS
4857 01:15:22.302350 RX DATLAT : PASS
4858 01:15:22.302945 RX DQ/DQS(Engine): PASS
4859 01:15:22.305635 TX OE : NO K
4860 01:15:22.306060 All Pass.
4861 01:15:22.306392
4862 01:15:22.309154 DramC Write-DBI off
4863 01:15:22.309713 PER_BANK_REFRESH: Hybrid Mode
4864 01:15:22.312357 TX_TRACKING: ON
4865 01:15:22.322180 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4866 01:15:22.325313 [FAST_K] Save calibration result to emmc
4867 01:15:22.328754 dramc_set_vcore_voltage set vcore to 662500
4868 01:15:22.329281 Read voltage for 933, 3
4869 01:15:22.331748 Vio18 = 0
4870 01:15:22.332282 Vcore = 662500
4871 01:15:22.332697 Vdram = 0
4872 01:15:22.335127 Vddq = 0
4873 01:15:22.335546 Vmddr = 0
4874 01:15:22.341837 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4875 01:15:22.345282 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4876 01:15:22.348784 MEM_TYPE=3, freq_sel=17
4877 01:15:22.351872 sv_algorithm_assistance_LP4_1600
4878 01:15:22.355216 ============ PULL DRAM RESETB DOWN ============
4879 01:15:22.358662 ========== PULL DRAM RESETB DOWN end =========
4880 01:15:22.365040 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4881 01:15:22.368657 ===================================
4882 01:15:22.369081 LPDDR4 DRAM CONFIGURATION
4883 01:15:22.372045 ===================================
4884 01:15:22.374897 EX_ROW_EN[0] = 0x0
4885 01:15:22.378636 EX_ROW_EN[1] = 0x0
4886 01:15:22.379160 LP4Y_EN = 0x0
4887 01:15:22.381847 WORK_FSP = 0x0
4888 01:15:22.382266 WL = 0x3
4889 01:15:22.384750 RL = 0x3
4890 01:15:22.385166 BL = 0x2
4891 01:15:22.388180 RPST = 0x0
4892 01:15:22.388598 RD_PRE = 0x0
4893 01:15:22.391700 WR_PRE = 0x1
4894 01:15:22.392293 WR_PST = 0x0
4895 01:15:22.394611 DBI_WR = 0x0
4896 01:15:22.395029 DBI_RD = 0x0
4897 01:15:22.398312 OTF = 0x1
4898 01:15:22.401219 ===================================
4899 01:15:22.404891 ===================================
4900 01:15:22.405342 ANA top config
4901 01:15:22.407984 ===================================
4902 01:15:22.411145 DLL_ASYNC_EN = 0
4903 01:15:22.414619 ALL_SLAVE_EN = 1
4904 01:15:22.417915 NEW_RANK_MODE = 1
4905 01:15:22.418336 DLL_IDLE_MODE = 1
4906 01:15:22.421707 LP45_APHY_COMB_EN = 1
4907 01:15:22.425177 TX_ODT_DIS = 1
4908 01:15:22.428130 NEW_8X_MODE = 1
4909 01:15:22.431243 ===================================
4910 01:15:22.434654 ===================================
4911 01:15:22.437566 data_rate = 1866
4912 01:15:22.437989 CKR = 1
4913 01:15:22.441457 DQ_P2S_RATIO = 8
4914 01:15:22.444188 ===================================
4915 01:15:22.447615 CA_P2S_RATIO = 8
4916 01:15:22.451530 DQ_CA_OPEN = 0
4917 01:15:22.454124 DQ_SEMI_OPEN = 0
4918 01:15:22.457394 CA_SEMI_OPEN = 0
4919 01:15:22.457857 CA_FULL_RATE = 0
4920 01:15:22.460836 DQ_CKDIV4_EN = 1
4921 01:15:22.464472 CA_CKDIV4_EN = 1
4922 01:15:22.467942 CA_PREDIV_EN = 0
4923 01:15:22.470804 PH8_DLY = 0
4924 01:15:22.474195 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4925 01:15:22.474723 DQ_AAMCK_DIV = 4
4926 01:15:22.477667 CA_AAMCK_DIV = 4
4927 01:15:22.480550 CA_ADMCK_DIV = 4
4928 01:15:22.484008 DQ_TRACK_CA_EN = 0
4929 01:15:22.487404 CA_PICK = 933
4930 01:15:22.490701 CA_MCKIO = 933
4931 01:15:22.494154 MCKIO_SEMI = 0
4932 01:15:22.494712 PLL_FREQ = 3732
4933 01:15:22.497563 DQ_UI_PI_RATIO = 32
4934 01:15:22.500428 CA_UI_PI_RATIO = 0
4935 01:15:22.503653 ===================================
4936 01:15:22.507356 ===================================
4937 01:15:22.510158 memory_type:LPDDR4
4938 01:15:22.513479 GP_NUM : 10
4939 01:15:22.513938 SRAM_EN : 1
4940 01:15:22.517053 MD32_EN : 0
4941 01:15:22.520079 ===================================
4942 01:15:22.520596 [ANA_INIT] >>>>>>>>>>>>>>
4943 01:15:22.523742 <<<<<< [CONFIGURE PHASE]: ANA_TX
4944 01:15:22.526837 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4945 01:15:22.530308 ===================================
4946 01:15:22.533743 data_rate = 1866,PCW = 0X8f00
4947 01:15:22.536574 ===================================
4948 01:15:22.540140 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4949 01:15:22.546645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 01:15:22.553667 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4951 01:15:22.556431 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4952 01:15:22.560229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4953 01:15:22.563554 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4954 01:15:22.566987 [ANA_INIT] flow start
4955 01:15:22.567495 [ANA_INIT] PLL >>>>>>>>
4956 01:15:22.570110 [ANA_INIT] PLL <<<<<<<<
4957 01:15:22.573210 [ANA_INIT] MIDPI >>>>>>>>
4958 01:15:22.573752 [ANA_INIT] MIDPI <<<<<<<<
4959 01:15:22.576634 [ANA_INIT] DLL >>>>>>>>
4960 01:15:22.580088 [ANA_INIT] flow end
4961 01:15:22.583034 ============ LP4 DIFF to SE enter ============
4962 01:15:22.586383 ============ LP4 DIFF to SE exit ============
4963 01:15:22.589944 [ANA_INIT] <<<<<<<<<<<<<
4964 01:15:22.592833 [Flow] Enable top DCM control >>>>>
4965 01:15:22.596411 [Flow] Enable top DCM control <<<<<
4966 01:15:22.599254 Enable DLL master slave shuffle
4967 01:15:22.606125 ==============================================================
4968 01:15:22.606669 Gating Mode config
4969 01:15:22.612367 ==============================================================
4970 01:15:22.612908 Config description:
4971 01:15:22.622967 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4972 01:15:22.629383 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4973 01:15:22.635814 SELPH_MODE 0: By rank 1: By Phase
4974 01:15:22.639548 ==============================================================
4975 01:15:22.642776 GAT_TRACK_EN = 1
4976 01:15:22.645784 RX_GATING_MODE = 2
4977 01:15:22.649185 RX_GATING_TRACK_MODE = 2
4978 01:15:22.652688 SELPH_MODE = 1
4979 01:15:22.655731 PICG_EARLY_EN = 1
4980 01:15:22.659093 VALID_LAT_VALUE = 1
4981 01:15:22.665291 ==============================================================
4982 01:15:22.668930 Enter into Gating configuration >>>>
4983 01:15:22.672180 Exit from Gating configuration <<<<
4984 01:15:22.674951 Enter into DVFS_PRE_config >>>>>
4985 01:15:22.685251 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4986 01:15:22.688717 Exit from DVFS_PRE_config <<<<<
4987 01:15:22.692157 Enter into PICG configuration >>>>
4988 01:15:22.695414 Exit from PICG configuration <<<<
4989 01:15:22.698187 [RX_INPUT] configuration >>>>>
4990 01:15:22.698653 [RX_INPUT] configuration <<<<<
4991 01:15:22.705134 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4992 01:15:22.711681 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4993 01:15:22.715263 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4994 01:15:22.721725 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4995 01:15:22.728548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4996 01:15:22.735003 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4997 01:15:22.737633 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4998 01:15:22.740914 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4999 01:15:22.748113 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5000 01:15:22.750971 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5001 01:15:22.754449 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5002 01:15:22.760790 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 01:15:22.764198 ===================================
5004 01:15:22.764665 LPDDR4 DRAM CONFIGURATION
5005 01:15:22.767828 ===================================
5006 01:15:22.770886 EX_ROW_EN[0] = 0x0
5007 01:15:22.774119 EX_ROW_EN[1] = 0x0
5008 01:15:22.774576 LP4Y_EN = 0x0
5009 01:15:22.777612 WORK_FSP = 0x0
5010 01:15:22.778166 WL = 0x3
5011 01:15:22.780793 RL = 0x3
5012 01:15:22.781279 BL = 0x2
5013 01:15:22.783882 RPST = 0x0
5014 01:15:22.784294 RD_PRE = 0x0
5015 01:15:22.787600 WR_PRE = 0x1
5016 01:15:22.788131 WR_PST = 0x0
5017 01:15:22.790588 DBI_WR = 0x0
5018 01:15:22.791008 DBI_RD = 0x0
5019 01:15:22.793991 OTF = 0x1
5020 01:15:22.797312 ===================================
5021 01:15:22.800372 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5022 01:15:22.804069 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5023 01:15:22.810757 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 01:15:22.813971 ===================================
5025 01:15:22.814392 LPDDR4 DRAM CONFIGURATION
5026 01:15:22.816652 ===================================
5027 01:15:22.820441 EX_ROW_EN[0] = 0x10
5028 01:15:22.823571 EX_ROW_EN[1] = 0x0
5029 01:15:22.823998 LP4Y_EN = 0x0
5030 01:15:22.827156 WORK_FSP = 0x0
5031 01:15:22.827670 WL = 0x3
5032 01:15:22.830365 RL = 0x3
5033 01:15:22.830796 BL = 0x2
5034 01:15:22.833956 RPST = 0x0
5035 01:15:22.834471 RD_PRE = 0x0
5036 01:15:22.836792 WR_PRE = 0x1
5037 01:15:22.837209 WR_PST = 0x0
5038 01:15:22.840479 DBI_WR = 0x0
5039 01:15:22.840993 DBI_RD = 0x0
5040 01:15:22.843171 OTF = 0x1
5041 01:15:22.846660 ===================================
5042 01:15:22.853659 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5043 01:15:22.856877 nWR fixed to 30
5044 01:15:22.857310 [ModeRegInit_LP4] CH0 RK0
5045 01:15:22.860062 [ModeRegInit_LP4] CH0 RK1
5046 01:15:22.863316 [ModeRegInit_LP4] CH1 RK0
5047 01:15:22.866700 [ModeRegInit_LP4] CH1 RK1
5048 01:15:22.867125 match AC timing 9
5049 01:15:22.873556 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5050 01:15:22.876753 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5051 01:15:22.879870 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5052 01:15:22.886359 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5053 01:15:22.889923 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5054 01:15:22.890455 ==
5055 01:15:22.893393 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 01:15:22.895965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 01:15:22.896390 ==
5058 01:15:22.903079 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 01:15:22.909264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5060 01:15:22.912690 [CA 0] Center 38 (8~69) winsize 62
5061 01:15:22.916567 [CA 1] Center 38 (8~69) winsize 62
5062 01:15:22.919425 [CA 2] Center 35 (5~66) winsize 62
5063 01:15:22.922730 [CA 3] Center 35 (4~66) winsize 63
5064 01:15:22.926055 [CA 4] Center 34 (4~65) winsize 62
5065 01:15:22.929393 [CA 5] Center 34 (4~64) winsize 61
5066 01:15:22.929974
5067 01:15:22.932582 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5068 01:15:22.933004
5069 01:15:22.936349 [CATrainingPosCal] consider 1 rank data
5070 01:15:22.938924 u2DelayCellTimex100 = 270/100 ps
5071 01:15:22.942046 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5072 01:15:22.945494 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5073 01:15:22.949164 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5074 01:15:22.952362 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5075 01:15:22.955716 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5076 01:15:22.962439 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5077 01:15:22.962994
5078 01:15:22.965372 CA PerBit enable=1, Macro0, CA PI delay=34
5079 01:15:22.965842
5080 01:15:22.968631 [CBTSetCACLKResult] CA Dly = 34
5081 01:15:22.969158 CS Dly: 7 (0~38)
5082 01:15:22.969497 ==
5083 01:15:22.972490 Dram Type= 6, Freq= 0, CH_0, rank 1
5084 01:15:22.975261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 01:15:22.978799 ==
5086 01:15:22.982188 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5087 01:15:22.988682 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5088 01:15:22.992035 [CA 0] Center 38 (8~69) winsize 62
5089 01:15:22.995692 [CA 1] Center 38 (8~69) winsize 62
5090 01:15:22.998522 [CA 2] Center 35 (5~66) winsize 62
5091 01:15:23.001933 [CA 3] Center 35 (5~66) winsize 62
5092 01:15:23.005455 [CA 4] Center 34 (4~65) winsize 62
5093 01:15:23.008374 [CA 5] Center 33 (3~64) winsize 62
5094 01:15:23.008836
5095 01:15:23.011615 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5096 01:15:23.012035
5097 01:15:23.015150 [CATrainingPosCal] consider 2 rank data
5098 01:15:23.018016 u2DelayCellTimex100 = 270/100 ps
5099 01:15:23.021670 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5100 01:15:23.025044 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5101 01:15:23.028204 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5102 01:15:23.034990 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5103 01:15:23.038022 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5104 01:15:23.041216 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5105 01:15:23.041779
5106 01:15:23.044534 CA PerBit enable=1, Macro0, CA PI delay=34
5107 01:15:23.044952
5108 01:15:23.047992 [CBTSetCACLKResult] CA Dly = 34
5109 01:15:23.048412 CS Dly: 7 (0~38)
5110 01:15:23.048879
5111 01:15:23.051439 ----->DramcWriteLeveling(PI) begin...
5112 01:15:23.054274 ==
5113 01:15:23.054789 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 01:15:23.061251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 01:15:23.061831 ==
5116 01:15:23.064783 Write leveling (Byte 0): 31 => 31
5117 01:15:23.067815 Write leveling (Byte 1): 32 => 32
5118 01:15:23.071120 DramcWriteLeveling(PI) end<-----
5119 01:15:23.071642
5120 01:15:23.071978 ==
5121 01:15:23.074405 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 01:15:23.078133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 01:15:23.078667 ==
5124 01:15:23.081326 [Gating] SW mode calibration
5125 01:15:23.087724 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5126 01:15:23.094330 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5127 01:15:23.097454 0 14 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5128 01:15:23.101169 0 14 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5129 01:15:23.107290 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 01:15:23.110656 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 01:15:23.113988 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 01:15:23.120881 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 01:15:23.124002 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 01:15:23.127475 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5135 01:15:23.133889 0 15 0 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (1 0)
5136 01:15:23.137418 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5137 01:15:23.140774 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 01:15:23.147353 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 01:15:23.150062 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 01:15:23.153619 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 01:15:23.160338 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 01:15:23.163466 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 01:15:23.166697 1 0 0 | B1->B0 | 2626 3939 | 1 1 | (0 0) (0 0)
5144 01:15:23.173679 1 0 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5145 01:15:23.176507 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 01:15:23.180276 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 01:15:23.186861 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 01:15:23.189822 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 01:15:23.194082 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 01:15:23.196787 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5151 01:15:23.203625 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5152 01:15:23.206853 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5153 01:15:23.209681 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 01:15:23.216676 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 01:15:23.220144 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 01:15:23.223725 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 01:15:23.230099 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 01:15:23.233363 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 01:15:23.236953 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 01:15:23.242890 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 01:15:23.246135 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 01:15:23.249591 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 01:15:23.256598 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 01:15:23.259733 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 01:15:23.262523 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 01:15:23.269872 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5167 01:15:23.272886 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5168 01:15:23.276121 Total UI for P1: 0, mck2ui 16
5169 01:15:23.279253 best dqsien dly found for B0: ( 1, 2, 28)
5170 01:15:23.282616 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5171 01:15:23.289032 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 01:15:23.292478 Total UI for P1: 0, mck2ui 16
5173 01:15:23.296228 best dqsien dly found for B1: ( 1, 3, 2)
5174 01:15:23.298811 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5175 01:15:23.302341 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5176 01:15:23.302863
5177 01:15:23.305847 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5178 01:15:23.309052 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5179 01:15:23.312643 [Gating] SW calibration Done
5180 01:15:23.313169 ==
5181 01:15:23.315332 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 01:15:23.318691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 01:15:23.319133 ==
5184 01:15:23.322067 RX Vref Scan: 0
5185 01:15:23.322501
5186 01:15:23.322936 RX Vref 0 -> 0, step: 1
5187 01:15:23.323349
5188 01:15:23.325475 RX Delay -80 -> 252, step: 8
5189 01:15:23.332651 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5190 01:15:23.336028 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5191 01:15:23.338737 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5192 01:15:23.342489 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5193 01:15:23.345802 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5194 01:15:23.348834 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5195 01:15:23.352768 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5196 01:15:23.359071 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5197 01:15:23.362443 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5198 01:15:23.365630 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5199 01:15:23.369143 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5200 01:15:23.371958 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5201 01:15:23.378810 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5202 01:15:23.382407 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5203 01:15:23.385449 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5204 01:15:23.389073 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5205 01:15:23.389647 ==
5206 01:15:23.392179 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 01:15:23.398832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 01:15:23.399366 ==
5209 01:15:23.399810 DQS Delay:
5210 01:15:23.401494 DQS0 = 0, DQS1 = 0
5211 01:15:23.402052 DQM Delay:
5212 01:15:23.402507 DQM0 = 94, DQM1 = 83
5213 01:15:23.404880 DQ Delay:
5214 01:15:23.408356 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5215 01:15:23.412094 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5216 01:15:23.415106 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5217 01:15:23.418494 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5218 01:15:23.419031
5219 01:15:23.419461
5220 01:15:23.419869 ==
5221 01:15:23.421734 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 01:15:23.424661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 01:15:23.425159 ==
5224 01:15:23.425502
5225 01:15:23.425866
5226 01:15:23.428327 TX Vref Scan disable
5227 01:15:23.431208 == TX Byte 0 ==
5228 01:15:23.434538 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5229 01:15:23.438128 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5230 01:15:23.441620 == TX Byte 1 ==
5231 01:15:23.444680 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5232 01:15:23.447787 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5233 01:15:23.448216 ==
5234 01:15:23.451530 Dram Type= 6, Freq= 0, CH_0, rank 0
5235 01:15:23.454837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5236 01:15:23.458443 ==
5237 01:15:23.458991
5238 01:15:23.459339
5239 01:15:23.459652 TX Vref Scan disable
5240 01:15:23.461429 == TX Byte 0 ==
5241 01:15:23.464718 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5242 01:15:23.471507 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5243 01:15:23.472040 == TX Byte 1 ==
5244 01:15:23.474944 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5245 01:15:23.481883 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5246 01:15:23.482402
5247 01:15:23.482740 [DATLAT]
5248 01:15:23.483056 Freq=933, CH0 RK0
5249 01:15:23.483358
5250 01:15:23.484514 DATLAT Default: 0xd
5251 01:15:23.484934 0, 0xFFFF, sum = 0
5252 01:15:23.488156 1, 0xFFFF, sum = 0
5253 01:15:23.491255 2, 0xFFFF, sum = 0
5254 01:15:23.491700 3, 0xFFFF, sum = 0
5255 01:15:23.494780 4, 0xFFFF, sum = 0
5256 01:15:23.495237 5, 0xFFFF, sum = 0
5257 01:15:23.497497 6, 0xFFFF, sum = 0
5258 01:15:23.497953 7, 0xFFFF, sum = 0
5259 01:15:23.500856 8, 0xFFFF, sum = 0
5260 01:15:23.501280 9, 0xFFFF, sum = 0
5261 01:15:23.504343 10, 0x0, sum = 1
5262 01:15:23.504768 11, 0x0, sum = 2
5263 01:15:23.507590 12, 0x0, sum = 3
5264 01:15:23.508024 13, 0x0, sum = 4
5265 01:15:23.511135 best_step = 11
5266 01:15:23.511552
5267 01:15:23.511881 ==
5268 01:15:23.514097 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 01:15:23.517778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 01:15:23.518199 ==
5271 01:15:23.518532 RX Vref Scan: 1
5272 01:15:23.518841
5273 01:15:23.521123 RX Vref 0 -> 0, step: 1
5274 01:15:23.521571
5275 01:15:23.524345 RX Delay -69 -> 252, step: 4
5276 01:15:23.524763
5277 01:15:23.527376 Set Vref, RX VrefLevel [Byte0]: 61
5278 01:15:23.530930 [Byte1]: 47
5279 01:15:23.534558
5280 01:15:23.535070 Final RX Vref Byte 0 = 61 to rank0
5281 01:15:23.537498 Final RX Vref Byte 1 = 47 to rank0
5282 01:15:23.540766 Final RX Vref Byte 0 = 61 to rank1
5283 01:15:23.544024 Final RX Vref Byte 1 = 47 to rank1==
5284 01:15:23.547451 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 01:15:23.554063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 01:15:23.554491 ==
5287 01:15:23.554825 DQS Delay:
5288 01:15:23.557263 DQS0 = 0, DQS1 = 0
5289 01:15:23.557702 DQM Delay:
5290 01:15:23.558037 DQM0 = 95, DQM1 = 82
5291 01:15:23.561121 DQ Delay:
5292 01:15:23.563759 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5293 01:15:23.567166 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5294 01:15:23.570376 DQ8 =76, DQ9 =68, DQ10 =82, DQ11 =78
5295 01:15:23.573922 DQ12 =86, DQ13 =86, DQ14 =92, DQ15 =90
5296 01:15:23.574338
5297 01:15:23.574667
5298 01:15:23.580806 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5299 01:15:23.583657 CH0 RK0: MR19=505, MR18=1211
5300 01:15:23.590792 CH0_RK0: MR19=0x505, MR18=0x1211, DQSOSC=416, MR23=63, INC=62, DEC=41
5301 01:15:23.591301
5302 01:15:23.593942 ----->DramcWriteLeveling(PI) begin...
5303 01:15:23.594370 ==
5304 01:15:23.597627 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 01:15:23.600590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 01:15:23.601116 ==
5307 01:15:23.603780 Write leveling (Byte 0): 31 => 31
5308 01:15:23.607116 Write leveling (Byte 1): 28 => 28
5309 01:15:23.610560 DramcWriteLeveling(PI) end<-----
5310 01:15:23.610978
5311 01:15:23.611385 ==
5312 01:15:23.614016 Dram Type= 6, Freq= 0, CH_0, rank 1
5313 01:15:23.616714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 01:15:23.617133 ==
5315 01:15:23.620072 [Gating] SW mode calibration
5316 01:15:23.626550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5317 01:15:23.633997 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5318 01:15:23.637075 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5319 01:15:23.643964 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 01:15:23.646483 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 01:15:23.650408 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 01:15:23.656524 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 01:15:23.659974 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 01:15:23.663223 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5325 01:15:23.670100 0 14 28 | B1->B0 | 3333 2b2b | 1 0 | (1 0) (1 0)
5326 01:15:23.673282 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (0 1) (0 0)
5327 01:15:23.676538 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 01:15:23.683500 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 01:15:23.686912 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 01:15:23.690081 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 01:15:23.696807 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 01:15:23.700132 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 01:15:23.703308 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5334 01:15:23.709552 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5335 01:15:23.713361 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 01:15:23.716118 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 01:15:23.723002 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 01:15:23.726312 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 01:15:23.729913 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 01:15:23.736097 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 01:15:23.739758 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5342 01:15:23.742668 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5343 01:15:23.749628 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5344 01:15:23.753130 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 01:15:23.755967 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 01:15:23.759587 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 01:15:23.766114 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 01:15:23.769339 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 01:15:23.772600 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 01:15:23.778783 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 01:15:23.782080 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 01:15:23.785991 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 01:15:23.792634 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 01:15:23.795353 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 01:15:23.799029 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 01:15:23.805410 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 01:15:23.808436 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5358 01:15:23.811920 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5359 01:15:23.815668 Total UI for P1: 0, mck2ui 16
5360 01:15:23.818840 best dqsien dly found for B0: ( 1, 2, 28)
5361 01:15:23.825727 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 01:15:23.826233 Total UI for P1: 0, mck2ui 16
5363 01:15:23.832122 best dqsien dly found for B1: ( 1, 3, 0)
5364 01:15:23.835556 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5365 01:15:23.838825 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5366 01:15:23.839241
5367 01:15:23.842199 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5368 01:15:23.845621 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5369 01:15:23.848637 [Gating] SW calibration Done
5370 01:15:23.849182 ==
5371 01:15:23.852617 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 01:15:23.855400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 01:15:23.855928 ==
5374 01:15:23.858678 RX Vref Scan: 0
5375 01:15:23.859092
5376 01:15:23.859414 RX Vref 0 -> 0, step: 1
5377 01:15:23.859718
5378 01:15:23.861576 RX Delay -80 -> 252, step: 8
5379 01:15:23.868365 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5380 01:15:23.872221 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5381 01:15:23.875660 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5382 01:15:23.878370 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5383 01:15:23.882083 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5384 01:15:23.885321 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5385 01:15:23.891299 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5386 01:15:23.894984 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5387 01:15:23.898076 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5388 01:15:23.902010 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5389 01:15:23.904974 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5390 01:15:23.911425 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5391 01:15:23.914662 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5392 01:15:23.918104 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5393 01:15:23.921230 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5394 01:15:23.924826 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5395 01:15:23.927845 ==
5396 01:15:23.928358 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 01:15:23.934514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 01:15:23.935031 ==
5399 01:15:23.935379 DQS Delay:
5400 01:15:23.937951 DQS0 = 0, DQS1 = 0
5401 01:15:23.938499 DQM Delay:
5402 01:15:23.941428 DQM0 = 92, DQM1 = 81
5403 01:15:23.941985 DQ Delay:
5404 01:15:23.944418 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5405 01:15:23.947538 DQ4 =91, DQ5 =79, DQ6 =107, DQ7 =107
5406 01:15:23.950921 DQ8 =75, DQ9 =63, DQ10 =87, DQ11 =71
5407 01:15:23.954322 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5408 01:15:23.954861
5409 01:15:23.955198
5410 01:15:23.955502 ==
5411 01:15:23.957480 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 01:15:23.961091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 01:15:23.961645 ==
5414 01:15:23.961979
5415 01:15:23.962298
5416 01:15:23.964749 TX Vref Scan disable
5417 01:15:23.968028 == TX Byte 0 ==
5418 01:15:23.970685 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5419 01:15:23.974184 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5420 01:15:23.977704 == TX Byte 1 ==
5421 01:15:23.980697 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5422 01:15:23.984014 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5423 01:15:23.984531 ==
5424 01:15:23.987420 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 01:15:23.993861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 01:15:23.994362 ==
5427 01:15:23.994690
5428 01:15:23.994998
5429 01:15:23.995281 TX Vref Scan disable
5430 01:15:23.997908 == TX Byte 0 ==
5431 01:15:24.001685 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5432 01:15:24.008025 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5433 01:15:24.008702 == TX Byte 1 ==
5434 01:15:24.011167 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5435 01:15:24.017866 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5436 01:15:24.018399
5437 01:15:24.018735 [DATLAT]
5438 01:15:24.019094 Freq=933, CH0 RK1
5439 01:15:24.019426
5440 01:15:24.021055 DATLAT Default: 0xb
5441 01:15:24.021545 0, 0xFFFF, sum = 0
5442 01:15:24.024683 1, 0xFFFF, sum = 0
5443 01:15:24.028250 2, 0xFFFF, sum = 0
5444 01:15:24.028823 3, 0xFFFF, sum = 0
5445 01:15:24.031750 4, 0xFFFF, sum = 0
5446 01:15:24.032324 5, 0xFFFF, sum = 0
5447 01:15:24.034598 6, 0xFFFF, sum = 0
5448 01:15:24.035206 7, 0xFFFF, sum = 0
5449 01:15:24.037918 8, 0xFFFF, sum = 0
5450 01:15:24.038371 9, 0xFFFF, sum = 0
5451 01:15:24.040866 10, 0x0, sum = 1
5452 01:15:24.041375 11, 0x0, sum = 2
5453 01:15:24.045366 12, 0x0, sum = 3
5454 01:15:24.045961 13, 0x0, sum = 4
5455 01:15:24.046310 best_step = 11
5456 01:15:24.046622
5457 01:15:24.047607 ==
5458 01:15:24.050654 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 01:15:24.053912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 01:15:24.054336 ==
5461 01:15:24.054671 RX Vref Scan: 0
5462 01:15:24.054982
5463 01:15:24.057359 RX Vref 0 -> 0, step: 1
5464 01:15:24.057806
5465 01:15:24.060907 RX Delay -77 -> 252, step: 4
5466 01:15:24.067409 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5467 01:15:24.070873 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5468 01:15:24.073809 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5469 01:15:24.077441 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5470 01:15:24.080801 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5471 01:15:24.084265 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5472 01:15:24.090834 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5473 01:15:24.094076 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5474 01:15:24.097590 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5475 01:15:24.100722 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5476 01:15:24.103854 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5477 01:15:24.110228 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5478 01:15:24.113940 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5479 01:15:24.117587 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5480 01:15:24.120480 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5481 01:15:24.123979 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5482 01:15:24.124527 ==
5483 01:15:24.127342 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 01:15:24.133698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 01:15:24.134249 ==
5486 01:15:24.134633 DQS Delay:
5487 01:15:24.137313 DQS0 = 0, DQS1 = 0
5488 01:15:24.137914 DQM Delay:
5489 01:15:24.138282 DQM0 = 92, DQM1 = 83
5490 01:15:24.140578 DQ Delay:
5491 01:15:24.143804 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5492 01:15:24.146715 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5493 01:15:24.150396 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5494 01:15:24.153924 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =92
5495 01:15:24.154474
5496 01:15:24.154865
5497 01:15:24.160494 [DQSOSCAuto] RK1, (LSB)MR18= 0x3011, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
5498 01:15:24.163269 CH0 RK1: MR19=505, MR18=3011
5499 01:15:24.169960 CH0_RK1: MR19=0x505, MR18=0x3011, DQSOSC=406, MR23=63, INC=65, DEC=43
5500 01:15:24.173442 [RxdqsGatingPostProcess] freq 933
5501 01:15:24.180075 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5502 01:15:24.180534 best DQS0 dly(2T, 0.5T) = (0, 10)
5503 01:15:24.183579 best DQS1 dly(2T, 0.5T) = (0, 11)
5504 01:15:24.186845 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5505 01:15:24.189958 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5506 01:15:24.193500 best DQS0 dly(2T, 0.5T) = (0, 10)
5507 01:15:24.196207 best DQS1 dly(2T, 0.5T) = (0, 11)
5508 01:15:24.199752 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5509 01:15:24.203206 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5510 01:15:24.206842 Pre-setting of DQS Precalculation
5511 01:15:24.212866 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5512 01:15:24.213332 ==
5513 01:15:24.216752 Dram Type= 6, Freq= 0, CH_1, rank 0
5514 01:15:24.219901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 01:15:24.220468 ==
5516 01:15:24.226769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 01:15:24.230103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5518 01:15:24.233772 [CA 0] Center 37 (7~68) winsize 62
5519 01:15:24.237100 [CA 1] Center 37 (7~68) winsize 62
5520 01:15:24.240595 [CA 2] Center 34 (5~64) winsize 60
5521 01:15:24.243594 [CA 3] Center 34 (5~64) winsize 60
5522 01:15:24.247085 [CA 4] Center 35 (5~65) winsize 61
5523 01:15:24.250339 [CA 5] Center 34 (4~64) winsize 61
5524 01:15:24.250906
5525 01:15:24.254122 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5526 01:15:24.254769
5527 01:15:24.256995 [CATrainingPosCal] consider 1 rank data
5528 01:15:24.260166 u2DelayCellTimex100 = 270/100 ps
5529 01:15:24.263642 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5530 01:15:24.266867 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5531 01:15:24.273619 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5532 01:15:24.277012 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5533 01:15:24.280139 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5534 01:15:24.283537 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5535 01:15:24.284103
5536 01:15:24.286940 CA PerBit enable=1, Macro0, CA PI delay=34
5537 01:15:24.287511
5538 01:15:24.290188 [CBTSetCACLKResult] CA Dly = 34
5539 01:15:24.290651 CS Dly: 6 (0~37)
5540 01:15:24.291022 ==
5541 01:15:24.293453 Dram Type= 6, Freq= 0, CH_1, rank 1
5542 01:15:24.300135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 01:15:24.300663 ==
5544 01:15:24.303156 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5545 01:15:24.309843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5546 01:15:24.313344 [CA 0] Center 38 (8~68) winsize 61
5547 01:15:24.316972 [CA 1] Center 37 (7~68) winsize 62
5548 01:15:24.320270 [CA 2] Center 35 (6~65) winsize 60
5549 01:15:24.323869 [CA 3] Center 34 (4~64) winsize 61
5550 01:15:24.326833 [CA 4] Center 35 (5~65) winsize 61
5551 01:15:24.330167 [CA 5] Center 34 (4~64) winsize 61
5552 01:15:24.330628
5553 01:15:24.333399 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5554 01:15:24.333986
5555 01:15:24.336777 [CATrainingPosCal] consider 2 rank data
5556 01:15:24.339863 u2DelayCellTimex100 = 270/100 ps
5557 01:15:24.343235 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5558 01:15:24.350445 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5559 01:15:24.353282 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5560 01:15:24.356538 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5561 01:15:24.359469 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5562 01:15:24.363278 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5563 01:15:24.363807
5564 01:15:24.366095 CA PerBit enable=1, Macro0, CA PI delay=34
5565 01:15:24.366515
5566 01:15:24.369666 [CBTSetCACLKResult] CA Dly = 34
5567 01:15:24.373277 CS Dly: 7 (0~39)
5568 01:15:24.373856
5569 01:15:24.376189 ----->DramcWriteLeveling(PI) begin...
5570 01:15:24.376720 ==
5571 01:15:24.379303 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 01:15:24.382999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 01:15:24.383528 ==
5574 01:15:24.386440 Write leveling (Byte 0): 25 => 25
5575 01:15:24.389771 Write leveling (Byte 1): 27 => 27
5576 01:15:24.393098 DramcWriteLeveling(PI) end<-----
5577 01:15:24.393714
5578 01:15:24.394057 ==
5579 01:15:24.395981 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 01:15:24.399477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 01:15:24.399905 ==
5582 01:15:24.403093 [Gating] SW mode calibration
5583 01:15:24.409446 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5584 01:15:24.415955 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5585 01:15:24.419522 0 14 0 | B1->B0 | 3433 3434 | 1 1 | (1 1) (1 1)
5586 01:15:24.422683 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 01:15:24.429045 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 01:15:24.432929 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 01:15:24.435924 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 01:15:24.441991 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 01:15:24.445551 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 01:15:24.449288 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 1)
5593 01:15:24.455637 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
5594 01:15:24.459120 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 01:15:24.461905 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 01:15:24.468774 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 01:15:24.472523 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 01:15:24.475224 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 01:15:24.482463 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 01:15:24.484917 0 15 28 | B1->B0 | 3636 3535 | 0 0 | (0 0) (0 0)
5601 01:15:24.488620 1 0 0 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
5602 01:15:24.495716 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 01:15:24.498343 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 01:15:24.501889 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 01:15:24.508860 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 01:15:24.511573 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 01:15:24.514577 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 01:15:24.521864 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5609 01:15:24.524866 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5610 01:15:24.528394 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 01:15:24.534454 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 01:15:24.538125 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 01:15:24.541125 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 01:15:24.547996 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 01:15:24.551291 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 01:15:24.554288 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 01:15:24.561344 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 01:15:24.564283 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 01:15:24.567736 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 01:15:24.574508 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 01:15:24.577571 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 01:15:24.580828 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 01:15:24.587974 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5624 01:15:24.590982 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5625 01:15:24.594360 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5626 01:15:24.601081 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 01:15:24.601743 Total UI for P1: 0, mck2ui 16
5628 01:15:24.607681 best dqsien dly found for B0: ( 1, 2, 28)
5629 01:15:24.608222 Total UI for P1: 0, mck2ui 16
5630 01:15:24.613625 best dqsien dly found for B1: ( 1, 2, 30)
5631 01:15:24.617033 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5632 01:15:24.620531 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5633 01:15:24.620953
5634 01:15:24.623797 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5635 01:15:24.626963 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5636 01:15:24.630253 [Gating] SW calibration Done
5637 01:15:24.630768 ==
5638 01:15:24.633837 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 01:15:24.636808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 01:15:24.637230 ==
5641 01:15:24.640313 RX Vref Scan: 0
5642 01:15:24.640727
5643 01:15:24.641059 RX Vref 0 -> 0, step: 1
5644 01:15:24.641368
5645 01:15:24.643225 RX Delay -80 -> 252, step: 8
5646 01:15:24.646780 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5647 01:15:24.653260 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5648 01:15:24.656982 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5649 01:15:24.660299 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5650 01:15:24.663871 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5651 01:15:24.666623 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5652 01:15:24.673587 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5653 01:15:24.676574 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5654 01:15:24.680014 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5655 01:15:24.683553 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5656 01:15:24.687005 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5657 01:15:24.690182 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5658 01:15:24.697195 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5659 01:15:24.700097 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5660 01:15:24.703655 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5661 01:15:24.707066 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5662 01:15:24.707594 ==
5663 01:15:24.710020 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 01:15:24.713200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 01:15:24.716615 ==
5666 01:15:24.717077 DQS Delay:
5667 01:15:24.717442 DQS0 = 0, DQS1 = 0
5668 01:15:24.720472 DQM Delay:
5669 01:15:24.720986 DQM0 = 94, DQM1 = 87
5670 01:15:24.723185 DQ Delay:
5671 01:15:24.726575 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5672 01:15:24.730093 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5673 01:15:24.733479 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5674 01:15:24.736588 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =95
5675 01:15:24.737152
5676 01:15:24.737560
5677 01:15:24.737935 ==
5678 01:15:24.739813 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 01:15:24.742692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 01:15:24.743163 ==
5681 01:15:24.743532
5682 01:15:24.743874
5683 01:15:24.746157 TX Vref Scan disable
5684 01:15:24.746580 == TX Byte 0 ==
5685 01:15:24.752912 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5686 01:15:24.756525 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5687 01:15:24.757050 == TX Byte 1 ==
5688 01:15:24.762880 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5689 01:15:24.766085 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5690 01:15:24.766507 ==
5691 01:15:24.769654 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 01:15:24.773433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 01:15:24.774003 ==
5694 01:15:24.774346
5695 01:15:24.774659
5696 01:15:24.775831 TX Vref Scan disable
5697 01:15:24.779258 == TX Byte 0 ==
5698 01:15:24.783462 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5699 01:15:24.786067 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5700 01:15:24.789853 == TX Byte 1 ==
5701 01:15:24.792781 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5702 01:15:24.795867 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5703 01:15:24.796294
5704 01:15:24.799545 [DATLAT]
5705 01:15:24.799971 Freq=933, CH1 RK0
5706 01:15:24.800302
5707 01:15:24.802871 DATLAT Default: 0xd
5708 01:15:24.803384 0, 0xFFFF, sum = 0
5709 01:15:24.805905 1, 0xFFFF, sum = 0
5710 01:15:24.806330 2, 0xFFFF, sum = 0
5711 01:15:24.809817 3, 0xFFFF, sum = 0
5712 01:15:24.810381 4, 0xFFFF, sum = 0
5713 01:15:24.812941 5, 0xFFFF, sum = 0
5714 01:15:24.813363 6, 0xFFFF, sum = 0
5715 01:15:24.816288 7, 0xFFFF, sum = 0
5716 01:15:24.816754 8, 0xFFFF, sum = 0
5717 01:15:24.819550 9, 0xFFFF, sum = 0
5718 01:15:24.820064 10, 0x0, sum = 1
5719 01:15:24.822767 11, 0x0, sum = 2
5720 01:15:24.823188 12, 0x0, sum = 3
5721 01:15:24.826117 13, 0x0, sum = 4
5722 01:15:24.826635 best_step = 11
5723 01:15:24.826969
5724 01:15:24.827277 ==
5725 01:15:24.829247 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 01:15:24.836128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 01:15:24.836673 ==
5728 01:15:24.837013 RX Vref Scan: 1
5729 01:15:24.837325
5730 01:15:24.839794 RX Vref 0 -> 0, step: 1
5731 01:15:24.840317
5732 01:15:24.842474 RX Delay -69 -> 252, step: 4
5733 01:15:24.842917
5734 01:15:24.845879 Set Vref, RX VrefLevel [Byte0]: 59
5735 01:15:24.849161 [Byte1]: 43
5736 01:15:24.849673
5737 01:15:24.852198 Final RX Vref Byte 0 = 59 to rank0
5738 01:15:24.855973 Final RX Vref Byte 1 = 43 to rank0
5739 01:15:24.858909 Final RX Vref Byte 0 = 59 to rank1
5740 01:15:24.862671 Final RX Vref Byte 1 = 43 to rank1==
5741 01:15:24.865502 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 01:15:24.868871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 01:15:24.869406 ==
5744 01:15:24.872441 DQS Delay:
5745 01:15:24.872963 DQS0 = 0, DQS1 = 0
5746 01:15:24.875554 DQM Delay:
5747 01:15:24.876126 DQM0 = 96, DQM1 = 88
5748 01:15:24.876476 DQ Delay:
5749 01:15:24.879293 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =92
5750 01:15:24.882117 DQ4 =94, DQ5 =108, DQ6 =106, DQ7 =94
5751 01:15:24.885622 DQ8 =74, DQ9 =78, DQ10 =86, DQ11 =82
5752 01:15:24.888745 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96
5753 01:15:24.889168
5754 01:15:24.892258
5755 01:15:24.898703 [DQSOSCAuto] RK0, (LSB)MR18= 0xfc05, (MSB)MR19= 0x405, tDQSOscB0 = 420 ps tDQSOscB1 = 423 ps
5756 01:15:24.902168 CH1 RK0: MR19=405, MR18=FC05
5757 01:15:24.908738 CH1_RK0: MR19=0x405, MR18=0xFC05, DQSOSC=420, MR23=63, INC=61, DEC=40
5758 01:15:24.909277
5759 01:15:24.912255 ----->DramcWriteLeveling(PI) begin...
5760 01:15:24.912709 ==
5761 01:15:24.915486 Dram Type= 6, Freq= 0, CH_1, rank 1
5762 01:15:24.919257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 01:15:24.919808 ==
5764 01:15:24.922027 Write leveling (Byte 0): 28 => 28
5765 01:15:24.925423 Write leveling (Byte 1): 29 => 29
5766 01:15:24.928994 DramcWriteLeveling(PI) end<-----
5767 01:15:24.929557
5768 01:15:24.929905 ==
5769 01:15:24.932088 Dram Type= 6, Freq= 0, CH_1, rank 1
5770 01:15:24.935565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 01:15:24.936096 ==
5772 01:15:24.938965 [Gating] SW mode calibration
5773 01:15:24.945908 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5774 01:15:24.951981 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5775 01:15:24.955145 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5776 01:15:24.958621 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 01:15:24.965119 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 01:15:24.968538 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 01:15:24.971768 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 01:15:24.978415 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 01:15:24.981552 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
5782 01:15:24.985052 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5783 01:15:24.992158 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 01:15:24.994922 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 01:15:24.998433 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 01:15:25.005106 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 01:15:25.008588 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 01:15:25.011030 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 01:15:25.018225 0 15 24 | B1->B0 | 2525 3232 | 0 0 | (0 0) (1 1)
5790 01:15:25.021207 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5791 01:15:25.025109 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 01:15:25.031203 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 01:15:25.034403 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 01:15:25.037588 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 01:15:25.044812 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 01:15:25.047945 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5797 01:15:25.050981 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5798 01:15:25.058511 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5799 01:15:25.060841 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 01:15:25.064198 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 01:15:25.071231 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 01:15:25.074248 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 01:15:25.077488 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 01:15:25.084483 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 01:15:25.088092 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 01:15:25.091015 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 01:15:25.097582 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 01:15:25.101153 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 01:15:25.104159 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 01:15:25.110507 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 01:15:25.113808 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 01:15:25.117436 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 01:15:25.124138 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5814 01:15:25.127247 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5815 01:15:25.130551 Total UI for P1: 0, mck2ui 16
5816 01:15:25.133770 best dqsien dly found for B0: ( 1, 2, 24)
5817 01:15:25.137019 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 01:15:25.140539 Total UI for P1: 0, mck2ui 16
5819 01:15:25.143816 best dqsien dly found for B1: ( 1, 2, 26)
5820 01:15:25.147360 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5821 01:15:25.150262 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5822 01:15:25.150678
5823 01:15:25.153558 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5824 01:15:25.160610 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5825 01:15:25.161131 [Gating] SW calibration Done
5826 01:15:25.161466 ==
5827 01:15:25.163365 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 01:15:25.170153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 01:15:25.170573 ==
5830 01:15:25.170902 RX Vref Scan: 0
5831 01:15:25.171216
5832 01:15:25.174079 RX Vref 0 -> 0, step: 1
5833 01:15:25.174598
5834 01:15:25.176933 RX Delay -80 -> 252, step: 8
5835 01:15:25.180125 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5836 01:15:25.183280 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5837 01:15:25.187050 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5838 01:15:25.193402 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5839 01:15:25.196731 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5840 01:15:25.200036 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5841 01:15:25.203327 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5842 01:15:25.206878 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5843 01:15:25.210442 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5844 01:15:25.216497 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5845 01:15:25.219873 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5846 01:15:25.222955 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5847 01:15:25.226940 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5848 01:15:25.229564 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5849 01:15:25.237060 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5850 01:15:25.239976 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5851 01:15:25.240493 ==
5852 01:15:25.243640 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 01:15:25.246347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 01:15:25.246868 ==
5855 01:15:25.249852 DQS Delay:
5856 01:15:25.250367 DQS0 = 0, DQS1 = 0
5857 01:15:25.250706 DQM Delay:
5858 01:15:25.253302 DQM0 = 93, DQM1 = 86
5859 01:15:25.253777 DQ Delay:
5860 01:15:25.256525 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5861 01:15:25.259554 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5862 01:15:25.262710 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5863 01:15:25.266372 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5864 01:15:25.266895
5865 01:15:25.267224
5866 01:15:25.267529 ==
5867 01:15:25.269694 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 01:15:25.276204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 01:15:25.276738 ==
5870 01:15:25.277076
5871 01:15:25.277386
5872 01:15:25.277759 TX Vref Scan disable
5873 01:15:25.279870 == TX Byte 0 ==
5874 01:15:25.282394 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5875 01:15:25.289267 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5876 01:15:25.289874 == TX Byte 1 ==
5877 01:15:25.292418 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5878 01:15:25.298855 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5879 01:15:25.299353 ==
5880 01:15:25.302844 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 01:15:25.305778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 01:15:25.306290 ==
5883 01:15:25.306625
5884 01:15:25.307054
5885 01:15:25.309225 TX Vref Scan disable
5886 01:15:25.309791 == TX Byte 0 ==
5887 01:15:25.316282 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5888 01:15:25.319111 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5889 01:15:25.322551 == TX Byte 1 ==
5890 01:15:25.325819 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5891 01:15:25.329304 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5892 01:15:25.329877
5893 01:15:25.330221 [DATLAT]
5894 01:15:25.332695 Freq=933, CH1 RK1
5895 01:15:25.333203
5896 01:15:25.333595 DATLAT Default: 0xb
5897 01:15:25.335672 0, 0xFFFF, sum = 0
5898 01:15:25.339135 1, 0xFFFF, sum = 0
5899 01:15:25.339654 2, 0xFFFF, sum = 0
5900 01:15:25.342558 3, 0xFFFF, sum = 0
5901 01:15:25.343070 4, 0xFFFF, sum = 0
5902 01:15:25.345532 5, 0xFFFF, sum = 0
5903 01:15:25.346061 6, 0xFFFF, sum = 0
5904 01:15:25.349148 7, 0xFFFF, sum = 0
5905 01:15:25.349722 8, 0xFFFF, sum = 0
5906 01:15:25.352126 9, 0xFFFF, sum = 0
5907 01:15:25.352646 10, 0x0, sum = 1
5908 01:15:25.355548 11, 0x0, sum = 2
5909 01:15:25.356066 12, 0x0, sum = 3
5910 01:15:25.359022 13, 0x0, sum = 4
5911 01:15:25.359543 best_step = 11
5912 01:15:25.359878
5913 01:15:25.360190 ==
5914 01:15:25.362183 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 01:15:25.365414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 01:15:25.365999 ==
5917 01:15:25.368874 RX Vref Scan: 0
5918 01:15:25.369385
5919 01:15:25.372431 RX Vref 0 -> 0, step: 1
5920 01:15:25.372944
5921 01:15:25.373281 RX Delay -69 -> 252, step: 4
5922 01:15:25.379641 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5923 01:15:25.383289 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5924 01:15:25.386918 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5925 01:15:25.389842 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5926 01:15:25.393183 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5927 01:15:25.399831 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5928 01:15:25.403084 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5929 01:15:25.406272 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5930 01:15:25.409689 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5931 01:15:25.412887 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5932 01:15:25.416773 iDelay=203, Bit 10, Center 90 (-1 ~ 182) 184
5933 01:15:25.422802 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5934 01:15:25.426441 iDelay=203, Bit 12, Center 100 (15 ~ 186) 172
5935 01:15:25.429759 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5936 01:15:25.433194 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5937 01:15:25.436350 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5938 01:15:25.439724 ==
5939 01:15:25.440236 Dram Type= 6, Freq= 0, CH_1, rank 1
5940 01:15:25.446480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5941 01:15:25.447048 ==
5942 01:15:25.447385 DQS Delay:
5943 01:15:25.449871 DQS0 = 0, DQS1 = 0
5944 01:15:25.450385 DQM Delay:
5945 01:15:25.453398 DQM0 = 91, DQM1 = 89
5946 01:15:25.453948 DQ Delay:
5947 01:15:25.456329 DQ0 =96, DQ1 =88, DQ2 =82, DQ3 =88
5948 01:15:25.459930 DQ4 =88, DQ5 =100, DQ6 =102, DQ7 =88
5949 01:15:25.463379 DQ8 =78, DQ9 =82, DQ10 =90, DQ11 =82
5950 01:15:25.466175 DQ12 =100, DQ13 =96, DQ14 =94, DQ15 =96
5951 01:15:25.466700
5952 01:15:25.467034
5953 01:15:25.473314 [DQSOSCAuto] RK1, (LSB)MR18= 0xa1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5954 01:15:25.476188 CH1 RK1: MR19=505, MR18=A1E
5955 01:15:25.482832 CH1_RK1: MR19=0x505, MR18=0xA1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5956 01:15:25.486466 [RxdqsGatingPostProcess] freq 933
5957 01:15:25.489768 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5958 01:15:25.493156 best DQS0 dly(2T, 0.5T) = (0, 10)
5959 01:15:25.496088 best DQS1 dly(2T, 0.5T) = (0, 10)
5960 01:15:25.499327 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5961 01:15:25.502541 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5962 01:15:25.505871 best DQS0 dly(2T, 0.5T) = (0, 10)
5963 01:15:25.509284 best DQS1 dly(2T, 0.5T) = (0, 10)
5964 01:15:25.512171 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5965 01:15:25.516382 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5966 01:15:25.518989 Pre-setting of DQS Precalculation
5967 01:15:25.522253 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5968 01:15:25.532219 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5969 01:15:25.539044 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5970 01:15:25.539572
5971 01:15:25.539907
5972 01:15:25.542329 [Calibration Summary] 1866 Mbps
5973 01:15:25.542851 CH 0, Rank 0
5974 01:15:25.545495 SW Impedance : PASS
5975 01:15:25.545988 DUTY Scan : NO K
5976 01:15:25.549005 ZQ Calibration : PASS
5977 01:15:25.551844 Jitter Meter : NO K
5978 01:15:25.552261 CBT Training : PASS
5979 01:15:25.555461 Write leveling : PASS
5980 01:15:25.559443 RX DQS gating : PASS
5981 01:15:25.559959 RX DQ/DQS(RDDQC) : PASS
5982 01:15:25.562055 TX DQ/DQS : PASS
5983 01:15:25.565689 RX DATLAT : PASS
5984 01:15:25.566202 RX DQ/DQS(Engine): PASS
5985 01:15:25.569134 TX OE : NO K
5986 01:15:25.569689 All Pass.
5987 01:15:25.570036
5988 01:15:25.572022 CH 0, Rank 1
5989 01:15:25.572533 SW Impedance : PASS
5990 01:15:25.575463 DUTY Scan : NO K
5991 01:15:25.578975 ZQ Calibration : PASS
5992 01:15:25.579484 Jitter Meter : NO K
5993 01:15:25.581925 CBT Training : PASS
5994 01:15:25.585328 Write leveling : PASS
5995 01:15:25.585885 RX DQS gating : PASS
5996 01:15:25.588873 RX DQ/DQS(RDDQC) : PASS
5997 01:15:25.592136 TX DQ/DQS : PASS
5998 01:15:25.592658 RX DATLAT : PASS
5999 01:15:25.595447 RX DQ/DQS(Engine): PASS
6000 01:15:25.598041 TX OE : NO K
6001 01:15:25.598486 All Pass.
6002 01:15:25.598815
6003 01:15:25.599123 CH 1, Rank 0
6004 01:15:25.601741 SW Impedance : PASS
6005 01:15:25.605568 DUTY Scan : NO K
6006 01:15:25.606108 ZQ Calibration : PASS
6007 01:15:25.608180 Jitter Meter : NO K
6008 01:15:25.608596 CBT Training : PASS
6009 01:15:25.611714 Write leveling : PASS
6010 01:15:25.615340 RX DQS gating : PASS
6011 01:15:25.615858 RX DQ/DQS(RDDQC) : PASS
6012 01:15:25.617929 TX DQ/DQS : PASS
6013 01:15:25.621399 RX DATLAT : PASS
6014 01:15:25.621848 RX DQ/DQS(Engine): PASS
6015 01:15:25.624957 TX OE : NO K
6016 01:15:25.625492 All Pass.
6017 01:15:25.625887
6018 01:15:25.628422 CH 1, Rank 1
6019 01:15:25.628833 SW Impedance : PASS
6020 01:15:25.631737 DUTY Scan : NO K
6021 01:15:25.634965 ZQ Calibration : PASS
6022 01:15:25.635385 Jitter Meter : NO K
6023 01:15:25.638296 CBT Training : PASS
6024 01:15:25.641178 Write leveling : PASS
6025 01:15:25.641727 RX DQS gating : PASS
6026 01:15:25.644823 RX DQ/DQS(RDDQC) : PASS
6027 01:15:25.647840 TX DQ/DQS : PASS
6028 01:15:25.648369 RX DATLAT : PASS
6029 01:15:25.651248 RX DQ/DQS(Engine): PASS
6030 01:15:25.654401 TX OE : NO K
6031 01:15:25.654820 All Pass.
6032 01:15:25.655150
6033 01:15:25.655455 DramC Write-DBI off
6034 01:15:25.658235 PER_BANK_REFRESH: Hybrid Mode
6035 01:15:25.661227 TX_TRACKING: ON
6036 01:15:25.668055 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6037 01:15:25.670640 [FAST_K] Save calibration result to emmc
6038 01:15:25.677456 dramc_set_vcore_voltage set vcore to 650000
6039 01:15:25.677998 Read voltage for 400, 6
6040 01:15:25.680742 Vio18 = 0
6041 01:15:25.681156 Vcore = 650000
6042 01:15:25.681488 Vdram = 0
6043 01:15:25.684195 Vddq = 0
6044 01:15:25.684611 Vmddr = 0
6045 01:15:25.687998 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6046 01:15:25.694519 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6047 01:15:25.697826 MEM_TYPE=3, freq_sel=20
6048 01:15:25.700758 sv_algorithm_assistance_LP4_800
6049 01:15:25.704518 ============ PULL DRAM RESETB DOWN ============
6050 01:15:25.707548 ========== PULL DRAM RESETB DOWN end =========
6051 01:15:25.710695 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6052 01:15:25.714047 ===================================
6053 01:15:25.717680 LPDDR4 DRAM CONFIGURATION
6054 01:15:25.721144 ===================================
6055 01:15:25.723829 EX_ROW_EN[0] = 0x0
6056 01:15:25.724242 EX_ROW_EN[1] = 0x0
6057 01:15:25.727208 LP4Y_EN = 0x0
6058 01:15:25.727629 WORK_FSP = 0x0
6059 01:15:25.730936 WL = 0x2
6060 01:15:25.731352 RL = 0x2
6061 01:15:25.734013 BL = 0x2
6062 01:15:25.734428 RPST = 0x0
6063 01:15:25.737222 RD_PRE = 0x0
6064 01:15:25.737674 WR_PRE = 0x1
6065 01:15:25.740723 WR_PST = 0x0
6066 01:15:25.744121 DBI_WR = 0x0
6067 01:15:25.744551 DBI_RD = 0x0
6068 01:15:25.747639 OTF = 0x1
6069 01:15:25.750594 ===================================
6070 01:15:25.753622 ===================================
6071 01:15:25.754095 ANA top config
6072 01:15:25.757343 ===================================
6073 01:15:25.760829 DLL_ASYNC_EN = 0
6074 01:15:25.761343 ALL_SLAVE_EN = 1
6075 01:15:25.764115 NEW_RANK_MODE = 1
6076 01:15:25.767563 DLL_IDLE_MODE = 1
6077 01:15:25.770343 LP45_APHY_COMB_EN = 1
6078 01:15:25.773842 TX_ODT_DIS = 1
6079 01:15:25.774261 NEW_8X_MODE = 1
6080 01:15:25.777683 ===================================
6081 01:15:25.781152 ===================================
6082 01:15:25.784319 data_rate = 800
6083 01:15:25.787222 CKR = 1
6084 01:15:25.790203 DQ_P2S_RATIO = 4
6085 01:15:25.793593 ===================================
6086 01:15:25.797046 CA_P2S_RATIO = 4
6087 01:15:25.800420 DQ_CA_OPEN = 0
6088 01:15:25.800846 DQ_SEMI_OPEN = 1
6089 01:15:25.803320 CA_SEMI_OPEN = 1
6090 01:15:25.807344 CA_FULL_RATE = 0
6091 01:15:25.810746 DQ_CKDIV4_EN = 0
6092 01:15:25.813683 CA_CKDIV4_EN = 1
6093 01:15:25.816981 CA_PREDIV_EN = 0
6094 01:15:25.817489 PH8_DLY = 0
6095 01:15:25.819940 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6096 01:15:25.823207 DQ_AAMCK_DIV = 0
6097 01:15:25.827033 CA_AAMCK_DIV = 0
6098 01:15:25.830057 CA_ADMCK_DIV = 4
6099 01:15:25.833859 DQ_TRACK_CA_EN = 0
6100 01:15:25.834377 CA_PICK = 800
6101 01:15:25.836575 CA_MCKIO = 400
6102 01:15:25.839844 MCKIO_SEMI = 400
6103 01:15:25.843883 PLL_FREQ = 3016
6104 01:15:25.846857 DQ_UI_PI_RATIO = 32
6105 01:15:25.850303 CA_UI_PI_RATIO = 32
6106 01:15:25.853234 ===================================
6107 01:15:25.856684 ===================================
6108 01:15:25.860171 memory_type:LPDDR4
6109 01:15:25.860692 GP_NUM : 10
6110 01:15:25.863239 SRAM_EN : 1
6111 01:15:25.863659 MD32_EN : 0
6112 01:15:25.866807 ===================================
6113 01:15:25.869972 [ANA_INIT] >>>>>>>>>>>>>>
6114 01:15:25.872991 <<<<<< [CONFIGURE PHASE]: ANA_TX
6115 01:15:25.876885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6116 01:15:25.879959 ===================================
6117 01:15:25.883004 data_rate = 800,PCW = 0X7400
6118 01:15:25.886581 ===================================
6119 01:15:25.890012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6120 01:15:25.896442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6121 01:15:25.906381 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6122 01:15:25.909627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6123 01:15:25.913313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6124 01:15:25.916442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6125 01:15:25.919172 [ANA_INIT] flow start
6126 01:15:25.922779 [ANA_INIT] PLL >>>>>>>>
6127 01:15:25.923194 [ANA_INIT] PLL <<<<<<<<
6128 01:15:25.926234 [ANA_INIT] MIDPI >>>>>>>>
6129 01:15:25.930002 [ANA_INIT] MIDPI <<<<<<<<
6130 01:15:25.932525 [ANA_INIT] DLL >>>>>>>>
6131 01:15:25.932941 [ANA_INIT] flow end
6132 01:15:25.936163 ============ LP4 DIFF to SE enter ============
6133 01:15:25.942630 ============ LP4 DIFF to SE exit ============
6134 01:15:25.943154 [ANA_INIT] <<<<<<<<<<<<<
6135 01:15:25.946049 [Flow] Enable top DCM control >>>>>
6136 01:15:25.949854 [Flow] Enable top DCM control <<<<<
6137 01:15:25.953130 Enable DLL master slave shuffle
6138 01:15:25.959073 ==============================================================
6139 01:15:25.959583 Gating Mode config
6140 01:15:25.966436 ==============================================================
6141 01:15:25.968972 Config description:
6142 01:15:25.979134 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6143 01:15:25.986143 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6144 01:15:25.989600 SELPH_MODE 0: By rank 1: By Phase
6145 01:15:25.995576 ==============================================================
6146 01:15:25.998864 GAT_TRACK_EN = 0
6147 01:15:26.002163 RX_GATING_MODE = 2
6148 01:15:26.002583 RX_GATING_TRACK_MODE = 2
6149 01:15:26.005588 SELPH_MODE = 1
6150 01:15:26.008695 PICG_EARLY_EN = 1
6151 01:15:26.012068 VALID_LAT_VALUE = 1
6152 01:15:26.018638 ==============================================================
6153 01:15:26.022087 Enter into Gating configuration >>>>
6154 01:15:26.025502 Exit from Gating configuration <<<<
6155 01:15:26.028985 Enter into DVFS_PRE_config >>>>>
6156 01:15:26.038925 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6157 01:15:26.042382 Exit from DVFS_PRE_config <<<<<
6158 01:15:26.045395 Enter into PICG configuration >>>>
6159 01:15:26.048977 Exit from PICG configuration <<<<
6160 01:15:26.052058 [RX_INPUT] configuration >>>>>
6161 01:15:26.055632 [RX_INPUT] configuration <<<<<
6162 01:15:26.058394 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6163 01:15:26.065676 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6164 01:15:26.071677 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6165 01:15:26.078094 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6166 01:15:26.081296 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6167 01:15:26.088490 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6168 01:15:26.094836 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6169 01:15:26.097966 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6170 01:15:26.101466 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6171 01:15:26.105017 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6172 01:15:26.108684 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6173 01:15:26.114726 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6174 01:15:26.118271 ===================================
6175 01:15:26.121259 LPDDR4 DRAM CONFIGURATION
6176 01:15:26.124399 ===================================
6177 01:15:26.124816 EX_ROW_EN[0] = 0x0
6178 01:15:26.128346 EX_ROW_EN[1] = 0x0
6179 01:15:26.128879 LP4Y_EN = 0x0
6180 01:15:26.131740 WORK_FSP = 0x0
6181 01:15:26.132260 WL = 0x2
6182 01:15:26.135410 RL = 0x2
6183 01:15:26.135925 BL = 0x2
6184 01:15:26.138005 RPST = 0x0
6185 01:15:26.138419 RD_PRE = 0x0
6186 01:15:26.141034 WR_PRE = 0x1
6187 01:15:26.141446 WR_PST = 0x0
6188 01:15:26.144362 DBI_WR = 0x0
6189 01:15:26.144926 DBI_RD = 0x0
6190 01:15:26.147660 OTF = 0x1
6191 01:15:26.151366 ===================================
6192 01:15:26.154712 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6193 01:15:26.158370 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6194 01:15:26.164836 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6195 01:15:26.167768 ===================================
6196 01:15:26.171087 LPDDR4 DRAM CONFIGURATION
6197 01:15:26.174159 ===================================
6198 01:15:26.174581 EX_ROW_EN[0] = 0x10
6199 01:15:26.177959 EX_ROW_EN[1] = 0x0
6200 01:15:26.178478 LP4Y_EN = 0x0
6201 01:15:26.180978 WORK_FSP = 0x0
6202 01:15:26.181493 WL = 0x2
6203 01:15:26.184605 RL = 0x2
6204 01:15:26.185125 BL = 0x2
6205 01:15:26.187989 RPST = 0x0
6206 01:15:26.188507 RD_PRE = 0x0
6207 01:15:26.190923 WR_PRE = 0x1
6208 01:15:26.191447 WR_PST = 0x0
6209 01:15:26.194356 DBI_WR = 0x0
6210 01:15:26.194914 DBI_RD = 0x0
6211 01:15:26.197486 OTF = 0x1
6212 01:15:26.200835 ===================================
6213 01:15:26.207651 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6214 01:15:26.210368 nWR fixed to 30
6215 01:15:26.214300 [ModeRegInit_LP4] CH0 RK0
6216 01:15:26.214721 [ModeRegInit_LP4] CH0 RK1
6217 01:15:26.217618 [ModeRegInit_LP4] CH1 RK0
6218 01:15:26.220254 [ModeRegInit_LP4] CH1 RK1
6219 01:15:26.220825 match AC timing 19
6220 01:15:26.227633 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6221 01:15:26.230962 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6222 01:15:26.233623 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6223 01:15:26.240780 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6224 01:15:26.243958 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6225 01:15:26.244478 ==
6226 01:15:26.246866 Dram Type= 6, Freq= 0, CH_0, rank 0
6227 01:15:26.250446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6228 01:15:26.250983 ==
6229 01:15:26.257324 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6230 01:15:26.263497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6231 01:15:26.267137 [CA 0] Center 36 (8~64) winsize 57
6232 01:15:26.270729 [CA 1] Center 36 (8~64) winsize 57
6233 01:15:26.273604 [CA 2] Center 36 (8~64) winsize 57
6234 01:15:26.277166 [CA 3] Center 36 (8~64) winsize 57
6235 01:15:26.280432 [CA 4] Center 36 (8~64) winsize 57
6236 01:15:26.280951 [CA 5] Center 36 (8~64) winsize 57
6237 01:15:26.281284
6238 01:15:26.286863 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6239 01:15:26.287384
6240 01:15:26.289943 [CATrainingPosCal] consider 1 rank data
6241 01:15:26.293897 u2DelayCellTimex100 = 270/100 ps
6242 01:15:26.297170 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 01:15:26.300151 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 01:15:26.303203 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 01:15:26.306656 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 01:15:26.309752 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 01:15:26.313232 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 01:15:26.313825
6249 01:15:26.316769 CA PerBit enable=1, Macro0, CA PI delay=36
6250 01:15:26.317408
6251 01:15:26.320169 [CBTSetCACLKResult] CA Dly = 36
6252 01:15:26.323267 CS Dly: 1 (0~32)
6253 01:15:26.323880 ==
6254 01:15:26.326173 Dram Type= 6, Freq= 0, CH_0, rank 1
6255 01:15:26.329678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 01:15:26.330101 ==
6257 01:15:26.336697 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6258 01:15:26.342782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6259 01:15:26.346288 [CA 0] Center 36 (8~64) winsize 57
6260 01:15:26.346777 [CA 1] Center 36 (8~64) winsize 57
6261 01:15:26.349772 [CA 2] Center 36 (8~64) winsize 57
6262 01:15:26.352839 [CA 3] Center 36 (8~64) winsize 57
6263 01:15:26.356431 [CA 4] Center 36 (8~64) winsize 57
6264 01:15:26.359606 [CA 5] Center 36 (8~64) winsize 57
6265 01:15:26.360117
6266 01:15:26.362870 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6267 01:15:26.363286
6268 01:15:26.369669 [CATrainingPosCal] consider 2 rank data
6269 01:15:26.370177 u2DelayCellTimex100 = 270/100 ps
6270 01:15:26.373118 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 01:15:26.379525 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 01:15:26.382681 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 01:15:26.385990 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 01:15:26.389497 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 01:15:26.392843 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 01:15:26.393353
6277 01:15:26.396021 CA PerBit enable=1, Macro0, CA PI delay=36
6278 01:15:26.396438
6279 01:15:26.399552 [CBTSetCACLKResult] CA Dly = 36
6280 01:15:26.403065 CS Dly: 1 (0~32)
6281 01:15:26.403581
6282 01:15:26.406042 ----->DramcWriteLeveling(PI) begin...
6283 01:15:26.406565 ==
6284 01:15:26.409554 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 01:15:26.412874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 01:15:26.413457 ==
6287 01:15:26.416214 Write leveling (Byte 0): 40 => 8
6288 01:15:26.419584 Write leveling (Byte 1): 40 => 8
6289 01:15:26.422293 DramcWriteLeveling(PI) end<-----
6290 01:15:26.422727
6291 01:15:26.423059 ==
6292 01:15:26.425575 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 01:15:26.428804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 01:15:26.429236 ==
6295 01:15:26.431948 [Gating] SW mode calibration
6296 01:15:26.438727 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6297 01:15:26.445077 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6298 01:15:26.448733 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6299 01:15:26.452415 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6300 01:15:26.458749 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 01:15:26.462200 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6302 01:15:26.465433 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 01:15:26.471743 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 01:15:26.475027 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 01:15:26.478385 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 01:15:26.485393 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 01:15:26.485951 Total UI for P1: 0, mck2ui 16
6308 01:15:26.491783 best dqsien dly found for B0: ( 0, 14, 24)
6309 01:15:26.492300 Total UI for P1: 0, mck2ui 16
6310 01:15:26.498093 best dqsien dly found for B1: ( 0, 14, 24)
6311 01:15:26.501755 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6312 01:15:26.505222 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6313 01:15:26.505795
6314 01:15:26.508881 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6315 01:15:26.511695 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6316 01:15:26.515044 [Gating] SW calibration Done
6317 01:15:26.515596 ==
6318 01:15:26.518730 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 01:15:26.521265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 01:15:26.521763 ==
6321 01:15:26.524787 RX Vref Scan: 0
6322 01:15:26.525191
6323 01:15:26.525542 RX Vref 0 -> 0, step: 1
6324 01:15:26.528539
6325 01:15:26.529049 RX Delay -410 -> 252, step: 16
6326 01:15:26.535227 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6327 01:15:26.538239 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6328 01:15:26.541460 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6329 01:15:26.544546 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6330 01:15:26.551180 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6331 01:15:26.554556 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6332 01:15:26.558356 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6333 01:15:26.561689 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6334 01:15:26.567931 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6335 01:15:26.571280 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6336 01:15:26.574584 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6337 01:15:26.577951 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6338 01:15:26.584516 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6339 01:15:26.588108 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6340 01:15:26.591024 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6341 01:15:26.598029 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6342 01:15:26.598550 ==
6343 01:15:26.600885 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 01:15:26.604466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 01:15:26.605016 ==
6346 01:15:26.605360 DQS Delay:
6347 01:15:26.607610 DQS0 = 59, DQS1 = 59
6348 01:15:26.608120 DQM Delay:
6349 01:15:26.610689 DQM0 = 18, DQM1 = 10
6350 01:15:26.611104 DQ Delay:
6351 01:15:26.614198 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6352 01:15:26.617621 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6353 01:15:26.620651 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6354 01:15:26.624037 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6355 01:15:26.624451
6356 01:15:26.624780
6357 01:15:26.625162 ==
6358 01:15:26.627905 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 01:15:26.630737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 01:15:26.631260 ==
6361 01:15:26.631589
6362 01:15:26.631892
6363 01:15:26.633675 TX Vref Scan disable
6364 01:15:26.637561 == TX Byte 0 ==
6365 01:15:26.641042 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 01:15:26.644428 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 01:15:26.647268 == TX Byte 1 ==
6368 01:15:26.650506 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 01:15:26.653498 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 01:15:26.653948 ==
6371 01:15:26.657284 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 01:15:26.660783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 01:15:26.661299 ==
6374 01:15:26.663644
6375 01:15:26.664053
6376 01:15:26.664378 TX Vref Scan disable
6377 01:15:26.667168 == TX Byte 0 ==
6378 01:15:26.670500 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 01:15:26.673986 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 01:15:26.677120 == TX Byte 1 ==
6381 01:15:26.680174 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 01:15:26.684125 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 01:15:26.684643
6384 01:15:26.684972 [DATLAT]
6385 01:15:26.687461 Freq=400, CH0 RK0
6386 01:15:26.687972
6387 01:15:26.688302 DATLAT Default: 0xf
6388 01:15:26.690918 0, 0xFFFF, sum = 0
6389 01:15:26.693767 1, 0xFFFF, sum = 0
6390 01:15:26.694289 2, 0xFFFF, sum = 0
6391 01:15:26.697579 3, 0xFFFF, sum = 0
6392 01:15:26.698099 4, 0xFFFF, sum = 0
6393 01:15:26.699911 5, 0xFFFF, sum = 0
6394 01:15:26.700328 6, 0xFFFF, sum = 0
6395 01:15:26.703988 7, 0xFFFF, sum = 0
6396 01:15:26.704509 8, 0xFFFF, sum = 0
6397 01:15:26.706838 9, 0xFFFF, sum = 0
6398 01:15:26.707271 10, 0xFFFF, sum = 0
6399 01:15:26.710244 11, 0xFFFF, sum = 0
6400 01:15:26.710669 12, 0xFFFF, sum = 0
6401 01:15:26.713438 13, 0x0, sum = 1
6402 01:15:26.713876 14, 0x0, sum = 2
6403 01:15:26.717179 15, 0x0, sum = 3
6404 01:15:26.717779 16, 0x0, sum = 4
6405 01:15:26.720100 best_step = 14
6406 01:15:26.720510
6407 01:15:26.720834 ==
6408 01:15:26.723583 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 01:15:26.726912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 01:15:26.727440 ==
6411 01:15:26.730057 RX Vref Scan: 1
6412 01:15:26.730469
6413 01:15:26.730795 RX Vref 0 -> 0, step: 1
6414 01:15:26.731102
6415 01:15:26.733711 RX Delay -359 -> 252, step: 8
6416 01:15:26.734124
6417 01:15:26.736786 Set Vref, RX VrefLevel [Byte0]: 61
6418 01:15:26.739539 [Byte1]: 47
6419 01:15:26.744876
6420 01:15:26.745389 Final RX Vref Byte 0 = 61 to rank0
6421 01:15:26.747617 Final RX Vref Byte 1 = 47 to rank0
6422 01:15:26.751173 Final RX Vref Byte 0 = 61 to rank1
6423 01:15:26.754337 Final RX Vref Byte 1 = 47 to rank1==
6424 01:15:26.757897 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 01:15:26.764296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 01:15:26.764857 ==
6427 01:15:26.765194 DQS Delay:
6428 01:15:26.767831 DQS0 = 60, DQS1 = 68
6429 01:15:26.768346 DQM Delay:
6430 01:15:26.768680 DQM0 = 14, DQM1 = 14
6431 01:15:26.770665 DQ Delay:
6432 01:15:26.773802 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6433 01:15:26.777659 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6434 01:15:26.781161 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6435 01:15:26.783785 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6436 01:15:26.784224
6437 01:15:26.784551
6438 01:15:26.790592 [DQSOSCAuto] RK0, (LSB)MR18= 0x7b7a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
6439 01:15:26.793726 CH0 RK0: MR19=C0C, MR18=7B7A
6440 01:15:26.800593 CH0_RK0: MR19=0xC0C, MR18=0x7B7A, DQSOSC=394, MR23=63, INC=380, DEC=253
6441 01:15:26.801009 ==
6442 01:15:26.803654 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 01:15:26.807360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 01:15:26.807877 ==
6445 01:15:26.810026 [Gating] SW mode calibration
6446 01:15:26.817056 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6447 01:15:26.823193 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6448 01:15:26.826822 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6449 01:15:26.829806 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6450 01:15:26.836508 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 01:15:26.839990 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6452 01:15:26.843542 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 01:15:26.849771 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 01:15:26.853087 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 01:15:26.856378 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 01:15:26.863110 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 01:15:26.866314 Total UI for P1: 0, mck2ui 16
6458 01:15:26.869701 best dqsien dly found for B0: ( 0, 14, 24)
6459 01:15:26.872875 Total UI for P1: 0, mck2ui 16
6460 01:15:26.876279 best dqsien dly found for B1: ( 0, 14, 24)
6461 01:15:26.879867 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6462 01:15:26.882552 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6463 01:15:26.882977
6464 01:15:26.886024 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6465 01:15:26.889505 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6466 01:15:26.893335 [Gating] SW calibration Done
6467 01:15:26.893954 ==
6468 01:15:26.895764 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 01:15:26.899214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 01:15:26.899637 ==
6471 01:15:26.902763 RX Vref Scan: 0
6472 01:15:26.903227
6473 01:15:26.906447 RX Vref 0 -> 0, step: 1
6474 01:15:26.906960
6475 01:15:26.907295 RX Delay -410 -> 252, step: 16
6476 01:15:26.912890 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6477 01:15:26.916205 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6478 01:15:26.919969 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6479 01:15:26.925975 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6480 01:15:26.929275 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6481 01:15:26.932833 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6482 01:15:26.936258 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6483 01:15:26.942407 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6484 01:15:26.945955 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6485 01:15:26.948838 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6486 01:15:26.952719 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6487 01:15:26.959007 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6488 01:15:26.962217 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6489 01:15:26.965475 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6490 01:15:26.968948 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6491 01:15:26.975592 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6492 01:15:26.976109 ==
6493 01:15:26.978969 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 01:15:26.982283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 01:15:26.982816 ==
6496 01:15:26.983153 DQS Delay:
6497 01:15:26.985170 DQS0 = 59, DQS1 = 59
6498 01:15:26.985631 DQM Delay:
6499 01:15:26.988510 DQM0 = 16, DQM1 = 10
6500 01:15:26.988925 DQ Delay:
6501 01:15:26.992097 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6502 01:15:26.995256 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6503 01:15:26.998600 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6504 01:15:27.002143 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6505 01:15:27.002672
6506 01:15:27.003016
6507 01:15:27.003367 ==
6508 01:15:27.005060 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 01:15:27.008067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 01:15:27.011543 ==
6511 01:15:27.011959
6512 01:15:27.012283
6513 01:15:27.012589 TX Vref Scan disable
6514 01:15:27.015136 == TX Byte 0 ==
6515 01:15:27.018004 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6516 01:15:27.021928 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6517 01:15:27.024614 == TX Byte 1 ==
6518 01:15:27.027874 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6519 01:15:27.031855 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6520 01:15:27.032391 ==
6521 01:15:27.034425 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 01:15:27.041796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 01:15:27.042338 ==
6524 01:15:27.042778
6525 01:15:27.043181
6526 01:15:27.043576 TX Vref Scan disable
6527 01:15:27.044338 == TX Byte 0 ==
6528 01:15:27.047983 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6529 01:15:27.051332 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6530 01:15:27.054197 == TX Byte 1 ==
6531 01:15:27.057841 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6532 01:15:27.061455 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6533 01:15:27.062043
6534 01:15:27.064184 [DATLAT]
6535 01:15:27.064607 Freq=400, CH0 RK1
6536 01:15:27.065041
6537 01:15:27.067978 DATLAT Default: 0xe
6538 01:15:27.068508 0, 0xFFFF, sum = 0
6539 01:15:27.070674 1, 0xFFFF, sum = 0
6540 01:15:27.071139 2, 0xFFFF, sum = 0
6541 01:15:27.074289 3, 0xFFFF, sum = 0
6542 01:15:27.074722 4, 0xFFFF, sum = 0
6543 01:15:27.077253 5, 0xFFFF, sum = 0
6544 01:15:27.077727 6, 0xFFFF, sum = 0
6545 01:15:27.080760 7, 0xFFFF, sum = 0
6546 01:15:27.081286 8, 0xFFFF, sum = 0
6547 01:15:27.084508 9, 0xFFFF, sum = 0
6548 01:15:27.087302 10, 0xFFFF, sum = 0
6549 01:15:27.087809 11, 0xFFFF, sum = 0
6550 01:15:27.090354 12, 0xFFFF, sum = 0
6551 01:15:27.090787 13, 0x0, sum = 1
6552 01:15:27.094187 14, 0x0, sum = 2
6553 01:15:27.094725 15, 0x0, sum = 3
6554 01:15:27.097235 16, 0x0, sum = 4
6555 01:15:27.097710 best_step = 14
6556 01:15:27.098138
6557 01:15:27.098539 ==
6558 01:15:27.100517 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 01:15:27.103573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 01:15:27.104000 ==
6561 01:15:27.106819 RX Vref Scan: 0
6562 01:15:27.107232
6563 01:15:27.110414 RX Vref 0 -> 0, step: 1
6564 01:15:27.110830
6565 01:15:27.111160 RX Delay -359 -> 252, step: 8
6566 01:15:27.119281 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6567 01:15:27.122598 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6568 01:15:27.125618 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6569 01:15:27.132685 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6570 01:15:27.135654 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6571 01:15:27.139075 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6572 01:15:27.142506 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6573 01:15:27.148862 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6574 01:15:27.152690 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6575 01:15:27.155608 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6576 01:15:27.159082 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6577 01:15:27.165939 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6578 01:15:27.168864 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6579 01:15:27.172385 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6580 01:15:27.175429 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6581 01:15:27.182065 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6582 01:15:27.182590 ==
6583 01:15:27.185131 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 01:15:27.188776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 01:15:27.189301 ==
6586 01:15:27.189790 DQS Delay:
6587 01:15:27.191955 DQS0 = 60, DQS1 = 72
6588 01:15:27.192516 DQM Delay:
6589 01:15:27.194975 DQM0 = 11, DQM1 = 16
6590 01:15:27.195527 DQ Delay:
6591 01:15:27.198517 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6592 01:15:27.201909 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6593 01:15:27.205260 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6594 01:15:27.208743 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6595 01:15:27.209251
6596 01:15:27.209629
6597 01:15:27.215123 [DQSOSCAuto] RK1, (LSB)MR18= 0xc77d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6598 01:15:27.218362 CH0 RK1: MR19=C0C, MR18=C77D
6599 01:15:27.224843 CH0_RK1: MR19=0xC0C, MR18=0xC77D, DQSOSC=385, MR23=63, INC=398, DEC=265
6600 01:15:27.228597 [RxdqsGatingPostProcess] freq 400
6601 01:15:27.235077 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6602 01:15:27.238857 best DQS0 dly(2T, 0.5T) = (0, 10)
6603 01:15:27.239373 best DQS1 dly(2T, 0.5T) = (0, 10)
6604 01:15:27.241506 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6605 01:15:27.245305 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6606 01:15:27.248456 best DQS0 dly(2T, 0.5T) = (0, 10)
6607 01:15:27.252061 best DQS1 dly(2T, 0.5T) = (0, 10)
6608 01:15:27.254867 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6609 01:15:27.258413 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6610 01:15:27.261498 Pre-setting of DQS Precalculation
6611 01:15:27.268522 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6612 01:15:27.269078 ==
6613 01:15:27.271683 Dram Type= 6, Freq= 0, CH_1, rank 0
6614 01:15:27.274813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 01:15:27.275276 ==
6616 01:15:27.281107 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6617 01:15:27.288267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6618 01:15:27.291495 [CA 0] Center 36 (8~64) winsize 57
6619 01:15:27.292054 [CA 1] Center 36 (8~64) winsize 57
6620 01:15:27.294192 [CA 2] Center 36 (8~64) winsize 57
6621 01:15:27.297647 [CA 3] Center 36 (8~64) winsize 57
6622 01:15:27.301074 [CA 4] Center 36 (8~64) winsize 57
6623 01:15:27.304288 [CA 5] Center 36 (8~64) winsize 57
6624 01:15:27.304706
6625 01:15:27.307894 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6626 01:15:27.308411
6627 01:15:27.310989 [CATrainingPosCal] consider 1 rank data
6628 01:15:27.313984 u2DelayCellTimex100 = 270/100 ps
6629 01:15:27.317450 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 01:15:27.324190 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 01:15:27.327170 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 01:15:27.330710 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 01:15:27.334181 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 01:15:27.337455 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 01:15:27.337893
6636 01:15:27.340966 CA PerBit enable=1, Macro0, CA PI delay=36
6637 01:15:27.341480
6638 01:15:27.344168 [CBTSetCACLKResult] CA Dly = 36
6639 01:15:27.344678 CS Dly: 1 (0~32)
6640 01:15:27.347729 ==
6641 01:15:27.350694 Dram Type= 6, Freq= 0, CH_1, rank 1
6642 01:15:27.354141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 01:15:27.354657 ==
6644 01:15:27.357406 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6645 01:15:27.364527 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6646 01:15:27.367912 [CA 0] Center 36 (8~64) winsize 57
6647 01:15:27.370479 [CA 1] Center 36 (8~64) winsize 57
6648 01:15:27.374200 [CA 2] Center 36 (8~64) winsize 57
6649 01:15:27.377720 [CA 3] Center 36 (8~64) winsize 57
6650 01:15:27.380497 [CA 4] Center 36 (8~64) winsize 57
6651 01:15:27.383867 [CA 5] Center 36 (8~64) winsize 57
6652 01:15:27.384379
6653 01:15:27.387237 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6654 01:15:27.387670
6655 01:15:27.390562 [CATrainingPosCal] consider 2 rank data
6656 01:15:27.394042 u2DelayCellTimex100 = 270/100 ps
6657 01:15:27.396978 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 01:15:27.400517 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 01:15:27.403379 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 01:15:27.410282 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 01:15:27.413609 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 01:15:27.416632 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 01:15:27.417050
6664 01:15:27.420479 CA PerBit enable=1, Macro0, CA PI delay=36
6665 01:15:27.420990
6666 01:15:27.423115 [CBTSetCACLKResult] CA Dly = 36
6667 01:15:27.423531 CS Dly: 1 (0~32)
6668 01:15:27.423862
6669 01:15:27.426763 ----->DramcWriteLeveling(PI) begin...
6670 01:15:27.427200 ==
6671 01:15:27.429983 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 01:15:27.436548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 01:15:27.436965 ==
6674 01:15:27.439754 Write leveling (Byte 0): 40 => 8
6675 01:15:27.443137 Write leveling (Byte 1): 40 => 8
6676 01:15:27.443548 DramcWriteLeveling(PI) end<-----
6677 01:15:27.446399
6678 01:15:27.446848 ==
6679 01:15:27.449674 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 01:15:27.453282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 01:15:27.453859 ==
6682 01:15:27.456776 [Gating] SW mode calibration
6683 01:15:27.463461 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6684 01:15:27.466368 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6685 01:15:27.473050 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6686 01:15:27.476806 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6687 01:15:27.480193 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 01:15:27.486653 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6689 01:15:27.489745 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 01:15:27.492842 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 01:15:27.499625 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 01:15:27.503315 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 01:15:27.506231 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 01:15:27.509503 Total UI for P1: 0, mck2ui 16
6695 01:15:27.512973 best dqsien dly found for B0: ( 0, 14, 24)
6696 01:15:27.515694 Total UI for P1: 0, mck2ui 16
6697 01:15:27.519716 best dqsien dly found for B1: ( 0, 14, 24)
6698 01:15:27.522751 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6699 01:15:27.529167 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6700 01:15:27.529730
6701 01:15:27.532675 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6702 01:15:27.535583 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6703 01:15:27.538668 [Gating] SW calibration Done
6704 01:15:27.539082 ==
6705 01:15:27.542265 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 01:15:27.545473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 01:15:27.546030 ==
6708 01:15:27.548879 RX Vref Scan: 0
6709 01:15:27.549294
6710 01:15:27.549667 RX Vref 0 -> 0, step: 1
6711 01:15:27.549988
6712 01:15:27.551931 RX Delay -410 -> 252, step: 16
6713 01:15:27.555478 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6714 01:15:27.562367 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6715 01:15:27.565584 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6716 01:15:27.568686 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6717 01:15:27.571890 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6718 01:15:27.578639 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6719 01:15:27.582131 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6720 01:15:27.585238 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6721 01:15:27.588746 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6722 01:15:27.595256 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6723 01:15:27.598514 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6724 01:15:27.601845 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6725 01:15:27.608917 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6726 01:15:27.611898 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6727 01:15:27.615200 iDelay=230, Bit 14, Center -51 (-314 ~ 213) 528
6728 01:15:27.618140 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6729 01:15:27.618602 ==
6730 01:15:27.621878 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 01:15:27.628135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 01:15:27.628559 ==
6733 01:15:27.629010 DQS Delay:
6734 01:15:27.631771 DQS0 = 51, DQS1 = 67
6735 01:15:27.632283 DQM Delay:
6736 01:15:27.634796 DQM0 = 12, DQM1 = 17
6737 01:15:27.635249 DQ Delay:
6738 01:15:27.638248 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6739 01:15:27.641413 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6740 01:15:27.644655 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6741 01:15:27.648508 DQ12 =24, DQ13 =32, DQ14 =16, DQ15 =24
6742 01:15:27.649025
6743 01:15:27.649360
6744 01:15:27.649717 ==
6745 01:15:27.651557 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 01:15:27.654492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 01:15:27.654914 ==
6748 01:15:27.655246
6749 01:15:27.655554
6750 01:15:27.658131 TX Vref Scan disable
6751 01:15:27.658549 == TX Byte 0 ==
6752 01:15:27.664581 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 01:15:27.667924 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 01:15:27.668439 == TX Byte 1 ==
6755 01:15:27.674742 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 01:15:27.678070 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 01:15:27.678630 ==
6758 01:15:27.681182 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 01:15:27.684220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 01:15:27.684739 ==
6761 01:15:27.685070
6762 01:15:27.685374
6763 01:15:27.687869 TX Vref Scan disable
6764 01:15:27.688313 == TX Byte 0 ==
6765 01:15:27.694707 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 01:15:27.697328 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 01:15:27.697793 == TX Byte 1 ==
6768 01:15:27.704349 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 01:15:27.707778 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 01:15:27.708293
6771 01:15:27.708622 [DATLAT]
6772 01:15:27.710722 Freq=400, CH1 RK0
6773 01:15:27.711237
6774 01:15:27.711568 DATLAT Default: 0xf
6775 01:15:27.714147 0, 0xFFFF, sum = 0
6776 01:15:27.714663 1, 0xFFFF, sum = 0
6777 01:15:27.717640 2, 0xFFFF, sum = 0
6778 01:15:27.718167 3, 0xFFFF, sum = 0
6779 01:15:27.720580 4, 0xFFFF, sum = 0
6780 01:15:27.721099 5, 0xFFFF, sum = 0
6781 01:15:27.723791 6, 0xFFFF, sum = 0
6782 01:15:27.727278 7, 0xFFFF, sum = 0
6783 01:15:27.727711 8, 0xFFFF, sum = 0
6784 01:15:27.730334 9, 0xFFFF, sum = 0
6785 01:15:27.730751 10, 0xFFFF, sum = 0
6786 01:15:27.733889 11, 0xFFFF, sum = 0
6787 01:15:27.734403 12, 0xFFFF, sum = 0
6788 01:15:27.736797 13, 0x0, sum = 1
6789 01:15:27.737306 14, 0x0, sum = 2
6790 01:15:27.740606 15, 0x0, sum = 3
6791 01:15:27.741120 16, 0x0, sum = 4
6792 01:15:27.743612 best_step = 14
6793 01:15:27.744040
6794 01:15:27.744370 ==
6795 01:15:27.746739 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 01:15:27.749849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 01:15:27.750269 ==
6798 01:15:27.750596 RX Vref Scan: 1
6799 01:15:27.753678
6800 01:15:27.754189 RX Vref 0 -> 0, step: 1
6801 01:15:27.754525
6802 01:15:27.757128 RX Delay -375 -> 252, step: 8
6803 01:15:27.757703
6804 01:15:27.760062 Set Vref, RX VrefLevel [Byte0]: 59
6805 01:15:27.763253 [Byte1]: 43
6806 01:15:27.767461
6807 01:15:27.767875 Final RX Vref Byte 0 = 59 to rank0
6808 01:15:27.771170 Final RX Vref Byte 1 = 43 to rank0
6809 01:15:27.774551 Final RX Vref Byte 0 = 59 to rank1
6810 01:15:27.777684 Final RX Vref Byte 1 = 43 to rank1==
6811 01:15:27.781078 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 01:15:27.788130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 01:15:27.788659 ==
6814 01:15:27.789010 DQS Delay:
6815 01:15:27.791310 DQS0 = 56, DQS1 = 68
6816 01:15:27.791822 DQM Delay:
6817 01:15:27.792151 DQM0 = 13, DQM1 = 14
6818 01:15:27.795101 DQ Delay:
6819 01:15:27.797955 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6820 01:15:27.798472 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6821 01:15:27.800775 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6822 01:15:27.804352 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6823 01:15:27.804883
6824 01:15:27.805291
6825 01:15:27.814156 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f62, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 399 ps
6826 01:15:27.817664 CH1 RK0: MR19=C0C, MR18=4F62
6827 01:15:27.824029 CH1_RK0: MR19=0xC0C, MR18=0x4F62, DQSOSC=397, MR23=63, INC=374, DEC=249
6828 01:15:27.824531 ==
6829 01:15:27.827846 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 01:15:27.830953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 01:15:27.831375 ==
6832 01:15:27.833774 [Gating] SW mode calibration
6833 01:15:27.840848 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6834 01:15:27.847590 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6835 01:15:27.850366 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6836 01:15:27.853733 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6837 01:15:27.860424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 01:15:27.863343 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6839 01:15:27.867153 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 01:15:27.873768 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 01:15:27.877111 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 01:15:27.880566 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 01:15:27.886694 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 01:15:27.887135 Total UI for P1: 0, mck2ui 16
6845 01:15:27.894074 best dqsien dly found for B0: ( 0, 14, 24)
6846 01:15:27.894585 Total UI for P1: 0, mck2ui 16
6847 01:15:27.896843 best dqsien dly found for B1: ( 0, 14, 24)
6848 01:15:27.903973 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6849 01:15:27.906560 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6850 01:15:27.907092
6851 01:15:27.909849 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6852 01:15:27.913604 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6853 01:15:27.916554 [Gating] SW calibration Done
6854 01:15:27.916983 ==
6855 01:15:27.919884 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 01:15:27.922983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 01:15:27.923409 ==
6858 01:15:27.926399 RX Vref Scan: 0
6859 01:15:27.926818
6860 01:15:27.927151 RX Vref 0 -> 0, step: 1
6861 01:15:27.927463
6862 01:15:27.929969 RX Delay -410 -> 252, step: 16
6863 01:15:27.936741 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6864 01:15:27.939449 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6865 01:15:27.942771 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6866 01:15:27.946169 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6867 01:15:27.953077 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6868 01:15:27.956268 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6869 01:15:27.959420 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6870 01:15:27.962711 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6871 01:15:27.969171 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6872 01:15:27.973002 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6873 01:15:27.976167 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6874 01:15:27.979333 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6875 01:15:27.986364 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6876 01:15:27.988945 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6877 01:15:27.992397 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6878 01:15:27.995877 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6879 01:15:27.999674 ==
6880 01:15:28.002490 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 01:15:28.005950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 01:15:28.006374 ==
6883 01:15:28.006712 DQS Delay:
6884 01:15:28.009501 DQS0 = 59, DQS1 = 59
6885 01:15:28.009947 DQM Delay:
6886 01:15:28.012391 DQM0 = 19, DQM1 = 10
6887 01:15:28.012811 DQ Delay:
6888 01:15:28.015736 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6889 01:15:28.018731 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6890 01:15:28.022035 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6891 01:15:28.025914 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6892 01:15:28.026335
6893 01:15:28.026666
6894 01:15:28.026974 ==
6895 01:15:28.029178 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 01:15:28.032125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 01:15:28.032549 ==
6898 01:15:28.032879
6899 01:15:28.033189
6900 01:15:28.035432 TX Vref Scan disable
6901 01:15:28.035851 == TX Byte 0 ==
6902 01:15:28.042482 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6903 01:15:28.045295 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6904 01:15:28.045851 == TX Byte 1 ==
6905 01:15:28.052215 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6906 01:15:28.055169 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6907 01:15:28.055620 ==
6908 01:15:28.058705 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 01:15:28.061968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 01:15:28.062394 ==
6911 01:15:28.062730
6912 01:15:28.063041
6913 01:15:28.065387 TX Vref Scan disable
6914 01:15:28.068650 == TX Byte 0 ==
6915 01:15:28.072493 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6916 01:15:28.075538 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6917 01:15:28.078199 == TX Byte 1 ==
6918 01:15:28.081785 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6919 01:15:28.085059 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6920 01:15:28.085477
6921 01:15:28.085847 [DATLAT]
6922 01:15:28.088142 Freq=400, CH1 RK1
6923 01:15:28.088558
6924 01:15:28.088888 DATLAT Default: 0xe
6925 01:15:28.091639 0, 0xFFFF, sum = 0
6926 01:15:28.092063 1, 0xFFFF, sum = 0
6927 01:15:28.095238 2, 0xFFFF, sum = 0
6928 01:15:28.098401 3, 0xFFFF, sum = 0
6929 01:15:28.098829 4, 0xFFFF, sum = 0
6930 01:15:28.101679 5, 0xFFFF, sum = 0
6931 01:15:28.102107 6, 0xFFFF, sum = 0
6932 01:15:28.105560 7, 0xFFFF, sum = 0
6933 01:15:28.105991 8, 0xFFFF, sum = 0
6934 01:15:28.108198 9, 0xFFFF, sum = 0
6935 01:15:28.108623 10, 0xFFFF, sum = 0
6936 01:15:28.111600 11, 0xFFFF, sum = 0
6937 01:15:28.112025 12, 0xFFFF, sum = 0
6938 01:15:28.115076 13, 0x0, sum = 1
6939 01:15:28.115502 14, 0x0, sum = 2
6940 01:15:28.118390 15, 0x0, sum = 3
6941 01:15:28.118819 16, 0x0, sum = 4
6942 01:15:28.121340 best_step = 14
6943 01:15:28.121807
6944 01:15:28.122146 ==
6945 01:15:28.124961 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 01:15:28.128546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 01:15:28.129079 ==
6948 01:15:28.129418 RX Vref Scan: 0
6949 01:15:28.131799
6950 01:15:28.132217 RX Vref 0 -> 0, step: 1
6951 01:15:28.132552
6952 01:15:28.134851 RX Delay -359 -> 252, step: 8
6953 01:15:28.142437 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6954 01:15:28.145674 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6955 01:15:28.148801 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6956 01:15:28.155351 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6957 01:15:28.158719 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6958 01:15:28.161939 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6959 01:15:28.165765 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6960 01:15:28.172215 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6961 01:15:28.175055 iDelay=217, Bit 8, Center -68 (-319 ~ 184) 504
6962 01:15:28.178278 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6963 01:15:28.182020 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6964 01:15:28.188409 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6965 01:15:28.192088 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6966 01:15:28.195484 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6967 01:15:28.198163 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6968 01:15:28.204872 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6969 01:15:28.205457 ==
6970 01:15:28.208445 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 01:15:28.211728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 01:15:28.212250 ==
6973 01:15:28.212585 DQS Delay:
6974 01:15:28.215026 DQS0 = 60, DQS1 = 68
6975 01:15:28.215444 DQM Delay:
6976 01:15:28.217751 DQM0 = 13, DQM1 = 13
6977 01:15:28.218203 DQ Delay:
6978 01:15:28.221401 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6979 01:15:28.224957 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6980 01:15:28.228338 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6981 01:15:28.231063 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6982 01:15:28.231487
6983 01:15:28.231843
6984 01:15:28.241492 [DQSOSCAuto] RK1, (LSB)MR18= 0x76a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
6985 01:15:28.242059 CH1 RK1: MR19=C0C, MR18=76A6
6986 01:15:28.248084 CH1_RK1: MR19=0xC0C, MR18=0x76A6, DQSOSC=389, MR23=63, INC=390, DEC=260
6987 01:15:28.250812 [RxdqsGatingPostProcess] freq 400
6988 01:15:28.258041 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6989 01:15:28.261390 best DQS0 dly(2T, 0.5T) = (0, 10)
6990 01:15:28.264697 best DQS1 dly(2T, 0.5T) = (0, 10)
6991 01:15:28.267898 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6992 01:15:28.271317 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6993 01:15:28.274172 best DQS0 dly(2T, 0.5T) = (0, 10)
6994 01:15:28.277255 best DQS1 dly(2T, 0.5T) = (0, 10)
6995 01:15:28.280609 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6996 01:15:28.284123 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6997 01:15:28.284651 Pre-setting of DQS Precalculation
6998 01:15:28.290703 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6999 01:15:28.297381 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7000 01:15:28.303803 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7001 01:15:28.304303
7002 01:15:28.304648
7003 01:15:28.307444 [Calibration Summary] 800 Mbps
7004 01:15:28.310833 CH 0, Rank 0
7005 01:15:28.311344 SW Impedance : PASS
7006 01:15:28.313756 DUTY Scan : NO K
7007 01:15:28.317871 ZQ Calibration : PASS
7008 01:15:28.318393 Jitter Meter : NO K
7009 01:15:28.320398 CBT Training : PASS
7010 01:15:28.320819 Write leveling : PASS
7011 01:15:28.324137 RX DQS gating : PASS
7012 01:15:28.326782 RX DQ/DQS(RDDQC) : PASS
7013 01:15:28.327200 TX DQ/DQS : PASS
7014 01:15:28.330508 RX DATLAT : PASS
7015 01:15:28.333310 RX DQ/DQS(Engine): PASS
7016 01:15:28.333783 TX OE : NO K
7017 01:15:28.336726 All Pass.
7018 01:15:28.337157
7019 01:15:28.337558 CH 0, Rank 1
7020 01:15:28.340515 SW Impedance : PASS
7021 01:15:28.341028 DUTY Scan : NO K
7022 01:15:28.343366 ZQ Calibration : PASS
7023 01:15:28.346411 Jitter Meter : NO K
7024 01:15:28.346831 CBT Training : PASS
7025 01:15:28.350125 Write leveling : NO K
7026 01:15:28.353402 RX DQS gating : PASS
7027 01:15:28.353859 RX DQ/DQS(RDDQC) : PASS
7028 01:15:28.356158 TX DQ/DQS : PASS
7029 01:15:28.360483 RX DATLAT : PASS
7030 01:15:28.360994 RX DQ/DQS(Engine): PASS
7031 01:15:28.363342 TX OE : NO K
7032 01:15:28.363855 All Pass.
7033 01:15:28.364191
7034 01:15:28.366841 CH 1, Rank 0
7035 01:15:28.367354 SW Impedance : PASS
7036 01:15:28.369540 DUTY Scan : NO K
7037 01:15:28.373264 ZQ Calibration : PASS
7038 01:15:28.373817 Jitter Meter : NO K
7039 01:15:28.376807 CBT Training : PASS
7040 01:15:28.379649 Write leveling : PASS
7041 01:15:28.380163 RX DQS gating : PASS
7042 01:15:28.382954 RX DQ/DQS(RDDQC) : PASS
7043 01:15:28.386746 TX DQ/DQS : PASS
7044 01:15:28.387260 RX DATLAT : PASS
7045 01:15:28.389827 RX DQ/DQS(Engine): PASS
7046 01:15:28.390244 TX OE : NO K
7047 01:15:28.393409 All Pass.
7048 01:15:28.393948
7049 01:15:28.394284 CH 1, Rank 1
7050 01:15:28.396200 SW Impedance : PASS
7051 01:15:28.396618 DUTY Scan : NO K
7052 01:15:28.399874 ZQ Calibration : PASS
7053 01:15:28.403038 Jitter Meter : NO K
7054 01:15:28.403461 CBT Training : PASS
7055 01:15:28.406280 Write leveling : NO K
7056 01:15:28.409498 RX DQS gating : PASS
7057 01:15:28.410174 RX DQ/DQS(RDDQC) : PASS
7058 01:15:28.412501 TX DQ/DQS : PASS
7059 01:15:28.415725 RX DATLAT : PASS
7060 01:15:28.416145 RX DQ/DQS(Engine): PASS
7061 01:15:28.419597 TX OE : NO K
7062 01:15:28.420019 All Pass.
7063 01:15:28.420350
7064 01:15:28.422806 DramC Write-DBI off
7065 01:15:28.425678 PER_BANK_REFRESH: Hybrid Mode
7066 01:15:28.426095 TX_TRACKING: ON
7067 01:15:28.436168 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7068 01:15:28.438809 [FAST_K] Save calibration result to emmc
7069 01:15:28.442275 dramc_set_vcore_voltage set vcore to 725000
7070 01:15:28.446022 Read voltage for 1600, 0
7071 01:15:28.446537 Vio18 = 0
7072 01:15:28.449017 Vcore = 725000
7073 01:15:28.449429 Vdram = 0
7074 01:15:28.449812 Vddq = 0
7075 01:15:28.450120 Vmddr = 0
7076 01:15:28.455989 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7077 01:15:28.458685 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7078 01:15:28.461892 MEM_TYPE=3, freq_sel=13
7079 01:15:28.465657 sv_algorithm_assistance_LP4_3733
7080 01:15:28.469051 ============ PULL DRAM RESETB DOWN ============
7081 01:15:28.475396 ========== PULL DRAM RESETB DOWN end =========
7082 01:15:28.478678 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7083 01:15:28.482366 ===================================
7084 01:15:28.485832 LPDDR4 DRAM CONFIGURATION
7085 01:15:28.488567 ===================================
7086 01:15:28.488985 EX_ROW_EN[0] = 0x0
7087 01:15:28.491783 EX_ROW_EN[1] = 0x0
7088 01:15:28.492194 LP4Y_EN = 0x0
7089 01:15:28.495275 WORK_FSP = 0x1
7090 01:15:28.495683 WL = 0x5
7091 01:15:28.498655 RL = 0x5
7092 01:15:28.501965 BL = 0x2
7093 01:15:28.502376 RPST = 0x0
7094 01:15:28.505673 RD_PRE = 0x0
7095 01:15:28.506188 WR_PRE = 0x1
7096 01:15:28.508459 WR_PST = 0x1
7097 01:15:28.508867 DBI_WR = 0x0
7098 01:15:28.512007 DBI_RD = 0x0
7099 01:15:28.512517 OTF = 0x1
7100 01:15:28.514905 ===================================
7101 01:15:28.518332 ===================================
7102 01:15:28.521552 ANA top config
7103 01:15:28.525155 ===================================
7104 01:15:28.525809 DLL_ASYNC_EN = 0
7105 01:15:28.528666 ALL_SLAVE_EN = 0
7106 01:15:28.532133 NEW_RANK_MODE = 1
7107 01:15:28.535004 DLL_IDLE_MODE = 1
7108 01:15:28.535513 LP45_APHY_COMB_EN = 1
7109 01:15:28.538059 TX_ODT_DIS = 0
7110 01:15:28.542027 NEW_8X_MODE = 1
7111 01:15:28.545215 ===================================
7112 01:15:28.549151 ===================================
7113 01:15:28.551159 data_rate = 3200
7114 01:15:28.554741 CKR = 1
7115 01:15:28.557883 DQ_P2S_RATIO = 8
7116 01:15:28.561206 ===================================
7117 01:15:28.561654 CA_P2S_RATIO = 8
7118 01:15:28.564638 DQ_CA_OPEN = 0
7119 01:15:28.568075 DQ_SEMI_OPEN = 0
7120 01:15:28.571734 CA_SEMI_OPEN = 0
7121 01:15:28.574106 CA_FULL_RATE = 0
7122 01:15:28.577558 DQ_CKDIV4_EN = 0
7123 01:15:28.578007 CA_CKDIV4_EN = 0
7124 01:15:28.580746 CA_PREDIV_EN = 0
7125 01:15:28.584488 PH8_DLY = 12
7126 01:15:28.587660 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7127 01:15:28.590532 DQ_AAMCK_DIV = 4
7128 01:15:28.594173 CA_AAMCK_DIV = 4
7129 01:15:28.597717 CA_ADMCK_DIV = 4
7130 01:15:28.598237 DQ_TRACK_CA_EN = 0
7131 01:15:28.600582 CA_PICK = 1600
7132 01:15:28.604144 CA_MCKIO = 1600
7133 01:15:28.607272 MCKIO_SEMI = 0
7134 01:15:28.610855 PLL_FREQ = 3068
7135 01:15:28.614034 DQ_UI_PI_RATIO = 32
7136 01:15:28.617728 CA_UI_PI_RATIO = 0
7137 01:15:28.620829 ===================================
7138 01:15:28.624301 ===================================
7139 01:15:28.624854 memory_type:LPDDR4
7140 01:15:28.627503 GP_NUM : 10
7141 01:15:28.631071 SRAM_EN : 1
7142 01:15:28.631635 MD32_EN : 0
7143 01:15:28.633678 ===================================
7144 01:15:28.637367 [ANA_INIT] >>>>>>>>>>>>>>
7145 01:15:28.640729 <<<<<< [CONFIGURE PHASE]: ANA_TX
7146 01:15:28.644368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7147 01:15:28.647690 ===================================
7148 01:15:28.650755 data_rate = 3200,PCW = 0X7600
7149 01:15:28.653893 ===================================
7150 01:15:28.657157 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7151 01:15:28.660698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7152 01:15:28.666773 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7153 01:15:28.670189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7154 01:15:28.673787 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7155 01:15:28.676855 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7156 01:15:28.680188 [ANA_INIT] flow start
7157 01:15:28.683591 [ANA_INIT] PLL >>>>>>>>
7158 01:15:28.684140 [ANA_INIT] PLL <<<<<<<<
7159 01:15:28.686687 [ANA_INIT] MIDPI >>>>>>>>
7160 01:15:28.689723 [ANA_INIT] MIDPI <<<<<<<<
7161 01:15:28.693885 [ANA_INIT] DLL >>>>>>>>
7162 01:15:28.694434 [ANA_INIT] DLL <<<<<<<<
7163 01:15:28.696753 [ANA_INIT] flow end
7164 01:15:28.700109 ============ LP4 DIFF to SE enter ============
7165 01:15:28.703005 ============ LP4 DIFF to SE exit ============
7166 01:15:28.706281 [ANA_INIT] <<<<<<<<<<<<<
7167 01:15:28.710016 [Flow] Enable top DCM control >>>>>
7168 01:15:28.713103 [Flow] Enable top DCM control <<<<<
7169 01:15:28.716432 Enable DLL master slave shuffle
7170 01:15:28.723148 ==============================================================
7171 01:15:28.723664 Gating Mode config
7172 01:15:28.729887 ==============================================================
7173 01:15:28.730409 Config description:
7174 01:15:28.739290 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7175 01:15:28.746510 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7176 01:15:28.752308 SELPH_MODE 0: By rank 1: By Phase
7177 01:15:28.756151 ==============================================================
7178 01:15:28.759719 GAT_TRACK_EN = 1
7179 01:15:28.762197 RX_GATING_MODE = 2
7180 01:15:28.765756 RX_GATING_TRACK_MODE = 2
7181 01:15:28.769088 SELPH_MODE = 1
7182 01:15:28.772560 PICG_EARLY_EN = 1
7183 01:15:28.776128 VALID_LAT_VALUE = 1
7184 01:15:28.782494 ==============================================================
7185 01:15:28.785711 Enter into Gating configuration >>>>
7186 01:15:28.789138 Exit from Gating configuration <<<<
7187 01:15:28.792432 Enter into DVFS_PRE_config >>>>>
7188 01:15:28.801976 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7189 01:15:28.805172 Exit from DVFS_PRE_config <<<<<
7190 01:15:28.808801 Enter into PICG configuration >>>>
7191 01:15:28.812065 Exit from PICG configuration <<<<
7192 01:15:28.815295 [RX_INPUT] configuration >>>>>
7193 01:15:28.818637 [RX_INPUT] configuration <<<<<
7194 01:15:28.821991 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7195 01:15:28.828666 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7196 01:15:28.835099 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7197 01:15:28.838141 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7198 01:15:28.845115 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7199 01:15:28.851366 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7200 01:15:28.855102 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7201 01:15:28.861651 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7202 01:15:28.865037 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7203 01:15:28.868458 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7204 01:15:28.871948 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7205 01:15:28.878104 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7206 01:15:28.881440 ===================================
7207 01:15:28.882047 LPDDR4 DRAM CONFIGURATION
7208 01:15:28.884665 ===================================
7209 01:15:28.888394 EX_ROW_EN[0] = 0x0
7210 01:15:28.891331 EX_ROW_EN[1] = 0x0
7211 01:15:28.891894 LP4Y_EN = 0x0
7212 01:15:28.895182 WORK_FSP = 0x1
7213 01:15:28.895794 WL = 0x5
7214 01:15:28.898060 RL = 0x5
7215 01:15:28.898705 BL = 0x2
7216 01:15:28.901322 RPST = 0x0
7217 01:15:28.901932 RD_PRE = 0x0
7218 01:15:28.904704 WR_PRE = 0x1
7219 01:15:28.905268 WR_PST = 0x1
7220 01:15:28.907831 DBI_WR = 0x0
7221 01:15:28.908316 DBI_RD = 0x0
7222 01:15:28.911622 OTF = 0x1
7223 01:15:28.914435 ===================================
7224 01:15:28.917956 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7225 01:15:28.920894 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7226 01:15:28.927804 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7227 01:15:28.931343 ===================================
7228 01:15:28.931930 LPDDR4 DRAM CONFIGURATION
7229 01:15:28.934507 ===================================
7230 01:15:28.937908 EX_ROW_EN[0] = 0x10
7231 01:15:28.940948 EX_ROW_EN[1] = 0x0
7232 01:15:28.941615 LP4Y_EN = 0x0
7233 01:15:28.944843 WORK_FSP = 0x1
7234 01:15:28.945609 WL = 0x5
7235 01:15:28.947430 RL = 0x5
7236 01:15:28.947888 BL = 0x2
7237 01:15:28.951366 RPST = 0x0
7238 01:15:28.951833 RD_PRE = 0x0
7239 01:15:28.954002 WR_PRE = 0x1
7240 01:15:28.954422 WR_PST = 0x1
7241 01:15:28.957318 DBI_WR = 0x0
7242 01:15:28.957814 DBI_RD = 0x0
7243 01:15:28.960697 OTF = 0x1
7244 01:15:28.964280 ===================================
7245 01:15:28.970229 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7246 01:15:28.970740 ==
7247 01:15:28.973563 Dram Type= 6, Freq= 0, CH_0, rank 0
7248 01:15:28.977031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7249 01:15:28.977453 ==
7250 01:15:28.980427 [Duty_Offset_Calibration]
7251 01:15:28.980846 B0:2 B1:0 CA:3
7252 01:15:28.981175
7253 01:15:28.984342 [DutyScan_Calibration_Flow] k_type=0
7254 01:15:28.994412
7255 01:15:28.994934 ==CLK 0==
7256 01:15:28.997763 Final CLK duty delay cell = 0
7257 01:15:29.000998 [0] MAX Duty = 5031%(X100), DQS PI = 12
7258 01:15:29.004282 [0] MIN Duty = 4907%(X100), DQS PI = 6
7259 01:15:29.007934 [0] AVG Duty = 4969%(X100)
7260 01:15:29.008496
7261 01:15:29.011518 CH0 CLK Duty spec in!! Max-Min= 124%
7262 01:15:29.014452 [DutyScan_Calibration_Flow] ====Done====
7263 01:15:29.014989
7264 01:15:29.017659 [DutyScan_Calibration_Flow] k_type=1
7265 01:15:29.034703
7266 01:15:29.035278 ==DQS 0 ==
7267 01:15:29.037262 Final DQS duty delay cell = 0
7268 01:15:29.041130 [0] MAX Duty = 5125%(X100), DQS PI = 32
7269 01:15:29.044597 [0] MIN Duty = 4875%(X100), DQS PI = 48
7270 01:15:29.047433 [0] AVG Duty = 5000%(X100)
7271 01:15:29.047900
7272 01:15:29.048266 ==DQS 1 ==
7273 01:15:29.051009 Final DQS duty delay cell = 0
7274 01:15:29.053780 [0] MAX Duty = 5156%(X100), DQS PI = 32
7275 01:15:29.057263 [0] MIN Duty = 5031%(X100), DQS PI = 14
7276 01:15:29.060796 [0] AVG Duty = 5093%(X100)
7277 01:15:29.061215
7278 01:15:29.064234 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7279 01:15:29.064809
7280 01:15:29.067616 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7281 01:15:29.070858 [DutyScan_Calibration_Flow] ====Done====
7282 01:15:29.071377
7283 01:15:29.074150 [DutyScan_Calibration_Flow] k_type=3
7284 01:15:29.092221
7285 01:15:29.092786 ==DQM 0 ==
7286 01:15:29.095602 Final DQM duty delay cell = 0
7287 01:15:29.098697 [0] MAX Duty = 5125%(X100), DQS PI = 14
7288 01:15:29.101867 [0] MIN Duty = 4844%(X100), DQS PI = 52
7289 01:15:29.105609 [0] AVG Duty = 4984%(X100)
7290 01:15:29.106180
7291 01:15:29.106551 ==DQM 1 ==
7292 01:15:29.108914 Final DQM duty delay cell = 4
7293 01:15:29.112275 [4] MAX Duty = 5156%(X100), DQS PI = 52
7294 01:15:29.114978 [4] MIN Duty = 5031%(X100), DQS PI = 12
7295 01:15:29.118362 [4] AVG Duty = 5093%(X100)
7296 01:15:29.118777
7297 01:15:29.122125 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7298 01:15:29.122542
7299 01:15:29.125477 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7300 01:15:29.128320 [DutyScan_Calibration_Flow] ====Done====
7301 01:15:29.128736
7302 01:15:29.131868 [DutyScan_Calibration_Flow] k_type=2
7303 01:15:29.148342
7304 01:15:29.148881 ==DQ 0 ==
7305 01:15:29.151478 Final DQ duty delay cell = -4
7306 01:15:29.155284 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7307 01:15:29.158432 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7308 01:15:29.161541 [-4] AVG Duty = 4938%(X100)
7309 01:15:29.161957
7310 01:15:29.162288 ==DQ 1 ==
7311 01:15:29.165187 Final DQ duty delay cell = 0
7312 01:15:29.168355 [0] MAX Duty = 5156%(X100), DQS PI = 58
7313 01:15:29.171834 [0] MIN Duty = 5000%(X100), DQS PI = 16
7314 01:15:29.175072 [0] AVG Duty = 5078%(X100)
7315 01:15:29.175596
7316 01:15:29.178194 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7317 01:15:29.178716
7318 01:15:29.181639 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7319 01:15:29.184631 [DutyScan_Calibration_Flow] ====Done====
7320 01:15:29.185045 ==
7321 01:15:29.187962 Dram Type= 6, Freq= 0, CH_1, rank 0
7322 01:15:29.190875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7323 01:15:29.191338 ==
7324 01:15:29.194263 [Duty_Offset_Calibration]
7325 01:15:29.194694 B0:1 B1:-2 CA:1
7326 01:15:29.195026
7327 01:15:29.197728 [DutyScan_Calibration_Flow] k_type=0
7328 01:15:29.208873
7329 01:15:29.209303 ==CLK 0==
7330 01:15:29.211749 Final CLK duty delay cell = 0
7331 01:15:29.215117 [0] MAX Duty = 5062%(X100), DQS PI = 22
7332 01:15:29.218983 [0] MIN Duty = 4844%(X100), DQS PI = 0
7333 01:15:29.219405 [0] AVG Duty = 4953%(X100)
7334 01:15:29.222599
7335 01:15:29.225227 CH1 CLK Duty spec in!! Max-Min= 218%
7336 01:15:29.228967 [DutyScan_Calibration_Flow] ====Done====
7337 01:15:29.229379
7338 01:15:29.231609 [DutyScan_Calibration_Flow] k_type=1
7339 01:15:29.248205
7340 01:15:29.248713 ==DQS 0 ==
7341 01:15:29.251468 Final DQS duty delay cell = 0
7342 01:15:29.255199 [0] MAX Duty = 5187%(X100), DQS PI = 22
7343 01:15:29.258255 [0] MIN Duty = 5031%(X100), DQS PI = 54
7344 01:15:29.262169 [0] AVG Duty = 5109%(X100)
7345 01:15:29.262688
7346 01:15:29.263024 ==DQS 1 ==
7347 01:15:29.264792 Final DQS duty delay cell = 0
7348 01:15:29.268294 [0] MAX Duty = 5093%(X100), DQS PI = 60
7349 01:15:29.271660 [0] MIN Duty = 4844%(X100), DQS PI = 24
7350 01:15:29.274530 [0] AVG Duty = 4968%(X100)
7351 01:15:29.274993
7352 01:15:29.278069 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7353 01:15:29.278484
7354 01:15:29.281572 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7355 01:15:29.284547 [DutyScan_Calibration_Flow] ====Done====
7356 01:15:29.284972
7357 01:15:29.288252 [DutyScan_Calibration_Flow] k_type=3
7358 01:15:29.305219
7359 01:15:29.305667 ==DQM 0 ==
7360 01:15:29.308556 Final DQM duty delay cell = 0
7361 01:15:29.312160 [0] MAX Duty = 5031%(X100), DQS PI = 24
7362 01:15:29.315514 [0] MIN Duty = 4813%(X100), DQS PI = 56
7363 01:15:29.318963 [0] AVG Duty = 4922%(X100)
7364 01:15:29.319490
7365 01:15:29.319822 ==DQM 1 ==
7366 01:15:29.321616 Final DQM duty delay cell = 0
7367 01:15:29.325235 [0] MAX Duty = 5062%(X100), DQS PI = 34
7368 01:15:29.328544 [0] MIN Duty = 4875%(X100), DQS PI = 24
7369 01:15:29.331549 [0] AVG Duty = 4968%(X100)
7370 01:15:29.331968
7371 01:15:29.334737 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7372 01:15:29.335158
7373 01:15:29.338115 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7374 01:15:29.341488 [DutyScan_Calibration_Flow] ====Done====
7375 01:15:29.341945
7376 01:15:29.344740 [DutyScan_Calibration_Flow] k_type=2
7377 01:15:29.362683
7378 01:15:29.363197 ==DQ 0 ==
7379 01:15:29.365315 Final DQ duty delay cell = 0
7380 01:15:29.368539 [0] MAX Duty = 5093%(X100), DQS PI = 20
7381 01:15:29.372299 [0] MIN Duty = 4907%(X100), DQS PI = 46
7382 01:15:29.372866 [0] AVG Duty = 5000%(X100)
7383 01:15:29.375696
7384 01:15:29.376156 ==DQ 1 ==
7385 01:15:29.378595 Final DQ duty delay cell = 0
7386 01:15:29.382101 [0] MAX Duty = 5125%(X100), DQS PI = 34
7387 01:15:29.385606 [0] MIN Duty = 4938%(X100), DQS PI = 24
7388 01:15:29.386166 [0] AVG Duty = 5031%(X100)
7389 01:15:29.386534
7390 01:15:29.392055 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7391 01:15:29.392585
7392 01:15:29.395087 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7393 01:15:29.398238 [DutyScan_Calibration_Flow] ====Done====
7394 01:15:29.401623 nWR fixed to 30
7395 01:15:29.402046 [ModeRegInit_LP4] CH0 RK0
7396 01:15:29.404890 [ModeRegInit_LP4] CH0 RK1
7397 01:15:29.409019 [ModeRegInit_LP4] CH1 RK0
7398 01:15:29.411643 [ModeRegInit_LP4] CH1 RK1
7399 01:15:29.412061 match AC timing 5
7400 01:15:29.418480 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7401 01:15:29.422028 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7402 01:15:29.425082 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7403 01:15:29.431394 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7404 01:15:29.435204 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7405 01:15:29.435727 [MiockJmeterHQA]
7406 01:15:29.436059
7407 01:15:29.438081 [DramcMiockJmeter] u1RxGatingPI = 0
7408 01:15:29.441433 0 : 4253, 4027
7409 01:15:29.441899 4 : 4368, 4142
7410 01:15:29.445377 8 : 4257, 4029
7411 01:15:29.445959 12 : 4255, 4029
7412 01:15:29.446306 16 : 4257, 4032
7413 01:15:29.447718 20 : 4365, 4140
7414 01:15:29.448143 24 : 4258, 4029
7415 01:15:29.451151 28 : 4366, 4139
7416 01:15:29.451575 32 : 4252, 4026
7417 01:15:29.454589 36 : 4257, 4030
7418 01:15:29.455015 40 : 4255, 4029
7419 01:15:29.458392 44 : 4366, 4139
7420 01:15:29.458922 48 : 4366, 4140
7421 01:15:29.459265 52 : 4255, 4029
7422 01:15:29.461170 56 : 4253, 4029
7423 01:15:29.461742 60 : 4366, 4142
7424 01:15:29.464779 64 : 4253, 4029
7425 01:15:29.465307 68 : 4368, 4142
7426 01:15:29.467607 72 : 4366, 4140
7427 01:15:29.468030 76 : 4252, 4029
7428 01:15:29.471171 80 : 4363, 4139
7429 01:15:29.471597 84 : 4252, 4029
7430 01:15:29.471937 88 : 4254, 4030
7431 01:15:29.474588 92 : 4255, 4029
7432 01:15:29.475118 96 : 4253, 4029
7433 01:15:29.477772 100 : 4367, 4143
7434 01:15:29.478325 104 : 4255, 3247
7435 01:15:29.481268 108 : 4360, 0
7436 01:15:29.481846 112 : 4254, 0
7437 01:15:29.484987 116 : 4253, 0
7438 01:15:29.485562 120 : 4253, 0
7439 01:15:29.485921 124 : 4255, 0
7440 01:15:29.487663 128 : 4365, 0
7441 01:15:29.488237 132 : 4366, 0
7442 01:15:29.488592 136 : 4366, 0
7443 01:15:29.490668 140 : 4250, 0
7444 01:15:29.491158 144 : 4366, 0
7445 01:15:29.494428 148 : 4255, 0
7446 01:15:29.494958 152 : 4252, 0
7447 01:15:29.495300 156 : 4254, 0
7448 01:15:29.496972 160 : 4255, 0
7449 01:15:29.497396 164 : 4255, 0
7450 01:15:29.500479 168 : 4250, 0
7451 01:15:29.500904 172 : 4253, 0
7452 01:15:29.501243 176 : 4255, 0
7453 01:15:29.504054 180 : 4363, 0
7454 01:15:29.504470 184 : 4252, 0
7455 01:15:29.507490 188 : 4253, 0
7456 01:15:29.507907 192 : 4253, 0
7457 01:15:29.508239 196 : 4252, 0
7458 01:15:29.511042 200 : 4255, 0
7459 01:15:29.511560 204 : 4255, 0
7460 01:15:29.514102 208 : 4254, 0
7461 01:15:29.514625 212 : 4253, 0
7462 01:15:29.514961 216 : 4255, 0
7463 01:15:29.517409 220 : 4253, 0
7464 01:15:29.517871 224 : 4363, 0
7465 01:15:29.518203 228 : 4253, 0
7466 01:15:29.520289 232 : 4252, 0
7467 01:15:29.520704 236 : 4252, 1347
7468 01:15:29.523957 240 : 4253, 4029
7469 01:15:29.524340 244 : 4363, 4140
7470 01:15:29.527067 248 : 4363, 4140
7471 01:15:29.527484 252 : 4253, 4029
7472 01:15:29.530558 256 : 4255, 4029
7473 01:15:29.531079 260 : 4255, 4030
7474 01:15:29.533726 264 : 4365, 4140
7475 01:15:29.534242 268 : 4366, 4140
7476 01:15:29.536993 272 : 4363, 4140
7477 01:15:29.537411 276 : 4252, 4026
7478 01:15:29.540521 280 : 4254, 4029
7479 01:15:29.540935 284 : 4363, 4140
7480 01:15:29.541269 288 : 4250, 4027
7481 01:15:29.543563 292 : 4252, 4027
7482 01:15:29.544083 296 : 4252, 4026
7483 01:15:29.546914 300 : 4363, 4140
7484 01:15:29.547431 304 : 4255, 4029
7485 01:15:29.550234 308 : 4255, 4030
7486 01:15:29.550649 312 : 4257, 4031
7487 01:15:29.553636 316 : 4365, 4140
7488 01:15:29.554057 320 : 4252, 4029
7489 01:15:29.556491 324 : 4253, 4029
7490 01:15:29.556907 328 : 4257, 4031
7491 01:15:29.560247 332 : 4365, 4139
7492 01:15:29.560763 336 : 4255, 4029
7493 01:15:29.563821 340 : 4364, 4140
7494 01:15:29.564340 344 : 4252, 4029
7495 01:15:29.566687 348 : 4255, 4029
7496 01:15:29.567204 352 : 4363, 4098
7497 01:15:29.567535 356 : 4253, 2383
7498 01:15:29.569873 360 : 4254, 0
7499 01:15:29.570290
7500 01:15:29.573195 MIOCK jitter meter ch=0
7501 01:15:29.573648
7502 01:15:29.573984 1T = (360-108) = 252 dly cells
7503 01:15:29.579827 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7504 01:15:29.580337 ==
7505 01:15:29.583080 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 01:15:29.590086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 01:15:29.590603 ==
7508 01:15:29.593062 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 01:15:29.596610 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 01:15:29.603017 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 01:15:29.609860 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 01:15:29.617172 [CA 0] Center 44 (14~75) winsize 62
7513 01:15:29.620317 [CA 1] Center 43 (13~74) winsize 62
7514 01:15:29.623664 [CA 2] Center 40 (11~69) winsize 59
7515 01:15:29.627442 [CA 3] Center 39 (10~68) winsize 59
7516 01:15:29.630213 [CA 4] Center 37 (8~67) winsize 60
7517 01:15:29.633489 [CA 5] Center 37 (7~67) winsize 61
7518 01:15:29.634039
7519 01:15:29.637160 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 01:15:29.637739
7521 01:15:29.643445 [CATrainingPosCal] consider 1 rank data
7522 01:15:29.644009 u2DelayCellTimex100 = 258/100 ps
7523 01:15:29.651033 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7524 01:15:29.653399 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7525 01:15:29.656804 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7526 01:15:29.660613 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7527 01:15:29.663508 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7528 01:15:29.667154 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7529 01:15:29.667677
7530 01:15:29.669857 CA PerBit enable=1, Macro0, CA PI delay=37
7531 01:15:29.670277
7532 01:15:29.673183 [CBTSetCACLKResult] CA Dly = 37
7533 01:15:29.676717 CS Dly: 11 (0~42)
7534 01:15:29.680481 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 01:15:29.682967 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 01:15:29.683390 ==
7537 01:15:29.686521 Dram Type= 6, Freq= 0, CH_0, rank 1
7538 01:15:29.693439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 01:15:29.694010 ==
7540 01:15:29.696458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7541 01:15:29.702874 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7542 01:15:29.706278 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7543 01:15:29.713214 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7544 01:15:29.720808 [CA 0] Center 44 (14~75) winsize 62
7545 01:15:29.724067 [CA 1] Center 44 (13~75) winsize 63
7546 01:15:29.727550 [CA 2] Center 39 (10~69) winsize 60
7547 01:15:29.730389 [CA 3] Center 39 (10~69) winsize 60
7548 01:15:29.733850 [CA 4] Center 37 (8~67) winsize 60
7549 01:15:29.737354 [CA 5] Center 37 (7~67) winsize 61
7550 01:15:29.737822
7551 01:15:29.740329 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7552 01:15:29.740935
7553 01:15:29.747251 [CATrainingPosCal] consider 2 rank data
7554 01:15:29.747708 u2DelayCellTimex100 = 258/100 ps
7555 01:15:29.753644 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7556 01:15:29.757205 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7557 01:15:29.760342 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7558 01:15:29.764252 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7559 01:15:29.767364 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7560 01:15:29.770452 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7561 01:15:29.770931
7562 01:15:29.773335 CA PerBit enable=1, Macro0, CA PI delay=37
7563 01:15:29.773802
7564 01:15:29.776881 [CBTSetCACLKResult] CA Dly = 37
7565 01:15:29.780510 CS Dly: 11 (0~43)
7566 01:15:29.783534 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7567 01:15:29.787048 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7568 01:15:29.787529
7569 01:15:29.790128 ----->DramcWriteLeveling(PI) begin...
7570 01:15:29.790553 ==
7571 01:15:29.793498 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 01:15:29.799823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 01:15:29.800434 ==
7574 01:15:29.803429 Write leveling (Byte 0): 36 => 36
7575 01:15:29.806870 Write leveling (Byte 1): 28 => 28
7576 01:15:29.807290 DramcWriteLeveling(PI) end<-----
7577 01:15:29.810160
7578 01:15:29.810579 ==
7579 01:15:29.813389 Dram Type= 6, Freq= 0, CH_0, rank 0
7580 01:15:29.816981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 01:15:29.817400 ==
7582 01:15:29.820435 [Gating] SW mode calibration
7583 01:15:29.827208 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7584 01:15:29.830251 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7585 01:15:29.837012 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 01:15:29.840114 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 01:15:29.843512 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 01:15:29.849793 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 01:15:29.853334 1 4 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7590 01:15:29.856339 1 4 20 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
7591 01:15:29.863168 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7592 01:15:29.867074 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 01:15:29.869544 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 01:15:29.876775 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 01:15:29.879726 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 01:15:29.882635 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7597 01:15:29.889771 1 5 16 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7598 01:15:29.893109 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
7599 01:15:29.896628 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7600 01:15:29.902600 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 01:15:29.906836 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 01:15:29.909373 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 01:15:29.916185 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 01:15:29.919281 1 6 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7605 01:15:29.922552 1 6 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7606 01:15:29.929234 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7607 01:15:29.932609 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7608 01:15:29.936218 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 01:15:29.942186 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 01:15:29.945968 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 01:15:29.949211 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 01:15:29.955883 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 01:15:29.959108 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7614 01:15:29.962177 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7615 01:15:29.969008 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7616 01:15:29.972270 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 01:15:29.975348 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 01:15:29.982236 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 01:15:29.985102 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 01:15:29.988787 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 01:15:29.995438 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 01:15:29.998168 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 01:15:30.001543 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 01:15:30.007902 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 01:15:30.011465 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 01:15:30.015042 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 01:15:30.021213 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 01:15:30.025105 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 01:15:30.028567 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7630 01:15:30.034706 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7631 01:15:30.037704 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7632 01:15:30.041375 Total UI for P1: 0, mck2ui 16
7633 01:15:30.045002 best dqsien dly found for B0: ( 1, 9, 18)
7634 01:15:30.047929 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 01:15:30.051136 Total UI for P1: 0, mck2ui 16
7636 01:15:30.054480 best dqsien dly found for B1: ( 1, 9, 24)
7637 01:15:30.057665 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7638 01:15:30.061415 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7639 01:15:30.061965
7640 01:15:30.067829 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7641 01:15:30.070752 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7642 01:15:30.074316 [Gating] SW calibration Done
7643 01:15:30.074829 ==
7644 01:15:30.077331 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 01:15:30.081187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 01:15:30.081749 ==
7647 01:15:30.082091 RX Vref Scan: 0
7648 01:15:30.084784
7649 01:15:30.085289 RX Vref 0 -> 0, step: 1
7650 01:15:30.085667
7651 01:15:30.087777 RX Delay 0 -> 252, step: 8
7652 01:15:30.091124 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7653 01:15:30.094117 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7654 01:15:30.101361 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7655 01:15:30.104112 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7656 01:15:30.107029 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7657 01:15:30.110308 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7658 01:15:30.114021 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7659 01:15:30.120618 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7660 01:15:30.124055 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7661 01:15:30.127000 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7662 01:15:30.130403 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7663 01:15:30.134101 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7664 01:15:30.140090 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7665 01:15:30.143637 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7666 01:15:30.147467 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7667 01:15:30.150219 iDelay=200, Bit 15, Center 127 (72 ~ 183) 112
7668 01:15:30.150685 ==
7669 01:15:30.153288 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 01:15:30.160502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 01:15:30.161026 ==
7672 01:15:30.161361 DQS Delay:
7673 01:15:30.163837 DQS0 = 0, DQS1 = 0
7674 01:15:30.164387 DQM Delay:
7675 01:15:30.167424 DQM0 = 128, DQM1 = 123
7676 01:15:30.167932 DQ Delay:
7677 01:15:30.170005 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7678 01:15:30.173563 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7679 01:15:30.177048 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7680 01:15:30.180247 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7681 01:15:30.180660
7682 01:15:30.180984
7683 01:15:30.181289 ==
7684 01:15:30.182995 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 01:15:30.189750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 01:15:30.190266 ==
7687 01:15:30.190602
7688 01:15:30.190910
7689 01:15:30.191201 TX Vref Scan disable
7690 01:15:30.193892 == TX Byte 0 ==
7691 01:15:30.197178 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7692 01:15:30.203302 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7693 01:15:30.203815 == TX Byte 1 ==
7694 01:15:30.206849 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7695 01:15:30.213960 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7696 01:15:30.214474 ==
7697 01:15:30.216728 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 01:15:30.220226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 01:15:30.220755 ==
7700 01:15:30.233065
7701 01:15:30.236598 TX Vref early break, caculate TX vref
7702 01:15:30.239889 TX Vref=16, minBit 8, minWin=21, winSum=363
7703 01:15:30.243085 TX Vref=18, minBit 8, minWin=21, winSum=370
7704 01:15:30.246500 TX Vref=20, minBit 9, minWin=22, winSum=380
7705 01:15:30.249818 TX Vref=22, minBit 8, minWin=23, winSum=391
7706 01:15:30.253136 TX Vref=24, minBit 4, minWin=23, winSum=402
7707 01:15:30.260143 TX Vref=26, minBit 9, minWin=24, winSum=407
7708 01:15:30.263293 TX Vref=28, minBit 8, minWin=24, winSum=411
7709 01:15:30.266679 TX Vref=30, minBit 8, minWin=24, winSum=405
7710 01:15:30.269563 TX Vref=32, minBit 8, minWin=23, winSum=394
7711 01:15:30.273135 TX Vref=34, minBit 8, minWin=21, winSum=387
7712 01:15:30.279626 [TxChooseVref] Worse bit 8, Min win 24, Win sum 411, Final Vref 28
7713 01:15:30.280140
7714 01:15:30.283110 Final TX Range 0 Vref 28
7715 01:15:30.283623
7716 01:15:30.283956 ==
7717 01:15:30.286168 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 01:15:30.289494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 01:15:30.290071 ==
7720 01:15:30.290403
7721 01:15:30.290707
7722 01:15:30.292969 TX Vref Scan disable
7723 01:15:30.299853 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7724 01:15:30.300369 == TX Byte 0 ==
7725 01:15:30.303214 u2DelayCellOfst[0]=15 cells (4 PI)
7726 01:15:30.306268 u2DelayCellOfst[1]=18 cells (5 PI)
7727 01:15:30.309601 u2DelayCellOfst[2]=15 cells (4 PI)
7728 01:15:30.312789 u2DelayCellOfst[3]=11 cells (3 PI)
7729 01:15:30.315960 u2DelayCellOfst[4]=11 cells (3 PI)
7730 01:15:30.319311 u2DelayCellOfst[5]=0 cells (0 PI)
7731 01:15:30.322616 u2DelayCellOfst[6]=22 cells (6 PI)
7732 01:15:30.325594 u2DelayCellOfst[7]=18 cells (5 PI)
7733 01:15:30.328938 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7734 01:15:30.332336 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7735 01:15:30.335583 == TX Byte 1 ==
7736 01:15:30.339273 u2DelayCellOfst[8]=0 cells (0 PI)
7737 01:15:30.342677 u2DelayCellOfst[9]=3 cells (1 PI)
7738 01:15:30.343388 u2DelayCellOfst[10]=11 cells (3 PI)
7739 01:15:30.345507 u2DelayCellOfst[11]=7 cells (2 PI)
7740 01:15:30.349295 u2DelayCellOfst[12]=15 cells (4 PI)
7741 01:15:30.352452 u2DelayCellOfst[13]=11 cells (3 PI)
7742 01:15:30.355713 u2DelayCellOfst[14]=15 cells (4 PI)
7743 01:15:30.359009 u2DelayCellOfst[15]=11 cells (3 PI)
7744 01:15:30.365382 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7745 01:15:30.369162 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7746 01:15:30.370028 DramC Write-DBI on
7747 01:15:30.370454 ==
7748 01:15:30.372261 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 01:15:30.378714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 01:15:30.379231 ==
7751 01:15:30.379568
7752 01:15:30.379875
7753 01:15:30.380171 TX Vref Scan disable
7754 01:15:30.382996 == TX Byte 0 ==
7755 01:15:30.386210 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7756 01:15:30.389588 == TX Byte 1 ==
7757 01:15:30.392580 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7758 01:15:30.396134 DramC Write-DBI off
7759 01:15:30.396546
7760 01:15:30.396872 [DATLAT]
7761 01:15:30.397178 Freq=1600, CH0 RK0
7762 01:15:30.397479
7763 01:15:30.399169 DATLAT Default: 0xf
7764 01:15:30.402670 0, 0xFFFF, sum = 0
7765 01:15:30.403280 1, 0xFFFF, sum = 0
7766 01:15:30.406045 2, 0xFFFF, sum = 0
7767 01:15:30.406465 3, 0xFFFF, sum = 0
7768 01:15:30.409308 4, 0xFFFF, sum = 0
7769 01:15:30.409921 5, 0xFFFF, sum = 0
7770 01:15:30.413164 6, 0xFFFF, sum = 0
7771 01:15:30.413974 7, 0xFFFF, sum = 0
7772 01:15:30.415928 8, 0xFFFF, sum = 0
7773 01:15:30.416348 9, 0xFFFF, sum = 0
7774 01:15:30.419206 10, 0xFFFF, sum = 0
7775 01:15:30.419627 11, 0xFFFF, sum = 0
7776 01:15:30.423022 12, 0xFFFF, sum = 0
7777 01:15:30.423533 13, 0xEFFF, sum = 0
7778 01:15:30.426031 14, 0x0, sum = 1
7779 01:15:30.426451 15, 0x0, sum = 2
7780 01:15:30.429576 16, 0x0, sum = 3
7781 01:15:30.430084 17, 0x0, sum = 4
7782 01:15:30.432481 best_step = 15
7783 01:15:30.433061
7784 01:15:30.433401 ==
7785 01:15:30.435858 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 01:15:30.439131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 01:15:30.439759 ==
7788 01:15:30.442409 RX Vref Scan: 1
7789 01:15:30.442830
7790 01:15:30.443482 Set Vref Range= 24 -> 127
7791 01:15:30.443960
7792 01:15:30.445745 RX Vref 24 -> 127, step: 1
7793 01:15:30.446162
7794 01:15:30.448826 RX Delay 11 -> 252, step: 4
7795 01:15:30.449240
7796 01:15:30.452465 Set Vref, RX VrefLevel [Byte0]: 24
7797 01:15:30.455256 [Byte1]: 24
7798 01:15:30.455848
7799 01:15:30.458705 Set Vref, RX VrefLevel [Byte0]: 25
7800 01:15:30.462193 [Byte1]: 25
7801 01:15:30.465696
7802 01:15:30.466108 Set Vref, RX VrefLevel [Byte0]: 26
7803 01:15:30.469257 [Byte1]: 26
7804 01:15:30.473372
7805 01:15:30.473853 Set Vref, RX VrefLevel [Byte0]: 27
7806 01:15:30.476817 [Byte1]: 27
7807 01:15:30.481080
7808 01:15:30.481620 Set Vref, RX VrefLevel [Byte0]: 28
7809 01:15:30.484525 [Byte1]: 28
7810 01:15:30.488803
7811 01:15:30.489304 Set Vref, RX VrefLevel [Byte0]: 29
7812 01:15:30.492658 [Byte1]: 29
7813 01:15:30.496389
7814 01:15:30.496915 Set Vref, RX VrefLevel [Byte0]: 30
7815 01:15:30.499896 [Byte1]: 30
7816 01:15:30.504392
7817 01:15:30.504908 Set Vref, RX VrefLevel [Byte0]: 31
7818 01:15:30.507058 [Byte1]: 31
7819 01:15:30.511857
7820 01:15:30.512369 Set Vref, RX VrefLevel [Byte0]: 32
7821 01:15:30.515052 [Byte1]: 32
7822 01:15:30.519322
7823 01:15:30.519823 Set Vref, RX VrefLevel [Byte0]: 33
7824 01:15:30.522415 [Byte1]: 33
7825 01:15:30.527081
7826 01:15:30.527582 Set Vref, RX VrefLevel [Byte0]: 34
7827 01:15:30.529852 [Byte1]: 34
7828 01:15:30.534628
7829 01:15:30.535161 Set Vref, RX VrefLevel [Byte0]: 35
7830 01:15:30.537749 [Byte1]: 35
7831 01:15:30.541950
7832 01:15:30.542745 Set Vref, RX VrefLevel [Byte0]: 36
7833 01:15:30.545248 [Byte1]: 36
7834 01:15:30.549620
7835 01:15:30.550179 Set Vref, RX VrefLevel [Byte0]: 37
7836 01:15:30.553296 [Byte1]: 37
7837 01:15:30.557245
7838 01:15:30.557837 Set Vref, RX VrefLevel [Byte0]: 38
7839 01:15:30.560937 [Byte1]: 38
7840 01:15:30.564886
7841 01:15:30.565439 Set Vref, RX VrefLevel [Byte0]: 39
7842 01:15:30.568381 [Byte1]: 39
7843 01:15:30.572508
7844 01:15:30.573064 Set Vref, RX VrefLevel [Byte0]: 40
7845 01:15:30.575782 [Byte1]: 40
7846 01:15:30.580053
7847 01:15:30.580619 Set Vref, RX VrefLevel [Byte0]: 41
7848 01:15:30.583173 [Byte1]: 41
7849 01:15:30.587622
7850 01:15:30.588171 Set Vref, RX VrefLevel [Byte0]: 42
7851 01:15:30.590641 [Byte1]: 42
7852 01:15:30.595407
7853 01:15:30.596046 Set Vref, RX VrefLevel [Byte0]: 43
7854 01:15:30.598714 [Byte1]: 43
7855 01:15:30.603161
7856 01:15:30.603717 Set Vref, RX VrefLevel [Byte0]: 44
7857 01:15:30.606317 [Byte1]: 44
7858 01:15:30.610473
7859 01:15:30.611024 Set Vref, RX VrefLevel [Byte0]: 45
7860 01:15:30.614091 [Byte1]: 45
7861 01:15:30.618117
7862 01:15:30.618667 Set Vref, RX VrefLevel [Byte0]: 46
7863 01:15:30.621214 [Byte1]: 46
7864 01:15:30.626080
7865 01:15:30.626653 Set Vref, RX VrefLevel [Byte0]: 47
7866 01:15:30.629417 [Byte1]: 47
7867 01:15:30.633578
7868 01:15:30.634142 Set Vref, RX VrefLevel [Byte0]: 48
7869 01:15:30.637092 [Byte1]: 48
7870 01:15:30.640879
7871 01:15:30.641446 Set Vref, RX VrefLevel [Byte0]: 49
7872 01:15:30.644100 [Byte1]: 49
7873 01:15:30.648759
7874 01:15:30.649328 Set Vref, RX VrefLevel [Byte0]: 50
7875 01:15:30.652120 [Byte1]: 50
7876 01:15:30.656312
7877 01:15:30.656869 Set Vref, RX VrefLevel [Byte0]: 51
7878 01:15:30.659919 [Byte1]: 51
7879 01:15:30.664273
7880 01:15:30.664864 Set Vref, RX VrefLevel [Byte0]: 52
7881 01:15:30.666942 [Byte1]: 52
7882 01:15:30.671633
7883 01:15:30.672202 Set Vref, RX VrefLevel [Byte0]: 53
7884 01:15:30.675100 [Byte1]: 53
7885 01:15:30.679024
7886 01:15:30.679566 Set Vref, RX VrefLevel [Byte0]: 54
7887 01:15:30.682535 [Byte1]: 54
7888 01:15:30.686791
7889 01:15:30.687338 Set Vref, RX VrefLevel [Byte0]: 55
7890 01:15:30.690073 [Byte1]: 55
7891 01:15:30.694372
7892 01:15:30.694921 Set Vref, RX VrefLevel [Byte0]: 56
7893 01:15:30.697925 [Byte1]: 56
7894 01:15:30.701868
7895 01:15:30.702415 Set Vref, RX VrefLevel [Byte0]: 57
7896 01:15:30.705496 [Byte1]: 57
7897 01:15:30.709496
7898 01:15:30.710098 Set Vref, RX VrefLevel [Byte0]: 58
7899 01:15:30.712683 [Byte1]: 58
7900 01:15:30.717110
7901 01:15:30.717695 Set Vref, RX VrefLevel [Byte0]: 59
7902 01:15:30.720603 [Byte1]: 59
7903 01:15:30.724382
7904 01:15:30.724838 Set Vref, RX VrefLevel [Byte0]: 60
7905 01:15:30.728184 [Byte1]: 60
7906 01:15:30.732307
7907 01:15:30.732763 Set Vref, RX VrefLevel [Byte0]: 61
7908 01:15:30.735248 [Byte1]: 61
7909 01:15:30.740173
7910 01:15:30.740792 Set Vref, RX VrefLevel [Byte0]: 62
7911 01:15:30.743357 [Byte1]: 62
7912 01:15:30.747552
7913 01:15:30.748104 Set Vref, RX VrefLevel [Byte0]: 63
7914 01:15:30.750660 [Byte1]: 63
7915 01:15:30.754773
7916 01:15:30.755183 Set Vref, RX VrefLevel [Byte0]: 64
7917 01:15:30.758105 [Byte1]: 64
7918 01:15:30.762721
7919 01:15:30.763240 Set Vref, RX VrefLevel [Byte0]: 65
7920 01:15:30.765691 [Byte1]: 65
7921 01:15:30.770388
7922 01:15:30.770917 Set Vref, RX VrefLevel [Byte0]: 66
7923 01:15:30.773338 [Byte1]: 66
7924 01:15:30.778013
7925 01:15:30.778600 Set Vref, RX VrefLevel [Byte0]: 67
7926 01:15:30.781418 [Byte1]: 67
7927 01:15:30.785895
7928 01:15:30.786463 Set Vref, RX VrefLevel [Byte0]: 68
7929 01:15:30.789061 [Byte1]: 68
7930 01:15:30.792987
7931 01:15:30.793591 Set Vref, RX VrefLevel [Byte0]: 69
7932 01:15:30.796211 [Byte1]: 69
7933 01:15:30.800958
7934 01:15:30.801547 Set Vref, RX VrefLevel [Byte0]: 70
7935 01:15:30.804537 [Byte1]: 70
7936 01:15:30.808395
7937 01:15:30.808958 Set Vref, RX VrefLevel [Byte0]: 71
7938 01:15:30.811519 [Byte1]: 71
7939 01:15:30.816003
7940 01:15:30.816535 Set Vref, RX VrefLevel [Byte0]: 72
7941 01:15:30.819039 [Byte1]: 72
7942 01:15:30.823430
7943 01:15:30.823868 Set Vref, RX VrefLevel [Byte0]: 73
7944 01:15:30.826704 [Byte1]: 73
7945 01:15:30.831325
7946 01:15:30.831832 Set Vref, RX VrefLevel [Byte0]: 74
7947 01:15:30.834715 [Byte1]: 74
7948 01:15:30.838741
7949 01:15:30.839250 Set Vref, RX VrefLevel [Byte0]: 75
7950 01:15:30.841976 [Byte1]: 75
7951 01:15:30.846235
7952 01:15:30.846849 Set Vref, RX VrefLevel [Byte0]: 76
7953 01:15:30.849906 [Byte1]: 76
7954 01:15:30.854455
7955 01:15:30.854966 Final RX Vref Byte 0 = 60 to rank0
7956 01:15:30.857568 Final RX Vref Byte 1 = 60 to rank0
7957 01:15:30.860803 Final RX Vref Byte 0 = 60 to rank1
7958 01:15:30.863986 Final RX Vref Byte 1 = 60 to rank1==
7959 01:15:30.867556 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 01:15:30.874067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 01:15:30.874570 ==
7962 01:15:30.874898 DQS Delay:
7963 01:15:30.875204 DQS0 = 0, DQS1 = 0
7964 01:15:30.877188 DQM Delay:
7965 01:15:30.877731 DQM0 = 125, DQM1 = 120
7966 01:15:30.880796 DQ Delay:
7967 01:15:30.884632 DQ0 =124, DQ1 =128, DQ2 =126, DQ3 =122
7968 01:15:30.887007 DQ4 =124, DQ5 =112, DQ6 =132, DQ7 =138
7969 01:15:30.890944 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7970 01:15:30.893995 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =128
7971 01:15:30.894517
7972 01:15:30.894849
7973 01:15:30.895156
7974 01:15:30.897406 [DramC_TX_OE_Calibration] TA2
7975 01:15:30.901065 Original DQ_B0 (3 6) =30, OEN = 27
7976 01:15:30.903780 Original DQ_B1 (3 6) =30, OEN = 27
7977 01:15:30.907210 24, 0x0, End_B0=24 End_B1=24
7978 01:15:30.907767 25, 0x0, End_B0=25 End_B1=25
7979 01:15:30.910879 26, 0x0, End_B0=26 End_B1=26
7980 01:15:30.913671 27, 0x0, End_B0=27 End_B1=27
7981 01:15:30.917312 28, 0x0, End_B0=28 End_B1=28
7982 01:15:30.917912 29, 0x0, End_B0=29 End_B1=29
7983 01:15:30.920898 30, 0x0, End_B0=30 End_B1=30
7984 01:15:30.924428 31, 0x4545, End_B0=30 End_B1=30
7985 01:15:30.926902 Byte0 end_step=30 best_step=27
7986 01:15:30.930288 Byte1 end_step=30 best_step=27
7987 01:15:30.933429 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 01:15:30.937195 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 01:15:30.937789
7990 01:15:30.938159
7991 01:15:30.943684 [DQSOSCAuto] RK0, (LSB)MR18= 0x1110, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
7992 01:15:30.947134 CH0 RK0: MR19=303, MR18=1110
7993 01:15:30.953230 CH0_RK0: MR19=0x303, MR18=0x1110, DQSOSC=401, MR23=63, INC=22, DEC=15
7994 01:15:30.953792
7995 01:15:30.956873 ----->DramcWriteLeveling(PI) begin...
7996 01:15:30.957407 ==
7997 01:15:30.960265 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 01:15:30.963482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 01:15:30.964046 ==
8000 01:15:30.967188 Write leveling (Byte 0): 32 => 32
8001 01:15:30.970513 Write leveling (Byte 1): 27 => 27
8002 01:15:30.973589 DramcWriteLeveling(PI) end<-----
8003 01:15:30.974101
8004 01:15:30.974432 ==
8005 01:15:30.976753 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 01:15:30.980351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 01:15:30.980864 ==
8008 01:15:30.983502 [Gating] SW mode calibration
8009 01:15:30.990418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 01:15:30.996984 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 01:15:31.000058 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 01:15:31.003750 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 01:15:31.010442 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 01:15:31.013734 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
8015 01:15:31.017159 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (1 1) (1 1)
8016 01:15:31.023443 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 01:15:31.026452 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 01:15:31.030019 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 01:15:31.036478 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 01:15:31.039890 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 01:15:31.043098 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8022 01:15:31.050069 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8023 01:15:31.052758 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8024 01:15:31.056146 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8025 01:15:31.063285 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 01:15:31.066161 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 01:15:31.069623 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 01:15:31.076539 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 01:15:31.079329 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8030 01:15:31.082871 1 6 12 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (1 1)
8031 01:15:31.089728 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8032 01:15:31.092823 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8033 01:15:31.096173 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 01:15:31.103103 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 01:15:31.105904 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 01:15:31.109190 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 01:15:31.115771 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 01:15:31.119094 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 01:15:31.122325 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8040 01:15:31.129506 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 01:15:31.132192 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 01:15:31.135624 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 01:15:31.142742 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 01:15:31.145849 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 01:15:31.149143 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 01:15:31.155683 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 01:15:31.158669 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 01:15:31.162316 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 01:15:31.168654 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 01:15:31.172117 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 01:15:31.175504 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 01:15:31.181814 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 01:15:31.185439 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8054 01:15:31.188569 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8055 01:15:31.195292 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 01:15:31.195831 Total UI for P1: 0, mck2ui 16
8057 01:15:31.202140 best dqsien dly found for B0: ( 1, 9, 10)
8058 01:15:31.204954 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8059 01:15:31.208508 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 01:15:31.211774 Total UI for P1: 0, mck2ui 16
8061 01:15:31.214653 best dqsien dly found for B1: ( 1, 9, 18)
8062 01:15:31.218451 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8063 01:15:31.221562 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8064 01:15:31.221984
8065 01:15:31.228424 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8066 01:15:31.232011 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8067 01:15:31.234571 [Gating] SW calibration Done
8068 01:15:31.234986 ==
8069 01:15:31.238410 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 01:15:31.241794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 01:15:31.242312 ==
8072 01:15:31.242643 RX Vref Scan: 0
8073 01:15:31.242955
8074 01:15:31.244644 RX Vref 0 -> 0, step: 1
8075 01:15:31.245150
8076 01:15:31.248001 RX Delay 0 -> 252, step: 8
8077 01:15:31.251549 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8078 01:15:31.254714 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8079 01:15:31.257878 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8080 01:15:31.264485 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8081 01:15:31.268404 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8082 01:15:31.270865 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8083 01:15:31.274220 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8084 01:15:31.281032 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8085 01:15:31.284729 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8086 01:15:31.288022 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8087 01:15:31.290951 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8088 01:15:31.294148 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8089 01:15:31.300878 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8090 01:15:31.304365 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8091 01:15:31.307562 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8092 01:15:31.310279 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8093 01:15:31.310696 ==
8094 01:15:31.314188 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 01:15:31.320551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 01:15:31.321090 ==
8097 01:15:31.321426 DQS Delay:
8098 01:15:31.323840 DQS0 = 0, DQS1 = 0
8099 01:15:31.324254 DQM Delay:
8100 01:15:31.324584 DQM0 = 128, DQM1 = 121
8101 01:15:31.327146 DQ Delay:
8102 01:15:31.330236 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8103 01:15:31.333502 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8104 01:15:31.336935 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8105 01:15:31.340796 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8106 01:15:31.341321
8107 01:15:31.341709
8108 01:15:31.342021 ==
8109 01:15:31.343585 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 01:15:31.350031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 01:15:31.350448 ==
8112 01:15:31.350772
8113 01:15:31.351074
8114 01:15:31.351365 TX Vref Scan disable
8115 01:15:31.353472 == TX Byte 0 ==
8116 01:15:31.356531 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8117 01:15:31.363738 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8118 01:15:31.364250 == TX Byte 1 ==
8119 01:15:31.367187 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8120 01:15:31.373398 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8121 01:15:31.374058 ==
8122 01:15:31.376567 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 01:15:31.379743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 01:15:31.380266 ==
8125 01:15:31.392897
8126 01:15:31.396256 TX Vref early break, caculate TX vref
8127 01:15:31.399527 TX Vref=16, minBit 0, minWin=22, winSum=364
8128 01:15:31.403122 TX Vref=18, minBit 8, minWin=22, winSum=370
8129 01:15:31.406204 TX Vref=20, minBit 8, minWin=22, winSum=376
8130 01:15:31.409616 TX Vref=22, minBit 1, minWin=23, winSum=389
8131 01:15:31.412683 TX Vref=24, minBit 0, minWin=24, winSum=398
8132 01:15:31.419720 TX Vref=26, minBit 8, minWin=24, winSum=406
8133 01:15:31.422530 TX Vref=28, minBit 8, minWin=24, winSum=410
8134 01:15:31.426137 TX Vref=30, minBit 8, minWin=23, winSum=405
8135 01:15:31.429354 TX Vref=32, minBit 8, minWin=23, winSum=395
8136 01:15:31.432817 TX Vref=34, minBit 8, minWin=22, winSum=386
8137 01:15:31.439075 [TxChooseVref] Worse bit 8, Min win 24, Win sum 410, Final Vref 28
8138 01:15:31.439595
8139 01:15:31.442209 Final TX Range 0 Vref 28
8140 01:15:31.442626
8141 01:15:31.442953 ==
8142 01:15:31.445563 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 01:15:31.448628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 01:15:31.449049 ==
8145 01:15:31.449374
8146 01:15:31.449776
8147 01:15:31.452049 TX Vref Scan disable
8148 01:15:31.458971 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8149 01:15:31.459491 == TX Byte 0 ==
8150 01:15:31.461860 u2DelayCellOfst[0]=11 cells (3 PI)
8151 01:15:31.465318 u2DelayCellOfst[1]=18 cells (5 PI)
8152 01:15:31.469144 u2DelayCellOfst[2]=11 cells (3 PI)
8153 01:15:31.472052 u2DelayCellOfst[3]=11 cells (3 PI)
8154 01:15:31.475523 u2DelayCellOfst[4]=7 cells (2 PI)
8155 01:15:31.478405 u2DelayCellOfst[5]=0 cells (0 PI)
8156 01:15:31.482028 u2DelayCellOfst[6]=18 cells (5 PI)
8157 01:15:31.485497 u2DelayCellOfst[7]=18 cells (5 PI)
8158 01:15:31.488825 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8159 01:15:31.492246 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8160 01:15:31.495314 == TX Byte 1 ==
8161 01:15:31.498537 u2DelayCellOfst[8]=0 cells (0 PI)
8162 01:15:31.501618 u2DelayCellOfst[9]=3 cells (1 PI)
8163 01:15:31.502076 u2DelayCellOfst[10]=7 cells (2 PI)
8164 01:15:31.504758 u2DelayCellOfst[11]=3 cells (1 PI)
8165 01:15:31.508254 u2DelayCellOfst[12]=15 cells (4 PI)
8166 01:15:31.511611 u2DelayCellOfst[13]=15 cells (4 PI)
8167 01:15:31.515017 u2DelayCellOfst[14]=15 cells (4 PI)
8168 01:15:31.518864 u2DelayCellOfst[15]=15 cells (4 PI)
8169 01:15:31.525151 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8170 01:15:31.528460 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8171 01:15:31.528880 DramC Write-DBI on
8172 01:15:31.529208 ==
8173 01:15:31.531844 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 01:15:31.538166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 01:15:31.538585 ==
8176 01:15:31.538914
8177 01:15:31.539215
8178 01:15:31.539510 TX Vref Scan disable
8179 01:15:31.542248 == TX Byte 0 ==
8180 01:15:31.545618 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8181 01:15:31.548980 == TX Byte 1 ==
8182 01:15:31.552292 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8183 01:15:31.555760 DramC Write-DBI off
8184 01:15:31.556475
8185 01:15:31.556929 [DATLAT]
8186 01:15:31.557250 Freq=1600, CH0 RK1
8187 01:15:31.557596
8188 01:15:31.558551 DATLAT Default: 0xf
8189 01:15:31.558912 0, 0xFFFF, sum = 0
8190 01:15:31.562400 1, 0xFFFF, sum = 0
8191 01:15:31.565308 2, 0xFFFF, sum = 0
8192 01:15:31.565774 3, 0xFFFF, sum = 0
8193 01:15:31.568881 4, 0xFFFF, sum = 0
8194 01:15:31.569383 5, 0xFFFF, sum = 0
8195 01:15:31.572301 6, 0xFFFF, sum = 0
8196 01:15:31.572721 7, 0xFFFF, sum = 0
8197 01:15:31.576022 8, 0xFFFF, sum = 0
8198 01:15:31.576564 9, 0xFFFF, sum = 0
8199 01:15:31.578408 10, 0xFFFF, sum = 0
8200 01:15:31.578852 11, 0xFFFF, sum = 0
8201 01:15:31.581899 12, 0xFFFF, sum = 0
8202 01:15:31.582339 13, 0xCFFF, sum = 0
8203 01:15:31.585354 14, 0x0, sum = 1
8204 01:15:31.585816 15, 0x0, sum = 2
8205 01:15:31.588498 16, 0x0, sum = 3
8206 01:15:31.588918 17, 0x0, sum = 4
8207 01:15:31.592477 best_step = 15
8208 01:15:31.592993
8209 01:15:31.593324 ==
8210 01:15:31.595225 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 01:15:31.598158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 01:15:31.598575 ==
8213 01:15:31.601675 RX Vref Scan: 0
8214 01:15:31.602198
8215 01:15:31.602578 RX Vref 0 -> 0, step: 1
8216 01:15:31.602898
8217 01:15:31.604853 RX Delay 3 -> 252, step: 4
8218 01:15:31.611677 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8219 01:15:31.614487 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8220 01:15:31.617773 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8221 01:15:31.621152 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8222 01:15:31.624764 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8223 01:15:31.631376 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8224 01:15:31.634516 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8225 01:15:31.637706 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8226 01:15:31.641428 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8227 01:15:31.645017 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8228 01:15:31.651199 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8229 01:15:31.654281 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8230 01:15:31.657504 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8231 01:15:31.661372 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8232 01:15:31.664880 iDelay=191, Bit 14, Center 126 (67 ~ 186) 120
8233 01:15:31.670831 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8234 01:15:31.671335 ==
8235 01:15:31.674492 Dram Type= 6, Freq= 0, CH_0, rank 1
8236 01:15:31.677452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 01:15:31.677897 ==
8238 01:15:31.678228 DQS Delay:
8239 01:15:31.680765 DQS0 = 0, DQS1 = 0
8240 01:15:31.681175 DQM Delay:
8241 01:15:31.684473 DQM0 = 124, DQM1 = 117
8242 01:15:31.685052 DQ Delay:
8243 01:15:31.687567 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8244 01:15:31.691129 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8245 01:15:31.693989 DQ8 =112, DQ9 =104, DQ10 =118, DQ11 =112
8246 01:15:31.700902 DQ12 =124, DQ13 =122, DQ14 =126, DQ15 =124
8247 01:15:31.701633
8248 01:15:31.701986
8249 01:15:31.702295
8250 01:15:31.702594 [DramC_TX_OE_Calibration] TA2
8251 01:15:31.704205 Original DQ_B0 (3 6) =30, OEN = 27
8252 01:15:31.707605 Original DQ_B1 (3 6) =30, OEN = 27
8253 01:15:31.710609 24, 0x0, End_B0=24 End_B1=24
8254 01:15:31.714000 25, 0x0, End_B0=25 End_B1=25
8255 01:15:31.717652 26, 0x0, End_B0=26 End_B1=26
8256 01:15:31.718172 27, 0x0, End_B0=27 End_B1=27
8257 01:15:31.720752 28, 0x0, End_B0=28 End_B1=28
8258 01:15:31.724044 29, 0x0, End_B0=29 End_B1=29
8259 01:15:31.727526 30, 0x0, End_B0=30 End_B1=30
8260 01:15:31.730570 31, 0x4141, End_B0=30 End_B1=30
8261 01:15:31.733860 Byte0 end_step=30 best_step=27
8262 01:15:31.734275 Byte1 end_step=30 best_step=27
8263 01:15:31.737667 Byte0 TX OE(2T, 0.5T) = (3, 3)
8264 01:15:31.740770 Byte1 TX OE(2T, 0.5T) = (3, 3)
8265 01:15:31.741281
8266 01:15:31.741654
8267 01:15:31.750674 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8268 01:15:31.751194 CH0 RK1: MR19=303, MR18=210E
8269 01:15:31.757239 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8270 01:15:31.760264 [RxdqsGatingPostProcess] freq 1600
8271 01:15:31.767345 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8272 01:15:31.770471 best DQS0 dly(2T, 0.5T) = (1, 1)
8273 01:15:31.773855 best DQS1 dly(2T, 0.5T) = (1, 1)
8274 01:15:31.777145 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8275 01:15:31.780132 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8276 01:15:31.780681 best DQS0 dly(2T, 0.5T) = (1, 1)
8277 01:15:31.784043 best DQS1 dly(2T, 0.5T) = (1, 1)
8278 01:15:31.786786 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8279 01:15:31.790199 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8280 01:15:31.793949 Pre-setting of DQS Precalculation
8281 01:15:31.800033 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8282 01:15:31.800577 ==
8283 01:15:31.803610 Dram Type= 6, Freq= 0, CH_1, rank 0
8284 01:15:31.807349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 01:15:31.807910 ==
8286 01:15:31.813493 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8287 01:15:31.816486 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8288 01:15:31.819920 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8289 01:15:31.826689 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8290 01:15:31.835761 [CA 0] Center 41 (12~71) winsize 60
8291 01:15:31.838782 [CA 1] Center 42 (13~72) winsize 60
8292 01:15:31.842078 [CA 2] Center 37 (9~66) winsize 58
8293 01:15:31.845279 [CA 3] Center 36 (7~66) winsize 60
8294 01:15:31.848549 [CA 4] Center 37 (8~66) winsize 59
8295 01:15:31.851904 [CA 5] Center 36 (7~66) winsize 60
8296 01:15:31.852312
8297 01:15:31.854851 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8298 01:15:31.855258
8299 01:15:31.858282 [CATrainingPosCal] consider 1 rank data
8300 01:15:31.861807 u2DelayCellTimex100 = 258/100 ps
8301 01:15:31.865580 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8302 01:15:31.871842 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8303 01:15:31.875587 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8304 01:15:31.878647 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8305 01:15:31.881704 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8306 01:15:31.885005 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8307 01:15:31.885413
8308 01:15:31.888703 CA PerBit enable=1, Macro0, CA PI delay=36
8309 01:15:31.889210
8310 01:15:31.891681 [CBTSetCACLKResult] CA Dly = 36
8311 01:15:31.895063 CS Dly: 10 (0~41)
8312 01:15:31.898636 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8313 01:15:31.901287 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8314 01:15:31.901718 ==
8315 01:15:31.904771 Dram Type= 6, Freq= 0, CH_1, rank 1
8316 01:15:31.911484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 01:15:31.911998 ==
8318 01:15:31.914927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8319 01:15:31.921405 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8320 01:15:31.924802 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8321 01:15:31.930987 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8322 01:15:31.938938 [CA 0] Center 42 (13~72) winsize 60
8323 01:15:31.942069 [CA 1] Center 42 (13~72) winsize 60
8324 01:15:31.945246 [CA 2] Center 38 (9~67) winsize 59
8325 01:15:31.948714 [CA 3] Center 36 (7~66) winsize 60
8326 01:15:31.951757 [CA 4] Center 38 (8~68) winsize 61
8327 01:15:31.955172 [CA 5] Center 36 (6~66) winsize 61
8328 01:15:31.955777
8329 01:15:31.958208 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8330 01:15:31.958660
8331 01:15:31.964812 [CATrainingPosCal] consider 2 rank data
8332 01:15:31.965371 u2DelayCellTimex100 = 258/100 ps
8333 01:15:31.971585 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8334 01:15:31.974980 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8335 01:15:31.978422 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8336 01:15:31.981477 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8337 01:15:31.985186 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8338 01:15:31.988412 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8339 01:15:31.988964
8340 01:15:31.991866 CA PerBit enable=1, Macro0, CA PI delay=36
8341 01:15:31.992413
8342 01:15:31.994653 [CBTSetCACLKResult] CA Dly = 36
8343 01:15:31.998036 CS Dly: 11 (0~44)
8344 01:15:32.001353 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8345 01:15:32.004956 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8346 01:15:32.005601
8347 01:15:32.008256 ----->DramcWriteLeveling(PI) begin...
8348 01:15:32.008810 ==
8349 01:15:32.011024 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 01:15:32.018411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 01:15:32.018969 ==
8352 01:15:32.021423 Write leveling (Byte 0): 24 => 24
8353 01:15:32.024606 Write leveling (Byte 1): 31 => 31
8354 01:15:32.025159 DramcWriteLeveling(PI) end<-----
8355 01:15:32.025556
8356 01:15:32.027762 ==
8357 01:15:32.030805 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 01:15:32.034447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 01:15:32.035007 ==
8360 01:15:32.037763 [Gating] SW mode calibration
8361 01:15:32.044500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8362 01:15:32.047497 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8363 01:15:32.053811 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 01:15:32.057489 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 01:15:32.060911 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 01:15:32.067406 1 4 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8367 01:15:32.070847 1 4 16 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
8368 01:15:32.073980 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 01:15:32.080575 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 01:15:32.084415 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 01:15:32.087402 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 01:15:32.094039 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 01:15:32.096913 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 01:15:32.100279 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8375 01:15:32.107139 1 5 16 | B1->B0 | 2727 2828 | 1 0 | (1 0) (1 0)
8376 01:15:32.109882 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8377 01:15:32.113579 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 01:15:32.120335 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 01:15:32.123896 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 01:15:32.127187 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 01:15:32.133477 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 01:15:32.137277 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8383 01:15:32.140256 1 6 16 | B1->B0 | 4343 4242 | 0 1 | (0 0) (1 1)
8384 01:15:32.147390 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 01:15:32.150728 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 01:15:32.153420 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 01:15:32.160118 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 01:15:32.163262 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 01:15:32.166949 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 01:15:32.173714 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 01:15:32.176924 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8392 01:15:32.180473 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8393 01:15:32.187019 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 01:15:32.190189 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 01:15:32.193286 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 01:15:32.199561 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 01:15:32.203470 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 01:15:32.206513 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 01:15:32.213060 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 01:15:32.216694 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 01:15:32.220146 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 01:15:32.226341 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 01:15:32.229972 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 01:15:32.232911 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 01:15:32.239349 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 01:15:32.242810 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 01:15:32.246061 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 01:15:32.249491 Total UI for P1: 0, mck2ui 16
8409 01:15:32.252694 best dqsien dly found for B0: ( 1, 9, 14)
8410 01:15:32.255826 Total UI for P1: 0, mck2ui 16
8411 01:15:32.259208 best dqsien dly found for B1: ( 1, 9, 14)
8412 01:15:32.262895 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8413 01:15:32.265642 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8414 01:15:32.266114
8415 01:15:32.272416 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8416 01:15:32.275802 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8417 01:15:32.279292 [Gating] SW calibration Done
8418 01:15:32.279817 ==
8419 01:15:32.282033 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 01:15:32.285658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 01:15:32.286189 ==
8422 01:15:32.286531 RX Vref Scan: 0
8423 01:15:32.286844
8424 01:15:32.289032 RX Vref 0 -> 0, step: 1
8425 01:15:32.289592
8426 01:15:32.292605 RX Delay 0 -> 252, step: 8
8427 01:15:32.295236 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8428 01:15:32.298783 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8429 01:15:32.302051 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8430 01:15:32.308789 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8431 01:15:32.312089 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8432 01:15:32.315069 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8433 01:15:32.319019 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8434 01:15:32.322141 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8435 01:15:32.328421 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8436 01:15:32.331928 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8437 01:15:32.335298 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8438 01:15:32.338227 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8439 01:15:32.345153 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8440 01:15:32.348118 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8441 01:15:32.352071 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8442 01:15:32.354752 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8443 01:15:32.355174 ==
8444 01:15:32.358191 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 01:15:32.365351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 01:15:32.365932 ==
8447 01:15:32.366273 DQS Delay:
8448 01:15:32.366585 DQS0 = 0, DQS1 = 0
8449 01:15:32.368191 DQM Delay:
8450 01:15:32.368607 DQM0 = 132, DQM1 = 126
8451 01:15:32.371824 DQ Delay:
8452 01:15:32.375268 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8453 01:15:32.378443 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8454 01:15:32.381762 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8455 01:15:32.385220 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8456 01:15:32.385833
8457 01:15:32.386178
8458 01:15:32.386494 ==
8459 01:15:32.388709 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 01:15:32.391375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 01:15:32.391909 ==
8462 01:15:32.394589
8463 01:15:32.394999
8464 01:15:32.395321 TX Vref Scan disable
8465 01:15:32.398464 == TX Byte 0 ==
8466 01:15:32.401775 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8467 01:15:32.404953 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8468 01:15:32.408521 == TX Byte 1 ==
8469 01:15:32.411833 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8470 01:15:32.414511 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8471 01:15:32.414979 ==
8472 01:15:32.418264 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 01:15:32.424500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 01:15:32.425068 ==
8475 01:15:32.436818
8476 01:15:32.440387 TX Vref early break, caculate TX vref
8477 01:15:32.443553 TX Vref=16, minBit 8, minWin=20, winSum=358
8478 01:15:32.446872 TX Vref=18, minBit 11, minWin=21, winSum=368
8479 01:15:32.450272 TX Vref=20, minBit 8, minWin=22, winSum=382
8480 01:15:32.453429 TX Vref=22, minBit 8, minWin=22, winSum=388
8481 01:15:32.456510 TX Vref=24, minBit 8, minWin=23, winSum=398
8482 01:15:32.463496 TX Vref=26, minBit 8, minWin=24, winSum=408
8483 01:15:32.466714 TX Vref=28, minBit 0, minWin=25, winSum=412
8484 01:15:32.470078 TX Vref=30, minBit 8, minWin=24, winSum=409
8485 01:15:32.473405 TX Vref=32, minBit 9, minWin=23, winSum=403
8486 01:15:32.476617 TX Vref=34, minBit 9, minWin=22, winSum=388
8487 01:15:32.483012 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 28
8488 01:15:32.483539
8489 01:15:32.486612 Final TX Range 0 Vref 28
8490 01:15:32.487138
8491 01:15:32.487470 ==
8492 01:15:32.490178 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 01:15:32.492934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 01:15:32.493357 ==
8495 01:15:32.493739
8496 01:15:32.494050
8497 01:15:32.496471 TX Vref Scan disable
8498 01:15:32.503509 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8499 01:15:32.504034 == TX Byte 0 ==
8500 01:15:32.506126 u2DelayCellOfst[0]=18 cells (5 PI)
8501 01:15:32.509784 u2DelayCellOfst[1]=15 cells (4 PI)
8502 01:15:32.513243 u2DelayCellOfst[2]=0 cells (0 PI)
8503 01:15:32.516541 u2DelayCellOfst[3]=7 cells (2 PI)
8504 01:15:32.519971 u2DelayCellOfst[4]=7 cells (2 PI)
8505 01:15:32.522876 u2DelayCellOfst[5]=22 cells (6 PI)
8506 01:15:32.526175 u2DelayCellOfst[6]=18 cells (5 PI)
8507 01:15:32.529754 u2DelayCellOfst[7]=7 cells (2 PI)
8508 01:15:32.533460 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8509 01:15:32.536327 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8510 01:15:32.539457 == TX Byte 1 ==
8511 01:15:32.542980 u2DelayCellOfst[8]=0 cells (0 PI)
8512 01:15:32.543575 u2DelayCellOfst[9]=7 cells (2 PI)
8513 01:15:32.546004 u2DelayCellOfst[10]=11 cells (3 PI)
8514 01:15:32.549740 u2DelayCellOfst[11]=3 cells (1 PI)
8515 01:15:32.552916 u2DelayCellOfst[12]=15 cells (4 PI)
8516 01:15:32.556410 u2DelayCellOfst[13]=18 cells (5 PI)
8517 01:15:32.559098 u2DelayCellOfst[14]=18 cells (5 PI)
8518 01:15:32.562695 u2DelayCellOfst[15]=15 cells (4 PI)
8519 01:15:32.566028 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8520 01:15:32.572400 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8521 01:15:32.572931 DramC Write-DBI on
8522 01:15:32.573373 ==
8523 01:15:32.576078 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 01:15:32.581937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 01:15:32.582362 ==
8526 01:15:32.582692
8527 01:15:32.583003
8528 01:15:32.583302 TX Vref Scan disable
8529 01:15:32.586133 == TX Byte 0 ==
8530 01:15:32.589564 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8531 01:15:32.593062 == TX Byte 1 ==
8532 01:15:32.596104 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8533 01:15:32.599306 DramC Write-DBI off
8534 01:15:32.599725
8535 01:15:32.600053 [DATLAT]
8536 01:15:32.600361 Freq=1600, CH1 RK0
8537 01:15:32.600663
8538 01:15:32.603319 DATLAT Default: 0xf
8539 01:15:32.603847 0, 0xFFFF, sum = 0
8540 01:15:32.606076 1, 0xFFFF, sum = 0
8541 01:15:32.609652 2, 0xFFFF, sum = 0
8542 01:15:32.610195 3, 0xFFFF, sum = 0
8543 01:15:32.613133 4, 0xFFFF, sum = 0
8544 01:15:32.613700 5, 0xFFFF, sum = 0
8545 01:15:32.615748 6, 0xFFFF, sum = 0
8546 01:15:32.616202 7, 0xFFFF, sum = 0
8547 01:15:32.619862 8, 0xFFFF, sum = 0
8548 01:15:32.620398 9, 0xFFFF, sum = 0
8549 01:15:32.622691 10, 0xFFFF, sum = 0
8550 01:15:32.623219 11, 0xFFFF, sum = 0
8551 01:15:32.626191 12, 0xFFFF, sum = 0
8552 01:15:32.626730 13, 0x8FFF, sum = 0
8553 01:15:32.629602 14, 0x0, sum = 1
8554 01:15:32.630134 15, 0x0, sum = 2
8555 01:15:32.633158 16, 0x0, sum = 3
8556 01:15:32.633729 17, 0x0, sum = 4
8557 01:15:32.636672 best_step = 15
8558 01:15:32.637193
8559 01:15:32.637722 ==
8560 01:15:32.639305 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 01:15:32.642811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 01:15:32.643337 ==
8563 01:15:32.646248 RX Vref Scan: 1
8564 01:15:32.646681
8565 01:15:32.647138 Set Vref Range= 24 -> 127
8566 01:15:32.647774
8567 01:15:32.649093 RX Vref 24 -> 127, step: 1
8568 01:15:32.649535
8569 01:15:32.652778 RX Delay 11 -> 252, step: 4
8570 01:15:32.653326
8571 01:15:32.655969 Set Vref, RX VrefLevel [Byte0]: 24
8572 01:15:32.659127 [Byte1]: 24
8573 01:15:32.659546
8574 01:15:32.662675 Set Vref, RX VrefLevel [Byte0]: 25
8575 01:15:32.665556 [Byte1]: 25
8576 01:15:32.669226
8577 01:15:32.669682 Set Vref, RX VrefLevel [Byte0]: 26
8578 01:15:32.673024 [Byte1]: 26
8579 01:15:32.677097
8580 01:15:32.677822 Set Vref, RX VrefLevel [Byte0]: 27
8581 01:15:32.680426 [Byte1]: 27
8582 01:15:32.684431
8583 01:15:32.684948 Set Vref, RX VrefLevel [Byte0]: 28
8584 01:15:32.687838 [Byte1]: 28
8585 01:15:32.691863
8586 01:15:32.692544 Set Vref, RX VrefLevel [Byte0]: 29
8587 01:15:32.695258 [Byte1]: 29
8588 01:15:32.699428
8589 01:15:32.699844 Set Vref, RX VrefLevel [Byte0]: 30
8590 01:15:32.702970 [Byte1]: 30
8591 01:15:32.707122
8592 01:15:32.707674 Set Vref, RX VrefLevel [Byte0]: 31
8593 01:15:32.710287 [Byte1]: 31
8594 01:15:32.714964
8595 01:15:32.715381 Set Vref, RX VrefLevel [Byte0]: 32
8596 01:15:32.717670 [Byte1]: 32
8597 01:15:32.722228
8598 01:15:32.722647 Set Vref, RX VrefLevel [Byte0]: 33
8599 01:15:32.726089 [Byte1]: 33
8600 01:15:32.729946
8601 01:15:32.730405 Set Vref, RX VrefLevel [Byte0]: 34
8602 01:15:32.733059 [Byte1]: 34
8603 01:15:32.737682
8604 01:15:32.738098 Set Vref, RX VrefLevel [Byte0]: 35
8605 01:15:32.741733 [Byte1]: 35
8606 01:15:32.745293
8607 01:15:32.745777 Set Vref, RX VrefLevel [Byte0]: 36
8608 01:15:32.748668 [Byte1]: 36
8609 01:15:32.752822
8610 01:15:32.753342 Set Vref, RX VrefLevel [Byte0]: 37
8611 01:15:32.756209 [Byte1]: 37
8612 01:15:32.760291
8613 01:15:32.760724 Set Vref, RX VrefLevel [Byte0]: 38
8614 01:15:32.763567 [Byte1]: 38
8615 01:15:32.767691
8616 01:15:32.768123 Set Vref, RX VrefLevel [Byte0]: 39
8617 01:15:32.771255 [Byte1]: 39
8618 01:15:32.775884
8619 01:15:32.776408 Set Vref, RX VrefLevel [Byte0]: 40
8620 01:15:32.778838 [Byte1]: 40
8621 01:15:32.783459
8622 01:15:32.783981 Set Vref, RX VrefLevel [Byte0]: 41
8623 01:15:32.786794 [Byte1]: 41
8624 01:15:32.790920
8625 01:15:32.791440 Set Vref, RX VrefLevel [Byte0]: 42
8626 01:15:32.794402 [Byte1]: 42
8627 01:15:32.798464
8628 01:15:32.798986 Set Vref, RX VrefLevel [Byte0]: 43
8629 01:15:32.801850 [Byte1]: 43
8630 01:15:32.806411
8631 01:15:32.806949 Set Vref, RX VrefLevel [Byte0]: 44
8632 01:15:32.809703 [Byte1]: 44
8633 01:15:32.813749
8634 01:15:32.814298 Set Vref, RX VrefLevel [Byte0]: 45
8635 01:15:32.817423 [Byte1]: 45
8636 01:15:32.821551
8637 01:15:32.822082 Set Vref, RX VrefLevel [Byte0]: 46
8638 01:15:32.824608 [Byte1]: 46
8639 01:15:32.829063
8640 01:15:32.829622 Set Vref, RX VrefLevel [Byte0]: 47
8641 01:15:32.832360 [Byte1]: 47
8642 01:15:32.836286
8643 01:15:32.836737 Set Vref, RX VrefLevel [Byte0]: 48
8644 01:15:32.840128 [Byte1]: 48
8645 01:15:32.844087
8646 01:15:32.844605 Set Vref, RX VrefLevel [Byte0]: 49
8647 01:15:32.847128 [Byte1]: 49
8648 01:15:32.851896
8649 01:15:32.852423 Set Vref, RX VrefLevel [Byte0]: 50
8650 01:15:32.855072 [Byte1]: 50
8651 01:15:32.859270
8652 01:15:32.859703 Set Vref, RX VrefLevel [Byte0]: 51
8653 01:15:32.862457 [Byte1]: 51
8654 01:15:32.867710
8655 01:15:32.868234 Set Vref, RX VrefLevel [Byte0]: 52
8656 01:15:32.870254 [Byte1]: 52
8657 01:15:32.875091
8658 01:15:32.875616 Set Vref, RX VrefLevel [Byte0]: 53
8659 01:15:32.877675 [Byte1]: 53
8660 01:15:32.882366
8661 01:15:32.882894 Set Vref, RX VrefLevel [Byte0]: 54
8662 01:15:32.885723 [Byte1]: 54
8663 01:15:32.890026
8664 01:15:32.890557 Set Vref, RX VrefLevel [Byte0]: 55
8665 01:15:32.896408 [Byte1]: 55
8666 01:15:32.896937
8667 01:15:32.899706 Set Vref, RX VrefLevel [Byte0]: 56
8668 01:15:32.902745 [Byte1]: 56
8669 01:15:32.903272
8670 01:15:32.906610 Set Vref, RX VrefLevel [Byte0]: 57
8671 01:15:32.909350 [Byte1]: 57
8672 01:15:32.912596
8673 01:15:32.913126 Set Vref, RX VrefLevel [Byte0]: 58
8674 01:15:32.916247 [Byte1]: 58
8675 01:15:32.920669
8676 01:15:32.921213 Set Vref, RX VrefLevel [Byte0]: 59
8677 01:15:32.924005 [Byte1]: 59
8678 01:15:32.927614
8679 01:15:32.928045 Set Vref, RX VrefLevel [Byte0]: 60
8680 01:15:32.931614 [Byte1]: 60
8681 01:15:32.935257
8682 01:15:32.935689 Set Vref, RX VrefLevel [Byte0]: 61
8683 01:15:32.939032 [Byte1]: 61
8684 01:15:32.943305
8685 01:15:32.943834 Set Vref, RX VrefLevel [Byte0]: 62
8686 01:15:32.946166 [Byte1]: 62
8687 01:15:32.950690
8688 01:15:32.951212 Set Vref, RX VrefLevel [Byte0]: 63
8689 01:15:32.954190 [Byte1]: 63
8690 01:15:32.958470
8691 01:15:32.958906 Set Vref, RX VrefLevel [Byte0]: 64
8692 01:15:32.961337 [Byte1]: 64
8693 01:15:32.966146
8694 01:15:32.966669 Set Vref, RX VrefLevel [Byte0]: 65
8695 01:15:32.969109 [Byte1]: 65
8696 01:15:32.974163
8697 01:15:32.974686 Set Vref, RX VrefLevel [Byte0]: 66
8698 01:15:32.977089 [Byte1]: 66
8699 01:15:32.981663
8700 01:15:32.982233 Set Vref, RX VrefLevel [Byte0]: 67
8701 01:15:32.984679 [Byte1]: 67
8702 01:15:32.988679
8703 01:15:32.989112 Set Vref, RX VrefLevel [Byte0]: 68
8704 01:15:32.992140 [Byte1]: 68
8705 01:15:32.996756
8706 01:15:32.997283 Set Vref, RX VrefLevel [Byte0]: 69
8707 01:15:32.999599 [Byte1]: 69
8708 01:15:33.004154
8709 01:15:33.004738 Set Vref, RX VrefLevel [Byte0]: 70
8710 01:15:33.007410 [Byte1]: 70
8711 01:15:33.011748
8712 01:15:33.012163 Final RX Vref Byte 0 = 57 to rank0
8713 01:15:33.015077 Final RX Vref Byte 1 = 56 to rank0
8714 01:15:33.018012 Final RX Vref Byte 0 = 57 to rank1
8715 01:15:33.021857 Final RX Vref Byte 1 = 56 to rank1==
8716 01:15:33.025170 Dram Type= 6, Freq= 0, CH_1, rank 0
8717 01:15:33.031210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 01:15:33.031735 ==
8719 01:15:33.032180 DQS Delay:
8720 01:15:33.034625 DQS0 = 0, DQS1 = 0
8721 01:15:33.035059 DQM Delay:
8722 01:15:33.035499 DQM0 = 131, DQM1 = 123
8723 01:15:33.037858 DQ Delay:
8724 01:15:33.041292 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =130
8725 01:15:33.044811 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8726 01:15:33.048081 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8727 01:15:33.051314 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8728 01:15:33.051747
8729 01:15:33.052180
8730 01:15:33.052592
8731 01:15:33.054469 [DramC_TX_OE_Calibration] TA2
8732 01:15:33.057628 Original DQ_B0 (3 6) =30, OEN = 27
8733 01:15:33.061195 Original DQ_B1 (3 6) =30, OEN = 27
8734 01:15:33.064502 24, 0x0, End_B0=24 End_B1=24
8735 01:15:33.067358 25, 0x0, End_B0=25 End_B1=25
8736 01:15:33.067799 26, 0x0, End_B0=26 End_B1=26
8737 01:15:33.071160 27, 0x0, End_B0=27 End_B1=27
8738 01:15:33.074112 28, 0x0, End_B0=28 End_B1=28
8739 01:15:33.078105 29, 0x0, End_B0=29 End_B1=29
8740 01:15:33.078641 30, 0x0, End_B0=30 End_B1=30
8741 01:15:33.080670 31, 0x4141, End_B0=30 End_B1=30
8742 01:15:33.083991 Byte0 end_step=30 best_step=27
8743 01:15:33.087621 Byte1 end_step=30 best_step=27
8744 01:15:33.090703 Byte0 TX OE(2T, 0.5T) = (3, 3)
8745 01:15:33.094453 Byte1 TX OE(2T, 0.5T) = (3, 3)
8746 01:15:33.094974
8747 01:15:33.095416
8748 01:15:33.100570 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8749 01:15:33.104198 CH1 RK0: MR19=303, MR18=80D
8750 01:15:33.110692 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8751 01:15:33.111208
8752 01:15:33.113948 ----->DramcWriteLeveling(PI) begin...
8753 01:15:33.114485 ==
8754 01:15:33.117300 Dram Type= 6, Freq= 0, CH_1, rank 1
8755 01:15:33.121064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 01:15:33.121627 ==
8757 01:15:33.123406 Write leveling (Byte 0): 24 => 24
8758 01:15:33.126739 Write leveling (Byte 1): 27 => 27
8759 01:15:33.130415 DramcWriteLeveling(PI) end<-----
8760 01:15:33.130967
8761 01:15:33.131413 ==
8762 01:15:33.133755 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 01:15:33.136924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 01:15:33.140612 ==
8765 01:15:33.141136 [Gating] SW mode calibration
8766 01:15:33.150224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8767 01:15:33.153639 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8768 01:15:33.156730 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 01:15:33.162903 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 01:15:33.166376 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8771 01:15:33.169896 1 4 12 | B1->B0 | 3232 3535 | 1 0 | (1 1) (0 0)
8772 01:15:33.176575 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 01:15:33.180256 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 01:15:33.183427 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 01:15:33.189748 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 01:15:33.192684 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 01:15:33.196689 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 01:15:33.203165 1 5 8 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
8779 01:15:33.207309 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
8780 01:15:33.209681 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 01:15:33.216164 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 01:15:33.219495 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 01:15:33.222873 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 01:15:33.229146 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 01:15:33.232511 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 01:15:33.236077 1 6 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8787 01:15:33.242612 1 6 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8788 01:15:33.245913 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 01:15:33.249306 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 01:15:33.255894 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 01:15:33.259305 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 01:15:33.262066 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 01:15:33.269156 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 01:15:33.272369 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8795 01:15:33.275364 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8796 01:15:33.282051 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8797 01:15:33.285129 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 01:15:33.288815 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 01:15:33.295074 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 01:15:33.298532 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 01:15:33.301881 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 01:15:33.308610 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 01:15:33.311712 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 01:15:33.315398 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 01:15:33.321721 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 01:15:33.325018 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 01:15:33.328093 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 01:15:33.334767 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 01:15:33.338048 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8810 01:15:33.341689 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8811 01:15:33.348150 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8812 01:15:33.348701 Total UI for P1: 0, mck2ui 16
8813 01:15:33.354702 best dqsien dly found for B0: ( 1, 9, 6)
8814 01:15:33.357844 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 01:15:33.360961 Total UI for P1: 0, mck2ui 16
8816 01:15:33.364410 best dqsien dly found for B1: ( 1, 9, 10)
8817 01:15:33.368087 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8818 01:15:33.371237 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8819 01:15:33.371846
8820 01:15:33.374283 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8821 01:15:33.377913 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8822 01:15:33.381192 [Gating] SW calibration Done
8823 01:15:33.381656 ==
8824 01:15:33.384083 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 01:15:33.391174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 01:15:33.391698 ==
8827 01:15:33.392031 RX Vref Scan: 0
8828 01:15:33.392336
8829 01:15:33.394343 RX Vref 0 -> 0, step: 1
8830 01:15:33.394763
8831 01:15:33.398115 RX Delay 0 -> 252, step: 8
8832 01:15:33.400638 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8833 01:15:33.404446 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8834 01:15:33.407921 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8835 01:15:33.410433 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8836 01:15:33.417680 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8837 01:15:33.420490 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8838 01:15:33.424026 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8839 01:15:33.427463 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8840 01:15:33.430687 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8841 01:15:33.437206 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8842 01:15:33.440547 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8843 01:15:33.443790 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8844 01:15:33.447293 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8845 01:15:33.453886 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8846 01:15:33.457220 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8847 01:15:33.460093 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8848 01:15:33.460519 ==
8849 01:15:33.463248 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 01:15:33.466589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 01:15:33.467012 ==
8852 01:15:33.469731 DQS Delay:
8853 01:15:33.470144 DQS0 = 0, DQS1 = 0
8854 01:15:33.473622 DQM Delay:
8855 01:15:33.474129 DQM0 = 132, DQM1 = 128
8856 01:15:33.474462 DQ Delay:
8857 01:15:33.479894 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8858 01:15:33.483141 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8859 01:15:33.486498 DQ8 =115, DQ9 =115, DQ10 =135, DQ11 =123
8860 01:15:33.489893 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8861 01:15:33.490416
8862 01:15:33.490747
8863 01:15:33.491055 ==
8864 01:15:33.493336 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 01:15:33.496456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 01:15:33.496878 ==
8867 01:15:33.497339
8868 01:15:33.497715
8869 01:15:33.499492 TX Vref Scan disable
8870 01:15:33.502610 == TX Byte 0 ==
8871 01:15:33.506444 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8872 01:15:33.509747 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8873 01:15:33.512641 == TX Byte 1 ==
8874 01:15:33.516521 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8875 01:15:33.519247 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8876 01:15:33.519664 ==
8877 01:15:33.522816 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 01:15:33.529592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 01:15:33.530113 ==
8880 01:15:33.542417
8881 01:15:33.545337 TX Vref early break, caculate TX vref
8882 01:15:33.548721 TX Vref=16, minBit 0, minWin=23, winSum=386
8883 01:15:33.552232 TX Vref=18, minBit 5, minWin=23, winSum=391
8884 01:15:33.555215 TX Vref=20, minBit 0, minWin=23, winSum=404
8885 01:15:33.558742 TX Vref=22, minBit 0, minWin=24, winSum=408
8886 01:15:33.561621 TX Vref=24, minBit 0, minWin=24, winSum=416
8887 01:15:33.568457 TX Vref=26, minBit 5, minWin=25, winSum=422
8888 01:15:33.571960 TX Vref=28, minBit 0, minWin=25, winSum=423
8889 01:15:33.574773 TX Vref=30, minBit 1, minWin=25, winSum=421
8890 01:15:33.578483 TX Vref=32, minBit 1, minWin=24, winSum=417
8891 01:15:33.581971 TX Vref=34, minBit 1, minWin=24, winSum=407
8892 01:15:33.585186 TX Vref=36, minBit 1, minWin=23, winSum=400
8893 01:15:33.592091 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8894 01:15:33.592702
8895 01:15:33.595292 Final TX Range 0 Vref 28
8896 01:15:33.595858
8897 01:15:33.596222 ==
8898 01:15:33.598330 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 01:15:33.601458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 01:15:33.601962 ==
8901 01:15:33.602328
8902 01:15:33.602669
8903 01:15:33.605030 TX Vref Scan disable
8904 01:15:33.611368 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8905 01:15:33.611834 == TX Byte 0 ==
8906 01:15:33.614892 u2DelayCellOfst[0]=18 cells (5 PI)
8907 01:15:33.618380 u2DelayCellOfst[1]=11 cells (3 PI)
8908 01:15:33.621604 u2DelayCellOfst[2]=0 cells (0 PI)
8909 01:15:33.624767 u2DelayCellOfst[3]=7 cells (2 PI)
8910 01:15:33.628351 u2DelayCellOfst[4]=7 cells (2 PI)
8911 01:15:33.631586 u2DelayCellOfst[5]=22 cells (6 PI)
8912 01:15:33.635274 u2DelayCellOfst[6]=18 cells (5 PI)
8913 01:15:33.638145 u2DelayCellOfst[7]=7 cells (2 PI)
8914 01:15:33.641500 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8915 01:15:33.645204 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8916 01:15:33.648022 == TX Byte 1 ==
8917 01:15:33.651207 u2DelayCellOfst[8]=0 cells (0 PI)
8918 01:15:33.654930 u2DelayCellOfst[9]=7 cells (2 PI)
8919 01:15:33.657887 u2DelayCellOfst[10]=11 cells (3 PI)
8920 01:15:33.658448 u2DelayCellOfst[11]=7 cells (2 PI)
8921 01:15:33.660968 u2DelayCellOfst[12]=15 cells (4 PI)
8922 01:15:33.664642 u2DelayCellOfst[13]=18 cells (5 PI)
8923 01:15:33.668014 u2DelayCellOfst[14]=22 cells (6 PI)
8924 01:15:33.670984 u2DelayCellOfst[15]=18 cells (5 PI)
8925 01:15:33.677304 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8926 01:15:33.681198 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8927 01:15:33.681797 DramC Write-DBI on
8928 01:15:33.684179 ==
8929 01:15:33.684732 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 01:15:33.690752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 01:15:33.691309 ==
8932 01:15:33.691678
8933 01:15:33.692040
8934 01:15:33.694470 TX Vref Scan disable
8935 01:15:33.695032 == TX Byte 0 ==
8936 01:15:33.700583 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8937 01:15:33.701146 == TX Byte 1 ==
8938 01:15:33.704288 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8939 01:15:33.707492 DramC Write-DBI off
8940 01:15:33.708040
8941 01:15:33.708407 [DATLAT]
8942 01:15:33.710642 Freq=1600, CH1 RK1
8943 01:15:33.711108
8944 01:15:33.711470 DATLAT Default: 0xf
8945 01:15:33.713628 0, 0xFFFF, sum = 0
8946 01:15:33.714097 1, 0xFFFF, sum = 0
8947 01:15:33.717126 2, 0xFFFF, sum = 0
8948 01:15:33.717622 3, 0xFFFF, sum = 0
8949 01:15:33.720409 4, 0xFFFF, sum = 0
8950 01:15:33.720889 5, 0xFFFF, sum = 0
8951 01:15:33.723782 6, 0xFFFF, sum = 0
8952 01:15:33.724302 7, 0xFFFF, sum = 0
8953 01:15:33.727242 8, 0xFFFF, sum = 0
8954 01:15:33.730632 9, 0xFFFF, sum = 0
8955 01:15:33.731147 10, 0xFFFF, sum = 0
8956 01:15:33.733811 11, 0xFFFF, sum = 0
8957 01:15:33.734331 12, 0xFFFF, sum = 0
8958 01:15:33.737221 13, 0x8FFF, sum = 0
8959 01:15:33.737761 14, 0x0, sum = 1
8960 01:15:33.740528 15, 0x0, sum = 2
8961 01:15:33.740952 16, 0x0, sum = 3
8962 01:15:33.744199 17, 0x0, sum = 4
8963 01:15:33.744723 best_step = 15
8964 01:15:33.745058
8965 01:15:33.745368 ==
8966 01:15:33.747030 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 01:15:33.750360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 01:15:33.750784 ==
8969 01:15:33.754027 RX Vref Scan: 0
8970 01:15:33.754539
8971 01:15:33.757077 RX Vref 0 -> 0, step: 1
8972 01:15:33.757630
8973 01:15:33.757974 RX Delay 11 -> 252, step: 4
8974 01:15:33.764387 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8975 01:15:33.767152 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8976 01:15:33.770553 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8977 01:15:33.774353 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8978 01:15:33.777479 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8979 01:15:33.784127 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8980 01:15:33.787627 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8981 01:15:33.790883 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8982 01:15:33.794128 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8983 01:15:33.796984 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
8984 01:15:33.803700 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8985 01:15:33.807281 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8986 01:15:33.810287 iDelay=195, Bit 12, Center 134 (79 ~ 190) 112
8987 01:15:33.813481 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8988 01:15:33.820635 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8989 01:15:33.823677 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8990 01:15:33.824099 ==
8991 01:15:33.827126 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 01:15:33.829931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 01:15:33.830404 ==
8994 01:15:33.833408 DQS Delay:
8995 01:15:33.833908 DQS0 = 0, DQS1 = 0
8996 01:15:33.834245 DQM Delay:
8997 01:15:33.836816 DQM0 = 130, DQM1 = 125
8998 01:15:33.837338 DQ Delay:
8999 01:15:33.840199 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =128
9000 01:15:33.843303 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =126
9001 01:15:33.847233 DQ8 =108, DQ9 =114, DQ10 =128, DQ11 =120
9002 01:15:33.853746 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =136
9003 01:15:33.854319
9004 01:15:33.854757
9005 01:15:33.855172
9006 01:15:33.856689 [DramC_TX_OE_Calibration] TA2
9007 01:15:33.860162 Original DQ_B0 (3 6) =30, OEN = 27
9008 01:15:33.860796 Original DQ_B1 (3 6) =30, OEN = 27
9009 01:15:33.863496 24, 0x0, End_B0=24 End_B1=24
9010 01:15:33.866355 25, 0x0, End_B0=25 End_B1=25
9011 01:15:33.869664 26, 0x0, End_B0=26 End_B1=26
9012 01:15:33.873639 27, 0x0, End_B0=27 End_B1=27
9013 01:15:33.874062 28, 0x0, End_B0=28 End_B1=28
9014 01:15:33.876471 29, 0x0, End_B0=29 End_B1=29
9015 01:15:33.879987 30, 0x0, End_B0=30 End_B1=30
9016 01:15:33.882804 31, 0x4545, End_B0=30 End_B1=30
9017 01:15:33.886188 Byte0 end_step=30 best_step=27
9018 01:15:33.889656 Byte1 end_step=30 best_step=27
9019 01:15:33.890085 Byte0 TX OE(2T, 0.5T) = (3, 3)
9020 01:15:33.893301 Byte1 TX OE(2T, 0.5T) = (3, 3)
9021 01:15:33.893885
9022 01:15:33.894324
9023 01:15:33.902857 [DQSOSCAuto] RK1, (LSB)MR18= 0xe19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
9024 01:15:33.906083 CH1 RK1: MR19=303, MR18=E19
9025 01:15:33.909177 CH1_RK1: MR19=0x303, MR18=0xE19, DQSOSC=397, MR23=63, INC=23, DEC=15
9026 01:15:33.912762 [RxdqsGatingPostProcess] freq 1600
9027 01:15:33.919753 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9028 01:15:33.922541 best DQS0 dly(2T, 0.5T) = (1, 1)
9029 01:15:33.925921 best DQS1 dly(2T, 0.5T) = (1, 1)
9030 01:15:33.929293 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9031 01:15:33.932721 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9032 01:15:33.935968 best DQS0 dly(2T, 0.5T) = (1, 1)
9033 01:15:33.936560 best DQS1 dly(2T, 0.5T) = (1, 1)
9034 01:15:33.938982 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9035 01:15:33.942578 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9036 01:15:33.945912 Pre-setting of DQS Precalculation
9037 01:15:33.952263 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9038 01:15:33.959018 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9039 01:15:33.965790 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9040 01:15:33.966358
9041 01:15:33.966836
9042 01:15:33.968971 [Calibration Summary] 3200 Mbps
9043 01:15:33.969445 CH 0, Rank 0
9044 01:15:33.972525 SW Impedance : PASS
9045 01:15:33.976001 DUTY Scan : NO K
9046 01:15:33.976550 ZQ Calibration : PASS
9047 01:15:33.978946 Jitter Meter : NO K
9048 01:15:33.982201 CBT Training : PASS
9049 01:15:33.982663 Write leveling : PASS
9050 01:15:33.985937 RX DQS gating : PASS
9051 01:15:33.989443 RX DQ/DQS(RDDQC) : PASS
9052 01:15:33.990054 TX DQ/DQS : PASS
9053 01:15:33.992454 RX DATLAT : PASS
9054 01:15:33.995982 RX DQ/DQS(Engine): PASS
9055 01:15:33.996532 TX OE : PASS
9056 01:15:33.999062 All Pass.
9057 01:15:33.999614
9058 01:15:33.999981 CH 0, Rank 1
9059 01:15:34.002077 SW Impedance : PASS
9060 01:15:34.002675 DUTY Scan : NO K
9061 01:15:34.005923 ZQ Calibration : PASS
9062 01:15:34.009324 Jitter Meter : NO K
9063 01:15:34.009921 CBT Training : PASS
9064 01:15:34.011979 Write leveling : PASS
9065 01:15:34.012439 RX DQS gating : PASS
9066 01:15:34.015574 RX DQ/DQS(RDDQC) : PASS
9067 01:15:34.019344 TX DQ/DQS : PASS
9068 01:15:34.019809 RX DATLAT : PASS
9069 01:15:34.021865 RX DQ/DQS(Engine): PASS
9070 01:15:34.026104 TX OE : PASS
9071 01:15:34.026660 All Pass.
9072 01:15:34.027023
9073 01:15:34.027368 CH 1, Rank 0
9074 01:15:34.028619 SW Impedance : PASS
9075 01:15:34.032283 DUTY Scan : NO K
9076 01:15:34.032836 ZQ Calibration : PASS
9077 01:15:34.035882 Jitter Meter : NO K
9078 01:15:34.038456 CBT Training : PASS
9079 01:15:34.038917 Write leveling : PASS
9080 01:15:34.041803 RX DQS gating : PASS
9081 01:15:34.045867 RX DQ/DQS(RDDQC) : PASS
9082 01:15:34.046416 TX DQ/DQS : PASS
9083 01:15:34.048981 RX DATLAT : PASS
9084 01:15:34.051616 RX DQ/DQS(Engine): PASS
9085 01:15:34.052076 TX OE : PASS
9086 01:15:34.055291 All Pass.
9087 01:15:34.055712
9088 01:15:34.056087 CH 1, Rank 1
9089 01:15:34.058762 SW Impedance : PASS
9090 01:15:34.059286 DUTY Scan : NO K
9091 01:15:34.062161 ZQ Calibration : PASS
9092 01:15:34.065276 Jitter Meter : NO K
9093 01:15:34.065931 CBT Training : PASS
9094 01:15:34.068923 Write leveling : PASS
9095 01:15:34.069433 RX DQS gating : PASS
9096 01:15:34.071897 RX DQ/DQS(RDDQC) : PASS
9097 01:15:34.075751 TX DQ/DQS : PASS
9098 01:15:34.076269 RX DATLAT : PASS
9099 01:15:34.078878 RX DQ/DQS(Engine): PASS
9100 01:15:34.082041 TX OE : PASS
9101 01:15:34.082460 All Pass.
9102 01:15:34.082828
9103 01:15:34.085108 DramC Write-DBI on
9104 01:15:34.085564 PER_BANK_REFRESH: Hybrid Mode
9105 01:15:34.088674 TX_TRACKING: ON
9106 01:15:34.098916 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9107 01:15:34.105231 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9108 01:15:34.111908 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9109 01:15:34.115033 [FAST_K] Save calibration result to emmc
9110 01:15:34.118385 sync common calibartion params.
9111 01:15:34.121858 sync cbt_mode0:1, 1:1
9112 01:15:34.122373 dram_init: ddr_geometry: 2
9113 01:15:34.124952 dram_init: ddr_geometry: 2
9114 01:15:34.128461 dram_init: ddr_geometry: 2
9115 01:15:34.131679 0:dram_rank_size:100000000
9116 01:15:34.132212 1:dram_rank_size:100000000
9117 01:15:34.138276 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9118 01:15:34.141828 DFS_SHUFFLE_HW_MODE: ON
9119 01:15:34.144480 dramc_set_vcore_voltage set vcore to 725000
9120 01:15:34.147873 Read voltage for 1600, 0
9121 01:15:34.148388 Vio18 = 0
9122 01:15:34.148723 Vcore = 725000
9123 01:15:34.151537 Vdram = 0
9124 01:15:34.152048 Vddq = 0
9125 01:15:34.152381 Vmddr = 0
9126 01:15:34.154271 switch to 3200 Mbps bootup
9127 01:15:34.154689 [DramcRunTimeConfig]
9128 01:15:34.158255 PHYPLL
9129 01:15:34.158759 DPM_CONTROL_AFTERK: ON
9130 01:15:34.161224 PER_BANK_REFRESH: ON
9131 01:15:34.164205 REFRESH_OVERHEAD_REDUCTION: ON
9132 01:15:34.164715 CMD_PICG_NEW_MODE: OFF
9133 01:15:34.167410 XRTWTW_NEW_MODE: ON
9134 01:15:34.167823 XRTRTR_NEW_MODE: ON
9135 01:15:34.170643 TX_TRACKING: ON
9136 01:15:34.171059 RDSEL_TRACKING: OFF
9137 01:15:34.174894 DQS Precalculation for DVFS: ON
9138 01:15:34.177831 RX_TRACKING: OFF
9139 01:15:34.178341 HW_GATING DBG: ON
9140 01:15:34.181195 ZQCS_ENABLE_LP4: ON
9141 01:15:34.181797 RX_PICG_NEW_MODE: ON
9142 01:15:34.184211 TX_PICG_NEW_MODE: ON
9143 01:15:34.187761 ENABLE_RX_DCM_DPHY: ON
9144 01:15:34.188312 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9145 01:15:34.190935 DUMMY_READ_FOR_TRACKING: OFF
9146 01:15:34.193839 !!! SPM_CONTROL_AFTERK: OFF
9147 01:15:34.197469 !!! SPM could not control APHY
9148 01:15:34.200700 IMPEDANCE_TRACKING: ON
9149 01:15:34.201251 TEMP_SENSOR: ON
9150 01:15:34.204283 HW_SAVE_FOR_SR: OFF
9151 01:15:34.204738 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9152 01:15:34.211022 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9153 01:15:34.211598 Read ODT Tracking: ON
9154 01:15:34.213912 Refresh Rate DeBounce: ON
9155 01:15:34.214384 DFS_NO_QUEUE_FLUSH: ON
9156 01:15:34.217105 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9157 01:15:34.220419 ENABLE_DFS_RUNTIME_MRW: OFF
9158 01:15:34.224127 DDR_RESERVE_NEW_MODE: ON
9159 01:15:34.224675 MR_CBT_SWITCH_FREQ: ON
9160 01:15:34.227506 =========================
9161 01:15:34.246541 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9162 01:15:34.250200 dram_init: ddr_geometry: 2
9163 01:15:34.268096 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9164 01:15:34.271421 dram_init: dram init end (result: 0)
9165 01:15:34.277963 DRAM-K: Full calibration passed in 24574 msecs
9166 01:15:34.281417 MRC: failed to locate region type 0.
9167 01:15:34.281934 DRAM rank0 size:0x100000000,
9168 01:15:34.284195 DRAM rank1 size=0x100000000
9169 01:15:34.294445 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9170 01:15:34.300883 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9171 01:15:34.307505 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9172 01:15:34.317560 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9173 01:15:34.318156 DRAM rank0 size:0x100000000,
9174 01:15:34.320461 DRAM rank1 size=0x100000000
9175 01:15:34.320920 CBMEM:
9176 01:15:34.324437 IMD: root @ 0xfffff000 254 entries.
9177 01:15:34.327776 IMD: root @ 0xffffec00 62 entries.
9178 01:15:34.330935 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9179 01:15:34.337485 WARNING: RO_VPD is uninitialized or empty.
9180 01:15:34.340576 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9181 01:15:34.348051 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9182 01:15:34.361142 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9183 01:15:34.372384 BS: romstage times (exec / console): total (unknown) / 24040 ms
9184 01:15:34.372939
9185 01:15:34.373304
9186 01:15:34.382053 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9187 01:15:34.385436 ARM64: Exception handlers installed.
9188 01:15:34.388983 ARM64: Testing exception
9189 01:15:34.392439 ARM64: Done test exception
9190 01:15:34.393025 Enumerating buses...
9191 01:15:34.395451 Show all devs... Before device enumeration.
9192 01:15:34.398754 Root Device: enabled 1
9193 01:15:34.402242 CPU_CLUSTER: 0: enabled 1
9194 01:15:34.402706 CPU: 00: enabled 1
9195 01:15:34.405885 Compare with tree...
9196 01:15:34.406440 Root Device: enabled 1
9197 01:15:34.409185 CPU_CLUSTER: 0: enabled 1
9198 01:15:34.412135 CPU: 00: enabled 1
9199 01:15:34.412683 Root Device scanning...
9200 01:15:34.415364 scan_static_bus for Root Device
9201 01:15:34.418900 CPU_CLUSTER: 0 enabled
9202 01:15:34.422214 scan_static_bus for Root Device done
9203 01:15:34.425406 scan_bus: bus Root Device finished in 8 msecs
9204 01:15:34.425918 done
9205 01:15:34.432029 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9206 01:15:34.435405 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9207 01:15:34.442070 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9208 01:15:34.445184 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9209 01:15:34.449091 Allocating resources...
9210 01:15:34.451511 Reading resources...
9211 01:15:34.455419 Root Device read_resources bus 0 link: 0
9212 01:15:34.455975 DRAM rank0 size:0x100000000,
9213 01:15:34.458306 DRAM rank1 size=0x100000000
9214 01:15:34.461576 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9215 01:15:34.465434 CPU: 00 missing read_resources
9216 01:15:34.471813 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9217 01:15:34.475064 Root Device read_resources bus 0 link: 0 done
9218 01:15:34.475576 Done reading resources.
9219 01:15:34.481538 Show resources in subtree (Root Device)...After reading.
9220 01:15:34.484971 Root Device child on link 0 CPU_CLUSTER: 0
9221 01:15:34.488393 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 01:15:34.497731 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 01:15:34.498261 CPU: 00
9224 01:15:34.501635 Root Device assign_resources, bus 0 link: 0
9225 01:15:34.504441 CPU_CLUSTER: 0 missing set_resources
9226 01:15:34.511191 Root Device assign_resources, bus 0 link: 0 done
9227 01:15:34.511772 Done setting resources.
9228 01:15:34.517874 Show resources in subtree (Root Device)...After assigning values.
9229 01:15:34.521060 Root Device child on link 0 CPU_CLUSTER: 0
9230 01:15:34.524578 CPU_CLUSTER: 0 child on link 0 CPU: 00
9231 01:15:34.534463 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9232 01:15:34.535026 CPU: 00
9233 01:15:34.537692 Done allocating resources.
9234 01:15:34.544197 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9235 01:15:34.544727 Enabling resources...
9236 01:15:34.545213 done.
9237 01:15:34.550526 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9238 01:15:34.551089 Initializing devices...
9239 01:15:34.553947 Root Device init
9240 01:15:34.557503 init hardware done!
9241 01:15:34.558046 0x00000018: ctrlr->caps
9242 01:15:34.560887 52.000 MHz: ctrlr->f_max
9243 01:15:34.563718 0.400 MHz: ctrlr->f_min
9244 01:15:34.564159 0x40ff8080: ctrlr->voltages
9245 01:15:34.567129 sclk: 390625
9246 01:15:34.567585 Bus Width = 1
9247 01:15:34.567917 sclk: 390625
9248 01:15:34.570846 Bus Width = 1
9249 01:15:34.571355 Early init status = 3
9250 01:15:34.577416 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9251 01:15:34.580919 in-header: 03 fc 00 00 01 00 00 00
9252 01:15:34.584301 in-data: 00
9253 01:15:34.586918 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9254 01:15:34.593023 in-header: 03 fd 00 00 00 00 00 00
9255 01:15:34.596469 in-data:
9256 01:15:34.599440 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9257 01:15:34.604027 in-header: 03 fc 00 00 01 00 00 00
9258 01:15:34.607513 in-data: 00
9259 01:15:34.610772 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9260 01:15:34.616052 in-header: 03 fd 00 00 00 00 00 00
9261 01:15:34.619006 in-data:
9262 01:15:34.622482 [SSUSB] Setting up USB HOST controller...
9263 01:15:34.625953 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9264 01:15:34.629074 [SSUSB] phy power-on done.
9265 01:15:34.632803 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9266 01:15:34.639466 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9267 01:15:34.642781 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9268 01:15:34.649259 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9269 01:15:34.655621 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9270 01:15:34.662276 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9271 01:15:34.668636 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9272 01:15:34.675471 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9273 01:15:34.678717 SPM: binary array size = 0x9dc
9274 01:15:34.682295 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9275 01:15:34.688741 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9276 01:15:34.695558 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9277 01:15:34.702047 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9278 01:15:34.704652 configure_display: Starting display init
9279 01:15:34.739087 anx7625_power_on_init: Init interface.
9280 01:15:34.742084 anx7625_disable_pd_protocol: Disabled PD feature.
9281 01:15:34.746098 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9282 01:15:34.773719 anx7625_start_dp_work: Secure OCM version=00
9283 01:15:34.776958 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9284 01:15:34.791804 sp_tx_get_edid_block: EDID Block = 1
9285 01:15:34.894707 Extracted contents:
9286 01:15:34.897506 header: 00 ff ff ff ff ff ff 00
9287 01:15:34.901207 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9288 01:15:34.903732 version: 01 04
9289 01:15:34.907253 basic params: 95 1f 11 78 0a
9290 01:15:34.910940 chroma info: 76 90 94 55 54 90 27 21 50 54
9291 01:15:34.913926 established: 00 00 00
9292 01:15:34.920418 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9293 01:15:34.926736 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9294 01:15:34.929985 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9295 01:15:34.936405 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9296 01:15:34.944034 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9297 01:15:34.946976 extensions: 00
9298 01:15:34.947607 checksum: fb
9299 01:15:34.947900
9300 01:15:34.953477 Manufacturer: IVO Model 57d Serial Number 0
9301 01:15:34.953869 Made week 0 of 2020
9302 01:15:34.956337 EDID version: 1.4
9303 01:15:34.956753 Digital display
9304 01:15:34.959693 6 bits per primary color channel
9305 01:15:34.963429 DisplayPort interface
9306 01:15:34.963843 Maximum image size: 31 cm x 17 cm
9307 01:15:34.966442 Gamma: 220%
9308 01:15:34.966907 Check DPMS levels
9309 01:15:34.973308 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9310 01:15:34.976697 First detailed timing is preferred timing
9311 01:15:34.977114 Established timings supported:
9312 01:15:34.979984 Standard timings supported:
9313 01:15:34.983148 Detailed timings
9314 01:15:34.986129 Hex of detail: 383680a07038204018303c0035ae10000019
9315 01:15:34.993038 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9316 01:15:34.996197 0780 0798 07c8 0820 hborder 0
9317 01:15:35.000214 0438 043b 0447 0458 vborder 0
9318 01:15:35.003085 -hsync -vsync
9319 01:15:35.003504 Did detailed timing
9320 01:15:35.009469 Hex of detail: 000000000000000000000000000000000000
9321 01:15:35.012765 Manufacturer-specified data, tag 0
9322 01:15:35.015859 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9323 01:15:35.019388 ASCII string: InfoVision
9324 01:15:35.023046 Hex of detail: 000000fe00523134304e574635205248200a
9325 01:15:35.026210 ASCII string: R140NWF5 RH
9326 01:15:35.026626 Checksum
9327 01:15:35.028918 Checksum: 0xfb (valid)
9328 01:15:35.032417 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9329 01:15:35.035739 DSI data_rate: 832800000 bps
9330 01:15:35.042611 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9331 01:15:35.045753 anx7625_parse_edid: pixelclock(138800).
9332 01:15:35.049001 hactive(1920), hsync(48), hfp(24), hbp(88)
9333 01:15:35.052150 vactive(1080), vsync(12), vfp(3), vbp(17)
9334 01:15:35.055517 anx7625_dsi_config: config dsi.
9335 01:15:35.062184 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9336 01:15:35.076451 anx7625_dsi_config: success to config DSI
9337 01:15:35.079674 anx7625_dp_start: MIPI phy setup OK.
9338 01:15:35.082614 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9339 01:15:35.086123 mtk_ddp_mode_set invalid vrefresh 60
9340 01:15:35.089421 main_disp_path_setup
9341 01:15:35.089884 ovl_layer_smi_id_en
9342 01:15:35.093070 ovl_layer_smi_id_en
9343 01:15:35.093635 ccorr_config
9344 01:15:35.093984 aal_config
9345 01:15:35.096165 gamma_config
9346 01:15:35.096580 postmask_config
9347 01:15:35.099367 dither_config
9348 01:15:35.102382 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9349 01:15:35.109044 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9350 01:15:35.112521 Root Device init finished in 555 msecs
9351 01:15:35.116086 CPU_CLUSTER: 0 init
9352 01:15:35.122276 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9353 01:15:35.128637 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9354 01:15:35.129067 APU_MBOX 0x190000b0 = 0x10001
9355 01:15:35.132063 APU_MBOX 0x190001b0 = 0x10001
9356 01:15:35.135680 APU_MBOX 0x190005b0 = 0x10001
9357 01:15:35.138504 APU_MBOX 0x190006b0 = 0x10001
9358 01:15:35.145046 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9359 01:15:35.154653 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9360 01:15:35.167373 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9361 01:15:35.173718 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9362 01:15:35.185678 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9363 01:15:35.195231 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9364 01:15:35.197860 CPU_CLUSTER: 0 init finished in 81 msecs
9365 01:15:35.201858 Devices initialized
9366 01:15:35.204444 Show all devs... After init.
9367 01:15:35.204725 Root Device: enabled 1
9368 01:15:35.208073 CPU_CLUSTER: 0: enabled 1
9369 01:15:35.211417 CPU: 00: enabled 1
9370 01:15:35.215254 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9371 01:15:35.218199 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9372 01:15:35.221679 ELOG: NV offset 0x57f000 size 0x1000
9373 01:15:35.228220 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9374 01:15:35.234675 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9375 01:15:35.238490 ELOG: Event(17) added with size 13 at 2024-04-23 01:15:35 UTC
9376 01:15:35.244552 out: cmd=0x121: 03 db 21 01 00 00 00 00
9377 01:15:35.248081 in-header: 03 55 00 00 2c 00 00 00
9378 01:15:35.258140 in-data: 09 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9379 01:15:35.264289 ELOG: Event(A1) added with size 10 at 2024-04-23 01:15:35 UTC
9380 01:15:35.270991 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9381 01:15:35.277894 ELOG: Event(A0) added with size 9 at 2024-04-23 01:15:35 UTC
9382 01:15:35.281550 elog_add_boot_reason: Logged dev mode boot
9383 01:15:35.284510 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9384 01:15:35.287887 Finalize devices...
9385 01:15:35.291435 Devices finalized
9386 01:15:35.294367 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9387 01:15:35.297558 Writing coreboot table at 0xffe64000
9388 01:15:35.301152 0. 000000000010a000-0000000000113fff: RAMSTAGE
9389 01:15:35.304528 1. 0000000040000000-00000000400fffff: RAM
9390 01:15:35.311419 2. 0000000040100000-000000004032afff: RAMSTAGE
9391 01:15:35.314338 3. 000000004032b000-00000000545fffff: RAM
9392 01:15:35.317731 4. 0000000054600000-000000005465ffff: BL31
9393 01:15:35.320760 5. 0000000054660000-00000000ffe63fff: RAM
9394 01:15:35.328094 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9395 01:15:35.330897 7. 0000000100000000-000000023fffffff: RAM
9396 01:15:35.334509 Passing 5 GPIOs to payload:
9397 01:15:35.337667 NAME | PORT | POLARITY | VALUE
9398 01:15:35.341429 EC in RW | 0x000000aa | low | undefined
9399 01:15:35.347694 EC interrupt | 0x00000005 | low | undefined
9400 01:15:35.350898 TPM interrupt | 0x000000ab | high | undefined
9401 01:15:35.357842 SD card detect | 0x00000011 | high | undefined
9402 01:15:35.360602 speaker enable | 0x00000093 | high | undefined
9403 01:15:35.363923 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9404 01:15:35.367764 in-header: 03 f9 00 00 02 00 00 00
9405 01:15:35.370288 in-data: 02 00
9406 01:15:35.370714 ADC[4]: Raw value=894081 ID=7
9407 01:15:35.373647 ADC[3]: Raw value=213070 ID=1
9408 01:15:35.377174 RAM Code: 0x71
9409 01:15:35.377634 ADC[6]: Raw value=74722 ID=0
9410 01:15:35.380905 ADC[5]: Raw value=213070 ID=1
9411 01:15:35.384333 SKU Code: 0x1
9412 01:15:35.387495 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9a05
9413 01:15:35.390245 coreboot table: 964 bytes.
9414 01:15:35.393885 IMD ROOT 0. 0xfffff000 0x00001000
9415 01:15:35.397382 IMD SMALL 1. 0xffffe000 0x00001000
9416 01:15:35.400653 RO MCACHE 2. 0xffffc000 0x00001104
9417 01:15:35.403870 CONSOLE 3. 0xfff7c000 0x00080000
9418 01:15:35.407251 FMAP 4. 0xfff7b000 0x00000452
9419 01:15:35.410546 TIME STAMP 5. 0xfff7a000 0x00000910
9420 01:15:35.413882 VBOOT WORK 6. 0xfff66000 0x00014000
9421 01:15:35.416954 RAMOOPS 7. 0xffe66000 0x00100000
9422 01:15:35.419983 COREBOOT 8. 0xffe64000 0x00002000
9423 01:15:35.424280 IMD small region:
9424 01:15:35.426964 IMD ROOT 0. 0xffffec00 0x00000400
9425 01:15:35.430459 VPD 1. 0xffffeb80 0x0000006c
9426 01:15:35.433159 MMC STATUS 2. 0xffffeb60 0x00000004
9427 01:15:35.437014 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9428 01:15:35.440259 Probing TPM: done!
9429 01:15:35.443816 Connected to device vid:did:rid of 1ae0:0028:00
9430 01:15:35.454157 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9431 01:15:35.457304 Initialized TPM device CR50 revision 0
9432 01:15:35.461341 Checking cr50 for pending updates
9433 01:15:35.464991 Reading cr50 TPM mode
9434 01:15:35.473690 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9435 01:15:35.480047 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9436 01:15:35.520630 read SPI 0x3990ec 0x4f1b0: 34861 us, 9294 KB/s, 74.352 Mbps
9437 01:15:35.523524 Checking segment from ROM address 0x40100000
9438 01:15:35.526546 Checking segment from ROM address 0x4010001c
9439 01:15:35.533092 Loading segment from ROM address 0x40100000
9440 01:15:35.533530 code (compression=0)
9441 01:15:35.543614 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9442 01:15:35.550047 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9443 01:15:35.550568 it's not compressed!
9444 01:15:35.557281 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9445 01:15:35.560103 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9446 01:15:35.580842 Loading segment from ROM address 0x4010001c
9447 01:15:35.581353 Entry Point 0x80000000
9448 01:15:35.583881 Loaded segments
9449 01:15:35.587293 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9450 01:15:35.593796 Jumping to boot code at 0x80000000(0xffe64000)
9451 01:15:35.600638 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9452 01:15:35.607021 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9453 01:15:35.615071 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9454 01:15:35.618115 Checking segment from ROM address 0x40100000
9455 01:15:35.621859 Checking segment from ROM address 0x4010001c
9456 01:15:35.628343 Loading segment from ROM address 0x40100000
9457 01:15:35.628860 code (compression=1)
9458 01:15:35.634897 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9459 01:15:35.644350 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9460 01:15:35.644898 using LZMA
9461 01:15:35.653427 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9462 01:15:35.660370 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9463 01:15:35.663002 Loading segment from ROM address 0x4010001c
9464 01:15:35.663419 Entry Point 0x54601000
9465 01:15:35.666656 Loaded segments
9466 01:15:35.669612 NOTICE: MT8192 bl31_setup
9467 01:15:35.677123 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9468 01:15:35.680584 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9469 01:15:35.683966 WARNING: region 0:
9470 01:15:35.686981 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 01:15:35.687498 WARNING: region 1:
9472 01:15:35.693750 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9473 01:15:35.696764 WARNING: region 2:
9474 01:15:35.700489 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9475 01:15:35.703908 WARNING: region 3:
9476 01:15:35.707176 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 01:15:35.710204 WARNING: region 4:
9478 01:15:35.716728 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 01:15:35.717249 WARNING: region 5:
9480 01:15:35.720523 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 01:15:35.723444 WARNING: region 6:
9482 01:15:35.726792 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 01:15:35.730487 WARNING: region 7:
9484 01:15:35.733249 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 01:15:35.740232 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9486 01:15:35.743710 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9487 01:15:35.746930 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9488 01:15:35.753397 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9489 01:15:35.756532 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9490 01:15:35.760473 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9491 01:15:35.766570 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9492 01:15:35.770461 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9493 01:15:35.776485 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9494 01:15:35.779999 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9495 01:15:35.783336 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9496 01:15:35.789814 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9497 01:15:35.793285 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9498 01:15:35.796549 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9499 01:15:35.803241 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9500 01:15:35.806520 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9501 01:15:35.813359 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9502 01:15:35.816145 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9503 01:15:35.819830 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9504 01:15:35.826381 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9505 01:15:35.829900 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9506 01:15:35.833241 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9507 01:15:35.839967 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9508 01:15:35.843255 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9509 01:15:35.849889 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9510 01:15:35.852909 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9511 01:15:35.860033 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9512 01:15:35.863149 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9513 01:15:35.866241 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9514 01:15:35.872778 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9515 01:15:35.876461 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9516 01:15:35.879861 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9517 01:15:35.886055 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9518 01:15:35.889387 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9519 01:15:35.893035 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9520 01:15:35.896116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9521 01:15:35.903339 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9522 01:15:35.906202 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9523 01:15:35.909630 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9524 01:15:35.913092 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9525 01:15:35.919913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9526 01:15:35.922734 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9527 01:15:35.925857 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9528 01:15:35.929207 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9529 01:15:35.936718 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9530 01:15:35.939462 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9531 01:15:35.942927 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9532 01:15:35.949739 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9533 01:15:35.952932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9534 01:15:35.956301 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9535 01:15:35.962836 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9536 01:15:35.966297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9537 01:15:35.972663 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9538 01:15:35.976030 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9539 01:15:35.983257 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9540 01:15:35.985910 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9541 01:15:35.989548 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9542 01:15:35.995880 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9543 01:15:35.999323 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9544 01:15:36.005619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9545 01:15:36.008814 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9546 01:15:36.016187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9547 01:15:36.018871 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9548 01:15:36.025232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9549 01:15:36.028982 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9550 01:15:36.032061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9551 01:15:36.039019 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9552 01:15:36.042398 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9553 01:15:36.048663 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9554 01:15:36.052078 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9555 01:15:36.058693 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9556 01:15:36.062481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9557 01:15:36.065630 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9558 01:15:36.071976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9559 01:15:36.075223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9560 01:15:36.082412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9561 01:15:36.085389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9562 01:15:36.091992 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9563 01:15:36.095871 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9564 01:15:36.102681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9565 01:15:36.105432 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9566 01:15:36.108989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9567 01:15:36.115419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9568 01:15:36.118552 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9569 01:15:36.125748 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9570 01:15:36.128507 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9571 01:15:36.135342 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9572 01:15:36.139062 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9573 01:15:36.142224 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9574 01:15:36.148410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9575 01:15:36.152066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9576 01:15:36.158965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9577 01:15:36.161793 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9578 01:15:36.168166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9579 01:15:36.172183 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9580 01:15:36.178897 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9581 01:15:36.182471 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9582 01:15:36.185257 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9583 01:15:36.188832 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9584 01:15:36.195655 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9585 01:15:36.198192 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9586 01:15:36.201807 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9587 01:15:36.208099 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9588 01:15:36.211795 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9589 01:15:36.214766 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9590 01:15:36.221801 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9591 01:15:36.225104 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9592 01:15:36.231719 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9593 01:15:36.234689 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9594 01:15:36.238116 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9595 01:15:36.245267 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9596 01:15:36.248363 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9597 01:15:36.254807 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9598 01:15:36.258070 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9599 01:15:36.261793 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9600 01:15:36.268094 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9601 01:15:36.271259 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9602 01:15:36.274833 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9603 01:15:36.281357 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9604 01:15:36.284510 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9605 01:15:36.288134 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9606 01:15:36.292093 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9607 01:15:36.298378 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9608 01:15:36.301448 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9609 01:15:36.304992 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9610 01:15:36.311682 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9611 01:15:36.314748 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9612 01:15:36.318098 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9613 01:15:36.324592 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9614 01:15:36.328096 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9615 01:15:36.334990 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9616 01:15:36.338161 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9617 01:15:36.341831 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9618 01:15:36.348318 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9619 01:15:36.352030 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9620 01:15:36.358193 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9621 01:15:36.361730 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9622 01:15:36.365142 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9623 01:15:36.371469 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9624 01:15:36.375029 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9625 01:15:36.378206 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9626 01:15:36.384671 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9627 01:15:36.388402 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9628 01:15:36.394599 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9629 01:15:36.397699 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9630 01:15:36.401293 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9631 01:15:36.407712 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9632 01:15:36.411299 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9633 01:15:36.418018 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9634 01:15:36.421268 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9635 01:15:36.424404 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9636 01:15:36.431438 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9637 01:15:36.434747 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9638 01:15:36.441006 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9639 01:15:36.444632 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9640 01:15:36.448146 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9641 01:15:36.454745 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9642 01:15:36.458286 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9643 01:15:36.461764 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9644 01:15:36.468117 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9645 01:15:36.471679 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9646 01:15:36.477733 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9647 01:15:36.481259 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9648 01:15:36.484804 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9649 01:15:36.491245 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9650 01:15:36.494346 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9651 01:15:36.501245 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9652 01:15:36.504575 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9653 01:15:36.507772 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9654 01:15:36.514180 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9655 01:15:36.517983 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9656 01:15:36.524081 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9657 01:15:36.527207 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9658 01:15:36.530985 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9659 01:15:36.537372 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9660 01:15:36.541013 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9661 01:15:36.547101 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9662 01:15:36.550601 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9663 01:15:36.556819 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9664 01:15:36.560357 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9665 01:15:36.563821 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9666 01:15:36.570360 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9667 01:15:36.573642 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9668 01:15:36.576388 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9669 01:15:36.583435 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9670 01:15:36.586598 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9671 01:15:36.593530 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9672 01:15:36.596521 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9673 01:15:36.600018 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9674 01:15:36.606866 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9675 01:15:36.609470 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9676 01:15:36.616428 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9677 01:15:36.619226 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9678 01:15:36.625744 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9679 01:15:36.629575 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9680 01:15:36.635769 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9681 01:15:36.639291 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9682 01:15:36.642200 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9683 01:15:36.649528 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9684 01:15:36.652481 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9685 01:15:36.658982 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9686 01:15:36.662370 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9687 01:15:36.668737 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9688 01:15:36.672624 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9689 01:15:36.675579 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9690 01:15:36.682013 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9691 01:15:36.685379 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9692 01:15:36.692384 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9693 01:15:36.695202 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9694 01:15:36.698362 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9695 01:15:36.705615 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9696 01:15:36.709039 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9697 01:15:36.715368 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9698 01:15:36.718471 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9699 01:15:36.725263 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9700 01:15:36.728718 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9701 01:15:36.732289 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9702 01:15:36.738722 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9703 01:15:36.741541 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9704 01:15:36.748290 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9705 01:15:36.751398 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9706 01:15:36.758367 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9707 01:15:36.761681 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9708 01:15:36.765189 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9709 01:15:36.771667 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9710 01:15:36.774434 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9711 01:15:36.781669 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9712 01:15:36.784474 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9713 01:15:36.791122 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9714 01:15:36.794502 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9715 01:15:36.797627 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9716 01:15:36.801171 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9717 01:15:36.804698 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9718 01:15:36.811427 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9719 01:15:36.814597 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9720 01:15:36.817731 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9721 01:15:36.823706 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9722 01:15:36.827130 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9723 01:15:36.833896 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9724 01:15:36.837333 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9725 01:15:36.840430 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9726 01:15:36.847334 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9727 01:15:36.850250 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9728 01:15:36.853707 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9729 01:15:36.860390 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9730 01:15:36.864021 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9731 01:15:36.870469 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9732 01:15:36.873887 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9733 01:15:36.876609 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9734 01:15:36.883188 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9735 01:15:36.886744 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9736 01:15:36.893108 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9737 01:15:36.896229 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9738 01:15:36.899868 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9739 01:15:36.906749 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9740 01:15:36.910005 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9741 01:15:36.913115 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9742 01:15:36.920005 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9743 01:15:36.922763 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9744 01:15:36.926591 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9745 01:15:36.933299 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9746 01:15:36.936368 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9747 01:15:36.942933 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9748 01:15:36.946425 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9749 01:15:36.949330 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9750 01:15:36.956360 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9751 01:15:36.959243 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9752 01:15:36.962856 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9753 01:15:36.969315 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9754 01:15:36.972826 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9755 01:15:36.975895 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9756 01:15:36.979315 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9757 01:15:36.985892 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9758 01:15:36.989225 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9759 01:15:36.993291 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9760 01:15:36.996035 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9761 01:15:37.002941 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9762 01:15:37.006218 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9763 01:15:37.009334 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9764 01:15:37.012716 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9765 01:15:37.019736 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9766 01:15:37.022431 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9767 01:15:37.026135 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9768 01:15:37.032574 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9769 01:15:37.035646 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9770 01:15:37.042971 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9771 01:15:37.045790 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9772 01:15:37.048938 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9773 01:15:37.055779 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9774 01:15:37.058843 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9775 01:15:37.065709 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9776 01:15:37.068921 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9777 01:15:37.075729 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9778 01:15:37.078605 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9779 01:15:37.081815 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9780 01:15:37.088851 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9781 01:15:37.092367 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9782 01:15:37.098447 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9783 01:15:37.101916 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9784 01:15:37.105607 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9785 01:15:37.111916 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9786 01:15:37.115293 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9787 01:15:37.121963 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9788 01:15:37.124724 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9789 01:15:37.131642 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9790 01:15:37.135309 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9791 01:15:37.138839 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9792 01:15:37.145121 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9793 01:15:37.147923 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9794 01:15:37.154751 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9795 01:15:37.158264 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9796 01:15:37.161692 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9797 01:15:37.168575 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9798 01:15:37.171420 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9799 01:15:37.178181 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9800 01:15:37.181218 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9801 01:15:37.184901 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9802 01:15:37.191067 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9803 01:15:37.194628 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9804 01:15:37.201319 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9805 01:15:37.204222 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9806 01:15:37.207986 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9807 01:15:37.214023 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9808 01:15:37.217902 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9809 01:15:37.223749 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9810 01:15:37.227380 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9811 01:15:37.234060 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9812 01:15:37.237438 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9813 01:15:37.244487 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9814 01:15:37.247559 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9815 01:15:37.250450 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9816 01:15:37.256804 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9817 01:15:37.260169 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9818 01:15:37.266862 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9819 01:15:37.270123 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9820 01:15:37.273488 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9821 01:15:37.280473 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9822 01:15:37.283494 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9823 01:15:37.290225 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9824 01:15:37.293942 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9825 01:15:37.297121 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9826 01:15:37.303904 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9827 01:15:37.306952 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9828 01:15:37.313726 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9829 01:15:37.317300 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9830 01:15:37.319968 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9831 01:15:37.326888 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9832 01:15:37.330274 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9833 01:15:37.336531 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9834 01:15:37.340375 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9835 01:15:37.346478 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9836 01:15:37.349615 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9837 01:15:37.352776 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9838 01:15:37.359338 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9839 01:15:37.363040 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9840 01:15:37.369606 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9841 01:15:37.373000 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9842 01:15:37.379519 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9843 01:15:37.383192 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9844 01:15:37.386712 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9845 01:15:37.392897 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9846 01:15:37.396467 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9847 01:15:37.402714 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9848 01:15:37.406254 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9849 01:15:37.412512 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9850 01:15:37.415877 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9851 01:15:37.422297 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9852 01:15:37.426001 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9853 01:15:37.429370 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9854 01:15:37.435707 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9855 01:15:37.439652 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9856 01:15:37.445694 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9857 01:15:37.448866 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9858 01:15:37.455777 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9859 01:15:37.458961 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9860 01:15:37.462690 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9861 01:15:37.468714 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9862 01:15:37.472098 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9863 01:15:37.478530 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9864 01:15:37.482098 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9865 01:15:37.488245 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9866 01:15:37.492041 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9867 01:15:37.498333 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9868 01:15:37.501856 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9869 01:15:37.505457 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9870 01:15:37.511709 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9871 01:15:37.515768 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9872 01:15:37.521958 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9873 01:15:37.525270 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9874 01:15:37.531731 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9875 01:15:37.535457 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9876 01:15:37.541666 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9877 01:15:37.545496 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9878 01:15:37.548434 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9879 01:15:37.555088 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9880 01:15:37.558449 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9881 01:15:37.565348 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9882 01:15:37.568067 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9883 01:15:37.575077 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9884 01:15:37.577896 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9885 01:15:37.581219 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9886 01:15:37.588187 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9887 01:15:37.591126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9888 01:15:37.597735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9889 01:15:37.601244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9890 01:15:37.604604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9891 01:15:37.611629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9892 01:15:37.614562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9893 01:15:37.621369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9894 01:15:37.624163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9895 01:15:37.631235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9896 01:15:37.634043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9897 01:15:37.640924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9898 01:15:37.643825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9899 01:15:37.650881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9900 01:15:37.653781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9901 01:15:37.660267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9902 01:15:37.663788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9903 01:15:37.670184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9904 01:15:37.673494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9905 01:15:37.680492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9906 01:15:37.683841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9907 01:15:37.690141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9908 01:15:37.693487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9909 01:15:37.700451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9910 01:15:37.703172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9911 01:15:37.709540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9912 01:15:37.713019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9913 01:15:37.719844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9914 01:15:37.723275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9915 01:15:37.729726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9916 01:15:37.733036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9917 01:15:37.739700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9918 01:15:37.742801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9919 01:15:37.749660 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9920 01:15:37.749762 INFO: [APUAPC] vio 0
9921 01:15:37.756232 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9922 01:15:37.759528 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9923 01:15:37.763336 INFO: [APUAPC] D0_APC_0: 0x400510
9924 01:15:37.766558 INFO: [APUAPC] D0_APC_1: 0x0
9925 01:15:37.769959 INFO: [APUAPC] D0_APC_2: 0x1540
9926 01:15:37.772818 INFO: [APUAPC] D0_APC_3: 0x0
9927 01:15:37.776245 INFO: [APUAPC] D1_APC_0: 0xffffffff
9928 01:15:37.779735 INFO: [APUAPC] D1_APC_1: 0xffffffff
9929 01:15:37.783197 INFO: [APUAPC] D1_APC_2: 0x3fffff
9930 01:15:37.786075 INFO: [APUAPC] D1_APC_3: 0x0
9931 01:15:37.789249 INFO: [APUAPC] D2_APC_0: 0xffffffff
9932 01:15:37.792804 INFO: [APUAPC] D2_APC_1: 0xffffffff
9933 01:15:37.796166 INFO: [APUAPC] D2_APC_2: 0x3fffff
9934 01:15:37.799728 INFO: [APUAPC] D2_APC_3: 0x0
9935 01:15:37.803154 INFO: [APUAPC] D3_APC_0: 0xffffffff
9936 01:15:37.806042 INFO: [APUAPC] D3_APC_1: 0xffffffff
9937 01:15:37.809547 INFO: [APUAPC] D3_APC_2: 0x3fffff
9938 01:15:37.812420 INFO: [APUAPC] D3_APC_3: 0x0
9939 01:15:37.815891 INFO: [APUAPC] D4_APC_0: 0xffffffff
9940 01:15:37.819341 INFO: [APUAPC] D4_APC_1: 0xffffffff
9941 01:15:37.822516 INFO: [APUAPC] D4_APC_2: 0x3fffff
9942 01:15:37.825696 INFO: [APUAPC] D4_APC_3: 0x0
9943 01:15:37.829169 INFO: [APUAPC] D5_APC_0: 0xffffffff
9944 01:15:37.832738 INFO: [APUAPC] D5_APC_1: 0xffffffff
9945 01:15:37.835615 INFO: [APUAPC] D5_APC_2: 0x3fffff
9946 01:15:37.835702 INFO: [APUAPC] D5_APC_3: 0x0
9947 01:15:37.839134 INFO: [APUAPC] D6_APC_0: 0xffffffff
9948 01:15:37.845847 INFO: [APUAPC] D6_APC_1: 0xffffffff
9949 01:15:37.848922 INFO: [APUAPC] D6_APC_2: 0x3fffff
9950 01:15:37.849006 INFO: [APUAPC] D6_APC_3: 0x0
9951 01:15:37.852304 INFO: [APUAPC] D7_APC_0: 0xffffffff
9952 01:15:37.855494 INFO: [APUAPC] D7_APC_1: 0xffffffff
9953 01:15:37.859144 INFO: [APUAPC] D7_APC_2: 0x3fffff
9954 01:15:37.862272 INFO: [APUAPC] D7_APC_3: 0x0
9955 01:15:37.865875 INFO: [APUAPC] D8_APC_0: 0xffffffff
9956 01:15:37.869250 INFO: [APUAPC] D8_APC_1: 0xffffffff
9957 01:15:37.872159 INFO: [APUAPC] D8_APC_2: 0x3fffff
9958 01:15:37.875398 INFO: [APUAPC] D8_APC_3: 0x0
9959 01:15:37.878716 INFO: [APUAPC] D9_APC_0: 0xffffffff
9960 01:15:37.881987 INFO: [APUAPC] D9_APC_1: 0xffffffff
9961 01:15:37.885247 INFO: [APUAPC] D9_APC_2: 0x3fffff
9962 01:15:37.889032 INFO: [APUAPC] D9_APC_3: 0x0
9963 01:15:37.892276 INFO: [APUAPC] D10_APC_0: 0xffffffff
9964 01:15:37.895135 INFO: [APUAPC] D10_APC_1: 0xffffffff
9965 01:15:37.898549 INFO: [APUAPC] D10_APC_2: 0x3fffff
9966 01:15:37.902057 INFO: [APUAPC] D10_APC_3: 0x0
9967 01:15:37.905492 INFO: [APUAPC] D11_APC_0: 0xffffffff
9968 01:15:37.908442 INFO: [APUAPC] D11_APC_1: 0xffffffff
9969 01:15:37.911978 INFO: [APUAPC] D11_APC_2: 0x3fffff
9970 01:15:37.914919 INFO: [APUAPC] D11_APC_3: 0x0
9971 01:15:37.918513 INFO: [APUAPC] D12_APC_0: 0xffffffff
9972 01:15:37.921975 INFO: [APUAPC] D12_APC_1: 0xffffffff
9973 01:15:37.925339 INFO: [APUAPC] D12_APC_2: 0x3fffff
9974 01:15:37.928327 INFO: [APUAPC] D12_APC_3: 0x0
9975 01:15:37.931615 INFO: [APUAPC] D13_APC_0: 0xffffffff
9976 01:15:37.935213 INFO: [APUAPC] D13_APC_1: 0xffffffff
9977 01:15:37.938418 INFO: [APUAPC] D13_APC_2: 0x3fffff
9978 01:15:37.941394 INFO: [APUAPC] D13_APC_3: 0x0
9979 01:15:37.945087 INFO: [APUAPC] D14_APC_0: 0xffffffff
9980 01:15:37.951363 INFO: [APUAPC] D14_APC_1: 0xffffffff
9981 01:15:37.954973 INFO: [APUAPC] D14_APC_2: 0x3fffff
9982 01:15:37.955059 INFO: [APUAPC] D14_APC_3: 0x0
9983 01:15:37.958331 INFO: [APUAPC] D15_APC_0: 0xffffffff
9984 01:15:37.964952 INFO: [APUAPC] D15_APC_1: 0xffffffff
9985 01:15:37.968150 INFO: [APUAPC] D15_APC_2: 0x3fffff
9986 01:15:37.968247 INFO: [APUAPC] D15_APC_3: 0x0
9987 01:15:37.971129 INFO: [APUAPC] APC_CON: 0x4
9988 01:15:37.974639 INFO: [NOCDAPC] D0_APC_0: 0x0
9989 01:15:37.978058 INFO: [NOCDAPC] D0_APC_1: 0x0
9990 01:15:37.981475 INFO: [NOCDAPC] D1_APC_0: 0x0
9991 01:15:37.984805 INFO: [NOCDAPC] D1_APC_1: 0xfff
9992 01:15:37.987843 INFO: [NOCDAPC] D2_APC_0: 0x0
9993 01:15:37.991470 INFO: [NOCDAPC] D2_APC_1: 0xfff
9994 01:15:37.994668 INFO: [NOCDAPC] D3_APC_0: 0x0
9995 01:15:37.998068 INFO: [NOCDAPC] D3_APC_1: 0xfff
9996 01:15:37.998149 INFO: [NOCDAPC] D4_APC_0: 0x0
9997 01:15:38.000867 INFO: [NOCDAPC] D4_APC_1: 0xfff
9998 01:15:38.004187 INFO: [NOCDAPC] D5_APC_0: 0x0
9999 01:15:38.007561 INFO: [NOCDAPC] D5_APC_1: 0xfff
10000 01:15:38.010842 INFO: [NOCDAPC] D6_APC_0: 0x0
10001 01:15:38.014349 INFO: [NOCDAPC] D6_APC_1: 0xfff
10002 01:15:38.017977 INFO: [NOCDAPC] D7_APC_0: 0x0
10003 01:15:38.021060 INFO: [NOCDAPC] D7_APC_1: 0xfff
10004 01:15:38.024478 INFO: [NOCDAPC] D8_APC_0: 0x0
10005 01:15:38.027452 INFO: [NOCDAPC] D8_APC_1: 0xfff
10006 01:15:38.031417 INFO: [NOCDAPC] D9_APC_0: 0x0
10007 01:15:38.031575 INFO: [NOCDAPC] D9_APC_1: 0xfff
10008 01:15:38.034072 INFO: [NOCDAPC] D10_APC_0: 0x0
10009 01:15:38.037427 INFO: [NOCDAPC] D10_APC_1: 0xfff
10010 01:15:38.040731 INFO: [NOCDAPC] D11_APC_0: 0x0
10011 01:15:38.044293 INFO: [NOCDAPC] D11_APC_1: 0xfff
10012 01:15:38.047479 INFO: [NOCDAPC] D12_APC_0: 0x0
10013 01:15:38.050374 INFO: [NOCDAPC] D12_APC_1: 0xfff
10014 01:15:38.054169 INFO: [NOCDAPC] D13_APC_0: 0x0
10015 01:15:38.057609 INFO: [NOCDAPC] D13_APC_1: 0xfff
10016 01:15:38.060586 INFO: [NOCDAPC] D14_APC_0: 0x0
10017 01:15:38.063871 INFO: [NOCDAPC] D14_APC_1: 0xfff
10018 01:15:38.067546 INFO: [NOCDAPC] D15_APC_0: 0x0
10019 01:15:38.070911 INFO: [NOCDAPC] D15_APC_1: 0xfff
10020 01:15:38.074365 INFO: [NOCDAPC] APC_CON: 0x4
10021 01:15:38.077367 INFO: [APUAPC] set_apusys_apc done
10022 01:15:38.080993 INFO: [DEVAPC] devapc_init done
10023 01:15:38.084175 INFO: GICv3 without legacy support detected.
10024 01:15:38.087732 INFO: ARM GICv3 driver initialized in EL3
10025 01:15:38.091183 INFO: Maximum SPI INTID supported: 639
10026 01:15:38.094106 INFO: BL31: Initializing runtime services
10027 01:15:38.100999 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10028 01:15:38.104571 INFO: SPM: enable CPC mode
10029 01:15:38.107746 INFO: mcdi ready for mcusys-off-idle and system suspend
10030 01:15:38.114081 INFO: BL31: Preparing for EL3 exit to normal world
10031 01:15:38.117595 INFO: Entry point address = 0x80000000
10032 01:15:38.120808 INFO: SPSR = 0x8
10033 01:15:38.125152
10034 01:15:38.125758
10035 01:15:38.126159
10036 01:15:38.128535 Starting depthcharge on Spherion...
10037 01:15:38.129045
10038 01:15:38.129373 Wipe memory regions:
10039 01:15:38.129725
10040 01:15:38.132091 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10041 01:15:38.132587 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10042 01:15:38.132976 Setting prompt string to ['asurada:']
10043 01:15:38.133466 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10044 01:15:38.134154 [0x00000040000000, 0x00000054600000)
10045 01:15:38.253994
10046 01:15:38.254544 [0x00000054660000, 0x00000080000000)
10047 01:15:38.514657
10048 01:15:38.515163 [0x000000821a7280, 0x000000ffe64000)
10049 01:15:39.258709
10050 01:15:39.258848 [0x00000100000000, 0x00000240000000)
10051 01:15:41.149115
10052 01:15:41.152233 Initializing XHCI USB controller at 0x11200000.
10053 01:15:42.190022
10054 01:15:42.193412 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10055 01:15:42.193529
10056 01:15:42.193629
10057 01:15:42.193709
10058 01:15:42.194009 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 01:15:42.294391 asurada: tftpboot 192.168.201.1 13468726/tftp-deploy-o740h9ux/kernel/image.itb 13468726/tftp-deploy-o740h9ux/kernel/cmdline
10061 01:15:42.294622 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 01:15:42.294743 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10063 01:15:42.298887 tftpboot 192.168.201.1 13468726/tftp-deploy-o740h9ux/kernel/image.ittp-deploy-o740h9ux/kernel/cmdline
10064 01:15:42.298978
10065 01:15:42.299062 Waiting for link
10066 01:15:42.459514
10067 01:15:42.459669 R8152: Initializing
10068 01:15:42.459762
10069 01:15:42.462890 Version 6 (ocp_data = 5c30)
10070 01:15:42.462974
10071 01:15:42.465672 R8152: Done initializing
10072 01:15:42.465760
10073 01:15:42.465843 Adding net device
10074 01:15:44.495779
10075 01:15:44.495932 done.
10076 01:15:44.496025
10077 01:15:44.496104 MAC: 00:24:32:30:78:ff
10078 01:15:44.496184
10079 01:15:44.498532 Sending DHCP discover... done.
10080 01:15:44.498614
10081 01:15:48.462372 Waiting for reply... done.
10082 01:15:48.462542
10083 01:15:48.462638 Sending DHCP request... done.
10084 01:15:48.466221
10085 01:15:48.472146 Waiting for reply... done.
10086 01:15:48.472250
10087 01:15:48.472315 My ip is 192.168.201.21
10088 01:15:48.472376
10089 01:15:48.475391 The DHCP server ip is 192.168.201.1
10090 01:15:48.475477
10091 01:15:48.481789 TFTP server IP predefined by user: 192.168.201.1
10092 01:15:48.481884
10093 01:15:48.488411 Bootfile predefined by user: 13468726/tftp-deploy-o740h9ux/kernel/image.itb
10094 01:15:48.488496
10095 01:15:48.491837 Sending tftp read request... done.
10096 01:15:48.491920
10097 01:15:48.495525 Waiting for the transfer...
10098 01:15:48.495607
10099 01:15:49.088330 00000000 ################################################################
10100 01:15:49.088497
10101 01:15:49.680748 00080000 ################################################################
10102 01:15:49.680903
10103 01:15:50.274113 00100000 ################################################################
10104 01:15:50.274275
10105 01:15:50.880793 00180000 ################################################################
10106 01:15:50.880933
10107 01:15:51.482430 00200000 ################################################################
10108 01:15:51.482619
10109 01:15:52.066196 00280000 ################################################################
10110 01:15:52.066343
10111 01:15:52.652532 00300000 ################################################################
10112 01:15:52.652681
10113 01:15:53.230219 00380000 ################################################################
10114 01:15:53.230370
10115 01:15:53.804135 00400000 ################################################################
10116 01:15:53.804284
10117 01:15:54.382632 00480000 ################################################################
10118 01:15:54.382774
10119 01:15:54.976379 00500000 ################################################################
10120 01:15:54.976524
10121 01:15:55.565624 00580000 ################################################################
10122 01:15:55.565773
10123 01:15:56.145649 00600000 ################################################################
10124 01:15:56.145801
10125 01:15:56.720985 00680000 ################################################################
10126 01:15:56.721135
10127 01:15:57.308712 00700000 ################################################################
10128 01:15:57.308859
10129 01:15:57.899127 00780000 ################################################################
10130 01:15:57.899275
10131 01:15:58.484115 00800000 ################################################################
10132 01:15:58.484268
10133 01:15:59.069064 00880000 ################################################################
10134 01:15:59.069211
10135 01:15:59.648572 00900000 ################################################################
10136 01:15:59.648723
10137 01:16:00.241316 00980000 ################################################################
10138 01:16:00.241485
10139 01:16:00.810488 00a00000 ################################################################
10140 01:16:00.810638
10141 01:16:01.397612 00a80000 ################################################################
10142 01:16:01.397765
10143 01:16:01.982658 00b00000 ################################################################
10144 01:16:01.982807
10145 01:16:02.577556 00b80000 ################################################################
10146 01:16:02.577703
10147 01:16:03.154958 00c00000 ################################################################
10148 01:16:03.155110
10149 01:16:03.740378 00c80000 ################################################################
10150 01:16:03.740534
10151 01:16:04.330800 00d00000 ################################################################
10152 01:16:04.330959
10153 01:16:04.925872 00d80000 ################################################################
10154 01:16:04.926037
10155 01:16:05.530990 00e00000 ################################################################
10156 01:16:05.531149
10157 01:16:06.121428 00e80000 ################################################################
10158 01:16:06.121622
10159 01:16:06.723174 00f00000 ################################################################
10160 01:16:06.723336
10161 01:16:07.313953 00f80000 ################################################################
10162 01:16:07.314112
10163 01:16:07.916714 01000000 ################################################################
10164 01:16:07.916872
10165 01:16:08.503240 01080000 ################################################################
10166 01:16:08.503400
10167 01:16:09.088914 01100000 ################################################################
10168 01:16:09.089099
10169 01:16:09.677657 01180000 ################################################################
10170 01:16:09.677809
10171 01:16:10.277765 01200000 ################################################################
10172 01:16:10.277921
10173 01:16:10.867740 01280000 ################################################################
10174 01:16:10.867890
10175 01:16:11.419462 01300000 ################################################################
10176 01:16:11.419617
10177 01:16:11.983108 01380000 ################################################################
10178 01:16:11.983265
10179 01:16:12.560849 01400000 ################################################################
10180 01:16:12.561001
10181 01:16:13.116972 01480000 ################################################################
10182 01:16:13.117128
10183 01:16:13.689702 01500000 ################################################################
10184 01:16:13.689856
10185 01:16:14.259121 01580000 ################################################################
10186 01:16:14.259287
10187 01:16:14.839235 01600000 ################################################################
10188 01:16:14.839374
10189 01:16:15.390549 01680000 ################################################################
10190 01:16:15.390690
10191 01:16:15.971616 01700000 ################################################################
10192 01:16:15.971748
10193 01:16:16.510069 01780000 ################################################################
10194 01:16:16.510208
10195 01:16:17.065871 01800000 ################################################################
10196 01:16:17.066007
10197 01:16:17.668326 01880000 ################################################################
10198 01:16:17.668811
10199 01:16:18.276628 01900000 ################################################################
10200 01:16:18.276764
10201 01:16:18.824830 01980000 ################################################################
10202 01:16:18.824964
10203 01:16:19.379489 01a00000 ################################################################
10204 01:16:19.379639
10205 01:16:19.938942 01a80000 ################################################################
10206 01:16:19.939435
10207 01:16:20.546882 01b00000 ################################################################
10208 01:16:20.547420
10209 01:16:21.114787 01b80000 ################################################################
10210 01:16:21.114923
10211 01:16:21.682628 01c00000 ################################################################
10212 01:16:21.682811
10213 01:16:22.289852 01c80000 ################################################################
10214 01:16:22.290009
10215 01:16:22.840315 01d00000 ################################################################
10216 01:16:22.840500
10217 01:16:23.464422 01d80000 ################################################################
10218 01:16:23.464555
10219 01:16:24.005861 01e00000 ################################################################
10220 01:16:24.005998
10221 01:16:24.566141 01e80000 ################################################################
10222 01:16:24.566273
10223 01:16:25.188836 01f00000 ################################################################
10224 01:16:25.188978
10225 01:16:25.814157 01f80000 ################################################################
10226 01:16:25.814301
10227 01:16:26.459885 02000000 ################################################################
10228 01:16:26.460398
10229 01:16:27.133994 02080000 ################################################################
10230 01:16:27.134517
10231 01:16:27.785324 02100000 ################################################################
10232 01:16:27.785961
10233 01:16:28.459157 02180000 ################################################################
10234 01:16:28.459685
10235 01:16:29.116460 02200000 ################################################################
10236 01:16:29.116953
10237 01:16:29.797481 02280000 ################################################################
10238 01:16:29.798055
10239 01:16:30.464353 02300000 ################################################################
10240 01:16:30.464862
10241 01:16:31.132227 02380000 ################################################################
10242 01:16:31.132923
10243 01:16:31.798300 02400000 ################################################################
10244 01:16:31.798819
10245 01:16:32.425453 02480000 ################################################################
10246 01:16:32.425637
10247 01:16:33.026898 02500000 ################################################################
10248 01:16:33.027031
10249 01:16:33.610033 02580000 ################################################################
10250 01:16:33.610170
10251 01:16:34.193525 02600000 ################################################################
10252 01:16:34.193667
10253 01:16:34.744180 02680000 ################################################################
10254 01:16:34.744326
10255 01:16:35.270512 02700000 ################################################################
10256 01:16:35.270658
10257 01:16:35.792575 02780000 ################################################################
10258 01:16:35.792753
10259 01:16:36.314660 02800000 ################################################################
10260 01:16:36.314800
10261 01:16:36.835077 02880000 ################################################################
10262 01:16:36.835226
10263 01:16:37.367561 02900000 ################################################################
10264 01:16:37.367708
10265 01:16:37.917223 02980000 ################################################################
10266 01:16:37.917361
10267 01:16:38.441673 02a00000 ################################################################
10268 01:16:38.441809
10269 01:16:38.996988 02a80000 ################################################################
10270 01:16:38.997131
10271 01:16:39.536303 02b00000 ################################################################
10272 01:16:39.536448
10273 01:16:40.084643 02b80000 ################################################################
10274 01:16:40.084783
10275 01:16:40.630101 02c00000 ################################################################
10276 01:16:40.630254
10277 01:16:41.172266 02c80000 ################################################################
10278 01:16:41.172412
10279 01:16:41.740491 02d00000 ################################################################
10280 01:16:41.740642
10281 01:16:42.315563 02d80000 ################################################################
10282 01:16:42.315695
10283 01:16:42.886135 02e00000 ################################################################
10284 01:16:42.886291
10285 01:16:43.465449 02e80000 ################################################################
10286 01:16:43.465636
10287 01:16:44.050140 02f00000 ################################################################
10288 01:16:44.050289
10289 01:16:44.625258 02f80000 ################################################################
10290 01:16:44.625420
10291 01:16:45.195563 03000000 ################################################################
10292 01:16:45.195699
10293 01:16:45.764317 03080000 ################################################################
10294 01:16:45.764464
10295 01:16:46.315677 03100000 ################################################################
10296 01:16:46.315821
10297 01:16:46.877451 03180000 ################################################################
10298 01:16:46.877614
10299 01:16:47.448438 03200000 ################################################################
10300 01:16:47.448611
10301 01:16:48.010726 03280000 ################################################################
10302 01:16:48.010865
10303 01:16:48.593219 03300000 ################################################################
10304 01:16:48.593353
10305 01:16:49.170379 03380000 ################################################################
10306 01:16:49.170523
10307 01:16:49.748212 03400000 ################################################################
10308 01:16:49.748382
10309 01:16:50.327982 03480000 ################################################################
10310 01:16:50.328126
10311 01:16:50.905001 03500000 ################################################################
10312 01:16:50.905152
10313 01:16:51.478268 03580000 ################################################################
10314 01:16:51.478409
10315 01:16:52.052066 03600000 ################################################################
10316 01:16:52.052245
10317 01:16:52.622642 03680000 ################################################################
10318 01:16:52.622814
10319 01:16:53.185841 03700000 ################################################################
10320 01:16:53.185975
10321 01:16:53.760452 03780000 ################################################################
10322 01:16:53.760614
10323 01:16:54.315122 03800000 ################################################################
10324 01:16:54.315272
10325 01:16:54.915938 03880000 ################################################################
10326 01:16:54.916493
10327 01:16:55.580629 03900000 ################################################################
10328 01:16:55.580771
10329 01:16:56.125217 03980000 ################################################################
10330 01:16:56.125352
10331 01:16:56.675855 03a00000 ################################################################
10332 01:16:56.675997
10333 01:16:57.209445 03a80000 ################################################################
10334 01:16:57.209619
10335 01:16:57.748600 03b00000 ################################################################
10336 01:16:57.748766
10337 01:16:58.288405 03b80000 ################################################################
10338 01:16:58.288573
10339 01:16:58.827157 03c00000 ################################################################
10340 01:16:58.827297
10341 01:16:59.372468 03c80000 ################################################################
10342 01:16:59.372604
10343 01:16:59.976024 03d00000 ################################################################
10344 01:16:59.976160
10345 01:17:00.560844 03d80000 ################################################################
10346 01:17:00.561158
10347 01:17:01.252899 03e00000 ################################################################
10348 01:17:01.253433
10349 01:17:01.936012 03e80000 ################################################################
10350 01:17:01.936278
10351 01:17:02.511909 03f00000 ################################################################
10352 01:17:02.512060
10353 01:17:03.102780 03f80000 ################################################################
10354 01:17:03.102928
10355 01:17:03.687267 04000000 ################################################################
10356 01:17:03.687841
10357 01:17:04.340491 04080000 ################################################################
10358 01:17:04.340656
10359 01:17:04.914841 04100000 ################################################################
10360 01:17:04.915013
10361 01:17:05.548921 04180000 ################################################################
10362 01:17:05.549084
10363 01:17:06.252336 04200000 ################################################################
10364 01:17:06.252487
10365 01:17:06.913256 04280000 ################################################################
10366 01:17:06.913952
10367 01:17:07.506781 04300000 ################################################################
10368 01:17:07.506933
10369 01:17:08.095236 04380000 ################################################################
10370 01:17:08.095371
10371 01:17:08.687881 04400000 ################################################################
10372 01:17:08.688050
10373 01:17:09.343696 04480000 ################################################################
10374 01:17:09.343867
10375 01:17:10.043721 04500000 ################################################################
10376 01:17:10.044272
10377 01:17:10.671550 04580000 ################################################################
10378 01:17:10.671689
10379 01:17:11.393298 04600000 ################################################################
10380 01:17:11.393914
10381 01:17:11.481092 04680000 ######### done.
10382 01:17:11.481212
10383 01:17:11.484312 The bootfile was 73997750 bytes long.
10384 01:17:11.484405
10385 01:17:11.487248 Sending tftp read request... done.
10386 01:17:11.487336
10387 01:17:11.487422 Waiting for the transfer...
10388 01:17:11.487505
10389 01:17:11.490644 00000000 # done.
10390 01:17:11.490732
10391 01:17:11.497315 Command line loaded dynamically from TFTP file: 13468726/tftp-deploy-o740h9ux/kernel/cmdline
10392 01:17:11.497403
10393 01:17:11.510704 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10394 01:17:11.510794
10395 01:17:11.514270 Loading FIT.
10396 01:17:11.514357
10397 01:17:11.517155 Image ramdisk-1 has 61038434 bytes.
10398 01:17:11.517241
10399 01:17:11.520508 Image fdt-1 has 47230 bytes.
10400 01:17:11.520595
10401 01:17:11.520682 Image kernel-1 has 12910050 bytes.
10402 01:17:11.523711
10403 01:17:11.530229 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10404 01:17:11.530317
10405 01:17:11.550051 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10406 01:17:11.550143
10407 01:17:11.553709 Choosing best match conf-1 for compat google,spherion-rev2.
10408 01:17:11.558438
10409 01:17:11.562629 Connected to device vid:did:rid of 1ae0:0028:00
10410 01:17:11.569653
10411 01:17:11.572814 tpm_get_response: command 0x17b, return code 0x0
10412 01:17:11.572923
10413 01:17:11.576215 ec_init: CrosEC protocol v3 supported (256, 248)
10414 01:17:11.580265
10415 01:17:11.583850 tpm_cleanup: add release locality here.
10416 01:17:11.583981
10417 01:17:11.584111 Shutting down all USB controllers.
10418 01:17:11.586830
10419 01:17:11.586960 Removing current net device
10420 01:17:11.587091
10421 01:17:11.593438 Exiting depthcharge with code 4 at timestamp: 122782778
10422 01:17:11.593636
10423 01:17:11.596854 LZMA decompressing kernel-1 to 0x821a6718
10424 01:17:11.597018
10425 01:17:11.600014 LZMA decompressing kernel-1 to 0x40000000
10426 01:17:13.195269
10427 01:17:13.195804 jumping to kernel
10428 01:17:13.199427 end: 2.2.4 bootloader-commands (duration 00:01:35) [common]
10429 01:17:13.200129 start: 2.2.5 auto-login-action (timeout 00:02:50) [common]
10430 01:17:13.200719 Setting prompt string to ['Linux version [0-9]']
10431 01:17:13.201292 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10432 01:17:13.201897 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10433 01:17:13.276729
10434 01:17:13.280240 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10435 01:17:13.284050 start: 2.2.5.1 login-action (timeout 00:02:50) [common]
10436 01:17:13.284190 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10437 01:17:13.284288 Setting prompt string to []
10438 01:17:13.284426 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10439 01:17:13.284562 Using line separator: #'\n'#
10440 01:17:13.284671 No login prompt set.
10441 01:17:13.284791 Parsing kernel messages
10442 01:17:13.284892 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10443 01:17:13.285084 [login-action] Waiting for messages, (timeout 00:02:50)
10444 01:17:13.285195 Waiting using forced prompt support (timeout 00:01:25)
10445 01:17:13.303614 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10446 01:17:13.307196 [ 0.000000] random: crng init done
10447 01:17:13.313413 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10448 01:17:13.316772 [ 0.000000] efi: UEFI not found.
10449 01:17:13.323211 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10450 01:17:13.333296 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10451 01:17:13.340138 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10452 01:17:13.349566 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10453 01:17:13.356924 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10454 01:17:13.362940 [ 0.000000] printk: bootconsole [mtk8250] enabled
10455 01:17:13.369356 [ 0.000000] NUMA: No NUMA configuration found
10456 01:17:13.376544 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10457 01:17:13.380209 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10458 01:17:13.383135 [ 0.000000] Zone ranges:
10459 01:17:13.389564 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10460 01:17:13.393090 [ 0.000000] DMA32 empty
10461 01:17:13.399602 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10462 01:17:13.402509 [ 0.000000] Movable zone start for each node
10463 01:17:13.406161 [ 0.000000] Early memory node ranges
10464 01:17:13.412758 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10465 01:17:13.419643 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10466 01:17:13.426070 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10467 01:17:13.432896 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10468 01:17:13.439615 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10469 01:17:13.445827 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10470 01:17:13.502405 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10471 01:17:13.508953 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10472 01:17:13.515728 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10473 01:17:13.518232 [ 0.000000] psci: probing for conduit method from DT.
10474 01:17:13.524779 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10475 01:17:13.528266 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10476 01:17:13.534273 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10477 01:17:13.537914 [ 0.000000] psci: SMC Calling Convention v1.2
10478 01:17:13.544603 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10479 01:17:13.548247 [ 0.000000] Detected VIPT I-cache on CPU0
10480 01:17:13.554611 [ 0.000000] CPU features: detected: GIC system register CPU interface
10481 01:17:13.561570 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10482 01:17:13.568064 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10483 01:17:13.574585 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10484 01:17:13.581335 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10485 01:17:13.590876 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10486 01:17:13.594844 [ 0.000000] alternatives: applying boot alternatives
10487 01:17:13.601005 [ 0.000000] Fallback order for Node 0: 0
10488 01:17:13.607534 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10489 01:17:13.610836 [ 0.000000] Policy zone: Normal
10490 01:17:13.624252 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10491 01:17:13.634210 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10492 01:17:13.646118 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10493 01:17:13.656013 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10494 01:17:13.662937 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10495 01:17:13.666203 <6>[ 0.000000] software IO TLB: area num 8.
10496 01:17:13.722759 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10497 01:17:13.871638 <6>[ 0.000000] Memory: 7904896K/8385536K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 447872K reserved, 32768K cma-reserved)
10498 01:17:13.878410 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10499 01:17:13.884856 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10500 01:17:13.888038 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10501 01:17:13.894544 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10502 01:17:13.901360 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10503 01:17:13.904374 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10504 01:17:13.914697 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10505 01:17:13.920642 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10506 01:17:13.927367 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10507 01:17:13.934308 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10508 01:17:13.937406 <6>[ 0.000000] GICv3: 608 SPIs implemented
10509 01:17:13.940636 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10510 01:17:13.947566 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10511 01:17:13.950565 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10512 01:17:13.957323 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10513 01:17:13.971012 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10514 01:17:13.983990 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10515 01:17:13.990071 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10516 01:17:13.998145 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10517 01:17:14.011283 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10518 01:17:14.017577 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10519 01:17:14.024388 <6>[ 0.009226] Console: colour dummy device 80x25
10520 01:17:14.034688 <6>[ 0.013956] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10521 01:17:14.041315 <6>[ 0.024398] pid_max: default: 32768 minimum: 301
10522 01:17:14.044411 <6>[ 0.029270] LSM: Security Framework initializing
10523 01:17:14.050832 <6>[ 0.034237] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10524 01:17:14.060851 <6>[ 0.042019] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10525 01:17:14.067474 <6>[ 0.051441] cblist_init_generic: Setting adjustable number of callback queues.
10526 01:17:14.074436 <6>[ 0.058881] cblist_init_generic: Setting shift to 3 and lim to 1.
10527 01:17:14.084514 <6>[ 0.065260] cblist_init_generic: Setting adjustable number of callback queues.
10528 01:17:14.090965 <6>[ 0.072688] cblist_init_generic: Setting shift to 3 and lim to 1.
10529 01:17:14.094418 <6>[ 0.079089] rcu: Hierarchical SRCU implementation.
10530 01:17:14.100839 <6>[ 0.084135] rcu: Max phase no-delay instances is 1000.
10531 01:17:14.107443 <6>[ 0.091165] EFI services will not be available.
10532 01:17:14.110837 <6>[ 0.096120] smp: Bringing up secondary CPUs ...
10533 01:17:14.119328 <6>[ 0.101199] Detected VIPT I-cache on CPU1
10534 01:17:14.125920 <6>[ 0.101270] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10535 01:17:14.132545 <6>[ 0.101300] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10536 01:17:14.136052 <6>[ 0.101629] Detected VIPT I-cache on CPU2
10537 01:17:14.145617 <6>[ 0.101676] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10538 01:17:14.152121 <6>[ 0.101691] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10539 01:17:14.155875 <6>[ 0.101952] Detected VIPT I-cache on CPU3
10540 01:17:14.162264 <6>[ 0.101998] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10541 01:17:14.168635 <6>[ 0.102011] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10542 01:17:14.172211 <6>[ 0.102314] CPU features: detected: Spectre-v4
10543 01:17:14.178970 <6>[ 0.102320] CPU features: detected: Spectre-BHB
10544 01:17:14.181991 <6>[ 0.102326] Detected PIPT I-cache on CPU4
10545 01:17:14.189197 <6>[ 0.102383] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10546 01:17:14.195647 <6>[ 0.102400] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10547 01:17:14.201820 <6>[ 0.102694] Detected PIPT I-cache on CPU5
10548 01:17:14.208462 <6>[ 0.102758] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10549 01:17:14.214709 <6>[ 0.102775] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10550 01:17:14.218226 <6>[ 0.103056] Detected PIPT I-cache on CPU6
10551 01:17:14.224948 <6>[ 0.103120] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10552 01:17:14.234584 <6>[ 0.103136] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10553 01:17:14.238145 <6>[ 0.103432] Detected PIPT I-cache on CPU7
10554 01:17:14.244773 <6>[ 0.103496] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10555 01:17:14.251292 <6>[ 0.103513] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10556 01:17:14.254825 <6>[ 0.103560] smp: Brought up 1 node, 8 CPUs
10557 01:17:14.261248 <6>[ 0.244877] SMP: Total of 8 processors activated.
10558 01:17:14.264761 <6>[ 0.249798] CPU features: detected: 32-bit EL0 Support
10559 01:17:14.274493 <6>[ 0.255194] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10560 01:17:14.280924 <6>[ 0.263995] CPU features: detected: Common not Private translations
10561 01:17:14.287444 <6>[ 0.270511] CPU features: detected: CRC32 instructions
10562 01:17:14.291023 <6>[ 0.275863] CPU features: detected: RCpc load-acquire (LDAPR)
10563 01:17:14.297422 <6>[ 0.281823] CPU features: detected: LSE atomic instructions
10564 01:17:14.304753 <6>[ 0.287604] CPU features: detected: Privileged Access Never
10565 01:17:14.311014 <6>[ 0.293384] CPU features: detected: RAS Extension Support
10566 01:17:14.317612 <6>[ 0.298993] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10567 01:17:14.320952 <6>[ 0.306212] CPU: All CPU(s) started at EL2
10568 01:17:14.327437 <6>[ 0.310529] alternatives: applying system-wide alternatives
10569 01:17:14.337205 <6>[ 0.321350] devtmpfs: initialized
10570 01:17:14.352514 <6>[ 0.330233] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10571 01:17:14.359234 <6>[ 0.340194] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10572 01:17:14.366133 <6>[ 0.348421] pinctrl core: initialized pinctrl subsystem
10573 01:17:14.368983 <6>[ 0.355064] DMI not present or invalid.
10574 01:17:14.375637 <6>[ 0.359478] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10575 01:17:14.385391 <6>[ 0.366360] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10576 01:17:14.392078 <6>[ 0.373952] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10577 01:17:14.402052 <6>[ 0.382188] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10578 01:17:14.405435 <6>[ 0.390429] audit: initializing netlink subsys (disabled)
10579 01:17:14.415669 <5>[ 0.396120] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10580 01:17:14.422190 <6>[ 0.396820] thermal_sys: Registered thermal governor 'step_wise'
10581 01:17:14.428810 <6>[ 0.404089] thermal_sys: Registered thermal governor 'power_allocator'
10582 01:17:14.431803 <6>[ 0.410342] cpuidle: using governor menu
10583 01:17:14.438728 <6>[ 0.421300] NET: Registered PF_QIPCRTR protocol family
10584 01:17:14.445078 <6>[ 0.426787] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10585 01:17:14.451674 <6>[ 0.433892] ASID allocator initialised with 32768 entries
10586 01:17:14.454675 <6>[ 0.440459] Serial: AMBA PL011 UART driver
10587 01:17:14.464579 <4>[ 0.449179] Trying to register duplicate clock ID: 134
10588 01:17:14.518362 <6>[ 0.506647] KASLR enabled
10589 01:17:14.533142 <6>[ 0.514345] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10590 01:17:14.539653 <6>[ 0.521360] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10591 01:17:14.546566 <6>[ 0.527849] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10592 01:17:14.552658 <6>[ 0.534855] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10593 01:17:14.559390 <6>[ 0.541341] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10594 01:17:14.565939 <6>[ 0.548343] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10595 01:17:14.572693 <6>[ 0.554827] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10596 01:17:14.579322 <6>[ 0.561830] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10597 01:17:14.582953 <6>[ 0.569350] ACPI: Interpreter disabled.
10598 01:17:14.590952 <6>[ 0.575771] iommu: Default domain type: Translated
10599 01:17:14.597459 <6>[ 0.580881] iommu: DMA domain TLB invalidation policy: strict mode
10600 01:17:14.601157 <5>[ 0.587544] SCSI subsystem initialized
10601 01:17:14.607726 <6>[ 0.591707] usbcore: registered new interface driver usbfs
10602 01:17:14.614434 <6>[ 0.597437] usbcore: registered new interface driver hub
10603 01:17:14.617838 <6>[ 0.602990] usbcore: registered new device driver usb
10604 01:17:14.624252 <6>[ 0.609077] pps_core: LinuxPPS API ver. 1 registered
10605 01:17:14.634049 <6>[ 0.614269] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10606 01:17:14.637674 <6>[ 0.623612] PTP clock support registered
10607 01:17:14.640788 <6>[ 0.627854] EDAC MC: Ver: 3.0.0
10608 01:17:14.648195 <6>[ 0.633003] FPGA manager framework
10609 01:17:14.654922 <6>[ 0.636685] Advanced Linux Sound Architecture Driver Initialized.
10610 01:17:14.658308 <6>[ 0.643461] vgaarb: loaded
10611 01:17:14.664978 <6>[ 0.646633] clocksource: Switched to clocksource arch_sys_counter
10612 01:17:14.667987 <5>[ 0.653080] VFS: Disk quotas dquot_6.6.0
10613 01:17:14.674723 <6>[ 0.657270] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10614 01:17:14.677867 <6>[ 0.664458] pnp: PnP ACPI: disabled
10615 01:17:14.686707 <6>[ 0.671177] NET: Registered PF_INET protocol family
10616 01:17:14.696796 <6>[ 0.676772] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10617 01:17:14.707572 <6>[ 0.689069] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10618 01:17:14.717661 <6>[ 0.697883] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10619 01:17:14.724253 <6>[ 0.705851] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10620 01:17:14.733803 <6>[ 0.714552] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10621 01:17:14.740513 <6>[ 0.724289] TCP: Hash tables configured (established 65536 bind 65536)
10622 01:17:14.747511 <6>[ 0.731151] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10623 01:17:14.757258 <6>[ 0.738350] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10624 01:17:14.763721 <6>[ 0.746028] NET: Registered PF_UNIX/PF_LOCAL protocol family
10625 01:17:14.767123 <6>[ 0.752198] RPC: Registered named UNIX socket transport module.
10626 01:17:14.773866 <6>[ 0.758350] RPC: Registered udp transport module.
10627 01:17:14.777177 <6>[ 0.763285] RPC: Registered tcp transport module.
10628 01:17:14.783494 <6>[ 0.768218] RPC: Registered tcp NFSv4.1 backchannel transport module.
10629 01:17:14.790191 <6>[ 0.774882] PCI: CLS 0 bytes, default 64
10630 01:17:14.793771 <6>[ 0.779260] Unpacking initramfs...
10631 01:17:14.803506 <6>[ 0.783445] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10632 01:17:14.810376 <6>[ 0.792077] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10633 01:17:14.816710 <6>[ 0.800911] kvm [1]: IPA Size Limit: 40 bits
10634 01:17:14.820463 <6>[ 0.805438] kvm [1]: GICv3: no GICV resource entry
10635 01:17:14.826822 <6>[ 0.810456] kvm [1]: disabling GICv2 emulation
10636 01:17:14.829840 <6>[ 0.815140] kvm [1]: GIC system register CPU interface enabled
10637 01:17:14.836802 <6>[ 0.821310] kvm [1]: vgic interrupt IRQ18
10638 01:17:14.843355 <6>[ 0.826702] kvm [1]: VHE mode initialized successfully
10639 01:17:14.846623 <5>[ 0.833141] Initialise system trusted keyrings
10640 01:17:14.856359 <6>[ 0.837957] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10641 01:17:14.863104 <6>[ 0.847942] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10642 01:17:14.869919 <5>[ 0.854345] NFS: Registering the id_resolver key type
10643 01:17:14.873407 <5>[ 0.859647] Key type id_resolver registered
10644 01:17:14.879657 <5>[ 0.864063] Key type id_legacy registered
10645 01:17:14.886176 <6>[ 0.868342] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10646 01:17:14.892852 <6>[ 0.875263] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10647 01:17:14.899317 <6>[ 0.882975] 9p: Installing v9fs 9p2000 file system support
10648 01:17:14.936030 <5>[ 0.920475] Key type asymmetric registered
10649 01:17:14.939251 <5>[ 0.924807] Asymmetric key parser 'x509' registered
10650 01:17:14.949019 <6>[ 0.929948] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10651 01:17:14.952052 <6>[ 0.937563] io scheduler mq-deadline registered
10652 01:17:14.955787 <6>[ 0.942319] io scheduler kyber registered
10653 01:17:14.974793 <6>[ 0.959267] EINJ: ACPI disabled.
10654 01:17:15.007439 <4>[ 0.984897] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10655 01:17:15.016993 <4>[ 0.995548] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10656 01:17:15.031527 <6>[ 1.016175] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10657 01:17:15.039758 <6>[ 1.024118] printk: console [ttyS0] disabled
10658 01:17:15.067892 <6>[ 1.048750] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10659 01:17:15.074300 <6>[ 1.058223] printk: console [ttyS0] enabled
10660 01:17:15.077427 <6>[ 1.058223] printk: console [ttyS0] enabled
10661 01:17:15.084171 <6>[ 1.067120] printk: bootconsole [mtk8250] disabled
10662 01:17:15.087721 <6>[ 1.067120] printk: bootconsole [mtk8250] disabled
10663 01:17:15.094187 <6>[ 1.078190] SuperH (H)SCI(F) driver initialized
10664 01:17:15.097503 <6>[ 1.083490] msm_serial: driver initialized
10665 01:17:15.111404 <6>[ 1.092423] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10666 01:17:15.121501 <6>[ 1.100968] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10667 01:17:15.127887 <6>[ 1.109510] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10668 01:17:15.138084 <6>[ 1.118137] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10669 01:17:15.147584 <6>[ 1.126843] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10670 01:17:15.154724 <6>[ 1.135556] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10671 01:17:15.164375 <6>[ 1.144102] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10672 01:17:15.170894 <6>[ 1.152893] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10673 01:17:15.180755 <6>[ 1.161438] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10674 01:17:15.192987 <6>[ 1.177375] loop: module loaded
10675 01:17:15.199415 <6>[ 1.183075] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10676 01:17:15.222150 <4>[ 1.206493] mtk-pmic-keys: Failed to locate of_node [id: -1]
10677 01:17:15.228890 <6>[ 1.213305] megasas: 07.719.03.00-rc1
10678 01:17:15.238705 <6>[ 1.222966] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10679 01:17:15.245965 <6>[ 1.230034] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10680 01:17:15.262484 <6>[ 1.246706] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10681 01:17:15.319023 <6>[ 1.296702] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10682 01:17:17.486552 <6>[ 3.471089] Freeing initrd memory: 59604K
10683 01:17:17.497914 <6>[ 3.482513] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10684 01:17:17.508653 <6>[ 3.493451] tun: Universal TUN/TAP device driver, 1.6
10685 01:17:17.512144 <6>[ 3.499512] thunder_xcv, ver 1.0
10686 01:17:17.515308 <6>[ 3.503022] thunder_bgx, ver 1.0
10687 01:17:17.518790 <6>[ 3.506512] nicpf, ver 1.0
10688 01:17:17.529250 <6>[ 3.510533] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10689 01:17:17.532627 <6>[ 3.518009] hns3: Copyright (c) 2017 Huawei Corporation.
10690 01:17:17.539461 <6>[ 3.523608] hclge is initializing
10691 01:17:17.542226 <6>[ 3.527184] e1000: Intel(R) PRO/1000 Network Driver
10692 01:17:17.549186 <6>[ 3.532313] e1000: Copyright (c) 1999-2006 Intel Corporation.
10693 01:17:17.552282 <6>[ 3.538326] e1000e: Intel(R) PRO/1000 Network Driver
10694 01:17:17.558907 <6>[ 3.543541] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10695 01:17:17.566144 <6>[ 3.549726] igb: Intel(R) Gigabit Ethernet Network Driver
10696 01:17:17.572613 <6>[ 3.555375] igb: Copyright (c) 2007-2014 Intel Corporation.
10697 01:17:17.579151 <6>[ 3.561210] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10698 01:17:17.585795 <6>[ 3.567728] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10699 01:17:17.589145 <6>[ 3.574193] sky2: driver version 1.30
10700 01:17:17.595589 <6>[ 3.579189] VFIO - User Level meta-driver version: 0.3
10701 01:17:17.602954 <6>[ 3.587434] usbcore: registered new interface driver usb-storage
10702 01:17:17.609478 <6>[ 3.593878] usbcore: registered new device driver onboard-usb-hub
10703 01:17:17.618175 <6>[ 3.603062] mt6397-rtc mt6359-rtc: registered as rtc0
10704 01:17:17.628068 <6>[ 3.608530] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:17:17 UTC (1713835037)
10705 01:17:17.631617 <6>[ 3.618098] i2c_dev: i2c /dev entries driver
10706 01:17:17.649200 <6>[ 3.629955] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10707 01:17:17.655447 <4>[ 3.638690] cpu cpu0: supply cpu not found, using dummy regulator
10708 01:17:17.661813 <4>[ 3.645109] cpu cpu1: supply cpu not found, using dummy regulator
10709 01:17:17.668724 <4>[ 3.651512] cpu cpu2: supply cpu not found, using dummy regulator
10710 01:17:17.675043 <4>[ 3.657915] cpu cpu3: supply cpu not found, using dummy regulator
10711 01:17:17.681536 <4>[ 3.664328] cpu cpu4: supply cpu not found, using dummy regulator
10712 01:17:17.688259 <4>[ 3.670725] cpu cpu5: supply cpu not found, using dummy regulator
10713 01:17:17.695041 <4>[ 3.677123] cpu cpu6: supply cpu not found, using dummy regulator
10714 01:17:17.701720 <4>[ 3.683518] cpu cpu7: supply cpu not found, using dummy regulator
10715 01:17:17.719611 <6>[ 3.704163] cpu cpu0: EM: created perf domain
10716 01:17:17.722817 <6>[ 3.709106] cpu cpu4: EM: created perf domain
10717 01:17:17.730484 <6>[ 3.714741] sdhci: Secure Digital Host Controller Interface driver
10718 01:17:17.736392 <6>[ 3.721169] sdhci: Copyright(c) Pierre Ossman
10719 01:17:17.743458 <6>[ 3.726129] Synopsys Designware Multimedia Card Interface Driver
10720 01:17:17.749875 <6>[ 3.732770] sdhci-pltfm: SDHCI platform and OF driver helper
10721 01:17:17.753418 <6>[ 3.732820] mmc0: CQHCI version 5.10
10722 01:17:17.759521 <6>[ 3.742734] ledtrig-cpu: registered to indicate activity on CPUs
10723 01:17:17.766172 <6>[ 3.749733] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10724 01:17:17.772590 <6>[ 3.756814] usbcore: registered new interface driver usbhid
10725 01:17:17.776118 <6>[ 3.762638] usbhid: USB HID core driver
10726 01:17:17.782685 <6>[ 3.766833] spi_master spi0: will run message pump with realtime priority
10727 01:17:17.826473 <6>[ 3.804716] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10728 01:17:17.845118 <6>[ 3.820195] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10729 01:17:17.851860 <6>[ 3.835143] cros-ec-spi spi0.0: Chrome EC device registered
10730 01:17:17.855420 <6>[ 3.841196] mmc0: Command Queue Engine enabled
10731 01:17:17.862370 <6>[ 3.845940] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10732 01:17:17.868436 <6>[ 3.853492] mmcblk0: mmc0:0001 DA4128 116 GiB
10733 01:17:17.878302 <6>[ 3.853786] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10734 01:17:17.882071 <6>[ 3.861744] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10735 01:17:17.888501 <6>[ 3.868524] NET: Registered PF_PACKET protocol family
10736 01:17:17.895055 <6>[ 3.874757] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10737 01:17:17.898315 <6>[ 3.878828] 9pnet: Installing 9P2000 support
10738 01:17:17.904984 <6>[ 3.884690] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10739 01:17:17.908426 <5>[ 3.888521] Key type dns_resolver registered
10740 01:17:17.915136 <6>[ 3.894387] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10741 01:17:17.917954 <6>[ 3.898781] registered taskstats version 1
10742 01:17:17.924982 <5>[ 3.909120] Loading compiled-in X.509 certificates
10743 01:17:17.952143 <4>[ 3.930154] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10744 01:17:17.962087 <4>[ 3.940831] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10745 01:17:17.968597 <3>[ 3.951358] debugfs: File 'uA_load' in directory '/' already present!
10746 01:17:17.975385 <3>[ 3.958057] debugfs: File 'min_uV' in directory '/' already present!
10747 01:17:17.982493 <3>[ 3.964664] debugfs: File 'max_uV' in directory '/' already present!
10748 01:17:17.988989 <3>[ 3.971327] debugfs: File 'constraint_flags' in directory '/' already present!
10749 01:17:17.999127 <3>[ 3.980465] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10750 01:17:18.008511 <6>[ 3.992970] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10751 01:17:18.015062 <6>[ 3.999797] xhci-mtk 11200000.usb: xHCI Host Controller
10752 01:17:18.021825 <6>[ 4.005300] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10753 01:17:18.032243 <6>[ 4.013155] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10754 01:17:18.038648 <6>[ 4.022576] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10755 01:17:18.045237 <6>[ 4.028667] xhci-mtk 11200000.usb: xHCI Host Controller
10756 01:17:18.051672 <6>[ 4.034147] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10757 01:17:18.058379 <6>[ 4.041803] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10758 01:17:18.065404 <6>[ 4.049501] hub 1-0:1.0: USB hub found
10759 01:17:18.068444 <6>[ 4.053518] hub 1-0:1.0: 1 port detected
10760 01:17:18.075083 <6>[ 4.057793] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10761 01:17:18.081667 <6>[ 4.066358] hub 2-0:1.0: USB hub found
10762 01:17:18.085141 <6>[ 4.070369] hub 2-0:1.0: 1 port detected
10763 01:17:18.093668 <6>[ 4.078520] mtk-msdc 11f70000.mmc: Got CD GPIO
10764 01:17:18.103940 <6>[ 4.085557] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10765 01:17:18.110969 <6>[ 4.093588] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10766 01:17:18.120660 <4>[ 4.101531] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10767 01:17:18.130458 <6>[ 4.111058] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10768 01:17:18.136927 <6>[ 4.119143] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10769 01:17:18.147186 <6>[ 4.127241] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10770 01:17:18.153590 <6>[ 4.135169] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10771 01:17:18.160388 <6>[ 4.143047] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10772 01:17:18.170110 <6>[ 4.150866] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10773 01:17:18.180345 <6>[ 4.161478] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10774 01:17:18.189606 <6>[ 4.169837] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10775 01:17:18.196378 <6>[ 4.178205] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10776 01:17:18.206450 <6>[ 4.186544] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10777 01:17:18.213040 <6>[ 4.194895] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10778 01:17:18.223068 <6>[ 4.203234] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10779 01:17:18.229596 <6>[ 4.211583] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10780 01:17:18.239508 <6>[ 4.219922] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10781 01:17:18.246105 <6>[ 4.228271] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10782 01:17:18.255784 <6>[ 4.236610] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10783 01:17:18.262535 <6>[ 4.244958] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10784 01:17:18.272793 <6>[ 4.253297] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10785 01:17:18.279361 <6>[ 4.261635] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10786 01:17:18.288875 <6>[ 4.269973] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10787 01:17:18.295219 <6>[ 4.278311] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10788 01:17:18.302066 <6>[ 4.287097] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10789 01:17:18.309553 <6>[ 4.294298] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10790 01:17:18.316226 <6>[ 4.301073] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10791 01:17:18.326638 <6>[ 4.307834] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10792 01:17:18.333069 <6>[ 4.314766] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10793 01:17:18.339665 <6>[ 4.321613] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10794 01:17:18.349167 <6>[ 4.330743] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10795 01:17:18.359210 <6>[ 4.339862] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10796 01:17:18.369571 <6>[ 4.349155] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10797 01:17:18.379226 <6>[ 4.358648] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10798 01:17:18.386006 <6>[ 4.368122] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10799 01:17:18.396157 <6>[ 4.377242] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10800 01:17:18.406032 <6>[ 4.386712] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10801 01:17:18.415768 <6>[ 4.395831] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10802 01:17:18.425503 <6>[ 4.405125] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10803 01:17:18.435657 <6>[ 4.415285] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10804 01:17:18.445029 <6>[ 4.426867] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10805 01:17:18.473373 <6>[ 4.455185] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10806 01:17:18.502161 <6>[ 4.486733] hub 2-1:1.0: USB hub found
10807 01:17:18.505373 <6>[ 4.491192] hub 2-1:1.0: 3 ports detected
10808 01:17:18.513447 <6>[ 4.498430] hub 2-1:1.0: USB hub found
10809 01:17:18.517117 <6>[ 4.502856] hub 2-1:1.0: 3 ports detected
10810 01:17:18.625036 <6>[ 4.606842] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10811 01:17:18.779493 <6>[ 4.764615] hub 1-1:1.0: USB hub found
10812 01:17:18.783066 <6>[ 4.769152] hub 1-1:1.0: 4 ports detected
10813 01:17:18.792889 <6>[ 4.777740] hub 1-1:1.0: USB hub found
10814 01:17:18.796224 <6>[ 4.782212] hub 1-1:1.0: 4 ports detected
10815 01:17:18.865336 <6>[ 4.847158] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10816 01:17:19.117220 <6>[ 5.098945] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10817 01:17:19.250252 <6>[ 5.234874] hub 1-1.4:1.0: USB hub found
10818 01:17:19.253468 <6>[ 5.239547] hub 1-1.4:1.0: 2 ports detected
10819 01:17:19.263248 <6>[ 5.248168] hub 1-1.4:1.0: USB hub found
10820 01:17:19.266695 <6>[ 5.252777] hub 1-1.4:1.0: 2 ports detected
10821 01:17:19.564746 <6>[ 5.546914] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10822 01:17:19.756971 <6>[ 5.738946] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10823 01:17:30.730371 <6>[ 16.719965] ALSA device list:
10824 01:17:30.736904 <6>[ 16.723256] No soundcards found.
10825 01:17:30.745551 <6>[ 16.731690] Freeing unused kernel memory: 8448K
10826 01:17:30.748835 <6>[ 16.736680] Run /init as init process
10827 01:17:30.795183 <6>[ 16.781500] NET: Registered PF_INET6 protocol family
10828 01:17:30.802024 <6>[ 16.787990] Segment Routing with IPv6
10829 01:17:30.805592 <6>[ 16.791957] In-situ OAM (IOAM) with IPv6
10830 01:17:30.851591 <30>[ 16.810907] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10831 01:17:30.857732 <30>[ 16.844015] systemd[1]: Detected architecture arm64.
10832 01:17:30.858162
10833 01:17:30.864780 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10834 01:17:30.865201
10835 01:17:30.865711
10836 01:17:30.880880 <30>[ 16.866963] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10837 01:17:31.026667 <30>[ 17.009765] systemd[1]: Queued start job for default target graphical.target.
10838 01:17:31.065873 <30>[ 17.048674] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10839 01:17:31.072155 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10840 01:17:31.072675
10841 01:17:31.092768 <30>[ 17.075557] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10842 01:17:31.102739 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10843 01:17:31.103276
10844 01:17:31.120488 <30>[ 17.103622] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10845 01:17:31.130742 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10846 01:17:31.131321
10847 01:17:31.149567 <30>[ 17.132237] systemd[1]: Created slice user.slice - User and Session Slice.
10848 01:17:31.156171 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10849 01:17:31.156645
10850 01:17:31.180325 <30>[ 17.159588] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10851 01:17:31.189808 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10852 01:17:31.190385
10853 01:17:31.207327 <30>[ 17.187044] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10854 01:17:31.213820 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10855 01:17:31.214312
10856 01:17:31.242344 <30>[ 17.215489] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10857 01:17:31.252538 <30>[ 17.235434] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10858 01:17:31.259266 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10859 01:17:31.259850
10860 01:17:31.275766 <30>[ 17.258965] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10861 01:17:31.282381 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10862 01:17:31.282850
10863 01:17:31.299923 <30>[ 17.282986] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10864 01:17:31.309659 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10865 01:17:31.310118
10866 01:17:31.325030 <30>[ 17.311441] systemd[1]: Reached target paths.target - Path Units.
10867 01:17:31.332009 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10868 01:17:31.332442
10869 01:17:31.352325 <30>[ 17.335383] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10870 01:17:31.358925 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10871 01:17:31.359504
10872 01:17:31.372678 <30>[ 17.358912] systemd[1]: Reached target slices.target - Slice Units.
10873 01:17:31.382503 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10874 01:17:31.382907
10875 01:17:31.396959 <30>[ 17.383435] systemd[1]: Reached target swap.target - Swaps.
10876 01:17:31.403600 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10877 01:17:31.404174
10878 01:17:31.424651 <30>[ 17.407448] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10879 01:17:31.434467 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10880 01:17:31.434918
10881 01:17:31.452654 <30>[ 17.435416] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10882 01:17:31.462587 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10883 01:17:31.463244
10884 01:17:31.482323 <30>[ 17.464915] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10885 01:17:31.491927 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10886 01:17:31.492510
10887 01:17:31.508612 <30>[ 17.491576] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10888 01:17:31.518797 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10889 01:17:31.519222
10890 01:17:31.536425 <30>[ 17.519609] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10891 01:17:31.542925 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10892 01:17:31.543341
10893 01:17:31.560958 <30>[ 17.543589] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10894 01:17:31.570881 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10895 01:17:31.571407
10896 01:17:31.589255 <30>[ 17.572107] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10897 01:17:31.599330 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10898 01:17:31.599798
10899 01:17:31.656977 <30>[ 17.639291] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10900 01:17:31.663109 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10901 01:17:31.663637
10902 01:17:31.682245 <30>[ 17.664978] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10903 01:17:31.689206 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10904 01:17:31.689819
10905 01:17:31.711146 <30>[ 17.693661] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10906 01:17:31.717646 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10907 01:17:31.718206
10908 01:17:31.743079 <30>[ 17.719461] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10909 01:17:31.757093 <30>[ 17.739672] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10910 01:17:31.766833 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10911 01:17:31.767380
10912 01:17:31.813089 <30>[ 17.795607] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10913 01:17:31.819389 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10914 01:17:31.819905
10915 01:17:31.846070 <30>[ 17.828410] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10916 01:17:31.855473 Startin<6>[ 17.837874] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10917 01:17:31.862194 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10918 01:17:31.862754
10919 01:17:31.913011 <30>[ 17.895745] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10920 01:17:31.919367 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10921 01:17:31.919889
10922 01:17:31.949771 <30>[ 17.932570] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10923 01:17:31.959862 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10924 01:17:31.960422
10925 01:17:31.985491 <30>[ 17.968310] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10926 01:17:31.991952 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10927 01:17:31.992424
10928 01:17:32.048363 <30>[ 18.031478] systemd[1]: Starting systemd-journald.service - Journal Service...
10929 01:17:32.055234 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10930 01:17:32.055777
10931 01:17:32.075124 <30>[ 18.058099] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10932 01:17:32.081757 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10933 01:17:32.082183
10934 01:17:32.106662 <30>[ 18.086598] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10935 01:17:32.113799 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10936 01:17:32.114357
10937 01:17:32.136525 <30>[ 18.119875] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10938 01:17:32.146492 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10939 01:17:32.147032
10940 01:17:32.168336 <30>[ 18.151046] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10941 01:17:32.174422 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10942 01:17:32.175039
10943 01:17:32.202514 <30>[ 18.185620] systemd[1]: Started systemd-journald.service - Journal Service.
10944 01:17:32.209338 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10945 01:17:32.209827
10946 01:17:32.232436 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10947 01:17:32.233228
10948 01:17:32.249466 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10949 01:17:32.250012
10950 01:17:32.269217 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10951 01:17:32.269741
10952 01:17:32.288713 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10953 01:17:32.289262
10954 01:17:32.305214 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10955 01:17:32.305908
10956 01:17:32.325277 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10957 01:17:32.325879
10958 01:17:32.347208 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10959 01:17:32.347774
10960 01:17:32.367031 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10961 01:17:32.367603
10962 01:17:32.387633 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10963 01:17:32.388192
10964 01:17:32.406333 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10965 01:17:32.406890
10966 01:17:32.428557 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10967 01:17:32.429233
10968 01:17:32.448976 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10969 01:17:32.449064
10970 01:17:32.468767 See 'systemctl status systemd-remount-fs.service' for details.
10971 01:17:32.469207
10972 01:17:32.493181 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10973 01:17:32.493759
10974 01:17:32.514725 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10975 01:17:32.515305
10976 01:17:32.573134 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10977 01:17:32.573707
10978 01:17:32.598891 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10979 01:17:32.599542
10980 01:17:32.611860 <46>[ 18.594923] systemd-journald[178]: Received client request to flush runtime journal.
10981 01:17:32.623796 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10982 01:17:32.624373
10983 01:17:32.645020 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10984 01:17:32.645631
10985 01:17:32.668129 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10986 01:17:32.668696
10987 01:17:32.694071 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10988 01:17:32.694635
10989 01:17:32.717671 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10990 01:17:32.718414
10991 01:17:32.737373 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10992 01:17:32.737559
10993 01:17:32.757135 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10994 01:17:32.757329
10995 01:17:32.777061 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10996 01:17:32.777349
10997 01:17:32.828466 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10998 01:17:32.829060
10999 01:17:32.851456 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11000 01:17:32.852073
11001 01:17:32.868193 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11002 01:17:32.868667
11003 01:17:32.883710 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11004 01:17:32.884175
11005 01:17:32.924163 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11006 01:17:32.924249
11007 01:17:32.954028 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11008 01:17:32.954118
11009 01:17:32.978500 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11010 01:17:32.978588
11011 01:17:33.002399 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11012 01:17:33.002505
11013 01:17:33.036654 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11014 01:17:33.036930
11015 01:17:33.066414 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11016 01:17:33.066843
11017 01:17:33.126247 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11018 01:17:33.126688
11019 01:17:33.146651 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11020 01:17:33.147079
11021 01:17:33.191238 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11022 01:17:33.191688
11023 01:17:33.290914 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11024 01:17:33.291593
11025 01:17:33.308260 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11026 01:17:33.308749
11027 01:17:33.324767 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11028 01:17:33.325189
11029 01:17:33.342384 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11030 01:17:33.342807
11031 01:17:33.360230 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11032 01:17:33.360657
11033 01:17:33.367056 <6>[ 19.349321] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11034 01:17:33.373625 <3>[ 19.350248] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11035 01:17:33.383401 <6>[ 19.357940] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11036 01:17:33.390136 <3>[ 19.366291] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11037 01:17:33.400331 <6>[ 19.374724] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11038 01:17:33.406310 <3>[ 19.382707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11039 01:17:33.420300 [[0;32m OK [0m] Listening on<3>[ 19.401821] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11040 01:17:33.426659 [0;1;39mdbus.s<6>[ 19.407295] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11041 01:17:33.436957 <3>[ 19.410758] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11042 01:17:33.446404 ocket[…- D-Bu<3>[ 19.427489] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11043 01:17:33.452798 s System Message<6>[ 19.430497] mc: Linux media interface: v0.10
11044 01:17:33.459989 <3>[ 19.436982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11045 01:17:33.466143 <6>[ 19.438021] remoteproc remoteproc0: scp is available
11046 01:17:33.469497 <6>[ 19.438083] remoteproc remoteproc0: powering up scp
11047 01:17:33.469965 Bus Socket.
11048 01:17:33.472815
11049 01:17:33.479712 <6>[ 19.438092] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11050 01:17:33.486113 <6>[ 19.438112] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11051 01:17:33.492380 <6>[ 19.463492] usbcore: registered new device driver r8152-cfgselector
11052 01:17:33.498978 <3>[ 19.471038] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11053 01:17:33.508958 <3>[ 19.479071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11054 01:17:33.515574 <4>[ 19.481082] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11055 01:17:33.522599 <6>[ 19.485254] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11056 01:17:33.528664 <4>[ 19.485385] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11057 01:17:33.538803 <3>[ 19.495660] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11058 01:17:33.545405 <6>[ 19.516335] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11059 01:17:33.552445 <6>[ 19.516957] videodev: Linux video capture interface: v2.00
11060 01:17:33.559388 <3>[ 19.521983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11061 01:17:33.569306 <4>[ 19.527771] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11062 01:17:33.572854 <4>[ 19.527771] Fallback method does not support PEC.
11063 01:17:33.579285 <6>[ 19.532327] pci_bus 0000:00: root bus resource [bus 00-ff]
11064 01:17:33.585673 <3>[ 19.536724] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11065 01:17:33.595571 <3>[ 19.537025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11066 01:17:33.602448 <6>[ 19.542523] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11067 01:17:33.612149 <3>[ 19.544676] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11068 01:17:33.619112 <3>[ 19.550599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11069 01:17:33.626062 <3>[ 19.550603] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11070 01:17:33.636726 <3>[ 19.550609] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11071 01:17:33.643111 <3>[ 19.550612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11072 01:17:33.649720 <3>[ 19.550655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11073 01:17:33.659716 <6>[ 19.563502] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11074 01:17:33.665740 <6>[ 19.563509] remoteproc remoteproc0: remote processor scp is now up
11075 01:17:33.672540 <6>[ 19.563525] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11076 01:17:33.682516 <6>[ 19.564506] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11077 01:17:33.692528 <6>[ 19.578752] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11078 01:17:33.698896 <6>[ 19.586275] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11079 01:17:33.708955 <6>[ 19.593699] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11080 01:17:33.715562 <6>[ 19.593848] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11081 01:17:33.725643 <6>[ 19.602244] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11082 01:17:33.731933 <6>[ 19.606907] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11083 01:17:33.742050 <6>[ 19.620167] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11084 01:17:33.745370 <6>[ 19.626505] pci 0000:00:00.0: supports D1 D2
11085 01:17:33.756198 <3>[ 19.626855] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11086 01:17:33.764020 <6>[ 19.639623] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11087 01:17:33.771063 <4>[ 19.640226] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11088 01:17:33.780707 <4>[ 19.640236] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11089 01:17:33.787585 <6>[ 19.642608] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11090 01:17:33.797364 <3>[ 19.642673] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11091 01:17:33.800824 <6>[ 19.651983] Bluetooth: Core ver 2.22
11092 01:17:33.807447 <6>[ 19.658775] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11093 01:17:33.814453 <6>[ 19.659253] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11094 01:17:33.827960 <6>[ 19.660719] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11095 01:17:33.835073 <6>[ 19.660833] usbcore: registered new interface driver uvcvideo
11096 01:17:33.838518 <6>[ 19.664734] NET: Registered PF_BLUETOOTH protocol family
11097 01:17:33.845081 <6>[ 19.674755] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11098 01:17:33.852092 <6>[ 19.684733] Bluetooth: HCI device and connection manager initialized
11099 01:17:33.858763 <6>[ 19.690912] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11100 01:17:33.865232 <6>[ 19.694823] r8152 2-1.3:1.0 eth0: v1.12.13
11101 01:17:33.868351 <6>[ 19.694901] usbcore: registered new interface driver r8152
11102 01:17:33.875565 <6>[ 19.699282] Bluetooth: HCI socket layer initialized
11103 01:17:33.882167 <6>[ 19.708322] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11104 01:17:33.889373 <6>[ 19.709479] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11105 01:17:33.892559 <6>[ 19.715774] Bluetooth: L2CAP socket layer initialized
11106 01:17:33.902506 <6>[ 19.725074] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11107 01:17:33.909229 <6>[ 19.725467] usbcore: registered new interface driver cdc_ether
11108 01:17:33.912349 <6>[ 19.733330] Bluetooth: SCO socket layer initialized
11109 01:17:33.915957 <6>[ 19.737939] pci 0000:01:00.0: supports D1 D2
11110 01:17:33.923059 <6>[ 19.738107] usbcore: registered new interface driver r8153_ecm
11111 01:17:33.933015 <3>[ 19.751102] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11112 01:17:33.939668 <6>[ 19.753342] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
11113 01:17:33.946515 <6>[ 19.754852] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11114 01:17:33.952687 <3>[ 19.763853] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11115 01:17:33.959823 <6>[ 19.766787] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11116 01:17:33.966027 <6>[ 19.792036] usbcore: registered new interface driver btusb
11117 01:17:33.975811 <4>[ 19.792795] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11118 01:17:33.982376 <3>[ 19.792806] Bluetooth: hci0: Failed to load firmware file (-2)
11119 01:17:33.988963 <3>[ 19.792809] Bluetooth: hci0: Failed to set up firmware (-2)
11120 01:17:33.999138 <4>[ 19.792813] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11121 01:17:34.008755 <6>[ 19.799741] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11122 01:17:34.015525 <3>[ 19.830132] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11123 01:17:34.025248 <6>[ 19.830727] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11124 01:17:34.031960 <6>[ 19.830738] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11125 01:17:34.038449 <6>[ 19.830751] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11126 01:17:34.048386 <3>[ 19.837019] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11127 01:17:34.058297 <6>[ 19.843607] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11128 01:17:34.064841 <3>[ 19.883216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11129 01:17:34.074745 <3>[ 19.883903] power_supply sbs-5-000b: driver failed to report `health' property: -6
11130 01:17:34.078074 <6>[ 19.885660] pci 0000:00:00.0: PCI bridge to [bus 01]
11131 01:17:34.088430 <3>[ 19.913428] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11132 01:17:34.094987 <6>[ 19.914892] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11133 01:17:34.104634 [[0;32m OK [<6>[ 20.087308] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11134 01:17:34.112055 0m] Reached targ<6>[ 20.096028] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11135 01:17:34.119011 et [0;1;39msock<6>[ 20.103023] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11136 01:17:34.122255 ets.target[0m - Socket Units.
11137 01:17:34.122734
11138 01:17:34.135945 <5>[ 20.118886] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11139 01:17:34.142967 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11140 01:17:34.143644
11141 01:17:34.156344 <5>[ 20.139540] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11142 01:17:34.163348 <5>[ 20.146910] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11143 01:17:34.173787 <4>[ 20.155349] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11144 01:17:34.176470 <6>[ 20.164233] cfg80211: failed to load regulatory.db
11145 01:17:34.190276 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11146 01:17:34.190917
11147 01:17:34.232363 <6>[ 20.215358] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11148 01:17:34.238976 <6>[ 20.222882] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11149 01:17:34.265619 Startin<6>[ 20.249567] mt7921e 0000:01:00.0: ASIC revision: 79610010
11150 01:17:34.268405 g [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11151 01:17:34.268868
11152 01:17:34.292572 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11153 01:17:34.293170
11154 01:17:34.312810 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11155 01:17:34.313435
11156 01:17:34.361925 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11157 01:17:34.362500
11158 01:17:34.372308 <6>[ 20.355513] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11159 01:17:34.376176 <6>[ 20.355513]
11160 01:17:34.398399 <46>[ 20.367815] systemd-journald[178]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.1 (1537 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
11161 01:17:34.412302 <46>[ 20.389365] systemd-journald[178]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11162 01:17:34.421665 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11163 01:17:34.422287
11164 01:17:34.443949 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11165 01:17:34.444557
11166 01:17:34.461141 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11167 01:17:34.461788
11168 01:17:34.480916 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11169 01:17:34.481481
11170 01:17:34.529761 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11171 01:17:34.530378
11172 01:17:34.550560 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11173 01:17:34.551003
11174 01:17:34.569083 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11175 01:17:34.569627
11176 01:17:34.584851 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11177 01:17:34.585422
11178 01:17:34.604442 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11179 01:17:34.604943
11180 01:17:34.639742 <6>[ 20.622897] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11181 01:17:34.665608 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11182 01:17:34.666055
11183 01:17:34.690988 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11184 01:17:34.691425
11185 01:17:34.715286 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11186 01:17:34.715712
11187 01:17:34.781905 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11188 01:17:34.782007
11189 01:17:34.801384 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11190 01:17:34.801467
11191 01:17:34.831367 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11192 01:17:34.831451
11193 01:17:34.888949
11194 01:17:34.889044
11195 01:17:34.892225 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11196 01:17:34.892305
11197 01:17:34.895057 debian-bookworm-arm64 login: root (automatic login)
11198 01:17:34.895163
11199 01:17:34.895255
11200 01:17:34.910447 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024 aarch64
11201 01:17:34.910528
11202 01:17:34.917265 The programs included with the Debian GNU/Linux system are free software;
11203 01:17:34.923741 the exact distribution terms for each program are described in the
11204 01:17:34.927256 individual files in /usr/share/doc/*/copyright.
11205 01:17:34.927336
11206 01:17:34.933788 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11207 01:17:34.936763 permitted by applicable law.
11208 01:17:34.937146 Matched prompt #10: / #
11210 01:17:34.937344 Setting prompt string to ['/ #']
11211 01:17:34.937435 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11213 01:17:34.937663 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11214 01:17:34.937749 start: 2.2.6 expect-shell-connection (timeout 00:02:28) [common]
11215 01:17:34.937819 Setting prompt string to ['/ #']
11216 01:17:34.937877 Forcing a shell prompt, looking for ['/ #']
11218 01:17:34.988127 / #
11219 01:17:34.988382 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11220 01:17:34.988620 Waiting using forced prompt support (timeout 00:02:30)
11221 01:17:34.993534
11222 01:17:34.994055 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11223 01:17:34.994330 start: 2.2.7 export-device-env (timeout 00:02:28) [common]
11224 01:17:34.994592 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11225 01:17:34.994832 end: 2.2 depthcharge-retry (duration 00:02:32) [common]
11226 01:17:34.995079 end: 2 depthcharge-action (duration 00:02:32) [common]
11227 01:17:34.995327 start: 3 lava-test-retry (timeout 00:07:04) [common]
11228 01:17:34.995617 start: 3.1 lava-test-shell (timeout 00:07:04) [common]
11229 01:17:34.995835 Using namespace: common
11231 01:17:35.096561 / # #
11232 01:17:35.097114 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11233 01:17:35.103268 #
11234 01:17:35.103966 Using /lava-13468726
11236 01:17:35.204957 / # export SHELL=/bin/sh
11237 01:17:35.211055 export SHELL=/bin/sh
11239 01:17:35.312428 / # . /lava-13468726/environment
11240 01:17:35.318151 . /lava-13468726/environment
11242 01:17:35.419535 / # /lava-13468726/bin/lava-test-runner /lava-13468726/0
11243 01:17:35.420027 Test shell timeout: 10s (minimum of the action and connection timeout)
11244 01:17:35.425494 /lava-13468726/bin/lava-test-runner /lava-13468726/0
11245 01:17:35.450994 + export TESTRUN_ID=0_igt-kms-me<8>[ 21.436293] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 13468726_1.5.2.3.1>
11246 01:17:35.451683 Received signal: <STARTRUN> 0_igt-kms-mediatek 13468726_1.5.2.3.1
11247 01:17:35.452050 Starting test lava.0_igt-kms-mediatek (13468726_1.5.2.3.1)
11248 01:17:35.452439 Skipping test definition patterns.
11249 01:17:35.454462 diatek
11250 01:17:35.457559 + cd /lava-13468726/0/tests/0_igt-kms-mediatek
11251 01:17:35.457980 + cat uuid
11252 01:17:35.461324 + UUID=13468726_1.5.2.3.1
11253 01:17:35.461881 + set +x
11254 01:17:35.481105 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic km<8>[ 21.466576] <LAVA_SIGNAL_TESTSET START core_auth>
11255 01:17:35.481994 Received signal: <TESTSET> START core_auth
11256 01:17:35.482569 Starting test_set core_auth
11257 01:17:35.487225 s_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11258 01:17:35.500184 <6>[ 21.487174] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11259 01:17:35.513577 <14>[ 21.500166] [IGT] core_auth: executing
11260 01:17:35.520265 IGT-Version: 1.2<14>[ 21.504777] [IGT] core_auth: starting subtest getclient-simple
11261 01:17:35.529958 8-ga44ebfe (aarc<14>[ 21.512354] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11262 01:17:35.533120 h64) (Linux: 6.1<14>[ 21.520608] [IGT] core_auth: exiting, ret=0
11263 01:17:35.536327 .86-cip19 aarch64)
11264 01:17:35.540042 Using IGT_SRANDOM=1713835055 for randomisation
11265 01:17:35.549875 Starting sub<8>[ 21.533318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11266 01:17:35.550323 test: getclient-simple
11267 01:17:35.550915 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11269 01:17:35.553340 Opened device: /dev/dri/card0
11270 01:17:35.559841 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11271 01:17:35.572815 <14>[ 21.559481] [IGT] core_auth: executing
11272 01:17:35.579701 IGT-Version: 1.2<14>[ 21.563854] [IGT] core_auth: starting subtest getclient-master-drop
11273 01:17:35.589428 8-ga44ebfe (aarc<14>[ 21.571973] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11274 01:17:35.596033 h64) (Linux: 6.1<14>[ 21.580624] [IGT] core_auth: exiting, ret=0
11275 01:17:35.596595 .86-cip19 aarch64)
11276 01:17:35.609670 Using IGT_SRANDOM=1713835055 for randomisati<8>[ 21.591183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11277 01:17:35.610180 on
11278 01:17:35.610799 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11280 01:17:35.612243 Starting subtest: getclient-master-drop
11281 01:17:35.616114 Opened device: /dev/dri/card0
11282 01:17:35.619486 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11283 01:17:35.626634 <14>[ 21.613047] [IGT] core_auth: executing
11284 01:17:35.633085 IGT-Version: 1.2<14>[ 21.617543] [IGT] core_auth: starting subtest basic-auth
11285 01:17:35.639217 8-ga44ebfe (aarc<14>[ 21.624542] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11286 01:17:35.645981 h64) (Linux: 6.1<14>[ 21.632482] [IGT] core_auth: exiting, ret=0
11287 01:17:35.649276 .86-cip19 aarch64)
11288 01:17:35.655747 Using IGT_SRANDOM=1713835055<8>[ 21.642469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11289 01:17:35.656024 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11291 01:17:35.659260 for randomisation
11292 01:17:35.662315 Opened device: /dev/dri/card0
11293 01:17:35.665916 Starting subtest: basic-auth
11294 01:17:35.669126 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11295 01:17:35.676303 <14>[ 21.663206] [IGT] core_auth: executing
11296 01:17:35.682702 IGT-Version: 1.2<14>[ 21.667624] [IGT] core_auth: starting subtest many-magics
11297 01:17:35.686249 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11298 01:17:35.696402 Using IGT_SRANDOM=1713835055 for randomisati<14>[ 21.681897] [IGT] core_auth: finished subtest many-magics, SUCCESS
11299 01:17:35.699440 on
11300 01:17:35.702674 Opened devic<14>[ 21.689517] [IGT] core_auth: exiting, ret=0
11301 01:17:35.705884 e: /dev/dri/card0
11302 01:17:35.715669 Starting subtest: many-magics<8>[ 21.699552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11303 01:17:35.715756
11304 01:17:35.715994 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11306 01:17:35.722407 Reopening device failed after <8>[ 21.707936] <LAVA_SIGNAL_TESTSET STOP>
11307 01:17:35.722486 1020 opens
11308 01:17:35.722721 Received signal: <TESTSET> STOP
11309 01:17:35.722788 Closing test_set core_auth
11310 01:17:35.725299 [1mSubtest many-magics: SUCCESS (0.007s)[0m
11311 01:17:35.754060 <14>[ 21.741403] [IGT] core_getclient: executing
11312 01:17:35.761153 IGT-Version: 1.2<14>[ 21.746286] [IGT] core_getclient: exiting, ret=0
11313 01:17:35.764391 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11314 01:17:35.774472 Using IGT_SR<8>[ 21.757794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11315 01:17:35.774904 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11317 01:17:35.778009 ANDOM=1713835055 for randomisation
11318 01:17:35.778244 Opened device: /dev/dri/card0
11319 01:17:35.781222 SUCCESS (0.006s)
11320 01:17:35.806179 <14>[ 21.792768] [IGT] core_getstats: executing
11321 01:17:35.812915 IGT-Version: 1.2<14>[ 21.797550] [IGT] core_getstats: exiting, ret=0
11322 01:17:35.815728 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11323 01:17:35.826246 Using IGT_SR<8>[ 21.809120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11324 01:17:35.827083 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11326 01:17:35.829605 ANDOM=1713835055 for randomisation
11327 01:17:35.830333 Opened device: /dev/dri/card0
11328 01:17:35.832916 SUCCESS (0.006s)
11329 01:17:35.872687 <14>[ 21.859680] [IGT] core_getversion: executing
11330 01:17:35.879283 IGT-Version: 1.2<14>[ 21.864939] [IGT] core_getversion: exiting, ret=0
11331 01:17:35.883208 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11332 01:17:35.892677 Using IGT_SR<8>[ 21.876544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11333 01:17:35.893671 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11335 01:17:35.896185 ANDOM=1713835055 for randomisation
11336 01:17:35.899706 Opened device: /dev/dri/card0
11337 01:17:35.900360 SUCCESS (0.006s)
11338 01:17:35.938178 <14>[ 21.925601] [IGT] core_setmaster_vs_auth: executing
11339 01:17:35.944845 IGT-Version: 1.2<14>[ 21.931487] [IGT] core_setmaster_vs_auth: exiting, ret=0
11340 01:17:35.952002 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11341 01:17:35.961447 Using IGT_SRANDOM=1713835055 for randomisati<8>[ 21.945406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11342 01:17:35.961555 on
11343 01:17:35.961793 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11345 01:17:35.965174 Opened device: /dev/dri/card0
11346 01:17:35.968353 SUCCESS (0.007s)
11347 01:17:35.987394 <8>[ 21.974051] <LAVA_SIGNAL_TESTSET START drm_read>
11348 01:17:35.987672 Received signal: <TESTSET> START drm_read
11349 01:17:35.987776 Starting test_set drm_read
11350 01:17:36.006954 <14>[ 21.994256] [IGT] drm_read: executing
11351 01:17:36.013618 IGT-Version: 1.2<14>[ 21.998886] [IGT] drm_read: exiting, ret=77
11352 01:17:36.017202 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11353 01:17:36.023713 Using IGT_SR<8>[ 22.009562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11354 01:17:36.023989 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11356 01:17:36.027119 ANDOM=1713835055 for randomisation
11357 01:17:36.029897 Opened device: /dev/dri/card0
11358 01:17:36.036665 No KMS driver or no outputs, pipes: 16, outputs: 0
11359 01:17:36.043571 [1mSubtest invalid-buffer: SKIP (0.000s)<14>[ 22.030531] [IGT] drm_read: executing
11360 01:17:36.043658 [0m
11361 01:17:36.047082 <14>[ 22.035465] [IGT] drm_read: exiting, ret=77
11362 01:17:36.053069 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11363 01:17:36.063333 Using IGT_SR<8>[ 22.046179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11364 01:17:36.063622 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11366 01:17:36.066278 ANDOM=1713835055 for randomisation
11367 01:17:36.066379 Opened device: /dev/dri/card0
11368 01:17:36.072949 No KMS driver or no outputs, pipes: 16, outputs: 0
11369 01:17:36.079763 [1mSubtest fault-buffer: SKIP (0.000s)[<14>[ 22.067097] [IGT] drm_read: executing
11370 01:17:36.079859 0m
11371 01:17:36.086463 IGT-Version: 1.2<14>[ 22.072624] [IGT] drm_read: exiting, ret=77
11372 01:17:36.089828 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11373 01:17:36.099744 Using IGT_SR<8>[ 22.083729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11374 01:17:36.100022 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11376 01:17:36.102760 ANDOM=1713835055 for randomisation
11377 01:17:36.102858 Opened device: /dev/dri/card0
11378 01:17:36.109361 No KMS driver or no outputs, pipes: 16, outputs: 0
11379 01:17:36.116195 [1mSubtest empty-block: SKIP (0.000s)[0<14>[ 22.104163] [IGT] drm_read: executing
11380 01:17:36.116296 m
11381 01:17:36.122470 IGT-Version: 1.2<14>[ 22.109167] [IGT] drm_read: exiting, ret=77
11382 01:17:36.126036 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11383 01:17:36.135752 Using IGT_SRANDOM=1713835055<8>[ 22.120551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11384 01:17:36.136027 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11386 01:17:36.139549 for randomisation
11387 01:17:36.142778 Opened device: /dev/dri/card0
11388 01:17:36.146151 No KMS driver or no outputs, pipes: 16, outputs: 0
11389 01:17:36.148925 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11390 01:17:36.156187 <14>[ 22.143025] [IGT] drm_read: executing
11391 01:17:36.162659 IGT-Version: 1.2<14>[ 22.147465] [IGT] drm_read: exiting, ret=77
11392 01:17:36.165985 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11393 01:17:36.172512 Using IGT_SR<8>[ 22.158326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11394 01:17:36.172773 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11396 01:17:36.175494 ANDOM=1713835056 for randomisation
11397 01:17:36.179050 Opened device: /dev/dri/card0
11398 01:17:36.185747 No KMS driver or no outputs, pipes: 16, outputs: 0
11399 01:17:36.189104 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11400 01:17:36.202078 <14>[ 22.189373] [IGT] drm_read: executing
11401 01:17:36.208816 IGT-Version: 1.2<14>[ 22.194102] [IGT] drm_read: exiting, ret=77
11402 01:17:36.212394 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11403 01:17:36.221819 Using IGT_SRANDOM=1713835056 for randomisati<8>[ 22.206750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11404 01:17:36.222077 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11406 01:17:36.225360 on
11407 01:17:36.225456 Opened device: /dev/dri/card0
11408 01:17:36.231867 No KMS driver or no outputs, pipes: 16, outputs: 0
11409 01:17:36.235195 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11410 01:17:36.243100 <14>[ 22.230069] [IGT] drm_read: executing
11411 01:17:36.249825 IGT-Version: 1.2<14>[ 22.234539] [IGT] drm_read: exiting, ret=77
11412 01:17:36.252941 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11413 01:17:36.260053 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11415 01:17:36.262792 Using IGT_SR<8>[ 22.245579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11416 01:17:36.269800 ANDOM=1713835056 for randomisati<8>[ 22.254703] <LAVA_SIGNAL_TESTSET STOP>
11417 01:17:36.269920 on
11418 01:17:36.270020 Opened device: /dev/dri/card0
11419 01:17:36.270299 Received signal: <TESTSET> STOP
11420 01:17:36.270405 Closing test_set drm_read
11421 01:17:36.276041 No KMS driver or no outputs, pipes: 16, outputs: 0
11422 01:17:36.279699 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11423 01:17:36.299818 <8>[ 22.286697] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11424 01:17:36.300407 Received signal: <TESTSET> START kms_addfb_basic
11425 01:17:36.300722 Starting test_set kms_addfb_basic
11426 01:17:36.328895 <14>[ 22.315654] [IGT] kms_addfb_basic: executing
11427 01:17:36.342151 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch6<14>[ 22.325207] [IGT] kms_addfb_basic: starting subtest unused-handle
11428 01:17:36.342549 4)
11429 01:17:36.349125 Using IGT_SR<14>[ 22.332723] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11430 01:17:36.352016 ANDOM=1713835056 for randomisation
11431 01:17:36.355059 Opened device: /dev/dri/card0
11432 01:17:36.358507 Starting subtest: unused-handle
11433 01:17:36.365178 [1mSubtest <14>[ 22.350110] [IGT] kms_addfb_basic: exiting, ret=0
11434 01:17:36.368663 unused-handle: SUCCESS (0.000s)[0m
11435 01:17:36.378361 Test requirement not met in function igt_re<8>[ 22.361958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11436 01:17:36.379030 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11438 01:17:36.381880 quire_intel, file ../lib/drmtest.c:880:
11439 01:17:36.385094 Test requirement: is_intel_device(fd)
11440 01:17:36.391782 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11441 01:17:36.394757 Test requirement: is_intel_device(fd)
11442 01:17:36.401863 No KMS driver or no outputs, pipes: 16, outputs: 0
11443 01:17:36.404934 <14>[ 22.393376] [IGT] kms_addfb_basic: executing
11444 01:17:36.418092 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch6<14>[ 22.402926] [IGT] kms_addfb_basic: starting subtest unused-pitches
11445 01:17:36.418650 4)
11446 01:17:36.428140 Using IGT_SR<14>[ 22.410521] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11447 01:17:36.431349 ANDOM=1713835056 for randomisation
11448 01:17:36.434892 Opened device: /dev/dri/card0
11449 01:17:36.435467 Starting subtest: unused-pitches
11450 01:17:36.441630 [1mSubtest<14>[ 22.427953] [IGT] kms_addfb_basic: exiting, ret=0
11451 01:17:36.445098 unused-pitches: SUCCESS (0.000s)[0m
11452 01:17:36.454923 Test requirement not met in function igt_<8>[ 22.439950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11453 01:17:36.455796 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11455 01:17:36.461596 require_intel, file ../lib/drmtest.c:880:
11456 01:17:36.464433 Test requirement: is_intel_device(fd)
11457 01:17:36.471342 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11458 01:17:36.477541 Test requirement: is_intel<14>[ 22.463883] [IGT] kms_addfb_basic: executing
11459 01:17:36.477635 _device(fd)
11460 01:17:36.484293 No KMS driver or no outputs, pipes: 16, outputs: 0
11461 01:17:36.491057 <14>[ 22.473980] [IGT] kms_addfb_basic: starting subtest unused-offsets
11462 01:17:36.491486
11463 01:17:36.497988 IGT-Version: 1.<14>[ 22.481666] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11464 01:17:36.504519 28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11465 01:17:36.510819 Using IGT_SRANDOM=1713835056 for randomisat<14>[ 22.498537] [IGT] kms_addfb_basic: exiting, ret=0
11466 01:17:36.510901 ion
11467 01:17:36.514378 Opened device: /dev/dri/card0
11468 01:17:36.517377 Starting subtest: unused-offsets
11469 01:17:36.523994 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11471 01:17:36.527589 [1mSubtes<8>[ 22.510002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11472 01:17:36.530302 t unused-offsets: SUCCESS (0.000s)[0m
11473 01:17:36.536975 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11474 01:17:36.540661 Test requirement: is_intel_device(fd)
11475 01:17:36.547090 Test requirem<14>[ 22.531845] [IGT] kms_addfb_basic: executing
11476 01:17:36.556920 ent not met in function igt_require_intel, file ../lib/drmtest.c<14>[ 22.542245] [IGT] kms_addfb_basic: starting subtest unused-modifier
11477 01:17:36.560506 :880:
11478 01:17:36.567063 Test requ<14>[ 22.550328] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11479 01:17:36.570062 irement: is_intel_device(fd)
11480 01:17:36.573159 No KMS driver or no outputs, pipes: 16, outputs: 0
11481 01:17:36.580164 IGT-Version: 1<14>[ 22.566861] [IGT] kms_addfb_basic: exiting, ret=0
11482 01:17:36.583357 .28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11483 01:17:36.593305 Using IGT_SRANDOM=17138350<8>[ 22.578300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11484 01:17:36.593599 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11486 01:17:36.596554 56 for randomisation
11487 01:17:36.600338 Opened device: /dev/dri/card0
11488 01:17:36.603364 Starting subtest: unused-modifier
11489 01:17:36.606931 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11490 01:17:36.613447 Test requirement not met in function <14>[ 22.601261] [IGT] kms_addfb_basic: executing
11491 01:17:36.619582 igt_require_intel, file ../lib/drmtest.c:880:
11492 01:17:36.626770 Test requirement:<14>[ 22.611189] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11493 01:17:36.636256 is_intel_device<14>[ 22.619173] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11494 01:17:36.636640 (fd)
11495 01:17:36.642805 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11496 01:17:36.649991 Test r<14>[ 22.636116] [IGT] kms_addfb_basic: exiting, ret=77
11497 01:17:36.653192 equirement: is_intel_device(fd)
11498 01:17:36.662712 No KMS driver or no outputs, pipes: 16, outputs<8>[ 22.647912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11499 01:17:36.663395 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11501 01:17:36.666288 : 0
11502 01:17:36.669726 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11503 01:17:36.676302 Using IGT_SRANDOM=1713835056 for randomisation
11504 01:17:36.676717 Opened device: /dev/dri/card0
11505 01:17:36.686319 Starting subtest: clobbe<14>[ 22.670399] [IGT] kms_addfb_basic: executing
11506 01:17:36.686771 rred-modifier
11507 01:17:36.699032 Test requirement not met in function igt_require_<14>[ 22.680738] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11508 01:17:36.705804 i915, file ../li<14>[ 22.689800] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11509 01:17:36.709220 b/drmtest.c:885:
11510 01:17:36.712420 Test requirement: is_i915_device(fd)
11511 01:17:36.722665 [1mSubtest clobberred-modifier: SKIP (0<14>[ 22.707127] [IGT] kms_addfb_basic: exiting, ret=77
11512 01:17:36.723087 .000s)[0m
11513 01:17:36.735465 Test requirement not met in function igt_require_intel, file ../lib/<8>[ 22.718459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11514 01:17:36.736261 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11516 01:17:36.738990 drmtest.c:880:
11517 01:17:36.742634 Test requirement: is_intel_device(fd)
11518 01:17:36.748728 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11519 01:17:36.755439 Test requirement: is_intel_device(fd)<14>[ 22.742158] [IGT] kms_addfb_basic: executing
11520 01:17:36.755862
11521 01:17:36.761990 No KMS driver or no outputs, pipes: 16, outputs: 0
11522 01:17:36.768572 IGT-Versio<14>[ 22.752327] [IGT] kms_addfb_basic: starting subtest legacy-format
11523 01:17:36.771860 n: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11524 01:17:36.781415 Using IGT_SRANDOM=1713<14>[ 22.765801] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11525 01:17:36.785100 835056 for randomisation
11526 01:17:36.788534 Opened device: /dev/dri/card0
11527 01:17:36.794983 Starting subtest: invalid-smem-bo-on-di<14>[ 22.782058] [IGT] kms_addfb_basic: exiting, ret=0
11528 01:17:36.795064 screte
11529 01:17:36.808260 Test requirement not met in function igt_require_intel, file ../lib/drmt<8>[ 22.793483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11530 01:17:36.808516 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11532 01:17:36.811164 est.c:880:
11533 01:17:36.814602 Test requirement: is_intel_device(fd)
11534 01:17:36.817965 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11535 01:17:36.827990 Test requirement not met in function igt_require_intel, file ../l<14>[ 22.816547] [IGT] kms_addfb_basic: executing
11536 01:17:36.831065 ib/drmtest.c:880:
11537 01:17:36.834645 Test requirement: is_intel_device(fd)
11538 01:17:36.840922 Test requirement not m<14>[ 22.828170] [IGT] kms_addfb_basic: starting subtest no-handle
11539 01:17:36.850828 et in function i<14>[ 22.834777] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11540 01:17:36.854611 gt_require_intel, file ../lib/drmtest.c:880:
11541 01:17:36.864383 Test requirement: is_intel_device(<14>[ 22.848953] [IGT] kms_addfb_basic: exiting, ret=0
11542 01:17:36.864471 fd)
11543 01:17:36.867586 No KMS driver or no outputs, pipes: 16, outputs: 0
11544 01:17:36.877507 IGT-Version: 1.28-ga44e<8>[ 22.861175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11545 01:17:36.877767 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11547 01:17:36.880823 bfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11548 01:17:36.884247 Using IGT_SRANDOM=1713835056 for randomisation
11549 01:17:36.887606 Opened device: /dev/dri/card0
11550 01:17:36.890566 Starting subtest: legacy-format
11551 01:17:36.897420 Successfully fuzzed<14>[ 22.883776] [IGT] kms_addfb_basic: executing
11552 01:17:36.900913 10000 {bpp, depth} variations
11553 01:17:36.903789 [1mSubtest legacy-format: SUCCESS (0.006s)[0m
11554 01:17:36.910509 <14>[ 22.895225] [IGT] kms_addfb_basic: starting subtest basic
11555 01:17:36.910591
11556 01:17:36.916975 Test requiremen<14>[ 22.901625] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11557 01:17:36.923857 t not met in function igt_require_intel, file ../lib/drmtest.c:880:
11558 01:17:36.930236 Test requir<14>[ 22.915270] [IGT] kms_addfb_basic: exiting, ret=0
11559 01:17:36.930317 ement: is_intel_device(fd)
11560 01:17:36.943743 Test requirement not met in function igt_require_int<8>[ 22.927376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11561 01:17:36.943996 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11563 01:17:36.947272 el, file ../lib/drmtest.c:880:
11564 01:17:36.950055 Test requirement: is_intel_device(fd)
11565 01:17:36.953473 No KMS driver or no outputs, pipes: 16, outputs: 0
11566 01:17:36.963487 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-c<14>[ 22.949715] [IGT] kms_addfb_basic: executing
11567 01:17:36.963569 ip19 aarch64)
11568 01:17:36.967057 Using IGT_SRANDOM=1713835056 for randomisation
11569 01:17:36.976670 Opened device: /d<14>[ 22.961277] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11570 01:17:36.976752 ev/dri/card0
11571 01:17:36.983902 St<14>[ 22.968206] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11572 01:17:36.987238 arting subtest: no-handle
11573 01:17:36.990614 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11574 01:17:36.997470 Test req<14>[ 22.982340] [IGT] kms_addfb_basic: exiting, ret=0
11575 01:17:37.003756 uirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11576 01:17:37.010257 Test<8>[ 22.994423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11577 01:17:37.011043 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11579 01:17:37.013416 requirement: is_intel_device(fd)
11580 01:17:37.020275 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11581 01:17:37.023322 Test requirement: is_intel_device(fd)
11582 01:17:37.030087 No KMS driver or n<14>[ 23.017227] [IGT] kms_addfb_basic: executing
11583 01:17:37.033083 o outputs, pipes: 16, outputs: 0
11584 01:17:37.043322 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6<14>[ 23.028971] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11585 01:17:37.053314 .1.86-cip19 aarc<14>[ 23.035763] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11586 01:17:37.053783 h64)
11587 01:17:37.056592 Using IGT_SRANDOM=1713835056 for randomisation
11588 01:17:37.062920 Opened device: /dev/dri/ca<14>[ 23.050251] [IGT] kms_addfb_basic: exiting, ret=0
11589 01:17:37.066233 rd0
11590 01:17:37.066652 Starting subtest: basic
11591 01:17:37.069864 [1mSubtest basic: SUCCESS (0.000s)[0m
11592 01:17:37.079628 Test requ<8>[ 23.062279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11593 01:17:37.080309 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11595 01:17:37.085887 irement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11596 01:17:37.089437 Test requirement: is_intel_device(fd)
11597 01:17:37.099131 Test requirement not met in function igt_require_intel, file .<14>[ 23.085041] [IGT] kms_addfb_basic: executing
11598 01:17:37.099559 ./lib/drmtest.c:880:
11599 01:17:37.102611 Test requirement: is_intel_device(fd)
11600 01:17:37.112513 No KMS driver or no<14>[ 23.096735] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11601 01:17:37.118930 outputs, pipes:<14>[ 23.103746] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11602 01:17:37.122325 16, outputs: 0
11603 01:17:37.132214 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch<14>[ 23.117994] [IGT] kms_addfb_basic: exiting, ret=0
11604 01:17:37.132645 64)
11605 01:17:37.135174 Using IGT_SRANDOM=1713835056 for randomisation
11606 01:17:37.145353 Opened device: /dev/dri/car<8>[ 23.130241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11607 01:17:37.145824 d0
11608 01:17:37.146417 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11610 01:17:37.148918 Starting subtest: bad-pitch-0
11611 01:17:37.152376 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11612 01:17:37.162274 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11613 01:17:37.165256 Test requi<14>[ 23.152546] [IGT] kms_addfb_basic: executing
11614 01:17:37.168408 rement: is_intel_device(fd)
11615 01:17:37.178295 Test requirement not met in function igt_require_in<14>[ 23.164845] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11616 01:17:37.188441 tel, file ../lib<14>[ 23.171653] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11617 01:17:37.188979 /drmtest.c:880:
11618 01:17:37.192110 Test requirement: is_intel_device(fd)
11619 01:17:37.201819 No KMS driver or no outp<14>[ 23.186035] [IGT] kms_addfb_basic: exiting, ret=0
11620 01:17:37.202246 uts, pipes: 16, outputs: 0
11621 01:17:37.214749 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-<8>[ 23.198239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11622 01:17:37.215173 cip19 aarch64)
11623 01:17:37.215766 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11625 01:17:37.221374 Using IGT_SRANDOM=1713835056 for randomisation
11626 01:17:37.221839 Opened device: /dev/dri/card0
11627 01:17:37.224970 Starting subtest: bad-pitch-32
11628 01:17:37.231467 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11629 01:17:37.237989 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11630 01:17:37.240898 Test requirem<14>[ 23.229596] [IGT] kms_addfb_basic: executing
11631 01:17:37.244490 ent: is_intel_device(fd)
11632 01:17:37.257640 Test requirement not met in function igt_require_intel, file ../lib/dr<14>[ 23.241921] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11633 01:17:37.258092 mtest.c:880:
11634 01:17:37.267330 Te<14>[ 23.249514] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11635 01:17:37.270798 st requirement: is_intel_device(fd)
11636 01:17:37.277300 No KMS driver or no outputs, pipes: 16, out<14>[ 23.264650] [IGT] kms_addfb_basic: exiting, ret=0
11637 01:17:37.280469 puts: 0
11638 01:17:37.283748 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11639 01:17:37.290706 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11641 01:17:37.294002 Usi<8>[ 23.275977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11642 01:17:37.297040 ng IGT_SRANDOM=1713835056 for randomisation
11643 01:17:37.300551 Opened device: /dev/dri/card0
11644 01:17:37.301098 Starting subtest: bad-pitch-63
11645 01:17:37.306938 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11646 01:17:37.310487 Test<14>[ 23.297712] [IGT] kms_addfb_basic: executing
11647 01:17:37.316893 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11648 01:17:37.323475 <14>[ 23.309419] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11649 01:17:37.333613 Test requirement<14>[ 23.316385] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11650 01:17:37.337075 : is_intel_device(fd)
11651 01:17:37.346462 Test requirement not met in function igt_require_intel, f<14>[ 23.330974] [IGT] kms_addfb_basic: exiting, ret=0
11652 01:17:37.346898 ile ../lib/drmtest.c:880:
11653 01:17:37.350050 Test requirement: is_intel_device(fd)
11654 01:17:37.359583 No KMS driver <8>[ 23.343127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11655 01:17:37.360289 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11657 01:17:37.363111 or no outputs, pipes: 16, outputs: 0
11658 01:17:37.369897 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11659 01:17:37.373342 Using IGT_SRANDOM=1713835057 for randomisation
11660 01:17:37.379793 Opened device: /dev/dr<14>[ 23.365759] [IGT] kms_addfb_basic: executing
11661 01:17:37.380223 i/card0
11662 01:17:37.382676 Starting subtest: bad-pitch-128
11663 01:17:37.392617 [1mSubtest bad-pitch-128: SUCCESS (0.<14>[ 23.377784] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11664 01:17:37.393059 000s)[0m
11665 01:17:37.402529 Test <14>[ 23.384796] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11666 01:17:37.409389 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11667 01:17:37.412649 T<14>[ 23.399195] [IGT] kms_addfb_basic: exiting, ret=0
11668 01:17:37.416050 est requirement: is_intel_device(fd)
11669 01:17:37.426202 Test requirement not met in function igt_r<8>[ 23.411298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11670 01:17:37.426934 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11672 01:17:37.432664 equire_intel, file ../lib/drmtest.c:880:
11673 01:17:37.435677 Test requirement: is_intel_device(fd)
11674 01:17:37.439175 No KMS driver or no outputs, pipes: 16, outputs: 0
11675 01:17:37.449161 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<14>[ 23.433988] [IGT] kms_addfb_basic: executing
11676 01:17:37.449629 : 6.1.86-cip19 aarch64)
11677 01:17:37.452041 Using IGT_SRANDOM=1713835057 for randomisation
11678 01:17:37.462165 Opened <14>[ 23.446002] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11679 01:17:37.468665 device: /dev/dri<14>[ 23.453014] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11680 01:17:37.471966 /card0
11681 01:17:37.472439 Starting subtest: bad-pitch-256
11682 01:17:37.481610 [1mSubtest bad-pitch-256: SUCCESS (0.0<14>[ 23.467671] [IGT] kms_addfb_basic: exiting, ret=0
11683 01:17:37.482032 00s)[0m
11684 01:17:37.495548 Test requirement not met in function igt_require_intel, file ../lib/dr<8>[ 23.479660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11685 01:17:37.496240 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11687 01:17:37.498317 mtest.c:880:
11688 01:17:37.501615 Test requirement: is_intel_device(fd)
11689 01:17:37.508165 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11690 01:17:37.511734 Test requirement: is_intel_device(fd)
11691 01:17:37.514899 <14>[ 23.502259] [IGT] kms_addfb_basic: executing
11692 01:17:37.521658 No KMS driver or no outputs, pipes: 16, outputs: 0
11693 01:17:37.531399 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aa<14>[ 23.516514] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11694 01:17:37.534895 rch64)
11695 01:17:37.541286 Using IG<14>[ 23.524948] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11696 01:17:37.544800 T_SRANDOM=1713835057 for randomisation
11697 01:17:37.551409 Opened d<14>[ 23.538068] [IGT] kms_addfb_basic: exiting, ret=0
11698 01:17:37.554780 evice: /dev/dri/card0
11699 01:17:37.557888 Starting subtest: bad-pitch-1024
11700 01:17:37.564355 [1mSubtest bad-pitch-1<8>[ 23.549274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11701 01:17:37.565033 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11703 01:17:37.568058 024: SUCCESS (0.000s)[0m
11704 01:17:37.574616 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11705 01:17:37.577562 Test requirement: is_intel_device(fd)
11706 01:17:37.587294 Test requirement not met i<14>[ 23.572289] [IGT] kms_addfb_basic: executing
11707 01:17:37.590807 n function igt_require_intel, file ../lib/drmtest.c:880:
11708 01:17:37.593973 Test requirement: is_intel_device(fd)
11709 01:17:37.604116 No KMS driver o<14>[ 23.586411] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11710 01:17:37.610692 r no outputs, pi<14>[ 23.594524] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11711 01:17:37.613906 pes: 16, outputs: 0
11712 01:17:37.620538 IGT-Version: 1.28-ga44ebfe <14>[ 23.607377] [IGT] kms_addfb_basic: exiting, ret=0
11713 01:17:37.623793 (aarch64) (Linux: 6.1.86-cip19 aarch64)
11714 01:17:37.633440 Using IGT_SRANDOM=1713835057 for random<8>[ 23.618508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11715 01:17:37.634170 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11717 01:17:37.637408 isation
11718 01:17:37.637881 Opened device: /dev/dri/card0
11719 01:17:37.640489 Starting subtest: bad-pitch-999
11720 01:17:37.646878 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11721 01:17:37.653207 Test requirement not met in function igt_require_intel<14>[ 23.641478] [IGT] kms_addfb_basic: executing
11722 01:17:37.656781 , file ../lib/drmtest.c:880:
11723 01:17:37.660253 Test requirement: is_intel_device(fd)
11724 01:17:37.673314 Test requirement not met in function igt_re<14>[ 23.655380] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11725 01:17:37.679921 quire_intel, fil<14>[ 23.664103] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11726 01:17:37.682904 e ../lib/drmtest.c:880:
11727 01:17:37.689596 Test requirement: is_in<14>[ 23.676991] [IGT] kms_addfb_basic: exiting, ret=0
11728 01:17:37.693002 tel_device(fd)
11729 01:17:37.696486 No KMS driver or no outputs, pipes: 16, outputs: 0
11730 01:17:37.706108 IGT-Version:<8>[ 23.688305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11731 01:17:37.706793 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11733 01:17:37.709774 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11734 01:17:37.712742 Using IGT_SRANDOM=1713835057 for randomisation
11735 01:17:37.716281 Opened device: /dev/dri/card0
11736 01:17:37.719316 Starting subtest: bad-pitch-65536
11737 01:17:37.725895 [1mSu<14>[ 23.711893] [IGT] kms_addfb_basic: executing
11738 01:17:37.729474 btest bad-pitch-65536: SUCCESS (0.000s)[0m
11739 01:17:37.742792 Test requirement not met in function igt_require_intel, file ../lib<14>[ 23.725295] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11740 01:17:37.743223 /drmtest.c:880:
11741 01:17:37.749254 <14>[ 23.733619] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11742 01:17:37.749722
11743 01:17:37.752401 Test requirement: is_intel_device(fd)
11744 01:17:37.759023 Test req<14>[ 23.746266] [IGT] kms_addfb_basic: exiting, ret=0
11745 01:17:37.765544 uirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11746 01:17:37.771891 Test<8>[ 23.757492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11747 01:17:37.772146 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11749 01:17:37.775106 requirement: is_intel_device(fd)
11750 01:17:37.781718 No KMS driver or no outputs, pipes: 16, outputs: 0
11751 01:17:37.788443 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11752 01:17:37.795118 Using IGT_SRANDOM=171<14>[ 23.779874] [IGT] kms_addfb_basic: executing
11753 01:17:37.795217 3835057 for randomisation
11754 01:17:37.798379 Opened device: /dev/dri/card0
11755 01:17:37.802000 Starting subtest: invalid-get-prop-any
11756 01:17:37.811472 [1mSubtest invalid-get-prop-a<14>[ 23.796362] [IGT] kms_addfb_basic: starting subtest master-rmfb
11757 01:17:37.817859 ny: SUCCESS (0.0<14>[ 23.803364] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11758 01:17:37.821487 00s)[0m
11759 01:17:37.828204 Test requirement not m<14>[ 23.813805] [IGT] kms_addfb_basic: exiting, ret=0
11760 01:17:37.831393 et in function igt_require_intel, file ../lib/drmtest.c:880:
11761 01:17:37.841431 Test requirement: <8>[ 23.825518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11762 01:17:37.841705 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11764 01:17:37.844519 is_intel_device(fd)
11765 01:17:37.851257 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11766 01:17:37.854345 Test requirement: is_intel_device(fd)
11767 01:17:37.861303 No KMS driver or no outputs, pip<14>[ 23.848355] [IGT] kms_addfb_basic: executing
11768 01:17:37.864645 es: 16, outputs: 0
11769 01:17:37.867779 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11770 01:17:37.874431 Using IGT_SRANDOM=1713835057 for randomisation
11771 01:17:37.881285 Opened d<14>[ 23.865767] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11772 01:17:37.891452 evice: /dev/dri/<14>[ 23.873475] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11773 01:17:37.891852 card0
11774 01:17:37.897857 Starting <14>[ 23.883192] [IGT] kms_addfb_basic: exiting, ret=0
11775 01:17:37.900842 subtest: invalid-get-prop
11776 01:17:37.903945 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11777 01:17:37.910561 T<8>[ 23.895492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11778 01:17:37.910852 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11780 01:17:37.921124 est requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11781 01:17:37.923912 Test requirement: is_intel_device(fd)
11782 01:17:37.934068 Test requirement not met in function igt_require_intel<14>[ 23.919010] [IGT] kms_addfb_basic: executing
11783 01:17:37.934207 , file ../lib/drmtest.c:880:
11784 01:17:37.937158 Test requirement: is_intel_device(fd)
11785 01:17:37.943621 No KMS driver or no outputs, pipes: 16, outputs: 0
11786 01:17:37.950591 IGT-Version: 1.28-ga44e<14>[ 23.936871] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11787 01:17:37.956718 bfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11788 01:17:37.967032 Using IGT_SRANDOM=1713835057 for ra<14>[ 23.949957] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11789 01:17:37.967234 ndomisation
11790 01:17:37.970269 Opened device: /dev/dri/card0
11791 01:17:37.973668 Starting subtest: invalid-set-prop-any
11792 01:17:37.980771 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11793 01:17:37.986789 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11794 01:17:37.989956 Test requirement: is_intel_device(fd)
11795 01:17:37.996914 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11796 01:17:38.000385 Test requirement: is_intel_device(fd)
11797 01:17:38.003267 No KMS driver or no outputs, pipes: 16, outputs: 0
11798 01:17:38.010103 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11799 01:17:38.013092 Using IGT_SRANDOM=1713835057 for randomisation
11800 01:17:38.016821 Opened device: /dev/dri/card0
11801 01:17:38.019805 Starting subtest: invalid-set-prop
11802 01:17:38.026350 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11803 01:17:38.032972 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11804 01:17:38.036622 Test requirement: is_intel_device(fd)
11805 01:17:38.043254 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11806 01:17:38.046251 Test requirement: is_intel_device(fd)
11807 01:17:38.049285 No KMS driver or no outputs, pipes: 16, outputs: 0
11808 01:17:38.056138 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11809 01:17:38.062873 Using IGT_SRANDOM=1713835057 for randomisation
11810 01:17:38.063436 Opened device: /dev/dri/card0
11811 01:17:38.065853 Starting subtest: master-rmfb
11812 01:17:38.069672 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11813 01:17:38.079550 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11814 01:17:38.082936 Test requirement: is_intel_device(fd)
11815 01:17:38.088787 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11816 01:17:38.092379 Test requirement: is_intel_device(fd)
11817 01:17:38.095234 No KMS driver or no outputs, pipes: 16, outputs: 0
11818 01:17:38.102010 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11819 01:17:38.105637 Using IGT_SRANDOM=1713835057 for randomisation
11820 01:17:38.108676 Opened device: /dev/dri/card0
11821 01:17:38.111874 Starting subtest: addfb25-modifier-no-flag
11822 01:17:38.118379 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11823 01:17:38.125066 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11824 01:17:38.128269 Test requirement: is_intel_device(fd)
11825 01:17:38.134980 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11826 01:17:38.138608 Test requirement: is_intel_device(fd)
11827 01:17:38.145270 No KMS driver or no outputs, pipes: 16, outputs: 0
11828 01:17:38.148201 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11829 01:17:38.154716 Using IGT_SRANDOM=1713835057 for randomisation
11830 01:17:38.158222 Opened device: /dev/dri/card0
11831 01:17:38.161366 Starting subtest: addfb25-bad-modifier
11832 01:17:38.171378 (kms_addfb_basic:431) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11833 01:17:38.187889 (kms_addfb_basic:431) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11834 01:17:38.191468 (kms_addfb_basic:431) CRITICAL: error: 0 != -1
11835 01:17:38.194806 Stack trace:
11836 01:17:38.198054 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11837 01:17:38.201587 #1 [<unknown>+0xb7a94358]
11838 01:17:38.202002 #2 [<unknown>+0xb7a95fbc]
11839 01:17:38.205002 #3 [<unknown>+0xb7a9156c]
11840 01:17:38.207888 #4 [__libc_init_first+0x80]
11841 01:17:38.211550 #5 [__libc_start_main+0x98]
11842 01:17:38.214634 #6 [<unknown>+0xb7a915b0]
11843 01:17:38.217785 Subtest addfb25-bad-modifier failed.
11844 01:17:38.218192 **** DEBUG ****
11845 01:17:38.227856 (kms_addfb_basic:431) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11846 01:17:38.237457 (kms_addfb_basic:431) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11847 01:17:38.254511 (kms_addfb_basic:431) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11848 01:17:38.257400 (kms_addfb_basic:431) CRITICAL: error: 0 != -1
11849 01:17:38.264495 (kms_addfb_basic:431) igt_core-INFO: Stack trace:
11850 01:17:38.271166 (kms_addfb_basic:431) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11851 01:17:38.277462 (kms_addfb_basic:431) igt_core-INFO: #1 [<unknown>+0xb7a94358]
11852 01:17:38.280700 (kms_addfb_basic:431) igt_core-INFO: #2 [<unknown>+0xb7a95fbc]
11853 01:17:38.287503 (kms_addfb_basic:431) igt_core-INFO: #3 [<unknown>+0xb7a9156c]
11854 01:17:38.294080 (kms_addfb_basic:431) igt_core-INFO: #4 [__libc_init_first+0x80]
11855 01:17:38.300576 (kms_addfb_basic:431) igt_core-INFO: #5 [__libc_start_main+0x98]
11856 01:17:38.307016 (kms_addfb_basic:431) <14>[ 24.292734] [IGT] kms_addfb_basic: exiting, ret=98
11857 01:17:38.310493 igt_core-INFO: #6 [<unknown>+0xb7a915b0]
11858 01:17:38.313374 **** END ****
11859 01:17:38.319888 [1<8>[ 24.304219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11860 01:17:38.320694 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11862 01:17:38.323776 mSubtest addfb25-bad-modifier: FAIL (0.006s)[0m
11863 01:17:38.330114 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11864 01:17:38.333401 Test requirement: is_intel_device(fd)
11865 01:17:38.340083 Tes<14>[ 24.325880] [IGT] kms_addfb_basic: executing
11866 01:17:38.346868 t requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11867 01:17:38.350053 Test requirement: is_intel_device(fd)
11868 01:17:38.359679 No KMS driver or no outputs, pipes: 16, <14>[ 24.344587] [IGT] kms_addfb_basic: exiting, ret=77
11869 01:17:38.360108 outputs: 0
11870 01:17:38.366908 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11871 01:17:38.373597 <8>[ 24.356971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11872 01:17:38.374398 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11874 01:17:38.379876 Using IGT_SRANDOM=1713835058 for randomisation
11875 01:17:38.383399 Opened device: /dev/dri/card0
11876 01:17:38.389580 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11877 01:17:38.392909 Test requirem<14>[ 24.381418] [IGT] kms_addfb_basic: executing
11878 01:17:38.396677 ent: is_intel_device(fd)
11879 01:17:38.403181 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11880 01:17:38.412756 Test requirement not met in function igt_require_intel, file ../lib/dr<14>[ 24.399548] [IGT] kms_addfb_basic: exiting, ret=77
11881 01:17:38.416295 mtest.c:880:
11882 01:17:38.419872 Test requirement: is_intel_device(fd)
11883 01:17:38.429486 No KMS driver or no outputs<8>[ 24.412008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11884 01:17:38.430075 , pipes: 16, outputs: 0
11885 01:17:38.430714 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11887 01:17:38.435841 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11888 01:17:38.439298 Using IGT_SRANDOM=1713835058 for randomisation
11889 01:17:38.445853 Opened device: /dev<14>[ 24.433630] [IGT] kms_addfb_basic: executing
11890 01:17:38.449429 /dri/card0
11891 01:17:38.456229 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11892 01:17:38.459477 Test requirement: is_intel_device(fd)
11893 01:17:38.465959 [1mSubtest addfb25-x-til<14>[ 24.451781] [IGT] kms_addfb_basic: exiting, ret=77
11894 01:17:38.468873 ed-legacy: SKIP (0.000s)[0m
11895 01:17:38.482367 Test requirement not met in function igt_require_i<8>[ 24.463692] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11896 01:17:38.483103 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11898 01:17:38.485877 ntel, file ../lib/drmtest.c:880:
11899 01:17:38.488926 Test requirement: is_intel_device(fd)
11900 01:17:38.492378 No KMS driver or no outputs, pipes: 16, outputs: 0
11901 01:17:38.499059 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11902 01:17:38.501751 Using IGT_SRANDOM=1713835058 for randomisation
11903 01:17:38.505405 Opened device: /dev/dri/card0
11904 01:17:38.508482 <14>[ 24.497167] [IGT] kms_addfb_basic: executing
11905 01:17:38.519118 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11906 01:17:38.521929 Test requirement: is_intel_device(fd)
11907 01:17:38.531608 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (<14>[ 24.516527] [IGT] kms_addfb_basic: exiting, ret=77
11908 01:17:38.532074 0.000s)[0m
11909 01:17:38.538293 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11910 01:17:38.544982 <8>[ 24.529631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11911 01:17:38.545720 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11913 01:17:38.548178
11914 01:17:38.551862 Test requirement: is_intel_device(fd)
11915 01:17:38.555118 No KMS driver or no outputs, pipes: 16, outputs: 0
11916 01:17:38.561503 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11917 01:17:38.565130 Using IGT_SRANDO<14>[ 24.552702] [IGT] kms_addfb_basic: executing
11918 01:17:38.568038 M=1713835058 for randomisation
11919 01:17:38.571440 Opened device: /dev/dri/card0
11920 01:17:38.578606 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11921 01:17:38.585172 Test requirem<14>[ 24.571540] [IGT] kms_addfb_basic: exiting, ret=77
11922 01:17:38.588491 ent: is_intel_device(fd)
11923 01:17:38.598046 Test requirement not met in function i<8>[ 24.582838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11924 01:17:38.598782 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11926 01:17:38.604925 gt_require_intel, file ../lib/drmtest.c:880:
11927 01:17:38.608114 Test requirement: is_intel_device(fd)
11928 01:17:38.611385 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11929 01:17:38.614796 No KMS driver or no outputs, pipes: 16, outputs: 0
11930 01:17:38.621405 IG<14>[ 24.607672] [IGT] kms_addfb_basic: executing
11931 01:17:38.627734 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11932 01:17:38.631327 Using IGT_SRANDOM=1713835058 for randomisation
11933 01:17:38.634984 Opened device: /dev/dri/card0
11934 01:17:38.637910 <14>[ 24.625222] [IGT] kms_addfb_basic: exiting, ret=77
11935 01:17:38.638328
11936 01:17:38.650935 Test requirement not met in function igt_require_intel, file ..<8>[ 24.635869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11937 01:17:38.651375 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11939 01:17:38.654288 /lib/drmtest.c:880:
11940 01:17:38.657454 Test requirement: is_intel_device(fd)
11941 01:17:38.664127 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11942 01:17:38.670973 Test requirement<14>[ 24.656732] [IGT] kms_addfb_basic: executing
11943 01:17:38.671155 : is_intel_device(fd)
11944 01:17:38.677466 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11945 01:17:38.680630 No KMS driver or no outputs, pipes: 16, outputs: 0
11946 01:17:38.690363 IGT-Version: 1.28-ga44ebfe <14>[ 24.674967] [IGT] kms_addfb_basic: exiting, ret=77
11947 01:17:38.693728 (aarch64) (Linux: 6.1.86-cip19 aarch64)
11948 01:17:38.700458 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11950 01:17:38.703851 Using IGT_SRANDOM=17138<8>[ 24.686688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11951 01:17:38.703933 35058 for randomisation
11952 01:17:38.706720 Opened device: /dev/dri/card0
11953 01:17:38.713773 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11954 01:17:38.720021 Test requirement: is<14>[ 24.708249] [IGT] kms_addfb_basic: executing
11955 01:17:38.723520 _intel_device(fd)
11956 01:17:38.730020 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11957 01:17:38.733532 Test requirement: is_intel_device(fd)
11958 01:17:38.740115 [1mSubtest tile-p<14>[ 24.725924] [IGT] kms_addfb_basic: exiting, ret=77
11959 01:17:38.743729 itch-mismatch: SKIP (0.000s)[0m
11960 01:17:38.753289 No KMS driver or no outputs, pipes: 16, output<8>[ 24.737837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11961 01:17:38.753372 s: 0
11962 01:17:38.753607 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11964 01:17:38.759715 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11965 01:17:38.763085 Using IGT_SRANDOM=1713835058 for randomisation
11966 01:17:38.766332 Opened device: /dev/dri/card0
11967 01:17:38.773017 Test re<14>[ 24.759444] [IGT] kms_addfb_basic: executing
11968 01:17:38.779811 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11969 01:17:38.783293 Test requirement: is_intel_device(fd)
11970 01:17:38.789657 Test requirement not met in function igt_req<14>[ 24.777029] [IGT] kms_addfb_basic: exiting, ret=77
11971 01:17:38.796284 uire_intel, file ../lib/drmtest.c:880:
11972 01:17:38.799804 Test requirement: is_intel_device(fd)
11973 01:17:38.806175 <8>[ 24.789111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11974 01:17:38.806455 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11976 01:17:38.809431 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11977 01:17:38.813077 No KMS driver or no outputs, pipes: 16, outputs: 0
11978 01:17:38.819323 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11979 01:17:38.825772 Using IGT_SRANDOM=17<14>[ 24.812901] [IGT] kms_addfb_basic: executing
11980 01:17:38.829146 13835058 for randomisation
11981 01:17:38.832728 Opened device: /dev/dri/card0
11982 01:17:38.839444 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11983 01:17:38.846081 Test requirement:<14>[ 24.831196] [IGT] kms_addfb_basic: exiting, ret=77
11984 01:17:38.846379 is_intel_device(fd)
11985 01:17:38.856289 Test requirement not met in function igt_r<8>[ 24.842828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11986 01:17:38.856965 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11988 01:17:38.862528 equire_intel, file ../lib/drmtest.c:880:
11989 01:17:38.866022 Test requirement: is_intel_device(fd)
11990 01:17:38.869209 No KMS driver or no outputs, pipes: 16, outputs: 0
11991 01:17:38.875602 [1mSubtest size-max: SKIP <14>[ 24.863249] [IGT] kms_addfb_basic: executing
11992 01:17:38.875693 (0.000s)[0m
11993 01:17:38.882706 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11994 01:17:38.885770 Using IGT_SRANDOM=1713835058 for randomisation
11995 01:17:38.888901 Opened device: /dev/dri/card0
11996 01:17:38.895702 <14>[ 24.880895] [IGT] kms_addfb_basic: exiting, ret=77
11997 01:17:38.895950
11998 01:17:38.909086 Test requirement not met in function igt_require_intel, file ..<8>[ 24.892891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11999 01:17:38.909339 /lib/drmtest.c:880:
12000 01:17:38.909709 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
12002 01:17:38.912586 Test requirement: is_intel_device(fd)
12003 01:17:38.918711 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12004 01:17:38.925584 Test requirement<14>[ 24.913235] [IGT] kms_addfb_basic: executing
12005 01:17:38.928491 : is_intel_device(fd)
12006 01:17:38.932236 No KMS driver or no outputs, pipes: 16, outputs: 0
12007 01:17:38.935667 [1mSubtest too-wide: SKIP (0.000s)[0m
12008 01:17:38.945050 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<14>[ 24.931341] [IGT] kms_addfb_basic: exiting, ret=77
12009 01:17:38.948785 6.1.86-cip19 aarch64)
12010 01:17:38.958733 Using IGT_SRANDOM=1713835058 for randomi<8>[ 24.942897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
12011 01:17:38.959229 sation
12012 01:17:38.960199 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
12014 01:17:38.962046 Opened device: /dev/dri/card0
12015 01:17:38.968761 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12016 01:17:38.975140 Test requirement: is_intel_device(fd)<14>[ 24.963547] [IGT] kms_addfb_basic: executing
12017 01:17:38.975562
12018 01:17:38.984824 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12019 01:17:38.988110 Test requirement: is_intel_device(fd)
12020 01:17:38.994737 No KMS driver or no outputs, pipes:<14>[ 24.980885] [IGT] kms_addfb_basic: exiting, ret=77
12021 01:17:38.998415 16, outputs: 0
12022 01:17:39.001806 [1mSubtest too-high: SKIP (0.000s)[0m
12023 01:17:39.007941 IGT-Ve<8>[ 24.992970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
12024 01:17:39.008617 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
12026 01:17:39.015041 rsion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12027 01:17:39.017707 Using IGT_SRANDOM=1713835058 for randomisation
12028 01:17:39.021756 Opened device: /dev/dri/card0
12029 01:17:39.031081 Test requirement not met in function igt_require_in<14>[ 25.016894] [IGT] kms_addfb_basic: executing
12030 01:17:39.034132 tel, file ../lib/drmtest.c:880:
12031 01:17:39.037852 Test requirement: is_intel_device(fd)
12032 01:17:39.044239 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12033 01:17:39.050645 Test<14>[ 25.035342] [IGT] kms_addfb_basic: exiting, ret=77
12034 01:17:39.054321 requirement: is_intel_device(fd)
12035 01:17:39.063852 No KMS driver or no outputs, <8>[ 25.046938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
12036 01:17:39.064389 pipes: 16, outputs: 0
12037 01:17:39.065221 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
12039 01:17:39.067525 [1mSubtest bo-too-small: SKIP (0.000s)[0m
12040 01:17:39.074104 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12041 01:17:39.084060 Using IGT_SRANDOM=1713835058 for randomi<14>[ 25.069752] [IGT] kms_addfb_basic: executing
12042 01:17:39.084650 sation
12043 01:17:39.086948 Opened device: /dev/dri/card0
12044 01:17:39.093669 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12045 01:17:39.100437 Test requirement: is_intel_device(fd)<14>[ 25.087874] [IGT] kms_addfb_basic: exiting, ret=77
12046 01:17:39.103857
12047 01:17:39.117138 Test requirement not met in function igt_require_intel, file .<8>[ 25.099691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
12048 01:17:39.117731 ./lib/drmtest.c:880:
12049 01:17:39.118396 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
12051 01:17:39.120147 Test requirement: is_intel_device(fd)
12052 01:17:39.127251 No KMS driver or no outputs, pipes: 16, outputs: 0
12053 01:17:39.130273 [1mSubtest small-bo: SKIP (0.000s)[0m
12054 01:17:39.133792 IGT-Ve<14>[ 25.121479] [IGT] kms_addfb_basic: executing
12055 01:17:39.140670 rsion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12056 01:17:39.143854 Using IGT_SRANDOM=1713835058 for randomisation
12057 01:17:39.146733 Opened device: /dev/dri/card0
12058 01:17:39.153237 Test requirement no<14>[ 25.139155] [IGT] kms_addfb_basic: exiting, ret=77
12059 01:17:39.160074 t met in function igt_require_intel, file ../lib/drmtest.c:880:
12060 01:17:39.167057 <8>[ 25.150777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
12061 01:17:39.167549
12062 01:17:39.167970 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
12064 01:17:39.169638 Test requirement: is_intel_device(fd)
12065 01:17:39.176277 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12066 01:17:39.186222 Test requirement: is_intel_device(fd<14>[ 25.173158] [IGT] kms_addfb_basic: executing
12067 01:17:39.186330 )
12068 01:17:39.189371 No KMS driver or no outputs, pipes: 16, outputs: 0
12069 01:17:39.196231 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
12070 01:17:39.206339 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6<14>[ 25.190577] [IGT] kms_addfb_basic: exiting, ret=77
12071 01:17:39.206449 .1.86-cip19 aarch64)
12072 01:17:39.209160 Using IGT_SRANDOM=1713835058 for randomisation
12073 01:17:39.219351 Opened dev<8>[ 25.202759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
12074 01:17:39.219749 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
12076 01:17:39.222655 Received signal: <TESTSET> STOP
12077 01:17:39.222842 Closing test_set kms_addfb_basic
12078 01:17:39.225606 ice: /dev/dri/ca<8>[ 25.212589] <LAVA_SIGNAL_TESTSET STOP>
12079 01:17:39.225765 rd0
12080 01:17:39.232427 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12081 01:17:39.235555 Test requirement: is_intel_device(fd)
12082 01:17:39.242225 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12083 01:17:39.245367 Test requirement: is_intel_device(fd)
12084 01:17:39.252186 No KMS driver or no outputs, pipes: 16, outputs: 0
12085 01:17:39.255411 Received signal: <TESTSET> START kms_atomic
12086 01:17:39.255487 Starting test_set kms_atomic
12087 01:17:39.258373 [1mSubtest addfb<8>[ 25.243572] <LAVA_SIGNAL_TESTSET START kms_atomic>
12088 01:17:39.261917 25-y-tiled-legacy: SKIP (0.000s)[0m
12089 01:17:39.265264 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12090 01:17:39.271614 Using IGT_SRANDOM=1713835058 for randomisation
12091 01:17:39.271701 Opened device: /dev/dri/card0
12092 01:17:39.281865 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12093 01:17:39.284802 Test requirement: is_intel_device(fd)
12094 01:17:39.291700 Test requirement not met in function igt_req<14>[ 25.279469] [IGT] kms_atomic: executing
12095 01:17:39.297862 uire_intel, file<14>[ 25.285091] [IGT] kms_atomic: exiting, ret=77
12096 01:17:39.301362 ../lib/drmtest.c:880:
12097 01:17:39.304296 Test requirement: is_intel_device(fd)
12098 01:17:39.311788 No KMS driver or <8>[ 25.296236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
12099 01:17:39.312467 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
12101 01:17:39.314729 no outputs, pipes: 16, outputs: 0
12102 01:17:39.321778 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
12103 01:17:39.328243 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12104 01:17:39.331754 Using IGT_SRANDOM<14>[ 25.319214] [IGT] kms_atomic: executing
12105 01:17:39.337999 =1713835059 for <14>[ 25.325218] [IGT] kms_atomic: exiting, ret=77
12106 01:17:39.341278 randomisation
12107 01:17:39.341720 Opened device: /dev/dri/card0
12108 01:17:39.351165 Test requirement n<8>[ 25.335665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
12109 01:17:39.351842 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
12111 01:17:39.358081 ot met in function igt_require_intel, file ../lib/drmtest.c:880:
12112 01:17:39.361186 Test requirement: is_intel_device(fd)
12113 01:17:39.371436 Test requirement not met in function igt_require_intel,<14>[ 25.357242] [IGT] kms_atomic: executing
12114 01:17:39.377366 file ../lib/drm<14>[ 25.362807] [IGT] kms_atomic: exiting, ret=77
12115 01:17:39.377454 test.c:880:
12116 01:17:39.380891 Test requirement: is_intel_device(fd)
12117 01:17:39.390631 No KMS drive<8>[ 25.373821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
12118 01:17:39.390875 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
12120 01:17:39.393740 r or no outputs, pipes: 16, outputs: 0
12121 01:17:39.400423 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
12122 01:17:39.407269 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 a<14>[ 25.396608] [IGT] kms_atomic: executing
12123 01:17:39.410856 arch64)
12124 01:17:39.413860 Using I<14>[ 25.401424] [IGT] kms_atomic: exiting, ret=77
12125 01:17:39.416991 GT_SRANDOM=1713835059 for randomisation
12126 01:17:39.426684 Opened device: /dev/dri<8>[ 25.412621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
12127 01:17:39.427014 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
12129 01:17:39.430305 /card0
12130 01:17:39.436519 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12131 01:17:39.440314 Test requirement: is_intel_device(fd)
12132 01:17:39.446469 Test requirement not met in function igt_requ<14>[ 25.434328] [IGT] kms_atomic: executing
12133 01:17:39.453001 ire_intel, file <14>[ 25.440477] [IGT] kms_atomic: exiting, ret=77
12134 01:17:39.456495 ../lib/drmtest.c:880:
12135 01:17:39.459940 Test requirement: is_intel_device(fd)
12136 01:17:39.466527 No<8>[ 25.451576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
12137 01:17:39.467059 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
12139 01:17:39.469548 KMS driver or no outputs, pipes: 16, outputs: 0
12140 01:17:39.473144 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
12141 01:17:39.483150 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarc<14>[ 25.471399] [IGT] kms_atomic: executing
12142 01:17:39.486049 h64)
12143 01:17:39.489400 Using IGT_<14>[ 25.476998] [IGT] kms_atomic: exiting, ret=77
12144 01:17:39.492964 SRANDOM=1713835059 for randomisation
12145 01:17:39.502889 Opened device: /dev/dri/ca<8>[ 25.488133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
12146 01:17:39.503301 rd0
12147 01:17:39.503882 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
12149 01:17:39.509398 No KMS driver or no outputs, pipes: 16, outputs: 0
12150 01:17:39.512821 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
12151 01:17:39.522861 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.8<14>[ 25.509138] [IGT] kms_atomic: executing
12152 01:17:39.529289 6-cip19 aarch64)<14>[ 25.514447] [IGT] kms_atomic: exiting, ret=77
12153 01:17:39.529674
12154 01:17:39.532787 Using IGT_SRANDOM=1713835059 for randomisation
12155 01:17:39.535996 Opened device: /dev/dri/card0
12156 01:17:39.542534 <8>[ 25.526337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
12157 01:17:39.542826
12158 01:17:39.543298 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
12160 01:17:39.545915 No KMS driver or no outputs, pipes: 16, outputs: 0
12161 01:17:39.552113 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
12162 01:17:39.558976 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-ci<14>[ 25.548385] [IGT] kms_atomic: executing
12163 01:17:39.561966 p19 aarch64)
12164 01:17:39.565498 Us<14>[ 25.553392] [IGT] kms_atomic: exiting, ret=77
12165 01:17:39.572190 ing IGT_SRANDOM=1713835059 for randomisation
12166 01:17:39.578834 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12168 01:17:39.582255 Opened device: /de<8>[ 25.563722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
12169 01:17:39.582337 v/dri/card0
12170 01:17:39.585186 No KMS driver or no outputs, pipes: 16, outputs: 0
12171 01:17:39.592242 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
12172 01:17:39.598675 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12173 01:17:39.601791 Using IGT_SRANDOM=1713835059 for randomisation
12174 01:17:39.605519 Opened device: /dev/dri/card0
12175 01:17:39.608496 No KMS dr<14>[ 25.597464] [IGT] kms_atomic: executing
12176 01:17:39.615428 iver or no outpu<14>[ 25.602896] [IGT] kms_atomic: exiting, ret=77
12177 01:17:39.618516 ts, pipes: 16, outputs: 0
12178 01:17:39.628275 [1mSubtest plane-immutable-zpos: SKI<8>[ 25.613541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12179 01:17:39.628611 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12181 01:17:39.632044 P (0.000s)[0m
12182 01:17:39.635249 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12183 01:17:39.641978 Using IGT_SRANDOM=1713835059 for randomisation
12184 01:17:39.642179 Opened device: /dev/dri/card0
12185 01:17:39.648048 No KMS driver<14>[ 25.635697] [IGT] kms_atomic: executing
12186 01:17:39.654901 or no outputs, <14>[ 25.641325] [IGT] kms_atomic: exiting, ret=77
12187 01:17:39.658513 pipes: 16, outputs: 0
12188 01:17:39.661624 [1mSubtest test-only: SKIP (0.000s)[0m
12189 01:17:39.667994 IGT-Version: 1.<8>[ 25.652680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12190 01:17:39.668809 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12192 01:17:39.675014 28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12193 01:17:39.678057 Using IGT_SRANDOM=1713835059 for randomisation
12194 01:17:39.681706 Opened device: /dev/dri/card0
12195 01:17:39.688463 No KMS driver or no outputs,<14>[ 25.675606] [IGT] kms_atomic: executing
12196 01:17:39.694773 pipes: 16, outp<14>[ 25.680669] [IGT] kms_atomic: exiting, ret=77
12197 01:17:39.695352 uts: 0
12198 01:17:39.697811 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12199 01:17:39.707707 IGT-Version: 1.28-ga<8>[ 25.692011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12200 01:17:39.708441 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12202 01:17:39.714694 44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12203 01:17:39.717790 Using IGT_SRANDOM=1713835059 for randomisation
12204 01:17:39.721028 Opened device: /dev/dri/card0
12205 01:17:39.724593 No KMS driver or no outputs, pipes: 16, outputs: 0
12206 01:17:39.731184 [1mSubtest plane-invalid-par<14>[ 25.717938] [IGT] kms_atomic: executing
12207 01:17:39.737740 ams: SKIP (0.000<14>[ 25.723886] [IGT] kms_atomic: exiting, ret=77
12208 01:17:39.738402 s)[0m
12209 01:17:39.750860 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip1<8>[ 25.735099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12210 01:17:39.751326 9 aarch64)
12211 01:17:39.751937 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12213 01:17:39.757423 Using IGT_SRANDOM=17<8>[ 25.744236] <LAVA_SIGNAL_TESTSET STOP>
12214 01:17:39.758198 Received signal: <TESTSET> STOP
12215 01:17:39.758560 Closing test_set kms_atomic
12216 01:17:39.761244 13835059 for randomisation
12217 01:17:39.761748 Opened device: /dev/dri/card0
12218 01:17:39.767636 No KMS driver or no outputs, pipes: 16, outputs: 0
12219 01:17:39.770675 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
12220 01:17:39.777642 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12221 01:17:39.780422 Using IGT_SRANDOM=1713835059 for randomisation
12222 01:17:39.784262 Opened device: /dev/dri/card0
12223 01:17:39.791006 No <8>[ 25.776730] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12224 01:17:39.791737 Received signal: <TESTSET> START kms_flip_event_leak
12225 01:17:39.792289 Starting test_set kms_flip_event_leak
12226 01:17:39.793588 KMS driver or no outputs, pipes: 16, outputs: 0
12227 01:17:39.800527 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12228 01:17:39.807068 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12229 01:17:39.810525 Using IGT_SRANDOM=1713835059 for randomisation
12230 01:17:39.813828 Opened device: /dev/dri/card0
12231 01:17:39.816863 No KMS driver or no outputs, pipes: 16, outputs: 0
12232 01:17:39.823834 [1mSubtest crtc-invalid-params-fenc<14>[ 25.811685] [IGT] kms_flip_event_leak: executing
12233 01:17:39.833532 e: SKIP (0.000s)<14>[ 25.818171] [IGT] kms_flip_event_leak: exiting, ret=77
12234 01:17:39.834034 [0m
12235 01:17:39.843844 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 <8>[ 25.829728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12236 01:17:39.844427 aarch64)
12237 01:17:39.845082 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12239 01:17:39.850079 Using IGT_SRANDOM=1713<8>[ 25.837743] <LAVA_SIGNAL_TESTSET STOP>
12240 01:17:39.850739 Received signal: <TESTSET> STOP
12241 01:17:39.851125 Closing test_set kms_flip_event_leak
12242 01:17:39.853256 835059 for randomisation
12243 01:17:39.856546 Opened device: /dev/dri/card0
12244 01:17:39.859925 No KMS driver or no outputs, pipes: 16, outputs: 0
12245 01:17:39.866492 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
12246 01:17:39.873379 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: <8>[ 25.860559] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12247 01:17:39.873860 Received signal: <TESTSET> START kms_prop_blob
12248 01:17:39.874072 Starting test_set kms_prop_blob
12249 01:17:39.876361 6.1.86-cip19 aarch64)
12250 01:17:39.879446 Using IGT_SRANDOM=1713835059 for randomisation
12251 01:17:39.883042 Opened device: /dev/dri/card0
12252 01:17:39.886490 No KMS driver or no outputs, pipes: 16, outputs: 0
12253 01:17:39.892809 [1mSu<14>[ 25.879996] [IGT] kms_prop_blob: executing
12254 01:17:39.899790 btest atomic-pla<14>[ 25.885331] [IGT] kms_prop_blob: starting subtest basic
12255 01:17:39.905903 ne-damage: SKIP <14>[ 25.892000] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12256 01:17:39.909471 (0.000s)[0m
12257 01:17:39.912999 IG<14>[ 25.899819] [IGT] kms_prop_blob: exiting, ret=0
12258 01:17:39.925756 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)<8>[ 25.911349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12259 01:17:39.925979
12260 01:17:39.926379 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12262 01:17:39.929690 Using IGT_SRANDOM=1713835059 for randomisation
12263 01:17:39.932506 Opened device: /dev/dri/card0
12264 01:17:39.935688 No KMS driver or no outputs, pipes: 16, outputs: 0
12265 01:17:39.945347 [1mSubtest basic: SKIP (0.<14>[ 25.930999] [IGT] kms_prop_blob: executing
12266 01:17:39.945584 000s)[0m
12267 01:17:39.952171 IGT-V<14>[ 25.936873] [IGT] kms_prop_blob: starting subtest blob-prop-core
12268 01:17:39.958821 ersion: 1.28-ga4<14>[ 25.944291] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12269 01:17:39.965483 4ebfe (aarch64) <14>[ 25.952886] [IGT] kms_prop_blob: exiting, ret=0
12270 01:17:39.969057 (Linux: 6.1.86-cip19 aarch64)
12271 01:17:39.979146 Using IGT_SRANDOM=1713835059 for <8>[ 25.964393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12272 01:17:39.979979 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12274 01:17:39.981965 randomisation
12275 01:17:39.982417 Opened device: /dev/dri/card0
12276 01:17:39.985902 Starting subtest: basic
12277 01:17:39.988853 [1mSubtest basic: SUCCESS (0.000s)[0m
12278 01:17:39.995357 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12279 01:17:40.001781 Using IGT_SR<14>[ 25.987621] [IGT] kms_prop_blob: executing
12280 01:17:40.008452 ANDOM=1713835059<14>[ 25.993319] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12281 01:17:40.018623 for randomisati<14>[ 26.001261] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12282 01:17:40.019084 on
12283 01:17:40.025170 Opened devic<14>[ 26.010157] [IGT] kms_prop_blob: exiting, ret=0
12284 01:17:40.025677 e: /dev/dri/card0
12285 01:17:40.028650 Starting subtest: blob-prop-core
12286 01:17:40.038310 [1mSubtest<8>[ 26.021628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12287 01:17:40.039043 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12289 01:17:40.041931 blob-prop-core: SUCCESS (0.000s)[0m
12290 01:17:40.044930 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12291 01:17:40.051586 Using IGT_SRANDOM=1713835059 for randomisation
12292 01:17:40.055060 Opene<14>[ 26.043145] [IGT] kms_prop_blob: executing
12293 01:17:40.064980 d device: /dev/d<14>[ 26.048226] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12294 01:17:40.065396 ri/card0
12295 01:17:40.071635 Starti<14>[ 26.056174] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12296 01:17:40.078165 ng subtest: blob<14>[ 26.065013] [IGT] kms_prop_blob: exiting, ret=0
12297 01:17:40.081468 -prop-validate
12298 01:17:40.091525 [1mSubtest blob-prop-validate: SUCCESS (0.000s)<8>[ 26.076462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12299 01:17:40.092088 [0m
12300 01:17:40.092733 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12302 01:17:40.097964 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12303 01:17:40.101340 Using IGT_SRANDOM=1713835059 for randomisation
12304 01:17:40.104745 Opened device: /dev/dri/card0
12305 01:17:40.110982 Startin<14>[ 26.097754] [IGT] kms_prop_blob: executing
12306 01:17:40.117612 g subtest: blob-<14>[ 26.103145] [IGT] kms_prop_blob: starting subtest blob-multiple
12307 01:17:40.121068 prop-lifetime
12308 01:17:40.127678 <14>[ 26.110641] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12309 01:17:40.134434 [1mSubtest blob-<14>[ 26.119152] [IGT] kms_prop_blob: exiting, ret=0
12310 01:17:40.138050 prop-lifetime: SUCCESS (0.000s)[0m
12311 01:17:40.143890 IGT-Version: 1.28-ga44ebfe <8>[ 26.130543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12312 01:17:40.144622 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12314 01:17:40.150863 (aarch64) (Linux: 6.1.86-cip19 aarch64)
12315 01:17:40.154037 Using IGT_SRANDOM=1713835059 for randomisation
12316 01:17:40.157359 Opened device: /dev/dri/card0
12317 01:17:40.160856 Starting subtest: blob-multiple
12318 01:17:40.163925 [1mSub<14>[ 26.151421] [IGT] kms_prop_blob: executing
12319 01:17:40.173664 test blob-multip<14>[ 26.156647] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12320 01:17:40.180636 le: SUCCESS (0.0<14>[ 26.164681] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12321 01:17:40.183914 00s)[0m
12322 01:17:40.187123 IGT-Ve<14>[ 26.173829] [IGT] kms_prop_blob: exiting, ret=0
12323 01:17:40.194119 rsion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12324 01:17:40.200038 Us<8>[ 26.185239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12325 01:17:40.200799 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12327 01:17:40.203699 ing IGT_SRANDOM=1713835060 for randomisation
12328 01:17:40.207364 Opened device: /dev/dri/card0
12329 01:17:40.210058 Starting subtest: invalid-get-prop-any
12330 01:17:40.216592 [1mSubtest invalid-get-pro<14>[ 26.205510] [IGT] kms_prop_blob: executing
12331 01:17:40.226835 p-any: SUCCESS (<14>[ 26.210667] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12332 01:17:40.227309 0.000s)[0m
12333 01:17:40.233444 IGT<14>[ 26.218304] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12334 01:17:40.239919 -Version: 1.28-g<14>[ 26.227064] [IGT] kms_prop_blob: exiting, ret=0
12335 01:17:40.246482 a44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12336 01:17:40.253756 Using IGT_SRAND<8>[ 26.238434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12337 01:17:40.254586 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12339 01:17:40.256468 OM=1713835060 for randomisation
12340 01:17:40.260245 Opened device: /dev/dri/card0
12341 01:17:40.263232 Starting subtest: invalid-get-prop
12342 01:17:40.266341 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12343 01:17:40.282878 <14>[ 26.269721] [IGT] kms_prop_blob: executing
12344 01:17:40.289861 IGT-Version: 1.2<14>[ 26.274918] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12345 01:17:40.299474 8-ga44ebfe (aarc<14>[ 26.282882] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12346 01:17:40.306178 h64) (Linux: 6.1<14>[ 26.291983] [IGT] kms_prop_blob: exiting, ret=0
12347 01:17:40.309203 .86-cip19 aarch64)
12348 01:17:40.319231 Using IGT_SRANDOM=1713835060 for randomisati<8>[ 26.303502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12349 01:17:40.319793 on
12350 01:17:40.320488 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12352 01:17:40.322245 Opened device: /dev/dri/card0
12353 01:17:40.325603 Starting subtest: invalid-set-prop-any
12354 01:17:40.332646 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12355 01:17:40.349454 <14>[ 26.336125] [IGT] kms_prop_blob: executing
12356 01:17:40.355730 IGT-Version: 1.2<14>[ 26.341146] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12357 01:17:40.365586 8-ga44ebfe (aarc<14>[ 26.348882] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12358 01:17:40.371923 h64) (Linux: 6.1<14>[ 26.357634] [IGT] kms_prop_blob: exiting, ret=0
12359 01:17:40.372617 .86-cip19 aarch64)
12360 01:17:40.378908 Using IGT_SRANDOM=1713835060 for randomisation
12361 01:17:40.385252 Opened devic<8>[ 26.369802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12362 01:17:40.386131 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12364 01:17:40.389436 e: /dev/dri/card0
12365 01:17:40.392213 Starting subt<8>[ 26.379740] <LAVA_SIGNAL_TESTSET STOP>
12366 01:17:40.392998 Received signal: <TESTSET> STOP
12367 01:17:40.393394 Closing test_set kms_prop_blob
12368 01:17:40.395415 est: invalid-set-prop
12369 01:17:40.398556 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12370 01:17:40.424883 <8>[ 26.411870] <LAVA_SIGNAL_TESTSET START kms_setmode>
12371 01:17:40.425730 Received signal: <TESTSET> START kms_setmode
12372 01:17:40.426126 Starting test_set kms_setmode
12373 01:17:40.459432 <14>[ 26.446259] [IGT] kms_setmode: executing
12374 01:17:40.465911 IGT-Version: 1.2<14>[ 26.451297] [IGT] kms_setmode: starting subtest basic
12375 01:17:40.472605 8-ga44ebfe (aarc<14>[ 26.457747] [IGT] kms_setmode: finished subtest basic, SKIP
12376 01:17:40.479363 h64) (Linux: 6.1<14>[ 26.465103] [IGT] kms_setmode: exiting, ret=77
12377 01:17:40.482362 .86-cip19 aarch64)
12378 01:17:40.485934 Using IGT_SRANDOM=1713835060 for randomisation
12379 01:17:40.492302 Opened devic<8>[ 26.477370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12380 01:17:40.493158 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12382 01:17:40.495338 e: /dev/dri/card0
12383 01:17:40.495790 Starting subtest: basic
12384 01:17:40.498632 No dynamic tests executed.
12385 01:17:40.501623 [1mSubtest basic: SKIP (0.000s)[0m
12386 01:17:40.513954 <14>[ 26.500442] [IGT] kms_setmode: executing
12387 01:17:40.520069 IGT-Version: 1.2<14>[ 26.505098] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12388 01:17:40.530081 8-ga44ebfe (aarc<14>[ 26.513329] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12389 01:17:40.536863 h64) (Linux: 6.1<14>[ 26.522205] [IGT] kms_setmode: exiting, ret=77
12390 01:17:40.537422 .86-cip19 aarch64)
12391 01:17:40.549627 Using IGT_SRANDOM=1713835060 for randomisati<8>[ 26.533671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12392 01:17:40.550186 on
12393 01:17:40.550858 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12395 01:17:40.553257 Opened device: /dev/dri/card0
12396 01:17:40.556345 Starting subtest: basic-clone-single-crtc
12397 01:17:40.559498 No dynamic tests executed.
12398 01:17:40.569500 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m<14>[ 26.555474] [IGT] kms_setmode: executing
12399 01:17:40.570095
12400 01:17:40.576093 IGT-Version: 1.2<14>[ 26.560470] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12401 01:17:40.586418 <14>[ 26.568906] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12402 01:17:40.589458 8-ga44ebfe (aarc<14>[ 26.576627] [IGT] kms_setmode: exiting, ret=77
12403 01:17:40.592394 h64) (Linux: 6.1.86-cip19 aarch64)
12404 01:17:40.605742 Using IGT_SRANDOM=1713835060<8>[ 26.587980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12405 01:17:40.606295 for randomisation
12406 01:17:40.606933 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12408 01:17:40.609321 Opened device: /dev/dri/card0
12409 01:17:40.612930 Starting subtest: invalid-clone-single-crtc
12410 01:17:40.615665 No dynamic tests executed.
12411 01:17:40.622161 [1mSubtest invalid-clone-single-crt<14>[ 26.610387] [IGT] kms_setmode: executing
12412 01:17:40.632157 c: SKIP (0.000s)<14>[ 26.615261] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12413 01:17:40.632713 [0m
12414 01:17:40.642443 IGT-Versio<14>[ 26.623641] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12415 01:17:40.645444 n: 1.28-ga44ebfe<14>[ 26.633140] [IGT] kms_setmode: exiting, ret=77
12416 01:17:40.652172 (aarch64) (Linux: 6.1.86-cip19 aarch64)
12417 01:17:40.661894 Using IGT_SRANDOM=1713<8>[ 26.644329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12418 01:17:40.662443 835060 for randomisation
12419 01:17:40.663091 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12421 01:17:40.665379 Opened device: /dev/dri/card0
12422 01:17:40.668775 Starting subtest: invalid-clone-exclusive-crtc
12423 01:17:40.672201 No dynamic tests executed.
12424 01:17:40.679063 [1mSubtest invalid-clone-e<14>[ 26.666545] [IGT] kms_setmode: executing
12425 01:17:40.688752 xclusive-crtc: S<14>[ 26.671910] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12426 01:17:40.695428 KIP (0.000s)[0m<14>[ 26.679685] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12427 01:17:40.695998
12428 01:17:40.701851 IGT-Version: 1<14>[ 26.688279] [IGT] kms_setmode: exiting, ret=77
12429 01:17:40.708608 .28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12430 01:17:40.714887 Using IGT_<8>[ 26.699765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12431 01:17:40.715756 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12433 01:17:40.718317 SRANDOM=1713835060 for randomisation
12434 01:17:40.721589 Opened device: /dev/dri/card0
12435 01:17:40.725286 Starting subtest: clone-exclusive-crtc
12436 01:17:40.728134 No dynamic tests executed.
12437 01:17:40.731457 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12438 01:17:40.742861 <14>[ 26.730133] [IGT] kms_setmode: executing
12439 01:17:40.752756 IGT-Version: 1.2<14>[ 26.735477] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12440 01:17:40.762828 8-ga44ebfe (aarc<14>[ 26.744196] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12441 01:17:40.769674 h64) (Linux: 6.1<14>[ 26.754124] [IGT] kms_setmode: exiting, ret=77
12442 01:17:40.770224 .86-cip19 aarch64)
12443 01:17:40.772721 Using IGT_SRANDOM=1713835060 for randomisation
12444 01:17:40.782471 Opened devic<8>[ 26.766846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12445 01:17:40.783326 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12447 01:17:40.786062 e: /dev/dri/card0
12448 01:17:40.789010 Starting subt<8>[ 26.777670] <LAVA_SIGNAL_TESTSET STOP>
12449 01:17:40.789724 Received signal: <TESTSET> STOP
12450 01:17:40.790109 Closing test_set kms_setmode
12451 01:17:40.795510 est: invalid-clone-single-crtc-stealing
12452 01:17:40.795978 No dynamic tests executed.
12453 01:17:40.802385 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12454 01:17:40.823098 <8>[ 26.810352] <LAVA_SIGNAL_TESTSET START kms_vblank>
12455 01:17:40.823911 Received signal: <TESTSET> START kms_vblank
12456 01:17:40.824299 Starting test_set kms_vblank
12457 01:17:40.842056 <14>[ 26.829173] [IGT] kms_vblank: executing
12458 01:17:40.848733 IGT-Version: 1.2<14>[ 26.833827] [IGT] kms_vblank: exiting, ret=77
12459 01:17:40.852398 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12460 01:17:40.858397 Using IGT_SR<8>[ 26.843947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12461 01:17:40.859230 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12463 01:17:40.861857 ANDOM=1713835060 for randomisation
12464 01:17:40.864908 Opened device: /dev/dri/card0
12465 01:17:40.868406 No KMS driver or no outputs, pipes: 16, outputs: 0
12466 01:17:40.874881 [1mSubtest invalid: SKIP (0.000s)[0m
12467 01:17:40.878376 <14>[ 26.865078] [IGT] kms_vblank: executing
12468 01:17:40.885286 IGT-Version: 1.2<14>[ 26.870322] [IGT] kms_vblank: exiting, ret=77
12469 01:17:40.887886 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12470 01:17:40.895130 Using IGT_SR<8>[ 26.880487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12471 01:17:40.895960 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12473 01:17:40.898171 ANDOM=1713835060 for randomisation
12474 01:17:40.901189 Opened device: /dev/dri/card0
12475 01:17:40.907921 No KMS driver or no outputs, pipes: 16, outputs: 0
12476 01:17:40.911477 [1mSubtest crtc-id: SKIP (0.000s)[0m
12477 01:17:40.914362 <14>[ 26.901844] [IGT] kms_vblank: executing
12478 01:17:40.921177 IGT-Version: 1.2<14>[ 26.906988] [IGT] kms_vblank: exiting, ret=77
12479 01:17:40.924742 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12480 01:17:40.932140 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12482 01:17:40.934535 Using IGT_SR<8>[ 26.917066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12483 01:17:40.937779 ANDOM=1713835060 for randomisation
12484 01:17:40.938332 Opened device: /dev/dri/card0
12485 01:17:40.944532 No KMS driver or no outputs, pipes: 16, outputs: 0
12486 01:17:40.951340 [1mSubtest accuracy-idle: SKIP (0.000s)<14>[ 26.938605] [IGT] kms_vblank: executing
12487 01:17:40.951834 [0m
12488 01:17:40.957971 <14>[ 26.943903] [IGT] kms_vblank: exiting, ret=77
12489 01:17:40.967786 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch6<8>[ 26.953282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12490 01:17:40.968371 4)
12491 01:17:40.969017 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12493 01:17:40.974738 Using IGT_SRANDOM=1713835060 for randomisation
12494 01:17:40.977777 Opened device: /dev/dri/card0
12495 01:17:40.981349 No KMS driver or no outputs, pipes: 16, outputs: 0
12496 01:17:40.987829 [1mSubtest query-idle: S<14>[ 26.974772] [IGT] kms_vblank: executing
12497 01:17:40.994334 KIP (0.000s)[0m<14>[ 26.979650] [IGT] kms_vblank: exiting, ret=77
12498 01:17:40.994888
12499 01:17:41.007352 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarc<8>[ 26.990111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12500 01:17:41.007895 h64)
12501 01:17:41.008525 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12503 01:17:41.010338 Using IGT_SRANDOM=1713835060 for randomisation
12504 01:17:41.013937 Opened device: /dev/dri/card0
12505 01:17:41.016956 No KMS driver or no outputs, pipes: 16, outputs: 0
12506 01:17:41.023650 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12507 01:17:41.035253 <14>[ 27.022606] [IGT] kms_vblank: executing
12508 01:17:41.042343 IGT-Version: 1.2<14>[ 27.027682] [IGT] kms_vblank: exiting, ret=77
12509 01:17:41.045289 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12510 01:17:41.055274 Using IGT_SRANDOM=1713835060 for randomisati<8>[ 27.041219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12511 01:17:41.055817 on
12512 01:17:41.056449 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12514 01:17:41.058888 Opened device: /dev/dri/card0
12515 01:17:41.065222 No KMS driver or no outputs, pipes: 16, outputs: 0
12516 01:17:41.068774 [1mSubtest query-forked: SKIP (0.000s)[0m
12517 01:17:41.077507 <14>[ 27.064366] [IGT] kms_vblank: executing
12518 01:17:41.084355 IGT-Version: 1.2<14>[ 27.069007] [IGT] kms_vblank: exiting, ret=77
12519 01:17:41.087354 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12520 01:17:41.097040 Using IGT_SR<8>[ 27.080223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12521 01:17:41.097924 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12523 01:17:41.100597 ANDOM=1713835060 for randomisation
12524 01:17:41.101050 Opened device: /dev/dri/card0
12525 01:17:41.106931 No KMS driver or no outputs, pipes: 16, outputs: 0
12526 01:17:41.110180 [1mSubtest query-forked-hang: SKIP (0.000s)[0m
12527 01:17:41.116969 <14>[ 27.103507] [IGT] kms_vblank: executing
12528 01:17:41.123557 IGT-Version: 1.2<14>[ 27.108259] [IGT] kms_vblank: exiting, ret=77
12529 01:17:41.127100 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12530 01:17:41.133913 Using IGT_SR<8>[ 27.119454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12531 01:17:41.134751 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12533 01:17:41.136635 ANDOM=1713835060 for randomisation
12534 01:17:41.139954 Opened device: /dev/dri/card0
12535 01:17:41.143270 No KMS driver or no outputs, pipes: 16, outputs: 0
12536 01:17:41.147135 [1mSubtest query-busy: SKIP (0.000s)[0m
12537 01:17:41.154492 <14>[ 27.141802] [IGT] kms_vblank: executing
12538 01:17:41.161290 IGT-Version: 1.2<14>[ 27.146472] [IGT] kms_vblank: exiting, ret=77
12539 01:17:41.164688 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12540 01:17:41.174707 Using IGT_SRANDOM=1713835061<8>[ 27.158463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12541 01:17:41.175424 for randomisation
12542 01:17:41.176137 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12544 01:17:41.177869 Opened device: /dev/dri/card0
12545 01:17:41.184712 No KMS driver or no outputs, pipes: 16, outputs: 0
12546 01:17:41.187456 [1mSubtest query-busy-hang: SKIP (0.000s)[0m
12547 01:17:41.191406 <14>[ 27.180082] [IGT] kms_vblank: executing
12548 01:17:41.197678 IGT-Version: 1.2<14>[ 27.184814] [IGT] kms_vblank: exiting, ret=77
12549 01:17:41.204050 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12550 01:17:41.210570 Using IGT_SR<8>[ 27.196060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12551 01:17:41.211294 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12553 01:17:41.214107 ANDOM=1713835061 for randomisation
12554 01:17:41.217441 Opened device: /dev/dri/card0
12555 01:17:41.221025 No KMS driver or no outputs, pipes: 16, outputs: 0
12556 01:17:41.227494 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12557 01:17:41.230740 <14>[ 27.219511] [IGT] kms_vblank: executing
12558 01:17:41.237317 IGT-Version: 1.2<14>[ 27.224144] [IGT] kms_vblank: exiting, ret=77
12559 01:17:41.240955 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12560 01:17:41.250815 Using IGT_SR<8>[ 27.235338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12561 01:17:41.251658 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12563 01:17:41.253946 ANDOM=1713835061 for randomisation
12564 01:17:41.257592 Opened device: /dev/dri/card0
12565 01:17:41.260269 No KMS driver or no outputs, pipes: 16, outputs: 0
12566 01:17:41.266884 [1mSubtest query-forked-busy-hang: SKIP (0.000s)[0m
12567 01:17:41.270361 <14>[ 27.259416] [IGT] kms_vblank: executing
12568 01:17:41.276988 IGT-Version: 1.2<14>[ 27.264084] [IGT] kms_vblank: exiting, ret=77
12569 01:17:41.283997 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12570 01:17:41.290342 Using IGT_SR<8>[ 27.275331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12571 01:17:41.291017 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12573 01:17:41.293447 ANDOM=1713835061 for randomisation
12574 01:17:41.296940 Opened device: /dev/dri/card0
12575 01:17:41.300052 No KMS driver or no outputs, pipes: 16, outputs: 0
12576 01:17:41.303472 [1mSubtest wait-idle: SKIP (0.000s)[0m
12577 01:17:41.306859 <14>[ 27.295858] [IGT] kms_vblank: executing
12578 01:17:41.307283
12579 01:17:41.313593 IGT-Version: 1.2<14>[ 27.300821] [IGT] kms_vblank: exiting, ret=77
12580 01:17:41.320047 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12581 01:17:41.326655 Using IGT_SR<8>[ 27.312039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12582 01:17:41.327589 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12584 01:17:41.329984 ANDOM=1713835061 for randomisation
12585 01:17:41.333184 Opened device: /dev/dri/card0
12586 01:17:41.336270 No KMS driver or no outputs, pipes: 16, outputs: 0
12587 01:17:41.346728 [1mSubtest wait-idle-hang: SKIP (0.000s)<14>[ 27.332884] [IGT] kms_vblank: executing
12588 01:17:41.347227 [0m
12589 01:17:41.349673 <14>[ 27.337912] [IGT] kms_vblank: exiting, ret=77
12590 01:17:41.363096 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch6<8>[ 27.348184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12591 01:17:41.363608 4)
12592 01:17:41.364212 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12594 01:17:41.366004 Using IGT_SRANDOM=1713835061 for randomisation
12595 01:17:41.369886 Opened device: /dev/dri/card0
12596 01:17:41.376633 No KMS driver or no outputs, pipes: 16, outputs: 0
12597 01:17:41.383410 [1mSubtest wait-forked: SKIP (0.000s)[0<14>[ 27.369776] [IGT] kms_vblank: executing
12598 01:17:41.383976 m
12599 01:17:41.389814 IGT-Version: 1.2<14>[ 27.375314] [IGT] kms_vblank: exiting, ret=77
12600 01:17:41.392983 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12601 01:17:41.402796 Using IGT_SRANDOM=1713835061<8>[ 27.387595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12602 01:17:41.403621 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12604 01:17:41.405838 for randomisation
12605 01:17:41.408775 Opened device: /dev/dri/card0
12606 01:17:41.413008 No KMS driver or no outputs, pipes: 16, outputs: 0
12607 01:17:41.415859 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12608 01:17:41.422599 <14>[ 27.409055] [IGT] kms_vblank: executing
12609 01:17:41.425871 IGT-Version: 1.2<14>[ 27.413702] [IGT] kms_vblank: exiting, ret=77
12610 01:17:41.432760 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12611 01:17:41.439380 Using IGT_SR<8>[ 27.424950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12612 01:17:41.440224 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12614 01:17:41.442517 ANDOM=1713835061 for randomisation
12615 01:17:41.446047 Opened device: /dev/dri/card0
12616 01:17:41.448795 No KMS driver or no outputs, pipes: 16, outputs: 0
12617 01:17:41.452083 [1mSubtest wait-busy: SKIP (0.000s)[0m
12618 01:17:41.458657 <14>[ 27.445260] [IGT] kms_vblank: executing
12619 01:17:41.459219
12620 01:17:41.465735 IGT-Version: 1.2<14>[ 27.450442] [IGT] kms_vblank: exiting, ret=77
12621 01:17:41.468571 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12622 01:17:41.475570 Using IGT_SR<8>[ 27.461525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12623 01:17:41.476299 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12625 01:17:41.478771 ANDOM=1713835061 for randomisation
12626 01:17:41.482424 Opened device: /dev/dri/card0
12627 01:17:41.489178 No KMS driver or no outputs, pipes: 16, outputs: 0
12628 01:17:41.492113 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12629 01:17:41.495583 <14>[ 27.483934] [IGT] kms_vblank: executing
12630 01:17:41.501905 IGT-Version: 1.2<14>[ 27.488613] [IGT] kms_vblank: exiting, ret=77
12631 01:17:41.505172 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12632 01:17:41.518829 Using IGT_SRANDOM=1713835061 for randomisati<8>[ 27.501407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12633 01:17:41.519392 on
12634 01:17:41.520038 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12636 01:17:41.521888 Opened device: /dev/dri/card0
12637 01:17:41.525011 No KMS driver or no outputs, pipes: 16, outputs: 0
12638 01:17:41.528409 [1mSubtest wait-forked-busy: SKIP (0.000s)[0m
12639 01:17:41.537881 <14>[ 27.524717] [IGT] kms_vblank: executing
12640 01:17:41.544152 IGT-Version: 1.2<14>[ 27.529352] [IGT] kms_vblank: exiting, ret=77
12641 01:17:41.547118 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12642 01:17:41.557660 Using IGT_SR<8>[ 27.540364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12643 01:17:41.558626 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12645 01:17:41.560559 ANDOM=1713835061 for randomisation
12646 01:17:41.561021 Opened device: /dev/dri/card0
12647 01:17:41.567130 No KMS driver or no outputs, pipes: 16, outputs: 0
12648 01:17:41.573869 [1mSubtest wait-forked-busy-hang: SKIP (<14>[ 27.562136] [IGT] kms_vblank: executing
12649 01:17:41.577301 0.000s)[0m
12650 01:17:41.580108 <14>[ 27.567180] [IGT] kms_vblank: exiting, ret=77
12651 01:17:41.593819 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch6<8>[ 27.578009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12652 01:17:41.594409 4)
12653 01:17:41.595067 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12655 01:17:41.597061 Using IGT_SRANDOM=1713835061 for randomisation
12656 01:17:41.600710 Opened device: /dev/dri/card0
12657 01:17:41.606792 No KMS driver or no outputs, pipes: 16, outputs: 0
12658 01:17:41.610227 [1mSubtest ts-continuati<14>[ 27.599051] [IGT] kms_vblank: executing
12659 01:17:41.617019 on-idle: SKIP (0<14>[ 27.604291] [IGT] kms_vblank: exiting, ret=77
12660 01:17:41.620269 .000s)[0m
12661 01:17:41.624005 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12662 01:17:41.633442 <8>[ 27.616302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12663 01:17:41.634326 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12665 01:17:41.636947 Using IGT_SRANDOM=1713835061 for randomisation
12666 01:17:41.640242 Opened device: /dev/dri/card0
12667 01:17:41.643094 No KMS driver or no outputs, pipes: 16, outputs: 0
12668 01:17:41.650261 [1mSubtest ts-continuation-i<14>[ 27.638912] [IGT] kms_vblank: executing
12669 01:17:41.657064 dle-hang: SKIP (<14>[ 27.643640] [IGT] kms_vblank: exiting, ret=77
12670 01:17:41.659843 0.000s)[0m
12671 01:17:41.669826 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86<8>[ 27.654776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12672 01:17:41.670648 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12674 01:17:41.673078 -cip19 aarch64)
12675 01:17:41.676429 Using IGT_SRANDOM=1713835061 for randomisation
12676 01:17:41.679540 Opened device: /dev/dri/card0
12677 01:17:41.683504 No KMS driver or no outputs, pipes: 16, outputs: 0
12678 01:17:41.692704 [1mSubtest ts-continuation-dpms-rpm: SKIP (<14>[ 27.679318] [IGT] kms_vblank: executing
12679 01:17:41.693234 0.000s)[0m
12680 01:17:41.696418 <14>[ 27.684334] [IGT] kms_vblank: exiting, ret=77
12681 01:17:41.713325 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch6<8>[ 27.695236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12682 01:17:41.713899 4)
12683 01:17:41.714513 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12685 01:17:41.716010 Using IGT_SRANDOM=1713835061 for randomisation
12686 01:17:41.719372 Opened device: /dev/dri/card0
12687 01:17:41.722844 No KMS driver or no outputs, pipes: 16, outputs: 0
12688 01:17:41.729856 [1mSubtest ts-continuati<14>[ 27.717171] [IGT] kms_vblank: executing
12689 01:17:41.735918 on-dpms-suspend:<14>[ 27.722267] [IGT] kms_vblank: exiting, ret=77
12690 01:17:41.736480 SKIP (0.000s)[0m
12691 01:17:41.748749 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aa<8>[ 27.734214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12692 01:17:41.749627 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12694 01:17:41.752397 rch64)
12695 01:17:41.755941 Using IGT_SRANDOM=1713835061 for randomisation
12696 01:17:41.758734 Opened device: /dev/dri/card0
12697 01:17:41.762311 No KMS driver or no outputs, pipes: 16, outputs: 0
12698 01:17:41.768750 [1mSubtest ts-contin<14>[ 27.756405] [IGT] kms_vblank: executing
12699 01:17:41.775879 uation-suspend: <14>[ 27.761568] [IGT] kms_vblank: exiting, ret=77
12700 01:17:41.776473 SKIP (0.000s)[0m
12701 01:17:41.788477 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aar<8>[ 27.772950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12702 01:17:41.789030 ch64)
12703 01:17:41.789648 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12705 01:17:41.795306 Using IGT_SRANDOM=1713835061 for randomisation
12706 01:17:41.798911 Opened device: /dev/dri/card0
12707 01:17:41.802474 No KMS driver or no outputs, pipes: 16, outputs: 0
12708 01:17:41.808903 [1mSubtest ts-continu<14>[ 27.795749] [IGT] kms_vblank: executing
12709 01:17:41.815404 ation-modeset: S<14>[ 27.800711] [IGT] kms_vblank: exiting, ret=77
12710 01:17:41.815867 KIP (0.000s)[0m
12711 01:17:41.828414 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6<8>[ 27.811844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12712 01:17:41.828981 .1.86-cip19 aarch64)
12713 01:17:41.829652 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12715 01:17:41.835542 Using IGT_SRANDOM=1713835061 for randomisation
12716 01:17:41.836104 Opened device: /dev/dri/card0
12717 01:17:41.842054 No KMS driver or no outputs, pipes: 16, outputs: 0
12718 01:17:41.848349 [1mSubtest ts-continuation-modeset-han<14>[ 27.836143] [IGT] kms_vblank: executing
12719 01:17:41.854858 g: SKIP (0.000s)<14>[ 27.841581] [IGT] kms_vblank: exiting, ret=77
12720 01:17:41.855367 [0m
12721 01:17:41.861543 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12722 01:17:41.871378 Using <8>[ 27.852946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12723 01:17:41.872057 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12725 01:17:41.878452 IGT_SRANDOM=1713835061 for rando<8>[ 27.864242] <LAVA_SIGNAL_TESTSET STOP>
12726 01:17:41.878981 misation
12727 01:17:41.879573 Received signal: <TESTSET> STOP
12728 01:17:41.879909 Closing test_set kms_vblank
12729 01:17:41.884478 Opened<8>[ 27.870212] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 13468726_1.5.2.3.1>
12730 01:17:41.885152 Received signal: <ENDRUN> 0_igt-kms-mediatek 13468726_1.5.2.3.1
12731 01:17:41.885588 Ending use of test pattern.
12732 01:17:41.885913 Ending test lava.0_igt-kms-mediatek (13468726_1.5.2.3.1), duration 6.43
12734 01:17:41.888085 device: /dev/dri/card0
12735 01:17:41.891668 No KMS driver or no outputs, pipes: 16, outputs: 0
12736 01:17:41.898303 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12737 01:17:41.898979 + set +x
12738 01:17:41.900998 <LAVA_TEST_RUNNER EXIT>
12739 01:17:41.901673 ok: lava_test_shell seems to have completed
12740 01:17:41.907323 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12741 01:17:41.907475 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12742 01:17:41.907563 end: 3 lava-test-retry (duration 00:00:07) [common]
12743 01:17:41.907650 start: 4 finalize (timeout 00:06:57) [common]
12744 01:17:41.907738 start: 4.1 power-off (timeout 00:00:30) [common]
12745 01:17:41.907889 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
12746 01:17:41.985982 >> Command sent successfully.
12747 01:17:41.991611 Returned 0 in 0 seconds
12748 01:17:42.092658 end: 4.1 power-off (duration 00:00:00) [common]
12750 01:17:42.094204 start: 4.2 read-feedback (timeout 00:06:57) [common]
12751 01:17:42.095590 Listened to connection for namespace 'common' for up to 1s
12752 01:17:43.096144 Finalising connection for namespace 'common'
12753 01:17:43.096790 Disconnecting from shell: Finalise
12754 01:17:43.097202 / #
12755 01:17:43.198188 end: 4.2 read-feedback (duration 00:00:01) [common]
12756 01:17:43.198796 end: 4 finalize (duration 00:00:01) [common]
12757 01:17:43.199365 Cleaning after the job
12758 01:17:43.199843 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/ramdisk
12759 01:17:43.226493 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/kernel
12760 01:17:43.241618 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/dtb
12761 01:17:43.241921 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468726/tftp-deploy-o740h9ux/modules
12762 01:17:43.250072 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468726
12763 01:17:43.362267 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468726
12764 01:17:43.362429 Job finished correctly