Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 27
- Boot result: PASS
1 19:25:34.333785 lava-dispatcher, installed at version: 2024.01
2 19:25:34.333980 start: 0 validate
3 19:25:34.334104 Start time: 2024-04-18 19:25:34.334096+00:00 (UTC)
4 19:25:34.334218 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:25:34.334342 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 19:25:34.604451 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:25:34.605179 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:25:34.876176 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:25:34.876901 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:25:35.147314 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:25:35.148126 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:25:35.410078 validate duration: 1.08
14 19:25:35.410368 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:25:35.410479 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:25:35.410572 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:25:35.410693 Not decompressing ramdisk as can be used compressed.
18 19:25:35.410774 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 19:25:35.410841 saving as /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/ramdisk/rootfs.cpio.gz
20 19:25:35.410903 total size: 8181887 (7 MB)
21 19:25:35.411983 progress 0 % (0 MB)
22 19:25:35.414100 progress 5 % (0 MB)
23 19:25:35.416142 progress 10 % (0 MB)
24 19:25:35.418449 progress 15 % (1 MB)
25 19:25:35.420443 progress 20 % (1 MB)
26 19:25:35.422717 progress 25 % (1 MB)
27 19:25:35.424710 progress 30 % (2 MB)
28 19:25:35.426969 progress 35 % (2 MB)
29 19:25:35.428972 progress 40 % (3 MB)
30 19:25:35.431294 progress 45 % (3 MB)
31 19:25:35.433304 progress 50 % (3 MB)
32 19:25:35.435486 progress 55 % (4 MB)
33 19:25:35.437646 progress 60 % (4 MB)
34 19:25:35.439812 progress 65 % (5 MB)
35 19:25:35.441818 progress 70 % (5 MB)
36 19:25:35.443931 progress 75 % (5 MB)
37 19:25:35.445945 progress 80 % (6 MB)
38 19:25:35.448062 progress 85 % (6 MB)
39 19:25:35.450016 progress 90 % (7 MB)
40 19:25:35.452124 progress 95 % (7 MB)
41 19:25:35.454140 progress 100 % (7 MB)
42 19:25:35.454331 7 MB downloaded in 0.04 s (179.68 MB/s)
43 19:25:35.454484 end: 1.1.1 http-download (duration 00:00:00) [common]
45 19:25:35.454724 end: 1.1 download-retry (duration 00:00:00) [common]
46 19:25:35.454812 start: 1.2 download-retry (timeout 00:10:00) [common]
47 19:25:35.454894 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 19:25:35.455024 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:25:35.455090 saving as /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/kernel/Image
50 19:25:35.455149 total size: 54286848 (51 MB)
51 19:25:35.455209 No compression specified
52 19:25:35.456287 progress 0 % (0 MB)
53 19:25:35.469776 progress 5 % (2 MB)
54 19:25:35.483499 progress 10 % (5 MB)
55 19:25:35.497453 progress 15 % (7 MB)
56 19:25:35.511156 progress 20 % (10 MB)
57 19:25:35.524965 progress 25 % (12 MB)
58 19:25:35.538825 progress 30 % (15 MB)
59 19:25:35.552238 progress 35 % (18 MB)
60 19:25:35.565798 progress 40 % (20 MB)
61 19:25:35.579466 progress 45 % (23 MB)
62 19:25:35.593144 progress 50 % (25 MB)
63 19:25:35.607041 progress 55 % (28 MB)
64 19:25:35.620813 progress 60 % (31 MB)
65 19:25:35.634662 progress 65 % (33 MB)
66 19:25:35.648287 progress 70 % (36 MB)
67 19:25:35.661843 progress 75 % (38 MB)
68 19:25:35.675380 progress 80 % (41 MB)
69 19:25:35.689047 progress 85 % (44 MB)
70 19:25:35.702842 progress 90 % (46 MB)
71 19:25:35.716612 progress 95 % (49 MB)
72 19:25:35.730443 progress 100 % (51 MB)
73 19:25:35.730700 51 MB downloaded in 0.28 s (187.89 MB/s)
74 19:25:35.730901 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:25:35.731135 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:25:35.731225 start: 1.3 download-retry (timeout 00:10:00) [common]
78 19:25:35.731311 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 19:25:35.731439 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:25:35.731507 saving as /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/dtb/mt8192-asurada-spherion-r0.dtb
81 19:25:35.731568 total size: 47230 (0 MB)
82 19:25:35.731629 No compression specified
83 19:25:35.732694 progress 69 % (0 MB)
84 19:25:35.732967 progress 100 % (0 MB)
85 19:25:35.733123 0 MB downloaded in 0.00 s (29.00 MB/s)
86 19:25:35.733245 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:25:35.733547 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:25:35.733631 start: 1.4 download-retry (timeout 00:10:00) [common]
90 19:25:35.733713 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 19:25:35.733818 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:25:35.733886 saving as /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/modules/modules.tar
93 19:25:35.733946 total size: 8631416 (8 MB)
94 19:25:35.734007 Using unxz to decompress xz
95 19:25:35.737529 progress 0 % (0 MB)
96 19:25:35.756379 progress 5 % (0 MB)
97 19:25:35.780817 progress 10 % (0 MB)
98 19:25:35.804599 progress 15 % (1 MB)
99 19:25:35.828191 progress 20 % (1 MB)
100 19:25:35.852749 progress 25 % (2 MB)
101 19:25:35.878050 progress 30 % (2 MB)
102 19:25:35.901662 progress 35 % (2 MB)
103 19:25:35.926824 progress 40 % (3 MB)
104 19:25:35.950505 progress 45 % (3 MB)
105 19:25:35.974815 progress 50 % (4 MB)
106 19:25:35.999082 progress 55 % (4 MB)
107 19:25:36.026810 progress 60 % (4 MB)
108 19:25:36.052101 progress 65 % (5 MB)
109 19:25:36.076734 progress 70 % (5 MB)
110 19:25:36.100634 progress 75 % (6 MB)
111 19:25:36.125954 progress 80 % (6 MB)
112 19:25:36.151868 progress 85 % (7 MB)
113 19:25:36.179767 progress 90 % (7 MB)
114 19:25:36.208170 progress 95 % (7 MB)
115 19:25:36.234325 progress 100 % (8 MB)
116 19:25:36.239808 8 MB downloaded in 0.51 s (16.27 MB/s)
117 19:25:36.240052 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:25:36.240316 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:25:36.240411 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 19:25:36.240507 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 19:25:36.240590 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:25:36.240678 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 19:25:36.240894 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a
125 19:25:36.241025 makedir: /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin
126 19:25:36.241130 makedir: /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/tests
127 19:25:36.241226 makedir: /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/results
128 19:25:36.241379 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-add-keys
129 19:25:36.241522 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-add-sources
130 19:25:36.241652 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-background-process-start
131 19:25:36.241781 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-background-process-stop
132 19:25:36.241905 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-common-functions
133 19:25:36.242026 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-echo-ipv4
134 19:25:36.242151 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-install-packages
135 19:25:36.242273 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-installed-packages
136 19:25:36.242397 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-os-build
137 19:25:36.242520 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-probe-channel
138 19:25:36.242642 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-probe-ip
139 19:25:36.242762 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-target-ip
140 19:25:36.242883 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-target-mac
141 19:25:36.243003 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-target-storage
142 19:25:36.243130 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-test-case
143 19:25:36.243252 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-test-event
144 19:25:36.243370 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-test-feedback
145 19:25:36.243491 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-test-raise
146 19:25:36.243614 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-test-reference
147 19:25:36.243736 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-test-runner
148 19:25:36.243857 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-test-set
149 19:25:36.243979 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-test-shell
150 19:25:36.244109 Updating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-install-packages (oe)
151 19:25:36.244257 Updating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/bin/lava-installed-packages (oe)
152 19:25:36.244378 Creating /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/environment
153 19:25:36.244477 LAVA metadata
154 19:25:36.244553 - LAVA_JOB_ID=13420412
155 19:25:36.244619 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:25:36.244722 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 19:25:36.244789 skipped lava-vland-overlay
158 19:25:36.244863 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:25:36.244943 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 19:25:36.245005 skipped lava-multinode-overlay
161 19:25:36.245079 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:25:36.245172 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 19:25:36.245245 Loading test definitions
164 19:25:36.245378 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 19:25:36.245452 Using /lava-13420412 at stage 0
166 19:25:36.245758 uuid=13420412_1.5.2.3.1 testdef=None
167 19:25:36.245848 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 19:25:36.245934 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 19:25:36.246460 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 19:25:36.246681 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 19:25:36.247305 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 19:25:36.247541 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 19:25:36.248149 runner path: /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/0/tests/0_dmesg test_uuid 13420412_1.5.2.3.1
176 19:25:36.248339 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 19:25:36.248551 Creating lava-test-runner.conf files
179 19:25:36.248618 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420412/lava-overlay-6cc02i8a/lava-13420412/0 for stage 0
180 19:25:36.248707 - 0_dmesg
181 19:25:36.248804 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 19:25:36.248889 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 19:25:36.255946 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 19:25:36.256056 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 19:25:36.256148 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 19:25:36.256239 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 19:25:36.256326 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 19:25:36.488416 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 19:25:36.488767 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 19:25:36.488883 extracting modules file /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420412/extract-overlay-ramdisk-jelv9oo6/ramdisk
191 19:25:36.689795 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 19:25:36.689969 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
193 19:25:36.690066 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420412/compress-overlay-ay7a1ix5/overlay-1.5.2.4.tar.gz to ramdisk
194 19:25:36.690143 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420412/compress-overlay-ay7a1ix5/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420412/extract-overlay-ramdisk-jelv9oo6/ramdisk
195 19:25:36.696430 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 19:25:36.696541 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
197 19:25:36.696635 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 19:25:36.696726 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
199 19:25:36.696810 Building ramdisk /var/lib/lava/dispatcher/tmp/13420412/extract-overlay-ramdisk-jelv9oo6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420412/extract-overlay-ramdisk-jelv9oo6/ramdisk
200 19:25:37.057531 >> 145406 blocks
201 19:25:39.307071 rename /var/lib/lava/dispatcher/tmp/13420412/extract-overlay-ramdisk-jelv9oo6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/ramdisk/ramdisk.cpio.gz
202 19:25:39.307498 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 19:25:39.307621 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
204 19:25:39.307725 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
205 19:25:39.307836 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/kernel/Image'
206 19:25:52.129648 Returned 0 in 12 seconds
207 19:25:52.230242 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/kernel/image.itb
208 19:25:52.631243 output: FIT description: Kernel Image image with one or more FDT blobs
209 19:25:52.631595 output: Created: Thu Apr 18 20:25:52 2024
210 19:25:52.631671 output: Image 0 (kernel-1)
211 19:25:52.631740 output: Description:
212 19:25:52.631803 output: Created: Thu Apr 18 20:25:52 2024
213 19:25:52.631864 output: Type: Kernel Image
214 19:25:52.631926 output: Compression: lzma compressed
215 19:25:52.631987 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
216 19:25:52.632050 output: Architecture: AArch64
217 19:25:52.632110 output: OS: Linux
218 19:25:52.632167 output: Load Address: 0x00000000
219 19:25:52.632224 output: Entry Point: 0x00000000
220 19:25:52.632283 output: Hash algo: crc32
221 19:25:52.632341 output: Hash value: bbac8b0b
222 19:25:52.632398 output: Image 1 (fdt-1)
223 19:25:52.632455 output: Description: mt8192-asurada-spherion-r0
224 19:25:52.632511 output: Created: Thu Apr 18 20:25:52 2024
225 19:25:52.632567 output: Type: Flat Device Tree
226 19:25:52.632622 output: Compression: uncompressed
227 19:25:52.632676 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 19:25:52.632730 output: Architecture: AArch64
229 19:25:52.632784 output: Hash algo: crc32
230 19:25:52.632838 output: Hash value: 4bf0d1ac
231 19:25:52.632892 output: Image 2 (ramdisk-1)
232 19:25:52.632946 output: Description: unavailable
233 19:25:52.633000 output: Created: Thu Apr 18 20:25:52 2024
234 19:25:52.633054 output: Type: RAMDisk Image
235 19:25:52.633108 output: Compression: Unknown Compression
236 19:25:52.633161 output: Data Size: 21407345 Bytes = 20905.61 KiB = 20.42 MiB
237 19:25:52.633215 output: Architecture: AArch64
238 19:25:52.633268 output: OS: Linux
239 19:25:52.633329 output: Load Address: unavailable
240 19:25:52.633383 output: Entry Point: unavailable
241 19:25:52.633437 output: Hash algo: crc32
242 19:25:52.633491 output: Hash value: 0ee0193c
243 19:25:52.633544 output: Default Configuration: 'conf-1'
244 19:25:52.633598 output: Configuration 0 (conf-1)
245 19:25:52.633652 output: Description: mt8192-asurada-spherion-r0
246 19:25:52.633706 output: Kernel: kernel-1
247 19:25:52.633759 output: Init Ramdisk: ramdisk-1
248 19:25:52.633812 output: FDT: fdt-1
249 19:25:52.633866 output: Loadables: kernel-1
250 19:25:52.633920 output:
251 19:25:52.634112 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 19:25:52.634210 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 19:25:52.634310 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
254 19:25:52.634403 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
255 19:25:52.634482 No LXC device requested
256 19:25:52.634561 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 19:25:52.634649 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
258 19:25:52.634727 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 19:25:52.634796 Checking files for TFTP limit of 4294967296 bytes.
260 19:25:52.635296 end: 1 tftp-deploy (duration 00:00:17) [common]
261 19:25:52.635401 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 19:25:52.635496 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 19:25:52.635623 substitutions:
264 19:25:52.635692 - {DTB}: 13420412/tftp-deploy-aanent8l/dtb/mt8192-asurada-spherion-r0.dtb
265 19:25:52.635759 - {INITRD}: 13420412/tftp-deploy-aanent8l/ramdisk/ramdisk.cpio.gz
266 19:25:52.635819 - {KERNEL}: 13420412/tftp-deploy-aanent8l/kernel/Image
267 19:25:52.635878 - {LAVA_MAC}: None
268 19:25:52.635936 - {PRESEED_CONFIG}: None
269 19:25:52.635992 - {PRESEED_LOCAL}: None
270 19:25:52.636048 - {RAMDISK}: 13420412/tftp-deploy-aanent8l/ramdisk/ramdisk.cpio.gz
271 19:25:52.636104 - {ROOT_PART}: None
272 19:25:52.636160 - {ROOT}: None
273 19:25:52.636215 - {SERVER_IP}: 192.168.201.1
274 19:25:52.636270 - {TEE}: None
275 19:25:52.636327 Parsed boot commands:
276 19:25:52.636383 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 19:25:52.636553 Parsed boot commands: tftpboot 192.168.201.1 13420412/tftp-deploy-aanent8l/kernel/image.itb 13420412/tftp-deploy-aanent8l/kernel/cmdline
278 19:25:52.636645 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 19:25:52.636732 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 19:25:52.636827 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 19:25:52.636913 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 19:25:52.636984 Not connected, no need to disconnect.
283 19:25:52.637060 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 19:25:52.637141 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 19:25:52.637243 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 19:25:52.640588 Setting prompt string to ['lava-test: # ']
287 19:25:52.640924 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 19:25:52.641030 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 19:25:52.641126 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 19:25:52.641253 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 19:25:52.641491 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 19:25:57.774842 >> Command sent successfully.
293 19:25:57.777385 Returned 0 in 5 seconds
294 19:25:57.877793 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 19:25:57.878133 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 19:25:57.878234 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 19:25:57.878323 Setting prompt string to 'Starting depthcharge on Spherion...'
299 19:25:57.878391 Changing prompt to 'Starting depthcharge on Spherion...'
300 19:25:57.878459 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 19:25:57.878723 [Enter `^Ec?' for help]
302 19:25:58.053535
303 19:25:58.053725
304 19:25:58.053796 F0: 102B 0000
305 19:25:58.053862
306 19:25:58.053925 F3: 1001 0000 [0200]
307 19:25:58.053989
308 19:25:58.057062 F3: 1001 0000
309 19:25:58.057149
310 19:25:58.057237 F7: 102D 0000
311 19:25:58.057365
312 19:25:58.057429 F1: 0000 0000
313 19:25:58.060537
314 19:25:58.060623 V0: 0000 0000 [0001]
315 19:25:58.060691
316 19:25:58.060753 00: 0007 8000
317 19:25:58.060859
318 19:25:58.064094 01: 0000 0000
319 19:25:58.064185
320 19:25:58.064257 BP: 0C00 0209 [0000]
321 19:25:58.064321
322 19:25:58.067943 G0: 1182 0000
323 19:25:58.068032
324 19:25:58.068100 EC: 0000 0021 [4000]
325 19:25:58.068164
326 19:25:58.071922 S7: 0000 0000 [0000]
327 19:25:58.072013
328 19:25:58.072082 CC: 0000 0000 [0001]
329 19:25:58.072146
330 19:25:58.074902 T0: 0000 0040 [010F]
331 19:25:58.074990
332 19:25:58.075058 Jump to BL
333 19:25:58.075125
334 19:25:58.100298
335 19:25:58.100455
336 19:25:58.100524
337 19:25:58.107554 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 19:25:58.111149 ARM64: Exception handlers installed.
339 19:25:58.115184 ARM64: Testing exception
340 19:25:58.115287 ARM64: Done test exception
341 19:25:58.122502 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 19:25:58.134089 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 19:25:58.141645 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 19:25:58.151259 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 19:25:58.157755 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 19:25:58.164438 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 19:25:58.176711 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 19:25:58.183469 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 19:25:58.202751 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 19:25:58.206084 WDT: Last reset was cold boot
351 19:25:58.209356 SPI1(PAD0) initialized at 2873684 Hz
352 19:25:58.212742 SPI5(PAD0) initialized at 992727 Hz
353 19:25:58.215990 VBOOT: Loading verstage.
354 19:25:58.222625 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 19:25:58.226113 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 19:25:58.229652 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 19:25:58.233004 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 19:25:58.240383 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 19:25:58.246858 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 19:25:58.257882 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 19:25:58.258028
362 19:25:58.258128
363 19:25:58.267799 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 19:25:58.271122 ARM64: Exception handlers installed.
365 19:25:58.274416 ARM64: Testing exception
366 19:25:58.274510 ARM64: Done test exception
367 19:25:58.281157 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 19:25:58.284752 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 19:25:58.298811 Probing TPM: . done!
370 19:25:58.298962 TPM ready after 0 ms
371 19:25:58.305268 Connected to device vid:did:rid of 1ae0:0028:00
372 19:25:58.313089 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 19:25:58.369773 Initialized TPM device CR50 revision 0
374 19:25:58.380533 tlcl_send_startup: Startup return code is 0
375 19:25:58.380685 TPM: setup succeeded
376 19:25:58.391650 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 19:25:58.400677 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 19:25:58.410714 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 19:25:58.419631 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 19:25:58.423105 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 19:25:58.432229 in-header: 03 07 00 00 08 00 00 00
382 19:25:58.436204 in-data: aa e4 47 04 13 02 00 00
383 19:25:58.439754 Chrome EC: UHEPI supported
384 19:25:58.447089 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 19:25:58.450489 in-header: 03 ad 00 00 08 00 00 00
386 19:25:58.454239 in-data: 00 20 20 08 00 00 00 00
387 19:25:58.454386 Phase 1
388 19:25:58.457927 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 19:25:58.465654 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 19:25:58.469153 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 19:25:58.473038 Recovery requested (1009000e)
392 19:25:58.481989 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 19:25:58.487693 tlcl_extend: response is 0
394 19:25:58.496933 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 19:25:58.503051 tlcl_extend: response is 0
396 19:25:58.509844 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 19:25:58.529976 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 19:25:58.537060 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 19:25:58.537200
400 19:25:58.537271
401 19:25:58.547109 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 19:25:58.550471 ARM64: Exception handlers installed.
403 19:25:58.550575 ARM64: Testing exception
404 19:25:58.553765 ARM64: Done test exception
405 19:25:58.575298 pmic_efuse_setting: Set efuses in 11 msecs
406 19:25:58.578686 pmwrap_interface_init: Select PMIF_VLD_RDY
407 19:25:58.585783 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 19:25:58.589737 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 19:25:58.592329 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 19:25:58.599053 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 19:25:58.602501 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 19:25:58.609589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 19:25:58.613267 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 19:25:58.616813 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 19:25:58.624206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 19:25:58.628356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 19:25:58.631622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 19:25:58.635234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 19:25:58.642050 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 19:25:58.648463 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 19:25:58.652075 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 19:25:58.659018 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 19:25:58.666282 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 19:25:58.669858 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 19:25:58.677027 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 19:25:58.680722 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 19:25:58.687492 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 19:25:58.691070 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 19:25:58.697984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 19:25:58.704739 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 19:25:58.708084 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 19:25:58.714632 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 19:25:58.718163 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 19:25:58.724521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 19:25:58.727801 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 19:25:58.734767 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 19:25:58.738179 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 19:25:58.744915 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 19:25:58.748008 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 19:25:58.754497 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 19:25:58.758054 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 19:25:58.764971 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 19:25:58.768259 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 19:25:58.775077 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 19:25:58.778203 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 19:25:58.781474 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 19:25:58.788438 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 19:25:58.791713 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 19:25:58.795356 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 19:25:58.799417 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 19:25:58.805777 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 19:25:58.808746 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 19:25:58.812325 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 19:25:58.819306 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 19:25:58.822666 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 19:25:58.825920 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 19:25:58.829005 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 19:25:58.839199 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 19:25:58.845671 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 19:25:58.852355 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 19:25:58.858977 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 19:25:58.869119 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 19:25:58.872418 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 19:25:58.875735 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 19:25:58.882279 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 19:25:58.888902 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 19:25:58.892107 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 19:25:58.899776 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 19:25:58.902535 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 19:25:58.912766 [RTC]rtc_get_frequency_meter,154: input=15, output=771
471 19:25:58.921667 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 19:25:58.931602 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 19:25:58.940997 [RTC]rtc_get_frequency_meter,154: input=17, output=817
474 19:25:58.950866 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 19:25:58.955153 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 19:25:58.958250 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 19:25:58.962177 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
478 19:25:58.969204 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 19:25:58.973251 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
480 19:25:58.973408 ADC[4]: Raw value=903245 ID=7
481 19:25:58.976662 ADC[3]: Raw value=213179 ID=1
482 19:25:58.979961 RAM Code: 0x71
483 19:25:58.984223 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 19:25:58.987671 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 19:25:58.997460 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 19:25:59.004003 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 19:25:59.007584 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 19:25:59.010992 in-header: 03 07 00 00 08 00 00 00
489 19:25:59.014007 in-data: aa e4 47 04 13 02 00 00
490 19:25:59.014096 Chrome EC: UHEPI supported
491 19:25:59.020564 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 19:25:59.024591 in-header: 03 ed 00 00 08 00 00 00
493 19:25:59.027806 in-data: 80 20 60 08 00 00 00 00
494 19:25:59.031407 MRC: failed to locate region type 0.
495 19:25:59.037869 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 19:25:59.041749 DRAM-K: Running full calibration
497 19:25:59.048967 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 19:25:59.049093 header.status = 0x0
499 19:25:59.052517 header.version = 0x6 (expected: 0x6)
500 19:25:59.056888 header.size = 0xd00 (expected: 0xd00)
501 19:25:59.056991 header.flags = 0x0
502 19:25:59.063649 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 19:25:59.082014 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
504 19:25:59.088768 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 19:25:59.092101 dram_init: ddr_geometry: 2
506 19:25:59.095240 [EMI] MDL number = 2
507 19:25:59.095332 [EMI] Get MDL freq = 0
508 19:25:59.099237 dram_init: ddr_type: 0
509 19:25:59.099325 is_discrete_lpddr4: 1
510 19:25:59.102216 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 19:25:59.102303
512 19:25:59.102372
513 19:25:59.105658 [Bian_co] ETT version 0.0.0.1
514 19:25:59.112023 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 19:25:59.112126
516 19:25:59.115844 dramc_set_vcore_voltage set vcore to 650000
517 19:25:59.115934 Read voltage for 800, 4
518 19:25:59.118957 Vio18 = 0
519 19:25:59.119046 Vcore = 650000
520 19:25:59.119114 Vdram = 0
521 19:25:59.122203 Vddq = 0
522 19:25:59.122291 Vmddr = 0
523 19:25:59.125686 dram_init: config_dvfs: 1
524 19:25:59.128703 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 19:25:59.135562 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 19:25:59.138883 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 19:25:59.142139 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 19:25:59.145626 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 19:25:59.148806 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 19:25:59.152130 MEM_TYPE=3, freq_sel=18
531 19:25:59.155609 sv_algorithm_assistance_LP4_1600
532 19:25:59.158986 ============ PULL DRAM RESETB DOWN ============
533 19:25:59.162387 ========== PULL DRAM RESETB DOWN end =========
534 19:25:59.168838 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 19:25:59.171942 ===================================
536 19:25:59.175237 LPDDR4 DRAM CONFIGURATION
537 19:25:59.178874 ===================================
538 19:25:59.178972 EX_ROW_EN[0] = 0x0
539 19:25:59.182106 EX_ROW_EN[1] = 0x0
540 19:25:59.182196 LP4Y_EN = 0x0
541 19:25:59.185243 WORK_FSP = 0x0
542 19:25:59.185341 WL = 0x2
543 19:25:59.188657 RL = 0x2
544 19:25:59.188746 BL = 0x2
545 19:25:59.191955 RPST = 0x0
546 19:25:59.192044 RD_PRE = 0x0
547 19:25:59.195254 WR_PRE = 0x1
548 19:25:59.195341 WR_PST = 0x0
549 19:25:59.198672 DBI_WR = 0x0
550 19:25:59.198760 DBI_RD = 0x0
551 19:25:59.201890 OTF = 0x1
552 19:25:59.205270 ===================================
553 19:25:59.209002 ===================================
554 19:25:59.209092 ANA top config
555 19:25:59.212231 ===================================
556 19:25:59.215448 DLL_ASYNC_EN = 0
557 19:25:59.218594 ALL_SLAVE_EN = 1
558 19:25:59.222150 NEW_RANK_MODE = 1
559 19:25:59.222241 DLL_IDLE_MODE = 1
560 19:25:59.225098 LP45_APHY_COMB_EN = 1
561 19:25:59.228455 TX_ODT_DIS = 1
562 19:25:59.231861 NEW_8X_MODE = 1
563 19:25:59.235645 ===================================
564 19:25:59.238617 ===================================
565 19:25:59.241977 data_rate = 1600
566 19:25:59.242065 CKR = 1
567 19:25:59.245497 DQ_P2S_RATIO = 8
568 19:25:59.248822 ===================================
569 19:25:59.251961 CA_P2S_RATIO = 8
570 19:25:59.255435 DQ_CA_OPEN = 0
571 19:25:59.258574 DQ_SEMI_OPEN = 0
572 19:25:59.261960 CA_SEMI_OPEN = 0
573 19:25:59.262052 CA_FULL_RATE = 0
574 19:25:59.265369 DQ_CKDIV4_EN = 1
575 19:25:59.268829 CA_CKDIV4_EN = 1
576 19:25:59.272118 CA_PREDIV_EN = 0
577 19:25:59.275317 PH8_DLY = 0
578 19:25:59.278495 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 19:25:59.278585 DQ_AAMCK_DIV = 4
580 19:25:59.281999 CA_AAMCK_DIV = 4
581 19:25:59.285739 CA_ADMCK_DIV = 4
582 19:25:59.288878 DQ_TRACK_CA_EN = 0
583 19:25:59.292064 CA_PICK = 800
584 19:25:59.295473 CA_MCKIO = 800
585 19:25:59.295564 MCKIO_SEMI = 0
586 19:25:59.298563 PLL_FREQ = 3068
587 19:25:59.302343 DQ_UI_PI_RATIO = 32
588 19:25:59.305363 CA_UI_PI_RATIO = 0
589 19:25:59.308656 ===================================
590 19:25:59.312145 ===================================
591 19:25:59.315266 memory_type:LPDDR4
592 19:25:59.315355 GP_NUM : 10
593 19:25:59.318649 SRAM_EN : 1
594 19:25:59.321962 MD32_EN : 0
595 19:25:59.322050 ===================================
596 19:25:59.326109 [ANA_INIT] >>>>>>>>>>>>>>
597 19:25:59.329539 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 19:25:59.333101 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 19:25:59.336796 ===================================
600 19:25:59.336890 data_rate = 1600,PCW = 0X7600
601 19:25:59.340522 ===================================
602 19:25:59.344630 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 19:25:59.351678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 19:25:59.355927 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 19:25:59.359413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 19:25:59.362730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 19:25:59.366309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 19:25:59.369528 [ANA_INIT] flow start
609 19:25:59.372986 [ANA_INIT] PLL >>>>>>>>
610 19:25:59.373077 [ANA_INIT] PLL <<<<<<<<
611 19:25:59.376515 [ANA_INIT] MIDPI >>>>>>>>
612 19:25:59.379373 [ANA_INIT] MIDPI <<<<<<<<
613 19:25:59.382613 [ANA_INIT] DLL >>>>>>>>
614 19:25:59.382700 [ANA_INIT] flow end
615 19:25:59.385924 ============ LP4 DIFF to SE enter ============
616 19:25:59.392904 ============ LP4 DIFF to SE exit ============
617 19:25:59.393013 [ANA_INIT] <<<<<<<<<<<<<
618 19:25:59.396319 [Flow] Enable top DCM control >>>>>
619 19:25:59.399629 [Flow] Enable top DCM control <<<<<
620 19:25:59.402753 Enable DLL master slave shuffle
621 19:25:59.409504 ==============================================================
622 19:25:59.409612 Gating Mode config
623 19:25:59.416649 ==============================================================
624 19:25:59.419615 Config description:
625 19:25:59.426180 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 19:25:59.432869 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 19:25:59.439648 SELPH_MODE 0: By rank 1: By Phase
628 19:25:59.443046 ==============================================================
629 19:25:59.446233 GAT_TRACK_EN = 1
630 19:25:59.449638 RX_GATING_MODE = 2
631 19:25:59.452889 RX_GATING_TRACK_MODE = 2
632 19:25:59.456216 SELPH_MODE = 1
633 19:25:59.459786 PICG_EARLY_EN = 1
634 19:25:59.462995 VALID_LAT_VALUE = 1
635 19:25:59.469812 ==============================================================
636 19:25:59.472870 Enter into Gating configuration >>>>
637 19:25:59.476390 Exit from Gating configuration <<<<
638 19:25:59.476486 Enter into DVFS_PRE_config >>>>>
639 19:25:59.489723 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 19:25:59.493224 Exit from DVFS_PRE_config <<<<<
641 19:25:59.496179 Enter into PICG configuration >>>>
642 19:25:59.499563 Exit from PICG configuration <<<<
643 19:25:59.499671 [RX_INPUT] configuration >>>>>
644 19:25:59.503430 [RX_INPUT] configuration <<<<<
645 19:25:59.509627 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 19:25:59.513180 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 19:25:59.519737 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 19:25:59.526878 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 19:25:59.533278 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 19:25:59.539911 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 19:25:59.543054 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 19:25:59.546595 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 19:25:59.550042 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 19:25:59.557518 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 19:25:59.560762 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 19:25:59.564011 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 19:25:59.568191 ===================================
658 19:25:59.571850 LPDDR4 DRAM CONFIGURATION
659 19:25:59.571937 ===================================
660 19:25:59.575244 EX_ROW_EN[0] = 0x0
661 19:25:59.575329 EX_ROW_EN[1] = 0x0
662 19:25:59.579186 LP4Y_EN = 0x0
663 19:25:59.579270 WORK_FSP = 0x0
664 19:25:59.582975 WL = 0x2
665 19:25:59.583059 RL = 0x2
666 19:25:59.586239 BL = 0x2
667 19:25:59.586323 RPST = 0x0
668 19:25:59.589967 RD_PRE = 0x0
669 19:25:59.590087 WR_PRE = 0x1
670 19:25:59.593642 WR_PST = 0x0
671 19:25:59.593759 DBI_WR = 0x0
672 19:25:59.597321 DBI_RD = 0x0
673 19:25:59.597428 OTF = 0x1
674 19:25:59.600960 ===================================
675 19:25:59.604509 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 19:25:59.608203 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 19:25:59.615464 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 19:25:59.615550 ===================================
679 19:25:59.619431 LPDDR4 DRAM CONFIGURATION
680 19:25:59.623365 ===================================
681 19:25:59.623450 EX_ROW_EN[0] = 0x10
682 19:25:59.627366 EX_ROW_EN[1] = 0x0
683 19:25:59.627450 LP4Y_EN = 0x0
684 19:25:59.630702 WORK_FSP = 0x0
685 19:25:59.630786 WL = 0x2
686 19:25:59.634151 RL = 0x2
687 19:25:59.634272 BL = 0x2
688 19:25:59.637666 RPST = 0x0
689 19:25:59.637750 RD_PRE = 0x0
690 19:25:59.641638 WR_PRE = 0x1
691 19:25:59.641722 WR_PST = 0x0
692 19:25:59.645054 DBI_WR = 0x0
693 19:25:59.645137 DBI_RD = 0x0
694 19:25:59.649071 OTF = 0x1
695 19:25:59.649155 ===================================
696 19:25:59.656428 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 19:25:59.661079 nWR fixed to 40
698 19:25:59.661165 [ModeRegInit_LP4] CH0 RK0
699 19:25:59.664360 [ModeRegInit_LP4] CH0 RK1
700 19:25:59.667723 [ModeRegInit_LP4] CH1 RK0
701 19:25:59.671465 [ModeRegInit_LP4] CH1 RK1
702 19:25:59.671549 match AC timing 13
703 19:25:59.675095 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 19:25:59.678971 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 19:25:59.686218 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 19:25:59.689567 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 19:25:59.693443 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 19:25:59.696966 [EMI DOE] emi_dcm 0
709 19:25:59.701465 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 19:25:59.701550 ==
711 19:25:59.704681 Dram Type= 6, Freq= 0, CH_0, rank 0
712 19:25:59.708199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 19:25:59.708284 ==
714 19:25:59.711750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 19:25:59.718930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 19:25:59.728435 [CA 0] Center 38 (7~69) winsize 63
717 19:25:59.731769 [CA 1] Center 38 (7~69) winsize 63
718 19:25:59.735584 [CA 2] Center 35 (5~66) winsize 62
719 19:25:59.739268 [CA 3] Center 35 (4~66) winsize 63
720 19:25:59.742986 [CA 4] Center 35 (5~65) winsize 61
721 19:25:59.747405 [CA 5] Center 34 (3~65) winsize 63
722 19:25:59.747490
723 19:25:59.750740 [CmdBusTrainingLP45] Vref(ca) range 1: 34
724 19:25:59.750863
725 19:25:59.754957 [CATrainingPosCal] consider 1 rank data
726 19:25:59.755042 u2DelayCellTimex100 = 270/100 ps
727 19:25:59.758342 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
728 19:25:59.762303 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
729 19:25:59.765621 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
730 19:25:59.770164 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
731 19:25:59.773930 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
732 19:25:59.777560 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
733 19:25:59.777646
734 19:25:59.780830 CA PerBit enable=1, Macro0, CA PI delay=34
735 19:25:59.780914
736 19:25:59.784843 [CBTSetCACLKResult] CA Dly = 34
737 19:25:59.784929 CS Dly: 6 (0~37)
738 19:25:59.788146 ==
739 19:25:59.788231 Dram Type= 6, Freq= 0, CH_0, rank 1
740 19:25:59.792212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 19:25:59.795673 ==
742 19:25:59.799521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 19:25:59.806291 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 19:25:59.814723 [CA 0] Center 38 (7~69) winsize 63
745 19:25:59.818904 [CA 1] Center 38 (8~69) winsize 62
746 19:25:59.822790 [CA 2] Center 36 (6~67) winsize 62
747 19:25:59.826652 [CA 3] Center 35 (5~66) winsize 62
748 19:25:59.829495 [CA 4] Center 35 (4~66) winsize 63
749 19:25:59.833143 [CA 5] Center 34 (4~65) winsize 62
750 19:25:59.833227
751 19:25:59.836965 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 19:25:59.837050
753 19:25:59.840762 [CATrainingPosCal] consider 2 rank data
754 19:25:59.840846 u2DelayCellTimex100 = 270/100 ps
755 19:25:59.844647 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 19:25:59.848351 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 19:25:59.852408 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 19:25:59.855684 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 19:25:59.859584 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
760 19:25:59.863564 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
761 19:25:59.863648
762 19:25:59.866789 CA PerBit enable=1, Macro0, CA PI delay=34
763 19:25:59.866873
764 19:25:59.870428 [CBTSetCACLKResult] CA Dly = 34
765 19:25:59.873813 CS Dly: 6 (0~38)
766 19:25:59.873898
767 19:25:59.877020 ----->DramcWriteLeveling(PI) begin...
768 19:25:59.877105 ==
769 19:25:59.880731 Dram Type= 6, Freq= 0, CH_0, rank 0
770 19:25:59.883995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 19:25:59.884080 ==
772 19:25:59.887593 Write leveling (Byte 0): 30 => 30
773 19:25:59.890597 Write leveling (Byte 1): 30 => 30
774 19:25:59.893985 DramcWriteLeveling(PI) end<-----
775 19:25:59.894068
776 19:25:59.894134 ==
777 19:25:59.897271 Dram Type= 6, Freq= 0, CH_0, rank 0
778 19:25:59.900562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 19:25:59.900646 ==
780 19:25:59.903754 [Gating] SW mode calibration
781 19:25:59.911140 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 19:25:59.915127 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 19:25:59.918852 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
784 19:25:59.926290 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
785 19:25:59.929198 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 19:25:59.932995 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 19:25:59.936253 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 19:25:59.942913 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 19:25:59.946328 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 19:25:59.949910 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 19:25:59.956277 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 19:25:59.959530 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 19:25:59.963006 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 19:25:59.969823 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 19:25:59.973057 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 19:25:59.976436 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 19:25:59.982946 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 19:25:59.986324 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 19:25:59.989893 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 19:25:59.996427 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
801 19:25:59.999735 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
802 19:26:00.003067 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 19:26:00.006712 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 19:26:00.013237 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 19:26:00.016674 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 19:26:00.019899 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 19:26:00.026647 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 19:26:00.031000 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
809 19:26:00.033637 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
810 19:26:00.039982 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
811 19:26:00.043426 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 19:26:00.046899 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 19:26:00.053409 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 19:26:00.056505 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 19:26:00.059935 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 19:26:00.066625 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
817 19:26:00.069980 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (1 1) (0 0)
818 19:26:00.073615 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 19:26:00.080185 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 19:26:00.083398 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 19:26:00.086510 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 19:26:00.093467 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 19:26:00.096703 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 19:26:00.099834 0 11 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
825 19:26:00.103217 0 11 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
826 19:26:00.110209 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
827 19:26:00.113645 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 19:26:00.116617 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 19:26:00.123113 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 19:26:00.126459 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 19:26:00.129783 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 19:26:00.136652 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 19:26:00.140046 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 19:26:00.143422 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 19:26:00.149793 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 19:26:00.153150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 19:26:00.156364 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 19:26:00.163216 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 19:26:00.166432 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 19:26:00.169981 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 19:26:00.176545 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 19:26:00.179911 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 19:26:00.183239 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 19:26:00.189979 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 19:26:00.193257 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 19:26:00.196726 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 19:26:00.200115 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 19:26:00.206862 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
849 19:26:00.209958 Total UI for P1: 0, mck2ui 16
850 19:26:00.213387 best dqsien dly found for B0: ( 0, 14, 2)
851 19:26:00.216589 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 19:26:00.220047 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 19:26:00.223390 Total UI for P1: 0, mck2ui 16
854 19:26:00.226754 best dqsien dly found for B1: ( 0, 14, 6)
855 19:26:00.230449 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
856 19:26:00.233622 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
857 19:26:00.233705
858 19:26:00.239815 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
859 19:26:00.243750 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
860 19:26:00.243835 [Gating] SW calibration Done
861 19:26:00.246786 ==
862 19:26:00.246870 Dram Type= 6, Freq= 0, CH_0, rank 0
863 19:26:00.253216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 19:26:00.253388 ==
865 19:26:00.253455 RX Vref Scan: 0
866 19:26:00.253516
867 19:26:00.256633 RX Vref 0 -> 0, step: 1
868 19:26:00.256716
869 19:26:00.260179 RX Delay -130 -> 252, step: 16
870 19:26:00.263767 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
871 19:26:00.266761 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 19:26:00.270093 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 19:26:00.276752 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 19:26:00.280236 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
875 19:26:00.283284 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 19:26:00.286864 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 19:26:00.290193 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 19:26:00.296946 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 19:26:00.300143 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 19:26:00.303278 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 19:26:00.306786 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 19:26:00.310402 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
883 19:26:00.316675 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 19:26:00.320028 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 19:26:00.323565 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
886 19:26:00.323649 ==
887 19:26:00.326600 Dram Type= 6, Freq= 0, CH_0, rank 0
888 19:26:00.329886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 19:26:00.333695 ==
890 19:26:00.333779 DQS Delay:
891 19:26:00.333846 DQS0 = 0, DQS1 = 0
892 19:26:00.337046 DQM Delay:
893 19:26:00.337128 DQM0 = 89, DQM1 = 79
894 19:26:00.337194 DQ Delay:
895 19:26:00.340273 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
896 19:26:00.343482 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
897 19:26:00.346737 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
898 19:26:00.350624 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
899 19:26:00.350762
900 19:26:00.350829
901 19:26:00.353781 ==
902 19:26:00.357237 Dram Type= 6, Freq= 0, CH_0, rank 0
903 19:26:00.360344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 19:26:00.360431 ==
905 19:26:00.360515
906 19:26:00.360593
907 19:26:00.363595 TX Vref Scan disable
908 19:26:00.363680 == TX Byte 0 ==
909 19:26:00.366815 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
910 19:26:00.373774 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
911 19:26:00.373865 == TX Byte 1 ==
912 19:26:00.377209 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 19:26:00.383792 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 19:26:00.383883 ==
915 19:26:00.387182 Dram Type= 6, Freq= 0, CH_0, rank 0
916 19:26:00.390170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 19:26:00.390261 ==
918 19:26:00.403337 TX Vref=22, minBit 11, minWin=26, winSum=440
919 19:26:00.406522 TX Vref=24, minBit 8, minWin=27, winSum=448
920 19:26:00.409869 TX Vref=26, minBit 4, minWin=28, winSum=453
921 19:26:00.413068 TX Vref=28, minBit 8, minWin=27, winSum=451
922 19:26:00.416748 TX Vref=30, minBit 6, minWin=28, winSum=455
923 19:26:00.422991 TX Vref=32, minBit 10, minWin=27, winSum=456
924 19:26:00.426891 [TxChooseVref] Worse bit 6, Min win 28, Win sum 455, Final Vref 30
925 19:26:00.427004
926 19:26:00.429987 Final TX Range 1 Vref 30
927 19:26:00.430080
928 19:26:00.430149 ==
929 19:26:00.433328 Dram Type= 6, Freq= 0, CH_0, rank 0
930 19:26:00.436693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 19:26:00.440048 ==
932 19:26:00.440143
933 19:26:00.440211
934 19:26:00.440273 TX Vref Scan disable
935 19:26:00.443669 == TX Byte 0 ==
936 19:26:00.446611 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
937 19:26:00.450210 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
938 19:26:00.453390 == TX Byte 1 ==
939 19:26:00.456624 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
940 19:26:00.459814 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
941 19:26:00.463256
942 19:26:00.463359 [DATLAT]
943 19:26:00.463429 Freq=800, CH0 RK0
944 19:26:00.463494
945 19:26:00.466580 DATLAT Default: 0xa
946 19:26:00.466674 0, 0xFFFF, sum = 0
947 19:26:00.470155 1, 0xFFFF, sum = 0
948 19:26:00.470247 2, 0xFFFF, sum = 0
949 19:26:00.473096 3, 0xFFFF, sum = 0
950 19:26:00.473183 4, 0xFFFF, sum = 0
951 19:26:00.476598 5, 0xFFFF, sum = 0
952 19:26:00.479867 6, 0xFFFF, sum = 0
953 19:26:00.479954 7, 0xFFFF, sum = 0
954 19:26:00.483361 8, 0xFFFF, sum = 0
955 19:26:00.483447 9, 0x0, sum = 1
956 19:26:00.483517 10, 0x0, sum = 2
957 19:26:00.486812 11, 0x0, sum = 3
958 19:26:00.486899 12, 0x0, sum = 4
959 19:26:00.490034 best_step = 10
960 19:26:00.490119
961 19:26:00.490187 ==
962 19:26:00.493573 Dram Type= 6, Freq= 0, CH_0, rank 0
963 19:26:00.497017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 19:26:00.497103 ==
965 19:26:00.500153 RX Vref Scan: 1
966 19:26:00.500238
967 19:26:00.500305 Set Vref Range= 32 -> 127
968 19:26:00.500368
969 19:26:00.503529 RX Vref 32 -> 127, step: 1
970 19:26:00.503645
971 19:26:00.507011 RX Delay -95 -> 252, step: 8
972 19:26:00.507095
973 19:26:00.510187 Set Vref, RX VrefLevel [Byte0]: 32
974 19:26:00.513334 [Byte1]: 32
975 19:26:00.513418
976 19:26:00.516799 Set Vref, RX VrefLevel [Byte0]: 33
977 19:26:00.520065 [Byte1]: 33
978 19:26:00.523646
979 19:26:00.523731 Set Vref, RX VrefLevel [Byte0]: 34
980 19:26:00.527377 [Byte1]: 34
981 19:26:00.531025
982 19:26:00.531109 Set Vref, RX VrefLevel [Byte0]: 35
983 19:26:00.534637 [Byte1]: 35
984 19:26:00.538680
985 19:26:00.538765 Set Vref, RX VrefLevel [Byte0]: 36
986 19:26:00.541940 [Byte1]: 36
987 19:26:00.546977
988 19:26:00.547062 Set Vref, RX VrefLevel [Byte0]: 37
989 19:26:00.549818 [Byte1]: 37
990 19:26:00.554515
991 19:26:00.554607 Set Vref, RX VrefLevel [Byte0]: 38
992 19:26:00.557886 [Byte1]: 38
993 19:26:00.561511
994 19:26:00.561615 Set Vref, RX VrefLevel [Byte0]: 39
995 19:26:00.564844 [Byte1]: 39
996 19:26:00.568945
997 19:26:00.569032 Set Vref, RX VrefLevel [Byte0]: 40
998 19:26:00.572586 [Byte1]: 40
999 19:26:00.577092
1000 19:26:00.577194 Set Vref, RX VrefLevel [Byte0]: 41
1001 19:26:00.580330 [Byte1]: 41
1002 19:26:00.584919
1003 19:26:00.585021 Set Vref, RX VrefLevel [Byte0]: 42
1004 19:26:00.588135 [Byte1]: 42
1005 19:26:00.592567
1006 19:26:00.592671 Set Vref, RX VrefLevel [Byte0]: 43
1007 19:26:00.595916 [Byte1]: 43
1008 19:26:00.599746
1009 19:26:00.599832 Set Vref, RX VrefLevel [Byte0]: 44
1010 19:26:00.603037 [Byte1]: 44
1011 19:26:00.607819
1012 19:26:00.607909 Set Vref, RX VrefLevel [Byte0]: 45
1013 19:26:00.610905 [Byte1]: 45
1014 19:26:00.615060
1015 19:26:00.615146 Set Vref, RX VrefLevel [Byte0]: 46
1016 19:26:00.617960 [Byte1]: 46
1017 19:26:00.622272
1018 19:26:00.622359 Set Vref, RX VrefLevel [Byte0]: 47
1019 19:26:00.625764 [Byte1]: 47
1020 19:26:00.630131
1021 19:26:00.630217 Set Vref, RX VrefLevel [Byte0]: 48
1022 19:26:00.633502 [Byte1]: 48
1023 19:26:00.637463
1024 19:26:00.637549 Set Vref, RX VrefLevel [Byte0]: 49
1025 19:26:00.641145 [Byte1]: 49
1026 19:26:00.645291
1027 19:26:00.645384 Set Vref, RX VrefLevel [Byte0]: 50
1028 19:26:00.648612 [Byte1]: 50
1029 19:26:00.652909
1030 19:26:00.652993 Set Vref, RX VrefLevel [Byte0]: 51
1031 19:26:00.656096 [Byte1]: 51
1032 19:26:00.660416
1033 19:26:00.660501 Set Vref, RX VrefLevel [Byte0]: 52
1034 19:26:00.663750 [Byte1]: 52
1035 19:26:00.667836
1036 19:26:00.667921 Set Vref, RX VrefLevel [Byte0]: 53
1037 19:26:00.671525 [Byte1]: 53
1038 19:26:00.675925
1039 19:26:00.676010 Set Vref, RX VrefLevel [Byte0]: 54
1040 19:26:00.678839 [Byte1]: 54
1041 19:26:00.683007
1042 19:26:00.683092 Set Vref, RX VrefLevel [Byte0]: 55
1043 19:26:00.686419 [Byte1]: 55
1044 19:26:00.690873
1045 19:26:00.690958 Set Vref, RX VrefLevel [Byte0]: 56
1046 19:26:00.694205 [Byte1]: 56
1047 19:26:00.698524
1048 19:26:00.698608 Set Vref, RX VrefLevel [Byte0]: 57
1049 19:26:00.701762 [Byte1]: 57
1050 19:26:00.706080
1051 19:26:00.706162 Set Vref, RX VrefLevel [Byte0]: 58
1052 19:26:00.709220 [Byte1]: 58
1053 19:26:00.713500
1054 19:26:00.713583 Set Vref, RX VrefLevel [Byte0]: 59
1055 19:26:00.716921 [Byte1]: 59
1056 19:26:00.720960
1057 19:26:00.721041 Set Vref, RX VrefLevel [Byte0]: 60
1058 19:26:00.724273 [Byte1]: 60
1059 19:26:00.729024
1060 19:26:00.729106 Set Vref, RX VrefLevel [Byte0]: 61
1061 19:26:00.732305 [Byte1]: 61
1062 19:26:00.736305
1063 19:26:00.736401 Set Vref, RX VrefLevel [Byte0]: 62
1064 19:26:00.739755 [Byte1]: 62
1065 19:26:00.744011
1066 19:26:00.744093 Set Vref, RX VrefLevel [Byte0]: 63
1067 19:26:00.747240 [Byte1]: 63
1068 19:26:00.751689
1069 19:26:00.751772 Set Vref, RX VrefLevel [Byte0]: 64
1070 19:26:00.754615 [Byte1]: 64
1071 19:26:00.759559
1072 19:26:00.759643 Set Vref, RX VrefLevel [Byte0]: 65
1073 19:26:00.762406 [Byte1]: 65
1074 19:26:00.766637
1075 19:26:00.766721 Set Vref, RX VrefLevel [Byte0]: 66
1076 19:26:00.769934 [Byte1]: 66
1077 19:26:00.774293
1078 19:26:00.774378 Set Vref, RX VrefLevel [Byte0]: 67
1079 19:26:00.777656 [Byte1]: 67
1080 19:26:00.782093
1081 19:26:00.782177 Set Vref, RX VrefLevel [Byte0]: 68
1082 19:26:00.785134 [Byte1]: 68
1083 19:26:00.789500
1084 19:26:00.789606 Set Vref, RX VrefLevel [Byte0]: 69
1085 19:26:00.792954 [Byte1]: 69
1086 19:26:00.797030
1087 19:26:00.797113 Set Vref, RX VrefLevel [Byte0]: 70
1088 19:26:00.800461 [Byte1]: 70
1089 19:26:00.804648
1090 19:26:00.804730 Set Vref, RX VrefLevel [Byte0]: 71
1091 19:26:00.807946 [Byte1]: 71
1092 19:26:00.812435
1093 19:26:00.812518 Set Vref, RX VrefLevel [Byte0]: 72
1094 19:26:00.815958 [Byte1]: 72
1095 19:26:00.819882
1096 19:26:00.822965 Set Vref, RX VrefLevel [Byte0]: 73
1097 19:26:00.826255 [Byte1]: 73
1098 19:26:00.826339
1099 19:26:00.830006 Set Vref, RX VrefLevel [Byte0]: 74
1100 19:26:00.833144 [Byte1]: 74
1101 19:26:00.833227
1102 19:26:00.836797 Set Vref, RX VrefLevel [Byte0]: 75
1103 19:26:00.839990 [Byte1]: 75
1104 19:26:00.840074
1105 19:26:00.842963 Set Vref, RX VrefLevel [Byte0]: 76
1106 19:26:00.846335 [Byte1]: 76
1107 19:26:00.850303
1108 19:26:00.850386 Set Vref, RX VrefLevel [Byte0]: 77
1109 19:26:00.853761 [Byte1]: 77
1110 19:26:00.858179
1111 19:26:00.858264 Set Vref, RX VrefLevel [Byte0]: 78
1112 19:26:00.861280 [Byte1]: 78
1113 19:26:00.865369
1114 19:26:00.865465 Set Vref, RX VrefLevel [Byte0]: 79
1115 19:26:00.869126 [Byte1]: 79
1116 19:26:00.872986
1117 19:26:00.873069 Final RX Vref Byte 0 = 61 to rank0
1118 19:26:00.876396 Final RX Vref Byte 1 = 62 to rank0
1119 19:26:00.879650 Final RX Vref Byte 0 = 61 to rank1
1120 19:26:00.883267 Final RX Vref Byte 1 = 62 to rank1==
1121 19:26:00.886368 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 19:26:00.893033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 19:26:00.893120 ==
1124 19:26:00.893188 DQS Delay:
1125 19:26:00.893250 DQS0 = 0, DQS1 = 0
1126 19:26:00.896419 DQM Delay:
1127 19:26:00.896502 DQM0 = 92, DQM1 = 83
1128 19:26:00.899995 DQ Delay:
1129 19:26:00.902865 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =88
1130 19:26:00.906306 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1131 19:26:00.909968 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1132 19:26:00.913041 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1133 19:26:00.913125
1134 19:26:00.913225
1135 19:26:00.920035 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a35, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1136 19:26:00.922868 CH0 RK0: MR19=606, MR18=3A35
1137 19:26:00.929651 CH0_RK0: MR19=0x606, MR18=0x3A35, DQSOSC=395, MR23=63, INC=94, DEC=63
1138 19:26:00.929740
1139 19:26:00.932900 ----->DramcWriteLeveling(PI) begin...
1140 19:26:00.932985 ==
1141 19:26:00.936582 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 19:26:00.940000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 19:26:00.940085 ==
1144 19:26:00.943119 Write leveling (Byte 0): 34 => 34
1145 19:26:00.946476 Write leveling (Byte 1): 28 => 28
1146 19:26:00.949603 DramcWriteLeveling(PI) end<-----
1147 19:26:00.949686
1148 19:26:00.949769 ==
1149 19:26:00.953215 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 19:26:00.956617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 19:26:00.956702 ==
1152 19:26:00.959857 [Gating] SW mode calibration
1153 19:26:00.966444 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 19:26:00.973194 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 19:26:00.976468 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 19:26:00.979650 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 19:26:01.023786 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 19:26:01.024164 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 19:26:01.024475 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 19:26:01.024583 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 19:26:01.024661 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 19:26:01.024749 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 19:26:01.024811 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 19:26:01.024908 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 19:26:01.025191 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 19:26:01.025268 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 19:26:01.041926 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 19:26:01.042316 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 19:26:01.042826 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 19:26:01.045410 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 19:26:01.045493 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 19:26:01.052238 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1173 19:26:01.055368 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1174 19:26:01.058890 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 19:26:01.065612 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 19:26:01.069327 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 19:26:01.071897 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 19:26:01.078605 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 19:26:01.082275 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 19:26:01.085518 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 19:26:01.092160 0 9 8 | B1->B0 | 2b2b 3434 | 1 0 | (1 1) (0 0)
1182 19:26:01.095513 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 19:26:01.098659 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 19:26:01.105646 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 19:26:01.108606 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 19:26:01.111997 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 19:26:01.118793 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 19:26:01.122121 0 10 4 | B1->B0 | 3333 3030 | 0 1 | (1 0) (0 0)
1189 19:26:01.125921 0 10 8 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
1190 19:26:01.129224 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 19:26:01.135701 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 19:26:01.139030 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 19:26:01.142472 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 19:26:01.149077 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 19:26:01.152219 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 19:26:01.155763 0 11 4 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
1197 19:26:01.162812 0 11 8 | B1->B0 | 3c3c 4545 | 1 0 | (1 1) (0 0)
1198 19:26:01.165971 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 19:26:01.169860 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 19:26:01.173529 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 19:26:01.180319 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 19:26:01.183755 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 19:26:01.187322 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 19:26:01.190470 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1205 19:26:01.197345 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 19:26:01.200550 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 19:26:01.204059 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 19:26:01.210773 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 19:26:01.213953 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 19:26:01.217256 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 19:26:01.224291 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 19:26:01.227550 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 19:26:01.230689 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 19:26:01.237274 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 19:26:01.241331 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 19:26:01.243930 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 19:26:01.250839 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 19:26:01.254027 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 19:26:01.257414 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1220 19:26:01.260853 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 19:26:01.267432 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 19:26:01.270777 Total UI for P1: 0, mck2ui 16
1223 19:26:01.273936 best dqsien dly found for B0: ( 0, 14, 2)
1224 19:26:01.277211 Total UI for P1: 0, mck2ui 16
1225 19:26:01.280698 best dqsien dly found for B1: ( 0, 14, 6)
1226 19:26:01.284369 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1227 19:26:01.287406 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1228 19:26:01.287491
1229 19:26:01.290809 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1230 19:26:01.294525 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1231 19:26:01.297182 [Gating] SW calibration Done
1232 19:26:01.297266 ==
1233 19:26:01.301022 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 19:26:01.303819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 19:26:01.303904 ==
1236 19:26:01.307240 RX Vref Scan: 0
1237 19:26:01.307323
1238 19:26:01.307390 RX Vref 0 -> 0, step: 1
1239 19:26:01.307450
1240 19:26:01.310785 RX Delay -130 -> 252, step: 16
1241 19:26:01.313869 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1242 19:26:01.320584 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1243 19:26:01.324060 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1244 19:26:01.327449 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1245 19:26:01.330906 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1246 19:26:01.334072 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1247 19:26:01.340672 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1248 19:26:01.344159 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1249 19:26:01.347280 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1250 19:26:01.350824 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1251 19:26:01.353934 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1252 19:26:01.360657 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1253 19:26:01.364058 iDelay=206, Bit 12, Center 85 (-18 ~ 189) 208
1254 19:26:01.367275 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1255 19:26:01.370840 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1256 19:26:01.374177 iDelay=206, Bit 15, Center 85 (-18 ~ 189) 208
1257 19:26:01.377685 ==
1258 19:26:01.380584 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 19:26:01.384032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 19:26:01.384116 ==
1261 19:26:01.384183 DQS Delay:
1262 19:26:01.387700 DQS0 = 0, DQS1 = 0
1263 19:26:01.387784 DQM Delay:
1264 19:26:01.390807 DQM0 = 88, DQM1 = 79
1265 19:26:01.390890 DQ Delay:
1266 19:26:01.394183 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1267 19:26:01.397454 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1268 19:26:01.401209 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
1269 19:26:01.404102 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1270 19:26:01.404185
1271 19:26:01.404250
1272 19:26:01.404309 ==
1273 19:26:01.407433 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 19:26:01.410705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 19:26:01.410788 ==
1276 19:26:01.410870
1277 19:26:01.410942
1278 19:26:01.414119 TX Vref Scan disable
1279 19:26:01.417458 == TX Byte 0 ==
1280 19:26:01.420659 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1281 19:26:01.424290 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1282 19:26:01.427535 == TX Byte 1 ==
1283 19:26:01.430974 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1284 19:26:01.434360 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1285 19:26:01.434442 ==
1286 19:26:01.438248 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 19:26:01.440738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 19:26:01.440855 ==
1289 19:26:01.456082 TX Vref=22, minBit 8, minWin=27, winSum=446
1290 19:26:01.459293 TX Vref=24, minBit 8, minWin=27, winSum=449
1291 19:26:01.462494 TX Vref=26, minBit 8, minWin=27, winSum=453
1292 19:26:01.465965 TX Vref=28, minBit 4, minWin=28, winSum=456
1293 19:26:01.469228 TX Vref=30, minBit 8, minWin=27, winSum=459
1294 19:26:01.472864 TX Vref=32, minBit 8, minWin=27, winSum=454
1295 19:26:01.479115 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 28
1296 19:26:01.479197
1297 19:26:01.482471 Final TX Range 1 Vref 28
1298 19:26:01.482550
1299 19:26:01.482614 ==
1300 19:26:01.485832 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 19:26:01.489479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 19:26:01.489560 ==
1303 19:26:01.489624
1304 19:26:01.492512
1305 19:26:01.492590 TX Vref Scan disable
1306 19:26:01.495907 == TX Byte 0 ==
1307 19:26:01.499788 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1308 19:26:01.505723 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1309 19:26:01.505805 == TX Byte 1 ==
1310 19:26:01.509255 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1311 19:26:01.512682 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1312 19:26:01.515704
1313 19:26:01.515785 [DATLAT]
1314 19:26:01.515849 Freq=800, CH0 RK1
1315 19:26:01.515909
1316 19:26:01.519307 DATLAT Default: 0xa
1317 19:26:01.519387 0, 0xFFFF, sum = 0
1318 19:26:01.522481 1, 0xFFFF, sum = 0
1319 19:26:01.522563 2, 0xFFFF, sum = 0
1320 19:26:01.525697 3, 0xFFFF, sum = 0
1321 19:26:01.525779 4, 0xFFFF, sum = 0
1322 19:26:01.529236 5, 0xFFFF, sum = 0
1323 19:26:01.532790 6, 0xFFFF, sum = 0
1324 19:26:01.532873 7, 0xFFFF, sum = 0
1325 19:26:01.536042 8, 0xFFFF, sum = 0
1326 19:26:01.536125 9, 0x0, sum = 1
1327 19:26:01.536189 10, 0x0, sum = 2
1328 19:26:01.539110 11, 0x0, sum = 3
1329 19:26:01.539192 12, 0x0, sum = 4
1330 19:26:01.542610 best_step = 10
1331 19:26:01.542691
1332 19:26:01.542754 ==
1333 19:26:01.546200 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 19:26:01.549038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 19:26:01.549130 ==
1336 19:26:01.552359 RX Vref Scan: 0
1337 19:26:01.552441
1338 19:26:01.552506 RX Vref 0 -> 0, step: 1
1339 19:26:01.552566
1340 19:26:01.555688 RX Delay -95 -> 252, step: 8
1341 19:26:01.562632 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1342 19:26:01.565694 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1343 19:26:01.569252 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1344 19:26:01.572687 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1345 19:26:01.576124 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1346 19:26:01.582622 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1347 19:26:01.585843 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1348 19:26:01.589706 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1349 19:26:01.592420 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1350 19:26:01.596229 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1351 19:26:01.602701 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1352 19:26:01.606038 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1353 19:26:01.609453 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1354 19:26:01.612497 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1355 19:26:01.615909 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1356 19:26:01.622500 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1357 19:26:01.622586 ==
1358 19:26:01.626068 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 19:26:01.629617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 19:26:01.629701 ==
1361 19:26:01.629766 DQS Delay:
1362 19:26:01.632874 DQS0 = 0, DQS1 = 0
1363 19:26:01.632955 DQM Delay:
1364 19:26:01.635905 DQM0 = 91, DQM1 = 80
1365 19:26:01.635991 DQ Delay:
1366 19:26:01.639093 DQ0 =88, DQ1 =92, DQ2 =92, DQ3 =84
1367 19:26:01.642754 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1368 19:26:01.646000 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =76
1369 19:26:01.649217 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1370 19:26:01.649363
1371 19:26:01.649431
1372 19:26:01.659438 [DQSOSCAuto] RK1, (LSB)MR18= 0x411b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1373 19:26:01.659564 CH0 RK1: MR19=606, MR18=411B
1374 19:26:01.665917 CH0_RK1: MR19=0x606, MR18=0x411B, DQSOSC=393, MR23=63, INC=95, DEC=63
1375 19:26:01.669292 [RxdqsGatingPostProcess] freq 800
1376 19:26:01.675907 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 19:26:01.679161 Pre-setting of DQS Precalculation
1378 19:26:01.682492 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 19:26:01.682579 ==
1380 19:26:01.685828 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 19:26:01.689455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 19:26:01.689540 ==
1383 19:26:01.696062 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 19:26:01.702489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 19:26:01.711034 [CA 0] Center 36 (6~67) winsize 62
1386 19:26:01.714427 [CA 1] Center 37 (6~68) winsize 63
1387 19:26:01.717802 [CA 2] Center 35 (5~65) winsize 61
1388 19:26:01.721305 [CA 3] Center 34 (3~65) winsize 63
1389 19:26:01.724485 [CA 4] Center 34 (4~65) winsize 62
1390 19:26:01.727619 [CA 5] Center 34 (3~65) winsize 63
1391 19:26:01.727704
1392 19:26:01.731459 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1393 19:26:01.731544
1394 19:26:01.734389 [CATrainingPosCal] consider 1 rank data
1395 19:26:01.737961 u2DelayCellTimex100 = 270/100 ps
1396 19:26:01.741519 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 19:26:01.744443 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1398 19:26:01.751163 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1399 19:26:01.754487 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1400 19:26:01.757802 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 19:26:01.761348 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1402 19:26:01.761440
1403 19:26:01.764637 CA PerBit enable=1, Macro0, CA PI delay=34
1404 19:26:01.764722
1405 19:26:01.767705 [CBTSetCACLKResult] CA Dly = 34
1406 19:26:01.767790 CS Dly: 5 (0~36)
1407 19:26:01.767857 ==
1408 19:26:01.771098 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 19:26:01.777796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 19:26:01.777910 ==
1411 19:26:01.781107 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 19:26:01.787570 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 19:26:01.797282 [CA 0] Center 36 (6~67) winsize 62
1414 19:26:01.800645 [CA 1] Center 37 (6~68) winsize 63
1415 19:26:01.804167 [CA 2] Center 35 (5~66) winsize 62
1416 19:26:01.807111 [CA 3] Center 34 (4~65) winsize 62
1417 19:26:01.810540 [CA 4] Center 34 (4~65) winsize 62
1418 19:26:01.813872 [CA 5] Center 34 (4~65) winsize 62
1419 19:26:01.813956
1420 19:26:01.817223 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1421 19:26:01.817311
1422 19:26:01.820584 [CATrainingPosCal] consider 2 rank data
1423 19:26:01.824291 u2DelayCellTimex100 = 270/100 ps
1424 19:26:01.827957 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 19:26:01.831886 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1426 19:26:01.835891 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 19:26:01.839598 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 19:26:01.843265 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 19:26:01.846975 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 19:26:01.847062
1431 19:26:01.850740 CA PerBit enable=1, Macro0, CA PI delay=34
1432 19:26:01.850825
1433 19:26:01.854653 [CBTSetCACLKResult] CA Dly = 34
1434 19:26:01.854739 CS Dly: 6 (0~38)
1435 19:26:01.854806
1436 19:26:01.857604 ----->DramcWriteLeveling(PI) begin...
1437 19:26:01.857689 ==
1438 19:26:01.861074 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 19:26:01.867605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 19:26:01.867696 ==
1441 19:26:01.870694 Write leveling (Byte 0): 26 => 26
1442 19:26:01.874475 Write leveling (Byte 1): 30 => 30
1443 19:26:01.874564 DramcWriteLeveling(PI) end<-----
1444 19:26:01.874631
1445 19:26:01.877421 ==
1446 19:26:01.880820 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 19:26:01.883976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 19:26:01.884061 ==
1449 19:26:01.887662 [Gating] SW mode calibration
1450 19:26:01.894157 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 19:26:01.897678 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 19:26:01.904111 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1453 19:26:01.907639 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1454 19:26:01.910678 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 19:26:01.917484 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 19:26:01.920797 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 19:26:01.924123 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 19:26:01.930951 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 19:26:01.934193 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 19:26:01.937469 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 19:26:01.944486 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 19:26:01.947663 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 19:26:01.951264 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 19:26:01.954174 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 19:26:01.961242 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 19:26:01.964507 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 19:26:01.967596 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 19:26:01.974564 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 19:26:01.977572 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 19:26:01.981109 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 19:26:01.987599 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 19:26:01.991388 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 19:26:01.994189 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 19:26:02.000903 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 19:26:02.004370 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 19:26:02.007939 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 19:26:02.014275 0 9 4 | B1->B0 | 2424 2d2c | 0 1 | (0 0) (0 0)
1478 19:26:02.017666 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 19:26:02.020860 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 19:26:02.027576 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 19:26:02.031107 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 19:26:02.034297 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 19:26:02.038083 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 19:26:02.044490 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 19:26:02.047687 0 10 4 | B1->B0 | 2f2f 2727 | 1 0 | (1 1) (0 0)
1486 19:26:02.051002 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 19:26:02.057736 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 19:26:02.060846 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 19:26:02.064764 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 19:26:02.071203 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 19:26:02.074220 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 19:26:02.077837 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1493 19:26:02.084558 0 11 4 | B1->B0 | 3232 3535 | 1 0 | (0 0) (1 1)
1494 19:26:02.087904 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 19:26:02.091330 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 19:26:02.097817 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 19:26:02.101247 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 19:26:02.104809 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 19:26:02.111280 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 19:26:02.114434 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1501 19:26:02.118017 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1502 19:26:02.121360 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 19:26:02.128130 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 19:26:02.131293 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 19:26:02.134570 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 19:26:02.141279 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 19:26:02.144472 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 19:26:02.147989 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 19:26:02.154428 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 19:26:02.158183 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 19:26:02.161259 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 19:26:02.167888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 19:26:02.171362 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 19:26:02.174629 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 19:26:02.181333 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 19:26:02.184845 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1517 19:26:02.188183 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 19:26:02.194348 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 19:26:02.194434 Total UI for P1: 0, mck2ui 16
1520 19:26:02.201128 best dqsien dly found for B0: ( 0, 14, 2)
1521 19:26:02.201221 Total UI for P1: 0, mck2ui 16
1522 19:26:02.204536 best dqsien dly found for B1: ( 0, 14, 4)
1523 19:26:02.211059 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1524 19:26:02.214517 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1525 19:26:02.214618
1526 19:26:02.217606 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1527 19:26:02.220927 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 19:26:02.224435 [Gating] SW calibration Done
1529 19:26:02.224523 ==
1530 19:26:02.227685 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 19:26:02.231467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 19:26:02.231552 ==
1533 19:26:02.231618 RX Vref Scan: 0
1534 19:26:02.234267
1535 19:26:02.234349 RX Vref 0 -> 0, step: 1
1536 19:26:02.234415
1537 19:26:02.237751 RX Delay -130 -> 252, step: 16
1538 19:26:02.241044 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1539 19:26:02.244555 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1540 19:26:02.251293 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1541 19:26:02.254473 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1542 19:26:02.257778 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1543 19:26:02.261105 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1544 19:26:02.264299 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1545 19:26:02.271481 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1546 19:26:02.274309 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1547 19:26:02.277766 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1548 19:26:02.281034 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1549 19:26:02.284574 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1550 19:26:02.291094 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1551 19:26:02.294670 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1552 19:26:02.297809 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1553 19:26:02.301210 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1554 19:26:02.301330 ==
1555 19:26:02.304602 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 19:26:02.311291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 19:26:02.311376 ==
1558 19:26:02.311441 DQS Delay:
1559 19:26:02.311501 DQS0 = 0, DQS1 = 0
1560 19:26:02.314479 DQM Delay:
1561 19:26:02.314574 DQM0 = 88, DQM1 = 80
1562 19:26:02.317653 DQ Delay:
1563 19:26:02.321012 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1564 19:26:02.324637 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1565 19:26:02.327650 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1566 19:26:02.331149 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1567 19:26:02.331231
1568 19:26:02.331297
1569 19:26:02.331355 ==
1570 19:26:02.334577 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 19:26:02.338012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 19:26:02.338096 ==
1573 19:26:02.338162
1574 19:26:02.338223
1575 19:26:02.341137 TX Vref Scan disable
1576 19:26:02.341219 == TX Byte 0 ==
1577 19:26:02.348024 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1578 19:26:02.351319 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1579 19:26:02.351403 == TX Byte 1 ==
1580 19:26:02.358036 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1581 19:26:02.361484 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1582 19:26:02.361569 ==
1583 19:26:02.364630 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 19:26:02.367699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 19:26:02.367782 ==
1586 19:26:02.382065 TX Vref=22, minBit 13, minWin=27, winSum=451
1587 19:26:02.385771 TX Vref=24, minBit 13, minWin=27, winSum=451
1588 19:26:02.388624 TX Vref=26, minBit 13, minWin=27, winSum=453
1589 19:26:02.391804 TX Vref=28, minBit 15, minWin=27, winSum=459
1590 19:26:02.395573 TX Vref=30, minBit 15, minWin=27, winSum=459
1591 19:26:02.402090 TX Vref=32, minBit 8, minWin=28, winSum=460
1592 19:26:02.405787 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 32
1593 19:26:02.405873
1594 19:26:02.409504 Final TX Range 1 Vref 32
1595 19:26:02.409587
1596 19:26:02.409652 ==
1597 19:26:02.412652 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 19:26:02.416041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 19:26:02.416126 ==
1600 19:26:02.416193
1601 19:26:02.416254
1602 19:26:02.419624 TX Vref Scan disable
1603 19:26:02.422702 == TX Byte 0 ==
1604 19:26:02.426293 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1605 19:26:02.429437 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1606 19:26:02.432877 == TX Byte 1 ==
1607 19:26:02.436135 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1608 19:26:02.439538 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1609 19:26:02.439622
1610 19:26:02.442678 [DATLAT]
1611 19:26:02.442761 Freq=800, CH1 RK0
1612 19:26:02.442827
1613 19:26:02.445997 DATLAT Default: 0xa
1614 19:26:02.446080 0, 0xFFFF, sum = 0
1615 19:26:02.449879 1, 0xFFFF, sum = 0
1616 19:26:02.449963 2, 0xFFFF, sum = 0
1617 19:26:02.453153 3, 0xFFFF, sum = 0
1618 19:26:02.453237 4, 0xFFFF, sum = 0
1619 19:26:02.456078 5, 0xFFFF, sum = 0
1620 19:26:02.456162 6, 0xFFFF, sum = 0
1621 19:26:02.459551 7, 0xFFFF, sum = 0
1622 19:26:02.459635 8, 0xFFFF, sum = 0
1623 19:26:02.463055 9, 0x0, sum = 1
1624 19:26:02.463141 10, 0x0, sum = 2
1625 19:26:02.466194 11, 0x0, sum = 3
1626 19:26:02.466278 12, 0x0, sum = 4
1627 19:26:02.469535 best_step = 10
1628 19:26:02.469617
1629 19:26:02.469682 ==
1630 19:26:02.472826 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 19:26:02.476508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 19:26:02.476594 ==
1633 19:26:02.479513 RX Vref Scan: 1
1634 19:26:02.479597
1635 19:26:02.479662 Set Vref Range= 32 -> 127
1636 19:26:02.479722
1637 19:26:02.483069 RX Vref 32 -> 127, step: 1
1638 19:26:02.483153
1639 19:26:02.486610 RX Delay -95 -> 252, step: 8
1640 19:26:02.486694
1641 19:26:02.489818 Set Vref, RX VrefLevel [Byte0]: 32
1642 19:26:02.492916 [Byte1]: 32
1643 19:26:02.493001
1644 19:26:02.496396 Set Vref, RX VrefLevel [Byte0]: 33
1645 19:26:02.499575 [Byte1]: 33
1646 19:26:02.499659
1647 19:26:02.502856 Set Vref, RX VrefLevel [Byte0]: 34
1648 19:26:02.506504 [Byte1]: 34
1649 19:26:02.510435
1650 19:26:02.510519 Set Vref, RX VrefLevel [Byte0]: 35
1651 19:26:02.513610 [Byte1]: 35
1652 19:26:02.518177
1653 19:26:02.518262 Set Vref, RX VrefLevel [Byte0]: 36
1654 19:26:02.521058 [Byte1]: 36
1655 19:26:02.525610
1656 19:26:02.525696 Set Vref, RX VrefLevel [Byte0]: 37
1657 19:26:02.529092 [Byte1]: 37
1658 19:26:02.533261
1659 19:26:02.533399 Set Vref, RX VrefLevel [Byte0]: 38
1660 19:26:02.536566 [Byte1]: 38
1661 19:26:02.540784
1662 19:26:02.540927 Set Vref, RX VrefLevel [Byte0]: 39
1663 19:26:02.543905 [Byte1]: 39
1664 19:26:02.548137
1665 19:26:02.548232 Set Vref, RX VrefLevel [Byte0]: 40
1666 19:26:02.551815 [Byte1]: 40
1667 19:26:02.555886
1668 19:26:02.555972 Set Vref, RX VrefLevel [Byte0]: 41
1669 19:26:02.559338 [Byte1]: 41
1670 19:26:02.563333
1671 19:26:02.563442 Set Vref, RX VrefLevel [Byte0]: 42
1672 19:26:02.566676 [Byte1]: 42
1673 19:26:02.571392
1674 19:26:02.571483 Set Vref, RX VrefLevel [Byte0]: 43
1675 19:26:02.574575 [Byte1]: 43
1676 19:26:02.578633
1677 19:26:02.578719 Set Vref, RX VrefLevel [Byte0]: 44
1678 19:26:02.581870 [Byte1]: 44
1679 19:26:02.586568
1680 19:26:02.586655 Set Vref, RX VrefLevel [Byte0]: 45
1681 19:26:02.589780 [Byte1]: 45
1682 19:26:02.593978
1683 19:26:02.594065 Set Vref, RX VrefLevel [Byte0]: 46
1684 19:26:02.597288 [Byte1]: 46
1685 19:26:02.601686
1686 19:26:02.601774 Set Vref, RX VrefLevel [Byte0]: 47
1687 19:26:02.605017 [Byte1]: 47
1688 19:26:02.608938
1689 19:26:02.609026 Set Vref, RX VrefLevel [Byte0]: 48
1690 19:26:02.612458 [Byte1]: 48
1691 19:26:02.616818
1692 19:26:02.616905 Set Vref, RX VrefLevel [Byte0]: 49
1693 19:26:02.620161 [Byte1]: 49
1694 19:26:02.624068
1695 19:26:02.624155 Set Vref, RX VrefLevel [Byte0]: 50
1696 19:26:02.627717 [Byte1]: 50
1697 19:26:02.631920
1698 19:26:02.632012 Set Vref, RX VrefLevel [Byte0]: 51
1699 19:26:02.635222 [Byte1]: 51
1700 19:26:02.639323
1701 19:26:02.639411 Set Vref, RX VrefLevel [Byte0]: 52
1702 19:26:02.642548 [Byte1]: 52
1703 19:26:02.647074
1704 19:26:02.647174 Set Vref, RX VrefLevel [Byte0]: 53
1705 19:26:02.650178 [Byte1]: 53
1706 19:26:02.655007
1707 19:26:02.655098 Set Vref, RX VrefLevel [Byte0]: 54
1708 19:26:02.658049 [Byte1]: 54
1709 19:26:02.662359
1710 19:26:02.662446 Set Vref, RX VrefLevel [Byte0]: 55
1711 19:26:02.665442 [Byte1]: 55
1712 19:26:02.669996
1713 19:26:02.670084 Set Vref, RX VrefLevel [Byte0]: 56
1714 19:26:02.672939 [Byte1]: 56
1715 19:26:02.677597
1716 19:26:02.677683 Set Vref, RX VrefLevel [Byte0]: 57
1717 19:26:02.680731 [Byte1]: 57
1718 19:26:02.684964
1719 19:26:02.685050 Set Vref, RX VrefLevel [Byte0]: 58
1720 19:26:02.688239 [Byte1]: 58
1721 19:26:02.692619
1722 19:26:02.692706 Set Vref, RX VrefLevel [Byte0]: 59
1723 19:26:02.695940 [Byte1]: 59
1724 19:26:02.700229
1725 19:26:02.700314 Set Vref, RX VrefLevel [Byte0]: 60
1726 19:26:02.703644 [Byte1]: 60
1727 19:26:02.707561
1728 19:26:02.707645 Set Vref, RX VrefLevel [Byte0]: 61
1729 19:26:02.711154 [Byte1]: 61
1730 19:26:02.715149
1731 19:26:02.715232 Set Vref, RX VrefLevel [Byte0]: 62
1732 19:26:02.718657 [Byte1]: 62
1733 19:26:02.723165
1734 19:26:02.723248 Set Vref, RX VrefLevel [Byte0]: 63
1735 19:26:02.726324 [Byte1]: 63
1736 19:26:02.730847
1737 19:26:02.730930 Set Vref, RX VrefLevel [Byte0]: 64
1738 19:26:02.734171 [Byte1]: 64
1739 19:26:02.738235
1740 19:26:02.738318 Set Vref, RX VrefLevel [Byte0]: 65
1741 19:26:02.741573 [Byte1]: 65
1742 19:26:02.745572
1743 19:26:02.745658 Set Vref, RX VrefLevel [Byte0]: 66
1744 19:26:02.748997 [Byte1]: 66
1745 19:26:02.753268
1746 19:26:02.753374 Set Vref, RX VrefLevel [Byte0]: 67
1747 19:26:02.756690 [Byte1]: 67
1748 19:26:02.760845
1749 19:26:02.760930 Set Vref, RX VrefLevel [Byte0]: 68
1750 19:26:02.764335 [Byte1]: 68
1751 19:26:02.768564
1752 19:26:02.768650 Set Vref, RX VrefLevel [Byte0]: 69
1753 19:26:02.772337 [Byte1]: 69
1754 19:26:02.776681
1755 19:26:02.776767 Set Vref, RX VrefLevel [Byte0]: 70
1756 19:26:02.779715 [Byte1]: 70
1757 19:26:02.783717
1758 19:26:02.783802 Set Vref, RX VrefLevel [Byte0]: 71
1759 19:26:02.787174 [Byte1]: 71
1760 19:26:02.791742
1761 19:26:02.791828 Set Vref, RX VrefLevel [Byte0]: 72
1762 19:26:02.794608 [Byte1]: 72
1763 19:26:02.799194
1764 19:26:02.799279 Set Vref, RX VrefLevel [Byte0]: 73
1765 19:26:02.802161 [Byte1]: 73
1766 19:26:02.806497
1767 19:26:02.806580 Set Vref, RX VrefLevel [Byte0]: 74
1768 19:26:02.809654 [Byte1]: 74
1769 19:26:02.814048
1770 19:26:02.814131 Set Vref, RX VrefLevel [Byte0]: 75
1771 19:26:02.817885 [Byte1]: 75
1772 19:26:02.822040
1773 19:26:02.822127 Set Vref, RX VrefLevel [Byte0]: 76
1774 19:26:02.825075 [Byte1]: 76
1775 19:26:02.829329
1776 19:26:02.829440 Set Vref, RX VrefLevel [Byte0]: 77
1777 19:26:02.832607 [Byte1]: 77
1778 19:26:02.837103
1779 19:26:02.837186 Final RX Vref Byte 0 = 52 to rank0
1780 19:26:02.840426 Final RX Vref Byte 1 = 63 to rank0
1781 19:26:02.843703 Final RX Vref Byte 0 = 52 to rank1
1782 19:26:02.847050 Final RX Vref Byte 1 = 63 to rank1==
1783 19:26:02.850281 Dram Type= 6, Freq= 0, CH_1, rank 0
1784 19:26:02.857198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 19:26:02.857334 ==
1786 19:26:02.857432 DQS Delay:
1787 19:26:02.857510 DQS0 = 0, DQS1 = 0
1788 19:26:02.860178 DQM Delay:
1789 19:26:02.860260 DQM0 = 92, DQM1 = 82
1790 19:26:02.863686 DQ Delay:
1791 19:26:02.867169 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1792 19:26:02.870264 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1793 19:26:02.870348 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =80
1794 19:26:02.876778 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1795 19:26:02.876865
1796 19:26:02.876931
1797 19:26:02.883765 [DQSOSCAuto] RK0, (LSB)MR18= 0x304e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1798 19:26:02.887140 CH1 RK0: MR19=606, MR18=304E
1799 19:26:02.893822 CH1_RK0: MR19=0x606, MR18=0x304E, DQSOSC=390, MR23=63, INC=97, DEC=64
1800 19:26:02.893909
1801 19:26:02.896957 ----->DramcWriteLeveling(PI) begin...
1802 19:26:02.897041 ==
1803 19:26:02.900748 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 19:26:02.903679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 19:26:02.903763 ==
1806 19:26:02.907373 Write leveling (Byte 0): 29 => 29
1807 19:26:02.910445 Write leveling (Byte 1): 29 => 29
1808 19:26:02.913990 DramcWriteLeveling(PI) end<-----
1809 19:26:02.914073
1810 19:26:02.914139 ==
1811 19:26:02.917290 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 19:26:02.920498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1813 19:26:02.920582 ==
1814 19:26:02.924100 [Gating] SW mode calibration
1815 19:26:02.930614 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1816 19:26:02.937441 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1817 19:26:02.940500 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1818 19:26:02.944112 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1819 19:26:02.950576 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 19:26:02.953848 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 19:26:02.956977 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 19:26:02.963902 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 19:26:02.967204 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 19:26:02.970388 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 19:26:02.976913 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 19:26:02.980369 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 19:26:02.983516 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 19:26:02.990088 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 19:26:02.993529 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 19:26:02.996943 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 19:26:03.000417 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 19:26:03.006821 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 19:26:03.010372 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1834 19:26:03.013742 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1835 19:26:03.020244 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1836 19:26:03.023429 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 19:26:03.026772 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 19:26:03.033258 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 19:26:03.036616 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 19:26:03.040210 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 19:26:03.047135 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 19:26:03.050364 0 9 4 | B1->B0 | 2323 2424 | 1 1 | (1 1) (0 0)
1843 19:26:03.053360 0 9 8 | B1->B0 | 3333 3333 | 1 1 | (0 0) (1 1)
1844 19:26:03.059944 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 19:26:03.062927 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 19:26:03.066584 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 19:26:03.072864 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 19:26:03.076313 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 19:26:03.080075 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 19:26:03.086335 0 10 4 | B1->B0 | 2929 3131 | 0 0 | (0 0) (0 1)
1851 19:26:03.089643 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 19:26:03.093254 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 19:26:03.099994 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 19:26:03.103245 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 19:26:03.106568 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 19:26:03.112890 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 19:26:03.116566 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 19:26:03.119660 0 11 4 | B1->B0 | 3232 3232 | 0 0 | (0 0) (0 0)
1859 19:26:03.126407 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 19:26:03.129875 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 19:26:03.132993 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 19:26:03.139681 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 19:26:03.142886 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 19:26:03.146252 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 19:26:03.149967 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 19:26:03.156320 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 19:26:03.159689 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1868 19:26:03.163188 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 19:26:03.169719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 19:26:03.173000 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 19:26:03.176376 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 19:26:03.183071 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 19:26:03.186281 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 19:26:03.189744 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 19:26:03.196469 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 19:26:03.199912 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 19:26:03.203399 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 19:26:03.209798 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 19:26:03.213220 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 19:26:03.216512 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 19:26:03.223510 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 19:26:03.226346 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1883 19:26:03.230092 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1884 19:26:03.236271 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 19:26:03.236354 Total UI for P1: 0, mck2ui 16
1886 19:26:03.240178 best dqsien dly found for B0: ( 0, 14, 6)
1887 19:26:03.243261 Total UI for P1: 0, mck2ui 16
1888 19:26:03.246632 best dqsien dly found for B1: ( 0, 14, 6)
1889 19:26:03.250037 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1890 19:26:03.253253 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1891 19:26:03.256518
1892 19:26:03.259770 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1893 19:26:03.263059 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1894 19:26:03.266488 [Gating] SW calibration Done
1895 19:26:03.266631 ==
1896 19:26:03.269890 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 19:26:03.273224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 19:26:03.273334 ==
1899 19:26:03.273437 RX Vref Scan: 0
1900 19:26:03.273500
1901 19:26:03.276499 RX Vref 0 -> 0, step: 1
1902 19:26:03.276581
1903 19:26:03.279995 RX Delay -130 -> 252, step: 16
1904 19:26:03.283271 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1905 19:26:03.286584 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1906 19:26:03.293250 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1907 19:26:03.296748 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1908 19:26:03.299931 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1909 19:26:03.303475 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1910 19:26:03.306803 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1911 19:26:03.310497 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1912 19:26:03.316653 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1913 19:26:03.320030 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1914 19:26:03.323736 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1915 19:26:03.326970 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1916 19:26:03.330495 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1917 19:26:03.336905 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1918 19:26:03.340185 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1919 19:26:03.343649 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1920 19:26:03.343732 ==
1921 19:26:03.346926 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 19:26:03.350120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 19:26:03.350203 ==
1924 19:26:03.353249 DQS Delay:
1925 19:26:03.353372 DQS0 = 0, DQS1 = 0
1926 19:26:03.356704 DQM Delay:
1927 19:26:03.356785 DQM0 = 90, DQM1 = 84
1928 19:26:03.356851 DQ Delay:
1929 19:26:03.360052 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1930 19:26:03.363577 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1931 19:26:03.366943 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1932 19:26:03.370252 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1933 19:26:03.370338
1934 19:26:03.370420
1935 19:26:03.373874 ==
1936 19:26:03.376746 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 19:26:03.380287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 19:26:03.380370 ==
1939 19:26:03.380436
1940 19:26:03.380497
1941 19:26:03.383454 TX Vref Scan disable
1942 19:26:03.383536 == TX Byte 0 ==
1943 19:26:03.386585 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1944 19:26:03.393489 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1945 19:26:03.393571 == TX Byte 1 ==
1946 19:26:03.396868 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1947 19:26:03.403266 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1948 19:26:03.403348 ==
1949 19:26:03.406668 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 19:26:03.410313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 19:26:03.410395 ==
1952 19:26:03.423090 TX Vref=22, minBit 13, minWin=27, winSum=452
1953 19:26:03.426501 TX Vref=24, minBit 13, minWin=27, winSum=453
1954 19:26:03.429894 TX Vref=26, minBit 13, minWin=27, winSum=456
1955 19:26:03.433046 TX Vref=28, minBit 8, minWin=28, winSum=459
1956 19:26:03.436280 TX Vref=30, minBit 8, minWin=28, winSum=461
1957 19:26:03.443246 TX Vref=32, minBit 8, minWin=28, winSum=458
1958 19:26:03.446496 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1959 19:26:03.446579
1960 19:26:03.449762 Final TX Range 1 Vref 30
1961 19:26:03.449845
1962 19:26:03.449912 ==
1963 19:26:03.453122 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 19:26:03.456482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 19:26:03.456564 ==
1966 19:26:03.459719
1967 19:26:03.459800
1968 19:26:03.459865 TX Vref Scan disable
1969 19:26:03.463193 == TX Byte 0 ==
1970 19:26:03.466902 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1971 19:26:03.469924 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1972 19:26:03.473271 == TX Byte 1 ==
1973 19:26:03.476591 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1974 19:26:03.479958 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1975 19:26:03.483524
1976 19:26:03.483606 [DATLAT]
1977 19:26:03.483671 Freq=800, CH1 RK1
1978 19:26:03.483732
1979 19:26:03.486531 DATLAT Default: 0xa
1980 19:26:03.486613 0, 0xFFFF, sum = 0
1981 19:26:03.490129 1, 0xFFFF, sum = 0
1982 19:26:03.490213 2, 0xFFFF, sum = 0
1983 19:26:03.493596 3, 0xFFFF, sum = 0
1984 19:26:03.493679 4, 0xFFFF, sum = 0
1985 19:26:03.496470 5, 0xFFFF, sum = 0
1986 19:26:03.496553 6, 0xFFFF, sum = 0
1987 19:26:03.500304 7, 0xFFFF, sum = 0
1988 19:26:03.503179 8, 0xFFFF, sum = 0
1989 19:26:03.503264 9, 0x0, sum = 1
1990 19:26:03.503368 10, 0x0, sum = 2
1991 19:26:03.507119 11, 0x0, sum = 3
1992 19:26:03.507200 12, 0x0, sum = 4
1993 19:26:03.509785 best_step = 10
1994 19:26:03.509866
1995 19:26:03.509930 ==
1996 19:26:03.513754 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 19:26:03.516517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 19:26:03.516598 ==
1999 19:26:03.520067 RX Vref Scan: 0
2000 19:26:03.520147
2001 19:26:03.520211 RX Vref 0 -> 0, step: 1
2002 19:26:03.520270
2003 19:26:03.523067 RX Delay -95 -> 252, step: 8
2004 19:26:03.529978 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2005 19:26:03.533562 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2006 19:26:03.536505 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2007 19:26:03.539985 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2008 19:26:03.543043 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2009 19:26:03.549995 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2010 19:26:03.553266 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2011 19:26:03.556813 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2012 19:26:03.560138 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2013 19:26:03.563486 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2014 19:26:03.569890 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2015 19:26:03.573577 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2016 19:26:03.576850 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2017 19:26:03.580180 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2018 19:26:03.583451 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2019 19:26:03.590103 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2020 19:26:03.590185 ==
2021 19:26:03.593688 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 19:26:03.596888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 19:26:03.596995 ==
2024 19:26:03.597062 DQS Delay:
2025 19:26:03.600204 DQS0 = 0, DQS1 = 0
2026 19:26:03.600284 DQM Delay:
2027 19:26:03.603395 DQM0 = 91, DQM1 = 83
2028 19:26:03.603477 DQ Delay:
2029 19:26:03.607017 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2030 19:26:03.610395 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2031 19:26:03.613407 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2032 19:26:03.616858 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2033 19:26:03.616943
2034 19:26:03.617020
2035 19:26:03.623392 [DQSOSCAuto] RK1, (LSB)MR18= 0x370d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2036 19:26:03.627008 CH1 RK1: MR19=606, MR18=370D
2037 19:26:03.633775 CH1_RK1: MR19=0x606, MR18=0x370D, DQSOSC=395, MR23=63, INC=94, DEC=63
2038 19:26:03.637480 [RxdqsGatingPostProcess] freq 800
2039 19:26:03.643786 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2040 19:26:03.643869 Pre-setting of DQS Precalculation
2041 19:26:03.650250 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2042 19:26:03.657134 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2043 19:26:03.663842 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2044 19:26:03.663927
2045 19:26:03.663993
2046 19:26:03.667141 [Calibration Summary] 1600 Mbps
2047 19:26:03.670338 CH 0, Rank 0
2048 19:26:03.670420 SW Impedance : PASS
2049 19:26:03.674055 DUTY Scan : NO K
2050 19:26:03.674137 ZQ Calibration : PASS
2051 19:26:03.677066 Jitter Meter : NO K
2052 19:26:03.680481 CBT Training : PASS
2053 19:26:03.680563 Write leveling : PASS
2054 19:26:03.683949 RX DQS gating : PASS
2055 19:26:03.687409 RX DQ/DQS(RDDQC) : PASS
2056 19:26:03.687492 TX DQ/DQS : PASS
2057 19:26:03.690740 RX DATLAT : PASS
2058 19:26:03.693918 RX DQ/DQS(Engine): PASS
2059 19:26:03.694001 TX OE : NO K
2060 19:26:03.694067 All Pass.
2061 19:26:03.697155
2062 19:26:03.697237 CH 0, Rank 1
2063 19:26:03.700455 SW Impedance : PASS
2064 19:26:03.700536 DUTY Scan : NO K
2065 19:26:03.704196 ZQ Calibration : PASS
2066 19:26:03.704278 Jitter Meter : NO K
2067 19:26:03.707575 CBT Training : PASS
2068 19:26:03.710463 Write leveling : PASS
2069 19:26:03.710545 RX DQS gating : PASS
2070 19:26:03.713914 RX DQ/DQS(RDDQC) : PASS
2071 19:26:03.717205 TX DQ/DQS : PASS
2072 19:26:03.717349 RX DATLAT : PASS
2073 19:26:03.720493 RX DQ/DQS(Engine): PASS
2074 19:26:03.723802 TX OE : NO K
2075 19:26:03.723885 All Pass.
2076 19:26:03.723950
2077 19:26:03.724009 CH 1, Rank 0
2078 19:26:03.727109 SW Impedance : PASS
2079 19:26:03.730917 DUTY Scan : NO K
2080 19:26:03.730999 ZQ Calibration : PASS
2081 19:26:03.734041 Jitter Meter : NO K
2082 19:26:03.737236 CBT Training : PASS
2083 19:26:03.737353 Write leveling : PASS
2084 19:26:03.740600 RX DQS gating : PASS
2085 19:26:03.743778 RX DQ/DQS(RDDQC) : PASS
2086 19:26:03.743860 TX DQ/DQS : PASS
2087 19:26:03.747134 RX DATLAT : PASS
2088 19:26:03.747216 RX DQ/DQS(Engine): PASS
2089 19:26:03.750417 TX OE : NO K
2090 19:26:03.750525 All Pass.
2091 19:26:03.750617
2092 19:26:03.753973 CH 1, Rank 1
2093 19:26:03.754055 SW Impedance : PASS
2094 19:26:03.757110 DUTY Scan : NO K
2095 19:26:03.760924 ZQ Calibration : PASS
2096 19:26:03.761006 Jitter Meter : NO K
2097 19:26:03.764118 CBT Training : PASS
2098 19:26:03.767209 Write leveling : PASS
2099 19:26:03.767291 RX DQS gating : PASS
2100 19:26:03.770662 RX DQ/DQS(RDDQC) : PASS
2101 19:26:03.773790 TX DQ/DQS : PASS
2102 19:26:03.773873 RX DATLAT : PASS
2103 19:26:03.777492 RX DQ/DQS(Engine): PASS
2104 19:26:03.780695 TX OE : NO K
2105 19:26:03.780778 All Pass.
2106 19:26:03.780844
2107 19:26:03.780905 DramC Write-DBI off
2108 19:26:03.783831 PER_BANK_REFRESH: Hybrid Mode
2109 19:26:03.787821 TX_TRACKING: ON
2110 19:26:03.790517 [GetDramInforAfterCalByMRR] Vendor 6.
2111 19:26:03.794297 [GetDramInforAfterCalByMRR] Revision 606.
2112 19:26:03.797239 [GetDramInforAfterCalByMRR] Revision 2 0.
2113 19:26:03.797345 MR0 0x3b3b
2114 19:26:03.800620 MR8 0x5151
2115 19:26:03.803967 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 19:26:03.804049
2117 19:26:03.804116 MR0 0x3b3b
2118 19:26:03.804176 MR8 0x5151
2119 19:26:03.807527 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 19:26:03.810459
2121 19:26:03.817319 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2122 19:26:03.820631 [FAST_K] Save calibration result to emmc
2123 19:26:03.824016 [FAST_K] Save calibration result to emmc
2124 19:26:03.827294 dram_init: config_dvfs: 1
2125 19:26:03.830587 dramc_set_vcore_voltage set vcore to 662500
2126 19:26:03.833937 Read voltage for 1200, 2
2127 19:26:03.834020 Vio18 = 0
2128 19:26:03.837406 Vcore = 662500
2129 19:26:03.837488 Vdram = 0
2130 19:26:03.837554 Vddq = 0
2131 19:26:03.837614 Vmddr = 0
2132 19:26:03.844351 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2133 19:26:03.850666 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2134 19:26:03.850751 MEM_TYPE=3, freq_sel=15
2135 19:26:03.853613 sv_algorithm_assistance_LP4_1600
2136 19:26:03.856982 ============ PULL DRAM RESETB DOWN ============
2137 19:26:03.863827 ========== PULL DRAM RESETB DOWN end =========
2138 19:26:03.867315 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2139 19:26:03.870423 ===================================
2140 19:26:03.873621 LPDDR4 DRAM CONFIGURATION
2141 19:26:03.877079 ===================================
2142 19:26:03.877164 EX_ROW_EN[0] = 0x0
2143 19:26:03.880607 EX_ROW_EN[1] = 0x0
2144 19:26:03.880690 LP4Y_EN = 0x0
2145 19:26:03.883808 WORK_FSP = 0x0
2146 19:26:03.883892 WL = 0x4
2147 19:26:03.887240 RL = 0x4
2148 19:26:03.887324 BL = 0x2
2149 19:26:03.890391 RPST = 0x0
2150 19:26:03.890474 RD_PRE = 0x0
2151 19:26:03.894151 WR_PRE = 0x1
2152 19:26:03.894235 WR_PST = 0x0
2153 19:26:03.897258 DBI_WR = 0x0
2154 19:26:03.900507 DBI_RD = 0x0
2155 19:26:03.900590 OTF = 0x1
2156 19:26:03.903826 ===================================
2157 19:26:03.907323 ===================================
2158 19:26:03.907404 ANA top config
2159 19:26:03.910512 ===================================
2160 19:26:03.913809 DLL_ASYNC_EN = 0
2161 19:26:03.917179 ALL_SLAVE_EN = 0
2162 19:26:03.920614 NEW_RANK_MODE = 1
2163 19:26:03.923718 DLL_IDLE_MODE = 1
2164 19:26:03.923800 LP45_APHY_COMB_EN = 1
2165 19:26:03.927004 TX_ODT_DIS = 1
2166 19:26:03.930265 NEW_8X_MODE = 1
2167 19:26:03.933699 ===================================
2168 19:26:03.936928 ===================================
2169 19:26:03.940528 data_rate = 2400
2170 19:26:03.943768 CKR = 1
2171 19:26:03.943851 DQ_P2S_RATIO = 8
2172 19:26:03.946880 ===================================
2173 19:26:03.950333 CA_P2S_RATIO = 8
2174 19:26:03.953674 DQ_CA_OPEN = 0
2175 19:26:03.957278 DQ_SEMI_OPEN = 0
2176 19:26:03.960577 CA_SEMI_OPEN = 0
2177 19:26:03.960660 CA_FULL_RATE = 0
2178 19:26:03.963691 DQ_CKDIV4_EN = 0
2179 19:26:03.967257 CA_CKDIV4_EN = 0
2180 19:26:03.970716 CA_PREDIV_EN = 0
2181 19:26:03.974225 PH8_DLY = 17
2182 19:26:03.977492 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2183 19:26:03.977576 DQ_AAMCK_DIV = 4
2184 19:26:03.980495 CA_AAMCK_DIV = 4
2185 19:26:03.984112 CA_ADMCK_DIV = 4
2186 19:26:03.987180 DQ_TRACK_CA_EN = 0
2187 19:26:03.990626 CA_PICK = 1200
2188 19:26:03.994080 CA_MCKIO = 1200
2189 19:26:03.997328 MCKIO_SEMI = 0
2190 19:26:03.997437 PLL_FREQ = 2366
2191 19:26:04.000815 DQ_UI_PI_RATIO = 32
2192 19:26:04.004034 CA_UI_PI_RATIO = 0
2193 19:26:04.007860 ===================================
2194 19:26:04.010842 ===================================
2195 19:26:04.014172 memory_type:LPDDR4
2196 19:26:04.014256 GP_NUM : 10
2197 19:26:04.017238 SRAM_EN : 1
2198 19:26:04.021109 MD32_EN : 0
2199 19:26:04.024196 ===================================
2200 19:26:04.024280 [ANA_INIT] >>>>>>>>>>>>>>
2201 19:26:04.027413 <<<<<< [CONFIGURE PHASE]: ANA_TX
2202 19:26:04.030900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2203 19:26:04.034235 ===================================
2204 19:26:04.037411 data_rate = 2400,PCW = 0X5b00
2205 19:26:04.040674 ===================================
2206 19:26:04.044212 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2207 19:26:04.050788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 19:26:04.054344 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 19:26:04.061076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2210 19:26:04.064392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2211 19:26:04.067624 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2212 19:26:04.067710 [ANA_INIT] flow start
2213 19:26:04.070953 [ANA_INIT] PLL >>>>>>>>
2214 19:26:04.074107 [ANA_INIT] PLL <<<<<<<<
2215 19:26:04.074193 [ANA_INIT] MIDPI >>>>>>>>
2216 19:26:04.077610 [ANA_INIT] MIDPI <<<<<<<<
2217 19:26:04.080876 [ANA_INIT] DLL >>>>>>>>
2218 19:26:04.080960 [ANA_INIT] DLL <<<<<<<<
2219 19:26:04.084164 [ANA_INIT] flow end
2220 19:26:04.087488 ============ LP4 DIFF to SE enter ============
2221 19:26:04.094297 ============ LP4 DIFF to SE exit ============
2222 19:26:04.094387 [ANA_INIT] <<<<<<<<<<<<<
2223 19:26:04.097814 [Flow] Enable top DCM control >>>>>
2224 19:26:04.101161 [Flow] Enable top DCM control <<<<<
2225 19:26:04.104509 Enable DLL master slave shuffle
2226 19:26:04.111038 ==============================================================
2227 19:26:04.111125 Gating Mode config
2228 19:26:04.117625 ==============================================================
2229 19:26:04.117710 Config description:
2230 19:26:04.127662 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2231 19:26:04.134452 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2232 19:26:04.140996 SELPH_MODE 0: By rank 1: By Phase
2233 19:26:04.144307 ==============================================================
2234 19:26:04.147905 GAT_TRACK_EN = 1
2235 19:26:04.151250 RX_GATING_MODE = 2
2236 19:26:04.154601 RX_GATING_TRACK_MODE = 2
2237 19:26:04.157995 SELPH_MODE = 1
2238 19:26:04.161225 PICG_EARLY_EN = 1
2239 19:26:04.164621 VALID_LAT_VALUE = 1
2240 19:26:04.171190 ==============================================================
2241 19:26:04.174295 Enter into Gating configuration >>>>
2242 19:26:04.177590 Exit from Gating configuration <<<<
2243 19:26:04.177675 Enter into DVFS_PRE_config >>>>>
2244 19:26:04.191299 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2245 19:26:04.194576 Exit from DVFS_PRE_config <<<<<
2246 19:26:04.197646 Enter into PICG configuration >>>>
2247 19:26:04.201085 Exit from PICG configuration <<<<
2248 19:26:04.201169 [RX_INPUT] configuration >>>>>
2249 19:26:04.204645 [RX_INPUT] configuration <<<<<
2250 19:26:04.211087 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2251 19:26:04.214701 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2252 19:26:04.221432 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 19:26:04.227984 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 19:26:04.234730 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 19:26:04.241175 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 19:26:04.244708 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2257 19:26:04.248057 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2258 19:26:04.251409 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2259 19:26:04.257936 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2260 19:26:04.261215 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2261 19:26:04.265081 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 19:26:04.268083 ===================================
2263 19:26:04.271160 LPDDR4 DRAM CONFIGURATION
2264 19:26:04.274604 ===================================
2265 19:26:04.274689 EX_ROW_EN[0] = 0x0
2266 19:26:04.277694 EX_ROW_EN[1] = 0x0
2267 19:26:04.281482 LP4Y_EN = 0x0
2268 19:26:04.281565 WORK_FSP = 0x0
2269 19:26:04.284398 WL = 0x4
2270 19:26:04.284482 RL = 0x4
2271 19:26:04.287709 BL = 0x2
2272 19:26:04.287793 RPST = 0x0
2273 19:26:04.291239 RD_PRE = 0x0
2274 19:26:04.291323 WR_PRE = 0x1
2275 19:26:04.294823 WR_PST = 0x0
2276 19:26:04.294907 DBI_WR = 0x0
2277 19:26:04.297901 DBI_RD = 0x0
2278 19:26:04.297984 OTF = 0x1
2279 19:26:04.301271 ===================================
2280 19:26:04.304509 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2281 19:26:04.311093 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2282 19:26:04.314437 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 19:26:04.317910 ===================================
2284 19:26:04.321391 LPDDR4 DRAM CONFIGURATION
2285 19:26:04.324473 ===================================
2286 19:26:04.324557 EX_ROW_EN[0] = 0x10
2287 19:26:04.327768 EX_ROW_EN[1] = 0x0
2288 19:26:04.330952 LP4Y_EN = 0x0
2289 19:26:04.331034 WORK_FSP = 0x0
2290 19:26:04.334469 WL = 0x4
2291 19:26:04.334551 RL = 0x4
2292 19:26:04.337810 BL = 0x2
2293 19:26:04.337891 RPST = 0x0
2294 19:26:04.340972 RD_PRE = 0x0
2295 19:26:04.341053 WR_PRE = 0x1
2296 19:26:04.344278 WR_PST = 0x0
2297 19:26:04.344359 DBI_WR = 0x0
2298 19:26:04.347834 DBI_RD = 0x0
2299 19:26:04.347945 OTF = 0x1
2300 19:26:04.351085 ===================================
2301 19:26:04.357786 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2302 19:26:04.357868 ==
2303 19:26:04.360850 Dram Type= 6, Freq= 0, CH_0, rank 0
2304 19:26:04.364342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2305 19:26:04.364423 ==
2306 19:26:04.367778 [Duty_Offset_Calibration]
2307 19:26:04.370818 B0:2 B1:0 CA:1
2308 19:26:04.370901
2309 19:26:04.374349 [DutyScan_Calibration_Flow] k_type=0
2310 19:26:04.381613
2311 19:26:04.381727 ==CLK 0==
2312 19:26:04.385092 Final CLK duty delay cell = -4
2313 19:26:04.388604 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2314 19:26:04.391912 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2315 19:26:04.395240 [-4] AVG Duty = 4953%(X100)
2316 19:26:04.395321
2317 19:26:04.398665 CH0 CLK Duty spec in!! Max-Min= 156%
2318 19:26:04.401832 [DutyScan_Calibration_Flow] ====Done====
2319 19:26:04.401913
2320 19:26:04.404899 [DutyScan_Calibration_Flow] k_type=1
2321 19:26:04.420604
2322 19:26:04.420685 ==DQS 0 ==
2323 19:26:04.424323 Final DQS duty delay cell = 0
2324 19:26:04.427262 [0] MAX Duty = 5187%(X100), DQS PI = 32
2325 19:26:04.430847 [0] MIN Duty = 4938%(X100), DQS PI = 0
2326 19:26:04.430928 [0] AVG Duty = 5062%(X100)
2327 19:26:04.434087
2328 19:26:04.434173 ==DQS 1 ==
2329 19:26:04.437085 Final DQS duty delay cell = -4
2330 19:26:04.440508 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2331 19:26:04.443843 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2332 19:26:04.447157 [-4] AVG Duty = 5031%(X100)
2333 19:26:04.447237
2334 19:26:04.450430 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2335 19:26:04.450510
2336 19:26:04.454133 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2337 19:26:04.457077 [DutyScan_Calibration_Flow] ====Done====
2338 19:26:04.457156
2339 19:26:04.460508 [DutyScan_Calibration_Flow] k_type=3
2340 19:26:04.477434
2341 19:26:04.477549 ==DQM 0 ==
2342 19:26:04.480588 Final DQM duty delay cell = 0
2343 19:26:04.483986 [0] MAX Duty = 5062%(X100), DQS PI = 26
2344 19:26:04.487338 [0] MIN Duty = 4813%(X100), DQS PI = 0
2345 19:26:04.487419 [0] AVG Duty = 4937%(X100)
2346 19:26:04.490505
2347 19:26:04.490585 ==DQM 1 ==
2348 19:26:04.494004 Final DQM duty delay cell = 0
2349 19:26:04.497482 [0] MAX Duty = 5187%(X100), DQS PI = 46
2350 19:26:04.500659 [0] MIN Duty = 5000%(X100), DQS PI = 12
2351 19:26:04.500740 [0] AVG Duty = 5093%(X100)
2352 19:26:04.504190
2353 19:26:04.507677 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2354 19:26:04.507756
2355 19:26:04.510769 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2356 19:26:04.514081 [DutyScan_Calibration_Flow] ====Done====
2357 19:26:04.514160
2358 19:26:04.517303 [DutyScan_Calibration_Flow] k_type=2
2359 19:26:04.533880
2360 19:26:04.533961 ==DQ 0 ==
2361 19:26:04.537234 Final DQ duty delay cell = -4
2362 19:26:04.540552 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2363 19:26:04.543636 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2364 19:26:04.547305 [-4] AVG Duty = 4953%(X100)
2365 19:26:04.547384
2366 19:26:04.547447 ==DQ 1 ==
2367 19:26:04.550528 Final DQ duty delay cell = 4
2368 19:26:04.553925 [4] MAX Duty = 5093%(X100), DQS PI = 6
2369 19:26:04.557587 [4] MIN Duty = 5031%(X100), DQS PI = 0
2370 19:26:04.557666 [4] AVG Duty = 5062%(X100)
2371 19:26:04.560928
2372 19:26:04.563686 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2373 19:26:04.563771
2374 19:26:04.566920 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2375 19:26:04.570496 [DutyScan_Calibration_Flow] ====Done====
2376 19:26:04.570576 ==
2377 19:26:04.573682 Dram Type= 6, Freq= 0, CH_1, rank 0
2378 19:26:04.577279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2379 19:26:04.577413 ==
2380 19:26:04.580482 [Duty_Offset_Calibration]
2381 19:26:04.580577 B0:0 B1:-1 CA:2
2382 19:26:04.580640
2383 19:26:04.583736 [DutyScan_Calibration_Flow] k_type=0
2384 19:26:04.594301
2385 19:26:04.594385 ==CLK 0==
2386 19:26:04.597546 Final CLK duty delay cell = 0
2387 19:26:04.600587 [0] MAX Duty = 5156%(X100), DQS PI = 16
2388 19:26:04.604154 [0] MIN Duty = 4938%(X100), DQS PI = 44
2389 19:26:04.604237 [0] AVG Duty = 5047%(X100)
2390 19:26:04.607228
2391 19:26:04.607310 CH1 CLK Duty spec in!! Max-Min= 218%
2392 19:26:04.614003 [DutyScan_Calibration_Flow] ====Done====
2393 19:26:04.614086
2394 19:26:04.617572 [DutyScan_Calibration_Flow] k_type=1
2395 19:26:04.633462
2396 19:26:04.633554 ==DQS 0 ==
2397 19:26:04.636984 Final DQS duty delay cell = 0
2398 19:26:04.639944 [0] MAX Duty = 5093%(X100), DQS PI = 26
2399 19:26:04.643494 [0] MIN Duty = 4969%(X100), DQS PI = 0
2400 19:26:04.643577 [0] AVG Duty = 5031%(X100)
2401 19:26:04.646606
2402 19:26:04.646687 ==DQS 1 ==
2403 19:26:04.650286 Final DQS duty delay cell = 0
2404 19:26:04.653530 [0] MAX Duty = 5156%(X100), DQS PI = 0
2405 19:26:04.656741 [0] MIN Duty = 4844%(X100), DQS PI = 36
2406 19:26:04.656823 [0] AVG Duty = 5000%(X100)
2407 19:26:04.656889
2408 19:26:04.663859 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2409 19:26:04.663944
2410 19:26:04.667033 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2411 19:26:04.670406 [DutyScan_Calibration_Flow] ====Done====
2412 19:26:04.670490
2413 19:26:04.673362 [DutyScan_Calibration_Flow] k_type=3
2414 19:26:04.690670
2415 19:26:04.690772 ==DQM 0 ==
2416 19:26:04.693840 Final DQM duty delay cell = 4
2417 19:26:04.697340 [4] MAX Duty = 5093%(X100), DQS PI = 6
2418 19:26:04.700629 [4] MIN Duty = 4969%(X100), DQS PI = 28
2419 19:26:04.700711 [4] AVG Duty = 5031%(X100)
2420 19:26:04.703837
2421 19:26:04.703918 ==DQM 1 ==
2422 19:26:04.707131 Final DQM duty delay cell = 0
2423 19:26:04.710405 [0] MAX Duty = 5249%(X100), DQS PI = 0
2424 19:26:04.713761 [0] MIN Duty = 4875%(X100), DQS PI = 36
2425 19:26:04.713844 [0] AVG Duty = 5062%(X100)
2426 19:26:04.717049
2427 19:26:04.720718 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2428 19:26:04.720800
2429 19:26:04.723923 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2430 19:26:04.727407 [DutyScan_Calibration_Flow] ====Done====
2431 19:26:04.727489
2432 19:26:04.730429 [DutyScan_Calibration_Flow] k_type=2
2433 19:26:04.747023
2434 19:26:04.747115 ==DQ 0 ==
2435 19:26:04.750230 Final DQ duty delay cell = 0
2436 19:26:04.753619 [0] MAX Duty = 5031%(X100), DQS PI = 18
2437 19:26:04.756977 [0] MIN Duty = 4938%(X100), DQS PI = 0
2438 19:26:04.757059 [0] AVG Duty = 4984%(X100)
2439 19:26:04.757125
2440 19:26:04.760508 ==DQ 1 ==
2441 19:26:04.763551 Final DQ duty delay cell = 0
2442 19:26:04.767129 [0] MAX Duty = 5062%(X100), DQS PI = 4
2443 19:26:04.770475 [0] MIN Duty = 4813%(X100), DQS PI = 34
2444 19:26:04.770558 [0] AVG Duty = 4937%(X100)
2445 19:26:04.770622
2446 19:26:04.773773 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2447 19:26:04.773855
2448 19:26:04.777193 CH1 DQ 1 Duty spec in!! Max-Min= 249%
2449 19:26:04.783542 [DutyScan_Calibration_Flow] ====Done====
2450 19:26:04.786904 nWR fixed to 30
2451 19:26:04.786986 [ModeRegInit_LP4] CH0 RK0
2452 19:26:04.790134 [ModeRegInit_LP4] CH0 RK1
2453 19:26:04.793409 [ModeRegInit_LP4] CH1 RK0
2454 19:26:04.793491 [ModeRegInit_LP4] CH1 RK1
2455 19:26:04.796941 match AC timing 7
2456 19:26:04.800054 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2457 19:26:04.803351 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2458 19:26:04.810086 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2459 19:26:04.813806 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2460 19:26:04.820424 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2461 19:26:04.820508 ==
2462 19:26:04.823553 Dram Type= 6, Freq= 0, CH_0, rank 0
2463 19:26:04.827176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2464 19:26:04.827260 ==
2465 19:26:04.833564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2466 19:26:04.836836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2467 19:26:04.846730 [CA 0] Center 38 (8~69) winsize 62
2468 19:26:04.850131 [CA 1] Center 38 (8~69) winsize 62
2469 19:26:04.853584 [CA 2] Center 35 (5~66) winsize 62
2470 19:26:04.857096 [CA 3] Center 35 (4~66) winsize 63
2471 19:26:04.860397 [CA 4] Center 34 (4~65) winsize 62
2472 19:26:04.863456 [CA 5] Center 33 (3~63) winsize 61
2473 19:26:04.863540
2474 19:26:04.866725 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2475 19:26:04.866831
2476 19:26:04.870153 [CATrainingPosCal] consider 1 rank data
2477 19:26:04.873246 u2DelayCellTimex100 = 270/100 ps
2478 19:26:04.876836 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2479 19:26:04.879896 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2480 19:26:04.886744 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2481 19:26:04.890080 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2482 19:26:04.893365 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2483 19:26:04.896770 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2484 19:26:04.896854
2485 19:26:04.900015 CA PerBit enable=1, Macro0, CA PI delay=33
2486 19:26:04.900099
2487 19:26:04.903195 [CBTSetCACLKResult] CA Dly = 33
2488 19:26:04.903295 CS Dly: 6 (0~37)
2489 19:26:04.903390 ==
2490 19:26:04.906678 Dram Type= 6, Freq= 0, CH_0, rank 1
2491 19:26:04.913457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 19:26:04.913542 ==
2493 19:26:04.916875 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 19:26:04.923193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2495 19:26:04.932792 [CA 0] Center 39 (8~70) winsize 63
2496 19:26:04.935555 [CA 1] Center 38 (8~69) winsize 62
2497 19:26:04.939081 [CA 2] Center 35 (5~66) winsize 62
2498 19:26:04.942774 [CA 3] Center 35 (5~66) winsize 62
2499 19:26:04.946123 [CA 4] Center 34 (4~65) winsize 62
2500 19:26:04.949237 [CA 5] Center 34 (4~64) winsize 61
2501 19:26:04.949346
2502 19:26:04.952280 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2503 19:26:04.952363
2504 19:26:04.955654 [CATrainingPosCal] consider 2 rank data
2505 19:26:04.959097 u2DelayCellTimex100 = 270/100 ps
2506 19:26:04.962304 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2507 19:26:04.965651 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2508 19:26:04.972305 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2509 19:26:04.975632 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2510 19:26:04.979391 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2511 19:26:04.982377 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2512 19:26:04.982460
2513 19:26:04.985747 CA PerBit enable=1, Macro0, CA PI delay=33
2514 19:26:04.985830
2515 19:26:04.989517 [CBTSetCACLKResult] CA Dly = 33
2516 19:26:04.989616 CS Dly: 7 (0~39)
2517 19:26:04.989711
2518 19:26:04.992559 ----->DramcWriteLeveling(PI) begin...
2519 19:26:04.992642 ==
2520 19:26:04.995910 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 19:26:05.002483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 19:26:05.002569 ==
2523 19:26:05.005922 Write leveling (Byte 0): 35 => 35
2524 19:26:05.009046 Write leveling (Byte 1): 30 => 30
2525 19:26:05.009130 DramcWriteLeveling(PI) end<-----
2526 19:26:05.012569
2527 19:26:05.012652 ==
2528 19:26:05.015929 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 19:26:05.019402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 19:26:05.019486 ==
2531 19:26:05.022480 [Gating] SW mode calibration
2532 19:26:05.029152 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2533 19:26:05.032482 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2534 19:26:05.039450 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2535 19:26:05.042639 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2536 19:26:05.045756 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 19:26:05.052673 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 19:26:05.056052 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 19:26:05.059090 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 19:26:05.065807 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2541 19:26:05.069263 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2542 19:26:05.072593 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
2543 19:26:05.079733 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 19:26:05.082696 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 19:26:05.086490 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 19:26:05.089428 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 19:26:05.096039 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 19:26:05.099393 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2549 19:26:05.103051 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2550 19:26:05.109529 1 1 0 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
2551 19:26:05.112816 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 19:26:05.116507 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 19:26:05.122796 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 19:26:05.126214 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 19:26:05.129659 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 19:26:05.136049 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 19:26:05.139471 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2558 19:26:05.142848 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2559 19:26:05.149704 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 19:26:05.152802 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 19:26:05.156344 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 19:26:05.163227 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 19:26:05.166346 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 19:26:05.169480 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 19:26:05.172979 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 19:26:05.179327 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 19:26:05.182843 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 19:26:05.186383 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 19:26:05.193066 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 19:26:05.196426 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 19:26:05.199586 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 19:26:05.206339 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 19:26:05.209523 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2574 19:26:05.212828 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2575 19:26:05.216416 Total UI for P1: 0, mck2ui 16
2576 19:26:05.219605 best dqsien dly found for B0: ( 1, 3, 28)
2577 19:26:05.226128 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 19:26:05.226215 Total UI for P1: 0, mck2ui 16
2579 19:26:05.232797 best dqsien dly found for B1: ( 1, 4, 0)
2580 19:26:05.236460 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2581 19:26:05.239504 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2582 19:26:05.239589
2583 19:26:05.242817 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2584 19:26:05.246416 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2585 19:26:05.249693 [Gating] SW calibration Done
2586 19:26:05.249776 ==
2587 19:26:05.252945 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 19:26:05.256318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 19:26:05.256402 ==
2590 19:26:05.259522 RX Vref Scan: 0
2591 19:26:05.259605
2592 19:26:05.259671 RX Vref 0 -> 0, step: 1
2593 19:26:05.259731
2594 19:26:05.262899 RX Delay -40 -> 252, step: 8
2595 19:26:05.266442 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2596 19:26:05.272883 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2597 19:26:05.276261 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2598 19:26:05.279934 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2599 19:26:05.282945 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2600 19:26:05.286523 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2601 19:26:05.289390 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2602 19:26:05.296597 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2603 19:26:05.299884 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2604 19:26:05.303021 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2605 19:26:05.306401 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2606 19:26:05.309702 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2607 19:26:05.316213 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2608 19:26:05.319675 iDelay=200, Bit 13, Center 111 (48 ~ 175) 128
2609 19:26:05.323166 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2610 19:26:05.326317 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2611 19:26:05.326401 ==
2612 19:26:05.329652 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 19:26:05.333028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 19:26:05.336473 ==
2615 19:26:05.336556 DQS Delay:
2616 19:26:05.336623 DQS0 = 0, DQS1 = 0
2617 19:26:05.340015 DQM Delay:
2618 19:26:05.340098 DQM0 = 122, DQM1 = 110
2619 19:26:05.343441 DQ Delay:
2620 19:26:05.346513 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2621 19:26:05.349733 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2622 19:26:05.352951 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2623 19:26:05.356433 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =115
2624 19:26:05.356517
2625 19:26:05.356584
2626 19:26:05.356646 ==
2627 19:26:05.359822 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 19:26:05.363408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 19:26:05.363492 ==
2630 19:26:05.363559
2631 19:26:05.366838
2632 19:26:05.366920 TX Vref Scan disable
2633 19:26:05.369692 == TX Byte 0 ==
2634 19:26:05.373049 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2635 19:26:05.376679 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2636 19:26:05.379802 == TX Byte 1 ==
2637 19:26:05.383250 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2638 19:26:05.386492 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2639 19:26:05.386576 ==
2640 19:26:05.390025 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 19:26:05.396686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 19:26:05.396770 ==
2643 19:26:05.407300 TX Vref=22, minBit 1, minWin=23, winSum=405
2644 19:26:05.410438 TX Vref=24, minBit 0, minWin=25, winSum=418
2645 19:26:05.414189 TX Vref=26, minBit 0, minWin=24, winSum=415
2646 19:26:05.417260 TX Vref=28, minBit 1, minWin=24, winSum=417
2647 19:26:05.420702 TX Vref=30, minBit 7, minWin=24, winSum=424
2648 19:26:05.424027 TX Vref=32, minBit 2, minWin=25, winSum=422
2649 19:26:05.430807 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 32
2650 19:26:05.430889
2651 19:26:05.433849 Final TX Range 1 Vref 32
2652 19:26:05.433954
2653 19:26:05.434034 ==
2654 19:26:05.437079 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 19:26:05.440373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 19:26:05.440455 ==
2657 19:26:05.440521
2658 19:26:05.443779
2659 19:26:05.443860 TX Vref Scan disable
2660 19:26:05.447180 == TX Byte 0 ==
2661 19:26:05.450589 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2662 19:26:05.453911 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2663 19:26:05.457064 == TX Byte 1 ==
2664 19:26:05.460530 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2665 19:26:05.463829 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2666 19:26:05.463911
2667 19:26:05.467158 [DATLAT]
2668 19:26:05.467240 Freq=1200, CH0 RK0
2669 19:26:05.467306
2670 19:26:05.470443 DATLAT Default: 0xd
2671 19:26:05.470524 0, 0xFFFF, sum = 0
2672 19:26:05.474249 1, 0xFFFF, sum = 0
2673 19:26:05.474348 2, 0xFFFF, sum = 0
2674 19:26:05.477018 3, 0xFFFF, sum = 0
2675 19:26:05.477101 4, 0xFFFF, sum = 0
2676 19:26:05.480308 5, 0xFFFF, sum = 0
2677 19:26:05.480391 6, 0xFFFF, sum = 0
2678 19:26:05.484075 7, 0xFFFF, sum = 0
2679 19:26:05.484158 8, 0xFFFF, sum = 0
2680 19:26:05.487101 9, 0xFFFF, sum = 0
2681 19:26:05.490384 10, 0xFFFF, sum = 0
2682 19:26:05.490467 11, 0xFFFF, sum = 0
2683 19:26:05.493882 12, 0x0, sum = 1
2684 19:26:05.493965 13, 0x0, sum = 2
2685 19:26:05.494031 14, 0x0, sum = 3
2686 19:26:05.497078 15, 0x0, sum = 4
2687 19:26:05.497161 best_step = 13
2688 19:26:05.497227
2689 19:26:05.500620 ==
2690 19:26:05.500702 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 19:26:05.507390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 19:26:05.507473 ==
2693 19:26:05.507539 RX Vref Scan: 1
2694 19:26:05.507599
2695 19:26:05.510778 Set Vref Range= 32 -> 127
2696 19:26:05.510860
2697 19:26:05.513749 RX Vref 32 -> 127, step: 1
2698 19:26:05.513831
2699 19:26:05.517325 RX Delay -13 -> 252, step: 4
2700 19:26:05.517420
2701 19:26:05.520603 Set Vref, RX VrefLevel [Byte0]: 32
2702 19:26:05.523870 [Byte1]: 32
2703 19:26:05.523952
2704 19:26:05.527341 Set Vref, RX VrefLevel [Byte0]: 33
2705 19:26:05.530534 [Byte1]: 33
2706 19:26:05.530616
2707 19:26:05.534212 Set Vref, RX VrefLevel [Byte0]: 34
2708 19:26:05.537575 [Byte1]: 34
2709 19:26:05.541244
2710 19:26:05.541355 Set Vref, RX VrefLevel [Byte0]: 35
2711 19:26:05.544655 [Byte1]: 35
2712 19:26:05.549294
2713 19:26:05.549396 Set Vref, RX VrefLevel [Byte0]: 36
2714 19:26:05.552517 [Byte1]: 36
2715 19:26:05.557241
2716 19:26:05.557344 Set Vref, RX VrefLevel [Byte0]: 37
2717 19:26:05.560283 [Byte1]: 37
2718 19:26:05.564846
2719 19:26:05.567945 Set Vref, RX VrefLevel [Byte0]: 38
2720 19:26:05.571341 [Byte1]: 38
2721 19:26:05.571423
2722 19:26:05.574687 Set Vref, RX VrefLevel [Byte0]: 39
2723 19:26:05.577916 [Byte1]: 39
2724 19:26:05.577998
2725 19:26:05.581660 Set Vref, RX VrefLevel [Byte0]: 40
2726 19:26:05.584900 [Byte1]: 40
2727 19:26:05.588826
2728 19:26:05.588908 Set Vref, RX VrefLevel [Byte0]: 41
2729 19:26:05.591716 [Byte1]: 41
2730 19:26:05.596793
2731 19:26:05.596875 Set Vref, RX VrefLevel [Byte0]: 42
2732 19:26:05.599581 [Byte1]: 42
2733 19:26:05.604542
2734 19:26:05.604624 Set Vref, RX VrefLevel [Byte0]: 43
2735 19:26:05.607813 [Byte1]: 43
2736 19:26:05.612651
2737 19:26:05.612732 Set Vref, RX VrefLevel [Byte0]: 44
2738 19:26:05.615542 [Byte1]: 44
2739 19:26:05.620219
2740 19:26:05.620301 Set Vref, RX VrefLevel [Byte0]: 45
2741 19:26:05.623315 [Byte1]: 45
2742 19:26:05.628042
2743 19:26:05.628123 Set Vref, RX VrefLevel [Byte0]: 46
2744 19:26:05.631256 [Byte1]: 46
2745 19:26:05.636018
2746 19:26:05.636099 Set Vref, RX VrefLevel [Byte0]: 47
2747 19:26:05.639291 [Byte1]: 47
2748 19:26:05.643703
2749 19:26:05.643784 Set Vref, RX VrefLevel [Byte0]: 48
2750 19:26:05.647452 [Byte1]: 48
2751 19:26:05.651634
2752 19:26:05.651716 Set Vref, RX VrefLevel [Byte0]: 49
2753 19:26:05.655138 [Byte1]: 49
2754 19:26:05.659467
2755 19:26:05.659548 Set Vref, RX VrefLevel [Byte0]: 50
2756 19:26:05.662719 [Byte1]: 50
2757 19:26:05.667919
2758 19:26:05.668007 Set Vref, RX VrefLevel [Byte0]: 51
2759 19:26:05.670612 [Byte1]: 51
2760 19:26:05.675552
2761 19:26:05.675636 Set Vref, RX VrefLevel [Byte0]: 52
2762 19:26:05.678754 [Byte1]: 52
2763 19:26:05.683316
2764 19:26:05.683398 Set Vref, RX VrefLevel [Byte0]: 53
2765 19:26:05.686821 [Byte1]: 53
2766 19:26:05.691466
2767 19:26:05.691626 Set Vref, RX VrefLevel [Byte0]: 54
2768 19:26:05.694814 [Byte1]: 54
2769 19:26:05.699358
2770 19:26:05.699520 Set Vref, RX VrefLevel [Byte0]: 55
2771 19:26:05.702334 [Byte1]: 55
2772 19:26:05.706965
2773 19:26:05.707126 Set Vref, RX VrefLevel [Byte0]: 56
2774 19:26:05.710612 [Byte1]: 56
2775 19:26:05.715077
2776 19:26:05.715240 Set Vref, RX VrefLevel [Byte0]: 57
2777 19:26:05.718531 [Byte1]: 57
2778 19:26:05.722885
2779 19:26:05.723056 Set Vref, RX VrefLevel [Byte0]: 58
2780 19:26:05.726119 [Byte1]: 58
2781 19:26:05.730933
2782 19:26:05.731110 Set Vref, RX VrefLevel [Byte0]: 59
2783 19:26:05.734300 [Byte1]: 59
2784 19:26:05.739027
2785 19:26:05.739220 Set Vref, RX VrefLevel [Byte0]: 60
2786 19:26:05.742205 [Byte1]: 60
2787 19:26:05.746422
2788 19:26:05.746647 Set Vref, RX VrefLevel [Byte0]: 61
2789 19:26:05.749677 [Byte1]: 61
2790 19:26:05.754504
2791 19:26:05.754748 Set Vref, RX VrefLevel [Byte0]: 62
2792 19:26:05.757911 [Byte1]: 62
2793 19:26:05.762279
2794 19:26:05.762581 Set Vref, RX VrefLevel [Byte0]: 63
2795 19:26:05.765722 [Byte1]: 63
2796 19:26:05.770865
2797 19:26:05.771219 Set Vref, RX VrefLevel [Byte0]: 64
2798 19:26:05.773885 [Byte1]: 64
2799 19:26:05.778235
2800 19:26:05.778630 Set Vref, RX VrefLevel [Byte0]: 65
2801 19:26:05.781690 [Byte1]: 65
2802 19:26:05.786360
2803 19:26:05.786837 Set Vref, RX VrefLevel [Byte0]: 66
2804 19:26:05.789388 [Byte1]: 66
2805 19:26:05.793988
2806 19:26:05.794382 Set Vref, RX VrefLevel [Byte0]: 67
2807 19:26:05.797208 [Byte1]: 67
2808 19:26:05.801851
2809 19:26:05.802037 Set Vref, RX VrefLevel [Byte0]: 68
2810 19:26:05.804852 [Byte1]: 68
2811 19:26:05.809661
2812 19:26:05.809836 Set Vref, RX VrefLevel [Byte0]: 69
2813 19:26:05.812968 [Byte1]: 69
2814 19:26:05.817773
2815 19:26:05.817944 Set Vref, RX VrefLevel [Byte0]: 70
2816 19:26:05.820834 [Byte1]: 70
2817 19:26:05.825177
2818 19:26:05.825338 Set Vref, RX VrefLevel [Byte0]: 71
2819 19:26:05.828659 [Byte1]: 71
2820 19:26:05.833349
2821 19:26:05.833507 Set Vref, RX VrefLevel [Byte0]: 72
2822 19:26:05.836532 [Byte1]: 72
2823 19:26:05.840977
2824 19:26:05.841099 Set Vref, RX VrefLevel [Byte0]: 73
2825 19:26:05.844461 [Byte1]: 73
2826 19:26:05.849294
2827 19:26:05.849444 Final RX Vref Byte 0 = 62 to rank0
2828 19:26:05.852484 Final RX Vref Byte 1 = 50 to rank0
2829 19:26:05.855848 Final RX Vref Byte 0 = 62 to rank1
2830 19:26:05.859207 Final RX Vref Byte 1 = 50 to rank1==
2831 19:26:05.862398 Dram Type= 6, Freq= 0, CH_0, rank 0
2832 19:26:05.868982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 19:26:05.869127 ==
2834 19:26:05.869197 DQS Delay:
2835 19:26:05.869259 DQS0 = 0, DQS1 = 0
2836 19:26:05.872396 DQM Delay:
2837 19:26:05.872486 DQM0 = 122, DQM1 = 109
2838 19:26:05.875611 DQ Delay:
2839 19:26:05.879324 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2840 19:26:05.882608 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2841 19:26:05.885508 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2842 19:26:05.888881 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2843 19:26:05.888966
2844 19:26:05.889033
2845 19:26:05.895603 [DQSOSCAuto] RK0, (LSB)MR18= 0x804, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2846 19:26:05.899110 CH0 RK0: MR19=404, MR18=804
2847 19:26:05.905961 CH0_RK0: MR19=0x404, MR18=0x804, DQSOSC=406, MR23=63, INC=39, DEC=26
2848 19:26:05.906052
2849 19:26:05.908867 ----->DramcWriteLeveling(PI) begin...
2850 19:26:05.908954 ==
2851 19:26:05.912346 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 19:26:05.915807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 19:26:05.915890 ==
2854 19:26:05.919302 Write leveling (Byte 0): 33 => 33
2855 19:26:05.922434 Write leveling (Byte 1): 29 => 29
2856 19:26:05.925810 DramcWriteLeveling(PI) end<-----
2857 19:26:05.925896
2858 19:26:05.925962 ==
2859 19:26:05.928968 Dram Type= 6, Freq= 0, CH_0, rank 1
2860 19:26:05.932417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 19:26:05.935656 ==
2862 19:26:05.935760 [Gating] SW mode calibration
2863 19:26:05.945592 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2864 19:26:05.949061 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2865 19:26:05.952632 0 15 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2866 19:26:05.959263 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 19:26:05.962671 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 19:26:05.966001 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 19:26:05.972732 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 19:26:05.975968 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 19:26:05.979289 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 19:26:05.986037 0 15 28 | B1->B0 | 3030 2c2c | 0 0 | (1 0) (0 1)
2873 19:26:05.989434 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 19:26:05.992797 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 19:26:05.996268 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 19:26:06.003057 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 19:26:06.006161 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 19:26:06.009600 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 19:26:06.016785 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2880 19:26:06.020506 1 0 28 | B1->B0 | 3a39 4343 | 1 0 | (0 0) (0 0)
2881 19:26:06.023040 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 19:26:06.029281 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 19:26:06.032958 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 19:26:06.036194 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 19:26:06.042840 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 19:26:06.046568 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 19:26:06.049493 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 19:26:06.056338 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2889 19:26:06.059595 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2890 19:26:06.063035 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 19:26:06.069710 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 19:26:06.073142 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 19:26:06.076174 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 19:26:06.079624 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 19:26:06.086556 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 19:26:06.090259 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 19:26:06.093841 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 19:26:06.100115 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 19:26:06.103697 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 19:26:06.107027 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 19:26:06.113728 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 19:26:06.117016 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 19:26:06.120074 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 19:26:06.126846 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2905 19:26:06.130180 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 19:26:06.133245 Total UI for P1: 0, mck2ui 16
2907 19:26:06.136627 best dqsien dly found for B0: ( 1, 3, 28)
2908 19:26:06.140443 Total UI for P1: 0, mck2ui 16
2909 19:26:06.143153 best dqsien dly found for B1: ( 1, 3, 28)
2910 19:26:06.146623 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2911 19:26:06.149926 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2912 19:26:06.150355
2913 19:26:06.153154 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2914 19:26:06.156653 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2915 19:26:06.159904 [Gating] SW calibration Done
2916 19:26:06.160327 ==
2917 19:26:06.162950 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 19:26:06.166760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 19:26:06.167206 ==
2920 19:26:06.170067 RX Vref Scan: 0
2921 19:26:06.170489
2922 19:26:06.173116 RX Vref 0 -> 0, step: 1
2923 19:26:06.173622
2924 19:26:06.173955 RX Delay -40 -> 252, step: 8
2925 19:26:06.180000 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2926 19:26:06.183208 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2927 19:26:06.186798 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2928 19:26:06.189834 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2929 19:26:06.193674 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2930 19:26:06.200254 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2931 19:26:06.203745 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2932 19:26:06.206787 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2933 19:26:06.210214 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2934 19:26:06.213449 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2935 19:26:06.216404 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2936 19:26:06.223733 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2937 19:26:06.226929 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2938 19:26:06.230167 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2939 19:26:06.233808 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2940 19:26:06.240054 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2941 19:26:06.240575 ==
2942 19:26:06.243564 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 19:26:06.246864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 19:26:06.247387 ==
2945 19:26:06.247734 DQS Delay:
2946 19:26:06.249985 DQS0 = 0, DQS1 = 0
2947 19:26:06.250411 DQM Delay:
2948 19:26:06.253794 DQM0 = 119, DQM1 = 108
2949 19:26:06.254318 DQ Delay:
2950 19:26:06.256687 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =115
2951 19:26:06.259991 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2952 19:26:06.263327 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2953 19:26:06.266491 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2954 19:26:06.266916
2955 19:26:06.267256
2956 19:26:06.267562 ==
2957 19:26:06.269821 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 19:26:06.276288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 19:26:06.276713 ==
2960 19:26:06.277057
2961 19:26:06.277402
2962 19:26:06.277710 TX Vref Scan disable
2963 19:26:06.280473 == TX Byte 0 ==
2964 19:26:06.283453 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2965 19:26:06.287017 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2966 19:26:06.290601 == TX Byte 1 ==
2967 19:26:06.293938 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2968 19:26:06.297472 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2969 19:26:06.300539 ==
2970 19:26:06.303666 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 19:26:06.307205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 19:26:06.307632 ==
2973 19:26:06.318715 TX Vref=22, minBit 7, minWin=24, winSum=417
2974 19:26:06.321647 TX Vref=24, minBit 0, minWin=25, winSum=421
2975 19:26:06.325274 TX Vref=26, minBit 1, minWin=24, winSum=421
2976 19:26:06.329006 TX Vref=28, minBit 1, minWin=25, winSum=426
2977 19:26:06.331910 TX Vref=30, minBit 1, minWin=25, winSum=428
2978 19:26:06.338696 TX Vref=32, minBit 1, minWin=25, winSum=423
2979 19:26:06.341434 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 30
2980 19:26:06.341862
2981 19:26:06.345036 Final TX Range 1 Vref 30
2982 19:26:06.345572
2983 19:26:06.345913 ==
2984 19:26:06.348836 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 19:26:06.352173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 19:26:06.352695 ==
2987 19:26:06.353036
2988 19:26:06.355269
2989 19:26:06.355688 TX Vref Scan disable
2990 19:26:06.358575 == TX Byte 0 ==
2991 19:26:06.361851 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2992 19:26:06.364979 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2993 19:26:06.368604 == TX Byte 1 ==
2994 19:26:06.371532 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2995 19:26:06.374887 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2996 19:26:06.375309
2997 19:26:06.378205 [DATLAT]
2998 19:26:06.378628 Freq=1200, CH0 RK1
2999 19:26:06.378970
3000 19:26:06.381432 DATLAT Default: 0xd
3001 19:26:06.381851 0, 0xFFFF, sum = 0
3002 19:26:06.384914 1, 0xFFFF, sum = 0
3003 19:26:06.385361 2, 0xFFFF, sum = 0
3004 19:26:06.388242 3, 0xFFFF, sum = 0
3005 19:26:06.388671 4, 0xFFFF, sum = 0
3006 19:26:06.391432 5, 0xFFFF, sum = 0
3007 19:26:06.391813 6, 0xFFFF, sum = 0
3008 19:26:06.394857 7, 0xFFFF, sum = 0
3009 19:26:06.397964 8, 0xFFFF, sum = 0
3010 19:26:06.398194 9, 0xFFFF, sum = 0
3011 19:26:06.401254 10, 0xFFFF, sum = 0
3012 19:26:06.401498 11, 0xFFFF, sum = 0
3013 19:26:06.404645 12, 0x0, sum = 1
3014 19:26:06.404829 13, 0x0, sum = 2
3015 19:26:06.407932 14, 0x0, sum = 3
3016 19:26:06.408087 15, 0x0, sum = 4
3017 19:26:06.408212 best_step = 13
3018 19:26:06.408325
3019 19:26:06.411382 ==
3020 19:26:06.411535 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 19:26:06.418034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 19:26:06.418150 ==
3023 19:26:06.418242 RX Vref Scan: 0
3024 19:26:06.418330
3025 19:26:06.421410 RX Vref 0 -> 0, step: 1
3026 19:26:06.421525
3027 19:26:06.424587 RX Delay -21 -> 252, step: 4
3028 19:26:06.427949 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3029 19:26:06.431692 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3030 19:26:06.437803 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3031 19:26:06.441504 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3032 19:26:06.444809 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3033 19:26:06.447783 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3034 19:26:06.451262 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3035 19:26:06.458108 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3036 19:26:06.461638 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3037 19:26:06.464786 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3038 19:26:06.468345 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3039 19:26:06.471523 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3040 19:26:06.477895 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3041 19:26:06.481254 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3042 19:26:06.484790 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3043 19:26:06.488276 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3044 19:26:06.488360 ==
3045 19:26:06.491224 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 19:26:06.498237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 19:26:06.498322 ==
3048 19:26:06.498390 DQS Delay:
3049 19:26:06.498451 DQS0 = 0, DQS1 = 0
3050 19:26:06.501234 DQM Delay:
3051 19:26:06.501335 DQM0 = 119, DQM1 = 107
3052 19:26:06.504837 DQ Delay:
3053 19:26:06.508016 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3054 19:26:06.511737 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =124
3055 19:26:06.514844 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =104
3056 19:26:06.518160 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3057 19:26:06.518241
3058 19:26:06.518307
3059 19:26:06.524672 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 403 ps
3060 19:26:06.528107 CH0 RK1: MR19=403, MR18=10F6
3061 19:26:06.534649 CH0_RK1: MR19=0x403, MR18=0x10F6, DQSOSC=403, MR23=63, INC=40, DEC=26
3062 19:26:06.538269 [RxdqsGatingPostProcess] freq 1200
3063 19:26:06.544551 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3064 19:26:06.547929 best DQS0 dly(2T, 0.5T) = (0, 11)
3065 19:26:06.548010 best DQS1 dly(2T, 0.5T) = (0, 12)
3066 19:26:06.551231 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3067 19:26:06.554549 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3068 19:26:06.557854 best DQS0 dly(2T, 0.5T) = (0, 11)
3069 19:26:06.561200 best DQS1 dly(2T, 0.5T) = (0, 11)
3070 19:26:06.564852 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3071 19:26:06.567846 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3072 19:26:06.571376 Pre-setting of DQS Precalculation
3073 19:26:06.578027 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3074 19:26:06.578112 ==
3075 19:26:06.581265 Dram Type= 6, Freq= 0, CH_1, rank 0
3076 19:26:06.584763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 19:26:06.584845 ==
3078 19:26:06.591602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3079 19:26:06.594618 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3080 19:26:06.604305 [CA 0] Center 37 (7~68) winsize 62
3081 19:26:06.607567 [CA 1] Center 37 (7~68) winsize 62
3082 19:26:06.610702 [CA 2] Center 35 (5~65) winsize 61
3083 19:26:06.614442 [CA 3] Center 34 (4~65) winsize 62
3084 19:26:06.617588 [CA 4] Center 34 (4~64) winsize 61
3085 19:26:06.621453 [CA 5] Center 33 (3~64) winsize 62
3086 19:26:06.621536
3087 19:26:06.624193 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3088 19:26:06.624277
3089 19:26:06.627605 [CATrainingPosCal] consider 1 rank data
3090 19:26:06.631147 u2DelayCellTimex100 = 270/100 ps
3091 19:26:06.634360 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3092 19:26:06.637640 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 19:26:06.641365 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3094 19:26:06.648082 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3095 19:26:06.651002 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 19:26:06.654421 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3097 19:26:06.654504
3098 19:26:06.657590 CA PerBit enable=1, Macro0, CA PI delay=33
3099 19:26:06.657673
3100 19:26:06.660865 [CBTSetCACLKResult] CA Dly = 33
3101 19:26:06.660948 CS Dly: 5 (0~36)
3102 19:26:06.661015 ==
3103 19:26:06.664274 Dram Type= 6, Freq= 0, CH_1, rank 1
3104 19:26:06.670656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 19:26:06.670740 ==
3106 19:26:06.674040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3107 19:26:06.680818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3108 19:26:06.690540 [CA 0] Center 38 (8~68) winsize 61
3109 19:26:06.693268 [CA 1] Center 38 (7~69) winsize 63
3110 19:26:06.696462 [CA 2] Center 35 (5~66) winsize 62
3111 19:26:06.699720 [CA 3] Center 35 (5~65) winsize 61
3112 19:26:06.703242 [CA 4] Center 34 (4~65) winsize 62
3113 19:26:06.706673 [CA 5] Center 34 (4~64) winsize 61
3114 19:26:06.706757
3115 19:26:06.709945 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3116 19:26:06.710029
3117 19:26:06.713042 [CATrainingPosCal] consider 2 rank data
3118 19:26:06.716576 u2DelayCellTimex100 = 270/100 ps
3119 19:26:06.720062 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3120 19:26:06.723527 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3121 19:26:06.726483 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3122 19:26:06.733381 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3123 19:26:06.736664 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3124 19:26:06.740215 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3125 19:26:06.740298
3126 19:26:06.743580 CA PerBit enable=1, Macro0, CA PI delay=34
3127 19:26:06.743663
3128 19:26:06.746736 [CBTSetCACLKResult] CA Dly = 34
3129 19:26:06.746819 CS Dly: 6 (0~39)
3130 19:26:06.746886
3131 19:26:06.750286 ----->DramcWriteLeveling(PI) begin...
3132 19:26:06.750370 ==
3133 19:26:06.753507 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 19:26:06.760086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 19:26:06.760170 ==
3136 19:26:06.763593 Write leveling (Byte 0): 25 => 25
3137 19:26:06.766465 Write leveling (Byte 1): 27 => 27
3138 19:26:06.766547 DramcWriteLeveling(PI) end<-----
3139 19:26:06.770242
3140 19:26:06.770324 ==
3141 19:26:06.773288 Dram Type= 6, Freq= 0, CH_1, rank 0
3142 19:26:06.776776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 19:26:06.776860 ==
3144 19:26:06.780069 [Gating] SW mode calibration
3145 19:26:06.786630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3146 19:26:06.789631 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3147 19:26:06.796526 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 19:26:06.799668 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 19:26:06.802880 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 19:26:06.809869 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 19:26:06.812971 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 19:26:06.816428 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3153 19:26:06.822811 0 15 24 | B1->B0 | 3333 2b2b | 0 0 | (0 0) (0 1)
3154 19:26:06.826262 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3155 19:26:06.829712 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 19:26:06.836243 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 19:26:06.839553 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 19:26:06.842668 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 19:26:06.849268 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 19:26:06.852744 1 0 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
3161 19:26:06.856071 1 0 24 | B1->B0 | 3a3a 4545 | 0 0 | (1 1) (0 0)
3162 19:26:06.862588 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 19:26:06.866146 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 19:26:06.869329 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 19:26:06.876199 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 19:26:06.879616 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 19:26:06.882815 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 19:26:06.889556 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3169 19:26:06.893056 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3170 19:26:06.896116 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 19:26:06.899502 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 19:26:06.906105 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 19:26:06.909651 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 19:26:06.912771 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 19:26:06.919470 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 19:26:06.922931 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 19:26:06.926461 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 19:26:06.932845 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 19:26:06.936144 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 19:26:06.939767 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 19:26:06.946115 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 19:26:06.949703 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 19:26:06.952793 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 19:26:06.959527 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3185 19:26:06.962896 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3186 19:26:06.966339 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3187 19:26:06.973176 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 19:26:06.973272 Total UI for P1: 0, mck2ui 16
3189 19:26:06.979499 best dqsien dly found for B0: ( 1, 3, 24)
3190 19:26:06.979583 Total UI for P1: 0, mck2ui 16
3191 19:26:06.982752 best dqsien dly found for B1: ( 1, 3, 26)
3192 19:26:06.989899 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3193 19:26:06.992917 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3194 19:26:06.992998
3195 19:26:06.996097 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3196 19:26:06.999646 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3197 19:26:07.002736 [Gating] SW calibration Done
3198 19:26:07.002816 ==
3199 19:26:07.006292 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 19:26:07.009584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 19:26:07.009666 ==
3202 19:26:07.012836 RX Vref Scan: 0
3203 19:26:07.012917
3204 19:26:07.012981 RX Vref 0 -> 0, step: 1
3205 19:26:07.013040
3206 19:26:07.016295 RX Delay -40 -> 252, step: 8
3207 19:26:07.019645 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3208 19:26:07.023264 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3209 19:26:07.029569 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3210 19:26:07.032912 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3211 19:26:07.036064 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3212 19:26:07.039410 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3213 19:26:07.042800 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3214 19:26:07.049575 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3215 19:26:07.053068 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3216 19:26:07.056202 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3217 19:26:07.059579 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3218 19:26:07.063237 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3219 19:26:07.069674 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3220 19:26:07.073006 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3221 19:26:07.076090 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3222 19:26:07.079693 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3223 19:26:07.079773 ==
3224 19:26:07.082849 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 19:26:07.089364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 19:26:07.089446 ==
3227 19:26:07.089512 DQS Delay:
3228 19:26:07.089571 DQS0 = 0, DQS1 = 0
3229 19:26:07.093054 DQM Delay:
3230 19:26:07.093134 DQM0 = 120, DQM1 = 112
3231 19:26:07.096315 DQ Delay:
3232 19:26:07.099820 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3233 19:26:07.102858 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3234 19:26:07.106337 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3235 19:26:07.109579 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3236 19:26:07.109661
3237 19:26:07.109727
3238 19:26:07.109786 ==
3239 19:26:07.113014 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 19:26:07.116481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 19:26:07.116563 ==
3242 19:26:07.116628
3243 19:26:07.116688
3244 19:26:07.119666 TX Vref Scan disable
3245 19:26:07.151955 == TX Byte 0 ==
3246 19:26:07.152109 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3247 19:26:07.152175 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3248 19:26:07.152237 == TX Byte 1 ==
3249 19:26:07.152296 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3250 19:26:07.152354 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3251 19:26:07.152410 ==
3252 19:26:07.152467 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 19:26:07.152524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 19:26:07.152581 ==
3255 19:26:07.159617 TX Vref=22, minBit 1, minWin=24, winSum=403
3256 19:26:07.162987 TX Vref=24, minBit 11, minWin=24, winSum=408
3257 19:26:07.166557 TX Vref=26, minBit 1, minWin=24, winSum=412
3258 19:26:07.169857 TX Vref=28, minBit 11, minWin=25, winSum=419
3259 19:26:07.172969 TX Vref=30, minBit 8, minWin=25, winSum=419
3260 19:26:07.179589 TX Vref=32, minBit 11, minWin=25, winSum=422
3261 19:26:07.182998 [TxChooseVref] Worse bit 11, Min win 25, Win sum 422, Final Vref 32
3262 19:26:07.183081
3263 19:26:07.186145 Final TX Range 1 Vref 32
3264 19:26:07.186227
3265 19:26:07.186292 ==
3266 19:26:07.190192 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 19:26:07.193128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 19:26:07.196325 ==
3269 19:26:07.196407
3270 19:26:07.196473
3271 19:26:07.196534 TX Vref Scan disable
3272 19:26:07.199644 == TX Byte 0 ==
3273 19:26:07.203167 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3274 19:26:07.206464 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3275 19:26:07.209740 == TX Byte 1 ==
3276 19:26:07.213251 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3277 19:26:07.216401 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3278 19:26:07.216483
3279 19:26:07.219795 [DATLAT]
3280 19:26:07.219877 Freq=1200, CH1 RK0
3281 19:26:07.219943
3282 19:26:07.223275 DATLAT Default: 0xd
3283 19:26:07.223357 0, 0xFFFF, sum = 0
3284 19:26:07.226786 1, 0xFFFF, sum = 0
3285 19:26:07.226869 2, 0xFFFF, sum = 0
3286 19:26:07.229791 3, 0xFFFF, sum = 0
3287 19:26:07.229875 4, 0xFFFF, sum = 0
3288 19:26:07.233513 5, 0xFFFF, sum = 0
3289 19:26:07.233596 6, 0xFFFF, sum = 0
3290 19:26:07.236391 7, 0xFFFF, sum = 0
3291 19:26:07.240256 8, 0xFFFF, sum = 0
3292 19:26:07.240341 9, 0xFFFF, sum = 0
3293 19:26:07.243172 10, 0xFFFF, sum = 0
3294 19:26:07.243253 11, 0xFFFF, sum = 0
3295 19:26:07.246772 12, 0x0, sum = 1
3296 19:26:07.246854 13, 0x0, sum = 2
3297 19:26:07.249732 14, 0x0, sum = 3
3298 19:26:07.249812 15, 0x0, sum = 4
3299 19:26:07.249878 best_step = 13
3300 19:26:07.249937
3301 19:26:07.253233 ==
3302 19:26:07.253353 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 19:26:07.260190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 19:26:07.260271 ==
3305 19:26:07.260335 RX Vref Scan: 1
3306 19:26:07.260395
3307 19:26:07.263164 Set Vref Range= 32 -> 127
3308 19:26:07.263243
3309 19:26:07.266543 RX Vref 32 -> 127, step: 1
3310 19:26:07.266623
3311 19:26:07.270013 RX Delay -13 -> 252, step: 4
3312 19:26:07.270094
3313 19:26:07.273205 Set Vref, RX VrefLevel [Byte0]: 32
3314 19:26:07.276293 [Byte1]: 32
3315 19:26:07.276373
3316 19:26:07.280007 Set Vref, RX VrefLevel [Byte0]: 33
3317 19:26:07.283159 [Byte1]: 33
3318 19:26:07.283241
3319 19:26:07.286761 Set Vref, RX VrefLevel [Byte0]: 34
3320 19:26:07.289741 [Byte1]: 34
3321 19:26:07.294106
3322 19:26:07.294186 Set Vref, RX VrefLevel [Byte0]: 35
3323 19:26:07.297249 [Byte1]: 35
3324 19:26:07.301992
3325 19:26:07.302072 Set Vref, RX VrefLevel [Byte0]: 36
3326 19:26:07.305160 [Byte1]: 36
3327 19:26:07.309745
3328 19:26:07.309826 Set Vref, RX VrefLevel [Byte0]: 37
3329 19:26:07.313688 [Byte1]: 37
3330 19:26:07.317671
3331 19:26:07.317750 Set Vref, RX VrefLevel [Byte0]: 38
3332 19:26:07.320947 [Byte1]: 38
3333 19:26:07.325677
3334 19:26:07.325756 Set Vref, RX VrefLevel [Byte0]: 39
3335 19:26:07.328935 [Byte1]: 39
3336 19:26:07.333608
3337 19:26:07.333689 Set Vref, RX VrefLevel [Byte0]: 40
3338 19:26:07.336651 [Byte1]: 40
3339 19:26:07.341610
3340 19:26:07.341689 Set Vref, RX VrefLevel [Byte0]: 41
3341 19:26:07.344617 [Byte1]: 41
3342 19:26:07.349430
3343 19:26:07.349513 Set Vref, RX VrefLevel [Byte0]: 42
3344 19:26:07.352692 [Byte1]: 42
3345 19:26:07.357208
3346 19:26:07.357290 Set Vref, RX VrefLevel [Byte0]: 43
3347 19:26:07.360486 [Byte1]: 43
3348 19:26:07.364771
3349 19:26:07.364851 Set Vref, RX VrefLevel [Byte0]: 44
3350 19:26:07.368649 [Byte1]: 44
3351 19:26:07.372928
3352 19:26:07.373008 Set Vref, RX VrefLevel [Byte0]: 45
3353 19:26:07.376110 [Byte1]: 45
3354 19:26:07.380939
3355 19:26:07.381018 Set Vref, RX VrefLevel [Byte0]: 46
3356 19:26:07.384240 [Byte1]: 46
3357 19:26:07.388628
3358 19:26:07.388708 Set Vref, RX VrefLevel [Byte0]: 47
3359 19:26:07.392104 [Byte1]: 47
3360 19:26:07.396578
3361 19:26:07.396657 Set Vref, RX VrefLevel [Byte0]: 48
3362 19:26:07.400242 [Byte1]: 48
3363 19:26:07.404356
3364 19:26:07.404435 Set Vref, RX VrefLevel [Byte0]: 49
3365 19:26:07.408053 [Byte1]: 49
3366 19:26:07.412454
3367 19:26:07.412532 Set Vref, RX VrefLevel [Byte0]: 50
3368 19:26:07.415722 [Byte1]: 50
3369 19:26:07.420203
3370 19:26:07.420282 Set Vref, RX VrefLevel [Byte0]: 51
3371 19:26:07.423469 [Byte1]: 51
3372 19:26:07.428055
3373 19:26:07.428135 Set Vref, RX VrefLevel [Byte0]: 52
3374 19:26:07.431640 [Byte1]: 52
3375 19:26:07.436058
3376 19:26:07.436137 Set Vref, RX VrefLevel [Byte0]: 53
3377 19:26:07.439181 [Byte1]: 53
3378 19:26:07.443806
3379 19:26:07.443885 Set Vref, RX VrefLevel [Byte0]: 54
3380 19:26:07.447282 [Byte1]: 54
3381 19:26:07.451730
3382 19:26:07.451809 Set Vref, RX VrefLevel [Byte0]: 55
3383 19:26:07.455067 [Byte1]: 55
3384 19:26:07.459845
3385 19:26:07.459924 Set Vref, RX VrefLevel [Byte0]: 56
3386 19:26:07.463099 [Byte1]: 56
3387 19:26:07.467719
3388 19:26:07.467798 Set Vref, RX VrefLevel [Byte0]: 57
3389 19:26:07.470904 [Byte1]: 57
3390 19:26:07.475429
3391 19:26:07.475508 Set Vref, RX VrefLevel [Byte0]: 58
3392 19:26:07.478509 [Byte1]: 58
3393 19:26:07.483410
3394 19:26:07.483490 Set Vref, RX VrefLevel [Byte0]: 59
3395 19:26:07.486857 [Byte1]: 59
3396 19:26:07.491022
3397 19:26:07.491101 Set Vref, RX VrefLevel [Byte0]: 60
3398 19:26:07.494671 [Byte1]: 60
3399 19:26:07.498916
3400 19:26:07.498995 Set Vref, RX VrefLevel [Byte0]: 61
3401 19:26:07.502427 [Byte1]: 61
3402 19:26:07.507046
3403 19:26:07.507123 Set Vref, RX VrefLevel [Byte0]: 62
3404 19:26:07.510333 [Byte1]: 62
3405 19:26:07.514714
3406 19:26:07.514793 Set Vref, RX VrefLevel [Byte0]: 63
3407 19:26:07.517970 [Byte1]: 63
3408 19:26:07.522921
3409 19:26:07.523000 Set Vref, RX VrefLevel [Byte0]: 64
3410 19:26:07.526143 [Byte1]: 64
3411 19:26:07.530699
3412 19:26:07.530779 Set Vref, RX VrefLevel [Byte0]: 65
3413 19:26:07.533866 [Byte1]: 65
3414 19:26:07.538465
3415 19:26:07.538561 Set Vref, RX VrefLevel [Byte0]: 66
3416 19:26:07.541926 [Byte1]: 66
3417 19:26:07.546339
3418 19:26:07.546420 Final RX Vref Byte 0 = 50 to rank0
3419 19:26:07.549809 Final RX Vref Byte 1 = 50 to rank0
3420 19:26:07.553234 Final RX Vref Byte 0 = 50 to rank1
3421 19:26:07.556350 Final RX Vref Byte 1 = 50 to rank1==
3422 19:26:07.559728 Dram Type= 6, Freq= 0, CH_1, rank 0
3423 19:26:07.563212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 19:26:07.566444 ==
3425 19:26:07.566564 DQS Delay:
3426 19:26:07.566632 DQS0 = 0, DQS1 = 0
3427 19:26:07.569855 DQM Delay:
3428 19:26:07.569940 DQM0 = 119, DQM1 = 111
3429 19:26:07.573479 DQ Delay:
3430 19:26:07.576510 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3431 19:26:07.579770 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =116
3432 19:26:07.583387 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =104
3433 19:26:07.586404 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3434 19:26:07.586531
3435 19:26:07.586648
3436 19:26:07.593249 [DQSOSCAuto] RK0, (LSB)MR18= 0xff13, (MSB)MR19= 0x304, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3437 19:26:07.596463 CH1 RK0: MR19=304, MR18=FF13
3438 19:26:07.603466 CH1_RK0: MR19=0x304, MR18=0xFF13, DQSOSC=402, MR23=63, INC=40, DEC=27
3439 19:26:07.603635
3440 19:26:07.606909 ----->DramcWriteLeveling(PI) begin...
3441 19:26:07.607089 ==
3442 19:26:07.609819 Dram Type= 6, Freq= 0, CH_1, rank 1
3443 19:26:07.613168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3444 19:26:07.616932 ==
3445 19:26:07.617052 Write leveling (Byte 0): 26 => 26
3446 19:26:07.620539 Write leveling (Byte 1): 29 => 29
3447 19:26:07.623844 DramcWriteLeveling(PI) end<-----
3448 19:26:07.624054
3449 19:26:07.624171 ==
3450 19:26:07.627031 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 19:26:07.633483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 19:26:07.633739 ==
3453 19:26:07.633892 [Gating] SW mode calibration
3454 19:26:07.643637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3455 19:26:07.646912 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3456 19:26:07.649942 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 19:26:07.657154 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 19:26:07.660384 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 19:26:07.663504 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 19:26:07.670238 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 19:26:07.673593 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 19:26:07.677259 0 15 24 | B1->B0 | 2c2c 3434 | 0 0 | (1 0) (1 1)
3463 19:26:07.684052 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (0 0)
3464 19:26:07.686904 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 19:26:07.690711 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 19:26:07.697088 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 19:26:07.700709 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 19:26:07.704181 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 19:26:07.710584 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3470 19:26:07.713709 1 0 24 | B1->B0 | 3d3d 2b2b | 0 0 | (0 0) (0 0)
3471 19:26:07.717090 1 0 28 | B1->B0 | 4646 3b3b | 0 0 | (0 0) (0 0)
3472 19:26:07.723615 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 19:26:07.727226 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 19:26:07.730573 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 19:26:07.733837 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 19:26:07.740712 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 19:26:07.743619 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 19:26:07.747212 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3479 19:26:07.753771 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3480 19:26:07.757219 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 19:26:07.760783 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 19:26:07.767046 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 19:26:07.770182 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 19:26:07.773732 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 19:26:07.780362 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 19:26:07.783699 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 19:26:07.786802 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 19:26:07.793375 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 19:26:07.797105 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 19:26:07.800238 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 19:26:07.807046 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 19:26:07.810292 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 19:26:07.813726 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 19:26:07.820315 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3495 19:26:07.823042 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3496 19:26:07.826807 Total UI for P1: 0, mck2ui 16
3497 19:26:07.830095 best dqsien dly found for B1: ( 1, 3, 24)
3498 19:26:07.833127 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 19:26:07.836860 Total UI for P1: 0, mck2ui 16
3500 19:26:07.839987 best dqsien dly found for B0: ( 1, 3, 26)
3501 19:26:07.843356 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3502 19:26:07.846488 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3503 19:26:07.847014
3504 19:26:07.853219 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3505 19:26:07.856178 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3506 19:26:07.856607 [Gating] SW calibration Done
3507 19:26:07.860063 ==
3508 19:26:07.862768 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 19:26:07.866365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 19:26:07.866791 ==
3511 19:26:07.867131 RX Vref Scan: 0
3512 19:26:07.867448
3513 19:26:07.869631 RX Vref 0 -> 0, step: 1
3514 19:26:07.870055
3515 19:26:07.872757 RX Delay -40 -> 252, step: 8
3516 19:26:07.876024 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3517 19:26:07.879120 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3518 19:26:07.885775 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3519 19:26:07.889089 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3520 19:26:07.892672 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3521 19:26:07.895826 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3522 19:26:07.899528 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3523 19:26:07.905895 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3524 19:26:07.908976 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3525 19:26:07.912752 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3526 19:26:07.915855 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3527 19:26:07.919444 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3528 19:26:07.925934 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3529 19:26:07.929272 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3530 19:26:07.932810 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3531 19:26:07.935700 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3532 19:26:07.936171 ==
3533 19:26:07.939134 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 19:26:07.945952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 19:26:07.946482 ==
3536 19:26:07.946826 DQS Delay:
3537 19:26:07.949203 DQS0 = 0, DQS1 = 0
3538 19:26:07.949764 DQM Delay:
3539 19:26:07.950109 DQM0 = 119, DQM1 = 112
3540 19:26:07.952078 DQ Delay:
3541 19:26:07.955709 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3542 19:26:07.959164 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3543 19:26:07.962326 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3544 19:26:07.965394 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3545 19:26:07.965827
3546 19:26:07.966161
3547 19:26:07.966475 ==
3548 19:26:07.968770 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 19:26:07.972087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 19:26:07.975440 ==
3551 19:26:07.975864
3552 19:26:07.976199
3553 19:26:07.976511 TX Vref Scan disable
3554 19:26:07.978688 == TX Byte 0 ==
3555 19:26:07.982321 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3556 19:26:07.985254 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3557 19:26:07.988799 == TX Byte 1 ==
3558 19:26:07.991966 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3559 19:26:07.995232 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3560 19:26:07.998898 ==
3561 19:26:07.999423 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 19:26:08.005426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 19:26:08.005952 ==
3564 19:26:08.016692 TX Vref=22, minBit 1, minWin=25, winSum=420
3565 19:26:08.019568 TX Vref=24, minBit 1, minWin=25, winSum=423
3566 19:26:08.022741 TX Vref=26, minBit 0, minWin=26, winSum=425
3567 19:26:08.026366 TX Vref=28, minBit 3, minWin=26, winSum=428
3568 19:26:08.029556 TX Vref=30, minBit 1, minWin=26, winSum=429
3569 19:26:08.036658 TX Vref=32, minBit 8, minWin=26, winSum=429
3570 19:26:08.039969 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3571 19:26:08.040487
3572 19:26:08.042725 Final TX Range 1 Vref 30
3573 19:26:08.043242
3574 19:26:08.043584 ==
3575 19:26:08.046482 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 19:26:08.049165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 19:26:08.049621 ==
3578 19:26:08.049960
3579 19:26:08.052507
3580 19:26:08.052926 TX Vref Scan disable
3581 19:26:08.056288 == TX Byte 0 ==
3582 19:26:08.059517 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3583 19:26:08.062851 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3584 19:26:08.066093 == TX Byte 1 ==
3585 19:26:08.069085 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3586 19:26:08.072551 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3587 19:26:08.072998
3588 19:26:08.075902 [DATLAT]
3589 19:26:08.076324 Freq=1200, CH1 RK1
3590 19:26:08.076666
3591 19:26:08.079477 DATLAT Default: 0xd
3592 19:26:08.079902 0, 0xFFFF, sum = 0
3593 19:26:08.082679 1, 0xFFFF, sum = 0
3594 19:26:08.083108 2, 0xFFFF, sum = 0
3595 19:26:08.085949 3, 0xFFFF, sum = 0
3596 19:26:08.086374 4, 0xFFFF, sum = 0
3597 19:26:08.089410 5, 0xFFFF, sum = 0
3598 19:26:08.089832 6, 0xFFFF, sum = 0
3599 19:26:08.092346 7, 0xFFFF, sum = 0
3600 19:26:08.096152 8, 0xFFFF, sum = 0
3601 19:26:08.096574 9, 0xFFFF, sum = 0
3602 19:26:08.099684 10, 0xFFFF, sum = 0
3603 19:26:08.100220 11, 0xFFFF, sum = 0
3604 19:26:08.102842 12, 0x0, sum = 1
3605 19:26:08.103374 13, 0x0, sum = 2
3606 19:26:08.105988 14, 0x0, sum = 3
3607 19:26:08.106419 15, 0x0, sum = 4
3608 19:26:08.106766 best_step = 13
3609 19:26:08.107076
3610 19:26:08.108936 ==
3611 19:26:08.112691 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 19:26:08.115968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 19:26:08.116496 ==
3614 19:26:08.116841 RX Vref Scan: 0
3615 19:26:08.117164
3616 19:26:08.118791 RX Vref 0 -> 0, step: 1
3617 19:26:08.119212
3618 19:26:08.122564 RX Delay -13 -> 252, step: 4
3619 19:26:08.125566 iDelay=191, Bit 0, Center 120 (63 ~ 178) 116
3620 19:26:08.132740 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3621 19:26:08.136092 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3622 19:26:08.139301 iDelay=191, Bit 3, Center 116 (55 ~ 178) 124
3623 19:26:08.142604 iDelay=191, Bit 4, Center 122 (63 ~ 182) 120
3624 19:26:08.145817 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3625 19:26:08.152297 iDelay=191, Bit 6, Center 126 (67 ~ 186) 120
3626 19:26:08.155647 iDelay=191, Bit 7, Center 116 (55 ~ 178) 124
3627 19:26:08.158952 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3628 19:26:08.162296 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3629 19:26:08.165822 iDelay=191, Bit 10, Center 112 (47 ~ 178) 132
3630 19:26:08.172426 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3631 19:26:08.175475 iDelay=191, Bit 12, Center 120 (55 ~ 186) 132
3632 19:26:08.178535 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3633 19:26:08.181999 iDelay=191, Bit 14, Center 122 (59 ~ 186) 128
3634 19:26:08.185663 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3635 19:26:08.188619 ==
3636 19:26:08.191983 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 19:26:08.195248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 19:26:08.195677 ==
3639 19:26:08.196018 DQS Delay:
3640 19:26:08.198892 DQS0 = 0, DQS1 = 0
3641 19:26:08.199416 DQM Delay:
3642 19:26:08.202211 DQM0 = 118, DQM1 = 112
3643 19:26:08.202655 DQ Delay:
3644 19:26:08.205553 DQ0 =120, DQ1 =114, DQ2 =108, DQ3 =116
3645 19:26:08.208783 DQ4 =122, DQ5 =128, DQ6 =126, DQ7 =116
3646 19:26:08.212122 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3647 19:26:08.215356 DQ12 =120, DQ13 =118, DQ14 =122, DQ15 =120
3648 19:26:08.215883
3649 19:26:08.216229
3650 19:26:08.225462 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 408 ps
3651 19:26:08.225981 CH1 RK1: MR19=403, MR18=5E9
3652 19:26:08.232421 CH1_RK1: MR19=0x403, MR18=0x5E9, DQSOSC=408, MR23=63, INC=39, DEC=26
3653 19:26:08.235199 [RxdqsGatingPostProcess] freq 1200
3654 19:26:08.242051 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3655 19:26:08.245729 best DQS0 dly(2T, 0.5T) = (0, 11)
3656 19:26:08.249182 best DQS1 dly(2T, 0.5T) = (0, 11)
3657 19:26:08.252557 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3658 19:26:08.255270 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3659 19:26:08.258680 best DQS0 dly(2T, 0.5T) = (0, 11)
3660 19:26:08.259203 best DQS1 dly(2T, 0.5T) = (0, 11)
3661 19:26:08.261797 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3662 19:26:08.265497 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3663 19:26:08.268814 Pre-setting of DQS Precalculation
3664 19:26:08.275181 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3665 19:26:08.281729 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3666 19:26:08.288324 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3667 19:26:08.288840
3668 19:26:08.289180
3669 19:26:08.292019 [Calibration Summary] 2400 Mbps
3670 19:26:08.294998 CH 0, Rank 0
3671 19:26:08.295450 SW Impedance : PASS
3672 19:26:08.298675 DUTY Scan : NO K
3673 19:26:08.299197 ZQ Calibration : PASS
3674 19:26:08.301884 Jitter Meter : NO K
3675 19:26:08.305254 CBT Training : PASS
3676 19:26:08.305817 Write leveling : PASS
3677 19:26:08.308020 RX DQS gating : PASS
3678 19:26:08.311637 RX DQ/DQS(RDDQC) : PASS
3679 19:26:08.312156 TX DQ/DQS : PASS
3680 19:26:08.315496 RX DATLAT : PASS
3681 19:26:08.318400 RX DQ/DQS(Engine): PASS
3682 19:26:08.318923 TX OE : NO K
3683 19:26:08.321859 All Pass.
3684 19:26:08.322382
3685 19:26:08.322729 CH 0, Rank 1
3686 19:26:08.325046 SW Impedance : PASS
3687 19:26:08.325537 DUTY Scan : NO K
3688 19:26:08.328341 ZQ Calibration : PASS
3689 19:26:08.331851 Jitter Meter : NO K
3690 19:26:08.332370 CBT Training : PASS
3691 19:26:08.334779 Write leveling : PASS
3692 19:26:08.338432 RX DQS gating : PASS
3693 19:26:08.338951 RX DQ/DQS(RDDQC) : PASS
3694 19:26:08.341463 TX DQ/DQS : PASS
3695 19:26:08.344933 RX DATLAT : PASS
3696 19:26:08.345392 RX DQ/DQS(Engine): PASS
3697 19:26:08.347876 TX OE : NO K
3698 19:26:08.348304 All Pass.
3699 19:26:08.348645
3700 19:26:08.351486 CH 1, Rank 0
3701 19:26:08.352003 SW Impedance : PASS
3702 19:26:08.354540 DUTY Scan : NO K
3703 19:26:08.354969 ZQ Calibration : PASS
3704 19:26:08.358056 Jitter Meter : NO K
3705 19:26:08.361275 CBT Training : PASS
3706 19:26:08.361730 Write leveling : PASS
3707 19:26:08.364531 RX DQS gating : PASS
3708 19:26:08.368242 RX DQ/DQS(RDDQC) : PASS
3709 19:26:08.368765 TX DQ/DQS : PASS
3710 19:26:08.371331 RX DATLAT : PASS
3711 19:26:08.374855 RX DQ/DQS(Engine): PASS
3712 19:26:08.375422 TX OE : NO K
3713 19:26:08.377943 All Pass.
3714 19:26:08.378362
3715 19:26:08.378697 CH 1, Rank 1
3716 19:26:08.381628 SW Impedance : PASS
3717 19:26:08.382172 DUTY Scan : NO K
3718 19:26:08.384681 ZQ Calibration : PASS
3719 19:26:08.387949 Jitter Meter : NO K
3720 19:26:08.388373 CBT Training : PASS
3721 19:26:08.391527 Write leveling : PASS
3722 19:26:08.394735 RX DQS gating : PASS
3723 19:26:08.395255 RX DQ/DQS(RDDQC) : PASS
3724 19:26:08.397956 TX DQ/DQS : PASS
3725 19:26:08.401607 RX DATLAT : PASS
3726 19:26:08.402122 RX DQ/DQS(Engine): PASS
3727 19:26:08.404879 TX OE : NO K
3728 19:26:08.405427 All Pass.
3729 19:26:08.405766
3730 19:26:08.407830 DramC Write-DBI off
3731 19:26:08.411356 PER_BANK_REFRESH: Hybrid Mode
3732 19:26:08.411889 TX_TRACKING: ON
3733 19:26:08.421331 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3734 19:26:08.424845 [FAST_K] Save calibration result to emmc
3735 19:26:08.427766 dramc_set_vcore_voltage set vcore to 650000
3736 19:26:08.431037 Read voltage for 600, 5
3737 19:26:08.431553 Vio18 = 0
3738 19:26:08.431898 Vcore = 650000
3739 19:26:08.434469 Vdram = 0
3740 19:26:08.434893 Vddq = 0
3741 19:26:08.435232 Vmddr = 0
3742 19:26:08.441201 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3743 19:26:08.444555 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3744 19:26:08.447882 MEM_TYPE=3, freq_sel=19
3745 19:26:08.450790 sv_algorithm_assistance_LP4_1600
3746 19:26:08.454699 ============ PULL DRAM RESETB DOWN ============
3747 19:26:08.457548 ========== PULL DRAM RESETB DOWN end =========
3748 19:26:08.464483 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3749 19:26:08.467954 ===================================
3750 19:26:08.468519 LPDDR4 DRAM CONFIGURATION
3751 19:26:08.470807 ===================================
3752 19:26:08.473996 EX_ROW_EN[0] = 0x0
3753 19:26:08.477720 EX_ROW_EN[1] = 0x0
3754 19:26:08.478243 LP4Y_EN = 0x0
3755 19:26:08.480798 WORK_FSP = 0x0
3756 19:26:08.481339 WL = 0x2
3757 19:26:08.484028 RL = 0x2
3758 19:26:08.484542 BL = 0x2
3759 19:26:08.487955 RPST = 0x0
3760 19:26:08.488479 RD_PRE = 0x0
3761 19:26:08.490730 WR_PRE = 0x1
3762 19:26:08.491151 WR_PST = 0x0
3763 19:26:08.494254 DBI_WR = 0x0
3764 19:26:08.494774 DBI_RD = 0x0
3765 19:26:08.497684 OTF = 0x1
3766 19:26:08.500862 ===================================
3767 19:26:08.504456 ===================================
3768 19:26:08.504984 ANA top config
3769 19:26:08.507687 ===================================
3770 19:26:08.511185 DLL_ASYNC_EN = 0
3771 19:26:08.513926 ALL_SLAVE_EN = 1
3772 19:26:08.514351 NEW_RANK_MODE = 1
3773 19:26:08.517661 DLL_IDLE_MODE = 1
3774 19:26:08.520725 LP45_APHY_COMB_EN = 1
3775 19:26:08.524372 TX_ODT_DIS = 1
3776 19:26:08.527573 NEW_8X_MODE = 1
3777 19:26:08.530453 ===================================
3778 19:26:08.533770 ===================================
3779 19:26:08.534197 data_rate = 1200
3780 19:26:08.537034 CKR = 1
3781 19:26:08.540737 DQ_P2S_RATIO = 8
3782 19:26:08.543647 ===================================
3783 19:26:08.547519 CA_P2S_RATIO = 8
3784 19:26:08.550661 DQ_CA_OPEN = 0
3785 19:26:08.553926 DQ_SEMI_OPEN = 0
3786 19:26:08.554446 CA_SEMI_OPEN = 0
3787 19:26:08.557445 CA_FULL_RATE = 0
3788 19:26:08.560892 DQ_CKDIV4_EN = 1
3789 19:26:08.564174 CA_CKDIV4_EN = 1
3790 19:26:08.567285 CA_PREDIV_EN = 0
3791 19:26:08.570881 PH8_DLY = 0
3792 19:26:08.571418 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3793 19:26:08.573894 DQ_AAMCK_DIV = 4
3794 19:26:08.577399 CA_AAMCK_DIV = 4
3795 19:26:08.580764 CA_ADMCK_DIV = 4
3796 19:26:08.583732 DQ_TRACK_CA_EN = 0
3797 19:26:08.587319 CA_PICK = 600
3798 19:26:08.590165 CA_MCKIO = 600
3799 19:26:08.590588 MCKIO_SEMI = 0
3800 19:26:08.593466 PLL_FREQ = 2288
3801 19:26:08.596842 DQ_UI_PI_RATIO = 32
3802 19:26:08.600647 CA_UI_PI_RATIO = 0
3803 19:26:08.603793 ===================================
3804 19:26:08.607119 ===================================
3805 19:26:08.610367 memory_type:LPDDR4
3806 19:26:08.610790 GP_NUM : 10
3807 19:26:08.613763 SRAM_EN : 1
3808 19:26:08.614186 MD32_EN : 0
3809 19:26:08.617408 ===================================
3810 19:26:08.620433 [ANA_INIT] >>>>>>>>>>>>>>
3811 19:26:08.624634 <<<<<< [CONFIGURE PHASE]: ANA_TX
3812 19:26:08.627059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3813 19:26:08.630578 ===================================
3814 19:26:08.633479 data_rate = 1200,PCW = 0X5800
3815 19:26:08.636880 ===================================
3816 19:26:08.640501 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3817 19:26:08.647113 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3818 19:26:08.650017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3819 19:26:08.656763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3820 19:26:08.660438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3821 19:26:08.663822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3822 19:26:08.664347 [ANA_INIT] flow start
3823 19:26:08.666948 [ANA_INIT] PLL >>>>>>>>
3824 19:26:08.670466 [ANA_INIT] PLL <<<<<<<<
3825 19:26:08.670980 [ANA_INIT] MIDPI >>>>>>>>
3826 19:26:08.673649 [ANA_INIT] MIDPI <<<<<<<<
3827 19:26:08.676781 [ANA_INIT] DLL >>>>>>>>
3828 19:26:08.677207 [ANA_INIT] flow end
3829 19:26:08.683404 ============ LP4 DIFF to SE enter ============
3830 19:26:08.687224 ============ LP4 DIFF to SE exit ============
3831 19:26:08.689891 [ANA_INIT] <<<<<<<<<<<<<
3832 19:26:08.693745 [Flow] Enable top DCM control >>>>>
3833 19:26:08.697111 [Flow] Enable top DCM control <<<<<
3834 19:26:08.697668 Enable DLL master slave shuffle
3835 19:26:08.703783 ==============================================================
3836 19:26:08.707170 Gating Mode config
3837 19:26:08.709862 ==============================================================
3838 19:26:08.713401 Config description:
3839 19:26:08.723438 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3840 19:26:08.730082 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3841 19:26:08.733658 SELPH_MODE 0: By rank 1: By Phase
3842 19:26:08.740304 ==============================================================
3843 19:26:08.743304 GAT_TRACK_EN = 1
3844 19:26:08.746763 RX_GATING_MODE = 2
3845 19:26:08.749732 RX_GATING_TRACK_MODE = 2
3846 19:26:08.750158 SELPH_MODE = 1
3847 19:26:08.753662 PICG_EARLY_EN = 1
3848 19:26:08.756513 VALID_LAT_VALUE = 1
3849 19:26:08.763813 ==============================================================
3850 19:26:08.766662 Enter into Gating configuration >>>>
3851 19:26:08.770499 Exit from Gating configuration <<<<
3852 19:26:08.773370 Enter into DVFS_PRE_config >>>>>
3853 19:26:08.783646 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3854 19:26:08.787001 Exit from DVFS_PRE_config <<<<<
3855 19:26:08.790434 Enter into PICG configuration >>>>
3856 19:26:08.793734 Exit from PICG configuration <<<<
3857 19:26:08.797390 [RX_INPUT] configuration >>>>>
3858 19:26:08.800214 [RX_INPUT] configuration <<<<<
3859 19:26:08.803549 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3860 19:26:08.810228 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3861 19:26:08.816875 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3862 19:26:08.824071 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3863 19:26:08.826510 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3864 19:26:08.832853 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3865 19:26:08.836425 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3866 19:26:08.842912 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3867 19:26:08.846501 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3868 19:26:08.849928 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3869 19:26:08.852859 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3870 19:26:08.859878 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3871 19:26:08.863277 ===================================
3872 19:26:08.866312 LPDDR4 DRAM CONFIGURATION
3873 19:26:08.869586 ===================================
3874 19:26:08.870150 EX_ROW_EN[0] = 0x0
3875 19:26:08.872699 EX_ROW_EN[1] = 0x0
3876 19:26:08.873209 LP4Y_EN = 0x0
3877 19:26:08.876394 WORK_FSP = 0x0
3878 19:26:08.876856 WL = 0x2
3879 19:26:08.879414 RL = 0x2
3880 19:26:08.879896 BL = 0x2
3881 19:26:08.883035 RPST = 0x0
3882 19:26:08.883707 RD_PRE = 0x0
3883 19:26:08.886181 WR_PRE = 0x1
3884 19:26:08.886644 WR_PST = 0x0
3885 19:26:08.889352 DBI_WR = 0x0
3886 19:26:08.889815 DBI_RD = 0x0
3887 19:26:08.893220 OTF = 0x1
3888 19:26:08.896330 ===================================
3889 19:26:08.899931 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3890 19:26:08.903336 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3891 19:26:08.909411 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3892 19:26:08.913026 ===================================
3893 19:26:08.913628 LPDDR4 DRAM CONFIGURATION
3894 19:26:08.916232 ===================================
3895 19:26:08.919549 EX_ROW_EN[0] = 0x10
3896 19:26:08.922753 EX_ROW_EN[1] = 0x0
3897 19:26:08.923215 LP4Y_EN = 0x0
3898 19:26:08.926195 WORK_FSP = 0x0
3899 19:26:08.926763 WL = 0x2
3900 19:26:08.929698 RL = 0x2
3901 19:26:08.930260 BL = 0x2
3902 19:26:08.932637 RPST = 0x0
3903 19:26:08.933102 RD_PRE = 0x0
3904 19:26:08.936319 WR_PRE = 0x1
3905 19:26:08.936882 WR_PST = 0x0
3906 19:26:08.939517 DBI_WR = 0x0
3907 19:26:08.940084 DBI_RD = 0x0
3908 19:26:08.942492 OTF = 0x1
3909 19:26:08.946093 ===================================
3910 19:26:08.953198 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3911 19:26:08.955965 nWR fixed to 30
3912 19:26:08.956432 [ModeRegInit_LP4] CH0 RK0
3913 19:26:08.959075 [ModeRegInit_LP4] CH0 RK1
3914 19:26:08.962536 [ModeRegInit_LP4] CH1 RK0
3915 19:26:08.965933 [ModeRegInit_LP4] CH1 RK1
3916 19:26:08.966350 match AC timing 17
3917 19:26:08.972656 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3918 19:26:08.975598 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3919 19:26:08.979039 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3920 19:26:08.986102 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3921 19:26:08.989169 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3922 19:26:08.989624 ==
3923 19:26:08.992467 Dram Type= 6, Freq= 0, CH_0, rank 0
3924 19:26:08.995450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3925 19:26:08.995871 ==
3926 19:26:09.002467 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3927 19:26:09.009226 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3928 19:26:09.012527 [CA 0] Center 36 (6~67) winsize 62
3929 19:26:09.015995 [CA 1] Center 36 (6~67) winsize 62
3930 19:26:09.019578 [CA 2] Center 34 (4~65) winsize 62
3931 19:26:09.022819 [CA 3] Center 34 (4~65) winsize 62
3932 19:26:09.025890 [CA 4] Center 33 (3~64) winsize 62
3933 19:26:09.029504 [CA 5] Center 33 (2~64) winsize 63
3934 19:26:09.030066
3935 19:26:09.032690 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3936 19:26:09.033248
3937 19:26:09.036143 [CATrainingPosCal] consider 1 rank data
3938 19:26:09.039109 u2DelayCellTimex100 = 270/100 ps
3939 19:26:09.042328 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3940 19:26:09.045680 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3941 19:26:09.049070 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3942 19:26:09.052381 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3943 19:26:09.055383 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3944 19:26:09.059237 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3945 19:26:09.059702
3946 19:26:09.065628 CA PerBit enable=1, Macro0, CA PI delay=33
3947 19:26:09.066206
3948 19:26:09.066588 [CBTSetCACLKResult] CA Dly = 33
3949 19:26:09.069006 CS Dly: 5 (0~36)
3950 19:26:09.069509 ==
3951 19:26:09.071806 Dram Type= 6, Freq= 0, CH_0, rank 1
3952 19:26:09.075287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 19:26:09.075756 ==
3954 19:26:09.081700 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3955 19:26:09.088485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3956 19:26:09.092186 [CA 0] Center 36 (6~67) winsize 62
3957 19:26:09.096015 [CA 1] Center 36 (6~67) winsize 62
3958 19:26:09.099600 [CA 2] Center 34 (4~65) winsize 62
3959 19:26:09.102030 [CA 3] Center 34 (4~65) winsize 62
3960 19:26:09.105231 [CA 4] Center 34 (3~65) winsize 63
3961 19:26:09.108645 [CA 5] Center 33 (3~64) winsize 62
3962 19:26:09.109071
3963 19:26:09.112631 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3964 19:26:09.113163
3965 19:26:09.115544 [CATrainingPosCal] consider 2 rank data
3966 19:26:09.118976 u2DelayCellTimex100 = 270/100 ps
3967 19:26:09.122288 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3968 19:26:09.125435 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3969 19:26:09.128921 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3970 19:26:09.132172 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 19:26:09.135362 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 19:26:09.139174 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 19:26:09.139801
3974 19:26:09.145978 CA PerBit enable=1, Macro0, CA PI delay=33
3975 19:26:09.146560
3976 19:26:09.148711 [CBTSetCACLKResult] CA Dly = 33
3977 19:26:09.149182 CS Dly: 6 (0~38)
3978 19:26:09.149602
3979 19:26:09.152210 ----->DramcWriteLeveling(PI) begin...
3980 19:26:09.152668 ==
3981 19:26:09.155089 Dram Type= 6, Freq= 0, CH_0, rank 0
3982 19:26:09.158856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 19:26:09.159437 ==
3984 19:26:09.162069 Write leveling (Byte 0): 35 => 35
3985 19:26:09.165224 Write leveling (Byte 1): 30 => 30
3986 19:26:09.168586 DramcWriteLeveling(PI) end<-----
3987 19:26:09.169091
3988 19:26:09.169531 ==
3989 19:26:09.172084 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 19:26:09.178432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 19:26:09.179004 ==
3992 19:26:09.179386 [Gating] SW mode calibration
3993 19:26:09.188330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3994 19:26:09.191768 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3995 19:26:09.195503 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 19:26:09.201875 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 19:26:09.205568 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 19:26:09.208744 0 9 12 | B1->B0 | 3333 2c2c | 0 0 | (0 0) (0 1)
3999 19:26:09.215588 0 9 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 1) (1 0)
4000 19:26:09.218499 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 19:26:09.221703 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 19:26:09.228767 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 19:26:09.231630 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 19:26:09.234951 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 19:26:09.241749 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 19:26:09.245050 0 10 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
4007 19:26:09.248243 0 10 16 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
4008 19:26:09.255099 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 19:26:09.258789 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 19:26:09.261728 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 19:26:09.268057 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 19:26:09.271127 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 19:26:09.274796 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 19:26:09.281357 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4015 19:26:09.284831 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4016 19:26:09.287908 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 19:26:09.295159 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 19:26:09.298428 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 19:26:09.301745 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 19:26:09.304899 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 19:26:09.311543 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 19:26:09.314969 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 19:26:09.318327 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 19:26:09.325186 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 19:26:09.327997 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 19:26:09.332002 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 19:26:09.337986 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 19:26:09.341866 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 19:26:09.344864 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 19:26:09.351617 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4031 19:26:09.354426 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 19:26:09.358388 Total UI for P1: 0, mck2ui 16
4033 19:26:09.361277 best dqsien dly found for B0: ( 0, 13, 12)
4034 19:26:09.364860 Total UI for P1: 0, mck2ui 16
4035 19:26:09.368190 best dqsien dly found for B1: ( 0, 13, 14)
4036 19:26:09.371137 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4037 19:26:09.374748 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4038 19:26:09.375216
4039 19:26:09.378186 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4040 19:26:09.381331 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4041 19:26:09.384460 [Gating] SW calibration Done
4042 19:26:09.384887 ==
4043 19:26:09.387985 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 19:26:09.391019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 19:26:09.394566 ==
4046 19:26:09.394985 RX Vref Scan: 0
4047 19:26:09.395322
4048 19:26:09.397995 RX Vref 0 -> 0, step: 1
4049 19:26:09.398419
4050 19:26:09.400994 RX Delay -230 -> 252, step: 16
4051 19:26:09.404624 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4052 19:26:09.407900 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4053 19:26:09.411380 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4054 19:26:09.418066 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4055 19:26:09.421611 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4056 19:26:09.424636 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4057 19:26:09.427926 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4058 19:26:09.434379 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4059 19:26:09.437683 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4060 19:26:09.441158 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4061 19:26:09.444584 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4062 19:26:09.447603 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4063 19:26:09.454332 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4064 19:26:09.457428 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4065 19:26:09.460890 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4066 19:26:09.463956 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4067 19:26:09.467502 ==
4068 19:26:09.470790 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 19:26:09.474499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 19:26:09.474974 ==
4071 19:26:09.475347 DQS Delay:
4072 19:26:09.477348 DQS0 = 0, DQS1 = 0
4073 19:26:09.477932 DQM Delay:
4074 19:26:09.480484 DQM0 = 51, DQM1 = 41
4075 19:26:09.480947 DQ Delay:
4076 19:26:09.483908 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4077 19:26:09.487148 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4078 19:26:09.490738 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4079 19:26:09.494092 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4080 19:26:09.494562
4081 19:26:09.494958
4082 19:26:09.495279 ==
4083 19:26:09.497328 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 19:26:09.500946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 19:26:09.501524 ==
4086 19:26:09.501881
4087 19:26:09.502196
4088 19:26:09.504260 TX Vref Scan disable
4089 19:26:09.507094 == TX Byte 0 ==
4090 19:26:09.510729 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4091 19:26:09.513808 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4092 19:26:09.517543 == TX Byte 1 ==
4093 19:26:09.520895 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4094 19:26:09.524090 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4095 19:26:09.524613 ==
4096 19:26:09.527363 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 19:26:09.530962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 19:26:09.534177 ==
4099 19:26:09.534691
4100 19:26:09.535031
4101 19:26:09.535348 TX Vref Scan disable
4102 19:26:09.538073 == TX Byte 0 ==
4103 19:26:09.541105 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4104 19:26:09.547804 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4105 19:26:09.548326 == TX Byte 1 ==
4106 19:26:09.551032 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4107 19:26:09.557819 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4108 19:26:09.558339
4109 19:26:09.558678 [DATLAT]
4110 19:26:09.558997 Freq=600, CH0 RK0
4111 19:26:09.559307
4112 19:26:09.561015 DATLAT Default: 0x9
4113 19:26:09.561465 0, 0xFFFF, sum = 0
4114 19:26:09.567996 1, 0xFFFF, sum = 0
4115 19:26:09.568423 2, 0xFFFF, sum = 0
4116 19:26:09.568766 3, 0xFFFF, sum = 0
4117 19:26:09.571161 4, 0xFFFF, sum = 0
4118 19:26:09.571588 5, 0xFFFF, sum = 0
4119 19:26:09.574017 6, 0xFFFF, sum = 0
4120 19:26:09.574446 7, 0xFFFF, sum = 0
4121 19:26:09.577402 8, 0x0, sum = 1
4122 19:26:09.577830 9, 0x0, sum = 2
4123 19:26:09.578172 10, 0x0, sum = 3
4124 19:26:09.580604 11, 0x0, sum = 4
4125 19:26:09.581031 best_step = 9
4126 19:26:09.581406
4127 19:26:09.581731 ==
4128 19:26:09.584066 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 19:26:09.592188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 19:26:09.592625 ==
4131 19:26:09.592971 RX Vref Scan: 1
4132 19:26:09.593318
4133 19:26:09.594044 RX Vref 0 -> 0, step: 1
4134 19:26:09.594468
4135 19:26:09.597487 RX Delay -163 -> 252, step: 8
4136 19:26:09.597925
4137 19:26:09.600753 Set Vref, RX VrefLevel [Byte0]: 62
4138 19:26:09.604025 [Byte1]: 50
4139 19:26:09.604503
4140 19:26:09.607420 Final RX Vref Byte 0 = 62 to rank0
4141 19:26:09.610454 Final RX Vref Byte 1 = 50 to rank0
4142 19:26:09.613806 Final RX Vref Byte 0 = 62 to rank1
4143 19:26:09.617166 Final RX Vref Byte 1 = 50 to rank1==
4144 19:26:09.620504 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 19:26:09.623946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 19:26:09.624487 ==
4147 19:26:09.627490 DQS Delay:
4148 19:26:09.627919 DQS0 = 0, DQS1 = 0
4149 19:26:09.630514 DQM Delay:
4150 19:26:09.631044 DQM0 = 48, DQM1 = 37
4151 19:26:09.631486 DQ Delay:
4152 19:26:09.633910 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4153 19:26:09.637079 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4154 19:26:09.640466 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4155 19:26:09.643798 DQ12 =44, DQ13 =36, DQ14 =48, DQ15 =48
4156 19:26:09.644333
4157 19:26:09.644771
4158 19:26:09.653819 [DQSOSCAuto] RK0, (LSB)MR18= 0x554e, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 393 ps
4159 19:26:09.657030 CH0 RK0: MR19=808, MR18=554E
4160 19:26:09.663546 CH0_RK0: MR19=0x808, MR18=0x554E, DQSOSC=393, MR23=63, INC=169, DEC=113
4161 19:26:09.663984
4162 19:26:09.666939 ----->DramcWriteLeveling(PI) begin...
4163 19:26:09.667429 ==
4164 19:26:09.670526 Dram Type= 6, Freq= 0, CH_0, rank 1
4165 19:26:09.673536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 19:26:09.674004 ==
4167 19:26:09.676692 Write leveling (Byte 0): 33 => 33
4168 19:26:09.680003 Write leveling (Byte 1): 31 => 31
4169 19:26:09.683711 DramcWriteLeveling(PI) end<-----
4170 19:26:09.684130
4171 19:26:09.684465 ==
4172 19:26:09.686861 Dram Type= 6, Freq= 0, CH_0, rank 1
4173 19:26:09.690028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 19:26:09.690473 ==
4175 19:26:09.693913 [Gating] SW mode calibration
4176 19:26:09.699822 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4177 19:26:09.706690 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4178 19:26:09.710337 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 19:26:09.713379 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 19:26:09.719904 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 19:26:09.723356 0 9 12 | B1->B0 | 3333 3434 | 1 0 | (0 0) (0 1)
4182 19:26:09.726627 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4183 19:26:09.733554 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 19:26:09.736586 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 19:26:09.740137 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 19:26:09.746544 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 19:26:09.750095 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 19:26:09.753279 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 19:26:09.759972 0 10 12 | B1->B0 | 2727 2f2f | 0 1 | (0 0) (0 0)
4190 19:26:09.763281 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4191 19:26:09.766631 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 19:26:09.773286 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 19:26:09.776413 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 19:26:09.779932 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 19:26:09.783129 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 19:26:09.789679 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 19:26:09.792979 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 19:26:09.796310 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4199 19:26:09.802885 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 19:26:09.806653 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 19:26:09.809561 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 19:26:09.816416 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 19:26:09.819999 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 19:26:09.823016 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 19:26:09.829601 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 19:26:09.832970 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 19:26:09.836072 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 19:26:09.842900 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 19:26:09.846105 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 19:26:09.849284 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 19:26:09.856086 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 19:26:09.859324 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 19:26:09.862423 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4214 19:26:09.869367 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 19:26:09.869792 Total UI for P1: 0, mck2ui 16
4216 19:26:09.876502 best dqsien dly found for B0: ( 0, 13, 12)
4217 19:26:09.876926 Total UI for P1: 0, mck2ui 16
4218 19:26:09.879666 best dqsien dly found for B1: ( 0, 13, 12)
4219 19:26:09.886531 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4220 19:26:09.889706 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4221 19:26:09.890127
4222 19:26:09.893041 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4223 19:26:09.896192 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4224 19:26:09.899502 [Gating] SW calibration Done
4225 19:26:09.899925 ==
4226 19:26:09.902881 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 19:26:09.906617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 19:26:09.907049 ==
4229 19:26:09.909795 RX Vref Scan: 0
4230 19:26:09.910215
4231 19:26:09.910548 RX Vref 0 -> 0, step: 1
4232 19:26:09.910864
4233 19:26:09.912855 RX Delay -230 -> 252, step: 16
4234 19:26:09.916201 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4235 19:26:09.922479 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4236 19:26:09.925696 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4237 19:26:09.929029 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4238 19:26:09.932768 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4239 19:26:09.939242 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4240 19:26:09.942331 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4241 19:26:09.945493 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4242 19:26:09.949338 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4243 19:26:09.952116 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4244 19:26:09.958969 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4245 19:26:09.962265 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4246 19:26:09.965034 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4247 19:26:09.971620 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4248 19:26:09.975114 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4249 19:26:09.978287 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4250 19:26:09.978400 ==
4251 19:26:09.981620 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 19:26:09.985201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 19:26:09.985293 ==
4254 19:26:09.988489 DQS Delay:
4255 19:26:09.988574 DQS0 = 0, DQS1 = 0
4256 19:26:09.991760 DQM Delay:
4257 19:26:09.991843 DQM0 = 50, DQM1 = 40
4258 19:26:09.991910 DQ Delay:
4259 19:26:09.995321 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4260 19:26:09.998642 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4261 19:26:10.001698 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4262 19:26:10.005016 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4263 19:26:10.005099
4264 19:26:10.005166
4265 19:26:10.008309 ==
4266 19:26:10.011770 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 19:26:10.014930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 19:26:10.015015 ==
4269 19:26:10.015082
4270 19:26:10.015146
4271 19:26:10.018032 TX Vref Scan disable
4272 19:26:10.018116 == TX Byte 0 ==
4273 19:26:10.024600 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4274 19:26:10.028087 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4275 19:26:10.028177 == TX Byte 1 ==
4276 19:26:10.034938 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4277 19:26:10.038538 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4278 19:26:10.038964 ==
4279 19:26:10.041599 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 19:26:10.044908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 19:26:10.045647 ==
4282 19:26:10.046016
4283 19:26:10.046340
4284 19:26:10.048326 TX Vref Scan disable
4285 19:26:10.051602 == TX Byte 0 ==
4286 19:26:10.054789 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4287 19:26:10.058191 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4288 19:26:10.061768 == TX Byte 1 ==
4289 19:26:10.065385 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4290 19:26:10.068090 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4291 19:26:10.068521
4292 19:26:10.071440 [DATLAT]
4293 19:26:10.071929 Freq=600, CH0 RK1
4294 19:26:10.072270
4295 19:26:10.074931 DATLAT Default: 0x9
4296 19:26:10.075343 0, 0xFFFF, sum = 0
4297 19:26:10.078072 1, 0xFFFF, sum = 0
4298 19:26:10.078493 2, 0xFFFF, sum = 0
4299 19:26:10.081505 3, 0xFFFF, sum = 0
4300 19:26:10.081929 4, 0xFFFF, sum = 0
4301 19:26:10.084567 5, 0xFFFF, sum = 0
4302 19:26:10.084987 6, 0xFFFF, sum = 0
4303 19:26:10.088023 7, 0xFFFF, sum = 0
4304 19:26:10.088530 8, 0x0, sum = 1
4305 19:26:10.091326 9, 0x0, sum = 2
4306 19:26:10.091905 10, 0x0, sum = 3
4307 19:26:10.094923 11, 0x0, sum = 4
4308 19:26:10.095346 best_step = 9
4309 19:26:10.095674
4310 19:26:10.095985 ==
4311 19:26:10.097981 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 19:26:10.104725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 19:26:10.105146 ==
4314 19:26:10.105525 RX Vref Scan: 0
4315 19:26:10.105840
4316 19:26:10.107936 RX Vref 0 -> 0, step: 1
4317 19:26:10.108352
4318 19:26:10.111069 RX Delay -179 -> 252, step: 8
4319 19:26:10.114145 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4320 19:26:10.117565 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4321 19:26:10.124094 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4322 19:26:10.127362 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4323 19:26:10.130707 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4324 19:26:10.134146 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4325 19:26:10.137696 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4326 19:26:10.144285 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4327 19:26:10.147565 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4328 19:26:10.150958 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4329 19:26:10.153918 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4330 19:26:10.160594 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4331 19:26:10.163784 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4332 19:26:10.167214 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4333 19:26:10.170504 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4334 19:26:10.176918 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4335 19:26:10.176999 ==
4336 19:26:10.180616 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 19:26:10.183862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 19:26:10.184277 ==
4339 19:26:10.184607 DQS Delay:
4340 19:26:10.187180 DQS0 = 0, DQS1 = 0
4341 19:26:10.187591 DQM Delay:
4342 19:26:10.190373 DQM0 = 48, DQM1 = 41
4343 19:26:10.190785 DQ Delay:
4344 19:26:10.193795 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4345 19:26:10.197277 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4346 19:26:10.200543 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4347 19:26:10.203426 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4348 19:26:10.203842
4349 19:26:10.204169
4350 19:26:10.210829 [DQSOSCAuto] RK1, (LSB)MR18= 0x6533, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4351 19:26:10.213911 CH0 RK1: MR19=808, MR18=6533
4352 19:26:10.220152 CH0_RK1: MR19=0x808, MR18=0x6533, DQSOSC=390, MR23=63, INC=172, DEC=114
4353 19:26:10.223939 [RxdqsGatingPostProcess] freq 600
4354 19:26:10.230528 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4355 19:26:10.233498 Pre-setting of DQS Precalculation
4356 19:26:10.236768 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4357 19:26:10.237264 ==
4358 19:26:10.240178 Dram Type= 6, Freq= 0, CH_1, rank 0
4359 19:26:10.243621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 19:26:10.244041 ==
4361 19:26:10.250053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4362 19:26:10.256876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4363 19:26:10.260365 [CA 0] Center 35 (5~66) winsize 62
4364 19:26:10.263222 [CA 1] Center 35 (5~66) winsize 62
4365 19:26:10.266619 [CA 2] Center 34 (4~65) winsize 62
4366 19:26:10.269904 [CA 3] Center 33 (3~64) winsize 62
4367 19:26:10.273066 [CA 4] Center 33 (3~64) winsize 62
4368 19:26:10.276664 [CA 5] Center 33 (3~64) winsize 62
4369 19:26:10.276847
4370 19:26:10.279685 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4371 19:26:10.279837
4372 19:26:10.283095 [CATrainingPosCal] consider 1 rank data
4373 19:26:10.286200 u2DelayCellTimex100 = 270/100 ps
4374 19:26:10.290132 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4375 19:26:10.293431 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4376 19:26:10.296516 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 19:26:10.299781 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4378 19:26:10.303146 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4379 19:26:10.309646 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4380 19:26:10.309764
4381 19:26:10.313052 CA PerBit enable=1, Macro0, CA PI delay=33
4382 19:26:10.313175
4383 19:26:10.316521 [CBTSetCACLKResult] CA Dly = 33
4384 19:26:10.316627 CS Dly: 4 (0~35)
4385 19:26:10.316720 ==
4386 19:26:10.320098 Dram Type= 6, Freq= 0, CH_1, rank 1
4387 19:26:10.323074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 19:26:10.323157 ==
4389 19:26:10.330139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 19:26:10.336615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4391 19:26:10.340210 [CA 0] Center 35 (5~66) winsize 62
4392 19:26:10.343396 [CA 1] Center 35 (5~66) winsize 62
4393 19:26:10.346639 [CA 2] Center 34 (4~65) winsize 62
4394 19:26:10.350261 [CA 3] Center 34 (4~64) winsize 61
4395 19:26:10.353401 [CA 4] Center 34 (4~65) winsize 62
4396 19:26:10.356823 [CA 5] Center 33 (3~64) winsize 62
4397 19:26:10.357244
4398 19:26:10.360128 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4399 19:26:10.360553
4400 19:26:10.363405 [CATrainingPosCal] consider 2 rank data
4401 19:26:10.366792 u2DelayCellTimex100 = 270/100 ps
4402 19:26:10.370230 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4403 19:26:10.373022 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4404 19:26:10.376280 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 19:26:10.379814 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4406 19:26:10.386280 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4407 19:26:10.389585 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 19:26:10.389890
4409 19:26:10.393255 CA PerBit enable=1, Macro0, CA PI delay=33
4410 19:26:10.393689
4411 19:26:10.396583 [CBTSetCACLKResult] CA Dly = 33
4412 19:26:10.396975 CS Dly: 4 (0~36)
4413 19:26:10.397372
4414 19:26:10.399895 ----->DramcWriteLeveling(PI) begin...
4415 19:26:10.400301 ==
4416 19:26:10.403229 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 19:26:10.410091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 19:26:10.410493 ==
4419 19:26:10.412806 Write leveling (Byte 0): 28 => 28
4420 19:26:10.413112 Write leveling (Byte 1): 31 => 31
4421 19:26:10.416494 DramcWriteLeveling(PI) end<-----
4422 19:26:10.416982
4423 19:26:10.419877 ==
4424 19:26:10.423177 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 19:26:10.426428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 19:26:10.426992 ==
4427 19:26:10.429485 [Gating] SW mode calibration
4428 19:26:10.436477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4429 19:26:10.440199 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4430 19:26:10.446323 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 19:26:10.449583 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4432 19:26:10.453075 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 19:26:10.459876 0 9 12 | B1->B0 | 2f2f 2b2b | 0 0 | (1 1) (0 0)
4434 19:26:10.463413 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 19:26:10.466150 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 19:26:10.473171 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 19:26:10.476486 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 19:26:10.479623 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 19:26:10.486250 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 19:26:10.489443 0 10 8 | B1->B0 | 2424 2323 | 0 1 | (0 0) (0 0)
4441 19:26:10.492871 0 10 12 | B1->B0 | 3c3c 3f3f | 1 0 | (0 0) (0 0)
4442 19:26:10.499401 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 19:26:10.502879 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 19:26:10.506034 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 19:26:10.509675 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 19:26:10.516481 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 19:26:10.519631 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 19:26:10.522729 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 19:26:10.529664 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4450 19:26:10.532873 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4451 19:26:10.536424 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 19:26:10.542786 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 19:26:10.546034 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 19:26:10.549904 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 19:26:10.555860 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 19:26:10.560019 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 19:26:10.562694 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 19:26:10.569404 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 19:26:10.572802 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 19:26:10.575573 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 19:26:10.582375 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 19:26:10.586080 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 19:26:10.588860 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 19:26:10.595706 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4465 19:26:10.599116 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4466 19:26:10.602511 Total UI for P1: 0, mck2ui 16
4467 19:26:10.605500 best dqsien dly found for B0: ( 0, 13, 8)
4468 19:26:10.609425 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 19:26:10.612798 Total UI for P1: 0, mck2ui 16
4470 19:26:10.615809 best dqsien dly found for B1: ( 0, 13, 12)
4471 19:26:10.619569 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4472 19:26:10.622738 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4473 19:26:10.623328
4474 19:26:10.626213 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4475 19:26:10.632086 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4476 19:26:10.632649 [Gating] SW calibration Done
4477 19:26:10.635623 ==
4478 19:26:10.636091 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 19:26:10.642437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 19:26:10.643019 ==
4481 19:26:10.643403 RX Vref Scan: 0
4482 19:26:10.643760
4483 19:26:10.645431 RX Vref 0 -> 0, step: 1
4484 19:26:10.646004
4485 19:26:10.648546 RX Delay -230 -> 252, step: 16
4486 19:26:10.652159 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4487 19:26:10.655621 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4488 19:26:10.662466 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4489 19:26:10.665682 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4490 19:26:10.668744 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4491 19:26:10.672376 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4492 19:26:10.675502 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4493 19:26:10.681963 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4494 19:26:10.685414 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4495 19:26:10.688545 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4496 19:26:10.691568 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4497 19:26:10.698389 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4498 19:26:10.701793 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4499 19:26:10.705248 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4500 19:26:10.708637 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4501 19:26:10.715246 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4502 19:26:10.715821 ==
4503 19:26:10.718815 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 19:26:10.722221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 19:26:10.722796 ==
4506 19:26:10.723175 DQS Delay:
4507 19:26:10.724906 DQS0 = 0, DQS1 = 0
4508 19:26:10.725420 DQM Delay:
4509 19:26:10.728450 DQM0 = 51, DQM1 = 45
4510 19:26:10.729025 DQ Delay:
4511 19:26:10.731552 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4512 19:26:10.735577 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4513 19:26:10.738204 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4514 19:26:10.741966 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4515 19:26:10.742540
4516 19:26:10.742917
4517 19:26:10.743265 ==
4518 19:26:10.745180 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 19:26:10.748594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 19:26:10.749171 ==
4521 19:26:10.749590
4522 19:26:10.751684
4523 19:26:10.752251 TX Vref Scan disable
4524 19:26:10.755277 == TX Byte 0 ==
4525 19:26:10.758656 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4526 19:26:10.762040 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4527 19:26:10.765156 == TX Byte 1 ==
4528 19:26:10.768533 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4529 19:26:10.771525 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4530 19:26:10.772002 ==
4531 19:26:10.774807 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 19:26:10.781674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 19:26:10.782254 ==
4534 19:26:10.782635
4535 19:26:10.783008
4536 19:26:10.783351 TX Vref Scan disable
4537 19:26:10.786170 == TX Byte 0 ==
4538 19:26:10.789554 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4539 19:26:10.796275 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4540 19:26:10.796854 == TX Byte 1 ==
4541 19:26:10.799160 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4542 19:26:10.806014 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4543 19:26:10.806477
4544 19:26:10.806849 [DATLAT]
4545 19:26:10.807188 Freq=600, CH1 RK0
4546 19:26:10.807523
4547 19:26:10.809123 DATLAT Default: 0x9
4548 19:26:10.809585 0, 0xFFFF, sum = 0
4549 19:26:10.812458 1, 0xFFFF, sum = 0
4550 19:26:10.812886 2, 0xFFFF, sum = 0
4551 19:26:10.815683 3, 0xFFFF, sum = 0
4552 19:26:10.819572 4, 0xFFFF, sum = 0
4553 19:26:10.820103 5, 0xFFFF, sum = 0
4554 19:26:10.822732 6, 0xFFFF, sum = 0
4555 19:26:10.823268 7, 0xFFFF, sum = 0
4556 19:26:10.825783 8, 0x0, sum = 1
4557 19:26:10.826206 9, 0x0, sum = 2
4558 19:26:10.826546 10, 0x0, sum = 3
4559 19:26:10.829101 11, 0x0, sum = 4
4560 19:26:10.829568 best_step = 9
4561 19:26:10.829904
4562 19:26:10.830219 ==
4563 19:26:10.832405 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 19:26:10.839097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 19:26:10.839616 ==
4566 19:26:10.839958 RX Vref Scan: 1
4567 19:26:10.840272
4568 19:26:10.842443 RX Vref 0 -> 0, step: 1
4569 19:26:10.842862
4570 19:26:10.846220 RX Delay -163 -> 252, step: 8
4571 19:26:10.846736
4572 19:26:10.848965 Set Vref, RX VrefLevel [Byte0]: 50
4573 19:26:10.852531 [Byte1]: 50
4574 19:26:10.853047
4575 19:26:10.855611 Final RX Vref Byte 0 = 50 to rank0
4576 19:26:10.859205 Final RX Vref Byte 1 = 50 to rank0
4577 19:26:10.862033 Final RX Vref Byte 0 = 50 to rank1
4578 19:26:10.865735 Final RX Vref Byte 1 = 50 to rank1==
4579 19:26:10.869406 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 19:26:10.872681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 19:26:10.873204 ==
4582 19:26:10.875608 DQS Delay:
4583 19:26:10.876026 DQS0 = 0, DQS1 = 0
4584 19:26:10.876366 DQM Delay:
4585 19:26:10.879142 DQM0 = 49, DQM1 = 41
4586 19:26:10.879560 DQ Delay:
4587 19:26:10.882396 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =48
4588 19:26:10.885720 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4589 19:26:10.889623 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4590 19:26:10.892618 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4591 19:26:10.893041
4592 19:26:10.893405
4593 19:26:10.902205 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4594 19:26:10.905653 CH1 RK0: MR19=808, MR18=4B72
4595 19:26:10.909640 CH1_RK0: MR19=0x808, MR18=0x4B72, DQSOSC=388, MR23=63, INC=174, DEC=116
4596 19:26:10.910174
4597 19:26:10.912411 ----->DramcWriteLeveling(PI) begin...
4598 19:26:10.916145 ==
4599 19:26:10.918793 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 19:26:10.922196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 19:26:10.922621 ==
4602 19:26:10.925706 Write leveling (Byte 0): 30 => 30
4603 19:26:10.928708 Write leveling (Byte 1): 28 => 28
4604 19:26:10.932305 DramcWriteLeveling(PI) end<-----
4605 19:26:10.932822
4606 19:26:10.933156 ==
4607 19:26:10.935787 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 19:26:10.938984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 19:26:10.939547 ==
4610 19:26:10.942232 [Gating] SW mode calibration
4611 19:26:10.948975 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4612 19:26:10.955327 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4613 19:26:10.958876 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 19:26:10.962311 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 19:26:10.968672 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
4616 19:26:10.972018 0 9 12 | B1->B0 | 2727 3030 | 0 1 | (0 0) (1 1)
4617 19:26:10.975308 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 19:26:10.981988 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 19:26:10.985051 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 19:26:10.988258 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 19:26:10.994878 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 19:26:10.998817 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 19:26:11.001569 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4624 19:26:11.004904 0 10 12 | B1->B0 | 3e3e 3333 | 0 1 | (0 0) (0 0)
4625 19:26:11.011622 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 19:26:11.014819 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 19:26:11.018194 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 19:26:11.024866 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 19:26:11.028399 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 19:26:11.031409 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 19:26:11.038634 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 19:26:11.041528 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4633 19:26:11.045346 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 19:26:11.051100 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 19:26:11.054752 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 19:26:11.058255 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 19:26:11.064711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 19:26:11.067963 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 19:26:11.071703 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 19:26:11.078088 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 19:26:11.081156 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 19:26:11.085006 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 19:26:11.091474 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 19:26:11.094559 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 19:26:11.097787 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 19:26:11.104823 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 19:26:11.107930 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 19:26:11.111435 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 19:26:11.114725 Total UI for P1: 0, mck2ui 16
4650 19:26:11.117764 best dqsien dly found for B0: ( 0, 13, 10)
4651 19:26:11.121089 Total UI for P1: 0, mck2ui 16
4652 19:26:11.124375 best dqsien dly found for B1: ( 0, 13, 10)
4653 19:26:11.127844 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4654 19:26:11.130839 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4655 19:26:11.131304
4656 19:26:11.138179 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4657 19:26:11.141114 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4658 19:26:11.141712 [Gating] SW calibration Done
4659 19:26:11.144105 ==
4660 19:26:11.147687 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 19:26:11.150873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 19:26:11.151341 ==
4663 19:26:11.151711 RX Vref Scan: 0
4664 19:26:11.152055
4665 19:26:11.154554 RX Vref 0 -> 0, step: 1
4666 19:26:11.155107
4667 19:26:11.157568 RX Delay -230 -> 252, step: 16
4668 19:26:11.161257 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4669 19:26:11.164272 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4670 19:26:11.171205 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4671 19:26:11.174690 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4672 19:26:11.177496 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4673 19:26:11.180954 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4674 19:26:11.184099 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4675 19:26:11.191109 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4676 19:26:11.194199 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4677 19:26:11.197657 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4678 19:26:11.201004 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4679 19:26:11.207603 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4680 19:26:11.210896 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4681 19:26:11.214078 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4682 19:26:11.217264 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4683 19:26:11.224054 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4684 19:26:11.224657 ==
4685 19:26:11.227925 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 19:26:11.230734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 19:26:11.231202 ==
4688 19:26:11.231572 DQS Delay:
4689 19:26:11.234159 DQS0 = 0, DQS1 = 0
4690 19:26:11.234707 DQM Delay:
4691 19:26:11.237625 DQM0 = 51, DQM1 = 44
4692 19:26:11.238184 DQ Delay:
4693 19:26:11.240524 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4694 19:26:11.244411 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4695 19:26:11.246978 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4696 19:26:11.250470 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =57
4697 19:26:11.251033
4698 19:26:11.251409
4699 19:26:11.251755 ==
4700 19:26:11.253910 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 19:26:11.257378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 19:26:11.257945 ==
4703 19:26:11.258318
4704 19:26:11.258661
4705 19:26:11.260682 TX Vref Scan disable
4706 19:26:11.263786 == TX Byte 0 ==
4707 19:26:11.267252 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4708 19:26:11.270521 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4709 19:26:11.273951 == TX Byte 1 ==
4710 19:26:11.277046 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4711 19:26:11.280275 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4712 19:26:11.280739 ==
4713 19:26:11.283487 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 19:26:11.290781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 19:26:11.291344 ==
4716 19:26:11.291718
4717 19:26:11.292060
4718 19:26:11.292388 TX Vref Scan disable
4719 19:26:11.294967 == TX Byte 0 ==
4720 19:26:11.298188 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4721 19:26:11.304830 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4722 19:26:11.305441 == TX Byte 1 ==
4723 19:26:11.308153 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4724 19:26:11.314897 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4725 19:26:11.315460
4726 19:26:11.315834 [DATLAT]
4727 19:26:11.316179 Freq=600, CH1 RK1
4728 19:26:11.316514
4729 19:26:11.318317 DATLAT Default: 0x9
4730 19:26:11.318890 0, 0xFFFF, sum = 0
4731 19:26:11.321901 1, 0xFFFF, sum = 0
4732 19:26:11.322467 2, 0xFFFF, sum = 0
4733 19:26:11.324684 3, 0xFFFF, sum = 0
4734 19:26:11.328297 4, 0xFFFF, sum = 0
4735 19:26:11.328864 5, 0xFFFF, sum = 0
4736 19:26:11.331272 6, 0xFFFF, sum = 0
4737 19:26:11.331755 7, 0xFFFF, sum = 0
4738 19:26:11.334571 8, 0x0, sum = 1
4739 19:26:11.335134 9, 0x0, sum = 2
4740 19:26:11.335576 10, 0x0, sum = 3
4741 19:26:11.337959 11, 0x0, sum = 4
4742 19:26:11.338527 best_step = 9
4743 19:26:11.338940
4744 19:26:11.339331 ==
4745 19:26:11.341161 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 19:26:11.348032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 19:26:11.348601 ==
4748 19:26:11.348981 RX Vref Scan: 0
4749 19:26:11.349387
4750 19:26:11.351034 RX Vref 0 -> 0, step: 1
4751 19:26:11.351540
4752 19:26:11.354301 RX Delay -163 -> 252, step: 8
4753 19:26:11.357909 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4754 19:26:11.364669 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4755 19:26:11.368177 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4756 19:26:11.371227 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4757 19:26:11.374501 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4758 19:26:11.377595 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4759 19:26:11.384565 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4760 19:26:11.388032 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4761 19:26:11.391165 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4762 19:26:11.394289 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4763 19:26:11.397465 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4764 19:26:11.404223 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4765 19:26:11.407733 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4766 19:26:11.411004 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4767 19:26:11.414000 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4768 19:26:11.421219 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4769 19:26:11.421832 ==
4770 19:26:11.424586 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 19:26:11.427777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 19:26:11.428356 ==
4773 19:26:11.428742 DQS Delay:
4774 19:26:11.430828 DQS0 = 0, DQS1 = 0
4775 19:26:11.431451 DQM Delay:
4776 19:26:11.434147 DQM0 = 48, DQM1 = 44
4777 19:26:11.434613 DQ Delay:
4778 19:26:11.437268 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4779 19:26:11.441065 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4780 19:26:11.444081 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4781 19:26:11.447553 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =56
4782 19:26:11.448124
4783 19:26:11.448502
4784 19:26:11.453850 [DQSOSCAuto] RK1, (LSB)MR18= 0x591f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4785 19:26:11.457340 CH1 RK1: MR19=808, MR18=591F
4786 19:26:11.464255 CH1_RK1: MR19=0x808, MR18=0x591F, DQSOSC=393, MR23=63, INC=169, DEC=113
4787 19:26:11.467362 [RxdqsGatingPostProcess] freq 600
4788 19:26:11.473998 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4789 19:26:11.476966 Pre-setting of DQS Precalculation
4790 19:26:11.480677 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4791 19:26:11.486983 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4792 19:26:11.494012 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4793 19:26:11.494651
4794 19:26:11.495268
4795 19:26:11.496944 [Calibration Summary] 1200 Mbps
4796 19:26:11.500708 CH 0, Rank 0
4797 19:26:11.501283 SW Impedance : PASS
4798 19:26:11.503732 DUTY Scan : NO K
4799 19:26:11.507255 ZQ Calibration : PASS
4800 19:26:11.507834 Jitter Meter : NO K
4801 19:26:11.510351 CBT Training : PASS
4802 19:26:11.513861 Write leveling : PASS
4803 19:26:11.514433 RX DQS gating : PASS
4804 19:26:11.517519 RX DQ/DQS(RDDQC) : PASS
4805 19:26:11.520321 TX DQ/DQS : PASS
4806 19:26:11.520901 RX DATLAT : PASS
4807 19:26:11.523884 RX DQ/DQS(Engine): PASS
4808 19:26:11.524460 TX OE : NO K
4809 19:26:11.526981 All Pass.
4810 19:26:11.527553
4811 19:26:11.527930 CH 0, Rank 1
4812 19:26:11.530368 SW Impedance : PASS
4813 19:26:11.530942 DUTY Scan : NO K
4814 19:26:11.534042 ZQ Calibration : PASS
4815 19:26:11.536884 Jitter Meter : NO K
4816 19:26:11.537425 CBT Training : PASS
4817 19:26:11.540280 Write leveling : PASS
4818 19:26:11.543632 RX DQS gating : PASS
4819 19:26:11.544216 RX DQ/DQS(RDDQC) : PASS
4820 19:26:11.547232 TX DQ/DQS : PASS
4821 19:26:11.550193 RX DATLAT : PASS
4822 19:26:11.550768 RX DQ/DQS(Engine): PASS
4823 19:26:11.553388 TX OE : NO K
4824 19:26:11.553884 All Pass.
4825 19:26:11.554260
4826 19:26:11.556571 CH 1, Rank 0
4827 19:26:11.557041 SW Impedance : PASS
4828 19:26:11.560117 DUTY Scan : NO K
4829 19:26:11.563496 ZQ Calibration : PASS
4830 19:26:11.563967 Jitter Meter : NO K
4831 19:26:11.566616 CBT Training : PASS
4832 19:26:11.569838 Write leveling : PASS
4833 19:26:11.570452 RX DQS gating : PASS
4834 19:26:11.573469 RX DQ/DQS(RDDQC) : PASS
4835 19:26:11.576482 TX DQ/DQS : PASS
4836 19:26:11.576957 RX DATLAT : PASS
4837 19:26:11.579898 RX DQ/DQS(Engine): PASS
4838 19:26:11.580369 TX OE : NO K
4839 19:26:11.583298 All Pass.
4840 19:26:11.583786
4841 19:26:11.584167 CH 1, Rank 1
4842 19:26:11.586717 SW Impedance : PASS
4843 19:26:11.587189 DUTY Scan : NO K
4844 19:26:11.590025 ZQ Calibration : PASS
4845 19:26:11.593417 Jitter Meter : NO K
4846 19:26:11.593980 CBT Training : PASS
4847 19:26:11.596422 Write leveling : PASS
4848 19:26:11.599822 RX DQS gating : PASS
4849 19:26:11.600294 RX DQ/DQS(RDDQC) : PASS
4850 19:26:11.603943 TX DQ/DQS : PASS
4851 19:26:11.607100 RX DATLAT : PASS
4852 19:26:11.607657 RX DQ/DQS(Engine): PASS
4853 19:26:11.609880 TX OE : NO K
4854 19:26:11.610354 All Pass.
4855 19:26:11.610728
4856 19:26:11.613287 DramC Write-DBI off
4857 19:26:11.616472 PER_BANK_REFRESH: Hybrid Mode
4858 19:26:11.616956 TX_TRACKING: ON
4859 19:26:11.626816 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4860 19:26:11.630020 [FAST_K] Save calibration result to emmc
4861 19:26:11.633283 dramc_set_vcore_voltage set vcore to 662500
4862 19:26:11.636594 Read voltage for 933, 3
4863 19:26:11.637151 Vio18 = 0
4864 19:26:11.637590 Vcore = 662500
4865 19:26:11.640089 Vdram = 0
4866 19:26:11.640650 Vddq = 0
4867 19:26:11.641049 Vmddr = 0
4868 19:26:11.646237 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4869 19:26:11.649747 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4870 19:26:11.652963 MEM_TYPE=3, freq_sel=17
4871 19:26:11.656663 sv_algorithm_assistance_LP4_1600
4872 19:26:11.659630 ============ PULL DRAM RESETB DOWN ============
4873 19:26:11.663085 ========== PULL DRAM RESETB DOWN end =========
4874 19:26:11.669533 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4875 19:26:11.673079 ===================================
4876 19:26:11.673792 LPDDR4 DRAM CONFIGURATION
4877 19:26:11.676367 ===================================
4878 19:26:11.679787 EX_ROW_EN[0] = 0x0
4879 19:26:11.682912 EX_ROW_EN[1] = 0x0
4880 19:26:11.683382 LP4Y_EN = 0x0
4881 19:26:11.686422 WORK_FSP = 0x0
4882 19:26:11.686893 WL = 0x3
4883 19:26:11.689975 RL = 0x3
4884 19:26:11.690538 BL = 0x2
4885 19:26:11.693430 RPST = 0x0
4886 19:26:11.693990 RD_PRE = 0x0
4887 19:26:11.696293 WR_PRE = 0x1
4888 19:26:11.696761 WR_PST = 0x0
4889 19:26:11.699468 DBI_WR = 0x0
4890 19:26:11.699973 DBI_RD = 0x0
4891 19:26:11.702839 OTF = 0x1
4892 19:26:11.706519 ===================================
4893 19:26:11.709719 ===================================
4894 19:26:11.710187 ANA top config
4895 19:26:11.713094 ===================================
4896 19:26:11.716174 DLL_ASYNC_EN = 0
4897 19:26:11.719597 ALL_SLAVE_EN = 1
4898 19:26:11.722735 NEW_RANK_MODE = 1
4899 19:26:11.723303 DLL_IDLE_MODE = 1
4900 19:26:11.725953 LP45_APHY_COMB_EN = 1
4901 19:26:11.729608 TX_ODT_DIS = 1
4902 19:26:11.732964 NEW_8X_MODE = 1
4903 19:26:11.736235 ===================================
4904 19:26:11.739300 ===================================
4905 19:26:11.742938 data_rate = 1866
4906 19:26:11.743410 CKR = 1
4907 19:26:11.745956 DQ_P2S_RATIO = 8
4908 19:26:11.749434 ===================================
4909 19:26:11.752864 CA_P2S_RATIO = 8
4910 19:26:11.756084 DQ_CA_OPEN = 0
4911 19:26:11.759500 DQ_SEMI_OPEN = 0
4912 19:26:11.762506 CA_SEMI_OPEN = 0
4913 19:26:11.763074 CA_FULL_RATE = 0
4914 19:26:11.765922 DQ_CKDIV4_EN = 1
4915 19:26:11.768927 CA_CKDIV4_EN = 1
4916 19:26:11.772851 CA_PREDIV_EN = 0
4917 19:26:11.775681 PH8_DLY = 0
4918 19:26:11.779337 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4919 19:26:11.779804 DQ_AAMCK_DIV = 4
4920 19:26:11.782362 CA_AAMCK_DIV = 4
4921 19:26:11.785589 CA_ADMCK_DIV = 4
4922 19:26:11.789007 DQ_TRACK_CA_EN = 0
4923 19:26:11.792818 CA_PICK = 933
4924 19:26:11.796028 CA_MCKIO = 933
4925 19:26:11.796497 MCKIO_SEMI = 0
4926 19:26:11.799406 PLL_FREQ = 3732
4927 19:26:11.802330 DQ_UI_PI_RATIO = 32
4928 19:26:11.805485 CA_UI_PI_RATIO = 0
4929 19:26:11.809260 ===================================
4930 19:26:11.812296 ===================================
4931 19:26:11.815829 memory_type:LPDDR4
4932 19:26:11.816396 GP_NUM : 10
4933 19:26:11.819280 SRAM_EN : 1
4934 19:26:11.822654 MD32_EN : 0
4935 19:26:11.825905 ===================================
4936 19:26:11.826465 [ANA_INIT] >>>>>>>>>>>>>>
4937 19:26:11.828926 <<<<<< [CONFIGURE PHASE]: ANA_TX
4938 19:26:11.831928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4939 19:26:11.835618 ===================================
4940 19:26:11.838899 data_rate = 1866,PCW = 0X8f00
4941 19:26:11.841864 ===================================
4942 19:26:11.845736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4943 19:26:11.851976 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4944 19:26:11.855280 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4945 19:26:11.862224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4946 19:26:11.865159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4947 19:26:11.868867 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4948 19:26:11.869360 [ANA_INIT] flow start
4949 19:26:11.872037 [ANA_INIT] PLL >>>>>>>>
4950 19:26:11.875178 [ANA_INIT] PLL <<<<<<<<
4951 19:26:11.878675 [ANA_INIT] MIDPI >>>>>>>>
4952 19:26:11.879174 [ANA_INIT] MIDPI <<<<<<<<
4953 19:26:11.881914 [ANA_INIT] DLL >>>>>>>>
4954 19:26:11.885217 [ANA_INIT] flow end
4955 19:26:11.888599 ============ LP4 DIFF to SE enter ============
4956 19:26:11.892153 ============ LP4 DIFF to SE exit ============
4957 19:26:11.895264 [ANA_INIT] <<<<<<<<<<<<<
4958 19:26:11.898421 [Flow] Enable top DCM control >>>>>
4959 19:26:11.901816 [Flow] Enable top DCM control <<<<<
4960 19:26:11.905232 Enable DLL master slave shuffle
4961 19:26:11.908771 ==============================================================
4962 19:26:11.911867 Gating Mode config
4963 19:26:11.915311 ==============================================================
4964 19:26:11.918354 Config description:
4965 19:26:11.928697 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4966 19:26:11.935131 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4967 19:26:11.938160 SELPH_MODE 0: By rank 1: By Phase
4968 19:26:11.945216 ==============================================================
4969 19:26:11.948243 GAT_TRACK_EN = 1
4970 19:26:11.951700 RX_GATING_MODE = 2
4971 19:26:11.954751 RX_GATING_TRACK_MODE = 2
4972 19:26:11.958193 SELPH_MODE = 1
4973 19:26:11.961737 PICG_EARLY_EN = 1
4974 19:26:11.962312 VALID_LAT_VALUE = 1
4975 19:26:11.968127 ==============================================================
4976 19:26:11.971465 Enter into Gating configuration >>>>
4977 19:26:11.974702 Exit from Gating configuration <<<<
4978 19:26:11.977937 Enter into DVFS_PRE_config >>>>>
4979 19:26:11.987918 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4980 19:26:11.991358 Exit from DVFS_PRE_config <<<<<
4981 19:26:11.994927 Enter into PICG configuration >>>>
4982 19:26:11.998228 Exit from PICG configuration <<<<
4983 19:26:12.001680 [RX_INPUT] configuration >>>>>
4984 19:26:12.004604 [RX_INPUT] configuration <<<<<
4985 19:26:12.011498 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4986 19:26:12.014785 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4987 19:26:12.021816 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4988 19:26:12.027979 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4989 19:26:12.034632 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4990 19:26:12.041396 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4991 19:26:12.044349 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4992 19:26:12.048020 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4993 19:26:12.051009 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4994 19:26:12.057959 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4995 19:26:12.061320 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4996 19:26:12.064517 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4997 19:26:12.068171 ===================================
4998 19:26:12.071033 LPDDR4 DRAM CONFIGURATION
4999 19:26:12.074670 ===================================
5000 19:26:12.075138 EX_ROW_EN[0] = 0x0
5001 19:26:12.077593 EX_ROW_EN[1] = 0x0
5002 19:26:12.078055 LP4Y_EN = 0x0
5003 19:26:12.081158 WORK_FSP = 0x0
5004 19:26:12.084660 WL = 0x3
5005 19:26:12.085219 RL = 0x3
5006 19:26:12.087931 BL = 0x2
5007 19:26:12.088495 RPST = 0x0
5008 19:26:12.090993 RD_PRE = 0x0
5009 19:26:12.091456 WR_PRE = 0x1
5010 19:26:12.094187 WR_PST = 0x0
5011 19:26:12.094649 DBI_WR = 0x0
5012 19:26:12.097755 DBI_RD = 0x0
5013 19:26:12.098362 OTF = 0x1
5014 19:26:12.101004 ===================================
5015 19:26:12.104576 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5016 19:26:12.111149 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5017 19:26:12.114110 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5018 19:26:12.117828 ===================================
5019 19:26:12.121217 LPDDR4 DRAM CONFIGURATION
5020 19:26:12.124528 ===================================
5021 19:26:12.125097 EX_ROW_EN[0] = 0x10
5022 19:26:12.127366 EX_ROW_EN[1] = 0x0
5023 19:26:12.128035 LP4Y_EN = 0x0
5024 19:26:12.130601 WORK_FSP = 0x0
5025 19:26:12.131063 WL = 0x3
5026 19:26:12.134018 RL = 0x3
5027 19:26:12.137762 BL = 0x2
5028 19:26:12.138321 RPST = 0x0
5029 19:26:12.140684 RD_PRE = 0x0
5030 19:26:12.141247 WR_PRE = 0x1
5031 19:26:12.144184 WR_PST = 0x0
5032 19:26:12.144747 DBI_WR = 0x0
5033 19:26:12.147379 DBI_RD = 0x0
5034 19:26:12.147943 OTF = 0x1
5035 19:26:12.150553 ===================================
5036 19:26:12.157121 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5037 19:26:12.161238 nWR fixed to 30
5038 19:26:12.164762 [ModeRegInit_LP4] CH0 RK0
5039 19:26:12.165367 [ModeRegInit_LP4] CH0 RK1
5040 19:26:12.167775 [ModeRegInit_LP4] CH1 RK0
5041 19:26:12.171374 [ModeRegInit_LP4] CH1 RK1
5042 19:26:12.171936 match AC timing 9
5043 19:26:12.177896 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5044 19:26:12.180830 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5045 19:26:12.184327 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5046 19:26:12.191033 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5047 19:26:12.194594 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5048 19:26:12.195064 ==
5049 19:26:12.197595 Dram Type= 6, Freq= 0, CH_0, rank 0
5050 19:26:12.200934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5051 19:26:12.201430 ==
5052 19:26:12.207896 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5053 19:26:12.214417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5054 19:26:12.217455 [CA 0] Center 38 (7~69) winsize 63
5055 19:26:12.220775 [CA 1] Center 38 (8~69) winsize 62
5056 19:26:12.224462 [CA 2] Center 35 (5~66) winsize 62
5057 19:26:12.227788 [CA 3] Center 35 (5~65) winsize 61
5058 19:26:12.230943 [CA 4] Center 34 (4~65) winsize 62
5059 19:26:12.234096 [CA 5] Center 33 (3~64) winsize 62
5060 19:26:12.234561
5061 19:26:12.237865 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5062 19:26:12.238427
5063 19:26:12.240852 [CATrainingPosCal] consider 1 rank data
5064 19:26:12.244498 u2DelayCellTimex100 = 270/100 ps
5065 19:26:12.247575 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5066 19:26:12.250909 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5067 19:26:12.253953 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5068 19:26:12.257722 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5069 19:26:12.260973 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5070 19:26:12.267752 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5071 19:26:12.268316
5072 19:26:12.270972 CA PerBit enable=1, Macro0, CA PI delay=33
5073 19:26:12.271534
5074 19:26:12.274161 [CBTSetCACLKResult] CA Dly = 33
5075 19:26:12.274626 CS Dly: 7 (0~38)
5076 19:26:12.274997 ==
5077 19:26:12.277737 Dram Type= 6, Freq= 0, CH_0, rank 1
5078 19:26:12.280435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 19:26:12.283812 ==
5080 19:26:12.287198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5081 19:26:12.293698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5082 19:26:12.297004 [CA 0] Center 38 (8~69) winsize 62
5083 19:26:12.300168 [CA 1] Center 38 (8~69) winsize 62
5084 19:26:12.303556 [CA 2] Center 36 (6~67) winsize 62
5085 19:26:12.307152 [CA 3] Center 35 (5~66) winsize 62
5086 19:26:12.310518 [CA 4] Center 34 (4~65) winsize 62
5087 19:26:12.313507 [CA 5] Center 34 (4~65) winsize 62
5088 19:26:12.313975
5089 19:26:12.317093 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5090 19:26:12.317668
5091 19:26:12.320319 [CATrainingPosCal] consider 2 rank data
5092 19:26:12.323892 u2DelayCellTimex100 = 270/100 ps
5093 19:26:12.327191 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5094 19:26:12.331012 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5095 19:26:12.333825 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5096 19:26:12.337577 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5097 19:26:12.343819 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5098 19:26:12.347309 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5099 19:26:12.347867
5100 19:26:12.350133 CA PerBit enable=1, Macro0, CA PI delay=34
5101 19:26:12.350690
5102 19:26:12.353802 [CBTSetCACLKResult] CA Dly = 34
5103 19:26:12.354363 CS Dly: 7 (0~39)
5104 19:26:12.354738
5105 19:26:12.356542 ----->DramcWriteLeveling(PI) begin...
5106 19:26:12.357007 ==
5107 19:26:12.360471 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 19:26:12.366596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 19:26:12.367154 ==
5110 19:26:12.370298 Write leveling (Byte 0): 32 => 32
5111 19:26:12.373860 Write leveling (Byte 1): 28 => 28
5112 19:26:12.374432 DramcWriteLeveling(PI) end<-----
5113 19:26:12.374809
5114 19:26:12.376942 ==
5115 19:26:12.377561 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 19:26:12.383495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 19:26:12.383977 ==
5118 19:26:12.386835 [Gating] SW mode calibration
5119 19:26:12.393664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5120 19:26:12.396738 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5121 19:26:12.403253 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
5122 19:26:12.406810 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 19:26:12.410169 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 19:26:12.416823 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 19:26:12.419978 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 19:26:12.423124 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 19:26:12.429858 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5128 19:26:12.433720 0 14 28 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)
5129 19:26:12.436764 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
5130 19:26:12.443065 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 19:26:12.446308 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 19:26:12.449885 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 19:26:12.456640 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 19:26:12.459871 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 19:26:12.463002 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
5136 19:26:12.469951 0 15 28 | B1->B0 | 2b2b 4545 | 1 0 | (1 1) (0 0)
5137 19:26:12.473378 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5138 19:26:12.476627 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 19:26:12.479859 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 19:26:12.486817 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 19:26:12.490074 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 19:26:12.492987 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 19:26:12.499917 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 19:26:12.503145 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5145 19:26:12.506387 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5146 19:26:12.512937 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 19:26:12.516327 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 19:26:12.519429 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 19:26:12.525947 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 19:26:12.529385 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 19:26:12.533154 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 19:26:12.539528 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 19:26:12.542751 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 19:26:12.546589 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 19:26:12.552950 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 19:26:12.556407 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 19:26:12.559883 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 19:26:12.566363 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 19:26:12.569526 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5160 19:26:12.573110 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5161 19:26:12.579749 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 19:26:12.580269 Total UI for P1: 0, mck2ui 16
5163 19:26:12.582889 best dqsien dly found for B0: ( 1, 2, 26)
5164 19:26:12.586160 Total UI for P1: 0, mck2ui 16
5165 19:26:12.589738 best dqsien dly found for B1: ( 1, 2, 30)
5166 19:26:12.595951 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5167 19:26:12.599464 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5168 19:26:12.599931
5169 19:26:12.602524 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5170 19:26:12.605805 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5171 19:26:12.609232 [Gating] SW calibration Done
5172 19:26:12.609743 ==
5173 19:26:12.612786 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 19:26:12.615975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 19:26:12.616447 ==
5176 19:26:12.619042 RX Vref Scan: 0
5177 19:26:12.619691
5178 19:26:12.620229 RX Vref 0 -> 0, step: 1
5179 19:26:12.620761
5180 19:26:12.622572 RX Delay -80 -> 252, step: 8
5181 19:26:12.626304 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5182 19:26:12.632524 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5183 19:26:12.635695 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5184 19:26:12.638840 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5185 19:26:12.642298 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5186 19:26:12.645877 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5187 19:26:12.648776 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5188 19:26:12.655908 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5189 19:26:12.658930 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5190 19:26:12.662227 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5191 19:26:12.665938 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5192 19:26:12.669069 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5193 19:26:12.672280 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5194 19:26:12.678919 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5195 19:26:12.682131 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5196 19:26:12.685256 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5197 19:26:12.685897 ==
5198 19:26:12.688652 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 19:26:12.692051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 19:26:12.692517 ==
5201 19:26:12.695225 DQS Delay:
5202 19:26:12.695684 DQS0 = 0, DQS1 = 0
5203 19:26:12.698619 DQM Delay:
5204 19:26:12.699179 DQM0 = 106, DQM1 = 90
5205 19:26:12.699554 DQ Delay:
5206 19:26:12.701945 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5207 19:26:12.705372 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5208 19:26:12.708546 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5209 19:26:12.712032 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5210 19:26:12.715377
5211 19:26:12.715966
5212 19:26:12.716384 ==
5213 19:26:12.718408 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 19:26:12.721780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 19:26:12.722275 ==
5216 19:26:12.722640
5217 19:26:12.722980
5218 19:26:12.725159 TX Vref Scan disable
5219 19:26:12.725683 == TX Byte 0 ==
5220 19:26:12.731499 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5221 19:26:12.734880 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5222 19:26:12.735371 == TX Byte 1 ==
5223 19:26:12.741572 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5224 19:26:12.745091 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5225 19:26:12.745611 ==
5226 19:26:12.748596 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 19:26:12.751640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 19:26:12.752111 ==
5229 19:26:12.752484
5230 19:26:12.752829
5231 19:26:12.754818 TX Vref Scan disable
5232 19:26:12.758121 == TX Byte 0 ==
5233 19:26:12.761062 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5234 19:26:12.764547 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5235 19:26:12.768065 == TX Byte 1 ==
5236 19:26:12.771305 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5237 19:26:12.774542 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5238 19:26:12.774967
5239 19:26:12.777975 [DATLAT]
5240 19:26:12.778477 Freq=933, CH0 RK0
5241 19:26:12.778905
5242 19:26:12.781165 DATLAT Default: 0xd
5243 19:26:12.781601 0, 0xFFFF, sum = 0
5244 19:26:12.784199 1, 0xFFFF, sum = 0
5245 19:26:12.784775 2, 0xFFFF, sum = 0
5246 19:26:12.787800 3, 0xFFFF, sum = 0
5247 19:26:12.788340 4, 0xFFFF, sum = 0
5248 19:26:12.790908 5, 0xFFFF, sum = 0
5249 19:26:12.791456 6, 0xFFFF, sum = 0
5250 19:26:12.794616 7, 0xFFFF, sum = 0
5251 19:26:12.797828 8, 0xFFFF, sum = 0
5252 19:26:12.798445 9, 0xFFFF, sum = 0
5253 19:26:12.799010 10, 0x0, sum = 1
5254 19:26:12.800827 11, 0x0, sum = 2
5255 19:26:12.801469 12, 0x0, sum = 3
5256 19:26:12.804685 13, 0x0, sum = 4
5257 19:26:12.805115 best_step = 11
5258 19:26:12.805691
5259 19:26:12.806069 ==
5260 19:26:12.807826 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 19:26:12.814370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 19:26:12.814802 ==
5263 19:26:12.815147 RX Vref Scan: 1
5264 19:26:12.815465
5265 19:26:12.817677 RX Vref 0 -> 0, step: 1
5266 19:26:12.818103
5267 19:26:12.820916 RX Delay -53 -> 252, step: 4
5268 19:26:12.821371
5269 19:26:12.824534 Set Vref, RX VrefLevel [Byte0]: 62
5270 19:26:12.828120 [Byte1]: 50
5271 19:26:12.828549
5272 19:26:12.830914 Final RX Vref Byte 0 = 62 to rank0
5273 19:26:12.834442 Final RX Vref Byte 1 = 50 to rank0
5274 19:26:12.837583 Final RX Vref Byte 0 = 62 to rank1
5275 19:26:12.841114 Final RX Vref Byte 1 = 50 to rank1==
5276 19:26:12.844042 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 19:26:12.847606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 19:26:12.848037 ==
5279 19:26:12.850983 DQS Delay:
5280 19:26:12.851410 DQS0 = 0, DQS1 = 0
5281 19:26:12.854087 DQM Delay:
5282 19:26:12.854515 DQM0 = 107, DQM1 = 91
5283 19:26:12.854859 DQ Delay:
5284 19:26:12.858035 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =104
5285 19:26:12.860983 DQ4 =110, DQ5 =98, DQ6 =118, DQ7 =116
5286 19:26:12.864221 DQ8 =88, DQ9 =78, DQ10 =90, DQ11 =90
5287 19:26:12.870877 DQ12 =94, DQ13 =92, DQ14 =104, DQ15 =98
5288 19:26:12.871315
5289 19:26:12.871750
5290 19:26:12.877936 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
5291 19:26:12.880675 CH0 RK0: MR19=505, MR18=1F1B
5292 19:26:12.887227 CH0_RK0: MR19=0x505, MR18=0x1F1B, DQSOSC=412, MR23=63, INC=63, DEC=42
5293 19:26:12.887789
5294 19:26:12.890919 ----->DramcWriteLeveling(PI) begin...
5295 19:26:12.891471 ==
5296 19:26:12.894187 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 19:26:12.897360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 19:26:12.897874 ==
5299 19:26:12.900570 Write leveling (Byte 0): 35 => 35
5300 19:26:12.903897 Write leveling (Byte 1): 28 => 28
5301 19:26:12.907520 DramcWriteLeveling(PI) end<-----
5302 19:26:12.907826
5303 19:26:12.908009 ==
5304 19:26:12.910934 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 19:26:12.913941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 19:26:12.914204 ==
5307 19:26:12.917421 [Gating] SW mode calibration
5308 19:26:12.924099 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5309 19:26:12.930407 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5310 19:26:12.933761 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 19:26:12.937195 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 19:26:12.943607 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 19:26:12.947036 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 19:26:12.950518 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 19:26:12.956990 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 19:26:12.960194 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5317 19:26:12.963354 0 14 28 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (1 0)
5318 19:26:12.970235 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 19:26:12.973494 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 19:26:12.977048 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 19:26:12.983673 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 19:26:12.986871 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 19:26:12.990876 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 19:26:12.997266 0 15 24 | B1->B0 | 2727 2d2d | 0 0 | (0 0) (0 0)
5325 19:26:13.000522 0 15 28 | B1->B0 | 3939 3c3c | 1 0 | (0 0) (1 1)
5326 19:26:13.003754 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 19:26:13.010549 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 19:26:13.013924 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 19:26:13.017329 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 19:26:13.023927 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 19:26:13.027263 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 19:26:13.030509 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 19:26:13.037575 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5334 19:26:13.040749 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5335 19:26:13.043914 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 19:26:13.047060 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 19:26:13.054119 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 19:26:13.057277 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 19:26:13.060688 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 19:26:13.066795 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 19:26:13.070421 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 19:26:13.073292 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 19:26:13.080003 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 19:26:13.083395 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 19:26:13.086800 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 19:26:13.093932 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 19:26:13.096788 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 19:26:13.100517 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5349 19:26:13.106672 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 19:26:13.110398 Total UI for P1: 0, mck2ui 16
5351 19:26:13.113856 best dqsien dly found for B0: ( 1, 2, 24)
5352 19:26:13.114417 Total UI for P1: 0, mck2ui 16
5353 19:26:13.120323 best dqsien dly found for B1: ( 1, 2, 24)
5354 19:26:13.123717 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5355 19:26:13.126724 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5356 19:26:13.127287
5357 19:26:13.130237 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5358 19:26:13.133623 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5359 19:26:13.136806 [Gating] SW calibration Done
5360 19:26:13.137414 ==
5361 19:26:13.139931 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 19:26:13.143137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 19:26:13.143608 ==
5364 19:26:13.146774 RX Vref Scan: 0
5365 19:26:13.147335
5366 19:26:13.147707 RX Vref 0 -> 0, step: 1
5367 19:26:13.148056
5368 19:26:13.149683 RX Delay -80 -> 252, step: 8
5369 19:26:13.156405 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5370 19:26:13.159818 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5371 19:26:13.162799 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5372 19:26:13.166496 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5373 19:26:13.169359 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5374 19:26:13.173074 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5375 19:26:13.179740 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5376 19:26:13.183118 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5377 19:26:13.186415 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5378 19:26:13.189471 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5379 19:26:13.192867 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5380 19:26:13.196582 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5381 19:26:13.202666 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5382 19:26:13.206040 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5383 19:26:13.209279 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5384 19:26:13.212877 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5385 19:26:13.213119 ==
5386 19:26:13.216106 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 19:26:13.219195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 19:26:13.219475 ==
5389 19:26:13.222468 DQS Delay:
5390 19:26:13.222770 DQS0 = 0, DQS1 = 0
5391 19:26:13.225932 DQM Delay:
5392 19:26:13.226225 DQM0 = 104, DQM1 = 90
5393 19:26:13.226500 DQ Delay:
5394 19:26:13.229132 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5395 19:26:13.232438 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5396 19:26:13.235456 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5397 19:26:13.242252 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =91
5398 19:26:13.242493
5399 19:26:13.242687
5400 19:26:13.242867 ==
5401 19:26:13.245930 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 19:26:13.249106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 19:26:13.249373 ==
5404 19:26:13.249575
5405 19:26:13.249756
5406 19:26:13.252122 TX Vref Scan disable
5407 19:26:13.252362 == TX Byte 0 ==
5408 19:26:13.259028 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5409 19:26:13.262223 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5410 19:26:13.262468 == TX Byte 1 ==
5411 19:26:13.268950 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5412 19:26:13.272259 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5413 19:26:13.272502 ==
5414 19:26:13.275738 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 19:26:13.279106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 19:26:13.279355 ==
5417 19:26:13.279547
5418 19:26:13.279741
5419 19:26:13.282900 TX Vref Scan disable
5420 19:26:13.285862 == TX Byte 0 ==
5421 19:26:13.288909 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5422 19:26:13.292352 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5423 19:26:13.295773 == TX Byte 1 ==
5424 19:26:13.299094 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5425 19:26:13.301999 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5426 19:26:13.302109
5427 19:26:13.305757 [DATLAT]
5428 19:26:13.305839 Freq=933, CH0 RK1
5429 19:26:13.305904
5430 19:26:13.308814 DATLAT Default: 0xb
5431 19:26:13.308895 0, 0xFFFF, sum = 0
5432 19:26:13.312612 1, 0xFFFF, sum = 0
5433 19:26:13.312773 2, 0xFFFF, sum = 0
5434 19:26:13.315363 3, 0xFFFF, sum = 0
5435 19:26:13.315549 4, 0xFFFF, sum = 0
5436 19:26:13.318886 5, 0xFFFF, sum = 0
5437 19:26:13.318997 6, 0xFFFF, sum = 0
5438 19:26:13.322006 7, 0xFFFF, sum = 0
5439 19:26:13.322119 8, 0xFFFF, sum = 0
5440 19:26:13.325436 9, 0xFFFF, sum = 0
5441 19:26:13.325521 10, 0x0, sum = 1
5442 19:26:13.328439 11, 0x0, sum = 2
5443 19:26:13.328522 12, 0x0, sum = 3
5444 19:26:13.331988 13, 0x0, sum = 4
5445 19:26:13.332105 best_step = 11
5446 19:26:13.332197
5447 19:26:13.332274 ==
5448 19:26:13.335183 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 19:26:13.341959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 19:26:13.342101 ==
5451 19:26:13.342187 RX Vref Scan: 0
5452 19:26:13.342280
5453 19:26:13.345188 RX Vref 0 -> 0, step: 1
5454 19:26:13.345351
5455 19:26:13.348796 RX Delay -53 -> 252, step: 4
5456 19:26:13.352013 iDelay=203, Bit 0, Center 102 (15 ~ 190) 176
5457 19:26:13.358559 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5458 19:26:13.361570 iDelay=203, Bit 2, Center 100 (11 ~ 190) 180
5459 19:26:13.366075 iDelay=203, Bit 3, Center 100 (15 ~ 186) 172
5460 19:26:13.368687 iDelay=203, Bit 4, Center 106 (19 ~ 194) 176
5461 19:26:13.372357 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5462 19:26:13.379073 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5463 19:26:13.381957 iDelay=203, Bit 7, Center 112 (27 ~ 198) 172
5464 19:26:13.385117 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5465 19:26:13.388352 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5466 19:26:13.391999 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5467 19:26:13.398739 iDelay=203, Bit 11, Center 90 (7 ~ 174) 168
5468 19:26:13.401629 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5469 19:26:13.404887 iDelay=203, Bit 13, Center 96 (15 ~ 178) 164
5470 19:26:13.408131 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5471 19:26:13.411591 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5472 19:26:13.412109 ==
5473 19:26:13.415054 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 19:26:13.421649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 19:26:13.422182 ==
5476 19:26:13.422715 DQS Delay:
5477 19:26:13.424735 DQS0 = 0, DQS1 = 0
5478 19:26:13.425193 DQM Delay:
5479 19:26:13.425619 DQM0 = 104, DQM1 = 92
5480 19:26:13.428401 DQ Delay:
5481 19:26:13.431736 DQ0 =102, DQ1 =106, DQ2 =100, DQ3 =100
5482 19:26:13.434948 DQ4 =106, DQ5 =96, DQ6 =114, DQ7 =112
5483 19:26:13.438060 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =90
5484 19:26:13.441648 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =98
5485 19:26:13.442209
5486 19:26:13.442616
5487 19:26:13.448303 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5488 19:26:13.451708 CH0 RK1: MR19=505, MR18=2B0C
5489 19:26:13.458290 CH0_RK1: MR19=0x505, MR18=0x2B0C, DQSOSC=408, MR23=63, INC=65, DEC=43
5490 19:26:13.461708 [RxdqsGatingPostProcess] freq 933
5491 19:26:13.468310 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5492 19:26:13.471443 best DQS0 dly(2T, 0.5T) = (0, 10)
5493 19:26:13.471942 best DQS1 dly(2T, 0.5T) = (0, 10)
5494 19:26:13.475267 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5495 19:26:13.478169 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5496 19:26:13.481657 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 19:26:13.485081 best DQS1 dly(2T, 0.5T) = (0, 10)
5498 19:26:13.487906 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 19:26:13.491588 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5500 19:26:13.494421 Pre-setting of DQS Precalculation
5501 19:26:13.501215 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5502 19:26:13.501875 ==
5503 19:26:13.504435 Dram Type= 6, Freq= 0, CH_1, rank 0
5504 19:26:13.507511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 19:26:13.508168 ==
5506 19:26:13.514177 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5507 19:26:13.517982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5508 19:26:13.522090 [CA 0] Center 37 (7~68) winsize 62
5509 19:26:13.525337 [CA 1] Center 37 (7~68) winsize 62
5510 19:26:13.528735 [CA 2] Center 36 (6~66) winsize 61
5511 19:26:13.531711 [CA 3] Center 34 (4~65) winsize 62
5512 19:26:13.535063 [CA 4] Center 35 (5~66) winsize 62
5513 19:26:13.538158 [CA 5] Center 34 (4~65) winsize 62
5514 19:26:13.538789
5515 19:26:13.541636 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5516 19:26:13.542142
5517 19:26:13.545019 [CATrainingPosCal] consider 1 rank data
5518 19:26:13.548112 u2DelayCellTimex100 = 270/100 ps
5519 19:26:13.551604 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5520 19:26:13.558461 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5521 19:26:13.561558 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5522 19:26:13.564934 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5523 19:26:13.568144 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5524 19:26:13.571214 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5525 19:26:13.571717
5526 19:26:13.574608 CA PerBit enable=1, Macro0, CA PI delay=34
5527 19:26:13.575037
5528 19:26:13.577887 [CBTSetCACLKResult] CA Dly = 34
5529 19:26:13.581238 CS Dly: 6 (0~37)
5530 19:26:13.581864 ==
5531 19:26:13.584389 Dram Type= 6, Freq= 0, CH_1, rank 1
5532 19:26:13.588051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 19:26:13.588511 ==
5534 19:26:13.594599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 19:26:13.598032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5536 19:26:13.601681 [CA 0] Center 38 (7~69) winsize 63
5537 19:26:13.605573 [CA 1] Center 38 (7~69) winsize 63
5538 19:26:13.608695 [CA 2] Center 36 (6~66) winsize 61
5539 19:26:13.612054 [CA 3] Center 35 (5~65) winsize 61
5540 19:26:13.615646 [CA 4] Center 35 (6~65) winsize 60
5541 19:26:13.619046 [CA 5] Center 35 (5~65) winsize 61
5542 19:26:13.619614
5543 19:26:13.621697 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5544 19:26:13.622184
5545 19:26:13.625391 [CATrainingPosCal] consider 2 rank data
5546 19:26:13.628744 u2DelayCellTimex100 = 270/100 ps
5547 19:26:13.632201 CA0 delay=37 (7~68),Diff = 2 PI (12 cell)
5548 19:26:13.635120 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5549 19:26:13.642081 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5550 19:26:13.645271 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5551 19:26:13.648585 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
5552 19:26:13.652121 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5553 19:26:13.652725
5554 19:26:13.655452 CA PerBit enable=1, Macro0, CA PI delay=35
5555 19:26:13.656044
5556 19:26:13.658822 [CBTSetCACLKResult] CA Dly = 35
5557 19:26:13.659415 CS Dly: 7 (0~39)
5558 19:26:13.659906
5559 19:26:13.661945 ----->DramcWriteLeveling(PI) begin...
5560 19:26:13.665505 ==
5561 19:26:13.666086 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 19:26:13.672489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 19:26:13.673084 ==
5564 19:26:13.675607 Write leveling (Byte 0): 26 => 26
5565 19:26:13.678851 Write leveling (Byte 1): 29 => 29
5566 19:26:13.682043 DramcWriteLeveling(PI) end<-----
5567 19:26:13.682592
5568 19:26:13.683186 ==
5569 19:26:13.685950 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 19:26:13.688497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 19:26:13.688993 ==
5572 19:26:13.691653 [Gating] SW mode calibration
5573 19:26:13.698275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5574 19:26:13.705431 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5575 19:26:13.708274 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 19:26:13.711936 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 19:26:13.715000 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 19:26:13.721665 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 19:26:13.724962 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 19:26:13.728731 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 19:26:13.735052 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5582 19:26:13.738149 0 14 28 | B1->B0 | 2828 2424 | 0 0 | (1 0) (1 0)
5583 19:26:13.741606 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 19:26:13.748114 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 19:26:13.751748 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 19:26:13.754817 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 19:26:13.761357 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 19:26:13.764704 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 19:26:13.768093 0 15 24 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
5590 19:26:13.774821 0 15 28 | B1->B0 | 3d3d 4545 | 1 0 | (1 1) (0 0)
5591 19:26:13.777954 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 19:26:13.781689 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 19:26:13.788341 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 19:26:13.791202 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 19:26:13.794769 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 19:26:13.801326 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5597 19:26:13.804787 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5598 19:26:13.807853 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5599 19:26:13.814684 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 19:26:13.818327 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 19:26:13.821455 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 19:26:13.824713 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 19:26:13.831343 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 19:26:13.834724 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 19:26:13.837888 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 19:26:13.844368 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 19:26:13.847807 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 19:26:13.851375 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 19:26:13.857582 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 19:26:13.861150 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 19:26:13.864577 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 19:26:13.871273 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 19:26:13.874174 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5614 19:26:13.878023 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5615 19:26:13.881253 Total UI for P1: 0, mck2ui 16
5616 19:26:13.884445 best dqsien dly found for B0: ( 1, 2, 24)
5617 19:26:13.891081 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 19:26:13.891501 Total UI for P1: 0, mck2ui 16
5619 19:26:13.897803 best dqsien dly found for B1: ( 1, 2, 26)
5620 19:26:13.901056 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5621 19:26:13.904218 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5622 19:26:13.904791
5623 19:26:13.908018 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5624 19:26:13.910853 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5625 19:26:13.914246 [Gating] SW calibration Done
5626 19:26:13.914677 ==
5627 19:26:13.918057 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 19:26:13.921039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 19:26:13.921654 ==
5630 19:26:13.924026 RX Vref Scan: 0
5631 19:26:13.924560
5632 19:26:13.924972 RX Vref 0 -> 0, step: 1
5633 19:26:13.925534
5634 19:26:13.927788 RX Delay -80 -> 252, step: 8
5635 19:26:13.930953 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5636 19:26:13.937559 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5637 19:26:13.941207 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5638 19:26:13.944126 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5639 19:26:13.947420 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5640 19:26:13.950749 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5641 19:26:13.954283 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5642 19:26:13.961325 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5643 19:26:13.964264 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5644 19:26:13.967657 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5645 19:26:13.971204 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5646 19:26:13.974490 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5647 19:26:13.977534 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5648 19:26:13.983926 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5649 19:26:13.987187 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5650 19:26:13.990761 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5651 19:26:13.991184 ==
5652 19:26:13.994059 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 19:26:13.997442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 19:26:13.997868 ==
5655 19:26:14.000614 DQS Delay:
5656 19:26:14.001122 DQS0 = 0, DQS1 = 0
5657 19:26:14.003841 DQM Delay:
5658 19:26:14.004259 DQM0 = 102, DQM1 = 95
5659 19:26:14.004594 DQ Delay:
5660 19:26:14.007449 DQ0 =111, DQ1 =95, DQ2 =91, DQ3 =99
5661 19:26:14.010846 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5662 19:26:14.014069 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5663 19:26:14.020420 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5664 19:26:14.020916
5665 19:26:14.021445
5666 19:26:14.021827 ==
5667 19:26:14.023748 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 19:26:14.027064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 19:26:14.027493 ==
5670 19:26:14.027831
5671 19:26:14.028162
5672 19:26:14.030592 TX Vref Scan disable
5673 19:26:14.031028 == TX Byte 0 ==
5674 19:26:14.037190 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5675 19:26:14.040421 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5676 19:26:14.040848 == TX Byte 1 ==
5677 19:26:14.047112 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5678 19:26:14.050563 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5679 19:26:14.050994 ==
5680 19:26:14.053819 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 19:26:14.057047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 19:26:14.057531 ==
5683 19:26:14.057877
5684 19:26:14.060878
5685 19:26:14.061333 TX Vref Scan disable
5686 19:26:14.063694 == TX Byte 0 ==
5687 19:26:14.067019 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5688 19:26:14.070448 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5689 19:26:14.073834 == TX Byte 1 ==
5690 19:26:14.076873 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5691 19:26:14.080739 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5692 19:26:14.081138
5693 19:26:14.083700 [DATLAT]
5694 19:26:14.084116 Freq=933, CH1 RK0
5695 19:26:14.084455
5696 19:26:14.086973 DATLAT Default: 0xd
5697 19:26:14.087390 0, 0xFFFF, sum = 0
5698 19:26:14.090166 1, 0xFFFF, sum = 0
5699 19:26:14.090590 2, 0xFFFF, sum = 0
5700 19:26:14.093558 3, 0xFFFF, sum = 0
5701 19:26:14.093983 4, 0xFFFF, sum = 0
5702 19:26:14.097276 5, 0xFFFF, sum = 0
5703 19:26:14.097736 6, 0xFFFF, sum = 0
5704 19:26:14.100400 7, 0xFFFF, sum = 0
5705 19:26:14.103575 8, 0xFFFF, sum = 0
5706 19:26:14.104000 9, 0xFFFF, sum = 0
5707 19:26:14.104411 10, 0x0, sum = 1
5708 19:26:14.106841 11, 0x0, sum = 2
5709 19:26:14.107417 12, 0x0, sum = 3
5710 19:26:14.110182 13, 0x0, sum = 4
5711 19:26:14.110667 best_step = 11
5712 19:26:14.111055
5713 19:26:14.111548 ==
5714 19:26:14.113872 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 19:26:14.120237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 19:26:14.120792 ==
5717 19:26:14.121285 RX Vref Scan: 1
5718 19:26:14.121748
5719 19:26:14.123746 RX Vref 0 -> 0, step: 1
5720 19:26:14.124167
5721 19:26:14.127082 RX Delay -53 -> 252, step: 4
5722 19:26:14.127509
5723 19:26:14.130270 Set Vref, RX VrefLevel [Byte0]: 50
5724 19:26:14.133573 [Byte1]: 50
5725 19:26:14.134001
5726 19:26:14.136678 Final RX Vref Byte 0 = 50 to rank0
5727 19:26:14.140072 Final RX Vref Byte 1 = 50 to rank0
5728 19:26:14.143523 Final RX Vref Byte 0 = 50 to rank1
5729 19:26:14.146807 Final RX Vref Byte 1 = 50 to rank1==
5730 19:26:14.150472 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 19:26:14.153800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 19:26:14.154230 ==
5733 19:26:14.156991 DQS Delay:
5734 19:26:14.157551 DQS0 = 0, DQS1 = 0
5735 19:26:14.157903 DQM Delay:
5736 19:26:14.160316 DQM0 = 104, DQM1 = 97
5737 19:26:14.160742 DQ Delay:
5738 19:26:14.163911 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5739 19:26:14.167207 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =100
5740 19:26:14.170631 DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =90
5741 19:26:14.176984 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =104
5742 19:26:14.177599
5743 19:26:14.178137
5744 19:26:14.183562 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5745 19:26:14.186901 CH1 RK0: MR19=505, MR18=1D35
5746 19:26:14.193907 CH1_RK0: MR19=0x505, MR18=0x1D35, DQSOSC=405, MR23=63, INC=66, DEC=44
5747 19:26:14.194487
5748 19:26:14.196988 ----->DramcWriteLeveling(PI) begin...
5749 19:26:14.197596 ==
5750 19:26:14.200652 Dram Type= 6, Freq= 0, CH_1, rank 1
5751 19:26:14.203837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 19:26:14.204325 ==
5753 19:26:14.207167 Write leveling (Byte 0): 26 => 26
5754 19:26:14.210133 Write leveling (Byte 1): 25 => 25
5755 19:26:14.213664 DramcWriteLeveling(PI) end<-----
5756 19:26:14.214145
5757 19:26:14.214623 ==
5758 19:26:14.216966 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 19:26:14.220323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 19:26:14.220841 ==
5761 19:26:14.223603 [Gating] SW mode calibration
5762 19:26:14.230608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5763 19:26:14.236990 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5764 19:26:14.240689 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 19:26:14.244034 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 19:26:14.250311 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 19:26:14.253720 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 19:26:14.257174 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 19:26:14.263786 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 19:26:14.267024 0 14 24 | B1->B0 | 2f2f 3434 | 1 0 | (1 1) (0 0)
5771 19:26:14.270387 0 14 28 | B1->B0 | 2c2c 3030 | 1 1 | (0 0) (1 0)
5772 19:26:14.276977 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5773 19:26:14.280101 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 19:26:14.283280 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 19:26:14.290301 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 19:26:14.293227 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 19:26:14.296754 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 19:26:14.303467 0 15 24 | B1->B0 | 2b2b 2525 | 1 0 | (0 0) (0 0)
5779 19:26:14.307061 0 15 28 | B1->B0 | 4343 3737 | 0 1 | (0 0) (0 0)
5780 19:26:14.310090 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5781 19:26:14.316394 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 19:26:14.320183 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 19:26:14.323429 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 19:26:14.330353 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 19:26:14.333228 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 19:26:14.336691 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5787 19:26:14.343509 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5788 19:26:14.346907 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 19:26:14.349997 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 19:26:14.353201 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 19:26:14.359952 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 19:26:14.363528 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 19:26:14.366911 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 19:26:14.373218 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 19:26:14.376437 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 19:26:14.379803 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 19:26:14.386730 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 19:26:14.389946 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 19:26:14.393528 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 19:26:14.400064 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 19:26:14.403008 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 19:26:14.406337 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5803 19:26:14.413108 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5804 19:26:14.413720 Total UI for P1: 0, mck2ui 16
5805 19:26:14.419800 best dqsien dly found for B1: ( 1, 2, 24)
5806 19:26:14.422991 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 19:26:14.426123 Total UI for P1: 0, mck2ui 16
5808 19:26:14.429484 best dqsien dly found for B0: ( 1, 2, 26)
5809 19:26:14.432702 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5810 19:26:14.436332 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5811 19:26:14.436896
5812 19:26:14.439497 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5813 19:26:14.443202 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5814 19:26:14.446306 [Gating] SW calibration Done
5815 19:26:14.446770 ==
5816 19:26:14.449226 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 19:26:14.453018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 19:26:14.456355 ==
5819 19:26:14.456990 RX Vref Scan: 0
5820 19:26:14.457411
5821 19:26:14.459523 RX Vref 0 -> 0, step: 1
5822 19:26:14.459983
5823 19:26:14.462464 RX Delay -80 -> 252, step: 8
5824 19:26:14.466473 iDelay=200, Bit 0, Center 103 (16 ~ 191) 176
5825 19:26:14.469389 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5826 19:26:14.472782 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5827 19:26:14.476095 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5828 19:26:14.483120 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5829 19:26:14.485656 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5830 19:26:14.489584 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5831 19:26:14.492536 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5832 19:26:14.495673 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5833 19:26:14.499196 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5834 19:26:14.505753 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5835 19:26:14.509543 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5836 19:26:14.512201 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5837 19:26:14.515603 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5838 19:26:14.519137 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5839 19:26:14.525560 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5840 19:26:14.526034 ==
5841 19:26:14.528884 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 19:26:14.532662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 19:26:14.533135 ==
5844 19:26:14.533585 DQS Delay:
5845 19:26:14.535572 DQS0 = 0, DQS1 = 0
5846 19:26:14.536202 DQM Delay:
5847 19:26:14.538962 DQM0 = 102, DQM1 = 95
5848 19:26:14.539501 DQ Delay:
5849 19:26:14.542163 DQ0 =103, DQ1 =99, DQ2 =91, DQ3 =103
5850 19:26:14.545653 DQ4 =103, DQ5 =107, DQ6 =107, DQ7 =103
5851 19:26:14.548824 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =87
5852 19:26:14.552100 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =107
5853 19:26:14.552595
5854 19:26:14.553146
5855 19:26:14.553560 ==
5856 19:26:14.555534 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 19:26:14.562361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 19:26:14.562821 ==
5859 19:26:14.563184
5860 19:26:14.563614
5861 19:26:14.563957 TX Vref Scan disable
5862 19:26:14.565483 == TX Byte 0 ==
5863 19:26:14.569115 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5864 19:26:14.575552 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5865 19:26:14.576140 == TX Byte 1 ==
5866 19:26:14.578913 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5867 19:26:14.585893 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5868 19:26:14.586316 ==
5869 19:26:14.588894 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 19:26:14.592004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 19:26:14.592445 ==
5872 19:26:14.592794
5873 19:26:14.593118
5874 19:26:14.595382 TX Vref Scan disable
5875 19:26:14.595807 == TX Byte 0 ==
5876 19:26:14.602275 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5877 19:26:14.605546 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5878 19:26:14.606148 == TX Byte 1 ==
5879 19:26:14.611975 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5880 19:26:14.615210 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5881 19:26:14.615793
5882 19:26:14.616305 [DATLAT]
5883 19:26:14.618794 Freq=933, CH1 RK1
5884 19:26:14.619396
5885 19:26:14.619949 DATLAT Default: 0xb
5886 19:26:14.621914 0, 0xFFFF, sum = 0
5887 19:26:14.622517 1, 0xFFFF, sum = 0
5888 19:26:14.625578 2, 0xFFFF, sum = 0
5889 19:26:14.626162 3, 0xFFFF, sum = 0
5890 19:26:14.628530 4, 0xFFFF, sum = 0
5891 19:26:14.628961 5, 0xFFFF, sum = 0
5892 19:26:14.632178 6, 0xFFFF, sum = 0
5893 19:26:14.634828 7, 0xFFFF, sum = 0
5894 19:26:14.634912 8, 0xFFFF, sum = 0
5895 19:26:14.638505 9, 0xFFFF, sum = 0
5896 19:26:14.638602 10, 0x0, sum = 1
5897 19:26:14.638695 11, 0x0, sum = 2
5898 19:26:14.641763 12, 0x0, sum = 3
5899 19:26:14.641882 13, 0x0, sum = 4
5900 19:26:14.645162 best_step = 11
5901 19:26:14.645280
5902 19:26:14.645420 ==
5903 19:26:14.648454 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 19:26:14.651594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 19:26:14.651677 ==
5906 19:26:14.655206 RX Vref Scan: 0
5907 19:26:14.655291
5908 19:26:14.655402 RX Vref 0 -> 0, step: 1
5909 19:26:14.655467
5910 19:26:14.658498 RX Delay -61 -> 252, step: 4
5911 19:26:14.665887 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5912 19:26:14.668819 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5913 19:26:14.672506 iDelay=199, Bit 2, Center 96 (19 ~ 174) 156
5914 19:26:14.675360 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5915 19:26:14.678836 iDelay=199, Bit 4, Center 106 (27 ~ 186) 160
5916 19:26:14.685596 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5917 19:26:14.689076 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5918 19:26:14.692212 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5919 19:26:14.695396 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5920 19:26:14.698910 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5921 19:26:14.702434 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5922 19:26:14.708837 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5923 19:26:14.711871 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5924 19:26:14.715255 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5925 19:26:14.718778 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5926 19:26:14.725208 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5927 19:26:14.725291 ==
5928 19:26:14.728958 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 19:26:14.731961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 19:26:14.732045 ==
5931 19:26:14.732112 DQS Delay:
5932 19:26:14.735810 DQS0 = 0, DQS1 = 0
5933 19:26:14.735894 DQM Delay:
5934 19:26:14.738819 DQM0 = 105, DQM1 = 96
5935 19:26:14.738911 DQ Delay:
5936 19:26:14.742161 DQ0 =110, DQ1 =98, DQ2 =96, DQ3 =102
5937 19:26:14.745271 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5938 19:26:14.748694 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =90
5939 19:26:14.751788 DQ12 =106, DQ13 =100, DQ14 =102, DQ15 =106
5940 19:26:14.751870
5941 19:26:14.751935
5942 19:26:14.761639 [DQSOSCAuto] RK1, (LSB)MR18= 0x1ffc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
5943 19:26:14.764952 CH1 RK1: MR19=504, MR18=1FFC
5944 19:26:14.768595 CH1_RK1: MR19=0x504, MR18=0x1FFC, DQSOSC=412, MR23=63, INC=63, DEC=42
5945 19:26:14.771534 [RxdqsGatingPostProcess] freq 933
5946 19:26:14.778101 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5947 19:26:14.781470 best DQS0 dly(2T, 0.5T) = (0, 10)
5948 19:26:14.784647 best DQS1 dly(2T, 0.5T) = (0, 10)
5949 19:26:14.788169 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5950 19:26:14.791598 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5951 19:26:14.794790 best DQS0 dly(2T, 0.5T) = (0, 10)
5952 19:26:14.798478 best DQS1 dly(2T, 0.5T) = (0, 10)
5953 19:26:14.801257 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5954 19:26:14.804788 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5955 19:26:14.804925 Pre-setting of DQS Precalculation
5956 19:26:14.811143 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5957 19:26:14.817878 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5958 19:26:14.824311 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5959 19:26:14.824451
5960 19:26:14.824586
5961 19:26:14.827659 [Calibration Summary] 1866 Mbps
5962 19:26:14.831161 CH 0, Rank 0
5963 19:26:14.831338 SW Impedance : PASS
5964 19:26:14.834691 DUTY Scan : NO K
5965 19:26:14.837819 ZQ Calibration : PASS
5966 19:26:14.838048 Jitter Meter : NO K
5967 19:26:14.840938 CBT Training : PASS
5968 19:26:14.844548 Write leveling : PASS
5969 19:26:14.844868 RX DQS gating : PASS
5970 19:26:14.847901 RX DQ/DQS(RDDQC) : PASS
5971 19:26:14.851612 TX DQ/DQS : PASS
5972 19:26:14.852011 RX DATLAT : PASS
5973 19:26:14.854479 RX DQ/DQS(Engine): PASS
5974 19:26:14.858315 TX OE : NO K
5975 19:26:14.858891 All Pass.
5976 19:26:14.859269
5977 19:26:14.859621 CH 0, Rank 1
5978 19:26:14.861601 SW Impedance : PASS
5979 19:26:14.862158 DUTY Scan : NO K
5980 19:26:14.864504 ZQ Calibration : PASS
5981 19:26:14.868205 Jitter Meter : NO K
5982 19:26:14.868770 CBT Training : PASS
5983 19:26:14.871483 Write leveling : PASS
5984 19:26:14.874442 RX DQS gating : PASS
5985 19:26:14.874916 RX DQ/DQS(RDDQC) : PASS
5986 19:26:14.877872 TX DQ/DQS : PASS
5987 19:26:14.881167 RX DATLAT : PASS
5988 19:26:14.881780 RX DQ/DQS(Engine): PASS
5989 19:26:14.884295 TX OE : NO K
5990 19:26:14.884972 All Pass.
5991 19:26:14.885460
5992 19:26:14.887685 CH 1, Rank 0
5993 19:26:14.888348 SW Impedance : PASS
5994 19:26:14.891023 DUTY Scan : NO K
5995 19:26:14.894465 ZQ Calibration : PASS
5996 19:26:14.894942 Jitter Meter : NO K
5997 19:26:14.898017 CBT Training : PASS
5998 19:26:14.901146 Write leveling : PASS
5999 19:26:14.901677 RX DQS gating : PASS
6000 19:26:14.904369 RX DQ/DQS(RDDQC) : PASS
6001 19:26:14.907849 TX DQ/DQS : PASS
6002 19:26:14.908327 RX DATLAT : PASS
6003 19:26:14.910928 RX DQ/DQS(Engine): PASS
6004 19:26:14.911654 TX OE : NO K
6005 19:26:14.914391 All Pass.
6006 19:26:14.914850
6007 19:26:14.915220 CH 1, Rank 1
6008 19:26:14.917575 SW Impedance : PASS
6009 19:26:14.918053 DUTY Scan : NO K
6010 19:26:14.921096 ZQ Calibration : PASS
6011 19:26:14.924243 Jitter Meter : NO K
6012 19:26:14.924705 CBT Training : PASS
6013 19:26:14.927842 Write leveling : PASS
6014 19:26:14.931207 RX DQS gating : PASS
6015 19:26:14.931770 RX DQ/DQS(RDDQC) : PASS
6016 19:26:14.934306 TX DQ/DQS : PASS
6017 19:26:14.938103 RX DATLAT : PASS
6018 19:26:14.938567 RX DQ/DQS(Engine): PASS
6019 19:26:14.941400 TX OE : NO K
6020 19:26:14.941882 All Pass.
6021 19:26:14.942262
6022 19:26:14.944529 DramC Write-DBI off
6023 19:26:14.947801 PER_BANK_REFRESH: Hybrid Mode
6024 19:26:14.948283 TX_TRACKING: ON
6025 19:26:14.957894 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6026 19:26:14.961073 [FAST_K] Save calibration result to emmc
6027 19:26:14.964433 dramc_set_vcore_voltage set vcore to 650000
6028 19:26:14.967721 Read voltage for 400, 6
6029 19:26:14.967807 Vio18 = 0
6030 19:26:14.967874 Vcore = 650000
6031 19:26:14.970531 Vdram = 0
6032 19:26:14.970614 Vddq = 0
6033 19:26:14.970681 Vmddr = 0
6034 19:26:14.977149 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6035 19:26:14.980643 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6036 19:26:14.983862 MEM_TYPE=3, freq_sel=20
6037 19:26:14.987322 sv_algorithm_assistance_LP4_800
6038 19:26:14.990647 ============ PULL DRAM RESETB DOWN ============
6039 19:26:14.994215 ========== PULL DRAM RESETB DOWN end =========
6040 19:26:15.000291 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6041 19:26:15.004045 ===================================
6042 19:26:15.004147 LPDDR4 DRAM CONFIGURATION
6043 19:26:15.007270 ===================================
6044 19:26:15.010249 EX_ROW_EN[0] = 0x0
6045 19:26:15.013765 EX_ROW_EN[1] = 0x0
6046 19:26:15.013917 LP4Y_EN = 0x0
6047 19:26:15.017170 WORK_FSP = 0x0
6048 19:26:15.017316 WL = 0x2
6049 19:26:15.021034 RL = 0x2
6050 19:26:15.021547 BL = 0x2
6051 19:26:15.024079 RPST = 0x0
6052 19:26:15.024558 RD_PRE = 0x0
6053 19:26:15.027442 WR_PRE = 0x1
6054 19:26:15.027922 WR_PST = 0x0
6055 19:26:15.030589 DBI_WR = 0x0
6056 19:26:15.031102 DBI_RD = 0x0
6057 19:26:15.034203 OTF = 0x1
6058 19:26:15.037417 ===================================
6059 19:26:15.040645 ===================================
6060 19:26:15.041124 ANA top config
6061 19:26:15.044131 ===================================
6062 19:26:15.047724 DLL_ASYNC_EN = 0
6063 19:26:15.050891 ALL_SLAVE_EN = 1
6064 19:26:15.054168 NEW_RANK_MODE = 1
6065 19:26:15.054648 DLL_IDLE_MODE = 1
6066 19:26:15.057605 LP45_APHY_COMB_EN = 1
6067 19:26:15.060938 TX_ODT_DIS = 1
6068 19:26:15.063965 NEW_8X_MODE = 1
6069 19:26:15.067542 ===================================
6070 19:26:15.070929 ===================================
6071 19:26:15.073968 data_rate = 800
6072 19:26:15.074441 CKR = 1
6073 19:26:15.077469 DQ_P2S_RATIO = 4
6074 19:26:15.081157 ===================================
6075 19:26:15.083953 CA_P2S_RATIO = 4
6076 19:26:15.087460 DQ_CA_OPEN = 0
6077 19:26:15.090723 DQ_SEMI_OPEN = 1
6078 19:26:15.091195 CA_SEMI_OPEN = 1
6079 19:26:15.093821 CA_FULL_RATE = 0
6080 19:26:15.097211 DQ_CKDIV4_EN = 0
6081 19:26:15.100358 CA_CKDIV4_EN = 1
6082 19:26:15.103988 CA_PREDIV_EN = 0
6083 19:26:15.107210 PH8_DLY = 0
6084 19:26:15.107684 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6085 19:26:15.110744 DQ_AAMCK_DIV = 0
6086 19:26:15.114238 CA_AAMCK_DIV = 0
6087 19:26:15.117005 CA_ADMCK_DIV = 4
6088 19:26:15.120786 DQ_TRACK_CA_EN = 0
6089 19:26:15.123828 CA_PICK = 800
6090 19:26:15.126880 CA_MCKIO = 400
6091 19:26:15.127353 MCKIO_SEMI = 400
6092 19:26:15.130092 PLL_FREQ = 3016
6093 19:26:15.134024 DQ_UI_PI_RATIO = 32
6094 19:26:15.137173 CA_UI_PI_RATIO = 32
6095 19:26:15.140149 ===================================
6096 19:26:15.143640 ===================================
6097 19:26:15.146727 memory_type:LPDDR4
6098 19:26:15.147196 GP_NUM : 10
6099 19:26:15.150148 SRAM_EN : 1
6100 19:26:15.153665 MD32_EN : 0
6101 19:26:15.156745 ===================================
6102 19:26:15.157219 [ANA_INIT] >>>>>>>>>>>>>>
6103 19:26:15.160168 <<<<<< [CONFIGURE PHASE]: ANA_TX
6104 19:26:15.164034 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6105 19:26:15.167007 ===================================
6106 19:26:15.170311 data_rate = 800,PCW = 0X7400
6107 19:26:15.173612 ===================================
6108 19:26:15.177238 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6109 19:26:15.183734 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6110 19:26:15.193345 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6111 19:26:15.199949 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6112 19:26:15.203553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6113 19:26:15.206738 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6114 19:26:15.207306 [ANA_INIT] flow start
6115 19:26:15.209988 [ANA_INIT] PLL >>>>>>>>
6116 19:26:15.213183 [ANA_INIT] PLL <<<<<<<<
6117 19:26:15.213791 [ANA_INIT] MIDPI >>>>>>>>
6118 19:26:15.216471 [ANA_INIT] MIDPI <<<<<<<<
6119 19:26:15.220016 [ANA_INIT] DLL >>>>>>>>
6120 19:26:15.220487 [ANA_INIT] flow end
6121 19:26:15.227010 ============ LP4 DIFF to SE enter ============
6122 19:26:15.229842 ============ LP4 DIFF to SE exit ============
6123 19:26:15.233092 [ANA_INIT] <<<<<<<<<<<<<
6124 19:26:15.236290 [Flow] Enable top DCM control >>>>>
6125 19:26:15.239649 [Flow] Enable top DCM control <<<<<
6126 19:26:15.240216 Enable DLL master slave shuffle
6127 19:26:15.246522 ==============================================================
6128 19:26:15.249686 Gating Mode config
6129 19:26:15.252928 ==============================================================
6130 19:26:15.256396 Config description:
6131 19:26:15.266393 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6132 19:26:15.273043 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6133 19:26:15.276281 SELPH_MODE 0: By rank 1: By Phase
6134 19:26:15.282787 ==============================================================
6135 19:26:15.286263 GAT_TRACK_EN = 0
6136 19:26:15.289582 RX_GATING_MODE = 2
6137 19:26:15.293247 RX_GATING_TRACK_MODE = 2
6138 19:26:15.296309 SELPH_MODE = 1
6139 19:26:15.296883 PICG_EARLY_EN = 1
6140 19:26:15.299475 VALID_LAT_VALUE = 1
6141 19:26:15.306284 ==============================================================
6142 19:26:15.309633 Enter into Gating configuration >>>>
6143 19:26:15.312889 Exit from Gating configuration <<<<
6144 19:26:15.316275 Enter into DVFS_PRE_config >>>>>
6145 19:26:15.326192 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6146 19:26:15.329463 Exit from DVFS_PRE_config <<<<<
6147 19:26:15.332997 Enter into PICG configuration >>>>
6148 19:26:15.336245 Exit from PICG configuration <<<<
6149 19:26:15.339660 [RX_INPUT] configuration >>>>>
6150 19:26:15.342990 [RX_INPUT] configuration <<<<<
6151 19:26:15.346215 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6152 19:26:15.352704 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6153 19:26:15.359163 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6154 19:26:15.366092 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6155 19:26:15.373135 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6156 19:26:15.375975 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6157 19:26:15.382373 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6158 19:26:15.386151 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6159 19:26:15.389404 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6160 19:26:15.392211 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6161 19:26:15.399358 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6162 19:26:15.402399 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6163 19:26:15.405589 ===================================
6164 19:26:15.409223 LPDDR4 DRAM CONFIGURATION
6165 19:26:15.412645 ===================================
6166 19:26:15.413225 EX_ROW_EN[0] = 0x0
6167 19:26:15.415916 EX_ROW_EN[1] = 0x0
6168 19:26:15.416473 LP4Y_EN = 0x0
6169 19:26:15.419396 WORK_FSP = 0x0
6170 19:26:15.419975 WL = 0x2
6171 19:26:15.422223 RL = 0x2
6172 19:26:15.422694 BL = 0x2
6173 19:26:15.425911 RPST = 0x0
6174 19:26:15.426474 RD_PRE = 0x0
6175 19:26:15.429016 WR_PRE = 0x1
6176 19:26:15.429609 WR_PST = 0x0
6177 19:26:15.432639 DBI_WR = 0x0
6178 19:26:15.435526 DBI_RD = 0x0
6179 19:26:15.436091 OTF = 0x1
6180 19:26:15.438563 ===================================
6181 19:26:15.442414 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6182 19:26:15.445516 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6183 19:26:15.452101 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6184 19:26:15.455122 ===================================
6185 19:26:15.458893 LPDDR4 DRAM CONFIGURATION
6186 19:26:15.461908 ===================================
6187 19:26:15.462384 EX_ROW_EN[0] = 0x10
6188 19:26:15.465626 EX_ROW_EN[1] = 0x0
6189 19:26:15.466182 LP4Y_EN = 0x0
6190 19:26:15.468880 WORK_FSP = 0x0
6191 19:26:15.469466 WL = 0x2
6192 19:26:15.471982 RL = 0x2
6193 19:26:15.472451 BL = 0x2
6194 19:26:15.475433 RPST = 0x0
6195 19:26:15.476032 RD_PRE = 0x0
6196 19:26:15.478467 WR_PRE = 0x1
6197 19:26:15.479217 WR_PST = 0x0
6198 19:26:15.481871 DBI_WR = 0x0
6199 19:26:15.482355 DBI_RD = 0x0
6200 19:26:15.485285 OTF = 0x1
6201 19:26:15.488222 ===================================
6202 19:26:15.495165 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6203 19:26:15.498219 nWR fixed to 30
6204 19:26:15.501681 [ModeRegInit_LP4] CH0 RK0
6205 19:26:15.502152 [ModeRegInit_LP4] CH0 RK1
6206 19:26:15.504664 [ModeRegInit_LP4] CH1 RK0
6207 19:26:15.508580 [ModeRegInit_LP4] CH1 RK1
6208 19:26:15.509062 match AC timing 19
6209 19:26:15.514922 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6210 19:26:15.518359 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6211 19:26:15.522030 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6212 19:26:15.528641 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6213 19:26:15.531692 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6214 19:26:15.532269 ==
6215 19:26:15.535096 Dram Type= 6, Freq= 0, CH_0, rank 0
6216 19:26:15.538297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6217 19:26:15.538800 ==
6218 19:26:15.544906 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6219 19:26:15.551938 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6220 19:26:15.555207 [CA 0] Center 36 (8~64) winsize 57
6221 19:26:15.558564 [CA 1] Center 36 (8~64) winsize 57
6222 19:26:15.559051 [CA 2] Center 36 (8~64) winsize 57
6223 19:26:15.561587 [CA 3] Center 36 (8~64) winsize 57
6224 19:26:15.565161 [CA 4] Center 36 (8~64) winsize 57
6225 19:26:15.568232 [CA 5] Center 36 (8~64) winsize 57
6226 19:26:15.568714
6227 19:26:15.571833 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6228 19:26:15.574914
6229 19:26:15.578650 [CATrainingPosCal] consider 1 rank data
6230 19:26:15.579205 u2DelayCellTimex100 = 270/100 ps
6231 19:26:15.584952 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 19:26:15.588372 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 19:26:15.591750 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 19:26:15.594970 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 19:26:15.598465 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 19:26:15.601386 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 19:26:15.601856
6238 19:26:15.604639 CA PerBit enable=1, Macro0, CA PI delay=36
6239 19:26:15.605109
6240 19:26:15.608815 [CBTSetCACLKResult] CA Dly = 36
6241 19:26:15.611453 CS Dly: 1 (0~32)
6242 19:26:15.612007 ==
6243 19:26:15.614620 Dram Type= 6, Freq= 0, CH_0, rank 1
6244 19:26:15.618344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 19:26:15.618836 ==
6246 19:26:15.624940 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6247 19:26:15.628025 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6248 19:26:15.631333 [CA 0] Center 36 (8~64) winsize 57
6249 19:26:15.634496 [CA 1] Center 36 (8~64) winsize 57
6250 19:26:15.637920 [CA 2] Center 36 (8~64) winsize 57
6251 19:26:15.641256 [CA 3] Center 36 (8~64) winsize 57
6252 19:26:15.644671 [CA 4] Center 36 (8~64) winsize 57
6253 19:26:15.648196 [CA 5] Center 36 (8~64) winsize 57
6254 19:26:15.648747
6255 19:26:15.651430 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6256 19:26:15.651912
6257 19:26:15.654447 [CATrainingPosCal] consider 2 rank data
6258 19:26:15.658271 u2DelayCellTimex100 = 270/100 ps
6259 19:26:15.661083 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 19:26:15.664660 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 19:26:15.667964 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 19:26:15.674667 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 19:26:15.677871 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 19:26:15.681253 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 19:26:15.681862
6266 19:26:15.685034 CA PerBit enable=1, Macro0, CA PI delay=36
6267 19:26:15.685670
6268 19:26:15.688054 [CBTSetCACLKResult] CA Dly = 36
6269 19:26:15.688539 CS Dly: 1 (0~32)
6270 19:26:15.689025
6271 19:26:15.691281 ----->DramcWriteLeveling(PI) begin...
6272 19:26:15.691770 ==
6273 19:26:15.694583 Dram Type= 6, Freq= 0, CH_0, rank 0
6274 19:26:15.701695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 19:26:15.702278 ==
6276 19:26:15.704760 Write leveling (Byte 0): 40 => 8
6277 19:26:15.708002 Write leveling (Byte 1): 32 => 0
6278 19:26:15.708578 DramcWriteLeveling(PI) end<-----
6279 19:26:15.709070
6280 19:26:15.711373 ==
6281 19:26:15.714476 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 19:26:15.717714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 19:26:15.718205 ==
6284 19:26:15.721267 [Gating] SW mode calibration
6285 19:26:15.727870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6286 19:26:15.731610 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6287 19:26:15.738201 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 19:26:15.740918 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6289 19:26:15.744357 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 19:26:15.750982 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6291 19:26:15.754273 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 19:26:15.757649 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 19:26:15.764191 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 19:26:15.767648 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 19:26:15.770803 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 19:26:15.774542 Total UI for P1: 0, mck2ui 16
6297 19:26:15.777575 best dqsien dly found for B0: ( 0, 14, 24)
6298 19:26:15.780867 Total UI for P1: 0, mck2ui 16
6299 19:26:15.783984 best dqsien dly found for B1: ( 0, 14, 24)
6300 19:26:15.787381 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6301 19:26:15.790801 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6302 19:26:15.791122
6303 19:26:15.797573 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6304 19:26:15.800695 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6305 19:26:15.801118 [Gating] SW calibration Done
6306 19:26:15.804531 ==
6307 19:26:15.804879 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 19:26:15.811005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 19:26:15.811520 ==
6310 19:26:15.811851 RX Vref Scan: 0
6311 19:26:15.812156
6312 19:26:15.814267 RX Vref 0 -> 0, step: 1
6313 19:26:15.814722
6314 19:26:15.817460 RX Delay -410 -> 252, step: 16
6315 19:26:15.820782 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6316 19:26:15.823953 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6317 19:26:15.830775 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6318 19:26:15.834736 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6319 19:26:15.837708 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6320 19:26:15.840791 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6321 19:26:15.847701 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6322 19:26:15.850987 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6323 19:26:15.854161 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6324 19:26:15.857751 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6325 19:26:15.864295 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6326 19:26:15.867543 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6327 19:26:15.871048 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6328 19:26:15.874127 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6329 19:26:15.880922 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6330 19:26:15.883911 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6331 19:26:15.884369 ==
6332 19:26:15.887465 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 19:26:15.890406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 19:26:15.890864 ==
6335 19:26:15.893747 DQS Delay:
6336 19:26:15.894204 DQS0 = 27, DQS1 = 43
6337 19:26:15.897212 DQM Delay:
6338 19:26:15.897828 DQM0 = 12, DQM1 = 13
6339 19:26:15.898197 DQ Delay:
6340 19:26:15.900846 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6341 19:26:15.904095 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6342 19:26:15.907211 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6343 19:26:15.910477 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6344 19:26:15.911037
6345 19:26:15.911403
6346 19:26:15.911739 ==
6347 19:26:15.913898 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 19:26:15.920412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 19:26:15.920877 ==
6350 19:26:15.921242
6351 19:26:15.921656
6352 19:26:15.921987 TX Vref Scan disable
6353 19:26:15.923904 == TX Byte 0 ==
6354 19:26:15.927090 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 19:26:15.930345 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 19:26:15.933480 == TX Byte 1 ==
6357 19:26:15.937177 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6358 19:26:15.940461 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6359 19:26:15.943281 ==
6360 19:26:15.943740 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 19:26:15.950699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 19:26:15.951261 ==
6363 19:26:15.951627
6364 19:26:15.951960
6365 19:26:15.953603 TX Vref Scan disable
6366 19:26:15.954058 == TX Byte 0 ==
6367 19:26:15.956683 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 19:26:15.963478 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 19:26:15.964027 == TX Byte 1 ==
6370 19:26:15.967000 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6371 19:26:15.973649 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6372 19:26:15.974214
6373 19:26:15.974574 [DATLAT]
6374 19:26:15.974911 Freq=400, CH0 RK0
6375 19:26:15.975232
6376 19:26:15.976862 DATLAT Default: 0xf
6377 19:26:15.977454 0, 0xFFFF, sum = 0
6378 19:26:15.980345 1, 0xFFFF, sum = 0
6379 19:26:15.980965 2, 0xFFFF, sum = 0
6380 19:26:15.983650 3, 0xFFFF, sum = 0
6381 19:26:15.984209 4, 0xFFFF, sum = 0
6382 19:26:15.986973 5, 0xFFFF, sum = 0
6383 19:26:15.990375 6, 0xFFFF, sum = 0
6384 19:26:15.990944 7, 0xFFFF, sum = 0
6385 19:26:15.993386 8, 0xFFFF, sum = 0
6386 19:26:15.993868 9, 0xFFFF, sum = 0
6387 19:26:15.997118 10, 0xFFFF, sum = 0
6388 19:26:15.997721 11, 0xFFFF, sum = 0
6389 19:26:15.999973 12, 0xFFFF, sum = 0
6390 19:26:16.000482 13, 0x0, sum = 1
6391 19:26:16.003445 14, 0x0, sum = 2
6392 19:26:16.004016 15, 0x0, sum = 3
6393 19:26:16.006849 16, 0x0, sum = 4
6394 19:26:16.007319 best_step = 14
6395 19:26:16.007760
6396 19:26:16.008103 ==
6397 19:26:16.009951 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 19:26:16.013265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 19:26:16.013771 ==
6400 19:26:16.016868 RX Vref Scan: 1
6401 19:26:16.017538
6402 19:26:16.020287 RX Vref 0 -> 0, step: 1
6403 19:26:16.020753
6404 19:26:16.021124 RX Delay -327 -> 252, step: 8
6405 19:26:16.023447
6406 19:26:16.023907 Set Vref, RX VrefLevel [Byte0]: 62
6407 19:26:16.026509 [Byte1]: 50
6408 19:26:16.032457
6409 19:26:16.032921 Final RX Vref Byte 0 = 62 to rank0
6410 19:26:16.035709 Final RX Vref Byte 1 = 50 to rank0
6411 19:26:16.039311 Final RX Vref Byte 0 = 62 to rank1
6412 19:26:16.042189 Final RX Vref Byte 1 = 50 to rank1==
6413 19:26:16.045757 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 19:26:16.052348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 19:26:16.052920 ==
6416 19:26:16.053332 DQS Delay:
6417 19:26:16.055472 DQS0 = 28, DQS1 = 48
6418 19:26:16.056057 DQM Delay:
6419 19:26:16.056438 DQM0 = 11, DQM1 = 14
6420 19:26:16.058836 DQ Delay:
6421 19:26:16.061858 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6422 19:26:16.065395 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6423 19:26:16.065968 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6424 19:26:16.068883 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6425 19:26:16.072131
6426 19:26:16.072698
6427 19:26:16.078524 [DQSOSCAuto] RK0, (LSB)MR18= 0xafa7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6428 19:26:16.081759 CH0 RK0: MR19=C0C, MR18=AFA7
6429 19:26:16.089352 CH0_RK0: MR19=0xC0C, MR18=0xAFA7, DQSOSC=388, MR23=63, INC=392, DEC=261
6430 19:26:16.090015 ==
6431 19:26:16.091797 Dram Type= 6, Freq= 0, CH_0, rank 1
6432 19:26:16.094922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 19:26:16.095393 ==
6434 19:26:16.098224 [Gating] SW mode calibration
6435 19:26:16.104867 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6436 19:26:16.111572 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6437 19:26:16.115348 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 19:26:16.118170 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6439 19:26:16.125332 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 19:26:16.128421 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 19:26:16.131653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 19:26:16.138668 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 19:26:16.141414 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 19:26:16.144760 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 19:26:16.151197 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 19:26:16.151760 Total UI for P1: 0, mck2ui 16
6447 19:26:16.154487 best dqsien dly found for B0: ( 0, 14, 24)
6448 19:26:16.158062 Total UI for P1: 0, mck2ui 16
6449 19:26:16.161661 best dqsien dly found for B1: ( 0, 14, 24)
6450 19:26:16.167972 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6451 19:26:16.171493 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6452 19:26:16.172070
6453 19:26:16.174387 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6454 19:26:16.178126 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6455 19:26:16.181420 [Gating] SW calibration Done
6456 19:26:16.182000 ==
6457 19:26:16.184781 Dram Type= 6, Freq= 0, CH_0, rank 1
6458 19:26:16.187956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 19:26:16.188429 ==
6460 19:26:16.190890 RX Vref Scan: 0
6461 19:26:16.191360
6462 19:26:16.191735 RX Vref 0 -> 0, step: 1
6463 19:26:16.192084
6464 19:26:16.194218 RX Delay -410 -> 252, step: 16
6465 19:26:16.201068 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6466 19:26:16.204551 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6467 19:26:16.207968 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6468 19:26:16.211022 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6469 19:26:16.214507 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6470 19:26:16.221433 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6471 19:26:16.224562 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6472 19:26:16.228216 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6473 19:26:16.231072 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6474 19:26:16.238066 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6475 19:26:16.241255 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6476 19:26:16.244411 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6477 19:26:16.251067 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6478 19:26:16.254474 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6479 19:26:16.257704 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6480 19:26:16.261082 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6481 19:26:16.261691 ==
6482 19:26:16.264636 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 19:26:16.271162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 19:26:16.271723 ==
6485 19:26:16.272105 DQS Delay:
6486 19:26:16.274621 DQS0 = 27, DQS1 = 43
6487 19:26:16.275088 DQM Delay:
6488 19:26:16.275487 DQM0 = 9, DQM1 = 15
6489 19:26:16.277978 DQ Delay:
6490 19:26:16.281366 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6491 19:26:16.281929 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6492 19:26:16.284705 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6493 19:26:16.287400 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6494 19:26:16.287895
6495 19:26:16.290651
6496 19:26:16.291117 ==
6497 19:26:16.294217 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 19:26:16.297696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 19:26:16.298260 ==
6500 19:26:16.298637
6501 19:26:16.298986
6502 19:26:16.300684 TX Vref Scan disable
6503 19:26:16.301155 == TX Byte 0 ==
6504 19:26:16.304079 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6505 19:26:16.310935 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6506 19:26:16.311482 == TX Byte 1 ==
6507 19:26:16.314114 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6508 19:26:16.320974 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6509 19:26:16.321590 ==
6510 19:26:16.324382 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 19:26:16.327604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 19:26:16.328178 ==
6513 19:26:16.328564
6514 19:26:16.328918
6515 19:26:16.331015 TX Vref Scan disable
6516 19:26:16.331571 == TX Byte 0 ==
6517 19:26:16.333861 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6518 19:26:16.340865 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6519 19:26:16.341470 == TX Byte 1 ==
6520 19:26:16.344556 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6521 19:26:16.350701 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6522 19:26:16.351267
6523 19:26:16.351649 [DATLAT]
6524 19:26:16.352003 Freq=400, CH0 RK1
6525 19:26:16.352347
6526 19:26:16.353738 DATLAT Default: 0xe
6527 19:26:16.357775 0, 0xFFFF, sum = 0
6528 19:26:16.358339 1, 0xFFFF, sum = 0
6529 19:26:16.360642 2, 0xFFFF, sum = 0
6530 19:26:16.361120 3, 0xFFFF, sum = 0
6531 19:26:16.364470 4, 0xFFFF, sum = 0
6532 19:26:16.365033 5, 0xFFFF, sum = 0
6533 19:26:16.367891 6, 0xFFFF, sum = 0
6534 19:26:16.368457 7, 0xFFFF, sum = 0
6535 19:26:16.370637 8, 0xFFFF, sum = 0
6536 19:26:16.371204 9, 0xFFFF, sum = 0
6537 19:26:16.374182 10, 0xFFFF, sum = 0
6538 19:26:16.374769 11, 0xFFFF, sum = 0
6539 19:26:16.377660 12, 0xFFFF, sum = 0
6540 19:26:16.378242 13, 0x0, sum = 1
6541 19:26:16.380723 14, 0x0, sum = 2
6542 19:26:16.381288 15, 0x0, sum = 3
6543 19:26:16.383973 16, 0x0, sum = 4
6544 19:26:16.384451 best_step = 14
6545 19:26:16.384824
6546 19:26:16.385175 ==
6547 19:26:16.387146 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 19:26:16.390465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 19:26:16.393919 ==
6550 19:26:16.394388 RX Vref Scan: 0
6551 19:26:16.394763
6552 19:26:16.397538 RX Vref 0 -> 0, step: 1
6553 19:26:16.398099
6554 19:26:16.400562 RX Delay -327 -> 252, step: 8
6555 19:26:16.404037 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6556 19:26:16.411011 iDelay=217, Bit 1, Center -20 (-247 ~ 208) 456
6557 19:26:16.413851 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6558 19:26:16.417148 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6559 19:26:16.420135 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6560 19:26:16.427256 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6561 19:26:16.430071 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6562 19:26:16.433655 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6563 19:26:16.437136 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6564 19:26:16.443505 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6565 19:26:16.446753 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6566 19:26:16.450469 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6567 19:26:16.456592 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6568 19:26:16.460371 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6569 19:26:16.463597 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6570 19:26:16.466704 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6571 19:26:16.467268 ==
6572 19:26:16.470433 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 19:26:16.476703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 19:26:16.477267 ==
6575 19:26:16.477688 DQS Delay:
6576 19:26:16.480349 DQS0 = 28, DQS1 = 44
6577 19:26:16.480904 DQM Delay:
6578 19:26:16.481282 DQM0 = 8, DQM1 = 15
6579 19:26:16.483447 DQ Delay:
6580 19:26:16.486634 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6581 19:26:16.490483 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6582 19:26:16.491046 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6583 19:26:16.493455 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =20
6584 19:26:16.497114
6585 19:26:16.497715
6586 19:26:16.503615 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6587 19:26:16.507066 CH0 RK1: MR19=C0C, MR18=BB6E
6588 19:26:16.513336 CH0_RK1: MR19=0xC0C, MR18=0xBB6E, DQSOSC=386, MR23=63, INC=396, DEC=264
6589 19:26:16.516951 [RxdqsGatingPostProcess] freq 400
6590 19:26:16.519892 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6591 19:26:16.523532 best DQS0 dly(2T, 0.5T) = (0, 10)
6592 19:26:16.526567 best DQS1 dly(2T, 0.5T) = (0, 10)
6593 19:26:16.530235 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6594 19:26:16.533733 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6595 19:26:16.536700 best DQS0 dly(2T, 0.5T) = (0, 10)
6596 19:26:16.539898 best DQS1 dly(2T, 0.5T) = (0, 10)
6597 19:26:16.543325 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6598 19:26:16.546953 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6599 19:26:16.549804 Pre-setting of DQS Precalculation
6600 19:26:16.553202 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6601 19:26:16.553839 ==
6602 19:26:16.556466 Dram Type= 6, Freq= 0, CH_1, rank 0
6603 19:26:16.563590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6604 19:26:16.564156 ==
6605 19:26:16.566310 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6606 19:26:16.573191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6607 19:26:16.576759 [CA 0] Center 36 (8~64) winsize 57
6608 19:26:16.579838 [CA 1] Center 36 (8~64) winsize 57
6609 19:26:16.583011 [CA 2] Center 36 (8~64) winsize 57
6610 19:26:16.586628 [CA 3] Center 36 (8~64) winsize 57
6611 19:26:16.589739 [CA 4] Center 36 (8~64) winsize 57
6612 19:26:16.592748 [CA 5] Center 36 (8~64) winsize 57
6613 19:26:16.593213
6614 19:26:16.596305 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6615 19:26:16.596879
6616 19:26:16.599297 [CATrainingPosCal] consider 1 rank data
6617 19:26:16.602900 u2DelayCellTimex100 = 270/100 ps
6618 19:26:16.606000 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 19:26:16.609459 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 19:26:16.612902 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 19:26:16.615934 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 19:26:16.619669 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 19:26:16.622801 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 19:26:16.623269
6625 19:26:16.629378 CA PerBit enable=1, Macro0, CA PI delay=36
6626 19:26:16.629843
6627 19:26:16.630215 [CBTSetCACLKResult] CA Dly = 36
6628 19:26:16.632939 CS Dly: 1 (0~32)
6629 19:26:16.633563 ==
6630 19:26:16.636462 Dram Type= 6, Freq= 0, CH_1, rank 1
6631 19:26:16.639361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 19:26:16.639938 ==
6633 19:26:16.646007 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6634 19:26:16.652925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6635 19:26:16.656027 [CA 0] Center 36 (8~64) winsize 57
6636 19:26:16.659465 [CA 1] Center 36 (8~64) winsize 57
6637 19:26:16.662657 [CA 2] Center 36 (8~64) winsize 57
6638 19:26:16.665938 [CA 3] Center 36 (8~64) winsize 57
6639 19:26:16.666508 [CA 4] Center 36 (8~64) winsize 57
6640 19:26:16.669649 [CA 5] Center 36 (8~64) winsize 57
6641 19:26:16.670221
6642 19:26:16.675992 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6643 19:26:16.676573
6644 19:26:16.679313 [CATrainingPosCal] consider 2 rank data
6645 19:26:16.682984 u2DelayCellTimex100 = 270/100 ps
6646 19:26:16.686027 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 19:26:16.689587 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 19:26:16.692480 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 19:26:16.696273 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 19:26:16.698991 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 19:26:16.702549 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 19:26:16.703124
6653 19:26:16.705789 CA PerBit enable=1, Macro0, CA PI delay=36
6654 19:26:16.706366
6655 19:26:16.709193 [CBTSetCACLKResult] CA Dly = 36
6656 19:26:16.712566 CS Dly: 1 (0~32)
6657 19:26:16.713139
6658 19:26:16.715681 ----->DramcWriteLeveling(PI) begin...
6659 19:26:16.716304 ==
6660 19:26:16.719087 Dram Type= 6, Freq= 0, CH_1, rank 0
6661 19:26:16.721873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 19:26:16.722352 ==
6663 19:26:16.725351 Write leveling (Byte 0): 40 => 8
6664 19:26:16.728668 Write leveling (Byte 1): 32 => 0
6665 19:26:16.731998 DramcWriteLeveling(PI) end<-----
6666 19:26:16.732466
6667 19:26:16.732842 ==
6668 19:26:16.735895 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 19:26:16.739090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 19:26:16.739661 ==
6671 19:26:16.742215 [Gating] SW mode calibration
6672 19:26:16.748716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6673 19:26:16.755502 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6674 19:26:16.758403 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6675 19:26:16.765686 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6676 19:26:16.768794 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 19:26:16.771575 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6678 19:26:16.775132 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 19:26:16.782182 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 19:26:16.785176 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 19:26:16.791791 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 19:26:16.794778 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 19:26:16.798743 Total UI for P1: 0, mck2ui 16
6684 19:26:16.801554 best dqsien dly found for B0: ( 0, 14, 24)
6685 19:26:16.804744 Total UI for P1: 0, mck2ui 16
6686 19:26:16.808520 best dqsien dly found for B1: ( 0, 14, 24)
6687 19:26:16.811913 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6688 19:26:16.814882 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6689 19:26:16.815350
6690 19:26:16.818398 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6691 19:26:16.821977 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6692 19:26:16.825070 [Gating] SW calibration Done
6693 19:26:16.825666 ==
6694 19:26:16.827957 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 19:26:16.831798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 19:26:16.832364 ==
6697 19:26:16.834713 RX Vref Scan: 0
6698 19:26:16.835172
6699 19:26:16.838165 RX Vref 0 -> 0, step: 1
6700 19:26:16.838627
6701 19:26:16.838998 RX Delay -410 -> 252, step: 16
6702 19:26:16.844960 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6703 19:26:16.847860 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6704 19:26:16.851136 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6705 19:26:16.854716 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6706 19:26:16.861588 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6707 19:26:16.864803 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6708 19:26:16.867999 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6709 19:26:16.871619 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6710 19:26:16.877848 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6711 19:26:16.881040 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6712 19:26:16.884398 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6713 19:26:16.887829 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6714 19:26:16.894578 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6715 19:26:16.898051 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6716 19:26:16.901184 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6717 19:26:16.907855 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6718 19:26:16.908275 ==
6719 19:26:16.911349 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 19:26:16.914821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 19:26:16.915243 ==
6722 19:26:16.915581 DQS Delay:
6723 19:26:16.917767 DQS0 = 27, DQS1 = 43
6724 19:26:16.918186 DQM Delay:
6725 19:26:16.921401 DQM0 = 5, DQM1 = 14
6726 19:26:16.921822 DQ Delay:
6727 19:26:16.924456 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6728 19:26:16.927727 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6729 19:26:16.930998 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6730 19:26:16.934538 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6731 19:26:16.935092
6732 19:26:16.935580
6733 19:26:16.936064 ==
6734 19:26:16.937937 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 19:26:16.940978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 19:26:16.941493 ==
6737 19:26:16.941836
6738 19:26:16.942151
6739 19:26:16.944335 TX Vref Scan disable
6740 19:26:16.944767 == TX Byte 0 ==
6741 19:26:16.950925 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 19:26:16.954338 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 19:26:16.954813 == TX Byte 1 ==
6744 19:26:16.960880 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6745 19:26:16.964557 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6746 19:26:16.965114 ==
6747 19:26:16.967637 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 19:26:16.970934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 19:26:16.971402 ==
6750 19:26:16.971779
6751 19:26:16.972302
6752 19:26:16.974225 TX Vref Scan disable
6753 19:26:16.977692 == TX Byte 0 ==
6754 19:26:16.981137 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 19:26:16.984342 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 19:26:16.984783 == TX Byte 1 ==
6757 19:26:16.991011 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6758 19:26:16.994124 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6759 19:26:16.994667
6760 19:26:16.995026 [DATLAT]
6761 19:26:16.997987 Freq=400, CH1 RK0
6762 19:26:16.998496
6763 19:26:16.998877 DATLAT Default: 0xf
6764 19:26:17.001253 0, 0xFFFF, sum = 0
6765 19:26:17.001701 1, 0xFFFF, sum = 0
6766 19:26:17.004460 2, 0xFFFF, sum = 0
6767 19:26:17.004849 3, 0xFFFF, sum = 0
6768 19:26:17.007656 4, 0xFFFF, sum = 0
6769 19:26:17.010798 5, 0xFFFF, sum = 0
6770 19:26:17.011243 6, 0xFFFF, sum = 0
6771 19:26:17.013981 7, 0xFFFF, sum = 0
6772 19:26:17.014442 8, 0xFFFF, sum = 0
6773 19:26:17.017562 9, 0xFFFF, sum = 0
6774 19:26:17.018132 10, 0xFFFF, sum = 0
6775 19:26:17.020780 11, 0xFFFF, sum = 0
6776 19:26:17.021234 12, 0xFFFF, sum = 0
6777 19:26:17.024078 13, 0x0, sum = 1
6778 19:26:17.024528 14, 0x0, sum = 2
6779 19:26:17.027569 15, 0x0, sum = 3
6780 19:26:17.028045 16, 0x0, sum = 4
6781 19:26:17.028557 best_step = 14
6782 19:26:17.031058
6783 19:26:17.031500 ==
6784 19:26:17.034458 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 19:26:17.037381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 19:26:17.037882 ==
6787 19:26:17.038252 RX Vref Scan: 1
6788 19:26:17.038720
6789 19:26:17.041046 RX Vref 0 -> 0, step: 1
6790 19:26:17.041526
6791 19:26:17.044361 RX Delay -327 -> 252, step: 8
6792 19:26:17.044802
6793 19:26:17.047347 Set Vref, RX VrefLevel [Byte0]: 50
6794 19:26:17.050965 [Byte1]: 50
6795 19:26:17.054592
6796 19:26:17.055024 Final RX Vref Byte 0 = 50 to rank0
6797 19:26:17.057781 Final RX Vref Byte 1 = 50 to rank0
6798 19:26:17.061191 Final RX Vref Byte 0 = 50 to rank1
6799 19:26:17.064412 Final RX Vref Byte 1 = 50 to rank1==
6800 19:26:17.067809 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 19:26:17.074604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 19:26:17.075056 ==
6803 19:26:17.075432 DQS Delay:
6804 19:26:17.078055 DQS0 = 32, DQS1 = 40
6805 19:26:17.078497 DQM Delay:
6806 19:26:17.078858 DQM0 = 11, DQM1 = 13
6807 19:26:17.081043 DQ Delay:
6808 19:26:17.084615 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6809 19:26:17.085053 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6810 19:26:17.087751 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6811 19:26:17.091013 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6812 19:26:17.091572
6813 19:26:17.094339
6814 19:26:17.100920 [DQSOSCAuto] RK0, (LSB)MR18= 0x92cd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6815 19:26:17.104309 CH1 RK0: MR19=C0C, MR18=92CD
6816 19:26:17.110945 CH1_RK0: MR19=0xC0C, MR18=0x92CD, DQSOSC=384, MR23=63, INC=400, DEC=267
6817 19:26:17.111406 ==
6818 19:26:17.114502 Dram Type= 6, Freq= 0, CH_1, rank 1
6819 19:26:17.117825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 19:26:17.118263 ==
6821 19:26:17.121325 [Gating] SW mode calibration
6822 19:26:17.127764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6823 19:26:17.131120 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6824 19:26:17.137736 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6825 19:26:17.141267 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6826 19:26:17.144714 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 19:26:17.151188 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6828 19:26:17.154099 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 19:26:17.157750 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 19:26:17.164353 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 19:26:17.167368 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 19:26:17.171088 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 19:26:17.174044 Total UI for P1: 0, mck2ui 16
6834 19:26:17.177503 best dqsien dly found for B0: ( 0, 14, 24)
6835 19:26:17.180829 Total UI for P1: 0, mck2ui 16
6836 19:26:17.183827 best dqsien dly found for B1: ( 0, 14, 24)
6837 19:26:17.187057 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6838 19:26:17.193811 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6839 19:26:17.194254
6840 19:26:17.196951 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6841 19:26:17.200578 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6842 19:26:17.203906 [Gating] SW calibration Done
6843 19:26:17.204358 ==
6844 19:26:17.207360 Dram Type= 6, Freq= 0, CH_1, rank 1
6845 19:26:17.210866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 19:26:17.211325 ==
6847 19:26:17.213945 RX Vref Scan: 0
6848 19:26:17.214386
6849 19:26:17.214729 RX Vref 0 -> 0, step: 1
6850 19:26:17.215073
6851 19:26:17.217107 RX Delay -410 -> 252, step: 16
6852 19:26:17.220533 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6853 19:26:17.227068 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6854 19:26:17.230528 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6855 19:26:17.234012 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6856 19:26:17.237272 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6857 19:26:17.243656 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6858 19:26:17.247232 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6859 19:26:17.250416 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6860 19:26:17.253860 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6861 19:26:17.260663 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6862 19:26:17.263614 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6863 19:26:17.267121 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6864 19:26:17.270405 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6865 19:26:17.276550 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6866 19:26:17.279985 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6867 19:26:17.283410 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6868 19:26:17.283839 ==
6869 19:26:17.286598 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 19:26:17.293674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 19:26:17.294145 ==
6872 19:26:17.294504 DQS Delay:
6873 19:26:17.296368 DQS0 = 35, DQS1 = 43
6874 19:26:17.296747 DQM Delay:
6875 19:26:17.297084 DQM0 = 18, DQM1 = 20
6876 19:26:17.299901 DQ Delay:
6877 19:26:17.303390 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6878 19:26:17.306693 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6879 19:26:17.310046 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6880 19:26:17.313371 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6881 19:26:17.313926
6882 19:26:17.314296
6883 19:26:17.314638 ==
6884 19:26:17.316159 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 19:26:17.319607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 19:26:17.320058 ==
6887 19:26:17.320426
6888 19:26:17.320771
6889 19:26:17.322922 TX Vref Scan disable
6890 19:26:17.323370 == TX Byte 0 ==
6891 19:26:17.329493 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6892 19:26:17.332825 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6893 19:26:17.333271 == TX Byte 1 ==
6894 19:26:17.339235 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6895 19:26:17.342929 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6896 19:26:17.343375 ==
6897 19:26:17.346223 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 19:26:17.349494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 19:26:17.349998 ==
6900 19:26:17.350380
6901 19:26:17.350740
6902 19:26:17.353014 TX Vref Scan disable
6903 19:26:17.353538 == TX Byte 0 ==
6904 19:26:17.359363 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6905 19:26:17.362453 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6906 19:26:17.362905 == TX Byte 1 ==
6907 19:26:17.369476 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6908 19:26:17.372500 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6909 19:26:17.372943
6910 19:26:17.373336 [DATLAT]
6911 19:26:17.375999 Freq=400, CH1 RK1
6912 19:26:17.376460
6913 19:26:17.376825 DATLAT Default: 0xe
6914 19:26:17.379770 0, 0xFFFF, sum = 0
6915 19:26:17.380232 1, 0xFFFF, sum = 0
6916 19:26:17.382333 2, 0xFFFF, sum = 0
6917 19:26:17.382831 3, 0xFFFF, sum = 0
6918 19:26:17.385918 4, 0xFFFF, sum = 0
6919 19:26:17.386374 5, 0xFFFF, sum = 0
6920 19:26:17.389389 6, 0xFFFF, sum = 0
6921 19:26:17.389846 7, 0xFFFF, sum = 0
6922 19:26:17.392442 8, 0xFFFF, sum = 0
6923 19:26:17.392967 9, 0xFFFF, sum = 0
6924 19:26:17.395838 10, 0xFFFF, sum = 0
6925 19:26:17.399152 11, 0xFFFF, sum = 0
6926 19:26:17.399620 12, 0xFFFF, sum = 0
6927 19:26:17.402443 13, 0x0, sum = 1
6928 19:26:17.402935 14, 0x0, sum = 2
6929 19:26:17.403306 15, 0x0, sum = 3
6930 19:26:17.406379 16, 0x0, sum = 4
6931 19:26:17.406827 best_step = 14
6932 19:26:17.407190
6933 19:26:17.407534 ==
6934 19:26:17.409020 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 19:26:17.416207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 19:26:17.416697 ==
6937 19:26:17.417094 RX Vref Scan: 0
6938 19:26:17.417521
6939 19:26:17.419357 RX Vref 0 -> 0, step: 1
6940 19:26:17.419801
6941 19:26:17.422856 RX Delay -327 -> 252, step: 8
6942 19:26:17.429411 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6943 19:26:17.432824 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6944 19:26:17.435946 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6945 19:26:17.439268 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6946 19:26:17.445967 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6947 19:26:17.449113 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6948 19:26:17.452342 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6949 19:26:17.455906 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6950 19:26:17.462156 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6951 19:26:17.465652 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6952 19:26:17.469350 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6953 19:26:17.472018 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6954 19:26:17.479157 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6955 19:26:17.482413 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6956 19:26:17.485937 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6957 19:26:17.492161 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6958 19:26:17.492589 ==
6959 19:26:17.495392 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 19:26:17.498847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 19:26:17.499276 ==
6962 19:26:17.499617 DQS Delay:
6963 19:26:17.502267 DQS0 = 32, DQS1 = 36
6964 19:26:17.502692 DQM Delay:
6965 19:26:17.505388 DQM0 = 12, DQM1 = 11
6966 19:26:17.505815 DQ Delay:
6967 19:26:17.508982 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6968 19:26:17.512409 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =12
6969 19:26:17.515348 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6970 19:26:17.518782 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6971 19:26:17.519209
6972 19:26:17.519548
6973 19:26:17.525352 [DQSOSCAuto] RK1, (LSB)MR18= 0xa34c, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
6974 19:26:17.528894 CH1 RK1: MR19=C0C, MR18=A34C
6975 19:26:17.535398 CH1_RK1: MR19=0xC0C, MR18=0xA34C, DQSOSC=389, MR23=63, INC=390, DEC=260
6976 19:26:17.538750 [RxdqsGatingPostProcess] freq 400
6977 19:26:17.545259 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6978 19:26:17.548450 best DQS0 dly(2T, 0.5T) = (0, 10)
6979 19:26:17.548850 best DQS1 dly(2T, 0.5T) = (0, 10)
6980 19:26:17.551930 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6981 19:26:17.555486 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6982 19:26:17.558982 best DQS0 dly(2T, 0.5T) = (0, 10)
6983 19:26:17.561893 best DQS1 dly(2T, 0.5T) = (0, 10)
6984 19:26:17.565362 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6985 19:26:17.568782 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6986 19:26:17.571902 Pre-setting of DQS Precalculation
6987 19:26:17.578447 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6988 19:26:17.585053 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6989 19:26:17.592022 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6990 19:26:17.592563
6991 19:26:17.592937
6992 19:26:17.595244 [Calibration Summary] 800 Mbps
6993 19:26:17.595692 CH 0, Rank 0
6994 19:26:17.598539 SW Impedance : PASS
6995 19:26:17.601715 DUTY Scan : NO K
6996 19:26:17.602180 ZQ Calibration : PASS
6997 19:26:17.605067 Jitter Meter : NO K
6998 19:26:17.605572 CBT Training : PASS
6999 19:26:17.608157 Write leveling : PASS
7000 19:26:17.611848 RX DQS gating : PASS
7001 19:26:17.612372 RX DQ/DQS(RDDQC) : PASS
7002 19:26:17.615327 TX DQ/DQS : PASS
7003 19:26:17.618308 RX DATLAT : PASS
7004 19:26:17.618815 RX DQ/DQS(Engine): PASS
7005 19:26:17.621603 TX OE : NO K
7006 19:26:17.622067 All Pass.
7007 19:26:17.622436
7008 19:26:17.624849 CH 0, Rank 1
7009 19:26:17.625352 SW Impedance : PASS
7010 19:26:17.628326 DUTY Scan : NO K
7011 19:26:17.631820 ZQ Calibration : PASS
7012 19:26:17.632242 Jitter Meter : NO K
7013 19:26:17.634965 CBT Training : PASS
7014 19:26:17.638244 Write leveling : NO K
7015 19:26:17.638667 RX DQS gating : PASS
7016 19:26:17.641396 RX DQ/DQS(RDDQC) : PASS
7017 19:26:17.644833 TX DQ/DQS : PASS
7018 19:26:17.645286 RX DATLAT : PASS
7019 19:26:17.647905 RX DQ/DQS(Engine): PASS
7020 19:26:17.651283 TX OE : NO K
7021 19:26:17.651728 All Pass.
7022 19:26:17.652063
7023 19:26:17.652373 CH 1, Rank 0
7024 19:26:17.654623 SW Impedance : PASS
7025 19:26:17.658220 DUTY Scan : NO K
7026 19:26:17.658670 ZQ Calibration : PASS
7027 19:26:17.661362 Jitter Meter : NO K
7028 19:26:17.661780 CBT Training : PASS
7029 19:26:17.664733 Write leveling : PASS
7030 19:26:17.668029 RX DQS gating : PASS
7031 19:26:17.668457 RX DQ/DQS(RDDQC) : PASS
7032 19:26:17.671347 TX DQ/DQS : PASS
7033 19:26:17.674892 RX DATLAT : PASS
7034 19:26:17.675360 RX DQ/DQS(Engine): PASS
7035 19:26:17.678187 TX OE : NO K
7036 19:26:17.678612 All Pass.
7037 19:26:17.678949
7038 19:26:17.681442 CH 1, Rank 1
7039 19:26:17.681861 SW Impedance : PASS
7040 19:26:17.684869 DUTY Scan : NO K
7041 19:26:17.687933 ZQ Calibration : PASS
7042 19:26:17.688355 Jitter Meter : NO K
7043 19:26:17.691419 CBT Training : PASS
7044 19:26:17.694824 Write leveling : NO K
7045 19:26:17.695244 RX DQS gating : PASS
7046 19:26:17.697805 RX DQ/DQS(RDDQC) : PASS
7047 19:26:17.701328 TX DQ/DQS : PASS
7048 19:26:17.701749 RX DATLAT : PASS
7049 19:26:17.704568 RX DQ/DQS(Engine): PASS
7050 19:26:17.704987 TX OE : NO K
7051 19:26:17.708394 All Pass.
7052 19:26:17.708812
7053 19:26:17.709195 DramC Write-DBI off
7054 19:26:17.711257 PER_BANK_REFRESH: Hybrid Mode
7055 19:26:17.714563 TX_TRACKING: ON
7056 19:26:17.721433 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7057 19:26:17.724212 [FAST_K] Save calibration result to emmc
7058 19:26:17.730899 dramc_set_vcore_voltage set vcore to 725000
7059 19:26:17.731327 Read voltage for 1600, 0
7060 19:26:17.734329 Vio18 = 0
7061 19:26:17.734750 Vcore = 725000
7062 19:26:17.735094 Vdram = 0
7063 19:26:17.735410 Vddq = 0
7064 19:26:17.737786 Vmddr = 0
7065 19:26:17.741294 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7066 19:26:17.747591 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7067 19:26:17.751329 MEM_TYPE=3, freq_sel=13
7068 19:26:17.751753 sv_algorithm_assistance_LP4_3733
7069 19:26:17.757635 ============ PULL DRAM RESETB DOWN ============
7070 19:26:17.760817 ========== PULL DRAM RESETB DOWN end =========
7071 19:26:17.764347 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7072 19:26:17.767344 ===================================
7073 19:26:17.770739 LPDDR4 DRAM CONFIGURATION
7074 19:26:17.774371 ===================================
7075 19:26:17.777434 EX_ROW_EN[0] = 0x0
7076 19:26:17.777878 EX_ROW_EN[1] = 0x0
7077 19:26:17.780788 LP4Y_EN = 0x0
7078 19:26:17.781211 WORK_FSP = 0x1
7079 19:26:17.784287 WL = 0x5
7080 19:26:17.784713 RL = 0x5
7081 19:26:17.787694 BL = 0x2
7082 19:26:17.788118 RPST = 0x0
7083 19:26:17.790949 RD_PRE = 0x0
7084 19:26:17.791446 WR_PRE = 0x1
7085 19:26:17.793998 WR_PST = 0x1
7086 19:26:17.794419 DBI_WR = 0x0
7087 19:26:17.797279 DBI_RD = 0x0
7088 19:26:17.800913 OTF = 0x1
7089 19:26:17.801380 ===================================
7090 19:26:17.803870 ===================================
7091 19:26:17.807593 ANA top config
7092 19:26:17.810795 ===================================
7093 19:26:17.814029 DLL_ASYNC_EN = 0
7094 19:26:17.814596 ALL_SLAVE_EN = 0
7095 19:26:17.817312 NEW_RANK_MODE = 1
7096 19:26:17.820585 DLL_IDLE_MODE = 1
7097 19:26:17.824071 LP45_APHY_COMB_EN = 1
7098 19:26:17.827444 TX_ODT_DIS = 0
7099 19:26:17.827885 NEW_8X_MODE = 1
7100 19:26:17.830840 ===================================
7101 19:26:17.833954 ===================================
7102 19:26:17.837109 data_rate = 3200
7103 19:26:17.840355 CKR = 1
7104 19:26:17.844070 DQ_P2S_RATIO = 8
7105 19:26:17.847436 ===================================
7106 19:26:17.850890 CA_P2S_RATIO = 8
7107 19:26:17.851312 DQ_CA_OPEN = 0
7108 19:26:17.854065 DQ_SEMI_OPEN = 0
7109 19:26:17.857200 CA_SEMI_OPEN = 0
7110 19:26:17.860453 CA_FULL_RATE = 0
7111 19:26:17.864082 DQ_CKDIV4_EN = 0
7112 19:26:17.867334 CA_CKDIV4_EN = 0
7113 19:26:17.867757 CA_PREDIV_EN = 0
7114 19:26:17.870829 PH8_DLY = 12
7115 19:26:17.874046 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7116 19:26:17.877395 DQ_AAMCK_DIV = 4
7117 19:26:17.880530 CA_AAMCK_DIV = 4
7118 19:26:17.883954 CA_ADMCK_DIV = 4
7119 19:26:17.884373 DQ_TRACK_CA_EN = 0
7120 19:26:17.887127 CA_PICK = 1600
7121 19:26:17.890385 CA_MCKIO = 1600
7122 19:26:17.894154 MCKIO_SEMI = 0
7123 19:26:17.897459 PLL_FREQ = 3068
7124 19:26:17.900649 DQ_UI_PI_RATIO = 32
7125 19:26:17.903980 CA_UI_PI_RATIO = 0
7126 19:26:17.907087 ===================================
7127 19:26:17.910480 ===================================
7128 19:26:17.910905 memory_type:LPDDR4
7129 19:26:17.913598 GP_NUM : 10
7130 19:26:17.916829 SRAM_EN : 1
7131 19:26:17.917229 MD32_EN : 0
7132 19:26:17.920516 ===================================
7133 19:26:17.923663 [ANA_INIT] >>>>>>>>>>>>>>
7134 19:26:17.926804 <<<<<< [CONFIGURE PHASE]: ANA_TX
7135 19:26:17.930258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7136 19:26:17.933631 ===================================
7137 19:26:17.936848 data_rate = 3200,PCW = 0X7600
7138 19:26:17.940361 ===================================
7139 19:26:17.943635 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7140 19:26:17.946839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7141 19:26:17.953154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7142 19:26:17.956849 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7143 19:26:17.960263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7144 19:26:17.966548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7145 19:26:17.967083 [ANA_INIT] flow start
7146 19:26:17.970228 [ANA_INIT] PLL >>>>>>>>
7147 19:26:17.970673 [ANA_INIT] PLL <<<<<<<<
7148 19:26:17.973810 [ANA_INIT] MIDPI >>>>>>>>
7149 19:26:17.976698 [ANA_INIT] MIDPI <<<<<<<<
7150 19:26:17.980014 [ANA_INIT] DLL >>>>>>>>
7151 19:26:17.980442 [ANA_INIT] DLL <<<<<<<<
7152 19:26:17.983228 [ANA_INIT] flow end
7153 19:26:17.986447 ============ LP4 DIFF to SE enter ============
7154 19:26:17.990006 ============ LP4 DIFF to SE exit ============
7155 19:26:17.993643 [ANA_INIT] <<<<<<<<<<<<<
7156 19:26:17.996862 [Flow] Enable top DCM control >>>>>
7157 19:26:17.999973 [Flow] Enable top DCM control <<<<<
7158 19:26:18.003307 Enable DLL master slave shuffle
7159 19:26:18.009884 ==============================================================
7160 19:26:18.010285 Gating Mode config
7161 19:26:18.016441 ==============================================================
7162 19:26:18.016829 Config description:
7163 19:26:18.026361 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7164 19:26:18.033273 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7165 19:26:18.040010 SELPH_MODE 0: By rank 1: By Phase
7166 19:26:18.043097 ==============================================================
7167 19:26:18.046510 GAT_TRACK_EN = 1
7168 19:26:18.049769 RX_GATING_MODE = 2
7169 19:26:18.052810 RX_GATING_TRACK_MODE = 2
7170 19:26:18.056498 SELPH_MODE = 1
7171 19:26:18.059779 PICG_EARLY_EN = 1
7172 19:26:18.062798 VALID_LAT_VALUE = 1
7173 19:26:18.069418 ==============================================================
7174 19:26:18.072914 Enter into Gating configuration >>>>
7175 19:26:18.076419 Exit from Gating configuration <<<<
7176 19:26:18.076850 Enter into DVFS_PRE_config >>>>>
7177 19:26:18.089718 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7178 19:26:18.093049 Exit from DVFS_PRE_config <<<<<
7179 19:26:18.096370 Enter into PICG configuration >>>>
7180 19:26:18.099452 Exit from PICG configuration <<<<
7181 19:26:18.099896 [RX_INPUT] configuration >>>>>
7182 19:26:18.103014 [RX_INPUT] configuration <<<<<
7183 19:26:18.109741 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7184 19:26:18.112957 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7185 19:26:18.119604 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7186 19:26:18.125987 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7187 19:26:18.132795 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7188 19:26:18.139387 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7189 19:26:18.142582 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7190 19:26:18.146058 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7191 19:26:18.152545 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7192 19:26:18.156484 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7193 19:26:18.159006 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7194 19:26:18.162508 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7195 19:26:18.165763 ===================================
7196 19:26:18.169218 LPDDR4 DRAM CONFIGURATION
7197 19:26:18.172465 ===================================
7198 19:26:18.175802 EX_ROW_EN[0] = 0x0
7199 19:26:18.176171 EX_ROW_EN[1] = 0x0
7200 19:26:18.178988 LP4Y_EN = 0x0
7201 19:26:18.179353 WORK_FSP = 0x1
7202 19:26:18.182809 WL = 0x5
7203 19:26:18.183173 RL = 0x5
7204 19:26:18.185650 BL = 0x2
7205 19:26:18.186009 RPST = 0x0
7206 19:26:18.189112 RD_PRE = 0x0
7207 19:26:18.189501 WR_PRE = 0x1
7208 19:26:18.192509 WR_PST = 0x1
7209 19:26:18.195555 DBI_WR = 0x0
7210 19:26:18.195924 DBI_RD = 0x0
7211 19:26:18.198980 OTF = 0x1
7212 19:26:18.202431 ===================================
7213 19:26:18.205846 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7214 19:26:18.209000 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7215 19:26:18.212161 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7216 19:26:18.215343 ===================================
7217 19:26:18.218996 LPDDR4 DRAM CONFIGURATION
7218 19:26:18.222310 ===================================
7219 19:26:18.225838 EX_ROW_EN[0] = 0x10
7220 19:26:18.226212 EX_ROW_EN[1] = 0x0
7221 19:26:18.228986 LP4Y_EN = 0x0
7222 19:26:18.229554 WORK_FSP = 0x1
7223 19:26:18.232640 WL = 0x5
7224 19:26:18.233028 RL = 0x5
7225 19:26:18.235602 BL = 0x2
7226 19:26:18.235966 RPST = 0x0
7227 19:26:18.238751 RD_PRE = 0x0
7228 19:26:18.239123 WR_PRE = 0x1
7229 19:26:18.241889 WR_PST = 0x1
7230 19:26:18.242263 DBI_WR = 0x0
7231 19:26:18.245743 DBI_RD = 0x0
7232 19:26:18.246129 OTF = 0x1
7233 19:26:18.248901 ===================================
7234 19:26:18.255535 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7235 19:26:18.255925 ==
7236 19:26:18.258793 Dram Type= 6, Freq= 0, CH_0, rank 0
7237 19:26:18.265199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7238 19:26:18.265682 ==
7239 19:26:18.266023 [Duty_Offset_Calibration]
7240 19:26:18.268558 B0:2 B1:0 CA:1
7241 19:26:18.268925
7242 19:26:18.271875 [DutyScan_Calibration_Flow] k_type=0
7243 19:26:18.280820
7244 19:26:18.281290 ==CLK 0==
7245 19:26:18.283861 Final CLK duty delay cell = -4
7246 19:26:18.287270 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7247 19:26:18.290639 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7248 19:26:18.293583 [-4] AVG Duty = 4922%(X100)
7249 19:26:18.293987
7250 19:26:18.297251 CH0 CLK Duty spec in!! Max-Min= 218%
7251 19:26:18.300619 [DutyScan_Calibration_Flow] ====Done====
7252 19:26:18.301039
7253 19:26:18.303858 [DutyScan_Calibration_Flow] k_type=1
7254 19:26:18.320423
7255 19:26:18.320868 ==DQS 0 ==
7256 19:26:18.323297 Final DQS duty delay cell = 0
7257 19:26:18.326685 [0] MAX Duty = 5249%(X100), DQS PI = 32
7258 19:26:18.330075 [0] MIN Duty = 4969%(X100), DQS PI = 0
7259 19:26:18.330526 [0] AVG Duty = 5109%(X100)
7260 19:26:18.333769
7261 19:26:18.334234 ==DQS 1 ==
7262 19:26:18.337181 Final DQS duty delay cell = -4
7263 19:26:18.339985 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7264 19:26:18.343405 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7265 19:26:18.347091 [-4] AVG Duty = 4984%(X100)
7266 19:26:18.347545
7267 19:26:18.350118 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7268 19:26:18.350514
7269 19:26:18.353330 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7270 19:26:18.356798 [DutyScan_Calibration_Flow] ====Done====
7271 19:26:18.357170
7272 19:26:18.359929 [DutyScan_Calibration_Flow] k_type=3
7273 19:26:18.377412
7274 19:26:18.377814 ==DQM 0 ==
7275 19:26:18.380656 Final DQM duty delay cell = 0
7276 19:26:18.383782 [0] MAX Duty = 5093%(X100), DQS PI = 26
7277 19:26:18.387117 [0] MIN Duty = 4813%(X100), DQS PI = 50
7278 19:26:18.390812 [0] AVG Duty = 4953%(X100)
7279 19:26:18.391193
7280 19:26:18.391533 ==DQM 1 ==
7281 19:26:18.394056 Final DQM duty delay cell = 0
7282 19:26:18.397335 [0] MAX Duty = 5249%(X100), DQS PI = 30
7283 19:26:18.400484 [0] MIN Duty = 5031%(X100), DQS PI = 6
7284 19:26:18.403819 [0] AVG Duty = 5140%(X100)
7285 19:26:18.404235
7286 19:26:18.407079 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7287 19:26:18.407489
7288 19:26:18.410158 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7289 19:26:18.413535 [DutyScan_Calibration_Flow] ====Done====
7290 19:26:18.413617
7291 19:26:18.416851 [DutyScan_Calibration_Flow] k_type=2
7292 19:26:18.434476
7293 19:26:18.434568 ==DQ 0 ==
7294 19:26:18.437502 Final DQ duty delay cell = 0
7295 19:26:18.441153 [0] MAX Duty = 5124%(X100), DQS PI = 34
7296 19:26:18.444221 [0] MIN Duty = 5000%(X100), DQS PI = 16
7297 19:26:18.444302 [0] AVG Duty = 5062%(X100)
7298 19:26:18.444374
7299 19:26:18.447584 ==DQ 1 ==
7300 19:26:18.451233 Final DQ duty delay cell = 0
7301 19:26:18.454218 [0] MAX Duty = 4969%(X100), DQS PI = 42
7302 19:26:18.457616 [0] MIN Duty = 4875%(X100), DQS PI = 10
7303 19:26:18.457697 [0] AVG Duty = 4922%(X100)
7304 19:26:18.457761
7305 19:26:18.460795 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7306 19:26:18.464087
7307 19:26:18.467520 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7308 19:26:18.470560 [DutyScan_Calibration_Flow] ====Done====
7309 19:26:18.470640 ==
7310 19:26:18.473933 Dram Type= 6, Freq= 0, CH_1, rank 0
7311 19:26:18.477123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7312 19:26:18.477232 ==
7313 19:26:18.480954 [Duty_Offset_Calibration]
7314 19:26:18.481035 B0:0 B1:-1 CA:2
7315 19:26:18.481099
7316 19:26:18.483904 [DutyScan_Calibration_Flow] k_type=0
7317 19:26:18.494251
7318 19:26:18.494326 ==CLK 0==
7319 19:26:18.497970 Final CLK duty delay cell = 0
7320 19:26:18.501243 [0] MAX Duty = 5156%(X100), DQS PI = 10
7321 19:26:18.504479 [0] MIN Duty = 4906%(X100), DQS PI = 46
7322 19:26:18.504559 [0] AVG Duty = 5031%(X100)
7323 19:26:18.507680
7324 19:26:18.511049 CH1 CLK Duty spec in!! Max-Min= 250%
7325 19:26:18.514580 [DutyScan_Calibration_Flow] ====Done====
7326 19:26:18.514661
7327 19:26:18.518024 [DutyScan_Calibration_Flow] k_type=1
7328 19:26:18.534396
7329 19:26:18.534477 ==DQS 0 ==
7330 19:26:18.537543 Final DQS duty delay cell = 0
7331 19:26:18.540849 [0] MAX Duty = 5062%(X100), DQS PI = 24
7332 19:26:18.544082 [0] MIN Duty = 4969%(X100), DQS PI = 0
7333 19:26:18.544163 [0] AVG Duty = 5015%(X100)
7334 19:26:18.547661
7335 19:26:18.547741 ==DQS 1 ==
7336 19:26:18.550958 Final DQS duty delay cell = 0
7337 19:26:18.554184 [0] MAX Duty = 5187%(X100), DQS PI = 0
7338 19:26:18.557538 [0] MIN Duty = 4844%(X100), DQS PI = 34
7339 19:26:18.557645 [0] AVG Duty = 5015%(X100)
7340 19:26:18.560776
7341 19:26:18.563982 CH1 DQS 0 Duty spec in!! Max-Min= 93%
7342 19:26:18.564062
7343 19:26:18.567390 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7344 19:26:18.570935 [DutyScan_Calibration_Flow] ====Done====
7345 19:26:18.571016
7346 19:26:18.573940 [DutyScan_Calibration_Flow] k_type=3
7347 19:26:18.591854
7348 19:26:18.591934 ==DQM 0 ==
7349 19:26:18.595136 Final DQM duty delay cell = 4
7350 19:26:18.598319 [4] MAX Duty = 5125%(X100), DQS PI = 22
7351 19:26:18.601821 [4] MIN Duty = 4969%(X100), DQS PI = 46
7352 19:26:18.601902 [4] AVG Duty = 5047%(X100)
7353 19:26:18.605334
7354 19:26:18.605427 ==DQM 1 ==
7355 19:26:18.608284 Final DQM duty delay cell = 0
7356 19:26:18.611578 [0] MAX Duty = 5281%(X100), DQS PI = 58
7357 19:26:18.614769 [0] MIN Duty = 4844%(X100), DQS PI = 34
7358 19:26:18.618357 [0] AVG Duty = 5062%(X100)
7359 19:26:18.618461
7360 19:26:18.621691 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7361 19:26:18.621772
7362 19:26:18.625211 CH1 DQM 1 Duty spec in!! Max-Min= 437%
7363 19:26:18.628316 [DutyScan_Calibration_Flow] ====Done====
7364 19:26:18.628397
7365 19:26:18.631372 [DutyScan_Calibration_Flow] k_type=2
7366 19:26:18.648458
7367 19:26:18.648538 ==DQ 0 ==
7368 19:26:18.651780 Final DQ duty delay cell = 0
7369 19:26:18.655186 [0] MAX Duty = 5062%(X100), DQS PI = 20
7370 19:26:18.658583 [0] MIN Duty = 4969%(X100), DQS PI = 0
7371 19:26:18.658664 [0] AVG Duty = 5015%(X100)
7372 19:26:18.658728
7373 19:26:18.661706 ==DQ 1 ==
7374 19:26:18.665165 Final DQ duty delay cell = 0
7375 19:26:18.668424 [0] MAX Duty = 5062%(X100), DQS PI = 0
7376 19:26:18.671690 [0] MIN Duty = 4813%(X100), DQS PI = 34
7377 19:26:18.671771 [0] AVG Duty = 4937%(X100)
7378 19:26:18.671836
7379 19:26:18.675240 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7380 19:26:18.675321
7381 19:26:18.678521 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7382 19:26:18.684987 [DutyScan_Calibration_Flow] ====Done====
7383 19:26:18.688368 nWR fixed to 30
7384 19:26:18.688449 [ModeRegInit_LP4] CH0 RK0
7385 19:26:18.691630 [ModeRegInit_LP4] CH0 RK1
7386 19:26:18.694841 [ModeRegInit_LP4] CH1 RK0
7387 19:26:18.694922 [ModeRegInit_LP4] CH1 RK1
7388 19:26:18.698445 match AC timing 5
7389 19:26:18.701659 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7390 19:26:18.705018 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7391 19:26:18.711476 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7392 19:26:18.714846 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7393 19:26:18.721590 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7394 19:26:18.721671 [MiockJmeterHQA]
7395 19:26:18.721734
7396 19:26:18.724872 [DramcMiockJmeter] u1RxGatingPI = 0
7397 19:26:18.728202 0 : 4255, 4029
7398 19:26:18.728284 4 : 4257, 4030
7399 19:26:18.728350 8 : 4252, 4027
7400 19:26:18.731567 12 : 4257, 4029
7401 19:26:18.731649 16 : 4255, 4027
7402 19:26:18.734874 20 : 4363, 4137
7403 19:26:18.734956 24 : 4252, 4027
7404 19:26:18.738030 28 : 4252, 4027
7405 19:26:18.738112 32 : 4252, 4027
7406 19:26:18.741355 36 : 4255, 4029
7407 19:26:18.741436 40 : 4252, 4026
7408 19:26:18.741501 44 : 4252, 4027
7409 19:26:18.744603 48 : 4252, 4026
7410 19:26:18.744684 52 : 4252, 4027
7411 19:26:18.747947 56 : 4253, 4027
7412 19:26:18.748030 60 : 4252, 4026
7413 19:26:18.751520 64 : 4252, 4027
7414 19:26:18.751601 68 : 4249, 4027
7415 19:26:18.754390 72 : 4363, 4140
7416 19:26:18.754472 76 : 4363, 4140
7417 19:26:18.754537 80 : 4250, 4027
7418 19:26:18.758151 84 : 4250, 4027
7419 19:26:18.758232 88 : 4250, 3501
7420 19:26:18.761285 92 : 4250, 0
7421 19:26:18.761408 96 : 4361, 0
7422 19:26:18.761476 100 : 4252, 0
7423 19:26:18.764403 104 : 4255, 0
7424 19:26:18.764487 108 : 4361, 0
7425 19:26:18.767982 112 : 4250, 0
7426 19:26:18.768108 116 : 4249, 0
7427 19:26:18.768176 120 : 4250, 0
7428 19:26:18.771145 124 : 4361, 0
7429 19:26:18.771229 128 : 4363, 0
7430 19:26:18.774250 132 : 4253, 0
7431 19:26:18.774335 136 : 4250, 0
7432 19:26:18.774402 140 : 4255, 0
7433 19:26:18.777538 144 : 4250, 0
7434 19:26:18.777622 148 : 4250, 0
7435 19:26:18.777689 152 : 4255, 0
7436 19:26:18.781069 156 : 4255, 0
7437 19:26:18.781153 160 : 4360, 0
7438 19:26:18.784534 164 : 4250, 0
7439 19:26:18.784618 168 : 4250, 0
7440 19:26:18.784685 172 : 4250, 0
7441 19:26:18.787658 176 : 4250, 0
7442 19:26:18.787742 180 : 4362, 0
7443 19:26:18.790919 184 : 4250, 0
7444 19:26:18.791002 188 : 4360, 0
7445 19:26:18.791069 192 : 4250, 0
7446 19:26:18.794152 196 : 4250, 0
7447 19:26:18.794236 200 : 4250, 60
7448 19:26:18.797740 204 : 4363, 3274
7449 19:26:18.797824 208 : 4360, 4138
7450 19:26:18.801159 212 : 4250, 4027
7451 19:26:18.801244 216 : 4250, 4027
7452 19:26:18.804281 220 : 4253, 4029
7453 19:26:18.804365 224 : 4250, 4026
7454 19:26:18.804433 228 : 4250, 4027
7455 19:26:18.807416 232 : 4250, 4027
7456 19:26:18.807499 236 : 4253, 4029
7457 19:26:18.810876 240 : 4250, 4027
7458 19:26:18.810960 244 : 4361, 4137
7459 19:26:18.814198 248 : 4361, 4138
7460 19:26:18.814282 252 : 4250, 4027
7461 19:26:18.817561 256 : 4250, 4027
7462 19:26:18.817644 260 : 4250, 4026
7463 19:26:18.820974 264 : 4255, 4030
7464 19:26:18.821058 268 : 4250, 4027
7465 19:26:18.824211 272 : 4366, 4142
7466 19:26:18.824295 276 : 4250, 4026
7467 19:26:18.827497 280 : 4250, 4027
7468 19:26:18.827580 284 : 4250, 4027
7469 19:26:18.827647 288 : 4255, 4032
7470 19:26:18.831127 292 : 4250, 4027
7471 19:26:18.831211 296 : 4366, 4140
7472 19:26:18.834138 300 : 4360, 4138
7473 19:26:18.834222 304 : 4250, 4027
7474 19:26:18.837557 308 : 4363, 4140
7475 19:26:18.837641 312 : 4255, 3807
7476 19:26:18.840893 316 : 4250, 1720
7477 19:26:18.840977
7478 19:26:18.841043 MIOCK jitter meter ch=0
7479 19:26:18.844195
7480 19:26:18.844278 1T = (316-92) = 224 dly cells
7481 19:26:18.850522 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7482 19:26:18.850606 ==
7483 19:26:18.853962 Dram Type= 6, Freq= 0, CH_0, rank 0
7484 19:26:18.857525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7485 19:26:18.857609 ==
7486 19:26:18.864280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7487 19:26:18.867505 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7488 19:26:18.873827 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7489 19:26:18.877161 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7490 19:26:18.887547 [CA 0] Center 42 (12~73) winsize 62
7491 19:26:18.890505 [CA 1] Center 42 (12~72) winsize 61
7492 19:26:18.893926 [CA 2] Center 37 (7~67) winsize 61
7493 19:26:18.897464 [CA 3] Center 37 (7~67) winsize 61
7494 19:26:18.900691 [CA 4] Center 36 (6~66) winsize 61
7495 19:26:18.904069 [CA 5] Center 35 (5~65) winsize 61
7496 19:26:18.904152
7497 19:26:18.907436 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7498 19:26:18.907521
7499 19:26:18.910870 [CATrainingPosCal] consider 1 rank data
7500 19:26:18.914362 u2DelayCellTimex100 = 290/100 ps
7501 19:26:18.917016 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7502 19:26:18.924067 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7503 19:26:18.927358 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7504 19:26:18.930406 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7505 19:26:18.934144 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7506 19:26:18.937046 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7507 19:26:18.937129
7508 19:26:18.940888 CA PerBit enable=1, Macro0, CA PI delay=35
7509 19:26:18.940970
7510 19:26:18.943892 [CBTSetCACLKResult] CA Dly = 35
7511 19:26:18.946926 CS Dly: 9 (0~40)
7512 19:26:18.950607 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7513 19:26:18.953861 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7514 19:26:18.953944 ==
7515 19:26:18.957079 Dram Type= 6, Freq= 0, CH_0, rank 1
7516 19:26:18.960323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7517 19:26:18.960407 ==
7518 19:26:18.967208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7519 19:26:18.970348 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7520 19:26:18.977131 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7521 19:26:18.980239 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7522 19:26:18.990258 [CA 0] Center 43 (13~73) winsize 61
7523 19:26:18.993707 [CA 1] Center 43 (13~73) winsize 61
7524 19:26:18.997082 [CA 2] Center 38 (8~68) winsize 61
7525 19:26:19.000613 [CA 3] Center 38 (8~68) winsize 61
7526 19:26:19.003680 [CA 4] Center 36 (6~66) winsize 61
7527 19:26:19.007146 [CA 5] Center 36 (6~66) winsize 61
7528 19:26:19.007229
7529 19:26:19.010420 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7530 19:26:19.010503
7531 19:26:19.014205 [CATrainingPosCal] consider 2 rank data
7532 19:26:19.017327 u2DelayCellTimex100 = 290/100 ps
7533 19:26:19.020623 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7534 19:26:19.027147 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7535 19:26:19.030457 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7536 19:26:19.033746 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7537 19:26:19.037464 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7538 19:26:19.040578 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7539 19:26:19.040661
7540 19:26:19.043836 CA PerBit enable=1, Macro0, CA PI delay=35
7541 19:26:19.043919
7542 19:26:19.047025 [CBTSetCACLKResult] CA Dly = 35
7543 19:26:19.050556 CS Dly: 10 (0~43)
7544 19:26:19.053637 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7545 19:26:19.057127 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7546 19:26:19.057209
7547 19:26:19.060513 ----->DramcWriteLeveling(PI) begin...
7548 19:26:19.060600 ==
7549 19:26:19.063846 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 19:26:19.067008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 19:26:19.070344 ==
7552 19:26:19.070426 Write leveling (Byte 0): 38 => 38
7553 19:26:19.073719 Write leveling (Byte 1): 29 => 29
7554 19:26:19.076949 DramcWriteLeveling(PI) end<-----
7555 19:26:19.077032
7556 19:26:19.077097 ==
7557 19:26:19.080079 Dram Type= 6, Freq= 0, CH_0, rank 0
7558 19:26:19.086970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 19:26:19.087054 ==
7560 19:26:19.087120 [Gating] SW mode calibration
7561 19:26:19.096817 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7562 19:26:19.100063 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7563 19:26:19.106757 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 19:26:19.110342 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 19:26:19.113331 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7566 19:26:19.116920 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7567 19:26:19.123408 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7568 19:26:19.126775 1 4 20 | B1->B0 | 3130 3434 | 1 1 | (1 1) (1 1)
7569 19:26:19.130133 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 19:26:19.137041 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 19:26:19.140319 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 19:26:19.143592 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 19:26:19.150418 1 5 8 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7574 19:26:19.153703 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7575 19:26:19.157136 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7576 19:26:19.163490 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7577 19:26:19.167263 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 19:26:19.170331 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 19:26:19.177158 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 19:26:19.180176 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7581 19:26:19.183383 1 6 8 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7582 19:26:19.190073 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7583 19:26:19.193725 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7584 19:26:19.196642 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7585 19:26:19.203235 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 19:26:19.206423 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 19:26:19.210170 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 19:26:19.216557 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 19:26:19.219897 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7590 19:26:19.223128 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7591 19:26:19.229944 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7592 19:26:19.233139 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7593 19:26:19.236433 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 19:26:19.243111 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 19:26:19.246515 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 19:26:19.250005 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 19:26:19.256144 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 19:26:19.259638 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 19:26:19.262946 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 19:26:19.269564 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 19:26:19.272475 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 19:26:19.275815 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 19:26:19.282558 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 19:26:19.285908 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7605 19:26:19.289434 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7606 19:26:19.292345 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7607 19:26:19.295719 Total UI for P1: 0, mck2ui 16
7608 19:26:19.299209 best dqsien dly found for B0: ( 1, 9, 6)
7609 19:26:19.305937 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7610 19:26:19.309212 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7611 19:26:19.312383 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 19:26:19.316119 Total UI for P1: 0, mck2ui 16
7613 19:26:19.319221 best dqsien dly found for B1: ( 1, 9, 20)
7614 19:26:19.322584 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
7615 19:26:19.325753 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7616 19:26:19.325829
7617 19:26:19.332396 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
7618 19:26:19.335724 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7619 19:26:19.338883 [Gating] SW calibration Done
7620 19:26:19.338956 ==
7621 19:26:19.342446 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 19:26:19.345623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 19:26:19.345695 ==
7624 19:26:19.345757 RX Vref Scan: 0
7625 19:26:19.348915
7626 19:26:19.348990 RX Vref 0 -> 0, step: 1
7627 19:26:19.349054
7628 19:26:19.352381 RX Delay 0 -> 252, step: 8
7629 19:26:19.355699 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7630 19:26:19.358967 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7631 19:26:19.365552 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7632 19:26:19.368773 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7633 19:26:19.372078 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7634 19:26:19.375452 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7635 19:26:19.378868 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7636 19:26:19.382226 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7637 19:26:19.388562 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7638 19:26:19.391855 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7639 19:26:19.395255 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7640 19:26:19.398691 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7641 19:26:19.405305 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7642 19:26:19.408301 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7643 19:26:19.411726 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7644 19:26:19.414991 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7645 19:26:19.415090 ==
7646 19:26:19.418386 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 19:26:19.421772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 19:26:19.425152 ==
7649 19:26:19.425251 DQS Delay:
7650 19:26:19.425340 DQS0 = 0, DQS1 = 0
7651 19:26:19.428500 DQM Delay:
7652 19:26:19.428575 DQM0 = 138, DQM1 = 126
7653 19:26:19.432194 DQ Delay:
7654 19:26:19.434979 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7655 19:26:19.438424 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7656 19:26:19.441576 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7657 19:26:19.445181 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7658 19:26:19.445253
7659 19:26:19.445350
7660 19:26:19.445412 ==
7661 19:26:19.448470 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 19:26:19.452116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 19:26:19.452218 ==
7664 19:26:19.452310
7665 19:26:19.454923
7666 19:26:19.455018 TX Vref Scan disable
7667 19:26:19.458397 == TX Byte 0 ==
7668 19:26:19.461441 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7669 19:26:19.464864 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7670 19:26:19.468171 == TX Byte 1 ==
7671 19:26:19.471419 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7672 19:26:19.474827 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7673 19:26:19.474926 ==
7674 19:26:19.478498 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 19:26:19.484722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 19:26:19.484797 ==
7677 19:26:19.497279
7678 19:26:19.500743 TX Vref early break, caculate TX vref
7679 19:26:19.503959 TX Vref=16, minBit 0, minWin=23, winSum=377
7680 19:26:19.507474 TX Vref=18, minBit 7, minWin=23, winSum=387
7681 19:26:19.510476 TX Vref=20, minBit 0, minWin=24, winSum=397
7682 19:26:19.514041 TX Vref=22, minBit 7, minWin=24, winSum=404
7683 19:26:19.517151 TX Vref=24, minBit 2, minWin=25, winSum=417
7684 19:26:19.524029 TX Vref=26, minBit 2, minWin=25, winSum=419
7685 19:26:19.527232 TX Vref=28, minBit 0, minWin=26, winSum=436
7686 19:26:19.530633 TX Vref=30, minBit 0, minWin=26, winSum=427
7687 19:26:19.533557 TX Vref=32, minBit 1, minWin=25, winSum=419
7688 19:26:19.536887 TX Vref=34, minBit 7, minWin=24, winSum=409
7689 19:26:19.543433 [TxChooseVref] Worse bit 0, Min win 26, Win sum 436, Final Vref 28
7690 19:26:19.543542
7691 19:26:19.547137 Final TX Range 0 Vref 28
7692 19:26:19.547239
7693 19:26:19.547336 ==
7694 19:26:19.550396 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 19:26:19.553556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 19:26:19.553656 ==
7697 19:26:19.553755
7698 19:26:19.553843
7699 19:26:19.556733 TX Vref Scan disable
7700 19:26:19.563584 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7701 19:26:19.563688 == TX Byte 0 ==
7702 19:26:19.566535 u2DelayCellOfst[0]=13 cells (4 PI)
7703 19:26:19.569988 u2DelayCellOfst[1]=20 cells (6 PI)
7704 19:26:19.573696 u2DelayCellOfst[2]=13 cells (4 PI)
7705 19:26:19.576673 u2DelayCellOfst[3]=16 cells (5 PI)
7706 19:26:19.580097 u2DelayCellOfst[4]=10 cells (3 PI)
7707 19:26:19.583052 u2DelayCellOfst[5]=0 cells (0 PI)
7708 19:26:19.586649 u2DelayCellOfst[6]=20 cells (6 PI)
7709 19:26:19.590033 u2DelayCellOfst[7]=16 cells (5 PI)
7710 19:26:19.592965 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7711 19:26:19.596330 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7712 19:26:19.599623 == TX Byte 1 ==
7713 19:26:19.603297 u2DelayCellOfst[8]=0 cells (0 PI)
7714 19:26:19.603370 u2DelayCellOfst[9]=0 cells (0 PI)
7715 19:26:19.606266 u2DelayCellOfst[10]=6 cells (2 PI)
7716 19:26:19.609852 u2DelayCellOfst[11]=3 cells (1 PI)
7717 19:26:19.612989 u2DelayCellOfst[12]=13 cells (4 PI)
7718 19:26:19.616429 u2DelayCellOfst[13]=10 cells (3 PI)
7719 19:26:19.619539 u2DelayCellOfst[14]=13 cells (4 PI)
7720 19:26:19.623644 u2DelayCellOfst[15]=10 cells (3 PI)
7721 19:26:19.626233 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7722 19:26:19.633206 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7723 19:26:19.633329 DramC Write-DBI on
7724 19:26:19.633415 ==
7725 19:26:19.636535 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 19:26:19.643126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 19:26:19.643226 ==
7728 19:26:19.643326
7729 19:26:19.643414
7730 19:26:19.643500 TX Vref Scan disable
7731 19:26:19.646817 == TX Byte 0 ==
7732 19:26:19.650281 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7733 19:26:19.653576 == TX Byte 1 ==
7734 19:26:19.657404 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7735 19:26:19.660244 DramC Write-DBI off
7736 19:26:19.660348
7737 19:26:19.660438 [DATLAT]
7738 19:26:19.660505 Freq=1600, CH0 RK0
7739 19:26:19.660564
7740 19:26:19.663401 DATLAT Default: 0xf
7741 19:26:19.663477 0, 0xFFFF, sum = 0
7742 19:26:19.667046 1, 0xFFFF, sum = 0
7743 19:26:19.667122 2, 0xFFFF, sum = 0
7744 19:26:19.670295 3, 0xFFFF, sum = 0
7745 19:26:19.673450 4, 0xFFFF, sum = 0
7746 19:26:19.673549 5, 0xFFFF, sum = 0
7747 19:26:19.676817 6, 0xFFFF, sum = 0
7748 19:26:19.676892 7, 0xFFFF, sum = 0
7749 19:26:19.680056 8, 0xFFFF, sum = 0
7750 19:26:19.680132 9, 0xFFFF, sum = 0
7751 19:26:19.683558 10, 0xFFFF, sum = 0
7752 19:26:19.683658 11, 0xFFFF, sum = 0
7753 19:26:19.686843 12, 0xFFFF, sum = 0
7754 19:26:19.686945 13, 0xFFFF, sum = 0
7755 19:26:19.690304 14, 0x0, sum = 1
7756 19:26:19.690407 15, 0x0, sum = 2
7757 19:26:19.693624 16, 0x0, sum = 3
7758 19:26:19.693709 17, 0x0, sum = 4
7759 19:26:19.696728 best_step = 15
7760 19:26:19.696815
7761 19:26:19.696900 ==
7762 19:26:19.700299 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 19:26:19.703311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 19:26:19.703398 ==
7765 19:26:19.703484 RX Vref Scan: 1
7766 19:26:19.707006
7767 19:26:19.707091 Set Vref Range= 24 -> 127
7768 19:26:19.707176
7769 19:26:19.710236 RX Vref 24 -> 127, step: 1
7770 19:26:19.710323
7771 19:26:19.713507 RX Delay 19 -> 252, step: 4
7772 19:26:19.713593
7773 19:26:19.716852 Set Vref, RX VrefLevel [Byte0]: 24
7774 19:26:19.720354 [Byte1]: 24
7775 19:26:19.720440
7776 19:26:19.723535 Set Vref, RX VrefLevel [Byte0]: 25
7777 19:26:19.726819 [Byte1]: 25
7778 19:26:19.726904
7779 19:26:19.729894 Set Vref, RX VrefLevel [Byte0]: 26
7780 19:26:19.733307 [Byte1]: 26
7781 19:26:19.736969
7782 19:26:19.737054 Set Vref, RX VrefLevel [Byte0]: 27
7783 19:26:19.740631 [Byte1]: 27
7784 19:26:19.744876
7785 19:26:19.744961 Set Vref, RX VrefLevel [Byte0]: 28
7786 19:26:19.748015 [Byte1]: 28
7787 19:26:19.752173
7788 19:26:19.752258 Set Vref, RX VrefLevel [Byte0]: 29
7789 19:26:19.755948 [Byte1]: 29
7790 19:26:19.760045
7791 19:26:19.760128 Set Vref, RX VrefLevel [Byte0]: 30
7792 19:26:19.763058 [Byte1]: 30
7793 19:26:19.767884
7794 19:26:19.767967 Set Vref, RX VrefLevel [Byte0]: 31
7795 19:26:19.771096 [Byte1]: 31
7796 19:26:19.775025
7797 19:26:19.775108 Set Vref, RX VrefLevel [Byte0]: 32
7798 19:26:19.778655 [Byte1]: 32
7799 19:26:19.782644
7800 19:26:19.782727 Set Vref, RX VrefLevel [Byte0]: 33
7801 19:26:19.785757 [Byte1]: 33
7802 19:26:19.790298
7803 19:26:19.790385 Set Vref, RX VrefLevel [Byte0]: 34
7804 19:26:19.793513 [Byte1]: 34
7805 19:26:19.798049
7806 19:26:19.798132 Set Vref, RX VrefLevel [Byte0]: 35
7807 19:26:19.800869 [Byte1]: 35
7808 19:26:19.805247
7809 19:26:19.805366 Set Vref, RX VrefLevel [Byte0]: 36
7810 19:26:19.808551 [Byte1]: 36
7811 19:26:19.812870
7812 19:26:19.812941 Set Vref, RX VrefLevel [Byte0]: 37
7813 19:26:19.816279 [Byte1]: 37
7814 19:26:19.820340
7815 19:26:19.820422 Set Vref, RX VrefLevel [Byte0]: 38
7816 19:26:19.823958 [Byte1]: 38
7817 19:26:19.828009
7818 19:26:19.828089 Set Vref, RX VrefLevel [Byte0]: 39
7819 19:26:19.831541 [Byte1]: 39
7820 19:26:19.835989
7821 19:26:19.836071 Set Vref, RX VrefLevel [Byte0]: 40
7822 19:26:19.839008 [Byte1]: 40
7823 19:26:19.843229
7824 19:26:19.843311 Set Vref, RX VrefLevel [Byte0]: 41
7825 19:26:19.846587 [Byte1]: 41
7826 19:26:19.850805
7827 19:26:19.850896 Set Vref, RX VrefLevel [Byte0]: 42
7828 19:26:19.854244 [Byte1]: 42
7829 19:26:19.858191
7830 19:26:19.858273 Set Vref, RX VrefLevel [Byte0]: 43
7831 19:26:19.861733 [Byte1]: 43
7832 19:26:19.866109
7833 19:26:19.866190 Set Vref, RX VrefLevel [Byte0]: 44
7834 19:26:19.869175 [Byte1]: 44
7835 19:26:19.873759
7836 19:26:19.873841 Set Vref, RX VrefLevel [Byte0]: 45
7837 19:26:19.876972 [Byte1]: 45
7838 19:26:19.881149
7839 19:26:19.881230 Set Vref, RX VrefLevel [Byte0]: 46
7840 19:26:19.884653 [Byte1]: 46
7841 19:26:19.888730
7842 19:26:19.888811 Set Vref, RX VrefLevel [Byte0]: 47
7843 19:26:19.891880 [Byte1]: 47
7844 19:26:19.896118
7845 19:26:19.896199 Set Vref, RX VrefLevel [Byte0]: 48
7846 19:26:19.899438 [Byte1]: 48
7847 19:26:19.903815
7848 19:26:19.903896 Set Vref, RX VrefLevel [Byte0]: 49
7849 19:26:19.907010 [Byte1]: 49
7850 19:26:19.911362
7851 19:26:19.911445 Set Vref, RX VrefLevel [Byte0]: 50
7852 19:26:19.914638 [Byte1]: 50
7853 19:26:19.919173
7854 19:26:19.919254 Set Vref, RX VrefLevel [Byte0]: 51
7855 19:26:19.922466 [Byte1]: 51
7856 19:26:19.926585
7857 19:26:19.926667 Set Vref, RX VrefLevel [Byte0]: 52
7858 19:26:19.929891 [Byte1]: 52
7859 19:26:19.934011
7860 19:26:19.934093 Set Vref, RX VrefLevel [Byte0]: 53
7861 19:26:19.937219 [Byte1]: 53
7862 19:26:19.941751
7863 19:26:19.941833 Set Vref, RX VrefLevel [Byte0]: 54
7864 19:26:19.945047 [Byte1]: 54
7865 19:26:19.949220
7866 19:26:19.949361 Set Vref, RX VrefLevel [Byte0]: 55
7867 19:26:19.952783 [Byte1]: 55
7868 19:26:19.956804
7869 19:26:19.956887 Set Vref, RX VrefLevel [Byte0]: 56
7870 19:26:19.959957 [Byte1]: 56
7871 19:26:19.964369
7872 19:26:19.964452 Set Vref, RX VrefLevel [Byte0]: 57
7873 19:26:19.967676 [Byte1]: 57
7874 19:26:19.972235
7875 19:26:19.972317 Set Vref, RX VrefLevel [Byte0]: 58
7876 19:26:19.975275 [Byte1]: 58
7877 19:26:19.979685
7878 19:26:19.979766 Set Vref, RX VrefLevel [Byte0]: 59
7879 19:26:19.983140 [Byte1]: 59
7880 19:26:19.987227
7881 19:26:19.987308 Set Vref, RX VrefLevel [Byte0]: 60
7882 19:26:19.990465 [Byte1]: 60
7883 19:26:19.994560
7884 19:26:19.994646 Set Vref, RX VrefLevel [Byte0]: 61
7885 19:26:19.998008 [Byte1]: 61
7886 19:26:20.002583
7887 19:26:20.002666 Set Vref, RX VrefLevel [Byte0]: 62
7888 19:26:20.005544 [Byte1]: 62
7889 19:26:20.009968
7890 19:26:20.010050 Set Vref, RX VrefLevel [Byte0]: 63
7891 19:26:20.013393 [Byte1]: 63
7892 19:26:20.017675
7893 19:26:20.017758 Set Vref, RX VrefLevel [Byte0]: 64
7894 19:26:20.020818 [Byte1]: 64
7895 19:26:20.025246
7896 19:26:20.025377 Set Vref, RX VrefLevel [Byte0]: 65
7897 19:26:20.028667 [Byte1]: 65
7898 19:26:20.032637
7899 19:26:20.032720 Set Vref, RX VrefLevel [Byte0]: 66
7900 19:26:20.035849 [Byte1]: 66
7901 19:26:20.040148
7902 19:26:20.040230 Set Vref, RX VrefLevel [Byte0]: 67
7903 19:26:20.043294 [Byte1]: 67
7904 19:26:20.047573
7905 19:26:20.047657 Set Vref, RX VrefLevel [Byte0]: 68
7906 19:26:20.051105 [Byte1]: 68
7907 19:26:20.055317
7908 19:26:20.055400 Set Vref, RX VrefLevel [Byte0]: 69
7909 19:26:20.058861 [Byte1]: 69
7910 19:26:20.062755
7911 19:26:20.062837 Set Vref, RX VrefLevel [Byte0]: 70
7912 19:26:20.066211 [Byte1]: 70
7913 19:26:20.070529
7914 19:26:20.070612 Set Vref, RX VrefLevel [Byte0]: 71
7915 19:26:20.073889 [Byte1]: 71
7916 19:26:20.078152
7917 19:26:20.078235 Set Vref, RX VrefLevel [Byte0]: 72
7918 19:26:20.081253 [Byte1]: 72
7919 19:26:20.085560
7920 19:26:20.085643 Set Vref, RX VrefLevel [Byte0]: 73
7921 19:26:20.088964 [Byte1]: 73
7922 19:26:20.093180
7923 19:26:20.093263 Set Vref, RX VrefLevel [Byte0]: 74
7924 19:26:20.096382 [Byte1]: 74
7925 19:26:20.100681
7926 19:26:20.100763 Set Vref, RX VrefLevel [Byte0]: 75
7927 19:26:20.104186 [Byte1]: 75
7928 19:26:20.108576
7929 19:26:20.108666 Set Vref, RX VrefLevel [Byte0]: 76
7930 19:26:20.111746 [Byte1]: 76
7931 19:26:20.116108
7932 19:26:20.116191 Set Vref, RX VrefLevel [Byte0]: 77
7933 19:26:20.119288 [Byte1]: 77
7934 19:26:20.123513
7935 19:26:20.123596 Set Vref, RX VrefLevel [Byte0]: 78
7936 19:26:20.126838 [Byte1]: 78
7937 19:26:20.131020
7938 19:26:20.131103 Set Vref, RX VrefLevel [Byte0]: 79
7939 19:26:20.134143 [Byte1]: 79
7940 19:26:20.138593
7941 19:26:20.138676 Set Vref, RX VrefLevel [Byte0]: 80
7942 19:26:20.142093 [Byte1]: 80
7943 19:26:20.145936
7944 19:26:20.146019 Final RX Vref Byte 0 = 62 to rank0
7945 19:26:20.149273 Final RX Vref Byte 1 = 62 to rank0
7946 19:26:20.152994 Final RX Vref Byte 0 = 62 to rank1
7947 19:26:20.156489 Final RX Vref Byte 1 = 62 to rank1==
7948 19:26:20.159389 Dram Type= 6, Freq= 0, CH_0, rank 0
7949 19:26:20.166246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7950 19:26:20.166331 ==
7951 19:26:20.166399 DQS Delay:
7952 19:26:20.166462 DQS0 = 0, DQS1 = 0
7953 19:26:20.169157 DQM Delay:
7954 19:26:20.169265 DQM0 = 136, DQM1 = 124
7955 19:26:20.172866 DQ Delay:
7956 19:26:20.176035 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7957 19:26:20.179202 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =144
7958 19:26:20.182699 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7959 19:26:20.186230 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7960 19:26:20.186314
7961 19:26:20.186380
7962 19:26:20.186442
7963 19:26:20.189041 [DramC_TX_OE_Calibration] TA2
7964 19:26:20.192640 Original DQ_B0 (3 6) =30, OEN = 27
7965 19:26:20.196012 Original DQ_B1 (3 6) =30, OEN = 27
7966 19:26:20.199113 24, 0x0, End_B0=24 End_B1=24
7967 19:26:20.199204 25, 0x0, End_B0=25 End_B1=25
7968 19:26:20.202530 26, 0x0, End_B0=26 End_B1=26
7969 19:26:20.206020 27, 0x0, End_B0=27 End_B1=27
7970 19:26:20.209098 28, 0x0, End_B0=28 End_B1=28
7971 19:26:20.212657 29, 0x0, End_B0=29 End_B1=29
7972 19:26:20.212740 30, 0x0, End_B0=30 End_B1=30
7973 19:26:20.215847 31, 0x4141, End_B0=30 End_B1=30
7974 19:26:20.219136 Byte0 end_step=30 best_step=27
7975 19:26:20.222343 Byte1 end_step=30 best_step=27
7976 19:26:20.225754 Byte0 TX OE(2T, 0.5T) = (3, 3)
7977 19:26:20.229073 Byte1 TX OE(2T, 0.5T) = (3, 3)
7978 19:26:20.229155
7979 19:26:20.229221
7980 19:26:20.235537 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7981 19:26:20.238832 CH0 RK0: MR19=303, MR18=1E1C
7982 19:26:20.245468 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
7983 19:26:20.245551
7984 19:26:20.249022 ----->DramcWriteLeveling(PI) begin...
7985 19:26:20.249106 ==
7986 19:26:20.252311 Dram Type= 6, Freq= 0, CH_0, rank 1
7987 19:26:20.255990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 19:26:20.256073 ==
7989 19:26:20.258914 Write leveling (Byte 0): 39 => 39
7990 19:26:20.262414 Write leveling (Byte 1): 28 => 28
7991 19:26:20.265941 DramcWriteLeveling(PI) end<-----
7992 19:26:20.266023
7993 19:26:20.266087 ==
7994 19:26:20.269085 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 19:26:20.272399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 19:26:20.272482 ==
7997 19:26:20.275553 [Gating] SW mode calibration
7998 19:26:20.281933 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7999 19:26:20.288930 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8000 19:26:20.292306 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 19:26:20.295268 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 19:26:20.301918 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8003 19:26:20.305635 1 4 12 | B1->B0 | 2524 3332 | 1 1 | (0 0) (0 0)
8004 19:26:20.308463 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 19:26:20.315447 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 19:26:20.318528 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 19:26:20.321995 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 19:26:20.328588 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 19:26:20.332106 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 19:26:20.335269 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 19:26:20.342485 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 0) (1 0)
8012 19:26:20.345346 1 5 16 | B1->B0 | 2828 2323 | 0 0 | (0 1) (1 0)
8013 19:26:20.348973 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 19:26:20.355377 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 19:26:20.358542 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 19:26:20.362061 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 19:26:20.368476 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 19:26:20.371739 1 6 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
8019 19:26:20.375641 1 6 12 | B1->B0 | 2c2c 4343 | 0 1 | (1 1) (0 0)
8020 19:26:20.382040 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 19:26:20.385471 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 19:26:20.388329 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 19:26:20.395116 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 19:26:20.398337 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 19:26:20.401798 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 19:26:20.408559 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8027 19:26:20.411555 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8028 19:26:20.414942 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8029 19:26:20.421442 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 19:26:20.425016 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 19:26:20.428195 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 19:26:20.431841 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 19:26:20.438211 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 19:26:20.441805 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 19:26:20.445136 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 19:26:20.451884 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 19:26:20.454618 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 19:26:20.458072 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 19:26:20.464627 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 19:26:20.467994 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 19:26:20.471420 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 19:26:20.478033 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8043 19:26:20.481239 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8044 19:26:20.484755 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8045 19:26:20.491344 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 19:26:20.494452 Total UI for P1: 0, mck2ui 16
8047 19:26:20.497745 best dqsien dly found for B0: ( 1, 9, 12)
8048 19:26:20.497859 Total UI for P1: 0, mck2ui 16
8049 19:26:20.505079 best dqsien dly found for B1: ( 1, 9, 14)
8050 19:26:20.507794 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8051 19:26:20.511168 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8052 19:26:20.511279
8053 19:26:20.514473 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8054 19:26:20.517671 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8055 19:26:20.521038 [Gating] SW calibration Done
8056 19:26:20.521121 ==
8057 19:26:20.524663 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 19:26:20.527870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 19:26:20.527954 ==
8060 19:26:20.531231 RX Vref Scan: 0
8061 19:26:20.531314
8062 19:26:20.531380 RX Vref 0 -> 0, step: 1
8063 19:26:20.534400
8064 19:26:20.534483 RX Delay 0 -> 252, step: 8
8065 19:26:20.537708 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8066 19:26:20.544388 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8067 19:26:20.547847 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8068 19:26:20.550956 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8069 19:26:20.554553 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8070 19:26:20.557778 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8071 19:26:20.564454 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8072 19:26:20.567796 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8073 19:26:20.571131 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8074 19:26:20.574711 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8075 19:26:20.577542 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8076 19:26:20.584150 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8077 19:26:20.587715 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8078 19:26:20.590927 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8079 19:26:20.594137 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8080 19:26:20.600808 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8081 19:26:20.600896 ==
8082 19:26:20.603977 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 19:26:20.607510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 19:26:20.607594 ==
8085 19:26:20.607661 DQS Delay:
8086 19:26:20.610680 DQS0 = 0, DQS1 = 0
8087 19:26:20.610763 DQM Delay:
8088 19:26:20.614244 DQM0 = 136, DQM1 = 125
8089 19:26:20.614327 DQ Delay:
8090 19:26:20.617501 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8091 19:26:20.620654 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8092 19:26:20.624275 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8093 19:26:20.627727 DQ12 =127, DQ13 =135, DQ14 =135, DQ15 =135
8094 19:26:20.627811
8095 19:26:20.627877
8096 19:26:20.627939 ==
8097 19:26:20.630893 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 19:26:20.637256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 19:26:20.637402 ==
8100 19:26:20.637516
8101 19:26:20.637584
8102 19:26:20.640550 TX Vref Scan disable
8103 19:26:20.640617 == TX Byte 0 ==
8104 19:26:20.644517 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8105 19:26:20.650524 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8106 19:26:20.650605 == TX Byte 1 ==
8107 19:26:20.653959 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8108 19:26:20.660455 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8109 19:26:20.660540 ==
8110 19:26:20.664258 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 19:26:20.667124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 19:26:20.667207 ==
8113 19:26:20.682834
8114 19:26:20.686206 TX Vref early break, caculate TX vref
8115 19:26:20.689290 TX Vref=16, minBit 0, minWin=23, winSum=389
8116 19:26:20.692699 TX Vref=18, minBit 1, minWin=24, winSum=397
8117 19:26:20.695982 TX Vref=20, minBit 8, minWin=24, winSum=407
8118 19:26:20.699577 TX Vref=22, minBit 8, minWin=24, winSum=414
8119 19:26:20.702682 TX Vref=24, minBit 0, minWin=25, winSum=421
8120 19:26:20.709532 TX Vref=26, minBit 0, minWin=26, winSum=428
8121 19:26:20.712815 TX Vref=28, minBit 0, minWin=26, winSum=430
8122 19:26:20.715865 TX Vref=30, minBit 2, minWin=26, winSum=429
8123 19:26:20.719582 TX Vref=32, minBit 0, minWin=26, winSum=419
8124 19:26:20.722544 TX Vref=34, minBit 4, minWin=24, winSum=412
8125 19:26:20.726150 TX Vref=36, minBit 3, minWin=24, winSum=403
8126 19:26:20.732452 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8127 19:26:20.732535
8128 19:26:20.735858 Final TX Range 0 Vref 28
8129 19:26:20.735941
8130 19:26:20.736006 ==
8131 19:26:20.738968 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 19:26:20.742752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 19:26:20.742835 ==
8134 19:26:20.742901
8135 19:26:20.742962
8136 19:26:20.745936 TX Vref Scan disable
8137 19:26:20.752641 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8138 19:26:20.752723 == TX Byte 0 ==
8139 19:26:20.755756 u2DelayCellOfst[0]=10 cells (3 PI)
8140 19:26:20.759398 u2DelayCellOfst[1]=16 cells (5 PI)
8141 19:26:20.762390 u2DelayCellOfst[2]=10 cells (3 PI)
8142 19:26:20.765838 u2DelayCellOfst[3]=10 cells (3 PI)
8143 19:26:20.769260 u2DelayCellOfst[4]=6 cells (2 PI)
8144 19:26:20.772501 u2DelayCellOfst[5]=0 cells (0 PI)
8145 19:26:20.776245 u2DelayCellOfst[6]=16 cells (5 PI)
8146 19:26:20.779208 u2DelayCellOfst[7]=13 cells (4 PI)
8147 19:26:20.782415 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8148 19:26:20.786078 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8149 19:26:20.789491 == TX Byte 1 ==
8150 19:26:20.792332 u2DelayCellOfst[8]=0 cells (0 PI)
8151 19:26:20.792414 u2DelayCellOfst[9]=0 cells (0 PI)
8152 19:26:20.795537 u2DelayCellOfst[10]=6 cells (2 PI)
8153 19:26:20.799427 u2DelayCellOfst[11]=3 cells (1 PI)
8154 19:26:20.802238 u2DelayCellOfst[12]=13 cells (4 PI)
8155 19:26:20.805820 u2DelayCellOfst[13]=10 cells (3 PI)
8156 19:26:20.809051 u2DelayCellOfst[14]=13 cells (4 PI)
8157 19:26:20.812527 u2DelayCellOfst[15]=10 cells (3 PI)
8158 19:26:20.815833 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8159 19:26:20.822484 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8160 19:26:20.822570 DramC Write-DBI on
8161 19:26:20.822637 ==
8162 19:26:20.825870 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 19:26:20.832255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 19:26:20.832339 ==
8165 19:26:20.832404
8166 19:26:20.832464
8167 19:26:20.832523 TX Vref Scan disable
8168 19:26:20.836174 == TX Byte 0 ==
8169 19:26:20.839684 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8170 19:26:20.842862 == TX Byte 1 ==
8171 19:26:20.846512 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8172 19:26:20.849459 DramC Write-DBI off
8173 19:26:20.849541
8174 19:26:20.849607 [DATLAT]
8175 19:26:20.849668 Freq=1600, CH0 RK1
8176 19:26:20.849728
8177 19:26:20.852843 DATLAT Default: 0xf
8178 19:26:20.852925 0, 0xFFFF, sum = 0
8179 19:26:20.856159 1, 0xFFFF, sum = 0
8180 19:26:20.856243 2, 0xFFFF, sum = 0
8181 19:26:20.859511 3, 0xFFFF, sum = 0
8182 19:26:20.862764 4, 0xFFFF, sum = 0
8183 19:26:20.862848 5, 0xFFFF, sum = 0
8184 19:26:20.866044 6, 0xFFFF, sum = 0
8185 19:26:20.866128 7, 0xFFFF, sum = 0
8186 19:26:20.869625 8, 0xFFFF, sum = 0
8187 19:26:20.869709 9, 0xFFFF, sum = 0
8188 19:26:20.873207 10, 0xFFFF, sum = 0
8189 19:26:20.873291 11, 0xFFFF, sum = 0
8190 19:26:20.876181 12, 0xFFFF, sum = 0
8191 19:26:20.876264 13, 0xFFFF, sum = 0
8192 19:26:20.879385 14, 0x0, sum = 1
8193 19:26:20.879468 15, 0x0, sum = 2
8194 19:26:20.883229 16, 0x0, sum = 3
8195 19:26:20.883313 17, 0x0, sum = 4
8196 19:26:20.886131 best_step = 15
8197 19:26:20.886213
8198 19:26:20.886278 ==
8199 19:26:20.889451 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 19:26:20.892794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 19:26:20.892877 ==
8202 19:26:20.896068 RX Vref Scan: 0
8203 19:26:20.896150
8204 19:26:20.896231 RX Vref 0 -> 0, step: 1
8205 19:26:20.896326
8206 19:26:20.899122 RX Delay 11 -> 252, step: 4
8207 19:26:20.902252 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8208 19:26:20.909201 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8209 19:26:20.912622 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8210 19:26:20.916305 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8211 19:26:20.919485 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8212 19:26:20.922590 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8213 19:26:20.929208 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8214 19:26:20.932736 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8215 19:26:20.936040 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8216 19:26:20.939502 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8217 19:26:20.942478 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8218 19:26:20.948864 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8219 19:26:20.952340 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8220 19:26:20.955880 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8221 19:26:20.958840 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8222 19:26:20.962574 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8223 19:26:20.965569 ==
8224 19:26:20.968819 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 19:26:20.972816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 19:26:20.972899 ==
8227 19:26:20.972965 DQS Delay:
8228 19:26:20.975459 DQS0 = 0, DQS1 = 0
8229 19:26:20.975541 DQM Delay:
8230 19:26:20.978844 DQM0 = 133, DQM1 = 123
8231 19:26:20.978926 DQ Delay:
8232 19:26:20.982088 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8233 19:26:20.985459 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8234 19:26:20.988699 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8235 19:26:20.992114 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8236 19:26:20.992197
8237 19:26:20.992262
8238 19:26:20.992321
8239 19:26:20.995394 [DramC_TX_OE_Calibration] TA2
8240 19:26:20.999064 Original DQ_B0 (3 6) =30, OEN = 27
8241 19:26:21.002010 Original DQ_B1 (3 6) =30, OEN = 27
8242 19:26:21.005244 24, 0x0, End_B0=24 End_B1=24
8243 19:26:21.008937 25, 0x0, End_B0=25 End_B1=25
8244 19:26:21.009020 26, 0x0, End_B0=26 End_B1=26
8245 19:26:21.012046 27, 0x0, End_B0=27 End_B1=27
8246 19:26:21.015304 28, 0x0, End_B0=28 End_B1=28
8247 19:26:21.018879 29, 0x0, End_B0=29 End_B1=29
8248 19:26:21.021772 30, 0x0, End_B0=30 End_B1=30
8249 19:26:21.021856 31, 0x4141, End_B0=30 End_B1=30
8250 19:26:21.025243 Byte0 end_step=30 best_step=27
8251 19:26:21.028747 Byte1 end_step=30 best_step=27
8252 19:26:21.032038 Byte0 TX OE(2T, 0.5T) = (3, 3)
8253 19:26:21.035507 Byte1 TX OE(2T, 0.5T) = (3, 3)
8254 19:26:21.035589
8255 19:26:21.035654
8256 19:26:21.041949 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8257 19:26:21.045185 CH0 RK1: MR19=303, MR18=1F0D
8258 19:26:21.051989 CH0_RK1: MR19=0x303, MR18=0x1F0D, DQSOSC=394, MR23=63, INC=23, DEC=15
8259 19:26:21.055189 [RxdqsGatingPostProcess] freq 1600
8260 19:26:21.061715 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8261 19:26:21.061799 best DQS0 dly(2T, 0.5T) = (1, 1)
8262 19:26:21.065156 best DQS1 dly(2T, 0.5T) = (1, 1)
8263 19:26:21.068270 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8264 19:26:21.071618 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8265 19:26:21.075056 best DQS0 dly(2T, 0.5T) = (1, 1)
8266 19:26:21.078628 best DQS1 dly(2T, 0.5T) = (1, 1)
8267 19:26:21.081398 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8268 19:26:21.084710 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8269 19:26:21.088130 Pre-setting of DQS Precalculation
8270 19:26:21.091859 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8271 19:26:21.091943 ==
8272 19:26:21.094732 Dram Type= 6, Freq= 0, CH_1, rank 0
8273 19:26:21.102036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 19:26:21.102124 ==
8275 19:26:21.104842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8276 19:26:21.111418 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8277 19:26:21.115036 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8278 19:26:21.121565 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8279 19:26:21.129442 [CA 0] Center 40 (11~70) winsize 60
8280 19:26:21.132485 [CA 1] Center 41 (11~71) winsize 61
8281 19:26:21.136151 [CA 2] Center 37 (8~66) winsize 59
8282 19:26:21.139255 [CA 3] Center 36 (7~66) winsize 60
8283 19:26:21.142707 [CA 4] Center 36 (7~66) winsize 60
8284 19:26:21.145982 [CA 5] Center 36 (6~66) winsize 61
8285 19:26:21.146066
8286 19:26:21.149183 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8287 19:26:21.149280
8288 19:26:21.152792 [CATrainingPosCal] consider 1 rank data
8289 19:26:21.155899 u2DelayCellTimex100 = 290/100 ps
8290 19:26:21.159109 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8291 19:26:21.165672 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8292 19:26:21.169346 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8293 19:26:21.172527 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8294 19:26:21.175706 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8295 19:26:21.179176 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8296 19:26:21.179257
8297 19:26:21.182775 CA PerBit enable=1, Macro0, CA PI delay=36
8298 19:26:21.182856
8299 19:26:21.185669 [CBTSetCACLKResult] CA Dly = 36
8300 19:26:21.185750 CS Dly: 8 (0~39)
8301 19:26:21.192468 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8302 19:26:21.195689 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8303 19:26:21.195770 ==
8304 19:26:21.198918 Dram Type= 6, Freq= 0, CH_1, rank 1
8305 19:26:21.202422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 19:26:21.202503 ==
8307 19:26:21.208898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8308 19:26:21.212223 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8309 19:26:21.218946 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8310 19:26:21.222747 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8311 19:26:21.232330 [CA 0] Center 42 (12~72) winsize 61
8312 19:26:21.235469 [CA 1] Center 41 (11~71) winsize 61
8313 19:26:21.239391 [CA 2] Center 37 (8~67) winsize 60
8314 19:26:21.242091 [CA 3] Center 37 (8~67) winsize 60
8315 19:26:21.245472 [CA 4] Center 37 (8~67) winsize 60
8316 19:26:21.248974 [CA 5] Center 36 (7~66) winsize 60
8317 19:26:21.249056
8318 19:26:21.252436 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8319 19:26:21.252518
8320 19:26:21.255815 [CATrainingPosCal] consider 2 rank data
8321 19:26:21.259060 u2DelayCellTimex100 = 290/100 ps
8322 19:26:21.262275 CA0 delay=41 (12~70),Diff = 5 PI (16 cell)
8323 19:26:21.268675 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8324 19:26:21.271914 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8325 19:26:21.275457 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8326 19:26:21.278689 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8327 19:26:21.282018 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8328 19:26:21.282099
8329 19:26:21.285164 CA PerBit enable=1, Macro0, CA PI delay=36
8330 19:26:21.285245
8331 19:26:21.288669 [CBTSetCACLKResult] CA Dly = 36
8332 19:26:21.291919 CS Dly: 9 (0~42)
8333 19:26:21.295134 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8334 19:26:21.298428 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8335 19:26:21.298509
8336 19:26:21.301820 ----->DramcWriteLeveling(PI) begin...
8337 19:26:21.301902 ==
8338 19:26:21.305236 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 19:26:21.308404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 19:26:21.311967 ==
8341 19:26:21.315215 Write leveling (Byte 0): 27 => 27
8342 19:26:21.315297 Write leveling (Byte 1): 27 => 27
8343 19:26:21.318407 DramcWriteLeveling(PI) end<-----
8344 19:26:21.318488
8345 19:26:21.318551 ==
8346 19:26:21.321959 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 19:26:21.328626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 19:26:21.328708 ==
8349 19:26:21.332051 [Gating] SW mode calibration
8350 19:26:21.338752 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8351 19:26:21.342180 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8352 19:26:21.348879 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 19:26:21.351634 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 19:26:21.355374 1 4 8 | B1->B0 | 2d2d 3131 | 0 1 | (0 0) (1 1)
8355 19:26:21.361928 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 19:26:21.365057 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 19:26:21.368337 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 19:26:21.371820 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 19:26:21.378531 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 19:26:21.381968 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 19:26:21.385002 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8362 19:26:21.391714 1 5 8 | B1->B0 | 2727 2424 | 1 1 | (1 0) (1 0)
8363 19:26:21.394885 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8364 19:26:21.398161 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 19:26:21.405259 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 19:26:21.408638 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 19:26:21.411606 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 19:26:21.418457 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 19:26:21.421724 1 6 4 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
8370 19:26:21.424771 1 6 8 | B1->B0 | 3e3e 4444 | 0 0 | (0 0) (0 0)
8371 19:26:21.431839 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 19:26:21.434723 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 19:26:21.438327 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 19:26:21.444756 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 19:26:21.448069 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 19:26:21.451501 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 19:26:21.457989 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 19:26:21.461547 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8379 19:26:21.464830 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8380 19:26:21.471467 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 19:26:21.474516 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 19:26:21.477997 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 19:26:21.484658 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 19:26:21.487936 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 19:26:21.491362 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 19:26:21.497634 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 19:26:21.501129 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 19:26:21.504367 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 19:26:21.510765 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 19:26:21.514024 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 19:26:21.517504 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 19:26:21.523953 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 19:26:21.527127 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8394 19:26:21.530489 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8395 19:26:21.536894 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8396 19:26:21.536998 Total UI for P1: 0, mck2ui 16
8397 19:26:21.543765 best dqsien dly found for B0: ( 1, 9, 6)
8398 19:26:21.547069 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 19:26:21.550294 Total UI for P1: 0, mck2ui 16
8400 19:26:21.553618 best dqsien dly found for B1: ( 1, 9, 10)
8401 19:26:21.557077 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8402 19:26:21.560425 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8403 19:26:21.560520
8404 19:26:21.563835 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8405 19:26:21.566946 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8406 19:26:21.570225 [Gating] SW calibration Done
8407 19:26:21.570326 ==
8408 19:26:21.573797 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 19:26:21.577229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 19:26:21.580747 ==
8411 19:26:21.580842 RX Vref Scan: 0
8412 19:26:21.580931
8413 19:26:21.583829 RX Vref 0 -> 0, step: 1
8414 19:26:21.583920
8415 19:26:21.584007 RX Delay 0 -> 252, step: 8
8416 19:26:21.590132 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8417 19:26:21.593476 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8418 19:26:21.597159 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8419 19:26:21.600094 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8420 19:26:21.603421 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8421 19:26:21.610096 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8422 19:26:21.613513 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8423 19:26:21.616738 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8424 19:26:21.620109 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8425 19:26:21.623368 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8426 19:26:21.630087 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8427 19:26:21.633314 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8428 19:26:21.637070 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8429 19:26:21.640056 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8430 19:26:21.643262 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8431 19:26:21.649937 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8432 19:26:21.650010 ==
8433 19:26:21.653272 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 19:26:21.656710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 19:26:21.656805 ==
8436 19:26:21.656894 DQS Delay:
8437 19:26:21.660114 DQS0 = 0, DQS1 = 0
8438 19:26:21.660206 DQM Delay:
8439 19:26:21.663519 DQM0 = 136, DQM1 = 130
8440 19:26:21.663610 DQ Delay:
8441 19:26:21.666688 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8442 19:26:21.669997 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8443 19:26:21.673109 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8444 19:26:21.676529 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
8445 19:26:21.676602
8446 19:26:21.680085
8447 19:26:21.680178 ==
8448 19:26:21.683257 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 19:26:21.686442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 19:26:21.686510 ==
8451 19:26:21.686570
8452 19:26:21.686631
8453 19:26:21.689756 TX Vref Scan disable
8454 19:26:21.689821 == TX Byte 0 ==
8455 19:26:21.693489 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8456 19:26:21.699860 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8457 19:26:21.699957 == TX Byte 1 ==
8458 19:26:21.706357 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8459 19:26:21.709830 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8460 19:26:21.709899 ==
8461 19:26:21.713055 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 19:26:21.716301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 19:26:21.716376 ==
8464 19:26:21.729582
8465 19:26:21.732596 TX Vref early break, caculate TX vref
8466 19:26:21.736232 TX Vref=16, minBit 10, minWin=21, winSum=372
8467 19:26:21.739198 TX Vref=18, minBit 10, minWin=22, winSum=381
8468 19:26:21.742479 TX Vref=20, minBit 10, minWin=23, winSum=392
8469 19:26:21.746069 TX Vref=22, minBit 10, minWin=23, winSum=402
8470 19:26:21.749247 TX Vref=24, minBit 1, minWin=25, winSum=412
8471 19:26:21.756046 TX Vref=26, minBit 10, minWin=25, winSum=422
8472 19:26:21.759275 TX Vref=28, minBit 12, minWin=25, winSum=421
8473 19:26:21.762623 TX Vref=30, minBit 9, minWin=25, winSum=420
8474 19:26:21.765934 TX Vref=32, minBit 11, minWin=24, winSum=408
8475 19:26:21.769434 TX Vref=34, minBit 5, minWin=24, winSum=399
8476 19:26:21.775861 [TxChooseVref] Worse bit 10, Min win 25, Win sum 422, Final Vref 26
8477 19:26:21.775961
8478 19:26:21.779403 Final TX Range 0 Vref 26
8479 19:26:21.779501
8480 19:26:21.779592 ==
8481 19:26:21.782968 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 19:26:21.785819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 19:26:21.785889 ==
8484 19:26:21.785952
8485 19:26:21.786009
8486 19:26:21.789216 TX Vref Scan disable
8487 19:26:21.795830 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8488 19:26:21.795928 == TX Byte 0 ==
8489 19:26:21.799269 u2DelayCellOfst[0]=13 cells (4 PI)
8490 19:26:21.802468 u2DelayCellOfst[1]=6 cells (2 PI)
8491 19:26:21.805948 u2DelayCellOfst[2]=0 cells (0 PI)
8492 19:26:21.809109 u2DelayCellOfst[3]=3 cells (1 PI)
8493 19:26:21.812443 u2DelayCellOfst[4]=6 cells (2 PI)
8494 19:26:21.815920 u2DelayCellOfst[5]=16 cells (5 PI)
8495 19:26:21.819045 u2DelayCellOfst[6]=16 cells (5 PI)
8496 19:26:21.822513 u2DelayCellOfst[7]=3 cells (1 PI)
8497 19:26:21.825827 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8498 19:26:21.829349 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8499 19:26:21.832907 == TX Byte 1 ==
8500 19:26:21.833007 u2DelayCellOfst[8]=0 cells (0 PI)
8501 19:26:21.835842 u2DelayCellOfst[9]=3 cells (1 PI)
8502 19:26:21.838981 u2DelayCellOfst[10]=10 cells (3 PI)
8503 19:26:21.842429 u2DelayCellOfst[11]=3 cells (1 PI)
8504 19:26:21.845652 u2DelayCellOfst[12]=13 cells (4 PI)
8505 19:26:21.849224 u2DelayCellOfst[13]=16 cells (5 PI)
8506 19:26:21.852366 u2DelayCellOfst[14]=20 cells (6 PI)
8507 19:26:21.855837 u2DelayCellOfst[15]=16 cells (5 PI)
8508 19:26:21.858789 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8509 19:26:21.865915 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8510 19:26:21.865985 DramC Write-DBI on
8511 19:26:21.866046 ==
8512 19:26:21.868990 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 19:26:21.875347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 19:26:21.875442 ==
8515 19:26:21.875531
8516 19:26:21.875619
8517 19:26:21.875705 TX Vref Scan disable
8518 19:26:21.878979 == TX Byte 0 ==
8519 19:26:21.882397 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8520 19:26:21.885583 == TX Byte 1 ==
8521 19:26:21.889130 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8522 19:26:21.892456 DramC Write-DBI off
8523 19:26:21.892524
8524 19:26:21.892585 [DATLAT]
8525 19:26:21.892642 Freq=1600, CH1 RK0
8526 19:26:21.892698
8527 19:26:21.895815 DATLAT Default: 0xf
8528 19:26:21.899171 0, 0xFFFF, sum = 0
8529 19:26:21.899241 1, 0xFFFF, sum = 0
8530 19:26:21.902564 2, 0xFFFF, sum = 0
8531 19:26:21.902630 3, 0xFFFF, sum = 0
8532 19:26:21.905674 4, 0xFFFF, sum = 0
8533 19:26:21.905740 5, 0xFFFF, sum = 0
8534 19:26:21.908590 6, 0xFFFF, sum = 0
8535 19:26:21.908685 7, 0xFFFF, sum = 0
8536 19:26:21.912221 8, 0xFFFF, sum = 0
8537 19:26:21.912316 9, 0xFFFF, sum = 0
8538 19:26:21.915381 10, 0xFFFF, sum = 0
8539 19:26:21.915474 11, 0xFFFF, sum = 0
8540 19:26:21.918805 12, 0xFFFF, sum = 0
8541 19:26:21.918874 13, 0xFFFF, sum = 0
8542 19:26:21.921865 14, 0x0, sum = 1
8543 19:26:21.921938 15, 0x0, sum = 2
8544 19:26:21.925133 16, 0x0, sum = 3
8545 19:26:21.925227 17, 0x0, sum = 4
8546 19:26:21.928758 best_step = 15
8547 19:26:21.928850
8548 19:26:21.928937 ==
8549 19:26:21.931973 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 19:26:21.935143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 19:26:21.935243 ==
8552 19:26:21.938466 RX Vref Scan: 1
8553 19:26:21.938563
8554 19:26:21.938655 Set Vref Range= 24 -> 127
8555 19:26:21.938741
8556 19:26:21.941824 RX Vref 24 -> 127, step: 1
8557 19:26:21.941891
8558 19:26:21.945349 RX Delay 19 -> 252, step: 4
8559 19:26:21.945414
8560 19:26:21.948412 Set Vref, RX VrefLevel [Byte0]: 24
8561 19:26:21.951667 [Byte1]: 24
8562 19:26:21.951763
8563 19:26:21.955202 Set Vref, RX VrefLevel [Byte0]: 25
8564 19:26:21.958679 [Byte1]: 25
8565 19:26:21.961689
8566 19:26:21.961759 Set Vref, RX VrefLevel [Byte0]: 26
8567 19:26:21.964937 [Byte1]: 26
8568 19:26:21.969371
8569 19:26:21.972740 Set Vref, RX VrefLevel [Byte0]: 27
8570 19:26:21.976166 [Byte1]: 27
8571 19:26:21.976235
8572 19:26:21.979254 Set Vref, RX VrefLevel [Byte0]: 28
8573 19:26:21.982535 [Byte1]: 28
8574 19:26:21.982609
8575 19:26:21.985669 Set Vref, RX VrefLevel [Byte0]: 29
8576 19:26:21.989456 [Byte1]: 29
8577 19:26:21.989527
8578 19:26:21.992662 Set Vref, RX VrefLevel [Byte0]: 30
8579 19:26:21.995449 [Byte1]: 30
8580 19:26:21.999817
8581 19:26:21.999888 Set Vref, RX VrefLevel [Byte0]: 31
8582 19:26:22.003206 [Byte1]: 31
8583 19:26:22.007408
8584 19:26:22.007501 Set Vref, RX VrefLevel [Byte0]: 32
8585 19:26:22.010834 [Byte1]: 32
8586 19:26:22.014682
8587 19:26:22.014774 Set Vref, RX VrefLevel [Byte0]: 33
8588 19:26:22.018202 [Byte1]: 33
8589 19:26:22.022431
8590 19:26:22.022498 Set Vref, RX VrefLevel [Byte0]: 34
8591 19:26:22.025916 [Byte1]: 34
8592 19:26:22.030068
8593 19:26:22.030163 Set Vref, RX VrefLevel [Byte0]: 35
8594 19:26:22.033201 [Byte1]: 35
8595 19:26:22.037579
8596 19:26:22.037649 Set Vref, RX VrefLevel [Byte0]: 36
8597 19:26:22.040789 [Byte1]: 36
8598 19:26:22.045077
8599 19:26:22.045176 Set Vref, RX VrefLevel [Byte0]: 37
8600 19:26:22.048260 [Byte1]: 37
8601 19:26:22.052765
8602 19:26:22.052859 Set Vref, RX VrefLevel [Byte0]: 38
8603 19:26:22.056107 [Byte1]: 38
8604 19:26:22.060361
8605 19:26:22.060457 Set Vref, RX VrefLevel [Byte0]: 39
8606 19:26:22.063608 [Byte1]: 39
8607 19:26:22.067788
8608 19:26:22.067855 Set Vref, RX VrefLevel [Byte0]: 40
8609 19:26:22.071094 [Byte1]: 40
8610 19:26:22.075319
8611 19:26:22.075386 Set Vref, RX VrefLevel [Byte0]: 41
8612 19:26:22.078720 [Byte1]: 41
8613 19:26:22.083187
8614 19:26:22.083292 Set Vref, RX VrefLevel [Byte0]: 42
8615 19:26:22.086256 [Byte1]: 42
8616 19:26:22.090642
8617 19:26:22.090715 Set Vref, RX VrefLevel [Byte0]: 43
8618 19:26:22.093704 [Byte1]: 43
8619 19:26:22.098061
8620 19:26:22.098131 Set Vref, RX VrefLevel [Byte0]: 44
8621 19:26:22.101736 [Byte1]: 44
8622 19:26:22.105828
8623 19:26:22.105894 Set Vref, RX VrefLevel [Byte0]: 45
8624 19:26:22.109226 [Byte1]: 45
8625 19:26:22.113448
8626 19:26:22.113542 Set Vref, RX VrefLevel [Byte0]: 46
8627 19:26:22.116507 [Byte1]: 46
8628 19:26:22.120822
8629 19:26:22.120909 Set Vref, RX VrefLevel [Byte0]: 47
8630 19:26:22.123979 [Byte1]: 47
8631 19:26:22.128394
8632 19:26:22.128492 Set Vref, RX VrefLevel [Byte0]: 48
8633 19:26:22.131509 [Byte1]: 48
8634 19:26:22.136344
8635 19:26:22.136441 Set Vref, RX VrefLevel [Byte0]: 49
8636 19:26:22.139211 [Byte1]: 49
8637 19:26:22.143577
8638 19:26:22.143671 Set Vref, RX VrefLevel [Byte0]: 50
8639 19:26:22.146883 [Byte1]: 50
8640 19:26:22.151311
8641 19:26:22.151408 Set Vref, RX VrefLevel [Byte0]: 51
8642 19:26:22.154327 [Byte1]: 51
8643 19:26:22.158554
8644 19:26:22.158623 Set Vref, RX VrefLevel [Byte0]: 52
8645 19:26:22.162107 [Byte1]: 52
8646 19:26:22.166261
8647 19:26:22.166328 Set Vref, RX VrefLevel [Byte0]: 53
8648 19:26:22.169499 [Byte1]: 53
8649 19:26:22.173933
8650 19:26:22.174001 Set Vref, RX VrefLevel [Byte0]: 54
8651 19:26:22.177411 [Byte1]: 54
8652 19:26:22.181598
8653 19:26:22.181663 Set Vref, RX VrefLevel [Byte0]: 55
8654 19:26:22.184902 [Byte1]: 55
8655 19:26:22.189202
8656 19:26:22.189317 Set Vref, RX VrefLevel [Byte0]: 56
8657 19:26:22.192134 [Byte1]: 56
8658 19:26:22.196419
8659 19:26:22.196520 Set Vref, RX VrefLevel [Byte0]: 57
8660 19:26:22.199938 [Byte1]: 57
8661 19:26:22.203977
8662 19:26:22.204072 Set Vref, RX VrefLevel [Byte0]: 58
8663 19:26:22.207636 [Byte1]: 58
8664 19:26:22.212118
8665 19:26:22.212212 Set Vref, RX VrefLevel [Byte0]: 59
8666 19:26:22.215310 [Byte1]: 59
8667 19:26:22.219338
8668 19:26:22.219408 Set Vref, RX VrefLevel [Byte0]: 60
8669 19:26:22.222511 [Byte1]: 60
8670 19:26:22.227142
8671 19:26:22.227208 Set Vref, RX VrefLevel [Byte0]: 61
8672 19:26:22.230406 [Byte1]: 61
8673 19:26:22.234258
8674 19:26:22.234360 Set Vref, RX VrefLevel [Byte0]: 62
8675 19:26:22.237828 [Byte1]: 62
8676 19:26:22.241736
8677 19:26:22.241805 Set Vref, RX VrefLevel [Byte0]: 63
8678 19:26:22.245331 [Byte1]: 63
8679 19:26:22.249564
8680 19:26:22.249651 Set Vref, RX VrefLevel [Byte0]: 64
8681 19:26:22.252906 [Byte1]: 64
8682 19:26:22.257189
8683 19:26:22.257284 Set Vref, RX VrefLevel [Byte0]: 65
8684 19:26:22.260526 [Byte1]: 65
8685 19:26:22.264660
8686 19:26:22.264758 Set Vref, RX VrefLevel [Byte0]: 66
8687 19:26:22.268254 [Byte1]: 66
8688 19:26:22.272306
8689 19:26:22.272376 Set Vref, RX VrefLevel [Byte0]: 67
8690 19:26:22.275454 [Byte1]: 67
8691 19:26:22.279788
8692 19:26:22.279881 Set Vref, RX VrefLevel [Byte0]: 68
8693 19:26:22.283271 [Byte1]: 68
8694 19:26:22.287693
8695 19:26:22.287785 Set Vref, RX VrefLevel [Byte0]: 69
8696 19:26:22.290907 [Byte1]: 69
8697 19:26:22.295157
8698 19:26:22.295256 Set Vref, RX VrefLevel [Byte0]: 70
8699 19:26:22.298273 [Byte1]: 70
8700 19:26:22.302388
8701 19:26:22.302461 Set Vref, RX VrefLevel [Byte0]: 71
8702 19:26:22.306057 [Byte1]: 71
8703 19:26:22.310061
8704 19:26:22.310129 Set Vref, RX VrefLevel [Byte0]: 72
8705 19:26:22.313444 [Byte1]: 72
8706 19:26:22.317657
8707 19:26:22.317728 Set Vref, RX VrefLevel [Byte0]: 73
8708 19:26:22.321186 [Byte1]: 73
8709 19:26:22.325557
8710 19:26:22.325624 Set Vref, RX VrefLevel [Byte0]: 74
8711 19:26:22.328901 [Byte1]: 74
8712 19:26:22.333231
8713 19:26:22.333359 Final RX Vref Byte 0 = 59 to rank0
8714 19:26:22.336452 Final RX Vref Byte 1 = 62 to rank0
8715 19:26:22.339448 Final RX Vref Byte 0 = 59 to rank1
8716 19:26:22.343168 Final RX Vref Byte 1 = 62 to rank1==
8717 19:26:22.346097 Dram Type= 6, Freq= 0, CH_1, rank 0
8718 19:26:22.352822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8719 19:26:22.352919 ==
8720 19:26:22.353010 DQS Delay:
8721 19:26:22.353097 DQS0 = 0, DQS1 = 0
8722 19:26:22.356681 DQM Delay:
8723 19:26:22.356780 DQM0 = 134, DQM1 = 129
8724 19:26:22.359677 DQ Delay:
8725 19:26:22.362992 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8726 19:26:22.365910 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8727 19:26:22.369418 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8728 19:26:22.372633 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8729 19:26:22.372726
8730 19:26:22.372815
8731 19:26:22.372903
8732 19:26:22.376408 [DramC_TX_OE_Calibration] TA2
8733 19:26:22.379439 Original DQ_B0 (3 6) =30, OEN = 27
8734 19:26:22.382697 Original DQ_B1 (3 6) =30, OEN = 27
8735 19:26:22.386412 24, 0x0, End_B0=24 End_B1=24
8736 19:26:22.386479 25, 0x0, End_B0=25 End_B1=25
8737 19:26:22.389356 26, 0x0, End_B0=26 End_B1=26
8738 19:26:22.392605 27, 0x0, End_B0=27 End_B1=27
8739 19:26:22.395865 28, 0x0, End_B0=28 End_B1=28
8740 19:26:22.395964 29, 0x0, End_B0=29 End_B1=29
8741 19:26:22.399517 30, 0x0, End_B0=30 End_B1=30
8742 19:26:22.402869 31, 0x4545, End_B0=30 End_B1=30
8743 19:26:22.406047 Byte0 end_step=30 best_step=27
8744 19:26:22.409060 Byte1 end_step=30 best_step=27
8745 19:26:22.412677 Byte0 TX OE(2T, 0.5T) = (3, 3)
8746 19:26:22.416085 Byte1 TX OE(2T, 0.5T) = (3, 3)
8747 19:26:22.416186
8748 19:26:22.416276
8749 19:26:22.422742 [DQSOSCAuto] RK0, (LSB)MR18= 0x1625, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8750 19:26:22.426254 CH1 RK0: MR19=303, MR18=1625
8751 19:26:22.432524 CH1_RK0: MR19=0x303, MR18=0x1625, DQSOSC=391, MR23=63, INC=24, DEC=16
8752 19:26:22.432623
8753 19:26:22.435831 ----->DramcWriteLeveling(PI) begin...
8754 19:26:22.435932 ==
8755 19:26:22.439288 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 19:26:22.442399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 19:26:22.442499 ==
8758 19:26:22.445739 Write leveling (Byte 0): 24 => 24
8759 19:26:22.449482 Write leveling (Byte 1): 28 => 28
8760 19:26:22.452319 DramcWriteLeveling(PI) end<-----
8761 19:26:22.452388
8762 19:26:22.452448 ==
8763 19:26:22.455609 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 19:26:22.459141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 19:26:22.459238 ==
8766 19:26:22.462397 [Gating] SW mode calibration
8767 19:26:22.468909 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8768 19:26:22.475626 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8769 19:26:22.478890 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 19:26:22.482366 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 19:26:22.488965 1 4 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8772 19:26:22.492099 1 4 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
8773 19:26:22.495325 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 19:26:22.502371 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 19:26:22.505536 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 19:26:22.509086 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 19:26:22.515635 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 19:26:22.518432 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 19:26:22.521853 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8780 19:26:22.528810 1 5 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 0)
8781 19:26:22.532342 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 19:26:22.535571 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 19:26:22.541912 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 19:26:22.545384 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 19:26:22.548956 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 19:26:22.555313 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8787 19:26:22.558543 1 6 8 | B1->B0 | 4141 2525 | 0 0 | (0 0) (0 0)
8788 19:26:22.562174 1 6 12 | B1->B0 | 4646 3b3b | 0 1 | (0 0) (0 0)
8789 19:26:22.568794 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 19:26:22.571819 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 19:26:22.575050 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 19:26:22.581826 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 19:26:22.585074 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 19:26:22.588546 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 19:26:22.595119 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8796 19:26:22.598590 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8797 19:26:22.601905 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 19:26:22.608338 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 19:26:22.611887 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 19:26:22.615117 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 19:26:22.618592 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 19:26:22.625325 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 19:26:22.628477 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 19:26:22.631908 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 19:26:22.638759 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 19:26:22.641657 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 19:26:22.645153 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 19:26:22.652211 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 19:26:22.655051 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 19:26:22.658481 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 19:26:22.665161 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8812 19:26:22.668432 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8813 19:26:22.671586 Total UI for P1: 0, mck2ui 16
8814 19:26:22.675038 best dqsien dly found for B1: ( 1, 9, 8)
8815 19:26:22.678472 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 19:26:22.681593 Total UI for P1: 0, mck2ui 16
8817 19:26:22.684900 best dqsien dly found for B0: ( 1, 9, 10)
8818 19:26:22.688364 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8819 19:26:22.691662 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8820 19:26:22.691731
8821 19:26:22.698239 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8822 19:26:22.701549 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8823 19:26:22.701619 [Gating] SW calibration Done
8824 19:26:22.705007 ==
8825 19:26:22.708475 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 19:26:22.711418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 19:26:22.711512 ==
8828 19:26:22.711601 RX Vref Scan: 0
8829 19:26:22.711669
8830 19:26:22.715188 RX Vref 0 -> 0, step: 1
8831 19:26:22.715284
8832 19:26:22.718547 RX Delay 0 -> 252, step: 8
8833 19:26:22.721634 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8834 19:26:22.725036 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8835 19:26:22.728322 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8836 19:26:22.734947 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8837 19:26:22.738171 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8838 19:26:22.741387 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8839 19:26:22.744648 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8840 19:26:22.748310 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8841 19:26:22.754660 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8842 19:26:22.757991 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8843 19:26:22.761496 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8844 19:26:22.765005 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8845 19:26:22.768247 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8846 19:26:22.775039 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8847 19:26:22.777892 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8848 19:26:22.781422 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8849 19:26:22.781517 ==
8850 19:26:22.785007 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 19:26:22.788154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 19:26:22.788225 ==
8853 19:26:22.791405 DQS Delay:
8854 19:26:22.791497 DQS0 = 0, DQS1 = 0
8855 19:26:22.794614 DQM Delay:
8856 19:26:22.794719 DQM0 = 136, DQM1 = 131
8857 19:26:22.798101 DQ Delay:
8858 19:26:22.800961 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8859 19:26:22.804543 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8860 19:26:22.808065 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8861 19:26:22.811061 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8862 19:26:22.811128
8863 19:26:22.811188
8864 19:26:22.811246 ==
8865 19:26:22.814306 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 19:26:22.817671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 19:26:22.817747 ==
8868 19:26:22.817811
8869 19:26:22.821059
8870 19:26:22.821155 TX Vref Scan disable
8871 19:26:22.824234 == TX Byte 0 ==
8872 19:26:22.827428 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8873 19:26:22.830908 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8874 19:26:22.834423 == TX Byte 1 ==
8875 19:26:22.837365 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8876 19:26:22.840688 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8877 19:26:22.840783 ==
8878 19:26:22.844337 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 19:26:22.850547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 19:26:22.850621 ==
8881 19:26:22.862115
8882 19:26:22.865620 TX Vref early break, caculate TX vref
8883 19:26:22.868933 TX Vref=16, minBit 8, minWin=22, winSum=383
8884 19:26:22.872721 TX Vref=18, minBit 10, minWin=22, winSum=391
8885 19:26:22.875666 TX Vref=20, minBit 9, minWin=23, winSum=397
8886 19:26:22.879096 TX Vref=22, minBit 10, minWin=23, winSum=406
8887 19:26:22.882465 TX Vref=24, minBit 12, minWin=24, winSum=415
8888 19:26:22.888859 TX Vref=26, minBit 10, minWin=24, winSum=419
8889 19:26:22.892154 TX Vref=28, minBit 9, minWin=25, winSum=426
8890 19:26:22.895649 TX Vref=30, minBit 0, minWin=25, winSum=416
8891 19:26:22.898774 TX Vref=32, minBit 10, minWin=24, winSum=406
8892 19:26:22.902384 TX Vref=34, minBit 9, minWin=24, winSum=402
8893 19:26:22.909026 [TxChooseVref] Worse bit 9, Min win 25, Win sum 426, Final Vref 28
8894 19:26:22.909098
8895 19:26:22.912292 Final TX Range 0 Vref 28
8896 19:26:22.912361
8897 19:26:22.912421 ==
8898 19:26:22.915485 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 19:26:22.918722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 19:26:22.918817 ==
8901 19:26:22.918905
8902 19:26:22.918990
8903 19:26:22.921952 TX Vref Scan disable
8904 19:26:22.928502 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8905 19:26:22.928579 == TX Byte 0 ==
8906 19:26:22.932320 u2DelayCellOfst[0]=13 cells (4 PI)
8907 19:26:22.935081 u2DelayCellOfst[1]=10 cells (3 PI)
8908 19:26:22.938594 u2DelayCellOfst[2]=0 cells (0 PI)
8909 19:26:22.941991 u2DelayCellOfst[3]=3 cells (1 PI)
8910 19:26:22.945144 u2DelayCellOfst[4]=6 cells (2 PI)
8911 19:26:22.948483 u2DelayCellOfst[5]=16 cells (5 PI)
8912 19:26:22.952048 u2DelayCellOfst[6]=16 cells (5 PI)
8913 19:26:22.955602 u2DelayCellOfst[7]=3 cells (1 PI)
8914 19:26:22.958602 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8915 19:26:22.962183 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8916 19:26:22.965565 == TX Byte 1 ==
8917 19:26:22.965633 u2DelayCellOfst[8]=0 cells (0 PI)
8918 19:26:22.968684 u2DelayCellOfst[9]=3 cells (1 PI)
8919 19:26:22.971963 u2DelayCellOfst[10]=6 cells (2 PI)
8920 19:26:22.975425 u2DelayCellOfst[11]=3 cells (1 PI)
8921 19:26:22.979128 u2DelayCellOfst[12]=13 cells (4 PI)
8922 19:26:22.981914 u2DelayCellOfst[13]=16 cells (5 PI)
8923 19:26:22.985365 u2DelayCellOfst[14]=16 cells (5 PI)
8924 19:26:22.988661 u2DelayCellOfst[15]=16 cells (5 PI)
8925 19:26:22.992192 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8926 19:26:22.998406 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8927 19:26:22.998481 DramC Write-DBI on
8928 19:26:22.998548 ==
8929 19:26:23.002073 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 19:26:23.005047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 19:26:23.008734 ==
8932 19:26:23.008801
8933 19:26:23.008861
8934 19:26:23.008919 TX Vref Scan disable
8935 19:26:23.011782 == TX Byte 0 ==
8936 19:26:23.015486 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8937 19:26:23.018948 == TX Byte 1 ==
8938 19:26:23.021901 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8939 19:26:23.025219 DramC Write-DBI off
8940 19:26:23.025348
8941 19:26:23.025415 [DATLAT]
8942 19:26:23.025512 Freq=1600, CH1 RK1
8943 19:26:23.025569
8944 19:26:23.028812 DATLAT Default: 0xf
8945 19:26:23.028884 0, 0xFFFF, sum = 0
8946 19:26:23.031976 1, 0xFFFF, sum = 0
8947 19:26:23.032071 2, 0xFFFF, sum = 0
8948 19:26:23.035073 3, 0xFFFF, sum = 0
8949 19:26:23.038503 4, 0xFFFF, sum = 0
8950 19:26:23.038574 5, 0xFFFF, sum = 0
8951 19:26:23.041872 6, 0xFFFF, sum = 0
8952 19:26:23.041939 7, 0xFFFF, sum = 0
8953 19:26:23.044964 8, 0xFFFF, sum = 0
8954 19:26:23.045048 9, 0xFFFF, sum = 0
8955 19:26:23.048610 10, 0xFFFF, sum = 0
8956 19:26:23.048677 11, 0xFFFF, sum = 0
8957 19:26:23.052083 12, 0xFFFF, sum = 0
8958 19:26:23.052152 13, 0xFFFF, sum = 0
8959 19:26:23.055043 14, 0x0, sum = 1
8960 19:26:23.055112 15, 0x0, sum = 2
8961 19:26:23.058428 16, 0x0, sum = 3
8962 19:26:23.058499 17, 0x0, sum = 4
8963 19:26:23.061696 best_step = 15
8964 19:26:23.061762
8965 19:26:23.061819 ==
8966 19:26:23.064902 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 19:26:23.068261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 19:26:23.068329 ==
8969 19:26:23.071618 RX Vref Scan: 0
8970 19:26:23.071684
8971 19:26:23.071744 RX Vref 0 -> 0, step: 1
8972 19:26:23.071802
8973 19:26:23.075112 RX Delay 19 -> 252, step: 4
8974 19:26:23.078165 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8975 19:26:23.084799 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8976 19:26:23.087984 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8977 19:26:23.091503 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8978 19:26:23.094864 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8979 19:26:23.098236 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8980 19:26:23.101412 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8981 19:26:23.108207 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8982 19:26:23.111399 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8983 19:26:23.114867 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8984 19:26:23.118208 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8985 19:26:23.121549 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8986 19:26:23.127985 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8987 19:26:23.131908 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8988 19:26:23.134944 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8989 19:26:23.137990 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8990 19:26:23.138062 ==
8991 19:26:23.141477 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 19:26:23.148116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 19:26:23.148211 ==
8994 19:26:23.148300 DQS Delay:
8995 19:26:23.151177 DQS0 = 0, DQS1 = 0
8996 19:26:23.151269 DQM Delay:
8997 19:26:23.154427 DQM0 = 133, DQM1 = 130
8998 19:26:23.154493 DQ Delay:
8999 19:26:23.158056 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9000 19:26:23.161272 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
9001 19:26:23.164410 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
9002 19:26:23.167859 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9003 19:26:23.167926
9004 19:26:23.167987
9005 19:26:23.168048
9006 19:26:23.171118 [DramC_TX_OE_Calibration] TA2
9007 19:26:23.174509 Original DQ_B0 (3 6) =30, OEN = 27
9008 19:26:23.177639 Original DQ_B1 (3 6) =30, OEN = 27
9009 19:26:23.181211 24, 0x0, End_B0=24 End_B1=24
9010 19:26:23.184559 25, 0x0, End_B0=25 End_B1=25
9011 19:26:23.184628 26, 0x0, End_B0=26 End_B1=26
9012 19:26:23.187855 27, 0x0, End_B0=27 End_B1=27
9013 19:26:23.191092 28, 0x0, End_B0=28 End_B1=28
9014 19:26:23.194031 29, 0x0, End_B0=29 End_B1=29
9015 19:26:23.194101 30, 0x0, End_B0=30 End_B1=30
9016 19:26:23.197644 31, 0x5151, End_B0=30 End_B1=30
9017 19:26:23.201003 Byte0 end_step=30 best_step=27
9018 19:26:23.204117 Byte1 end_step=30 best_step=27
9019 19:26:23.207536 Byte0 TX OE(2T, 0.5T) = (3, 3)
9020 19:26:23.210927 Byte1 TX OE(2T, 0.5T) = (3, 3)
9021 19:26:23.210993
9022 19:26:23.211052
9023 19:26:23.217464 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9024 19:26:23.220783 CH1 RK1: MR19=303, MR18=1B06
9025 19:26:23.227239 CH1_RK1: MR19=0x303, MR18=0x1B06, DQSOSC=396, MR23=63, INC=23, DEC=15
9026 19:26:23.230579 [RxdqsGatingPostProcess] freq 1600
9027 19:26:23.237087 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9028 19:26:23.237191 best DQS0 dly(2T, 0.5T) = (1, 1)
9029 19:26:23.240352 best DQS1 dly(2T, 0.5T) = (1, 1)
9030 19:26:23.244035 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9031 19:26:23.247262 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9032 19:26:23.250708 best DQS0 dly(2T, 0.5T) = (1, 1)
9033 19:26:23.253860 best DQS1 dly(2T, 0.5T) = (1, 1)
9034 19:26:23.257121 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9035 19:26:23.260635 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9036 19:26:23.263763 Pre-setting of DQS Precalculation
9037 19:26:23.267340 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9038 19:26:23.276865 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9039 19:26:23.283927 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9040 19:26:23.284025
9041 19:26:23.284115
9042 19:26:23.287102 [Calibration Summary] 3200 Mbps
9043 19:26:23.287197 CH 0, Rank 0
9044 19:26:23.290328 SW Impedance : PASS
9045 19:26:23.290399 DUTY Scan : NO K
9046 19:26:23.293748 ZQ Calibration : PASS
9047 19:26:23.296846 Jitter Meter : NO K
9048 19:26:23.296913 CBT Training : PASS
9049 19:26:23.300429 Write leveling : PASS
9050 19:26:23.303534 RX DQS gating : PASS
9051 19:26:23.303603 RX DQ/DQS(RDDQC) : PASS
9052 19:26:23.307068 TX DQ/DQS : PASS
9053 19:26:23.307161 RX DATLAT : PASS
9054 19:26:23.310547 RX DQ/DQS(Engine): PASS
9055 19:26:23.313664 TX OE : PASS
9056 19:26:23.313734 All Pass.
9057 19:26:23.313795
9058 19:26:23.313852 CH 0, Rank 1
9059 19:26:23.317013 SW Impedance : PASS
9060 19:26:23.320353 DUTY Scan : NO K
9061 19:26:23.320452 ZQ Calibration : PASS
9062 19:26:23.323557 Jitter Meter : NO K
9063 19:26:23.326995 CBT Training : PASS
9064 19:26:23.327064 Write leveling : PASS
9065 19:26:23.330208 RX DQS gating : PASS
9066 19:26:23.333549 RX DQ/DQS(RDDQC) : PASS
9067 19:26:23.333644 TX DQ/DQS : PASS
9068 19:26:23.336953 RX DATLAT : PASS
9069 19:26:23.340483 RX DQ/DQS(Engine): PASS
9070 19:26:23.340554 TX OE : PASS
9071 19:26:23.343586 All Pass.
9072 19:26:23.343683
9073 19:26:23.343772 CH 1, Rank 0
9074 19:26:23.347073 SW Impedance : PASS
9075 19:26:23.347166 DUTY Scan : NO K
9076 19:26:23.350629 ZQ Calibration : PASS
9077 19:26:23.353575 Jitter Meter : NO K
9078 19:26:23.353642 CBT Training : PASS
9079 19:26:23.357018 Write leveling : PASS
9080 19:26:23.357083 RX DQS gating : PASS
9081 19:26:23.360368 RX DQ/DQS(RDDQC) : PASS
9082 19:26:23.363952 TX DQ/DQS : PASS
9083 19:26:23.364023 RX DATLAT : PASS
9084 19:26:23.366799 RX DQ/DQS(Engine): PASS
9085 19:26:23.369918 TX OE : PASS
9086 19:26:23.369990 All Pass.
9087 19:26:23.370051
9088 19:26:23.370109 CH 1, Rank 1
9089 19:26:23.373571 SW Impedance : PASS
9090 19:26:23.376957 DUTY Scan : NO K
9091 19:26:23.377031 ZQ Calibration : PASS
9092 19:26:23.380136 Jitter Meter : NO K
9093 19:26:23.383511 CBT Training : PASS
9094 19:26:23.383579 Write leveling : PASS
9095 19:26:23.387028 RX DQS gating : PASS
9096 19:26:23.389999 RX DQ/DQS(RDDQC) : PASS
9097 19:26:23.390066 TX DQ/DQS : PASS
9098 19:26:23.393236 RX DATLAT : PASS
9099 19:26:23.397201 RX DQ/DQS(Engine): PASS
9100 19:26:23.397273 TX OE : PASS
9101 19:26:23.397379 All Pass.
9102 19:26:23.400256
9103 19:26:23.400351 DramC Write-DBI on
9104 19:26:23.403501 PER_BANK_REFRESH: Hybrid Mode
9105 19:26:23.403570 TX_TRACKING: ON
9106 19:26:23.413402 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9107 19:26:23.419986 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9108 19:26:23.429906 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9109 19:26:23.433292 [FAST_K] Save calibration result to emmc
9110 19:26:23.436594 sync common calibartion params.
9111 19:26:23.436668 sync cbt_mode0:1, 1:1
9112 19:26:23.440101 dram_init: ddr_geometry: 2
9113 19:26:23.443569 dram_init: ddr_geometry: 2
9114 19:26:23.443667 dram_init: ddr_geometry: 2
9115 19:26:23.446576 0:dram_rank_size:100000000
9116 19:26:23.450284 1:dram_rank_size:100000000
9117 19:26:23.453432 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9118 19:26:23.456817 DFS_SHUFFLE_HW_MODE: ON
9119 19:26:23.460195 dramc_set_vcore_voltage set vcore to 725000
9120 19:26:23.463241 Read voltage for 1600, 0
9121 19:26:23.463309 Vio18 = 0
9122 19:26:23.466696 Vcore = 725000
9123 19:26:23.466762 Vdram = 0
9124 19:26:23.466822 Vddq = 0
9125 19:26:23.466879 Vmddr = 0
9126 19:26:23.469789 switch to 3200 Mbps bootup
9127 19:26:23.473267 [DramcRunTimeConfig]
9128 19:26:23.473401 PHYPLL
9129 19:26:23.476761 DPM_CONTROL_AFTERK: ON
9130 19:26:23.476828 PER_BANK_REFRESH: ON
9131 19:26:23.479953 REFRESH_OVERHEAD_REDUCTION: ON
9132 19:26:23.483464 CMD_PICG_NEW_MODE: OFF
9133 19:26:23.483537 XRTWTW_NEW_MODE: ON
9134 19:26:23.486804 XRTRTR_NEW_MODE: ON
9135 19:26:23.486872 TX_TRACKING: ON
9136 19:26:23.490021 RDSEL_TRACKING: OFF
9137 19:26:23.493431 DQS Precalculation for DVFS: ON
9138 19:26:23.493500 RX_TRACKING: OFF
9139 19:26:23.493559 HW_GATING DBG: ON
9140 19:26:23.496657 ZQCS_ENABLE_LP4: ON
9141 19:26:23.499691 RX_PICG_NEW_MODE: ON
9142 19:26:23.499787 TX_PICG_NEW_MODE: ON
9143 19:26:23.502915 ENABLE_RX_DCM_DPHY: ON
9144 19:26:23.506415 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9145 19:26:23.509934 DUMMY_READ_FOR_TRACKING: OFF
9146 19:26:23.510001 !!! SPM_CONTROL_AFTERK: OFF
9147 19:26:23.513200 !!! SPM could not control APHY
9148 19:26:23.516719 IMPEDANCE_TRACKING: ON
9149 19:26:23.516793 TEMP_SENSOR: ON
9150 19:26:23.519997 HW_SAVE_FOR_SR: OFF
9151 19:26:23.522838 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9152 19:26:23.526596 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9153 19:26:23.526666 Read ODT Tracking: ON
9154 19:26:23.529553 Refresh Rate DeBounce: ON
9155 19:26:23.533186 DFS_NO_QUEUE_FLUSH: ON
9156 19:26:23.536306 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9157 19:26:23.536403 ENABLE_DFS_RUNTIME_MRW: OFF
9158 19:26:23.539690 DDR_RESERVE_NEW_MODE: ON
9159 19:26:23.542837 MR_CBT_SWITCH_FREQ: ON
9160 19:26:23.542931 =========================
9161 19:26:23.562994 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9162 19:26:23.566154 dram_init: ddr_geometry: 2
9163 19:26:23.584711 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9164 19:26:23.588082 dram_init: dram init end (result: 0)
9165 19:26:23.594400 DRAM-K: Full calibration passed in 24540 msecs
9166 19:26:23.597968 MRC: failed to locate region type 0.
9167 19:26:23.598042 DRAM rank0 size:0x100000000,
9168 19:26:23.601093 DRAM rank1 size=0x100000000
9169 19:26:23.611323 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9170 19:26:23.617546 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9171 19:26:23.624439 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9172 19:26:23.631102 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9173 19:26:23.634531 DRAM rank0 size:0x100000000,
9174 19:26:23.637932 DRAM rank1 size=0x100000000
9175 19:26:23.638031 CBMEM:
9176 19:26:23.641174 IMD: root @ 0xfffff000 254 entries.
9177 19:26:23.644254 IMD: root @ 0xffffec00 62 entries.
9178 19:26:23.647386 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9179 19:26:23.651132 WARNING: RO_VPD is uninitialized or empty.
9180 19:26:23.657572 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9181 19:26:23.664471 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9182 19:26:23.677341 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9183 19:26:23.688727 BS: romstage times (exec / console): total (unknown) / 24030 ms
9184 19:26:23.688803
9185 19:26:23.688873
9186 19:26:23.698516 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9187 19:26:23.702029 ARM64: Exception handlers installed.
9188 19:26:23.705260 ARM64: Testing exception
9189 19:26:23.708546 ARM64: Done test exception
9190 19:26:23.708615 Enumerating buses...
9191 19:26:23.711683 Show all devs... Before device enumeration.
9192 19:26:23.715251 Root Device: enabled 1
9193 19:26:23.718363 CPU_CLUSTER: 0: enabled 1
9194 19:26:23.718434 CPU: 00: enabled 1
9195 19:26:23.721588 Compare with tree...
9196 19:26:23.721660 Root Device: enabled 1
9197 19:26:23.724940 CPU_CLUSTER: 0: enabled 1
9198 19:26:23.728198 CPU: 00: enabled 1
9199 19:26:23.728267 Root Device scanning...
9200 19:26:23.731768 scan_static_bus for Root Device
9201 19:26:23.734857 CPU_CLUSTER: 0 enabled
9202 19:26:23.738274 scan_static_bus for Root Device done
9203 19:26:23.741592 scan_bus: bus Root Device finished in 8 msecs
9204 19:26:23.741692 done
9205 19:26:23.748279 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9206 19:26:23.751821 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9207 19:26:23.758363 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9208 19:26:23.761985 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9209 19:26:23.765067 Allocating resources...
9210 19:26:23.768686 Reading resources...
9211 19:26:23.771753 Root Device read_resources bus 0 link: 0
9212 19:26:23.771851 DRAM rank0 size:0x100000000,
9213 19:26:23.775231 DRAM rank1 size=0x100000000
9214 19:26:23.778261 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9215 19:26:23.781606 CPU: 00 missing read_resources
9216 19:26:23.785144 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9217 19:26:23.791696 Root Device read_resources bus 0 link: 0 done
9218 19:26:23.791794 Done reading resources.
9219 19:26:23.798007 Show resources in subtree (Root Device)...After reading.
9220 19:26:23.801537 Root Device child on link 0 CPU_CLUSTER: 0
9221 19:26:23.804777 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 19:26:23.814538 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 19:26:23.814618 CPU: 00
9224 19:26:23.817787 Root Device assign_resources, bus 0 link: 0
9225 19:26:23.821519 CPU_CLUSTER: 0 missing set_resources
9226 19:26:23.828190 Root Device assign_resources, bus 0 link: 0 done
9227 19:26:23.828290 Done setting resources.
9228 19:26:23.834523 Show resources in subtree (Root Device)...After assigning values.
9229 19:26:23.837933 Root Device child on link 0 CPU_CLUSTER: 0
9230 19:26:23.841113 CPU_CLUSTER: 0 child on link 0 CPU: 00
9231 19:26:23.851121 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9232 19:26:23.851222 CPU: 00
9233 19:26:23.854481 Done allocating resources.
9234 19:26:23.861015 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9235 19:26:23.861097 Enabling resources...
9236 19:26:23.861196 done.
9237 19:26:23.867347 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9238 19:26:23.867467 Initializing devices...
9239 19:26:23.870722 Root Device init
9240 19:26:23.870821 init hardware done!
9241 19:26:23.874018 0x00000018: ctrlr->caps
9242 19:26:23.877406 52.000 MHz: ctrlr->f_max
9243 19:26:23.877475 0.400 MHz: ctrlr->f_min
9244 19:26:23.880573 0x40ff8080: ctrlr->voltages
9245 19:26:23.883751 sclk: 390625
9246 19:26:23.883845 Bus Width = 1
9247 19:26:23.883934 sclk: 390625
9248 19:26:23.887109 Bus Width = 1
9249 19:26:23.887204 Early init status = 3
9250 19:26:23.893903 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9251 19:26:23.897206 in-header: 03 fc 00 00 01 00 00 00
9252 19:26:23.900387 in-data: 00
9253 19:26:23.903952 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9254 19:26:23.909263 in-header: 03 fd 00 00 00 00 00 00
9255 19:26:23.912448 in-data:
9256 19:26:23.916117 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9257 19:26:23.920476 in-header: 03 fc 00 00 01 00 00 00
9258 19:26:23.923813 in-data: 00
9259 19:26:23.926965 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9260 19:26:23.932384 in-header: 03 fd 00 00 00 00 00 00
9261 19:26:23.935800 in-data:
9262 19:26:23.939118 [SSUSB] Setting up USB HOST controller...
9263 19:26:23.942337 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9264 19:26:23.945496 [SSUSB] phy power-on done.
9265 19:26:23.948967 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9266 19:26:23.955728 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9267 19:26:23.959034 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9268 19:26:23.965789 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9269 19:26:23.972373 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9270 19:26:23.978948 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9271 19:26:23.985660 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9272 19:26:23.992662 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9273 19:26:23.995715 SPM: binary array size = 0x9dc
9274 19:26:23.998964 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9275 19:26:24.005431 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9276 19:26:24.012267 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9277 19:26:24.015419 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9278 19:26:24.022280 configure_display: Starting display init
9279 19:26:24.055661 anx7625_power_on_init: Init interface.
9280 19:26:24.059286 anx7625_disable_pd_protocol: Disabled PD feature.
9281 19:26:24.062633 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9282 19:26:24.090402 anx7625_start_dp_work: Secure OCM version=00
9283 19:26:24.093310 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9284 19:26:24.108589 sp_tx_get_edid_block: EDID Block = 1
9285 19:26:24.210905 Extracted contents:
9286 19:26:24.214479 header: 00 ff ff ff ff ff ff 00
9287 19:26:24.217898 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9288 19:26:24.220928 version: 01 04
9289 19:26:24.224378 basic params: 95 1f 11 78 0a
9290 19:26:24.227599 chroma info: 76 90 94 55 54 90 27 21 50 54
9291 19:26:24.230898 established: 00 00 00
9292 19:26:24.237396 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9293 19:26:24.240763 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9294 19:26:24.247514 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9295 19:26:24.253923 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9296 19:26:24.260613 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9297 19:26:24.264398 extensions: 00
9298 19:26:24.264496 checksum: fb
9299 19:26:24.264587
9300 19:26:24.267629 Manufacturer: IVO Model 57d Serial Number 0
9301 19:26:24.270491 Made week 0 of 2020
9302 19:26:24.270558 EDID version: 1.4
9303 19:26:24.274168 Digital display
9304 19:26:24.277486 6 bits per primary color channel
9305 19:26:24.277564 DisplayPort interface
9306 19:26:24.280593 Maximum image size: 31 cm x 17 cm
9307 19:26:24.283756 Gamma: 220%
9308 19:26:24.283848 Check DPMS levels
9309 19:26:24.287487 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9310 19:26:24.290664 First detailed timing is preferred timing
9311 19:26:24.293947 Established timings supported:
9312 19:26:24.297203 Standard timings supported:
9313 19:26:24.300427 Detailed timings
9314 19:26:24.303700 Hex of detail: 383680a07038204018303c0035ae10000019
9315 19:26:24.307374 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9316 19:26:24.313741 0780 0798 07c8 0820 hborder 0
9317 19:26:24.317101 0438 043b 0447 0458 vborder 0
9318 19:26:24.320451 -hsync -vsync
9319 19:26:24.320518 Did detailed timing
9320 19:26:24.323740 Hex of detail: 000000000000000000000000000000000000
9321 19:26:24.327040 Manufacturer-specified data, tag 0
9322 19:26:24.333791 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9323 19:26:24.333887 ASCII string: InfoVision
9324 19:26:24.340617 Hex of detail: 000000fe00523134304e574635205248200a
9325 19:26:24.343725 ASCII string: R140NWF5 RH
9326 19:26:24.343821 Checksum
9327 19:26:24.343912 Checksum: 0xfb (valid)
9328 19:26:24.350599 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9329 19:26:24.353694 DSI data_rate: 832800000 bps
9330 19:26:24.356913 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9331 19:26:24.363561 anx7625_parse_edid: pixelclock(138800).
9332 19:26:24.366916 hactive(1920), hsync(48), hfp(24), hbp(88)
9333 19:26:24.370643 vactive(1080), vsync(12), vfp(3), vbp(17)
9334 19:26:24.373462 anx7625_dsi_config: config dsi.
9335 19:26:24.379964 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9336 19:26:24.392664 anx7625_dsi_config: success to config DSI
9337 19:26:24.395876 anx7625_dp_start: MIPI phy setup OK.
9338 19:26:24.399434 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9339 19:26:24.403222 mtk_ddp_mode_set invalid vrefresh 60
9340 19:26:24.406086 main_disp_path_setup
9341 19:26:24.406152 ovl_layer_smi_id_en
9342 19:26:24.409426 ovl_layer_smi_id_en
9343 19:26:24.409497 ccorr_config
9344 19:26:24.409561 aal_config
9345 19:26:24.412964 gamma_config
9346 19:26:24.413054 postmask_config
9347 19:26:24.416306 dither_config
9348 19:26:24.419386 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9349 19:26:24.426307 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9350 19:26:24.429571 Root Device init finished in 555 msecs
9351 19:26:24.432672 CPU_CLUSTER: 0 init
9352 19:26:24.439472 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9353 19:26:24.442746 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9354 19:26:24.445937 APU_MBOX 0x190000b0 = 0x10001
9355 19:26:24.449198 APU_MBOX 0x190001b0 = 0x10001
9356 19:26:24.452543 APU_MBOX 0x190005b0 = 0x10001
9357 19:26:24.455721 APU_MBOX 0x190006b0 = 0x10001
9358 19:26:24.458978 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9359 19:26:24.472072 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9360 19:26:24.484022 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9361 19:26:24.490935 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9362 19:26:24.502378 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9363 19:26:24.511785 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9364 19:26:24.514947 CPU_CLUSTER: 0 init finished in 81 msecs
9365 19:26:24.518387 Devices initialized
9366 19:26:24.521501 Show all devs... After init.
9367 19:26:24.521620 Root Device: enabled 1
9368 19:26:24.524982 CPU_CLUSTER: 0: enabled 1
9369 19:26:24.528437 CPU: 00: enabled 1
9370 19:26:24.531511 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9371 19:26:24.534822 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9372 19:26:24.538131 ELOG: NV offset 0x57f000 size 0x1000
9373 19:26:24.545173 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9374 19:26:24.551524 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9375 19:26:24.554523 ELOG: Event(17) added with size 13 at 2024-04-18 19:25:11 UTC
9376 19:26:24.561234 out: cmd=0x121: 03 db 21 01 00 00 00 00
9377 19:26:24.564628 in-header: 03 08 00 00 2c 00 00 00
9378 19:26:24.574668 in-data: 57 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9379 19:26:24.580939 ELOG: Event(A1) added with size 10 at 2024-04-18 19:25:11 UTC
9380 19:26:24.587579 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9381 19:26:24.594497 ELOG: Event(A0) added with size 9 at 2024-04-18 19:25:11 UTC
9382 19:26:24.597532 elog_add_boot_reason: Logged dev mode boot
9383 19:26:24.604534 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9384 19:26:24.604609 Finalize devices...
9385 19:26:24.607385 Devices finalized
9386 19:26:24.611072 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9387 19:26:24.614309 Writing coreboot table at 0xffe64000
9388 19:26:24.617769 0. 000000000010a000-0000000000113fff: RAMSTAGE
9389 19:26:24.621063 1. 0000000040000000-00000000400fffff: RAM
9390 19:26:24.627249 2. 0000000040100000-000000004032afff: RAMSTAGE
9391 19:26:24.630932 3. 000000004032b000-00000000545fffff: RAM
9392 19:26:24.634091 4. 0000000054600000-000000005465ffff: BL31
9393 19:26:24.637826 5. 0000000054660000-00000000ffe63fff: RAM
9394 19:26:24.644014 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9395 19:26:24.647560 7. 0000000100000000-000000023fffffff: RAM
9396 19:26:24.650642 Passing 5 GPIOs to payload:
9397 19:26:24.653896 NAME | PORT | POLARITY | VALUE
9398 19:26:24.657211 EC in RW | 0x000000aa | low | undefined
9399 19:26:24.663944 EC interrupt | 0x00000005 | low | undefined
9400 19:26:24.667367 TPM interrupt | 0x000000ab | high | undefined
9401 19:26:24.674097 SD card detect | 0x00000011 | high | undefined
9402 19:26:24.677407 speaker enable | 0x00000093 | high | undefined
9403 19:26:24.680271 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9404 19:26:24.683607 in-header: 03 f9 00 00 02 00 00 00
9405 19:26:24.687199 in-data: 02 00
9406 19:26:24.687298 ADC[4]: Raw value=900295 ID=7
9407 19:26:24.690355 ADC[3]: Raw value=212810 ID=1
9408 19:26:24.693678 RAM Code: 0x71
9409 19:26:24.696842 ADC[6]: Raw value=74502 ID=0
9410 19:26:24.696913 ADC[5]: Raw value=212441 ID=1
9411 19:26:24.700519 SKU Code: 0x1
9412 19:26:24.703537 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7bd6
9413 19:26:24.707424 coreboot table: 964 bytes.
9414 19:26:24.710216 IMD ROOT 0. 0xfffff000 0x00001000
9415 19:26:24.713454 IMD SMALL 1. 0xffffe000 0x00001000
9416 19:26:24.716950 RO MCACHE 2. 0xffffc000 0x00001104
9417 19:26:24.720298 CONSOLE 3. 0xfff7c000 0x00080000
9418 19:26:24.723492 FMAP 4. 0xfff7b000 0x00000452
9419 19:26:24.726960 TIME STAMP 5. 0xfff7a000 0x00000910
9420 19:26:24.729981 VBOOT WORK 6. 0xfff66000 0x00014000
9421 19:26:24.733416 RAMOOPS 7. 0xffe66000 0x00100000
9422 19:26:24.736640 COREBOOT 8. 0xffe64000 0x00002000
9423 19:26:24.740218 IMD small region:
9424 19:26:24.743404 IMD ROOT 0. 0xffffec00 0x00000400
9425 19:26:24.746698 VPD 1. 0xffffeb80 0x0000006c
9426 19:26:24.749840 MMC STATUS 2. 0xffffeb60 0x00000004
9427 19:26:24.753550 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9428 19:26:24.756783 Probing TPM: done!
9429 19:26:24.760399 Connected to device vid:did:rid of 1ae0:0028:00
9430 19:26:24.770764 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9431 19:26:24.773965 Initialized TPM device CR50 revision 0
9432 19:26:24.777459 Checking cr50 for pending updates
9433 19:26:24.781110 Reading cr50 TPM mode
9434 19:26:24.790180 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9435 19:26:24.796562 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9436 19:26:24.836651 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9437 19:26:24.839744 Checking segment from ROM address 0x40100000
9438 19:26:24.843308 Checking segment from ROM address 0x4010001c
9439 19:26:24.849888 Loading segment from ROM address 0x40100000
9440 19:26:24.849961 code (compression=0)
9441 19:26:24.860226 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9442 19:26:24.866494 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9443 19:26:24.866573 it's not compressed!
9444 19:26:24.873168 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9445 19:26:24.876648 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9446 19:26:24.897094 Loading segment from ROM address 0x4010001c
9447 19:26:24.897170 Entry Point 0x80000000
9448 19:26:24.900441 Loaded segments
9449 19:26:24.903562 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9450 19:26:24.910645 Jumping to boot code at 0x80000000(0xffe64000)
9451 19:26:24.916976 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9452 19:26:24.924049 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9453 19:26:24.931676 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9454 19:26:24.935160 Checking segment from ROM address 0x40100000
9455 19:26:24.938143 Checking segment from ROM address 0x4010001c
9456 19:26:24.945009 Loading segment from ROM address 0x40100000
9457 19:26:24.945109 code (compression=1)
9458 19:26:24.951594 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9459 19:26:24.961457 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9460 19:26:24.961556 using LZMA
9461 19:26:24.969893 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9462 19:26:24.976576 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9463 19:26:24.980113 Loading segment from ROM address 0x4010001c
9464 19:26:24.980210 Entry Point 0x54601000
9465 19:26:24.983195 Loaded segments
9466 19:26:24.986570 NOTICE: MT8192 bl31_setup
9467 19:26:24.993660 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9468 19:26:24.997046 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9469 19:26:25.000532 WARNING: region 0:
9470 19:26:25.003580 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 19:26:25.003680 WARNING: region 1:
9472 19:26:25.010404 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9473 19:26:25.013500 WARNING: region 2:
9474 19:26:25.017159 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9475 19:26:25.020451 WARNING: region 3:
9476 19:26:25.023423 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 19:26:25.026626 WARNING: region 4:
9478 19:26:25.033289 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 19:26:25.033416 WARNING: region 5:
9480 19:26:25.036632 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 19:26:25.039863 WARNING: region 6:
9482 19:26:25.043488 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 19:26:25.046935 WARNING: region 7:
9484 19:26:25.050208 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 19:26:25.056611 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9486 19:26:25.060333 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9487 19:26:25.063158 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9488 19:26:25.069804 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9489 19:26:25.073374 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9490 19:26:25.077109 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9491 19:26:25.083407 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9492 19:26:25.086893 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9493 19:26:25.093391 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9494 19:26:25.097015 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9495 19:26:25.099937 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9496 19:26:25.107071 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9497 19:26:25.110399 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9498 19:26:25.113255 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9499 19:26:25.120252 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9500 19:26:25.123558 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9501 19:26:25.130285 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9502 19:26:25.133568 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9503 19:26:25.137049 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9504 19:26:25.143403 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9505 19:26:25.146649 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9506 19:26:25.150300 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9507 19:26:25.156851 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9508 19:26:25.160181 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9509 19:26:25.166636 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9510 19:26:25.169633 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9511 19:26:25.173034 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9512 19:26:25.179701 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9513 19:26:25.183491 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9514 19:26:25.189811 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9515 19:26:25.193252 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9516 19:26:25.196414 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9517 19:26:25.202995 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9518 19:26:25.206703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9519 19:26:25.209928 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9520 19:26:25.212882 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9521 19:26:25.219657 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9522 19:26:25.223260 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9523 19:26:25.226490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9524 19:26:25.229901 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9525 19:26:25.236562 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9526 19:26:25.239678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9527 19:26:25.243204 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9528 19:26:25.246620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9529 19:26:25.253290 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9530 19:26:25.256490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9531 19:26:25.259926 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9532 19:26:25.263568 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9533 19:26:25.270241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9534 19:26:25.273077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9535 19:26:25.279878 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9536 19:26:25.283213 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9537 19:26:25.286856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9538 19:26:25.293242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9539 19:26:25.296543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9540 19:26:25.303489 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9541 19:26:25.306489 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9542 19:26:25.313374 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9543 19:26:25.316659 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9544 19:26:25.319760 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9545 19:26:25.326764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9546 19:26:25.329888 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9547 19:26:25.336587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9548 19:26:25.340249 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9549 19:26:25.346736 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9550 19:26:25.349781 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9551 19:26:25.356551 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9552 19:26:25.360325 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9553 19:26:25.363530 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9554 19:26:25.370057 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9555 19:26:25.373189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9556 19:26:25.380037 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9557 19:26:25.383115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9558 19:26:25.386386 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9559 19:26:25.393551 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9560 19:26:25.396803 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9561 19:26:25.403249 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9562 19:26:25.406566 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9563 19:26:25.413203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9564 19:26:25.416465 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9565 19:26:25.423484 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9566 19:26:25.426702 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9567 19:26:25.429910 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9568 19:26:25.436673 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9569 19:26:25.439989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9570 19:26:25.446637 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9571 19:26:25.450259 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9572 19:26:25.456899 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9573 19:26:25.460101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9574 19:26:25.463220 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9575 19:26:25.470322 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9576 19:26:25.473896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9577 19:26:25.480361 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9578 19:26:25.483357 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9579 19:26:25.490448 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9580 19:26:25.493784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9581 19:26:25.496948 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9582 19:26:25.503344 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9583 19:26:25.506784 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9584 19:26:25.509978 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9585 19:26:25.513407 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9586 19:26:25.520059 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9587 19:26:25.523753 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9588 19:26:25.530275 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9589 19:26:25.533478 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9590 19:26:25.536669 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9591 19:26:25.543580 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9592 19:26:25.546828 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9593 19:26:25.553785 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9594 19:26:25.557118 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9595 19:26:25.560478 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9596 19:26:25.566967 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9597 19:26:25.570340 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9598 19:26:25.573882 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9599 19:26:25.580555 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9600 19:26:25.583610 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9601 19:26:25.587172 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9602 19:26:25.593539 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9603 19:26:25.597511 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9604 19:26:25.600394 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9605 19:26:25.607094 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9606 19:26:25.610357 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9607 19:26:25.614078 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9608 19:26:25.617181 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9609 19:26:25.623848 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9610 19:26:25.627336 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9611 19:26:25.630286 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9612 19:26:25.636973 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9613 19:26:25.640726 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9614 19:26:25.647361 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9615 19:26:25.650571 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9616 19:26:25.653969 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9617 19:26:25.660379 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9618 19:26:25.663852 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9619 19:26:25.670703 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9620 19:26:25.674127 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9621 19:26:25.677034 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9622 19:26:25.684112 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9623 19:26:25.687139 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9624 19:26:25.690566 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9625 19:26:25.696975 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9626 19:26:25.700391 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9627 19:26:25.707186 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9628 19:26:25.710241 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9629 19:26:25.713728 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9630 19:26:25.720547 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9631 19:26:25.723903 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9632 19:26:25.730307 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9633 19:26:25.733567 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9634 19:26:25.737205 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9635 19:26:25.743846 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9636 19:26:25.746926 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9637 19:26:25.753764 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9638 19:26:25.756818 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9639 19:26:25.760562 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9640 19:26:25.767031 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9641 19:26:25.770124 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9642 19:26:25.773881 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9643 19:26:25.780316 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9644 19:26:25.783902 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9645 19:26:25.790637 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9646 19:26:25.793596 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9647 19:26:25.796843 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9648 19:26:25.803611 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9649 19:26:25.807186 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9650 19:26:25.813820 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9651 19:26:25.816940 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9652 19:26:25.819957 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9653 19:26:25.826785 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9654 19:26:25.830104 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9655 19:26:25.837023 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9656 19:26:25.839933 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9657 19:26:25.843503 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9658 19:26:25.850330 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9659 19:26:25.853490 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9660 19:26:25.856896 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9661 19:26:25.863445 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9662 19:26:25.866535 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9663 19:26:25.873427 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9664 19:26:25.876518 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9665 19:26:25.880171 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9666 19:26:25.886694 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9667 19:26:25.890029 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9668 19:26:25.896788 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9669 19:26:25.899994 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9670 19:26:25.903178 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9671 19:26:25.909716 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9672 19:26:25.913386 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9673 19:26:25.919890 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9674 19:26:25.923158 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9675 19:26:25.926268 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9676 19:26:25.932826 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9677 19:26:25.936320 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9678 19:26:25.942913 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9679 19:26:25.945958 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9680 19:26:25.952987 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9681 19:26:25.955748 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9682 19:26:25.959195 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9683 19:26:25.965990 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9684 19:26:25.969335 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9685 19:26:25.975848 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9686 19:26:25.979358 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9687 19:26:25.985807 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9688 19:26:25.988827 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9689 19:26:25.992355 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9690 19:26:25.998881 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9691 19:26:26.001909 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9692 19:26:26.008672 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9693 19:26:26.011727 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9694 19:26:26.018430 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9695 19:26:26.021670 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9696 19:26:26.025184 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9697 19:26:26.032123 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9698 19:26:26.034881 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9699 19:26:26.042100 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9700 19:26:26.045166 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9701 19:26:26.048414 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9702 19:26:26.055178 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9703 19:26:26.058358 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9704 19:26:26.064803 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9705 19:26:26.068125 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9706 19:26:26.074749 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9707 19:26:26.078076 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9708 19:26:26.081580 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9709 19:26:26.088123 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9710 19:26:26.091887 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9711 19:26:26.098142 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9712 19:26:26.102000 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9713 19:26:26.105355 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9714 19:26:26.111566 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9715 19:26:26.114995 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9716 19:26:26.118372 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9717 19:26:26.121478 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9718 19:26:26.125176 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9719 19:26:26.131575 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9720 19:26:26.134752 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9721 19:26:26.141502 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9722 19:26:26.144774 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9723 19:26:26.148150 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9724 19:26:26.154895 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9725 19:26:26.157956 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9726 19:26:26.164431 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9727 19:26:26.167953 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9728 19:26:26.171281 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9729 19:26:26.177813 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9730 19:26:26.181174 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9731 19:26:26.184499 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9732 19:26:26.191261 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9733 19:26:26.194630 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9734 19:26:26.197985 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9735 19:26:26.204312 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9736 19:26:26.207772 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9737 19:26:26.214620 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9738 19:26:26.217878 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9739 19:26:26.220981 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9740 19:26:26.227668 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9741 19:26:26.231007 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9742 19:26:26.234112 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9743 19:26:26.240854 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9744 19:26:26.244333 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9745 19:26:26.250828 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9746 19:26:26.253855 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9747 19:26:26.257554 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9748 19:26:26.264120 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9749 19:26:26.267435 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9750 19:26:26.270679 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9751 19:26:26.277595 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9752 19:26:26.280951 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9753 19:26:26.283952 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9754 19:26:26.290485 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9755 19:26:26.293718 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9756 19:26:26.297178 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9757 19:26:26.300420 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9758 19:26:26.303846 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9759 19:26:26.310604 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9760 19:26:26.314197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9761 19:26:26.317224 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9762 19:26:26.320500 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9763 19:26:26.327538 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9764 19:26:26.330828 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9765 19:26:26.333709 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9766 19:26:26.340399 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9767 19:26:26.343836 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9768 19:26:26.347177 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9769 19:26:26.353937 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9770 19:26:26.356934 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9771 19:26:26.363859 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9772 19:26:26.366883 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9773 19:26:26.373770 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9774 19:26:26.376787 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9775 19:26:26.380106 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9776 19:26:26.386750 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9777 19:26:26.390466 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9778 19:26:26.396816 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9779 19:26:26.400314 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9780 19:26:26.403530 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9781 19:26:26.409974 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9782 19:26:26.413594 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9783 19:26:26.420496 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9784 19:26:26.423896 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9785 19:26:26.426906 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9786 19:26:26.433521 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9787 19:26:26.436519 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9788 19:26:26.443156 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9789 19:26:26.446869 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9790 19:26:26.450052 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9791 19:26:26.456317 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9792 19:26:26.460070 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9793 19:26:26.466593 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9794 19:26:26.469752 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9795 19:26:26.476415 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9796 19:26:26.479806 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9797 19:26:26.482707 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9798 19:26:26.489665 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9799 19:26:26.492867 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9800 19:26:26.499616 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9801 19:26:26.502976 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9802 19:26:26.506104 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9803 19:26:26.512809 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9804 19:26:26.516263 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9805 19:26:26.522495 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9806 19:26:26.525927 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9807 19:26:26.529364 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9808 19:26:26.536166 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9809 19:26:26.539483 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9810 19:26:26.545882 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9811 19:26:26.548657 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9812 19:26:26.555743 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9813 19:26:26.559092 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9814 19:26:26.562375 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9815 19:26:26.568885 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9816 19:26:26.572209 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9817 19:26:26.578622 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9818 19:26:26.582095 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9819 19:26:26.585585 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9820 19:26:26.592544 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9821 19:26:26.595610 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9822 19:26:26.599276 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9823 19:26:26.605569 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9824 19:26:26.608915 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9825 19:26:26.615569 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9826 19:26:26.618895 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9827 19:26:26.625484 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9828 19:26:26.629047 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9829 19:26:26.631950 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9830 19:26:26.638660 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9831 19:26:26.641923 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9832 19:26:26.648419 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9833 19:26:26.652002 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9834 19:26:26.655555 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9835 19:26:26.662119 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9836 19:26:26.665339 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9837 19:26:26.671898 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9838 19:26:26.675475 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9839 19:26:26.678821 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9840 19:26:26.685084 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9841 19:26:26.688473 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9842 19:26:26.695006 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9843 19:26:26.698801 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9844 19:26:26.704740 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9845 19:26:26.708074 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9846 19:26:26.714679 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9847 19:26:26.718151 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9848 19:26:26.721235 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9849 19:26:26.727963 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9850 19:26:26.731271 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9851 19:26:26.738346 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9852 19:26:26.741338 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9853 19:26:26.748180 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9854 19:26:26.751758 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9855 19:26:26.754925 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9856 19:26:26.761571 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9857 19:26:26.764772 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9858 19:26:26.771310 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9859 19:26:26.774843 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9860 19:26:26.781546 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9861 19:26:26.784710 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9862 19:26:26.788128 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9863 19:26:26.794696 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9864 19:26:26.797938 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9865 19:26:26.804496 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9866 19:26:26.807833 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9867 19:26:26.814732 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9868 19:26:26.817913 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9869 19:26:26.824808 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9870 19:26:26.828001 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9871 19:26:26.831264 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9872 19:26:26.837774 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9873 19:26:26.840837 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9874 19:26:26.847649 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9875 19:26:26.851059 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9876 19:26:26.857393 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9877 19:26:26.860717 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9878 19:26:26.864034 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9879 19:26:26.870669 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9880 19:26:26.873996 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9881 19:26:26.880653 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9882 19:26:26.884209 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9883 19:26:26.890565 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9884 19:26:26.893894 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9885 19:26:26.900578 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9886 19:26:26.903840 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9887 19:26:26.907240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9888 19:26:26.913934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9889 19:26:26.917292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9890 19:26:26.923555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9891 19:26:26.927254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9892 19:26:26.933923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9893 19:26:26.937181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9894 19:26:26.943758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9895 19:26:26.947124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9896 19:26:26.953772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9897 19:26:26.956906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9898 19:26:26.963646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9899 19:26:26.966744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9900 19:26:26.970604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9901 19:26:26.976990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9902 19:26:26.980396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9903 19:26:26.986931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9904 19:26:26.990105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9905 19:26:26.996762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9906 19:26:27.000096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9907 19:26:27.006959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9908 19:26:27.010151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9909 19:26:27.016608 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9910 19:26:27.020010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9911 19:26:27.026388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9912 19:26:27.029703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9913 19:26:27.036456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9914 19:26:27.039637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9915 19:26:27.046786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9916 19:26:27.050214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9917 19:26:27.056501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9918 19:26:27.059704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9919 19:26:27.066228 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9920 19:26:27.066312 INFO: [APUAPC] vio 0
9921 19:26:27.073462 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9922 19:26:27.076596 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9923 19:26:27.080439 INFO: [APUAPC] D0_APC_0: 0x400510
9924 19:26:27.083187 INFO: [APUAPC] D0_APC_1: 0x0
9925 19:26:27.086789 INFO: [APUAPC] D0_APC_2: 0x1540
9926 19:26:27.089944 INFO: [APUAPC] D0_APC_3: 0x0
9927 19:26:27.093448 INFO: [APUAPC] D1_APC_0: 0xffffffff
9928 19:26:27.096621 INFO: [APUAPC] D1_APC_1: 0xffffffff
9929 19:26:27.100021 INFO: [APUAPC] D1_APC_2: 0x3fffff
9930 19:26:27.103135 INFO: [APUAPC] D1_APC_3: 0x0
9931 19:26:27.107147 INFO: [APUAPC] D2_APC_0: 0xffffffff
9932 19:26:27.109829 INFO: [APUAPC] D2_APC_1: 0xffffffff
9933 19:26:27.113019 INFO: [APUAPC] D2_APC_2: 0x3fffff
9934 19:26:27.116255 INFO: [APUAPC] D2_APC_3: 0x0
9935 19:26:27.119644 INFO: [APUAPC] D3_APC_0: 0xffffffff
9936 19:26:27.123068 INFO: [APUAPC] D3_APC_1: 0xffffffff
9937 19:26:27.126559 INFO: [APUAPC] D3_APC_2: 0x3fffff
9938 19:26:27.129965 INFO: [APUAPC] D3_APC_3: 0x0
9939 19:26:27.133242 INFO: [APUAPC] D4_APC_0: 0xffffffff
9940 19:26:27.136211 INFO: [APUAPC] D4_APC_1: 0xffffffff
9941 19:26:27.139810 INFO: [APUAPC] D4_APC_2: 0x3fffff
9942 19:26:27.139893 INFO: [APUAPC] D4_APC_3: 0x0
9943 19:26:27.143148 INFO: [APUAPC] D5_APC_0: 0xffffffff
9944 19:26:27.149528 INFO: [APUAPC] D5_APC_1: 0xffffffff
9945 19:26:27.152926 INFO: [APUAPC] D5_APC_2: 0x3fffff
9946 19:26:27.153010 INFO: [APUAPC] D5_APC_3: 0x0
9947 19:26:27.156257 INFO: [APUAPC] D6_APC_0: 0xffffffff
9948 19:26:27.159687 INFO: [APUAPC] D6_APC_1: 0xffffffff
9949 19:26:27.162680 INFO: [APUAPC] D6_APC_2: 0x3fffff
9950 19:26:27.166660 INFO: [APUAPC] D6_APC_3: 0x0
9951 19:26:27.169422 INFO: [APUAPC] D7_APC_0: 0xffffffff
9952 19:26:27.173002 INFO: [APUAPC] D7_APC_1: 0xffffffff
9953 19:26:27.176075 INFO: [APUAPC] D7_APC_2: 0x3fffff
9954 19:26:27.179470 INFO: [APUAPC] D7_APC_3: 0x0
9955 19:26:27.182900 INFO: [APUAPC] D8_APC_0: 0xffffffff
9956 19:26:27.186570 INFO: [APUAPC] D8_APC_1: 0xffffffff
9957 19:26:27.189617 INFO: [APUAPC] D8_APC_2: 0x3fffff
9958 19:26:27.193102 INFO: [APUAPC] D8_APC_3: 0x0
9959 19:26:27.196471 INFO: [APUAPC] D9_APC_0: 0xffffffff
9960 19:26:27.199537 INFO: [APUAPC] D9_APC_1: 0xffffffff
9961 19:26:27.203065 INFO: [APUAPC] D9_APC_2: 0x3fffff
9962 19:26:27.206507 INFO: [APUAPC] D9_APC_3: 0x0
9963 19:26:27.209459 INFO: [APUAPC] D10_APC_0: 0xffffffff
9964 19:26:27.213494 INFO: [APUAPC] D10_APC_1: 0xffffffff
9965 19:26:27.215948 INFO: [APUAPC] D10_APC_2: 0x3fffff
9966 19:26:27.219498 INFO: [APUAPC] D10_APC_3: 0x0
9967 19:26:27.222712 INFO: [APUAPC] D11_APC_0: 0xffffffff
9968 19:26:27.226146 INFO: [APUAPC] D11_APC_1: 0xffffffff
9969 19:26:27.229479 INFO: [APUAPC] D11_APC_2: 0x3fffff
9970 19:26:27.232911 INFO: [APUAPC] D11_APC_3: 0x0
9971 19:26:27.236095 INFO: [APUAPC] D12_APC_0: 0xffffffff
9972 19:26:27.239583 INFO: [APUAPC] D12_APC_1: 0xffffffff
9973 19:26:27.242676 INFO: [APUAPC] D12_APC_2: 0x3fffff
9974 19:26:27.246076 INFO: [APUAPC] D12_APC_3: 0x0
9975 19:26:27.249550 INFO: [APUAPC] D13_APC_0: 0xffffffff
9976 19:26:27.252438 INFO: [APUAPC] D13_APC_1: 0xffffffff
9977 19:26:27.255701 INFO: [APUAPC] D13_APC_2: 0x3fffff
9978 19:26:27.259082 INFO: [APUAPC] D13_APC_3: 0x0
9979 19:26:27.262380 INFO: [APUAPC] D14_APC_0: 0xffffffff
9980 19:26:27.265846 INFO: [APUAPC] D14_APC_1: 0xffffffff
9981 19:26:27.268980 INFO: [APUAPC] D14_APC_2: 0x3fffff
9982 19:26:27.272183 INFO: [APUAPC] D14_APC_3: 0x0
9983 19:26:27.275433 INFO: [APUAPC] D15_APC_0: 0xffffffff
9984 19:26:27.279004 INFO: [APUAPC] D15_APC_1: 0xffffffff
9985 19:26:27.282027 INFO: [APUAPC] D15_APC_2: 0x3fffff
9986 19:26:27.285581 INFO: [APUAPC] D15_APC_3: 0x0
9987 19:26:27.288808 INFO: [APUAPC] APC_CON: 0x4
9988 19:26:27.292088 INFO: [NOCDAPC] D0_APC_0: 0x0
9989 19:26:27.295341 INFO: [NOCDAPC] D0_APC_1: 0x0
9990 19:26:27.299010 INFO: [NOCDAPC] D1_APC_0: 0x0
9991 19:26:27.302271 INFO: [NOCDAPC] D1_APC_1: 0xfff
9992 19:26:27.305637 INFO: [NOCDAPC] D2_APC_0: 0x0
9993 19:26:27.308788 INFO: [NOCDAPC] D2_APC_1: 0xfff
9994 19:26:27.308871 INFO: [NOCDAPC] D3_APC_0: 0x0
9995 19:26:27.311812 INFO: [NOCDAPC] D3_APC_1: 0xfff
9996 19:26:27.315350 INFO: [NOCDAPC] D4_APC_0: 0x0
9997 19:26:27.318382 INFO: [NOCDAPC] D4_APC_1: 0xfff
9998 19:26:27.322011 INFO: [NOCDAPC] D5_APC_0: 0x0
9999 19:26:27.325453 INFO: [NOCDAPC] D5_APC_1: 0xfff
10000 19:26:27.328393 INFO: [NOCDAPC] D6_APC_0: 0x0
10001 19:26:27.332021 INFO: [NOCDAPC] D6_APC_1: 0xfff
10002 19:26:27.335762 INFO: [NOCDAPC] D7_APC_0: 0x0
10003 19:26:27.338621 INFO: [NOCDAPC] D7_APC_1: 0xfff
10004 19:26:27.338705 INFO: [NOCDAPC] D8_APC_0: 0x0
10005 19:26:27.341918 INFO: [NOCDAPC] D8_APC_1: 0xfff
10006 19:26:27.345419 INFO: [NOCDAPC] D9_APC_0: 0x0
10007 19:26:27.348816 INFO: [NOCDAPC] D9_APC_1: 0xfff
10008 19:26:27.351945 INFO: [NOCDAPC] D10_APC_0: 0x0
10009 19:26:27.355320 INFO: [NOCDAPC] D10_APC_1: 0xfff
10010 19:26:27.358615 INFO: [NOCDAPC] D11_APC_0: 0x0
10011 19:26:27.362044 INFO: [NOCDAPC] D11_APC_1: 0xfff
10012 19:26:27.365575 INFO: [NOCDAPC] D12_APC_0: 0x0
10013 19:26:27.368627 INFO: [NOCDAPC] D12_APC_1: 0xfff
10014 19:26:27.371752 INFO: [NOCDAPC] D13_APC_0: 0x0
10015 19:26:27.375276 INFO: [NOCDAPC] D13_APC_1: 0xfff
10016 19:26:27.378490 INFO: [NOCDAPC] D14_APC_0: 0x0
10017 19:26:27.381781 INFO: [NOCDAPC] D14_APC_1: 0xfff
10018 19:26:27.381865 INFO: [NOCDAPC] D15_APC_0: 0x0
10019 19:26:27.385254 INFO: [NOCDAPC] D15_APC_1: 0xfff
10020 19:26:27.388361 INFO: [NOCDAPC] APC_CON: 0x4
10021 19:26:27.391750 INFO: [APUAPC] set_apusys_apc done
10022 19:26:27.395003 INFO: [DEVAPC] devapc_init done
10023 19:26:27.401527 INFO: GICv3 without legacy support detected.
10024 19:26:27.405135 INFO: ARM GICv3 driver initialized in EL3
10025 19:26:27.408417 INFO: Maximum SPI INTID supported: 639
10026 19:26:27.411370 INFO: BL31: Initializing runtime services
10027 19:26:27.418456 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10028 19:26:27.421573 INFO: SPM: enable CPC mode
10029 19:26:27.424913 INFO: mcdi ready for mcusys-off-idle and system suspend
10030 19:26:27.431649 INFO: BL31: Preparing for EL3 exit to normal world
10031 19:26:27.435100 INFO: Entry point address = 0x80000000
10032 19:26:27.435184 INFO: SPSR = 0x8
10033 19:26:27.441919
10034 19:26:27.442002
10035 19:26:27.442069
10036 19:26:27.445072 Starting depthcharge on Spherion...
10037 19:26:27.445159
10038 19:26:27.445226 Wipe memory regions:
10039 19:26:27.445311
10040 19:26:27.445964 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10041 19:26:27.446067 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10042 19:26:27.446149 Setting prompt string to ['asurada:']
10043 19:26:27.446229 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10044 19:26:27.447907 [0x00000040000000, 0x00000054600000)
10045 19:26:27.570839
10046 19:26:27.571280 [0x00000054660000, 0x00000080000000)
10047 19:26:27.831148
10048 19:26:27.831278 [0x000000821a7280, 0x000000ffe64000)
10049 19:26:28.576461
10050 19:26:28.577068 [0x00000100000000, 0x00000240000000)
10051 19:26:30.466087
10052 19:26:30.469219 Initializing XHCI USB controller at 0x11200000.
10053 19:26:31.508655
10054 19:26:31.511847 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10055 19:26:31.512321
10056 19:26:31.512690
10057 19:26:31.513034
10058 19:26:31.513854 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 19:26:31.615034 asurada: tftpboot 192.168.201.1 13420412/tftp-deploy-aanent8l/kernel/image.itb 13420412/tftp-deploy-aanent8l/kernel/cmdline
10061 19:26:31.615595 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 19:26:31.616043 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10063 19:26:31.620521 tftpboot 192.168.201.1 13420412/tftp-deploy-aanent8l/kernel/image.ittp-deploy-aanent8l/kernel/cmdline
10064 19:26:31.620997
10065 19:26:31.621395 Waiting for link
10066 19:26:31.781029
10067 19:26:31.781589 R8152: Initializing
10068 19:26:31.781976
10069 19:26:31.784098 Version 9 (ocp_data = 6010)
10070 19:26:31.784567
10071 19:26:31.787638 R8152: Done initializing
10072 19:26:31.788108
10073 19:26:31.788480 Adding net device
10074 19:26:33.729675
10075 19:26:33.729821 done.
10076 19:26:33.729889
10077 19:26:33.729950 MAC: 00:e0:4c:72:2d:d6
10078 19:26:33.730010
10079 19:26:33.732677 Sending DHCP discover... done.
10080 19:26:33.732760
10081 19:26:37.074512 Waiting for reply... done.
10082 19:26:37.075063
10083 19:26:37.075475 Sending DHCP request... done.
10084 19:26:37.077789
10085 19:26:37.078315 Waiting for reply... done.
10086 19:26:37.078713
10087 19:26:37.080800 My ip is 192.168.201.21
10088 19:26:37.081258
10089 19:26:37.084387 The DHCP server ip is 192.168.201.1
10090 19:26:37.084847
10091 19:26:37.087397 TFTP server IP predefined by user: 192.168.201.1
10092 19:26:37.087860
10093 19:26:37.093948 Bootfile predefined by user: 13420412/tftp-deploy-aanent8l/kernel/image.itb
10094 19:26:37.094415
10095 19:26:37.097186 Sending tftp read request... done.
10096 19:26:37.097784
10097 19:26:37.100738 Waiting for the transfer...
10098 19:26:37.104054
10099 19:26:37.376835 00000000 ################################################################
10100 19:26:37.376971
10101 19:26:37.627308 00080000 ################################################################
10102 19:26:37.627466
10103 19:26:37.879213 00100000 ################################################################
10104 19:26:37.879372
10105 19:26:38.125741 00180000 ################################################################
10106 19:26:38.125877
10107 19:26:38.374195 00200000 ################################################################
10108 19:26:38.374361
10109 19:26:38.622110 00280000 ################################################################
10110 19:26:38.622265
10111 19:26:38.869399 00300000 ################################################################
10112 19:26:38.869552
10113 19:26:39.116766 00380000 ################################################################
10114 19:26:39.116897
10115 19:26:39.365673 00400000 ################################################################
10116 19:26:39.365809
10117 19:26:39.610775 00480000 ################################################################
10118 19:26:39.610929
10119 19:26:39.859148 00500000 ################################################################
10120 19:26:39.859303
10121 19:26:40.107262 00580000 ################################################################
10122 19:26:40.107387
10123 19:26:40.355224 00600000 ################################################################
10124 19:26:40.355362
10125 19:26:40.604350 00680000 ################################################################
10126 19:26:40.604475
10127 19:26:40.853548 00700000 ################################################################
10128 19:26:40.853684
10129 19:26:41.101687 00780000 ################################################################
10130 19:26:41.101813
10131 19:26:41.350530 00800000 ################################################################
10132 19:26:41.350660
10133 19:26:41.596161 00880000 ################################################################
10134 19:26:41.596297
10135 19:26:41.844144 00900000 ################################################################
10136 19:26:41.844272
10137 19:26:42.094359 00980000 ################################################################
10138 19:26:42.094491
10139 19:26:42.343547 00a00000 ################################################################
10140 19:26:42.343714
10141 19:26:42.593449 00a80000 ################################################################
10142 19:26:42.593572
10143 19:26:42.842210 00b00000 ################################################################
10144 19:26:42.842332
10145 19:26:43.091492 00b80000 ################################################################
10146 19:26:43.091643
10147 19:26:43.337738 00c00000 ################################################################
10148 19:26:43.337869
10149 19:26:43.583234 00c80000 ################################################################
10150 19:26:43.583424
10151 19:26:43.828216 00d00000 ################################################################
10152 19:26:43.828371
10153 19:26:44.072923 00d80000 ################################################################
10154 19:26:44.073080
10155 19:26:44.318283 00e00000 ################################################################
10156 19:26:44.318422
10157 19:26:44.566279 00e80000 ################################################################
10158 19:26:44.566413
10159 19:26:44.815594 00f00000 ################################################################
10160 19:26:44.815729
10161 19:26:45.065456 00f80000 ################################################################
10162 19:26:45.065588
10163 19:26:45.314639 01000000 ################################################################
10164 19:26:45.314777
10165 19:26:45.562181 01080000 ################################################################
10166 19:26:45.562312
10167 19:26:45.809658 01100000 ################################################################
10168 19:26:45.809784
10169 19:26:46.057130 01180000 ################################################################
10170 19:26:46.057286
10171 19:26:46.304245 01200000 ################################################################
10172 19:26:46.304400
10173 19:26:46.550822 01280000 ################################################################
10174 19:26:46.550975
10175 19:26:46.798486 01300000 ################################################################
10176 19:26:46.798622
10177 19:26:47.043951 01380000 ################################################################
10178 19:26:47.044114
10179 19:26:47.291009 01400000 ################################################################
10180 19:26:47.291151
10181 19:26:47.538587 01480000 ################################################################
10182 19:26:47.538745
10183 19:26:47.785950 01500000 ################################################################
10184 19:26:47.786078
10185 19:26:48.032602 01580000 ################################################################
10186 19:26:48.032731
10187 19:26:48.278309 01600000 ################################################################
10188 19:26:48.278444
10189 19:26:48.528511 01680000 ################################################################
10190 19:26:48.528652
10191 19:26:48.776148 01700000 ################################################################
10192 19:26:48.776288
10193 19:26:49.023985 01780000 ################################################################
10194 19:26:49.024127
10195 19:26:49.273041 01800000 ################################################################
10196 19:26:49.273177
10197 19:26:49.522751 01880000 ################################################################
10198 19:26:49.522881
10199 19:26:49.772503 01900000 ################################################################
10200 19:26:49.772635
10201 19:26:50.019696 01980000 ################################################################
10202 19:26:50.019826
10203 19:26:50.266389 01a00000 ################################################################
10204 19:26:50.266530
10205 19:26:50.514529 01a80000 ################################################################
10206 19:26:50.514651
10207 19:26:50.759794 01b00000 ################################################################
10208 19:26:50.759921
10209 19:26:51.007754 01b80000 ################################################################
10210 19:26:51.007880
10211 19:26:51.254832 01c00000 ################################################################
10212 19:26:51.254961
10213 19:26:51.502470 01c80000 ################################################################
10214 19:26:51.502603
10215 19:26:51.748350 01d00000 ################################################################
10216 19:26:51.748469
10217 19:26:51.995367 01d80000 ################################################################
10218 19:26:51.995512
10219 19:26:52.243982 01e00000 ################################################################
10220 19:26:52.244121
10221 19:26:52.492732 01e80000 ################################################################
10222 19:26:52.492880
10223 19:26:52.740160 01f00000 ################################################################
10224 19:26:52.740302
10225 19:26:52.987370 01f80000 ################################################################
10226 19:26:52.987512
10227 19:26:53.236807 02000000 ################################################################
10228 19:26:53.236946
10229 19:26:53.373001 02080000 #################################### done.
10230 19:26:53.373140
10231 19:26:53.376951 The bootfile was 34366966 bytes long.
10232 19:26:53.377088
10233 19:26:53.379980 Sending tftp read request... done.
10234 19:26:53.380064
10235 19:26:53.383321 Waiting for the transfer...
10236 19:26:53.383405
10237 19:26:53.383472 00000000 # done.
10238 19:26:53.383537
10239 19:26:53.389910 Command line loaded dynamically from TFTP file: 13420412/tftp-deploy-aanent8l/kernel/cmdline
10240 19:26:53.389995
10241 19:26:53.403110 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10242 19:26:53.406627
10243 19:26:53.406711 Loading FIT.
10244 19:26:53.406777
10245 19:26:53.409732 Image ramdisk-1 has 21407345 bytes.
10246 19:26:53.409816
10247 19:26:53.413131 Image fdt-1 has 47230 bytes.
10248 19:26:53.413239
10249 19:26:53.413364 Image kernel-1 has 12910355 bytes.
10250 19:26:53.416442
10251 19:26:53.423417 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10252 19:26:53.423502
10253 19:26:53.439822 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10254 19:26:53.443149
10255 19:26:53.446643 Choosing best match conf-1 for compat google,spherion-rev2.
10256 19:26:53.450638
10257 19:26:53.455968 Connected to device vid:did:rid of 1ae0:0028:00
10258 19:26:53.463310
10259 19:26:53.466817 tpm_get_response: command 0x17b, return code 0x0
10260 19:26:53.466901
10261 19:26:53.470049 ec_init: CrosEC protocol v3 supported (256, 248)
10262 19:26:53.474486
10263 19:26:53.477592 tpm_cleanup: add release locality here.
10264 19:26:53.477676
10265 19:26:53.477743 Shutting down all USB controllers.
10266 19:26:53.480881
10267 19:26:53.480964 Removing current net device
10268 19:26:53.481031
10269 19:26:53.487690 Exiting depthcharge with code 4 at timestamp: 55384182
10270 19:26:53.487773
10271 19:26:53.491018 LZMA decompressing kernel-1 to 0x821a6718
10272 19:26:53.491102
10273 19:26:53.494296 LZMA decompressing kernel-1 to 0x40000000
10274 19:26:55.088284
10275 19:26:55.088841 jumping to kernel
10276 19:26:55.090521 end: 2.2.4 bootloader-commands (duration 00:00:28) [common]
10277 19:26:55.091026 start: 2.2.5 auto-login-action (timeout 00:03:58) [common]
10278 19:26:55.091421 Setting prompt string to ['Linux version [0-9]']
10279 19:26:55.091804 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10280 19:26:55.092174 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10281 19:26:55.170308
10282 19:26:55.173884 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10283 19:26:55.177374 start: 2.2.5.1 login-action (timeout 00:03:57) [common]
10284 19:26:55.177910 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10285 19:26:55.178293 Setting prompt string to []
10286 19:26:55.178704 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10287 19:26:55.179089 Using line separator: #'\n'#
10288 19:26:55.179400 No login prompt set.
10289 19:26:55.179725 Parsing kernel messages
10290 19:26:55.180029 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10291 19:26:55.180555 [login-action] Waiting for messages, (timeout 00:03:57)
10292 19:26:55.180905 Waiting using forced prompt support (timeout 00:01:59)
10293 19:26:55.196999 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j170728-arm64-gcc-10-defconfig-arm64-chromebook-wrkxq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024
10294 19:26:55.200245 [ 0.000000] random: crng init done
10295 19:26:55.206624 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10296 19:26:55.210198 [ 0.000000] efi: UEFI not found.
10297 19:26:55.216781 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10298 19:26:55.223567 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10299 19:26:55.233060 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10300 19:26:55.243214 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10301 19:26:55.250150 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10302 19:26:55.256509 [ 0.000000] printk: bootconsole [mtk8250] enabled
10303 19:26:55.263158 [ 0.000000] NUMA: No NUMA configuration found
10304 19:26:55.270015 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10305 19:26:55.273270 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10306 19:26:55.276409 [ 0.000000] Zone ranges:
10307 19:26:55.282923 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10308 19:26:55.286361 [ 0.000000] DMA32 empty
10309 19:26:55.292776 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10310 19:26:55.296276 [ 0.000000] Movable zone start for each node
10311 19:26:55.299605 [ 0.000000] Early memory node ranges
10312 19:26:55.306409 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10313 19:26:55.312934 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10314 19:26:55.319678 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10315 19:26:55.323687 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10316 19:26:55.329638 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10317 19:26:55.336513 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10318 19:26:55.395041 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10319 19:26:55.401622 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10320 19:26:55.408123 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10321 19:26:55.411317 [ 0.000000] psci: probing for conduit method from DT.
10322 19:26:55.418335 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10323 19:26:55.421792 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10324 19:26:55.427859 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10325 19:26:55.431323 [ 0.000000] psci: SMC Calling Convention v1.2
10326 19:26:55.437805 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10327 19:26:55.441346 [ 0.000000] Detected VIPT I-cache on CPU0
10328 19:26:55.447849 [ 0.000000] CPU features: detected: GIC system register CPU interface
10329 19:26:55.454083 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10330 19:26:55.461270 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10331 19:26:55.467529 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10332 19:26:55.477670 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10333 19:26:55.483869 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10334 19:26:55.486994 [ 0.000000] alternatives: applying boot alternatives
10335 19:26:55.493927 [ 0.000000] Fallback order for Node 0: 0
10336 19:26:55.500359 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10337 19:26:55.503817 [ 0.000000] Policy zone: Normal
10338 19:26:55.517279 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10339 19:26:55.526882 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10340 19:26:55.538693 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10341 19:26:55.548566 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10342 19:26:55.555386 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10343 19:26:55.558299 <6>[ 0.000000] software IO TLB: area num 8.
10344 19:26:55.615486 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10345 19:26:55.764651 <6>[ 0.000000] Memory: 7943664K/8385536K available (18048K kernel code, 4118K rwdata, 22288K rodata, 8448K init, 616K bss, 409104K reserved, 32768K cma-reserved)
10346 19:26:55.771109 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10347 19:26:55.777938 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10348 19:26:55.781202 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10349 19:26:55.787834 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10350 19:26:55.794676 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10351 19:26:55.798068 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10352 19:26:55.807795 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10353 19:26:55.814600 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10354 19:26:55.821000 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10355 19:26:55.827836 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10356 19:26:55.830901 <6>[ 0.000000] GICv3: 608 SPIs implemented
10357 19:26:55.834300 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10358 19:26:55.840902 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10359 19:26:55.844390 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10360 19:26:55.851146 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10361 19:26:55.864147 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10362 19:26:55.873991 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10363 19:26:55.884049 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10364 19:26:55.891338 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10365 19:26:55.904495 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10366 19:26:55.911158 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10367 19:26:55.917911 <6>[ 0.009201] Console: colour dummy device 80x25
10368 19:26:55.927807 <6>[ 0.013930] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10369 19:26:55.934361 <6>[ 0.024372] pid_max: default: 32768 minimum: 301
10370 19:26:55.937474 <6>[ 0.029243] LSM: Security Framework initializing
10371 19:26:55.944259 <6>[ 0.034183] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10372 19:26:55.954386 <6>[ 0.041997] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10373 19:26:55.960986 <6>[ 0.051413] cblist_init_generic: Setting adjustable number of callback queues.
10374 19:26:55.967813 <6>[ 0.058854] cblist_init_generic: Setting shift to 3 and lim to 1.
10375 19:26:55.977482 <6>[ 0.065193] cblist_init_generic: Setting adjustable number of callback queues.
10376 19:26:55.984077 <6>[ 0.072666] cblist_init_generic: Setting shift to 3 and lim to 1.
10377 19:26:55.987365 <6>[ 0.079065] rcu: Hierarchical SRCU implementation.
10378 19:26:55.994329 <6>[ 0.084080] rcu: Max phase no-delay instances is 1000.
10379 19:26:56.000590 <6>[ 0.091105] EFI services will not be available.
10380 19:26:56.004101 <6>[ 0.096088] smp: Bringing up secondary CPUs ...
10381 19:26:56.012262 <6>[ 0.101132] Detected VIPT I-cache on CPU1
10382 19:26:56.019133 <6>[ 0.101202] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10383 19:26:56.025801 <6>[ 0.101235] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10384 19:26:56.028802 <6>[ 0.101572] Detected VIPT I-cache on CPU2
10385 19:26:56.035710 <6>[ 0.101624] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10386 19:26:56.042155 <6>[ 0.101642] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10387 19:26:56.048652 <6>[ 0.101899] Detected VIPT I-cache on CPU3
10388 19:26:56.055532 <6>[ 0.101948] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10389 19:26:56.062125 <6>[ 0.101961] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10390 19:26:56.065237 <6>[ 0.102263] CPU features: detected: Spectre-v4
10391 19:26:56.072214 <6>[ 0.102269] CPU features: detected: Spectre-BHB
10392 19:26:56.075274 <6>[ 0.102274] Detected PIPT I-cache on CPU4
10393 19:26:56.082185 <6>[ 0.102332] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10394 19:26:56.088724 <6>[ 0.102349] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10395 19:26:56.091929 <6>[ 0.102641] Detected PIPT I-cache on CPU5
10396 19:26:56.102202 <6>[ 0.102705] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10397 19:26:56.108628 <6>[ 0.102722] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10398 19:26:56.111992 <6>[ 0.103002] Detected PIPT I-cache on CPU6
10399 19:26:56.118820 <6>[ 0.103068] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10400 19:26:56.125521 <6>[ 0.103084] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10401 19:26:56.128777 <6>[ 0.103383] Detected PIPT I-cache on CPU7
10402 19:26:56.138741 <6>[ 0.103442] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10403 19:26:56.145216 <6>[ 0.103458] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10404 19:26:56.148628 <6>[ 0.103505] smp: Brought up 1 node, 8 CPUs
10405 19:26:56.152082 <6>[ 0.244729] SMP: Total of 8 processors activated.
10406 19:26:56.158619 <6>[ 0.249681] CPU features: detected: 32-bit EL0 Support
10407 19:26:56.168513 <6>[ 0.255044] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10408 19:26:56.175193 <6>[ 0.263899] CPU features: detected: Common not Private translations
10409 19:26:56.178379 <6>[ 0.270415] CPU features: detected: CRC32 instructions
10410 19:26:56.185083 <6>[ 0.275766] CPU features: detected: RCpc load-acquire (LDAPR)
10411 19:26:56.191844 <6>[ 0.281763] CPU features: detected: LSE atomic instructions
10412 19:26:56.198275 <6>[ 0.287545] CPU features: detected: Privileged Access Never
10413 19:26:56.201742 <6>[ 0.293324] CPU features: detected: RAS Extension Support
10414 19:26:56.208283 <6>[ 0.298933] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10415 19:26:56.214911 <6>[ 0.306154] CPU: All CPU(s) started at EL2
10416 19:26:56.218212 <6>[ 0.310497] alternatives: applying system-wide alternatives
10417 19:26:56.229760 <6>[ 0.321325] devtmpfs: initialized
10418 19:26:56.242063 <6>[ 0.330260] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10419 19:26:56.251882 <6>[ 0.340222] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10420 19:26:56.258889 <6>[ 0.348446] pinctrl core: initialized pinctrl subsystem
10421 19:26:56.261883 <6>[ 0.355197] DMI not present or invalid.
10422 19:26:56.268623 <6>[ 0.359615] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10423 19:26:56.278716 <6>[ 0.366498] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10424 19:26:56.284936 <6>[ 0.374076] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10425 19:26:56.295253 <6>[ 0.382308] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10426 19:26:56.298198 <6>[ 0.390546] audit: initializing netlink subsys (disabled)
10427 19:26:56.308294 <5>[ 0.396239] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10428 19:26:56.314859 <6>[ 0.396982] thermal_sys: Registered thermal governor 'step_wise'
10429 19:26:56.321689 <6>[ 0.404204] thermal_sys: Registered thermal governor 'power_allocator'
10430 19:26:56.325041 <6>[ 0.410458] cpuidle: using governor menu
10431 19:26:56.331428 <6>[ 0.421417] NET: Registered PF_QIPCRTR protocol family
10432 19:26:56.338150 <6>[ 0.426900] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10433 19:26:56.341581 <6>[ 0.434003] ASID allocator initialised with 32768 entries
10434 19:26:56.349037 <6>[ 0.440644] Serial: AMBA PL011 UART driver
10435 19:26:56.358403 <4>[ 0.449713] Trying to register duplicate clock ID: 134
10436 19:26:56.415030 <6>[ 0.509821] KASLR enabled
10437 19:26:56.429192 <6>[ 0.517582] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10438 19:26:56.435893 <6>[ 0.524596] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10439 19:26:56.442911 <6>[ 0.531083] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10440 19:26:56.449050 <6>[ 0.538086] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10441 19:26:56.455849 <6>[ 0.544571] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10442 19:26:56.462362 <6>[ 0.551574] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10443 19:26:56.468942 <6>[ 0.558062] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10444 19:26:56.476030 <6>[ 0.565065] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10445 19:26:56.479191 <6>[ 0.572582] ACPI: Interpreter disabled.
10446 19:26:56.487685 <6>[ 0.579053] iommu: Default domain type: Translated
10447 19:26:56.494415 <6>[ 0.584164] iommu: DMA domain TLB invalidation policy: strict mode
10448 19:26:56.497608 <5>[ 0.590827] SCSI subsystem initialized
10449 19:26:56.504147 <6>[ 0.595003] usbcore: registered new interface driver usbfs
10450 19:26:56.510503 <6>[ 0.600731] usbcore: registered new interface driver hub
10451 19:26:56.514020 <6>[ 0.606279] usbcore: registered new device driver usb
10452 19:26:56.520998 <6>[ 0.612409] pps_core: LinuxPPS API ver. 1 registered
10453 19:26:56.531113 <6>[ 0.617605] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10454 19:26:56.534251 <6>[ 0.626951] PTP clock support registered
10455 19:26:56.537606 <6>[ 0.631194] EDAC MC: Ver: 3.0.0
10456 19:26:56.544850 <6>[ 0.636377] FPGA manager framework
10457 19:26:56.548567 <6>[ 0.640052] Advanced Linux Sound Architecture Driver Initialized.
10458 19:26:56.552315 <6>[ 0.646827] vgaarb: loaded
10459 19:26:56.558841 <6>[ 0.650009] clocksource: Switched to clocksource arch_sys_counter
10460 19:26:56.565525 <5>[ 0.656446] VFS: Disk quotas dquot_6.6.0
10461 19:26:56.572397 <6>[ 0.660635] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10462 19:26:56.575316 <6>[ 0.667824] pnp: PnP ACPI: disabled
10463 19:26:56.583278 <6>[ 0.674488] NET: Registered PF_INET protocol family
10464 19:26:56.593287 <6>[ 0.680083] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10465 19:26:56.604611 <6>[ 0.692435] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10466 19:26:56.614398 <6>[ 0.701249] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10467 19:26:56.621179 <6>[ 0.709219] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10468 19:26:56.627604 <6>[ 0.717921] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10469 19:26:56.640042 <6>[ 0.727683] TCP: Hash tables configured (established 65536 bind 65536)
10470 19:26:56.646614 <6>[ 0.734547] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10471 19:26:56.653364 <6>[ 0.741742] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10472 19:26:56.659622 <6>[ 0.749449] NET: Registered PF_UNIX/PF_LOCAL protocol family
10473 19:26:56.666937 <6>[ 0.755606] RPC: Registered named UNIX socket transport module.
10474 19:26:56.670193 <6>[ 0.761755] RPC: Registered udp transport module.
10475 19:26:56.676289 <6>[ 0.766690] RPC: Registered tcp transport module.
10476 19:26:56.683186 <6>[ 0.771622] RPC: Registered tcp NFSv4.1 backchannel transport module.
10477 19:26:56.686079 <6>[ 0.778289] PCI: CLS 0 bytes, default 64
10478 19:26:56.689367 <6>[ 0.782629] Unpacking initramfs...
10479 19:26:56.714475 <6>[ 0.802122] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10480 19:26:56.724081 <6>[ 0.810783] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10481 19:26:56.728038 <6>[ 0.819656] kvm [1]: IPA Size Limit: 40 bits
10482 19:26:56.734210 <6>[ 0.824172] kvm [1]: GICv3: no GICV resource entry
10483 19:26:56.737552 <6>[ 0.829193] kvm [1]: disabling GICv2 emulation
10484 19:26:56.744375 <6>[ 0.833877] kvm [1]: GIC system register CPU interface enabled
10485 19:26:56.747817 <6>[ 0.840038] kvm [1]: vgic interrupt IRQ18
10486 19:26:56.754043 <6>[ 0.844433] kvm [1]: VHE mode initialized successfully
10487 19:26:56.761060 <5>[ 0.850865] Initialise system trusted keyrings
10488 19:26:56.767560 <6>[ 0.855657] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10489 19:26:56.774561 <6>[ 0.865719] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10490 19:26:56.781429 <5>[ 0.872087] NFS: Registering the id_resolver key type
10491 19:26:56.784621 <5>[ 0.877388] Key type id_resolver registered
10492 19:26:56.791197 <5>[ 0.881804] Key type id_legacy registered
10493 19:26:56.797429 <6>[ 0.886095] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10494 19:26:56.804062 <6>[ 0.893018] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10495 19:26:56.810762 <6>[ 0.900727] 9p: Installing v9fs 9p2000 file system support
10496 19:26:56.846604 <5>[ 0.937735] Key type asymmetric registered
10497 19:26:56.849930 <5>[ 0.942065] Asymmetric key parser 'x509' registered
10498 19:26:56.860039 <6>[ 0.947252] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10499 19:26:56.863370 <6>[ 0.954871] io scheduler mq-deadline registered
10500 19:26:56.866651 <6>[ 0.959638] io scheduler kyber registered
10501 19:26:56.885806 <6>[ 0.976905] EINJ: ACPI disabled.
10502 19:26:56.918787 <4>[ 1.002958] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10503 19:26:56.928323 <4>[ 1.013566] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10504 19:26:56.943284 <6>[ 1.034428] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10505 19:26:56.951211 <6>[ 1.042411] printk: console [ttyS0] disabled
10506 19:26:56.979154 <6>[ 1.067037] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10507 19:26:56.985694 <6>[ 1.076506] printk: console [ttyS0] enabled
10508 19:26:56.988968 <6>[ 1.076506] printk: console [ttyS0] enabled
10509 19:26:56.995579 <6>[ 1.085401] printk: bootconsole [mtk8250] disabled
10510 19:26:56.998978 <6>[ 1.085401] printk: bootconsole [mtk8250] disabled
10511 19:26:57.005417 <6>[ 1.096446] SuperH (H)SCI(F) driver initialized
10512 19:26:57.008725 <6>[ 1.101730] msm_serial: driver initialized
10513 19:26:57.022813 <6>[ 1.110816] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10514 19:26:57.032771 <6>[ 1.119360] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10515 19:26:57.039311 <6>[ 1.127903] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10516 19:26:57.049382 <6>[ 1.136533] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10517 19:26:57.059640 <6>[ 1.145240] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10518 19:26:57.066163 <6>[ 1.153952] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10519 19:26:57.078465 <6>[ 1.162493] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10520 19:26:57.082419 <6>[ 1.171288] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10521 19:26:57.092404 <6>[ 1.179830] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10522 19:26:57.103775 <6>[ 1.195123] loop: module loaded
10523 19:26:57.110279 <6>[ 1.201162] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10524 19:26:57.133591 <4>[ 1.224622] mtk-pmic-keys: Failed to locate of_node [id: -1]
10525 19:26:57.140061 <6>[ 1.231491] megasas: 07.719.03.00-rc1
10526 19:26:57.150247 <6>[ 1.241300] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10527 19:26:57.158235 <6>[ 1.249412] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10528 19:26:57.174749 <6>[ 1.266068] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10529 19:26:57.231401 <6>[ 1.315918] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10530 19:26:57.592259 <6>[ 1.683529] Freeing initrd memory: 20904K
10531 19:26:57.607528 <6>[ 1.699120] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10532 19:26:57.618674 <6>[ 1.710228] tun: Universal TUN/TAP device driver, 1.6
10533 19:26:57.622038 <6>[ 1.716326] thunder_xcv, ver 1.0
10534 19:26:57.625319 <6>[ 1.719831] thunder_bgx, ver 1.0
10535 19:26:57.628623 <6>[ 1.723326] nicpf, ver 1.0
10536 19:26:57.639261 <6>[ 1.727405] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10537 19:26:57.642400 <6>[ 1.734880] hns3: Copyright (c) 2017 Huawei Corporation.
10538 19:26:57.649327 <6>[ 1.740471] hclge is initializing
10539 19:26:57.652328 <6>[ 1.744053] e1000: Intel(R) PRO/1000 Network Driver
10540 19:26:57.659240 <6>[ 1.749182] e1000: Copyright (c) 1999-2006 Intel Corporation.
10541 19:26:57.662705 <6>[ 1.755196] e1000e: Intel(R) PRO/1000 Network Driver
10542 19:26:57.669426 <6>[ 1.760411] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10543 19:26:57.675756 <6>[ 1.766598] igb: Intel(R) Gigabit Ethernet Network Driver
10544 19:26:57.682683 <6>[ 1.772248] igb: Copyright (c) 2007-2014 Intel Corporation.
10545 19:26:57.689502 <6>[ 1.778085] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10546 19:26:57.696289 <6>[ 1.784602] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10547 19:26:57.699287 <6>[ 1.791067] sky2: driver version 1.30
10548 19:26:57.705978 <6>[ 1.796092] VFIO - User Level meta-driver version: 0.3
10549 19:26:57.713163 <6>[ 1.804417] usbcore: registered new interface driver usb-storage
10550 19:26:57.719758 <6>[ 1.810863] usbcore: registered new device driver onboard-usb-hub
10551 19:26:57.728981 <6>[ 1.820089] mt6397-rtc mt6359-rtc: registered as rtc0
10552 19:26:57.738654 <6>[ 1.825555] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-18T19:25:44 UTC (1713468344)
10553 19:26:57.742102 <6>[ 1.835142] i2c_dev: i2c /dev entries driver
10554 19:26:57.759229 <6>[ 1.847106] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10555 19:26:57.766377 <4>[ 1.855846] cpu cpu0: supply cpu not found, using dummy regulator
10556 19:26:57.772761 <4>[ 1.862270] cpu cpu1: supply cpu not found, using dummy regulator
10557 19:26:57.779530 <4>[ 1.868676] cpu cpu2: supply cpu not found, using dummy regulator
10558 19:26:57.786222 <4>[ 1.875097] cpu cpu3: supply cpu not found, using dummy regulator
10559 19:26:57.792822 <4>[ 1.881499] cpu cpu4: supply cpu not found, using dummy regulator
10560 19:26:57.799530 <4>[ 1.887915] cpu cpu5: supply cpu not found, using dummy regulator
10561 19:26:57.802719 <4>[ 1.894313] cpu cpu6: supply cpu not found, using dummy regulator
10562 19:26:57.809359 <4>[ 1.900710] cpu cpu7: supply cpu not found, using dummy regulator
10563 19:26:57.829981 <6>[ 1.921338] cpu cpu0: EM: created perf domain
10564 19:26:57.833368 <6>[ 1.926282] cpu cpu4: EM: created perf domain
10565 19:26:57.840708 <6>[ 1.931906] sdhci: Secure Digital Host Controller Interface driver
10566 19:26:57.847170 <6>[ 1.938339] sdhci: Copyright(c) Pierre Ossman
10567 19:26:57.854020 <6>[ 1.943315] Synopsys Designware Multimedia Card Interface Driver
10568 19:26:57.860211 <6>[ 1.949961] sdhci-pltfm: SDHCI platform and OF driver helper
10569 19:26:57.863561 <6>[ 1.950061] mmc0: CQHCI version 5.10
10570 19:26:57.870227 <6>[ 1.959985] ledtrig-cpu: registered to indicate activity on CPUs
10571 19:26:57.877127 <6>[ 1.967136] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10572 19:26:57.883661 <6>[ 1.974197] usbcore: registered new interface driver usbhid
10573 19:26:57.887324 <6>[ 1.980022] usbhid: USB HID core driver
10574 19:26:57.893561 <6>[ 1.984229] spi_master spi0: will run message pump with realtime priority
10575 19:26:57.935843 <6>[ 2.020368] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10576 19:26:57.950735 <6>[ 2.035268] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10577 19:26:57.958789 <6>[ 2.049507] mmc0: Command Queue Engine enabled
10578 19:26:57.965138 <6>[ 2.054273] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10579 19:26:57.971793 <6>[ 2.061036] cros-ec-spi spi0.0: Chrome EC device registered
10580 19:26:57.974721 <6>[ 2.061527] mmcblk0: mmc0:0001 DA4128 116 GiB
10581 19:26:57.983811 <6>[ 2.075279] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10582 19:26:57.991328 <6>[ 2.082494] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10583 19:26:57.998074 <6>[ 2.088434] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10584 19:26:58.004354 <6>[ 2.094319] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10585 19:26:58.020469 <6>[ 2.108179] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10586 19:26:58.027677 <6>[ 2.118838] NET: Registered PF_PACKET protocol family
10587 19:26:58.030954 <6>[ 2.124241] 9pnet: Installing 9P2000 support
10588 19:26:58.037323 <5>[ 2.128807] Key type dns_resolver registered
10589 19:26:58.040761 <6>[ 2.133784] registered taskstats version 1
10590 19:26:58.047594 <5>[ 2.138168] Loading compiled-in X.509 certificates
10591 19:26:58.078001 <4>[ 2.162532] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 19:26:58.088503 <4>[ 2.173327] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 19:26:58.094932 <3>[ 2.183868] debugfs: File 'uA_load' in directory '/' already present!
10594 19:26:58.101247 <3>[ 2.190572] debugfs: File 'min_uV' in directory '/' already present!
10595 19:26:58.108113 <3>[ 2.197186] debugfs: File 'max_uV' in directory '/' already present!
10596 19:26:58.114642 <3>[ 2.203793] debugfs: File 'constraint_flags' in directory '/' already present!
10597 19:26:58.125640 <3>[ 2.213596] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10598 19:26:58.139541 <6>[ 2.231073] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10599 19:26:58.146331 <6>[ 2.237864] xhci-mtk 11200000.usb: xHCI Host Controller
10600 19:26:58.152713 <6>[ 2.243370] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10601 19:26:58.163262 <6>[ 2.251295] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10602 19:26:58.169922 <6>[ 2.260728] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10603 19:26:58.176228 <6>[ 2.266915] xhci-mtk 11200000.usb: xHCI Host Controller
10604 19:26:58.182822 <6>[ 2.272414] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10605 19:26:58.189259 <6>[ 2.280071] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10606 19:26:58.196490 <6>[ 2.288005] hub 1-0:1.0: USB hub found
10607 19:26:58.199484 <6>[ 2.292032] hub 1-0:1.0: 1 port detected
10608 19:26:58.209665 <6>[ 2.296342] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10609 19:26:58.212754 <6>[ 2.305138] hub 2-0:1.0: USB hub found
10610 19:26:58.216000 <6>[ 2.309164] hub 2-0:1.0: 1 port detected
10611 19:26:58.225057 <6>[ 2.317107] mtk-msdc 11f70000.mmc: Got CD GPIO
10612 19:26:58.238946 <6>[ 2.327162] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10613 19:26:58.245846 <6>[ 2.335311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10614 19:26:58.255130 <4>[ 2.343288] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10615 19:26:58.265170 <6>[ 2.352817] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10616 19:26:58.271863 <6>[ 2.360901] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10617 19:26:58.281719 <6>[ 2.368908] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10618 19:26:58.288274 <6>[ 2.376827] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10619 19:26:58.294955 <6>[ 2.384647] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10620 19:26:58.304448 <6>[ 2.392467] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10621 19:26:58.314745 <6>[ 2.403020] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10622 19:26:58.324270 <6>[ 2.411395] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10623 19:26:58.331288 <6>[ 2.419740] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10624 19:26:58.340689 <6>[ 2.428078] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10625 19:26:58.347337 <6>[ 2.436415] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10626 19:26:58.357683 <6>[ 2.444754] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10627 19:26:58.363873 <6>[ 2.453091] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10628 19:26:58.374010 <6>[ 2.461428] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10629 19:26:58.380784 <6>[ 2.469765] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10630 19:26:58.390361 <6>[ 2.478102] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10631 19:26:58.396967 <6>[ 2.486439] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10632 19:26:58.407355 <6>[ 2.494777] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10633 19:26:58.413507 <6>[ 2.503122] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10634 19:26:58.423418 <6>[ 2.511459] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10635 19:26:58.430007 <6>[ 2.519796] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10636 19:26:58.436530 <6>[ 2.528553] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10637 19:26:58.443726 <6>[ 2.535734] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10638 19:26:58.450769 <6>[ 2.542498] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10639 19:26:58.460821 <6>[ 2.549267] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10640 19:26:58.467353 <6>[ 2.556203] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10641 19:26:58.474345 <6>[ 2.563043] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10642 19:26:58.484219 <6>[ 2.572172] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10643 19:26:58.494004 <6>[ 2.581292] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10644 19:26:58.503752 <6>[ 2.590586] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10645 19:26:58.513480 <6>[ 2.600054] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10646 19:26:58.520462 <6>[ 2.609522] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10647 19:26:58.530350 <6>[ 2.618641] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10648 19:26:58.540203 <6>[ 2.628110] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10649 19:26:58.550202 <6>[ 2.637230] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10650 19:26:58.559932 <6>[ 2.646534] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10651 19:26:58.569635 <6>[ 2.656694] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10652 19:26:58.579346 <6>[ 2.668045] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10653 19:26:58.629723 <6>[ 2.718154] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10654 19:26:58.784477 <6>[ 2.876189] hub 1-1:1.0: USB hub found
10655 19:26:58.788045 <6>[ 2.880716] hub 1-1:1.0: 4 ports detected
10656 19:26:58.797998 <6>[ 2.889530] hub 1-1:1.0: USB hub found
10657 19:26:58.800818 <6>[ 2.893854] hub 1-1:1.0: 4 ports detected
10658 19:26:58.909894 <6>[ 2.998323] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10659 19:26:58.936257 <6>[ 3.027988] hub 2-1:1.0: USB hub found
10660 19:26:58.939205 <6>[ 3.032517] hub 2-1:1.0: 3 ports detected
10661 19:26:58.948740 <6>[ 3.040553] hub 2-1:1.0: USB hub found
10662 19:26:58.952157 <6>[ 3.044989] hub 2-1:1.0: 3 ports detected
10663 19:26:59.121559 <6>[ 3.210328] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10664 19:26:59.254898 <6>[ 3.346343] hub 1-1.4:1.0: USB hub found
10665 19:26:59.257696 <6>[ 3.351020] hub 1-1.4:1.0: 2 ports detected
10666 19:26:59.267188 <6>[ 3.358958] hub 1-1.4:1.0: USB hub found
10667 19:26:59.270457 <6>[ 3.363504] hub 1-1.4:1.0: 2 ports detected
10668 19:26:59.333761 <6>[ 3.422510] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10669 19:26:59.565587 <6>[ 3.654334] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10670 19:26:59.757568 <6>[ 3.846319] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10671 19:27:10.863427 <6>[ 14.959557] ALSA device list:
10672 19:27:10.869947 <6>[ 14.962842] No soundcards found.
10673 19:27:10.878052 <6>[ 14.970764] Freeing unused kernel memory: 8448K
10674 19:27:10.881132 <6>[ 14.975955] Run /init as init process
10675 19:27:10.916312 Starting syslogd: OK
10676 19:27:10.921019 Starting klogd: OK
10677 19:27:10.930379 Running sysctl: OK
10678 19:27:10.940009 Populating /dev using udev: <30>[ 15.031941] udevd[186]: starting version 3.2.9
10679 19:27:10.946891 <27>[ 15.039723] udevd[186]: specified user 'tss' unknown
10680 19:27:10.953538 <27>[ 15.045086] udevd[186]: specified group 'tss' unknown
10681 19:27:10.956757 <30>[ 15.051554] udevd[187]: starting eudev-3.2.9
10682 19:27:10.995515 <27>[ 15.088272] udevd[187]: specified user 'tss' unknown
10683 19:27:11.001780 <27>[ 15.093636] udevd[187]: specified group 'tss' unknown
10684 19:27:11.166451 <6>[ 15.255876] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10685 19:27:11.176220 <6>[ 15.264029] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10686 19:27:11.182834 <6>[ 15.273371] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10687 19:27:11.192805 <6>[ 15.285558] usbcore: registered new device driver r8152-cfgselector
10688 19:27:11.207071 <6>[ 15.296538] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10689 19:27:11.214052 <6>[ 15.296929] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10690 19:27:11.219992 <4>[ 15.297432] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10691 19:27:11.226943 <4>[ 15.297956] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10692 19:27:11.236812 <3>[ 15.310958] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 19:27:11.240273 <6>[ 15.315567] remoteproc remoteproc0: scp is available
10694 19:27:11.249745 <3>[ 15.318938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 19:27:11.253670 <6>[ 15.319453] mc: Linux media interface: v0.10
10696 19:27:11.260722 <6>[ 15.326352] remoteproc remoteproc0: powering up scp
10697 19:27:11.267197 <3>[ 15.334465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 19:27:11.277427 <6>[ 15.339530] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10699 19:27:11.280678 <6>[ 15.339562] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10700 19:27:11.290488 <4>[ 15.340214] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10701 19:27:11.294382 <4>[ 15.340214] Fallback method does not support PEC.
10702 19:27:11.304242 <3>[ 15.347861] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 19:27:11.310621 <3>[ 15.358392] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10704 19:27:11.320623 <3>[ 15.365573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 19:27:11.330813 <3>[ 15.394930] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10706 19:27:11.337070 <3>[ 15.401282] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 19:27:11.343659 <3>[ 15.401291] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 19:27:11.353740 <3>[ 15.401298] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 19:27:11.360215 <3>[ 15.401438] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 19:27:11.370588 <6>[ 15.402604] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10711 19:27:11.376834 <6>[ 15.403005] videodev: Linux video capture interface: v2.00
10712 19:27:11.383447 <6>[ 15.406735] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10713 19:27:11.390056 <6>[ 15.408267] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10714 19:27:11.396305 <6>[ 15.408278] pci_bus 0000:00: root bus resource [bus 00-ff]
10715 19:27:11.403216 <6>[ 15.408286] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10716 19:27:11.413148 <6>[ 15.408288] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10717 19:27:11.419406 <6>[ 15.408323] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10718 19:27:11.429695 <6>[ 15.408339] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10719 19:27:11.432983 <6>[ 15.408411] pci 0000:00:00.0: supports D1 D2
10720 19:27:11.439336 <6>[ 15.408413] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10721 19:27:11.445917 <6>[ 15.409592] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10722 19:27:11.452800 <6>[ 15.409680] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10723 19:27:11.462536 <6>[ 15.409708] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10724 19:27:11.469307 <6>[ 15.409729] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10725 19:27:11.475977 <6>[ 15.409743] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10726 19:27:11.482753 <6>[ 15.409849] pci 0000:01:00.0: supports D1 D2
10727 19:27:11.489001 <6>[ 15.409851] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10728 19:27:11.495717 <6>[ 15.414187] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10729 19:27:11.502571 <3>[ 15.418277] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 19:27:11.512734 <6>[ 15.419032] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10731 19:27:11.522334 <6>[ 15.419553] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10732 19:27:11.532440 <4>[ 15.426447] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10733 19:27:11.539225 <4>[ 15.426464] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10734 19:27:11.548767 <6>[ 15.427160] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10735 19:27:11.555548 <3>[ 15.435131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 19:27:11.562168 <6>[ 15.443232] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10737 19:27:11.571962 <3>[ 15.451294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 19:27:11.578772 <3>[ 15.451350] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 19:27:11.588686 <6>[ 15.459608] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10740 19:27:11.595290 <3>[ 15.467729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 19:27:11.605151 <3>[ 15.467737] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 19:27:11.611804 <3>[ 15.467751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 19:27:11.618362 <3>[ 15.467757] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 19:27:11.628150 <3>[ 15.467803] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 19:27:11.631712 <6>[ 15.468390] Bluetooth: Core ver 2.22
10746 19:27:11.638356 <6>[ 15.468501] NET: Registered PF_BLUETOOTH protocol family
10747 19:27:11.644785 <6>[ 15.468504] Bluetooth: HCI device and connection manager initialized
10748 19:27:11.647905 <6>[ 15.468532] Bluetooth: HCI socket layer initialized
10749 19:27:11.654647 <6>[ 15.468540] Bluetooth: L2CAP socket layer initialized
10750 19:27:11.658096 <6>[ 15.468551] Bluetooth: SCO socket layer initialized
10751 19:27:11.667859 <6>[ 15.469982] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10752 19:27:11.678227 <6>[ 15.471242] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10753 19:27:11.684448 <6>[ 15.471400] usbcore: registered new interface driver uvcvideo
10754 19:27:11.694076 <6>[ 15.473754] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10755 19:27:11.700702 <6>[ 15.477607] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10756 19:27:11.704121 <6>[ 15.482203] r8152 2-1.3:1.0 eth0: v1.12.13
10757 19:27:11.710744 <6>[ 15.482275] usbcore: registered new interface driver r8152
10758 19:27:11.717801 <6>[ 15.482864] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10759 19:27:11.727641 <6>[ 15.489705] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10760 19:27:11.734113 <6>[ 15.491550] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10761 19:27:11.743757 <6>[ 15.493329] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10762 19:27:11.750660 <6>[ 15.495772] remoteproc remoteproc0: remote processor scp is now up
10763 19:27:11.753940 <6>[ 15.496286] usbcore: registered new interface driver cdc_ether
10764 19:27:11.760562 <6>[ 15.497148] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10765 19:27:11.766952 <6>[ 15.503366] pci 0000:00:00.0: PCI bridge to [bus 01]
10766 19:27:11.774036 <6>[ 15.510418] usbcore: registered new interface driver r8153_ecm
10767 19:27:11.780401 <6>[ 15.531310] usbcore: registered new interface driver btusb
10768 19:27:11.790490 <4>[ 15.532237] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10769 19:27:11.796663 <3>[ 15.532246] Bluetooth: hci0: Failed to load firmware file (-2)
10770 19:27:11.800085 <3>[ 15.532250] Bluetooth: hci0: Failed to set up firmware (-2)
10771 19:27:11.810014 <4>[ 15.532253] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10772 19:27:11.820379 <6>[ 15.537808] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10773 19:27:11.826549 <6>[ 15.917921] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10774 19:27:11.833445 <6>[ 15.926168] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10775 19:27:11.839733 <6>[ 15.932454] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10776 19:27:11.856519 <5>[ 15.946428] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10777 19:27:11.898788 <5>[ 15.988492] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10778 19:27:11.905231 <5>[ 15.995840] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10779 19:27:11.915494 <4>[ 16.004301] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10780 19:27:11.918213 <6>[ 16.013202] cfg80211: failed to load regulatory.db
10781 19:27:11.969247 <6>[ 16.059326] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10782 19:27:11.975914 <6>[ 16.066878] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10783 19:27:12.000413 <6>[ 16.093643] mt7921e 0000:01:00.0: ASIC revision: 79610010
10784 19:27:12.106208 <6>[ 16.196227] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10785 19:27:12.109519 <6>[ 16.196227]
10786 19:27:12.109606 done
10787 19:27:12.120739 Saving random seed: OK
10788 19:27:12.134363 Starting network: OK
10789 19:27:12.164382 Starting dropbear sshd: <6>[ 16.257853] NET: Registered PF_INET6 protocol family
10790 19:27:12.171244 <6>[ 16.264423] Segment Routing with IPv6
10791 19:27:12.174711 <6>[ 16.268362] In-situ OAM (IOAM) with IPv6
10792 19:27:12.177675 OK
10793 19:27:12.187162 /bin/sh: can't access tty; job control turned off
10794 19:27:12.187596 Matched prompt #10: / #
10796 19:27:12.187887 Setting prompt string to ['/ #']
10797 19:27:12.187981 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10799 19:27:12.188175 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10800 19:27:12.188264 start: 2.2.6 expect-shell-connection (timeout 00:03:40) [common]
10801 19:27:12.188338 Setting prompt string to ['/ #']
10802 19:27:12.188399 Forcing a shell prompt, looking for ['/ #']
10804 19:27:12.238614 / #
10805 19:27:12.238712 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10806 19:27:12.238847 Waiting using forced prompt support (timeout 00:02:30)
10807 19:27:12.243700
10808 19:27:12.243968 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10809 19:27:12.244099 start: 2.2.7 export-device-env (timeout 00:03:40) [common]
10810 19:27:12.244193 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10811 19:27:12.244280 end: 2.2 depthcharge-retry (duration 00:01:20) [common]
10812 19:27:12.244367 end: 2 depthcharge-action (duration 00:01:20) [common]
10813 19:27:12.244453 start: 3 lava-test-retry (timeout 00:01:00) [common]
10814 19:27:12.244538 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10815 19:27:12.244610 Using namespace: common
10817 19:27:12.344928 / # #
10818 19:27:12.345036 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10819 19:27:12.350588 #
10820 19:27:12.350853 Using /lava-13420412
10822 19:27:12.451148 / # export SHELL=/bin/sh
10823 19:27:12.451277 <6>[ 16.465051] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10824 19:27:12.456582 export SHELL=/bin/sh
10826 19:27:12.557093 / # . /lava-13420412/environment
10827 19:27:12.562439 . /lava-13420412/environment
10829 19:27:12.662969 / # /lava-13420412/bin/lava-test-runner /lava-13420412/0
10830 19:27:12.663137 Test shell timeout: 10s (minimum of the action and connection timeout)
10831 19:27:12.668072 /lava-13420412/bin/lava-test-runner /lava-13420412/0
10832 19:27:12.687081 + export 'TESTRUN_ID=0_dmesg'
10833 19:27:12.693730 + c<8>[ 16.786224] <LAVA_SIGNAL_STARTRUN 0_dmesg 13420412_1.5.2.3.1>
10834 19:27:12.693987 Received signal: <STARTRUN> 0_dmesg 13420412_1.5.2.3.1
10835 19:27:12.694060 Starting test lava.0_dmesg (13420412_1.5.2.3.1)
10836 19:27:12.694147 Skipping test definition patterns.
10837 19:27:12.697137 d /lava-13420412/0/tests/0_dmesg
10838 19:27:12.697220 + cat uuid
10839 19:27:12.700584 + UUID=13420412_1.5.2.3.1
10840 19:27:12.700668 + set +x
10841 19:27:12.707192 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10842 19:27:12.716885 <8>[ 16.806535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10843 19:27:12.717142 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10845 19:27:12.737602 <8>[ 16.827513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10846 19:27:12.737854 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10848 19:27:12.757776 <8>[ 16.847975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10849 19:27:12.758029 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10851 19:27:12.761239 + set +x
10852 19:27:12.764595 <8>[ 16.857536] <LAVA_SIGNAL_ENDRUN 0_dmesg 13420412_1.5.2.3.1>
10853 19:27:12.764848 Received signal: <ENDRUN> 0_dmesg 13420412_1.5.2.3.1
10854 19:27:12.764931 Ending use of test pattern.
10855 19:27:12.764995 Ending test lava.0_dmesg (13420412_1.5.2.3.1), duration 0.07
10857 19:27:12.768223 <LAVA_TEST_RUNNER EXIT>
10858 19:27:12.768473 ok: lava_test_shell seems to have completed
10859 19:27:12.768576 alert: pass
crit: pass
emerg: pass
10860 19:27:12.768664 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10861 19:27:12.768747 end: 3 lava-test-retry (duration 00:00:01) [common]
10862 19:27:12.768833 start: 4 finalize (timeout 00:08:23) [common]
10863 19:27:12.768920 start: 4.1 power-off (timeout 00:00:30) [common]
10864 19:27:12.769074 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
10865 19:27:12.844147 >> Command sent successfully.
10866 19:27:12.846431 Returned 0 in 0 seconds
10867 19:27:12.946798 end: 4.1 power-off (duration 00:00:00) [common]
10869 19:27:12.947111 start: 4.2 read-feedback (timeout 00:08:22) [common]
10870 19:27:12.947361 Listened to connection for namespace 'common' for up to 1s
10871 19:27:13.948321 Finalising connection for namespace 'common'
10872 19:27:13.948491 Disconnecting from shell: Finalise
10873 19:27:13.948570 / #
10874 19:27:14.048874 end: 4.2 read-feedback (duration 00:00:01) [common]
10875 19:27:14.049023 end: 4 finalize (duration 00:00:01) [common]
10876 19:27:14.049139 Cleaning after the job
10877 19:27:14.049239 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/ramdisk
10878 19:27:14.051688 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/kernel
10879 19:27:14.058771 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/dtb
10880 19:27:14.058940 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420412/tftp-deploy-aanent8l/modules
10881 19:27:14.064498 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420412
10882 19:27:14.100766 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420412
10883 19:27:14.100925 Job finished correctly